最新美国发明专利第2015-06-16期 - 专利汇|PatentHub专利检索|专利查询网|发明专利查询分析

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US09059465B2	Positive electrode active material for lithium ion battery, positive electrode for secondary battery, and lithium ion battery Provided is a positive electrode active material for a lithium ion battery positive electrode material made of lithium-containing nickel-manganese-cobalt composite oxide of a layered structure represented with LiaNixMnyCozO2 (1.0
US09059459B2	Secondary battery A secondary battery including an electrode assembly including a first electrode plate, a second electrode plate, and a separator between the first electrode plate and the second electrode plate; a case containing the electrode assembly; an electrode terminal electrically connected to the first electrode plate; a current collector coupled between and electrically connecting the first electrode plate and the electrode terminal, the current collector including a fuse portion; and an insulating unit on the fuse portion of the current collector.
US09059443B2	Fuel cell, fuel cell system and electronic device There are provided a fuel cell having stable and good power generation characteristics and good safety, a fuel cell system including the fuel cell and an electronic device equipped with the fuel cell. The fuel cell includes at least an electrolyte membrane, an anode formed on one surface of the electrolyte membrane, a cathode formed on the other surface of the electrolyte membrane, a liquid fuel chamber for supplying a liquid fuel to the anode, and a separating layer formed between the anode and the liquid fuel chamber. The separating layer and/or the anode has an exhaust passage that is continuously formed in an in-plane direction to discharge exhaust gas generated at the anode. The separating layer allows the liquid fuel to pass from the liquid fuel chamber to the anode and blocks the movement of gas from the anode to the liquid fuel chamber.
US09059440B2	Enhanced efficiency turbine Hydrocarbon fuel is sent to a reformer, which produces carbon and hydrogen. The hydrogen is sent to a fuel cell which uses it to generate electricity, and the electricity is used to actuate an electric motor that is coupled to an output shaft of a turbine to impart torque to the shaft. Additionally, hydrocarbon fuel can be provided to the turbine intake directly and/or carbon from the reformer can be mixed with steam from the fuel cell and sent to the turbine intake, in either case to impinge on the turbine blades and impart further torque to the output shaft.
US09059438B2	Fuel cell system A fuel cell system includes a fuel cell, a control valve and a controller. The controller controls the control valve to periodically increase and decrease the anode gas pressure downstream of the control valve. The controller executes a shutdown operation of the fuel cell by closing the control valve to stop the anode gas and shutting down power generation of the fuel cell upon receiving a shutdown command. The controller estimates an anode gas concentration at a location where the anode gas concentration is locally lower within a power generation region of the fuel cell based on a control state of the anode gas at a time the shutdown command is issued. The controller determines whether to permit or prohibit shutting down the power generating operation based on the anode gas concentration.
US09059433B2	Display device and method of manufacturing the same A display device and a method of manufacturing the same. The display device includes: a substrate; and a reflection member that is disposed on a surface of the substrate and has a first thickness in a first reflection region corresponding to a light-emitting region and a second thickness in a second reflection region corresponding to a non-light-emitting region.
US09059425B2	Multilayer electronic device having one or more barrier stacks A device includes an organic polymer layer and an electrode positioned against the polymer layer, the electrode being constituted by a transparent stack of thin layers including an alternation of n thin metallic layers and of (n+1) antireflection coatings, with n≧1, where each thin metallic layer is placed between two antireflection coatings. At least one of the two antireflection coatings located at the ends of the constituent stack of the electrode includes a stack that is a barrier to moisture and gases, the layers of the or each barrier stack having alternately lower and higher densities.
US09059422B2	Substrate with transparent conductive film and thin film photoelectric conversion device Disclosed is a substrate with a transparent conductive film, wherein an underlying layer and a transparent conductive film are arranged in this order on a transparent insulating substrate. The transparent conductive film-side surface of the underlying layer is provided with a pyramid-shaped or inverse pyramid-shaped irregular structure, and the transparent conductive film comprises a first transparent electrode layer which is formed on the underlying layer and a second transparent electrode layer which forms the outermost surface of the transparent conductive film. By forming a zinc oxide layer that serves as the second transparent electrode layer by a reduced pressure CVD method, a substrate with a transparent conductive film that is provided with an irregular structure smaller than that of the underlying layer can be obtained. The substrate with a transparent conductive film can improve the conversion efficiency of a photoelectric conversion device through an increased light trapping effect.
US09059421B2	Light-emitting element, light-emitting device, display device, electronic appliance, and lighting device A multicolor light-emitting element using fluorescence and phosphorescence, which has a small number of manufacturing steps owing to a relatively small number of layers to be formed and is advantageous for practical application can be provided. In addition, a multicolor light-emitting element using fluorescence and phosphorescence, which has favorable emission efficiency is provided. A light-emitting element which includes a light-emitting layer having a stacked-layer structure of a first light-emitting layer exhibiting light emission from a first exciplex and a second light-emitting layer exhibiting phosphorescence is provided.
US09059420B2	Organic EL element with light extraction and light emission efficiency An organic EL element includes a transparent supporting substrate; a diffraction grating having a concavity and convexity layer with first concavities and convexities formed on a surface thereof, disposed on the transparent supporting substrate; and a transparent electrode, an organic layer having at least a light emitting layer, and a metal electrode having second concavities and convexities on a surface facing organic layer, which are stacked in this order on the diffraction grating and formed into such shapes such that a shape of the first concavities and convexities is maintained, wherein conditions (A), (B) and (C) respectively relating to a Fourier transformed, standard deviations pertaining to depth distributions for first and second concavities and convexities, and a ratio of the change in standard deviation of depth distribution of the second concavities and convexities relative to depth distributions of the first concavities and convexities are satisified.
US09059411B2	Fluorene compound, light-emitting element, light-emitting device, electronic device, and lighting device One embodiment of the present invention is a fluorene compound. Specifically, one embodiment of the present invention is a fluorene compound in which two 9-phenylfluoren-9-yl groups are each bonded to any of a pyridine skeleton and a pyrimidine skeleton through an arylene group, and in which the arylene group is any of one to three phenylene groups.
US09059408B2	Hexacene derivative, method for forming hexacene, method for forming hexacene crystal, process for making organic semiconductor device, and organic semiconductor device A hexacene derivative is described, being expressed by formula (1): wherein X1-X6 denote the presence or absence of a carbonyl bridge [—C(═O)—], with a proviso that at least one of X1-X6 is a carbonyl bridge while any six-member ring absent of a carbonyl bridge is aromatic. A method for forming hexacene is also described, including: thermally treating the hexacene derivative to expel volatile units of CO from the hexacene derivative.
US09059406B2	PZT-based ferroelectric thin film and method of manufacturing the same A PZT-based ferroelectric thin film formed on a lower electrode of a substrate having the lower electrode in which the crystal plane is oriented in a (111) axis direction, having an orientation controlling layer which is formed on the lower electrode and has a layer thickness in which a crystal orientation is controlled in a (111) plane preferentially in a range of 45 nm to 270 nm, and a film thickness adjusting layer which is formed on the orientation controlling layer and has the same crystal orientation as the crystal orientation of the orientation controlling layer, in which an interface is formed between the orientation controlling layer and the film thickness adjusting layer.
US09059402B2	Resistance-variable element and method for manufacturing the same A resistance-variable element as disclosed has high reliability, high densification, and good insulating properties. The device provides a resistance-variable element in which a first electrode including a metal primarily containing copper, an oxide film of valve-metal, an ion-conductive layer containing oxygen and a second electrode are laminated in this order.
US09059390B2	Self-isolated conductive bridge memory device A conductive-bridge random access memory device is disclosed comprising a second metal layer configured to provide second metal cations; a layer of insulator adjacent to the second metal layer; the layer of insulator comprising a layer of first insulator and a layer of second insulator; the layer of second insulator being adjacent to the second metal layer; a first metal layer adjacent to the layer of first insulator, the first metal layer being opposite to the second metal layer; wherein the density of the layer of second insulator is higher than the density of the layer of first insulator.
US09059387B2	Semiconductor light-emitting device A semiconductor light-emitting device includes a lead frame, a semiconductor light-emitting element mounted on the top surface of the bonding region, and a case covering part of the lead frame. The bottom surface of the bonding region is exposed to the outside of the case. The lead frame includes a thin extension extending from the bonding region and having a top surface which is flush with the top surface of the bonding region. The thin extension has a bottom surface which is offset from the bottom surface of the bonding region toward the top surface of the bonding region.
US09059385B2	Light emitting device package A light emitting device package is provided comprising a light emitting device including at least one light emitting diode and a body including a first lead frame on which the light emitting device is mounted and a second lead frame spaced apart from the first lead frame, wherein at least one of the first and second lead frames is extending to a bending region in a first direction by a predetermined length on the basis of an outer surface of the body and is bent in a second direction intersecting the first direction.
US09059384B2	LED packaging construction and manufacturing method thereof LED packaging construction includes a substrate, a cavernous construction, a LED, and a reflection layer. The substrate is daubed with an insulation layer and a circuit layer on a surface on the substrate, wherein the substrate is made of metal, and the insulation layer is disposed between the circuit layer and the substrate. The cavernous construction is disposed on the substrate and surrounds the LED, and is formed by disposing a photoresist layer and patterning the photoresist layer. The circuit layer electrically connects the LED through a conducting wire. The reflection layer is at least disposed on a first surface of the cavernous construction, wherein the first surface surrounds the LED and faces toward the LED, and a part of light emitted from the LED is reflected by the reflection layer.
US09059380B2	Discontinuous patterned bonds for semiconductor devices and associated systems and methods Discontinuous bonds for semiconductor devices are disclosed herein. A device in accordance with a particular embodiment includes a first substrate and a second substrate, with at least one of the first substrate and the second substrate having a plurality of solid-state transducers. The second substrate can include a plurality of projections and a plurality of intermediate regions and can be bonded to the first substrate with a discontinuous bond. Individual solid-state transducers can be disposed at least partially within corresponding intermediate regions and the discontinuous bond can include bonding material bonding the individual solid-state transducers to blind ends of corresponding intermediate regions. Associated methods and systems of discontinuous bonds for semiconductor devices are disclosed herein.
US09059375B2	Semiconductor light emitting device and method for manufacturing the same According to one embodiment, a semiconductor light emitting device includes first and second semiconductor layers, and a light emitting unit. The light emitting unit is provided between the first and second semiconductor layers and includes well layers and barrier layers. The barrier layers include p-side and n-side barrier layers, and a first intermediate barrier layer. The n-side barrier layer is provided between the p-side barrier layer and the first semiconductor layer. The first intermediate barrier layer is provided between the barrier layers. The well layers include p-side and n-side well layers, and a first intermediate well layer. The p-side well layer is provided between the p-side barrier layer and the second semiconductor layer. The n-side well layer is provided between the n-side barrier layer and the first intermediate barrier layer. The first intermediate well layer is provided between the first intermediate barrier layer and the p-side barrier layer.
US09059374B2	Semiconductor light emitting device A method for manufacturing a semiconductor light emitting device is provided. The device includes: an n-type semiconductor layer; a p-type semiconductor layer; and a light emitting unit provided between the n-type semiconductor layer and the p-type semiconductor layer. The method includes: forming a buffer layer made of a crystalline AlxGa1−xN (0.8≦x≦1) on a first substrate made of c-plane sapphire and forming a GaN layer on the buffer layer; stacking the n-type semiconductor layer, the light emitting unit, and the p-type semiconductor layer on the GaN layer; and separating the first substrate by irradiating the GaN layer with a laser having a wavelength shorter than a bandgap wavelength of GaN from the first substrate side through the first substrate and the buffer layer.
US09059366B2	Bonding of photovoltaic device to covering material A solar energy collection system includes a solar cell, a transparent covering, and a eutectic interlayer binding the solar cell and the transparent covering together. At least some of a compound of the eutectic interlayer bonds with the transparent covering, raising the melting temperature of the eutectic interlayer above the melting temperature with the full amount of the compound present.
US09059363B2	Thermoelectric materials A thermoelectric material having a high ZT value is provided. In general, the thermoelectric material is a thin film thermoelectric material that includes a heterostructure formed of IV-VI semiconductor materials, where the heterostructure includes at least one potential barrier layer. In one embodiment, the heterostructure is formed of IV-VI semiconductor materials and includes a first matrix material layer, a potential barrier material layer adjacent to the first matrix material layer and formed of a wide bandgap material, and a second matrix material layer that is adjacent the potential barrier material layer opposite the first matrix material layer. A thickness of the potential barrier layer is approximately equal to a mean free path distance for charge carriers at a desired temperature.
US09059357B2	Bifacial solar cell A bifacial solar cell is discussed. The bifacial solar cell includes a substrate, a p+-type doped region positioned at a first surface of the substrate, a P-type electrode part electrically connected to the p+-type doped region, an n+-type doped region positioned at a second surface of the substrate, and an N-type electrode part electrically connected to the n+-type doped region. The P-type electrode part is formed of a first inorganic solid powder including a first powder, which contains silver (Ag) and has an average diameter of about 0.2 μm to 1 μm, and a second powder, which contains a group III element and has an average diameter of about 1 μm to 5 μm. The N-type electrode part is formed of a second inorganic solid powder including only the first powder.
US09059352B2	Solar energy systems using external reflectors A solar energy concentrating system with high light collection efficiency includes a light concentrating unit, a light homogenizing unit and photovoltaic modules. The light concentrating unit includes a parabolic reflector and an ellipsoidal reflector which are coaxial and confocal. The light homogenizing unit includes an infrared filter and a hollow spherical reflector with a hole in its surface. When the system is under illumination, light is concentrated by the light concentrating unit through the hole in the spherical reflector surface and reflected by the inner surface of the spherical reflector onto the photovoltaic modules. The infrared filter covers the hole in the spherical reflector surface and reduces the heat in the photovoltaic modules under concentrated light. The combination of the parabolic reflector and the ellipsoidal reflector obtain highly concentrated light, and the hollow spherical reflector ensures light uniformity on the photovoltaic modules and light utilization efficiency.
US09059351B2	Integrated diode assemblies for photovoltaic modules Provided are bypass diode assemblies for use in photovoltaic modules. Also provided are methods of fabricating such assemblies and a method of fabricating photovoltaic modules using such assemblies. A diode assembly may include an insulating strip, at least one lead-diode assembly having a diode and two leads, and at least two interconnecting conductors overlapping with and electrically contacting the leads of the lead-diode assembly. The insulating strip supports the lead-diode assembly and conductors and at least partially insulates these components from photovoltaic cells. Specifically, during module fabrication, the interconnecting conductors make electrical connections to the back sides of the cells through cutouts in the insulating strip. The electrical connections may be made to every cell in a row or a subset of selected cells in that row. In certain embodiments, the same interconnecting conductor is connected to two or more cells positioned in adjacent rows.
US09059347B2	Photoelectric conversion device and manufacturing method thereof A photoelectric conversion device having a high electric generating capacity at low illuminance, in which a semiconductor layer is appropriately separated and short circuit of a side surface portion of a cell is prevented. The photoelectric conversion device includes an isolation groove formed between one first electrode and the other first electrode that is adjacent to the one first electrode; a stack including a first semiconductor layer having one conductivity type over the first electrode, a second semiconductor layer formed using an intrinsic semiconductor, and a third semiconductor layer having a conductivity type opposite to the one conductivity type; and a connection electrode connecting one first electrode and a second electrode that is in contact with a third semiconductor layer included in a stack formed over the other first electrode that is adjacent to the one first electrode. A side surface portion of the second semiconductor layer is not crystallized.
US09059346B2	Laser power and energy sensor utilizing anisotropic thermoelectric material A laser-radiation sensor includes a copper substrate on which is grown an oriented polycrystalline buffer layer surmounted by an oriented polycrystalline sensor-element of an anisotropic transverse thermoelectric material. An absorber layer, thermally connected to the sensor-element, is heated by laser-radiation to be measured and communicates the heat to the sensor-element, causing a thermal gradient across the sensor-element. Spaced-apart electrodes in electrical contact with the sensor-element sense a voltage corresponding to the thermal gradient as a measure of the incident laser-radiation power. At least two protection layers are positioned between the sensor layer and the absorber layer.
US09059344B2	Nanowire-based photovoltaic energy conversion devices and related fabrication methods Nanowire-based photovoltaic energy conversion devices and related fabrication methods therefor are described. A plurality of photovoltaic (PV) nanowires extend outwardly from a surface layer of a substrate, each PV nanowire having a root end near the substrate surface layer and a tip end opposite the root end. For one preferred embodiment, a canopy-style tip-side electrode layer contacts the tip ends of the PV nanowires and is separated from the substrate surface layer by an air gap layer, the PV nanowires being disposed within the air gap layer. For another preferred embodiment, a tip-side electrode layer is disposed upon a layer of optically transparent, electrically insulating solid filler material that laterally surrounds the PV nanowires along a portion of their lengths, wherein an air gap is disposed between the solid filler layer and the substrate surface layer. Methods for fabricating the nanowire-based photovoltaic energy conversion devices are also described.
US09059343B2	Radiation image pickup apparatus, radiation image pickup system, and method for manufacturing radiation image pickup apparatus A radiation image pickup apparatus includes a base, at least one image pickup element, a scintillator, a first heat peelable adhesive layer which is arranged between the base and the image pickup element and which fixes the base and the image pickup element, and a second heat peelable adhesive layer which is arranged between the image pickup element and the scintillator and which fixes the image pickup element and the scintillator, and in the radiation image pickup element described above, the first heat peelable adhesive layer contains first heat-expandable microspheres, the second heat peelable adhesive layer contains second heat-expandable microspheres, and the first heat-expandable microspheres have a different expansion starting temperature from that of the second heat-expandable microspheres.
US09059340B2	Method of manufacturing solar cell and solar cell Provided is a method capable of easily manufacturing a back contact solar cell with high photoelectric conversion efficiency. A semiconductor layer having a first conductivity which is the same as that of a semiconductor substrate is formed substantially entirely on the principal surface of the semiconductor substrate inclusive of a surface of an insulation layer. A portion of the semiconductor layer located on the insulation layer is removed, and thereby an opening is formed. The insulation layer exposed through the opening is removed while the semiconductor layer is used as a mask, and thereby a surface of a first semiconductor region is partially exposed. Electrodes which are electrically connected to the surface of the first semiconductor region and to a surface of the semiconductor layer respectively are formed.
US09059339B1	Light emitting diodes with via contact scheme A method of forming an inorganic light emitting diode (LED) with a via contact scheme for large-area display and backlighting applications is provided. An inorganic LED stack comprising, from bottom to top, a first contact layer, an active layer, and a second contact layer having a polarity different from the first contact layer is removed from the underlying base substrate by a controlled spalling or chemical liftoff process. A via contact scheme that can provide ohmic contacts to both the first contact layer and the second contact layer is then formed on the released LED stack.
US09059336B2	Thermoelectric conversion element A thermoelectric conversion element includes: a magnetic layer; a conductive film formed on the magnetic layer and configured to generate an electromotive force in an in-plane direction by inverse spin-Hall effect; and two terminal sections formed to contact with the conductive film at two portions whose potentials are different to each other by the electromotive force. Each of the two terminal sections contacts with the conductive film in a continuous or discrete contact surface. A longitudinal direction of a minimum rectangle which encompasses the continuous or discrete contact surface of each of the two terminal sections intersects with the direction of the electromotive force.
US09059335B2	Anisotropic conducting films for electromagnetic radiation applications Electronic devices for the generation of electromagnetic radiation are provided. Also provided are methods for using the devices to generate electromagnetic radiation. The radiation sources include an anisotropic electrically conducting thin film that is characterized by a periodically varying charge carrier mobility in the plane of the film. The periodic variation in carrier mobility gives rise to a spatially varying electric field, which produces electromagnetic radiation as charged particles pass through the film.
US09059333B1	Facilitating chip dicing for metal-metal bonding and hybrid wafer bonding A method of forming a stacked assembly of semiconductor chips can include juxtaposing and metallurgically joining kerf metal elements exposed in kerf regions of a first wafer with corresponding kerf metal elements exposed in kerf regions of a second wafer, and affixing undiced semiconductor chips of the first wafer with corresponding undiced semiconductor chips of the second wafer. The assembled wafers are then cut along the dicing lanes thereof into a plurality of individual assemblies of stacked semiconductor chips, each assembly including an undiced semiconductor chip of the first wafer and an undiced semiconductor chip of the second wafer affixed therewith.
US09059323B2	Method of forming fin-field effect transistor (finFET) structure Various embodiments include methods of forming semiconductor structures. In one embodiment, a method includes: providing a precursor structure including a substrate and a set of fins overlying the substrate; forming a dummy epitaxy between the fins in the set of fins; masking a first group of fins in the set of fins and the dummy epitaxy between the first group of fins in the set of fins; removing the dummy epitaxy to expose a second group of the fins; forming a first in-situ doped epitaxy between the exposed fins; masking the second group of fins in the set of fins and the in-situ doped epitaxy between the second group of fins in the set of fins; unmasking the first group of fins; removing the dummy epitaxy layer between the first group of fins to expose of the first group of fins; and forming a second in-situ doped epitaxy between the exposed fins.
US09059320B2	Structure and method of forming enhanced array device isolation for implanted plate EDRAM A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.
US09059319B2	Embedded dynamic random access memory device and method Embodiments of the invention provide an integrated circuit for an embedded dynamic random access memory (eDRAM), a semiconductor-on-insulator (SOI) wafer in which such an integrated circuit may be formed, and a method of forming an eDRAM in such an SOI wafer. One embodiment of the invention provides an integrated circuit for an embedded dynamic random access memory (eDRAM) comprising: a semiconductor-on-insulator (SOI) wafer including: an n-type substrate; an insulator layer atop the n-type substrate; and an active semiconductor layer atop the insulator layer; a plurality of deep trenches, each extending from a surface of the active semiconductor layer into the n-type substrate; a dielectric liner along a surface of each of the plurality of deep trenches; and an n-type conductor within each of the plurality of deep trenches, the dielectric liner separating the n-type conductor from the n-type substrate; wherein the n-type substrate, the dielectric liner, and the n-type conductor form a buried plate, a node dielectric, and a node plate, respectively, of a cell capacitor.
US09059317B2	Method of making an electronic device having a liquid crystal polymer solder mask laminated to an interconnect layer stack and related devices A method for making an electronic device includes forming an interconnect layer stack on a rigid wafer substrate having a plurality of patterned electrical conductor layers, a dielectric layer between adjacent patterned electrical conductor layers, and at least one solder pad on an uppermost patterned electrical conductor layer. An LCP solder mask having at least one aperture therein alignable with the at least one solder pad is formed. The LCP solder mask and interconnect layer stack are aligned and laminated together. Solder is positioned in the at least one aperture. At least one circuit component is attached to the at least one solder pad using the solder.
US09059316B2	Structure and method for mobility enhanced MOSFETs with unalloyed silicide While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.
US09059314B2	Structure and method to obtain EOT scaled dielectric stacks Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.
US09059312B2	Semiconductor device and manufacturing method of semiconductor device A semiconductor device includes: a first conductivity type transistor and a second conductivity type transistor, wherein each of the first conductivity type transistor and the second conductivity type includes a gate insulating film formed on a base, a metal gate electrode formed on the gate insulating film, and side wall spacers formed at side walls of the metal gate electrode, wherein the gate insulating film is made of a high dielectric constant material, and wherein offset spacers are formed between the side walls of the metal gate electrode and the inner walls of the side wall spacers in any one of the first conductivity type transistor and the second conductivity type transistor, or offset spacers having different thicknesses are formed in the first conductivity type transistor and the second conductivity type transistor.
US09059311B1	CMOS transistors with identical active semiconductor region shapes A disposable semiconductor material is deposited to form disposable semiconductor material portions on semiconductor fins. A first dielectric liner is deposited and patterned to form openings above a first set of disposable semiconductor material portions on a first semiconductor fin. The first set of disposable semiconductor material portions is replaced with a first set of active semiconductor regions by a combination of an etch and a selective epitaxy process that deposits a first semiconductor material. A second dielectric liner is deposited and patterned to form openings above the second set of disposable semiconductor material portions. The second set of disposable semiconductor material portions is replaced with a second set of active semiconductor regions employing another epitaxy process that deposits a second semiconductor material. The active semiconductor regions can have the same faceting profile irrespective of the semiconductor materials therein.
US09059310B2	SRAM devices utilizing strained-channel transistors and methods of manufacture A novel SRAM memory cell structure and method of making the same are provided. The SRAM memory cell structure comprises strained PMOS transistors formed in a semiconductor substrate. The PMOS transistors comprise epitaxial grown source/drain regions that result in significant PMOS transistor drive current increase. An insulation layer is formed atop an STI that is used to electrically isolate adjacent PMOS transistors. The insulation layer is substantially elevated from the semiconductor substrate surface. The elevated insulation layer facilitates the formation of desirable thick epitaxial source/drain regions, and prevents the bridging between adjacent epitaxial layers due to the epitaxial layer lateral extension during the process of growing epitaxial sour/drain regions. The processing steps of forming the elevated insulation layer are compatible with a conventional CMOS process flow.
US09059308B2	Method of manufacturing dummy gates of a different material as insulation between adjacent devices Embodiments of the present invention include a semiconductor structure including two transistor structures separated by a dummy gate of a different material and methods for forming said structure. Embodiments including forming sacrificial gates on a semiconductor substrate, forming spacers on the sacrificial gates, forming source/drain regions adjacent to two sacrificial gates separated by a third sacrificial gate, and replacing the third sacrificial gate with an insulating material. The insulating material replacing the third sacrificial gate may serve as a dummy gate to electrically isolate nearby source/drain regions. Embodiments further include forming sacrificial gates on a semiconductor substrate, forming spacers on the sacrificial gates, forming source/drain regions adjacent to two sacrificial gates separated by a third sacrificial gate, and replacing the two sacrificial gates with metal gates while leaving the third sacrificial gate in place to serve as a dummy gate.
US09059304B2	Enhanced flip chip package According to various embodiments, a flip chip package structure is provided in which a redistribution layer (RDL) is disposed on a surface of both a semiconductor chip and one or more lateral extensions of the semiconductor chip surface. The lateral extensions may be made using, e.g., a reconstituted wafer to implement a fanout region lateral to one or more sides of the semiconductor chip. One or more electrical connectors such as solder bumps or copper cylinders may be applied to the RDL, and an interposer such as a PCB interposer may be connected to the electrical connectors. In this way, a relatively tight semiconductor pad pitch may be accommodated and translated to an appropriate circuit board pitch without necessarily requiring a silicon or glass interposer.
US09059302B2	Floating gate memory device with at least partially surrounding control gate One or more embodiments relate to a floating gate memory device, comprising: a substrate; a floating gate disposed over the substrate; and a control gate substantially laterally surrounding at least a portion of the floating gate.
US09059301B2	Self-aligned charge-trapping layers for non-volatile data storage, processes of forming same, and devices containing same A discrete storage element film is disposed above a tunneling dielectric film against a shallow trench isolation structure and under conditions to resist formation of the discrete storage element film upon vertical exposures of the shallow trench isolation structure. A discrete storage element film is also disposed above a tunneling dielectric film against a recessed isolation structure. A microelectronic device incorporates the discrete storage element film. A computing system incorporates the microelectronic device.
US09059300B2	Nonvolatile semiconductor memory device having element isolating region of trench type Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.
US09059293B2	Array substrate and its manufacturing method An array substrate comprises a substrate, a gate electrode, a source electrode and a drain electrode, the source electrode and the drain electrode being provided in different areas on the substrate and the vertical projections of the source electrode and the drain electrode on the substrate having an overlapping area; a semiconductor layer formed between the source electrode and the drain electrode, a vertical projection of the semiconductor layer on the substrate having overlapping areas with the vertical projections of the source electrode and the drain electrode on the substrate; a first insulating layer formed on the substrate while below the gate electrode and covering the source electrode or the drain electrode; a pixel electrode, a gate line, and a data line. A manufacturing method for the array substrate is also disclosed.
US09059289B2	Stringer-free gate electrode for a suspended semiconductor fin At least one semiconductor fin is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor fin. The amount of the etched portions of the insulator is selected such that a metallic gate electrode layer fills the entire gap between the recessed surfaces of the insulator layer and the bottom surface(s) of the at least one semiconductor fin. An interface between the metallic gate electrode layer and a semiconductor gate electrode layer contiguously extends over the at least one semiconductor fin and does not underlie any of the at least one semiconductor fin. During patterning of a gate electrode, removal of the semiconductor material in the semiconductor gate electrode layer can be facilitated because the semiconductor gate electrode layer is not present under the at least one semiconductor fin.
US09059288B2	Overlapped III-V finfet with doped semiconductor extensions A semiconductor structure that includes a semiconductor fin comprising an III-V compound semiconductor material. A functional gate structure straddles a portion of the semiconductor fin. A semiconductor channel material having an electron mobility greater than silicon and comprising a different semiconductor material than the semiconductor fin and is located beneath the functional gate structure. The semiconductor channel material is present on at least each vertical sidewall of the semiconductor fin. A dielectric spacer is located on each vertical sidewall surface of the functional gate structure. A doped semiconductor is located on each side of the functional gate structure and underneath each dielectric spacer. A portion of the doped semiconductor material located beneath each dielectric spacer directly contacts a sidewall surface of semiconductor channel material located on each vertical sidewall of the semiconductor fin.
US09059284B2	Semiconductor device A semiconductor device includes a first semiconductor layer of a first conductivity type. A second semiconductor layer of a second conductivity type is on the first semiconductor layer. A third semiconductor layer is on the second semiconductor layer. A fourth semiconductor layer is selectively in the first semiconductor layer. A first trench and second trench penetrate from a surface of the third layer through the second layer to reach the first layer. An embedded electrode is in the first trench. A control electrode is above the embedded electrode via an insulating film. A lower end of the second trench is connected to the fourth semiconductor layer. A first main electrode is electrically connected to the first layer. A second main electrode is provided in the second trench. A Schottky junction is formed by the first layer and the second main electrode at a sidewall of the second trench.
US09059282B2	Semiconductor devices having transistors along different orientations Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes an array having at least one first region and at least one second region. The at least one first region includes at least one first device oriented in a first direction. The at least one second region includes at least one second device oriented in a second direction. The second direction is different than the first direction.
US09059279B2	Semiconductor device and method for forming the same A semiconductor device includes a first gate structure formed in a semiconductor substrate; a second gate structure formed over the semiconductor substrate and over the first gate structure; and a bit line formed in the semiconductor substrate, and formed below the first gate structure.
US09059277B2	RF LDMOS device and fabrication method thereof A radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) device is disclosed, wherein a lightly doped n-type drain region has a laterally non-uniform n-type dopant concentration distribution, which is achieved by forming a moderately n-type doped region, having a higher doping concentration and a greater depth than the rest portion of the lightly doped n-type drain region, in a portion of the lightly n-type doped region proximate to the polysilicon gate. The structure enables the RF LDMOS device of the present invention to have both a high breakdown voltage and a significantly reduced on-resistance. A method of fabricating such a RF LDMOS device is also disclosed.
US09059263B2	Low-K dielectric protection spacer for patterning through substrate vias through a low-K wiring layer A low-K value dielectric protection spacer for patterning through substrate vias (TSVs) through a low-K value wiring layer. A method for forming a low-K value dielectric protection spacer includes etching a via opening through a low-K value dielectric interconnect layer. A protective layer is deposited in the via opening and on the low-K value dielectric interconnect layer. At least a portion of the protective layer is etched from the bottom of the via opening and from a horizontal surface of the low-K value dielectric interconnect layer. The etching leaving a protective sidewall spacer on a sidewall of the via opening. A through substrate via is etched through the bottom of the via opening and through the semiconductor substrate. The through substrate via is filled with a conductive material.
US09059262B2	Integrated circuits including conductive structures through a substrate and methods of making the same An integrated circuit includes a substrate having a first surface and a second surface. At least one conductive structure continuously extends through the substrate. At least one sidewall of the at least one conductive structure is spaced from a sidewall of the substrate by an air gap.
US09059259B2	Hard mask for back-end-of-line (BEOL) interconnect structure A method of fabricating an interconnect structure on a wafer and an interconnect structure are provided. A dielectric layer is provided on the wafer. An interconnect is formed by etching a recess into the dielectric layer, where the etching utilizes a hard mask that includes a first layer deposited over the dielectric layer. The interconnect is planarized using a chemical mechanical polishing (CMP) process, where the first layer remains on the dielectric layer at a completion of the CMP process. The first layer or a portion of the first layer is transformed into a nitride layer or an oxide layer after the CMP process.
US09059250B2	Lateral-dimension-reducing metallic hard mask etch A combination of gases including at least a fluorocarbon gas, oxygen, and an inert sputter gas is employed to etch at least one opening into an organic photoresist. The amount of oxygen is controlled to a level that limits conversion of a metallic nitride material in an underlying hard mask layer to a metal oxide, and causes organic polymers generated from the organic photoresist to cover peripheral regions of each opening formed in the organic photoresist. The hard mask layer is etched with a taper by the oxygen-limited fluorine-based etch chemistry provided by the combination of gases. The taper angle can be controlled such that a shrink ratio of the lateral dimension by the etch can exceed 2.0.
US09059244B2	Fabricating shallow-trench isolation semiconductor devices to reduce or eliminate oxygen diffusion A method is disclosed for forming a semiconductor device. A first opening is formed for an STI on a semiconductor substrate and a first process is performed to deposit first oxide into the first opening. A second opening is formed to remove a portion of the first oxide from the first opening and second process(es) is/are performed to deposit second oxide into the second opening and over a remaining portion of the first oxide. A portion of the semiconductor device is formed over a portion of a surface of the second oxide. A semiconductor device includes an STI including a first oxide formed in a lower portion of a trench of the STI and a second oxide formed in an upper portion of the trench and above the first oxide. The semiconductor device includes a portion of the semiconductor device formed over a portion of the second oxide.
US09059242B2	FinFET semiconductor device having increased gate height control A semiconductor device includes a silicon-on-insulator (SOI) substrate having a buried oxide (BOX) layer, and a plurality of semiconductor fins formed on the BOX layer. The plurality of semiconductor fins include at least one pair of fins defining a BOX region therebetween. Gate lines are formed on the SOI substrate and extend across the plurality of semiconductor fins. Each gate line initially includes a dummy gate and a hardmask. A high dielectric (high-k) layer is formed on the hardmask and the BOX regions. At least one spacer is formed on each gate line such that the high-k layer is disposed between the spacer and the hardmask. A replacement gate process replaces the hardmask and the dummy gate with a metal gate. The high-k layer is ultimately removed from the gate line, while the high-k layer remains on the BOX region.
US09059235B2	Semiconductor device and method of manufacturing the same In one embodiment, a semiconductor device includes a substrate including a trench, and a gate electrode disposed at a position adjacent to the trench on the substrate, the gate electrode having a first side surface located on an opposite side of the trench, and a second side surface located on the same side as the trench. The device further includes a first sidewall insulator disposed on the first side surface, and a second sidewall insulator disposed on the second side surface and a side surface of the trench. The device further includes a source region of a first conductivity type disposed in the substrate on the same side as the first sidewall insulator with respect to the first side surface, and a drain region of a second conductivity type disposed in the substrate on the same side as the second sidewall insulator with respect to the second side surface.
US09059233B2	Formation of an asymmetric trench in a semiconductor substrate and a bipolar semiconductor device having an asymmetric trench isolation region Disclosed is a trench formation technique wherein an opening having a first sidewall with planar contour and a second sidewall with a saw-tooth contour is etched through a semiconductor layer and into a semiconductor substrate. Then, a crystallographic wet etch process expands the portion of the opening within the semiconductor substrate to form a trench. Due to the different contours of the sidewalls and, thereby the different crystal orientations, one sidewall etches faster than the other, resulting in an asymmetric trench. Also disclosed is a bipolar semiconductor device formation method that incorporates the above-mentioned trench formation technique when forming a trench isolation region that undercuts an extrinsic base region and surrounds a collector pedestal. The asymmetry of the trench ensures that the trench isolation region has a relatively narrow width and, thereby ensures that both collector-to-base capacitance Ccb and collector resistance Rc are minimized within the resulting bipolar semiconductor device.
US09059232B2	T-shaped compound semiconductor lateral bipolar transistor on semiconductor-on-insulator A base region extends upward from a recessed semiconductor surface of a semiconductor material portion present on an insulator. The base region includes a vertical stack of, an extrinsic base region and an intrinsic base region. The extrinsic base region includes a first compound semiconductor material portion of a first conductivity type and a first dopant concentration. The intrinsic base region includes another first compound semiconductor material portion of the first conductivity type and a second dopant concentration which is less than the first dopant concentration. A collector region including a second compound semiconductor material portion of a second conductivity type opposite of the first conductivity type is located on one side on the base region. An emitter region including another second compound semiconductor material portion of the second conductivity type is located on another side on the base region.
US09059231B2	T-shaped compound semiconductor lateral bipolar transistor on semiconductor-on-insulator A base region extends upward from a recessed semiconductor surface of a semiconductor material portion present on an insulator. The base region includes a vertical stack of, an extrinsic base region and an intrinsic base region. The extrinsic base region includes a first compound semiconductor material portion of a first conductivity type and a first dopant concentration. The intrinsic base region includes another first compound semiconductor material portion of the first conductivity type and a second dopant concentration which is less than the first dopant concentration. A collector region including a second compound semiconductor material portion of a second conductivity type opposite of the first conductivity type is located on one side on the base region. An emitter region including another second compound semiconductor material portion of the second conductivity type is located on another side on the base region.
US09059227B2	Methods and apparatus for vertically orienting substrate processing tools in a clean space The present invention provides various aspects of support for a fabrication facility capable of routine placement and replacement of processing tools in at least a vertical dimension relative to each other.
US09059222B2	Washing device and method for fabricating the same The present invention relates a washing device and a method for fabricating the same which has good chemical resistance and can prevent a scratch from forming on a substrate. The washing device includes a substrate entry guide for making a substrate to enter in a right direction from an outside of the washing device, a foreign matter removal unit for receiving the substrate from the substrate entry guide unit and removing foreign matters from the substrate, a foreign matter washing unit for receiving the substrate from the foreign matter removal unit and washing remained foreign matters from the substrate, and a position control unit for controlling a position of the substrate moving out of the foreign matter washing unit, wherein the substrate entry guide, the foreign matter removal unit, the foreign matter washing unit, and the position control unit are formed of metallic porous material.
US09059219B2	Semiconductor device and method for manufacturing semiconductor device Provided is a method for manufacturing a transistor by which the defective shape of a semiconductor device is prevented in the case where a source electrode layer and a drain electrode layer are formed on an oxide semiconductor film. A source electrode layer and a drain electrode layer are formed each having a cross-sectional shape with which disconnection of a gate insulating film is unlikely to occur even when the gate insulating film over the source electrode layer and the drain electrode layer has a small thickness. An oxide semiconductor film having a crystal structure over an insulating surface is formed; an electrode layer on the oxide semiconductor film is formed; and a thickness of an exposed portion of the oxide semiconductor film is reduced by exposing the oxide semiconductor film to dilute hydrofluoric acid with a concentration higher than 0.0001% and lower than or equal to 0.25%.
US09059215B2	Method for adjusting the threshold voltage of LTPS TFT The N-type poly-silicon is applied in the LTPS productions. The LTPS productions comprise an N-type poly-silicon and a P-type poly-silicon. The N-type poly-silicon, from bottom to top, successively includes a substrate layer, a SiOx layer, a SiNx layer, a metal layer and a photoresist. The substrate layer is an A-type silicon layer. Wherein, the method for controlling the threshold voltage of the N-type poly-silicon specifically comprise the following steps: (a) etching the metal layer and the SiNx layer, and over etching the SiOx layer in a small quantity; (b) over etching the metal layer, and etching a portion of the SiOx layer, and the SiOx layer is not etched through.
US09059214B2	Manufacturing method for thin film transistor with polysilicon active layer Embodiments of the disclosed technology relate to a method for manufacturing a thin film transistor (TFT) with a polysilicon active layer comprising: depositing an amorphous silicon layer on a substrate, and patterning the amorphous silicon layer so as to form an active layer comprising a source region, a drain region and a channel region; depositing an inducing metal layer on the source region and the drain region; performing a first thermal treatment on the active layer provided with the inducing metal layer so that the active layer is crystallized under the effect of the inducing metal; doping the source region and the drain region with a first impurity for collecting the inducing metal; and performing a second thermal treatment on the doped active layer so that the first impurity absorbs the inducing metal remained in the channel region.
US09059211B2	Oxygen scavenging spacer for a gate electrode At least one layer including a scavenging material and a dielectric material is deposited over a gate stack, and is subsequently anisotropically etched to form a oxygen-scavenging-material-including gate spacer. The oxygen-scavenging-material-including gate spacer can be a scavenging-nanoparticle-including gate spacer or a scavenging-island-including gate spacer. The scavenging material is distributed within the oxygen-scavenging-material-including gate spacer in a manner that prevents an electrical short between a gate electrode and a semiconductor material underlying a gate dielectric. The scavenging material actively scavenges oxygen that diffuses toward the gate dielectric from above, or from the outside of, a dielectric gate spacer that can be formed around the oxygen-scavenging-material-including gate spacer.
US09059209B2	Replacement gate ETSOI with sharp junction A method includes providing a silicon-on-insulator wafer (e.g., an ETSOI wafer); forming a sacrificial gate structure that overlies a sacrificial insulator layer; forming raised source/drains adjacent to the sacrificial gate structure; depositing an oxide layer that covers the raised source/drains and that surrounds the sacrificial gate structure; and removing the sacrificial gate structure leaving an opening that extends to the sacrificial insulator layer. The method further includes widening the opening so as to expose some of the raised source/drains, removing the sacrificial insulator layer and forming a spacer layer on sidewalls of the opening, the spacer layer covering only an upper portion of the exposed raised source/drains, and depositing a layer of gate dielectric material within the opening. A gate conductor is deposited within the opening.
US09059204B2	Methodology and apparatus for tuning driving current of semiconductor transistors A method and apparatus for repairing transistors may include applying a first voltage to a source, a second voltage to the gate and a third voltage to the drain for a predetermined time. In this manner the transistor structure may be repaired or returned to operate at or near the original operating characteristics.
US09059202B2	Metal-oxide-semiconductor (MOS) device and method for fabricating the same A Metal-Oxide-Semiconductor (MOS) device is disclosed. The MOS device includes a substrate, a well region formed in the substrate, and a gate located on the substrate. The MOS device also includes a first lightly-doped region arranged in the well region at a first side of the gate and overlapping with the gate, and a second lightly-doped region arranged in the well region at a second side of the gate and overlapping with the gate. Further, the MOS device includes a first heavily-doped region formed in the first lightly-doped region, and a second heavily-doped region formed in the second lightly-doped region. The MOS device also includes a first high-low-voltage gate oxide boundary arranged between the first heavily-doped region and the gate, and a second high-low-voltage gate oxide boundary arranged between the second heavily-doped region and the gate. The gate covers the first high-low-voltage gate oxide boundary and the second high-low-voltage gate oxide boundary at the first side and the second side of the gate, respectively.
US09059199B2	Method and system for a gallium nitride vertical transistor A vertical JFET includes a GaN substrate comprising a drain of the JFET and a plurality of patterned epitaxial layers coupled to the GaN substrate. A distal epitaxial layer comprises a first part of a source channel and adjacent patterned epitaxial layers are separated by a gap having a predetermined distance. The vertical JFET also includes a plurality of regrown epitaxial layers coupled to the distal epitaxial layer and disposed in at least a portion of the gap. A proximal regrown epitaxial layer comprises a second part of the source channel. The vertical JFET further includes a source contact passing through portions of a distal regrown epitaxial layer and in electrical contact with the source channel, a gate contact in electrical contact with a distal regrown epitaxial layer, and a drain contact in electrical contact with the GaN substrate.
US09059198B2	Bi-directional silicon controlled rectifier structure Fabrication methods for bi-directional silicon controlled rectifier device structures. A well of a first conductivity type is formed in a device region, which may be defined from a device layer of a semiconductor-on-insulator substrate. An anode of a first silicon controlled rectifier is formed in the first well. A cathode of a second silicon controlled rectifier is formed in the first well. The anode of the first silicon controlled rectifier has the first conductivity type. The cathode of the second silicon controlled rectifier has a second conductivity type opposite to the first conductivity type.
US09059193B2	Epitaxial wafer and semiconductor element A silicon carbide semiconductor element, including: i) an n-type silicon carbide substrate doped with a dopant, such as nitrogen, at a concentration C, wherein the substrate has a lattice constant that decreases with doping; ii) an n-type silicon carbide epitaxially-grown layer doped with the dopant, but at a smaller concentration than the substrate; and iii) an n-type buffer layer doped with the dopant, and arranged between the substrate and the epitaxially-grown layer, wherein the buffer layer has a multilayer structure in which two or more layers having the same thickness are laminated, and is configured such that, based on a number of layers (N) in the multilayer structure, a doping concentration of a K-th layer from a silicon carbide epitaxially-grown layer side is C·K/(N+1).
US09059192B2	Metal-insulation-metal device A metal-insulation-metal (MIM) device including a first metal layer, a first insulation layer, a second metal layer, and a second insulation layer is provided. The first insulation layer is disposed on the first metal layer. The second metal layer is disposed on a part of the first insulation layer. The second insulation layer is disposed on a side wall of the second metal layer and on another part of the first insulation layer. A width of the first insulation layer under the second metal layer and the second insulation layer parallel to the first metal layer is greater than a with of the second metal layer parallel to the first metal layer. A manufacture method of an MIM device is also provided.
US09059191B2	Chamfered corner crackstop for an integrated circuit chip A corner crackstop is formed in each of the four corners of an integrated circuit (IC) chip, in which the corner crackstop differs structurally from a portion of the crackstop disposed along the sides of the IC chip. Each corner crackstop includes a plurality of layers, formed on a top surface of a silicon layer of the IC chip, within a perimeter boundary region that comprises a triangular area, in which a right angle is disposed on a bisector of the corner, equilateral sides of the triangle are parallel to sides of the IC chip, and the right angle is proximate to the corner relative to a hypotenuse of the triangle. The plurality of layers of the corner crackstop include crackstop elements, each comprising a metal cap centered over a via bar, in which the plurality of layers of the corner crackstop is chamfered to deflect crack ingress forces by each corner crackstop.
US09059181B2	Wafer leveled chip packaging structure and method thereof A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.
US09059180B2	Thick bond pad for chip with cavity package Disclosed herein an image sensor chip, including a substrate having at least one via extending through at least one inter layer dielectric (ILD); a first conductive layer over the ILD, wherein the first conductive layer has a first thickness; a second conductive layer over the first conductive layer, wherein the second conductive layer has a second thickness of less than the first thickness; a polymer layer over the second conductive layer, the polymer layer including a cavity; a plurality of cavity components in the cavity; and protective layer contacting the polymer layer and covering the cavity.
US09059179B2	Semiconductor package with a bridge interposer There are disclosed herein various implementations of semiconductor packages including a bridge interposer. One exemplary implementation includes a first active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The semiconductor package also includes a second active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The second portion of the first active die and the second portion of the second active die include solder balls mounted on a package substrate, and are configured to communicate electrical signals to the package substrate utilizing the solder balls and without utilizing through-semiconductor vias (TSVs).
US09059178B2	Method for forming carbon nanotubes and carbon nanotube film forming apparatus A method for forming carbon nanotubes includes preparing a target object having a surface on which one or more openings are formed, each of the openings having a catalyst metal layer on a bottom thereof; performing an oxygen plasma process on the catalyst metal layers; and activating the surfaces of the catalyst metal layers by performing a hydrogen plasma process on the metal catalyst layers subjected to the oxygen plasma process. The method further includes filling carbon nanotubes in the openings on the target object by providing an electrode member having a plurality of through holes above the target object in a processing chamber, and then growing the carbon nanotubes by plasma CVD on the activated catalyst metal layer by diffusing active species in a plasma generated above the electrode member toward the target object through the through holes while applying a DC voltage to the electrode member.
US09059177B2	Doping of copper wiring structures in back end of line processing A method of forming a metal interconnect structure includes forming a copper line within an interlevel dielectric (ILD) layer; directly doping a top surface of the copper line with a copper alloy material; and forming a dielectric layer over the ILD layer and the copper alloy material; wherein the copper alloy material serves an adhesion interface layer between the copper line and the dielectric layer.
US09059174B2	Method to reduce metal fuse thickness without extra mask Methods of fabricating a multi-layer semiconductor structure are provided. In one embodiment, a method includes depositing a first dielectric layer over a semiconductor structure, depositing a first metal layer over the first dielectric layer, patterning the first metal layer to form a plurality of first metal lines, and depositing a second dielectric layer over the first metal lines and the first dielectric layer. The method also includes removing a portion of the second dielectric layer over selected first metal lines to expose a respective top surface of each of the selected first metal lines. The method further includes reducing a thickness of the selected first metal lines to be less than a thickness of the unselected first metal lines. A multi-layer semiconductor structure is also provided.
US09059173B2	Electronic fuse line with modified cap An electronic fuse structure having an Mx level including an Mx dielectric, a fuse line, an Mx cap dielectric above at least a portion of the Mx dielectric, and a modified portion of the Mx cap dielectric directly above at least a portion of the fuse line, where the modified portion of the Mx cap dielectric is chemically different from the remainder of the Mx cap dielectric, an Mx+1 level including an Mx+1 dielectric, a first Mx+1 metal, an Mx+1 cap dielectric above of the Mx+1 dielectric and the first Mx+1 metal, where the Mx+1 level is above the Mx level, and a first via electrically connecting the fuse line to the first Mx+1 metal.
US09059172B2	Fuse circuit A fuse circuit includes a plurality of fuses, a plurality of switches and a plurality of trimming components. The fuses are coupled in parallel to a first node and a second node. The first node is coupled to an operating voltage. The switches are coupled to the second node. The trimming components are respectively disposed between the switches and a ground voltage, and coupled to the second node via the switches, respectively. When one of the trimming components is activated, the activated trimming component allows a plurality of branch currents to be generated between the first node and the second node. The branch currents respectively flow through the fuses so that one of the fuses is blown out by the branch current flowing through the one of the fuses.
US09059165B2	Semiconductor device having mesh-pattern wirings Disclosed herein is a device that includes: first lines formed on a first wiring layer extending in a first direction; second lines formed on a second wiring layer extending in a second direction; and conductor plugs connecting the first lines to the second lines such that the first and second lines form a mesh-structure wiring. The first lines include first enlarged portions at intersection positions where the first and second lines cross to each other, a width in the second direction of the first enlarged portions is wider than a line width of the first lines at other than the intersection position. The second lines include second enlarged portions at the intersection positions, a width in the first direction of the second enlarged portions is wider than a line width of the second lines at other than the intersection position.
US09059164B2	Embedded interlevel dielectric barrier layers for replacement metal gate field effect transistors A semiconductor structure may be formed by forming a sacrificial gate above a substrate covered by a hard mask, depositing a first interlevel dielectric (ILD) layer above the sacrificial gate, recessing the first ILD layer to a thickness less than the height of the sacrificial gate, depositing an etch barrier layer above the first ILD layer, depositing a second ILD layer above the etch barrier layer, planarizing the second ILD layer and the etch barrier layer to expose the hard mask using the hard mask as a planarization stop, removing the hard mask and sacrificial gate to form a gate cavity, forming a replacement metal gate in the gate cavity, removing the second ILD layer, and planarizing the replacement metal gate using the etch barrier layer as a planarization stop. A supplementary electrode layer may be formed above the replacement metal gate prior to planarizing the replacement metal gate.
US09059163B2	Structure for logic circuit and serializer-deserializer stack Serializer-deserializer (SERDES) and integrated circuit package including a package substrate, first and second SERDES dies having a SERDES circuit, and a logic die having a logic circuit. The SERDES circuit communicatively connected to the package substrate. The first and second SERDES dies positioned adjacent, in a plane, and disposed on the package substrate. The logic circuit communicatively connected to the SERDES circuit and to the package substrate. The logic die stacked vertically and disposed on the first and second SERDES dies. A method of assembling a SERDES and integrated circuit package including providing a SERDES structure selected from a menu of SERDES die and SERDES circuit combinations. A design structure of a SERDES and integrated circuit package including a package substrate, first and second SERDES dies having a SERDES circuit, and a logic die having a logic circuit. The SERDES circuit communicatively connected to the package substrate.
US09059157B2	Integrated circuit packaging system with substrate and method of manufacture thereof An integrated circuit packaging system and method of manufacture thereof includes: a substrate having a top insulation layer and a top conductive layer; an inter-react layer on the substrate; an integrated circuit die on the substrate; a package body on the inter-react layer and the integrated circuit die; and a top solder bump on the top conductive layer, the top solder bump in a 3D via formed through the package body, the inter-react layer, and the top insulation layer for exposing the top conductive layer in the 3D via.
US09059155B2	Chip package and method for manufacturing the same Various embodiments provide a chip package. The chip package may include a metallic chip carrier; at least one chip carried by the metallic chip carrier; encapsulation material encapsulating the at least one chip and the metallic chip carrier; and a plurality of redistribution layers disposed over the at least one chip opposite the metallic chip carrier, wherein at least one redistribution layer of the plurality of redistribution layers is electrically coupled with the at least one chip.
US09059153B2	Semiconductor device A semiconductor device includes a semiconductor chip, a first electrode terminal, a second electrode terminal, and a connector. The semiconductor chip is carried on the first electrode terminal. The second electrode terminal is separated from the first electrode terminal. The connector includes first through third structural parts. The first structural part is connected to an electrode of the semiconductor chip via the first connecting part; the third structural part is connected to a second electrode terminal via the second connecting part; the second structural part connects the first and third structural parts; and holes are formed on at least one of the first through third structural parts. Additionally, laser ablated recesses may be formed in the first electrode terminal to align the semiconductor chip therewith.
US09059151B2	Integrated circuit packaging system with island terminals and embedded paddle and method of manufacture thereof A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having an upper structure, upper protrusions, and a base side facing away from the upper structure and the upper protrusions; forming tie bars in the leadframe with an opening surrounding the upper structure, the tie bars connected to the upper structure and exposed on the base side; connecting an integrated circuit to the upper protrusions; applying an encapsulant over the integrated circuit, over the upper structure, and in the opening with the base side exposed; removing the tie bars exposing a first surface and a second surface of the encapsulant below the first surface, and forming a die paddle from the upper structure and exposed from the second surface; and removing the leadframe from the base side forming island terminals from the upper protrusions exposed from the second surface and isolated from the die paddle.
US09059147B1	Junction barrier schottky (JBS) with floating islands A Schottky diode includes a Schottky barrier and a plurality of dopant regions disposed near the Schottky barrier as floating islands to function as PN junctions for preventing a leakage current generated from a reverse voltage. At least a trench opened in a semiconductor substrate with a Schottky barrier material disposed therein constitutes the Schottky barrier. The Schottky barrier material may also be disposed on sidewalls of the trench for constituting the Schottky barrier. The trench may be filled with the Schottky barrier material composed of Ti/TiN or a tungsten metal disposed therein for constituting the Schottky barrier. The trench is opened in a N-type semiconductor substrate and the dopant regions includes P-doped regions disposed under the trench constitute the floating islands. The P-doped floating islands may be formed as vertical arrays under the bottom of the trench.
US09059144B2	Method for forming die assembly with heat spreader A method for forming a molded die assembly includes attaching a first major surface of a semiconductor die onto a package substrate; attaching a heat spreader to a second major surface of the semiconductor die, wherein the second major surface is opposite the first major surface, and wherein the semiconductor die, package substrate, and heat spreader form a die assembly; conforming a die release film to a transfer mold; closing the transfer mold around the die assembly such that the die release film is compressed against the heat spreader and a cavity is formed around the die assembly; transferring a thermoset material into the cavity; and releasing the die assembly from the die release film and the transfer mold.
US09059142B2	Semiconductor device having vertical gates and fabrication thereof A method for forming a semiconductor device with a vertical gate is disclosed, including providing a substrate, forming a recess in the substrate, forming a gate dielectric layer on a sidewall and a bottom of the recess, forming an adhesion layer in the recess and on the gate dielectric layer, wherein the adhesion layer is a metal silicide nitride layer, and forming a gate layer in the recess and on the adhesion layer.
US09059130B2	Phase changing on-chip thermal heat sink A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip.
US09059127B1	Packages for three-dimensional die stacks Packages for a three-dimensional die stack, methods for fabricating a package for a three-dimensional die stack, and methods for distributing power in a package for a three-dimensional die stack. The package may include a first lid, a second lid, a die stack located between the first lid and the second lid, a first thermal interface material layer between the first lid and a first die of the die stack, and a second thermal interface material layer between the second lid and the second die of the die stack. The second thermal interface material layer is comprised of a thermal interface material having a high electrical conductivity and a high thermal conductivity.
US09059124B2	Display device and method for manufacturing display device Provided is a display device, including: a substrate; signal lines including a gate line, a data line, and a driving voltage line that collectively define an outer boundary of a pixel area; a transistor connected to the signal line; a first electrode extending across the pixel area and formed on the signal line and the transistor, and connected to the transistor, the first electrode having a first portion overlying only the signal line and the transistor, and a second portion comprising all of the first electrode not included in the first portion; a pixel defining layer formed on only the first portion of the first electrode; an organic emission layer formed on substantially the entire second portion but not on the first portion; and a second electrode formed on the pixel defining layer and the organic emission layer.
US09059120B2	In-situ relaxation for improved CMOS product lifetime Methods and structures for restoring an electrical parameter of a field-effect transistor in an integrated circuit deployed in an end product. A source, a drain, and a gate electrode of a field-effect transistor are coupled with ground. A restoration voltage is applied to a well beneath the field-effect transistor while the source, the drain, and the gate electrode of the field-effect transistor are coupled with ground. The well may be coupled with either a positive supply voltage or ground when a switch is in a first position during normal operation of the integrated circuit and with the restoration voltage when the switch is in a second position during a relaxation operation.
US09059115B2	Methods of forming memory cells; and methods of forming vertical structures Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.
US09059112B1	Display device and manufacturing method thereof A display device includes a first insulating substrate including a display area, a peripheral area and a test area, a gate conductor including a test element group gate electrode, a gate electrode and a gate line on the first insulating substrate, a gate insulating layer on the gate conductor, a semiconductor layer including a test element group semiconductor layer and a pixel semiconductor layer on the gate insulating layer, a data conductor including a test element group source electrode, a test element group drain electrode, a data line including a source electrode, and a drain electrode on the semiconductor layer, a first passivation layer on the data conductor, a test element group common electrode and a pixel common electrode on the first passivation layer, a second passivation layer on the test element group common electrode and the pixel common electrode, and a pixel electrode on the second passivation layer.
US09059111B2	Reliable back-side-metal structure A semiconductor structure, method of manufacturing the same and design structure thereof are provided. The semiconductor structure includes a substrate including a semiconductor layer and a plurality of TSVs embedded therein. At least one TSV has a TSV tip extending from a backside surface of the substrate. The semiconductor structure further includes a multilayer metal contact structure positioned on the backside surface of the substrate. The multilayer metal contact structure includes at least a conductive layer covering the backside surface of the substrate and covering protruding surfaces of the TSV tip. The conductive layer has a non-planar first surface and a substantially planar second surface opposite of the first surface.
US09059103B2	Processing method and storage medium Disclosed is a processing method that removes moisture in a low permittivity film formed on a substrate to be processed which has a damaged layer on the surface thereof while maintaining the specific permittivity or a leakage current value low when the film is subjected to a recovery processing. The method for the recovery processing includes applying, on the damaged layer of the low permittivity film, a first processing gas whose molecules are small sufficient to permeate the inside of the damaged layer of the low permittivity film and which is able to remove the moisture in the damaged layer and a second processing gas which forms a hydrophobic dense reformatted layer on the surface of the damaged layer, thereby allowing the first processing gas and the second processing gas to react with the damaged layer.
US09059099B2	Thermal treatment method of silicon wafer and silicon wafer There is provided a thermal treatment method of a silicon wafer. The method includes the successive steps of: (a) terminating silicon atoms existing on an active surface of the silicon wafer with hydrogen, wherein the active surface is mirror-polished, and a semiconductor device is to be formed on the active surface; (b) terminating the silicon atoms existing on the active surface of the silicon wafer with fluorine; (c) rapidly heating the silicon wafer to a first temperature under an inert gas atmosphere or a reducing gas atmosphere, wherein the first temperature is in a range of 1300° C. to 1400° C.; (d) holding the silicon wafer at the first temperature for a certain time; and (e) rapidly cooling the silicon wafer.
US09059097B2	Inhibiting propagation of imperfections in semiconductor devices Aspects of the disclosure provide a method of inhibiting crack propagation in a silicon wafer. In one embodiment, a method of repairing an imperfection on a surface of a semiconductor device is disclosed. The method includes: screening for imperfections on a surface of a silicon wafer of a semiconductor device; and in response to at least one imperfection on the surface of the silicon wafer, depositing a material on the surface of the silicon wafer.
US09059095B2	Self-aligned borderless contacts using a photo-patternable dielectric material as a replacement contact A photo-patternable dielectric material is provided to a structure which includes a substrate having at least one gate structure. The photo-patternable dielectric material is then patterned forming a plurality of sacrificial contact structures adjacent the at least one gate structure. A planarized middle-of-the-line dielectric material is then provided in which an uppermost surface of each of the sacrificial contact structures is exposed. Each of the exposed sacrificial contact structures is then removed providing contact openings within the planarized middle-of-the-line dielectric material. A conductive metal-containing material is formed within each contact opening.
US09059093B2	Forming finfet cell with fin tip and resulting device Methods for forming a variable fin FinFET cell wherein a plurality of fins is formed above a substrate, a portion of a fin is removed, forming a fin tip, a first area of a gate oxide layer is formed above the fin tip, and a second area of the gate oxide layer is formed above at least a remaining portion of the plurality of fins, wherein the first area is thicker than the second area.
US09059091B2	Transistor having replacement metal gate and process for fabricating the same A transistor is fabricated by removing a polysilicon gate over a doped region of a substrate and forming a mask layer over the substrate such that the doped region is exposed through a hole within the mask layer. An interfacial layer is deposited on top and side surfaces of the mask layer and on a top surface of the doped region. A layer adapted to reduce a threshold voltage of the transistor and/or reduce a thickness of an inversion layer of the transistor is deposited on the interfacial layer. The layer includes metal, such as aluminum or lanthanum, which diffuses into the interfacial layer, and also includes oxide, such as hafnium oxide. A conductive plug, such as a metal plug, is formed within the hole of the mask layer. The interfacial layer, the layer on the interfacial layer, and the conductive plug are a replacement gate of the transistor.
US09059089B2	Method of manufacturing semiconductor device A metal-containing film capable of adjusting a work function is formed. A first source containing a first metal element and a halogen element and a second source containing a second metal element different from the first metal element and an amino group are alternately supplied onto a substrate having a high-k dielectric film to form a composite metal nitride film on the high-k dielectric film.
US09059088B2	Electronic component built-in substrate An electronic component built-in substrate, includes a lower wiring substrate, an electronic component mounted on the lower wiring substrate, an intermediate wiring substrate including an opening portion in which the electronic component is mounted, and arranged in a periphery of the electronic component, and connected to the lower wiring substrate via a first conductive ball, an upper wiring substrate arranged over the electronic component and the intermediate wiring substrate, and connected to the intermediate wiring substrate via a second conductive ball, and a resin filled into respective areas between the lower wiring substrate, the intermediate wiring substrate, and the upper wiring substrate, and sealing the electronic component, wherein the first conductive ball and the second conductive ball are arranged in displaced positions mutually.
US09059082B2	Semiconductor device and operation method for same A semiconductor device includes a first switching element, a second switching element, and at least one third switching element; wherein the third switching element includes a first terminal and a second terminal, wherein each of the first switching element and the second switching element includes an ion conductor, a first electrode which is disposed so as to have contact with the ion conductor and supplies metal ions to the ion conductor, and a second electrode which is disposed so as to have contact with the ion conductor and is less susceptible to ionization than the first electrode; and wherein (a) the first electrode of the first switching element and the first electrode of the second switching element are electrically connected each other, and the first terminal of the third switching element is electrically connected to only the first electrodes which are electrically connected each other or (b) the second electrode of the first switching element and the second electrode of the second switching element are electrically connected each other, and the first terminal of the third switching element is electrically connected to only the second electrodes which are electrically connected each other.
US09059073B2	Method for controlled removal of a semiconductor device layer from a base substrate A method of removing a semiconductor device layer from a base substrate is provided that includes providing a crack propagation layer on an upper surface of a base substrate. A semiconductor device layer including at least one semiconductor device is formed on the crack propagation layer. Next, end portions of the crack propagation layer are etched to initiate a crack in the crack propagation layer. The etched crack propagation layer is then cleaved to provide a cleaved crack propagation layer portion to a surface of the semiconductor device layer and another cleaved crack propagation layer portion to the upper surface of the base substrate. The cleaved crack propagation layer portion is removed from the surface of the semiconductor device layer and the another cleaved crack propagation layer portion is removed from the upper surface of the base substrate.
US09059071B2	Semiconductor device and method of manufacturing the same A semiconductor device provided with a silicon carbide semiconductor substrate, and an ohmic metal layer joined to one surface of the silicon carbide semiconductor substrate in an ohmic contact and composed of a metal material whose silicide formation free energy and carbide formation free energy respectively take negative values. The ohmic metal layer is composed of, for example, a metal material such as molybdenum, titanium, chromium, manganese, zirconium, tantalum, or tungsten.
US09059068B2	Pixel structures of CMOS imaging sensors and fabrication method thereof A method is provided for fabricating a pixel structure of a CMOS transistor. The method includes providing a semiconductor substrate doped with first type doping ions; and forming a trench in the semiconductor substrate by etching the semiconductor substrate. The method also includes forming isolation layers on side surfaces of the trench to prevent dark current from laterally transferring; and forming an epitaxial layer doped with second type doping ions with a doping type opposite to a doping type of the first type doping ions in the trench. Further, the method includes forming a pinning layer on a top surface of the epitaxial layer; and forming a gate structure on a surface of the semiconductor substrate at one side of the epitaxial layer. Further, the method also includes forming a floating diffusion region in the semiconductor substrate at one side of the gate structure far from the epitaxial layer.
US09059065B2	Method of varying gain of amplifying photoelectric conversion device and variable gain photoelectric conversion device Provided is a method of varying the gain of an amplifying photoelectric conversion device and a variable gain photoelectric conversion device which are capable of achieving both signal processing under low illuminance and high-current processing under high light intensity, and thereby capable of securing a wide dynamic range. An amplifying photoelectric conversion part includes a photoelectric conversion element and amplification transistors forming a Darlington circuit. The sources and the drains of field-effect transistors are connected to the bases and the emitters of the amplification transistors, respectively. The gates of the field-effect transistors each function as a gain control part.
US09059064B2	Sensor module with dual optical sensors for a camera A sensor module has first and second sensor arrays formed on a substrate, with the first and second sensor arrays adapted to share common readout circuitry and shared read out for a pair of sensors on a single array.
US09059059B2	Solid state image sensor having a first optical waveguide with one contiguous core and a second optical waveguide with plural cores A solid state image sensor has a plurality of ranging pixels on the imaging area thereof and each of the ranging pixels has a photoelectric conversion section and an optical waveguide arranged at the light-receiving side of the photoelectric conversion section. The optical waveguide has at least two optical waveguides including a first optical waveguide arranged at the light-receiving side and a second optical waveguide arranged at the side of the photoelectric conversion section in the direction of propagation of light. The core region of the first optical waveguide shows a refractive index lower than the refractive index of the core region of the second optical waveguide and is designed so as to show a high light-receiving sensitivity relative to light entering at a specific angle.
US09059057B2	Image sensor having compressive layers An image sensor device including a semiconductor substrate that includes an array region and a black level correction region. The array region contains a plurality of radiation-sensitive pixels. The black level correction region contains one or more reference pixels. The substrate has a front side and a back side. The image sensor device includes a first compressively-stressed layer formed on the back side of the substrate. The first compressively-stressed layer contains silicon oxide, and is negatively charged. The second compressively-stressed layer contains silicon nitride, and is negatively charged. A metal shield is formed over at least a portion of the black level correction region. The image sensor device includes a third compressively-stressed layer formed on the metal shield and the second compressively-stressed layer. The third compressively-stressed layer contains silicon oxide. A sidewall of the metal shield is protected by the third compressively-stressed layer.
US09059055B2	Solid-state imaging device According to one embodiment, a solid-state imaging device includes a first structure part, a second structure part, and a third structure part. The first structure part includes a first insulating body and a first photoelectric conversion part. The first photoelectric conversion part is periodically disposed in the first insulating body and selectively absorbs light in the first wavelength band. The second structure part includes a second insulating body and a second photoelectric conversion part. The second photoelectric conversion part is periodically disposed in the second insulating body and selectively absorbs light in the second wavelength band. The third structure part includes a third photoelectric conversion part. The third photoelectric conversion part absorbs light in a third wavelength band. When viewed in the light incidence direction, the first photoelectric conversion part, the second photoelectric conversion part, and the third photoelectric conversion part are disposed in this order.
US09059053B2	Multi-die stack structure A multi-die stack structure including N dies stacked vertically is described. N is an integer larger than or equal to 2. Each die includes N die-specific input pads, wherein a specific pad among the N pads is for the input of the die. The specific pad of each die above the bottom die is electrically connected with a different pad of the bottom die other than the specific pad of the bottom die, via at least one TSV and, when not being in the die neighboring to the bottom die, also via a different pad of each underlying die above the bottom die. The specific pad of the bottom die is electrically connected with at least one pad of the overlying die(s) that is not the specific pad of any overlying die and not any pad electrically connected with the specific pad of any overlying die.
US09059046B2	Thin film transistor, thin film transistor array panel, and method of manufacturing a thin film transistor array panel A thin film transistor array panel according to an exemplary embodiment of the invention includes: a substrate; a gate line positioned on the substrate and including a gate electrode; a gate insulating layer positioned on the gate line; an oxide semiconductor layer positioned on the substrate; a source electrode and a drain electrode positioned on the oxide semiconductor layer; a first insulating layer positioned on the source electrode and the drain electrode and including a first contact hole; a data line positioned on the first insulating layer and intersecting the gate line; and a pixel electrode over the first insulating layer. The source electrode and the drain electrode each comprise a metal oxide. The data line is electrically connected to the source electrode through the first contact hole.
US09059045B2	Semiconductor device and manufacturing method thereof A TFT is manufactured using at least five photomasks in a conventional liquid crystal display device, and therefore the manufacturing cost is high. By performing the formation of the pixel electrode 127, the source region 123 and the drain region 124 by using three photomasks in three photolithography steps, a liquid crystal display device prepared with a pixel TFT portion, having a reverse stagger type n-channel TFT, and a storage capacitor can be realized, FIG. 2.
US09059043B1	Fin field effect transistor with self-aligned source/drain regions A gate cavity is formed over a semiconductor fin by forming a disposable gate structure and a planarization dielectric layer over the semiconductor fin, and by removing the disposable gate structure. A doped silicate glass spacer including an electrical dopant is formed on sidewalls of the gate cavity by deposition and an anisotropic etch of a conformal doped silicate glass layer. A gate spacer including a diffusion barrier material is formed on inner sidewalls of the doped silicate glass spacer. A replacement gate structure is formed within the gate cavity, and source/drain regions are formed in portions of the semiconductor fin by outdiffusion of the electrical dopant during an anneal. The source/drain regions are formed within the semiconductor fin, and are self-aligned to the replacement gate electrode.
US09059042B2	Methods of forming replacement gate structures and fins on FinFET devices and the resulting devices One method disclosed includes, among other things, removing a sacrificial gate structure to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to define a fin structure in a layer of semiconductor material using a patterned hard mask exposed within the replacement gate cavity as an etch mask and forming a replacement gate structure in the replacement gate cavity around at least a portion of the fin structure.
US09059039B2	Reducing wafer bonding misalignment by varying thermal treatment prior to bonding A bonding layer of the first wafer article is thermally treated and a bonding layer of a second wafer article is thermally treated in accordance with first and second process parameters, respectively prior to bonding the first wafer article with the second wafer article. First and second grid distortion in the first and second wafer articles is measured and a difference is determined between the first and second grid distortions. A prediction is made for maintaining the difference within a prescribed tolerance. At least one of the first process parameters and the second process parameters can be conditionally varied in accordance with the prediction. The thermally treating of the first wafer article and the thermally treating of the second wafer article can then be performed with respect to another pair of the first and second wafer articles prior to bonding the another pair of wafer articles to one another through their respective bonding layers.
US09059038B2	System for in-situ film stack measurement during etching and etch control method Disclosed is an in-situ optical monitor (ISOM) system and associated method for controlling plasma etching processes during the forming of stepped structures in semiconductor manufacturing. The in-situ optical monitor (ISOM) can be optionally configured for coupling to a surface-wave plasma source (SWP), for example a radial line slotted antenna (RLSA) plasma source. A method is described to correlate the lateral recess of the steps and the etched thickness of a photoresist layer for use with the in-situ optical monitor (ISOM) during control of plasma etching processes in the forming of stepped structures.
US09059036B2	Semiconductor integrated circuit including memory cells A semiconductor integrated circuit includes a plurality of memory cells arranged in a cell-placement row extending in a first direction, a first N well and a first P well arranged in a second direction perpendicular to the first direction in each area of the memory cells, and a second N well and a second P well each having the same length as a width of the cell-placement row and situated between at least two adjacent memory cells of the plurality of memory cells, wherein the first N well and the second N well are integrated, and the first P well and the second P well are integrated.
US09059035B2	Nonvolatile semiconductor device and its manufacturing method having memory cells with multiple layers A nonvolatile semiconductor memory device a first memory cell array layer, a first insulation layer formed on top of the first memory cell array layer, a second memory cell array layer formed on the first insulation layer, and a control gate. The first and second memory cell array layers have first and second NAND cell units provided with multiple first and second memory cells connected in series in a first direction and the first and second selection gates connected at both ends of the multiple first and second memory cells. The control gate is formed via an insulation layer between gates of the memory cells on both sides thereof in the first direction, and extends in the second direction perpendicular to the first direction.
US09059033B2	Semiconductor device with pads of enhanced moisture blocking ability A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a Pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film.
US09059031B2	DRAM with dual level word lines A top semiconductor layer and conductive cap structures over deep trench capacitors are simultaneously patterned by an etch. Each patterned portion of the conductive cap structures constitutes a conductive cap structure, which laterally contacts a semiconductor material portion that is one of patterned remaining portions of the top semiconductor layer. Gate electrodes are formed as discrete structures that are not interconnected. After formation and planarization of a contact-level dielectric layer, passing gate lines are formed above the contact-level dielectric layer in a line level to provide electrical connections to the gate electrodes. Gate electrodes and passing gate lines that are electrically connected among one another constitute a gate line that is present across two levels.
US09059028B2	Semiconductor device and method for manufacturing same The objective of the present invention is to provide a semiconductor device provided with a resistance-variable element having sufficient switching property and exhibiting high reliability and high densification as well as good insulating property.The present invention provides a semiconductor device comprising a resistance-variable element provided within multiple wiring layers on a semiconductor substrate, wherein the resistance-variable element comprises a laminated structure in which a first electrode, a first ion-conductive layer of valve-metal oxide film, a second ion-conductive layer containing oxygen and a second electrode are laminated in this order, and the wiring of the multiple wiring layers also serves as the first electrode.
US09059026B2	3-D inductor and transformer In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture.
US09059023B2	Semiconductor device with reduced turn-on resistance and method of fabricating the same A semiconductor device includes a gate pattern over source and drain regions. The gate pattern includes a first gate adjacent the source region and a second gate adjacent the drain region. A concentration of dopants in the first gate is higher than a concentration of dopants in the second gate. As a result, channels are produced between the source and drain regions based on different threshold voltages.
US09059021B2	FinFET device A method for forming a field effect transistor device includes patterning an arrangement of fin portions on a substrate, patterning a gate stack portion over portions of the fin portions and the substrate, growing an epitaxial material from the fin portions that electrically connects portions of adjacent fin structures, and removing a portion of the gate stack portion to expose a portion of the substrate.
US09059020B1	Implementing buried FET below and beside FinFET on bulk substrate A method and circuit for implementing an enhanced transistor topology enabling enhanced current capability with added device drive strength with buried field effect transistors (FETs) below and beside a traditional FinFET on a bulk substrate, and a design structure on which the subject circuit resides are provided. Buried field effect transistors (FETs) are formed on either side and under the traditional FinFET. The gate of the FinFET becomes the gate of the parallel buried (FETs) and allows self alignment to the underlying sources and drains of the buried FET devices in the bulk semiconductor.
US09059017B2	Source/drain-to-source/drain recessed strap and methods of manufacture of same A structure and a method of making the structure. The structure includes first and second semiconductor regions in a semiconductor substrate and separated by a region of trench isolation in the semiconductor substrate; a first gate electrode extending over the first semiconductor region; a second gate electrode extending over the second semiconductor region; a trench contained in the region of trench isolation and between and abutting the first and second semiconductor regions; and an electrically conductive strap in the trench, the strap electrically connecting the first and second semiconductor regions.
US09059014B2	Integrated circuit diode A method includes forming isolation regions in a semiconductor substrate to define a first field effect transistor (FET) region, a second FET region, and a diode region, forming a first gate stack in the first FET region and a second gate stack in the second FET region, forming a layer of spacer material over the second FET region and the second gate stack, forming a first source region and a first drain region in the first FET region and a first diode layer in the diode region using a first epitaxial growth process, forming a hardmask layer over the first source region, the first drain region, the first gate stack and a portion of the first diode layer, and forming a second source region and a second drain region in the first FET region and a second diode layer on the first diode layer using a second epitaxial growth process.
US09059013B2	Self-formation of high-density arrays of nanostructures A method for forming nanostructures includes bonding a flexible substrate to a crystalline semiconductor layer having a two-dimensional material formed on a side opposite the flexible substrate. The crystalline semiconductor layer is stressed in a first direction to initiate first cracks in the crystalline semiconductor layer. The first cracks are propagated through the crystalline semiconductor layer and through the two-dimensional material. The stress of the crystalline semiconductor layer is released to provide parallel structures including the two-dimensional material on the crystalline semiconductor layer.
US09059012B2	Epitaxial layer wafer having void for separating growth substrate therefrom and semiconductor device fabricated using the same An epitaxial wafer having a void for separation of a substrate and a semiconductor device fabricated using the same. The epitaxial wafer includes a substrate, a mask pattern disposed on the substrate and comprising a masking region and an opening region, and an epitaxial layer covering the mask pattern. The epitaxial layer includes a void disposed on the masking region. The epitaxial layer can be separated from the growth substrate by applying chemical lift-off or stress lift-off, at the void.
US09059008B2	Resurf high voltage diode A trench-isolated RESURF diode structure (100) is provided which includes a substrate (150) in which is formed anode (130, 132) and cathode (131) contact regions separated from one another by a shallow trench isolation region (114, 115), along with a buried cathode extension region (104) formed under a RESURF anode extension region (106, 107) such that the cathode extension region (104) extends beyond the cathode contact (131) to be sandwiched between upper and lower regions (103, 106, 107) of opposite conductivity type.
US09059006B2	Replacement-gate-compatible programmable electrical antifuse After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).
US09059001B2	Semiconductor device with biased feature A method of fabricating a semiconductor device includes forming a plurality of line element on a provided substrate. The plurality of line elements includes a first line element having a first region having a first width and a biased region having a second width. The second width different than the first width. Spacer elements are then formed abutting sidewalls of each of the plurality of line elements including the biased region where the spacer elements may be shifted. After forming the spacer elements, the plurality of line elements from the substrate are removed from the substrate. An underlying layer is etched using the spacer elements after removing the plurality of line elements.
US09058997B2	Process of multiple exposures with spin castable films Methods of multiple exposure in the fields of deep ultraviolet photolithography, next generation lithography, and semiconductor fabrication comprise a spin-castable methodology for enabling multiple patterning by completing a standard lithography process for the first exposure, followed by spin casting an etch selective overcoat layer, applying a second photoresist, and subsequent lithography. Utilizing the etch selectivity of each layer, provides a cost-effective, high resolution patterning technique. The invention comprises a number of double or multiple patterning techniques, some aimed at achieving resolution benefits, as well as others that achieve cost savings, or both resolution and cost savings. These techniques include, but are not limited to, pitch splitting techniques, pattern decomposition techniques, and dual damascene structures.
US09058996B2	Method for generating mask data and method for manufacturing integrated circuit device According to one embodiment, a method for generating mask data is configured to form a circuit pattern on a substrate using a directed self-assembly material. The method includes extracting a first region, setting a second region and setting a third region. The first region does not existing in the circuit pattern and existing in an initial pattern. The initial pattern includes a plurality of interconnect patterns extending in a first direction. The second region is formed by elongating the first region in a second direction intersecting the first direction. The second region straddles the first region in the second direction. The third region includes at least one of the second regions. The directed self-assembly material is disposed in the third region.
US09058995B2	Self-protected drain-extended metal-oxide-semiconductor transistor Device structures, design structures, and fabrication methods for a drain-extended metal-oxide-semiconductor (DEMOS) transistor. A first well of a first conductivity type and a second well of a second conductivity type are formed in a device region. The first and second wells are juxtaposed to define a p-n junction. A first doped region of the first conductivity type and a doped region of the second conductivity type are in the first well. The first doped region of the first conductivity type is separated from the second well by a first portion of the first well. The doped region of the second conductivity type is separated from the second well by a second portion of the first well. A second doped region of the first conductivity type, which is in the second well, is separated by a portion of the second well from the first and second portions of the first well.
US09058990B1	Controlled spalling of group III nitrides containing an embedded spall releasing plane A spall releasing plane is formed embedded within a Group III nitride material layer. The spall releasing plane includes a material that has a different strain, a different structure and a different composition compared with the Group III nitride material portions that provide the Group III nitride material layer and embed the spall releasing plane. The spall releasing plane provides a weakened material plane region within the Group III nitride material layer which during a subsequently performed spalling process can be used to release one of the portions of Group III nitride material from the original Group III nitride material layer. In particular, during the spalling process crack initiation and propagation occurs within the spall releasing plane embedded within the original Group III nitride material layer.
US09058986B2	Dual-gate FinFET Designs and fabrication of a FinFET are provided. In one implementation, the fabrication can include forming a dielectric stripe on a substrate; implanting ions to the substrate by using the dielectric stripe as a mask so as to convert a surface layer of the substrate to an amorphous layer; forming an amorphous semiconductor layer on the substrate covering the dielectric stripe and recrystallizing each of the amorphous layer and the amorphous semiconductor layer to be a monocrystalline layer; processing regions beside two ends of the dielectric stripe to form a protective layer, the regions being predesigned as source and drain regions; forming recrystallized semiconductor spacers at two sides of the dielectric stripe uncovered by the protective layer, and forming recrystallized semiconductor blocks on regions covered by the protective layer; removing the dielectric stripe between the spacers so that the spacers can be formed as Fin bodies.
US09058984B2	Method for fabricating semiconductor device A semiconductor device includes a dielectric layer in which zirconium, hafnium, and a IV group element are mixed. A method for fabricating a capacitor includes forming a bottom electrode, forming the dielectric layer and forming a top electrode over the dielectric layer.
US09058981B2	Dielectric composition for thin-film transistors An electronic device, such as a thin-film transistor, includes a substrate and a dielectric layer formed from a dielectric composition. The dielectric composition includes a dielectric material, a crosslinking agent, and a thermal acid generator. In particular embodiments, the dielectric material comprises a lower-k dielectric material and a higher-k dielectric material. When deposited, the lower-k dielectric material and the higher-k dielectric material form separate phases. The thermal acid generator allows the dielectric layer to be cured at relatively lower temperatures and/or shorter time periods, permitting the selection of lower-cost substrate materials that would otherwise be deformed by the curing of the dielectric layer.
US09058978B2	Memory device and method of manufacturing the same A memory device includes a plurality of memory elements, each having a first electrode, a second electrode, and a memory layer between the first electrode and the second electrode. The plurality of memory layers are in a dotlike pattern. Two adjacent first electrodes share a same memory layer.
US09058977B2	Substrate cleaning apparatus and substrate cleaning method A substrate cleaning apparatus performs scrub cleaning of a surface of a substrate such as a semiconductor wafer. The substrate cleaning apparatus includes a cleaning member having a lower-end contact surface, and a cleaning liquid supply nozzle configured to supply a cleaning liquid to the surface of the substrate. The cleaning member is configured to scrub-clean the surface of the substrate by moving the cleaning member in one direction while the cleaning member is being rotated about its rotational axis and by rubbing the lower-end contact surface of the cleaning member against the surface of the substrate which is being rotated horizontally in the presence of the cleaning liquid. The cleaning member has an inverted truncated-cone shape wherein the angle α between the lower-end contact surface and a straight line on an outer circumferential surface of the cleaning member is larger than 90° and is not more than 150°.
US09058976B2	Cleaning composition and process for cleaning semiconductor devices and/or tooling during manufacturing thereof Cleaning solutions and processes for cleaning semiconductor devices or semiconductor tooling during manufacture thereof generally include contacting the semiconductor devices or semiconductor tooling with an acidic aqueous cleaning solution free of a fluorine containing compound, the acidic aqueous cleaning solution including at least one antioxidant and at least one non-oxidizing acid.
US09058971B2	Electro-optical module An electro-optical module is provided, which includes: a substrate having a first surface with a groove and an opposite second surface; a plurality of support members disposed on the first surface of the substrate; at least an electro-optical element having opposite active and non-active surfaces and disposed in the groove of the substrate via the non-active surface thereof; an interposer disposed on the first surface of the substrate and the electro-optical element for electrically connecting the electro-optical element to the substrate, wherein the interposer has a through hole corresponding in position to the active surface of the electro-optical element; and a transparent plate disposed over the first surface of the substrate and the interposer through the support members and having a lens portion corresponding in position to the through hole of the interposer, thereby reducing signal losses, improving alignment precision, and achieving preferred thermal dissipation and EMI shielding effects.
US09058970B2	Gas-discharge lamp The invention describes a gas-discharge lamp (1) comprising a vessel (5), which vessel is partially coated with an essentially rectangular stripe (Sv) arranged circumferentially on a surface of the vessel, and wherein a first long side (14) of the stripe is situated close to a base (6) of the lamp, and the width (wv) of the stripe is such that a first angle (αv2) subtended at a lamp center between a radius (r) and a point on the first long side (14) of the stripe comprises at most 55°, and a second angle (αv1) subtended at the lamp center between the radius and a point on a second long side (15) of the stripe comprises at most 50°. The invention also describes a reflector for a lamp, comprising a reflective interior surface realized to deflect light originating from the lamp outward to give a specific beam profile with a bright/dark cutoff line and a shoulder, and wherein the lamp, in particular a lamp as described above, is positioned horizontally in the reflector, and wherein the reflective interior surface comprises at least one beam-shaping region realized to deflect a portion of the light emitted from the lamp between 7.5° and 15° below a horizontal plane, at a specific region within the beam profile.
US09058969B2	Extraction and detection system and method An apparatus, system and method for the continuous flow extraction, collection and analysis of small amounts of energetic substance/s and their reacted/unreacted residue/s in real time are provided. The apparatus includes an agitator that generates a particulate material from a surface. A vacuum gathers particulate material which is provided to a mixing module. The mixing module creates a supercritical matrix containing the particulate matter. A separator separates and removes waste in the supercritical matrix from the supercritical matrix. Concentrated particulate material from the supercritical matrix is provided to a mass spectrometer for analysis and detection of a target material in proximate real-time. In one embodiment, the separator provides the supercritical matrix to a tube arm. The tube arm is heated to reduce solvent in the supercritical matrix. A collector in the tube arm concentrates particulate material, which is volatilized by a laser. Volatilized particulate material is provided to the mass spectrometer. In another embodiment, the separator provides the supercritical matrix to an electrospray or APCI module whose output is provided direct to the mass spectrometer.
US09058961B2	Rotatable sputter target comprising an end-block with a liquid coolant supply system A tube target with an end block for supplying coolant to the tube target is provided. The end block comprises a rotatably mounted carrier shaft for holding and rotating the tube target; a connecting sleeve arranged in the carrier shaft; a sealing element for the tube target on its end facing the end block; a coolant inlet port in the interior of the tube target; and a coolant outlet port. The coolant outlet port is formed by at least one aperture in the sealing element. The aperture is located in the vicinity of the wall of the tube target, and eccentrically to the rotational axis of the tube target.
US09058960B2	Compression member for use in showerhead electrode assembly A compression member for use in a showerhead electrode assembly of a capacitively coupled plasma chamber. The member applies a compression force to a portion of a film heater adjacent a power supply boot on an upper surface of a thermal control plate and is located between the thermal control plate and a temperature-controlled top plate. The member is composed of an electrically insulating elastomeric material which can work over a large range of compressions and temperatures.
US09058959B2	Scanning ion microscope and secondary particle control method The present invention is provided to enable a detailed inspection of a specimen and preventing a distortion of an observation image even when a specimen containing an insulating material is partially charged. For a scanning ion microscope utilizing a gas field ionization ion source, a thin film is disposed between an ion optical system and a specimen, and an ion beam is applied to and transmitted through this thin film in order to focus a neutralized beam on the specimen. Furthermore, an electrode for regulating secondary electrons discharged from this thin film is provided in order to eliminate mixing of noises into an observation image.
US09058956B2	Exposure apparatus for forming a reticle A method of forming a reticle includes: loading a blank reticle; projecting an electron beam; moving a second aperture plate having a first pattern aperture and a second pattern aperture so that the first pattern aperture is directly overlapped by a first aperture of a first aperture plate, the electron beam passing through the first pattern aperture after passing the first aperture; exposing the blank reticle with the electron beam after the electron beam passes the first pattern aperture, to form a first exposure pattern; moving the second aperture plate so that the second pattern aperture is directly overlapped by the first aperture of the first aperture plate, the electron beam passing through the second pattern aperture after passing the first aperture; exposing the blank reticle with the electron beam after the electron beam passes the second pattern aperture, to form a second exposure pattern; and developing the blank reticle having the first and second exposure patterns to form the reticle having first and second patterns.
US09058951B2	Electrical switch An electrical switch, in particular an electrical circuit breaker, is disclosed including an overcurrent trip device which cuts off the flow of current through the switch in the event of an overcurrent situation. In at least one embodiment, a partial current of the current flowing through the electrical switch flows through a tripping arrangement of the overcurrent trip device and at least one further partial current of the current flowing through the electrical switch is conducted past the tripping arrangement.
US09058949B2	Thermal switch A thermal switch comprises a first and second electrically conducting terminals and a pre-stressable electrically conducting connecting device such as a compression spring member. The connecting device, in a compressed state, contacts at most one of the first and second terminals, and, in a released state, electrically connects the first and second terminals. The thermal switch further comprises a retainer device retaining the connecting device in the compressed state. The retainer device comprises a retaining material that melts at or above a predetermined temperature for releasing the connecting device into the released state. In the compressed state of the connecting device, the first and second terminals are electrically insulated from each other by a hollow space formed between the connecting device and at least one of the first and second terminals.
US09058947B2	Puffer-type gas circuit-breaker A puffer-type gas circuit-breaker having improved interruption performance and dielectric performance, comprising: a partition wall provided in a stationary cylinder on the moving side of the circuit-breaker to form an intra-stationary cylinder space, a mechanical puffer chamber provided adjacent to one flange of the partition wall and a hot gas exhaust chamber provided on the same side as another flange of the partition wall, wherein the stationary cylinder has gas inlet holes communicated with the intra-stationary cylinder space and formed on one side relative to a virtual plane that bisects the stationary cylinder in a radial direction, gas outlet holes communicated with the intra-stationary cylinder space, and hot gas exhaust openings communicated with the hot gas exhaust chamber, further communicated with the puffer shaft flow hole after an arc is generated and formed in radial directions of the stationary cylinder and on the other side relative to the virtual plane.
US09058945B2	Electrical switch and method of producing the same A method of producing an electrical switch which includes a rolling ball movable within a housing thereof to bridge and contact an array of pin terminals includes the steps of forming the pin terminals by using a punching process, wherein one or more smooth burr-free surfaces are formed on each of the pin terminals; and assembling the pin terminals, the housing and the rolling ball by spacing apart the pin terminals along a polygonal line and by arranging the smooth burr-free surfaces of the pin terminals to face toward each other substantially along diagonal lines such that the rolling ball contacts only the smooth burr-free surfaces when bridging the pin terminals.
US09058943B2	Keyboard with gel containing chambers in key cap A device is provided. The device includes a first T-shaped structure defined via a first leg and a first platform. The device further includes a key cap with an interior open chamber. The cap is mounted onto the first structure such that the chamber contains the first platform. The device also includes a second T-shaped structure defined via a second leg and a second platform. The first leg vertically moves within the second leg such that the cap travels between a non-pressed position and a pressed position. The cap is raised above the second platform in the non-pressed position. The cap is in contact with the second platform in the pressed position.
US09058941B2	Floating switch assemblies and methods for making the same Switch assemblies that mitigate stack up variations and methods of making the same are provided. The stack up variations are mitigated by embodiments that use a floating switch design. The floating switch design may eliminate height variations in the stack up by directly mounting an activation assembly to a support bracket. This ensures that the stack up height of the activation assembly and support bracket remain fixed, independent of a flexible printed circuit board (PCB) that may also be secured to the activation assembly. This way, regardless of the thickness of the flexible PCB and any height variations in solder used to secure the flexible PCB to the activation assembly, the stack up height of the activation assembly and support bracket remains fixed.
US09058940B2	Cutout switch or changeover switch having breakable permanent electrical junction The present invention relates to an electric switch having a hollow body defining a cavity, an actuator, and a slide mounted in said cavity. Under the action of the actuator, the slide is suitable for passing from a first position, in which at least one conductive portion of the slide is electrically connected via permanent breakable electrical junctions to at least two primary electrically-conductive studs that lead laterally into said cavity to a second position in which at least one of said primary electrically-conductive studs is no longer electrically connected to said conductive portion of the slide.
US09058936B2	Multilayer ceramic capacitor and manufacturing method thereof A multilayer ceramic capacitor uses internal electrodes which are embedded between the dielectric layers and whose primary constituent is Cu, wherein when the composition of the dielectric layer is expressed by 100CaxZrO3+aMnO2+bLiO1/2+cBO3/2+dSiO2+eAlO3/2, the contents of the respective constituents are 1.5≦a≦4.5 mol, 0.8≦b/(c+d)≦2.0, 0.9≦d/c≦1.5, and 0≦e≦0.3 mol relative to 100 mol of CaxZrO3 (where 1.005≦x≦1.06), and when 10≦(b+c+d)≦14.9, an upper limit of x is defined by a line passing through (10, 1.03) and (14.9, 1.06), and a lower limit of x is defined by a line passing through (10, 1.005) and (14.9, 1.02), wherein the coordinates indicate ((b+c+d), x).
US09058934B2	Method of forming a VDF oligomer or co-oligomer film on a substrate and an electrical device comprising the VDF oligomer or co-oligomer film on the substrate A method of forming a vinylidene fluoride (VDF) oligomer or co-oligomer film on a substrate is disclosed. The method comprises forming a VDF oligomer or co-oligomer precursor solution; depositing the VDF oligomer or co-oligomer precursor solution onto the substrate to form a preliminary VDF oligomer or co-oligomer film on the substrate; and applying uniaxial pressure on the preliminary VDF oligomer or co-oligomer film and the substrate at an elevated temperature to form the VDF oligomer or co-oligomer film on the substrate. The substrate may comprise a metal surface which may be used as a bottom electrode and a top electrode may be deposited on the VDF oligomer or co-oligomer film. The VDF oligomer or co-oligomer film, the bottom electrode on the substrate and the top electrode on the VDF oligomer or co-oligomer film form an electrical device.
US09058931B2	Composite electrode structure A method of forming a composite involving the steps of providing a porous carbon electrode structure having a surface and pores wherein the pores have an average diameter that ranges from about 2 nm to about 1 μm, depositing a coating comprising FeOx via self-limiting electroless deposition without completely filling or obstructing a majority of the pores, wherein the coating comprising FeOx covers most to all of the interior and exterior surfaces of the prefabricated porous carbon electrode structure and can be deposited in a homogenous form and wherein it can be used directly as an electrode without requiring additional conductive additives or binders to be processed into a device-suitable electrode.
US09058930B2	Multiple winding apparatus and multiple winding method for coil The multiple winding apparatus for coil includes a winding core, a spindle shaft on a tip end of which the winding core is removably mounted and which rotates together with the winding core, a wire rod feeding flyer which feeds a wire rod while rotating around the winding core mounted on the spindle shaft, a winding core removal mechanism which removes the winding core from the spindle shaft by moving the winding core in an axial direction, a supporting member which faces the spindle shaft and supports a plurality of the winding cores removed by the winding core removal mechanism at desired intervals in the axial direction, and a support member moving mechanism which moves the supporting member supporting the winding cores from a position facing the spindle shaft in a direction away from the spindle shaft.
US09058926B2	Fluid insulated high voltage coil Exemplary embodiments include a fluid insulated high voltage coil having closed tank for an insulation fluid and a high voltage coil arranged therein with at least two taps. An insulation tube extends into the tank, where the inner part of the tube is accessible from an outer side of the tank. Electric contact elements extend through the tube walls along its longitudinal axis, where at least some of the contact elements are electrically connected with the taps. A removable column-like electrical interaction device is arranged within the inner part of the insulation tube, which is electrically connected to the at least two taps by means of the contact elements.
US09058917B2	Fatigue resistant metallic moisture barrier in submarine power cable A submarine power cable (10) has an electrical conductor (1) surrounded by an insulation (2,3,4), said insulation being surrounded by a metallic moisture barrier (5) characterized in that the cable (10) further comprises a semi-conductive adhesive layer (6) surrounding said metallic moisture barrier (5), and a semi-conductive polymeric jacket (7) able to be in electrical contact with sea water surrounding said semi-conductive adhesive layer (6), the overlaying of the metallic moisture barrier (5), the semi-conductive adhesive layer (6) and the semi-conductive polymeric jacket (7) forming a 3-layer sheath.
US09058912B2	Paste composition and dielectric composition using the same A paste composition containing an inorganic filler, a resin and a solvent, wherein the paste composition is characterized in that it contains one or more solvents of which the boiling point is 160° C. or higher and an inorganic filler of which the mean particle diameter is 5 μm or smaller, and the total content of the solvent is 25 wt % or less based on the total amount of the paste composition, and a dielectric composition containing an inorganic filler and resin, wherein the inorganic filler includes inorganic fillers of at least two kinds of mean particle diameter, and the greatest mean particle diameter of said mean particle diameters is 0.1-5 μm and is 3 times or more the minimum mean particle diameter.
US09058911B2	Shielded electric wire wrapped with metal foil A shielded electric wire wrapped with metal foil includes coated conductive wires and a drain wire provided along the length of the coated conductive wires and grounded at the ends of the coated conductive wires and a metal foil member wrapped around the coated conductive wires and the drain wire forming a shielding layer covering the periphery of the coated conductive wires and the drain wire, wherein foil electrically connected parts, which are electrically connected to the drain wire, are provided at both ends or positions near both the ends of the coated conductive wires.
US09058910B2	Charged particle beam acceleration method and apparatus as part of a charged particle cancer therapy system The invention comprises a charged particle beam acceleration method and apparatus used as part of multi-axis charged particle radiation therapy of cancerous tumors. The accelerator includes a synchrotron having advances in turning magnets, edge focusing magnets, magnetic field concentration magnets, and extraction and intensity control elements that minimize the overall size of the synchrotron, provide a tightly controlled proton beam, directly reduce the size of required magnetic fields, directly reduces required operating power, and allows independent energy and intensity control of extracted charged particles from the synchrotron.
US09058905B2	Automated inside reactor inspection system An apparatus and method for maintaining contact between a pod of transducers and an inner surface of a reactor pressure vessel filled with water of a nuclear power plant is described. An underwater carriage carries the pod of transducers each of which is independently movable and are constantly urged against the surface of the vessel during inspection. Each transducer is independently pivotable about two axes. Each transducer emits and receives signals to detect any flaws of potential problems in the reactor pressure vessel.
US09058901B2	Semiconductor apparatus with boundary scan test circuit A semiconductor apparatus includes: a receiver configured to receive a plurality of input signals through a plurality of pads; a signal processing unit configured to process the input signals received by the receiver and output the processed signals as a plurality of internal signals; a MUX unit configured to select the plurality of internal signals as a plurality of MUX output or select test input data and a plurality of latch signals as the plurality of MUX output signals in response to an input/output select signal; a latch unit configured to output the plurality of MUX output signals as the plurality of latch signals and a final output signal in response to a latch clock signal; and a clock selection unit configured to output any one of a test clock signal and an internal clock signal as the latch clock signal in response to a test mode signal.
US09058895B2	Self-refresh control device and method for reducing a current requisite for self-refresh operation using the same Provided is a device and method for controlling self-refresh which reduces current when a semiconductor device stays in a self-refresh operation. The device for controlling self-refresh includes a bulk voltage controller configured to combine an idle signal indicating an active termination state of a bank and a self-refresh signal so as to generate a control signal for controlling a bulk voltage, a bulk voltage driver configured to vary a level of the bulk voltage in response to the control signal, and output the bulk voltage with a different level, and a refresh controller configured to output the self-refresh active signal upon receiving the bulk voltage as a bulk bias voltage.
US09058894B2	Device, system, and method of memory allocation Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random Access Memory (DRAM) units to store data, wherein each DRAM unit includes a plurality of banks and each bank is divided into a plurality of sub-banks; and a memory management unit to allocate a set of interleaved sub-banks of said DIMM to a memory page of an Operating System, wherein a combined memory size of the set of interleaved sub-banks is equal to a size of the memory page of the Operating System.
US09058893B2	Shift register and the driving method thereof, gate driving apparatus and display apparatus The present invention provides a shift register, a driving method, a gate driving apparatus and a display apparatus. Said shift register comprises a pull-up unit, a reset unit, a pull-down unit and a signal output; the pull-up unit is connected to said signal output and pulls up an output signal; the reset unit is connected to a control end of said pull-up unit and said signal output respectively and resets the potential of the control end of said pull-up unit after said output signal is at high level; the pull-down unit is connected to a control end of said pull-up unit and said signal output respectively and pulls down the potential of the control end of said pull-up unit and said output signal after said reset unit has reset the potential of the control end of said pull-up unit, so that said pull-up unit switches off.
US09058892B2	Semiconductor device and shift register Data can be stored even when the supply of a power source voltage is stopped. A semiconductor device includes a logic circuit to which a data signal is input through an input terminal; a capacitor having a pair of electrodes, one of which is supplied with a high power source potential or a low power source potential and the other of which is supplied with a potential of the input terminal of the logic circuit, so that data of the data signal is written as stored data to the capacitor; and a transistor for controlling conduction between the input terminal of the logic circuit and the other of the pair of electrodes of the capacitor, thereby controlling rewriting, storing, and reading of the stored data. The off-state current per micrometer of channel width of the transistor is lower than or equal to 100 zA.
US09058889B2	Pulse output circuit, display device, and electronic device An object is to suppress the stress applied to a transistor as well as suppressing generation of defective operation. In a pulse output circuit having a function of outputting a pulse signal and including a transistor that controls whether to set the pulse signal to high level, in a period during which the pulse signal output from the pulse output circuit is at low level, the potential of a gate of a transistor is not set to a constant value but intermittently set to a value higher than the potential VSS. Accordingly, the stress to the transistor can be suppressed.
US09058888B2	Control circuitry for memory cells Control circuitry for memory cells is described. In an embodiment, a breakdown detection circuit is described which is arranged to detect abnormally high currents indicative of a defective cell during programming of a memory cell through monitoring the impedance level at a terminal in the breakdown detection circuit. The breakdown detection circuit is connected between the device being programmed and ground and comprises three transistors, at least one of which is capable of withstanding the programming voltage in case of breakdown. Other embodiments describe a flag bit cell design, a memory array and methods of reading and writing from/to that array, and circuitry for biasing a memory word-line for both read and write operations. The embodiments may be used separately or in a combination.
US09058886B2	Power supply circuit and protection circuit A power supply circuit includes a first circuit connected to a first line, to which a power supply voltage is applied, and a second line, and a power supply clamp circuit connected to the first and second lines. The power supply clamp circuit includes a current path circuit which connects the first and the second lines to each other, and a control circuit which outputs a control signal to the current path circuit. The current path circuit includes a transistor and a diode group. The power supply clamp circuit is driven during a period in which a first voltage is applied to the first line and controls a potential of the first line so as to become a potential lower than the first voltage.
US09058885B2	Magnetoresistive device and a writing method for a magnetoresistive device A magnetoresistive device including a fixed magnetic layer structure, a first free magnetic layer structure, and a second free magnetic layer structure, wherein the fixed magnetic layer structure is arranged in between the first free magnetic layer structure and the second free magnetic layer structure, wherein the magnetization orientation of the first free magnetic layer structure is variable in response to a first electrical signal of a first polarity and the magnetization orientation of the second free magnetic layer structure is at least substantially non-variable in response to the first electrical signal, and wherein the magnetization orientation of the second free magnetic layer structure is variable in response to a second electrical signal of a second polarity and the magnetization orientation of the first free magnetic layer structure is at least substantially non-variable in response to the second electrical signal, wherein the second polarity is opposite to the first polarity.
US09058883B2	Control apparatus for controlling data reading and writing to flash memory To record data in a flash memory, upon detecting that a current destination memory block is full, a control apparatus records data in a destination memory block one block by one block, with “in-advance” data erasure of the next memory block and by determining if data erasure of the next memory block is successful. When data erasure of the next memory block fails, such memory block is designated as broken, and such memory block is excluded from a group of blocks to be used as recording destination. After determining the data erasure result of a yet-next memory block is successful, the required data is copied to the yet-next memory block. Therefore, even when one of the blocks is broken, a sequential data recording in the flash memory is performed without increasing the number of data copy operations between blocks.
US09058880B2	Unequal bit reliability information storage method for communication and storage systems An unequal bit-reliability information storage method for communication and storage systems at least includes one storage unit having a first memory and a second memory; the most significant information bits are stored in the first memory; and least significant information bits are stored in the second memory. Based on the significance of each bit of the information with the use of the first or second memories of different reliability for storage, the complexity of the storage unit, the production cost and the power consumption can be reduced while maintaining the performance.
US09058879B2	Methods and apparatus for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well as the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided.
US09058878B2	Read methods of semiconductor memory device A read method of a semiconductor memory device includes performing a read operation on target cells by using a first read voltage, terminating the read operation on the target cells if, as a result of the read operation on the target cells, error correction is feasible, performing a read operation on first cells next to the target cells along a first direction if, as a result of the read operation on the target cells, error correction is unfeasible, performing the read operation again on the target cells by selecting one of a plurality of read voltages in response to a result of the read operation on the first cells and by using the selected read voltage for reading data of the target cells, and terminating the read operation on the target cells if error correction is feasible.
US09058876B2	Methods and circuits for bulk erase of resistive memory A resistive random access memory integrated circuit for use as a mass storage media and adapted for bulk erase by substantially simultaneously switching all memory cells to one of at least two possible resistive states. Bulk switching is accomplished by biasing all bottom electrodes within an erase area to a voltage lower than that of the top electrodes, wherein the erase area can comprise the entire memory array of the integrated circuit or else a partial array. Alternatively the erase area may be a single row and, upon receiving the erase command, the row address is advanced automatically and the erase step is repeated until the entire array has been erased.
US09058875B2	Resistive memory sensing The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal.
US09058874B2	Sensing circuits and phase change memory devices including the same A sensing circuit includes a plurality of cell read current generators, a reference current generator and a plurality of sense amplifiers. Each of the cell read current generators generates a cell read current from each of a plurality of memory cells. The reference current generator sums the cell read currents to generate a sum current. Each of the sense amplifiers determines data state stored in each of the memory cells based on each of the cell read currents and an average current. The average current is obtained based on the sum current.
US09058873B2	Memory element having ion source layers with different contents of a chalcogen element A memory element includes: a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer provided on the first electrode side, and an ion source layer containing one or more of metallic elements, and the ion source layer being provided on the second electrode side. The ion source layer includes a first ion source layer and a second ion source layer, the first ion source layer containing one or more of chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se) and being provided on the resistance change layer side, and the second ion source layer containing the chalcogen element with a content different from a content in the first ion source layer and being provided on the second electrode side.
US09058871B2	Resistive random access memory(ReRAM) device The resistive random access memory (ReRAM) device includes a first amplifier configured to amplify a sensing current corresponding to data sensed in a memory cell, and a second amplifier configured to store the sensing current amplified by the first amplifier, and amplify electric charges when storing the amplified sensing current.
US09058867B2	Semiconductor device and driving method thereof A data saving period control circuit; a power gating control circuit; and a data processing circuit including a general-purpose register, an error correction code storage register, and an error correction code circuit are included. The general-purpose register and the error correction code storage register each include a volatile memory unit and a nonvolatile memory unit. The data saving period control circuit is a circuit for changing a length of a data saving period in which data output from the power gating control circuit is saved from the volatile memory unit to the nonvolatile memory unit included in the general-purpose register, depending on whether an error in an error correction code stored in the error correction code storage register is detected by the error correction code circuit.
US09058866B2	SRAM local evaluation logic for column selection An SRAM includes a first SRAM column having first SRAM cells and a first local evaluation logic coupled to a global bit line and a second SRAM column having second SRAM cells and a second local evaluation logic coupled to the same global bit line. The first SRAM column is selected with a first column select line and the second SRAM column is selected with a second column select line.
US09058862B2	Voltage regulator The present invention relates to a voltage regulator and to a method of operating a voltage regulator that is operable in a reset mode and in a sampling mode. The voltage regulator comprises a capacitive voltage divider having a first capacitor and a second capacitor in series with the first capacitor, wherein the capacitive voltage divider is connectable to an output of a voltage supply to activate the sampling mode, a comparator having an output connected to an input of the voltage supply, the comparator further having a first input connected to a sampling node arranged between the first capacitor and the second capacitor and the comparator having a second input connected to a reference voltage, wherein the sampling node is connectable to the reference voltage for activating the reset mode.
US09058861B2	Power management SRAM write bit line drive circuit A static random access memory (SRAM) having two or more SRAM memory cells connected with a write bit line (WBL) and a write bit line complement (WBLC) is disclosed. The SRAM may include a write driver logic coupled to the WBL and the WBLC. The write driver logic is adapted to drive a selected bit line of the WBL and the WBLC to a voltage uplevel below a first supply voltage and shut off the drive to the selected bit line when the selected bit line reaches the uplevel. The write driver logic is further adapted to drive an unselected bit line of the WBL and the WBLC to a downlevel, in conjunction with the driving of the selected bit line to the uplevel, where the downlevel is a second supply voltage lower than the first supply voltage.
US09058856B2	Semiconductor memory device A memory cell array comprises first wiring lines, second wiring lines, and memory cells disposed at intersections thereof. A control circuit comprises a first power-supply line supplying a first voltage to selected ones of the first or second wiring lines, and first selection circuits connected between the first or second wiring lines and the first power-supply line, each first selection circuit comprising first and second transistors connected in series. The first selection circuits arranged along a first direction are connected to a first selection line. The first selection circuits arranged along a second direction perpendicular to the first direction are commonly connected to a second selection line. The first and second transistors each comprise a columnar semiconductor portion extending in a direction perpendicular to a semiconductor substrate, a gate-insulating film in contact with a side surface of the columnar semiconductor, and a gate electrode in contact with the gate-insulating film.
US09058855B2	Pad selection in memory devices configured for stacked arrangements Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.
US09058852B2	Memory state sensing based on cell capacitance A memory cell and method for operating a memory cell including a bidirectional access device and memory element electrically coupled in series. The bidirectional access device includes a tunneling capacitance. The memory element programmable to a first and second state by application of a first and second write voltage opposite in polarity to one another. The memory element has a lower capacitance in the first state than the second state. A read unit senses a transient read current due to a voltage drop upon application of a read voltage. Determining if the memory element is the first or second state is based on whether the read current is greater or less than a sense threshold. The sense threshold is based on a capacitance ratio between the first and second state.
US09058851B1	Information-storage device including an oxygen absorbing device An information-storage device comprises an information-storage medium, a transducer operable to write and to read information on the information-storage medium, and a sealed enclosure enclosing the same in an interior space containing an atmosphere comprising a gas mixture including a substantially inert gas and oxygen gas having a molar concentration between about 0% and about 10%. The sealed enclosure includes a base, a cover, and a seal that joins cover to base. The information-storage device may include at least one oxygen permeable component integrated with the sealed enclosure. The information-storage device further comprises an oxygen absorbing device operable to remove a substantial portion of oxygen gas from the atmosphere within. The oxygen absorbing device includes an oxygen absorbent material comprising oxygen-deficient cerium oxide, CeO2-x, where 0
US09058847B2	Communication apparatus, control method, and computer-readable recording medium A communication apparatus includes a communication unit that communicates with an external apparatus via communication lines conforming to HDMI standard, a first detection unit that determines whether a first signal is detected indicating that the communication unit and the external apparatus are connected, a second detection unit that determines whether a second signal is detected indicating that the external apparatus is in a state where the external apparatus displays video data transmitted from the communication unit, and a control unit that controls the communication unit to transmit the video data to the external apparatus if the first signal and the second signal are detected.
US09058846B2	Video map synchronizing diagnostic information A method comprising comparing a frame rate of a source video program to a frame rate of a target video program to generate a conversion factor between the two sources; retrieving a target frame and retrieving, responsive to a location of the target video frame within the target video program, and responsive to the conversion factor, a source video frame from within the source video program; determining, by means of an image comparison, equivalence between the target frame and the source frame; generating, responsive to the determining of equivalence, synchronization diagnostic information; and synchronizing, responsive to an analysis of the synchronization diagnostic information, the target frame and the source frame, the synchronizing enabling a set of non-sequential segments of the target video program to be equivalent to a set of non-sequential segments of the source video program.
US09058835B2	Methods and systems for optimized staggered disk drive spinup An array may comprise a plurality of disk drives and a controller coupled to the plurality of drives. The controller may be configured to initiate spin-up of one or more first disk drives of the array; determine when each of the first disk drive(s) of the array for which spin-up was initiated reaches a predetermined spin rate that is less than a target spin rate at which the disk drive is ready to process data access commands; and initiate spin-up of one or more second disk drives of the array as the first disk drive(s) is determined to have reached the predetermined spin rate.
US09058833B1	Spindle motor, and disk drive apparatus including the spindle motor A spindle motor includes a shaft extending in an axial direction, and a base portion configured to define a portion of a housing, and including a through hole in which the shaft is inserted. The shaft includes a non-through hole portion, a first connection channel, and a second connection channel extending from the non-through hole portion in a radial direction. An upper portion of the hole portion includes a screw hole portion including a screw thread. A minimum diameter of the screw thread is greater than an inside diameter of the hole portion. A sealing member is located between the screw hole portion and the first connection channel.
US09058831B2	Perpendicular magnetic recording medium with grain boundary controlling layers In one embodiment, a perpendicular magnetic recording medium includes an oxide recording layer including an oxide and a non-oxide recording layer which does not contain an oxide positioned above the oxide recording layer. The oxide recording layer includes a region R1 where a grain boundary width in a direction parallel to a plane of formation of R1 increases therealong from a lowermost portion of the oxide recording layer toward a medium surface, a region R3 positioned above R1 wherein a grain boundary width increases therealong toward the medium surface, a region R2 where a grain boundary width of R2 decreases therealong from R1 to R3, with R2 being positioned between R1 and R3, and a region R4 where a grain boundary width of R4 decreases therealong from R3 toward the medium surface, with R4 being positioned above R3 and near an uppermost portion of the oxide recording layer.
US09058828B1	Servo pattern of a tape storage medium A tape storage medium comprises at least one servo band (SB) along a longitudinal extension (x) of the tape storage medium (TP) for supporting to determine positional information. The servo band (SB) comprises a set of servo tracks (STx) extending along the longitudinal extension (x) of the tape storage medium (TP) and arranged next to each other. Each servo track (STx) of the set contains a servo pattern with magnetic transitions at a defined frequency (fx), wherein the frequencies (fx) of magnetic transitions of servo patterns of adjacent servo tracks (STx) are different from each other. The set of servo tracks (STx) contains at least three servo tracks (STx) with magnetic transitions of different frequencies (fx).
US09058820B1	Identifying speech portions of a sound model using various statistics thereof Speech portions of a sound model may be identified using various statistics associated with the sound model for voice enhancement of noisy audio signals. A spectral motion transform may be performed on an input signal to obtain a linear fit in time of a sound model of the input signal. Statistics may be extracted from the linear fit of the sound model of the input signal. Speech portions of the linear fit of the sound model of the input signal may be identified by detecting a presence of harmonics as a function of time in the linear fit of the sound model of the input signal based on individual ones of the extracted statistics. An output signal may be provided that conveys audio comprising a reconstructed speech component of the input signal with a noise component of the input signal being suppressed.
US09058816B2	Emotional and/or psychiatric state detection Mental state of a person is classified in an automated manner by analysing natural speech of the person. A glottal waveform is extracted from a natural speech signal. Pre-determined parameters defining at least one diagnostic class of a class model are retrieved, the parameters determined from selected training glottal waveform features. The selected glottal waveform features are extracted from the signal. Current mental state of the person is classified by comparing extracted glottal waveform features with the parameters and class model. Feature extraction from a glottal waveform or other natural speech signal may involve determining spectral amplitudes of the signal, setting spectral amplitudes below a pre-defined threshold to zero and, for each of a plurality of sub bands, determining an area under the thresholded spectral amplitudes, and deriving signal feature parameters from the determined areas in accordance with a diagnostic class model.
US09058815B2	System. apparatus, and method for interfacing workflow instructions A system, method, and apparatus for interfacing an operating management system with an operator is provided. The system provides a processor configured to execute workflow instructions; and an operator device in communication with the processor. The processor is configured to execute commands which convert the workflow instructions from a text command into an audible command and transmit the audible command to the operator device and the operator device is configured to receive the audible command, and is further configured to transmit an operator response to the processor.
US09058814B2	Mobile devices, methods, and computer program products for enhancing social interactions with relevant social networking information Devices, methods, and computer program products are for facilitating enhanced social interactions using a mobile device. A method for facilitating an enhanced social interaction using a mobile device includes receiving an audio input at the mobile device, determining a salient portion of the audio input, receiving relevant information associated with the salient portion, and presenting the relevant information via the mobile device.
US09058809B2	Method and system for automated speech recognition that rearranges an information data base to disrupt formation of recognition artifacts A system and a method perform information recognition. The method arranges data base information in a data base information structure. The method matches input information to the data base information using at least one matching algorithm and using a matching information structure. In accordance with the system and the method, the matching information structure differs from the data base information structure.
US09058804B2	Speech signal transmission and reception apparatuses and speech signal transmission and reception methods A speech signal transmission apparatus includes an extractor to extract speech signals from speech source signals collected by a plurality of microphones, a power calculator to calculate powers of speech signals of multiple channels and set any one of the speech signals of the multiple channels as a reference speech signal, a synchronization adjustor to adjust synchronization of the other speech signals based on the reference speech signal, a signal generator to generate extraction signals by offsetting the reference speech signal from the other synchronization-adjusted speech signals, an encryptor to compress and encrypt the reference speech signal and the extraction signals, and a transmitter to transmit the compressed and encrypted reference speech signal and extraction signals.
US09058799B2	Sound diffuser inspired by cymatics phenomenon Sound diffusers are important components in enhancing the quality of room acoustics. The present disclosure relates to a sound diffuser obtained by using properties of the cymatics phenomena. Cymatics is the study of sound and vibration made visible, typically on the surface of a plate, diaphragm or membrane. Two examples of diffusers are designed by the cymatic shapes and modeled by using a quadratic quadratic residue sequence. It is found that this type of acoustic diffusers can be used to maintain the acoustic energy in a room and at the same time can treat unwanted echoes and reflections by scattering sound waves in many directions. The design allows for creating different interior space designs by changing the arrangement of the diffuser panels, and this leads to different applications for the diffusers.
US09058798B2	Tunable polymer-based sonic structures Tunable polymer-based sonic structures (“TuPSS”) are made up of sonic structures and polymers. The TuPSS has three general requirements: a) The sonic structure is composed of one or materials engineered to behave as a lens, filter, cloak, or dampener; b) Stimulus sensitive polymer is incorporated into the sonic structure; and c) The actuation of the polymer tunes the acoustic behavior of the structure in a predictable manner. The tunable polymer-based sonic structures utilize stimuli-driven physical properties of the polymers in these acoustic structures to produce a stimulus driven, or tunable, sonic structure or device. The sonic structures actively modulate mechanical vibrations that propagate through the structures, but are passive in that they do not produce mechanical vibrations. The stimuli for the structures include electric, magnetic, electromagnetic, chemical, thermal, and shaking/orientation.
US09058793B1	Key mechanism for a saxophone A key mechanism for a saxophone includes a lever, a sound-hole cover, an adjustment member, and a touch piece. The lever includes a connecting portion in which being formed a rotation-stop hole, and a slot in communication with and perpendicular to the rotation-stop hole. The adjustment member is rotatably and partially disposed in the slot and has a threaded hole in communication with the rotation-stop hole. The touch piece includes a press portion, a rotation-stop portion and a screw. The rotation-stop portion is engaged in the rotation-shaped hole, and the screw is screwed in the threaded hole of the adjustment member, so that rotating the adjustment member causes the screw to linearly move with respect to the adjustment member. Therefore, the height position of touch piece of the saxophone can be adjusted without using any hand tools.
US09058792B1	Coalescing to avoid read-modify-write during compressed data operations Sequential write operations to a unit of compressed memory, known as a compression tile, are examined to see if the same compression tile is being written. If the same compression tile is being written, the sequential write operations are coalesced into a single write operation and the entire compression tile is overwritten with the new data. Coalescing multiple write operations into a single write operation improves performance, because it avoids the read-modify-write operations that would otherwise be needed.
US09058789B2	Synchronous processing system and semiconductor integrated circuit A synchronous processing system having semiconductor integrated circuits. One of the semiconductor integrated circuits as a master chip includes a first synchronization controller and a first counter controller that allows a counter in the master chip to perform counting synchronously with a clock pulse in response to a synchronization control signal from the first synchronization controller. Another semiconductor integrated circuit as a slave chip includes a second synchronization controller that receives the synchronization control signal from the master chip, and a second counter controller that allows a counter in the stave chip to perform counting synchronously with the clock pulse in response to the synchronization control signal received. Each of the first and second counter controllers allows the counter to stop counting if the synchronization control signal is not supplied at the time point that a count value of the counter has reached a predetermined value.
US09058785B2	Image displaying method for display device An exemplary image displaying method for a display device includes steps of: providing display data to pixels of the display device for displaying images; taking a special amount of frame of images as an image group, making polarities of a same pixel being of adjacent two frame of images in the image group and using a same polarity inversion in the adjacent two frame of images be different from each other, and making polarities of a same pixel being of the last frame of image in a former one of adjacent two image groups and of the first frame of image in a latter one of the adjacent two image groups and using the same polarity inversion in the last and first frame of images be the same with each other.
US09058784B2	Liquid crystal display device A liquid crystal display device for carrying out a 3D display by a frame sequential method as well as a 2D display includes: a digital γ correction section for changing an input gray level to a gamma characteristic corresponding to either the 2D display or the 3D display in accordance with a preset analog gamma value; an overdrive circuit for finding, in accordance with a parameter set according to the gamma characteristic thus corrected by the digital γ correction section, an overdrive value corresponding to the input gray level; and an analog γ correction section for finding a voltage value to be applied to liquid crystal by correcting the overdrive value found by the overdrive circuit. In the digital γ correction section, an analog gamma value for the 3D display is set to be larger than an analog gamma value for the 2D display.
US09058781B2	Backlight unit with changing oscillation frequency in stereoscopic mode and liquid crystal display using the same A liquid crystal display for displaying either a flat image or a stereoscopic image, comprising: a panel; and a backlight unit for providing a light source to the panel. The backlight unit comprising: a switch circuit and an oscillator. One end of the switch circuit is electrically connected with a first resistor, and another end of the switch circuit is electrically connected with a second resistor. When the switch circuit is turned on, the first resistor is connected with the second resistor in parallel. The oscillator is electrically connected with the first resistor and the switch circuit. When the switch circuit is turned off, the oscillator outputs a first frequency, and when the switch circuit is turned on, the oscillator outputs a second frequency.
US09058778B2	Maintaining DC balance in electronic paper displays using contrast correction Systems and methods for maintaining DC balance in bi-stable displays using contrast correction are disclosed. The system includes a DC balance module and storage for DC corrective waveforms. The DC balance module generates transitional driving schemes which drive pixels to new color values while simultaneously shifting each pixel's relative impulse potential values to be in line with those of the new speed drive scheme. The transitional driving schemes ensure DC balance by performing contrast and color-depth correction. In particular, the transitional driving schemes lower the contrast and reduce the color depth of pixels when increasing the speed of page flipping and raise the contrast and color depth when reducing the speed of page flipping. The present embodiment of the invention also includes a method for variable-speed page flipping with contrast correction and a method for creating a transitional driving scheme.
US09058774B2	Pixel and organic light emitting display using the same A pixel includes a first transistor coupled between a first power source and a first node, the first transistor including a gate electrode coupled to a second node, an organic light emitting diode (OLED) coupled between the first node and a second power source, a second transistor for supplying a data signal to the second node in response to a scan signal, a third transistor having a source electrode and a drain electrode electrically coupled to each other, the third transistor being coupled to the first power source and the second node, and a fourth transistor having a source electrode and a drain electrode electrically coupled to each other, the fourth transistor being coupled between the second node and the first node.
US09058769B2	Method and system for compensating ageing effects in light emitting diode display devices The present invention relates to a method for compensating ageing effects of pixel outputs displaying an image on a display device. The method involves displaying a first image on an active display area (6) on the display device (1) having a first plurality of pixels; displaying a second image on a sub-area (7) of the display device (1) and having a second plurality of pixels, the active display area (6) being larger than the sub-area (7) and the second image being smaller than the first image and having fewer pixels than the active display area (6); driving the pixels of the sub-area (7) with pixel values that are representative or indicative for the pixels in the activity display area (6); making optical measurements on light emitted from the sub-area (7) and generating optical measurement signals (11) therefrom, and; controlling the display of the image on the active display area (6) in accordance with the optical measurement signals (11) of the sub-area (7).
US09058768B2	Display device and arranging method for image data thereof A display device including a display panel having first pixels emitting light in a first field and second pixels emitting light in a second field is disclosed. According to one aspect, the display device includes a controller configured to extract first field data transmitted to the first pixels and second field data transmitted to the second pixels from input data, divide the first field data, insert black data between two neighboring first field data to generate first output data, divide the second field data, and insert black data between two neighboring second field data to generate second output data. The display device also includes a data driver configured to transmit a first data signal based on the first output data to the display panel in the first field and transmitting a second data signal based on the second output data to the display panel in the second field.
US09058767B2	Electrooptical device having pixel subfields controllable to produce gray levels An electrooptical device according to the invention includes a plurality of pixels and a driving section that drives the pixel in such a way that the pixel is brought into a bright state or a dark state in each of subfields, and, when a specific gray level is designated, the details of driving of at least one pixel and a pixel adjacent to the one pixel, the details of driving in one frame, are different from each other.
US09058756B2	Modular art-post assembly and method of using the same An outdoor art-post assembly includes an elongate support pole, an art post, and at least one mounting mechanism. The elongate support pole has a lower portion and an auger disposed at the lower portion. The auger allows for vertical installation of the support pole in soil in response to manual rotation of the support pole. The art post has an inner surface defining a bore. The bore is capable of receiving at least a portion of the elongate support pole. The art post also has an outer surface including decorative indicia thereon. The mounting mechanism is located on the support pole and has protruding portions extending away from the support pole. The protruding portions are configured to contact the inner surface of the art post and affix the art post relative to the support pole. Methods of assembling the same are also disclosed.
US09058753B2	Paper, labels made therefrom and methods of making paper and labels Paper is disclosed for use in making repositionable or removable adhesive labels. The adhesive can be applied in patches or discrete areas to the paper or to a layer of material that cleans rollers in the manufacturing line and/or in printers. The adhesive can be applied in single or multiple layers. The paper is light weight paper and preferably thermal paper for use in POS printers.
US09058748B2	Classifying training method and apparatus using training samples selected at random and categories According to an embodiment, a learning apparatus includes a learning sample storage unit configured to store therein a plurality of learning samples that are classified into a plurality of categories; a selecting unit configured to perform, plural times, a selection process of selecting a plurality of groups each including one or more learning samples from the learning sample storage unit; and a learning unit configured to learn a classification metric for classifying the plurality of groups selected in each selection process and generate an evaluation metric including the learned classification metrics.
US09058747B2	Locator system A locator system employs personal communicators which are carried on or worn in a holster by drivers. The communicators are employed to automatically transmit data for determining the identity of the driver, the identity of the vehicle and date and time stamps when the vehicle enters and exits various detection zones. In one embodiment the detections zones are defined by Bluetooth signals.
US09058742B2	Methods for illustrating aircraft situational information Methods of illustrating aircraft situational information on a flight display in a cockpit of an aircraft, include determining a location of the aircraft, displaying on the flight display a forward looking graphical representation of the runway from the determined location of the aircraft, displaying situational awareness information on the graphical representation, and updating the location determination, graphical representation and the situational awareness information as the aircraft moves.
US09058739B2	Electromechanical switch for controlling toxic gas An electromechanical switch comprising a plunger, a first switch in contact with the plunger in a first position of the plunger, in which a connection of the switch is open, a button in sliding contact with the plunger, and a solenoid in contact with the plunger in a second position of the plunger, in which a connection of the first switch is closed.
US09058738B1	Doorbell communication systems and methods Doorbells can be configured to wirelessly communicate with a remotely located computing device. Some embodiments of the doorbell can be configured to enter a network connection mode. The network connection mode can include detecting a first wireless network having a name and a password. The network connection mode can also include using the remotely located computing device to scan a barcode such as a Quick Response Code.
US09058735B2	Method and system for detecting conditions of drivers, and electronic apparatus thereof A system for detecting a condition of a driver is provided, wherein the system includes a first electrical device, a second electrical device, a regulation unit and an alert unit. The first electrical device detects an initial vehicle angle of a vehicle, the second electrical device detects an initial head angle of the driver and the regulation unit calculates a regulation angle based on the initial head angle and the initial vehicle angle. Additionally, the first electrical device detects a current vehicle angle of the vehicle, the second electrical device detects a current head angle of the driver and the regulation unit calculates a regulated head angle based on the current head angle and the regulation angle. Furthermore, the alert unit calculates a difference value between the regulated head angle and the current vehicle angle and generates a warning message if the difference value is larger than a threshold.
US09058730B2	Intruder deterrent system This invention relates to portable area denial systems and to related methods. We describe an intruder deterrent system, the system comprising a plurality of nodes, each said node having a strobe light, and at least one of said nodes having an intruder-detecting sensor, wherein the system is configured to flash at least one of said strobe lights on detection of an intruder by said sensor to deter said intruder.
US09058722B2	Random payout system and method for gaming devices A random payout system provides self-funding winning symbol combinations that allow various wagering games to be quickly and easily defined. The winning symbol combinations may individually be associated with a funding pool. Symbols from a winning symbol combination may be disabled or not presented when an associated funding pool is negative. The symbols may be activated or presented when the associated funding pool is non-negative. In this manner, the winning symbol combinations are self-funding. Funds for a funding pool may come from various sources including advertising revenue and placed wagers.
US09058720B2	Login application for a wagering game portal Systems described herein include wagering game systems having a portal container with one or more portal applications running within the portal container. The portal container includes a login application that receives player credentials and logs into various servers using the login credentials. The login application serves as a proxy for the portal applications that communicate with the servers.
US09058719B2	Gaming terminal chair electrical interface Gaming terminals, gaming systems, and electrical and mechanical connector assemblies for coupling a gaming terminal to a chair positioned in front of the gaming terminal are presented herein. A gaming system is disclosed. The gaming system includes a gaming terminal for playing a wagering game and a chair positioned in front of the gaming terminal. The chair includes electronic components operated by a digital data signal and powered by a power supply signal. The gaming terminal includes an electrical connector assembly for coupling to a complementary electrical connector assembly on the chair. The electrical connector assembly also includes a switching device for automatically electrically coupling the electronic components with a power supply signal from a power supply once the respective electrical connector assemblies are securely coupled.
US09058718B2	Gaming machine and gaming method of performing rendering effect A gaming machine according to an embodiment of the present invention includes: a first display unit that includes a plurality of reels including a plurality of symbols thereon; and a controller configured to: determine whether a rendering effect activation is selected; execute a game by spinning and stopping the plurality of reels of the display device; and perform a rendering effect on the spinning and stopping of the plurality of reels when it is determined that the rendering effect activation is selected.
US09058715B2	Gaming device having a second separate bonusing event A gaming system wherein a second game is triggered once a specific event occurs in a first game.
US09058712B2	Beverage vending machine cup dispenser assembly A dispenser assembly for dispensing cups in a beverage vending machine, the assembly having a dispensing device for releasing one cup at a time from a stack of cups; and a belt conveyor, which defines a store for two parallel, staggered lines of stacks, communicates with the dispensing device via an outlet, and is connected to a wall, for pushing the stacks, by a friction coupling, so as to draw the wall, in use, towards the outlet.
US09058710B2	Systems, methods, and computer-readable media for sheet material processing and verification Methods and systems disclosed herein for processing a sheet of sheet material include a plurality of processes. The methods and systems include a process of receiving the sheet in a sheet-accepting device. The methods and systems include detecting, by a first sensor mechanism of the sheet-accepting device, first information of the sheet. The first information of the sheet includes a value of the sheet and a serial number of the sheet. The methods and systems include disposing the sheet in a removable container coupled to the sheet-accepting device. The methods and systems include storing the first information of the sheet in a memory coupled to the removable container.
US09058708B2	Ballot box cart A utility cart for storage, transport and setup of voting devices into a completely-operational configuration, ready for use, while still on the cart. The utility cart employs a deployable privacy curtain that erects a 360 degree private voting environment around the equipment using the voting equipment. When loaded with a tabulator/ballot box, the cart may be wheeled from storage into a usable position in the precinct, onboard equipment plugged in, the utility cart deployed and privacy curtain erected, and the precinct is then ready for voting traffic. All the loaded equipment is fully protected during transport and restrained against lateral motion, and yet when deployed full access is given to the control panels, doors, etc. Moreover, the particular design maximizes strength and usability, and yet keeps weight to a minimum with a framework that is as light weight as possible.
US09058705B2	Communication system with personal information management and remote vehicle monitoring and control features A vehicle communication system includes a control unit in a vehicle, a vehicle data bus operable to transmit vehicle data to the control unit, and a mobile communication device having data network access. The mobile device has a self-contained mode in which the mobile communication device processes and displays the network data received via the data network and in which the control unit transmits the vehicle data to the mobile communication device. The mobile communication device also has an immersive mode in which the control unit processes the network data received via the data network and in which the control unit converts the vehicle data to audible speech and plays the audible speech in the vehicle.
US09058702B2	Method for securely delivering indoor positioning data and applications Methods and devices are described for providing localized secure navigation in conjunction with near field communication access control systems. In one potential embodiment, a mobile device such as a cell phone may communicate with a door access control point using near field communication to receive location access system information. The mobile device may then authorize download and execution of a local secure navigation module from a location access system using the location access system information for use in receiving location assistance data, based on an authentication level associated with the mobile device. Such location assistance data may be used by the local secure navigation module to provide location assistance when the mobile device is in a secure location. The location of the mobile device may then be tracked using at least the location assistance data and the communication with the door access control point.
US09058695B2	Method of graphically representing a tree structure In a data visualization system, a method of creating a visual representation of data points from metric data, wherein the method includes the steps of: a data retrieval module retrieving the metric data from a data storage module in communication with the data visualization system, a determination module determining the data points based on the retrieved metric data, and a display module arranging the data points for displaying on a display device according to a predetermined visual representation, arranging the data points into a plurality of meta groups in a hierarchical manner, and arranging the meta groups into a plurality of layers, where each layer represents the data points at different levels of granularity, and a statistical distance determination module determining a statistical distance between items in the meta groups, and the display module arranging the items within the meta groups based on the determined statistical distance.
US09058688B2	Tomographic reconstruction of an object in motion A method for processing a sequence of a plurality of 2D projection images of an object of interest, acquired with a medical imaging system comprising a source of X-rays adapted to move around the object is provided. The method comprises obtaining 2D projection images of the object of interest according to a plurality of angulations at a first time when the object is without injection of a contrast product; obtaining 2D projection images of the object of interest according to a plurality of angulations at a second time when the object is opacified by injection of a contrast product iteratively treating the projection images by minimizing relative to a sequence of 3D images, wherein the minimizing solution is a set of estimated 3D images.
US09058686B2	Information display system, information display apparatus, information provision apparatus and non-transitory storage medium The utility of a service using AR is improved. The information display apparatus which applies an information display according to augmented reality (AR) acquires a reference image for matching with a subject in a captured image and scale information which shows a scale of the subject in the reference image from an information provision apparatus. Then, an inputter-outputter of the information display apparatus displays the captured image as well as a distribution of the reference images by a scale of the subject. On this distribution display, a guide display according to the scale of the subject in the captured image is performed. This guide display moves on the distribution display corresponding to a change of an angle of view. Accordingly, it is easily set the angle of view by which the matching using the acquired reference image can be performed appropriately, and the convenience improves.
US09058683B2	Automatic image rectification for visual search Disclosed is a computing device that can perform automatic image rectification for a visual search. A method implemented at a computing device includes receiving one or more images from an image capture device, storing the one or more images with the computing device, building a three dimensional (3D) geometric model for one or more potential objects of interest within an environment based on at least one image of the one or more images, and automatically creating at least one rectified image having at least one potential object of interest for a visual search.
US09058680B2	Multi-threaded multi-format blending device for computer graphics operations The disclosed invention provides a solution for the problem of blending colors in a graphics processing unit. The plurality of blending equations used in various graphics layers is performed with a programmable streaming processor. Multiple simultaneous threads are used to eliminate pipeline latency and memory stalls. Overlays of predefined blending modes are used to minimize the time instruction memory is updated.The processing unit includes: (a) an instruction memory (b) hardware context registers for each executing stream (c) pipelined arithmetic units of predefined precision, including support for floating point (d) units that convert multi-format data to and from floating point precision (e) Look-up tables for quick color space transformations.
US09058679B2	Visualization of anatomical data An apparatus and a method for examination and visualization of an object of interest. The apparatus comprises a display, an input device, and a calculation unit, wherein the calculation unit is adapted for performing the following steps: acquiring a first data set; acquiring a second data set; fusing the first and second data sets; determining image parameters entered by means of the input device, related to at least one of an image plane, an angle of view, a contrast and a transparency; rendering an image on the basis of the data sets and the determined parameters, resulting in a combined image with selected areas of transparency and selected areas of visible contrast information, wherein the image is visualized on the display.
US09058678B1	System and method for reducing the complexity of performing broad-phase collision detection on GPUs One embodiment of the present invention sets forth a technique for efficiently performing broad phase collision detection using parallel spatial subdivision. The technique involves organizing candidate objects according to a hashed representation of each object centroid, constructing a cell identification (ID) array, sorting the cell ID array, creating a collision cell list, and traversing the collision cell list. The result is a candidate list of object groups that may collide, based on an initial assessment of spatial proximity. Whether a given pair of objects actually collides is determined by a precise narrow phase collision analysis.
US09058677B1	System and method for reducing the complexity of performing broad-phase collision detection on GPUS One embodiment of the present invention sets forth a technique for efficiently performing broad phase collision detection using parallel spatial subdivision. The technique involves organizing candidate objects according to a hashed representation of each object centroid, constructing a cell identification (ID) array, sorting the cell ID array, creating a collision cell list, and traversing the collision cell list. The result is a candidate list of object groups that may collide, based on an initial assessment of spatial proximity. Whether a given pair of objects actually collides is determined by a precise narrow phase collision analysis.
US09058657B2	System and method for filtering data captured by a 3D camera In an exemplary embodiment, a system includes a three-dimensional camera and a processor. The processor is operable to access a first portion of visual data captured by the three-dimensional camera wherein the visual data comprises an image of a dairy livestock and access a second portion of the visual data, wherein the first portion and the second portion are aligned in a first dimension. The processor is further operable to determine a first coordinate, wherein the first coordinate comprises a location of the first portion in a second dimension, the second dimension orthogonal to the first dimension and determine a second coordinate, wherein the second coordinate comprises a location of the second portion in the second dimension. The processor is further operable to determine a first distance exceeds a distance threshold, wherein the first distance is the distance between the first coordinate and the second coordinate in the second dimension.
US09058651B2	System and methods for functional analysis of soft organ segments in SPECT-CT images An analysis system and method for measuring soft organ functions in general and the liver specifically utilizing both measurement and imaging devices such as a SPECT system and a CT system. The two images utilize a common coordinate system and segment the liver image for enhanced functional analysis.
US09058650B2	Methods, apparatuses, and computer program products for identifying a region of interest within a mammogram image Methods, apparatuses, and computer program products are provided for identifying a region of interest within a mammogram image. A method may include applying a clustering algorithm to a histogram of the mammogram image to identify a predefined number of threshold values. The method may further include determining a predefined number of seed values based at least in part on the identified threshold values. The method may additionally include generating a kernel image for each of the seed values. The method may also include using the generated kernel images to identify a region of interest including a breast within the mammogram image. Corresponding apparatuses and computer program products are also provided.
US09058649B2	Ultrasound imaging system and method with peak intensity detection The present invention relates to an ultrasound imaging system (10) and method that allow for a quantitative analysis of the acquired images during acquisition and for an optimized workflow for image acquisition and analysis. The proposed ultrasound imaging system (10) comprises a transducer (12) configured to acquire ultrasound images (14) of an object based on one or more adjustable acquisition parameters, an analyzer (22) configured to analyze an ultrasound image (14) in real-time for a mean intensity value (24), and a processor (28) configured to determine in real-time when the mean intensity value (24) has reached a peak and to change the setting of at least one of the one or more adjustable acquisition parameters after a peak has been determined.
US09058646B2	Simultaneous acquisition of biometric data and nucleic acid Systems, methods, and kits are disclosed for collection, labeling and analyzing biological samples containing nucleic acid in conjunction with collecting at least one ridge and valley signature of an individual. Such devices and methods are used in forensic, human identification, access control and screening technologies to rapidly process an individual's identity or determine the identity of an individual.
US09058643B2	Process and device for detection of drops in a digital image and computer program for executing this method Devices and methods for detecting of drops on a transparent wall through which digital image is acquired by means of an image acquisition system. The method includes establishing a gradient image from the digital image by assigning to each pixel the value of the gradient for the pixel; filtering the gradient image by assigning to each pixel a value obtained by rank filtering; and establishing a mask representing the position of the detected drops in the digital image by activating the pixels for which the difference between the value of the pixel in the filtered image and the value of the pixel in the gradient image exceeds a predetermined value.
US09058638B2	Super resolution encoding screens that minimize affects of lossy compression and data variations Methods and systems for super resolution encoding. A matching pattern can be encoded with respect to an original pattern to generate a matching function for converting a screen into an IOT screen. Then, an operation can be implemented for accounting for a disturbance that causes a change in gray value that includes a minimal error while remaining close to the original pattern. The gray value is then mapped to the matching pattern via the matching function to convert the screen into the IOT screen and thereby minimize the effects of lossy compression and data variations caused by the disturbance.
US09058630B2	Coverage for transmission of data method and apparatus The present invention provides systems and methods which afford a technical application for insuring, bonding, and underwriting a transmission of a data set, streaming data, and/or document over the Internet through TCP/IP and all other electronic media such as WAP, VOIP, fiber optic channels, microwave channels, and through standard electrical switches, electrical outlets and power lines. The present invention includes a computer-readable medium having computer-executable instructions to cause a system perform a method for insuring, bonding, and/or underwriting data transmission. The method includes enabling a first remote client coupled to a communications network to insure, bond, and/or underwrite a transmission of an electronic data set, streaming data, and/or document, with a selected coverage type for a selected coverage amount, from the first remote client to one or more second remote clients. The method includes charging a fee to an appropriate account for the selected coverage type and amount.
US09058628B2	Marketplace for trading intangible asset derivatives and a method for trading intangible asset derivatives A marketplace for trading derivative financial contracts includes a forum that publishes a financial contract and allows the financial contract to be traded by one or more market participants. The financial contracts are based on one or more underlying intangible assets of one or more entities. The price of the contract is derived from a measure of value of the one or more underlying assets of the particular financial contract. The forum may include an exchange for trading financial contracts and may also host trading of over-the-counter financial contracts.
US09058627B1	Circular rotational interface for display of consumer credit information A credit score user interface that may comprise a circular visual interface to view a consumer's credit information is disclosed herein. Sections of the circular visual interface may correspond to credit categories, where each section is sized according to the impact of the associated credit category on the consumer's credit score. One of the category sections may be selected, and credit information about a specific consumer that is related to that section may be displayed. The selected credit category may change based on touch input. A change in selection may cause new credit information related to the newly selected credit category to be displayed about the specific consumer.
US09058622B2	Wireless email communications system providing resource update tracking features and related methods A wireless communications system may include a plurality of mobile wireless communications devices to permit users to send and receive wireless electronic mail (email) messages. Each device may be enabled for email communication based upon user acceptance of terms and conditions (T&Cs) in a corresponding user selected language and in a corresponding version at a time of acceptance. The system may further include a resource deployment server which may include a database module for storing the corresponding user selected language and version for the accepted T&Cs for each user. The resource deployment server may also include a service module cooperating with the database module for enabling user review of the accepted T&Cs in the corresponding user selected language and version thereof, and independent of any subsequent change in the user selected language of a given mobile wireless communications device and independent of any subsequent change in version of the T&Cs.
US09058620B1	System and method for communicating between a mobile communication device and a gaming device A system and method for communicating between a mobile communication device and a venue apparatus is disclosed herein. The system comprises a mobile communication device, a venue apparatus, and a wireless local area network (WLAN) for a venue. The venue apparatus comprises a beacon for transmitting low energy BLUETOOTH transmissions. The mobile application is configured to verify a transmission from the venue apparatus in a registry when the mobile communication device is within three feet of the venue apparatus.
US09058617B2	Methods and apparatus to determine an adjustment factor for media impressions Examples to determine media impressions are disclosed. An example method includes detecting a cookie identifier established by a database proprietor at a computing device, determining an impression of media, wherein the impression occurs after the cookie identifier is established, determining a first panelist identifier associated with the impression based on the cookie identifier, determining a second panelist identifier associated with the impression based on determination of a user identity by a panelist meter associated with the computing device, and storing an adjustment factor determined by comparing the first panelist identifier and the second panelist identifier.
US09058616B2	System and method for providing mobile advertisement Provided is a system and method for providing advertisement information using voice recognition when performing a voice call based on a Voice over Internet Protocol (VoIP). The system for providing advertisement information based on a VoIP may include a voice recognition unit to recognize voice information received via an application of a user terminal, an information converter to convert the voice information to text information, an advertisement selector to select advertisement information corresponding to the text information among a plurality of pieces of advertisement information stored in a database, and a transmitter to transmit the selected advertisement information.
US09058611B2	System and method for advertising using image search and classification An advertising system and method are disclosed for generating advertising content based on a user's images. These can be photographs owned by a user of a web page. An advertising template for an advertising sponsor is provided. For a user viewing the web page, a set of the user's images is categorized, based on image content of the images in the set. The categorization is performed with at least one classifier which has been trained on a finite set of image categories. An advertising image is selected for advertising content based on the categorization of the user's images. The template is combined with the selected advertising image to form the advertising content. The advertising content can then be displayed to the user on the web page. A user profile is also disclosed which can be used as the categorized user images.
US09058602B1	Software emulation of contactless smart card behaviour within a portable contactless reader device A handheld transit fare device is provided. The transit fare device includes an NFC interface configured to send and receive data, a memory, and a processor. The processor is configured to receive, via the interface, a list of transactions from a host device using standard smart card protocol commands and reply structures. The list of transactions includes identifiers of fare access media used to gain access to a transit vehicle. The processor is configured to store the list of transactions on the memory and to provide a first indication that the list of transactions has been received. The processor is configured to receive, via the interface, an identifier from a fare access media on the transit vehicle, determine whether the identifier from the fare access media matches one of the identifiers from the list of transactions, and provide a second indication that provides a result of the determination.
US09058599B1	System and method for usage billing of hosted applications A system, method, and computer readable medium for usage billing of one or more hosted applications serving one or more clients. The hosted applications are contained within one or more isolated environments or run without isolated environments. The system may include usage billing based on one or more of resources open, amount of data flowing through resources, number of open files, number of transactions, number of concurrent users, number of processes, CPU utilization and memory usage, The system may further include a management interface where administrators may add, remove and configure isolated environments, configure client policies and credentials, and force upgrades. If using isolated environments, the isolated environments may be isolated from other applications and the host operating system on the clients and applications within the isolated environments may run without performing an application-installation on the client.
US09058594B2	Storing and sharing personal information over the internet A system and method for providing a social network computing system having a database of user records of members of the social network where the user records are structured according to topic. Topics are arranged in an interlinked manner in a topic library stored on the database and managed by database manager. Each topic is related to a set of questions relevant to the topic. For each question, a user preferably records a video recording containing a response to the question. The user records may be edited by the owner or viewed by other members of the social network according to permissions.
US09058593B2	Reception method, reception device, transmission method, transmission device, transmission/reception method, transmission/reception device An electronic mail on which a control command is interpolated is transmitted through a public line, received by a modem section of a gate way, converted to a digital data, and supplied to the control section. A CPU of the control section stores the received electronic mail in a RAM, and extracts the control command contained in the electronic mail. The CPU supplies a control signal corresponding to the control command to an interface section. The interface section controls an IR transmission section to transmit a signal corresponding to the control signal supplied from the CPU or outputs a signal through a connection line, and controls a video deck.
US09058589B2	Subjective user interface Disclosed is a subjective user interface that allows a user to define a worknet from a set of data objects of a business enterprise. The user may instantiate channels which are subsets of the worknet. In embodiments, predefined channels may be created and then installed in the user's subjective user interface, which the user may choose as a new channel. Activity spaces may be defined within a channel comprising members of the channel. The data objects that comprise a worknet, or a channel, or an activity space may comprise people as well as non-person (inanimate) entities.
US09058588B2	Computer-implemented system and method for managing a context-sensitive sidebar window A computer-implemented system and method for managing a context-sensitive sidebar window is provided. Contextual information relevant to an electronic document is determined. A portion of the determined contextual information is presented in a sidebar window. A display of the context-sensitive sidebar window is managed by automatically opening the context-sensitive sidebar window when the electronic document is opened and automatically closing the context-sensitive sidebar window when the document is closed.
US09058587B2	Communication support device, communication support system, and communication support method It is provided a communication support device, which analyzes communications among a plurality of persons who belong to an organization, comprising a recording module for storing data that indicates the communications among the plurality of persons, a network constructing module for constructing a network structure of the plurality of persons from the data that indicates the communications, a improvement candidate determining module for identifying a first person whose communication is to be improved from the data that indicates the communications, and a connection candidate determining module for identifying a second person and a third person who can help increase triangle structures around the identified first person in the network structure, based on the network structure. The communication support device outputs display data for prompting the second person and the third person to communicate with each other.
US09058586B2	Identification of a person located proximite to a contact identified in an electronic communication client A method, which includes, within an electronic communication client, identifying a first person. Via a processor, at least a second person geographically located proximate to a geographic location associated with the first person can be identified. The method further can include, within the electronic communication client, indicating that the second person is geographically located proximate to the geographic location associated with the first person.
US09058580B1	Systems and methods for identification document processing and business workflow integration A method includes receiving or capturing an image comprising an identity document (ID) using a mobile device; classifying the ID; building an extraction model based on the ID classification; extracting data from the ID based on the extraction model; building an ID profile based on the extracted data; storing the ID profile to a memory of the mobile device; detecting a predetermined stimulus in a workflow; identifying workflow-relevant data in the stored ID profile at least partially in response to detecting the predetermined stimulus; providing the workflow-relevant data from the stored ID profile to the workflow; and driving at least a portion of the workflow using the workflow-relevant data. Related systems and computer program products are also disclosed.
US09058578B2	Systems and methods for battery remediation in connection with an electric powered mobiel thing (EPMT) The present disclosure provides, among other things, various systems and methods for battery remediation in connection with electric powered mobile things (EPMTs). A representative method, among others, can be summarized by the following steps: monitoring electric power capacity (EPC) associated with locomotion of the EPMT; monitoring travel data relating to the EPMT; engaging in a communication session with a remote host computer system (H-CS) based upon the EPC monitoring; requesting assistance of a battery remediation station (BRS) during the communication session; communicating location information relating to the EPMT during the communication session so that the BRS can visit and remediate (recharge, repair, or replace) a battery associated with the EPMT. Upon receiving this information, the H-CS can contact and dispatch the BRS to visit the EPMT. A representative system, among others, comprises an EPMT-CS that is programmed or designed to perform the foregoing steps.
US09058576B2	Multiple project areas in a development environment Provided are a computer implemented method, computer program product, and system for partitioning a development environment. A development environment is divided into multiple project areas. Each of the multiple project areas is assigned to a different physical test environment. A solution is assigned to a project area among the multiple project areas. The solution is tested in the assigned physical test environment to modify the physical test environment. The physical test environment associated with the project area is re-initialized without re-initializing other physical test environments.
US09058574B2	Method for estimating the lifespan of a deep-sub-micron integrated electronic circuit A method for estimating the lifetime of a deep-submicron-generation integrated electronic component, linked to a wear mechanism occurring in previously defined special conditions of use, said component being of a deep submicron type, with very large-scale integration, commercially available off the shelf, wherein one assumes that the same sample population always experiences a failure due to: the most predominant failure mechanism, during the period of useful life, described by an exponential law, and the most critical wear mechanism, represented by a Weibull distribution at the end of the previous period.
US09058573B2	Network traffic-analysis-based suggestion generation In one embodiment, a networked device running a social networking application logs local area network traffic in order to maintain a table of connected users on the same LAN. In such embodiments, the networked device uploads its log of LAN traffic to a social networking system, which associates each MAC address with a user of the social networking system, and detects and identifies recurring patterns when the user of the networked device and other users are on the same LAN. Based upon such patterns, the social networking system may suggest that the two users become friends or otherwise interact on the social networking system. In particular embodiments, a networked device running a social networking application may broadcast mDNS messages containing its social networking ID, allowing other similarly configured devices on the same LAN to interact with the user of the device.
US09058567B2	Intelligent production station and production method One aspect related to design of systems and methods for manufacturing products that include technology in skilled areas is configuring a production station for use by an operator without specialized skills. The present invention contemplates an approach to designing a station configurable to perform one or more of incoming inspection, assembly, testing, and branding. A preferred approach includes verifying data associated with units prior to accepting them for incorporation, preventing incorporation of an incorrect unit, and guiding an operator in possible remedial action. This approach includes storing data in a server and making such data substantially instantly accessible to production stations once written in the server. Such data preferably includes software to configure the production station such that the operator need not have specialized skills. A production station designed using this approach is particularly useful in the manufacture of an outdoor unit of a split-mount microwave radio system.
US09058565B2	Opportunistic crowd-based service platform A method and apparatus for providing an opportunistic crowd based service platform is disclosed. A mobile sensor device is identified based on a current location and/or other qualities, such as intrinsic properties, previous sensor data, or demographic data of an associated user of the mobile sensor device. Data is collected from the mobile sensor device. The data collected from the mobile sensor device is aggregated with data collected from other sensor devices, and content generated based on the aggregated data is delivered to a user device.
US09058564B2	Controlling quarantining and biasing in cataclysms for optimization simulations Some examples are directed to selecting at least one candidate solution from a first plurality of candidate solutions that has converged on a suboptimal solution during a computer simulation. The computer simulation tests fitness of the first plurality of candidate solutions for an optimization problem. Some examples are further direct to storing a copy of the at least one candidate solution, performing a cataclysm on the first plurality of candidate solutions, and generating a second plurality of candidate solutions. Some examples are further direct to integrating the copy of the at least one candidate solution into the second plurality of candidate solutions after performing of one or more additional computer simulations that test the fitness of the second plurality of candidate solutions for the optimization problem.
US09058562B2	Traffic prediction for web sites A traffic prediction component may automatically generate predicted traffic profiles for web sites based on tags that characterize the sites. An initial set of tags can be selected for a web site based on a set of predefined rules. An initial traffic profile may be selected based on the initial set of tags. The predicted profile of user traffic is then generated based on the initial set of tags and on the initial traffic profile.
US09058560B2	Methods, apparatus and systems for generating, updating and executing an invasive species control plan Invasive species control plans may be automatically generated using vegetation control information received from a variety of sources. Such invasive species control plans may aid vegetation control personnel and professionals when determining an invasive species control strategy, including treatment and restoration, and then guide the implementation of that strategy. Invasive species control plans may include a variety of recommended vegetation control practices and projected outcomes for the implementation of recommended vegetation control management practices.
US09058558B2	Image processing apparatus and computer program product for performing a drawing process to add a color and a background color of a spot color image based in part on color transparency information An image processing apparatus includes a reception unit, an intermediate data generation unit, an extraction unit, a conversion unit, an addition unit, a determination unit, and a drawing processing unit. In the case where the determination unit determines that intermediate data for spot color image data have background image data, the drawing processing unit performs a drawing process so as to add a color of spot color image data and a color of the background image data of the spot color image data on the basis of color transparency information added by the addition unit, color information on spot color image data converted by the conversion unit, and color information on the background image data.
US09058555B2	Printing apparatus and method of controlling the same, and storage medium There are provided a printing apparatus which holds a job, determines whether attribution information of a sheet to be used by the stored job is registered for a sheet storage unit, judges whether a sheet exists in a sheet storage unit to be used by the job, and notifies a result of the determination and a result of the judgment.
US09058552B2	RFID tag temperature adaptation An RFID system and tag, and a method for identifying objects using an RFID system are disclosed. In an embodiment, an RFID tag comprises a microchip for storing an identification sequence, a tag antenna coupled with the microchip for receiving and transmitting the RF signal; and a ferrous metal portion disposed near the IC and the tag antenna. The ferrous metal portion is sensitive to, and heats up when subjected to, magnetic induction. The heat of the ferrous metal is propagated to the RFID tag such that the tag reaches its operating temperature more quickly.
US09058541B2	Object detection method, object detector and object detection computer program Object detection receives an input image to detect an object of interest. It determines feature matrices based on the received image, wherein each matrix represents a feature of the received image. The plurality of matrices are Fourier transformed to Fourier feature matrices. Fourier filter matrices are provided, each representing a feature of an object transformed in Fourier space. Each filter matrix is point-wise multiplied with one of the feature matrices corresponding to the same feature. The plurality of matrices are summed, resulting by point-wise multiplying each Fourier filter matrix with the corresponding Fourier feature matrix to obtain a Fourier score matrix. An inverse Fourier transform of the Fourier score matrix is performed, resulting in a score matrix, which is used to detect the object in the input image.
US09058540B2	Data clustering method and device, data processing apparatus and image processing apparatus A data clustering method, a data clustering device using the same, and an image processing apparatus and a data processing apparatus equipped with the data clustering device are provided. The method includes sorting a plurality of data point to be clustered and generating a processing sequence based on the sorting, wherein each of the data point has at least one feature value. The method also includes using a non-iterative mechanism to cluster the data points into a plurality of data clusters according to the processing sequence. The method further includes optimizing the generated data clusters. Accordingly, the data clustering method can fast cluster the data points.
US09058539B2	Systems and methods for quantifying graphics or text in an image Systems and methods for quantifying an image generate a grayscale histogram of an image, wherein the grayscale histogram includes a respective number of pixels for a plurality of histogram values; determine a respective percentage of pixels in each of the histogram values based on the numbers of pixels for the respective histogram value and a total number of pixels in the image; compare the respective percentages of the histogram values to a first threshold; add the respective percentages that exceed the first threshold to a total percentage; and compare the total percentage to a second threshold.
US09058538B1	Bundle adjustment based on image capture intervals Methods, systems, and computer program products are provided for determining camera parameters and three dimensional locations of features from a plurality of images of a geographic area. These include, determining a correlation between a pose of a first camera and a pose of a second camera, generating one or more constraints incorporating the correlation, and determining at least one of camera parameters and three dimensional locations of features using a plurality of constraints including the generated one or more constraints. The first camera and the second camera have substantially rigid positions and poses relative to each other. A strength of the correlation is based at least upon a time interval between respective image captures by the first camera and the second camera.
US09058537B2	Method for estimating attribute of object, apparatus thereof, and storage medium An information processing method includes detecting a partial area configuring a target object from an input image, evaluating appropriateness of the detection result, voting with respect to the target object based on the detection result and the evaluation result, and identifying an attribute of the target object based on the voting result.
US09058536B1	Image-based character recognition Various embodiments enable a computing device to capture multiple images (or video) of text and provide at least a portion of the same to a recognizer to separately recognize text from each image. Each of the recognized outputs will typically include one or more text strings for each image. Substrings common to each of the one or more text strings are computed and compared to each text string within each image to determine an alignment consensus for each substring within the text. A template string is generated that includes each common substring in a position corresponding to a determined alignment for a respective substring. A character frequency vote is then applied to unresolved portions and the final text string is determined by filling the unresolved spaces with the character having the highest occurrence rate for a respective space.
US09058535B2	Security barcode A security barcode is made up of modules that include optical disrupters that are too small to be deliberately placed in precise positions. The barcode is authenticated by a simple webcam including three-dimensional positioning means co-operating with a recognizable graphic structure referred to as a “marker”. In order to establish the authenticity of an article protected by the code, a description of the code is made after the code has been printed and is stored in a database, and that description is compared with a new description that results from at least two acquisitions, one made under the same conditions, and the other made while changing the three-dimensionally defined viewpoint and/or the lighting. In its preferred variant, the barcode cannot be printed in order to represent a predetermined number. It is also impossible to reproduce the barcode.
US09058533B2	Method for encoding information in illumination patterns A method for retrieving information encoded in a structured illumination pattern including selecting an encoded structured illumination pattern having a variable intensity; providing an object with a surface having a 3D relief pattern; selecting at least one portion but not all of the object's surface including the 3D surface relief pattern; projecting the selected structured illumination pattern onto the selected portion of the surface; using a digital camera to capture an image of the reflected structured light pattern from the selected portion of the surface; storing the image in a memory; and processing the image of the detected reflected structured light pattern using a processor responsive to the detected reflected structured light pattern and the selected structured light pattern to retrieve the encoded information, wherein the encoded information is based on the geometrical and material properties of the 3D surface relief pattern and is distinct from the object, surface, or relief pattern.
US09058527B2	Apparatus having hybrid monochrome and color image sensor array There is provided in one embodiment an apparatus having an image sensor array. In one embodiment, the image sensor array can include monochrome pixels and color sensitive pixels. The monochrome pixels can be pixels without wavelength selective color filter elements. The color sensitive pixels can include wavelength selective color filter elements.
US09058521B2	Mobile robot and simultaneous localization and map building method thereof A simultaneous localization and map building method of a mobile robot including an omni-directional camera. The method includes acquiring an omni-directional image from the omni-directional camera, dividing the obtained omni-directional image into upper and lower images according to a preset reference to generate a first image, which is the lower image, and a second image, which is the upper image, extracting feature points from the first image and calculating visual odometry information calculating visual odometry information to track locations of the extracted feature points based on a location of the omni-directional camera, and performing localization and map building of the mobile robot using the calculated visual odometry information and the second image as an input of an extended Kalman filter.
US09058516B2	Automatic identification of fields and labels in forms A system and method for processing form images including strokes. A controller receives a plurality of form images including a plurality of strokes. A stroke identification module identifies the position of each stroke in each of the form images. A geometry engine generates an overlay of the plurality of form images and identifies a group of overlapping strokes from the overlay. The geometry engine generates a field bounding box encompassing the group of strokes, the field bounding box representing a field in the plurality of form images. The geometry engine crops a field image from each form image based on the size and position of the field bounding box. A label detector analyzes an area around the field image in the form image to determine a label and generates a label image.
US09058515B1	Systems and methods for identification document processing and business workflow integration A method involves: receiving an image comprising an ID; iteratively classifying the ID; and driving at least a portion of a workflow based at least in part on the classifying; wherein at least some of the classification iterations are based at least in part on comparing feature vector data, wherein a first classification iteration comprises determining the ID belongs to a particular class, and wherein each classification iteration subsequent to the first classification iteration comprises determining whether the ID belongs to a subclass falling within the particular class to which the ID was determined to belong in a prior classification iteration. Related systems and computer program products are also disclosed.
US09058513B2	Image verification device, image processing system, image verification program, computer readable recording medium, and image verification method An image verification device that checks an input image obtained by photographing an object to be checked against a registered image database, wherein, in the registered image database, an amount of feature of an image obtained by photographing an object is registered as a registered image, and the registered image includes registered images registered with respect to a plurality of objects, has a verification score calculating unit that calculates a verification score serving as a score representing a degree of approximation between the objects indicated by the registered images and the object of the input image by using the amount of feature of the input image and the amounts of feature of the registered images, and a relative evaluation score calculating unit.
US09058512B1	Systems and methods for digital signature detection A system, method and computer-readable medium are provided to enable digital bank endorsement. A digital image of a back side of a check may be placed in a computer memory. Appropriate coordinates for a bank endorsement may be determined. A bank endorsement may be automatically generated. The digital image may then be electronically altered by overlaying, merging, or rendering text of the generated bank endorsement. A modified digital image may be combined with an image of the front side of the check and stored and/or exported to check clearing operations.
US09058511B2	Biometrics sensor module, assembly, manufacturing method and electronic apparatus using such biometrics sensor module A biometrics sensor module includes a housing, a biometrics sensor and a coupling electrode. The housing has a first surface and a second surface opposite to the first surface. The biometrics sensor has a sensing surface, which is disposed on the first surface of the housing and has sensing members arranged in an array. The coupling electrode is disposed on the first or second surface of the housing. Two regions, projected from the sensing surface and the coupling electrode to the second surface of the housing, do not overlap with each other. A coupling signal is provided to the coupling electrode and directly or indirectly couples the coupling signal to an object, so that the sensing members of the biometrics sensor sense biometrics messages of the object contacting with the second surface of the housing.
US09058510B1	System for and method of controlling display characteristics including brightness and contrast A system and method for controlling display characteristics is disclosed. The system and method includes a memory and a processor coupled to the memory configured to execute instructions stored in the memory to detect video input from a sensor, receive a control signal from a user and use the input control signal to alter a level of pixel intensity in a video output. The system and method for controlling display characteristics also includes altering the video input into the video output according to an algorithm and displaying the video output signal with an altered level of pixel intensity.
US09058507B2	Signal processor with an encrypting or decrypting device in a memory system Original data to be a source for an encryption key is read from a memory cell array and stored in a buffer region. An encryption key generation unit generates a plurality of encryption keys by variously modifying the original data read from the buffer region based on a predetermined generation rule. The encryption unit generates an encrypted command by encrypting commands individually with an encryption key different for each command, out of the plurality of encryption keys generated by the encryption key generation unit.
US09058501B2	Method, apparatus, and computer program product for determining media item privacy settings An apparatus for determining media item privacy settings may include a processor. The processor may be configured to receive media item capture data associated with a media item. The media item capture data may include at least a capture location. The processor may also be configured to identify a privacy context that corresponds to the media item capture data. In this regard, the capture location of the media item capture data may be within a geographic zone of the privacy context. The processor may be further configured to determine a privacy setting for the media item based on the corresponding privacy context, and, in some embodiments, control access to the media item in accordance with the determined privacy setting. Associated methods and computer program products may also be provided.
US09058500B2	Method and apparatus for inputting data Embodiments of the present invention provide a method and an apparatus for inputting data. The present invention relates to the communications field and aims to improve security of input information. The method includes: acquiring, by a virtual machine manager, input data; performing, by the virtual machine manager, encryption processing on the input data according to an encryption rule of a security connection to obtain encrypted data, where the security connection refers to a connection that is established between an application interface and a server and used for data transmission; and sending, by the virtual machine manager, the encrypted data to the server. The present invention is applicable to a data input scenario.
US09058496B1	Securely reconfiguring a multi-node system to prevent firmware rollback A method initiates boot of a multi-node system including a first compute node scaled together with a second compute node, wherein the multi-node system boots from a basic input output system of the first compute node that is identified as a primary node by a trusted platform module of the first compute node. The method further includes receiving a request to reconfigure the multi-node system so that the second compute node would become the primary node, and reconfiguring the multi-node system so that the second node is the primary mode only in response to a user manually asserting physical presence to a trusted platform module of the first compute node. A system provides compute nodes that each include a trusted platform module having first and second non-volatile indices for controlling the configuration of the multimode system.
US09058490B1	Systems and methods for providing a secure uniform resource locator (URL) shortening service A computer-implemented method to provide a secure uniform resource locator (URL) shortening service is described. A URL is received via a browser provided on a display of a computing device. A shortened URL is generated to represent the received URL. A determination is made as to whether a classification assigned to a web site associated with the shortened URL is valid. Upon determining that the assigned classification is not valid, the web site is evaluated in order to assign an updated valid classification to the web site.
US09058489B2	Marking documents with executable text for processing by computing systems Techniques for processing documents with executable text are disclosed. The techniques, among other things, can effectively address XSS attacks to Internet users when browsing web sites. Content deemed not to be trusted or fully trusted (“untrusted”) can be marked in a document that can include executable text. Remedial action, including not allowing execution of executable text marked as “untrusted” can be taken. In addition, when the document is processed, content deemed not to be trusted or fully trusted (“untrusted”) can be effectively monitored in order to identify executable text that may have been effectively produced by “untrusted” content and/or somehow may have been affected by “untrusted” content.
US09058484B2	Method for checking whether program instructions have been executed by a portable end device A method and a system for checking whether program instructions have been executed by an end device, wherein, the end device calls for program instructions and the program instructions are stored in executable form in a trustworthy entity, in particular a chip card. Subsequently, the program instructions are variably modified in the trustworthy entity such that the modified program instructions vary upon each execution of the method. Through execution of the instructions in the end device there is obtained a check value which is in turn transferred to the trustworthy entity and verified in the trustworthy entity.
US09058480B2	Directional touch unlocking for electronic devices A system and machine-implemented method for matching input gestures on a touch interface to a security pattern to allow user access to an electronic device or account. The security pattern may correspond to a combination of linear and non-linear input gestures relating to directional changes of the input gestures. A determination of the security pattern may be based on the end motion and speed of each input gesture.
US09058474B2	Biometric device, system, and method for individual access control A biometric device, and a corresponding system and a method, is used to control human access to an arbitrary area. The device includes a biometric capture system that reads specified biometric information from an individual and that compares the biometric information to previously stored biometric information to determine a match between the read and stored biometric information; a position location system that records the geographic location of the device, and determines if the device is inside the United States or outside the United States; an encryption system that encrypts the geographic location and a device-unique identification; and a wireless system that sends the encrypted geographic location and the device-unique identification to a remote location, where if the geographic location is inside the United States, the device receives a test satisfactory signal, and where if the geographic location is outside the United States, the device receives an exit satisfactory signal.
US09058469B2	End user license agreement detection and monitoring An approach is provided for detecting and monitoring end user license agreement (EULA) compliance is provided. A request to access a executable software code is received from an end user. A EULA version corresponding to the requested executable software code is identified. A determination is made as to whether the end user has accepted the identified EULA. If the end user has not accepted the identified EULA, then an out of date EULA notification is sent to the end user, the EULA is sent to the end user requesting an acceptance to the EULA. A EULA response is received from the end user. If the end user accepts the EULA, then the end user is allowed access to the executable software code.
US09058466B1	Enabling security of a computer system Enabling security of a computer system. Physical proximity of an authorized user with the computer system is detected without requiring the authorized user to physically access the interior of the computer system is monitored. In response to detecting the physical proximity of an authorized user, the authorized user is allowed access to privileged operations of the computer system.
US09058465B2	Counter operation in a state machine lattice Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may include a counter suitable for counting a number of times a programmable element in the lattice detects a condition. The counter may be configured to output in response to counting the condition was detected a certain number of times. For example, the counter may be configured to output in response to determining a condition was detected at least (or no more than) the certain number of times, determining the condition was detected exactly the certain number of times, or determining the condition was detected within a certain range of times. The counter may be coupled to other counters in the device for determining high-count operations and/or certain quantifiers.
US09058464B2	Customer aircraft customization system A method and apparatus for managing options for an aircraft. A selected option for the aircraft is received. A number of engineering options is identified for the selected option. The number of engineering options is in an aircraft option database comprising engineering options for the options for the aircraft. An engineering option in the engineering options is a pre-certified design meeting a group of regulations pertaining to airworthiness of the pre-certified design in the aircraft. A final design including the number of engineering options associated with resources in which the final design is for building the selected option in the aircraft is generated using the number of engineering options identified in the aircraft option database for the selected option.
US09058462B2	System and method for leakage estimation for standard integrated circuit cells with shared polycrystalline silicon-on-oxide definition-edge (PODE) A system and method of producing an integrated circuit using abutted cells having shared polycrystalline silicon on an oxide definition region edge (PODE) includes modeling inter-cell leakage current in a plurality of different cells. Each of the plurality of different cells is abutted with another cell and having the shared PODE. The method also comprises verifying a pre-determined acceptable power consumption of the integrated circuit based on the inter-cell leakage current.
US09058461B2	Transferring heat through an optical layer of integrated circuitry A method in a computer-aided design system for generating a functional design model of an integrated circuitry structure including generating a functional representation of at least first and second regions of the integrated circuitry structure, generating a functional representation of an optical layer comprising optical waveguides, and generating a functional representation of a heat-conductive material for transferring heat from at least the second region through the optical layer to a heat sink.
US09058459B1	Integrated circuit layouts and methods to reduce leakage An embodiment includes a method, comprising: receiving a layout of an integrated circuit having a plurality of regions; determining a utilization for each of the regions; for each region, selecting from among a plurality of switch cell organizations for the region in response to the corresponding utilization; and for each region, modifying the layout to include switch cells for the region according to the selected switch cell organization.
US09058454B1	Method and apparatus to reduce power segmentation overhead within an integrated circuit A method and apparatus to provide a power segmentation architecture that substantially eliminates the routing and area penalties associated with conventional power segmentation architectures. Power switching components are configured within the external interconnect portion of the integrated circuit (IC) to reduce the number of inter-layer interconnects that must be traversed in order to programmably supply operational power to the various device segments of the IC. A system-in-package (SIP) integration approach is alternately taken, whereby the power switching components utilized within the power segmentation architecture are conveniently allocated among the base or stacked die to reduce the number of inter-layer interconnects. The power switching components may also be implemented off-chip as discrete switching components such as a transistor or a micro-miniature switch/relay.
US09058453B2	System and method for configuring a channel A system and method are provided for configuring a plurality of pin resources. The method includes identifying a plurality of pin resources of a primary application specific integrated circuit (ASIC) device and configuring the plurality of pin resources based on a pin distribution between a first interface and a second interface, where the first interface provides a first communication path between the primary ASIC device and a first device, and the second interface provides a second communication path between the primary ASIC device and a second device.
US09058452B1	Systems and methods for tracing and fixing unknowns in gate-level simulation A computer executable tool analyzes unknowns (Xs) in gate-level simulation and traces their sources to determine if the Xs are generated due to X-pessimism. For Xs generated due to X-pessimism, fixes are generated to correct simulation results. Corrected simulation results match real hardware behavior and greatly reduce the analysis effort of engineers.
US09058449B2	Simulating machine and method for determining sensitivity of a system output to changes in underlying system parameters The invention provides improved apparatus, systems and methods for simulating systems, processes and environments characterized by stochastic processes. The invention is particularly useful when Monte Carlo or Quasi Monte Carlo simulation techniques are employed in a simulation. The invention provides indications of sensitivities of simulated process outputs to changes in underlying process parameters. Embodiments of a simulator of the invention operate at a speed suitable for use in real time environments. In addition, the computational cost of a simulator of the invention relative to the cost associated with the output process is independent of the number of sensitivities and of the number of observations involved in the simulation.
US09058448B2	Usage-based temporal degradation estimation for memory elements Methods and systems for computing threshold voltage degradation of transistors in an array of memory cells are disclosed. In accordance with one method, a process that models an expected usage of the array is selected. In addition, a hardware processor can run the process to populate the array with data over time to simulate the expected usage of the array. The method further includes compiling data that detail different durations at which each of the memory cells in the array stores 1 or at which each of the memory cells in the array stores 0. For each separate grouping of memory cells that share a common duration of the different compiled durations, a threshold voltage degradation is determined for each transistor in the corresponding grouping of cells based on at least one biased temperature instability model.
US09058442B2	Incorporating noise and/or jitter into waveform generation Methods and apparatus disclosed herein operate, for example, to derive a non-ideal received signal from an ideal signal, to compute, from the non-ideal received signal, at least one probability density function of amplitude and time values representing deviations from the ideal signal, to derive at least one amplitude noise component and at least one timing jitter component from the at least one probability density function, and to generate a non-ideal waveform by applying the at least one amplitude noise component and the at least one timing jitter component to an ideal waveform.
US09058440B1	Method and mechanism for verifying and simulating power aware mixed-signal electronic designs Disclosed are methods, systems, and structures for implementing an improved approach for simulating mixed-signal electronic circuits with specialized power management requirements, such as low power designs. Some approaches provide an improved method and system for providing a highly reliable, usable and scalable solution to allow for designers to use their power information files in a mixed-signal simulation and carry the impact of power intents defined on the digital blocks onto the analog blocks without needing any manual changes to models/designs.
US09058438B2	Application-requirement based configuration designer for distributed computing systems Techniques for automatically designing an application-requirement based configuration for a distributed computing system are provided. One or more application-level templates are obtained, wherein the one or more templates are representative of one or more requirements associated with one or more applications. Using the one or more application-level templates, one or more logical flows are created. The one or more logical flows are then used to generate one or more system-level configuration plans of the distributed computing system.
US09058435B2	Labeling method and apparatus for documenting the occurrence of triggering events Provided is a labeling apparatus that generates a label for labeling a drug container. The labeling apparatus includes a code reader that interrogates a computer-readable code, and a local computer-readable memory that stores a drug formulary with a plurality of drug entries. A processing component identifies, from the formulary, a specific drug that corresponds to the computer-readable code read by the code reader and creates log entries in response to triggering events. The log entries include at least one of system information, user information, drug information, and patient information. And a printer is provided to print label content identifying the specific drug onto a label that is to be applied to the drug container.
US09058433B2	Advanced extensible interface bus and corresponding data transmission method An advanced extensible interface (AXI) bus is disclosed. 2×2 AXI crossbars are used as basic units; each including two slave interfaces and two master interfaces; an N2 full Mesh fabric is built by using the basic units, so that each slave interface on one basic unit is connected to a master interface on another basic unit to form a first path. A data transmission method includes: receiving, through a master interface of a basic unit, a data packet sent by a master device; sending, through a slave interface of the basic unit, the data packet to a destination slave device by using an AXI bus; receiving, through the slave interface of the basic unit, a response packet returned by the destination slave device, where the basic units are 2×2 AXI crossbars and the AXI bus is based on an N2 full mesh fabric built by using the basic units.
US09058432B2	Data transferring circuit and data transferring/receiving system A data transferring circuit includes a data transferor configured to transfer data through a plurality of parallel data transfer lines, wherein the data transferor is further configured to partially invert the transferred data in response to an inversion signal, and a pattern sensor configured to enable the inversion signal when data transferred through the parallel data transfer lines is to cause three sequential lines to transfer data of a logic value through a middle one of the sequential lines and data of an inverse of the logic value through the remaining ones of the sequential lines or cause all of the transfer lines to transfer data of a same logic value.
US09058431B2	Methods and articles of manufacture for hosting a safety critical application on an uncontrolled data processing device Methods and articles of manufacture for hosting a safety critical application on an uncontrolled data processing device are provided. Various combinations of installation, functional, host integrity, coexistence, interoperability, power management, and environment checks are performed at various times to determine if the safety critical application operates properly on the device. The operation of the SCA on the UDPD may be controlled accordingly.
US09058428B1	Software testing using shadow requests The techniques described herein provide software testing that may concurrently process a user request using a live version of software and a shadow request, which is based on the user request, using a shadow version of software (e.g., trial or test version, etc.). The live version of software, unlike the shadow version, is user-facing and transmits data back to the users while the shadow request does not output to the users. An allocation module may vary allocation of the shadow requests to enable a ramp up of allocations (or possibly ramp down) of the shadow version of software. The allocation module may use allocation rules to dynamically initiate the shadow request based on various factors such as load balancing, user attributes, and/or other rules or logic. Thus, not all user requests may be issued as shadow requests.
US09058427B2	Iterative generation of symbolic test drivers for object-oriented languages A method includes, by one or more computing devices, determining instructions for a computing device to be evaluated, creating a first symbolic test driver including one or more of the instructions to be evaluated and a designation of a symbolic variable corresponding to a portion of the instructions, symbolically executing the instructions with respect to the symbolic variable, determining a test case from the results of the symbolic execution including one or more commands to execute the instructions with a given value for the symbolic variable, determining one or more calls to an object-oriented-programming component in the commands, creating a new symbolic test driver including the calls based on the determined calls, and subsequently symbolically executing the new symbolic test driver.
US09058426B2	Identifying potential lock conditions in transactional software applications Methods for testing a transactional software application which interacts with a database structure. The software application includes a plurality of application units, which are adapted to be executed at least in part concurrently. The method includes executing the software application. Executing the software application includes executing a plurality of transaction operations on the database structure by a plurality of respective invocations of a database management system of the database structure by the respective plurality of application units. The method also includes determining locks being applied by the database management system on elements of the database structure for each transaction operation executed by each application unit individually. The method also includes identifying potential lock conditions of the software application in possible successions of application of the locks according to possible interleaving of the application units.
US09058422B2	Polling determination Techniques for polling an input/output (I/O) device are described herein. The techniques include polling a device for data from the I/O device, and receiving the data from the I/O device at the host device as a result of the polling. The techniques include determining whether the data received is the same as data received at a previous polling of the I/O device. Upon determining the data received is the same, the techniques include decreasing the polling rate if the data is the same, and if it is not the same. Upon determining the data is not the same, the techniques include increasing the polling rate if the data is not the same.
US09058418B2	Molecular profiling of tumors Provided herein are methods and systems of molecular profiling of diseases, such as cancer. In some embodiments, the molecular profiling can be used to identify treatments for a disease, such as treatments that were not initially identified as a treatment for the disease or not expected to be a treatment for a particular disease.
US09058417B2	Thread serialization and disablement tool A computer-implemented method of performing runtime analysis on and control of a multithreaded computer program. One embodiment of the present invention can include identifying threads of a computer program to be analyzed. With a supervisor thread, execution of the identified threads can be controlled and execution of the identified threads can be monitored to determine a status of the identified threads. An indicator corresponding to the determined status of the threads can be output.
US09058414B2	Remotely controlled data logging A method and system to remotely control data logging are described including establishing a first connection, transmitting a signal to initiate data logging, terminating the established first connection, initializing a timer, determining if the timer has expired, establishing a second connection, transmitting a signal to cease data logging, transmitting a signal to collect the logged data and receiving the logged data.
US09058407B2	Persistent multimedia content versioning Systems, methods, and other embodiments associated with versioned persistent storage of multimedia content in a database object are described. One example method includes controlling a database management system (DBMS) to instantiate a database object that has a binary large object (BLOB) attribute, an XML edits attribute, and a set of metadata attributes. The method includes storing a binary stream associated with a multimedia content (e.g., medical image) in the BLOB attribute and storing an editing history of the set of metadata attributes as a set of edit entries in the XML edits attribute. The method also includes controlling the DBMS to store the database object in a column in a table in a relational database managed by the DBMS.
US09058406B2	Management of multiple advertising inventories using a monetization platform In embodiments of the present invention improved capabilities are described for delivery of a sponsored content to a mobile communication facility user. In embodiments, a request may be received for a sponsored content from a publisher, and one or more content inventories may be searched for a content that is relevant to the request. Content may be selected for delivery to the publisher from one or more content inventory. The content may be selected based at least in part on a relevance between the content and the request. The content, and the content inventory from which the relevant content is chosen, may be selected based at least in part on a statistical weight relating to the amount of revenue a wireless operator may realize upon presentation of the content to a mobile communication facility.
US09058405B2	Playback apparatus and playback method A playback apparatus includes a storage unit and a processor. The storage unit stores therein, for each of a plurality of playback environments, information indicating suitability for playback of a content in association with an identifier of the content. The processor receives a content via a network. The processor selects a playback environment based on an identifier of the received content and the information stored in the storage unit. The processor starts a first virtual machine that includes the selected playback environment. The first virtual machine is one of a plurality of virtual machines each including a playback environment. The playback environments included in the plurality of virtual machines are different from one another. The processor requests the first virtual machine to play back the received content.
US09058399B2	System and method for providing network resource identifier shortening service to computing devices A system and method for providing shortened network resource identifier service to computing devices uses a link translating technique to replace at least some of the links in network resources requested by the computing devices using shortened network resource identifiers so that network activities of the computing devices can be monitored or controlled.
US09058398B2	Managing use of a shared content consumption device Features are disclosed for identifying multiple users contending for use of a shared media device with which to present a content item. Users may be detected by the shared media device or a management component, and each user may have previously begun and stopped consumption at a different point within the content item. When multiple users wish to consume the content, a component or module determines which presentation position to use, or creates a new presentation position for use. In cases in which not all users have begun consuming or wish to consume the same content item, a component or module determines which content item to present.
US09058394B2	Matching and recommending relevant videos and media to individual search engine results A computer-implemented system and process for generating video search engine results page is disclosed. The system provides a query term and retrieves a collection of search results. Tags are generated for each search result and used to match media objects to each search result. The search results and video objects related to each search result are returned as a video search engine results page.
US09058393B1	Tools for appraising a domain name using keyword monetary value data Systems and methods of the present invention provide for storing one or more data records, comprising a text string and a monetary value associated with the text string, in a database. One or more server computers may receive an appraisal request for a domain name and identify one or more keywords in the domain name. The server(s) may then determine an existence of one or more matching data records wherein the text string in the record(s) match the identified keyword. If the matching data records exist, the server(s) may identify a keyword frequency count and a keyword monetary value for that keyword. A keyword appraisal value may be generated by dividing the keyword monetary value by the keyword frequency count. The appraisal value for all identified keywords may be added to the domain name appraisal and the domain name appraisal may be transmitted to a client computer.
US09058392B1	Client state result de-duping Methods, systems, and computer-readable media for client state result de-duping may comprise receiving from a client a first query comprising one or more search terms; obtaining from a data store a first list of search results relevant to the one or more search terms; generating state information representing the first list of search results; sending a first response to the client that includes the first list of search results and the state information; receiving from the client a second query comprising the one or more search terms and the state information; obtaining a second list of search results comprising items that have been added to the data store since the first query; removing from the second list of search results one or more search results represented by the received state information; and sending a second response to the client that includes the second list of search results.
US09058391B2	System and method for transmitting a feed related to a first user to a second user Disclosed is a server computer and method that provides a first user interface to a first client computer operated by a first user for display by a first web browser. The first web browser displays web content to the first user. The server computer provides a second user interface to a second client computer operated by a second user for display by a second web browser. The server computer receives a feed request from the second client computer of the second user for a feed related to the first user. The server computer transmits the feed related to the first user to the second client computer to enable the second user to receive at least a portion of the web content.
US09058372B2	Database management in a wireless communication system An apparatus, system, and method provide database management within a wireless communication system by maintaining a database within wireless communication devices transmitting changes using wireless messages. An initiating slave wireless communication device, maintaining a first data version of a database, transmits a database modification request message to a master wireless communication device maintaining a second data version of the database. After modifying the second data version of the database in accordance with the database modification request message, the master wireless communication device transmits a database modification instruction to any number of non-initiating slave wireless communication devices to modify other data versions of the database maintained at the respective non-initiating slave wireless device. As a result, the multiple data versions are synchronized to maintain a database within the wireless communication system.
US09058371B2	Distributed database log recovery Log entries are recorded in a data storage application (such as an in-memory database, etc.) for a plurality of transactions among nodes in a node hierarchy. The node hierarchy comprises master node having a plurality of slave nodes. Thereafter, at least a portion of the master node log entries are replayed until a first replay position is reached. Next, for each slave node, at least a portion of its respective log entries are replayed until the first replay position is reached (or an error occurs). Subsequently, replay of at least a portion of the log entries of the master node that are subsequent to the first replay position is initiated by the master node in parallel to at least a portion of the replaying by the slave nodes. Related apparatus, systems, techniques and articles are also described.
US09058369B2	Consolidated network repository (CNR) The disclosed subject matter relates to an architecture that can facilitate support for or integration of disparate communications networks. The architecture can embody a consolidated network repository (CNR) that can be configured as a single logical repository that can potentially be configured according to a common schema regardless of the type or number of schema employed by the disparate communications networks.
US09058367B2	Methods and systems for staging and propagating data A method and system for propagating database records from staging database to a production database so that the production database reflects record changes made in the staging database. The system of the present disclosure propagates record changes from the staging database to the production database in a flexible, customizable, and reliable way. The system consolidates database record changes to cull out any unnecessary record changes that do not need to be propagated. The system may also track the status of the database record changes, and send alerts related to the propagation status.
US09058366B2	Indexing and searching content behind links presented in a communication Among other disclosures, a method may include identifying content in an electronic communication, the content including a link. The method may include characterizing content associated with the link and storing the characterization. Upon detecting a match of a characterization, presenting one or more of the communication or portion thereof, the link or content associated with the link.
US09058364B2	Variable personalization of search results in a search engine A search engine provides personalized rankings of search results. A user interest profile identifies topics of interest to a user. Each topic is associated with one or more sites, and a boost value, which can be used to augment an information retrieval score of any document from the site. Search results from any search are provided to the user, with a variable control of the ranking of the results. The results can be ranked by their unboosted information retrieval score, thus reflecting no personalization, or by their fully or partially boosted information retrieval scores. This allows the user to selectively control how their interests affect the ranking of the documents.
US09058363B2	Computer implemented methods and apparatus for providing a distribution list of users in an online social network A distribution list of users of an online social network can be used to communicate database record information to the users. In some implementations, one or more users of the online social network are identified as being relevant to the record and who are not following the record. A distribution list is provided and includes the information identifying the one or more relevant users. A network communication can be sent to users identified in the distribution list. The network communication identifies the record or information associated with the record.
US09058361B2	Method and system for applying a group of instructions to metadata In accordance with embodiments, there are provided mechanisms and methods for applying a group of instructions to metadata in the context of an on-demand database service. These mechanisms and methods for applying a group of instructions to metadata can enable embodiments that ensure that “all or none” of the operations corresponding to the grouped instructions are performed. The ability of embodiments to provide such feature can prevent a scenario where only a portion of a desired effect is accomplished which, in turn, may complicate any effort to undo the same.
US09058360B2	Extensible language framework using data cartridges A framework for extending the capabilities of an event processing system using one or more plug-in components referred to herein as data cartridges. In one set of embodiments, the data cartridge framework described herein can enable an event processing system to support one or more extension languages that are distinct from the native event processing language supported by the system. For example, certain “extension language” data cartridges can be provided that enable an event processing system to support complex data types and associated methods/operations that are common in object-oriented languages, but are not common in event processing languages. In these embodiments, an event processing system can access an extension language data cartridge to compile and execute queries that are written using a combination of the system's native event processing language and the extension language.
US09058359B2	Proactive risk analysis and governance of upgrade process An incompatible software level of an information technology infrastructure component is determined by comparing collected inventory information to a minimum recommended software level. If a knowledge base search finds that the incompatible software level is associated with a prior infrastructure outage event, an outage count score is determined for the incompatible software level by applying an outage rule to a historic count of outages caused by a similar incompatible software level, and combined with an average outage severity score assigned to the incompatible software level based on a level of severity of an actual historic failure of the component within a context of the infrastructure to generate a normalized historical affinity risk score. The normalized historical affinity risk score is provided for prioritizing the correction of the incompatible software level in the context of other normalized historical risk level scores of other determined incompatible software levels.
US09058356B2	SQL execution plan baselines Approaches, techniques, and mechanisms are disclosed for maintaining a set of baseline query plans for a database command. Except in rare circumstances, a database server may only execute a command according to a baseline plan, even if the database server predicts that a different plan has a lower cost. The set of baseline plans are plans that, for one reason or another, have been determined to provide acceptable actual performance in at least one execution context. When the database server receives a request to execute a particular command, the database server, if possible, always executes the command according to the lowest predicted cost baseline plan. The database server may evolve the plan baseline to include additional plans by generating and testing new plans in response to new requests to execute the database command, or as part of a query optimization or tuning process.
US09058355B1	Scalable, adaptable, and manageable system for multimedia identification An architecture for a multimedia search system is described. To perform similarity matching of multimedia query frames against reference content, reference database comprising of a cluster index using cluster keys to perform similarity matching and a multimedia index to perform sequence matching is built. Methods to update and maintain the reference database that enables addition and removal of the multimedia contents, including portions of multimedia content, from the reference database in a running system are described. Hierarchical multi-level partitioning methods to organize the reference database are presented. Smart partitioning of the reference multimedia content according to the nature of the multimedia content, and according to the popularity among the social media, that supports scalable fast multimedia identification is also presented. A caching mechanism for multimedia search queries in a centralized or in a decentralized distributed system and a client based local multimedia search system enabling multimedia tracking are described.
US09058353B2	Computer relational database method and system having role based access control A computer method, system and apparatus control access to secured data in a plurality of databases. A repository is coupled to the databases and has a security runtime subsystem. The repository intercepts a user query of a subject database in the plurality. The security runtime subsystem determines from the intercepted query a user and corresponding user role. Based on user role, the security runtime subsystem automatically modifies the user query to filter out secure data for which the identified user is unauthorized to access but are part of the user query.
US09058350B2	Computer-implemented method of determining validity of a command line Provided is a method of determining command line validity, including: a step of maintaining a block network address database including block network address information; a step of receiving a command line from a terminal of a user; a step of extracting network address information included in the command line; a step of determining whether the network address information is the block network address information, with reference to the block network address database; a step of generating log information associated with the command line in case that the network address information is not the block network address information as the result of the determination, in which the log information comprises at least one of the network address information included in the command line, input time point information with respect to the input time point of the command line, and request content information; a step of recording the log information in a log database; and a step of determining the validity of the command line by using the log information.
US09058348B2	Method for building and maintaining trusted supplier records An Enterprise Network includes a master data management (MDM) system that is linked to two or more data sources each of which include means for storing local management information. The MDM system builds a master management information database that is comprised of some or all of the management information stored by the data sources. The master database in the MDM includes master records each of which is comprised of one or more attributes. The MDM system is configured to only update particular master record attributes with selected management information received from a trusted data source.
US09058347B2	Prospective search of objects using K-D forest A collection of content objects and a representative content object may be stored in a k-dimensional tree. In one embodiment, a method includes receiving a content object; constructing a first k-dimensional tree in response to determining a second k-dimensional tree is storing information corresponding to a number of content objects that is equal to a number of nodes of the second k-dimensional tree; storing information corresponding to the received content object as a node in the first k-dimensional tree; and moving information corresponding to a stored content object from of each node of the second k-dimensional tree to a corresponding node of the first k-dimensional tree, wherein the corresponding node of the first k-dimensional tree is identified based at least in part on content of the content object.
US09058346B2	Ordered index Systems and methods for processing an index are described. A postings list of items containing a particular term are ordered in a desired retrieval order, e.g., most recent first. The ordered items are inserted into an inverted index in the desired retrieval order, resulting in an ordered inverted index from which items may be efficiently retrieved in the desired retrieval order. During retrieval, items may first be retrieved from a live index, and the retrieved items from the live and ordered indexes may be merged. The retrieved items may also be filtered in accordance with the items' file grouping parameters.
US09058345B2	System and method of generating reusable distance measures for data processing In one embodiment the present invention includes a computer-implemented method of analyzing data. The method includes storing, by a computer system, a column definition that includes metadata that defines a column. The method further includes generating, by the computer system, a distance measure for the column. The method further includes storing, by the computer system, the distance measure for the column as part of the metadata for the column in the column definition. In this manner, improvements may result in the areas of reuse, delegation, usability, and precalculation.
US09058342B2	Image classification device, method, program, recording media with program thereon, and integrated circuit According to a conventional image classification device that extracts a feature from an image and classifies the image with use of the extracted feature, in the case where one image and another one image, which are included in an image group, each have a different feature, the one image and the other one image might be each classified into a different category. In order to solve this problem, an image classification device relating to the present invention calculates, with respect to each of persons appearing in a plurality of images included in an image group which have been photographed with respect to one event, a main character degree that is an index indicating an important degree in units of image groups, and classifies the images into any one of different classification destination events in units of image groups based on the calculated main character degrees.
US09058333B2	Publishable metadata for content management and component testing Techniques related to publishable metadata for content management are described that enable selective invocation of new components in a web content management system. Metadata that is published in connection with corresponding content can be configured to include tags or other identifiers that cause a content management system to selectively direct content processing between existing and new components. Switches implemented by the content management system can operate to examine the metadata to determine which processing components are selected for particular content and direct the content to corresponding components. Switches can also be placed in websites to direct page requests from clients to existing or new rendering controls based upon publishable metadata that is associated with a requested page. Thus, the metadata and switches can be employed to perform testing of and load balancing between new and existing components in a live environment.
US09058331B2	Generating a conversation in a social network based on visual search results The present invention includes a system and method for generating a conversation in a social network based on visual search results. A mixed media reality (MMR) engine indexes source materials as MMR objects, receives images from a user device and identifies matching MMR objects. A content management engine generates metadata corresponding to the MMR objects. A social network application generates conversations corresponding to the MMR object. The conversation includes multiple discussion threads. If a conversation already exists, the social network application provides the user with access to the conversation.
US09058326B1	Recovery and flush of endurant cache Various embodiments are directed towards enabling data writes utilizing a node cache and a logstore stored on a stable storage device. A client device may send data to a node for writing to a parent file. The node may cache the received data prior to writing the data to the parent file. Caching the received data may comprise adding the received data to a node cache and to a logstore. In one embodiment, the node cache may include a coalescer that combines data from a plurality of data writes from the client device to the node prior to writing to the parent file. In some embodiments, the logstore may be mirrored logstore on one or more stable storage devices. The parent file may periodically be updated from the node cache data. After the parent file is updated, the node cache data and the logstore data may be purged.
US09058325B2	Information providing system, apparatus and method for information processing, and computer program product An information providing system includes the following elements. An IC card stores card ID. An information providing terminal reads out the card ID of the IC card, provides information to the IC card, and transmits the card ID and the information provided to the IC card or the ID of the provided information to a management server. The management server receives the card ID and the information provided to the IC card or the provided information ID from the information providing terminal, has a database to manage the card ID and the provided information such that the card ID is associated with the provided information, acquires the information provided to the IC card from the database in response to an information request from a client terminal, and supplies the provided information to the client terminal. The client terminal displays the provided information supplied from the management server.
US09058322B2	Apparatus and method for providing two-way automatic interpretation and translation service The present invention relates to an apparatus and method for providing a two-way automatic interpretation and translation service. The apparatus includes a first interpretation and translation unit for interpreting and translating a first language into a second language. A second interpretation and translation unit interprets and translates the second language into the first language. A context information management unit receives conversational context and translation history information, and shares and manages the conversational context and translation history information. Each of the first and second interpretation and translation units provides an interpretation service for receiving an input conversation in the first or second language in speech and outputting results of interpretation in speech in the second or first language, and a translation service for receiving an input conversation in the first or second language in text and outputting results of translation in text in the second or first language.
US09058321B2	Support for international search terms—translate as you crawl A search engine server delivers search results to a web browser of a client device communicatively coupled to the search engine server via the Internet. The system identifies new web pages in a source language during crawling, translates them into a plurality of destination languages, creates reverse indexes in respective languages, and stores both reverse indexes and cache web pages in a database. Upon the entry of search strings by a user using a web browser, the search engine server responds by delivering links of web pages in the user-desired language (the language of the search string or a language chosen by the user) as well as web pages translated from a plurality of destination languages, ranked based upon popularity or other means. The search engine server contains a plurality of translators that translate new web pages, links that are obtained during crawling, in to a plurality of destination languages.
US09058318B2	Flexible web page template building system and method A flexible web page template and template building tool which generates templates that grow and shrink according to an amount of user content.
US09058316B2	System and method for annotation of data visualizations A method and computer program product for generating a data visualization based, at least in part, upon a data set. A first user is allowed to add an annotation to at least a portion of the data visualization. A determination is made concerning whether the annotation is associatable with any portion of the data set.
US09058313B2	Test method for distributed processing system and distributed processing system A program on a plurality of processing units executes test input data. In the case where an error occurs so that processing of the program is not completed normally, it is determined that a test performed by using the input data failed. Meanwhile, in the case where an error does not occur so that processing of the program is completed normally, if the same feature pattern as that of the input data is stored in a storing unit which stores feature patterns of the executed input data, it is determined that the test performed by using the input data succeeded, while if the feature pattern is not stored in the storing unit, the result of the test performed by using the input data is judged based on the result of comparing the expected data with result data of the program.
US09058310B2	Method for determining effective core aspect ratio for display of content created in an online collage-based editor In an online collage-based editor, a method for determining an effective aspect ratio for a selected project orientation that includes a group of two or more available page sizes having different aspect ratios and displaying a project page at a derived aspect ratio in the GUI during editing includes the steps (a) determining for each page size in the group, the viewable area of each page, (b) recording the aspect ratios of the viewable areas of step (a), (c) using a mathematical function, describing a total amount of error present amongst the available aspect ratios of step (b) for a given aspect ratio, (d) using a mathematical program, process, or automated calculation tool, finding the effective aspect ratio that minimizes the function and hence the error value of step (c), and (e) displaying the project page at the selected effective aspect ratio.
US09058309B2	Methods and systems for multiple styling HyperText Markup Language (HTML) form fields Techniques to provide multiple styles in a single HTML text object. An input field to receive user-generated input is presented. User-generated input is received via the input field. The user-generated input based on formatting criteria. The formatting criteria provides N formatting types to be applied to the user-generated input, where N is at least two. An underlay field is provided for each of N−1 formatting types. One of the formatting types is applied to each of the N−1 underlay fields and the input field. The N−1 underlay fields are aligned with and the input field. Portions of the user-generated input are displayed within the corresponding fields while maintaining spacing of the user-generated input.
US09058306B2	Redundant storage enclosure processor (SEP) implementation for use in serial attached SCSI (SAS) environment An information handling system includes a storage enclosure operable to communicate with a storage initiator. The storage enclosure includes a first controller corresponding to a first storage domain for enabling access between the storage initiator and a plurality of storage targets using a storage protocol. A second controller of the system, corresponding to a second storage domain, is operable to enable access between the storage initiator and the plurality of storage targets. A second storage enclosure subsystem is part of the second controller and a second configurable extra-protocol interconnection between the second storage enclosure subsystem and the first controller enables the second storage enclosure subsystem to function as a storage enclosure subsystem for the first controller.
US09058305B2	Remote copy method and remote copy system A remote copy system includes: a first storage system having a first logical volume accompanied with a first plurality of disk drives in the first storage system; a second storage system having a second logical volume, which is a virtual volume not accompanied with a second plurality of disk drives in the second storage system, the virtual volume configuring a first remote copy pair with the first logical volume; and a third storage system having a third logical volume accompanied with a third plurality of disk drives in the third storage system, the third logical volume configuring a second remote copy pair with the virtual volume and storing a copied data of data stored in the first logical volume. If the second storage system receives write data sent from the first storage system to the virtual volume, the second storage system transfers the write data to the third logical volume.
US09058304B2	Continuous workload availability between sites at unlimited distances Continuous workload availability between sites at unlimited distances, which includes receiving a unit of work data. Once the unit of work data has been received the workload that the unit of work data is directed to is determined, and a primary site of a plurality of sites to process the unit of work is chosen. If the processing of the unit of work data is successful, then one of one or more processing systems of the primary site are selected to process the unit of work data, and the unit of work data is replicated to at least one other site. The primary site is separated from each of the plurality of sites by a distance greater than a metropolitan area network (MAN) and operations occur within a customer acceptability window.
US09058303B2	Convex collective matrix factorization A method operates on observed relationship data between pairs of entities of a set of entities including entities of at least two (and optionally at least three) different entity types. An observed collective symmetric matrix is constructed in which element (n,m)=element (m,n) stores the observed relationship between entities indexed n and m when the observed relationship data includes this observed relationship. A prediction collective symmetric matrix is optimized in order to minimize a loss function comparing the observed collective symmetric matrix and the prediction collective symmetric matrix. A relationship between two entities of the set of entities is predicted using the optimized prediction collective symmetric matrix. Entities of the same entity type may be indexed using a contiguous set of indices such that the entity type maps to a contiguous set of rows and corresponding contiguous set of columns in the observed collective symmetric matrix.
US09058296B2	Data processing method, memory storage device and memory control circuit unit A data processing method, a memory storage device, and a memory control circuit unit are provided. Here, each physical address corresponds to one flag. The data processing method includes: receiving a reading command; reading first data stored in the physical addresses of a physical programming unit; determining whether a first flag in the physical programming unit is in a first status or a second status; transmitting decrypted first data or decrypted specific-format data to a host system according to whether the first flag is in the first status or the second status. Accordingly, the encryption operation may be simplified.
US09058292B2	System and method for one step address translation of graphics addresses in virtualization A system and method including, in some embodiments, receiving a request for a graphics memory address for an input/output (I/O) device assigned to a virtual machine in a system that supports virtualization, and installing, in a graphics memory translation table, a physical guest graphics memory address to host physical memory address translation.
US09058291B2	Multiple erasure correcting codes for storage arrays Embodiments of the invention relate to erasure correcting codes for storage arrays. An aspect of the invention includes receiving a read stripe from a plurality of storage devices. The read stripe includes a block of pages arranged in rows and columns, with each column corresponding to one of the storage devices. The pages include data pages and parity pages, with the number of parity pages at least one more than the number of rows and not a multiple of the number of rows. The method further includes reconstructing at least one erased page in response to determining that the read stripe includes the at least one erased page and that the number of erased pages is less than or equal to the number of parity pages. The reconstructing is responsive to a multiple erasure correcting code and to the block of pages. The reconstructing results in a recovered read stripe.
US09058287B2	Relocating page tables and data amongst memory modules in a virtualized environment Relocating data in a virtualized environment maintained by a hypervisor administering access to memory with a Cache Page Table (‘CPT’) and a Physical Page Table (‘PPT’), the CPT and PPT including virtual to physical mappings. Relocating data includes converting the virtual to physical mappings of the CPT to virtual to logical mappings; establishing a Logical Memory Block (‘LMB’) relocation tracker that includes logical addresses of an LMB, source physical addresses of the LMB, target physical addresses of the LMB, a translation block indicator for each relocation granule, and a pin count associated with each relocation granule; establishing a PPT entry tracker including PPT entries corresponding to the LMB to be relocated; relocating the LMB in a number of relocation granules including blocking translations to the relocation granules during relocation; and removing the logical addresses from the LMB relocation tracker.
US09058285B2	Method and system for forensic data analysis in fraud detection employing a digital pattern more prevalent than Benford's Law A computerized system for a digital method for the detection of fraud and/or anomalous transactions is disclosed based on a novel statistical interpretation of Benford's Law and a unique set of computer implementations outlining the development of digital distributions from the low-value region on the left of a given data set to the high-value region on the right. A division into sub-intervals of the entire data set along adjacent integral powers of ten suggested in the method provides the unique manner of visualizing and computer output actualization of the gradual evolution of digital distribution from near digital equality on the left to severe inequality on the right. The method provides a venue for detecting fraud committed by the sophisticated cheater well-aware of Benford's Law but inventing data without regards to development. Experimental results consistently demonstrate the effectiveness of the techniques used in embodiments of the invention.
US09058282B2	Dynamic cache write policy A system, processor and method to monitor specific cache events and behavior based on established principles of quantized architectural vulnerability factor (AVF) through the use of a dynamic cache write policy controller. The output of the controller is then used to set the write back or write through mode policy for any given cache. This method can be used to change cache modes dynamically and does not require the system to be rebooted. The dynamic nature of the controller provides the capability of intelligently switching from reliability to performance mode and back as needed. This method eliminates the residency time of dirty lines in a cache, which increases soft errors (SER) resiliency of protected caches in the system and reduces detectable unrecoverable errors (DUE), while keeping implementation cost of hardware at a minimum.
US09058279B2	Methods and systems for caching data using behavioral event correlations A method is disclosed including a client accessing a cache for a value of an object based on an object identification (ID), initiating a request to a cache loader if the cache does not include a value for the object, the cache loader performing a lookup in an object table for the object ID corresponding to the object, the cache loader retrieving a vector of execution context IDs, from an execution context table that correspond to the object IDs looked up in the object table and the cache loader performing an execution context lookup in an execution context table for every retrieved execution context ID in the vector to retrieve object IDs from an object vector.
US09058276B2	Per-rank channel marking in a memory system Channel marking is provided in a memory system that includes a memory channel with a plurality of memory devices. The memory devices are arranged into a first group of memory devices and a second group of memory devices. The memory system is configured to perform a method that includes determining that more than a threshold number of memory devices in the first group are failing. An error correction code (ECC) is configured to compensate for errors associated with memory devices in the first group on the memory channel and to perform error correction on errors associated with memory devices in the second group on the memory channel.
US09058273B1	Frequency determination across an interface of a data processing system One or more systems, devices, methods, and/or processes described can determine a maximum cache command rate of a processor unit. For example, an interface of the processor unit configured to be coupled to an interconnect of a multiprocessor system and configured such that a first portion of the interface provides a signal to a second portion of the interface, where the first portion of the interface operates utilizing a known frequency and the second portion of the interface operates utilizing a cache frequency of the processor unit; the second portion of the interface circulates the signal; the first portion of the interface receives the signal from the second portion of the interface; the first portion of the interface determines a cache command rate based on the known frequency, the frequency of the cache, and the signal; and the interface provides information indicating the cache command rate to the interconnect.
US09058272B1	Method and apparatus having a snoop filter decoupled from an associated cache and a buffer for replacement line addresses An apparatus including a snoop filter decoupled from a cache and an associated method for snoop filtering are disclosed. The snoop filter is decoupled from the cache such that the cache changes states of lines in the cache from a first state that is a clean state, such as an exclusive (E) state, to a second state that is not a clean state, such as a modified (M) state, without the snoop filter's knowledge. The snoop filter buffers addresses of replaced lines that are unknown to be clean until a write-back associated with the replacement lines occurs, or until actual states of the replaced lines are determined by the snoop filter generating a snoop. A multi-level cache system in which a reallocation or replacement policy is biased to favor replacing certain lines such as inclusive lines, non-temporal lines or prefetched lines that have not been accessed, is also disclosed.
US09058267B2	I/O path selection A map of storage locations that indicates storage locations associated whose associated I/O transactions are to be processed by firmware running on a storage controller is maintained. The map is communicated to a storage controller driver. The storage controller driver receives a first I/O transaction request. Based on the map, and the storage location to be accessed by the first I/O transaction request, the first I/O transaction request is sent to a storage device without further processing by the firmware running on the storage controller. The storage controller driver receives a second I/O transaction request. Based on the map and the location to be accessed by the second I/O transaction request, the second I/O transaction request is sent for further processing by the firmware running on the storage controller.
US09058266B2	Deskew apparatus and method for peripheral component interconnect express Disclosed herein are a deskew apparatus and method for Peripheral Component Interconnect (PCI) Express for compensating for a skew. The deskew apparatus includes a lane data input unit, a lane data alignment unit, and a lane data detection unit. The lane data input unit receives 18-bit data from each of lanes of the PCI Express. The lane data alignment unit aligns the 18-bit data using a COM symbol. The lane data detection unit detects a change in a state of alignment of the 18-bit data attributable to deletion or addition of an SKP symbol when the 18-bit data is aligned, and to perform synchronization between the lanes.
US09058264B2	Method for repairing communication abnormality between data card and host and data card An embodiment of the present invention provides a method for repairing a communication abnormality between a data card and a host. When an abnormality occurs on communication between a data card and a host, executing repair data in the data card to repair the operating system of the host; resetting the data card and reporting an optical disk descriptor; and detecting, by the data card, the type of the operating system of the host according to a received minicomputer system interface command. According to the embodiments of the present invention, in a process of communication between the data card and the host, when an abnormality occurs on the communication between the data card and the host and therefore the data card can no longer be used, the abnormality is able to be automatically repaired, thereby greatly improving repair efficiency and reducing a repair duration and repair complexity.
US09058256B2	Data writing method, memory controller and memory storage apparatus A data writing method for a rewritable non-volatile memory module is provided. The method includes selecting at least one physical erasing unit as a global random area and building a global random area searching table for recording update information corresponding to updated logical pages that data stored in the global random area belongs to. The method also includes receiving updated data belonging to a logical page; and determining whether a data dispersedness degree corresponding to the global random area is smaller than a data dispersedness degree threshold. The method further includes, if the data dispersedness degree corresponding to the global random area is smaller than the data dispersedness degree threshold, writing the update data into the global random area and recording update information corresponding to the logical page in the global random area searching table.
US09058253B2	Data tree storage methods, systems and computer program products using page structure of flash memory A tree data structure is stored in a flash memory device by storing a leaf node and an index node comprising a pointer to the leaf node in a same page of the flash memory device, which may be read on a per-page basis. A modified version of the leaf node and a modified version of the index node may be stored in a new page of the flash memory device when, for example, a key value is added to or deleted from the leaf node.
US09058245B2	Releasing blocks of storage class memory An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.
US09058240B2	Multi-context remote development A method implemented by a processor and a system develop a software project targeting one or more remote systems. The method includes generating a project on a local system, which includes receiving user input through a user interface. The project includes one or more source files. The method also includes generating one or more remote contexts corresponding to the one or more remote systems.
US09058239B2	Hypervisor subpartition as concurrent upgrade A processor-implemented method for a concurrent software service upgrade is provided. The processor implemented method may include receiving a type of service request corresponding to the software service upgrade, determining, by the processor, the type of service request and then generating a plurality of subpartitions corresponding to a hypervisor. The method may further include applying the service request to at least one subpartition within the plurality of subpartitions, wherein the service request is applied to the at least one subpartition based on the type of service request and balancing the system resources among the plurality of subpartitions upon the applying of the service request to the at least one subpartition.
US09058236B2	Monitoring apparatus, management system, firmware updating method, and program thereof An apparatus, control method, and system for updating firmware of an image forming apparatus remotely such that the image forming apparatus is monitored to determine the state of the image forming apparatus at the time the update instruction is received and to monitor whether the firmware in the image forming apparatus has been updated successfully.
US09058232B2	Systems and methods to create a clean install of an application Disclosed herein are methods, systems, and software for computer application installation. In one example, a method of computer application installation includes executing a computer application installer. The method further provides, interrupting the computer application installer with a clean install mechanism, and forcing installation of all application components even if one or more of the application components was previously installed.
US09058230B1	Online expert system guided application installation An online expert system that can communicate software installation instructions to a remote node through the use of a generic installer executing on the remote node is provided. Embodiments of the online expert system can identify a set of installation instructions configured to install a software product on the remote node, execute the set of installation instructions, record results of the execution of the installation instructions, and, if an error is detected in the results, submit the results for analysis to determine whether a solution to the error is available and execute the solution, if any. Aspects of the online expert system provide for the executing of the installation instructions to include communicating installation-related information to the remote node over a network. Further aspects of the online expert system provide for executing a solution to an error to include communicating solution-related information to the remote node over the network.
US09058229B2	Method and apparatus for maintaining operability with a cloud computing environment A method and apparatus for maintaining operability with a cloud computing environment. The apparatus includes a storage module and a local environment module. The storage module may store cloud computing data from a cloud computing environment onto a local storage device. The storage module may communicate with the cloud computing environment through a remote connection. The local environment module may operate a local cloud computing environment from the local storage device while the remote connection to the cloud computing environment is unavailable. The local cloud environment may replicate at least a portion of the cloud computing environment and may be operated from the stored cloud computing data.
US09058227B2	Transactional service pipeline An approach for connecting the inputs and the outputs of multiple services in such a way that the entire transaction can be tracked from beginning to end and from service to service is provided. The pipeline architecture of the present invention passes information through a sequence of nodes, each node providing some processing or filtering before passing information to the next node in the pipe. A transaction's token passes down a pipe of services. The pipe can have forks and branches, so a transaction's token is passed from node to node carrying messages from one node to another. The overall transactional information is not lost from service to service; instead it is carried up and down the length of the pipeline. As the transaction's token is passed up and down the pipeline, its history passes with it. The pipe links a chain of nodes connected end-to-end.
US09058226B2	Automated execution of processes Example systems and methods of executing processes are described. In one implementation, a method identifies an event and accesses a business rule to identify and execute a process associated with the event. A decision table is accessed to identify multiple conditions associated with the event. The decision table is also accessed to identify multiple actions associated with the event. The multiple conditions and actions were previously defined by at least one user of the system. The event and the multiple conditions are evaluated to determine whether to perform at least one of the multiple actions.
US09058222B1	System and method for distributed login with secure transfer to processor node based on one or more identifiers A distributed networked computer system is provided. The distributed networked computer system receives processing threads from a plurality of workstations and distributes the processing threads to selected processing nodes through a load balancer. The load balancer is configured to recognize certain enterprise users and transfer the processing threads from the certain enterprise users to dedicated processing nodes dedicated to processing the threads of those certain users.
US09058215B2	Integration of a calculation engine with a software component Various embodiments of systems and methods for integrating a calculation engine of an in-memory database with a software component are described herein. A control unit schedules and triggers jobs to be processed by an operational unit. The control unit and the operational unit are at an application level. The operational unit divides a job workload corresponding to a job trigger into work packages based on one or more parameters. The work packages are sent to a calculation engine in an in-memory database. At the in-memory database, operations are performed on the work packages and an output is generated. A log in the control unit is updated based on the output.
US09058214B2	Computer network, computer system, computer-implemented method, and computer program product for managing session tokens A computer network for managing session tokens may include a client operable to run a client application; a web server hosting at least one web service; and a session token manager. The session token manager may be operable to receive a check out message along with user credentials from the client application, wherein the user credentials identify a user operating the client application; process the check out message to determine a session token from a pool of session tokens managed for the user; and send a token identifier (token ID) to the client application pointing to the determined session token, wherein the session token can be used by the client application to point to and/or to re-use a previously established session with the web service without re-establishing a new session.
US09058209B2	Methods and apparatus for efficient tone detection An apparatus for determining the presence of a tone in an input signal includes memory circuitry and data processing circuitry coupled to the memory circuitry. The data processing circuitry is operative to receive multiple samples of the input signal, and to determine a first value at least in part by multiplying each of the samples by respective ones of a first set of values for an impulse response and summing the results. The data processing system is also operative to determine a second value at least in part by multiplying each of a portion of the samples by respective ones of a second set of values for the impulse response and summing the results. The data processing system is operative to determine the power of the tone in the multiple samples of the input signal at least in part by utilizing the first value and the second value.
US09058208B2	Method of scheduling tasks for memories and memory system thereof A method of scheduling a plurality of tasks for a plurality of memories in a memory system is disclosed. The method includes classifying each task among the plurality of tasks to a task type among a plurality of task types, disposing a plurality of task queues according to the plurality of task types wherein each task queue stores tasks to be executed within the plurality of tasks, assigning a priority for each task type among the plurality of task types, disposing at least one execution queue; and converting a first task stored in a first task queue among the plurality of task queues into at least one command to be stored in a first execution queue among the at least one execution queue, wherein the at least one command is executed according to the priority of a first task type corresponding to the first task queue.
US09058206B2	System, method and program product for determining execution flow of the scheduler in response to setting a scheduler control variable by the debugger or by a processing entity A system, computer program and a method for debugging a system, the method includes: controlling, by a debugger, an execution flow of a processing entity; setting, by the debugger or the processing entity, a value of a scheduler control variable accessible by the scheduler; wherein the debugger is prevented from directly controlling an execution flow of a scheduler; and determining, by the scheduler, an execution flow of the scheduler in response to a value of the scheduler control variable.
US09058203B2	System, apparatus and method for translating data A distributed processor-based system comprises a plurality of communicating platforms, wherein a number of platforms in the distributed processor-based system comprise at least one compiler, the at least one compiler being operably coupled to data type translation logic and arranged to generate a memory layout for the respective platform. In response to an indication for a communication to occur between a first platform and a second platform the data type translation logic translates a memory layout using data type attributes for data to be transferred from the first platform to the second platform based on at least one platform-specific characteristic, such that the data does not require translating when received at the second platform.
US09058197B2	Method for sharing memory of virtual machine and computer system using the same A method for sharing memories of virtual machines is provided. The method is applied for a computer system configured to execute at least one virtual machine. The method includes the following steps. A memory map corresponding to the virtual machines is obtained, wherein usage states of memory pages of the virtual machine are stored in the corresponding memory map. Unused memory pages of the virtual machines are marked as free pages according to the corresponding memory map. The free pages of the virtual machines are shared. Therefore, the unused memory pages in the virtual machine can be shared. A computer system using the foregoing method is also provided.
US09058192B2	Handling pointers in program code in a system that supports multiple address spaces Some embodiments include a processing subsystem that compiles program code to generate compiled program code. In these embodiments, while compiling the program code, the processing subsystem first identifies a pointer in the program code that points to an unspecified address space. The processing subsystem then analyzes at least a portion of the program code to determine one or more address spaces to which the pointer may point. Next, the processor updates metadata for the pointer to indicate the one or more address spaces to which the pointer may point, the metadata enabling a determination of an address space to which the pointer points during subsequent execution of the compiled program code.
US09058191B2	Direct transfer of executable software image to memory allocated by target processor based on transferred image header In a multiprocessor system, a primary processor may store an executable image for a secondary processor. A communication protocol assists the transfer of an image header and data segment(s) of the executable image from the primary processor to the secondary processor. Messages between the primary processor and secondary processor indicate successful receipt of transferred data, termination of a transfer process, and acknowledgement of same.
US09058189B1	Automatic user account selection for launching an application A system and method is provided for selecting an appropriate user account for accessing an application, the system, the method including receiving a request to launch an application while in a first user account, identifying a plurality of user accounts including the first user account, selecting one of the plurality of identified user accounts for launching the application, wherein the selected one of the plurality of user accounts provides functionality for launching the application and providing the user with access to the selected one of the plurality of identified user accounts.
US09058187B2	Displaying current task lists on graphical user interfaces of processing machine control Methods, computer program products and devices for displaying a current task list on a graphical user interface of a control computer of a processing machine. In implementations, a running task list is provided, each task of the running task list including a task that is running on the control computer, a release task list is defined, each task of the release task list being selectively provided in the release task list based on predetermined, dynamically monitored selection criteria, the current task list is defined, each task of the current task list being provided in the running task list and in the release task list, and the current task list is displayed on the graphical user interface.
US09058185B2	Information processing system, device, mobile terminal and device driver installation method There is provided an information processing system including an information processing apparatus, at least one device, and a mobile terminal, the information processing apparatus being configured to perform a data communication with the at least one device in accordance with a first communication method, the mobile terminal being configured to perform the data communication with the information processing apparatus in accordance with the first communication method, and a data communication with the at least one device in accordance with a second communication method. If there exists device information, among a plurality of pieces of the device information the information processing apparatus obtained from the devices, coincides with the particular device information, the device corresponding to the piece of information that is identical to the particular device information is set as the device subjected to the installation.
US09058184B2	Run time generation and functionality validation of device drivers A method of generating and validating a device driver for a hardware device is provided. The method include (i) dynamically querying the hardware device for a device programming specification, (ii) dynamically querying a run time environment for a run time specification, (iii) obtaining the device programming specification that is specific to the hardware device, (iv) obtaining the run time specification that is specific to the hardware device and the run time environment, (v) dynamically synthesizing a device driver, by a device driver generation tool to obtain a synthesized device driver, (vi) automatically testing, by the device driver generation tool, the synthesized device driver based on a device class of the hardware device, and (vii) automatically evaluating, by the device driver generation tool, a performance of the synthesized driver with respect to standard performance parameters for the device class of the hardware device for validating the synthesized device driver.
US09058183B2	Hypervisor isolation of processor cores to enable computing accelerator cores Techniques for utilizing processor cores include sequestering processor cores for use independently from an operating system. In at least one embodiment of the invention, a method includes executing an operating system on a first subset of cores including one or more cores of a plurality of cores of a computer system. The operating system executes as a guest under control of a virtual machine monitor. The method includes executing work for an application on a second subset of cores including one or more cores of the plurality of cores. The first and second subsets of cores are mutually exclusive and the second subset of cores is not visible to the operating system. In at least one embodiment, the method includes sequestering the second subset of cores from the operating system.
US09058182B2	Management device for causing devices to update programs and computer readable media A management device may be connected with first and second devices via a network. The management device may acquire “m” programs that are to be updated in the first device and “n” programs that are to be updated in the second device, from a server. Each of “m” and “n” may be an integer greater than or equal to 2, the “m” programs may include first and second programs, and the “n” programs may include a third and a fourth programs. The management device may transmit the first program to the first device and transmit the third program to the second device. The management device may, after completion of the transmitting the first program and the third program, transmit the second program to the first device and transmit the fourth program to the second device.
US09058181B2	Conditional processing method and apparatus A conditional processing method and apparatus for efficient memory management are provided. A conditional processing method includes generating a parse tree by loading a plurality of nodes of data structured based on a declarative description language in a memory in series; evaluating, when a parsing switch node having an attribute describing a condition for conditional processing exists among the nodes, child nodes of the parsing switch node according to the attribute; loading only the child nodes fulfilling the attribute in the memory; and outputting the child nodes retained on the memory.
US09058179B2	Retirement serialisation of status register access operations A processor 2 for performing out-of-order execution of a stream of program instructions includes a special register access pipeline for performing status access instructions accessing a status register 20. In order to serialise these status access instructions relative to other instructions within the system access timing control circuitry 32 permits dispatch of other instructions to proceed but controls the commit queue and the result queue such that no program instructions in program order succeeding the status access instruction are permitted to complete until after a trigger state has been detected in which all program instructions preceding in program order the status access instruction have been performed and made any updates to the architectural state. This is followed by the performance of the status access instruction itself.
US09058178B2	Selective posted data error detection based on request type In a data processing system, a selection is made, based at least on an access type of a memory access request, between at least a first timing and a second timing of data transmission with respect to completion of error detection processing on a target memory block of the memory access request. In response to receipt of the memory access request and selection of the first timing, data from the target memory block is transmitted to a requestor prior to completion of error detection processing on the target memory block. In response to receipt of the memory access request and selection of the second timing, data from the target memory block is transmitted to the requestor after and in response to completion of error detection processing on the target memory block.
US09058175B2	Parameter promotion in a block diagram modeling environment A computational device receives, from a user, a selection of a block, a subsystem or multiple blocks from a block diagram modeling environment, and presents, to the user, a set of parameters associated with the block, subsystem, or multiple blocks. The computational device receives, from the user, selection of a first subset of parameters from the set of parameters, and creates a customized dialog box by promoting the selected first subset of parameters to the customized dialog box, wherein the customized dialog box permits editing of values associated only with the first subset of parameters.
US09058172B2	Method for conserving power using a wireless card reader Methods, systems, and apparatus, for conserving power in a system, comprising: (a) receiving a card interaction from a card at a card interface of the system, where the system comprises components including: a microcontroller, one or more card interfaces, a power source, an antenna, and a wake-up circuit, where the components are powered down, and where the card interaction triggers the wake-up circuit; (b) activating a power source using a signal from the wake-up circuit; (c) powering the microcontroller using the power source and in response to powering the microcontroller: (i) powering down the wake-up circuit; (ii) powering up the card and the respective card interface associated with the card interaction; (iii) receiving card data from the card through the card interface; (iv) powering down the card and the respective card interface; (v) powering up the antenna; and (vi) sending the card data using the antenna.
US09058166B2	Method and apparatus for managing processing resources in a distributed processing system In one aspect, the present invention reduces average power consumption in a distributed processing system by concentrating an overall processing load to the minimum number of processing units required to maintain a defined level of processing redundancy. When the required number of active processing units is fewer than all available processing units, the inactive processing units may be held in a reduced-power condition. The present invention thereby maintains the defined level of processing redundancy for reallocating jobs responsive to the failure of one of the active processing units, while reducing power consumption and simplifying jobs allocation and re-allocation when expanding or shrinking the active set of processing units responsive to changing processing load. As a non-limiting example, the distributed processing system is implemented within a telecommunications network router or other apparatus having a configured set of processing cards, such as control-plane processing cards.
US09058161B2	Universal power supplying apparatus and universal power supplying method There are provided a universal power supplying apparatus and a universal power supplying method that can be universally used for various types of devices having a variety of voltage and current levels of a driving power. The universal power supplying apparatus includes a power supplying unit that converts an input power into a driving power having a previously set voltage level and supplies the converted power, a power recognizing unit that outputs a recognized voltage having the previously set voltage level to an output terminal from which power is output to recognize connection of a device, and controls a power output of the power supplying unit according to a detected rated output, and a detecting unit that provides a detection voltage having the previously set voltage level to the output terminal.
US09058159B2	Electronic device with air guiding duct An electronic device includes an enclosure and a first air guiding duct mounted in the enclosure. The first air guiding duct includes a first part and a second part. The first part defines a first air channel and a second air channel. The second part defines a third air channel communicating with the first air channel and a fourth air channel located at a side of the second air channel. A guiding wall is located in the second air channel and extends from the second air channel to the fourth air channel. When air flows from the first part to the second part of the first air guiding duct, air flows from the first air channel to the third channel to cool a first electronic component, and flows from the second air channel to the fourth air channel by the guiding wall to cool a second electronic component.
US09058154B2	Window substrate and display device having the same A window substrate for a display device includes a base substrate including a display region and a non-display region disposed adjacent to at least one portion of the display region, a light shielding layer on the base substrate and facing at least one portion of the non-display region, the light shielding layer having at least one opening, and a filter layer on the base substrate and facing the opening, the filter layer being adapted to transmit a portion of a light passing through the opening.
US09058151B2	Handle module, hard disk drive assembly, and server A handle module, a hard disk drive (HDD) assembly, and a server are provided. The server includes a case with a mounting hole, a main board, and the HDD assembly. The HDD assembly includes a tray with two slide rails and a fixing hole, a HDD, the handle module, and a rubber pad. The handle module includes a handle with a body plate and a sidewall, a backing sheet, and a switch button. The body plate has a first opening and an inner surface. The sidewall has a second opening. The switch button is disposed between the backing sheet and the inner surface and has a first protrusion protruded out of the first opening and a second protrusion. The number of components disassembled from the server relies on the relative position between the second protrusion and the second opening, the fixing hole, and the mounting hole.
US09058148B2	Communication apparatus, control method therefor, and storage medium A communication apparatus configured to communicate with an external apparatus includes a recording unit configured to record content data on a removable recording medium, a transmission unit configured to transmit the content data to the external apparatus, a selection unit configured to select a mode from among a plurality of modes including a setting mode and a transmission mode, a determination unit configured to determine whether the removable recording medium is in an attachable and detachable state, and a control unit configured to control communication with the external apparatus, wherein, in a case where the selected mode is the setting mode when it is determined by the determination unit that the removable recording medium is in the attachable and detachable state, the control unit does not stop communication with the external apparatus.
US09058140B2	Print control apparatus and method utilizing a paper saving print setting When a printer apparatus is allowed to execute a printing of a document using paper based on a print setting set by the user, the following processes are executed in order to allow the user to recognize a paper saving print setting. Whether or not there is a print setting which can save an amount of paper compared to the print setting set by the user is determined. If it is determined that a paper saving print setting exists, the user is notified of such a paper saving print setting.
US09058138B2	System and method for releasing print jobs based on location information A system and method that provides a user interface on a mobile network terminal for operation with a printer resource access system wherein the user interface is modified for releasing a print job from a nearby printer resource. Since printer resources may include any number of print job release mechanism each requiring different authentication information, the user interface must be modified appropriately. The mobile network terminal obtains location information from a location service, such as GPS or an internet based location service, and provides the location information to a punter directory service in a printer resource access system. The printer directory service then consults the database of printer resource information and provides connection and configuration information for printer resource located nearby the mobile network terminal. The mobile network terminal modifies its user interface to accept the appropriate type of authentication and configuration information specified by the printer directory service. The authentication information may then be provided over a secure network connection to the printer resource to release the print job.
US09058135B1	Synchronization of timers across clock domains in a digital system Testing a digital system includes calculating a first ratio of a first clock frequency for a first clock domain and a second clock frequency for a second clock domain different from the first clock domain using a processing device and calculating a first offset between a first timer in the first clock domain and a second timer in the second clock domain. Using an expression dependent upon the first offset and the first ratio, event data from at least one of the first clock domain or the second clock domain is converted to a common clock domain.
US09058134B2	Signal synchronizing device A signal synchronizing device includes a trigger module for capturing an input signal according to a first clock signal which corresponds with the input signal so as to generate a trigger signal, a storage unit for forming a first pulse signal by pulling an output thereof to a first logic level according to the trigger signal, and by pulling the output thereof to a second logic level according to a feedback reset signal, and a synchronizing module for performing synchronous transfer according to the first pulse signal so as to output an output signal corresponding with frequency of a second clock signal, and for generating the feedback reset signal according to the output signal.
US09058129B2	System and method of correlation and change tracking between business requirements, architectural design, and implementation of applications A system can use metadata and metadata mappings to track changes between business requirements, architectural design and implementation.
US09058123B2	Systems, methods, and interfaces for adaptive persistence A storage module may be configured to service I/O requests according to different persistence levels. The persistence level of an I/O request may relate to the storage resource(s) used to service the I/O request, the configuration of the storage resource(s), the storage mode of the resources, and so on. In some embodiments, a persistence level may relate to a cache mode of an I/O request. I/O requests pertaining to temporary or disposable data may be serviced using an ephemeral cache mode. An ephemeral cache mode may comprise storing I/O request data in cache storage without writing the data through (or back) to primary storage. Ephemeral cache data may be transferred between hosts in response to virtual machine migration.
US09058117B2	Block-level single instancing Described in detail herein are systems and methods for single instancing blocks of data in a data storage system. For example, the data storage system may include multiple computing devices (e.g., client computing devices) that store primary data. The data storage system may also include a secondary storage computing device, a single instance database, and one or more storage devices that store copies of the primary data (e.g., secondary copies, tertiary copies, etc.). The secondary storage computing device receives blocks of data from the computing devices and accesses the single instance database to determine whether the blocks of data are unique (meaning that no instances of the blocks of data are stored on the storage devices). If a block of data is unique, the single instance database stores it on a storage device. If not, the secondary storage computing device can avoid storing the block of data on the storage devices.
US09058114B2	Enabling throttling on average write throughput for solid state storage devices A mechanism is provided for enabling throttling on average write throughput instead of peak write throughput for solid-state storage devices. The mechanism assures an average write throughput within a range but allows excursions of high throughput with periods of low throughput offsetting against those of heavy usage. The mechanism periodically determines average throughput and determines whether average throughput exceeds a high throughput threshold for a certain amount of time without being offset by periods of low throughput.
US09058113B2	Storage region providing device, storage region providing method, and recording medium A storage region providing device provides a physical storage region (a physical region) as a virtual storage region (a logical region). The device accepts a writing request including data and information for specifying a partial logical region that is part of the logical region. In a case that part of the physical region is not allocated yet to a partial logical region specified by a writing request, the device allocates at least part of an initial allocation region of the physical allocation region to the partial logical region. The device moves data stored in the partial physical region included in the initial allocation region, to a movement destination region that is at least part of a reallocation region other than the initial allocation region of the physical region, and reallocates the movement destination region to the partial logical region.
US09058112B2	Retrieving data in a storage system using thin provisioning The invention relates to retrieving data from a storage system. One embodiment of the invention comprises receiving a write operation, establishing a correspondence relationship between a logic block address and a physical block address of the write operation, and determining whether a valid data percentage in a mapping table is greater than a predetermined threshold after the correspondence relationship is added in stored metadata. In response to the valid data percentage being less than the predetermined threshold, the embodiment adds the correspondence relationship to a B-tree data structure of stored metadata.
US09058109B2	System and method for identifying failing drives or media in media library Embodiments of methods and systems comprise identifying failing media and/or drives for a media library. Error data can be collected from media libraries. For each tape exhibiting an error rate of interest, a determination can be made whether the tape would still have been of interest had it not been loaded in certain drives. This information can be analyzed to identify failing drives or tapes.
US09058108B2	Vector-based matching circuit for data streams Systems and methods are described relating to a matcher that inputs partial vectors at a rate of 1 per clock cycle and delivers complete vectors at the output with an indication per vector of its validity. The matcher can copy a maximum number of valid elements from an input queue to target vector in-order each clock cycle and eliminate copied elements from the input queue. The completely filled target vectors are paired with the complete data vectors and outputted as composite vectors.
US09058107B2	Dynamic provisioning of a virtual storage appliance Systems, methods, and apparatus for facilitating dynamic provisioning of a virtual storage appliance in a cloud computing environment are presented herein. A storage system management component can provision storage from a storage medium to facilitate access of at least a portion of the storage by a virtual storage appliance (VSA) based on a request for at least one resource associated with the VSA. Further, a network management component can provision the VSA to facilitate the access of the portion of the storage by the VSA. Furthermore, a storage fabric management component can configure a network to facilitate the access of the portion of the storage by the VSA via the network.
US09058104B2	Gestures for special characters In one embodiment, a method includes displaying a keyboard on a touch-screen of a computing device; in response to a touch gesture within a display area of the touch-screen, the touch gesture comprising one or more paths that comprise two or more points on the touch-screen, determining a particular one of a plurality of characters corresponding to the touch gesture; and entering the particular one of the characters as user input to the computing device.
US09058102B2	Symbol input device, image forming apparatus including the symbol input device, and method for inputting symbols A symbol input device includes a plurality of symbol keys, a correction key, a time keeping portion for measuring a time for which the symbol key is pressed and held, a storage portion for storing data, and an input receiving portion which accepts input with the symbol key or the correction key, recognizes a time for which the symbol key is pressed and held based on the measurement by the time keeping portion, automatically accepts re-input of the symbol corresponding to the symbol key when the time for which the same symbol key is pressed and held exceeds a predetermined long press time, and increases the long press time every time when the number of correction times that is the number of times of which the correction key has been pressed reaches a predetermined first number of times after the automatic re-input.
US09058093B2	Active element A method for managing information elements on axes is provided, the method comprising providing a plurality of axes of information elements adapted to display information elements thereon in a substantially rectilinear fashion, displaying at least a portion of at least one of the plurality of axes of information elements with information elements respectively displayed thereon, at least some of the information elements displayed being adapted to be selectable, to enable a first group of actions thereon, and adapted to be activated, to enable a second group of actions thereon. Another embodiment of the present invention provides a method for enabling logical functions on a basis of a plurality of axes of information elements adapted to be displayed on a display. Another embodiment of the present invention provides a method for navigating among axes of information elements identifying directions where movements of the active information element are allowed.
US09058086B1	Implementation of electronic muscles in a portable computer as user input/output devices A portable computer system contained within a housing that comprises an electronic muscle material for performing a plurality of functions. The electronic muscle can be used to replace buttons or keys used in many PDAs. The movement of the electronic muscle material can charge the battery. When handled, the electronic muscle material can further detect the left- or right-handedness of the user and, based on the handedness, can generate function buttons or other alterations to accommodate the user's hand preference and finger placement. The electronic muscle can change shape to accommodate the user's hand for comfort and, further, as a security function to identify and authorize the user. Additionally, the electronic muscle material in the housing can be caused to vibrate at given frequencies so that it can generate an alarm and can function as a speaker or a dynamically directional microphone.
US09058082B2	Synchronous timed orthogonal measurement pattern for multi-touch sensing on a touchpad A method for detecting multiple objects on a touchpad having a grid of orthogonal electrodes, wherein all drive electrodes are simultaneously stimulated, and then frequency or electrode coding is used to separate each electrode junction and produce a capacitance image of the touchpad surface in a single measurement sequence.
US09058080B2	User input device failure prediction Detection of degradation of a user input device may allow for notifying a user of an impending failure of the user input device so that the device may be taken out of service or repaired. A method for detecting degradation of a user input device may carry out one or more operations including, but not necessarily limited to: determining that a portion of the user input device is degraded based on two or more received signals of the user input device, the two or more received signals being indicative of one or more user inputs; and providing a user notification indicative of a degradation of the user input device in response to determining that a portion of the user input device is degraded based on two or more received signals of the user input device.
US09058076B2	Touch panel The present invention provides a touch panel used in a display device. The touch panel of the present invention is configured to display images and to receive as well as to process instructions inputted by user's touches. A display substrate partially overlaps with an image driving circuit substrate of the touch panel. A touch sensing circuit is disposed on the inner side of the display substrate. A touch sensing processor is disposed on the inner side of a touch sensing circuit and is also electrically coupled to the touch sensing circuit. Consequently, the thickness of the touch panel as well as the overall thickness of the display device is reduced.
US09058074B2	Organic light emitting display Disclosed is an organic light emitting display an organic light emitting display that can efficiently prevent permeation of moisture in a structure including an in-cell touch electrode array, the uppermost layer of the second buffer layer contacting the sealant between the dead region adjacent to the touch pad portion and the touch pads is an inorganic film.
US09058068B2	Photodetector-based stylus system An electronic device is configured to determine a location of a stylus with respect to a display screen dependent upon first and second timing signals. A change in state of a reference pixel cell is detected using a photodetector located in close proximity to the reference pixel cell and a change in state of a pixel cell in proximity to the stylus, in response to a stylus photodetector signal received from a photodetector of the stylus. The location of the stylus with respect to the display screen is determined from the time difference between the change in state of the reference pixel cell and the change in state of the pixel cell in proximity to the stylus.
US09058062B2	System and method for accessing content Example systems and methods for facilitating access to stored content using a computer system comprising multiple non-alphanumeric buttons involve converting at least a portion of an identifier associated with the content to a code comprising a combination of one or more of the non-alphanumeric buttons. The code is stored along with access information for accessing the content and the access information is provided in response to receipt of the code.
US09058059B2	Gesture input device and method for controlling gesture input device A gesture input device that controls a control device on the basis of a gesture action of a user has a gesture detecting unit that detects a gesture from an image picked up by a camera, a first gesture determining unit that determines that the gesture detected by the gesture detecting unit includes a first gesture, a second gesture determining unit that determines that the gesture detected by the gesture detecting unit includes a second gesture, and a control signal generating unit that sets a period in which the first gesture determining unit determines that the gesture includes the first gesture as a second gesture valid period in which recognition of the second gesture is valid and generates a control signal on the basis of the second gesture when the second gesture determining unit determines that the gesture includes the second gesture in the second gesture valid period.
US09058056B2	System and method of dynamically generating a frequency pattern to realize the sense of touch in a computing device Systems and methods for providing tactile feedback. A method for providing tactile feedback, comprises extracting a plurality of features from a visual representation of a physical object, wherein the extracting is performed using at least one image processing technique, generating a variable frequency pattern corresponding to the extracted features, sending the variable frequency pattern to a computing device, and generating the tactile feedback via the computing device in response to a stimulation applied by a user, wherein the tactile feedback is based on the variable frequency pattern.
US09058055B2	Systems and methods for enhancing teleconferencing collaboration An advanced video teleconferencing system facilitates an engaging and realistic video conferencing experience. Key design elements and video, audio, and control capabilities are provided for a video conferencing experience that cannot be attained with conventional methods, which elements and capabilities include careful design of the table and room at each site, supplementary displays showing imagery in a mirrored manner, networked environmental control, an AutoDirector with keyword and gesture recognition, and audio reflection from a display or beam splitter.
US09058049B2	Modular low-power unit with analog synchronization loop usable with a low-dropout regulator A low-power-mode unit connected in parallel with a low-dropout regulator to provide a low-power mode includes a power P-MOS transistor, a differential amplifier, and an analog synchronization loop. The analog synchronization loop is configured to add a variable voltage offset depending on a total current at the output such that, in a high-power mode, the low-power unit current flowing through the P-MOS transistor is not zero, while being substantially smaller than the low-dropout regulator current flowing through the low-dropout regulator, and smaller than a predetermined value.
US09058048B2	Voltage regulator having error amplifier According to an embodiment, a voltage regulator having an output transistor, a voltage dividing circuit, an error amplifier, a detection circuit and a phase compensation capacitance circuit is provided. The output transistor has one end to which a power supply voltage is supplied, a control terminal to which a control signal is input, and the other end which outputs an output voltage. The voltage dividing circuit is connected between the other end of the output transistor and a first reference voltage. The error amplifier is configured to output the control signal according to the difference between a divided voltage and a second reference voltage. The detection circuit is configured to detect an operation environment. The phase compensation capacitance circuit is configured to adjust a phase compensation capacitance between the other end of the output transistor and an input terminal of the error amplifier, in accordance with the detected operation environment.
US09058044B2	Reference voltage generation circuit A reference voltage generation circuit includes an auto-activation unit, an operational amplifier unit, and a tail current resistor. An input of the operational amplifier is grounded via the tail current resistor. The auto-activation unit is coupled to the operational amplifier so that the circuit operates at an operating point. A reduction of current noises, circuit area, and overall cost occurs implemented through the described tail current unit
US09058038B2	Method and system for predicting vehicle battery health using a collaborative vehicle battery health model A method includes collecting vehicle health data from a plurality of vehicles. A peer group is identified among the plurality of vehicles. The collected vehicle health data from the peer group into a collaborative vehicle health model, the collaborative vehicle health model being applicable to a current vehicle to predict a state of at least a component of the current vehicle.
US09058034B2	Integrated circuit product yield optimization using the results of performance path testing Disclosed are embodiments of a method, system and computer program product for optimizing integrated circuit product yield by re-centering the manufacturing line and, optionally, adjusting wafer-level chip dispositioning rules based on the results of post-manufacture (e.g., wafer-level or module-level) performance path testing. In the embodiments, a correlation is made between in-line parameter measurements and performance measurements acquired during the post-manufacture performance path testing. Then, based on this correlation, the manufacturing line can be re-centered. Optionally, an additional correlation is made between performance measurements acquired during wafer-level performance testing and performance measurements acquired particularly during module-level performance path testing and, based on this additional correlation, adjustments can be made to the wafer-level chip dispositioning rules to further minimize yield loss.
US09058033B2	Computer system and method for controlling charging of a blast furnace by means of a user interface The invention relates to computer-implemented charging of a blast furnace equipped with an automated top-charging installation and stockhouse for batchwise charging. It proposes: obtaining a nominal charge dataset reflecting a nominal blast furnace charge and comprising plural charge material records, each charge material record comprising a material type and an associated nominal charge quantity; generating a graphical user interface comprising batch data fields for entering and displaying plural batch datasets for pre-configuring batches, each batch dataset comprising at least one batching record, each batching record comprising a material type and an associated batching proportion. According to the invention, the batching proportion associated to a material type in a batching record is used for predefining a ratio between the material quantity that is to be contained in a batch and the nominal charge quantity. Further according to the invention, the method comprises computing, for the respective material type of each batching record, based on the batching proportion and the nominal charge quantity associated to the respective material type, an associated batching quantity which the stockhouse is to provide in a batch as pre-configured by the batch dataset.
US09058028B2	Systems and methods for parameter dependent riccati equation approaches to adaptive control Systems and methods for adaptive control are disclosed. The systems and methods can control uncertain dynamic systems. The control system can comprise a controller that employs a parameter dependent Riccati equation. The controller can produce a response that causes the state of the system to remain bounded. The control system can control both minimum phase and non-minimum phase systems. The control system can augment an existing, non-adaptive control design without modifying the gains employed in that design. The control system can also avoid the use of high gains in both the observer design and the adaptive control law.
US09058024B2	User interface—oven timer A domestic appliance with timer control for the treatment of contents, the domestic appliance comprising a timer configured to track a treatment time period, a display configured to display a plurality of screens, at least one user input component programmed to receive a treatment time input corresponding to a treatment time and receive an expiration function input corresponding to an expiration function subsequent to receiving the treatment time input, and a controller programmed to set the timer with the treatment time in accordance with the received treatment time input and set the expiration function.
US09058021B2	Regulating member including a balance, a balance spring, a balance spring stud and stud holder and an assembly formed of a balance spring stud and a stud holder The balance spring stud holder has a housing in the form of a groove arranged to longitudinally receive and position the stud. The housing is at least partially laterally closed by an elastic strip which is arranged to return the stud against the bottom of the groove so that the stud can be locked, when the stud is inserted into the housing between the elastic strip and the bottom of the groove.
US09058019B2	Image forming apparatus The present invention prevents condensation on a pressure roller and excessive temperature rise of a non-paper-passage portion of a fixing unit by switching a blower unit that cools the fixing unit between a blowing mode in which the blower unit sends air to the non-paper-passage portion and an exhausting mode in which a fan of the blower unit is rotated reversely and the air in the fixing unit is exhausted out of the apparatus.
US09058013B2	Image forming device and cartridge configuration A developer cartridge according to one aspect of the invention is attachable to a photoconductor unit that comprises a photoconductive drum. The developer cartridge may comprise a developing frame defining a developer container configured to contain developer, the developing frame having a first side and a second side; a developing roller located at the first side of the developing frame so as to receive developer conveyed from the developer container in a first direction; a contact terminal located at the second side of the developing frame; and a memory electrically connected to the contact terminal, wherein the first side is downstream in the first direction from the second side.
US09058009B2	Method of designing drive unit A design method of a drive unit includes: deriving a minimum reference contact pressure Fa causing any of the shaft portion among the plurality of the shaft portions to result in damage; and designing the shaft portions or the gears to be of form such that the plurality of shaft portions and the plurality of gears satisfy the relationship F/D×L
US09058007B2	Torque transmitting member disposed at an end of a photosensitive drum, photosensitive drum unit, and process cartridge There is provided a torque transmitting member that appropriately maintains conductivity between an image forming apparatus body and a photosensitive drum and can suppress the occurrence of conduction failure. A torque transmitting member, which is disposed at an end portion of a photosensitive drum unit and transmits torque, includes: an cylindrical end member that includes a bearing portion at one end portion thereof and a fitting portion, which is inserted into a photosensitive drum, at the other end portion thereof; and a conductive conducting shaft member that is disposed so as to extend along a cylindrical shaft of the end member and includes a conductive material, which is elastically deformed, on at least a part thereof.
US09058006B2	Punching processing apparatus, sheet post-processing apparatus, and image forming apparatus A punching processing apparatus includes: a punching scrap collection member that is disposed at a position where punching scraps produced after punching a sheet drop; a punching scrap housing unit that is disposed in the punching scrap collection member and movable in a horizontal direction; a registration detection unit that is movable in a width direction of the sheet for detecting a positional deviation amount of the sheet in the width direction when a position of the sheet in the width direction is adjusted so as to meet a punching position, wherein punching scraps accumulated in the punching scrap housing unit are shaken and flattened out by causing the punching scrap housing unit to move in the horizontal direction in coordination with the movement of the registration detection unit.
US09058002B2	Image forming apparatus An image forming apparatus includes a belt unit detachable from a main body, a sensor unit, a blocking member, a moving mechanism, and a determination portion. The sensor unit includes a light emitting element configured to emit an outgoing light toward the belt, a first light receiving element configured to output a first signal, and a second light receiving element. The blocking member includes a first window and a second window. The moving mechanism is configured to move the blocking member between a first position in which the outgoing light passes the first window and a second position in which the outgoing light passes through the second window. The determination portion is configured to, when the blocking member is in the second position, determine whether the belt unit is attached to the main body based on the first signal output from the first light receiving element.
US09057997B2	Moving object detecting device, power supply control device, and image processing apparatus A moving object detecting device includes a detecting device body that includes a detection unit formed in a chassis covering the inside of an apparatus and disposed to correspond to a monitoring window of which at least an aperture area or an aperture size is restricted and which monitors a moving object approaching the apparatus and a circuit board unit controlling a signal output from the detection unit and is disposed so that some optical axes among optical axes having detection surfaces of plural infrared detecting elements included in the detection unit, as focal points passes through the monitoring window and the other optical axes are blocked by the chassis, and an optical member that is formed in an inner wall of the chassis and that deflects the other optical axes of the infrared detection elements to pass through the monitoring window.
US09057996B2	Image forming device and method for controlling a power supply for transfer An image forming device includes a power supply for transfer for applying a voltage for transfer for transferring the toner image on the image carrier onto the recording paper sheet to the transfer member, and a recording paper sheet feed device for feeding the recording paper sheet into the pressing nip, and the method for controlling a power supply for transfer. The power supply for transfer is turned on and the output voltage of the power supply for transfer is set to 0 V before the transfer member is pressed against the image carrier, and the output voltage of the power supply for transfer is switched from 0 V to a high voltage for transfer after the transfer member is pressed against the image carrier.
US09057992B2	Fixing device including fixing belt with holes A fixing device includes an endless fixing belt, a heating unit, a supporting member, and a pressure roller. The pressure roller sandwiches the fixing belt to form a fixing nip portion between the pressure roller and the fixing belt. The fixing device is configured to insert a recording medium into the fixing nip portion to fix an unfixed toner image carried on the recording medium. The fixing belt includes a heating layer and a sliding layer. The heating layer is configured to generate heat using the heating unit. The sliding layer is laminated onto an inner circumferential surface of the fixing belt and sliding on the supporting member. The plurality of holes are formed in the sliding layer such that the sliding layer has a mesh pattern in plan view.
US09057983B2	Developer container, developer replenishing device, developing device, and image forming apparatus using same A developer container removably installable in an apparatus body of an image forming apparatus includes a container body to contain developer, a cap connectable to the container body, the cap including a supply opening, and a flange projecting beyond an outer circumferential surface of the cap in a radial direction extending from a center of a cross section of the container body. The flange is formed along a circumference of the container body and provided between the container body and the cap.
US09057981B2	Developer container and developing device A developer container includes: a container body that has an opening at an upper part and is configured to accommodate therein developer; a conveyance member that is provided in the container body, and includes a rotation member having a rotary shaft and an elastic part, which is supported by the rotation member, is configured to be elastically deformed and is configured to rotate to convey the developer from the opening to an outside of the container body; and a driving member that is connected to one end portion of the rotary shaft and is configured to rotate the rotary shaft. The container body includes a first support part to which the other end portion of the rotary shaft is loosely fitted and a second support part that supports the one end portion of the rotary shaft.
US09057978B2	Enhanced color toner images using fluorescing magenta toners A composite color toner image can be enhanced in a printed receiver material by having a separate fluorescing magenta toner image applied over it to provide a “pinkish” fluorescing effect. This separate fluorescing magenta toner image is obtained using visible fluorescing dry magenta toner particles, each of which has a polymeric binder phase and a visible fluorescing colorant that emits at one or more peak wavelengths of from 510 nm and to and including 590 nm. The covering power of the fused visible fluorescing magenta toner particles in the enhanced composite color toner image is at least 350 cm2/g to and including 1100 cm2/g, and the covering power of each of the non-fluorescing cyan, non-fluorescing yellow, non-fluorescing magenta, and non-fluorescing black toner particles in the enhanced composite color toner image is at least 1500 cm2/g to and including 2300 cm2/g.
US09057977B2	Image forming apparatus and image forming method This invention is to provide a technique of always obtaining a stable output image in image formation using toner. A supplier (1217) supplies toner in a decided toner supply amount. A developing device (1206) agitates the supplied toner and supplies the agitated toner to an electrostatic latent image formed on a photosensitive drum (1203), thereby developing a toner image on the photosensitive drum (1203). A correction amount calculation unit (1106) estimates the toner charge amount by calculating a function model that approximates the variation characteristic of the toner charge amount using the toner consumption necessary for printing a print target image, the toner supply amount necessary for printing the print target image, and the toner agitation time. At least one of an image processing condition and a process condition is controlled using the estimated toner charge amount.
US09057972B2	Electrophotographic photoreceptor, process cartridge, and image forming apparatus An electrophotographic photoreceptor includes an electroconductive substrate, a photosensitive layer provided on the electroconductive substrate, and an outermost surface layer, wherein the outermost surface layer is a layer constituted with a cured product of a composition including at least one of non-charge transporting compounds represented by formulae (I) and (II), and at least one non-reactive charge transporting material:
US09057970B2	Method for producing core-shell structured resin microparticles and core-shell structured toner containing core-shell structured resin microparticles Provided is a method for producing core-shell structured resin particles, comprising the steps of: providing a dispersion liquid of hydrophobic resin particles in which the hydrophobic resin particles are dispersed into an aqueous medium containing an anionic surfactant A and an anionic surfactant B; providing a dispersion liquid of resin microparticles in which resin microparticles are dispersed into an aqueous medium; mixing the dispersion liquid of hydrophobic resin particles and the dispersion liquid of resin microparticles; adhering the resin microparticles to surfaces of the hydrophobic resin particles by adding a water soluble metal salt to a mixture resulting from above step, wherein the surfactant A and the surfactant B satisfy the specific conditions.
US09057969B2	Electrophotographic photosensitive member, process cartridge, and electrophotographic apparatus A photosensitive layer or a charge generation layer of an electrophotographic photosensitive member contains a gallium phthalocyanine and a particular diamine compound such as 1,2-diaminoethane or 1,3-diaminopropane. The content of the particular diamine compound in the photosensitive layer or the charge generation layer is from 10 ppm to 1,000 ppm (mass ratio) based on the gallium phthalocyanine.
US09057964B2	Imaging optics and projection exposure installation for microlithography with an imaging optics Imaging optics includes a first mirror in the imaging beam path after the object field, a last mirror in the imaging beam path before the image field, and a fourth to last mirror in the imaging beam path before the image field. In an unfolded imaging beam path between the object plane and the image plane, an impingement point of the chief ray on a used region of each of the plurality of mirrors has a mirror spacing from the image plane. The mirror spacing of the first mirror is greater than the mirror spacing of the last mirror. The mirror spacing of the fourth to last mirror is greater than the mirror spacing of the first mirror. Chief rays that emanate from points of the object field that are spaced apart from another have a mutually diverging beam course, giving a negative back focus of the entrance pupil.
US09057963B2	Illumination optical system, exposure apparatus, optical element and manufacturing method thereof, and device manufacturing method An illumination optical system which illuminates a surface to be illuminated on the basis of light from a light source has a first optical path in which a diffractive optical element can be arranged at a first position thereof; a second optical path in which a spatial light modulator with a plurality of optical elements arrayed two-dimensionally and controlled individually can be arranged at a second position thereof; and a third optical path which is an optical path of light having passed via at least one of the first optical path and the second optical path and in which a distribution forming optical system is arranged. The distribution forming optical system forms a predetermined light intensity distribution on an illumination pupil located in the third optical path, based on the light having passed via at least one of the first and second optical paths.
US09057959B2	Developer for photosensitive resist material and patterning process An aqueous solution containing 0.1-20 wt % of a substituted choline or thiocholine hydroxide is a useful developer for photosensitive resist materials. A resist pattern is formed by applying a chemically amplified positive resist composition onto a substrate to form a resist film, exposing the resist film to high-energy radiation, and developing the exposed resist film in an ammonium hydroxide-containing aqueous solution.
US09057957B2	Extreme ultraviolet (EUV) radiation pellicle formation method An extreme ultraviolet (EUV) photolithography pellicle with at least 70% transmissivity to EUV can be formed from a layer of semiconductor material applied to a substrate. The bottom surface of the layer can be exposed by forming support structure(s) from the substrate. Semiconductor material between the exposed surfaces can become the pellicle by anodizing until an objective is reached, such as a particular transmissivity, range of size of pores formed, pellicle region thickness, elapse of a period, and/or another objective indicative of 70% transmissivity to EUV for the semiconductor material between the exposed surfaces.
US09057956B2	Method and system for design of enhanced edge slope patterns for charged particle beam lithography A method and system for fracturing or mask data preparation are presented in which overlapping shots are generated to increase dosage in selected portions of a pattern, thus improving the fidelity and/or the critical dimension variation of the transferred pattern. In various embodiments, the improvements may affect the ends of paths or lines, or square or nearly-square patterns. Simulation is used to determine the pattern that will be produced on the surface.
US09057955B2	Functional film, liquid immersion member, method of manufacturing liquid immersion member, exposure apparatus, and device manufacturing method A functional film which is applied to a surface of a base material includes a film of Ti-doped tetrahedral amorphous carbon (ta-C:Ti film).
US09057952B2	Positive resist composition and method of pattern formation with the same A positive resist composition comprising: (A) a resin which comes to have an enhanced solubility in an alkaline developing solution by an action of an acid; (B) a compound which generates an acid upon irradiation with actinic rays or a radiation; (C) a fluorine-containing compound containing at least one group selected from the groups (x) to (z); and (F) a solvent, and a method of pattern formation with the composition: (x) an alkali-soluble group; (y) a group which decomposes by an action of an alkaline developing solution to enhance a solubility in an alkaline developing solution; and (z) a group which decomposes by an action of an acid.
US09057948B2	Resist composition for EUV or EB, and method of forming resist pattern A resist composition including a base component containing a polymer (A1) having a structural unit (a5) containing a group represented by general formula (a5-0-1) or (a5-0-2), wherein the amount of the monomer that derives the structural unit (a5) is not more than 100 ppm relative to (A1). In the formulas, each of Q1 and Q2 represents single bond or divalent linking group, R3, R4 and R5 represent organic groups, and R4 and R5 may be bonded to each other to form a ring in combination with the sulfur atom, provided that —R3—S+(R4)(R5) has a total of only one aromatic ring or has no aromatic rings, V− represents a counter anion, A− represents an organic group containing anion, and Mm+ represents an organic cation having a valency of m, wherein m represents an integer of 1 to 3, provided that Mm+ has only one aromatic ring or has no aromatic rings.
US09057943B2	Directional sound capturing This disclosure is directed to a sound recording arrangement comprising a sound recording arrangement and a method in the sound recording arrangement for amplifying sounds in a primary gaze direction of the user of the sound recording arrangement. The method comprises the actions of recording sounds arriving at a sound recording unit from objects in the field of view of the user, and recording a first set of images of the head and/or the eyes of the user, and determining a primary gaze direction of the user based on the first set of images, and amplifying sounds arriving in the primary gaze direction compared to sounds arriving from other directions.
US09057940B2	Light source module and projection apparatus for switching illumination between wavelength conversion element and reflection element A projection apparatus has a light source module including a light-emitting element, an optical path switching element, a wavelength conversion element, a first reflection element, and a first beam splitter element. The optical path switching element switches a first color beam between a first optical path and a second optical path. When the first color beam is switched to the first optical path, the first color beam is propagated to the wavelength conversion element to excite a first and second wavelength conversion layers on the wavelength conversion element to produce a second color beam and a third color beam. When the first color beam is switched to the second optical path, the first color beam is propagated to the first reflection element.
US09057936B2	Micromechanical projection device and method for manufacturing a micromechanical projection device A micromechanical projection device includes: a carrier which has a first, a second, and a third section, the second section being situated between the first and the third sections and having a flexible design; a mirror, which is mounted on the first section; and a light source which is mounted on the third section. The second section is bent in such a way that a light beam from the light source is directable onto the mirror.

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