| Document | Document Title |
|---|---|
| US09049278B2 |
Screen display processing apparatus and method
A screen display processing apparatus used for a portable terminal apparatus includes a moving unit configured to relatively move a plurality of cases of the portable terminal apparatus, a detection unit configured to detect a parameter value representing a degree of relative movement of the cases, a determination unit configured to determine based on the parameter value whether a shape of the portable terminal apparatus changes, and a first control unit configured to control a function about the screen display provided in the portable terminal apparatus in accordance with the parameter value and the change or no change in the shape. |
| US09049272B2 |
Presenting information in a conference
One conferencing system allows conference participants to share all or a portion of the display seen on their computer screens. The conferees may be at sites removed from each other, or may view a recorded presentation or archived conference at different times. Conference participants are either “presenters” who can modify the display or “attendees” who cannot modify the display. A pointer icon, which can be labeled to identify the conferee, is displayed on the shared image area. Each conferee can modify the position of his or her own pointer, even when not presenting, so that every participant can see what each conferee is pointing to, should a conferee choose to point to an element of the display. These and other features apply to other data streams shared in the conference or in meetings where there is no shared-image data stream. |
| US09049271B1 |
Switch-initiated congestion management method
A method for managing media communications. In one embodiment, the method comprises establishing a session to a computer over a network and through a switch; generating first and second frames of an image stream; identifying updated regions of the first and the second frames, wherein the updated region of the first frame has a first size and the updated region of the second frame has a second size different from the first size; compressing, based on a value from a congestion manager, the updated regions of the first and the second frames to generate a first and a second encoding, respectively; transmitting the first encoding over the session at a first rate determined from the first size and the value; and transmitting the second encoding over the session at a second rate determined from the second size and the value, wherein the second rate is different from the first rate. |
| US09049270B2 |
Device for selecting digital service streams, and method, computer program and storage means corresponding thereto
A device is positioned upstream of a modulator in a digital service stream broadcasting chain, and is adapted to receive a plurality of transport streams and to transmit a transport stream to a modulator, each transport stream encapsulating a digital service stream adapted to be broadcast by the modulator, the digital service streams representing the same digital service. The device is also adapted to: digital service streams from the received transport streams; detect errors in the streams; align the extracted streams; select a stream from the aligned streams, according to any errors detected; encapsulate the selected stream, in order to form the stream to be transmitted to the modulator. |
| US09049269B2 |
Method for grouping and transmitting multimedia data
A method for data communication is provided and may include storing multimedia data in a first database, the multimedia data being associated with enhanced metadata stored in the first database. The enhanced metadata may be created based on at least a user profile stored at a central management unit. Multimedia data may be selected from the first database based on at least the enhanced metadata, and the selected multimedia data may be modified to produce user-specific multimedia data. The user-specific multimedia data may be stored in a second database and may be communicated from the second database to a user terminal. An alarm to a user interface of the user terminal may be generated, if in producing the user-specific multimedia data from the profiled multimedia data, it was not possible to generate the user-specific multimedia data in conformance with the user specific hardware or network characteristics. |
| US09049267B2 |
System and method for processing information via networked computers including request handlers, process handlers, and task handlers
Systems and methods for processing information via networked computers leverage request handlers, process handlers, and task handlers to provide efficient distributed processing of processing jobs. A request handler can receive service requests for processing jobs, process handlers can identify tasks to be performed in connection with the processing jobs, and task handlers can perform the identified tasks, where the request handler, the process handlers, and the task handlers can be distributed across a plurality of networked computers. |
| US09049266B2 |
Network server layer providing disjoint channels in response to client-layer disjoint path requests
In one embodiment, a network server layer provides disjoint channels in response to client-layer disjoint path requests. For example, the network layer can be an optical network, and the client layer may be a packet switching layer (e.g., label switching, Internet Protocol). In one embodiment, a server-layer node receives a client-layer disjoint path request to provide a server-layer channel through a server-layer network. The client-layer disjoint path request includes an identifier corresponding to an existing client-layer path that traverses a current channel through the server-layer network that does not include the server-layer node. The server-layer network determines a particular channel through the server-layer network that is disjoint to the current channel based on route information of the current channel, and then signaling is performed within the server-layer network to establish the particular channel. |
| US09049264B2 |
Media start position based on inserting a start position indentifier
A device may generate an index for providing media files via a HTTP Live media stream. The index may include an ordered list of uniform resource identifiers for obtaining the media files. The device may determine a start position for content corresponding to the media files and may insert a start point identifier into the index. The start point identifier may identify one of the uniform resource identifiers included in the ordered list of uniform resource identifiers, for obtaining one of media files that corresponds to the start position for the content. The device may send the index to a client device. The device may receive a request the one of the media files and may provide the one of the media files to the client device via the HTTP Live media stream. |
| US09049263B2 |
Method and terminal for establishing PT session in order to use PT box
A PT (Push-To) service among SIP based session services, and particularly, a method and terminal for establishing a PT session in order to allow a certain user to use a PT box service under control of a PT server in a SIP (Session Initiation Protocol) based service, are discussed. According to an embodiment, the method of providing a Push-To (PT) box service, includes storing, in a PT server, PT box setting information of a terminal; receiving, by the PT server, a session invitation directed to the terminal; and determining, by the PT server, a routing of the session invitation to a PT box for the terminal based on at least the PT box setting information. |
| US09049262B2 |
Method and system for combined peer-to-peer (P2P) and central relay server-based telecommunication conferencing using a telephony and conferencing protocol
A method and system for combined Peer-to-Peer (P2P) conferencing and central relay server-based conferencing using a telephony and conferencing protocol that includes Web Real-Time Communication (WebRTC) or Session Initiation Protocol (SIP), including receiving by a central relay server a request from a client device to participate in a conference call, comparing by the central relay server a received client device policy and a central relay server policy for selecting at least one of the P2P conferencing or the central relay server-based conferencing, and selecting at least one suggested connection mode for the client device based on a result of the comparing of the received client device policy and the central relay server policy, the combined P2P conferencing and central relay server-based conferencing including mixing server-based conferencing streams and P2P conferencing streams. |
| US09049258B2 |
Systems and methods for anchoring content objects to structured documents
In one embodiment, a method includes, in connection with a target structured document rendered by a first client application and in response to a user input directed to target content of the target structured document, accessing, by a second client application, a document object model (DOM) representation of the target structured document, determining a target DOM node associated with the target content, recursively scanning one or more properties of each of one or more DOM nodes logically arranged proximal to the target DOM node within the DOM hierarchical tree, generating a set of one or more anchor point definitions based on one or more selected properties of each of the target DOM node and one or more selected ones of the scanned DOM nodes, and storing the set of anchor point definitions in a data structure. |
| US09049251B2 |
Method and apparatus for internet protocol based content router
An internet protocol (IP) content router, comprising a forwarding information base (FIB) engine comprising a data store comprising forwarding instructions, an IP packet classifier comprising a processor configured to classify a first incoming IP packet as an information centric networking (ICN) packet and a second incoming IP packet as a non-ICN packet, and an IP packet processor comprising a processor, wherein the IP packet processor is coupled to the FIB engine and to the IP packet classifier, wherein the IP packet processor is configured to intercept the ICN packet for further ICN processing in the IP content router, consult the FIB engine for forwarding instructions for the non-ICN packet, and forward the non-ICN packet according to the forwarding instructions. |
| US09049250B2 |
Providing relevant non-requested content to a mobile device
A system and method are directed towards providing non-requested content to a mobile terminal based on characteristics of, and tracked usage of the mobile terminal to request content through an online portal service, which provides access to content in multiple subject areas. A mobile user profile is created from the characteristics and patterns of the tracked usage. The tracked usage information includes the time, location, frequency at which the content was requested. Based on the mobile user profile information, content related to previously requested content is provided to the mobile terminal upon a trigger that is related to the requested content. The trigger event may include the mobile terminal returning to a location from which certain content was previously requested. The non-requested content may further be based on a related general user profile that indicates usage of an alternate electronic device to access content through the portal. |
| US09049248B2 |
Method and apparatus pertaining to energy efficient task execution offloading
A control circuit (such as a smartphone processor) having access to a wireless two-way transceiver (such as a short-range transceiver) determines a need to offload execution of a task to a server and then determines present unavailability of that server. This control circuit then transmits a first message to the server to prompt the server to awaken. The control circuit then transmits a second message to the server to establish a wireless connection that the control circuit employs to offload execution of the task to the server. By one approach, the aforementioned first message can include a unique identifier for the server. If desired, this unique identifier can have been provided earlier by the server via a general broadcast. |
| US09049244B2 |
Registering for internet-based proxy services
A domain name is received from a customer. DNS is queried for multiple possible subdomains of the domain. For each subdomain that resolves, information about that subdomain's corresponding resource record is stored in a zone file that also includes a resource record for the domain name. The zone file is presented to the customer. A designation from the customer of which of the resource records are to point to an IP address of a proxy server is received. The resource records are modified according to the input of the customer and the zone file is propagated including the modified resource records. |
| US09049243B2 |
System and method for allowing a user to opt for automatic or selectively sending of media
The present invention is directed to a system and method which allows for the seamless integration of the sending mechanism with the media acquiring mechanism of a portable device. In this manner the end-user has instant access to media sharing with complete control over how the media is shared. This integration is accomplished by presenting to the user a series of screens that are available directly from the media creation applications (e.g. cameras or audio recorders) and media viewing applications (e.g. photo galleries or screen savers) on the device. When a photo (or other media) is captured or viewed, a series of pre-established processing options, including on-device uses for the media, internet services and accounts, email addresses and/or phone numbers to which the media can be sent are presented to the user. Some options require no further user interaction. Defaults are also available which require no user interaction at all, combining together the manual selection of certain processing options or destinations with the automatic selection of other processing options or destinations. Thus, the sending process becomes essentially a selection process allowing the user to override defaults by either selecting from choices tailored to the user including already known address information of potential recipients or to allow the media to be automatically sent to a previously identified location according to the current “default” user preferences. In the situation where a new address or phone number is desired, the user can add such information in a simple and straight-forward manner. |
| US09049242B2 |
Atomic cache transactions in a distributed storage system
An atomic write descriptor associated with stripe buffer list metadata. |
| US09049241B2 |
Peer discovery and secure communication in failover schemes
A system discovers peer nodes in a failover system, establishes a secure channel between at least two of the peer nodes, and exchanges state information over the secure channel. |
| US09049240B2 |
Device and method for sharing files
The present invention concerns a method at a network device, the device comprising a first interface to a first network, a second interface to a second network, and routing means, for enabling access to a file shared by a first device located on the first network, the network device having detected the presence of the first device on the first network, the first device comprising at least one shared file. The method comprises the step, at the network device, of detecting that the first device is not accessible, on reception of a request from a second device located on the second network for getting a shared file on the first device, storing the request, on detection that the first device is accessible, retrieving the shared file in a memory of the network device, and sending a notification to the second device that the shared file is available at the network device or sending the file to the second device. |
| US09049234B2 |
HTTP trigger for out-of-protocol action
A hypertext transfer protocol (HTTP) request is used to actuate a secondary communications protocol (e.g., Short Message Service). A server receiving the request may be configured to take actions not specified by the URL associated with the request in response to the characters encoded in the request, such as accessing a secondary communications protocol. The server parses the request to identify action codes and/or content in the request itself, and takes action based on the code or content value. A token code representing a value or fixed number of uses may be utilized in connection with the techniques disclosed herein. |
| US09049232B2 |
Configurable-quality random data service
Methods and apparatus for a configurable-quality random data service are disclosed. A method includes implementing programmatic interfaces enabling a determination of respective characteristics of random data to be delivered to one or more clients of a random data service of a provider network. The method includes implementing security protocols for transmission of random data to the clients, including a protocol for transmission of random data to trusted clients at devices within the provider network. The method further includes obtaining, on behalf of a particular client and in accordance with the determined characteristics, random data from one or more servers of the provider network, and initiating a transmission of the random data directed to a destination associated with the particular client. |
| US09049231B2 |
Location based network usage policies
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for location based network usage policies. One of the methods includes storing information defining a plurality of network policy groups, receiving first information indicating that a client device is connected to the network at a first physical location, and identifying a first user role associated with the client device, identifying, from among the plurality of network policy groups, a first network policy group having both (i) an associated first policy location that corresponds to the client device's first physical location, and (ii) an associated policy role that corresponds to the client device's first user role, and regulating the client device's access to resources available on the network based on the one or more network usage policies associated with the identified first network policy group. |
| US09049230B2 |
Backup method and backup device for TCP connection
The present invention discloses a backup method and backup device. The backup method for the TCP connection provided by embodiments of the present invention includes: processing a first input packet, and generating, according to a processing result of the first input packet, a new transmission control protocol status and a new socket status; backing up the generated transmission control protocol status and the generated socket status to a transmission control module of the standby board; sending a second input packet to an application module; receiving a first output packet; processing the first output packet, and generating, according to a processing result of first output packet, a new transmission control protocol status and a new socket status; and backing up the transmission control protocol status and the socket status. The present invention further discloses a backup device for a TCP connection. |
| US09049227B2 |
System and method for adapting an internet and intranet filtering system
According to the present invention, there is provided a system and method for continuously interfacing with a plurality of computer based event monitoring systems such as Internet and Intranet filtering systems and or virus scanning software to determine whether these systems have detected a non-threatening and or security threatening event that corresponds with an event pre-determined and recorded within the events list which contains a plurality of non-threatening and security threatening events that may occur within a computer which in turn triggers a classified, targeted and value-adding hypertext message or information to be instantly displayed to the computer user through a browser or user interface instead of an event monitoring system default hypertext security message, and preferably an editing function shall be provided that enables the login of authorized authors including computer administrator/s to edit and publish targeted and value-adding hypertext messages and information, and preferably a measuring function shall be provided that enables the login of authorized authors including computer administrator/s to define and set up a plurality of metrics that may enable them to measure the effectiveness of the displayed targeted and value-adding hypertext messages and information in terms of being useful, entertaining, educational, interesting or instructional to a computer user through an alternate browser or user interface at the unique point in time when their computer has detected an event. |
| US09049221B1 |
Detecting suspicious web traffic from an enterprise network
Methods, apparatus and articles of manufacture for detecting suspicious web traffic are provided herein. A method includes generating a database comprising information corresponding to each of multiple connections between one or more destinations external to an enterprise network and one or more hosts within the enterprise network, wherein said multiple connections occur over a given period of time; processing multiple additional connections between one or more destinations external to the enterprise network and one or more hosts within the enterprise network with one or more filtering operations to produce one or more filtered connections, wherein said multiple additional connections occur subsequent to said given period of time; and analyzing said filtered connections against the database to identify a connection to a destination external to the enterprise network that is not included in the information in the database. |
| US09049216B2 |
Identifying related network traffic data for monitoring and analysis
Network traffic information from multiple sources, at multiple time scales, and at multiple levels of detail are integrated so that users may more easily identify relevant network information. The network monitoring system stores and manipulates low-level and higher-level network traffic data separately to enable efficient data collection and storage. Packet traffic data is collected, stored, and analyzed at multiple locations. The network monitoring locations communicate summary and aggregate data to central modules, which combine this data to provide an end-to-end description of network traffic at coarser time scales. The network monitoring system enables users to zoom in on high-level, coarse time scale network performance data to one or more lower levels of network performance data at finer time scales. When high-level network performance data of interest is selected, corresponding low-level network performance data is retrieved from the appropriate distributed network monitoring locations to provide additional detailed information. |
| US09049215B2 |
Dynamic network transport selection
A method for dynamic network transport selection is described. An indication from a user of a client device is received, to fetch over a data network media of a predefined type. One of a number of network transport physical layers in the client device is automatically assigned, based on a number of stored, ranked media types and network transport physical layer types, for use in fetching the media over the data network. Other embodiments are also described and claimed. |
| US09049208B2 |
Set top box architecture supporting mixed secure and unsecure media pathways
A media processing device, such as a set top box, having a plurality of selectable hardware and software components for supporting multiple media pathways providing differing levels of security. In general, each security level corresponds to a particular certification service boundary definition(s) or key/authentication and security management scheme for managing resources such as hardware acceleration blocks and software interfaces. Different sets of components may be adaptively employed to ensure composited compliance with one or more security constraints and to address component unavailability. Security constraints may be applied, for example, on a source or media specific basis, and different versions of a media item may be provided over multiple pathways providing corresponding levels of security. In one embodiment, a service operator or content provider may provide requisite certification or security requirements, or otherwise assist in selection of pathway components. |
| US09049198B2 |
Methods and systems for distributing pull protocol requests via a relay server
Distributing pull protocol requests via a relay server and thereby reducing the number of outgoing packets used by a fragment pull protocol, including the steps of aggregating, by an assembling device, a plurality of fragment pull protocol requests into an aggregated message; transmitting the aggregated message to a relay server, whereby the relay server distributes the requests to at least two fractional-storage servers; and receiving, by the assembling device from the at least two fractional-storage servers, a plurality of fragments in response to the aggregated message. |
| US09049197B2 |
System and method for handling call recording failures for a contact center
A system and method for handling call recording failures for a contact center. A processor receives information on a first media controller currently assigned to a telephony call. The first media controller bridges a first media path between the first and second communication devices and records, into a storage device, media exchanged in the first media path during the telephony call. The processor detects failure of the first media controller during the telephony call, where the failure of the first media controller tears down the first media path. In response to detecting the failure, the processor bridges a second media path between the first and second communication devices until a second media controller is identified. In response to the second media controller being identified, the second media controller is signaled to bridge and record media exchanged during the telephony call. |
| US09049195B2 |
Cross-domain security for data vault
Cross-domain security for data vault is described. At least one database is accessible from a plurality of network domains, each network domain having a domain security level. The at least one database includes at least one partitioned data table that includes at least two partitions. Each partition has a security level. Each partition is configured to store data records. Access control security is operable to provide, to a selected network domain, access to a selected data record in the at least one database based on a domain security level of the selected network domain and a security level of a selected partition storing the selected data record. |
| US09049193B2 |
Method and system for distributing resource-availability information within a distrubited computer system
Methods and systems disclosed in the current application are directed to efficient distribution of resource-availability information with respect to individual computer systems within a distributed computer system in order to facilitate various types of computational tasks, including configuration and management tasks and facilities. Certain of these implementations are based on highly efficient, lockless, message-based information-distribution methods and subsystems that transmission of messages at a frequency computed from a computed level of resource availability. |
| US09049191B2 |
Biometric authentication system, communication terminal device, biometric authentication device, and biometric authentication method
Provided is a biometric authentication system capable of preventing spoofing attacks even if leakage of key information and a registration conversion template occurs. A communication terminal device (300) calculates secret key information k′ which is exclusive OR of key information k of the registration biological information and masked value c′ which is randomly selected from a predetermined error correction code group, and calculates verified information c′″ which is exclusive OR of sent information c″ and value c′. A biometric authentication device (500) calculates exclusive OR of authentication biological information, information k′, and registration conversion template w, as information c″, wherein the template w is exclusive OR of information x, information k, and authentication parameter c randomly selected from the code group; and performs biometric authentication on the basis of a degree of matching between information c′″ corresponding to information c″, and the parameter c. |
| US09049190B2 |
Secure information storage and delivery system and method
A system for secure information storage and delivery includes a vault repository that includes a secure vault associated with a user, wherein the secure vault is associated with a service level including at least one of a data type or a data size limit associated with the secure vault, the secure vault being adapted to receive and at least one data entry and securely store the at least one data entry if the at least one of a size or a type of the at least one data entry is consistent with the service level. A mobile vault server coupled to the vault repository creates a mobile vault on a mobile device based on the secure vault and is capable of authenticating the mobile device based on user authentication information. The mobile vault server includes a mobile device handler that communicates with the mobile device. A synchronization utility determines whether the at least one data entry on the secure vault is transferable to or storable on the mobile vault based on at least one of the size or the type of the at least one data entry and transfers the at least one data entry from the secure vault to a corresponding data entry on the mobile vault if the at least one data entry on the secure vault is determined to be transferable to or storable on the mobile vault. |
| US09049188B1 |
Hybrid device having a personal digital key and receiver-decoder circuit and methods of use
A hybrid device includes a personal digital key (PDK) and a receiver-decoder circuit (RDC). The PDK and RDC of the hybrid device are coupled for communication with each other. In one embodiment, the hybrid device also provides a physical interconnect for connecting to other devices to send and receive control signals and data, and receive power. The hybrid device operates in one of several modes including, PDK only, RDC only, or PDK and RDC. This allows a variety of system configurations for mixed operation including: PDK/RDC, RDC/RDC or PDK/PDK. The present invention also includes a number of system configurations for use of the hybrid device including: use of the hybrid device in a cell phone; simultaneous use of the PDK and the RDC functionality of hybrid device; use of multiple links of hybrid device to generate an authorization signal, use of multiple PDK links to the hybrid device to generate an authorization signal; and use of the hybrid device for authorization inheritance. |
| US09049187B2 |
Connectivity, adjacencies and adaptation functions
Example embodiments are directed to a method of publishing an element template from a first service provider to an administrative owner to determine an optimal end-to-end connectivity path from a source to a destination across at least one resource domain for data transport. The method includes determining, at the first service provider, adjacencies between a first resource domain of the first service provider and a second resource domain of a second service provider. The first service provider publishes to an administrative owner, an element template that identifies connectivity attributes, including adjacencies and adaptation capabilities of the first resource domain. The AO may develop a plurality of possible paths from a source end-point to a destination end-point to transmit data based on the element template from the first service provider and element templates from other service providers. The AO selects an optimal path from the plurality of possible paths. |
| US09049185B1 |
Authenticated hierarchical set operations and applications
Methods and apparatus are provided for authenticated hierarchical set operations. A third party server processes a query q (possibly from a client) on outsourced data sets S1, . . . , Sn on behalf of a source of the data. The query q comprises a hierarchical set operation. Authenticated Set Operation techniques for flat set operations can be iteratively applied for hierarchical set operations. In addition, bilinear accumulators are extended to provide an extractable accumulation scheme comprising a primary bilinear accumulator and a secondary bilinear accumulator. In addition, a query q is parsed as a tree and for each tree node, a Union/Intersection argument is provided that is related to one or more accumulation values associated with the corresponding tree node. The client receives an answer to the query and a verification proof comprising, for example, subset witnesses, completeness witnesses, and/or accumulation values, but not necessarily intermediate results associated with the internal tree nodes of the query q. |
| US09049182B2 |
Techniques for virtual representational state transfer (REST) interfaces
Techniques for virtual Representational State Transfer (REST) interfaces are provided. A proxy is interposed between a client and a REST service over a network. The proxy performs independent authentication of the client and provides credentials to the client and for the client to authenticate to the REST service using a REST service authentication mechanism. The proxy inspects requests and responses and translates the requests and responses into formats expected by the client and the REST service. Moreover, the proxy enforces policy and audits the requests and responses occurring between the client and the REST service over the network. |
| US09049177B2 |
User interface to facilitate exchanging files among processor-based devices
A first processor-based device (PBD), such as a personal computer functioning as a host and containing digital media files, may share a selected file with a second PBD. Media file-sharing may be facilitated by an automated technique including graphical user interfaces (GUIs). In one embodiment, when a device user wishes to transfer a file to another device, the user hovers the file over a particular desktop icon and drops it, causing it to be automatically transmitted to a corresponding destination. Optionally, in response to hovering, a software program automatically generates a GUI indicating potential destinations. The user then selects a destination, and the system automatically transfers the file to that destination. In another embodiment, media sharing can be initiated from a digital appliance, such as a digital picture frame, and a file can be sent to another PBD, such as another digital picture frame via an intermediary PBD. |
| US09049174B2 |
Maintaining sessions in a smart thin client server
A method for maintaining a session between a smart thin client and a smart thin client server is provided. The smart thin client server permits a user to create, manage, and deploy enterprise applications via the smart thin client but lacks the ability to save state information. The method includes detecting a log-off event for the session between the smart thin client and the smart thin client server; and saving, by the smart thin client server in a database accessible by the smart thin client server, state information for the session, in a record containing a user identification corresponding to a user of the smart thin client. |
| US09049170B2 |
Building filter through utilization of automated generation of regular expression
A system and method performed by a computing device connected to a network and having one or more processors and memory storing one or more programs for execution by the one or more processors. At least one packet is received over a network. The packet is analyzed to detect predetermined content. The predetermined content is selected if it is determined that the packet contains the predetermined content. Future transmission of any packet containing the predetermined content is prevented in response to selection of the predetermined content. |
| US09049163B2 |
Scalable message fidelity
Message content is scaled to support rich messaging. Devices and associated messaging systems can support various levels of content richness or fidelity. Message content scaling is employed to ensure sharing of content in as rich a manner as possible given limitations associated with various messaging systems, among other things. Messages can be scaled down or degraded, for instance where communicating devices do not support high fidelity content being transmitted. Alternatively, messages can be scaled up or enriched in cases, where low fidelity content is transmitted to a device supporting richer content, for example. |
| US09049157B1 |
Method and device for improving scalability of longest prefix match
A Ternary Content Addressable Memory (TCAM)-based Longest Prefix Match (LPM) lookup table including a TCAM holding a plurality of prefix entries for looking up results in an associated RAM, the associated RAM storing results corresponding to TCAM match indices; additional Random Access Memory (RAM) storing results from the associated RAM; and one entry in the TCAM representing at least two entries in the additional RAM from the associated RAM, whereby at least one entry in the TCAM is made available. |
| US09049153B2 |
Logical packet processing pipeline that retains state information to effectuate efficient processing of packets
Some embodiments provide a method of processing a packet through a logical switching element implemented by several managed switching elements. The method receives a packet for processing through a processing pipeline of the logical switching element. The method processes the packet through the processing pipeline. The method stores state information in the packet for indicating that the packet has been processed through the processing pipeline in order to prevent other managed switching elements from processing the packet through the processing pipeline. The method forwards the processed packet to a managed switching element of the several managed switching elements. |
| US09049152B2 |
Hotkey access to legacy application tasks
Methods, systems, and techniques for assigning hotkeys to legacy tasks as part of modernizing such tasks are provided. A user can assign a hotkey to an individual task so that the user can have instant access to a legacy or a non-legacy task without needing to navigate to “sub-” tasks of the legacy task. Hotkey access may be used with role-based modernization of legacy tasks to provide navigation to and from legacy tasks without starting and stopping sessions. Example embodiments provide a Role-Based Modernization System (“RBMS”), which uses these enhanced modernization techniques to provide role-based modernization of menu-based legacy applications. |
| US09049151B2 |
Low-power policy for port
Various example embodiments are disclosed. According to an example embodiment, a method may include determining, by a port processor, a buffer length based on an amount of data stored in a port controlled by the port processor, comparing the buffer length to a low-power buffer threshold, determining a link utilization based on a number of packets transmitted by the port, comparing the link utilization to a link utilization threshold, and placing the port into a low-power state based on the comparison of the buffer length to the low-power buffer threshold and the comparison of the link utilization to the link utilization threshold. |
| US09049149B2 |
Minimal data loss load balancing on link aggregation groups
An example embodiment includes a network element. The network element includes an ingress port, an ingress line card, a link aggregation group (LAG) including multiple egress ports, and a distributor. The ingress port receives multiple packets including flood traffic. The ingress line card separates the packets into buckets. The distributor is configured to allocate the buckets to the egress ports, transmit the buckets to the egress ports, and when a failed egress port is identified, reallocate the buckets from the failed egress port to at least one functional egress port while continuing to transmit the buckets to functional egress ports of the LAG. |
| US09049144B2 |
Method and node for employing network connections over a connectionless transport layer protocol
A method of establishing a network connection between two nodes of a communication network via a connectionless transport layer communication protocol is presented. In the method, a plurality of data packets is exchanged between a first node and a second node. Each of the data packets comprises a header and a payload formatted according to the connectionless protocol. The connectionless protocol payload of the data packets includes a separate header comprising a first port indicator for the first node and a second port indicator for the second node. The separate header of at least one of the data packets includes an indication to establish a connection between the first node and the second node. In response to the exchange of data packets, the first and second nodes establish the connection, wherein the first port indicator and the second port indicator are associated with the established connection between the nodes. |
| US09049143B2 |
Voice over IP (VoIP) network infrastructure components and method
A voice over Internet protocol communication system and method provides infrastructure components as intermediaries between networks, the components include multi-protocol session controllers and a multi-protocol signaling switch as well as a management system. The session controllers process calls and participate in the calls that flow through it. The session controllers process calls that are either at the edge of the network or at the core of the voice over Internet protocol network. The session controllers associate calls with one another in call peers for incoming calls as ingress call peers and for outgoing calls as egress call peers. A centralized database of call routing policies is provided to the session controllers. The session controllers provide cost management, topology hiding, and inter-working, or conversion, of calls from SIP networks to H.323 networks for both voice and video. |
| US09049139B2 |
Pervasive network diagnostics using HBAs
Specially configured host bus adaptors (HBAs) are located in the switches in the fabric or added to a management server. The HBAs are programmed to perform higher level protocol analysis, such as monitoring exchanges, LUNs, and VM/LUN/LBA ranges and developing SCSI statistics on the flows. The HBA can detect protocol exceptions. When located in the switches, mirroring of the desired frames is simplified as all routing is handled internally to the switch, with the HBA/switch combination providing data over the management Ethernet port to a management server. To maintain performance, preferably only the protocol relevant frames are mirrored to the HBAs. With the data provided from the HBAs, in conjunction with the normal diagnostic and statistics data available from the switch itself, the management server can correlate events end-to-end, correlate I/O error statistics collected from the fabric with server statistics, and correlate performance statistics collected from the fabric with server statistics. |
| US09049136B2 |
System and method for packet transmission along shortest-path to multiple destinations
A system, method and apparatus arranged for efficient usage of network resources. Embodiments include nodes linked together, and the links having differing costs, e.g., bandwidth, frequency, and/or monetary cost, or any combination of these. Embodiments may identify neighboring nodes as either next-hop-neighbors or non-next-hop-neighbors. Next-hop-neighbors lie on the shortest path to any node, while non-next-hop-neighbors are nodes linked directly to a node, but the link is more costly than an alternative multi-hop path to the same node. Accordingly, embodiments may suppress packets to the non-next-hop-neighbors. |
| US09049135B2 |
Network spares audit optimization and maintenance systems and methods
A network spares audit, optimization, and maintenance system and method, including: an application running on a processor of one of (1) a network management system of a network and (2) a logistics management tool external to the network and in communication with the network management system of the network, the application including: a mapping algorithm executed by the application and operable for mapping network elements of one or more networks to spares depots; and a probabilistic risk analysis algorithm executed by the application and operable for utilizing statistical analysis to determine how many and what types of spares are stocked at each spares depot based on inputted conditions; wherein operation and output of the application is dynamically updated based on network configuration information automatically received from the network management system of the network. |
| US09049134B2 |
Network condition predictions for multimedia streaming
Network condition prediction and multimedia streaming consumption prediction are provided. The prediction may be based on a device's prior location, behavior, and statistics thereof. By gathering location data from users anonymously and securely, a virtual location network with millions of nodes are provided. Each virtual location, at a given time, is stored with associated network metrics gathered from various devices in a database. The database may comprise a probabilistic model and a behavioral model tracking device metrics. |
| US09049133B2 |
Virtual private wire services using E-VPN
In one embodiment, one or more point-to-point (P2P) services are established between attachment circuits on provider edge (PE) devices in a computer network, and each of the one or more P2P services (e.g., Virtual Private Wire Service, VPWS) are associated with an Ethernet virtual private network (E-VPN) Ethernet Auto-Discovery (A-D) route, where links between the PE devices and customer edge (CE) devices are configured as Ethernet interfaces with Ethernet tagging. As such, the Ethernet A-D route may then be exchanged for each P2P service attachment circuit, and forwarding can be performed on the one or more P2P services without performing a media access control (MAC) address lookup and without performing MAC learning. |
| US09049128B1 |
Application identification
A method may include receiving a communication from a client device and identifying a port number, a protocol and a destination associated with the communication. The method may also include identifying a first application being executed by the first client device based on the port number, the protocol and the destination associated with the first communication. |
| US09049127B2 |
Methods and devices for providing service clustering in a trill network
The methods and devices discussed herein provide service clustering within a TRILL network without relying on an additional service insertion framework. A TRILL network can include one or more flow distribution RBridges for distributing flows to service nodes. Each flow distribution RBridge can have a virtual base identifier and one or more virtual cluster identifiers. An example method can include maintaining N service cluster load balancing structures and receiving a packet that is encapsulated with an inner header (source/destination addresses) and an outer header (ingress/egress RBridge identifiers). The method can include determining whether the egress RBridge identifier is a virtual cluster identifier, and if so, applying a hash function to a predetermined flow tuple and selecting a service node associated with the hash value from one of the N service cluster load balancing structures. The method can include forwarding the packet to the selected service node. |
| US09049125B2 |
General input/output architecture, protocol and related methods to implement flow control
An enhanced general input/output communication architecture, protocol and related methods are presented. |
| US09049124B2 |
Zero-latency network on chip (NoC)
Packet format configurability is extended for packets transported on physical links of an Intellectual Property (IP) core interconnect by using at least two independent parameters: one parameter governing data-width and one parameter governing latency penalty. The at least two independent parameters allow creation of transport protocol packets without additional latency insertion, which is useful for low-latency applications. The at least two independent parameters also allow creation of narrow packets with multi-cycle additional latency, which is useful for latency tolerant, area sensitive applications. |
| US09049122B2 |
Bandwidth probing messages
Techniques are provided for detecting network characteristics. At a first endpoint device configured to communicate with a second endpoint device in a network, a request is made to a relay server in a network for an address and port assignment on the relay server. The address and port assignment are obtained from the relay server, and a probing packet is sent at a first time instance to the relay server at an address and port corresponding to the address and port assignment. The first time instance is stored in a timestamp field of the probing packet. A response packet responsive to the probing packet is then received from the address and port on the relay server at a second time instance. The second time instance is stored in a timestamp field of the response packet. |
| US09049118B2 |
Probe election in failover configuration
A first sensor transmits one or more probes to a host device identified on a network, each probe used to obtain information regarding the host and the plurality of probes are prioritized according to probe type. A set of replies to the plurality of probes are received and it is determined that a first of the plurality of probes is the highest priority probe for which a reply from the host device was received. A second probe transmitted by a second sensor is identified as the highest priority probe for which a reply from the host device was received by the second sensor, where the first sensor is designated as a primary sensor and the second sensor is designated as a secondary sensor. Respective priorities of the probe types of the first and second probes are compared to determine whether to perform a probe handover to the second sensor. |
| US09049109B1 |
Method and apparatus for a client connection manager
A method and apparatus for a connection manager have been disclosed. By providing for persistent connections with clients, the connection manager allows for servers to communicate with clients, which would otherwise be inaccessible. |
| US09049104B2 |
Coordination of M2M device operation by M2M device managers in a LAN
Teachings herein include a first machine-to-machine (M2M) device manager in a local area network (LAN). The first manager receives operating information for a first M2M device managed by the first manager. This operating information may indicate, for example, the operating state (e.g., on or off) of the first device. Responsive to receiving this operating information, the first manager coordinates operation of a second M2M device that is managed by a second M2M device manager in the LAN. The first manager effectively does so by evaluating the received operating information according to a set of policy-based rules, generating control signaling according to that evaluation, and then sending the generated control signaling to the second manager. Because this control signaling is sent horizontally between different M2M device managers, rather than vertically to some centralized server, such operation coordination can occur across M2M devices that would not otherwise be inter-operable. |
| US09049100B2 |
Method and apparatus for providing interfacing between content delivery networks
A method and apparatus are described for forwarding content delivery network interconnection (CDNI) signaling. A CDNI router content delivery network (CDN) may establish CDNIs with upstream and downstream CDNs. The CDNI router CDN may receive a CDNI route advertisement message from at least one of the upstream and downstream CDNs. The CDNI router CDN may update at least one end-user-based CDNI routing table based on Internet protocol (IP) address blocks in the CDNI route advertisement message. The CDNI router CDN may transmit an updated CDNI route advertisement message to at least one of the upstream and downstream CDNs. At least one of the upstream and downstream CDNs may update at least one end-user-based CDNI routing table based on the end user IP address blocks in the updated CDNI route advertisement message. |
| US09049093B2 |
Coded pulse data transmission using a look-up table
Input data is encoded using a look-up table and then transmitted over a transmission medium as a series of pulses. The look-up table includes data elements. The length of each pulse is calibrated to correspond to one of the data elements in the look-up table. Upon receipt at another end of the transmission medium, the data is decoded using a look-up table. This decoding includes measuring the length of each received pulse to match the measured length to a corresponding one of data elements in the look-up table. |
| US09049090B2 |
Methods and systems for fine timing synchronization
A method for determining timing synchronization for demodulating a signal by a receiver, comprises the steps of: generating a channel response for the signal; transforming the signal into the time domain using an inverse fast fourier transform (“IFFT”); determining a signal power for the transformed signal as a function of the generated channel response; and calculating the timing synchronization by the receiver as a function of the determined signal power. |
| US09049086B2 |
Apparatus and method for performing automatic frequency control
Disclosed are a device and method for automatically controlling frequency. The automatic frequency control device includes a frequency error detection unit configured to obtain a frequency error detection value of a received carrier, a frequency error prediction unit configured to calculate a first frequency error prediction value on the basis of the frequency error detection value when the frequency error detection value satisfies a preset first criterion, and a frequency error compensation unit configured to calculate a second frequency error prediction value by correcting the first frequency error prediction value, and compensate for a frequency of the carrier on the basis of the second frequency error prediction value when a frequency change rate of the received carrier satisfies a preset second criterion. Therefore, overshoot and undershoot effects are minimized, and thus frequency control may be correctly performed. |
| US09049085B2 |
Method and a device for determining an extrinsic information
A device for detecting an estimated value for a symbol at a given time, which is supplied to a phase modulation and transmitted via a transmission channel with a time-variable phase, provides a unit for determining log weighting factors in a forward recursion, a unit for determining complex coefficients in a forward recursion, a unit for determining log weighting factors in a backward recursion, a unit for determining complex coefficients in a backward recursion, a unit for determining an extrinsic information, a unit for determining the phase factor with the maximal weighting factor in a forward recursion and a unit for determining the phase factor with the maximal weighting factor in a backward recursion. |
| US09049081B2 |
Receiver
According to one embodiment, a receiver, which is configured to receive a radio signal having a preamble including a synchronization pattern and a payload containing data, includes an antenna, a low noise amplifier, a down-conversion module, a variable gain amplifier, an auto gain controller, a synchronization acquisition module, and a demodulator. The antenna is configured to receive the radio signal. The low noise amplifier is configured to amplify an output from the antenna by applying a first variable gain. The down-conversion module is configured to down-convert an output from the low noise amplifier. The variable gain amplifier is configured to amplify an output from the down-conversion module by applying a second variable gain. The auto gain controller is configured to, in accordance with strength of the radio signal, firstly adjust the first variable gain, and after fixing the first variable gain, adjust the second variable gain. |
| US09049077B2 |
Host controller using reduced network resources to monitor hosts
A host controller generates and sends a request for first status information to a host. The host controller receives first status information from the host along with a unique identifier that is associated with the first status information. After a time period, the host controller generates and sends a new request for second status information to the host, the new request including the unique identifier. When second status information and the first status information are associated with the same unique identifier, the host controller receives a response from the host indicating that the second status information is the same as the first status information. |
| US09049076B1 |
Content selection with privacy features
Systems and methods for content selection with privacy features include determining that a period of time from when the cookie was last used to visit a webpage has exceeded a threshold value. Based on the determination, the topic may be removed from an interest category profile used to select content. |
| US09049068B1 |
Multipath continuous time linear equalizer with allpass filter
An equalizer includes a first module and a second module. The first module is configured to receive a differential input signal, perform low pass filtering on the differential input signal to generate a low pass differential input signal, and perform high pass filtering on the differential input signal to generate a high pass differential input signal. The second module is configured to receive the low pass differential input signal and the high pass differential input signal and generate a differential output signal based on a combination of the low pass differential input signal and the high pass differential input signal. |
| US09049067B2 |
Receiver interface
In an embodiment, a circuit may include an input node, an output node, an internal node, a compensation circuit, and an adjustable capacitance circuit. The compensation circuit may be configured to modify a return loss of a signal received at the input node. The compensation circuit may include a first inductive element, a second inductive element, and a capacitive element. The first inductive element may couple the input node and the output node. The second inductive element may couple the output node and the internal node. The capacitive element may couple the input node and the internal node. The adjustable capacitance circuit may be configured to adjustably modify the return loss of the signal received at the input node. The capacitance circuit may be coupled to the compensation circuit. |
| US09049064B2 |
Radio reception apparatus, radio transmission apparatus, and radio communication method
Where first and second reference signals for a first and second communication system, respectively, are transmitted, resources that affect a reception apparatus compatible only with the first communication system can be minimized, and the throughput can be prevented from being deteriorated. As resources for a reference signal CSI-RS for LTE-A, last half symbols in a time direction of a resource unit RB/Sub-frame defined in a frequency-time domain are used, and the CSI-RS is allocated in a position up to the last two symbols or in the last symbol, or the like, of a particular RB/Sub-frame and transmitted when a reference signal 4RS for LTE is transmitted to a reception apparatus in addition to transmitting CSI-RS for LTE-A. The reception apparatus receives CSI-RS allocated in the last half symbol of RB/Sub-frame based on CSI-RS allocation information, measures channel quality by using this CSI-RS, and transmits and reports feedback information. |
| US09049062B2 |
Communication apparatus and reception method
It is possible to provide a radio communication terminal device and a radio transmission method which can improve reception performance of a CQI and a reference signal. A phase table storage unit stores a phase table which correlates the amount of cyclic shift to complex coefficients {w1, w2} to be multiplied on the reference signal. A complex coefficient multiplication unit reads out a complex coefficient corresponding to the amount of cyclic shift indicated by resource allocation information, from the phase table storage unit and multiplies the read-out complex coefficient on the reference signal so as to change the phase relationship between the reference signals in a slot. |
| US09049061B2 |
CMOS device and method for manufacturing the same
This invention discloses a CMOS device, which includes: a first MOSFET; a second MOSFET different from the type of the first MOSFET; a first stressed layer covering the first MOSFET and having a first stress; and a second stressed layer covering the second MOSFET, wherein the second stressed layer is doped with ions, and thus has a second stress different from the first stress. This invention's CMOS device and method for manufacturing the same make use of a partitioned ion implantation method to realize a dual stress liner, without the need of removing the tensile stressed layer on the PMOS region or the compressive stressed layer on the NMOS region by photolithography/etching, thus simplifying the process and reducing the cost, and at the same time, preventing the stress in the liner on the NMOS region or PMOS region from the damage that might be caused by the thermal process of the deposition process. |
| US09049056B2 |
Communication terminal and communication system
A communication terminal may include a processing unit that includes information identifying another communication terminal as path information in data when the data is directly transmitted from its own communication terminal to the other communication terminal, and a transmitting unit that directly transmits the data in which the path information is included by the processing unit to the other communication terminal. |
| US09049053B2 |
Method of managing an object by means of a management gateway using a telecommunications network
The present invention relates to a method of managing an object (OBJ) through a management gateway (ONG) communicating with a system architecture present on a telecommunications network offering functionalities for registering objects and for routing messages. The method includes the registering (201) of the object with the system architecture by way of the management gateway, by using the registration functionality, and the control (203) of a parameter associated with the object through the management gateway, using the message routing functionality. The present invention also relates to a management gateway (ONG) corresponding to the management method. |
| US09049051B2 |
Techniques to access messaging services for branch offices
Techniques to access messaging services for branch offices are described. In one embodiment, for example, an apparatus may include a network interface for a packet-switched network, a private branch exchange for a circuit-switched network, and a gateway to couple to the network interface and the private branch exchange. The gateway may be operative to establish a packet-switched call connection with the network interface and a circuit-switched call connection with the private branch exchange. The gateway may further include a call router to route a call request over a circuit-switched network with the private branch exchange on behalf of a call terminal to access messaging services from a data center with a messaging server when the call terminal and the network interface are unavailable. Other embodiments are described and claimed. |
| US09049050B2 |
System and method for equalizing transmission delay in a network
A network device includes an antenna connected to an RF chip and a processor coupled to an Ethernet port, the RF chip, a program memory, a packet buffer memory, a pointer buffer memory, and a program memory. The program memory contains instruction that, when executed by the processor, cause a plurality of packets received by the antenna and the RF chip in a first order to be stored in the packet buffer memory in such order, cause a pointer associated with each one of the plurality of packets to be stored in the pointer buffer memory, cause the pointers stored in the pointer buffer memory to be placed in a second order in accordance with a timestamp that is included with each packet, cause the packets stored in the packet buffer memory to be passed along to the Ethernet port in accordance with the sorted pointer to each packet. |
| US09049049B2 |
Routing method in in-vehicle gateway device
A routing method and an in-vehicle gateway device having a plurality of interfaces for communication, automatic setting of routing function is enabled to perform, in consideration of characteristics of data which a connecting network handles. A network is classified to an information-system, a control-system and a safety-system, based on characteristics thereof, and which one of the systems includes a network connecting to the in-vehicle gateway device, is judged from equipments connecting to the network, or traffic of the network. Still more processing in data exchange among different classifications is set in advance. |
| US09049042B2 |
System for providing mobile VoIP
A system for providing handoff for a mobile devices comprising a mobile phone programmed to automatically handover between differing data bearers and to optimally detect those bearers in a roaming environment keeping power consumption to a minimum. Repeating means for these mobile devices to extend the range of coverage and the protocol for that coverage. |
| US09049038B2 |
Method of associating or re-associating devices in a control network
This invention relates to a method of associating or re-associating devices in a control network including control zones to respective zone controllers (ZCs) controlling the control zones. In a first step, an associating or re-associating timer (ZC_REASSC_TIMER) window is initialized at the (ZCs) defining the time during which said associating or re-associating of the devices takes place. In a second step, during the (ZC_REASSC_TIMER) window zone specific information (ZN_SPEC) message sage is transmitted, the (ZN_SPEC) message including information about the devices expected to be in the zones controlled by the (ZCs). In a third step, it is compared whether the zone specific information contained in the (ZN_SPEC) received by the devices includes device specific information that match with local device specific information associated to the devices. In case the comparing results in that a pre-defined matching criteria is fulfilled an association or re-association request message (RA_REQ) is sent from the devices to the zone controllers (ZCs) where the pre-defined matching criteria was met. The (RA_REQ) message including device description parameters and indicates a request from the devices to join the control zones controlled by said (ZCs). Finally, it is determined whether the association or re-association of the respective devices is to be confirmed by means of comparing, by the respective (ZCs) receiving the (RA_REQ) message, the device description parameters included in the (RA_REQ) message match with zone specific information included in the (ZN_SPEC). |
| US09049037B2 |
Method and system for monitoring and encoding signals in a local facility and communicating the signals between a local collection facility and a remote facility using an IP network
A system and method for collecting signals includes an IP network, a remote facility and a local collection facility in communication with the local collection facility through the IP network. The local collection facility receives channel signals, encoding the channel signals into respective IP signals, communicating the respective IP signals through an IP network to the remote facility. The remote facility controls an antenna switch at the local collection facility to communicate a first channel signal of the channel signals to a monitoring receiver circuit module. The local collection facility generates a monitoring signal at the monitoring receiver circuit module and communicates the monitoring signal through to a remote facility through the IP network. |
| US09049035B2 |
Method and device for reliable broadcast
The invention is embodied in a technique for broadcasting content data from a broadcaster (including a multicaster) to a plurality of clients. After a client receives content data from the broadcaster, a plurality of available proxy servers may be contacted for post-processing after the content data broadcast is determined. The client subsequently randomly selects one of the available proxy servers to contact for post-processing after the content data broadcast. The client may further randomly select a delay time within a contact interval for the selected proxy server, at which time the client contacts the selected proxy server at the delay time to initiate post-processing. |
| US09049033B2 |
Information mixer and system control for attention management
Systems and methods for controlling various aspects of ensemble experiences and system control for attention management are disclosed. In one embodiment, a method for providing attention management for a specific participant in an online ensemble event, may comprise: receiving live stream signals, including audio signals, from each of a plurality of participants; displaying a plurality of objects on the corresponding user device of each specific participant, each of the plurality of objects corresponding to one specific participant; providing options for each specific participant to manipulate sizes of each of the plurality of objects and volume from each of the plurality of participants; providing a customized participation layer/interface to a specific participant to manage how other participants perceive the expression from the specific participant; and providing options for each specific participant to initiate an interaction with any of the plurality of participants. |
| US09049032B2 |
Prioritizing digital streams during digital conferencing
Using switching technologies to duplicate packets of a digital stream (e.g., digital video stream) sent from one workstation to multiple recipient workstations, where the switching technologies enable the multiple streams sent from the switch to the recipient workstations to be generated from a single digital stream sent from the sending workstation to the switch. Data units, such as video data units, may be transmitted by using a switch to enable receipt of a stream of data units including a payload portion and an attribute portion from at least two conferencing participants. The switch is used to duplicate at least a subportion of the payload portion of a data unit within the stream of data units, and to enable access to the duplicated subportion of the data unit by two or more conferencing participants. |
| US09049028B2 |
Power supplying system, monitoring apparatus, monitoring method and computer program
A power supplying system is configured so that a power supply server for supplying power and a client for receiving power are connected through a bus line on which an information signal representing information and power exist superimposed on one another, and the information signal is exchanged between the power supply server and the client. To the bus line of the power supplying system, a monitoring apparatus to monitor at least one of the information signal and power information related to power is connected. The monitoring apparatus includes a receiving portion to detect an information signal existing on the bus line, and a display control portion to display at least one of the information signal and the power information exchanged between the power supply server and the client. |
| US09049027B2 |
Non-PKI digital signatures and information notary public in the cloud
A digital signature is applied to digital documents/information. In certain instances, juridically strong digital signatures are achieved. Cloud computing technologies may be used to aid in the production of the cryptographically secure, authenticated digital signatures. Digital signatures may be produced with a digital notarization. The techniques of generating a digital signature may not require the use of traditional public key infrastructure (PKI). |
| US09049026B2 |
Authenticator, authenticatee and authentication method
According to one embodiment, an authenticatee includes, a memory configured to store secret information XYmain, XYsub, and secret information XYmainE, XYsubE, a generation module configured to generate a random number A, a generation module configured to generate a random number D which is composed of at least a part of the generated random number A and a random number B which is received, a generation module configured to generate secret information XY based on the secret information XYmain, XYsub loaded from the memory, a calculating module configured to generate data C by executing a compression calculated operation with respect to at least a part of the random number D and the secret information XY, a generation module configured to generate data ν, and a bit-by-bit addition module configured to calculate an calculated result Z from the data ν and the data C. |
| US09049021B2 |
Method for determining the cofactor of an elliptic curve, corresponding electronic component and computer program product
A method and apparatus are proposed for cryptographic computations implemented in an electronic component. The method includes determining the cofactor of an elliptic curve E defined over a finite field Fq with q elements, the elliptic curve comprising a base point P having an order equal to n. The step of determining includes determining a value of floor((q+2ceil(b/2)+1+1)/n) when n>6√q, where the function ceil corresponds to the ceiling function, floor corresponds to the floor function, and b corresponds to the size q in number of bits of q. |
| US09049019B2 |
Network equipment and optional tether
A piece of data terminal equipment having an Ethernet connector having first and second pairs of contacts used to carry high frequency data communication signals. The piece of data terminal equipment to have at least one path coupled across at least one of the contacts of the first pair of contacts of the Ethernet connector and at least one of the contacts of the second pair of contacts of the Ethernet connector. The piece of data terminal equipment to draw different magnitudes of DC current through the at least one path. |
| US09049017B2 |
Efficient TCP ACK prioritization in wireless networks
An improved acknowledgement (ACK) prioritization scheme is disclosed that provides ACKs with a lower block error rate (BLER) (as opposed to data) over an air interface, provides a separate radio bearer for ACKs, and successively increases the priority of ACKs for each retransmission required. A lower BLER target for ACKs may be achieved by an increase in transmit (Tx) power, additional coding for the radio bearer, or the use of diversity or hybrid automatic repeat request (ARQ) schemes. After packets are identified as either data or an ACK, they are sent to separate Tx buffers over separate radio bearers. Because the ACKs are transmitted over separate bearers and Tx buffers as compared to the data, ACKs are never queued behind the data, and are effectively prioritized as compared to the data. When retransmissions are required for an ACK packet, the scheduling prioritization is increased successively for each ACK retransmission required. |
| US09049016B2 |
MAC and RLC architecture and procedures to enable reception from multiple transmission points
A method for use in a wireless transmit receive unit (WTRU) for two-stage reordering of received protocol data units (PDUs). The method comprising receiving PDUs from Node-Bs, wherein each of the received PDUs has a transmission sequence number (TSN), reordering the received PDUs from Node-Bs using the TSN in a MAC layer in different reordering queues, delivering the received PDUs from reordering queues to one logical channel in the RLC layer, reordering the received PDUs in the RLC layer based on a sequence number (SN), starting a timer when at least a RLC PDU is missing based on SN of the RLC PDU, and transmitting a status report indicating a missing RLC PDU based on SN of the RLC PDU if the timer expires, wherein transmission of the status report is delayed if a RLC PDU is missing based on SN of the RLC PDU and the timer is running. |
| US09049013B2 |
Trusted security zone containers for the protection and confidentiality of trusted service manager data
Embodiments relate generally to systems and methods for providing access to a trusted security zone container within a trusted security zone of a mobile device. An application may receive trusted service manager validation data from a trusted service manager. The application may also receive a trusted security zone master key, wherein the trusted security zone master key provides access to a plurality of trusted security zone containers within the trusted security zone. The application may hash the trusted service manager validation data with the trusted security zone master key. The application may generate the trusted security zone sub key based on hashing to access one or more containers. One or more signal may be transmitted to provision the set of one or more trusted security zone containers with the trusted security zone sub key. The application may provide the sub key to the trusted service manager to access a container. |
| US09049009B2 |
Data transmission system
A cipher key is generated by first information shared in secrete between a data transmitting unit 10 and a data receiving unit 20, second information derived from duplication control information of transmit data and third information which is time change information shared between the data transmitting unit and the data receiving unit to cipher data by a CPU 12 by using the above-mentioned cipher key to transmit, from the data transmitting unit 10 to the data receiving unit 20, transmit data in which the duplication control information and the time change information are added to the ciphered data. |
| US09049007B2 |
Low-power encryption apparatus and method
An encryption apparatus and method that provide a mobile fast block cipher algorithm that supports low-power encryption. The encryption apparatus includes a user interface unit, a key scheduler unit, an initial conversion unit, a round function processing unit, and a final conversion unit. The user interface unit receives plain text to be encrypted and a master key. The key scheduler unit generates a round key from the master key. The initial conversion unit generates initial round function values from the plain text. The round function processing unit repeatedly processes a round function using the round key and the initial round function values. The final conversion unit generates ciphertext from the resulting values of the round function processed in a final round by the round function processing unit. |
| US09049002B2 |
Node and method for uplink detection with an assigned uplink physical layer identity
Example embodiments presented herein are directed towards the elimination of physical layer identity ambiguities for uplink detection in a wireless network. Some of the example embodiments are directed towards a source network node, and corresponding methods therein, for assigning an unique uplink physical layer identity for a user equipment uplink transmission of a first user equipment being served by the source network node. The unique uplink physical layer identity is provided to ensure that at least one second user equipment, which may be in proximity to a non-serving cell associated with the uplink transmission, does not have a physical layer identity ambiguity with the first user equipment. Some of the example embodiments are also directed towards a target network node, and corresponding methods therein, for performing uplink detection of the first user equipment using the unique physical layer identity described above. |
| US09049001B2 |
Apparatus, system, and method for timing recovery
Described herein are an apparatus, system and method for timing recovery in processors by means of a simplified receiver architecture that consumes less power consumption, has lower bit error rate (BER), and higher jitter tolerance. The apparatus comprises a phase interpolator to generate a clock signal; a first integrator to integrate a first portion of a data signal over a duration of a phase of the clock signal; a first sampler to sample the first integrated portion by means of the clock signal; a first circuit to store a first edge sample of the data signal; a second sampler to sample the stored first edge sample by means of the clock signal; and a clock data recovery unit to update the phase interpolator based at least on the sampled first integrated portion and sampled stored first edge sample of the data signal. |
| US09048999B2 |
Unequalized clock data recovery for serial I/O receiver
A serial input/output method and receiver include an receiver portion to receive an analog differential serial input and sample the input to provide data and error signals, an equalization feedback loop responsive to the data and error signals to adjust the receiver portion, a phase feedback mechanism separate from the equalization feedback loop to provide a phase error, and a clock data recovery block coupled to receive the phase error to perform timing recovery for the receiver portion independent of the equalization feedback to adjust the sampling. |
| US09048998B2 |
Feedback signaling error detection and checking in MIMO wireless communication systems
A method of feedback in a wireless transmit receive unit includes providing a precoding matrix index (PMI), error checking the (PMI) to produce an error check (EC) bit, coding the PMI and the EC bit and transmitting the coded PMI and EC bit. |
| US09048997B2 |
Apparatus and method using matrix network coding
Provided are a communication apparatus and method using a matrix network coding scheme. The communication apparatus includes a reception unit to receive a corrupted packet including a plurality of corrupted words, and a controller to estimate a first decoded word corresponding to the corrupted words based on the corrupted words and a generator matrix. The controller generates a second decoded word corresponding to the corrupted words based on a codebook and the estimated first decoded word. The codebook is based on the generator matrix. The controller generates a message based on a plurality of second decoded words respectively corresponding to the plurality of corrupted words. |
| US09048995B2 |
Method and system for low latency radio frequency wave transmission
An approach is provided for low latency radio frequency wave transmission. A long haul transport network receives a first signal representing latency sensitive data, receives a second signal representing latency insensitive data, and combines the first signal and the second signal to output a combined radio frequency signal, wherein the latency sensitive data of the combined radio frequency signal are at a first level of error coding, and the latency insensitive data of the combined radio frequency signal are at a second level of error coding. |
| US09048989B2 |
Methods and apparatuses for transmitting downlink control signaling on wireless relay link
Using an allocated control channel resource in a relay transmission frame, with an identified starting point, in a semi-static allocation scheme is disclosed. The control signaling may be mapped to the allocated control channel resource using different mapping schemes. Also disclosed is decoding a control channel element from a relay transmission frame received via a wireless relay link. The control channel resource associated with the relay transmission frame may be allocated in a semi-static allocation scheme. A starting indicator may be extracted from the decoded control channel element. A part of control signaling may be extracted from the decoded control channel element using the extracted starting indicator. |
| US09048985B2 |
Transmission method, transmission device, reception method, and reception device
Provided is a precoding method for generating, from a plurality of baseband signals, a plurality of precoded signals to be transmitted over the same frequency bandwidth at the same time, including the steps of selecting a matrix F[i] from among N matrices, which define precoding performed on the plurality of baseband signals, while switching between the N matrices, i being an integer from 0 to N−1, and N being an integer at least two, generating a first precoded signal z1 and a second precoded signal z2, generating a first encoded block and a second encoded block using a predetermined error correction block encoding method, generating a baseband signal with M symbols from the first encoded block and a baseband signal with M symbols the second encoded block, and precoding a combination of the generated baseband signals to generate a precoded signal having M slots. |
| US09048984B2 |
Channel switching method, apparatus, and system
A channel switching method, apparatus, and system are disclosed. A mobile terminal sends a channel switching command to a first access point, so that the first access point parses the channel switching command and sends a parsed channel switching command to a second access point and the second access point performs channel switching according to the parsed channel switching command. The mobile terminal receives a feedback message from the first access point. When the feedback message indicates that channel switching preparation of the second access point is ready, the mobile terminal breaks a connection to the first access point and sets up a connection to the second access point to complete the channel switching. |
| US09048983B2 |
Device-empowered radio resource assignment
A system and method are provided for mitigating interference between wireless access points (APs). A user equipment (UE) device uses a first set of radio resources to wirelessly communicate with a first AP and a second set of radio resources to wirelessly communicate with a second AP. The UE device then uses the first and second radio resources to communicate cooperation data between the first and second access points to mitigate interference thereinbetween. |
| US09048982B2 |
Method for distributed interference coordination in a femtocell environment
Distributed inter-cell interference coordination in a communications system can include: at one other femtocell system, sending channel quality information of a subordinate device communicating with the other femtocell system to the first femtocell system; receiving the channel quality information of the at least one other femtocell system at the first femtocell system; estimating an influence of a use of a resource on the communications system at the first femtocell system according to the channel quality information received by one or more of the at least one other femtocell system; and determining at the first femtocell system whether to use the resource. |
| US09048980B2 |
RF carrier synchronization and phase alignment methods and systems
A method comprising generating a baseband information signal by mixing a received modulated carrier signal with a local oscillator (LO) signal having an LO frequency; obtaining baseband signal samples of the baseband information signal having a baseband signal magnitude and a baseband signal phase; determining a cumulative phase measurement associated with baseband signal samples having a baseband signal magnitude greater than a threshold; and, applying a correction signal to compensate for an LO frequency offset of the LO frequency based on the cumulative phase. |
| US09048973B2 |
Base station device
A base station device performs switching of its transmission power distribution in accordance with a transmission power distribution switching timing of another base station device. The base station device includes a control unit 22 that controls transmission power distribution in the frequency domain, and a detection unit 23 that detects a switching timing at which another base station device switches transmission power distribution. The control unit 22 changes its transmission power distribution at a power distribution switching timing in the another base station device or a timing near the switching timing. Accordingly, inter-cell interference is prevented. |
| US09048971B1 |
Optical communication method and system
A first optical data signal is transmitted on a first data carrier from a first network element. First service information is transmitted from a first service by means of a first optical service signal on a first service carrier. A second optical data signal is transmitted on a second data carrier from a second network element, and second service information is transmitted by a second optical service signal on a second service carrier. An offset between a frequency of the first data carrier and a frequency of the first service carrier is substantially equal to an offset between a frequency of the second data carrier and a frequency of the second service carrier. |
| US09048969B2 |
Mobile station-assisted interference mitigation
Devices and methods are provided for using a mobile station to mitigate interference between wireless access points. A mobile station communicates interference mitigation data corresponding to a first and second set of radio resources between a first and second wireless access point (AP). The interference mitigation data is processed by the first wireless AP to resolve conflicts in the claiming, and subsequent assignment, of the first and second radio resource assignments to the mobile station. |
| US09048967B2 |
Asymmetric OTN network traffic support
A method of network communications includes determining an access identifier (AID) for an egress signal through a network interface of a network element, an Optical Transport Network (OTN) multiplexing structure identifier (MSI) associated with the egress signal through the network interface, another AID associated with a defined ingress signal through the network interface, another OTN MSI associated with the defined ingress signal through the network interface, and associating the egress signal and the defined ingress signal based on the AIDs and OTN MSIs. The first OTN MSI is not equal to the second OTN MSI. |
| US09048965B2 |
Input-controllable dynamic cross-connect
A multiplexer capable of automatically and dynamically selecting a correct or the best input out of a pre-configurable set of alternative inputs, based on the current status of the alternative inputs. An input status-sensitive, dynamic, M-by-M digital cross-connect can be formed out of an arrangement of M (an integer) instances of such input-controllable dynamic M:1 multiplexers. An application is an SDH/SONET cross-connect system that is able to perform a protection-switch for any number, up to all, of its output paths, simultaneously, if necessary, thereby enabling a short and deterministic latency for individual-path-granular protection-switch process for cross-connects of unlimited capacity. Another application is an SDH/SONET path that can be dynamically shared, even at a single time-slot granularity, among multiple path sources. Such a multi-source-bus configuration of an SDH/SONET path enables allocating network resources dynamically based on the real-time capacity demand patterns, thereby maximizing the network throughput for bursty data traffic. |
| US09048963B1 |
Conveying information using an audio signal
During a communication technique, an electronic device receives an audio signal from a remote electronic device, such as another electronic device that is proximate to the electronic device. This audio signal may include information that specifies an identifier. The electronic device may analyze the audio signal to extract the identifier, and may provide the identifier to a pre-defined location via a network, such as a web page on the Internet. In response to providing the identifier, the electronic device receives the operation from the pre-defined location via the network. For example, the operation may include an instruction to open a document (such as a web page) on the network. |
| US09048959B2 |
Method and apparatus for a wireless optical link
Example method, apparatus, and system embodiments are disclosed to provide a high data throughput optical communication link. An example embodiment comprises: a high frequency optical receiver configured to receive signals modulated with high frequency data; an optical waveguide having a receiving portion and a transmitting portion juxtaposed with the receiver, configured to transfer signals incident on the receiving portion, to the transmitting portion, and to transmit the signals to the receiver; a guide portion configured to releasably engage another apparatus, for positioning the waveguide with respect to the other apparatus, to receive at the receiving portion of the waveguide, signals from the other apparatus, for delivery to the receiver; and a wireless power circuit configured to exchange wireless power with the other apparatus, to convert between electrical signals modulated with high frequency data and the optical signals modulated with high frequency data received by the waveguide. |
| US09048955B2 |
Tunable dispersion compensation device, optical reception apparatus, and method for controlling tunable dispersion compensation
A tunable dispersion compensation device includes a plurality of tunable dispersion compensators coupled in series, a controller configured to control an amount of chromatic dispersion to be set in each of the plurality of tunable dispersion compensators, and a table including a correspondence relationship between an amount of chromatic dispersion and a wavelength band, for each of the plurality of tunable dispersion compensators, wherein the controller decides an amount of chromatic dispersion to be set in each of the plurality of tunable dispersion compensators, based on a total amount of chromatic dispersion desired for the plurality of tunable dispersion compensators and the correspondence relationship included in the table so that a difference between bandwidths of a first tunable dispersion compensator having the widest wavelength band and a second tunable dispersion compensator having the narrowest wavelength band, among the plurality of tunable dispersion compensators, is within a given range. |
| US09048954B2 |
Optical interconnect using optical transmitter pre-distortion
In one embodiment, the invention provides an optical interconnect comprising a transmitter for generating and transmitting an optical signal, a receiver for receiving the optical signal from the transmitter and for converting the received optical signal to an electrical signal, and a pre-transmitter distort circuit for applying a pre-transmitter distort signal to the transmitter to adjust the shape of the optical signal generated by the transmitter. Distortions are introduced into the optical signal when the optical signal is generated, transmitted to the receiver, and converted to the electrical signal. As a result of the signal applied to the transmitter by the pre-transmitter distort circuit, the optical signal generated by the transmitter has distortions to compensate for the distortions introduced into the optical signal, wherein the electrical signal, into which the optical signal is converted, has a desired shape. |
| US09048953B2 |
Optical communication system, optical transmitter, and transponder
A technique for reducing a necessary bandwidth of an optical receiver in an optical OFDM communication system is disclosed. Optical OFDM signals of different spectra are alternately transmitted for each OFDM symbol time, and; after this light is transmitted via an optical fiber, the light undergoes photoelectric conversion by a delay interferometer having a delay time equal to one symbol time and a balanced direct detection receiver and is received. |
| US09048952B2 |
Communication cable apparatus including switch turned off in reverse connection state of communication cable apparatus
A switch is inserted and connected between a first portion and a second portion of an HPD line. The switch connects the first portion to the second portion when an HPD signal is outputted to the second portion. The switch cuts off the connection between the first portion and the second portion when the HPD signal is not outputted to the second portion. An AND gate generates a connection state detection signal that represents the connection state of an HDMI optical active cable, and outputs the connection state detection signal to a switch. |
| US09048948B2 |
Device for transmitting data between two railway vehicles using optical radio relay
The invention relates to a device (10) for transmitting data between two rail vehicles (12, 14). At each rail vehicle (12, 14) one data transmission unit (16 to 22, 80, 90, 92) is arranged, wherein between the data transmission units (16 to 22, 80, 90, 92) a data transmission link for transmitting data is formed. Data transmission via this data transmission link is carried out by means of an optical radio relay system. |
| US09048947B2 |
Optical receiver having an automatic fiber optic signal adjustment circuit
A fiber optic communication system includes a first fiber optic device configured to transmit a fiber optic signal. A second fiber optic device is in fiber optic communication with and configured to receive the fiber optic signal from the first fiber optic device. The second fiber optic device includes an adjustment circuit configured to automatically adjust the fiber optic signal if the fiber optic signal is transmitted outside of a predetermined signal strength range. |
| US09048946B1 |
Hybrid ranging using an out of band signal in optical networks
A method of ranging comprises broadcasting a discovery request to a plurality of optical network units and receiving a respective discovery response from one or more of the plurality of optical network units. Each respective discovery response is transmitted as an out-of-band signal. The method also comprises approximating a respective out-of-band round trip delay to each corresponding optical network unit based on the respective discovery response; dynamically adjusting a size of a respective quiet window for each optical network unit based on the approximated out-of-band round trip delay; determining when to start the quiet window for each corresponding optical network unit based on the respective approximated out-of-band round trip delay; receiving an in-band ranging signal from the corresponding optical network unit during the respective quiet window; and determining an in-band round trip delay estimate based on the in-band ranging signal received during the respective quiet window. |
| US09048944B2 |
System and method for reducing signal interference between Bluetooth and WLAN communications
Methods and systems are disclosed for reducing signal interference between Bluetooth (BT) and WLAN (e.g. WiFi) communications in an information handling system. The WLAN receiver has configurable front-end filter circuitry. Based upon information concerning the BT frequency region for current BT communications, the WLAN receiver can adjust or set its configurable front-end filter circuitry to filter out the BT communications. As the BT communications hop from frequency to frequency, the WLAN receiver can continue to adjust its configurable front-end filter circuitry accordingly. Example implementations for the configurable front-end filter circuitry include bandpass filters and selectable low pass and high pass filters. These filters are selected and/or tuned such that BT frequency regions are filtered from the WLAN input signal before further WLAN signal processing is conducted, thereby improving the performance of simultaneous BT and WLAN communications. |
| US09048942B2 |
Method and system for reducing interference and noise in speech signals
Interference in an audio signal is reduced by estimating a target signal using beam-forming in a direction of the signal source. A set of estimates of interference is determined by using a microphone array filtering matrix to block the target signal in the audio signal. A set of filters is optimized by minimizing an objective function measuring a mismatch between the set of estimates of interference and the estimate of the target signal. The minimizing uses a sparse regularization of coefficients of the set of filters. The set of estimates of interference are filtered using the set of filters after the optimizing. Then, the estimate of interference after the optimizing is subtracted from the target signal. |
| US09048941B2 |
Characteristic response extraction for non-linear transmit channels
Techniques for extracting the characteristic response of a non-linear channel are presented. In various implementations of the invention, a channel's characteristic response may be determined by identifying a first input sequence, determining the ones compliment of the first input sequence and then determining the response of the channel to these two input sequences. Subsequently, two input matrices and two response matrices may be generated based upon the two input sequences and their corresponding responses. Given these four matrices, a symmetrical response component may be determined by iteratively solving a system of equations formed from the columns of each matrix. Subsequently, given the symmetric component and these four matrices, an asymmetrical response component may be determined by again iteratively solving the system of equations for the columns of each matrix. |
| US09048940B2 |
Passive bypass for network extending
In one or more embodiments, a cellular signal is received and directed to a path bypassing active amplifier circuitry. This may be in response to the active amplifier circuitry being non-operational (e.g., in a fault state) or detecting that an RF environment does not necessitate amplification. Bypassing the active amplifier circuitry may enable transmission of a non-amplified cellular signal when active circuitry is in a fault state or while traveling through areas of strong cellular service (e.g., proximate a cell tower). |
| US09048939B2 |
Photonic cell control device and method for ultra-wideband (UWB)transmitters/receivers
The present disclosure relates to a cell organization and method for controlling ultra-wideband (UWB) transmitting/receiving devices, the aim of which is to improve spatial occupancy (number of transmitters/receivers operating per unit area) and spectral efficiency (number of transmitters/receivers operating in a certain frequency range) in a predetermined area. The control method is based on configuring the optimum parameters—transmission power, bandwidth among others—for each UWB transmitter/receiver present in each cell. The configuration is calculated by monitoring the spectral parameters of the UWB transmitters/receivers operating in the area under control using a series of UWB sensors. In a preferred embodiment of the disclosure the sensors can be interconnected using photonic technology. |
| US09048938B2 |
Chirp communications
A method for receiving chirp signals at a receiver device according to a protocol in which each chirp signal has a gradient known to the receiver device, the method comprising: receiving a chirp signal having a first gradient g; generating a reference chirp signal having a second gradient g′, wherein the second gradient g′ differs from the first gradient g by a fixed value v; multiplying the reference chirp signal and the received chirp signal so as to form a mixed chirp signal; and detecting the received chirp signal by correlating the mixed chirp signal with a fixed gradient correlating chirp signal. |
| US09048937B2 |
Method for operating a UWB device
The method for operating a UWB device having at least one transmitting antenna and/or at least one receiving antenna comprises the following steps: controlling the transmitting antenna (12) or the receiving antenna (12′) with a control pulse signal (13,13′) having a sequence of substantially sinusoidal pulses of alternating polarity and differing amplitudes and particularly having the waveform of a fifth-order Gaussian pulse signal, wherein the transmitting antenna (12) can be alternately supplied with current pulses of differing polarity and differing magnitude by switching on and off first electronic switch units (16) that are coupled to the transmitting antenna (12) and have resistances associated with the amplitudes of the pulses to be generated, wherein each first switch unit (16) has a specifiable, particularly equal, number of first switching transistors (18,19), each having substantially identical on-state resistance values (R), wherein the resistance of a first switch unit is adjusted either by using only one of the first switching transistors (18,19) or by using a plurality of first switching transistors (18,19) connected in parallel, and wherein the first switch units (16) are controlled sequentially according to a specifiable temporal schema and each for a control time interval of a predetermined length. |
| US09048936B2 |
Systems and methods for managing on-time of wireless receivers
Systems, methods, and devices for communicating in a wireless network are described herein. In an aspect, a method of transmitting a data unit includes generating a data unit. The data unit includes one or more short training field (STF) sequences. The method further includes encoding each of the STF sequences with a pseudo-random spreading code. The code is based on an addressee of the data unit. The method further includes transmitting, at a transmitter, the data unit over a wireless channel. In another aspect, a method of processing a data unit includes receiving, at a receiver, a data unit. The data unit includes one or more STF sequences. The method further includes determining whether the data unit comprises one or more differentially encoded symbols. The method further includes receiving one or more long training field (LTF) sequences when the data unit does not comprise one or more differentially encoded symbols. |
| US09048935B2 |
Joint synchronization and modulation scheme for energy-efficient communication
A system including a transmitter and a receiver that are loosely synchronized, the transmitter encodes signal waveforms having a start time, a width and a height that are determined based on a range of possible relative drifts of a receiver clock with respect to a transmitter clock and the receiver decodes the waveforms based on a sequence of tests, chosen to account for any uncertainty that may arise due to the lack of tight synchronization. |
| US09048934B1 |
Voltage mode driver with enhanced transmit hybrid circuit
A voltage mode transceiver having an input/output (I/O) node for coupling to a bidirectional signaling link is disclosed. The transceiver includes a transmit circuit having an output coupled to the node and a receive circuit. The transmit circuit includes a transmit digital-to-analog converter (DAC) circuit having a transmit impedance network and a hybrid impedance network. The transmit impedance network generates an analog transmit version of a digital data signal while the hybrid impedance network couples to the transmit impedance network to generate an analog mirror version of the digital data signal. The receive circuit has a first input coupled to the I/O node and a second input coupled to receive the analog mirror version of the digital data signal. |
| US09048933B2 |
Radio-frequency transceiving front-end apparatus using passive elements in wireless communication system
Disclosed is a radio-frequency front-end apparatus that can be used in wireless communication systems performing transmission/reception by using a single antenna. The radio-frequency transceiving front-end apparatus using passive elements in a wireless communication system includes: a transmitting unit's hybrid coupler configured to divide and output a transmission signal into two outputs having a phase difference of 90°; a first circulator configured to receive a first output of the hybrid coupler through a first terminal thereof and output the received first output through a second terminal thereof; a second circulator configured to receive a second output of the hybrid coupler through a first terminal thereof and output the received second output through a second terminal thereof; and an output unit's hybrid coupler configured to receive transmission signals from the second terminal of the first circulator and the second terminal of the second circulator, and combine and output the received signals. |
| US09048932B2 |
Method and apparatus for co-existence of an OFDMA transmitter with a synchronous frame-based transmitter
A method and apparatus reduces the likelihood of packet loss when an OFDMA transceiver and synchronous frame-based transceiver are operating on the same device. More specifically, a method protects reception of Bluetooth signals (such as reception of slave device signals) from co-existence interference caused by co-located OFDMA transceiver transmissions. The method receives a transmission-enable (TXE) signal indicating that the OFDMA transceiver is transmitting, determines an estimated transmission-enable (TXE′) signal indicating when the OFDMA transceiver is expected to be transmitting in the future, and sends the TXE′ signal to the Bluetooth transmitter to shut down Bluetooth transmissions when a transmission is expected to be sent from the OFDMA transceiver. |
| US09048931B2 |
Method and arrangement for feeder sharing in a telecommunication system
A filter arrangement comprises a first terminal that handles duplex radio antenna feeder signals for at least two transceiver modules, a second terminal that handles at least duplex signals for a first transceiver module, a third terminal that outputs a first multi carrier power amplifier system input signal, the input signal representing a transmit signal from the first transceiver module, and a fourth terminal that receives a multi carrier power amplifier system output signal. The output signal includes an amplified representation of the transmit signals from the two transceiver modules. The first and second terminals are connected via first a single filter, the second and third terminals are connected via a second single filter, and the fourth and first terminals are connected via a third single filter. |
| US09048930B2 |
Detection and estimation of narrowband interference by matrix multiplication
One or more processing units are programmed to select from among M tones in a frequency domain representation of a signal, a set of tones including at least a strongest tone (relative to background noise) and a tone adjacent thereto. From among M complex numbers in the frequency domain representation of the signal, a set of complex numbers are identified and denoted as a vector Z, corresponding to the selected set of tones. Vector Z is then multiplied with each of M columns of a matrix G which is predetermined to identify a sub-resolution maxima in Z. The M products that result from the vector multiplication of Z and G are used to determine and store in memory at least one or both of: (A) a flag indicating presence or absence of narrowband interference in the signal; and (B) an estimate of a frequency of the narrowband interference. |
| US09048929B2 |
Broadband radio frequency data communication system using twisted pair wiring
A system for distributing broadband signals via twisted pair wiring is disclosed. Various aspects of the system involve use of a broadband signal distribution interface device and/or a broadband line driver. In one aspect, a broadband signal distribution interface device includes a broadband signal interface configured to receive broadband radio frequency signals, and a plurality of broadband signal connections configured to distribute broadband radio frequency signals. The interface device also includes circuitry defining an upstream signal path and a downstream signal path and including a gain control circuit and a slope control circuit each positioned along the downstream signal path. The circuitry is configured to accommodate downstream transmission of the broadband signals onto twisted pair wiring. |
| US09048928B2 |
Expandable transceivers and receivers
Expandable transceivers and receivers support operation on multiple frequency bands and multiple carriers. In an exemplary design, an apparatus (e.g., a wireless device, an integrated circuit (IC) chip, or circuit module) includes a low noise amplifier (LNA) and interface circuit. The LNA resides on an IC chip and includes a first/on-chip output and a second/off-chip output. The interface circuit also resides on the IC chip, is coupled to the second output of the LNA, and provides an amplified RF signal outside of the IC chip. The apparatus may further include a buffer, load circuit, and downconverter circuit. The buffer resides on the IC chip, is coupled to the first output of the LNA, and receives a second amplified RF signal from outside of the IC chip. The load circuit is coupled to the first output of the LNA. The downconverter circuit is coupled to the load circuit. |
| US09048926B2 |
Multi-card mobile terminal and SIM card data dumping method thereof
The present disclosure discloses a multi-card mobile terminal and an SIM card data dumping method thereof An MCC and an MNC of a secondary SIM card is compared with data in a white list preset in the mobile terminal. If the secondary SIM card is to be locked, short message data is copied from the secondary SIM card, saved into a short message function module of the mobile terminal, labeled as being from the secondary SIM card and used by a primary SIM card. This helps a user to switch services from one operator to another without substantially affecting use of the mobile terminal, which represents conveniences for the user. |
| US09048925B2 |
Method and device for processing data and communication system comprising such device
A method and a device for processing data has data transmitted from a first network component to at least one second network component via at least two lines. According to the novel method the data to be conveyed via the at least two lines is distributed within at least one frame. |
| US09048921B2 |
Receiver for wireless communication system
One exemplary receiver for a wireless communication system includes signal processing components arranged to generate a receiver output according to a radio frequency (RF) signal. The signal processing components include amplifiers having a class-AB biased amplifier included therein. The signal processing components are disposed in a chip, and the class-AB biased amplifier is an amplifier which processes a signal corresponding to the RF signal before any other amplifier included in the chip. The class-AB biased amplifier has a first amplifier block, a bias circuit and a second amplifier block. The first amplifier block is arranged to receive an input at the input port and generating a first output. The bias circuit is arranged to bias the first amplifier block for a class-AB operation. The second amplifier block is arranged to generate an output at the output port according to the first output. |
| US09048919B2 |
Method and apparatus for an adaptive filter architecture
A system that incorporates teachings of the subject disclosure may include, for example, a method for identifying a spectral region in a radio frequency spectrum, determining a signal strength of the spectral region, determining a correlation factor by correlating the signal strength of the spectral region, identifying from the correlation factor interference in the spectral region, repeating a determination of the correlation factor and an identification of the interference until a desired confidence level has been achieved, and generating coefficient data to substantially suppress the interference in the channel responsive to achieving the desired confidence level. Other embodiments are disclosed. |
| US09048918B2 |
Antenna grouping and group-based enhancements for MIMO systems
Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the transmitter has at least three transmit antennas and includes a feedback decoding portion configured to recover at least one group-based channel quality indicator provided by a feedback signal from a receiver, wherein each group-based channel quality indicator corresponds to one of a set of transmission layer groupings. The transmitter also includes a modulator portion configured to generate at least one symbol stream and a mapping portion configured to multiplex each symbol stream to at least one transmission layer grouping. The transmitter further includes a pre-coder portion configured to couple the transmission layers to the transmit antennas for a transmission. The receiver includes a decoder portion which is configured to use decoded signals from at least one group to decode the other groups. |
| US09048917B1 |
Method and apparatus for estimating noise covariance in a wireless network
The present disclosure includes systems and techniques relating to processing received spatially diverse transmissions. In some implementations, an apparatus includes: circuitry configured to receive signals from separate communication inputs; circuitry configured to filter the signals to reduce noise, interference, or both; circuitry configured to estimate covariance of the separate communication inputs, including estimating a correlation between the separate communication inputs; and circuitry configured to apply the covariance estimation to the filtering circuitry to effect noise whitening and to force an underestimation of the correlation between the separate communication inputs as applied. |
| US09048916B2 |
Method for reducing channel length and corresponding filter and signal
A method and apparatus are provided for reducing a channel length. The method implements a channel-length reduction filter that takes into account a pulse response of the channel. The method includes the following steps: cutting the filter into at least one first and one second portion; optimizing said first portion of the filter according to a first criterion in order to output a first set of filtering coefficients; reducing the length of the channel by optimizing said second portion of the filter according to a second criterion different from the first one and based on the first set of filtering coefficients of said first portion of the filter in order to output a second set of filtering coefficients. |
| US09048915B2 |
Method and apparatus for splitting received signal
A method and apparatus for splitting signals received via a plurality of antennas. A signal split apparatus of the present disclosure includes a first antenna which receives a first input signal, a second antenna which receives a second input signal, a first phase shifter which shifts phase by applying a first modulation frequency to the first input signal, a second phase shifter which shifts phase by applying a second modulation frequency to the second input signal, a summer which sums the phase-shifted first and second input signals, and an analog-digital converter which converts the summed signal to a digital signal, wherein the first and second modulation frequencies are different from each other. The signal split apparatus and method of the present disclosure is capable of splitting signals efficiently. |
| US09048911B2 |
Alamouti encoding and decoding
The present invention relates to a refinement of the Alamouti encoding scheme. The Alamouti scheme provides transmitting in a first period, the symbols S1 and S2 and in the next period the symbols—S2* and S1*, wherein S1* is the complex conjugate of S1. The symbols carrying the same information are transmitted on different paths to a receiver. If a disturbance occurs during the first period, the receiver may recover the symbol from symbol S1* in the second time period and vice versa. If no disturbance occurs, the receiver may use both symbols to further improve the transmission quality. An interleaver is provided to increase the transmission distance between redundant symbols, thereby causing the spread delay to be set to a value larger than the maximum length of typical channel disturbance in the communication channel. |
| US09048910B2 |
Downlink 8 TX codebook sub-sampling for CSI feedback
This invention is codebook sub-sampling of the reporting of RI, CQI, W1 and W2. If CSI mode 1 is selected RI and W1 are jointly encoded using codebook sub-sampling in report 1. If CSI mode 2 is selected W1 and W2 are jointly encoded using codebook sub-sampling in report 2. |
| US09048909B2 |
Method for transmitting channel state information and device thereof
Disclosed in an embodiment of the present invention is a method for transmitting channel state information and device thereof. By applying the technical schemes of the embodiment of the present invention, in a LTE-A system using PUCCH reporting mode 1-1, in a situation where PMI feedback for 8 antenna ports is needed to be reported in a sub-frame and PUCCH capacity is limited, therefore codebook compression is required, a corresponding relationship definition of the pre-coding matrix indicator information or the pre-coding matrix indicator information pair and the codebook index or the codebook index pair after codebook compression is provided, thus realizing the feedback and receiving of channel state information between a base station and terminal equipment. |
| US09048905B2 |
Method and system for RF transmitting and receiving beamforming with location or GPS guidance
A method and system for radio frequency transmitting and receiving beamforming using both GPS guidance and wireless access points is disclosed. The method and system comprises providing a wireless networking device with a locating system; providing an access point, the access point broadcasting its location; calculating a relative vector from the device to the access point based upon the location; steering a transmitted beam with a sounding packet to the access point; calculating a channel condition by the access point; and sending a packet by the access point to the wireless networking device to establish a connection. |
| US09048903B2 |
Method and apparatus for measuring and reporting a rank and a precoding matrix for multiple-input multiple-output communication
A method and apparatus for measuring and reporting a rank and/or a precoding matrix for multiple-input multiple-output (MIMO) communication are disclosed. A metric indicating a channel condition is measured and a rank is selected based on the metric. The metric may be a signal-to-interference and noise ratio (SINR), throughput, a block error rate (BLER), system capacity, a sum rate, or the like. An SINR for each radio block group (RBG) for each rank is calculated. A data rate is calculated for each RBG based on the SINR for each rank. An overall rate for all RBGs is calculated for each rank. At least one rank is selected based on the overall rate. At least one precoding matrix may be selected jointly with or separately from the at least one rank. |
| US09048902B2 |
Transmission apparatus and method using pre-distortion
A transmission apparatus and method for transmitting data within a multi-carrier transmission system including two or more transmission apparatuses configured to transmit same data. To avoid destructive interferences the transmission apparatus includes a signal input configured to receive multi-carrier signals carrying data to be transmitted, a distortion unit configured to distort the multi-carrier signals by use of a distortion function including a phase parameter for differently modulating phase of the multi-carrier signals, the distortion function being different from distortion functions used by other transmission apparatuses, whose coverage areas overlap with the coverage area of the present transmission apparatus, by using a phase parameter different from the phase parameter used by the other transmission apparatuses, and a transmission unit configured to transmit the distorted multi-carrier signals as a transmission signal. |
| US09048901B2 |
Wireless interface within transmitter
A process transmitter is configured to measure a process variable of an industrial process. The process transmitter includes a process variable sensor which senses the process variable and responsively provides a process variable sensor output. Sensor circuitry is coupled to the process variable sensor. A housing to encloses the sensor circuitry and the output circuitry. The sensor circuitry electrical couples to the housing. The sensor circuitry wirelessly communicates with the output circuitry. |
| US09048900B2 |
All digital transmitter noise correction
An all digital model of nonlinear transmitter signal distortion in signals received at a receiver of a transmitter-receiver may be used to estimate distortion. The estimated distortion may then be cancelled from the received signals to improve signal quality of the received signal. The digital nonlinear model may be part of an estimator circuit that estimates nonlinear distortion terms by applying a formula or transformation to a digitized version of the signals transmitter at a transmitter of the transmitter-receiver. A mixer may be used to shift a frequency of the estimated nonlinear terms away from a transmitter frequency so that the nonlinear terms can later be subtracted from the incoming signal received at the receiver at a receiver frequency. Circuits and methods are provided. |
| US09048899B2 |
Transmission method, transmitter apparatus, reception method and receiver apparatus
Transmission quality is improved in an environment in which direct waves dominate in a transmission method for transmitting a plurality of modulated signals from a plurality of antennas at the same time. All data symbols used in data transmission of a modulated signal are precoded by hopping between precoding matrices so that the precoding matrix used to precode each data symbol and the precoding matrices used to precode data symbols that are adjacent to the data symbol in the frequency domain and the time domain all differ. A modulated signal with such data symbols arranged therein is transmitted. |
| US09048896B2 |
Apparatus for multi-user multi-antenna transmission based on double codebook and method for the same
Double codebook-based multi-user, a multi-antenna transmission apparatus and a transmission method are started. A transmission apparatus includes an effective channel information reception unit configured to receive an effective channel matrix for a transmission channel, a zero-forcing precoding unit configured to receive data streams and perform zero-forcing precoding to null inter-user interference based on the effective channel matrix, a beam forming unit configured to receive the data streams subjected to the zero-forcing precoding from the zero-forcing precoding unit and perform beam forming, and a multi-antenna array configured to transmit the data streams subjected to the beam forming by the beam forming unit to the multi-user. With the method and apparatus, it is possible to improve a transmission capacity and effectively process an interference between terminals in a multi-layer beam forming environment. |
| US09048895B2 |
Multi-user null data packet (MU-NDP) sounding within multiple user, multiple access, and/or MIMO wireless
Multi-user null data packet (MU-NDP) sounding within multiple user, multiple access, and/or MIMO wireless communications. Within communication systems including multiple wireless communication devices (e.g., one or more APs, STAs, etc.), channel sounding of the selected communication links between the various wireless communication devices is performed. A MU-NDP announcement frame is transmitted to and received by various wireless communication devices indicating which of those wireless communication devices (e.g., one, some, or all) are being sounded. Then, respective NDP sounding frames are transmitted via the communication links corresponding to those wireless communication devices (e.g., one, some, or all) are being sounded, and sounding feedback signals are subsequently sent back to the original transmitting wireless communication device. In some instances, after transmission of the MU-NDP announcement frame, a clear to send (CTS) is sent from at least one of the wireless communication devices thereby precipitating the transmission of the NDP sounding frames. |
| US09048894B2 |
Method and apparatus of beam training for MIMO operation
The disclosed invention provides an efficient method for beam training to enable spatial multiplexing MIMO operation and spatial combining in a wireless network. The invention discloses a simple and efficient beam-training algorithm and protocol for MIMO operation that operates in high SNR condition for reliable MIMO operation. In one novel aspect, the best MIMO beam combinations are determined after TX sector sweeping and RX sector sweeping. In addition, the selection criteria includes not only signal quality, but also considers mutual interference and leakage among multiple MIMO spatial streams to improve overall MIMO performance. |
| US09048891B2 |
Multi-tiered quantization of channel state information in multiple antenna systems
A multi-tiered CSI vector quantizer (VQ) is provided for time-correlated channels. The VQ operates by quantizing channel state information by reference to both the current channel state information and a prior channel state quantization. A system is also provided that uses multi-tiered CSI quantizers. Enhanced signaling between the transmitter and receivers is provided in order to facilitate the use of multi-tiered CSI quantizers. |
| US09048886B2 |
Signal transmitting method and base station device
The present invention provides a signal transmitting method and a base station device. The signal transmitting method is applied to a base station device including a time domain exchanging module and a baseband processing unit, where the time domain exchanging module is connected to the baseband processing unit. The method includes: receiving, by the time domain exchanging module, a first time domain signal transmitted by a user equipment through a radio frequency channel of a serving cell of the user equipment, and receiving a second time domain signal transmitted by the user equipment through a radio frequency channel of a coordinating cell of the user equipment; and transmitting the first time domain signal and the second time domain signal to the baseband processing unit, which is corresponding to the serving cell of the user equipment. Through the present invention, CoMP data exchange can be implemented in an LTE-A system. |
| US09048881B2 |
Method of time-synchronized data transmission in induction type power supply system
The present invention provides a method of time-synchronized data transmission in induction type power supply system, comprising timers and programs installed in a supplying-end module and a receiving-end module to predict the time for generating the trigger signal at the receiving-end end and perform steps for detecting signals to avoid omission. Under the condition of high power transmission, power output on the supplying-end coil is pre-reduced prior to the time expected for receiving trigger data, making the main carrier wave amplitude decrease in a short time period. In every process of data transmission, timers are mutually calibrated and synchronized again to transmit power without detecting and receiving in the period when no data are expected to be transmitted, thus preventing interference of power load noise and enabling the induction type power supply system to transmit data code stably. |
| US09048878B2 |
Semiconductor memory device
A CRC code is generated from an original data, a BCH code is generated with respect to the original data and the CRC code, and the original data, the CRC code, and the BCH code are recorded in pages selected from different planes of a plurality of memory chips. An RS code is generated from the original data across pages, a CRC code is generated with respect to the RS code, a BCH code is generated with respect to the RS code and the CRC code, and the RS code, the CRC code, the BCH code are recorded in a memory chip different from a memory chip including the original data. When reading data, error correction is performed on the original data by using the BCH code, and then CRC is calculated. If the number of errors is the number of errors that is correctable by erasure correction using the RS code, the original data is corrected by the erasure correction. If the number of errors exceeds an erasure correction capability of the RS code, normal error correction using the RS code is performed, and further error correction using the BCH code is performed. |
| US09048873B2 |
Systems and methods for multi-stage encoding of concatenated low density parity check codes
A data encoding system includes a data encoder circuit operable to encode each of a number of data sectors with a component matrix of a low density parity check code matrix and to yield an output codeword. The data encoder circuit includes a syndrome calculation circuit operable to calculate and combine syndromes for the data sectors. |
| US09048869B2 |
Transmission apparatus including encoder, reception apparatus including decoder, and associated methods
An encoder and decoder using LDPC-CC which avoid lowering the transmission efficiency of information while not deteriorating error correction performance, even at termination; and an encoding method of the same. A termination sequence length determining unit determines the sequence length of a termination sequence transmitted added to the end of an information sequence, according to the information length (information size) and encoding rate of the information sequence. A parity calculation unit carries out LDPC-CC coding on the information sequence and the known-information sequence necessary for generating a termination sequence of the determined termination sequence length, and calculates a parity sequence. |
| US09048868B2 |
LDPC decoding with on the fly error recovery
It is decided whether to adjust data associated with a decoder. In the event it is decided to adjust the data associated with the decoder, the data is adjusted to obtain adjusted data and decoding is performed on the adjusted data. In the event it is decided to not adjust the data associated with the decoder, decoding is performed on the data associated with the decoder. |
| US09048867B2 |
Shift register-based layered low density parity check decoder
An apparatus for layered low density parity check decoding includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to calculate perceived data values based on check node to variable node messages. The check node processor includes an intermediate message generator circuit operable to generate intermediate check node messages, a shift register based memory operable to store the intermediate check node messages, and at least one check node to variable node message generator circuit operable to generate the check node to variable node messages based on the intermediate check node messages from the shift register based memory. |
| US09048865B2 |
Conversion of a discrete time quantized signal into a continuous time, continuously variable signal
Provided are, among other things, systems, apparatuses, methods and techniques for converting a discrete-time quantized signal into a continuous-time, continuously variable signal. An exemplary converter preferably includes: (1) multiple oversampling converters, each processing a different frequency band, operated in parallel; (2) multirate (i.e., polyphase) delta-sigma modulators (preferably second-order or higher); (3) multi-bit quantizers; (4) multi-bit-to-variable-level signal converters, such as resistor ladder networks or current source networks; (5) adaptive nonlinear, bit-mapping to compensate for mismatches in the multi-bit-to-variable-level signal converters (e.g., by mimicking such mismatches and then shifting the resulting noise to a frequently range where it will be filtered out by a corresponding bandpass (reconstruction) filter); (6) multi-band (e.g., programmable noise-transfer-function response) bandpass delta-sigma modulators; and/or (7) a digital pre-distortion linearizer (DPL) for canceling noise and distortion introduced by an analog signal bandpass (reconstruction) filter bank. |
| US09048864B2 |
Digital to analog converter with current steering source for reduced glitch energy error
A digital to analog converter including a current steering source and a master replica bias network. The current steering source includes a data current source providing a source current to a source node, a switch circuit operative to steer the source current to a selected one of first and second control nodes based on a data bit, a buffer circuit that buffers the source current between the first control node and a first current output node or between the second control node and a second current output node, and an activation current source provides activation current to the buffer circuit via the first and second control nodes. The master replica bias network replicates biasing of the buffer circuit relative to a replica control node and drives the buffer circuit to maintain the first control node, the second control node and the replica control node at a common master control voltage. |
| US09048845B2 |
Semiconductor system
A semiconductor system includes a controller and a semiconductor device that may communicate signals with the controller through a single input/output pad. The semiconductor device includes a self power generation block that may generate a driving voltage in response to a first signal inputted from the controller through the single input/output pad, and generate a start-up signal when the driving voltage is over a set voltage, a state machine block that may detect a pulse width of a second signal inputted from the controller through the single input/output pad, in response to the start-up signal, and may generate commands and data in response to the pulse width, and a data output block that may convert the data into a third signal of a current level corresponding to the data and output the third signal to the controller through the single input/output pad, in response to the commands. |
| US09048842B2 |
Sensor element device for a capacitive proximity switch
A sensor element device for a capacitive proximity switch of an operating device, where the sensor element device has an upper side for contacting the underside of an operating panel of the operating device and a block-like illuminated display with a lighting direction towards the underside of the operating panel. The sensor element device is electrically conductive on its side or an upper side facing the operating panel, thereby forming a sensor element. The illuminated display is mounted on a component carrier by a voluminous, spatial-shape-variable, elastic and electrically conductive material, where this material layer provides the required variable distance and electrical connection from the upper side to the underside as electrical contacts. |
| US09048841B2 |
Driver circuit, driver apparatus, and image forming apparatus
A driver circuit drives a plurality of groups of light emitting elements. Each element includes an anode, a cathode connected to the ground, and a gate that controls electrical conduction between the anode and cathode. A first driver section simultaneously drives the anodes of the elements of the plurality of groups of elements. A second driver section simultaneously drives the gates of the elements in a corresponding group of the plurality of groups. The second driver section includes a series connection of a first switch element and a voltage level shifter. The series connection is connected between a power supply and the group of gates. The second driver section further includes a second switch element connected between the group of gates and the ground. |
| US09048838B2 |
Switching circuit
In an embodiment, a switching circuit includes input drain, source and gate nodes, a high voltage depletion mode transistor including a current path coupled in series with a current path of a low voltage enhancement mode transistor, and a current sense circuit for sensing the current flowing through a current sense path. |
| US09048836B2 |
Body bias switching for an RF switch
Embodiments of radio frequency (RF) switching circuitry are disclosed that include (at least) a first switch and a body switching network operably associated with the first switch. The first switch has a first control contact, a first switch contact and a first body contact. The body switching network includes a first switchable path and a second switchable path. The first switchable path is connected between the first body contact and the first control contact of the first switch. Additionally, the second switchable path is connected between the first body contact and the first switch contact. Accordingly, the first body contact is can be appropriately biased by the switchable paths without requiring a resistor network and thus there is less loading. This maintains the Q factor of the RF switching circuitry. |
| US09048832B2 |
Programmable logic device and semiconductor device
A programmable logic device includes a plurality of programmable logic elements (PLE) whose electrical connection is controlled by first configuration data. Each of The PLEs includes an LUT in which a relationship between a logic level of an input signal and a logic level of an output signal is determined by second configuration data, an FF to which the output signal of the LUT is input, and an MUX. The MUX includes at least two switches each including first and second transistor. A signal including third configuration data is input to a gate of the second transistor through the first transistor. The output signal of the LUT or an output signal of the FF is input to one of a source and a drain of the second transistor. |
| US09048831B2 |
Systems and methods for regulating semiconductor devices
A system for regulating semiconductor devices may include a current regulator configured to regulate one or more currents provided to an insulated gate bipolar transistor (IGBT). The current regulator may regulate the currents by generating a current profile based at least in part on a collector voltage value associated with the IGBT, a rate of collector voltage change value associated with the IGBT, or any combination thereof. The current profile may include one or more current values to be provided to a gate of the IGBT such that the current values are configured to limit the rate of collector voltage change to a first value. The current regulator may then send the one or more current values to a current source configured to supply the gate of the IGBT with one or more currents that correspond to the one or more current values. |
| US09048830B2 |
Circuits for soft logical functions
A circuit implementing a soft logical processing network includes an interconnection of analog processing elements, which can include soft logic gates, for instance soft Equals gates and soft XOR gates. In some examples, each of the soft logic gates include multiple circuit parts, with each part including an input configured to accept a voltage signal representation of a soft logical quantity, and a conversion section configured to use the accepted voltage representation to form a corresponding current signal. The current signals are combined to form a signal representation of the output of the gate. In an application of soft logic gates, a memory includes a group of electrical storage elements, each electrical storage elements carrying a respective storage values; a group of conversion elements, each conversion element being coupled to a respective electrical storage element for selectively converting the corresponding storage value to a current signal; and a current combination element for combining the current signals to form an output signal. |
| US09048829B2 |
Power semiconductor device driving circuit
A power semiconductor device driving circuit includes a gate control terminal, which is provided at a position separated from a drain terminal of a power semiconductor device by a predetermined distance so that electric discharge is generated between the drain terminal and the gate control terminal at the time of generation of surge. A surge voltage is applied to the gate control terminal due to this discharge, the gate of the power semiconductor device is charged to turn on and absorb the surge energy. Thus it becomes possible to suppress the surge voltage applied to the drain terminal and prevent breakdown of the power semiconductor device. |
| US09048823B2 |
Duty cycle distortion correction circuitry
Integrated circuits with clock generation and distribution circuitry are provided. Integrated circuits may include phase-locked loops configured to generate multiple clock signals that are delayed versions of one another. The clocks signal may be distributed to various regions on an integrated circuit using serially connected clock buffer blocks. Each buffer block may include bidirectional pairs of buffer circuits coupled in parallel. Each buffer circuit may have a first input configured to receive an input clock signal, an output at which a corrected version of the input clock signal is provided (e.g., an output at which an output clock signal with desired duty cycle is provided), a second input that receives a first delayed clock signal for setting the desired duty cycle for the output clock signal, and a third input that receives a second delayed clock signal that is high at least when the first delayed clock signal rises high. |
| US09048822B2 |
Single ended ring oscillator with fully differential signal
A single-ended ring oscillation device for generating a fully differential signal is provided. The single-ended oscillation device includes a single-ended ring oscillator and a phase processing unit. The single-ended ring oscillator includes an odd number of inverting delay units. The inverting delay units sequentially generate a first signal, a second signal and a third signal. The phase processing unit generates an intermediate signal according to the first signal and the third signal, and outputs the intermediate signal and a delayed version of the second signal as a fully differential signal. The intermediate signal and the second signal are opposite to each other in phase. |
| US09048821B2 |
Low power relaxation oscillator
A relaxation oscillator circuit includes a comparator including a first input, a second input, a bias input, and an output. The first input is coupled to a charging node, and the second input is configured to receive a reference voltage. The relaxation oscillator circuit further includes a first bias circuit configured to provide a bias signal to the bias input of the first comparator when a first node voltage on the charging node exceeds a first reference. |
| US09048819B2 |
Method and apparatus for detecting RF field strength
A method and apparatus for detecting RF field strength. A field strength reference generator develops a field strength reference current as a function of a field strength of a received RF signal; and a field strength quantizer develops a digital field-strength value indicative of the field strength reference current. In one embodiment, detected field strength is used to dynamically vary the impedance of a tank circuit whereby, over time, induced current is maximized. In another embodiment, using the quantized field strength to sense changes to the environment to which the RFID tag is exposed. |
| US09048814B2 |
Resistance adjusting circuit and resistance adjusting method
A resistance adjusting circuit including, a reference resistor, a first power source configured to output a first voltage, a first current source configured to output a first current based on a reference current set by using the reference resistor, a first variable resistor, a second current source configured to output a second current obtained by multiplying the first current by a reciprocal ratio, the reciprocal ratio being obtained as a reciprocal number of a ratio of a target resistance of the first variable resistor to a resistance of the reference resistor, and a controller configured to set a resistance of the first variable resistor so that a voltage at a second terminal of the reference resistor and a voltage at a connecting part of the first variable resistor and the second current source become equal to each other. |
| US09048807B2 |
Surface acoustic wave resonator with an open circuit grating for high temperature environments
Surface acoustic wave resonators for use in high temperature applications including a piezoelectric substrate, at least one interdigital transducer supported by the piezoelectric substrate, and a grating reflector supported by the piezoelectric substrate, the grating reflector being fabricated of a heavy metal and comprising a plurality of electrodes, at least one electrode of the plurality of electrodes being electrically isolated from at least one other electrode. Methods of making surface acoustic wave resonators are also included. |
| US09048804B2 |
Device and a method for fixing a gain or attenuation factor
A device for fixing a gain or attenuation factor for a gain or attenuation element during a transmission of a sequence of synchronization-data symbols registers the signal level of a received signal at the input of the gain or attenuation element. It then identifies the start of transmission of the sequence of synchronization-data symbols on the basis of the signal level of the registered, received signal and signals the time interval for the fixing of the gain or attenuation factor starting with the identified start of transmission of the sequence of synchronization-data symbols. |
| US09048802B2 |
Radio frequency power amplifier with linearizing predistorter
A power amplifier circuit includes an amplifier MOSFET and a predistorter MOSFET. The predistorter MOSFET source and drain are connected together, and the predistorter MOSFET is connected between the gate of the amplifier MOSFET and a second bias voltage signal. This biasing of the predistorter MOSFET causes it to provide a nonlinear capacitance at the gate of the amplifier MOSFET. The combined non-linear capacitances of the amplifier MOSFET and predistorter MOSFET provide predistortion that promotes cancellation of the distortion or nonlinearity contributed by the amplifier MOSFET alone. |
| US09048801B2 |
Apparatus and methods for buffer linearization
Apparatus and methods for buffer linearization are provided. In certain implementations, an amplifier includes a buffer circuit and a gain circuit. The buffer circuit includes a buffer transistor pair used to buffer a differential input signal to generate a differential buffered signal. Additionally, the gain circuit includes a gain transistor pair configured to amplify the buffered differential signal to generate an amplified differential signal. The buffer circuit can include a linearization transistor pair configured to decrease the buffer circuit's output impedance and to provide feedback that reduces changes in the voltage of the differential buffered signal in response to displacement currents associated with the CJC or CGD capacitances of the gain transistor pair. |
| US09048795B2 |
Method for implementing compensation filter and apparatus for signal bandwidth compensation
An apparatus for signal bandwidth compensation is disclosed. The apparatus includes: a digital predistortion filtering unit, a compensation filter, a conversion unit, and a power amplifier; where the digital predistortion filtering unit receives an original signal, performs predistortion processing on the original signal; the compensation filter receives the predistortion signal, compensates for distortion caused during a process of transmitting the predistortion signal to the power amplifier, and outputs a compensated predistortion signal to the conversion unit; the conversion unit receives the compensated predistortion signal, converts the compensated predistortion signal into an analog signal, performs frequency mixing processing, and outputs a predistortion signal experiencing the frequency mixing to the power amplifier; the power amplifier receives the predistortion signal experiencing the frequency mixing, amplifies the predistortion signal experiencing the frequency mixing, and outputs an amplified signal. |
| US09048793B2 |
Systems and methods for operating a power amplifier
A power amplifier configured to receive an AC input signal and output, based on the AC input signal, an output voltage via a first output voltage terminal and a second output voltage terminal. The power amplifier includes a first transistor and a second transistor connected in a push-pull configuration, a first inductor, a second inductor, and a first capacitor. The first output voltage terminal is located between the first inductor and the first transistor. The second output voltage terminal is located between the second transistor and ground. The first capacitor is configured to provide a first circuit path between the first output voltage terminal and the second output voltage terminal. The first circuit path functions as a short circuit for even harmonics of a fundamental frequency of the AC input signal but does not function as a short circuit for the fundamental frequency of the AC input signal. |
| US09048792B2 |
Power amplifier and liquid jet printing apparatus
A power amplifier includes: a modulator pulse-modulating a drive waveform signal serving as a reference of a drive signal applied to an actuator and outputting a plurality of modulated signals; a digital power amplifier having a plurality of digital power amplifier stages each including a pair of push-pull switching elements, amplifying the power of the plurality of modulated signals, and outputting multi-value amplified digital signals; and a low pass filter smoothing the amplified digital signals and outputting the drive signal, wherein the modulator includes a control section switching one of a state where the same modulated signal is connected to two or more of the digital power amplifier stages and a state where different modulated signals are connected to different digital power amplifier stages to the other. |
| US09048791B2 |
Multi-stage amplifier with pulse width modulation (PWM) noise shaping
A pulse width modulation (PWM) amplifier includes a first amplifier stage, a second amplifier stage, and a gain module. The first amplifier stage is configured to amplify an analog input signal in the analog and digital domains using a first pulse width modulation (PWM) generator, to provide a first stage output for coupling to a load. The gain module is configured to amplify a quantization error of the first PWM generator by a predetermined gain. The second amplifier stage is configured to spectrally shape and attenuate the amplified quantization error of the first PWM generator using a second PWM generator, to provide a second stage output for coupling to the load. |
| US09048789B2 |
Current re-using wideband low-noise active balun
Some aspects of the present disclosure relate to a low-noise amplifier (LNA) having a balun configuration. The LNA includes a DC current path coupling a first DC supply node to a second DC supply node. First and second output nodes and first and second input nodes are spaced apart along a length of the DC current path. A single-ended radio frequency (RF) input terminal is configured to deliver a single-ended RF signal to the first and second input nodes. A differential RF output terminal is made up of the first and second output nodes. The first and second output nodes are configured to cooperatively establish a differential output signal based on the single-ended RF signal. Other devices and methods are also disclosed. |
| US09048785B2 |
Periodically resetting integration angle demodulation device and method using the same
A periodically resetting integration angle demodulation device and a method using the same is disclosed, which uses a waveform multiplier and a periodically resetting integrator to modulate a continuous-time angle modulation signal into a discrete-time signal. The waveform multiplier multiplies the continuous-time angle modulation signal by a square wave signal whose frequency is integer times a carrier frequency, and then transmits the continuous-time angle modulation signal to a periodically resetting integrated circuit. The periodically resetting integrated circuit performs integration during a carrier period to generate a discrete-time angle modulation output signal. The present invention can greatly reduce the difficulty for designing an optical sensing system in the front end without limiting a modulation depth. Besides, the present invention achieves a small volume, high speed, high sensitivity, high reliability, high performance and high condition-adapting properties. |
| US09048783B2 |
Reconfigurable voltage controlled oscillator for supporting multi-mode applications
In accordance with an embodiment of the disclosure, circuits and methods are provided for using a reconfigurable voltage controlled oscillator to support multi-mode applications. A voltage control oscillator circuit comprises a resonant circuit, a first oscillator circuitry coupled to the resonant circuit, and a second oscillator circuitry coupled to the resonant circuit. The voltage control oscillator circuit further comprises switching circuitry configured to select, based on an operating metric, one of the first oscillator circuitry and the second oscillator circuitry for providing an output voltage. |
| US09048782B2 |
Evaluation method for solar module and manufacturing method for solar module
Provided is a method for evaluating a solar cell incorporated into a solar module. A PL evaluation step is performed. The PL evaluation step is a step for evaluating the solar cell to be evaluated among a plurality of solar cells (10) by illuminating the solar cell (10) with light from a light source (20) and detecting the intensity of photoluminescent light (L2) emitted by the solar cell (10). The light is irradiated while a light-blocking member (21) is provided between the solar module (1) and the light source (20) so that light from the light source (20) is not incident on portions of the solar module other than the solar cell (10) to be evaluated. |
| US09048773B2 |
Method and device for regulating separately excited synchronous machines
A regulating method and device for loss-optimized operation of a separately excited synchronous machine having a stator and a rotor are provided. The method may include: providing reference values for stator and rotor currents, wherein the reference value for the stator current and/or the reference value for the rotor current or an auxiliary parameter representing the reference value of the stator current and/or an auxiliary parameter representing the reference value of the rotor current is dependent on a predefined reference torque; providing maximum values for stator and rotor currents; comparing reference values for the stator and/or rotor currents or an auxiliary parameter representing the reference value of the stator current and/or an auxiliary parameter representing a reference value of the rotor current to the corresponding maximum values and reducing of the reference torque by a torque value if at least one reference value reaches or exceeds the corresponding maximum value. |
| US09048767B2 |
Motor drive for permanent magnet synchronous motor
A pulse-width modulation (PWM) inverter controller compensates for harmonics in the output current provided by a PWM inverter to permanent magnet (PM) motor. The PWM inverter controller includes a field-oriented controller (FOC) that monitors output currents provided by the PWM inverter to the PM motor and employs the monitored output currents in a current loop feedback that generates control signals. A harmonic compensator transforms monitored phase currents into rectangular waveforms having magnitudes modified based on detected harmonics within the monitored phase currents to generate compensation signals. The compensation signals generated by the harmonic compensator are summed with the control signals generated by the FOC to generate compensated control signals. A PWM signal generator generates PWM signals for controlling the PWM inverter based on the compensated control signals. |
| US09048766B2 |
Method and apparatus for monitoring and controlling a synchronous electric machine
Controlling a synchronous electric machine includes determining a rotor field current of a wound rotor of the synchronous electric machine and determining a time-rate change in field flux linkage. A rotor field voltage is determined based upon the time-rate change in the field flux linkage, and a rotor field resistance is determined based upon the rotor field voltage and the rotor field current. A rotor temperature is determined based upon the rotor field resistance. Operation of the synchronous electric machine is controlled responsive to a torque command and the rotor temperature. |
| US09048765B2 |
Engine powered generator
An electric power generation system including an engine, an electrical generator, and a system controller. The engine is configured to produce mechanical power and includes an engine controller and a turbocharger for raising air pressure to a boost pressure. The turbocharger is controlled by the engine controller during steady state operation of the system. The electrical generator is mechanically connected to the engine and converts mechanical power into electrical power. The system controller is configured to receive a signal indicative of an electrical load on the generator. During a transient condition during which the electrical load increases, the system controller is configured to directly control the turbocharger in order to change the configuration of the turbocharger in order to increase boost pressure. |
| US09048764B2 |
Connection for improved current balancing in a parallel bridge power converter
A power generation system may include a generator and a power converter coupled to the generator. The power converter may include a plurality of bridge circuits coupled in parallel. Each bridge circuit may be coupled to an inductor. In addition, the power converter may include a plurality of parallel shorting devices. The shorting devices may be coupled to the bridge circuits such that an impedance of the inductors is effectively coupled between the shorting devices and the generator. |
| US09048760B2 |
Driving unit of vibration-type actuator
A driving unit of a vibration-type actuator includes a command unit, a change making unit, an AC signal generating unit, and a filter unit. The command unit outputs a command signal that directs at least one of a frequency, an amplitude, and a phase difference of an AC signal. The change making unit makes a change to the command signal and outputs the command signal. The AC signal generating unit generates a generated AC signal in which at least one of a frequency, an amplitude, and a phase difference of the generated AC signal is modulated in accordance with the output of the change making unit. The filter unit selectively dampens a frequency component, of at least one of the output signal of the change making unit and an output signal of the AC signal generating unit, that excites vibration other than vibration in a predetermined vibration mode. |
| US09048755B2 |
Adjustable speed drive lifetime improvement system
The present techniques include methods and systems for operating an inverter to maintain a lifespan of the inverter. In some embodiments, the switching frequency and/or the output current of the inverter may be changed such that stress may be reduced on the inverter bond wires of the inverter. More specifically, embodiments involve calculating the aging parameters for certain operating conditions of the inverter and determining whether the operating conditions result in aging the inverter to a point which reduces the inverter lifespan below a desired lifespan. If the operating conditions reduce the inverter lifespan below the desired lifespan, the switching frequency may be reduced to a lower or minimum switching frequency of the inverter and/or the output current of the inverter may be reduced to a maximum output current at the minimum switching frequency. |
| US09048753B2 |
PFC converter including transformer
A PFC converter that reduces a superimposed voltage generated by an inrush current into a filter capacitor operates such that, when a commercial alternating-current power supply is connected to input terminals of a PFC converter, a rectified voltage is applied to a filter capacitor via a diode bridge and a charging current flows through the filter capacitor. At the same time, the rectified voltage is also applied to a series circuit including a diode and a capacitor and a charging current for the capacitor flows through the series circuit. Accordingly, a charging time constant becomes large and a superimposed voltage generated by the inductance component of a line or a line filter connected to the line and the charging current becomes low. |
| US09048746B2 |
Electric device having an interference suppression capacitor circuit
An electrical device having at least one interference suppression capacitor (6, 60) that is actively discharged when there is an interruption to the mains voltage (7) by connecting an electrical load (69) in parallel. For this purpose, the device has a monitor for the mains voltage (7) and means for connecting (68) the electrical load. |
| US09048742B2 |
Systems and methods for adjusting current consumption of control chips to reduce standby power consumption of power converters
System and method for regulating a power conversion system. For example, a system controller includes a signal generator and one or more power-consumption components. The signal generator is configured to receive a feedback signal related to an output signal of the power conversion system, a current sensing signal and an input voltage, and to generate a control signal based on at least information associated with the feedback signal, the current sensing signal and the input voltage. The power-consumption components are configured to receive the control signal. The signal generator is further configured to determine whether the feedback signal is smaller than a feedback threshold for a first predetermined period of time, the current sensing signal is smaller than a current sensing threshold for a second predetermined period of time, and the input voltage is smaller than a first threshold for a third predetermined period of time in magnitude. |
| US09048739B2 |
Power supply device and image forming apparatus
The power supply device includes a transformer, a switching unit for driving a primary side of the transformer, a detection unit for detecting an output corresponding to a current flowing on the primary side, a transmission unit for transmitting an output voltage from a secondary side to the primary side, and a control unit for controlling an operation of the switching unit in accordance with an output from the transmission unit, in which, when a switching frequency for driving the switching unit falls within a predetermined frequency range including a resonant frequency of the transformer, the control unit controls the switching unit so as to shorten a turn-ON time of the switching unit in accordance with an output from the detection unit. |
| US09048738B2 |
Systems and methods for zero voltage switching in power conversion systems
System and method for regulating a power converter. A system for regulating a power converter includes a controller, a first switch, and a second switch. The controller is configured to generate a first switching signal and a second switching signal. The first switch is configured to receive the first switching signal, the first switch being coupled to an auxiliary winding of the power converter further including a primary winding and a secondary winding. The second switch is configured to receive the second switching signal and coupled to the primary winding of the power converter. The controller is further configured to, change, at a first time, the second switching signal to open the second switch, maintain, from the first time to a second time, the first switching signal to keep the first switch open, and change, at the second time, the first switching signal to close the first switch. |
| US09048733B2 |
Motor driving device having reactive current instruction generating unit
A motor driving device includes a converter that converts an input alternating current into a direct current, an inverter that inverts the direct current output by the converter into an alternating current for driving a motor, a voltage detecting unit that detects a voltage on a direct current output side of the converter, and a numerical control unit that causes the inverter to output a reactive current to increase electric power consumed in the motor, when the voltage detected by the voltage detecting unit exceeds a predetermined threshold. |
| US09048731B2 |
Rectifying apparatus
A rectifying apparatus (power receiving apparatus) 100 is configured to receive electric power output from the power transmitting apparatus 101. The rectifying apparatus 100 is mobile equipment, such as a battery, a smartphone incorporating a battery and a tablet PC, or equipment for a battery charger connected to the equipment. The rectifying apparatus (power receiving apparatus) 100 may be any other equipment that receives electric power output from the associated power transmitting apparatus 101, including a rechargeable electric car, a household appliance and a product for underwater application. |
| US09048727B2 |
Power converter with capacitive energy transfer and fast dynamic response
A converter circuit and related technique for providing high power density power conversion includes a reconfigurable switched capacitor transformation stage coupled to a magnetic converter (or regulation) stage. The circuits and techniques achieve high performance over a wide input voltage range or a wide output voltage range. The converter can be used, for example, to power logic devices in portable battery operated devices. |
| US09048725B2 |
Electric device and a method for a wave power plant
The invention relates to an electric device with a winding (12) and means for inducing a current in the winding. A bridge circuit (400) electrically connects the winding (12) to a load (13). According to the invention the bridge circuit (400) includes capacitor means (401, 402), which is adapted for obtaining resonance with the impedance of the winding (12). |
| US09048723B2 |
Active feedback control integrated circuit applied to an alternating current/direct current converter and operation method thereof
An active feedback control integrated circuit applied to an alternating current/direct current converter includes a feedback pin, an operation unit, a control unit, and a controlled-current generation unit. The feedback pin is used for receiving a feedback current of an output feedback unit of the alternating current/direct current converter. The operation unit is used for generating an operation signal according to the feedback current. The control unit is coupled to the operation unit for generating a current control signal. The controlled-current generation unit is coupled to the control unit for generating a controlled current to the feedback pin according to the current control signal. |
| US09048720B2 |
Bidirectional motor driver low voltage power supply (LVPS)
A bidirectional low voltage power supply (LVPS) for providing power to motor drive electronics. The bidirectional LVPS includes two simple, discrete converters. A first converter is used to provide power to an output and the second converter recycles power from the output to the power source. The first converter powers the drive electronics which drives the motor. During an operating process, the first converter shuts off and the second converter turns on to recycle power from the motor to the power source. |
| US09048719B1 |
Photovoltaic cell and related method
A photovoltaic cell for the production from solar radiation of electrical energy includes a reservoir adapted to contain a quantity of photoionizable solution, a solar powered plasma generator in fluid communication with the reservoir, a solar powered ionization chamber in fluid communication with the plasma generator, an electrode baffle in fluid communication with the ionization chamber and a return fluid communication path from the electrode baffle to the reservoir. As arranged, the reservoir, the plasma generator, the ionization chamber and the electrode baffle form a closed fluid loop in order from the reservoir to the plasma generator to the ionization chamber to the electrode baffle and back to the reservoir. |
| US09048714B2 |
Squirrel cage rotor having reduced radius to accommodate permanent magnets
A rotor (11) with a squirrel cage and permanent magnets (19) mounted on and distributed around the circumference of the rotor, including a core stack extending over the entire rotor region with longitudinally continuous rotor slots extending over the length of the core stack. The squirrel cage is constructed with cage bars disposed, and preferably cast, in the rotor slots; short circuit rings connect the cage bars at both end faces of the core; and the radius of the rotor region is reduced by at least the radial thickness of the magnets. The radius of rotor (11) is reduced over the entire length between short circuit rings (17) such that the radial height of cage bars (15, 29) or cage webs (27) connected thereto is reduced. Also an electric motor or a radial pump having such a rotor, and methods of producing or operating such devices. |
| US09048712B2 |
Motor and rotor thereof
A rotor having an improved structure capable of achieving an enhancement in durability and a motor having the rotor are disclosed. The rotor is configured to co-operate with a stator in an electromagnetic manner such that the rotor rotates. The rotor includes a sleeve having a shaft hole, through which the motor shaft extends, rotor cores spaced apart from one another in a circumferential direction of the rotor, and at least one of permanent magnets disposed between adjacent ones of the rotor cores such that the permanent magnets are arranged in a radial manner about the sleeve. First and second cover plates are disposed at opposite sides of the permanent magnets in an axial direction. The first and second cover plates have plate holes respectively corresponding to the through holes of the rotor cores. The rotor cores and the first and second cover plates are coupled by fastening members. |
| US09048706B1 |
Small scale renewable energy power generating apparatus
An apparatus uses mechanical means to allow low volume, intermittent air or water or other energy sources to provide electrical power through a power train connected to an electrical generator. |
| US09048705B2 |
Wind power generating apparatus having a wind guide
Provided is a wind power generating apparatus including a generating tower that has a wall surface in which a plurality of through-holes for inflow of wind are formed, wind inlet walls that protrude outwardly from the respective through-holes so as to guide the inflow of wind, a generating blade that rotates by means of the wind introduced into the generating tower, a generator that generates electricity in conjunction with the rotation of the generating blade, a wind inlet port formed through the respective through-holes formed in the wall surface of the generating tower, and a wind contact member, which is connected to an end of the generating blade, which has a triangular pyramid shape with an open front surface so as to extend the area pressurized by the wind introduced through the wind inlet port, and which has a flow channel dividing member arranged across the open front surface. |
| US09048703B2 |
System and method for controlling power trunk
Disclosed is a system for controlling a power trunk in a trunk-equipped vehicle, including: a motor configured to transfer power to the trunk to drive the trunk; a velocity sensing unit configured to sense a velocity of the motor; a control unit configured to compute a current trunk position and an operational velocity based on information on the velocity of the motor sensed by the velocity sensing unit and control the motor based on the computed position and the operational velocity, wherein a predetermined target velocity and the operational velocity are compared, and a difference between the target velocity and the operational velocity is compensated using a proportional integral derivative (PID) control scheme. It is possible to constantly control an open/close velocity of a power trunk regardless of a change of external environments when a power trunk is opened or closed in a vehicle having a power trunk system. |
| US09048702B2 |
Generator with compact single turn wave winding and wind turbine
A generator is provided that includes at least one pole set representing one phase. Each pole set includes a plurality of poles. Only one conductor is turned about the poles of a particular pole set such that only half a single turn is associated to each pole of the particular pole set. |
| US09048699B2 |
Power tool
According to an aspect of the present invention, there is provided a power tool including: a brushless motor; switching elements that drive the brushless motor; a circuit board on which the switching elements are mounted; a transmission portion that transmits a driving force of the brushless motor; and a housing that houses the brushless motor, the switching elements, the circuit board and the transmission portion therein, wherein the switching elements include semiconductor elements each having terminals on a bottom surface thereof, and wherein the switching elements are surface mounted on the circuit board. |
| US09048693B2 |
Method and apparatus for detecting impairment of a solar array
An apparatus for detecting an impairment of a solar array. The apparatus comprises an impairment detection module for performing a comparison of a power production profile and at least one reference profile, wherein the power production profile and the at least one reference profile are for at least one of the solar array, at least one solar subarray of the solar array, or at least one solar panel of the solar array. The apparatus determines, based on the comparison, whether the impairment exists. |
| US09048688B2 |
Method and apparatus for preventing overloads of power distribution networks
Systems and methods for monitoring power in power distribution systems are provided. In one aspect, a system for monitoring power includes a power monitoring device that measures a value of at least one characteristic of power provided to a branch of a power distribution system. The power monitoring device includes an output that provides the value measured. The system further includes a controller having an input to receive the value measured and an output that couples to a first device powered by the branch to send a maximum power signal to the first device to command the first device to operate at a percentage of maximum power. |
| US09048686B2 |
Power supply system, controller therefor, and method of manufacture of controller
A power supply system of the present invention aims to achieve optimization of the efficiency and therefore includes: z (z is a natural number equal to or larger than 2) power supplies (PS-1 to PS-z) connected in parallel; and a controller (8) for the number of power supplies in operation which controls the number of power supplies in operation among the power supplies (PS-1 to PS-z). The controller (8) for the number of power supplies in operation determines the number of the power supplies in operation based on values of intersection currents i1 to i(z-1) which are determined through processes of: identifying output loss characteristics with respect to load currents of the z power supplies (PS-1 to PS-z) by use of convex functions f1 to fz, respectively; obtaining a function hn expressing a conversion efficiency of a total load current at the time of operating the n (n is a natural number equal to or smaller than z) power supplies (PS-1 to PS-z) based on the functions f1 to fz; and obtaining an intersection current iq (q is a natural number equal to or smaller than (z−1)) which is a current of an intersection point between a function hq and a function h(q+1). (Greek letter eta is replaced with h.) |
| US09048684B2 |
Intelligent high speed automatic transfer switch
A transfer system may be provided. The transfer system may comprise a first transfer switch comprising first normally closed contacts and first normally open contacts. In addition, the transfer system may comprise a second transfer switch comprising second normally closed contacts and second normally open contacts. Furthermore, the transfer system may comprise third normally closed contacts with a solid state switch in parallel. A source monitor may be configured to monitor the quality of a primary source and a backup source. And a source control may be configured to operate the first transfer switch, the second transfer switch, the third normally closed contacts, and the solid state switch to transfer a load from the primary source to the backup source in response to the monitored quality of the primary source and the backup source. |
| US09048683B2 |
Method for controlling charging power and wireless charging apparatus for the same
Disclosed is a method for advance detection of output power, before arrival at a boundary frequency between an inband and an outband during frequency tracking in a wireless charging apparatus, the wireless charging apparatus including a first resonator resonating at a lower-limit frequency of the inband and a second resonator resonating at an upper-limit frequency of the inband, to adaptively adjust the frequency based on the power values output from the first and second resonators, and to determine a power transmission control value corresponding to the adjusted frequency, thereby enabling frequency control and power control within the inband. |
| US09048676B2 |
Charging circuit and charging method
A charging circuit that simultaneously charges a battery with an electrical current supplied from an external power source and supplies the electrical current supplied from the external power source to a load includes a power supply circuit to supply an electrical current from the battery to the load when a load current required by the load is greater than a maximum supply current of the external power source, a detector to detect a voltage of the battery, and a controller to control power supply to the load as well as charging the battery. When the detected voltage of the battery is lower than the predetermined threshold, the controller stops supplying the electrical current from the battery to the load and charges the battery with the electrical current supplied from the external power source. |
| US09048672B2 |
Semiconductor integrated circuit, protection circuit and battery pack
A semiconductor integrated circuit that protects a secondary battery by controlling an on/off status of a discharge control switch and a charge control switch includes an over discharge detection part configured to detect an over discharge condition based on a battery voltage of the secondary battery, a load removal detection part to detect whether a load connected to the secondary battery is removed based on a voltage of a load removal detection terminal connected to a negative electrode side of at least one of the load connected to the secondary battery and a battery charger through a resistor, an over discharge return part to return to a normal condition from the over discharge condition, and a control part to output a control signal for returning the over discharge condition to the normal condition to the over discharge return part upon detecting the load being removed in the over discharge condition. |
| US09048671B2 |
Delayed reactive electrical consumption mitigation
The electrical consumption mitigation provided by energy storage systems can be unreliable when a consumption peak lasts long enough to deplete the energy stored and the remainder of the peak is unmitigated. By implementing a waiting period between detecting the peak and discharging the energy storage in which characteristics of the peak are observed, a peak mitigation system can lengthen the effective discharge duration of the energy storage system and prevent unmitigated plateaus from appearing. For example, when a consumption plateau is detected, the system may discharge at a slower rate than when a spike is detected in order to prolong mitigation activities before the conclusion of the plateau. Thus otherwise-incurred demand-related utility charges can be reduced without having to increase the capacity of the mitigation system. In some cases, these processes are performed with respect to the bounds of demand-averaged time periods used to calculate demand charges. |
| US09048670B2 |
System and method for balancing electrical energy storage devices via differential power bus and capacitive load switched-mode power supply
System and method are provided for transferring electrical energy among multiple electrical energy storage devices via a differential power bus and a capacitive load switched-mode power supply. The switched-mode power supply transfers the electrical energy between the load capacitor and the differential power bus to which the electrical energy storage devices (e.g., rechargeable batteries and/or capacitors connected in parallel or series or combinations of both) are electrically connected via bus switches. As a result, electrical energy is efficiently transferred and distributed among the electrical energy storage devices. |
| US09048669B2 |
Charge equalization apparatus and method for series-connected battery string
Provided are a charge equalization apparatus and method for a battery string connected in series, and more particularly, are a charge equalization apparatus and method that efficiently perform charge equalization while reducing entire complexity and volume and lowering production costs through a configuration that an individual battery included in a battery string shares a single voltage sensing module and a single charge equalizing module; a switch block of a two-stage structure forms a current path for measuring voltage of individual batteries included in the battery string, and at the same time, forms a charging or discharging path of a low-charged or over-charged battery among the battery strings; and a switch device having low withstand voltage is used. |
| US09048668B2 |
Charger
The charger 10 includes a first charging path that charges battery banks via current limiting resistors R1 to R3, a second charging path that charges the battery banks without passing through the current limiting resistors R1 to R3, and a circuit that is capable of selectively switching the first and second charging paths to one another, being provided to the respective battery banks, and being identical in resistance values of the current limiting resistors R1 to R3. A battery voltage detection circuit detects the voltages of the battery banks; and a controller 16 controls the first to third charging circuits so that the battery banks are charged through the first charging path when there is difference in the voltages of the battery banks. The battery banks are charged through the second charging path when there is no difference in the voltages of the battery banks. |
| US09048667B2 |
Cell controller, battery module and power supply system
A suppressed noise cell controller includes, corresponding to a number of cell packs, a plurality of ICs each having a voltage detecting circuit detecting voltages of respective cells of a cell pack in which four cells are connected in series, a switch control circuit controlling conduction and a blocking operation of a plurality of switch elements connected in parallel to the respective cells via capacity adjusting resistors, terminal LIN1 for inputting control information, terminal LIN2 for outputting control information, terminal Vcc and GND terminal, and terminal LIN2 of a higher-order IC and terminal LIN1 of a lower-order IC are daisy chain connected. The Vcc terminal of each IC is connected to a positive electrode of a higher-order cell among cells constituting a corresponding cell pack via a noise eliminating inductor, and the GND terminal is coupled directly to Vcc of the lower-order IC. Noise isn't superposed on LIN1 or LIN2. |
| US09048665B2 |
Electronic device case
A protective enclosure for an electronic device is provided. The protective enclosure includes a hard shell that includes a front shell formed to a rigid shape of a front portion of the electronic device and a back shell formed to a rigid shape of a rear portion of the electronic device. The protective enclosure also includes a stretchable cushion layer over the hard shell that has a sufficient elasticity to conform to the hard shell and provide cushioning to the protective enclosure. The protective enclosure also includes a battery and electrical circuitry configured to receive electronic communications from the electronic device and distribute electrical current received from an external power source among the battery and the electronic device based on the received electronic communications. |
| US09048663B2 |
Electrical energy distribution system with ride-through capability
This invention concerns an electrical energy distribution system. The system incorporates ‘ride-through’ capability, comprising: a supply side for supplying energy in the form of direct current at a supply voltage, a delivery side for delivering energy, having plural connection ports for selective connection to respective electrical energy loads. Wherein each connection port includes electricity conditioning circuitry to deliver and vary electrical power supply to a load connected at the port. And further comprising a bank of charge storage devices arranged in series and connected across the supply voltage. |
| US09048657B2 |
Control circuit for electric power circuit switch
A control circuit for an electric power circuit switch includes: a sampling/hold circuit section configured to sample a period of a detection signal of a current of an electric power system and provide a sampled signal; a discrete Fourier transforming (abbreviated as DFT) circuit section perform DFT on the one-period sampled signal to provide a magnitude and a phase of a frequency component of the current of the electric power system; a differentiator configured to differentiate the detection signal to provide a rate of change of the current over time; and a controller to determine whether to perform trip controlling according to the magnitude of the frequency component of the current from the DFT circuit section or the rate of change from the differentiator on the basis of the rate of change of the current and the reference rate of change. |
| US09048652B2 |
Cable termination device, a method for prefabricating a cable termination device and a method for achieving a cable termination
A cable termination device of the dry type, including an insulator housing with an upper end and a lower end and having a hollow interior, which lower end has an opening for insertion of the cable. The device further includes a stress controller device located inside the insulator housing and adapted to be mounted on a high voltage cable, and an electrically insulating gel filling at least part of the hollow interior of the insulator housing and surrounding at least part of the stress controller device. Further, the stress controller device extends from the lower end of the insulator housing and into the housing where it has a free end, whereby a space is formed between the stress controller device and an inner wall of the insulator housing. |
| US09048649B2 |
Method and apparatus for anti-icing and deicing power transmission lines
A method and apparatus for managing icing of a plurality of transmission lines in a power transmission system. A power transmission system comprises a plurality of transmission lines and a control system. A first amount of power flows into the power transmission system through the plurality of transmission lines and a second amount of power flows out of the power transmission system through the plurality of transmission lines. The control system is configured to change a flow of power through the plurality of transmission lines such that icing of the plurality of transmission lines is managed. The first amount of power flowing into the power transmission system and the second amount of power flowing out of the power transmission system remains substantially constant during the change in the flow of power through the plurality of transmission lines. |
| US09048641B2 |
Terminal box
A terminal box includes a box body forming a recessed portion and a terminal board accommodated within the recessed portion and providing conduction between a tab of a solar cell panel and a power line. The terminal board includes a projecting portion projecting from the box body toward the solar cell panel, and a spring portion extended along a direction perpendicular to the projecting direction of the projecting portion. The projecting portion includes a contact portion for contacting the tab of the solar cell panel. The projecting portion is supported by a first-side end of the spring portion. The spring portion has a meander structure having a plurality of folded portions in a plane having a normal line perpendicular to both the projecting direction of the projecting portion and the extending direction of the spring portion. |
| US09048638B2 |
7-Way crab joint
An apparatus and method for interconnecting mains cables used for underground secondary low-voltage AC network systems utilizing an improved crab joint connector arranged to maximize the number of interconnections in a compact design wherein the plurality of legs are arranged in a rectangle configuration and a single bus leg is positioned at an end of an insulated housing. |
| US09048637B2 |
Gas-insulated switchgear
A gas-insulated switchgear includes: a circuit breaker; a connection bus bar; a first disconnect switch; a second disconnect switch; a line bus bar; a main bus bar; and an abutment. The circuit breaker includes first and second branch outlets provided on a side surface of a cylindrical circuit breaker tank. The connection bus bar has one end connected to the first branch outlet. The first disconnect switch is connected to the other end of the connection bus bar. The second disconnect switch is connected to the second branch outlet. The line bus bar is led out from the second disconnect switch in a horizontal direction. The main bus bar is arranged above the second disconnect switch coaxially with the second branch outlet. The abutment is fixed to a top portion of the second disconnect switch and supports the main bus bar from below. |
| US09048636B2 |
Electrical pedestal
The invention is directed to an electrical pedestal comprising an elastomeric base and housing which are configured as one piece to together define a unitary hollow enclosure for accommodating one or more electrical components. |
| US09048634B2 |
Water resistant direct spark igniter
A direct spark igniter for a fuel-fired heating appliance is provided with enhanced ignition performance in environments having substantial levels of both moisture and pollution. Such enhanced ignition performance is representatively achieved by the combination of (1) forming external annular ribs on the ceramic body portion of the igniter; (2) extending a top end of the igniter electrode rod into the body portion; (3) bending the igniter electrode and ground rods and angling them toward one another; and (4) knurling external side surfaces on lower end portions of the igniter electrode and ground rods. |
| US09048631B2 |
Laser light source
A laser light source having a ridge waveguide structure includes a semi-conductor layer sequence having a number of functional layers and an active region that is suitable for generating laser light during operation. At least one of the functional layers is designed as a ridge of the ridge waveguide structure. The semiconductor layer sequence has a mode filter structure that is formed as part of the ridge and/or along a main extension plane of the functional layers next to the ridge and/or perpendicular to the main extension plane of the functional layers below the ridge. |
| US09048626B2 |
Noise detection, diagnostics, and control of modelocked lasers
The present invention features a laser based system configured with a noise detection unit. The system includes a mode-locked oscillator. A noise detection unit includes at least one optical detector that monitors optical pulses generated by the mode-locked oscillator and produces an electrical signal in response to the optical pulses. The noise detection unit includes a first filter to transmit signal power over a signal bandwidth which includes the mode-locked laser repetition frequency, frep. The noise detection unit may include one or more filters to transmit power over a noise bandwidth that substantially excludes repetition frequency, frep. Non-linear signal processing equipment is utilized to generate one or more signals representative of the power in the signal bandwidth relative to the power in the noise bandwidth. The system includes a controller operable to generate a signal for controlling the laser based system based on the relative power. |
| US09048623B2 |
Photonic crystal laser
A photonic crystal laser capable of producing a radially-polarized halo-shaped laser beam having a smaller width than conventional beams includes: an active layer; a ring-shaped photonic crystal including a plate-shaped base body on one side of the active layer, the base body having a number of modified refractive index areas of the same shape, the modified refractive index areas having a refractive index different from the base body and periodically arranged in the circumferential direction of a ring, and each of the modified refractive index areas being asymmetrically shaped with respect to an axis extending through the center of the modified refractive index area in the radial direction of the ring; a first and second electrode facing each other across the active layer and the ring-shaped photonic crystal; and a window provided in the second electrode capable of allowing passage of a laser light generated from the ring-shaped photonic crystal. |
| US09048616B1 |
Method, system and apparatus for automatically determining operating conditions of a periodically poled lithium niobate crystal in a laser system
A method, system and apparatus for automatically determining operating conditions of a periodically poled lithium niobate crystal in a laser system are provided. The system comprise: a laser; a periodic poled lithium niobate (PPLN) crystal for receiving laser input from the laser; a temperature control device for adjusting the temperature of the PPLN crystal; a temperature sensor for monitoring the temperature of the PPLN crystal; and a computing device. While the PPLN crystal is receiving laser input, temperature of the PPLN crystal is changed using the temperature control device. The computing device monitors the temperature of the PPLN crystal and corresponding power of the temperature control device during the changing, the temperature monitored using the temperature sensor. The computing device determines one or more of operating conditions of the temperature control device and an operating temperature of the PPLN crystal from a function of the power vs. the temperature. |
| US09048613B2 |
Hybrid vertical cavity laser and method of manufacturing the same
A hybrid vertical cavity laser includes an optical circuit substrate including a grating having refractive index units having a lower refractive index and a higher refractive index with respect to each other that are alternately arranged in a first direction, and a waveguide guiding light in the first direction, a mesa structure on the optical circuit substrate, the mesa structure including a first-type semiconductor layer including an exposed portion, an active layer, a second-type semiconductor layer, and an upper reflective layer sequentially stacked in a second direction perpendicular to the first direction, a first electrode on the exposed portion, and a second electrode on the upper reflective layer. An overlapped length between the waveguide and a mesa aperture forming an opening through which light produced from the active layer enters the grating is D, a pitch of the grating is p, and 0 |
| US09048612B2 |
Laser light source module
A laser light source module that does not emit laser light when taken out of a device or that does not emit laser light when the device is modified by removing a portion of the device is installed and used in a case and is provided with: a laser unit that includes a memory unit that stores a password and that operates when an input password that is entered matches a password stored in the memory unit; a password-setting mechanism that generates different data according to the state of the case; and a password-generating circuit that generates an input password that matches the password stored in the memory unit by means of data generated by means of the password-setting mechanism when the case is in a normal state. |
| US09048610B2 |
External cavity tunable laser with 25GHz frequency interval
The invention relates to an external cavity tunable laser with 25 GHz frequency interval. The laser comprise a laser cavity end mirror directly plated on a laser gain medium, and the laser gain medium, an intracavity collimating lens, an active optical phase modulator, a tunable acousto-optic filter and an intracavity total reflection mirror all arranged inside a laser cavity sequentially. The laser further comprises: an active polarization rotator arranged on the opposite side of the tunable acousto-optic filter from the intracavity total reflection mirror, a polarization beam splitter arranged behind the active polarization rotator, a first etalon, a first total reflection mirror, a second etalon, a second total reflection mirror, a drive source for the tunable acousto-optic filter, a pumping source for the laser gain medium, a drive source for the active optical phase modulator, a drive source for the active polarization rotator and a laser drive control circuit. The invention is compact with high performance, low cost for volume production and installation, achieves high spectral density, narrow spectral bandwidth and stable tunable laser output within a wide spectrum range. |
| US09048605B2 |
Hand operated crimping tool
A hand operated crimping tool comprising a body arranged between a distal end and a proximal end of the crimping tool, a tool head arranged distally on the crimping tool, and handles arranged proximally on the crimping tool, which handles are movably arranged in relation to each other, where at least one handle is movably arranged in relation to the body, where two crimping dies between which at least one workpiece is to be crimped form a die pair, and where the relative movement of the tool handles is connected to the relative movement of crimping dies forming at least one die pair. The crimping tool comprises at least three crimping dies, the crimping dies forming at least two die pairs, where the distances between the respective crimping dies in at least two die pairs are further arranged adjustable independently of each other. |
| US09048602B2 |
Audio-visual connector
A cover for an electronic device is provided that may include a connector housing integrally molded with the cover. The connector housing may define a cavity configured to receive a connector plug therein, and a plurality of connector springs may be configured to contact the connector plug when the connector plug occupies the cavity. The plurality of springs may be protected and, as such, may not be visible when the cover is removed from the electronic device. |
| US09048600B2 |
Shielded coaxial connector
A coaxial connector has a selectively engageable radio frequency interference shield. |
| US09048595B2 |
Retaining clip for electrical connectors
A retaining clip that provides a method for securing electrical connections between a male and female electrical connectors is disclosed. Current locking mechanisms are on both the electrical plug and the connector. These locking mechanisms often break when disconnecting the plug. Some embodiments of the present invention eliminate the need for the locking mechanisms. Furthermore, in cases where the mechanisms have been broken, some embodiments provide a method for reusing the electrical plug and/or the connector. |
| US09048589B2 |
Shielding shell for a connector
A Shielding shell for a connector is disclosed which includes a first wall, a second wall and a third wall. The first wall, the second wall and the third wall are arranged mutually at an angle to each other. At least the first wall and the second wall are connected to each other by a first folded edge. The shielding shell further includes a first contact portion connected with the second wall by a second folded edge, the first contact portion being arranged substantially parallel to the third wall and including a plurality of contact segments contacting said third wall. |
| US09048586B2 |
Earth connection for electrically and mechanically connecting earth wires
An earth connection for electrically and mechanically connecting a plurality of earth wires to a structure, in particular to an aircraft structure, comprising an angled element which element is formed in one piece and is made of electrically conductive material, which comprises a first and a second fastening portion. The first fastening portion is fastened to the structure and the second fastening portion comprises a plurality of electrical connections for connecting the earth wires. The electrical connections comprise socket contact elements which are formed so as to receive pin contact elements of the earth wires. |
| US09048583B2 |
Electrical connector having ribbed ground plate
An electrical connector includes a dielectric housing, a plurality of electrical signal contacts carried by the dielectric housing, and a ground plate carried by the dielectric housing. The electrical signal contacts are arranged along a first plane, wherein the signal contacts define signal pairs such that a respective gap is disposed between adjacent signal pairs. The signal contacts further define respective mating and mounting ends. The ground plate includes a ground plate body oriented in a second plane that is substantially parallel to the first plane and offset from the first plane. The ground plate body defines first and second opposed surfaces. The ground plate includes at least one rib that defines first and second opposed surfaces, wherein the first surface of the rib projects from the first surface of the ground plate body in a direction toward the gap, and the second surface is recessed into the second surface of the ground plate body. The ground plate further includes a plurality of mating ends and mounting ends extending from the ground plate body and disposed in the first plane so as to be aligned with the respective mating ends and mounting ends of the electrical signal contacts. |
| US09048582B2 |
Half fitting prevention connector
A half fitting prevention connector includes a cylindrical case, a connector body, a lever, and a release lever. The release lever has a lock hole. An electromagnetic coil has a plunger. The plunger is arranged so as to face a microswitch. The electromagnetic coil is excited by connection between the signal terminal of the connector body and a signal terminal of a mating connector, and thereby moving the plunger toward the microswitch. The release lever is rotatable so that the plunger can enter the lock hole to press the microswitch in a state that the connector body is completely fitted with the mating connector and the plunger cannot enter the lock hole in a state that the connector body is half fitted with the mating connector. |
| US09048578B2 |
Lever-fitting-type connector
A boss drawing-in groove of a lever includes: a lever inversion groove portion configured to cause the lever drawing-in boss to rotate the lever in an opposite direction opposite to a fitting rotation direction, in response to an insertion of a male connector into a hood with the lever being positioned at an initial rotation position; a drawing-in groove portion configured to guide the lever drawing-in boss by a rotating operation of the lever in the fitting rotation direction and cause the male connector to be fitted into a female connector; and a lever inertial rotation portion configured to rotate in the fitting rotation direction due to an inertial force of the lever after rotation of the lever in the opposite direction and cause the lever drawing-in boss to move to the drawing-in groove portion. |
| US09048576B2 |
Multiple-stage interlocking electrical connector with locking assurance mechanism
An electrical connector assembly comprises a primary connector housing, a mating connector housing, a primary lock, and a secondary lock. The primary lock is defined by both the primary connector housing and the mating connector housing. The secondary lock is supported by the mating connector housing and is arranged and configured for interacting with the primary lock so as to prevent the primary lock, when positioned in a locked position, from disengaging. The primary lock comprises a lock arm extending from the primary connector housing and a lock lever extending from the mating connector housing. |
| US09048573B2 |
Industrial interconnect system incorporating transceiver module cage
An interconnect system (30, 100) includes a transceiver module assembly (105) that is mountable in an industrial receptacle (28, 103). The receptacle mates to an industrial optical connector (34) to form an environmentally sealed connection. The receptacle has an interior passageway (143, 162) and mating means (124) for attaching the module assembly. The module assembly includes a spring-loaded module cage (50) for receiving active devices (48), such as SFP transceivers. The spring-loaded module cage can adjust its position within the receptacle to accommodate different type of modules from various vendors. When attached to the platform, the module assembly is positioned so that the cage's open end is accessible through the receptacle's passageway. Users have the option of plugging/unplugging the transceiver module either through the passageway or by removing the module assembly from the receptacle. |
| US09048567B2 |
Connector having a regulating portion received in a regulated portion along a predetermined direction
A connector capable of being fitted to a partner connector is provided with a lock member, a solenoid having a plunger, a restriction member having a restricting part, and a restricted part. In a fitted state in which the connector and the partner connector are fitted to each other, the lock member engages the partner connector and locks the two connectors into a fitted state. The solenoid drives the plunger between a restriction position and a release position. The restriction member is movably supported by the plunger. The restricted part receives the restricting part when the plunger is driven into the restriction position. When the plunger is in the restriction position, movement of the restricted part is restricted by the restricting part, and thereby the restricted part directly or indirectly prevents release of the fitted state. |
| US09048566B2 |
Cable assembly having improved strain relief
A cable assembly includes a connector, a cover enclosing the connector, a strain relief located on the rear end of the cover, a spring, and a cable. The cover includes a blocking. The strain relief is fixed by the blocking. The strain relief defines a through hole and a receiving cavity communicated with the through hole. The through hole has an inner diameter smaller than an inner diameter of the receiving cavity. A shoulder is formed between the through hole and the receiving cavity. The spring is received in the cavity, and has one end restricted by the shoulder and an opposite end restricted by the blocking. The cable is connected to the connector and runs through the spring and the through hole. |
| US09048562B2 |
Contacting system for producing electrical contact between a cable and a sensor
A contacting system, comprising: an essentially cylindrical contact body having at least a first opening, a second opening and a contact body interior between the first opening and the second opening. The first opening is embodied for accommodating the cable, wherein a holding element is provided in the contact body interior and is so embodied that it produces contact between the first conductor and the contact body. A sealing element is provided at the first opening and is so embodied that it seals off the contact body interior from the medium. |
| US09048560B2 |
Modular electrical connector assembly and associated method of making
A method for producing modular electrical connectors having varying contact element configurations includes providing a common header component having a plurality of receptacle spaces defined therein. A plurality of different contact sub-assemblies are provided having varying contact element configurations, with each of sub-assembly having a common size configured for receipt in the receptacle spaces. A pattern of the contact sub-assemblies is defined for a particular desired connector configuration from any combination of the contact sub-assemblies, and the contact sub-assemblies are fitted and adhered into the receptacle spaces in the header component according to the pattern. A kit may be provided with the modular components for making the connectors. |
| US09048558B1 |
Receptacle connector
A receptacle connector includes a main body, an insulating base, a tenon member, a compressing spring, and a cap body. The main body includes a first concave area. The insulating base includes a second concave area. The first and the second concave area constitute a joint cavity and an opening. The tenon member erected on the bottom surface of the first concave area and is threaded through the compression spring. The cap body includes a sheath portion slidably threaded through the tenon member and a cover portion occupied a part of the opening. The sheath portion is connected to the compression spring and when the sheath portion of the cap body compresses the compression spring, the cover portion of the cap body is capable of moving from a closing position to an accessing position relative to the opening. |
| US09048555B2 |
Wire connector
A wire connector includes a connection box having two closed end walls spaced in a longitudinal direction. The connect box includes a compartment having first and second end walls spaced in a height direction. At least one partitioning wall extends from the second end wall toward but spaced from the first end wall, defining a gap. The at least one partitioning wall divides the compartment into a plurality of channels spaced in a width direction. The channels are respectively aligned with and in communication with through-holes in at least one of the closed end walls. Each channel has a first end at the first end wall and a second end at the second end wall. The first ends of the channels and the gap together define a flat receiving groove in which a conductive plate is received. An elastic pressing plate is received in each channel. |
| US09048551B2 |
Casing for an electrical connector
An electrical connector (2) housing (1) for connecting at least one cable lug (31) to a threaded terminal of an electrical device (4), including, for each lug, a hole (11) for receiving a screw (12) for retaining a lug in a threaded terminal, which hole has a lateral slot (13) designed to allow a lug to penetrate the hole, a lower opening (14) for connecting the lug to a threaded terminal and an upper opening (15) designed to allow the passage of a screwing tool for the screw, the size of the upper opening of the hole at its widest point being strictly less than the size of the hole at its widest point, said opening being designed so as to allow the passage of the screwing tool and having a section which is less than the section of a human finger. |
| US09048546B2 |
Flat semi-transparent ground plane for reducing multipath reception and antenna system
Multipath reception by an antenna is reduced by mounting the antenna on a semi-transparent ground plane that has a controlled distribution of layer impedance over a central region and a peripheral region. The central region includes a continuous conductive segment on which the ground element of the antenna is disposed. The distribution of the layer impedance over the peripheral region is configured by multiple conductive segments electromagnetically coupled by lumped circuit elements. A semi-transparent ground plane can be fabricated by depositing a metal film on a dielectric substrate and etching grooves into the metal film to form a desired pattern of conductive segments. Lumped circuit elements can be fabricated as discrete devices, surface mount devices, and integrated circuit devices. Various semi-transparent ground planes can be configured for linearly-polarized and circularly-polarized radiation. |
| US09048542B2 |
Side-face radiation antenna and wireless communication module
Disclosed herein are a side-face radiation antenna and a wireless communication module. According to an embodiment of the present invention, there is provided the side-face radiation antenna including a via patch part formed at a side portion of a module substrate including laminated substrates to perform a side-face radiation, and formed by metal filled in a plurality of vias arranged at a predetermined interval in the side portion and connected, and a feed line part inserted between intermediate layers of the module substrate, and connected to the via at a center portion of the via patch part. In addition, there is provided the wireless communication module including the side-face radiation antenna. |
| US09048540B2 |
Multiple-antenna system for cellular communication and broadcasting
A reception method and apparatus for use in a multi-cell orthogonal frequency division multiple access (OFDMA) wireless system. In a unicast receive mode during a first receive time period, a first group of orthogonal frequency division multiplexing (OFDM) symbols is received by a mobile device from multiple of a plurality of antennas at a serving base station. In a single-frequency-network (SFN) receive mode during a second receive time period, a second group of OFDM symbols is received by the mobile device from one of a plurality of antennas at the serving base station. The transition between the first receive time period and the second receive time period occurs during a cyclic prefix or a cyclic postfix between OFDM symbols, and the plurality of antennas produce a first beam pattern during the unicast receive mode and a second beam pattern during the SFN receive mode. |
| US09048538B2 |
Antenna assembly and wireless communication device employing same
A wireless communication device includes a housing and an antenna assembly. The antenna assembly includes a base board, a feed member electronically connecting with the base board to carry an electrical current, and a radio member including a first radio portion, the first radio portion defining a first slot. The radiator couples with the feed member, inducing an electrical current in the first radio portion. The radio member is electronically connected to the base board through the metal housing, enabling the induced electrical current to flow through the first radio portion, the metal housing, and the base board to form a current loop. The induced electrical current flows through the first slot to excite a first resonance mode, enabling the antenna assembly to receive/transmit a first wireless signal. |
| US09048537B2 |
Antenna and proximity sensor structures having printed circuit and dielectric carrier layers
An electronic device may have a conductive housing with an antenna window. A display cover layer may be mounted on the front face of the device. Antenna and proximity sensor structures may include a dielectric support structure with a notch. The antenna window may have a protruding portion that extends into the notch between the display cover layer and the antenna and proximity sensor structures. The antenna and proximity sensor structures may have an antenna feed that is coupled to a first conductive layer by a high pass circuit and capacitive proximity sensor circuitry that is coupled to the first conductive layer and a parallel second conductive layer by a low pass circuit. The first conductive layer may be formed from a metal coating on the support structure. The second conductive layer may be formed from patterned metal traces in a flexible printed circuit. |
| US09048528B1 |
Antenna structure with strongly coupled grounding element
Antenna structures of electronic devices and methods of operating the electronic devices with the antenna structures are described. One antenna structure includes a ground plane, a radio frequency (RF) feed, a first antenna element coupled to the RF feed, a second antenna element coupled to the RF feed and a third antenna element coupled to the ground plane at a grounding point. The third antenna element is at least partially disposed between the first and second antenna elements to form a first coupling between the first antenna element and the third antenna element, a second coupling between the second antenna element and the third antenna element and a third coupling between the second antenna element and the third antenna element. |
| US09048527B2 |
Coaxial connector with capacitively coupled connector interface and method of manufacture
A connector with a capacitively coupled connector interface for interconnection with a mating portion with a sidewall. A connector body has an outer conductor coupling surface at an interface end, covered by an outer conductor dielectric spacer. The outer conductor coupling surface is dimensioned to seat, spaced apart from the sidewall by the outer conductor dielectric spacer, when the connector body and the mating portion are in an interlocked position. A releasable retainer may be provided, the releasable retainer dimensioned to secure the connector body and the mating portion in the interlocked position. |
| US09048526B2 |
Resonant circuit and antenna device
A resonant circuit and an antenna device achieve a low resonance frequency without increasing a coil size, and improve communication performance. In the resonant circuit, two coil-shaped conductors are arranged so as to be opposed to each other with a dielectric sheet interposed therebetween. The two coil-shaped conductors are, at the opposed portions thereof, coupled with a capacitance interposed therebetween, and wound so that electric currents flowing through the respective conductors trend in the same direction in a planar view. The opposed area in at least a portion of the outermost windings and/or innermost windings of the coil-shaped conductors is larger as compared with the opposed area in any other winding, and the respective ends of the conductors define power feeding units. |
| US09048521B2 |
Broadband waveguide
A broadband waveguide incorporates various reflection suppression techniques to reduce reflections in signals communicated thereby. The waveguide includes one or more filaments that each include a first and second end. A first matrix may be configured proximate the first end(s) while a second matrix may be configured proximate an intermediate location between the first and second ends. A damping material may cover a portion of the filament(s) that extends from the second matrix to the second end(s) (including the second end(s) themselves) and/or the second end(s) of the filament(s) is/are shaped to at least partially suppress reflections of the signal therefrom. When configured with multiple filaments, at least two of the filaments may have differing lengths that extend from the second matrix and also operate to at least partially suppress reflections of a signal. |
| US09048519B2 |
Filter
A filter includes a first printed circuit board (PCB), poles mounted on the first PCB, a second PCB located at a top of the first PCB, and caps mounted on the second PCB and covering the poles. Each the cap surrounds the corresponding pole. The cap and the pole cooperatively form a resonator. Each the first PCB and the second PCB is made of light, dielectric material with metallic layers. |
| US09048518B2 |
Transmission line RF applicator for plasma chamber
A transmission line RF applicator apparatus and method for coupling RF power to a plasma in a plasma chamber. The apparatus comprises an inner conductor and one or two outer conductors. The main portion of each of the one or two outer conductors includes a plurality of apertures that extend between an inner surface and an outer surface of the outer conductor. |
| US09048516B2 |
Safety device of battery temperature control system
To provide a safety device of a battery temperature control system for an EV or an HEV capable of preventing an electric shock due to the electrical conduction across terminals of batteries in the event of a vehicle collision.A safety device used in a temperature control system of a battery for a vehicle, including a first heat exchange unit (1) which includes a first heat exchange section (2) filled with a liquid-state heat medium into a pipe (3) and exchanging heat with a battery (B) by the heat medium, and a second heat exchange unit (20) which includes a second heat exchange section (21) heating or cooling the heat medium subjected to heat exchange in the first heat exchange section (2), wherein the heat medium existing in the first heat exchange section is discharged to the outside of the first heat exchange section, for example, under a predetermined condition such as a vehicle collision. |
| US09048512B2 |
Nanosized electrochemical dispersion for rechargeable alkaline zinc batteries
The present invention relates to a nanosized electrochemical dispersion comprising essentially modified silica sol and at least one additive; also a process of preparing nanosized electrochemical dispersion, wherein the process comprises step of loading at least one additive to metalate modified silica sol to obtain the dispersion; in addition a rechargeable alkaline storage zinc battery comprising nanosized electrochemical dispersion consisting of essentially modified silica sol and at least one additive; further a method of manufacturing a rechargeable alkaline storage zinc battery, wherein the method comprises steps of adding a nanosized electrochemical dispersion consisting essentially modified silica sol and at least one additive into a conventional alkaline storage zinc battery to obtain a rechargeable alkaline storage zinc battery; and further a process to prevent dissolution of zinc in a battery, wherein the process comprises addition of nanosized aqueous electrochemical dispersion comprising essentially modified silica sol and at least one additive to the battery, and preventing the dissolution of zinc electrode in the battery. |
| US09048508B2 |
Nonaqueous electrolytes and nonaqueous-electrolyte secondary batteries employing the same
A subject is to provide a nonaqueous electrolyte excellent in cycle performances such as capacity retention after cycling, output after cycling, discharge capacity after cycling, and cycle discharge capacity ratio, output characteristics, high-temperature storability, low-temperature discharge characteristics, heavy-current discharge characteristics, high-temperature storability, safety, high capacity, high output, high-current-density cycle performances, compatibility of these performances, etc. Another subject is to provide a nonaqueous-electrolyte secondary battery employing the nonaqueous electrolyte. The subjects have been accomplished with a nonaqueous electrolyte which contains a monofluorophosphate and/or a difluorophosphate and further contains a compound having a specific chemical structure or specific properties. |
| US09048503B2 |
Cable-type secondary battery and method for manufacturing the same
A method for manufacturing a cable-type secondary battery includes: preparing a first polarity current collector having a long and thin shape; forming at least two first polarity electrode active material layers on the first polarity current collector to be spaced apart from each other in the longitudinal direction; forming an electrolyte layer to surround the at least two first polarity electrode active material layers; forming at least two second polarity electrode active material layers on the electrolyte layer to be spaced apart from each other at positions corresponding to the first polarity electrode active material layers; forming an electrode assembly by surrounding the second polarity electrode active material layers with a second polarity current collector; surrounding the electrode assembly with a cover member; and bending the electrode assembly and the cover member into a serpentine configuration with the active regions spaced apart from one another. |
| US09048502B2 |
Lithium secondary battery and method for producing the same
A lithium secondary battery and a method for producing the lithium secondary battery. The lithium secondary battery includes a negative electrode 1 in which negative electrode mixture layers 2 and 3 that contain active material particles containing silicon and/or a silicon alloy and a binder are disposed on the surfaces of a current collector 4. A electrode body is formed by spirally winding, from inside to outside, a laminate body; and in an outer end portion of the negative electrode 1, the negative electrode mixture layers 2 and 3 have tapering portions 2a and 3a whose thicknesses decrease toward ends 2b and 3b of the negative electrode mixture layers 2 and 3; and oozing portions 2d and 3d mainly containing the binder are formed at the tips of the tapering portions 2a and 3a of the negative electrode mixture layers 2 and 3. |
| US09048501B2 |
Electrode for secondary battery, preparation thereof, and secondary battery and cable-type secondary battery comprising the same
A sheet-form electrode for a secondary battery includes a current collector; an electrode active material layer formed on one surface of the current collector; a porous organic-inorganic layer formed on the electrode active material layer and including inorganic particles and a polymer binder; and a first porous supporting layer formed on the porous organic-inorganic layer. The sheet-form electrode for a secondary battery has supporting layers on at least one surface thereof to exhibit surprisingly improved flexibility and prevent the release of the electrode active material layer from a current collector even if intense external forces are applied to the electrode, thereby preventing the decrease of battery capacity and improving the cycle life characteristic of the battery. |
| US09048500B2 |
Fuel cell system with controlled standby power
A fuel cell system includes an IG switch disposed between a 14V battery and a controller. The fuel cell system also includes a start switch disposed independently of the IG switch. Upon detection of the ON state of the start switch, the controller outputs an FC start instruction to an FC auxiliary device. Moreover, an FC inverter switch is disposed between the 14V battery and the FC auxiliary device. Through the function of the controller, power supply from the 14V battery to the FC auxiliary device is suspended for a period from when a wait time, which is predeterminedly set from the moment when the IG switch is turned ON, has elapsed to the moment when the start switch is turned ON, during a wait period between the moment when the IG switch is turned ON and the moment when the start switch is turned ON. |
| US09048498B2 |
Anode for a high-temperature fuel cell and production thereof
The substrate-supported anode for a high-temperature fuel cell comprises an at least three-layer anode laminate on a metallic substrate. Each of the layers of the anode laminate comprises yttria-stabilized zirconia and nickel, wherein the mean particle size of the nickel decreases from one layer to the next as the distance from the substrate increases. The last layer of the anode laminate, which is provided for contact with the electrolyte, has a root mean square roughness of less than 4 μm. The overall mean pore size of this layer is typically between 0.3 and 1.5 μm. Starting powders having a bimodal particle size distribution of yttria-stabilized zirconia and nickel-containing powder are used at least for the first and second layers of the anode laminate. The mean particle size of the nickel-containing powder is reduced from one layer to the next, whereby it is advantageously no more than 0.5 μm in the last layer of the anode laminate. |
| US09048493B2 |
Cathode active material, cathode including the cathode active material, and lithium battery including the cathode
A cathode active material, a cathode including the cathode active material, and a lithium battery including the cathode. The cathode active material includes a lithium composite oxide and a lithium titanium oxide, wherein the lithium titanium oxide includes titanium having an average oxidation number of 4-y (0 |
| US09048491B2 |
Lithium-ion secondary battery
In the invention, a lithium-ion secondary battery, in which a value obtained by dividing average 3% modulus strength of a separator by average 3% modulus strength of a negative electrode including a negative electrode active material layer containing silicon and silicon oxide as a main component is 0.079 or less, is used. |
| US09048490B2 |
Lithium ion secondary battery
A lithium ion secondary battery includes an electrode group formed by winding a positive electrode having a positive electrode current collector and a positive electrode active material layer, and a negative electrode having a negative electrode current collector and a negative electrode active material layer, with a separator interposed between the electrodes. A wound positive electrode current collector exposing section faces a wound negative electrode current collector exposing section with the separator interposed therebetween, thereby forming a heteropolar electrode current collector facing zone corresponding to at least one turn in the electrode group. A unipolar electrode current collector facing zone, in which adjacent portions of the wound current collector exposing section or the wound current collector exposing section face each other directly or with the separator interposed therebetween corresponds to at least one turn in the electrode group. |
| US09048486B2 |
Negative active material, method of preparing the negative active material, electrode including the negative active material, and lithium battery including the electrode
A negative active material including: a composite including a matrix comprising silicon oxide, silicon carbide, and carbon and silicon particles dispersed in the matrix; and a carbon coating film formed on a surface of the composite, wherein an intensity ratio of a SiC peak to a Si peak in an X-ray diffraction spectrum is 1 or more, a method of preparing the negative active material, a negative electrode including the negative active material, and a lithium battery including the electrode. |
| US09048485B2 |
Lithium-ion secondary battery, negative electrode for lithium-ion secondary battery, battery pack, electric vehicle, power storage system, electric tool, and electronic device
A lithium-ion secondary battery includes a positive electrode, a negative electrode containing an active material, and an electrolytic solution, in which the active material includes a core portion capable of occluding and releasing lithium ions, and a covering portion arranged on at least part of a surface of the core portion, in which the covering portion contains, as constituent elements, Si, O, and at least one element M1 selected from Li, C, Mg, Al, Ca, Ti, Cr, Mn, Fe, Co, Ni, Cu, Ge, Zr, Mo, Ag, Sn, Ba, W, Ta, Na, and K, and the atomic ratio y (O/Si) of O to Si is 0.5≦y≦1.8. |
| US09048484B2 |
Battery pack
A battery pack (13) is disposed at a lower part of a vehicular body. The battery pack (13) includes: a protrusion (27, 31) protruding in a vehicular upward direction and disposed at an upper face of the battery pack (13), and a dent portion (29) disposed at the upper face of the battery pack (13) and formed lower than the protrusion (27, 31), wherein an accessory (25) is disposed in the dent portion (29). |
| US09048483B2 |
Power supply device, power-supply-device separator, and power supply-device-equipped vehicle and electric power storage
A power supply device includes battery cells, separators, and fastening members. The plurality of battery cells have a rectangular-box exterior shape. The separators are interposed between the battery cells, which are arranged side by side. The fastening members securely hold a battery assembly of the battery cells and the separators, which are alternately arranged side by side. The surfaces of each of the battery cells is covered by an electrically insulating covering member. Each of the separators has recessed parts that form a plurality of gas-flowing paths between the battery cells so that cooling gas can flow along surfaces of these battery cells when this separator is interposed between these battery cells. Edge parts of the recessed part, which forms the gas-flowing paths, are rounded. |
| US09048472B2 |
Fuel cell shut-down procedure including vaporization phase
A shut-down procedure for an electricity delivery system comprising a fuel cell, the cell being fed with pure oxygen as oxidant and delivering an electrical voltage to an electrical power line. The electricity delivery system comprises a fuel gas circuit on the anode side, and a pure oxygen circuit on the cathode side. The shut-down procedure comprises the steps of an initial step during which the oxygen gas feed is interrupted, and an electrical consumption phase during which a hold current is drawn from the fuel cell until the pressure in the oxygen circuit reaches the water vapor pressure. |
| US09048470B2 |
Fuel directing reaction device for passive fuel cell
A fuel directing reaction device for a passive fuel cell comprises: a substrate, which has a first side and a second side opposite to the first side; a fuel reservoir, which is disposed on the first side of the substrate; a fuel introducing microfluidic channel portion, which is disposed on the first side of the substrate and connected with the fuel reservoir; a first rib array portion, which is disposed on the first side of the substrate, and connected with the fuel introducing microfluidic channel portion; a second rib array portion, which is disposed on the first side of the substrate, and connected with the first rib array; and a plurality of reaction holes, each of which is disposed on the open side of the V-shaped portion of the second ribs and extends through the substrate to connect the first side and the second side of the substrate. |
| US09048464B2 |
Vacuum chamber method to form polymer coatings on porous support
A bi-polar electrode having ion exchange polymers on opposite faces of a porous substrate is formed using a method that includes providing an electrode substrate with activated carbon layers on opposite faces of the electrode substrate, wherein said faces have an outer perimeter band void of the activated carbon layers. Gaskets are placed against the outer perimeter band of the electrode substrate void of activated carbon and the electrode substrate is clamped between two rigid plates to form a first airtight chamber on one side of the electrode substrate and a second airtight chamber on the opposite side of the electrode substrate. A first polymerizable monomer mixture having an anion exchange group is added into the first chamber and a second polymerizable monomer mixture having a cation exchange group is added into the second chamber. The first and second polymerizable monomer mixtures are then polymerized in an oven. |
| US09048462B2 |
Method of handling large format battery cells for high speed assembly
A battery pack assembly and a method of making the same. The method includes using lifters with a cammed conveyor delivery mechanism to facilitate edgewise stacking of generally planar battery cells. The lifter spacing and cam profile are designed in such a way as to orient individual battery cell tabs and cooling fin assemblies to keep them close together but without applying significant forces to the stackable components. Combining conveyor streams allows components to be processed in parallel and sequenced correctly onto a single conveyor. Use of lifter integrated conveyor belt with cams and guides for individual battery cell orientation and sequencing promotes high speed assembly without a need to change component directions. The use of high-speed component delivery high is compatible with allowing more component placement variation, while the edgewise orientation of the components being assembled permits the use of small manufacturing footprints. |
| US09048461B2 |
Methods of manufacturing OLED pixel and display device
A method of manufacturing an Organic Light Emitting Diode (OLED) pixel is disclosed. The method includes forming an anode and forming a pixel definition layer. The pixel definition layer includes a first sub-pixel area, a second sub-pixel area, a third sub-pixel area corresponding to the third sub-pixel, and a pixel spacing area. The first sub-pixel, the second sub-pixel and the third sub-pixel are separated from each other by the pixel spacing area. The method also includes coating a long-chain fatty acid ester layers on the pixel spacing area, the second sub-pixel area, and the third sub-pixel area, coating light emitting layers on the sub-pixel areas and on the long-chain fatty acid ester layers, and ashing the substrate and removing the long-chain fatty acid ester layers to form light emitting patterns. The method also includes forming a cathode. |
| US09048459B2 |
Display device and method of manufacturing the same
A display device and a method of manufacturing the same. The display device includes a substrate, an organic light emitting diode (OLED) arranged on the substrate, a thin film encapsulation layer arranged on the substrate to cover the OLED and including an inorganic material layer and an organic material layer, and an anti-reflection layer arranged on the thin film encapsulation layer and including a dielectric layer and a metal layer. |
| US09048457B2 |
Organic EL display device
An organic EL display device including a substrate, a transparent electrode, a luminescent layer, and a metal electrode layer in this order from a light emission side, a circularly polarizing plate disposed on the light emission side of the substrate, the circularly polarizing plate including a polarizing film and phase difference films that stacked on each other. The phase difference film includes a resin composition (A) containing polystyrene-based polymer having a syndiotactic structure and polyarylene ether, a ratio of the polystyrene-based polymer having the syndiotactic structure with respect to the polyarylene ether in the resin composition (A) is 65:35 to 55:45, being a weight ratio of (the polystyrene-based polymer having the syndiotactic structure) with respect to (the polyarylene ether), the phase difference film satisfies a relation Re450 |
| US09048456B2 |
Organic light-emitting diode
An organic light-emitting diode (OLED) having first, second and third sub-pixels of different colors includes: a substrate; first and second electrodes; an organic emission layer (OEL) between the electrodes including a first OEL in the first sub-pixel, a second OEL in the second sub-pixel, and a common third OEL in the first, second and third sub-pixels; a hole transport layer (HTL) between the first electrode and OEL; a hole injection layer (HIL) between the first electrode and HTL; an intermediate layer between the HTL and HIL; a first optical thickness auxiliary layer (OTAL) between the first OEL and third OEL in the first sub-pixel and including a first hole transporting compound and a cyano group-containing compound; and a second OTAL including a second hole transporting compound between the third OEL and HTL in the first sub-pixel, and between the second OEL and HTL in the second sub-pixel. |
| US09048452B2 |
Method for manufacturing transparent electrode of organic light emitting display device and organic light emitting display device using the transparent electrode
A method for manufacturing an organic light emitting display device includes mounting in a chamber a substrate where a transparent electrode is to be formed and a SnO member that is a source of forming the transparent electrode, injecting argon gas and oxygen into the chamber, and evaporating the SnO member to be deposited on the substrate. |
| US09048451B2 |
Laminated structure, display device and display unit employing same
A laminated structure which can reduce defect by preventing deposition failure or holes of an insulating film, manufacturing method, and a display unit that employ same are provided. The laminated structure as an anode for organic light-emitting devices is provided on a flat surface of a substrate. In the laminated structure, an adhesive layer made of ITO, a reflective layer made of silver or an alloy containing silver, and a barrier layer made of ITO are layered in this order from the substrate side. A cross sectional shape of the laminated structure in the laminated direction is a forward tapered shape. A sidewall face of the adhesive layer, the reflective layer, and the barrier layer is totally covered by an insulating film, and deposition failure or holes of the insulating film is prevented. A taper angle made by the sidewall face and the flat surface is preferably from about 10° to about 70°. The laminated structure can be used as a reflective electrode, a reflective film, or a wiring for a liquid crystal display. |
| US09048450B2 |
OLED device with a brightness distribution controlling means
The invention describes an OLED device (1) comprising an active layer (13) between a first electrode (11) and a second electrode (12); a contact means (3, 34, 35) for connecting the electrodes (11, 12) to a power supply (2); and a brightness distribution controlling means (20, 21, 21′, 24, 24′, 25, 25′), which brightness distribution controlling means (20, 21, 21′, 24, 24′, 25, 25′) comprises a plurality of openings (20), wherein an opening (20) extends through the second electrode (12) and the active layer (13) to expose an area (21, 21′) of the first electrode (11); and a plurality of selectively addressable current distribution lines (24, 24′, 25, 25′), wherein a current distribution line (24, 24′, 25, 25′) is arranged to extend between a contact means (3, 34, 35) and an exposed area (21, 21) such that an electrical connection can be established between the power supply (2) and the first electrode (11) to (specifically) regulate the brightness of the active layer (13) in the vicinity of the exposed area (21, 21′) accessed by that current distribution line (24, 24′, 25, 25′), and whereby the current distribution lines (24, 24′, 25, 25′) are electrically connected to each other by means of the first electrode (11). The invention further describes an OLED lighting arrangement (4) comprising such an OLED device (1), a line regulation means (22) for regulating the current flow through a selectively addressable current distribution line (24, 24′, 25, 25′) between the contact means (3) and the first electrode (11) to regulate the brightness of the active layer (13) in the vicinity of the exposed area (21, 21′) accessed by that current distribution line (24, 24′, 25, 25′); and a brightness distribution controller (41) for controlling the line activation means (22) to address a specific current distribution line (24, 24′, 25, 25′). The invention also describes a method of manufacturing an OLED device (1) with a brightness distribution controlling means (20, 21, 21′, 24, 24′, 25, 25′). The invention also describes a method of controlling the brightness of distribution of such an OLED device in such an OLED lighting arrangement. |
| US09048449B2 |
Organic light emitting display apparatus having a light conversion layer
An organic light emitting display apparatus includes a substrate, a light conversion layer on the substrate, the light conversion layer including an oxide semiconductor, a passivation layer covering the light conversion layer, a first electrode on the passivation layer, an intermediate layer on the first electrode, the intermediate layer including an organic emission layer, and a second electrode on the intermediate layer. |
| US09048447B2 |
Organic light emitting display device having auxiliary charge generation layer
An organic light emitting display device with improved lifespan is disclosed. The organic light emitting display device includes first and second electrodes facing each other on a substrate, at least two light emitting units formed between the first and second electrodes, an N-type charge generation layer and a P-type charge generation layer sequentially stacked between the light emitting units, and at least one auxiliary charge generation layer formed between at least any one of the P-type charge generation layer and the N-type charge generation layer and an emitting layer of the light emitting unit disposed on an upper or lower portion of the at least any one thereof and generating electrons and holes supplied to the emitting layer of the light emitting unit. |
| US09048446B2 |
Organic light emitting device
An organic light emitting device is described. The organic light emitting device includes: a substrate; a first electrode on the substrate; an emission layer on the first electrode; a second electrode on the emission layer; and an exciton blocking layer between the first electrode and the emission layer, in which a LUMO energy level of the exciton blocking layer is higher than a LUMO energy level of the emission layer. |
| US09048442B2 |
Composition containing a metal complex and organic compound, and light-emitting element using said compound
Disclosed is a composition containing a metal complex and an organic compound, wherein the difference between the absolute value of the energy level of the lowest unoccupied molecular orbit of said metal complex and the absolute value of the lowest unoccupied molecular orbit of said organic compound, as calculated with a computational technique, is less than 0.40 eV. |
| US09048440B2 |
Material for organic electroluminescence device and electroluminescence device
Provided is a material for organic electroluminescence device containing (a) a phosphorescent metal complex containing a monoanionic bidentate ligand and a metal having an atomic weight of 40 or greater, wherein the monoanionic bidentate ligand is represented by the following formula (A): wherein, each of E1a, E1d, E1e, E1f, E1k, E1l, E1p, and E1q independently represents a carbon atom or a hetero atom, each of Z1, Z2, and Z3 independently represents an aromatic ring or aromatic heterocycle, the aromatic ring or aromatic heterocycle may have a substituent, and a skeleton represented by the formula (A) has, in total, a 18π electron structure, and the bidentate ligand represented by the formula (A) may be coupled to another ligand to form a tridentate or higher-dentate ligand; and (b) a structural isomer represented by the same chemical formula as that of the phosphorescent metal complex (a) but different sterically in a coordination method of the ligand, wherein the structural isomer (b) is contained in an amount of 0.05 mass % or greater but not greater than 5 mass % relative to the phosphorescent metal complex (a). |
| US09048438B2 |
Tetraazaperopyrene compounds and their use as n-type semiconductors
A tetraazaperopyrene compound of formula (I): wherein: R1, R2, R3, R4, R5, R6, R7, R8 at each occurrence, independently are selected from H, Cl and Br, with the proviso that at least one of R1, R2, R3, R4, R5, R6, R7 and R8 is Cl or Br, R9, R10, at each occurrence, independently are selected from H, a C1-30 alkyl group, a C1-30 haloalkyl group, a C6-14 aryl group, a heteroaryl group having 5 to 14 ring atoms, and a C7-20 arylalkyl group, wherein aryl, heteroaryl and arylalkyl can be optionally substituted with one or more halogen, C1-4 haloalkyl, —CN, —NO2, —CHO, —COOH, —CONH2, —CO(C1-14 alkyl), —COO(C1-14 alkyl), —CONHC(C1-14 alkyl) and —CON(C1-14 alkyl)2 groups. |
| US09048435B2 |
Organic semiconducting materials and organic component
An organic semiconductive material comprising at least one matrix material and at least one doping material, wherein the doping material is selected from an organic compound and wherein the matrix material is selected from an diamine compound, also an organic component and a mixture for producing a doped semiconductor layer. |
| US09048434B2 |
Organic electroluminescent element, display device and lighting device
Disclosed is an organic electroluminescent device having long life, while exhibiting high luminous efficiency. Also disclosed are an illuminating device and a display, each using such an organic electroluminescent device. In the organic electroluminescent device, a compound represented by the general formula (A) which is suitable as a host material for a phosphorescent metal complex is used at least in one sublayer of a light-emitting layer. |
| US09048433B2 |
Conjugated polymers
The invention relates to novel polymers containing one or more thieno[3,2-b]thiophene-2,5-dione and/or furo[3,2-b]furan-2,5-dionerepeating units or their thioketone derivatives, monomers and methods for their preparation, their use as semiconductors in organic electronic (OE) devices, especially in organic photovoltaic (OPV) devices, and to OE and OPV devices comprising these polymers. |
| US09048432B2 |
Perylenebisimide-polyester blend
The present invention provides a perylenebisimide-polyester copolymer and a transesterification process for the preparation thereof. The perylenebisimide-polyester copolymer prepared is useful in organic light emitting diodes, solar cells and such other photovoltaic applications. |
| US09048428B2 |
Enabling communication between source and target mail transfer agents
A system is provided for enabling a source MTA to communicate with a target MTA via an SMTP proxy using SMTP commands for transmitting email messages in a networked environment. An email message may be received by a source mail transport agent (MTA) and the source MTA may route the incoming email message to a target MTA via an SMTP proxy. The SMTP proxy may serve as an intermediary proxy server for enabling the source MTA to communicate with an external and internal target MTA. The SMTP proxy may connect to a target MTA via a connection command, and the SMTP proxy may implement custom SMTP commands to communicate additional information about the source MTA to the target MTA. The system may additionally enable the SMTP proxy to perform actions designated by the SMTP commands and to communicate the result of the SMTP proxy's actions back to the source MTA. |
| US09048426B2 |
Piezoelectric sheet, method for manufacturing piezoelectric sheet, and manufacturing apparatus
A specific region of a polylactic acid sheet is heated by a microwave. To allow the polylactic acid sheet to exhibit piezoelectricity in the thickness direction of the polylactic acid sheet, a high voltage is applied to the heated polylactic acid sheet in the thickness direction of the polylactic acid sheet, and thereby the screw axes of at least a part of the polylactic acid molecules are relatively aligned with the thickness direction. Then the polylactic acid sheet is rapidly cooled, and thereby the polylactic acid molecules are immobilized. The same step is executed for other regions of the polylactic acid sheet, and thereby piezoelectricity is imparted to a wide area of the polylactic acid sheet in the thickness direction. The resultant piezoelectric sheet is capable of exhibiting a high piezoelectricity in the thickness direction. |
| US09048425B2 |
Bipolar multistate nonvolatile memory
Embodiments generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching capacity by using multiple layers of variable resistance layers. In one embodiment, the resistive switching element comprises at least three layers of variable resistance materials to increase the number of logic states. Each variable resistance layer may have an associated high resistance state and an associated low resistance state. As the resistance of each variable resistance layer determines the digital data bit that is stored, the multiple variable resistance layers per memory element allows for additional data storage without the need to further increase the density of nonvolatile memory devices. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. |
| US09048424B2 |
Semiconductor device and method of manufacturing the same
The method of manufacturing a semiconductor device selectively forms a resist film on the multilayer gate film and the gate side wall insulating film extending on the semiconductor substrate. An upper part of the gate side wall insulating film and the hard mask film selectively are removed by etching using the resist film as a mask so as to expose a surface of the metal film. the metal film and the barrier metal film adjoining the metal film are removed, by wet etching. After the removal of the resist film, embedding a space formed by removal of the metal film and the barrier metal film and depositing a pre-metal dielectric to a level higher than an upper surface of the remaining hard mask film. A top part of the pre-metal dielectric is planarized by CMP using the remaining hard mask film as a stopper. |
| US09048420B2 |
Power generation unit, electronic apparatus, transportation device, and method of controlling power generation unit
A power generation unit includes a beam (a deforming member) having a piezoelectric element and deforming while switching a deformation direction, an inductor electrically connected to the piezoelectric element, a switch disposed between the piezoelectric element and the inductor, a memory (a storage section) adapted to store switching period information (information of a characteristic vibration period of the beam), and a control circuit (a control section) adapted to control one of a timing at which the switch is set to a conductive state and a timing at which the switch is set to a nonconductive state in accordance with the switching period information stored in the memory. |
| US09048419B2 |
Piezo devices with air-spaced cantilever
An arrangement that converts mechanical energy into electrical energy employs a base member and a cantilever member coupled thereto. The cantilever member has two piezoelectric layers with an air space therebetween. A proof mass is coupled to the cantilever member distal from the base member. The first and second piezoelectric layers are formed of lead zirconate titanate (PZT), and the output voltage of the cantilever member is proportional to the height of the air gap. A piezoresistive accelerometer that is useful for measuring mechanical vibration has a suspension beam and a piezoresistive layer be separated from the suspension beam. A method of monitoring an acoustic vibration utilizes a piezoresistive element having an air-spaced cantilever formed of a piezoelectric material in the vicinity of the system to be monitored and obtains an alternating voltage form the air-spaced cantilever of the piezoresistive element. |
| US09048418B2 |
Sensor element, sensor device, and electronic apparatus
A sensor element includes a base part, a detection vibrating arm extended from the base part, and detection parts that are provided on the detection vibrating arm and detect flexural vibration of the detection vibrating arm, the detection parts each have a first electrode layer, a second electrode layer provided at an opposite side to the detection vibrating arm with respect to the first electrode layer, and a piezoelectric layer provided between the first electrode layer and the second electrode layer, and the detection parts have parts provided over boundary parts between the detection vibrating arm and the base part and the parts bend or curve to extend in a direction including a direction component orthogonal to an extension direction of the detection vibrating arm along side surfaces of the detection vibrating arm and the base part. |
| US09048416B2 |
Memory element and memory apparatus
According to some aspects, a layered structure includes a memory layer, a magnetization-fixed layer, and a tunnel insulating layer. The memory layer has magnetization perpendicular to a film face in which a direction of the magnetization is configured to be changed according to information by applying a current in a lamination direction of the layered structure. The magnetization-fixed layer has magnetization parallel or antiparallel to the magnetization direction of the memory layer and comprises a laminated ferripinned structure including a plurality of ferromagnetic layers and one or more non-magnetic layers, and includes a layer comprising an antiferromagnetic material formed on a first ferromagnetic layer of the plurality of ferromagnetic layers and situated between the first ferromagnetic layer and the non-magnetic layer. The tunnel insulating layer is located between the memory layer and the magnetization-fixed layer. |
| US09048412B2 |
Magnetic memory devices including magnetic layers separated by tunnel barriers
A magnetic memory device may include a first vertical magnetic layer, a non-magnetic layer on the first vertical magnetic layer, and a first junction magnetic layer on the non-magnetic layer, with the non-magnetic layer being between the first vertical magnetic layer and the first junction magnetic layer. A tunnel barrier may be on the first junction magnetic layer, with the first junction magnetic layer being between the non-magnetic layer and the tunnel barrier. A second junction magnetic layer may be on the tunnel barrier with the tunnel barrier being between the first and second junction magnetic layers, and a second vertical magnetic layer may be on the second junction magnetic layer with the second junction magnetic layer being between the tunnel barrier and the second vertical magnetic layer. |
| US09048410B2 |
Memory devices comprising magnetic tracks individually comprising a plurality of magnetic domains having domain walls and methods of forming a memory device comprising magnetic tracks individually comprising a plurality of magnetic domains having domain walls
A method of forming a memory device having magnetic tracks individually comprising a plurality of magnetic domains having domain walls, includes forming an elevationally outer substrate material of uniform chemical composition. The uniform composition material is partially etched into to form alternating regions of elevational depressions and elevational protrusions in the uniform composition material. A plurality of magnetic tracks is formed over and which angle relative to the alternating regions. Interfaces of immediately adjacent of the regions individually form a domain wall pinning site in individual of the magnetic tracks. Other methods, including memory devices independent of method, are disclosed. |
| US09048405B2 |
Light emitting device
The light emitting device comprising a light emitting element; and a wavelength converting member having a first face and a second face, in which light emitted from the light emitting element enters in through the first face, and a part of the second face serves as a light emitting face, wherein the light emitting element further comprises a reflection control structure around the light emitting face of the second face, and the reflection control structure comprises a reflection film on the wavelength converting member and an anti-reflection film on the reflection film. |
| US09048404B2 |
Thin flat solid state light source module
Thin, flat solid state light source device and methods for manufacturing is described. LED chips and their circuit boards are mounted on a thermal conductive substrate. The LED chips are surrounded with a flat layer of reflecting material which may embed the circuit boards. The LED chips and the reflecting layer is then topped with a layer of diffusion material and a layer of cover material. |
| US09048400B2 |
Light-emitting device with a wavelength converting layer and method for manufacturing the same
A light-emitting device (1) includes a base (10), a light-emitting element (11) placed on the base (10), and a wavelength converting layer (12) that covers the light-emitting element (11). The wavelength converting layer (12) includes a wavelength converting portion (13) that converts a wavelength of light from the light-emitting element (11), and a light guide portion (14) made of a light-transmitting material, and the light guide portion (14) extends from a light-emitting element (11) side to a light extraction side of the wavelength converting layer (12). Consequently, it is possible to provide a light-emitting device that can be miniaturized and reduced in thickness easily and can prevent a decrease in the light extraction efficiency. |
| US09048391B2 |
Light emitting diode package
A light emitting diode package includes a package body having a cavity, a light emitting diode chip having a plurality of light emitting cells connected in series to one another, a phosphor converting a frequency of light emitted from the light emitting diode chip, and a pair of lead electrodes. The light emitting cells are connected in series between the pair of lead electrodes. |
| US09048388B2 |
Multi-layer thermoelectric module and method for fabricating the same
A multi-layer thermoelectric module and a fabricating method thereof are provided. The module includes two thermoelectric element sets and a metal electrode set, in which the thermoelectric element sets are corresponding to different operating temperature ranges. Each thermoelectric element set includes a thermoelectric unit, an interfacial adhesion layer, a diffusion barrier layer and a high melting-point metal layer. In the method, the thermoelectric unit, the interfacial adhesion layer, and the diffusion barrier layer are sequentially formed on the thermoelectric unit. Then, two high melting-point metal layers are formed respectively on the electrode layers of the metal electrode set. Thereafter, a solid-liquid interdiffusion jointing step is conducted to use a low melting-point metal layer to react with the high melting-point metal layer for producing an intermetallic compound layer jointing the thermoelectric element set with the metal electrode set, and the low melting-point metal layer is consumed completely. |
| US09048384B2 |
Steam generation apparatus
A steam generation apparatus 1 including a high-temperature pipe 10 disposed extending horizontally and through which a high-temperature fluid passes; low-temperature pipes 20 disposed on both sides of the high-temperature pipe 10 in a horizontal direction and through which a low-temperature fluid having a temperature lower than that of the high-temperature fluid passes; and a thermoelectric module 30 interposed between the high-temperature pipe 10 and each of the low-temperature pipes 20 for generating electrical power using a temperature difference between the high-temperature pipe 10 and the low-temperature pipes 20, the low-temperature pipes 20 being configured such that the supplied low-temperature fluid in a liquid form is turned into steam due to heat exchange with the high-temperature fluid and is discharged from an upper portion of the low-temperature pipes 20. |
| US09048379B2 |
Light-emitting devices
A light-emitting device of an embodiment of the present application comprises a semiconductor layer sequence provided with a first main side, a second main side, and an active layer; a beveled trench formed in the semiconductor layer sequence, having a top end close to the second main side, a bottom end, and an inner sidewall connecting the top end and the bottom end. In the embodiment, the inner sidewall is an inclined surface. The light-emitting device further comprises a dielectric layer disposed on the inner sidewall of the beveled trench and the second main side; a first metal layer formed on the dielectric layer; a carrier substrate; and a first connection layer connecting the carrier substrate and the semiconductor layer sequence. |
| US09048374B1 |
Method for manufacturing an interdigitated back contact solar cell
A method for manufacturing an interdigitated back contact solar cell, comprising steps of: (a) providing a doped silicon substrate; (b) forming a first silicon dioxide layer on the front surface and the rear surface; (c) depositing a boron-containing doping paste on the first silicon dioxide layer of the rear surface in a first pattern; (d) heating the silicon substrate; (e) removing the first silicon dioxide layer; (f) forming a second silicon dioxide layer on the front surface and the rear surface; (g) depositing a phosphorus-containing doping paste on the second dioxide layer of the rear surface in a second pattern; (h) heating the silicon substrate; and (i) removing the second silicon dioxide layer from the silicon substrate, wherein the first pattern and the second pattern collectively form an interdigitated pattern. |
| US09048371B2 |
Semiconductor devices including avalanche photodetector diodes integrated on waveguides and methods for fabricating the same
Semiconductor devices and methods for fabricating semiconductor devices are provided. In one example, a method for fabricating a semiconductor device includes etching a trench into a waveguide layer in a detector region of a semiconductor substrate. An avalanche photodetector diode is formed about the trench. Forming the avalanche photodetector diode includes forming a multiplication region in the waveguide layer laterally adjacent to the trench. An absorption region is formed at least partially disposed in the trench. |
| US09048369B2 |
Electroluminescence display device
There is provided an EL display device of a color filter system which obtains sufficient brightness and contrast while making it difficult to generate a color mixture even if pixels become fine. An EL display device 100 according to the present invention includes a first substrate 1, a circuit layer 2 formed on the first substrate 1, a color selection reflection layer 11 formed in an upper layer of the circuit layer 2, lower electrodes 5 formed in an upper layer of the color selection reflection layer 11, a white light emission EL layer 7 formed in an upper layer of the lower electrodes 5, an upper electrode 8 formed in an upper layer of the EL layer 7, and a sealing layer 9 formed in an upper layer of the upper electrode 8. |
| US09048368B2 |
Light emitting device
A light emitting device includes a conductive support member, and first and second light emitting structures. A channel layer is provided around lower portions of the first and second light emitting structures. A first electrode is coupled to a first conductive first semiconductor layer of the first light emitting structure, and a second electrode is coupled to a second semiconductor layer of the first light emitting structure. A third electrode is coupled to a third semiconductor layer of the second light emitting structure, and a fourth electrode is coupled to a fourth semiconductor layer of the second light emitting structure. A first connection part is coupled to the first electrode and the conductive support member, and a second connection part is coupled to the second and third electrodes. A third connection part is coupled to the fourth electrode and has one end provided on the channel layer. |
| US09048364B2 |
Nitride semiconductor structure and semiconductor light emitting device including the same
A nitride semiconductor structure and a semiconductor light emitting device including the same are revealed. The nitride semiconductor structure mainly includes a stress control layer disposed between a light emitting layer and a p-type carrier blocking layer. The p-type carrier blocking layer is made from AlxGa1−xN (0 |
| US09048362B2 |
Semiconductor light emitting device
According to one embodiment, a semiconductor light emitting device includes n-type and p-type semiconductor layers containing a nitride semiconductor and a light emitting layer. The emitting layer includes a barrier layer containing III group elements, and a well layer stacked with the barrier layer and containing III group elements. The barrier layer is divided into a first portion on an n-type semiconductor layer side and a second portion on a p-type semiconductor layer side, an In composition ratio in the III group elements of the second portion is lower than that of the first portion. The well layer is divided into a third portion on an n-type semiconductor layer side and a fourth portion on a p-type semiconductor layer side, an In composition ratio in the III group elements of the fourth portion is higher than that of the third portion. |
| US09048354B2 |
Methods of forming a through via structure
Methods of manufacturing an integrated circuit device including a through via structure are provided. The methods may include forming an isolation trench through a substrate to form an inner substrate, which is enclosed by the isolation trench and forming an insulating layer in the isolation trench and on a surface of the substrate. The methods may also include forming a hole, which is spaced apart from the isolation trench and passes through a portion of the insulating layer formed on the surface of the substrate and the inner substrate and forming a conductive layer in the hole and on the insulating layer formed on the surface of the substrate. The methods may be used to manufacture image sensors. |
| US09048353B2 |
Photovoltaic DC/DC micro-converter
A photo-voltaic (PV) power generating system and a control system for PV array string-level control and PV modules serially-connected into strings of PV modules. The system includes plural parallel strings of serially-connected power-generating photovoltaic modules that form a PV array, DC/DC micro-converters that are coupled to a DC voltage buss and to the output of a corresponding photovoltaic module or to the output of a string of photovoltaic modules; a gating or central inverter; and a control system. The micro-converters are structured and arranged to include at least one of: an active clamp device, a ground fault detection device, and a fractional power converter that injects power in series or in parallel with voltage or current from the power-generating portion onto the DC buss. |
| US09048352B2 |
Solid image-pickup device with flexible circuit substrate
A solid image pick-up device has a plurality of light sensors arranged on its image pick-up area of a semiconductor substrate. A transparent plate having the same shape and size as the semiconductor substrate is bonded to the surface of the semiconductor substrate. A plurality of bonding pads are formed on the surface of the semiconductor substrate and arranged around the image pick-up area. Further, a plurality of through holes are formed through the semiconductor substrate, extending from the lower surfaces of the bonding pads to the back surface of the semiconductor substrate. An insulating film is attached to the inner surface of each of the through holes, while another insulating film is attached to the back surface of the semiconductor substrate. |
| US09048351B2 |
LED die, method for manufacturing the LED die and automobile lamp having the LED die
An LED die includes a transparent substrate, an N-type layer, an active layer and a P-type layer successively arranged on a first surface of the transparent substrate. A part of the N-type layer is exposed. The LED die further includes an electrode structure arranged on the P-type layer and the exposed surface of the N-type layer. A light outputting surface is formed on a second surface of the transparent substrate. The light outputting surface is a smoothly concave and arc-shaped surface. An LED automobile lamp with the LED die and a method for manufacturing the LED die are also provided. The light outputting surface of the LED die directly faces a lens of the LED automobile lamp. |
| US09048348B2 |
Method of separating substrate and method of fabricating semiconductor device using the same
A method of fabricating a semiconductor device, the method including: forming a first mask pattern including a masking region and an open region on a substrate; forming a sacrificial layer to cover the substrate and the first mask pattern; patterning the sacrificial layer to form a seed layer and to expose the first mask pattern; forming a second mask pattern on the exposed first mask pattern; forming an epitaxial layer on the seed layer and the second mask pattern, and forming a void between the second mask pattern and the epitaxial layer; and separating the substrate from the epitaxial layer. |
| US09048347B2 |
Epitaxial structure including carbon nanotube layer in grooves
An epitaxial structure is provided. The epitaxial structure comprises a substrate, a carbon nanotube layer and an epitaxial layer stacked in that order. The substrate has an epitaxial growth surface and defines a plurality of first grooves and first bulges on the epitaxial growth surface. The carbon nanotube layer covers the epitaxial growth surface, wherein a first part of the carbon nanotube layer is attached on top surface of the first bulges, and a second part of the carbon nanotube layer is attached on bottom surface and side surface of the first grooves. The epitaxial layer is formed on the epitaxial growth surface, and the carbon nanotube layer is sandwiched between the epitaxial layer and the substrate. |
| US09048346B2 |
Semiconductor light emitting device including a metal nitride buffer layer and fabrication method thereof
Provided are embodiments of a light emitting device and fabrication methods thereof. The light emitting device can include a buffer layer provided between a substrate and a semiconductor layer incorporating a high fusion point metal. In a fabrication method of the light emitting device, the buffer layer incorporating a high fusion point metal can be formed on a substrate, and a semiconductor layer can be formed on the buffer layer. |
| US09048343B2 |
Semiconductor light emitting device and method of manufacturing the same
A method of manufacturing a semiconductor light emitting device, includes forming a light emitting structure on a growth substrate. The light emitting structure includes a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer. A support substrate having one or more protrusions formed on one surface thereof is prepared. The one or more protrusions formed on the one surface of the support substrate are attached to one surface of the light emitting structure. The growth substrate is separated from the light emitting structure. |
| US09048342B2 |
Semiconductor device stacked structure
A semiconductor device stacked structure is disclosed, which includes multiple semiconductor devices and at least one reinforcing structure. The semiconductor devices are stacked on one another. At least one semiconductor device has at least one through silicon via. Each reinforcing structure surrounds a corresponding one of the at least one through silicon via and is electrically insulated from the semiconductor devices. The at least one reinforcing structure includes multiple reinforcing elements and at least one connecting element. Each reinforcing element is disposed between the semiconductor devices. Vertical projections of the reinforcing elements on a plane define a close region, and a projection of the at least one through silicon via on the plane is located within the close region. The connecting element is located in an overlapping region of the vertical projections of the reinforcing elements on the plane, for connecting the reinforcing elements to form the reinforcing structure. |
| US09048341B2 |
Integrated circuit capacitor and method
An example of a capacitor includes a series of ridges and trenches and an interconnect region on the integrated circuit substrate. The series of ridges and trenches and the interconnect region have a capacitor foundation surface with a serpentine cross-sectional shape on the series of ridges and trenches. Electrical conductors are electrically connected to the electrode layers from the interconnect region for access to the electrode layers of the capacitor assembly. |
| US09048335B2 |
Method of fabricating multiple gate stack compositions
An integrated circuit having multiple different device gate configurations and a method for fabricating the circuit are disclosed. An exemplary embodiment of forming the circuit includes receiving a substrate having a first device region, a second device region, and a third device region. A first interfacial layer is formed over at least a portion of each of the first device region, the second device region, and the third device region. The first interfacial layer is patterned to define a gate stack within the third device region. A second interfacial layer is formed over at least a portion of the second device region. The second interfacial layer is patterned to define a gate stack within the second device region. A third interfacial layer is formed over at least a portion of the first device region. The third interfacial layer defines a gate stack within the first device region. |
| US09048333B2 |
Isolation rings for packages and the method of forming the same
A device includes a first package component, and a second package component underlying, and bonded to, the first package component. A molding material is disposed under the first package component and molded to the first and the second package components, wherein the molding material and the first package component form an interface. An isolation region includes a first edge, wherein the first edge of the isolation region contacts a first edge of the first package component and a first edge of the molding material. The isolation has a bottom lower than the interface. |
| US09048332B2 |
Semiconductor device manufacturing method and semiconductor mounting substrate
A semiconductor device manufacturing method includes: a first-process for placing, on a first-substrate on which traces and first-electrodes are formed, each of the first-electrodes being connected to one of traces, a second-substrate in which through-holes corresponding to the first-electrodes and relay-members are disposed, each of the relay-members being formed of solder, penetrating through one of the through-holes, and projecting from both ends of the one of the through-holes, so that the first-electrodes are aligned with the through-holes in a plan view; a second-process for melting the relay-members so that the relay-members are connected to the first-electrodes, after the first-process; and a third-process for placing a semiconductor substrate on which a second-electrodes corresponding to the first-electrodes are formed on a side opposite to the first-substrate across the second-substrate, after the second-process, to connect the first-electrodes and the second-electrodes to each other via the relay-members. |
| US09048331B2 |
Method of manufacturing semiconductor device
A method of manufacturing a semiconductor chip includes forming a masking member including an opening on a wiring substrate including a chip mounting region so as to align the opening with the chip mounting region, forming an uncured sealing resin on at least the chip mounting region of the wiring substrate, wherein a support film is formed on the uncured sealing resin, removing the support film from the uncured sealing resin, removing the masking member from the wiring substrate so that the uncured sealing resin remains on the chip mounting region, and flip-chip mounting a semiconductor chip onto the chip mounting region with the uncured sealing resin arranged in between. The uncured sealing resin has a higher temperature when removing the masking member than when removing the support film. |
| US09048330B2 |
Three-dimensional gate-wrap-around field-effect transistor
A three-dimensional Gate-Wrap-Around Field-Effect Transistor (GWAFET). The GWAFET includes a substrate of III-V semiconductor material. The GWAFET further includes one or more channel layers with a gate wrapped around these one or more channel layers. Additionally, the GWAFET includes a barrier layer residing on the top channel layer with a layer of doped III-V semiconductor material residing on each end of the barrier layer. A source and drain contact are connected to the layer of doped III-V semiconductor material as well as to the multiple channels in the embodiment with the GWAFET including multiple channel layers. By having such a structure, integration density is improved. Furthermore, electrostatic control is improved due to gate coupling, which helps reduce standby power consumption. Furthermore, by using III-V semiconductor material as opposed to silicon, the current drive capacity is improved. |
| US09048327B2 |
Microcrystalline semiconductor film, method for manufacturing the same, and method for manufacturing semiconductor device
An embodiment of the present invention is a microcrystalline semiconductor film having a thickness of more than or equal to 70 nm and less than or equal to 100 nm and including a crystal grain partly projecting from a surface of the microcrystalline semiconductor film. The crystal grain has an orientation plane and includes a crystallite having a size of 13 nm or more. Further, the film density of the microcrystalline semiconductor film is higher than or equal to 2.25 g/cm3 and lower than or equal to 2.35 g/cm3, preferably higher than or equal to 2.30 g/cm3 and lower than or equal to 2.33 g/cm3. |
| US09048326B2 |
Thin film transistor substrate and method of manufacturing the same
A thin film transistor substrate includes a substrate; a gate electrode on the substrate; a semiconductor pattern on the gate electrode; a source electrode on the semiconductor pattern; a drain electrode on the semiconductor pattern and spaced apart from the source electrode; a pixel electrode connected to the drain electrode; and a common electrode partially overlapped with the pixel electrode. The semiconductor pattern is in a same layer of the thin film transistor substrate as the pixel electrode and has an electrical property different from an electrical property of the pixel electrode. |
| US09048324B2 |
Semiconductor device
A highly reliable semiconductor device the yield of which can be prevented from decreasing due to electrostatic discharge damage is provided. A semiconductor device is provided which includes a gate electrode layer, a first gate insulating layer over the gate electrode layer, a second gate insulating layer being over the first gate insulating layer and having a smaller thickness than the first gate insulating layer, an oxide semiconductor layer over the second gate insulating layer, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer. The first gate insulating layer contains nitrogen and has a spin density of 1×1017 spins/cm3 or less corresponding to a signal that appears at a g-factor of 2.003 in electron spin resonance spectroscopy. The second gate insulating layer contains nitrogen and has a lower hydrogen concentration than the first gate insulating layer. |
| US09048323B2 |
Semiconductor device
A transistor that is to be provided has such a structure that a source electrode layer and a drain electrode layer between which a channel formation region is sandwiched has regions projecting in a channel length direction at lower end portions, and an insulating layer is provided, in addition to a gate insulating layer, between the source and drain electrode layers and a gate electrode layer. In the transistor, the width of the source and drain electrode layers is smaller than that of an oxide semiconductor layer in the channel width direction, so that an area where the gate electrode layer overlaps with the source and drain electrode layers can be made small. Further, the source and drain electrode layers have regions projecting in the channel length direction at lower end portions. |
| US09048318B2 |
Dual material finFET on same substrate
A method of fabricating a semiconductor device including proving a substrate having a germanium containing layer that is present on a dielectric layer, and etching the germanium containing layer of the substrate to provide a first region including a germanium containing fin structure and a second region including a mandrel structure. A first gate structure may be formed on the germanium containing fin structures. A III-V fin structure may then be formed on the sidewalls of the mandrel structure. The mandrel structure may be removed. A second gate structure may be formed on the III-V fin structure. |
| US09048316B2 |
Flash memory structure and method of forming the same
Embodiments of mechanisms of a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a word line cell disposed over the substrate. The semiconductor device further includes a memory gate disposed over the substrate and adjacent to the word line cell and a spacer on a sidewall of the memory gate. The spacer and the word line cell are at opposite sides of the memory gate. In addition, an angle between a top surface of the memory gate and a sidewall of the memory gate is in a range from about 75° to about 90°. |
| US09048315B2 |
Semiconductor device
A semiconductor device includes a pillar-shaped silicon layer and a first-conductivity-type diffusion layer in an upper portion of the pillar-shaped silicon layer. A sidewall having a laminated structure including an insulating film and polysilicon resides on an upper sidewall of the pillar-shaped silicon layer. A top of the polysilicon of the sidewall is electrically connected to a top of the first-conductivity-type diffusion layer and has the same conductivity as the diffusion layer. |
| US09048314B2 |
Field effect transistor with narrow bandgap source and drain regions and method of fabrication
A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode. |
| US09048312B2 |
Semiconductor device and method for forming the same
A semiconductor device including a substrate having an active region is disclosed. A field-plate region and a bulk region are in the active region, wherein the bulk region is at a first side of the field-plate region. At least one trench-gate structure is disposed in the substrate corresponding to the bulk region. At least one source-doped region is in the substrate corresponding to the bulk region, wherein the source-doped region surrounds the trench-gate structure. A drain-doped region is in the substrate at a second side opposite to the first side of the field-plate region, wherein an extending direction of length of the trench-gate structure is perpendicular to that of the drain-doped region as viewed from a top view perspective. |
| US09048307B2 |
Method of manufacturing a semiconductor device having sequentially stacked high-k dielectric layers
A semiconductor device having reduced leakage current and increased capacitance without increasing an equivalent oxide thickness (EOT) can be manufactured by a method that includes providing a substrate having a dummy gate pattern; forming a gate forming trench by removing the dummy gate pattern; forming a stacked insulation layer within the gate forming trench, wherein the forming of the stacked insulation layer includes forming a first high-k dielectric layer, forming a second high-k dielectric layer by performing heat treatment on the first high-k dielectric layer, and, after the heat treatment, forming a third high-k dielectric layer on the second high-k dielectric layer, the third high-k dielectric layer having a higher relative permittivity than the second high-k dielectric layer and having a dielectric constant of 40 or higher; and forming a gate electrode within the gate forming trench. |
| US09048304B2 |
Semiconductor device and method of manufacturing semiconductor device
In a semiconductor device, a first-layer includes a group-III nitride semiconductor of a first conduction type. A second-layer includes a group-III nitride semiconductor of a second conduction type on a first surface of the first layer. A third-layer includes an Al-containing group-III nitride semiconductor on a first region of a surface of the second layer. A gate electrode has one end above a surface of the third-layer and has the other end within the first-layer via the second-layer. The gate electrode is insulated from the first- to third-layers. A first electrode is connected to the third-layer. A second electrode is connected to a second region of the surface of the second-layer. A third electrode is provided above a second surface of the first layer. The second surface is opposite to the first surface of the first layer. |
| US09048301B2 |
Nanowire MOSFET with support structures for source and drain
A transistor device and method for forming a nanowire field effect transistor (FET) device are provided. A device layer including a source region and a drain region is formed, where the source region and the drain region are connected by a suspended nanowire channel. Etch stop layers are formed beneath the source region and the drain region. The etch stop layers comprise support structures interposed between a semiconductor substrate and the source and drain regions. The suspended nanowire channel is formed by etching a sacrificial material beneath the suspended nanowire channel. The etching is selective to the sacrificial material to prevent the removal of the etch stop layers beneath the source region and the drain region. |
| US09048300B2 |
Strained-induced mobility enhancement nano-device structure and integrated process architecture for CMOS technologies
A method for forming a CMOS integrated circuit device, the method including; providing a semiconductor substrate, forming a gate layer overlying the semiconductor substrate, patterning the gate layer to form NMOS and PMOS gate structures including edges; forming a first dielectric layer overlying the NMOS and PMOS gate structures to protect the NMOS and PMOS gate structures including the edges, forming a first masking layer overlying a first region adjacent the NMOS gate structure; etching a first source region and a first drain region adjacent to the PMOS gate structure using the first masking layer as a protective layer for the first region adjacent the NMOS gate structure, and depositing a silicon germanium material into the first source and drain regions to cause the channel region between the first source and drain regions of the PMOS gate structure to be strained in a compressive mode. |
| US09048298B1 |
Backside warpage control structure and fabrication method
Through vias extend through a substrate between a frontside surface and a backside surface, the through vias comprising active surface ends at the frontside surface. A frontside redistribution structure is coupled to the active surface ends, the frontside redistribution structure exerting force on the frontside surface, e.g., due to a difference in the thermal coefficient of expansion (TCE) between the frontside redistribution structure and the substrate. To prevent warpage of the substrate, a backside warpage control structure is coupled to the backside surface of the substrate. The backside warpage control structure exerts an equal but opposite force to the force exerted by the frontside redistribution structure thus avoiding warpage of the substrate. |
| US09048297B2 |
Contact and via interconnects using metal around dielectric pillars
An integrated circuit containing a vertical interconnect that includes a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure. An upper conductive structure contacts a top surface of the vertical interconnect. A process of forming an integrated circuit that includes forming a vertical interconnect that has a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure, and an upper conductive structure contacts a top surface of the vertical interconnect. |
| US09048292B2 |
Patterning methods and methods of forming electrically conductive lines
Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the photoresist features having a narrowed region. The photoresist features are trimmed, which punches through the narrowed region to form a gap. Spacers are formed along sidewalls of the photoresist features. Two of the spacers merge within the gap. The photoresist features are removed to leave a pattern comprising the spacers. The pattern is extended into the substrate to form a plurality of recesses within the substrate. Electrically conductive material is formed within the recesses to create the electrically conductive lines. Some embodiments include semiconductor constructions having a plurality of lines over a semiconductor substrate. Two of the lines are adjacent to one another and are substantially parallel to one another except in a region wherein said two of the lines merge into one another. |
| US09048285B2 |
Semiconductor structure and method of forming a harmonic-effect-suppression structure
A semiconductor structure includes a SOI/BOX semiconductor substrate, a device, a deep trench, a silicon layer, and a dielectric layer. The deep trench is adjacent to the device and extends through a shallow trench isolation layer within the SOI layer and the BOX layer and into the base semiconductor substrate. The silicon layer is disposed within a lower portion of the deep trench. The silicon layer has a top surface height substantially the same as or lower than a top surface height of the base semiconductor substrate. The dielectric layer is disposed within the deep trench and on the silicon layer. The deep trench can be formed before or after formation of an interlayer dielectric. |
| US09048282B2 |
Dual-gate trench IGBT with buried floating P-type shield
A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate. |
| US09048271B2 |
Modular semiconductor processing system
Disclosed is a modular semiconductor substrate processing system (1), including a plurality of independently operable substrate processing units (100). Each unit (100) comprises a reactor module (104) and a substrate transfer module (102). Within the system (1), the substrate transfer modules (102) of the different units (100) are serially interconnected such that substrates (116) may be exchanged between them. Exchange of substrates (116) between neighboring processing units (100) is facilitated by a shared substrate hand-off station (130) that is associated with each pair of neighboring processing units. The actual transfer of substrates is performed by a substrate handling robot (122), which may preferably be of the SCARA-type. |
| US09048269B2 |
Substrate liquid treatment apparatus with lift pin plate
Disclosed is a liquid treatment apparatus for processing a lower surface of the substrate. The apparatus includes a first nozzle disposed below a lower surface of the substrate retained by the substrate retaining unit to eject a treatment liquid towards the lower surface of the substrate, the first nozzle having a plurality of first ejection ports, which are arrayed from a position opposing a central portion of the substrate retained by the substrate retaining unit to a position opposing a peripheral portion of the substrate retained by the substrate retaining unit. An ejecting direction of the treatment liquid ejected from the first ejection port is inclined towards a rotation direction of the substrate rotated by the rotational driving unit. |
| US09048266B2 |
Apparatus and methods for improving parallel conduction in a quantum well device
Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed. |
| US09048259B2 |
Dielectric punch-through stoppers for forming FinFETs having dual fin heights
A semiconductor structure includes a semiconductor substrate having a first portion and a second portion. A first Fin field-effect transistor (FinFET) is formed over the first portion of the semiconductor substrate, wherein the first FinFET includes a first fin having a first fin height. A second FinFET is formed over the second portion of the semiconductor substrate, wherein the second FinFET includes a second fin having a second fin height different from the first fin height. A top surface of the first fin is substantially level with a top surface of the second fin. A punch-through stopper is underlying and adjoining the first FinFET, wherein the punch-through stopper isolates the first fin from the first portion of the semiconductor substrate. |
| US09048258B2 |
Narrow body field-effect transistor structures with free-standing extension regions
Narrow-body FETs, such as, FinFETs and trigates, exhibit superior short-channel characteristics compared to thick-body devices, such as planar bulk Si FETs and planar partially-depleted SOI (PDSOI) FETs. A common problem, however, with narrow-body devices is high series resistance that often negates the short-channel benefits. The high series resistance is due to either dopant pile-up at the SOI/BOX interface or dopant diffusion into the BOX. This disclosure describes a novel narrow-body device geometry that is expected to overcome the high series resistance problem. |
| US09048257B2 |
Backplane for flat panel display apparatus, flat panel display apparatus, and method of manufacturing the backplane
A backplane includes: a substrate, a pixel electrode, which includes a transparent conductive material, on the substrate, a capacitor first electrode formed on the same layer as the pixel electrode, a first protection layer covering the capacitor first electrode and an upper edge of the pixel electrode, a gate electrode of a thin film transistor (TFT) formed on the first protection layer, a capacitor second electrode formed on the same layer as the gate electrode, a first insulating layer that covers the gate electrode and the capacitor second electrode, a semiconductor layer that is formed on the first insulating layer and includes a transparent conductive material, a second insulating layer covering the semiconductor layer, source and drain electrodes of the TFT that are formed on the second insulating layer, and a third insulating layer that covers the source and drain electrodes and exposes the pixel electrode. |
| US09048255B2 |
Apparatus and method for power MOS transistor
A method comprises forming a first trench and a second trench, depositing a dielectric material in a lower portion of the first trench, depositing a gate electrode material in the second trench and an upper portion of the first trench, forming a first N+ region and a second N+ region through an ion implantation process, wherein the first N+ region and the second N+ region are on opposite sides of the first trench and forming an accumulation layer along a sidewall of the second trench. |
| US09048251B2 |
Semiconductor device and method of manufacturing the same
The semiconductor device of this embodiment includes: a first region of a first conductivity type SiC; a second region of a first conductivity type SiC, impurity concentration of first conductivity type of the second region being lower than impurity concentration of first conductivity type of the first region; a third region of a second conductivity type SiC provided between the first region and the second region; a Si layer provided on surfaces of the first, second, and third regions, a thickness of the Si layer on the third region being thicker than a thickness of the Si layer on the second region; a gate insulating film provided on the Si layer; and a date electrode provided on the gate insulating film. |
| US09048247B2 |
Method for producing a metal structure in a semiconductor substrate
A method for producing a metal structure in a semiconductor substrate includes: producing an opening in the rear side of the semiconductor substrate in the area of the metal structure to be produced, which extends to the front side layer structure; filling the opening at least partially with a metal so that a metal structure is created which extends from the rear side of the semiconductor substrate to the front side layer structure; masking the rear side of the semiconductor substrate for a trench process for exposing the metal structure in such a way that the trench mask includes a lattice structure in an area adjacent to the metal structure; producing an isolation trench adjacent to the metal structure, the metal structure acting as a lateral etch stop and the lattice structure being laterally undercut in the trench mask; and applying a sealing layer to the mask. |
| US09048246B2 |
Die seal ring and method of forming the same
A die seal ring is provided. The die seal ring includes a substrate and a first layer extruding from the substrate. The first layer has a first fin ring structure and a layout of the first fin ring structure has a stamp-like shape. In addition, a method for forming a die seal ring is provided. A substrate having an active region is provided. A patterned sacrificial layer is formed on the substrate. A spacer is formed on the sidewall of the patterned sacrificial layer. The patterned sacrificial layer is removed. The substrate is patterned by using the spacer as a mask, thereby simultaneously forming at least a fin structure of a Fin-FET and a first layer of the die seal ring. |
| US09048245B2 |
Method for shaping a laminate substrate
A method including providing a fixture comprising a trap ring, a base plate having a recess adapted to receive a laminate substrate, the base plate including an opening and an adjustable height center button disposed in the opening, the opening being located within the recess and located in a center of the laminate substrate, characterizing the laminate substrate for warpage characteristics by using one of room temperature techniques and elevated temperature techniques, determining a horizontal plane distortion based on the warpage characteristics, and placing the laminate substrate into the fixture with an adjustment to correct the horizontal plane distortion, the adjustment is provided by the adjustable height center button, wherein the adjustable height center button contacts the laminate substrate. The method further includes fluxing the laminate substrate, placing a chip onto the laminate substrate, and placing the fixture into a reflow furnace to join the chip and the laminate substrate. |
| US09048243B2 |
Chip package
A chip package structure includes a package body, a first lead and a second lead. Elements embedded inside the package body include a core circuit having at least one first connection terminal, at least one ESD protection circuit having at least one second connection terminal, at least one third connection terminal and at least one interconnection structure. The interconnection structure is electrically connected to the second connection terminal and the third connection terminal. The first lead on the package body is electrically connected to the second connection terminal and an external circuit. The second lead on the package body electrically connects the first connection terminal and the third connection terminal. The second lead and the first lead are separate in structure. |
| US09048241B2 |
Semiconductor device utilzing redistribution layers to couple stacked die
A semiconductor device utilizing redistribution layers to couple stacked die is disclosed and may include a first semiconductor die with a first surface comprising bond pads, a second surface opposite the first surface, and sloped side surfaces between the first and second surfaces, such that a cross-section of the first die is trapezoidal in shape. A second semiconductor die with a first surface may be bonded to the second surface of the first die, wherein the first surface of the second die may comprise bond pads. A passivation layer may be formed on the first surface and sloped side surfaces of the first die and the first surface of the second die. A redistribution layer may be formed on the passivation layer, electrically coupling bond pads on the first and second die. A conductive pillar may extend from a bond pad on the second die to the second redistribution layer. |
| US09048239B2 |
Semiconductor device including stacked semiconductor chips
A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups. |
| US09048236B2 |
Semiconductor device and method of fabricating the same
A semiconductor device includes an interlayer insulating film formed on a substrate, the insulating layer including a trench. A gate insulating layer is formed on a bottom surface of the trench and a reaction prevention layer is formed on the gate insulating layer on the bottom surface of the trench. A replacement metal gate structure is formed on the reaction prevention layer of the trench to fill the trench. |
| US09048234B2 |
Off-chip vias in stacked chips
A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements. |
| US09048233B2 |
Package systems having interposers
A package system includes an integrated circuit disposed over an interposer. The interposer includes a first interconnect structure. A first substrate is disposed over the first interconnect structure. The first substrate includes at least one first through silicon via (TSV) structure therein. A molding compound material is disposed over the first interconnect structure and around the first substrate. The integrated circuit is electrically coupled with the at least one first TSV structure. |
| US09048224B2 |
Nonvolatile semiconductor memory device and method for manufacturing same
According to one embodiment, a nonvolatile semiconductor memory device includes: first and second stacked bodies, first and second semiconductor pillars, a connection portion, a memory film, and a partitioning insulating layer. The stacked bodes include electrode films stacked along a first axis and an inter-electrode insulating film provided between the electrode films. Through-holes are provided in the stacked bodies. The semiconductor pillars are filled into the through-holes. The connection portion electrically connects the semiconductor pillars. The memory film is provided between the semiconductor pillars and the electrode films. The partitioning insulating layer partitions the first and second electrode films. A side surface of the first through-hole on the partitioning insulating layer side and a side surface of the second through-hole on the partitioning insulating layer side have a portion parallel to a plane orthogonal to a second axis from the first stacked body to the second stacked body. |
| US09048221B2 |
Device having electrodes formed from bumps with different diameters
A device has a first substrate having a first surface; a first electrode pad arranged on the first surface of the first substrate; a first insulator film provided on the first surface of the first substrate so that the first electrode pad is exposed; a first bump electrode provided on the first electrode pad and having a first diameter; and a second bump electrode provided on the first insulator film and having a second diameter smaller than the first diameter. |
| US09048220B2 |
Method of crystallizing silicon thin film and method of manufacturing silicon thin-film transistor device
A method of crystallizing a silicon thin film, which enables uniforming the size of a crystalline grain of the silicon thin film, includes: a second process of stacking, on a substrate, a first gate electrode having a first reflectivity; a third process of stacking a second gate electrode on the first gate electrode, the second gate electrode having a second reflectivity lower than the first reflectivity and including a top face having an area smaller than an area of the top face of the first gate electrode; a fourth process of stacking a gate insulation film to cover a first region and a second region; a fifth process of stacking a noncrystalline silicon thin film on the stacked gate insulation film; and a sixth process of crystallizing the noncrystalline silicon thin film by irradiating the noncrystalline silicon thin film from above with a laser beam. |
| US09048218B2 |
Semiconductor device with buried gates and method for fabricating the same
A semiconductor device includes a supplementary layer and a silicon layer stacked over a substrate, a trench penetrating the supplementary layer and the silicon layer and formed over the substrate, a gate insulation layer formed along a surface of the trench, and a buried gate formed over the gate insulation layer and filling a portion of the trench. |
| US09048217B2 |
Middle of-line borderless contact structure and method of forming
Various embodiments disclosed include semiconductor structures and methods of forming such structures. In one embodiment, a method includes: providing a semiconductor structure including: a substrate; at least one gate structure overlying the substrate; and an interlayer dielectric overlying the substrate and the at least one gate structure; removing the ILD overlying the substrate to expose the substrate; forming a silicide layer over the substrate; forming a conductor over the silicide layer and the at least one gate structure; forming an opening in the conductor to expose a portion of a gate region of the at least one gate structure; and forming a dielectric in the opening in the conductor. |
| US09048215B2 |
Semiconductor device having a high breakdown voltage
A semiconductor device includes a first layer of a first-type, a second layer of a second-type formed on the first layer, a third layer of the first type formed on the second layer, a first electrode connected to the second and third layers, a second electrode connected to the first layer, a third electrode embedded in a trench formed through the third and second layers and into the first layer, a fourth electrode embedded in the trench below the third electrode, and an insulating layer formed in the trench around the fourth electrode. The first layer includes a first region that is in contact with the insulating layer and at which a concentration of the first-type dopant is lower than the concentration at a second region that is formed around the first region. |
| US09048213B2 |
Semiconductor device
A field plate electrode is repetitively disposed in a folded manner or a spiral shape in a direction along an edge of a first circuit region. A coupling transistor couples a first circuit to a second circuit lower in supply voltage than the first circuit. A second conductivity type region is disposed around the coupling transistor. A part of the field plate electrode partially overlaps with the second conductivity type region. The field plate electrode is electrically coupled to a drain electrode of the coupling transistor at a portion located on the first circuit region side from a center thereof in a width direction of the separation region. A ground potential or a power potential of the second circuit is applied to the field plate electrode at a portion located on the second conductivity type region side from the center. |
| US09048209B2 |
Semiconductor device and method of mounting semiconductor die to heat spreader on temporary carrier and forming polymer layer and conductive layer over the die
A semiconductor device is made by forming a heat spreader over a carrier. A semiconductor die is mounted over the heat spreader with a first surface oriented toward the heat spreader. A first insulating layer is formed over the semiconductor die and heat spreader. A via is formed in the first insulating layer. A first conductive layer is formed over the first insulating layer and connected to the heat spreader through the via and to contact pads on the semiconductor die. The heat spreader extends from the first surface of the semiconductor die to the via. A second insulating layer is formed over the first conductive layer. A second conductive layer is electrically connected to the first conductive layer. The carrier is removed. The heat spreader dissipates heat from the semiconductor die and provides shielding from inter-device interference. The heat spreader is grounded through the first conductive layer. |
| US09048207B2 |
Bubble discharging structure, reverse printing block, display device, printing method, and method of manufacturing display device
Disclosed herein is a bubble discharging structure, including a substrate which has a first area and a second area adjacent to the first area, and on which a counter substrate is caused to come in contact with the first area to provide a film having a first pattern, and a bubble discharging path through which the first area and the second area communicate with each other, and through which a bubble confined between the substrate and the counter substrate when the counter substrate is caused to come in contact with the first area is discharged from the first area to the second area. |
| US09048202B2 |
Organic EL panel
The present invention is to ensure that when it has been judged that film-formation areas of a plurality of layers laminated on the same luminescent areas of organic EL devices involve a defect, it is possible to exactly find which layer of the multi-laminated layers is a defective layer. The film formation areas of layers to be laminated on luminescent area are formed in a manner such that overlap deviations e1-e3 are intentionally formed. |
| US09048201B2 |
Sacrificial wafer probe pads through seal ring for electrical connection to circuit inside an integrated circuit
The disclosure is directed to a semiconductor wafer, integrated circuit product, and method of making same, having multiple non-singulated chips separated by scribe lines, comprising a plurality of seal rings, each seal ring surrounding a corresponding chip and disposed between the corresponding chip and adjacent scribe lines. Well resistors are disposed below the seal rings and probe pads disposed in the scribe lines. In particular, at least one of the probe pads is coupled by at least one of the well resistors to at least one of the chips. |
| US09048189B2 |
Plasma processing method of semiconductor manufacturing apparatus
Plasma processing methods of a semiconductor manufacturing apparatus which can minimize the amount of impurities adhered to the surface of a wafer, when a desired process using plasma is performed. According to the plasma processing methods of the semiconductor manufacturing apparatus, after the desired process is completed, the plasma generated over the wafer is diffused, and then the wafer is de-chucked. |
| US09048185B2 |
Profile pre-shaping for replacement poly gate interlayer dielectric
Some embodiments relate to an integrated circuit (IC). The IC includes a semiconductor substrate having an upper surface with a source region and drain region proximate thereto. A channel region is disposed in the substrate between the source region and the drain region. A gate electrode is disposed over the channel region and separated from the channel region by a gate dielectric. Sidewall spacers are formed about opposing sidewalls of the gate electrode. Upper outer edges of the sidewall spacers extend outward beyond corresponding lower outer edges of the sidewall spacers. A liner is disposed about opposing sidewalls of the sidewall spacers and has a first thickness at an upper portion of liner and a second thickness at a lower portion of the liner. The first thickness is less than the second thickness. Other embodiments are also disclosed. |
| US09048183B2 |
NMOS metal gate materials, manufacturing methods, and equipment using CVD and ALD processes with metal based precursors
Embodiments provide methods for depositing metal-containing materials. The methods include deposition processes that form metal, metal carbide, metal silicide, metal nitride, and metal carbide derivatives by a vapor deposition process, including thermal decomposition, CVD, pulsed-CVD, or ALD. A method for processing a substrate is provided which includes depositing a dielectric material forming a feature definition in the dielectric material, depositing a work function material conformally on the sidewalls and bottom of the feature definition, and depositing a metal gate fill material on the work function material to fill the feature definition, wherein the work function material is deposited by reacting at least one metal-halide precursor having the formula MXY, wherein M is tantalum, hafnium, titanium, and lanthanum, X is a halide selected from the group of fluorine, chlorine, bromine, or iodine, and y is from 3 to 5. |
| US09048181B2 |
Mechanisms for forming ultra shallow junction
A method of making a semiconductor device includes forming a fin structure over a substrate. The method further includes performing a plasma doping process on the fin structure. Performing the plasma doping process includes implanting plasma ions into the fin structures at a plurality of implant angles, and the plurality of implant angles has an angular distribution and at least one highest angle frequency value. |
| US09048180B2 |
Low stress sacrificial cap layer
A low stress sacrificial cap layer 120 having a silicon oxide liner film 130, a low stress silicon film 140, and a silicon nitride film Alternatively, a low stress sacrificial cap layer 410 having a silicon oxide liner film 130 and a graded silicon nitride film 420. Also, methods 300, 500 for fabricating a transistor 20, 400 having a low stress sacrificial cap layer 120, 410. |
| US09048179B2 |
Systems and methods for preparing films using sequential ion implantation, and films formed using same
Systems and methods for preparing films using sequential ion implantation, and films formed using same, are provided herein. A structure prepared using ion implantation may include a substrate; an embedded structure having pre-selected characteristics; and a film within or adjacent to the embedded structure and including ions having a perturbed arrangement arising from the presence of the embedded structure. The perturbed arrangement may include the ions being covalently bonded to each other, to the embedded structure, or to the substrate, whereas the ions instead may be free to diffuse through the substrate in the absence of the embedded structure. The embedded structure may inhibit or impede the ions from diffusing through the substrate, such that the ions instead covalently bond to each other, to the embedded structure, or to the substrate. The film may include, for example, diamond-like carbon, graphene, or SiC having a pre-selected phase. |
| US09048178B2 |
Plasma etching method and semiconductor device manufacturing method
A plasma etching method is provided for etching a substrate corresponding to an etching object within an etching apparatus that includes a supply condition adjustment unit for adjusting a supply condition for supplying etching gas to the substrate, a temperature adjustment unit for adjusting a temperature of the substrate placed on a stage along a radial direction, and a plasma generating unit for generating plasma within a space between the supply condition adjustment unit and the stage. The plasma etching method includes a control step in which the temperature adjustment unit controls the temperature of the substrate to be uniform within a substrate plane of the substrate, and an adjustment step in which the supply condition adjustment unit adjusts a concentration distribution of active species contained in the plasma generated by the plasma generation unit within the space above the substrate. |
| US09048177B2 |
Resin coating device, and resin coating method
A translucent member 41 that has been trial-coated with a resin 8 for measurement of a light emission characteristic is placed on a translucent member placement portion 53, an excitation light that excites a phosphor is emitted from a light source unit 42 disposed above, the resin 8 coated on the translucent member 41 is irradiated with the excitation light from above, a deviation between a measurement result obtained by measuring the light emission characteristic of the light emitted from the resin 8, and a light emission characteristic specified in advance is obtained, and an appropriate resin coating amount of the resin to be coated on the LED element for actual production is derived on the basis of the deviation. |
| US09048172B2 |
Method of manufacturing white light emitting device (LED) and apparatus measuring phosphor film
A method of manufacturing a white light emitting device includes dividing a phosphor sheet into phosphor film units to be applied to individual light emitting diode (LED) devices, measuring light conversion characteristics of the respective phosphor film units, classifying the phosphor film units of the phosphor sheet into a plurality of groups according to measurement results of the light conversion characteristics and combining the phosphor film units classified into the plurality of groups and an LED device having predetermined light characteristics so as to obtain target color characteristics. |
| US09048171B2 |
Method to dynamically tune precision resistance
A precision resistor is formed with a controllable resistance to compensate for variations that occur with temperature. An embodiment includes forming a resistive semiconductive element having a width and a length on a substrate, patterning an electrically conductive line across the width of the resistive semiconductive element, but electrically isolated therefrom, and forming a depletion channel in the resistive semiconductive element under the electrically conductive line to control the resistance value of the resistive semiconductive element. The design enables dynamic adjustment of the resistance, thereby improving the reliability of the resistor or allowing for resistance modification during final packaging. |
| US09048169B2 |
Formation of substantially pit free indium gallium nitride
A method of fabricating a device layer structure includes providing a III-nitride semiconductor layer which is bonded to a bonding substrate. A device layer structure is formed on a nitrogen polar surface of the III-nitride semiconductor layer. The device layer structure includes an indium gallium nitride layer with a metal polar surface adjacent to the nitrogen polar surface of the III-nitride semiconductor layer. |
| US09048166B2 |
Method for controlled growth of silicon carbide and structures produced by same
A method for controlled growth of silicon carbide and structures produced by the method are disclosed. A crystal of silicon carbide (SiC) can be grown by placing a sacrificial substrate in a growth zone with a source material. The source material may include a low-solubility impurity. SiC is then grown on the sacrificial substrate to condition the source material. The sacrificial substrate is then replaced with the final substrate, and SiC is grown on the final substrate. A single crystal of silicon carbide is produced, wherein the crystal of silicon carbide has substantially few micropipe defects. Such a crystal may also include a substantially uniform concentration of the low-solubility impurity, and may be used to make wafers and/or SiC die. |
| US09048164B2 |
Solid-state image sensing device containing electron multiplication function having N-type floating diffusion (FD) region formed within a P-type well region
A solid state imaging device includes a P-type semiconductor substrate 1A, a P-type epitaxial layer 1B grown on the semiconductor substrate 1A, an imaging region VR grown within the epitaxial layer 1B, and an N-type semiconductor region 1C grown within the epitaxial layer 1B. The solid state imaging device further includes a horizontal shift register HR that transmits a signal from the imaging region VR, and a P-type well region 1D formed within the epitaxial layer 1B. The N-type semiconductor region 1C extends in the well region 1D. A P-type impurity concentration in the well region 1D is higher than a P-type impurity concentration in the epitaxial layer 1B. A multiplication register EM that multiplies electrons from the horizontal shift register HR is formed in the well region 1D. |
| US09048163B2 |
Transistor, electronic device including transistor, and manufacturing methods thereof
A transistor may include an active layer having a plurality of oxide semiconductor layers and an insulating layer disposed therebetween. The insulating layer may include a material that has higher etch selectivity with respect to at least one of the plurality of oxide semiconductor layers. The electronic device may include a first transistor and a second transistor connected to the first transistor. The second transistor may include an active layer having a different structure from that of the active layer included in the first transistor. The active layer of the second transistor may have the same structure as one of the plurality of oxide semiconductor layers constituting the active layer of the first transistor. |
| US09048162B2 |
CMOS image sensors and methods for forming the same
A device includes a diode, which includes a first, a second, and a third doped region in a semiconductor substrate. The first doped region is of a first conductivity type, and has a first impurity concentration. The second doped region is of the first conductivity type, and has a second impurity concentration lower than the first impurity concentration. The second doped region encircles the first doped region. The third doped region is of a second conductivity type opposite the first conductivity type, wherein the third doped region overlaps a portion of the first doped region and a portion of the second doped region. |
| US09048161B2 |
Method for fabricating sensor
A method for fabricating a sensor includes: forming, on a base substrate, a pattern of a source electrode and a drain electrode, a pattern of a data line, a pattern of a receiving electrode, a pattern of a photodiode, and a pattern of a transparent electrode disposed by using a first patterning process; forming a pattern of an ohmic layer by using a second patterning process; forming a pattern of an active layer by using a third patterning process; forming a pattern of a gate insulating layer by using a fourth patterning process, wherein the gate insulating layer has a via hole above the transparent electrode; and forming a pattern of a gate electrode, a pattern of a gate line, and a pattern of a bias line connected to the transparent electrode via the via hole above the transparent electrode by using a fifth patterning process. |
| US09048160B2 |
Radiographic imaging array fabrication process for metal oxide thin-film transistors with reduced mask count
Embodiments of radiographic imaging systems; radiography detectors and methods for using the same; and/or fabrication methods therefore can include radiographic imaging array that can include a plurality of pixels that each include a photoelectric conversion element coupled to a thin-film switching element. In certain exemplary embodiments, thin-film switching element is a metal oxide (e.g., a-IGZO) TFT manufactured using a reduce photolithography mask counts. In certain exemplary embodiments, the thin-film switching element is a metal oxide (e.g., a-IGZO) TFT that includes reduced lower alignment tolerances between TFT electrodes. In certain exemplary embodiments, the thin-film switching element is a metal oxide (e.g., a-IGZO) TFT including a reduced thickness active layer. |
| US09048157B2 |
Solid-state imaging device and portable information terminal
A solid-state imaging device according to an embodiment includes: an imaging element formed on a semiconductor substrate, and comprising an imaging region including a plurality of pixel blocks each including a plurality of pixels; a first optical system forming an image of an object on an imaging plane; and a second optical system comprising a microlens array including a plurality of microlenses each corresponding to one of the pixel blocks, and reducing and re-forming the image to be formed on the imaging plane on the pixel blocks corresponding to the respective microlenses. The imaging plane of the first optical system is located further away from the first optical system than the imaging element when the object is located at an infinite distance. |
| US09048156B2 |
Semiconductor image pickup device
According to one embodiment, a semiconductor image pickup device includes a pixel area and a non-pixel area. The device includes a first photoelectric conversion element formed in the pixel area, a first transistor formed in the pixel area and connected to the first photoelectric conversion element, a second photoelectric conversion element formed in the non-pixel area, a second transistor formed in the non-pixel area and connected to the second photoelectric conversion element, a metal wire formed at least in the non-pixel area, a first cap layer formed on the metal wire to prevent diffusion of metal contained in the metal wire, and a dummy via wire formed in the non-pixel area and penetrating the first cap layer. |
| US09048151B2 |
Self-powered integrated circuit with photovoltaic cell
A photovoltaic cell is provided as a composite unit together with elements of an integrated circuit on a common substrate. In a described embodiment, connections are established between a photovoltaic cell portion and a circuitry portion of an integrated structure to enable self-powering of the circuitry portion by the photovoltaic cell portion. |
| US09048150B1 |
Testing of semiconductor components and circuit layouts therefor
In one embodiment of the present invention, a method of forming a semiconductor device includes performing a test during the forming of the semiconductor device within and/or over a substrate. A first voltage is applied to a first node coupled to a component to be tested in the substrate and a test voltage at a pad coupled to the component to be tested through a second node. The test voltage has a peak voltage higher than the first voltage. The component to be tested is coupled between the first node and the second node. A leakage current is measured through the component to be tested in response to the test voltage. After performing the test, the second node is connected to a functional block in the substrate. The first node is coupled to a third node coupled to the functional block. |
| US09048149B2 |
Self-alignment structure for wafer level chip scale package
A packaged semiconductor device includes a semiconductor substrate, a metal pad, a metal base, a polymer insulating layer, a copper-containing structure and a conductive bump. The metal pad and the metal base are disposed on the semiconductor substrate. The polymer insulating layer overlies the metal base and the semiconductor substrate. The copper-containing structure is disposed over the polymer insulating layer, and includes a support structure and a post-passivation interconnect (PPI) line. The support structure is aligned with the metal base. The PPI line is located partially within the support structure, and extends out through an opening of the support structure, in which a top of the support structure is elevated higher than a top of the PPI line. The conductive bump is held by the support structure. |
| US09048145B2 |
Array substrate, method for manufacturing the same, and display apparatus
Disclosed is a method for manufacturing an array substrate, comprising: step A, sequentially forming patterns of a first conduction layer, source and drain electrodes, an active layer, and an insulation layer on one side of the substrate, wherein at least one via hole is provided on the insulation layer; step B, sequentially forming a gate metal layer and a passivation layer on the substrate on which the first conduction layer, the source and drain electrodes, the active layer, and the insulation layer have been formed, wherein the gate metal layer comprises a gate electrode and a gate line, and the gate metal layer is coupled to the first conduction layer through the at least one via hole to form a path for dispersing static electricity. |
| US09048142B2 |
Semiconductor device
The degree of integration of a semiconductor device is enhanced and the storage capacity per unit area is increased. The semiconductor device includes a first transistor provided in a semiconductor substrate and a second transistor provided over the first transistor. In addition, an upper portion of a semiconductor layer of the second transistor is in contact with a wiring, and a lower portion thereof is in contact with a gate electrode of the first transistor. With such a structure, the wiring and the gate electrode of the first transistor can serve as a source electrode and a drain electrode of the second transistor, respectively. Accordingly, the area occupied by the semiconductor device can be reduced. |
| US09048140B2 |
Semiconductor integrated circuit
Disclosed herein is a semiconductor integrated circuit including: a cell layout region including circuit cells subject to power control the supply and interruption of power to which is controlled by a power switch, and always-on circuit cell groups which are always powered after the activation; a main line laid out in the cell layout region and applied with a source or reference voltage; and first and second branch lines which branch from the main line in the cell layout region. |
| US09048139B2 |
Method for fabricating non-volatile memory device
A method for fabricating a non-volatile memory device includes alternately stacking a plurality of inter-layer dielectric layers and a plurality of sacrificial layers over a substrate, forming at least a channel hole that exposes the substrate by selectively etching the inter-layer dielectric layers and the sacrificial layers, forming a protective layer on sidewalls of the sacrificial layers that are exposed through the channel hole, sequentially forming a memory layer and a channel layer on the sidewalls of the channel hole, forming slit holes that penetrate through the inter-layer dielectric layers and the sacrificial layers on both sides of the channel hole, removing the sacrificial layers that are exposed through the slit holes, removing the protective layer, and forming gate electrodes in space from which the sacrificial layers and the protective layer are removed. |
| US09048134B2 |
Memory device and method for manufacturing the same
A memory device comprises a substrate, a plurality of buried word lines, a plurality of digital contacts, a patterned insulating layer, a liner layer, a plurality of buried bit lines, and a cap layer. The buried word lines are arranged in the substrate in parallel along a first direction. Each of the digital contacts is arranged between one pair of the neighboring buried word lines. The patterned insulating layer is arranged on the buried word lines, having a plurality of contact holes opposite to the digital contacts. The liner layer is arranged on the substrate, and abuts the patterned insulating layer. The buried bit lines are arranged in parallel along a second direction different from the first direction. The cap layer arranged to cover the buried bit lines. |
| US09048127B2 |
Three dimensional circuit including shielded inductor and method of forming same
The three dimensional (3D) circuit includes a first tier including a semiconductor substrate, a second tier disposed adjacent to the first tier, a three dimensional inductor including an inductive element portion, the inductive element portion including a conductive via extending from the first tier to a dielectric layer of the second tier. The 3D circuit includes a ground shield surrounding at least a portion of the conductive via. In some embodiments, the ground shield includes a hollow cylindrical cage. In some embodiments, the 3D circuit is a low noise amplifier. |
| US09048126B2 |
Methods for measuring the full well capacity of CMOS image sensors
An integrated circuit device includes a transfer-gate transistor, and a photo diode connected to a source/drain region of the transfer-gate transistor. An electrical fuse is electrically coupled to a gate of the transfer-gate transistor. A diode is electrically coupled to the electrical fuse. |
| US09048121B2 |
FinFET cell architecture with insulator structure
A finFET block architecture includes a first set of semiconductor fins having a first conductivity type, and a second set of semiconductor fins having a second conductivity type. An inter-block insulator is placed between outer fins of the first and second sets. A patterned gate conductor layer includes a first plurality of gate traces extending across the set of fins in the first block without crossing the inter-block insulator, and a second plurality of gate traces extending across the set of fins in the second block without crossing the inter-block insulator. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and include an inter-block connector arranged to connect gate traces in the first and second blocks. |
| US09048120B2 |
Integrated junction and junctionless nanotransistors
Semiconductor devices including a first transistor and a second transistor are integrated on a substrate. Each of the first and second transistors include a nano-sized active region including source and drain regions provided in respective end portions of the nano-sized active region and a channel forming region provided between the source and drain regions. The source and drain regions of the first transistor have the same conductivity type as those of the second transistor, and the second transistor has a threshold voltage lower than that of the first transistor. The channel forming region of the second transistor may include a homogeneously doped region, whose conductivity type is the same as the source and drain regions of the second transistor and is different from the channel forming region of the first transistor. |
| US09048119B2 |
Semiconductor device with normally off and normally on transistors
There exists a possibility that a semiconductor device configured with a normally-on JFET and a normally-off MOSFET which are coupled in cascade may break by erroneous conduction, etc. A semiconductor device is configured with a normally-on SiCJFET and a normally-off Si-type MOSFET. The normally-on SiCJFET and the normally-off Si-type MOSFET are coupled in cascade and configure a switching circuit. According to one input signal, the normally-on SiCJFET and the normally-off Si-type MOSFET are controlled so as to have a period in which both transistors are set in an OFF state. |
| US09048116B2 |
Semiconductor device having isolation trenches
A semiconductor uses an isolation trench, and one or more additional trenches to those required for isolation are provided. These additional trenches can be connected between a transistor gate and the drain to provide additional gate-drain capacitance, or else they can be used to form series impedance coupled to the transistor gate. These measures can be used separately or in combination to reduce the switching speed and thereby reduce current spikes. |
| US09048113B2 |
Cost-effective LED lighting instrument with good light output uniformity
A lighting instrument includes: a substrate; a plurality of first light-emitting diodes (LEDs) disposed over the substrate, wherein the first LEDs each have a first value range for a light output characteristic; a plurality of second LEDs disposed over the substrate, wherein the second LEDs each have a second value range for the light output characteristic, the second value range being different from the first value range; a phosphor layer located at a distance above the first LEDs and the second LEDs; and a light-reflective layer that is disposed on a surface of the phosphor layer; wherein the first LEDs interleave with the second LEDs according to a predefined pattern. |
| US09048112B2 |
Integrated voltage regulator with embedded passive device(s) for a stacked IC
A stacked integrated circuit includes a first tier IC and a second tier IC. Active faces of the first tier IC and the second tier IC face each other. An interconnect structure, such as microbumps, couples the first tier IC to the second tier IC. An active portion of a voltage regulator is integrated in the first semiconductor IC and coupled to passive components (for example a capacitor or an inductor) embedded in a packaging substrate on which the stacked IC is mounted. The passive components may be multiple through vias in the packaging substrate providing inductance to the active portion of the voltage regulator. The inductance provided to the active portion of the voltage regulator is increased by coupling the through via in the packaging substrate to through vias in a printed circuit board that the packaging substrate is mounted on. |
| US09048110B2 |
Noise isolation between circuit blocks in an integrated circuit chip
An integrated circuit includes a p-well block region having a low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further includes a guard region and a grounded, highly doped region for providing additional noise isolation. |
| US09048109B2 |
Semiconductor device, module and system each including the same, and method for manufacturing the semiconductor device
A barrier for preventing a bridge between adjacent storage node contacts is formed below a bit line located between the bit line contacts, so that a contact region between each storage node contact and an active region is increased in size. The semiconductor device includes a device isolation film defining an active region, a bit line contact coupling the active region to a bit line, and a barrier formed below the bit line located between the bit line contacts. |
| US09048104B2 |
Multi-chip package module and a doped polysilicon trench for isolation and connection
A circuit module comprises a die attach pad with a surface and a plurality of leads surrounding the surface. A nonconductive adhesive is on the surface. A plurality of electronic circuit dies are on the surface of the die attach pad. Each die has a top surface and a bottom surface with the bottom surface on the adhesive. The top surface has a plurality of bonding pads. A first electronic circuit die has at least one routing path of a conductive material connecting a first bonding pad to a second bonding pad. A first bonding wire connects a bonding pad of a second electronic circuit die to the first bonding pad of the first electronic die. A second bonding wire connects the second bonding pad of the first electronic circuit die to a lead. Where one of the dies contains vertical circuit element, where a doped layer forms a terminal along the bottom surface of the layer, a trench filled with doped polysilicon extends from the top surface to the terminal to connect to the terminal. The doped polysilicon filled trench also serves to isolate and separate different circuit elements. |
| US09048102B2 |
SiC single crystal, SiC wafer, and semiconductor device
An SiC single crystal includes a low dislocation density region (A) where the density of dislocations each of which has a Burgers vector in a {0001} in-plane direction (mainly a direction parallel to a <11-20> direction) is not more than 3,700 cm/cm3. Such an SiC single crystal is obtained by: cutting out a c-plane growth seed crystal of a high offset angle from an a-plane grown crystal; applying c-plane growth so that the density of screw dislocations introduced into a c-plane facet may fall in a prescribed range; cutting out a c-plane growth crystal of a low offset angle from the obtained c-plane grown crystal; and applying c-plane growth so that the density of screw dislocations introduced into a c-plane facet may fall in a prescribed range. An SiC wafer and a semiconductor device are obtained from such an SiC single crystal. |
| US09048100B2 |
Nitride semiconductor and nitride semiconductor crystal growth method
A base at least one principal plane of which is a nitride is prepared for use in epitaxial growth. The base is placed on a susceptor in an epitaxial growth reactor and heated to a predetermined temperature (step A). The heating is started with inactive, nitrogen gas being supplied into the reactor. Then, active, NH3 gas is supplied. Then, a growth step (step B) of a first nitride semiconductor layer is started without an intervening step of thermally cleaning the principal nitride plane of the base. In step B, the first nitride semiconductor layer is epitaxially grown on a principal nitride plane of a base without supply of an Si source material. Then, a relatively thick, second nitride semiconductor layer is epitaxially grown on the first nitride semiconductor layer by supplying an n-type dopant source material (step C). |
| US09048098B2 |
Electrostatic discharge protection device
An electrostatic discharge protection device, having a P-type semiconductor substrate set as floating; a first N-well and a second N-well formed in the P-type substrate; a first P-doped region and a second P-doped region formed in the first N-well and the second N-well, respectively. The first N-well and the first P-doped region form a first diode, and the second N-well and the second P-doped region form a second diode. A first N-doped region and a second N-doped region formed in the first N-well and the second N-well respectively. A third P-doped region is formed in the P-type substrate, wherein the third P-doped region is disposed between the first N-well and the second N-well, and the third P-doped region is electrically connected to the first N-doped region and the second P-doped region. |
| US09048096B2 |
Diode-based ESD concept for DEMOS protection
The invention relates to an ESD protection circuit for an integrated circuit including a drain-extended MOS device and an output pad that requires protection. The ESD protection circuit includes a first diode coupled to the output pad and to a bias voltage rail, a second diode coupled to the output pad and to another bias voltage rail, and an ESD power clamp coupled between the two bias voltage rails. The ESD power clamp is formed as a vertical npn transistor with its base and emitter coupled together. The collector of the npn transistor is formed using an n-well implantation and a DEMOS n-drain extension to produce a snapback-based voltage limiting characteristic. The diodes are formed with a lightly p-doped substrate region over a buried n-type layer, and a p-well implant and an n-well implant separated by intervening substrate. A third diode may be coupled between the two bias voltage rails. |
| US09048092B2 |
Process for preparing graphene based on metal film-assisted annealing and the reaction with Cl2
A method for preparing graphene by reaction with Cl2 based on annealing with assistant metal film is provided, comprising the following steps: applying normal wash to a Si-substrate, then putting the Si-substrate into a reaction chamber of a CVD system and evacuating, rising the temperature to 950° C.-1150° C. gradually, supplying C3H8 and carbonizing the Si-substrate for 3-10 min; rising the temperature to 1150° C.-1350° C. rapidly, supplying C3H8 and SiH4, growing a 3C—SiC hetero-epitaxial film on the carbonized layer, and then reducing the temperature to ambient temperature under the protection of H2 gradually, introducing the grown sample wafer of 3C—SiC into a quartz tube, heating to 700-1100° C., supplying mixed gas of Ar and Cl2, and reacting Cl2 with 3C—SiC to generate a carbon film, applying the sample wafer of carbon film on a metal film, annealing at 900° C.-1100° C. for 10-30 min to reconstruct the carbon film into graphene; and taking out of the metal film from the sample wafer of graphene to obtain large area graphene. The graphene obtained by the method has large area, smooth surface, good continuity, and low porosity; and the product can be used to seal gas and liquid. |
| US09048091B2 |
Method and substrate for thick III-N epitaxy
A method of manufacturing an III-N substrate includes bonding a Si substrate to a support substrate, the Si substrate having a (111) growth surface facing away from the support substrate, thinning the Si substrate at the (111) growth surface to a thickness of 100 μm or less, and forming III-N material on the (111) growth surface of the Si substrate after the Si substrate is thinned. The support substrate has a coefficient of thermal expansion more closely matched to that of the III-N material than the Si substrate. Other methods of manufacturing an III-N substrate are disclosed, as well as the corresponding wafer structures. |
| US09048090B2 |
Semiconductor element and method of manufacturing same
A method of manufacturing a semiconductor element includes forming a first bonding layer containing a metal, which forms a eutectic crystal with Au, on a first substrate to provide a first laminated body. The method also includes forming an element structure layer having a semiconductor layer on a second substrate. The method also includes forming a second bonding layer on the element structure layer to provide a second laminated body. The second bonding layer has a metal underlayer containing a metal, which forms a eutectic crystal with Au. The second bonding layer also has a surface layer that contains Au. The method also includes performing heating pressure-bonding on the first and second laminated bodies with the first and second bonding layers facing each other. The heating temperature of the second substrate in the heating pressure-bonding is higher than the heating temperature of the first substrate. |
| US09048082B2 |
Time-of-flight mass spectrometer
A thin metal plate and two prismatic-bar-shaped metal members that are parallel to each other are alternately and repeatedly stacked, and the stack is sandwiched between two thick metal plates. Each contact surface is bonded to the counterpart surface by diffusion bonding to form an integrated multilayer body. The multilayer body is cut at predetermined intervals at planes perpendicular to the thin metal plates, whereby a grid-like electrode is completed, with the thin metal plates serving as crosspieces and the metal members serving as spacers for defining a gap which serves as openings. |
| US09048079B2 |
Method and apparatus for improving ion transmission into a mass spectrometer
An ion transfer device for transferring ions emerging from an electrospray ion source at atmosphere to a vacuum chamber includes an inner surface in the shape of a diverging conical duct. The ion transfer device has an entrance aperture for positioning proximate the exit port of the electrospray ion source emitter, the entrance aperture receiving the electrosprayed ions from the exit port of the electrospray ion source emitter at atmosphere, the diverging conical duct being an electrode toward which the ions migrate and having an exit aperture with an inner diameter larger than an inner diameter of its entrance aperture, the exit aperture enclosed in the vacuum chamber, the diverging conical duct transporting the ions from atmosphere to vacuum. The vacuum chamber can be a chamber of a vacuum housing enclosing a mass analyzer. |
| US09048071B2 |
Imaging mass spectrometer and method of controlling same
An imaging mass spectrometer capable of reducing the dependence of the resolution of a projection image on mass is offered. Also, a method of controlling this spectrometer is offered. The imaging mass spectrometer includes: a plate on which a sample is placed; a lens system through which ions generated by irradiating the sample with laser light pass; an ion optical system for separating the ions according to flight time corresponding to mass-to-charge ratio; a detection system for measuring arrival positions and flight times of the ions passed through the ion optical system and generating an image of the sample when it is ionized; and a voltage control portion for sweeping the voltage applied to an electrode included in the lens system such that the lens effect of the lens system increases with time during a given period synchronized with the laser irradiation. |
| US09048069B2 |
Dosage accuracy monitoring systems of implanters
An apparatus for monitoring beam currents of an implanter is provided. The apparatus includes a beam-sensing unit for sensing the beam currents; a position-determining unit for determining scan positions; and a computing unit. The computing unit is configured to perform the functions of receiving the beam currents from the beam-sensing unit; receiving the scan positions from the position-determining unit; and determining a drift status of the implanter from the beam currents, wherein the computing unit is configured to receive the beam currents and the scan position periodically between a starting time and an ending time of a scan process of the implanter. |
| US09048066B2 |
Method of etching
A method is for etching successive substrates on a platen in an inductively coupled plasma chamber in which the etching process results in carbonaceous deposits in the chamber. The method includes (a) interrupting the etching processing of substrates, (b) running an oxygen or oxygen containing plasma within the chamber and removing gaseous by-products, and (c) resuming the etch processing of substrates. The method is characterized in that it further includes the step of running an argon plasma in the chamber after step (b) with the platen biased. |
| US09048065B2 |
Methods of using temperature control devices in electron microscopy
Methods of using temperature control devices in electron microscopes. The temperature of the device structure may be controlled to extract information about reactions and processes that was previously unobtainable. |
| US09048058B2 |
Radiation generating tube and radiation generating apparatus using the same
A radiation generating tube, which includes: a cathode connected to an electron gun structure; an anode including a target and configured to generate radiation; and a tubular side wall disposed between the cathode and the anode to surround the electron gun structure; and an electrical potential defining member disposed at an intermediate portion of the tubular side wall between the anode and the cathode. The electrical potential defining member is electrically connected to an electrical potential defining unit via an electrical resistance member or an inductor, and a potential of the electrical potential defining member is defined to be a higher potential than a potential of the cathode and to be a lower potential than a potential of the anode. |
| US09048056B2 |
Glass composition and covering and sealing members using same
A glass composition according to the present invention comprises: transition metals; phosphorus; barium; and zinc, the transition metals including: vanadium; and tungsten and/or iron, the glass composition not containing substances included in the JIG level A and B lists, an softening point of the glass composition being from 430 to 530° C., an average linear expansion coefficient of the glass composition being from 6 to 9 ppm/° C. at temperatures from 30 to 250° C. |
| US09048047B2 |
Micro-reed switch with high current carrying capacity and manufacturing method thereof
A micro-reed switch includes a first magnetic reed and a second magnetic reed. The first magnetic reed includes a first metal electrode and a first non-wettable area. The first metal electrode includes a liquid metal. The second magnetic reed includes a second metal electrode and a second non-wettable area. The first magnetic reed and second magnetic reed is parallel to each other and a gap is defined there between. When a magnetic field is available, the liquid metal and the second metal electrode are engaged with one another by a magnetic force of the magnet. |
| US09048044B2 |
Cursor control device
A cursor control device having a low profile characteristic is disclosed to include a module holder defining an accommodation space and a slot, an operation module having a carrier frame mounted in the accommodation space and inserted through the slot, a rolling roll rotatably and axially movably set in a rotation groove on the carrier frame outside the module holder, and a circuit module having a microprocessor and a sensor module mounted in carrier frame outside the rotation groove and electrically connected with the microprocessor for detecting the direction and amount of movement of the rolling roll. The rolling roll can be directly removed from the carrier frame by the user for cleaning or for a replacement. |
| US09048042B2 |
Domed metal switch having a flange with an actuation protrusion
A connector (100) and connector system are provided. A connector can include a domed metal switch (102) that is partially covered with a liquid impermeable barrier (101) such that a portion of the domed metal switch is exposed and the liquid impermeable barrier is coupled to the domed metal switch with a liquid impermeable junction (221). In a connector system, a complementary connector can include a dome switch actuator (706,707), partially covered with another liquid impermeable barrier. When pressed against the connector, the domed metal switch can deform to contact an electrical conductor (104). A control circuit (1309) can determine whether an electronic device or user is causing the deformation by detecting whether voltage or current is applied to the domed metal switch while deformed. |
| US09048041B2 |
Key press detecting circuit and method for detecting the status of multiple keys through a single pin
A key press detecting circuit and method detect the status of multiple keys through a single pin. In an embodiment, a constant current is provided to apply to a key module through a single pin, to generate a voltage at the single pin that is related to the equivalent resistance of the key module observed from the single pin, and the voltage of the single pin is compared with a set of reference values to identify the status of the plurality of keys. In another embodiment, a variable current is provided to apply to a key module through a single pin in such a way that the variable current is adjusted to maintain a constant voltage at the single pin, and the variable current is compared with a set of reference values to identify the status of the plurality of keys. |
| US09048033B2 |
Press-fit contact accommodated in an electrical device housing
An electrical switch is disclosed, including a switch housing and a busbar routed through a housing opening in the switch housing. In at least one embodiment, a contact element is present for making electrical contact with the busbar, the contact element being clamped in between the busbar and the switch housing in the housing opening. |
| US09048028B2 |
Hybrid electrochemical cell systems and methods
Disclosed herein are systems, devices, and methods for a hybrid electrochemical cell which utilizes two different chemistries in the same cell. According to one aspect, the hybrid cell includes a first pair of electrode units which form a first electrochemical cell and a second pair of electrode units, which form a second electrochemical cell. The second electrochemical cell utilizes a different chemistry than the first electrochemical cells, but both chemistries share a common electrolyte. The hybrid cell further comprises a common electrolyte layer provided between each pair of electrodes. In certain implementations, the common electrolyte layer is a single cavity such that the electrolyte is shared between both the first and the second electrochemical cell. |
| US09048027B2 |
Aluminum foil for aluminum electrolytic capacitor electrode and method for manufacturing the same
A fluid dispersion obtained by mixing oxide particles and water is sprayed to a raw aluminum foil from a direction opposite to a travelling direction of the raw aluminum foil while the raw aluminum foil is allowed to travel. In this way, a roll-pressed mark of the raw aluminum foil is eliminated, and thus aluminum foil for aluminum electrolytic capacitor electrode is produced. Pyramidal-shaped recesses each having an acute angle tip are present all over a surface of the aluminum foil. |
| US09048026B2 |
Multilayered ceramic capacitor, mounting structure of circuit board having multilayered ceramic capacitor mounted thereon, and packing unit for multilayered ceramic capacitor
There is provided a multilayered ceramic capacitor, including: a ceramic body; an active layer including a plurality of first and second internal electrodes; an upper cover layer; a lower cover layer, the lower cover layer being thicker than the upper cover layer; a dummy electrode formed inside at least one of the upper and lower cover layers; and first and second external electrodes, wherein, when A is defined as ½ of an overall thickness of the ceramic body, B is defined as a thickness of the lower cover layer, C is defined as ½ of an overall thickness of the active layer, and D is defined as a thickness of the upper cover layer, a ratio of deviation between a center of the active layer and a center of the ceramic body, (B+C)/A, satisfies 1.063≦(B+C)/A≦1.745. |
| US09048022B2 |
Electromagnetically-countered transformer systems and methods
The present invention relates to an electromagnetically-countered system including at least one wave source irradiating harmful electromagnetic waves and at least one counter unit emitting counter electromagnetic waves which are capable of countering the harmful waves by such counter waves. More particularly, the present invention relates to generic counter units of various electromagnetically-countered transformer systems and to various mechanisms for countering the harmful waves by the counter units by, e.g., matching configurations of such counter units with those of the wave sources, matching shapes of the counter waves with shapes of the harmful waves, and the like. The present invention also relates to various methods of countering the harmful waves with the counter waves by such source matching or wave matching and various methods of providing such counter units as well as emitting the counter waves. The present invention also relates to various processes for providing such systems and their counter units. The present invention further relates to various electric and/or magnetic shields which may be used alone and/or in combination with such counter units to minimize irradiation of the harmful waves from the system. |
| US09048019B2 |
Semiconductor structure including guard ring
One or more embodiments relate to a semiconductor structure, comprising: a conductive feature; an outer guard ring; and an inner guard ring between the outer guard ring and the conductive feature, the inner guard ring being electrically coupled to the conductive feature. |
| US09048017B2 |
Circuits for and methods of implementing a gain stage in an integrated circuit
A circuit for implementing a gain stage in an integrated circuit is described. The circuit comprises a first inductor formed in a first plurality of metal layers; a second inductor formed in a second plurality of metal layers, the second inductor coupled to a center tap of the first inductor; and wherein the second inductor has a diameter that is less than a diameter of the first inductor. A method of implementing a gain stage in an integrated circuit is also described. |
| US09048014B2 |
Permanent magnet and manufacturing method thereof
There are provided a permanent magnet and a manufacturing method thereof capable of decreasing an activity level of a calcined body activated by a calcination process. To fine powder of milled neodymium magnet is added an organometallic compound solution containing an organometallic compound expressed with a structural formula of M−(OR)x (M represents Dy or Tb, R represents a substituent group consisting of a straight-chain or branched-chain hydrocarbon, x represents an arbitrary integer) so as to uniformly adhere the organometallic compound to particle surfaces of the neodymium magnet powder. Thereafter, desiccated magnet powder is held for several hours in hydrogen atmosphere at 200 through 900 degrees Celsius. Thereafter, the powdery calcined body calcined through the calcination process in hydrogen is held for several hours in vacuum atmosphere at 200 through 600 degrees Celsius for a dehydrogenation process. Thereafter, through powder compaction and sintering process, the powdery calcined body is formed into a permanent magnet. |
| US09048008B2 |
Method for forming a vegetable oil having high dielectric purity
A dielectric high purity vegetable oil—free from antioxidants and/or external additives to be used in electric equipment such as transformers, as isolating element and as cooling means and a method for obtaining the same in which the dielectric high purity vegetable oil—is obtained by means of the optimization of the bleaching steps—and deodorizing—from the Refining process—known as Modified Caustic Refining Long-Mix (RBD). |
| US09048007B2 |
Separator structure for Cat 6 cable
A separator structure for Cat 6 cable has a core (2); a shield layer (1) between the core (2) and a jacket, or a jacket (1); four conductor sets (3) each consisting of a pair of conductors (21), and insulating layers (22) covering the conductors provided inside the core (2); and a separator (25) among the four conductor set (3). The separator (25) has a shape of “V”, the bottom end of which is located at the center of the core (2) and the two sides of which respectively separate the adjacent conductor sets (3) from each other. |
| US09048005B2 |
Electric power transmission cable comprising continuously synthesized titanium aluminide intermetallic composite wire
A method of manufacturing wire comprising aluminum oxide particles formed in situ in a fully dense matrix of titanium aluminide intermetallic material by means of the combustion synthesis of aluminum and titanium oxide followed by thermo-mechanical forming. The pre-combustion aluminum may be elemental, or an aluminum alloy containing one or more of the elements vanadium, niobium, molybdenum, or boron. The preferred embodiment of the present invention is an electric power transmission cable comprising a plurality of wires manufactured according to the present invention. |
| US09048004B2 |
Half-heusler alloys with enhanced figure of merit and methods of making
Thermoelectric materials and methods of making thermoelectric materials having a nanometer mean grain size less than 1 micron. The method includes combining and arc melting constituent elements of the thermoelectric material to form a liquid alloy of the thermoelectric material and casting the liquid alloy of the thermoelectric material to form a solid casting of the thermoelectric material. The method also includes ball milling the solid casting of the thermoelectric material into nanometer mean size particles and sintering the nanometer size particles to form the thermoelectric material having nanometer scale mean grain size. |
| US09048002B2 |
Three-dimensional focused anti-scatter grid and method for manufacturing thereof
A device for, and method of manufacture of, a focused anti-scatter grid for improving the image contrast of x-ray images produced in medical, veterinary or industrial applications. The grid comprising a series of modular units so juxtaposed with each other as to form a series of focused channels for the passage of the focused imaging x-rays. The modules comprise a series of focusing ribbons of a heavy metal or a series of mating solid arcuate forms, formed of a polymer and having on at least one side surface a layer of heavy metal. |
| US09048001B2 |
XRF system having multiple excitation energy bands in highly aligned package
An x-ray analysis apparatus for illuminating a sample spot with an x-ray beam. An x-ray tube is provided having a source spot from which a diverging x-ray beam is produced having a characteristic first energy, and bremsstrahlung energy; a first x-ray optic receives the diverging x-ray beam and directs the beam toward the sample spot, while monochromating the beam; and a second x-ray optic receives the diverging x-ray beam and directs the beam toward the sample spot, while monochromating the beam to a second energy. The first x-ray optic may monochromate characteristic energy from the source spot, and the second x-ray optic may monochromate bremsstrahlung energy from the source spot. The x-ray optics may be curved diffracting optics, for receiving the diverging x-ray beam from the x-ray tube and focusing the beam at the sample spot. Detection is also provided to detect and measure various toxins in, e.g., manufactured products including toys and electronics. |
| US09047998B2 |
Method of producing radionuclides
The invention relates to a method of producing radionuclides. According to the method, a target medium comprising at least a target nuclide material is irradiated in an irradiation zone with neutron irradiation. Radionuclides form in the target nuclide material as a result of the irradiation, and at least some of the formed radionuclides are ejected from the target nuclide material. The ejected radionuclides are then captured and collected in a carbon-based recoil capture material which does not have an empty cage structure at crystallographic level. |
| US09047997B2 |
Techniques for on-demand production of medical isotopes such as Mo-99/Tc-99m and radioactive iodine isotopes including I-131
A system for radioisotope production uses fast-neutron-caused fission of depleted or naturally occurring uranium targets in an irradiation chamber. Fast fission can be enhanced by having neutrons encountering the target undergo scattering or reflection to increase each neutron's probability of causing fission (n, f) reactions in U-238. The U-238 can be deployed as layers sandwiched between layers of neutron-reflecting material, or as rods surrounded by neutron-reflecting material. |
| US09047990B2 |
Determination of series resistance of an array of capacitive elements
A circuit for determination of a resistance of an array of capacitive elements includes a reference ring oscillator circuit, the reference ring oscillator circuit being loaded with low-loss capacitive elements; an array test ring oscillator circuit, the array test ring oscillator circuit being loaded with the array of capacitive elements; and a resistance determination module, the resistance determination module configured to determine the resistance of the array of capacitive elements based on data from the reference ring oscillator circuit and the array test ring oscillator circuit. |
| US09047988B2 |
Flash interface error injector
A flash interface error injector for end-of-life testing of a flash-based array includes a plurality of error injection logic blocks that are implemented by one or more processors. Each of the plurality of error injection logic blocks corresponds with a respective flash channel. The flash injector also includes a bit flip probability logic that identifies one or more bits to be flipped. |
| US09047984B2 |
Asymmetric log-likelihood ratio for flash channel
Disclosed is a system and method for reading a flash memory cell with an adjusted read level. A current read level is set to a new read level associated with increasing a first error rate to decrease a second error rate. The first error rate is associated with determining that the most significant bit of the flash memory cell is a binary 1 and the second error rate is associated with determining that the most significant bit is a binary 0. On reading the memory cell, a probability value is generated for the most significant bit, the probability being higher if the bit is equivalent to a binary 0 than if the bit is equivalent to a binary 1. |
| US09047983B2 |
Temperature compensation of conductive bridge memory arrays
Methods for operating a semiconductor memory array including dynamically adjusting control line voltages (e.g., unselected word line or unselected bit line voltages) based on one or more array conditions associated with the semiconductor memory array are described. The one or more array conditions may include a temperature associated with the semiconductor memory array or a particular number of write cycles associated with the semiconductor memory array. In some embodiments, an intermediate voltage is generated based on the one or more array conditions and applied to the unselected word lines and the unselected bit lines of the semiconductor memory array. The one or more intermediate voltages may be generated such that a first voltage difference across unselected memory cells sharing a selected word line is different from a second voltage difference across other unselected memory cells sharing a selected bit line based on the one or more array conditions. |
| US09047978B2 |
Apparatuses and methods for selective row refreshes
Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells. |
| US09047975B2 |
Coding techniques for reducing write cycles for memory
Structures and methods for encoding data to reduce write cycles in a semiconductor memory device are disclosed herein. In one embodiment, a method of writing data to a semiconductor memory device can include: (i) determining a number of significant bits for data to be written in the semiconductor memory device; (ii) determining a tag associated with the data to be written in the semiconductor memory device, where the tag is determined based on the determined number of significant bits; (iii) encoding the data when the tag has a first state, where the tag is configured to indicate data encoding that comprises using N bits of the encoded data to store M bits of the data, where M and N are both positive integers and N is greater than M; and (iv) writing the encoded data and the tag in the semiconductor memory device. |
| US09047973B2 |
Group word line erase and erase-verify methods for 3D non-volatile memory
An erase operation for a 3D stacked memory device assigned storage elements to groups according to an expected erase speed. The storage elements are then erased according to their group to provide a more uniform erase depth and a tighter erase distribution. In one approach, the control gate voltages are set differently for the different groups to slow down the storage elements which are expected to have a faster programming speed. An erase or inhibit status can be set for all groups together. In another approach, the control gate voltages are common for the different groups but an erase or inhibit status is set for each group separately. |
| US09047972B2 |
Methods, devices, and systems for data sensing
Methods, devices, and systems for data sensing in a memory system can include performing a number of successive sense operations on a number of memory cells using a number of different sensing voltages, determining a quantity of the number memory cells that change states between consecutive sense operations of the number of successive sense operations, and determining, based at least partially on the determined quantity of the number of memory cells that change states between consecutive sense operations, whether to output hard data corresponding to one of the number of successive sense operations. |
| US09047971B2 |
Operation for non-volatile storage system with shared bit lines
A non-volatile storage system is disclosed that includes pairs of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. To operate the system, two selection lines are used so that the NAND strings (or other groupings of memory cells) sharing a bit line can be selected at the block level. Both selection lines are connected to a selection gate for each of the NAND strings (or other groupings of memory cells) sharing the bit line. One set of embodiments avoid unwanted boosting during read operations by keeping the channels of the memory cells connected to word lines on the drain side of the selected word line biased at a fixed potential. |
| US09047968B2 |
High capacity low cost multi-state magnetic memory
A multi-state current-switching magnetic memory element includes a stack of magnetic tunneling junction (MTJ) separated by a non-magnetic layer for storing more than one bit of information, wherein different levels of current applied to the memory element cause switching to different states. |
| US09047966B2 |
Architecture of magneto-resistive memory device
Provided is a semiconductor memory device including a column decoder, a plurality of sub-cell blocks, and a bit line selection circuit. The column decoder is configured to decode column addresses and drive column selection signals. Each of the sub-cell blocks includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells connected to the plurality of bit lines and the plurality of word lines. The bit line selection circuit includes a plurality of bit line connection controllers, and is configured to select one or more bit lines in response to the column selection signals. Each of the bit line connection controllers electrically couples a respective first bit line to corresponding first and second local input/output (I/O) lines in response to first and second column selection signals of the column selection signals, respectively. |
| US09047965B2 |
Circuit and method for spin-torque MRAM bit line and source line voltage regulation
Circuitry and a method for regulating voltages applied to source and bit lines of a spin-torque magnetoresistive random access memory (ST-MRAM) reduces time-dependent dielectric breakdown stress of the word line transistors. During a read or write operation, only the selected bit lines and source lines are pulled down to a low voltage and/or pulled up to a high voltage depending on the operation (write 0, write 1, and read) being performed. The unselected bit lines and source lines are held at the voltage while separately timed signals pull up or pull down the selected bit lines and source lines during read and write operations. |
| US09047959B1 |
Data storage device, memory control method, and electronic device with data storage device
According to one embodiment, a data storage device comprises a buffer memory and a controller. The buffer memory stores a data group including sector unit data with addresses specified by a host, the data group in unit of page includes a plurality of addresses. The controller comprises an adding module configured to be operative, if the sector unit data with addresses specified by the host as valid addresses for write targets are stored in the buffer, to add information that identifies a last address included in valid addresses belonging to the same page addresses and specified by the host and starting with a start address, to a single sector unit data with the last address. |
| US09047956B2 |
Concurrent operation of plural flash memories
A device comprises an address storage device. A first circuit includes a first flash memory, configured to sequentially receive first and second addresses and store the first address in the address storage device. The first circuit has a first set of control inputs for causing the first circuit to perform a first operation from the group consisting of read, program and erase on a cell of the first flash memory corresponding to a selected one of the first and second addresses. A second circuit includes a second flash memory, configured to receive the second address. The second circuit has a second set of control inputs for causing the second circuit to read data from a cell of the second flash memory corresponding to the second address while the first operation is being performed. |
| US09047954B2 |
Bit line resistance compensation
Methods for compensating for variations in bit line resistance during sensing of memory cells are described. The variations in bit line resistance may occur die-to-die or plane-to-plane on the same die. In some embodiments, for each die or memory plane on a die, a plurality of bit line read voltages associated with a plurality of zones may be determined based on sensing criteria. The sensing criteria may comprise a number of fail bits. Each zone of the plurality of zones may be associated with a memory array region within a die or memory plane. Prior to performing a read or verify operation on a group of memory cells, a bit line read voltage used during sensing of the group of memory cells may be determined based on the plurality of bit line read voltages and a zone associated with the group of memory cells. |
| US09047952B2 |
Nonvolatile memory devices and methods forming the same
Provided are nonvolatile memory devices and methods of forming the same. The nonvolatile memory device includes a plurality of word lines, a ground select line, string select line, and a dummy word line. Each of distances between the dummy word line and the ground select line and between the dummy word line and the word line is greater than a distance between a pair of the word lines adjacent to each other. |
| US09047950B2 |
Read-disturbance-free nonvolatile content addressable memory (CAM)
Voltage controlled magnetoelectric tunnel junction (MEJ) based content addressable memory is described which provides efficient high speed switching of MEJs toward eliminating any read disturbance of written data. Each cell of said CAM having two MEJs and transistor circuitry for performing a write at voltages of a first polarity, and reads at voltages of a second polarity. If the data searched does not equal the data written in the CAM, then the match line state is changed. |
| US09047944B2 |
Resistance variable memory sensing
The present disclosure includes apparatuses and methods for sensing a resistance variable memory cell. A number of embodiments include programming a memory cell to an initial data state and determining a data state of the memory cell by applying a programming signal to the memory cell, the programming signal associated with programming memory cells to a particular data state, and determining whether the data state of the memory cell changes from the initial data state to the particular data state during application of the programming signal. |
| US09047942B2 |
Non-transitory computer-readable media describing a hybrid volatile and non-volatile memory device with an overlapping region of addressable range of storage cells
Non-transitory computer-readable media having information embodied therein that includes a description of an integrated circuit device. The information includes descriptions of a volatile storage die having a first addressable range of storage cells and a non-volatile storage die. The description of the non-volatile storage die having a second addressable range of storage cells that defines an overlapping region with the first addressable range of storage cells. The information also includes a description of an interface circuit coupled to the volatile and non-volatile storage die to selectively transfer data stored in the overlapping region of storage cells between the die. |
| US09047938B2 |
Phase change memory management
A three dimensional (3D) stack of phase change memory (PCM) devices which includes PCM devices stacked in a 3D array, the PCM devices having memory regions; a memory management unit on at least one of the PCM devices; a stack controller in the memory management unit to monitor an ambient device temperature (Tambient) with respect to a neighborhood of memory regions in the PCM devices and to adjust a programming current with respect to at least one of the memory regions in the neighborhood of memory regions in accordance with the Tambient. Also disclosed is a method of programming a PCM device. |
| US09047936B2 |
Memory device having control circuitry for write tracking using feedback-based controller
A memory device includes a memory array comprising a plurality of memory cells, and control circuitry coupled to the memory array. The control circuitry comprises at least one dummy memory cell, a feedback-based controller having inputs coupled to respective internal nodes of the dummy memory cell, and write signal generation circuitry coupled to the feedback-based controller and configured to provide one or more write signals for controlling writing of data to portions of the memory array. The feedback-based controller generates a reset signal for application to a reset input of the write signal generation circuitry at least in part as a function of a logic level transition delay of a selected one of the first and second internal nodes of the dummy memory cell. |
| US09047935B2 |
Read timing generation circuit
Disclosed is a read timing generation circuit, capable of reducing dynamic power consumption. After a multi-bit address Add1, Add2, . . . , and AddN passes through an address change monitoring unit (100), a response pulse signal corresponding the address is generated. After the response pulse signal passes through an address trigger determination unit (200), a single trigger determination signal ATDPRE is generated. The single trigger determination signal ATDPRE passes through an ATD timing generation unit (300) and a post-timing generation unit (1000), thereby forming a read timing generation circuit in a serial link and generating corresponding read timing. Compared with the conventional read timing generation circuit in which each bit of an address signal corresponds to a stage of structures to execute the trigger, ATD control timing output, and ATD determination process separately, the present invention greatly reduces the total dynamic power consumption of the circuit. |
| US09047927B2 |
Semiconductor device latching data signal in response to strobe signal and information processing system including the same
Disclosed herein is a device including a timing control circuit that receives a strobe signal supplied from outside to generate an internal strobe signal that is used as a timing signal to latch a data signal. An operation state of the timing control circuit is changed according to temperature change so as to keep an output timing of the internal strobe signal with respect to an input timing of the strobe signal. |
| US09047926B2 |
Dual thermal sensor for HAMR waveguide power monitor and integration with the contact sensor
Embodiments of the present invention generally relate to a HAMR device having two temperature sensors. The first temperature sensor is disposed adjacent a waveguide and is about two or more micrometers away from an air bearing surface. The first temperature sensor has a length, a width and a thickness, and the length is greater than the width and the thickness. The length of the first temperature sensor is substantially perpendicular to the waveguide. |
| US09047925B2 |
Spindle motor, and disk drive apparatus including the spindle motor
A spindle motor includes a shaft arranged to extend in an axial direction, and a base portion arranged to define a portion of a housing, and including a through hole in which the shaft is inserted. A fixing region is defined between an inner circumferential portion of the base portion and a lower portion of the shaft. The fixing region includes a press-fitting region and an adhesion region defined on a lower side of the press-fitting region and in which a seal gap is defined between the inner circumferential portion of the base portion and the lower portion of the shaft. The seal gap is arranged to gradually decrease in radial width with increasing height. The seal gap is arranged to include an adhesive arranged therein over an entire circumference thereof. |
| US09047922B2 |
Autonomous event logging for drive failure analysis
A method and system for providing autonomous event logging and retrieval for failure analysis. In one implementation, storage device firmware monitors and records events (e.g., storage device errors and/or failures) to the storage device flash in substantially real time from power on of the storage device to power off. Additionally, diagnostic data relating to an event, including a time stamp and storage device environmental conditions are recorded. The logged event data may be utilized to streamline failure analysis by determining whether the storage device failed and if so, when the storage device failed and what the conditions of the storage device were at the time of the failure. Such information may be used for failure, warranty, integrator, and/or troubleshooting analysis. |
| US09047921B2 |
Adjusting recording density in a circumferential direction
Approaches for adjusting the recording density of a recording medium in a circumferential direction are disclosed. A hard-disk drive includes one or more electronic components configured to divide a track, of a plurality of concentric tracks on a magnetic-recording disk, into a plurality of portions, and write data to each of the plurality of portions at a recording density that is independent of the recording density used for any of the other portions. Data may be written to a first portion of a track at a different frequency than to a second portion of the same track. The frequency at which data is written may be adjusted for different portions of the same track to allow the frequency to be reduced at certain portions shown to have relatively higher soft error rate while increasing the frequency for other portions to achieve a desired average error rate for the track. |
| US09047920B2 |
Multitrack recorder and mixdown method
An apparatus and a method for efficiently converting, by means of mixdown, audio signals recorded in multiple tracks into stereo signals.A plurality of audio signals input from an input terminal are recorded into a plurality of tracks of a recording medium. A mixer reads the audio signals recorded in the multiple tracks, subjects the audio signals to mixdown according to a mixer parameter set by an operation section, and records the processed signals as audio signals in the recording medium without reproducing the processed signal in real time. A plurality of mixer parameters are set, and a user can select a desired mixer parameter. |
| US09047919B1 |
Disk drive initializing servo read channel by reading data preceding servo preamble during access operation
A disk drive is disclosed comprising a disk having a plurality of data tracks defined by servo sectors, where each data track comprises a plurality of data sectors, and each servo sector comprises a servo preamble and servo data. The disk drive further comprises a head comprising a read element and a write element, and a servo read channel comprising an analog front end and a timing recovery circuit. During an access operation, data preceding the servo preamble of a first servo sector in the first data track is read in order to initialize the analog front end of the servo read channel. At least part of the servo preamble is read to initialize the timing recovery circuit of the servo read channel, and at least part of the servo data of the servo sector is read using the timing recovery circuit. |