最新美国发明专利第2011-10-04期 - 专利汇|PatentHub专利检索|专利查询网|发明专利查询分析

Document	Document Title
US08031587B1	Method and device of synchronizing symbol timing, and OFDM communication system To synchronize symbol timing in a communication system, time-domain signals are generated by performing an IFFT on frequency-domain signals. Positions of power peaks are detected by analyzing a channel impulse response (CIR) of the time-domain signals. Channel state informations are provided by analyzing a channel state, such that each channel state information corresponds to each position of the power peaks. A proper symbol start position is determined based on the channel state informations.
US08031582B2	Optical information recording medium, BCA information recorder, and BCA information recording method Multilayered optical information recording media involve a problem that a BCA is erroneously formed in a different information recording layer even if the BCA is intended to be formed in a specific information recording layer.An optical information medium (1) for recording/reproducing information by applying a laser beam includes two or more recording layers (11, 12) for recording/reproducing information by receiving a laser beam at the same laser beam incident surface (1a). A geometrical irregularity (K) is formed in an area (inner peripheral side) (21) for a BCA on one recording layer (12), and a mirror surface is formed in the area of the other information recording layer (11) corresponding to the BCA area (21). The geometrical irregularity (K) is detected when focus servo is actuated so as to detect the desired information recording layer. Thus, a BCA is prevented from being erroneously formed in another information recording layer.
US08031580B1	Recording media with features to render media unreadable and method and apparatus for replication of said media Optical recording media configured to deter unauthorized access are described. Methods for manufacturing the optical recording media described above are also presented.
US08031575B2	Optical pickup device and recording/reproducing device An optical pickup device has a near-field optical system having a numerical aperture of NA>1; a first light source emitting a first light having a first wavelength; a second light source emitting a second light having a second wavelength; an optical system multiplexing the first light and second light and irradiating the multiplexed light onto an optical recording medium having at least two recording layers; a first photodetector detecting the first light returned from the recording medium a second photodetector detecting the second light returned from the recording medium; a controller obtaining a signal corresponding to distance between the near-field optical system and the recording medium based on the returned second light, and obtaining a reproducing signal and a tracking signal of the recording medium and a focus signal corresponding to the recording layer based on the returned first light; and a focus position adjustment mechanism moving a focus position of the first light under control of the focus signal.
US08031562B2	Master disk for magnetic transfer, a method of drawing a magnetic transfer pattern, and a magnetic recording medium having a transferred magnetic transfer pattern A master disk for magnetic transfer of a reference servo signal in a spiral mode, having a pattern including a plurality of dots groups, which are disposed at different radial positions of the master disk with a first pitch, and correspond to the reference servo signal in the spiral mode. Each of the plurality of dot groups includes a plurality of dots, successively disposed with a second pitch along a circumferential direction of the master disk at a same one of the radial positions. Each of the plurality of dots is of a ferromagnetic material, and has four sides, two opposing sides thereof extending in the circumferential direction, and the other two opposing sides thereof extending in a radial direction of the master disk.
US08031558B2	Forced acoustic dipole and forced acoustic multipole array using the same Provided is a forced acoustic dipole capable of regulating phases and acoustic pressures of first and second acoustic signals output from first and second pole speakers to freely steer the direction of an acoustic lobe. In addition, a forced acoustic multipole array is constituted by a plurality of forced acoustic dipoles. When the phases and acoustic pressures of the first and second acoustic signals output from the forced acoustic dipoles are regulated to steer an acoustic lobe in a specific direction, sound can be heard from a desired direction only without disturbing others.
US08031554B2	Circuit and method for controlling loading of write data in semiconductor memory device A circuit for controlling the loading of write data in a semiconductor memory device includes a global bus; a data block configured to selectively load data of a predetermined first burst length or data of a second burst length, which is a half of the first burst length, for writing on the global bus in response to a control signal; and a memory bank configured to write the data of the first burst length or the data of the second burst length.
US08031551B2	Systems, methods and devices for monitoring capacitive elements in devices storing sensitive data Power-backup capabilities are provided by implementing a variety of different methods, systems and devices. According to one such implementation, a data storage device stores data in response to data accesses under the control of a memory control circuit. A solid-state memory circuit and a volatile caching memory circuit provide the memory control circuit with access to a set of common data. A power-reservoir circuit includes two or more capacitor cells that respectively hold charge to provide operating power to the data storage device to permit transfer of the data from the volatile memory circuit to the solid-state memory circuit in the event of a power loss. A detection circuit is connected to a center tap between the capacitor cells and uses the tap to detect characteristics of the cells relative to one another, and to provide an output that can be used to characterize the cells' electrical characteristics relative to one another.
US08031550B2	Voltage regulator circuit for a memory circuit A voltage regulator circuit for a memory circuit comprises a voltage divider, a capacitor, an active-mode voltage regulator and a standby-mode voltage regulator. The active-mode voltage regulator is always on while in active mode, and turned on whenever a refresh is requested. The standby-mode voltage regulator is periodically turned on while in standby mode, and turned on whenever a refresh is requested. In addition, the active voltage regulator uses stronger transistors than those used by the standby-mode voltage regulator, and both the active-mode voltage regulator and the standby-mode voltage regulator are coupled to the voltage divider and the capacitor.
US08031547B2	Differential sense amplifier A differential sense amplifier can perform data sensing using a very low supply voltage.
US08031546B2	Semiconductor device In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced. In another aspect, power consumption is reduced by changing from the active to the inactive state in a time period from a write command issuing to a next command issuing.
US08031544B2	Semiconductor memory device with three-dimensional array and repair method thereof A nonvolatile memory device includes a three-dimensional (3D) cell array, a column selection circuit and a fuse block. The 3D cell array includes multiple cell arrays located in corresponding stacked substrate layers, the cell arrays sharing a bit line. The column selection circuit selects a memory unit included in the 3D cell array. The fuse block controls the column selection circuit to repair defective columns with one of multiple redundant bit lines located in the 3D cell array.
US08031543B2	Memory chip having a complex termination A memory chip has a signal line and a complex impedance which is connected to the signal line for termination of the signal line. A memory having such a memory chip and a method for operating a memory chip are also described. The memory chip on the memory having a signal line that is terminated with a complex impedance.
US08031542B2	Low leakage ROM architecture A Read only memory (ROM) with minimum leakage includes a ROM array including a first transistor, wherein a drain, a source, a gate, and a bulk of the first transistor is electrically connected to a logic zero in the idle state for ensuring zero junction and sub-threshold leakage current. The drain of the first transistor is electrically connected to a main bit line through a second transistor. The second transistor includes a gate, electrically connected to a first decoding circuit, a drain, electrically connected to the main bit line. A first reference bit line is electrically connected to a drain of a third transistor, wherein gate of the third transistor is electrically connected to a second decoding circuit for generating a stop read signal. A second reference bit line, electrically connected to the first decoding circuit through a first sensing unit for generating a stop pre-charge signal.
US08031540B2	Randomizing current consumption in memory devices In some implementations, a memory device includes a plurality of memory cells, each memory cell storing a plurality of data bits; an input/output interface that is configured to, in response to receiving a read signal and an address value that identifies a specific memory cell in the plurality of memory cells, output a plurality of data bits corresponding to the identified specific memory cell; and a delay controller that is configured to delay the outputting to the input/output interface of at least one of the plurality of data bits based on a randomly selected or pseudo-randomly selected delay value. The memory device can further include a delay block having a plurality delay paths having varying delays, and randomly selecting or pseudo-randomly selecting the delay value can include randomly selecting or pseudo-randomly selecting one of the plurality of delay paths through which to transmit a control signal.
US08031537B2	Time reduction of address setup/hold time for semiconductor memory In the storage device of the invention, latch control is performed on a series of signals in response to latch control signals. Latch control terminals are provided to which the latch control signals are input respectively and a plurality of signal terminals to which a series of signals are input. Herein, a plurality of latch circuits is provided so as to correspond to the plurality of signal terminals, respectively. The plurality of latch circuits are located within a specified distance from their associated signal terminals respectively and within a specified distance from the latch control terminals. The delays of signal transmission from the signal terminals to their associated latch circuits can be equalized and the delays of signal transmission from the latch control terminals to which the latch control signals for executing latch control are input to the latch circuits can be equalized. This contributes to a reduction in the skew of the latch characteristics of the signals.
US08031532B2	Methods of operating embedded flash memory devices Flash memory device structures and methods of manufacture thereof are disclosed. The flash memory devices are manufactured on silicon-on-insulator (SOI) substrates. Shallow trench isolation (STI) regions and the buried oxide layer of the SOI substrate are used to isolate adjacent devices from one another. The methods of manufacture require fewer lithography masks and may be implemented in stand-alone flash memory devices, embedded flash memory devices, and system on a chip (SoC) flash memory devices.
US08031527B2	Semiconductor device and method for adjusting reference levels of reference cells A semiconductor device includes a first reference cell used for programming or reading non-volatile memory cells, and an adjustment circuit adjusting a first reference level of the first reference cell when the first reference level is changed.
US08031525B2	Flash memory device and program method thereof A flash memory device that includes a voltage generator circuit configured to generate a program voltage, a pass voltage, and a high voltage; a plurality of planes configured to perform a program operation in response to the program, pass, and high voltages and to verify the program operation, respectively; and control logic configured to control the planes in response to verification results from the planes, wherein the control logic controls the planes so as to interrupt the program and pass voltages or the high voltage from being applied to program-passed planes.
US08031521B1	Reprogramming non-volatile memory devices for read disturbance mitigation The present disclosure includes systems and techniques relating to non-volatile memory. The systems and techniques can include accessing a threshold value that is associated with a data area of a non-volatile memory structure, performing a comparison using the threshold value and a first value associated with the data area, and selectively reprogramming data of the data area based on the comparison. A programming operation on the data area can trigger a reset of the first value. Accessing a threshold value can include accessing a second value that reflects a count of programming operations on the data area or a time between programmings and using the second value to select the threshold value.
US08031519B2	Shared line magnetic random access memory cells A memory unit with one field line; at least two thermally-assisted switching magnetic tunnel junction-based magnetic random access memory cells, each cell comprising a magnetic tunnel junction having an insulating layer disposed between a magnetic storage layer and a magnetic reference layer; wherein a selection transistor is connected to the magnetic tunnel junction; the one field line is used for passing a field current for switching a magnetization of the storage layer of the magnetic tunnel junctions of the cells. A magnetic memory device can be formed by assembling an array of the memory units, wherein at least two adjacent magnetic tunnel junctions of the cells can be addressed simultaneously by the field line. The memory unit and magnetic memory device have a reduced surface area. Magnetic memory devices with an increased density of memory units can be fabricated resulting in lower die fabrication cost and lower power consumption.
US08031518B2	Methods, structures, and devices for reducing operational energy in phase change memory Methods of forming and operating phase change memory devices include adjusting an activation energy barrier between a metastable phase and a stable phase of a phase change material in a memory cell. In some embodiments, the activation energy barrier is adjusted by applying stress to the phase change material in the memory cell. Memory devices include a phase change memory cell and a material, structure, or device for applying stress to the phase change material in the memory cell. In some embodiments, a piezoelectric device may be used to apply stress to the phase change material. In additional embodiments, a material having a thermal expansion coefficient greater than that of the phase change material may be positioned to apply stress to the phase change material.
US08031517B2	Memory device, memory system having the same, and programming method of a memory cell A method of writing multi-bit data to a semiconductor memory device with memory cells storing data defined by a threshold value, the method comprising, for each memory cell, writing a least significant bit, verifying completion of writing the least significant bit, verifying including comparing a written value to one of a low least significant bit verification value and a high least significant bit verification value, and writing a next significant bit upon completion of writing the least significant bit.
US08031516B2	Writing memory cells exhibiting threshold switch behavior A memory cell exhibiting threshold switch behavior, such as a phase change memory, can be programmed in a way that eliminates the need for a separate post-programming verification cycle. In particular, a circuit can be used to apply the programming pulse to a cell in a way that determines whether the cell has reached the desired threshold voltage. If the cell has not reached the desired threshold voltage, it receives another programming pulse. If it has, it does not receive another programming pulse. Thus, by applying a voltage across the cell that never exceeds the threshold voltage of the cell, the need for a separate verification cycle can be eliminated in some embodiments.
US08031513B2	Semiconductor device and method of operating thereof A semiconductor device includes: a memory cell; a precharge circuit; a negative potential applying circuit; and a sense amplifier. The memory cell is connected to a first bit line and store data. The precharge circuit is connected to the first and second bit lines and precharges the first and second bit lines to a ground potential. The negative potential applying circuit is connected to the first bit line and applies a negative potential to the first bit line. The sense amplifier is connected to the first and second bit lines and read data based on a difference between a first potential of the first bit line and a second potential of the second bit line. An absolute value of the negative potential is smaller than the difference between the first potential and the second potential.
US08031512B2	Multiple-valued DRAM Provided herein is an MV DRAM device for storing multiple value levels using an SET device. The device includes one or more word lines; one or more bitlines; a DRAM cell connected to intersections of the word lines and the bitlines; a current source transistor having a source connected to a power supply voltage and a gate and a drain connected to the bitlines; an SET (single electron transistor) device having a gate connected to the bitlines and a source connected to the ground voltage; and a transistor connected between the bitlines and the drain of the SET device, where the gate of the transistor is connected to the ground voltage.
US08031511B2	Semiconductor device At the time of, for example, a set operation (SET) for making a phase-change element in a crystalline state, a pulse of a voltage Vreset required for melting the element is applied to the phase-change element, and subsequently a pulse of a voltage Vset that is lower than Vreset and is required for crystallizing the element is applied thereto. And, the magnitude of this voltage Vset is then changed depending on the ambient temperature so that the magnitude of the voltage Vset is small as the temperature becomes high (TH). In this manner, a margin of a write operation between the set operation and a reset operation (RESET) for making the element to be in amorphous state is improved.
US08031509B2	Conductive metal oxide structures in non-volatile re-writable memory devices A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).
US08031507B2	Semiconductor memory device The sense amplifier detects and amplifies a signal read via bit lines from the ferroelectric capacitor of the memory cell. The dummy capacitor provides a reference voltage to bit lines. The dummy capacitor includes a first dummy capacitor and a second dummy capacitor. The first dummy capacitor is provided with a first dummy plate potential at one end to set the reference voltage to a certain potential. The other end is connected to the bit line. The second dummy capacitor is provided with a second dummy plate potential at one end to fine-tune the reference voltage from the certain potential. The other end thereof is connected to the bit line.
US08031506B2	One-time programmable memory cell A disclosed embodiment is a programmable memory cell having improved IV characteristics comprising a thick oxide spacer transistor interposed between a programmable thin oxide antifuse and a thick oxide access transistor. The spacer transistor separates a rupture site formed during programming the programmable antifuse from the access transistor, so as to result in the improved IV characteristics. The programmable antifuse is proximate to one side of the spacer transistor, while the access transistor is proximate to an opposite side of the spacer transistor. The source region of the access transistor is coupled to ground, and the drain region of the access transistor also serves as the source region of the spacer transistor. The access transistor is coupled to a row line, while the spacer transistor and the programmable antifuse are coupled to a column line. The rupture site is formed during programming by applying a programming voltage to the programmable antifuse.
US08031504B2	Motherboard and memory device thereof A memory device can be directly mounted on a motherboard supporting DDR3 SDRAM, and then the memory device have advantages of the fly-by bus topology and the T branch topology established by the joint electron device engineering council (JEDEC). Thus, the system performance of a desktop computer in a unit interval can be enhanced.
US08031503B1	System for dynamically managing power consumption in a search engine The power consumption of a search engine such as a CAM device is dynamically adjusted to prevent performance degradation and/or damage resulting from overheating. For some embodiments, the CAM device is continuously sampled to generate sampling signals indicating the number of active states and number of compare operations performed during each sampling period. The sampling signals are accumulated to generate an estimated device power profile, which is compared with reference values corresponding to predetermined power levels to generate a dynamic power control signal indicating predicted increases in the device's operating temperature resulting from its power consumption. The dynamic power control signal is then used to selectively reduce the input data rate of the CAM device, thereby reducing power consumption and allowing the device to cool.
US08031501B1	Segmented content addressable memory device having pipelined compare operations Present embodiments describe a CAM device having a segmented CAM array. Each segment of the CAM array, or cell blocks, includes one or more rows of CAM cells. One or more of the cell blocks in the CAM array are selectively enabled during a search operation based on a detected matching condition of another cell block. By selectively enabling cell blocks during search operations only when needed, energy consumption is reduced. Selectively enabling a cell block includes selectively pre-charging match lines to the cell block, selectively enabling word lines to the cell block, and selectively enabling comparand line to the cell block. In accordance with certain embodiments, the CAM device is configurable to perform search operations in a pipelined manner. Accordingly, the CAM device is capable of performing multiple search operations simultaneously.
US08031497B2	Three-leg power converter apparatus A three-leg power converter apparatus including first, second and third input/output ports, a three-leg bridge converter, a filter circuit, a decoupling circuit and a controller is presented. The three-leg bridge converter has three single-leg circuits, two DC terminals connecting to two terminals of the first input/output port, and three mid-terminals with each of them being formed by a middle point of one of the three single-leg circuits. The controller connects to the three-leg bridge converter for controlling an input or output current passing through each DC terminal and mid-terminal. The filter circuit connects between two of the mid-terminals and the second input/output port. The decoupling circuit has two terminals connecting to the second input/output port and another terminal connecting to a terminal of the third input/output port, with the third input/output port having another terminal connecting to the other mid-terminal that dose not connect with the filter circuit.
US08031496B2	Driving circuit for power switching device, driving method thereof, and switching power supply apparatus A driving circuit includes a generation unit configured to generate a driving signal for turning on and off a power switching device, the driving signal having plural levels of voltage at which the power switching device is turned on. The driving circuit also includes a switching control unit configured to switch between the plural levels of voltage at which the power switching device is turned on, depending on a status of the power switching device.
US08031492B2	PWM controller for compensating a maximum output power of a power converter A PWM controller having an oscillator, a control circuit and a two-level limiter is provided. The oscillator generates a pulse signal. The control circuit couples to the oscillator for generating a PWM signal in response to the pulse signal, wherein the PWM signal controls a power switch. The two-level limiter couples to the control circuit for generating a two-level limit signal in response to an on-time of the PWM signal, wherein the two-level limit signal is formed by a first-level signal and a second-level signal during a switching period of the PWM signal, and the first-level signal is used to limit the maximum output power of the power converter under a high-line input voltage with a heavy-load condition, and the second-level signal is used to limit the maximum output power of the power converter under a low-line input voltage with the heavy-load condition.
US08031486B2	Electrical distribution system and modular high power board contactor therefor An electrical distribution system provides a Line Replaceable Modules (LRM) with a printed wire board (PWB) which is of a relatively thick construction. The PWB is manufactured of a relatively thick construction to provide structural support for a multitude of electrical components as well as a board mounted contactor. Each contactor is mounted directly to the PWB. As the primary contactor switch function is board mounted, support functions such as coil drivers, economizing switches, auxiliary switches become PWB mounted components that are assembled to the PWB for communication through the board circuit traces rather than the heretofore required wiring harnesses.
US08031480B2	Structure for mounting feedthrough capacitors In a structure for mounting a first feedthrough capacitor and a second feedthrough capacitor on a mounting surface of a substrate, the first and second feedthrough capacitors are disposed so as to be substantially parallel and to face each other in their partial regions, and a current in the partial region of the first feedthrough capacitor flows in a direction opposite to that in the partial region of the second feedthrough capacitor.
US08031478B2	Power conversion apparatus A power conversion apparatus comprising a base 110 which includes a first fixation portion 110a and a second fixation portion 110b that are coupled to each other at a desired angle, wherein power modules IPM1, IPM2 and IPM3 are fixed on the first fixation portion 110a of the base 110, a control circuit board 10 is fixed with its first principal surface 10a held in direct or indirect touch with the second fixation portion 110b of the base 110, and components constituting a control circuit are packaged on the second principal surface 10b of the control circuit board 10. Owing to the configuration, a versatility for the installation of the power conversion apparatus on a vehicle becomes high, the vibration-proofness of the control circuit board is enhanced, and heats generated by the electronic components, etc. packaged on the control circuit board are sufficiently emitted.
US08031477B2	System and method for coupling a lens to a printed circuit An optical assembly is disclosed which may include a lens having first and second electrodes; and a flexible printed circuit (FPC) configured for placement in proximity to the lens, wherein the FPC may include a bottom insulating layer; a top insulating layer; and an FPC electrode configured to contact the second electrode of the lens, wherein the FPC electrode may include a center portion disposed between the bottom and top insulating layers of the FPC; a post connected to the center portion and extending through the top insulating layer of the FPC; and a contact layer connected to the post and configured to provide the contact with the second electrode of the lens.
US08031472B2	Electronic device with weather-tight housing An electronic device includes a housing with electrical circuitry that is sealed against penetration by dust, moisture, water, and the like, and permits convenient mounting and reconfiguration during operation. The electronic device can be reconfigured to add or delete a connecting plug and cable without compromising the seal. Mounting brackets are provided for mounting to both horizontal and vertical support structures, depending on orientation of the brackets.
US08031471B2	Secure transparent enclosure for communication device An enclosure comprises first and second sections formed of a transparent material, a plurality of wall sections, a plurality of vent holes, a hinge, a cable access and a lock. The wall sections are joined to the first section to form the enclosure. The vent holes are formed in the wall sections to provide thermal flow through the enclosure. The hinge connects the second section to one of the plurality of wall sections to form a door in the enclosure. The cable access is located to allow authorized power and data connections within the enclosure when the door is in an open position, and sized to prevent unauthorized data connections within the enclosure when the door is in a closed position. The lock secures the enclosure by locking the door in the closed position.
US08031469B2	Electronic device According to one embodiment, the electronic device includes a housing, the first to third printed circuit boards, and a fan unit. The first printed circuit board includes the first heat-generating part secured to the first wiring board. The second printed circuit board includes the second and third heat-generating parts, has an amount of heat generation larger than that of the first printed circuit board, and is located between the first printed circuit board and the second wall. The third printed circuit board includes the fourth heat-generating part, has an amount of heat generation smaller than that of the first printed circuit board, and is located between the first printed circuit board and the first wall.
US08031468B2	Hot aisle containment cooling unit and method for cooling A cooling unit, which is configured to contain and cool air between two rows of equipment racks defining a hot aisle, includes a housing configured to be secured mounted on the two rows of equipment racks such that the housing spans the hot aisle, a heat exchanger supported by the housing and coupled to and in fluid communication with a coolant supply and a coolant return, and an air movement assembly supported by the housing and configured to move air over the heat exchanger. Other embodiments of the cooling unit and methods of cooling are further disclosed.
US08031466B2	Thermal management of a personal computing apparatus A method and system are provided for thermal management of a portable computing apparatus. Accelerometers are provided to detect changes in attitude, and temperature sensors are provided to detect changes in temperature. A fan is used to cool the internal temperature of the electronic components of the computer. In response to lift of the computer from a stationary surface, the computer may transition to an alternative state of operation. The transition may include the change of the speed of the fan and/or adjustment of the processor clock.
US08031465B2	Electronic apparatus The invention discloses an electronic apparatus comprising a motherboard, a connector, a card member and a first holder. The connector is disposed on the motherboard and the card member is disposed on the connector. The motherboard comprises a first fixing portion and the card member comprises a second fixing portion. The first holder comprises a third fixing portion fixed to the first fixing portion of the motherboard and a fourth fixing portion fixed to the second fixing portion of the card member. Accordingly, once the motherboard or the card member is hit or pulled by an external force, since two ends of the first holder respectively fix the card member and the motherboard, the card member will not be detached from the connector, such that the card member can be connected to the connector well.
US08031464B2	Ruggedized computer capable of operating in high-temperature environments Illustrative embodiments of the present invention are directed to a computer that has a housing with walls that form a substantially sealed interior cavity from an exterior environment. The computer includes a plurality of computer components within the interior cavity. The computer also includes at least one heat sink for dissipating thermal energy into the exterior environment. A cooling element is thermally coupled to the heat sink and at least one of the computer components to transfer thermal energy from the computer component into the heat sink and the exterior environment.
US08031462B2	Molded component, electronic apparatus, and method of producing a molded component A molded component includes: a primary molded layer including a boxlike base portion that has a width direction in a first direction, a length direction in a second direction, and a height direction in a third direction and includes a first surface protruding in the third direction and a second surface that forms a spatial portion on the other side of the first surface, and a pedestal portion protruding outwardly in parallel to the first direction and the second direction from a circumferential edge of the base portion; a secondary molded layer formed of an optically-transparent resin material, that is laminated on the primary molded layer and has the same width and length as the primary molded layer; and an in-mold layer formed between the primary molded layer and the secondary molded layer.
US08031460B2	Multilayer capacitor A first internal conductor has a first portion. A second internal conductor has a lead portion and a main electrode portion. The second internal conductor is arranged in the same layer as the first internal conductor. A third internal conductor has a lead portion and a main electrode portion. The third internal conductor is arranged so as to be adjacent to the second internal conductor in a laminate direction. A fourth internal conductor has a lead portion and a main electrode portion. The fourth internal conductor is arranged so as to be adjacent to the third internal conductor in the laminate direction. When the laminate body is viewed from the laminate direction, the main electrode portion of the third internal conductor overlaps with the main electrode portions of the second and fourth internal conductors. A width of the first portion is smaller than a width of the main electrode portion of the second internal conductor in the longitudinal direction of the laminate body and a width of the main electrode portion of the second internal conductor in the transverse direction of the laminate body.
US08031459B2	Movable micro-device A micro-device includes a movable part, a frame and a connecting part. The movable part has a main portion, a first capacitor electrode and a first driver electrode. The capacitor electrode and the driver electrode have electrode teeth extending from the main portion. The frame includes second capacitor and driver electrodes, where the second capacitor electrode has electrode teeth extending toward the first capacitor electrode, and the second driver electrode has electrode teeth extending toward the first driver electrode. The connecting part connects the movable part to the frame. The first and second capacitor electrodes have their electrode teeth overlapped in their initial position. The movable part is rotatable for varying the extent of the overlapping between the first and second driver electrodes.
US08031458B2	Current return network A composite moving apparatus made substantially of composites may include a plurality of longitudinal conductive electrical pathways extending along a substantial length of the composite moving apparatus, and a plurality of lateral conductive electrical pathways extending along a substantial lateral width of the composite moving apparatus. The longitudinal and lateral conductive electrical pathways may be connected in order to provide redundant electrical pathways extending along a substantial portion of the composite moving apparatus. The redundant electrical pathways may carry return current, carry fault current, provide grounding, carry lightning current, provide electromagnetic shielding, minimize resistance and voltage differential, and/or provide a bleed path for electrostatic charge.
US08031456B2	Explosion-roof and flameproof pullout safety surge absorbing module An explosion-proof and flameproof pullout safety surge-absorbing module includes a surge-absorbing unit, a protective unit, a function member, and a hot melt component. The unit has a body defining an electrode side. The middle section of electrode side defines a partially exposed electrode side further connected to a first pin. The protective component includes a base and a top cover conjoint to the base. The body is between the base and the top cover. The function member includes a recovery component and a function part. The recovery component is flexible, of which one terminal connects the base and the other terminal connects the function part pivoting onto the base and working in a first state and a second state. In the first state, one terminal of the function part is connected to the partially exposed electrode side; in the second state, the hot melt component is heated and melt.
US08031452B2	Single-supply single-ended high voltage peak detector A device for current detection is disclosed and includes a protection circuit having a current input provided via a positive input and a negative input arranged in parallel to the positive input, a pair of diodes communicatively coupling the positive input to the negative input, wherein the pair of diodes are configured to protect an operational amplifier from an overvoltage and negative voltages, and a peak detector in communication with the protection stage, wherein the peak detector is configured to receive an output provided by the operation amplifier of the protection stage, and wherein the peak detector is configured to create a peak detector output representative of the current input.
US08031441B2	CPP device with an enhanced dR/R ratio A CPP-GMR spin valve having a composite spacer layer comprised of at least one metal (M) layer and at least one semiconductor or semi-metal (S) layer is disclosed. The composite spacer may have a M/S, S/M, M/S/M, S/M/S, M/S/M/S/M, or a multilayer (M/S/M)n configuration where n is an integer ≧1. The pinned layer preferably has an AP2/coupling/AP1 configuration wherein the AP2 portion is a FCC trilayer represented by CoZFe(100-Z)/FeYCo(100-Y)/CoZFe(100-Z) where y is 0 to 60 atomic %, and z is 75 to 100 atomic %. In one embodiment, M is Cu with a thickness from 0.5 to 50 Angstroms and S is ZnO with a thickness of 1 to 50 Angstroms. The S layer may be doped with one or more elements. The dR/R ratio of the spin valve is increased to 10% or greater while maintaining acceptable EM and RA performance.
US08031440B2	Coil support structure and magnetic disk drive A voice coil includes a stack of a plurality of layers of aligned windings held between an outer holding portion and an inner holding portion of the carriage assembly. The carriage assembly is formed integrally with the voice coil through injection molding. An outermost peripheral layer is a conductive wire wound a number of turns that falls short of the number of turns required to constitute a complete layer. A step is thereby formed between the outermost peripheral layer and a layer adjacent thereto and inner therefrom. The outer holding portion includes a reinforcement portion formed thereon to cover part of a transverse end face of the voice coil. The outermost peripheral layer opposes a force acting on the outer holding portion from top downward and the reinforcement portion opposes a force acting on the outer holding portion from bottom upward.
US08031436B2	Electron beam writing method for magnetic recording medium When performing writing on a substrate applied with a resist by rapidly vibrating electron beam in a direction orthogonal to a radial direction of the substrate and X-Y deflecting the electron beam while rotating the substrate in one direction, a long element is written by scanning the electron beam with the middle position of a 2-bit signal length as the center position of the electron beam so as to completely fill the area of the writing length reduced by a predetermined ratio and an unwritten portion of predetermined width remaining on each side of the long element with respect to a final 2-bit signal length on a magnetic disk medium.
US08031421B2	Method for measuring optimum seeking time and inspection apparatus using the same The present invention provides a method for measuring an optimum seeking time and an inspection apparatus using this method capable of measuring and setting an optimum seeking time for inspection of a magnetic disk or magnetic head. The method samples average level differences of sector-wise read signals in positive and negative domains for one round of track and detects a minimum value H and a minimum value L among these differences. The method recalculates the seeking time while changing the settling time. After writing and reading test data, calculates a deviation DEV of average levels DEV=(H−L)/(H+L). The method is adapted to obtain a minimum one of the values of settling time having measured when the deviation DEV of average levels is equal to or less than a predetermined value as an optimum settling time or an optimum seeking time.
US08031419B2	Compact imaging device An imaging apparatus may comprise a lens assembly including one or more lenses, an image sensor to receive light from the lens assembly, and an actuator to adjust a position of the lens assembly. An actuator may be mounted on an image sensor, wherein a surface area of the actuator need not extend substantially beyond a surface area of the image sensor.
US08031418B2	Lens driving mechanism and image pickup apparatus using the same A lens driving mechanism for an image pickup apparatus capable of being reduced in size, and having excellent driving accuracy and tranquility is provided. The lens driving mechanism is characterized in that vibration of a piezoelectric vibration motor is used as a driving source, and the vibration is transmitted to a motor power transmission ring directly or via a gear structure, to rotationally drive a lens driving ring. In a first lens driving mechanism, the motor power transmission ring is rotated by rotating the first transmission gear by use of the vibration of the piezoelectric vibration motor. In a second lens driving mechanism, a thrust bearing is provided on a gear side for rotating the motor power transmission ring, and the gear is rotated by vertically pressing a vibrator of the piezoelectric vibration motor in an urged state against a plane of the gear. In a third lens driving mechanism, the lens driving ring is rotationally driven by directly pressing a vibrator of each of one or more piezoelectric vibration motors in an urged state against the outer periphery of the lens driving ring.
US08031417B1	Dual resolution, vacuum compatible optical mount An optical mount for an optical element includes a mounting plate, a lever arm pivot coupled to mounting plate, and an adjustment plate. The optical mount also includes a flexure pivot mechanically coupling the adjustment plate to the mounting plate and a lever arm. The optical mount further includes a first adjustment device extending from the adjustment plate to make contact with the lever arm at a first contact point. A projection of a line from the first contact point to a pivot point, measured along the lever arm, is a first predetermined distance. The optical mount additionally includes a second adjustment device extending from the adjustment plate to make contact with the lever arm at a second contact point. A projection of a line from the second contact point to the pivot point, measured along the lever arm, is a second predetermined distance greater than the first predetermined distance.
US08031413B2	Single focus wide-angle lens module A single focus wide-angle lens module includes a fixed aperture diaphragm, a first lens, a second lens, a third lens and a fourth lens arranged from an object side to an image side in a sequence of: the first lens, the diaphragm, the second lens, the third lens and the fourth lens. The first lens has a concave surface on the image side and at least one aspheric surface. The second lens has a positive refractive power, a concave surface on the object side and at least one aspheric surface. The third lens has a meniscus shape, a negative refractive power, a concave surface on the object side and at least one aspheric surface. The fourth lens has a positive refractive power, a convex surface on the object side and at least one aspheric surface.
US08031410B2	Zoom lens and image pickup apparatus equipped with same A zoom lens includes, in order from its object side, a first lens unit having a negative refracting power, a second lens unit having a positive refracting power, and a third lens unit having a refracting power. During zooming from the wide angle end to the telephoto end, the distance between the first lens unit and the second lens unit decreases, the distance between the second lens unit and the third lens unit changes. The first lens unit includes, in order from the object side, a first lens element, which is a negative lens element, and a second lens element, which is a positive lens element. The negative lens element and the positive lens element satisfy specific conditions.
US08031408B2	Fluid displacement mechanism A fluid displacement mechanism is disclosed. In an embodiment, first and second cavities are separated by a flexible membrane. The first cavity contains a non-conductive fluid and the second cavity contains a conductive fluid. First and second electrodes are positioned in the first and second cavities respectively such that the application of a voltage between the electrodes causes movement of the membrane by the build up of an electrostatic charge between the membrane and first electrode.
US08031407B2	Imaging assembly An imaging assembly for an image sensor may include a lens, a transparent substrate and two aspherical optical coatings on each side of the substrate. The imaging assembly can also incorporate an opaque coating with an opening in-line with the lens to form an aperture, an anti-reflection coating, and an infrared filter coating.
US08031403B2	System and method for reducing visible speckle in a projection visual display system The invention provides an apparatus for reducing speckle in a projection visual display (PVD) system, a method of reducing visible speckle in a PVD system and a PVD system incorporating the method or apparatus. In one embodiment, the apparatus includes a diffuser interposable in an optical path of a PVD system and a diffuser actuator having a single drive axis configured to cause the diffuser to travel in a lissajous curve at least partially transverse to the optical path.
US08031395B2	Optical transmission system using Raman amplifier and controlling method thereof The optical transmission system modulates backward Raman pump light provided to an optical transmission line on one link side of an uplink and downlink, to thereby transmit a pilot signal for confirming a connection state of the optical transmission line to a node on an upstream side. When the pilot signal is received by the node on the upstream side, the backward Raman pump light provided to the optical transmission link on the opposite link side is modulated to thereby send back a response signal to an own node. Then by confirming receipt of the response signal at the own node, the backward Raman pump light provided to the optical transmission line on the one link side is changed over from a low output state to a high output state.
US08031394B2	Wavelength conversion system, optical integrated device and wavelength conversion method A wavelength conversion system includes a Mach-Zehnder interferometer including two optical waveguides, a non-linear medium provided on one of the two optical waveguides, and a branching ratio adjuster for adjusting the branching ratio of multiplexed light produced by multiplexing signal light and pumping light so that the powers of the signal light and the pumping light which are to be emitted from the two optical waveguides are equal to each other. The multiplexed light whose branching ratio is adjusted by the branching ratio adjuster is introduced into the two optical waveguides such that the non-linear medium generates phase conjugation light of the signal light and the light guided through the one optical waveguide and the light guided through the other one of the two optical waveguides interfere with each other so that the phase conjugation light is extracted as wavelength conversion light.
US08031387B2	Two-element fθ lens used for micro-electro mechanical system (MEMS) laser scanning unit A two-element f-θ lens used for a micro-electro mechanical system (MEMS) laser scanning unit includes a first lens and a second lens, the first lens is a positive refraction meniscus lens of which the convex surface is disposed on a side of a MEMS mirror, the second lens is a positive refraction meniscus lens of which the concave surface is disposed on the side of the MEMS mirror, at least one optical surface is an Aspherical surface in both main scanning direction and sub scanning direction, and satisfies special optical conditions. The two-element f-θ lens corrects the nonlinear relationship between scanned angle and time into the linear relationship between image spot distances and time. The two-element f-θ lens focuses the scan light to the target in the main scanning and sun scanning directions, such that the purpose of the scanning linearity effect and the high resolution scanning can be achieved.
US08031386B2	Galvano motor and galvano motor system A galvano motor 10 includes a motor shaft 1, a coil 5 which rotationally drives the motor shaft 1, and an encoder scale 6 which is joined to one end of the rotating shaft, the motor shaft 1 is configured so that a mirror 9 which is heavier than the encoder scale 6 at the other end opposite to the one end to which the encoder scale 6 is joined, a phase crossover frequency fphase in open-loop characteristics of the galvano motor 10, a torsion resonance frequency fscale between a center part of the motor shaft 1 and the encoder scale 6, and a torsion resonance frequency fmirror between the center part of the motor shaft 1 and the mirror 9 satisfy the relation of fphase
US08031385B2	Method for adjusting drive characteristics of scanner driver of galvanometric scanner A scanner driver of a galvanometric scanner system includes an analog drive circuit; a control unit 31 for storing and holding optimized data formed from combinations of optimal values of circuit constants set in advance in accordance with a plurality of drive modes of a galvanometric scanner; and an electronic trimmer for changing the circuit constants of the analog drive circuit. The control unit selects one of the optimized data in accordance with an external input, and sets or updates parameters of the circuit constants via the electronic trimmer in accordance with the selected optimized data. When a drive mode of the galvanometric scanner system is changed, the scanner driver can accordingly be optimized readily and quickly.
US08031384B2	Device for a layerwise manufacturing of a three-dimensional object and method for adjusting an optical system of the same A device (1) for manufacturing a three-dimensional object by a layer-wise solidification of a building material at positions in the respective layers corresponding to the object is provided. The device has an energy source (6) that emits a beam (9) for solidifying the building material, a scanner (8) that selectively directs the beam (9) to different positions in a building plane (11), and a deflection mirror (7) that deflects the beam (9) coming from the energy source (6) to the scanner (8). The beam (9) from the energy source (6) to the scanner (8) runs in a space (13, 14) secluded from the outside and an adjustment mechanism (16) for the alignment of the deflection mirror (7) is provided, which is adjustable from the outside of the secluded space (13, 14).
US08031383B2	Common aperture holographic storage system with reduced noise An apparatus for reading from or writing to holographic storage media, and more specifically a common aperture type apparatus for reading from or writing to holographic storage media with multiple reference beams having a reduced noise. In a common aperture type apparatus for reading from or writing to a holographic storage medium using shift-multiplexing, with a coaxial arrangement of two or more reference beams and an object beam or a reconstructed object beam, the reference beams being arranged around the object beam or the reconstructed object beam in a storage layer of the holographic storage medium. Each of the reference beams is located essentially halfway between two adjacent central peaks of shift-multiplexed holograms.
US08031379B2	Data communication system In a system in which a facsimile apparatus is connected to a LAN (Local Area Network) to which a plurality of computer terminals are connected, image data obtained by reading an original image by the scanner of the facsimile apparatus under the control of the operation unit of the facsimile apparatus is transmitted to a destination designated by the operation unit. In this operation, if a user ID is designated, transmitted image data and information (destination, transmission time/date, or the like) related to transmission is transferred to the LAN to notify the information to a user corresponding to the user ID. In this manner, data communication performed by a local operation of the facsimile apparatus and data communication performed by a remote designation from the computer terminal can be managed together.
US08031370B2	Device and method removes background component from image using white reference value and background removal level value An image processing device includes a histogram generation unit configured to generate a density histogram on the basis of image data of an original document, a white-reference value detection unit configured to acquire as a white reference value a density value at a density distribution peak in a predetermined white side range of the density histogram, a background-removal level determination unit configured to determine a background-removal level value having the maximum density to remove a background component by using a reference table on the basis of the white reference value, and a background removal unit configured to remove the background component from the image data by using the white reference value and the background-removal level value.
US08031368B2	Image processing device The present invention provides an image processing device which aims for appropriate settings and simplification of printing functions. In a print server, when a print job is received, an application name used in a client terminal is specified from a drawing command of the print job, and standard settings of printing functions provided for each application are read from database files. Thereafter, the standard settings and settings of printing functions of the print job are compared. When the settings are different, after carrying out a warning processing, setting of printing functions based on the standard settings is carried out, and image processing and printing processing based on the set printing functions are executed. In this way, while simplifying settings of printing functions in the client terminal, image processing and printing processing by appropriate printing functions are possible.
US08031366B2	Control apparatus, controlling method, program and recording medium A problem of the present invention is to provide a control apparatus, a controlling method, a program, and a recording medium which can print by using at least one or more special colors in addition to four colors of Cyan, Magenta, Yellow, and Black. To solve the above problem, the control apparatus according to the present invention includes analyzing unit that provides command analysis for a CMYK plate and a clear toner plate, generating unit that generates image data of the CMYK plate based on a result of the command analysis by the analyzing unit, and embedding unit that embeds a clear toner attribute obtained by analyzing the clear toner plate in an attribute flag accompanying each of pixels of the image data of the CMYK plate, which is generated by the generating unit.
US08031365B2	Image processor and image processing method for reducing consumption amount of recording material The present invention provides an image processor for outputting image data to an image forming device forming an image with use of a recording material having a plurality of color components. The processor comprises a component determining a region having higher brightness than predetermined brightness and a region having lower brightness than the predetermined brightness in the image data based on the image data and a component adjusting saturation so as to reduce density values of color components other than a color component having a maximum density value among the plurality of color components of the recording material to increase saturation in a region having brightness determined to be high and reduce density values of color components other than a color component having a minimum density value among the plurality of color components of the recording material to decrease saturation in a region having brightness determined to be low.
US08031362B2	Optical scanning device, image forming apparatus, and liquid crystal element A disclosed optical scanning device scans an object scanning surface with a light beam projected from a light source and traveling through an optical system. The optical scanning device includes a liquid crystal element configured to modulate a phase. The liquid crystal element is driven by electric signals and provided on a light path between the light source and the object scanning surface. The liquid crystal element generates different power components in a main scanning direction and a sub scanning direction under temperature variations.
US08031361B2	Image forming apparatus An aspect of the invention provides an image forming apparatus including: a image forming section that forms an image based on a print data on at least one sheet equipped with a non-contact tag; a writing section that wirelessly writes a tag data into the non-contact tag of the at least one sheet; a first cassette that holds a plurality of sheets equipped with first type non-contact tags having a first storage capacity; a second cassette that holds a plurality of sheets equipped with second type non-contact tags having a second storage capacity larger than the first storage capacity; and a selecting section that selects a print cassette from among the first and second cassettes based on a data size of the tag data. The at least one sheet on which the image is formed by the image forming section is provided from the print cassette.
US08031360B2	Methods and systems for fax routing In an illustrative embodiment, methods and systems are provided for processing facsimiles. A call processing system receives a first message transmitted from a first carrier system regarding a facsimile call to a phone address. The first message includes an identifier associated with the user. The identifier is used to determine if the user is authorized to receive call processing system services. If the user is authorized, a second message is transmitted to the first carrier system, the second message indicating that the first carrier system is to connect the call to the call processing system. The call processing system is connected to the call. A facsimile is received via the call at the call processing system. Information regarding the facsimile call is provided over a network, wherein some or all of the information is displayed in a call log visually accessible by the user.
US08031357B2	Handheld display device for interacting with printed substrate A handheld display device for displaying and interacting with information corresponding to a printed substrate. The device comprises: a transceiver for sending and receiving digital information; an optical sensor for imaging an area of the printed substrate and for generating image data; a processor for determining interaction data using the image data, the interaction data identifying a substrate identity; and a touch-sensitive screen for displaying display information based on retrieved display data. The touch-sensitive screen enables user interaction with the display information.
US08031354B2	Image communication apparatus for determining a correct destination location of image data An image communication apparatus capable of communicating with external apparatuses determines whether image data received from the external apparatuses is a first type of image data that was to be transmitted to the image communication apparatus or a second type of image data that was to be transmitted to other image communication apparatuses, and performs predetermined processing based on the determination result.
US08031352B2	Apparatus and method for processing received data In an apparatus capable of handing data received by a communication function, such as facsimile function or the like, information for generating a file name to be set for received data is registered so as to correspond to receiving conditions (for example, in facsimile reception, a sender's telephone number, an F code, a password and the like). When data has been received, receiving conditions are determined, and a file name based on the information registered for the data is set in accordance with the result of the determination. Thus, the receiving side can easily discriminate the contents of the data.
US08031351B2	Image formation apparatus connected to power supplying device capable of supplying power via data communication line, control method performed by same image formation apparatus and storage medium storing program executed by same image formation apparatus A message displaying area displays a message “DATA HAS BEEN RECEIVED”, which indicates that a print instruction has been received, as well as a message “CONDUCT AUTHENTICATION”, which urges a user to enter identification information. On the other hand, an input area displays a form in which a “username” and a corresponding “password” are to be entered. Specifically, a display presents an entry screen for identification information, including messages indicating that a print instruction has been received and authentication is required.
US08031348B2	Approach for securely printing electronic documents An approach is provided for securely printing electronic documents using a portable media. The approach is applicable to a wide variety of contexts and implementations and includes secure direct printing of electronic documents, secure direct printing of electronic documents with remote user authentication and secure printing of electronic documents with remote data management. The particular information provided on the portable media varies, depending upon the implementation. Furthermore, the approach provides varying degrees of security and may be used in conjunction with conventional printing of electronic documents.
US08031347B2	Default media selection methods in a multi-media printer A multi-media print includes a decoding module, a configuration memory, and a parameter determination module. The decoding module decodes print job parameters and print job data, and outputs decoded print job parameters including decoded print job media selection parameters and the decoded print job data. The configuration memory stores default configuration parameters. The parameter determination module receives the decoded print job parameters including the decoded print job media selection parameters and the decoded print job data and also receives the default configuration parameters including the default media selection parameters from the configuration memory. The parameter determination module determines the final print job media selection parameters for the print job, utilizing the decoded print job media selection parameters and the default media selection parameters. The default media selection parameters are utilized when the print job parameters and print job data are not sufficient to select the media.
US08031344B2	Z-stage configuration and application thereof A stage configuration is provided, wherein a ceramic plate is used as the z-stage body to decrease the use of the metal plates in the conventional configuration, so that the compact structure of the z-stage may decrease the vibrational movements of the z-stage. Further, two Laser interferometer are used to detect a movement of different points along a vertical line of the z-stage sidewall to calculate a movement of the specimen surface, so that a horizontal movement of the specimen surface can be detected more accurately.
US08031338B2	Measuring Forster resonance energy transfer with polarized and depolarized light The present invention provides improved methods for assessing Förster resonance energy transfer using polarized light. Specifically, the methods rely on measuring depolarized light emitted by fluorescent acceptor molecules.
US08031337B2	Angularly resolved scatterometer An angularly resolved scatterometer uses a broadband radiation source and an acousto-optical tunable filter to select one or more narrowband components from the broadband beam emitted by the source for use in measurements. A feedback loop can be used to control the intensity of the selected narrowband components to reduce noise.
US08031329B2	Overlay mark, and fabrication and application of the same An overlay mark is described, including a portion of a lower layer having two x-directional and two y-directional bar-like patterns therein, and two x-directional and two y-directional photoresist bars defined by the lithography process for defining an upper layer and surrounded by the bar-like patterns. At least one of the patterning process for defining the lower layer and the above lithography process includes two exposure steps respectively for defining a first device area and a second device area. When the patterning process includes two exposure steps, one x-directional and one y-directional bar-like patterns are defined simultaneously and the other x-directional and the other y-directional bar-like patterns are defined simultaneously. When the lithography process includes two exposure steps, one x-directional and one y-directional photoresist bars are defined simultaneously and the other x-directional and the other y-directional photoresist bars are defined simultaneously.
US08031326B2	Illumination system or projection lens of a microlithographic exposure system In some embodiments, the disclosure provides an optical system, in particular an illumination system or a projection lens of a microlithographic exposure system, having an optical system axis and at least one element group including three birefringent elements each of which includes optically uniaxial material and having an aspheric surface, wherein a first birefringent element of the group has a first orientation of its optical crystal axis, a second birefringent element of the group has a second orientation of its optical crystal axis, wherein the second orientation can be described as emerging from a rotation of the first orientation, the rotation not corresponding to a rotation around the optical system axis by an angle of 90° or an integer multiple thereof, and a third birefringent element of the group has a third orientation of its optical crystal axis, wherein the third orientation can be described as emerging from a rotation of the second orientation, the rotation not corresponding to a rotation around the optical system axis by an angle of 90° or an integer multiple thereof.
US08031324B2	Substrate processing apparatus with integrated cleaning unit In a substrate processing apparatus, an indexer block, a resist film processing block, a cleaning/drying processing block, a development processing block, and an interface block are provided side by side in this order. An exposure device is arranged adjacent to the interface block. The exposure device subjects a substrate to exposure processing by means of a liquid immersion method. Substrate platforms are provided in close proximity one above the other between the cleaning/drying processing block and the development processing block for receiving and transferring the substrate therebetween. Reversing units that reverse one surface and the other surface of the substrate are respectively stacked above and below the substrate platforms.
US08031321B2	Methods of manufacturing liquid crystal display devices An LCD device and a method for manufacturing the same is disclosed, in which it is possible to correct a problem of insufficient or excessive supply of liquid crystal in an LCD device by controlling an amount of liquid crystal. The method includes preparing a liquid crystal cell comprised of a first substrate, a second substrate, a liquid crystal layer between the first and second substrates, and a first sealant formed in the periphery of the liquid crystal layer between the first and second substrates; measuring an amount of liquid crystal provided to the inside of liquid crystal cell; forming an inlet for liquid crystal in the first sealant; and regulating the amount of liquid crystal by supplying or discharging the liquid crystal through the inlet; and sealing the inlet.
US08031313B2	Lateral electric field type liquid crystal display device A lateral electric field type LCD device displays images uniformly and stably, where abnormally displayed areas caused by mechanical deformation such as a press with a finger do not remain on the display screen for a long time. A first liquid crystal driving electrode and a second liquid crystal driving electrode comprise a first bend and a second bend, respectively. Each pixel region is divided into a first sub-region and a second sub-region by the first and second bends as a boundary in such a way that a rotation direction of liquid crystal molecules in the first sub-region is different from that in the second sub-region. A boundary stabilization electrode is formed at least one of the first and second bends, wherein a shape or position of the boundary stabilization electrode deviates from a line of symmetry of the first and second bends.
US08031312B2	Array substrate for liquid crystal display device and method of manufacturing the same An array substrate for a liquid crystal display device includes a substrate, a gate line on the substrate, a thin film transistor including a gate electrode of the gate line, a gate insulating layer over the gate electrode, an active layer on the gate insulating layer and ohmic contact layers on the active layer, and source and drain electrodes over the ohmic contact layers, a pixel electrode electrically connected to the drain electrode, a data line electrically connected to the source electrode and crossing the gate line, a common electrode spaced apart from the pixel electrode, and a passivation layer directly between the pixel electrode and the common electrode and directly between the source and drain electrodes.
US08031309B2	Liquid crystal display device having retardation film on inside of substrate compensating for light of a particular wavelength A liquid crystal display device comprising a pair of substrates, at least one polarizing film provided outside the pair of substrates, a liquid crystal cell having a red color filter, a green color filter and a blue color filter provided inside the pair of substrates, a first retardation film compensating for light of a wavelength or wavelengths corresponding to a color or colors of any one or two of the three color filters, and a second retardation film compensating for light of a wavelength that is not compensated for by the first retardation film.
US08031307B2	Liquid crystal display apparatus containing image sensor and process for producing the same A liquid crystal display apparatus containing an image sensor, which comprises a liquid crystal display part comprising an active matrix circuit, a peripheral driver circuit for driving the active matrix circuit, and a sensor part, integrated on one substrate, wherein the sensor part is sealed and protected with a sealing part and a counter substrate.
US08031304B2	Liquid crystal display device A transfiective liquid crystal display panel, in which at least one of a pixel electrode substrate and a counter electrode substrate is provided with a protruding portion so that the thickness of a liquid crystal layer in a reflective region is smaller than that in a transmissive region, wherein a light-blocking section for shading a defective orientation domain formed by an insufficiently-rubbed portion around the protruding portion is formed simultaneously with, and using the same material as, another element such as a storage capacitor electrode section, a signal line or a scanning line. Thus, the decrease in the display quality due to the defective orientation domain can be suppressed without adding to the production process.
US08031302B2	Directional diffusion film, polarizing plate, liquid crystal display, and method of manufacturing directional diffusion film A directional diffusion film with diffusion properties that vary depending on the incidence angle is characterized in that a diffusion axis direction is in the range of 20° to 50° with respect to a normal direction of the film, and a diffusion half-value angle is at least 20° and lower than 90°. The diffusion axis direction is a light irradiation direction in which the strongest diffusion light is obtained when the film is irradiated with light. The diffusion half-value angle is a diffusion angle at which intensity of outgoing diffusion light at a plane A is 50% of the peak intensity, with the plane A containing the normal direction and the diffusion axis direction of the directional diffusion film, when collimated light is incident at an incidence angle of 30° from the normal direction of the directional diffusion film in the plane A. A polarizing plate containing the directional diffusion film. An LCD device containing the directional diffusion film.
US08031299B2	Display device The present invention is intended to control the color temperature of white exhibited by a liquid crystal display device. White is produced when light waves emitted through pixels associated with three colors of red; green, and blue have maximum intensities. The amounts of light emitted through the respective pixels are controlled by differentiating the shapes of the pixel electrodes disposed at the respective pixels from one another. Thus, the color temperature of white is controlled. Otherwise, the shapes of interceptive films disposed at the respective pixels are differentiated from one another in order to control light waves emitted through the respective pixels. Thus, the color temperature of white is controlled. The interceptive film may be shaped like the pixel electrode. Otherwise, the interceptive film may be realized with an interceptive pattern other than that of the pixel electrode or one of openings bored in a black matrix.
US08031293B2	Backlight module with light source holder and liquid crystal display using the same An exemplary backlight module (1) includes a light guide plate (10) and at least one light source assembly (16). Each of the light source assembly includes a plurality of point light sources (163) and a light source holder (160). The light source holder accommodates the point light sources and an end portion (12) of the light guide plate, with a distance between the end portion and the point light sources.
US08031291B2	Liquid crystal display and tablet computer having a chassis fastening member that receives a printed circuit board The present invention relates to a liquid crystal display and a tablet computer having the same. According to the present invention, there is provided a liquid crystal display, comprising: a liquid crystal display panel for displaying an image; a driving circuit unit connected to the liquid crystal display panel and including a printed circuit board mounted with a circuit component; a top chassis disposed over the liquid crystal display panel; and a fastening member for fastening the printed circuit board of the driving circuit unit to the top chassis.
US08031288B2	Polarization conversion element, polarized light illumination optical element, and liquid crystal projector A prism sheet is bonded to the bottom faces of rectangular prisms constituting a polarization beam splitter array. In the front face of the prism sheet, a plurality of rectangular prism elements are arranged in parallel to each other and a phase difference compensation film is formed on the surface. The edge lines of the rectangular prism elements are inclined at 45 degrees relative to the edge lines of the rectangular prisms. Linear polarized light of S-polarization component reflected by a polarized light separation film is reflected twice sequentially in a phase difference compensation film formed in a pair of oblique faces of the rectangular prism elements, so that the polarization direction is rotated by 90 degrees and then the light reenters the rectangular prism. Then, the light is transmitted through the polarized light separation film and then extracted from the rectangular prism.
US08031287B2	Display panel and liquid crystal display including the same The present invention relates to a display panel and a liquid crystal display including the same. The display panel includes a pixel electrode, which includes a first subpixel electrode, a second subpixel electrode, and a third subpixel electrode insulated from each other, a first thin film transistor connected to the first subpixel electrode, a second thin film transistor connected to the second subpixel electrode, a third thin film transistor connected to the third subpixel electrode, a gate line connected to the first, second, and third thin film transistors, a data line connected to the first, second, and third thin film transistors, and a voltage differentiating member to change voltages of the first, second, and third subpixel electrodes, the voltages of the first, second, and third subpixel electrodes being different from each other.
US08031284B2	Reflective liquid crystal display panel and device using same There is disclosed an active matrix reflective liquid crystal display panel on which an active matrix circuit is integrated with peripheral driver circuits. Metal lines in the peripheral driver circuits are formed simultaneously with pixel electrodes. Thus, neither the process sequence nor the structure is complicated.
US08031278B2	Pixels using associated dot polarity and associated dot switching elements for multi-domain vertical alignment liquid crystal displays A multi-domain vertical alignment liquid crystal display that does not require physical features on the substrate (such as protrusions and ITO slits) is disclosed. Each pixel of the MVA LCD is subdivided into color components, which are further divided into color dots. The drive component areas, i.e. where switching elements and storage capacitors are located, are converted to associated dots by adding an electrode that can be electrically biased. The voltage polarity of the color dots and associated dots are arranged so that fringe fields in each color dot causes multiple liquid crystal domains in each color dot. Specifically, the color dots and associated dots of a pixel are arranged so that associated dots have opposite polarity as compared to neighboring color dots.
US08031268B2	Audio over a standard video cable A source unit has a video source, a digital audio source, a DDC/CI communications capability and a switch for coupling a pin of a standard video cable either to the digital audio source or to a non-audio conventional connection. A display device has a video consumer, a digital audio consumer, a DDC/CI communications capability and a switch for coupling the pin of the standard video cable either to the digital audio consumer or to a non-audio conventional connection. The switch in the display device is responsive to a DDC/CI command.
US08031267B2	Motion adaptive upsampling of chroma video signals Upsampling for video signals is described. In particular chroma pixels may be upsampled in a luminance, chrominance signal using motion adaptive approaches. In one example, the operations include selecting an absent chroma pixel of the current frame, developing a spatial candidate value for the absent chroma pixel using pixel values for nearby pixels in the current frame, developing a temporal candidate value for the absent chroma pixel using pixel values for nearby pixels in the previous and subsequent frames, computing a value for the absent chroma pixel by combining the spatial candidate value and the temporal candidate value, and producing an output video frame including the computed absent chroma pixel values.
US08031265B2	System and method for combining interlaced video frames System and method for combining interlaced video frames. A method embodiment for displaying a de-interlaced video sequence includes receiving a video stream, decoding the video stream to produce a sequence of interlaced video fields, creating a first de-interlaced video frame by combining at least two interlaced video fields, determining a cadence of the first de-interlaced video frame, and outputting the first de-interlaced video frame in a next de-interlaced video frame display time slot if the first de-interlaced video frame has proper cadence, while if the de-interlaced video frame has a broken cadence, re-outputting a previously outputted de-interlaced video frame in the next de-interlaced video frame display time slot. A feed-forward control signal may be used to determine which de-interlaced video frame to output and helps to minimize latency as well as storage requirements.
US08031262B2	Determining a final exposure setting automatically for a solid state camera without a separate light metering circuit An embodiment of the invention is a method of generating a final exposure setting, including, (a) selecting one of a number of predetermined exposure settings as a current exposure setting for a solid state camera having a camera imager, (b) generating a captured scene by the camera imager using the current exposure setting, (c) selecting according to an automated search methodology another one of the exposure settings to be the current setting in response to the captured scene being underexposed or overexposed, and, (d) repeating (b) and (c) until the captured scene is neither underexposed or overexposed.
US08031254B2	Optical device, imaging device, control method for optical device, and program An optical device which allows size and cost reductions and enables simultaneous capture of images taken by a first optical system and images taken by a composite optical system composed of the first optical system and a second optical system. A first optical system is adapted to form a first image. A second optical system is disposed on a subject side of the first optical system, and is adapted to form a second image within the first image formed by the first optical system.
US08031248B2	Solid state imaging element having horizontal scanning circuit for providing reset signals Since the great number of elements constituting a unit pixel having an amplification function would hinder reduction of pixel size, unit pixel n,m arranged in a matrix form is comprised of a photodiode, a transfer switch for transferring charges stored in the photodiode, a floating diffusion for storing charges transferred by the transfer switch, a reset switch for resetting the floating diffusion, and an amplifying transistor for outputting a signal in accordance with the potential of the floating diffusion to a vertical signal line, and by affording vertical selection pulse φVn to the drain of the reset switch to control a reset potential thereof, pixels are selected in units of rows.
US08031241B2	Solid-state imaging device and imaging apparatus A solid-state imaging device includes a pixel array unit configured by arranging plural unit pixels including charge generating units and output transistors that output processing object signals corresponding to charges generated by the charge generating units, an imaging-condition determining unit that determines whether a large light-amount imaging condition, when an amount of light larger than that of light representing a saturation level is made incident on the charge generating units, is satisfied, and a control unit that performs control, on condition that the imaging-condition determining unit determines that the large light-amount imaging condition is satisfied, to correct an output signal based on processing object signals outputted from the unit pixels such that a harmful effect due to the large light-amount imaging condition is suppressed in the output signal.
US08031232B2	Image pickup apparatus including a first image formation system and a second image formation system, method for capturing image, and method for designing image pickup apparatus The present invention relates to an image pickup apparatus, a method for capturing an image, and a method for designing the image pickup apparatus capable of realizing a fixed focal length image pickup apparatus of high resolution and fine resolution at a low cost by disposing a plurality of image pickup elements therein. An image pickup device 31 is of a focal coincidence type having a plurality of image pickup elements, such as CCD sensors 62-1 to 62-3, arranged in an array. That is, the image pickup device 31 has an optical system including a first image formation system 41 for forming an image of focal coincidence, a field lens 43 disposed in an image formation plane or in the vicinity of the image formation plane of the first image formation system, and a second image formation system group formed by a plurality of second image formation systems arranged in an array and including an image pickup element CCD sensor 62-K (K is a value between 1 and 3 in this example) for capturing the image formed on itself and a zoom lens 61-K for reforming a predetermined, part of the image formed on the image formation plane on the CCD sensor 62-K. The present invention is applicable to a digital still camera and a digital video camera including a plurality of image pickup elements.
US08031229B2	Imaging apparatus and imaging control method The imaging apparatus includes an image sensor for obtaining a picture image from an optical image that is projected to the image sensor through an optical system, an image moving portion for moving the optical image on the image sensor, a motion detecting portion for detecting a movement on the picture image of a moving subject that appears in the optical image, and a control portion for controlling, during an exposure period after a predetermined operation, the image moving portion in the direction of canceling the movement of the moving subject on the image sensor due to a movement of the moving subject in the real space, based on a movement of the moving subject detected in advance. The control portion sets length of the exposure period based on the movement of the moving subject detected in advance.
US08031228B2	Electronic camera and method which adjust the size or position of a feature search area of an imaging surface in response to panning or tilting of the imaging surface An electronic camera includes an image sensor. The image sensor has an imaging surface for capturing an object scene, and repeatedly generates an object scene image. A CPU assigns a search area on the imaging surface, and repeatedly executes search processing for searching a facial image on the search area in parallel with executing object scene image generating processing of the image sensor. A character representative of a position of a facial image detected by the search processing is superposed on a through-image on an LCD monitor. The size of the search area assigned on the imaging surface is reduced as a panning and/or tilting speed of the imaging surface is increased.
US08031227B2	Position tracking system A position tracking system includes an infrared-sensitive device, such as an infrared camera that generates signals in response to detected infrared light in a field of view of the infrared-sensitive device. A processor is responsive to the signals generated by the infrared-sensitive device for determining a position of the detected infrared light. The processor also generates tilt and pan signals based on the position of the detected infrared light. A tilt and pan mechanism moves a visible-light video camera in response to the tilt and pan signals from the processor. The active infrared light-emitting device includes a loop having at least two infrared light-emitting elements disposed along the loop, on opposite sides of the loop. A control box is disposed in the loop and is in electrical communication with the infrared light-emitting elements. When the loop is disposed around an object that rotates relative to the infrared-sensitive device, a constantly unimpeded viewing channel is provided between the infrared-sensitive device and at least one of the elements due to the positioning of the elements. The position information obtained from the infrared-sensitive device is used to direct a visible-light camera to track the active infrared light-emitting device in a manner similar to that performed by a human camera operator.
US08031225B2	Surroundings monitoring system for a vehicle A soundings monitoring system for a vehicle includes a first camera capturing a fist imaging surface, a second camera capturing a second imaging surface, and a monitor for displaying a first image of the first imaging surface and a second image of the second imaging surface. A standard point is specified relative to the vehicle, the first image and the second image are synthesized and displayed on the monitor so that a coordinate position of the standard point in an expanded imaging surface from the first imaging surface and a coordinate position of the standard point in the second imaging surface match each other, and an imaginary line including the standard point and extending over the first image and the second image is displayed on the monitor in such a manner that the imaginary line is superimposed on the synthesized image of the first image and the second image.
US08031224B2	Camera system, method for operation of a camera system and sensor device of a camera system The invention concerns a camera system, especially a camera system in a camera-based analysis system and/or assistance system of a vehicle, comprising a camera with an optical beam path (12), which has at least one optical element to guide image information to a light-sensitive image sensor (14). At least one test beam (22) can be coupled into a transparent test element (30) arranged on the input side in front of beam path (12) and, depending on a degree of soiling of the test element (30), at least one partial beam (24) indicating soiling can be directed from the test element (30) onto a sensor (14a) to receive the partial beam (24) indicating soiling.
US08031217B2	Processes and structures for IC fabrication The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process forms interconnect wires on a thermal decomposable adhesive, and after positioning the wires at proper bond pad locations, releases the interconnect wires onto the bond pads.
US08031215B2	Thermal head, thermal printer and manufacturing method of thermal head A thermal head which forms an image on a recording medium by pressing a protruding portion on which heating elements are arranged on the recording medium while driving the heating elements to be heated includes a support substrate in which a concave gap portion facing the protruding portion is formed and a glaze layer provided on the support substrate and in which the protruding portion is formed, in which the glaze layer has a base layer stacked on the support substrate as well as forming a ceiling surface of the gap portion and a heat resistant layer stacked on the base layer and on which the heating elements are arranged.
US08031214B2	Line head and image forming apparatus incorporating the same In a line head, a plurality of element arrays arranged in a first direction. Each array includes a plurality of light emission elements arrayed in a second direction which is perpendicularly to the first direction. The light emission elements emit light for forming an electrostatic latent image on a photosensitive surface of an image carrier. A switcher activates the light emission elements in at least one of the element arrays while deactivating the others. A developer develops the latent image as a visible image with toner.
US08031208B2	Drawing apparatus and method for processing plural pixels in parallel A drawing apparatus includes a reception unit, a first holding unit and a drawing processing unit. The reception unit receives graphic information. The first holding unit holds a plurality of first data which is a part of the graphic information received by the reception unit, in association with identification numbers assigned to the first data. The drawing processing unit draws a graphic on the basis of the first data held in the first holding unit. The drawing processing unit uses the plurality of the first data in a same task to draw the graphic. The reception unit records the identification numbers of the first data and a synchronization flag in order of reception. The synchronization flag is set for the first data received first among the plurality of first data processed by the same task in the drawing processing unit.
US08031205B2	Image data set with embedded pre-subpixel rendered image Various imaging processing techniques for displaying a pre-subpixel rendered image. The pre-subpixel rendered image can be transmitted directly to a display capable of displaying a subpixel rendered image. The pre-subpixel rendered image can also be stored for later transmission for output to the display. Additionally, the pre-subpixel rendered image can be embedded in an image data stream and later extracted and displayed.
US08031201B2	Computer-aided methods and systems for pattern-based cognition from fragmented material A method for obtaining and analyzing information objects including generating, collecting or discovering information objects. The information objects are signified at least in part using deliberately ambiguated signifier prompts, for example, linear scale opposing negatives or positives, and/or multi-dimensional signifier prompts. The information objects may comprise text or non-text fragments, and may be generated or selected. The responses to the signifier prompts are stored with the fragments to provide a dataset of signified fragments. The signified fragments may be analyzed based on the signifiers and can be utilized as part of an explorable knowledge repository, or objective measures can be created to aid in mass opinion capture or human attitude auditing. The fragments may be represented on a graphical template. In one embodiment, fragment exemplars are identified that exemplify significant locations on the template, and the exemplar signifiers are used to automatically locate other signified fragments on the template.
US08031200B2	Video matrix display interface In a video matrix display interface, an interface includes one or more subsystems to receive information from a plurality of display devices, compile the information from the plurality of display devices, report the compiled information to a graphics processing device, generate a video image using the compiled information, the image to be viewable across the plurality of display devices, splice the video image into portions and transmit the video image portions to the plurality of display devices, thereby creating a continuous image across the plurality of display devices.
US08031196B2	Display, electronic device, data transmitting method, information terminal, host apparatus, program, recording medium A display device comprises a display section, a pattern specifying code input section which receives a pattern specifying code externally, a pattern storage section which stores therein an image of a predetermined pattern, and a pattern display processing section which reads out the image of a pattern specified by the pattern specifying code from the pattern storage section and displays the image on the display section. With this arrangement, the load on a host to display an image can be reduced.
US08031188B2	Digital/analog converter circuit, level shift circuit, shift register utilizing level shift circuit, sampling latch circuit, and liquid crystal display device incorporating the same A digital/analog converter circuit, a level shift circuit, a shift register containing this level shift circuit, a sampling latch circuit and a latch circuit as well as a liquid crystal display device mounted with these respective circuits, wherein a drive circuit integrated with the LCD device containing the digital/analog converter circuit has polysilicon thin film transistors arrayed in a matrix on the substrate as switching devices for the pixels. A level shift circuit in the shift register has a basic structure of CMOS latch cells and is utilized in each level shift of the clock signal at each transfer stage, a sampling latch circuit with a basic structure of CMOS latch cells has a level shift function, and these respective circuits may be incorporated into a single scanning type structural circuit with the drive circuit-integrated liquid crystal display device to provide an LCD panel with an extremely narrow picture frame, stable level shift operation, stable sampling & latch operation in a circuit structure having an extremely small number of components, low power consumption and a small surface area.
US08031183B2	Touch panel and method for manufacturing touch panel A touch panel having high durability is provided. Either one or both of a display device and a flexible panel have island-shaped protective bodies formed on surfaces of electrode layers (upper electrode layer, lower electrode layer), and a transparent conductive film is exposed between the protective bodies. Since the protective bodies protrude highly from the surface of the transparent conductive film, when the flexible panel is pressed and the upper electrode and the lower electrode layer are brought into contact, a load to be applied to the transparent conductive film is reduced by the protective bodies, so that the transparent conductive film is not broken.
US08031178B2	Keyboard with chassis structure A keyboard apparatus includes a group of switches, a key having a corresponding group of plungers, and a chassis structure including a panel and a post. The post projects upward from the panel to support the key for manual movement pivotally into multiple actuated positions in which the plungers actuate the switches. The panel has a group of apertures through which the plungers are movable into actuating engagement with the switches upon such multi-directional movement of the key.
US08031177B2	Electronic pen with retractable nib An electronic pen for interacting with a substrate having coded data disposed thereon. The pen comprises: an image sensor for sensing the coded data when the pen is used to interact with the surface; a slidably retractable nib for contacting the surface; a processor configured to generate indicating data indicative of the interaction with the substrate; and communication means for communicating the indicating data to a computer system. The image sensor is configured to sense the coded data only when the nib is configured in the extended position.
US08031175B2	Touch sensitive remote control system that detects hand size characteristics of user and adapts mapping to screen display Sensors around the periphery of the remote control unit detect contact with the user's hand. A trained model-based pattern classification system analyzes the periphery sensor data and makes a probabilistic prediction of the user's hand size. The hand size is then used to control a mapping system that defines how gestures by the user's thumb upon a touchpad of the remote control unit are mapped to the control region upon a separate display screen.
US08031169B2	Automated system and method for high-frequency signal attenuation compensation Disclosed is a high-frequency boost circuitry for use with a computer management system. Detection circuitry at the receiving end of a video signal measures the amplitudes of various frequency components of the video signal. If the amplitudes of the high-frequency components of the video signal are substantially lower than the amplitudes of the low frequency components of the video signal, the detection circuitry sends the amplitude information to analysis circuitry located at the transmitting end of the video signal. The analysis circuitry utilizes this information to determine the appropriate level of amplification needed for the video signal. This results in improved signal to noise ratio at the receiver in the computer management system.
US08031167B2	Method and apparatus for controlling backlight in display device A method and circuit for controlling the brightness of a backlight in a display device. The circuit comprises a backlight brightness selecting block that measures the brightness of ambient light and selects brightness information of the backlight based on the measured brightness of the ambient light. An image processing block performs image processing on received image signal based on the measured brightness of the ambient light, and calculates an image processing gain of the received image signal based on the result of image processing and the received image signal. A backlight adjusting unit controls the brightness of the backlight based on the selected backlight brightness information and the image processing gain.
US08031166B2	Liquid crystal display method and the appratus thereof The present invention discloses a liquid crystal display method, which can adjust the brightness of different segments of backlight according to the different images. Especially, the present invention discloses a liquid crystal display method, which includes: receiving a image signal; analyzing the image signal; dividing the image into at least two image segments according to the analysis result of the image signal; dividing the backlight into at least two backlight segments according to the division result of the image; adjusting the brightness of the backlight in each backlight segment; adjusting the image signal in each image segment. The liquid crystal display method of the present invention divide the image and the backlight according to the image signal, while adjusting the brightness of the image and backlight in each segment to not only decrease the power consumption of the liquid crystal display, but also increase the contrast of the image signal, thereby improving the effect of liquid crystal display.
US08031165B2	Back light unit and liquid crystal display apparatus A back light unit includes a lamp, a lamp house where the lamp is housed, a diffusion plate provided parallel to a main surface of the lamp house, a display part receiving light irradiated from the lamp and displaying, a frame member that has a structure in which the diffusion plate and the display part can be housed inside of the frame member and that detachably connects to the lamp house, and a shield member connected in a range from the diffusion plate to the frame member so that a space between the diffusion plate and the frame member is shielded.
US08031163B2	Liquid crystal display device and driving method thereof A liquid crystal display (LCD) device includes a data converter for processing first and second data signals, a backlight unit emitting light having a luminance, and a liquid crystal panel supplied with the light. The LCD panel has a first and second region corresponding to the first and second data signals. The data converter differently processes gray levels of the first and second data signals a and the luminance is adjusted when the first and second regions have different brightness. The LCD driving method allows presentation of different image regions on a screen, such as moving image screens and static image screens without brightness degradation.
US08031162B2	Display device and method, recording medium, and program The present invention relates to display devices and methods, recording media, and programs that allow moving images to be displayed with less double vision. An LCD 11 updates the display in the order of the columns or rows of pixels on the screen in units of column or row in each period of a frame. LED backlights 12-1 to 12-N illuminate the pixels of the LCD 11, respectively, so as to illuminate part of all the columns or rows on the screen. A display control section 31 controls the light emission of the LED backlights 12-1 to 12-N in a manner such that the LED backlights 12-1 to 12-N illuminate the pixels updated in sequence in each period of the frame.The invention can be applied to display devices.
US08031159B2	Driving circuit for TFT liquid crystal display A driving circuit for a liquid crystal display includes a plurality of driving units each including a first OP amplifier, a second OP amplifier and a plurality of switches for switching outputs and feedback paths of the OP amplifiers. Because the switches are disposed in the feedback paths of the OP amplifiers of the driving unit, an output impedance of the driving unit can be effectively reduced and the stable time of the output voltage can be shortened.
US08031157B2	Output circuit and liquid crystal display device According to an aspect of the present invention, there is provided an output circuit including a first output unit supplying a first voltage, a second output unit supplying a second voltage, a switching unit selectively outputting, to an output end, the first voltage from the first output unit and the second voltage from the second output unit, a detection unit detecting a voltage of the output end, and a control unit controlling one of the first voltage and the second voltage on the basis of the voltage detected by the detection unit.
US08031156B2	Data driving circuit of liquid crystal display for selectively switching and multiplexing voltages in accordance with a bit order of input data A data driving circuit of a liquid crystal display for selectively switching and multiplexing voltages in accordance with a bit order of input data is disclosed. The data driver circuit includes: a voltage distributor that selects one of a first voltage and a second voltages as first output voltage in accordance with the most significant bit of input data including a plurality of n data bits, that multiplexes the first voltage and the second voltage to be output as one of more multiplexed output voltage is one of the first voltage and the second voltage selected in accordance with bits of the input data lower in significance than the most significant bit, and that outputs the first voltage as a final output voltage; and an output buffer that is driven by the first output voltage, the one or more multiplexed output voltages, and the final output voltage.
US08031154B2	Display device A display panel is scanned every two lines during a period of binary writing area in the first half of one frame period in partial display (or in small gradation display) and a steady-state current of an output amplifier for buffering gradation signals supplied to the display panel in a non-scanning period in the second half of one frame period is reduced.
US08031148B2	Liquid crystal display, apparatus for driving a liquid crystal display, and method of generating gray voltages A liquid crystal display, apparatus for driving a liquid crystal display and a method of driving gray voltages for the same. The liquid crystal display includes a plurality of gate lines transmitting gate signals, a plurality of data lines intersecting the plurality of gate lines and transmitting data voltages, and a plurality of pixel rows. Each pixel row includes a plurality of pixels, and each pixel includes a switching element connected to one of the plurality of gate lines and one of the plurality of data lines. The polarity of the data voltages supplied to the plurality of pixels are inverted by a pixel group including two or more pixel rows. The absolute values of the data voltages applied to one row of the pixel group with respect to a first predetermined voltage are greater than the absolute values of the data voltages applied to another row of the pixel group for the same grays.
US08031145B2	Liquid crystal display device and method of driving same In a liquid crystal display device which uses an electric field whereby a sufficient reset effect or sufficient overdrive effect is obtained at a lower-limit temperature at which the device is used, but which does not produce bounce at normal temperatures, the electric field applied has an intensity greater than that of an electric field at which a 99% response is obtained, and less than that of an electric field at which a 99.9% response is obtained, between a white image and a black image at the lower-limit temperature at which the device is used. Alternatively, the electric field applied has an intensity greater than that of an electric field at which average tilt angle of the liquid crystal exceeds 81 degrees, and at which average tilt angle does not exceed 85 degrees.
US08031143B2	Display device with flexible members distributing reference voltage to attached circuit board A display device includes; an insulating substrate, a display element which defines a display region and includes an organic light emitting layer which is formed on the insulating substrate, a first circuit board disposed parallel with a first side of the insulating substrate, a reference voltage pad formed on a circumference of the display region and which is electrically connected to the display element, and a first flexible member which includes a first part which adheres to the first circuit board and a second part connected to the reference voltage pad along a second side of the face of the insulating substrate.
US08031140B2	Display device and driving method thereof A pixel circuit of display device for realizing a certain color during a display period of time comprising. The pixel circuit includes at least two light emitting elements, each said light emitting element for emitting a corresponding one of colors during the display period of time. An active element is commonly connected to the at least two light emitting elements to drive the at least two light emitting elements in response to at least one emission control signal. The active element time-divisionally drives the at least two light emitting elements using the at least one emission control signal during the display period of time per a sub display period of time. The at least two light emitting elements realize the certain color in the display period of time by time-divisionally emitting the corresponding ones of the colors, one of the corresponding ones of the colors being emitted per the sub display period of time.
US08031138B2	Plasma display panel and plasma display apparatus A plasma display panel and a plasma display apparatus are disclosed. The plasma display panel includes a front substrate including a scan electrode and a sustain electrode positioned parallel to each other, an upper dielectric layer positioned on the scan and sustain electrodes, a rear substrate on which an address electrode is positioned to intersect the scan and sustain electrodes, a lower dielectric layer positioned on the address electrode, a barrier rib positioned between the front substrate and the rear substrate to partition a discharge cell, and a phosphor layer positioned inside the discharge cell. The upper dielectric layer includes a glass-based material and a blue pigment. The phosphor layer includes a phosphor material and MgO material.
US08031134B2	Method of driving plasma display panel In the initializing period of each of sub-fields comprising one field, one of all-cell initializing operation and selective initializing operation is performed. The all-cell initializing operation causes initializing discharge in all the discharge cells for displaying an image. The selective initializing operation selectively causes initializing discharge only in the discharge cells subjected to sustaining discharge in the preceding sub-field. Provided in the all-cell initializing period is an abnormal charge erasing part in which application of a rectangular waveform voltage to the scan electrodes causes self-erasing discharge in the discharge cells having excessive wall voltage accumulated therein.
US08031133B2	Method and device for manipulating color in a display A method and device for manipulating color in a display includes a display in which one or more of the pixels includes one or more display elements, such as interferometric modulators, configured to output colored light and one or more display elements configured to output white light. Other embodiments include methods of making such displays. In addition, embodiments include color displays configured to provide a greater proportion of the intensity of output light in green portions of the visible spectrum in order to increase perceived brightness of the display.
US08031130B2	Display driver and electronic instrument A display driver comprising: a high-speed serial interface circuit which receives a packet from a host device through a high-speed serial bus using differential signals, and outputs a command or data included in the received packet; a driver circuit which drives a main display panel based on the output command or data; and a low-speed serial interface circuit which outputs a command or data to a sub display driver through a low-speed serial bus when the packet received from the host device includes the sub display driver command or data. And the display driver inserts dummy data to the packet to adjust the difference of the transfer rate by inserting a dummy the dummy data. And the display driver adjust the difference of the transfer rate.
US08031129B2	Dual band dual polarization antenna array A wireless device having vertically and horizontally polarized antenna arrays can operate at multiple frequencies concurrently. A horizontally polarized antenna array allows for the efficient distribution of RF energy in dual bands using, for example, selectable antenna elements, reflectors and/or directors that create and influence a particular radiation pattern. A vertically polarized array can provide a high-gain dual band wireless environment using reflectors and directors as well. The polarized horizontal antenna arrays and polarized vertical antenna arrays can operate concurrently to provide dual band operation simultaneously.
US08031127B2	Semiconductor memory module incorporating antenna The semiconductor memory module incorporating antenna includes a wiring board (11) having a connection terminal (17) connected with a control semiconductor element (16) and arranged at a position exposed to the surface of an outer case (15), and a terminal electrode (18) for antenna connection connected with the control semiconductor element (16) and arranged in the outer case (15); a semiconductor storage element (12) mounted on one side of the wiring board (11); and a loop-like antenna (13) and an antenna terminal electrode (20) formed on the other side of the wiring board (11) along the outer peripheral thereof, the wiring board (11) includes at least one magnetic body layer (14) and the terminal electrode (18) for antenna connection is connected with the antenna terminal electrode (20).
US08031124B2	Container with electromagnetic coupling module A container includes an electromagnetic coupling module on an inner surface of a container main body and a radiator made of a metal material on an outer surface of the container main body. The electromagnetic coupling module includes a feeder circuit board, on which a radio IC chip is mounted and in which a feeder circuit including a resonant circuit that has a predetermined resonant frequency and includes an inductance element is provided. The electromagnetic coupling module and the radiator preferably transmit and receive high-frequency signals through electromagnetic coupling. The container thus has an electromagnetic coupling module that includes a radio IC chip that is resistant to a shock applied from the outside and an environmental change, realizes an easy arrangement of a radiator and the electromagnetic coupling module, provides a preferable radiation characteristic, and is suitably used in an RFID system.
US08031120B2	Wireless position location and tracking system Techniques for accurate position location and tracking suitable for a wide range of facilities in variable environments are disclosed. In one aspect, a system for position location comprises a plurality of sensors (e.g. a network monitor, an environment sensor) for generating measurements of a plurality of sources, a plurality of objects or tags, each object generating measurements of the plurality of sources, and a processor for receiving the measurements and generating a position location for one or more objects in accordance with the received measurements. In another aspect, a position engine comprises a mapped space of a physical environment, and a processor for updating the mapped space in response to received measurements. The position engine may receive second measurements from an object within the physical environment, and generate a position location estimate for the object from the received second measurements and the mapped space.
US08031119B1	Determining the angle of arrival of a target signal received by an array of antenna elements In a system for determining the angle of arrival of a target signal received by an array of antenna elements, a pair of receivers simultaneously obtain observations of a received target signal from multiple elements of an array of antenna elements; and a computer processes the simultaneously obtained samples of the target signal to determine a maximum likelihood estimation (MLE) of the angle of arrival φ of the target signal by using the following equation: φMLE=argmaxφRe(α*β). The value of β is determined in accordance with whether the target signal is known or unknown. When the target signal is unknown, the computer also processes the simultaneously obtained samples of the target signal to estimate the bandwidth of the received target signal by using binary hypotheses and a generalized log likelihood ratio test (GLLRT) or by using multiple hypotheses and pair-wise generalized log likelihood ratio tests. The value of a bandwidth constraint M that is associated with the estimated bandwidth is used to derive the value of β that is used to determine the MLE of φ.
US08031118B2	Phase correction apparatus, DVOR apparatus, and phase correction method A phase correction apparatus comprising a storing means configured to store a phase correction value associated with each of a plurality of transmission antennas in which the phase correction value is calculated according to an electrical length of a signal path extending from a signal generator generating a transmission signal to the transmission antenna, and correction means configured to correct a phase of the transmission signal to be supplied from the signal generator to each transmission antenna according to the phase correction value for the transmission antenna stored in the storing means.
US08031113B2	System and method to obtain signal acquisition assistance data Signal acquisition assistance data is obtained for receiving devices such as wireless position assisted location devices seeking signals from any source, such as satellite vehicles and base stations. The data may be obtained from previously acquired data, based upon evaluation of changes in parameters such as time and location that may jeopardize validity. In some cases the data may be adjusted for the changes in parameters. Refined data may be calculated by a receiver using partial measurements of signal sets, particularly if the acquisition assistance data provided by a remote entity includes more distinct parameters than have typically been provided. New data need not be obtained until the validity of previous data expires due to limitations upon temporal extrapolation using Doppler coefficients, unless mobile station movement that cannot be compensated is detected, and jeopardizes validity of the previous data.
US08031104B2	Microwave absorber, especially for high temperature applications A microwave absorber, especially for high temperature applications, has at least one resistive sheet and at least one dielectric layer. The resistive sheet has a material of construction that is a MAX phase material.
US08031103B2	Digitizer with variable sampling clock and method using the same A digitizer includes an analog to digital converter (ADC), a sampling frequency generator, and a controller. The ADC samples an IF signal to generate a digital signal. The sampling frequency generator is connected to the ADC and provides a sampling clock of variable frequency to the ADC. The controller is connected to the sampling frequency generator and determines frequency of the sampling clock.
US08031101B2	Spur cancellation A technique to mitigate in-band spurs introduced into a signal due to various board/SiP layout issues at a receiver is disclosed. The spurs can be approximated as sinusoids at different known frequencies with unknown amplitudes and phases. The technique is applicable to both single and multiple spur cancellation.
US08031100B2	Fine resistance adjustment for polysilicon A resistor string digital to analog converter formed of polysilicon resistor segments to each of which is applied an electric field. The approach improves the overall accuracy.
US08031099B2	Analog/digital or digital/analog conversion system having improved linearity A digital-to-analog converter (DAC) circuit includes a least significant bit (LSB) set of capacitors, each commonly coupled to an LSB node, and a most significant bit (MSB) set of capacitors, each coupled to an MSB node. A section-coupling capacitor couples the LSB and MSB nodes. The LSB node exhibits a parasitic capacitance, which tends to introduce a jump error voltage. Digital input signals are applied to the LSB and MSB capacitors, and in response, an analog output signal is developed on the MSB node. A compensation capacitor coupled to the MSB node has a compensation capacitance selected to offset the jump error voltage introduced by the parasitic capacitance. The compensation capacitor is enabled when all of the LSB capacitors are coupled to digital input signals having a logic ‘0’ state. Otherwise, the compensation capacitor is disabled (e.g., left in a floating state).
US08031098B1	DAC circuit with pseudo-return-to-zero scheme and DAC calibration circuit and method In one embodiment, digital-to-analog converter (DAC) circuit includes dual DAC units employing pseudo-return-to-zero DAC operations to reduce inter-symbol interference. Moreover, each DAC unit is implemented using complementary MOS transistors to improve conversion performance. In another embodiment, a DAC calibration scheme performs background calibration of an array of DAC circuits in continuous time using a reference DAC circuit and a spare DAC circuit. Calibration (also referred to as “trimming”) of the DAC circuit using the calibration scheme of the present invention ensures that the DAC operates with high linearity over process variations. In one embodiment, the DAC circuit and the DAC calibration scheme are applied as the feedback DAC in a continuous-time sigma-delta (CT-ΣΔ) analog-to-digital converter to realize high performance and high precision analog-to-digital conversions.
US08031097B2	Multiplying digital-to-analog converter for high speed and low supply voltage A multiplying digital-to-analog converter includes an operational amplifier (OP-amp) operated under a first power supply voltage and a second power supply voltage; an OP-amp input switch block coupled to a common mode voltage for selectively coupling the common mode voltage to input nodes of the OP-amp, wherein the common mode voltage is substantially equal to the first power supply voltage; a capacitor block coupled to the OP-amp input switch block; a sampling switch block coupled to the input signal for selectively coupling the input signal to the capacitor block; a reference voltage switch block coupled to the capacitor block for selectively coupling the reference signal to the capacitor block; and a feedback switch block coupled between the capacitor block and output nodes of the OP-amp.
US08031096B2	High resolution delta-sigma digital-to-analog converter A circuit for a delta-sigma digital-to-analog converter (DAC) includes a first stage with a delta-sigma noise-shaping loop. The first stage is capable of receiving an input signal, includes a first quantizer that has a first quantization error, and provides a first stage output. A first DAC receives the first stage output and provides a first analog output. A second stage receives the first quantization error. The second stage provides a second stage output to the digital differentiator. A second DAC receives a digital differentiator output and provides a second analog output. An adder adds the first analog output and the second analog output to provide a third analog output, so that the first quantization error is cancelled out and the inband noise is suppressed in the third analog output.
US08031092B1	Dual-mode based digital background calibration of pipelined ADCs for gain variations and device mismatches Methods and systems are described relating to dual-mode based digital background calibration of pipelined ADCs, for gain variations and device mismatches. Errors caused by gain insufficiency, nonlinearity, and capacitor mismatches are corrected by operating one ADC in two circuit configurations. These two modes are so arranged that their digital outputs differ in the presence of gain nonlinearity, gain insufficiency, and capacitor mismatches. The output difference is measured by randomly choosing one of the two operation modes at each sampling clock and digitally correlating the resulting digital output sequence. The measured output difference, which represents ADC errors, is used to remove the errors.
US08031090B2	Codebook for multiple user multiple input multiple output system and communication device using the codebook Disclosed are a Multiple User Multiple Input Multiple Output (MU-MIMO) codebook design method, and a communication device using the codebook. A MU-MIMO codebook design method includes analyzing beam patterns of candidate vectors included in a predetermined candidate codebook, and eliminating at least one of the candidate vectors based on the beam patterns of the candidate vectors to generate the MU-MIMO codebook for a MU-MIMO system being comprised of the remaining vectors.
US08031087B2	Detecting key actuation in a keyboard A system and method for detecting key actuation in a keyboard assembly, which, in one embodiment, is used as a conductor to electrically communicate with an information appliance. The rows in the keyboard assembly are electrically isolated from one another, and each row contains keys bridging a two-wire bus. Each key has a switch that is closed during key actuation, a diode to polarize the key, and a resistor to provide a resistive load when the switch is closed and the diode is biased with the current flow. Alternatively, each key has a switch that is closed during key actuation, a timer with an output that goes high after a predetermined time period, and a resistor that provides an identifying load when the switch is closed and the output of the timer is high. Other features of the invention include a linear matrix coupled to a row of keys to allow the row to be scanned by sections and individual keys, and a flexible circuit that provides the electrical pathways for the linear matrix.
US08031086B2	Method and system for determining a position of a vehicle Radio frequency identification tags are spaced apart from one another in or around a work area for the vehicle. Each of the tags has a corresponding unique identifier. A path planning module establishes a path comprising a path segment between at least two of the radio frequency identification tags. The path segment comprises at least one of a distance between the tags, an angular heading between the tags, and unique identifiers corresponding to the tags. A data processor determines an estimated position of the vehicle based on at least one of odometer data and accelerometer data. A vehicle controller navigates between at least two of the radio frequency identification tags based on the estimated position, the distance and the angular heading. A reader reads the tag identifiers of each tag to track the progress of the vehicle to facilitate execution of or retrieval of any next path segment of the vehicle along the established path.
US08031080B2	Patient support surface with vital signs sensors A patient support surface comprises a cover defining an interior region, a modifiable support layer situated in the interior region and having at least one air bladder, and a sensor layer situated in the interior region and having at least one sensor configured to detect a physiological parameter of a patient atop the patient support surface.
US08031079B2	Method and apparatus for detecting water leaks A low cost, robust, wireless sensor system that provides an extended period of operability without maintenance is described. The system includes one or more intelligent sensor units and a base unit that can communicate with a large number of sensors. When one or more of the sensors detects an anomalous condition (e.g., smoke, fire, water, etc.) the sensor communicates with the base unit and provides data regarding the anomalous condition. The base unit can contact a supervisor or other responsible person by a plurality of techniques, such as, telephone, pager, cellular telephone, Internet, etc. In one embodiment, one or more wireless repeaters are used between the sensors and the base unit to extend the range of the system and to allow the base unit to communicate with a larger number of sensors.
US08031078B1	Key chain holder with clock and alarm The invention is a key chain holder with clock and audible alarm. The invention includes a housing that contains the alarm, which is actuated by a spring-loaded trigger. The spring-loaded trigger requires at least 5 pounds of pressure in order to set off the alarm. The invention also includes a hand strap and flash light. The clock displays the time and date.
US08031071B2	IC tag label An IC tag label 1A includes an inlet substrate 11; an antenna pattern 2 and an IC chip 3 which are provided on one surface of the inlet substrate 11; and an adhesive layer 6 which is mounted on the other surface of the inlet substrate 11. A release paper 7 is attached to the adhesive layer 6. An opening 12 which serves as a clearance for the IC chip 3 is provided in a portion of the release paper 7 and adhesive layer 6, the portion corresponding to the IC chip 3.
US08031070B2	Automated system for producing location-based inventories A system for producing a location-based inventory of objects each furnished with an RFID transponder (24) designed to interact with an RFID reader/interrogator (30) and placed at different locations of a warehousing structure (10) including a plurality of rows (16A-16C) supported by vertical uprights (18A-18D). Each of the uprights of this warehousing structure is furnished at each of the rows with an RFID location transponder (26) and a processor (30; 32) to produce a location-based inventory of the objects present on the warehousing structure according to the information received from the transponders.
US08031068B1	System and method for detecting emplacement of improvised explosive devices An explosive device detection system includes sensors and base station that detect and report on suspected Improvised Explosive Devices (IED) or landmine emplacement activity within a geographic area. When disposed within a geographic area, each sensor forms part of a wireless communications network which allows communication among neighboring sensors. As a sensor detects activity in its proximity, such as activity that indicates emplacement of an IED, the sensor transmits a reporting signal through the network to the base station. The neighboring sensors receive and transmit the reporting signal in a sequential manner toward the base station. Because the reporting signal takes multiple hops toward the base station, the sensors do not require large amounts of power to transmit the signal. Furthermore, the detection system allows detection of IED emplacement within the geographic area as the activity occurs. As a result, the base station can direct mobile response units to take immediate responsive action to prevent detonation of the IED's.
US08031064B2	Tire pressure detecting apparatus and tire pressure detector identification copying method for the same A tire pressure detecting apparatus has an identification rewriteable tire pressure detector and a setting apparatus. The tire pressure detector is securely mounted on a valve stem inside a tire of a vehicle and has a micro-processing module, a sensing module, a transmitting module and a receiving interface, where the micro-processing module has a memory unit. The setting apparatus is capable of reading or inputting an identification from a failure tire pressure detector, transmits the identification to the identification rewriteable tire pressure detector and writes the identification into the memory unit.
US08031063B2	Method and apparatus for driver assistance A method and an apparatus for driver assistance, in which a distinction is made, with the aid of operating variables and a classifier, between an intentional and unintentional lane change by the vehicle.
US08031062B2	Method and apparatus to improve vehicle situational awareness at intersections The present invention includes a number of embodiments for improving vehicle situational awareness at intersections. A first embodiment may comprise a lens fitted at the top of the windshield or outside the vehicle, for refracting the light to the driver, so the driver may more easily see signals, signage and other features of an intersection, as well as other traffic. A second embodiment of the invention is used as an aid to prompt the driver that a light has changed. In a third embodiment, the light change sensor may be combined with other vehicle status information. As the car comes to a stop, the route guidance system may determine if the vehicle is at or in the vicinity of an intersection. Depending on the route guidance database, the system may also know whether or not there are traffic lights at the intersection. Using the vehicle's on board forward-looking radar sensor, the system may then determine if it is first in line at the intersection. In a fourth embodiment the system may be part of a portable after-market routing device. In a fifth embodiment the system, either portable or fixed, may be used to detect changes in the intensity of the brake lights of the vehicle ahead.
US08031060B2	Mobile system and method of operating mobile system A mobile system and method of operation thereof, comprising a radio frequency system, adapted to derive information relating to a position within an environment, based on communications with at least one terrestrial or extraterrestrial transmitter, and remotely transmit to and receive radio frequency information-bearing communications; a memory adapted to store at least a vehicle itinerary or position-related information; a controller, receiving the derived information and controlling a communication of the information-bearing communications relating to at least the stored itinerary or position related information; and a user interface, having a functionality defined by the controller, adapted to interface a user for receipt or presentation of information relating at least one of the itinerary or position-related information and the communicated information.
US08031059B2	Communication system A system (100) for communicating multimedia messages includes a multimedia message server (102) that is operable to transmit (1404, 1406, 1408) visual media, a vibration melody (1200), and an audio segment (1300) that is preferably filtered (1402) to exclude frequencies of the vibration melody (1200) through a network (104) to a client device (106), and is operable to, preferably at a later time, to transmit instructions (1410) to the client device (106) to output the vibration melody (1200), audio segment (1300) and visual media. At the client device, (106) the audio segment (1300) and the vibration melody (1200) and visual media are preferably stored (1504, 1508, 1512) in a memory (608) and in response to the instruction signal are read (1616, 1518, 1520) from the memory (608), decoded (1522, 1524, 1526) and output (1528, 1530, 1532) to a user. The vibration melody (1200) and the audio segment (1300) are preferably applied at least partially concurrently applied to an electromechanical transducer (212).
US08031058B2	Sound-emitting device A sound-emitting device (10, FIG. 1) may be mounted to a wall near places which will be unsuitable for the congregation of young person, such as outside shops and on street corners. The device generates sound waves at a frequency that is detectable by one or more subgroups of individuals within a group of individuals.
US08031054B2	Multi-antenna element systems and related methods Multi-Antenna element systems and related methods. At least some of the illustrative embodiments comprise a radio frequency identification (RFID) tag comprising an antenna system. The antenna system comprises a ground plane, a first antenna element on a first side of the ground plane, and a second antenna element on a second side of the ground plane opposite first antenna element. The illustrative RFID tag further comprises a first radio frequency identification circuit coupled to the first antenna element.
US08031052B2	Systems and methods for radio frequency identification Systems and methods providing radio frequency identification (RFID) of individuals, as may be implemented with respect to a controlled environment facility, using RFID transducer technology deployed in association with a user terminal, such as telephone or multimedia kiosk, are shown. Embodiments operate to identify residents of a controlled environment facility and control one or more transactions associated with the residents and/or actions of the residents using a RFID system in which a user presents a RFID transponder in proximity to a RFID transducer for identification. RFID tags of embodiments comprise data which identifies an individual, data which may be used to identify an individual, or a combination of both. RFID systems of embodiments are adapted to utilize existing communication links for identification of individuals using RFID and/or for controlling transactions, such as calls, using RFID.
US08031051B2	Privacy protection method, device for transmitting identifier for privacy protection, privacy protection system and program, and monitoring system To prevent privacy invasion performed according to a proper identifier which has been read.A pseudo-RFID transmission device for transmitting a pseudo identifier (RFID) for disturbing an invader is provided to an individual user. When an RFID transmission instruction is received from a tag reader (SAI), a variable type pseudo RFID different from the one which has been transmitted previously is transmitted (SA3 to SA5) and different RFID is transmitted each time for the same person. The respective pseudo RFID transmission devices are grouped into a plurality of types, so that the pseudo RFID transmission devices belonging to the same group transmit their variable type pseudo RFID while increasing the possibility to transmit common pseudo RFID accorded with one another. An area is specified for each group and the respective pseudo RFID transmission devices are provided to individual users, so that the same RFID may be transmitted for the same person.
US08031047B2	Trainable transceiver A wireless control system for a vehicle includes a controller provided in a vehicle for controlling a vehicle component in response to a first signal transmitted from a first transmitter and a transceiver provided in the vehicle for receiving a second signal from a second transmitter. The second signal differs from the first signal. The transceiver is configured to transmit a third signal to the controller in response to the second signal, the third signal emulating at least a portion of the first signal.
US08031046B2	Finger sensing device with low power finger detection and associated methods A finger sensing device may include an array of finger sensing electrodes, and a processor cooperating with the array of finger sensing electrodes for operation in a lower power consumption finger detecting mode, and for operation in a higher power consumption reading mode upon detection of a finger. The processor may selectively bus together finger sensing electrodes into at least one group from the array thereof when in the lower power consumption finger detecting mode to thereby detect a finger adjacent the array of finger sensing electrodes. Accordingly, a finger may be accurately detected and while in a low power mode, such as may be particularly beneficial to extend battery life for portable electronic devices.
US08031043B2	Arrangement comprising a shunt resistor and method for producing an arrangement comprising a shunt resistor The invention relates to an arrangement comprising a shunt resistor with at least an electrically conductive first connecting leg and an electrically conductive second connecting leg. A resistance area of the shunt resistor is electrically connected to the first connecting leg and to the second connecting leg. The arrangement further comprises a circuit carrier with a first metallization and a second metallization. The first connecting leg is directly joined to the first metallization and the second connecting leg is directly joined to the second metallization. The resistance area of the shunt resistor is in thermal contact with the thermally conductive substrate by use of a thermal filler arranged between the resistance area and the substrate, and/or by directly contacting the resistance area with the substrate.The invention further relates to a method for producing an arrangement with a shunt resistor and a circuit carrier.
US08031042B2	Power converter magnetic devices Magnetic structures for use in components utilized in switched mode power supplies can be combined to provide space and cost savings. Portions of magnetic cores can be utilized to form more than one component and/or separate magnetic cores can be combined into a single core. Further, a layer of material that has a higher flux density saturation point than the core and that is lower in permeability than the core (but higher than that of air) can be placed adjacent to the air gap in a core to decrease the magnetic flux passing through the vicinity surrounding the core so as to reduce EMI. A differential-mode choke and a separate common-mode choke can be combined onto a single core. An extra leg for a PFC choke core can be added to an isolation transformer core to form a single combined core. A pair of E-E core structures can be combined into a single core structure such as could be used to combine a pair of separate PFC chokes into an integrated pair of PFC chokes.
US08031038B2	Magnetic fixing device The magnetic fixing device comprises a clamping plate having a fixing surface to which a clamping object is fixed and plural magnetic force generation mechanisms. The magnetic force generation mechanisms each comprise a magnetic material member facing the fixing surface, plural permanent magnets arranged around the outer periphery of the magnetic material member, a first Alnico magnet placed on the back of the magnetic material member, and a first coil for switching the polarity of the first Alnico magnet, and can be switched between the absorption state in which the clamping object is adsorbed and the non-absorption state in which the clamping object is not adsorbed. An operation state indication mechanism capable of presenting an indicator indicating that the plural magnetic force generation mechanisms are in the absorption state or in the non-absorption state is provided on the fixing surface or outer periphery of the clamping plate.
US08031036B2	Dielectric resonator and filter with low permittivity material A resonator cavity for supporting a plurality of resonant modes and filtering electromagnetic energy includes a cavity and a resonator element with a mounting flange. The cavity is defined by a top end wall, a bottom end wall and a sidewall and has a longitudinal axis along its length is defined. The resonator element is positioned within the cavity along the longitudinal axis and includes a mounting flange. The resonator element is only in physical contact with the cavity through the mounting flange at a mounting location and where at least one resonant mode of the electromagnetic energy exhibits a local minima. The dimensions of the cavity and the resonator element are selected so that the associated electromagnetic energy is defined by an electromagnetic field pattern that substantially repeats itself at least twice along the length of the resonator.
US08031029B2	Differential signal transmission cable and method for compensating length offset thereof A compensation method compensates for a length offset between a first transmission line and a second transmission line of a differential signal transmission. The compensation method includes calculating a transmission speed of a first signal in the first transmission line, measuring lengths of the first and second transmission lines, calculating a transmission time of the first signal in the first transmission line, and calculating a relationship between permittivity values of the first and second transmission lines. The compensation method further changes the permittivity values of the first and second transmission lines according to the relationship.
US08031028B2	Polar signal processor to drive a segmented power amplifier and method therefore A circuit for providing AM/PM modulation is described. The circuit provides two drive signals which are later combined in a constructive/destructive fashion. The circuit provides AM modulation with a drive signal having a consistent power level modulated to have varying pulse widths in order to provide variable power within each cycle.
US08031027B2	Voltage-controlled oscillator, phase-locked loop (PLL) circuit, and clock generator A voltage-controlled oscillator includes a voltage regulator, and a delay unit. The voltage regulator independently receives a first oscillation control signal and a second oscillation control signal to provide a regulated voltage signal which is represented by a regular ratio of combination of the first and second oscillation control signals, and the regulated voltage signal is feedback to the voltage regulator. The delay unit generates an output signal having a frequency varying in response to the regulated voltage signal.
US08031023B2	Crystal oscillator for surface mounting The crystal oscillator for surface mounting includes: a container body having first and second recesses on both principal surfaces thereof; a crystal blank hermetically encapsulated within the first recess; and an IC chip in which an oscillation circuit using the crystal blank is integrated, the IC chip being accommodated within the second recess. The IC chip is provided with a plurality of IC terminals including a pair of crystal terminals used for electrical connection with the crystal blank. A plurality of mounting electrodes to which the IC terminals are connected through flip-chip bonding are formed on a bottom surface of the second recess in correspondence with the IC terminals. A pair of mounting electrodes corresponding to the pair of crystal terminals are electrically connected to the crystal blank and also formed as a pair of dual-purpose electrodes having greater areas than the other mounting electrodes.
US08031022B2	Oscillation circuit including MIT device and method of adjusting oscillation frequency of the oscillation circuit Provided are an MIT device-based oscillation circuit including a power source, an MIT device and a variable resistor, in which a generation of an oscillation and an oscillation frequency are determined according to a voltage applied from the power source and a resistance of the variable resistor, and a method of adjusting the oscillation frequency of the oscillation circuit. The MIT device includes an MIT thin film and an electrode thin film connected to the MIT thin film, and generates a discontinuous MIT at an MIT generation voltage, the variable resistor is connected in series to the MIT device, and the power source applies a voltage or an electric current to the MIT device. The generation of an oscillation and an oscillation frequency are determined according to the voltage applied from the power source and the resistance of the variable resistor.
US08031021B2	Oscillation circuit based on metal-insulator transition device and method of driving the oscillation circuit Provided are an oscillatory circuit based on a metal-insulator transition (MIT) device that can generate a simple and very high oscillating frequency using the MIT device, and a method of driving the oscillatory circuit. The oscillatory circuit includes the MIT device that comprises an MIT thin film and an electrode thin film connected to the MIT thin film and in which an abrupt MIT is generated due to an MIT generating voltage, a resistor that is serially connected to the MIT device, an electric al power source limiting the maximum amount of an applied current and applying a direct current constant voltage to the MIT device, and a light source irradiating electromagnetic waves on the MIT device, wherein the oscillating properties are generated by irradiating the electromagnetic waves using the light source.
US08031019B2	Integrated voltage-controlled oscillator circuits Techniques for providing voltage-controlled oscillator circuits having improved phase noise performance and lower power consumption. In an exemplary embodiment, a voltage controlled oscillator (VCO) is coupled to a mixer or a frequency divider such as a divide-by-two circuit. The VCO includes a transistor pair with magnetically cross-coupled inductors, and variable capacitance coupled to the gates of the transistor pair. In an exemplary embodiment, a frequency divider is configured to divide the frequency of the differential current flowing through the transistor pair to generate the LO output. In an alternative exemplary embodiment, a mixer is configured to mix the differential current flowing through the transistor pair with another signal. The VCO and mixer or frequency divider share common bias currents, thereby reducing power consumption. Various exemplary apparatuses and methods utilizing these techniques are disclosed.
US08031017B2	Method and apparatus for determining within-die and across-die variation of analog circuits Described herein is the method and apparatus for determining frequency of an oscillator coupled with one or more analog devices, and for determining within-die or across-die variations in an analog property associated with the one or more analog devices, the determining based on the oscillator frequency. The analog property includes output signal swing, bandwidth, offset, gain, and delay line linearity and range. The one or more analog devices include input-output (I/O) buffer, analog amplifier, and delay line. The method further comprises updating a simulation model file based on the determining of the within-die and/or across-die variations of the analog property.
US08031011B2	Digitally controlled oscillators Oscillator circuitry is provided that is based on a ring of inverters. The ring of inverters may be single-ended or differential inverters. Digitally controlled adjustable load capacitors may be provided at inverter outputs to tune the oscillator circuitry. Each digitally controlled adjustable load capacitor may be formed from multiple varactors connected in parallel. Each varactor may have a control input that receives a digital control signal. The digitally controlled adjustable load capacitors in a given oscillator may be adjusted in unison to produce the same capacitance value for each capacitor or may be adjusted individually so that they produce different capacitance values. The inverters may include common-mode-gain reduction features such as series-connected current sources, series-connected resistors, and cross-coupled negative feedback transistors.
US08031003B2	Solid-state RF power amplifier for radio transmitters An RF power amplifier includes a push-pull amplifier having field effect transistors. Temperature compensating bias circuitry provides a temperature compensated bias voltage to the transistors for decreasing the bias voltage thereof as temperature increases. The temperature compensating bias circuitry includes a temperature sensor generating a temperature signal. A first amplifier provides a first temperature dependent voltage based on the temperature signal. A second amplifier provides a second temperature dependent voltage based on the temperature signal. The first and second temperature dependent voltages change at substantially the same rate in response to the temperature signal. A potentiometer receives the first and second temperature dependent voltages such that a voltage across the potentiometer remains substantially constant when the first and second temperature dependent voltages change. An output of the bias circuitry is connected to at least one of the transistors and supplies the temperature compensated bias voltage to the at least one of the transistors.
US08031001B2	Differential amplifier, reference voltage generating circuit, differential amplifying method, and reference voltage generating method A differential amplifier includes a main differential amplifier circuit that receives a pair of input signals and supplies a pair of output signals based on a difference between the input signals; and a bias control differential amplifier circuit that receives the pair of output signals, controls a control terminal of a current-limiting transistor making up the main differential amplifying circuit based on an offset voltage included in the output signals, and reduces the offset voltage.
US08030997B2	Resource efficient adaptive digital pre-distortion system A digital pre-distortion system which can provide the flexibility to model the highly non-linear distortion associated with High Efficiency RF Power Amplifiers while through a novel implementation of a least squares estimation process allows an implementation well suited for an FPGA application where limited resources and in particular memory resources are available.
US08030996B1	Apparatus and method for automatic level control A circuit and method for automatic level control is provided. The circuit includes an amplifier including a variable resistance circuit that is connected between a first node and a second node. The circuit also includes a first resistance circuit that is connected between a first input node and the first node, and a second resistance circuit that is connected between the first input node and a first op amp node. The first and second resistance circuits are at least approximately linear elements. The circuit also includes an op amp having at least a first input that is connected to the first op amp input node.
US08030995B2	Power circuit used for an amplifier A power circuit used for an amplifier, which includes an amplifier provided with a linear amplifier serving as a voltage source, a DC/DC converter serving as a current source, a hysteresis comparator controlling the DC/DC converter, and a current detector detecting output current from the linear amplifier to output the detected output current to the hysteresis comparator; and a switching restricting device for restricting a switching interval in the DC/DC converter such that the switching interval is not equal to or less than a constant time or is not shorter than the constant time.
US08030994B2	Driver for an inductive load A driver supplies an output voltage to an inductive load. The driver includes an input to receive a pulse width modulated control signal having a controllable duty cycle within a predetermined range. A first switch circuit receives a first switch signal to supply a first voltage, a second switch circuit receives a second switch signal to supply a second voltage, and the output voltage is the difference between the first voltage and the second voltage. An inverter and delay circuit receives the control signal to supply the first switch signal and the second switch signal being inverted and delayed with respect to each other. The delay of the delay circuit is selected to obtain an output voltage having a single polarity for each one of the controllable duty cycles within the predetermined range.
US08030990B2	Measuring instrument in two-conductor technology In a two-conductor technology circuit the use of certain ASIC components is made possible which, for instance, allow for the supply of contact-free rotational angle sensors, although said ASIC components have a high current consumption.
US08030987B2	Level shifter circuit and semiconductor device having the same A level shifter circuit includes a pull-up unit configured to pull up an output node to a second voltage level being higher than a first voltage level in response to an input signal swinging with an amplitude of the first voltage level, a pull-down unit configured to pull down the output node in response to the input signal, and a protection unit connected between the output node and the pull-down unit to prevent a voltage of the output node from being applied to the pull-down unit.
US08030986B2	Power transistor with turn off control and method for operating A circuit has a power transistor, a driver control circuit, a variable clamp circuit and a turn-off control circuit. The power transistor has a first current electrode coupled to a first power supply terminal, a second current electrode as an output of the circuit, and a control electrode. The driver control circuit has an output coupled to the control electrode of the power transistor for controlling the power transistor during an active mode of the circuit. The variable clamp circuit is coupled between the output of circuit and the first power supply terminal. The turn-off control circuit is coupled to the variable clamp circuit and selects clamping levels of the variable clamp circuit during a transition from the active mode to an inactive mode of the circuit.
US08030985B2	System and method for compensating pulse generator for process and temperature variations An apparatus for generating a pulse having a pulse width substantially independent of process variation in resistive and capacitive values. The apparatus includes a PTAT current source to generate a first current to charge a capacitor to produce a first voltage; a ΔVGS current source to generate a second current through a resistor to produce a second voltage V2; a comparator to generate the pulse in response to the first and second voltages; and a circuit to enable the charging and discharging of the capacitor. The use of the distinct current sources (e.g., PTAT and ΔVGS) enables the pulse generator to be configured substantially process independent of resistive value. The use of a MOSFET capacitor for the capacitor enables the pulse generator to be made substantially process independent of capacitive value. An additional bandgap current source in parallel with the ΔVGS current source reduces the pulse width dependency on temperature.
US08030979B2	Circuit for generating reference voltage A reference voltage generating circuit includes a reference voltage generating unit generating a uniform reference voltage in response to a bias voltage, a bias voltage generating unit generating the bias voltage, and a start-up circuit, after activating the bias voltage generating unit by receiving a first supply voltage, canceling a change of the first supply voltage to maintain a separation from the bias voltage generating unit. The circuit adopts a start-up circuit having a voltage distributing unit, thereby preventing a quiescent point of a bias voltage generating unit from entering a zero state and prevents a reference voltage from rising in a power-up state that an analog supply voltage rises according to a change of an external design environment such as a power, a temperature, a process parameter and the like, thereby generating a reference voltage more stably. As a result, current consumption and power consumption are minimized.
US08030978B2	Soft-start circuit A soft-start circuit is provided. The soft-start circuit comprises: an input stage, a pump stage, a second resistor and a capacitor. The input stage comprises a first resistor to receive an input voltage to provide a reference current at a first node. The pump stage comprises N current branches connected in parallel each comprising a current source connected to the first node and a switch to transfer the current from the current source to the second node while the switch operates in a connecting state. The switches has 2N connecting modes performed one after another to generate an output current with a gradual increment output current at the second node with 2N current levels; and the second resistor and the capacitor are connected in parallel between the second node and the ground potential to generate an output voltage with a gradual increment with 2N voltage levels according to output current.
US08030977B2	Clock generating circuit A main (sub) clock circuit comprising a first (second) capacitor, a first (second) current-supply circuit to supply to the first (second) capacitor a first (third) current for charging at a predetermined-current value or a second (fourth) current for discharging at a predetermined-current value, a first (second) charge/discharge-control circuit to output a first (second) control signal for switching between the first (third) current and second (fourth) current which are supplied to the first (second) capacitor from the first (second) current-supply circuit when a voltage across the first (second) capacitor has reached a first (third) reference voltage or second (fourth) reference voltage higher than the first (third) reference voltage, and a first (second) output circuit to output a main (sub) clock according to the first (second) control signal, the first capacitor having one end connected to a first potential, the second capacitor having one end to which the main clock is input.
US08030971B2	High-density logic techniques with reduced-stack multi-gate field effect transistors Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required in series or “stacked” portions of logic gates. Circuit area can be reduced and performance can be enhanced.
US08030970B2	Device forming a logic gate for detecting a logic error The invention relates to a device for forming an electric circuit comprising logic means (30) generating and using small signals of intermediate levels between the device supply levels and means for detecting signals leaving the small signal range.
US08030964B1	Techniques for level shifting signals A level shifter circuit includes an input circuit, an inverter, a pull-up circuit, and a pull-down circuit. The input circuit generates a pull-up signal in response to an input signal using charge from a supply voltage. The inverter inverts the input signal to generate a pull-down signal. The inverter comprises complementary transistors that receive charge from the supply voltage. The pull-up circuit pulls a level shifted output signal of the level shifter circuit to the supply voltage in response to the pull-up signal. The pull-down circuit pulls the level shifted output signal to a low voltage in response to the pull-down signal.
US08030961B2	Semiconductor integrated circuit A semiconductor integrated circuit includes a control signal generating circuit which is configured to set, at least at a time of a first state, first and fifth control signals at a first voltage level, and second, third and fourth control signals at a second voltage level, and to set, at a time of a second state, the first to fourth control signals at the first voltage level, and the fifth control signal at an arbitrary voltage level.
US08030955B2	Probe card inclination adjusting method, inclination detecting method and storage medium storing a program for performing the inclination detecting method An inclination adjusting method adjusts an inclination of a probe card installed at a probe apparatus to make the probe card be in parallel with a mounting surface of a movable mounting table for mounting thereon an object to be inspected. The method includes: detecting an average tip height of multiple probes disposed at each of plural locations of the probe card by using a tip position detecting device; obtaining an inclination of the probe card with respect to the mounting table based on differences in the average tip heights detected from the plural locations of the probe card; and adjusting the inclination of the probe card based on the obtained inclination.
US08030953B2	Device and method for testing integrated circuits A method and device for testing an integrated circuit. The method includes selecting between a shadow latch data retention mode and a shadow latch test mode; performing a first test of an integrated circuit; storing, at the shadow latch if the shadow latch test mode is selected, information representative of a first test-imposed state; performing a second test of the integrated circuit; and generating a test equipment detectable signal if the first test-imposed state differs from a second test-imposed state of the tested latch.
US08030952B2	Power sink for IC temperature control The use of a power sink function in IC testing results in a simple and rapid method for testing ICs, and assembled modules, at elevated temperature profiles without the use of environmental ovens. Testing IC devices at elevated temperatures may be useful for ‘burn-in’, for ‘hot sort’ performance testing that may be used in electronic devices such as DRAM memory, logic, communication devices, and microprocessors. The power sink function may be implemented as an additional isolated area of active devices, or as a section of the circuit that is not involved in the testing procedure. Alternately, the power dissipation circuit may consist of a resistive path between two external pins that are not used for IC operation, where the resistor may be on the IC or on the package. This allows for control of the temperature level and profile by simple adjustment of the voltage between the two external pins.
US08030951B2	Cathodic protection monitor A cathodic protection monitor to be electrically connected to a cathodic protection rectifier that is adapted to prevent rust, corrosion and possible leakage in an underground pipe or storage tank above which the rectifier is supported. The cathodic protection monitor includes a CPU that reads, digitizes and stores analog current and voltage signals which are indicative of the effectiveness of the rectifier. The monitor includes an ISM band transceiver and antenna by which the CPU is polled and from which packets of stored data are transmitted to a data collector for retransmission and analysis by the pipe owner or maintenance crew. Synchronized timing signals are supplied (from the National Bureau of Standards) to a stable auxiliary clock by way of a WWVB transceiver and antenna so that a plurality of cathodic protection rectifiers can be turned on and off at the same time as may be required to compile ground voltage readings along the pipeline as part of a government-mandated survey.
US08030949B2	Measurement method for determining moisture content In a method for capacitive determination of the moisture content in a gas to be measured, it is provided that a capacitive element (2) brought into contact with a gas to be measured is operated in the manner of an RC oscillator (5) in charge-discharge cycles (27, 28), with the moisture content of the gas to be measured being determined from the time duration of a cycle. To assess measurement errors brought about by contaminants or aging effects, a measure for the time duration of a charging process (27) and a discharging process (28) is determined from output signal (26) of RC oscillator (5) and is processed with the measurement signal for the moisture content into a corrected measurement signal.
US08030946B2	In-pipe coating integrity monitor for very long pipes Systems, methods and program products of instructions stored on a computer readable medium related to a tether free piggable inspection tool capable of detecting holidays and able to read and store non-conductive internal coating thickness values in very long conductive pipes, along with distance values for further off-line analysis, are provided. The inspection tool includes a plurality of thickness probes, a data storage unit, a control unit, a plurality of navigation wheels and a holiday detector that uses an electrical conductive medium, such as a gas or fluid, as the ground connection. A closed loop configuration is adopted allowing the system to autocorrect itself for different coating thicknesses along the pipe.
US08030943B2	Circuit for the detection of solder-joint failures in a digital electronic package The solder-joint integrity of digital electronic packages, such as FPGAs or microcontrollers that have internally connected input/output buffers, is evaluated by applying a time-varying voltage through one or more solder-joint networks to charge a charge-storage component. Each network includes an I/O buffer on the die in the package and a solder-joint connection, typically one or more such connections inside the package and between the package and a board. The time constant for charging the component is proportional to the resistance of the solder-joint network, hence the voltage across the charge-storage component is a measurement of the integrity of the solder-joint network.
US08030942B2	Method and apparatus for providing stable voltage to analytical system An electrochemical cell has two terminals. One of the terminals is connected to a pulse-width-modulated (PWM) power supply and to a voltmeter. The other terminal is connected to circuitry capable of switching between amperometric and potentiometric measurement modes. A sequence of successive approximations permits selection of a PWM duty cycle giving rise to a desired voltage at the terminal connected with the power supply. In this way a stable excitation voltage is supplied to the cell even in the face of supply voltage instability or drift or instability in electronics coupled with the cell.
US08030939B2	Electronic apparatus and controlling method for the same An electronic apparatus which is capable of correctly displaying the remaining usable time even if a discharged current of a battery pack is changed by an unexpected load due to an external apparatus connected. The electronic apparatus has a battery pack with a secondary battery mounted therein. A first remaining usable time of the electronic apparatus is calculated based on a consumed current of the electronic apparatus. A second remaining usable time of the electronic apparatus is calculated based on a discharged current of the secondary battery. The first remaining usable time calculated by the first remaining usable time calculating unit or the second remaining usable time calculated by the second remaining usable time calculating unit, whichever is smaller, is selected, and then a displaying unit displays the selected remaining usable time.
US08030937B2	Multiple frequency based leakage correction for imaging in oil based muds Oil-based mud imaging systems and methods having leakage current compensation. In some embodiments, disclosed logging systems include a logging tool in communication with surface computing facilities. The logging tool is provided with a sensor array having at least two voltage electrodes positioned between at least two current electrodes that create an electric field in a borehole wall, and is further provided with electronics coupled to the current electrodes to determine a differential voltage between the voltage electrodes in response to different current frequencies from the current electrodes. From the voltage measurements at different frequencies, the computing facilities determine borehole wall resistivity as a function of depth and azimuth, and may display the resistivity as a borehole wall image.
US08030930B2	Magnetic resonance imaging local coil composed of separate parts A separated coil for a magnetic resonance imaging system has a first partial coil in a first partial casing and a second partial coil in a second partial casing, the first and second partial coils being connected to a connector for connection to the imaging system via a first cable and a second cable, respectively. The coil also has a coupler having a first part disposed in the first partial casing and connected to the first partial coil, and a second part, coupled to the first part, disposed in the second partial casing. The first cable is disposed in the second partial casing, and the second part of the coupler is connected to the connector for connection to the imaging system via the first cable. The signals in the first partial coil are coupled and connected to the cable and the connector via the coupler.
US08030929B2	Coil and MRI system A coil includes a coil element to receive MR signals with a first frequency from a subject. The coil element includes a main current path section in which an MR current arising due to electromagnetic induction of the MR signals with said first frequency flows, and a current blocking section that makes smaller than said MR current an electromagnetic current flowing in said main current path section due to electromagnetic induction of electromagnetic waves with a second frequency different from said first frequency.
US08030926B2	Surface coil arrays for simultaneous reception and transmission with a volume coil and uses thereof This invention provides arrays of counter rotating current surface coils for simultaneous reception and transmission with a volume coil for improved signal-to-noise ratio and radio frequency field homogeneity for in particular high-field (4-8 T) imaging of deep body regions, such as central brain structures.
US08030925B2	Tunable superconducting resonator and methods of tuning thereof A method of tuning a high temperature superconductor (HTS) resonator includes the steps of providing a HTS inductor and a HTS capacitor, the HTS capacitor being electrically connected to the HTS inductor. A tuning body is provided adjacent to the HTS inductor and the HTS capacitor. The relative position of the tuning body with respect to the HTS inductor and the HTS capacitor is altered so as to tune the resonator. A tunable resonant circuit is provided that includes a substrate having a planar surface. At least one resonator formed from HTS material is disposed on the substrate, the resonator having one or more turns that when combined, turn through greater than 360°.
US08030924B2	Magnetic resonance imaging system A magnetic resonance imaging system capable of conducting spectroscopic imaging with an improved SNR without degrading the spatial resolution includes edge-preserving filter processing means for spectroscopic imaging. The edge-preserving filter processing means executes processing including the steps of calculating spectral similarity in spatial neighborhoods (spatially neighboring voxels) at each voxel in spectroscopic imaging data, calculating a spectral weight according to the spectral similarity, and conducting weighted smoothing for compounding spectra of spatial neighborhoods (spatially neighboring voxels) according to the spectral weight.
US08030915B2	Integrated sensor with capacitive coupling rejection to the mechanical ground An integrated sensor includes: i) a voltage regulator coupled with a mechanical ground and delivering a regulated voltage based on a primary power supply voltage referencing an electrical ground; ii) a high-impedance sensitive element powered by the primary power supply, electrically coupled to the mechanical ground and delivering an electrical quantity representative of a physical quantity; iii) an amplification module powered by the regulated voltage and including a first input receiving an analog reference dependent on the regulated voltage and a second input receiving the electrical quantity, and designed to deliver a first output voltage representing the amplified measurement voltage; and iv) a differential amplifier powered by the primary power supply voltage, referencing the electrical ground and including first and a second inputs receiving the analog reference and the first output voltage, respectively, and delivering a second output voltage representing the first amplified output voltage referenced to the electrical ground.
US08030914B2	Portable electronic device having self-calibrating proximity sensors A method of a portable electronic device for self-calibration of a proximity sensor. A background measurement is obtained by the proximity sensor and a detection threshold of the proximity sensor is adjusted based on the background measurement. The background measurement is a measure of a received signal when no signal is transmitted by the proximity sensor, and the detection threshold is associated with a sensitivity of the proximity sensor to environmental conditions. A source signal is emitted by the proximity sensor based on the adjusted detection threshold of the proximity sensor, and a return signal is received by the proximity sensor corresponding to the source signal. A function of the portable electronic device may be performed base don the received return signal.
US08030913B1	Detector circuit with improved bandwidth A detector circuit for an operational bandwidth having a center frequency including a diode, a first inductor in series with the diode, a transmission line coupled across the diode on a first end of the transmission line, the transmission line having an impedance and being in length a quarter wavelength of a frequency near the center frequency of the operational bandwidth, and a capacitor coupled across a second end of the transmission line.
US08030912B2	Method and apparatus for controlling the maximum output power of a power converter A controller for a power converter is disclosed. An example circuit controller according to aspects of the present invention includes an input voltage sensor to be coupled to receive an input signal representative of an input voltage of the power converter. A current sensor is also included and is to be coupled to sense a current flowing in a power switch. A drive signal generator is to be coupled to drive the power switch into an on state for an on time period and an off state for an off time period. The controller is coupled to adjust a duty cycle of the power switch in response to a difference between a time it takes the current flowing in the power switch to change between two current values when the power switch is in the on state and a control time period.
US08030910B2	DC-DC converter A dual-mode switching voltage regulator has a duty cycle that varies with the input and output voltages so as to dynamically compensate for changes in the operating conditions. The switching voltage regulator uses input and output voltages/currents to optimize the duty cycle of the signals applied to a pair of switches disposed in the regulator. In the PFM mode, a control block senses the time that a first switch used to discharge an inductor is turned off. If the control block senses that the first switch is opened too early, the control block increases the on-time of a second switch used to charge the inductor. If the control block senses that the first switch is opened too late, the control block decreases the on-time of the second switch.
US08030908B2	Control method for multi-phase DC-DC controller and multi-phase DC-DC controller A multi-phase DC-DC controller. The multi-phase DC-DC controller comprises converter channels, a channel control device and a power control device. Each converter channel comprises a switch device, a first output node and an inductor coupled between the switch device and the first output node. The channel control device generates adjusted pulse width modulation signals according to control signals of the converter channels to respectively control operation of the switch device in each converter channel. The power control device generates the control signals according to sensed currents in the converter channels so as to dynamically turn on or off each converter channel according to the sensed currents.
US08030903B2	Power generator and electronic apparatus A power generator capable of improving power generation efficiency is obtained. This power generator includes a movable portion moving by kinetic energy acting on a power generator body, a first conversion portion converting kinetic energy of the movable portion to electric energy and a movement direction changing portion changing a direction in which the movable portion moves to a direction along a direction in which acceleration applied to the movable portion is larger regardless of a direction of the power generator body.
US08030900B2	Circuits and methods for controlling power in a battery operated system Embodiments of the present invention include systems and methods of controlling power in battery operated systems. In one embodiment, the present invention includes a switching regulator for boosting voltage on a depleted battery to power up a system. The system may communicate with an external system to increase the current received from the external system. Embodiments of the present invention include circuits for controlling power received from external power sources such as a USB power source. In another embodiment, input-output control techniques are disclosed for controlling the delivery of power to a system or charging a system battery, or both, from an external power source.
US08030899B2	Battery management for optimizing battery and service life The provision of a mode in silver zinc batteries where a user can access extra capacity as an emergency reserve for times when extra capacity is needed. While this temporarily increases capacity, it does not detrimentally affect cycle life over the longer term, and it permits a silver zinc battery to essentially mimic the long term capacity and cycle life characteristics of a lithium ion battery while still affording inherent advantages associated with silver zinc batteries. In a variant embodiment, this ability to temporarily increase capacity is optimally employed at the end of a battery life cycle in a controlled “roll-off” that accords additional cycles of battery service life. In another variant embodiment, the general capability to control capacity is employed to gradually decrease the available capacity of a battery over the life of the battery, to thereby extend the battery service life.
US08030894B2	System and method for rebalancing a vehicle battery A vehicle may include an electric machine, a battery, a driver interface and one or more controllers. The one or more controllers may be configured to determine whether a battery imbalance condition exists, to cause an alert to be generated via the driver interface if a battery imbalance condition exists, to determine whether a response to the alert is received, and to cause the battery to be rebalanced in a single cycle if a response to the alert is received.
US08030893B2	Battery pack and method for detecting disconnection of same The battery pack includes an assembled battery including a plurality of secondary battery cells connected at least in series; a voltage detector which detects a terminal voltage of each of the plurality of secondary battery cells; a charge/discharge controller which controls charge/discharge of the assembled battery based on the terminal voltage of each cell detected by the voltage detector; a short-circuiting section which short-circuits a node between cells to the high voltage side or the low voltage side of a power line, or which short-circuits nodes between the cells to each other; and a disconnection detector which controls conduction/non-conduction of the short-circuiting section and which detects a disconnection of the connection line from the voltage detector to the node between the cells, based on a state of controlling the conduction/non-conduction, and at least one of a voltage at the node between the cells detected by the voltage detector, a voltage of the high voltage side or the low voltage side of the power line, and a terminal voltage of each cell. The floating (disconnection) of intermediate taps of the secondary battery cells can be reliably detected without causing losses in regular processes.
US08030891B2	Ambulatory medical device with electrical isolation from connected peripheral device Methods and apparatus are provided for electrically isolating an ambulatory medical device for infusing treatment materials into a patient when the medical device is connected to a peripheral device via an active communication cable. In one embodiment, the ambulatory medical device include first circuitry controlling infusion of a medicament to the patient by a fluid conduit connectable to the patient and second circuitry controlling communications when an active communication cable is connected to the medical device. The first and second circuitry are electrically isolated using a pair of first and second isolation transceivers, where the first pair of isolation transceivers communicate a control signal and the second pair of isolation transceivers are giant magneto-resistive (GMR) transceivers that communicate at least one data signal.
US08030884B2	Apparatus for transferring energy using onboard power electronics and method of manufacturing same An apparatus comprises a first energy storage device configured to output a DC voltage, a first bi-directional voltage modification assembly coupled to the first energy storage device, and a charge bus coupled to the first energy storage device and to the first bi-directional voltage modification assembly. The apparatus also comprises high-impedance voltage source coupleable to the charge bus and a controller configured to monitor a transfer of charging energy supplied from the high-impedance voltage source to the first energy storage device. The controller is also configured to compare the monitored transfer of charging energy with a threshold value and, after the threshold value has been crossed, control the first bi-directional voltage modification assembly to modify one of a voltage and a current of the charging energy supplied to the first energy storage device.
US08030883B2	Hybrid control device In a hybrid control device performing cooling control of a secondary battery of a hybrid vehicle, the hybrid control device limiting the amount of charge/discharge of the secondary battery based on an air volume flow of a cooling fan cooling the secondary battery, an operation control mode of the secondary battery cooling fan is changed from an ordinary control mode to a power mode in which an air volume flow of the cooling fan is larger than in the ordinary control mode, whereby a limiting value of the amount of charge/discharge of the secondary battery is varied to expand the usable range of the secondary battery. Accordingly, when improvement of drive power performance is desired by an operator more than low noise within the vehicle, the amount of charge/discharge of the secondary battery is not limited by the cooling fan, and larger drive power performance is thus achieved.
US08030882B2	Power supply unit A power supply unit that allows a main battery and an auxiliary battery to be charged by a system power supply is disclosed. The first and second bridge circuits of the power supply unit are each formed of four switching elements. The transformer of the power supply unit has a primary winding connected to the first bridge circuit, and a secondary winding connected to the second bridge circuit. The DC/DC converter of the power supply unit allows the auxiliary battery to be connected to the first and second circuits. The controller of the power supply unit controls the switching elements of the first bridge circuit, the switching elements of the second bridge circuit, and the switching element of the DC/DC converter such that power that has been charged to the main battery is output as an AC voltage having voltage and frequency for electric appliances.
US08030877B2	Device and method for detecting back electromotive force phase and device and method for controlling excitation In a back electromotive force phase detecting device, a timing generating unit generates a timing signal indicating a start timing, an intermediate timing and an end timing of a 180-degree electrical angle period in a detection target phase, from an excitation pulse signal. A difference calculating unit receives the timing signal, and calculates a difference between a total PWM control period of the detection target phase during a first-half 90-degree period, and a total PWM control period of the detection target phase during a second-half 90-degree period. In an excitation control device, a control unit changes the capability of driving a motor based on an output of the back electromotive force phase detecting device.
US08030876B2	Stepper motor device with compensating non-sinusoidal driving values and method of producing the driving values A stepper motor device uses compensating non-sinusoidal driving values to compensate for operational non-sinusoidal drive characteristics of a motor of the device due to at least design and manufacturing imperfections in the motor. The compensating non-sinusoidal driving values may be derived using back electromagnetic force produced from the motor or using measured rotational positions of the motor when the motor is driven using known driving values.
US08030859B2	Cold-cathode lamp, and display illumination device and display device therewith A cold cathode lamp includes a light-transmitting insulating tube, first and second internal electrodes arranged inside the insulating tube, first and second external electrodes arranged outside the insulating tube and respectively connected with the first and second internal electrodes, first and second insulating bodies respectively covering the first and second external electrodes, a first counter electrode arranged opposite to the first external electrode via the first insulating body, and a second counter electrode arranged opposite to the second external electrode via the second insulating body. The first (second) counter electrode has a portion which does not face the first (second) external electrode, and the space between this portion and the insulating tube is filled with the first (second) insulating body. A plurality of such cold cathode lamps can be lit by being connected in parallel with a power supply. In addition, generation of corona discharge near the outer peripheries of the counter electrodes can be suppressed.
US08030858B2	Inverter circuit, backlight device and liquid crystal display having the same An inverter circuit for a backlight device includes an inverter transformer which supplies a high AC voltage to a plurality of discharge tubes, a filter circuit connected to an output terminal of the inverter transformer, and an abnormal discharge detection circuit. The filter circuit passes a current signal having a high frequency component of the high AC voltage to the abnormal discharge detection circuit, and the abnormal discharge detection circuit detects an abnormal discharge current based on the current signal.
US08030857B2	Backlight LED drive circuit A backlight LED drive circuit 20 includes a step-up DC/DC converter 22 for stepping up a DC power voltage based on a PWM signal and supplying the voltage to the anode of an LED device 12c, a voltage detector 24 for detecting a feedback voltage FBV based on a voltage at a terminal 22b coupled to the cathode of the LED device, a PWM control circuit 26 for outputting a PWM signal to the step-up DC/DC converter 22 so that the feedback voltage FBV may become a predetermined voltage, and a PWM stop circuit 28 for stopping the PWM signal when the feedback voltage FBV is below a second predetermined voltage set smaller than the predetermined voltage. Thereby, such backlight LED drive circuit causes no troubles even when terminal to which the LED device is connected is rendered open.
US08030855B2	Single-stage electronic ballast for a fluorescent lamp The invention provides a single-stage electronic ballast for a fluorescent lamp, comprising a boost circuit and a load unit. The boost circuit includes a first inductor, a first capacitor, a first diode and at least a switch, wherein the positive terminal of the first diode is connected to the first inductor, and the negative terminal of the first diode is connected to the at least a switch. The load unit includes at least a fluorescent lamp, two terminals of the first capacitor are respectively connected to the at least a load unit, and the at least a switch is connected to the load unit for controlling its turning-on and turning-off, wherein the boost circuit and the load unit share the at least a switch.
US08030851B2	Switchable induction light A light fitting is provided with a first connector piece arranged to support a light and provide power thereto, an input connected to a power source and arranged to provide power permanently to an output comprising a primary coil, and a transmitter operable to transmit a switch signal. A light is provided comprising a sealed light housing, a light source, a back-up battery, a controller and a second connector piece having a secondary coil and a receiver. The receiver receives the switch signal and the controller controls power delivery to the light source in response to the switch signal received by the receiver thereby to turn the light on and off. The light fitting and the light are arranged to present the primary coil and the secondary coil for inductive coupling therebetween and to present the transmitter and the receiver for wireless communication therebetween.
US08030847B2	Low power discharge lamp with high efficacy In order to achieve a discharge lamp suited to operate under reduced nominal power of e.g. 20-30 W, a lamp is proposed with two electrodes (24) arranged at a distance in a discharge vessel (20, 120) for generating an arc discharge. The discharge vessel (20, 120) has a filling with a substantially free of mercury and comprises a metal halide and a rare gas. The lamp (10, 110) further comprises an outer bulb (18) arranged around the discharge vessel at a distance (d2). The outer bulb (18) is sealed and has a gas filling of a thermal conductivity (λ). The inner diameter (d1) of the discharge vessel is preferably in a range from 2-2.7 mm. The wall thickness (w1) is in a range from 1.4-2 mm. A heat transition coefficient (λ/d2) is calculated as thermal conductivity (λ) at 800° C. of the outer bulb filling divided by the distance (d2). The so-defined heat 10 transition coefficient is below 150 W/(m2K).
US08030836B2	Illuminator for photodynamic therapy An apparatus and method for photodynamic therapy or photodynamic diagnosis using an illuminator comprising a plurality of light sources generally conforming to a contoured surface and irradiating the contoured surface with substantially uniform intensity visible light. The light sources may comprise generally U-shaped fluorescent tubes that are driven by electronic ballasts. Adjustment of the ballast voltage controls the output power of the tubes. The tubes are supported by a sheet-metal or plastic housing and are covered by a polycarbonate shield which directs cooling airflow within the unit and prevents glass-patient contact in the vent of tube breakage. An aluminum reflector located behind the tubes increases both the output irradiance and the uniformity of the output distribution. The spacing of the U-shaped tubes is varied to increase the output at the edges of the illuminator to make the output more uniform. Also, different portions of the tubes are cooled at different amounts, to improve uniformity. A light sensor monitors output from the U-shaped tubes to provide a signal for adjusting the output from the tubes.
US08030831B1	High thread spark plug with undercut insulator A spark plug for an internal combustion engine, the spark plug having an elongated center electrode having a center electrode tip at one end and a terminal proximate to another end of the center electrode; an insulator surrounding a portion of the center electrode, the insulator having a channel formed in an exterior surface of the insulator; and a jamb nut surrounding the insulator, the jamb nut being aligned with the channel such that a distal end of the jamb nut does not contact the insulator.
US08030830B2	Iridium alloy for spark plug electrodes A spark plug comprises a shell having a substantially cylindrical threaded portion for threadable engagement in a cylinder head of an internal combustion engine, an insulator disposed coaxially in the shell, a center electrode disposed coaxially in the insulator, a side ground electrode having a first end coupled to the shell and a second end facing an end of the center electrode to define a spark discharge gap therebetween, and an electrode tip portion secured to either the side ground electrode or the center electrode proximate the spark discharge gap. The tip portion is formed from an alloy comprising from about 60 to about 70 percent by weight iridium, from about 30 to about 35 percent by weight rhodium, from 0 to about 10 percent by weight nickel, from about 3500 to about 4500 parts per million tantalum, and from about 100 to about 200 parts per million zirconium.
US08030828B2	Piezoelectric device, process for producing the piezoelectric device, and liquid discharge device A piezoelectric device includes a piezoelectric film, and electrodes through which an electric field can be applied to the piezoelectric film along the thickness direction of the piezoelectric film. The piezoelectric film contains a ferroelectric phase in which the thickness direction and a normal of a plane determined by the spontaneous-polarization axis and the axis makes an angle θm satisfying the condition that −45 degrees<θm<+45 degrees and θm≠0 degrees. Further, the spontaneous-polarization axis or the axis may be perpendicular to the thickness direction of the piezoelectric film.
US08030824B2	Wide bandwidth matrix transducer with polyethylene third matching layer A third matching layer (140) affording wide bandwidth for an ultrasound matrix probe is made of polyethylene, and may extend downwardly to surround the array (S360) and attach to the housing to seal the array (S370).
US08030811B2	Stator and gap winding motor using the same A so-called gap winding motor capable of preventing a rotation detector from being affected by noise generated by a stator coil connection portion and decreasing the size and cost is provided. The gap winding motor comprises a stator including a stator core, a plurality of stator coils arranged on an inner peripheral surface of the stator core, a ring-shaped coil connection board configured to connect the plurality of stator coils, and ring-shaped shield patterns provided at both surfaces of the ring-shaped coil connection board. The stator core, the coil connection board, and the shield patterns are encapsulated with resin, and a rotation detector mounting printed circuit board is arranged in a gap located at an inner side of the stator core.
US08030807B2	Electromechanical energy harvesting system An ambient energy harvesting system, and method of use thereof, includes a magnetic flux-generating assembly (28), a coil (30) positioned adjacent to the magnetic flux-generating assembly (28), and a cantilevered arm (24). Vibration of the cantilevered arm (24) enables relative movement between the magnetic flux-generating assembly (28) and the coil (30) to generate an electric current in the coil (30). An effective flexible length (L) of the cantilevered arm (24) is selected such that applied kinetic energy causes the cantilevered arm (24) to vibrate at approximately its resonant frequency.
US08030802B2	Uninterruptible power supply for a medical appliance An apparatus for metered supply of a liquid medicament having a power supply which not only allows the primary battery to be replaced without interrupting the insulin supply, but also makes it possible to bridge uncontrolled short-term interruptions in the current supply or voltage supply resulting from bouncing of the battery contacts, while also providing an adequate emergency power reserve is disclosed.
US08030800B1	Integrated power sources for mobile electronic devices A mobile electronic device comprises at least one electronic component, at least one mobile power source, and at least one integrated power source. The at least one mobile power source is operable to supply power to the at least one electronic component. The at least one integrated power source is operable to supply power to at least a portion of the at least one electronic component to maintain operation of the portion of the at least one electronic component while a voltage level of the power supplied by the at least one mobile power source is below a threshold and the mobile electronic device does not receive power from an external power source.
US08030796B2	System and method for controlling current in a movable barrier operator A barrier operator comprises a current limit portion and a barrier operator portion. The current limit portion is coupled to a mains supply and the barrier operator position is coupled to the mains supply and the current limit portion. The barrier operator portion actuates a movable barrier. The current limit portion regulates electrical current to at least one additional device.
US08030794B2	Device for capturing energy from a fluid flow A device (10) for capturing energy from a fluid flow is disclosed. The device (10) comprises a base (12) adapted for stationary mounting relative to the fluid flow. A member (20), having a longitudinal axis (21), is movably connected relative to the base (12) and is adapted to move relative to the base (12) towards a position in which the longitudinal axis (21) generally aligns with a vertical plane parallel to the direction of the fluid flow passing the member (20). A lift generating element (26) is connected to the member (20) and is movable relative to the direction of the fluid flow to vary a direction of lift produced by the lift generating element (26) as fluid flows therearound. The lift generated by the lift generating element (26) drives the member (20) in oscillatory motion relative to the base (12). An energy transfer mechanism is attached to the member (20) and is adapted to be driven by the oscillation of the member (20).
US08030793B2	Power generation A power generating system 10 includes a drive arrangement 12 and a compressor 18 arranged to be driven by the drive arrangement 12 to compress gas, in particular air. The system 10 also includes an underwater storage arrangement 20 for storing compressed gas provided by the compressor 18 and an expander 22 for expanding compressed gas from the underwater storage arrangement 20 and/or the compressor 18 to thereby drive a generator 16 to generate electrical power.
US08030792B2	Vertical axis wind turbine system Wind turbine system. The system includes a lower wind speed vertical axis wind turbine operatively connected to a first electrical motor/generator and a higher wind speed vertical axis wind turbine operatively connected to at least one second electrical motor/generator. Electrical power from the first electrical motor/generator is directed to the at least one second electrical motor/generator and mag-lev system to cause the higher wind speed turbine to begin turning.
US08030790B2	Hybrid water pressure energy accumulating wind turbine and method A hybrid water pressure energy accumulating, wind turbine tower assembly used to directly propel water pumps to raise water from low elevation reservoir(s) to high elevation reservoir(s) where it is used as a potential energy. The wind tower assembly includes a wind turbine having propeller with a rotor, a generator driven by the rotor and a yaw assembly attached to a tower with a foundation. The tower includes in-tower storage reservoirs configured for storing water. The in-tower storage reservoirs could be defined by lower and upper water storage containers attached to the inner or outer surface of the tower that might be connected to other neighboring reservoir(s). The wind turbine may be of the vertical or horizontal-axis type and may be installed inside a residential or commercial building. The lifted water is used to generate electricity utilizing a hydropower generator.
US08030788B2	Method and systems for an engine starter/generator A method and system for an engine starter/generator is provided. The starter/generator system includes a three phase squirrel cage induction machine, a three phase inverter/converter electrically coupled to the three phase squirrel cage induction machine. The starter/generator system also includes a bidirectional DC-DC converter electrically coupled to the three phase inverter/converter, and a digital control board configured to sensorlessly determine a rotor angle from a plurality of phase currents to the induction machine during a start mode. During the start mode, logic in the digital control board configures the starter/generator system into a combination of an induction motor, a three phase DC-AC inverter, and a DC-DC boost converter, and during a generate mode, the logic in the digital control board configures the starter/generator system into a combination of an induction generator, a three phase AC-DC converter, and a DC-DC buck converter.
US08030786B2	System for generating electrical energy from ambient energy A system for generating electrical energy from ambient energy such as the energy of ambient motion and acoustic vibrations. The system has at least two stages, a resonating electrical generator and a kinetic energy conversion system. The stages have differing resonant frequencies to enable harvesting energy from lower frequency ambient motion and converting the energy to higher frequency resonant oscillation for efficiently generating electrical energy. A multiaxial system having a plurality of systems for generating electrical energy from ambient motion each oriented to be responsive to motion along a different axis. An embodiment of a system for generating electrical energy from ambient motion for which the resonating electrical generator is at least part of a driving mass of the kinetic energy conversion system.
US08030783B2	Integrated circuit package with open substrate A method of manufacturing an integrated circuit package includes: forming a substrate that includes: forming a core layer, forming vias in the core layer, and forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the predetermined thickness in the vias; and forming connections between an integrated circuit die and the conductive layer.
US08030782B2	Metal-metal bonding of compliant interconnect Embodiments of the invention provide a first component with a compliant interconnect bonded to a second component with a land pad by a metal to metal bond. In some embodiments, the first component may be a microprocessor die and the second component a package substrate.
US08030777B1	Protection of Cu damascene interconnects by formation of a self-aligned buffer layer Methods of protecting exposed metal damascene interconnect surfaces in a process for making electronic components and the electronic components made according to such methods. An integrated circuit structure having damascene regions with exposed metal surfaces is provided into a closed processing chamber, whereby a first reactant is contacted to the exposed metal surfaces to transform a top portion of the metal layer into a protective self-aligned buffer layer. Reacting molecules of the first reactant with metal atoms of this metal layer forms the protective self-aligned buffer layer entirely within such metal layer. Alternatively, adsorbing surface-active reactant molecules onto the exposed metal surface forms the protective self-aligned buffer layer. A second reactant may be contacted to the protective self-aligned buffer layer to form a self-aligned dielectric cap layer directly over the protective self-aligned buffer layer.
US08030768B2	Semiconductor package with under bump metallization aligned with open vias A semiconductor package with a semiconductor chip having under bump metallizations (UBMs) on a first surface and a substrate having open vias. The substrate is attached to the semiconductor chip with the UBMs in alignment with the open vias. An encapsulant surrounds the semiconductor chip and the substrate and a conductor fills the open vias to form external package connections.
US08030767B2	Bump structure with annular support A bump structure with an annular support suitable for being disposed on a substrate is provided. The substrate has at least one pad and a passivation layer that has at least one opening exposing a portion of the pad. The bump structure with the annular support includes an under ball metal (UBM) layer, a bump, and an annular support. The UBM layer is disposed on the passivation layer and covers the pad exposed by the passivation layer. The bump is disposed on the UBM layer over the pad, and a diameter of a lower surface of the bump is less than the diameter of an upper surface thereof. The annular support surrounds and contacts the bump, and a material of the annular support is photoresist. An under cut effect is not apt to happen on the bump structure.
US08030766B2	Semiconductor device A semiconductor device that can cope with larger numbers of pins and finer pitches while suppressing lowering of the manufacturing yield and reliability includes: a semiconductor chip having a plurality of electrodes provided on an upper surface thereof; a plurality of lead terminals including inner lead portions disposed toward the semiconductor chip; a sheet-form wiring member having a plurality of conductors insulated from one another on one main surface thereof; and a sealing-resin layer for sealing at least the semiconductor chip, the inner lead portions and the wiring member. The electrodes of the semiconductor device and the inner lead portions of the lead terminals are electrically connected respectively to each other via the conductors of the wiring member.
US08030762B2	Light emitting diode package having anodized insulation layer and fabrication method therefor An LED package having an anodized insulation layer which increases heat radiation effect to prolong the lifetime LEDs and maintains high luminance and high output, and a method therefor. The LED package includes an Al substrate having a reflecting region and a light source mounted on the substrate and connected to patterned electrodes. The package also includes an anodized insulation layer formed between the patterned electrodes and the substrate and a lens covering over the light source of the substrate. The Al substrate provides superior heat radiation effect of the LED, thereby significantly increasing the lifetime and light emission efficiency of the LED.
US08030761B2	Mold design and semiconductor package A chip package includes a carrier having a first and a second major surface. The first major surface includes an active region surrounded by an inactive region. The chip package includes contact pads in the active region for mating with chip contacts of a chip. A support structure is disposed on the inactive region of the first major surface. The support structure forms a dam that surrounds the active region. When a chip or chip stack is mounted in the active region, spacing exists between the dam and the chip or chip stack. The spacing creates convention paths for heat dissipation.
US08030755B2	Integrated circuit package system with a heat sink An integrated circuit package system is provided forming a substrate having an integrated circuit die thereon, thermally connecting a heat slug and a resilient thermal structure to the integrated circuit die, and encapsulating the resilient thermal structure.
US08030753B2	Semiconductor device and method for making the same A semiconductor device includes a semiconductor element, an electrode formed on the semiconductor element, and a protective member covering the semiconductor element. The protective member is formed with a through-hole facing the electrode. In the through-hole, a wiring pattern is formed to be electrically connected to the electrode.
US08030748B2	Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second microelectronic die is attached to the first die on one side, and to a second substrate on the other side. Electrical connections are made between the first die and the first substrate, between the second die and the second substrate, and between the first and second substrates, e.g., via wire bonding. The electrical connecting elements are advantageously encased in a molding compound. Exposed contacts on the first and/or second substrates, not covered by the molding compound, provide for electrical connections between the package, and another package stacked onto the package. The package may avoid coplanarity factors, can be manufactured using existing equipment, allows for intermediate testing, and can also offer a thinner package height.
US08030745B2	ID chip and IC card The present invention provides an ID chip or an IC card in which the mechanical strength of an integrated circuit can be enhanced without suppressing a circuit scale. An ID chip or an IC card of the present invention has an integrated circuit in which a TFT (a thin film transistor) is formed from an insulated thin semiconductor film. Further, an ID chip or an IC card of the present invention has a light-emitting element and a light-receiving element each using a non-single-crystal thin film for a layer conducting photoelectric conversion. Such a light-emitting element or a light-receiving element may be formed consecutively to (integrally with) an integrated circuit or may be formed separately and attached to an integrated circuit.
US08030744B2	Arrangement for electrically connecting semiconductor circuit arrangements to an external contact device and method for producing the same An electrical connection arrangement between a semiconductor circuit arrangement and an external contact device, and to a method for producing the connection arrangement is disclosed. In one embodiment, a metallic layer is deposited onto at least one contact terminal and/or the contacts and the wire, the metallic layer protecting the contact terminal or the electrical connection against ambient influences and ensuring a high reliability.
US08030740B2	Deposited semiconductor structure to minimize N-type dopant diffusion and method of making A microelectronic structure including a layerstack is provided, the layerstack including: (a) a first layer including semiconductor material that is very heavily n-doped before being annealed, having a first-layer before-anneal dopant concentration, the first layer being between about 50 and 200 angstroms thick, wherein the first layer is above a substrate, and wherein the first layer is heavily n-doped after being annealed, having a first-layer after-anneal dopant concentration, the first-layer before-anneal dopant concentration exceeding the first-layer after-anneal concentration; (b) a second layer including semiconductor material that is not heavily doped before being annealed, having a second-layer before-anneal dopant concentration, the second layer being about as thick as the first layer, wherein the second layer is above and in contact with the first layer, and wherein the second layer includes heavily n-doped semiconductor material after being annealed, having a second-layer after-anneal dopant concentration, the second-layer after-anneal dopant concentration exceeding the second-layer before-anneal concentration; and (c) a third layer including semiconductor material that is above and in contact with the second layer and that is not heavily n-doped before or after being annealed, the third layer having a third-layer dopant concentration.
US08030737B2	Semiconductor device and method of manufacturing the same A semiconductor device including: a substrate; an insulating film formed over the substrate; a copper interconnect, having a plurality of hillocks formed over the surface thereof, buried in the insulating film; a first insulating interlayer formed over the insulating film and the copper interconnect; a second insulating interlayer formed over the first insulating interlayer; and an electroconductive layer formed over the second insulating interlayer, wherein the top surface of at least one hillock highest of all hillocks is brought into contact with the lower surface of the second insulating interlayer is provided.
US08030730B2	Semiconductor device and manufacturing method thereof An N-layer is formed on a semiconductor substrate, with a BOX layer interposed. In the N-layer, a trench isolation region is formed to surround the N-layer to be an element forming region. The trench isolation region is formed to reach the BOX layer, from the surface of the N-layer. Between trench isolation region and the N-layer, a P type diffusion region 10a is formed. The P type diffusion region is formed continuously without any interruption, to be in contact with the entire surface of an inner sidewall of the trench isolation region surrounding the element forming region. In the element forming region of the N-layer, a prescribed semiconductor element is formed. Thus, a semiconductor device is formed, in which electrical isolation is established reliably, without increasing the area occupied by the element forming region.
US08030729B2	Device for absorbing or emitting light and methods of making the same A device disclosed herein includes a first layer, a second layer, and a first plurality of nanowires established between the first layer and the second layer. The first plurality of nanowires is formed of a first semiconductor material. The device further includes a third layer, and a second plurality of nanowires established between the second and third layers. The second plurality of nanowires is formed of a second semiconductor material having a bandgap that is the same as or different from a bandgap of the first semiconductor material.
US08030728B2	Optical semiconductor device An optical semiconductor device includes a semiconductor substrate; a light receiving element formed on the semiconductor substrate; a light absorbing element formed on the semiconductor substrate and located adjacent to the light receiving element; and a semiconductor element formed on the semiconductor substrate and used for signal processing. The light absorbing element includes a fifth semiconductor layer, and a light absorption region in the light receiving element has a different structure from a light absorption region in the light absorbing element.
US08030727B2	Image sensor and method for manufacturing the same An image sensor includes a semiconductor substrate, an interconnection and an interlayer dielectric, an image sensing device, a trench, a buffer layer, a barrier pattern, a via hole, and a metal contact. The semiconductor substrate includes a readout circuitry. The interconnection and an interlayer dielectric layer are formed on and/or over the semiconductor substrate while the interconnection is connected to the readout circuitry. The image sensing device may be formed on and/or over the interlayer dielectric and a trench may be formed in the image sensing device, the trench corresponding to the interconnection. The buffer layer may be formed on a sidewall of the trench. The barrier pattern may be formed on the buffer layer with the via hole penetrating through the image sensing device and the interlayer dielectric under the barrier pattern and exposing the interconnection. The metal contact may be formed in the via hole.
US08030724B2	Solid-state imaging device and method for fabricating the same A solid-state imaging device comprises an imaging region, a peripheral circuit region formed in an outer peripheral portion of the imaging region, a first conductivity type semiconductor substrate having the imaging region and the peripheral circuit region on a main surface thereof, a second conductivity type first semiconductor layer formed in the semiconductor substrate, a first conductivity type second semiconductor layer formed in first semiconductor layer, a through electrode formed in a through hole penetrating through the semiconductor substrate in a thickness direction of the semiconductor substrate, and a pad portion formed on the semiconductor substrate and connected to the through electrode. The through hole penetrates through a first conductivity type region of the semiconductor substrate.
US08030723B2	Image sensor with decreased optical interference between adjacent pixels An image sensor with decreased optical interference between adjacent pixels is provided. An image sensor, which is divided into a pixel region and a peripheral region, the image sensor including a photodiode formed in a substrate in the pixel region, first to Mth metal lines formed over the substrate in the pixel region, where M is a natural number greater than approximately 1, first to Nth metal lines formed over a substrate in the peripheral region, where N is a natural number greater than M, at least one layer of dummy metal lines formed over the Mth metal lines but formed not to overlap with the photodiode, and a microlens formed over the one layer of the dummy metal lines to overlap with the photodiode.
US08030722B1	Reversible top/bottom MEMS package A semiconductor device has a base substrate having a plurality of metal traces and a plurality of base vias. An opening is formed through the base substrate. A cover substrate having a plurality of metal traces and a plurality of cover vias is provided. A first die is attached to the first surface of the substrate and positioned over the opening. Side members are coupled to ground planes on the base substrate and cover substrate to form an RF shield around the first die. At least one wirebond having a first end attached to the first die and a second end attached to a metal trace of the base substrate is provided. The at least one wirebond forms a loop wherein a top section of the loop contacts a metal trace of the cover substrate.
US08030721B2	Method to optimize substrate thickness for image sensor device Provided is a method for fabricating an image sensor device that includes providing a substrate having a front side and a back side; patterning a photoresist on the front side of the substrate to define an opening having a first width, the photoresist having a first thickness correlated to the first width; performing an implantation process through the opening using an implantation energy correlated to the first thickness thereby forming a first doped isolation feature; forming a light sensing feature adjacent to the first doped isolation feature, the light sensing feature having a second width; and thinning the substrate from the back side so that the substrate has a second thickness that does not exceed twice a depth of the first doped isolation feature. A pixel size is substantially equal to the first and second widths.
US08030719B2	Thermal sensing and reset protection for an integrated circuit chip There is provided a semiconductor package that includes a first semiconductor die mounted on a package substrate. The semiconductor package further includes a second semiconductor die mounted on the first semiconductor die and including a thermal sensing and reset protection circuit. The thermal sensing and reset protection circuit is configured to determine a temperature of the first semiconductor die and to provide a reset protection signal to the first semiconductor die when the temperature of the first semiconductor die is substantially equal to a preset temperature so as to protect the first semiconductor die from thermal runaway. The reset protection signal can cause the first semiconductor die to be in a sleep mode or a reset state.
US08030717B2	Semiconductor device A disclosed semiconductor device includes a gate insulation film formed on a silicon substrate and a metal gate electrode formed in the gate insulation film, wherein the gate insulation film includes a first insulation film, a second insulation film that is formed on the first insulation film and has a greater dielectric constant than the first insulation film, and a third insulation film formed on the second insulation film.
US08030715B2	Semiconductor device with a gate having a bulbous area and a flattened area underneath the bulbous area and method for manufacturing the same A semiconductor device with a gate having a bulbous area and a flattened area underneath the bulbous are is presented. The semiconductor device includes a semiconductor substrate, an isolation layer, a gate insulation layer, and gates. The semiconductor substrate has recess parts that have first grooves which have bulbous-shaped profiles and second vertically flattened profile grooves which extend downward from the first grooves. The gates are formed in the recess parts in which the gate insulation layer is double layered in the bulbous profile areas and is single layered in the flattened profile areas.
US08030712B2	Method for manufacturing high-stability resistors, such as high ohmic poly resistors, integrated on a semiconductor substrate A method for protecting a circuit component on a semiconductor substrate from a plasma etching or other removal process includes forming a screening layer over an auxiliary layer to conceal at least an area of the auxiliary layer that overlays at least a portion of the circuit component, such as for example a high-ohmic poly resistor. The method transfers a pattern defined by a mask onto the screening layer by selectively removing portions of the screening layer in accordance with the pattern. Portions of the auxiliary layer that are not protected by the screening layer are removed using a plasma gas selective to the auxiliary layer material, without removing the area of the auxiliary layer that overlays the portion of the circuit component, thereby protecting the circuit component from the plasma gas via the screening layer and auxiliary layer.
US08030710B2	Strained semiconductor device A semiconductor device having: a semiconductor substrate; an isolation trench formed in a surface portion of the semiconductor substrate and defining an NMOSFET active region and a PMOSFET active region; a silicon oxide film burying only a lower portion of the isolation trench and defining a recess above the lower portion; an NMOSFET structure formed in the NMOSFET active region and having an insulated gate electrode structure and n-type source/drain regions; a PMOSFET structure formed in the PMOSFET active region and having an insulated gate electrode structure and p-type source/drain regions; a tensile stress film covering the NMOSFET structure and extending to the recess surrounding the NMOSFET active region and to the recess outside the PMOSFET active region along a gate width direction; and a compressive stress film covering the PMOSFET structure and extending to the recess outside the PMOSFET active region along a channel length direction.
US08030709B2	Metal gate stack and semiconductor gate stack for CMOS devices A semiconductor gate stack comprising a silicon oxide based gate dielectric and a doped semiconductor material is formed on a semiconductor substrate. A high-k material metal gate electrode comprising a high-k gate dielectric and a metal gate portion is also formed on the semiconductor substrate. Oxygen-impermeable dielectric spacers are formed on the sidewalls of the semiconductor gate stack and the high-k material metal gate stack. The oxygen-impermeable dielectric spacer on the semiconductor gate stack is removed, while the oxygen impermeable dielectric spacer on the high-k material metal gate electrode is preserved. A low-k dielectric spacer is formed on the semiconductor gate stack, which provides a low parasitic capacitance for the device employing the semiconductor gate stack.
US08030706B2	Power semiconductor device A semiconductor device according to an embodiment of the present invention includes a device part and a terminal part. The device includes a first semiconductor layer, and second and third semiconductor layers formed on the first semiconductor layer, and alternately arranged along a direction parallel to a surface of the first semiconductor layer, wherein the device part is provided with a first region and a second region, each of which includes at least one of the second semiconductor layers and at least one of the third semiconductor layers, and with regard to a difference value ΔN (=NA−NB) obtained by subtracting an impurity amount NB per unit length of each of the third semiconductor layers from an impurity amount NA per unit length of each of the second semiconductor layers, a difference value ΔNC1 which is the difference value ΔN in the first region of the device part, a difference value ΔNC2 which is the difference value ΔN in the second region of the device part, and a difference value ΔNT which is the difference value ΔN in the terminal part satisfy a relationship of ΔNC1>ΔNT>ΔNC2.
US08030703B2	Field-effect transistor and method for manufacturing a field-effect transistor A field-effect transistor and a method for manufacturing a field-effect transistor is disclosed. One embodiment includes a substrate having a surface along which a trench is implemented, wherein the trench has a trench bottom and a trench edge. A source area is implemented at the trench edge and a gate electrode at least partially implemented in the trench and separated from the substrate by an insulation layer. The field-effect transistor includes a drain electrode at a side of the substrate facing away from the surface. An additional electrode is implemented between the gate electrode and the trench bottom and electrically insulated from the substrate and an electrical connection between the additional electrode and the gate electrode, wherein the electrical connection has a predetermined ohmic resistance value.
US08030697B2	Cell structure of semiconductor device having an active region with a concave portion A cell structure of a semiconductor device includes an active region, having a concave portion, and an inactive region that defines the active region. A gate pattern in the active region is arranged perpendicular to the active region. A landing pad on the active region and the inactive region contacts the active region. A bit line pattern on the inactive region intersects the gate pattern perpendicularly, the bit line pattern being electrically connected to the landing pad and having a first protrusion corresponding to the concave portion of the active region.
US08030696B2	Thin film transistor substrate, defect repairing method therefor, and display device A thin film transistor substrate includes: a substrate; a thin film transistor and a capacitor formed on the substrate; and a protective film for protecting an electrode on a back surface side of the capacitor when an electrode on a front surface side of the capacitor is cut by irradiation with laser light, the protective film being disposed at such a position as to enclose a corner part of the electrode on the front surface side between the electrode on the front surface side and the electrode on the back surface side of the capacitor.
US08030695B2	Structure and manufacturing method of semiconductor memory device A semiconductor memory device having a cross point structure includes a plurality of upper electrodes arranged to extend in one direction, and a plurality of lower electrodes arranged to extend in another direction at a right angle to the one direction of the upper electrodes. Memory materials are provided between the upper electrodes and the lower electrodes for storage of data. The memory materials are made of a perovskite material and arranged at the lower electrodes side of the corresponding upper electrode extending along the corresponding upper electrode.
US08030694B2	Dielectric film and semiconductor device using dielectric film including hafnium, aluminum or silicon, nitrogen, and oxygen The present invention provides a dielectric film having a high permittivity and a high heat resistance. An embodiment of the present invention is a dielectric film (103) including a composite oxynitride containing an element A made of Hf, an element B made of Al or Si, and N and O, wherein mole fractions of the element A, the element B, and N expressed as B/(A+B+N) range from 0.015 to 0.095 and N/(A+B+N) equals or exceeds 0.045, and has a crystalline structure.
US08030689B2	Integrated circuit device and associated layout including separated diffusion regions of different type each having four gate electrodes with each of two complementary gate electrode pairs formed from respective linear conductive segment A semiconductor device includes a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. Each of the conductive features within the gate electrode level region has a width less than a wavelength of light used in a photolithography process to fabricate the conductive features. Conductive features within the gate electrode level region form respective PMOS transistor devices and respective NMOS transistor devices. A total number of the PMOS transistor devices and the NMOS transistor devices in the gate electrode level region is greater than or equal to eight.
US08030688B2	Ohmic metal contact protection using an encapsulation layer A method for fabricating a semiconductor device which protects the ohmic metal contacts and the channel of the device during subsequent high temperature processing steps is explained. An encapsulation layer is used to cover the channel and ohmic metal contacts. The present invention provides a substrate on which a plurality of semiconductor layers are deposited. The semiconductor layers act as the channel of the device. The semiconductor layers are covered with an encapsulation layer. A portion of the encapsulation layer and the plurality of semiconductor layers are removed, wherein ohmic metal contacts are deposited. The ohmic metal contacts are then annealed to help reduce their resistance. The encapsulation layer ensures that the ohmic metal contacts do not migrate during the annealing step and that the channel is not harmed by the high temperatures needed during the annealing step.
US08030683B2	Protection circuit A protection circuit according to an embodiment of the present invention is provided between a first terminal and a second terminal and includes: a capacitor element having one end connected to the second terminal; and a multi-cathode thyristor formed on a semiconductor substrate, and including an anode connected to the first terminal, a first cathode connected to the second terminal, and a second cathode disposed between the anode and the first cathode and connected to another terminal of the capacitor element.
US08030682B2	Zinc-blende nitride semiconductor free-standing substrate, method for fabricating same, and light-emitting device employing same A zinc-blende nitride semiconductor free-standing substrate has a front surface and a back surface opposite the front surface. The distance between the front and back surfaces is not less than 200 μm. The area ratio of the zinc-blende nitride semiconductor to the front surface is not less than 95%.
US08030679B2	Nitride semiconductor light emitting device and fabrication method therefor Disclosed is a nitride semiconductor light emitting device including: one or more AllnN layers; an In-doped nitride semiconductor layer formed above the AllN layers; a first electrode contact layer formed above the In-doped nitride semiconductor layer; an active layer formed above the first electrode contact layer; and a p-type nitride semiconductor layer formed above the active layer. According to the nitride semiconductor light emitting device, a crystal defect of the active layer is suppressed, so that the reliability of the nitride semiconductor light emitting device is increased and the light output is enhanced.
US08030674B2	Light-emitting diode package with roughened surface portions of the lead-frame An LED package including a lead-frame, at least an LED chip and an encapsulant is provided. The lead-frame has a roughened surface, the LED chip is disposed on the lead-frame and electrically connected to the lead-frame, and the roughened surface is suitable to scatter the light emitted from the LED chip. In addition, the encapsulant encapsulates the LED chip and a part of the lead-frame, and the rest part of the lead-frame is exposed out of the encapsulant.
US08030673B2	Nitride semiconductor light emitting element Provided is a nitride semiconductor light emitting element capable of producing an emission spectrum having two peaks with stable ratio of emission peak intensity. The nitride semiconductor light emitting 1 comprises an active layer 12 disposed between an n-type nitride semiconductor layer 11 and a p-type nitride semiconductor layer 13. The active layer 12 comprises a first well layer 14, second well layers 15 interposing the first well layer 14 and disposed at outermost sides among the well layers, and barrier layers 16, 17 disposed between each of the well layers. The second well layer 15 comprises a nitride semiconductor having a larger band gap energy than the band gap energy of a nitride semiconductor constituting the first well layer 14, and the nitride semiconductor light emitting element 1 has peaks in the emission spectrum respectively corresponding to the first well layer 14 and the second well layer 15.
US08030670B2	Multi-chip package for LED chip and multi-chip package LED device including the multi-chip package Provided is a multi-chip package light emitting diode (LED) device including a plurality of LED chips within a single package. The LED device may include a base substrate, a multi-chip package for a LED on the base substrate, and a light radiator surrounding the multi-chip package and radiating light emitted by the multi-chip package for a LED, wherein the multi-chip package for a LED may include a plurality of LED chips on a single wafer substrate.
US08030668B2	Semiconductor LED, opto-electronic integrated circuits (OEIC), and method of fabricating OEIC A light emitting diode demonstrating high luminescence efficiency and comprising a Group IV semiconductor such as silicon or germanium equivalent thereto as a basic component formed on a silicon substrate by a prior art silicon process, and a fabricating method of waveguide thereof are provided. The light emitting diode of the invention comprises a first electrode for implanting electrons, a second electrode for implanting holes, and a light emitting section electrically connected to the first and the second electrode, wherein the light emitting section is made out of single crystalline silicon and has a first surface and a second surface facing the first surface, wherein with respect to plane orientation (100) of the first and second surfaces, the light emitting section crossing at right angles to the first and second surfaces is made thinner, and wherein a material having a high refractive index is arranged around the thin film section.
US08030667B2	Nitride semiconductor light emitting diode A nitride semiconductor light emitting diode (LED) comprises an n-type nitride semiconductor layer; an electron emitting layer formed on the n-type nitride semiconductor layer, the electron emitting layer being composed of a nitride semiconductor layer including a transition element of group III; an active layer formed on the electron emitting layer; and a p-type nitride semiconductor layer formed on the active layer.
US08030666B2	Group-III nitride epitaxial layer on silicon substrate A semiconductor device includes a silicon substrate; silicon faceted structures formed on a top surface of the silicon substrate; and a group-III nitride layer over the silicon faceted structures. The silicon faceted structures are separated from each other, and have a repeated pattern.
US08030662B2	Semiconductor memory device There is offered a switching resistance RAM that is very much reduced in an occupied area and is highly integrated. Memory cells CEL11-CEL14 are formed corresponding to four intersections of word lines WL0 and WL1 and bit lines BL0 and BL1. Each of the memory cells CEL11-CEL14 are composed of a switching layer 13 formed on a surface of an N+ type Si layer 11. The switching layer 13 is electrically connected to the bit line BL0 or BL1 thereabove through an electrode 14. The switching layer 13 is composed of a SiC layer 13A stacked on the surface of the N+ type Si layer 11 and a Si oxide layer 13B stacked on the SiC layer 13A. A top surface of the Si oxide layer 13B, that is the uppermost layer of the switching layer 13, is electrically connected to the corresponding bit line BL0 or BL1.
US08030654B2	Thin film transistor and method of manufacturing the same A thin film transistor comprising a gate electrode, a gate insulating layer, an active layer, and source and drain electrodes is provided. The gate electrode overlaps with a channel region of the active layer, the gate insulating layer is provided between the gate electrode and the active layer, the source and drain electrodes overlap a source region and a drain region of the active layer, respectively, and a thin film of SiNx or SiOxNy through which electrons are allowed to tunnel is provided between the active layer and the source and drain electrodes.
US08030651B2	Micro electro mechanical device and manufacturing method thereof To manufacture a micro structure and an electric circuit included in a micro electro mechanical device over the same insulating surface in the same step. In the micro electro mechanical device, an electric circuit including a transistor and a micro structure are integrated over a substrate having an insulating surface. The micro structure includes a structural layer having the same stacked-layer structure as a layered product of a gate insulating layer of the transistor and a semiconductor layer provided over the gate insulating layer. That is, the structural layer includes a layer formed of the same insulating film as the gate insulating layer and a layer formed of the same semiconductor film as the semiconductor layer of the transistor. Further, the micro structure is manufactured by using each of conductive layers used for a gate electrode, a source electrode, and a drain electrode of the transistor as a sacrificial layer.
US08030648B2	Organic thin film transistor and organic thin film transistor manufacturing process Disclosed is a stable organic thin film transistor having good switching property and a process for manufacturing an organic thin film transistor by a simple method. The organic thin film transistor comprises a substrate and provided thereon, at least a source electrode, a drain electrode, an organic semiconductor connecting the source electrode and the drain electrode, a gate electrode, and an insulating layer composed of a plurality of layers, the insulating layer being provided between the gate electrode and the organic semiconductor, wherein the organic thin film transistor comprises a mercapto group-containing compound represented by the following formula (I), (R)n—Si(A)3-n-(B) Formula (I) wherein R represents an alkyl group having a carbon atom number of not more than 8; A represents an alkoxy group or a halogen atom; B represents a substituent containing an SH group; and n is an integer of from 0 to 2.
US08030645B2	Electronic device, process for producing the same and electronic equipment making use thereof An electronic device of the present invention includes at least one electrode (Au electrode 65) and an organic molecule layer (semiconductor layer 14) formed adjacent to the electrode, and in which charge transfers between the layer and the electrode. The organic molecule layer includes a plurality of first organic molecules containing a conjugated π electron that composes a π conjugate plane (64). A plurality of second organic molecules is bonded chemically to a surface of the electrode at an interface between the electrode and the organic molecule layer. The second organic molecule contains a conjugated π electron that composes a π conjugate plane (67a). The second organic molecule is a molecule having a structure in which the π conjugate plane (67a) and the surface of the electrode form an angle within a predetermined range when the second organic molecule is bonded chemically to the surface of the electrode.
US08030642B2	Organic thin film transistor, method of manufacturing the same, and flat panel display having the same Provided are an organic TFT, a method of manufacturing the same, and a flat panel display having the same. The organic TFT includes source and drain electrodes formed on the surface of a substrate, an organic semiconductor layer that includes source and drain regions and a channel region, located on the source and drain electrodes, a gate electrode located above the organic semiconductor layer, and a first insulating layer located on the surface of the organic semiconductor layer, wherein a through hole is formed in at least a portion of the organic semiconductor layer and the first insulating layer, outside an active region that includes the source and drain regions and the channel region.
US08030640B2	Nitride semiconductor light emitting device and method of manufacturing the same A nitride semiconductor light emitting device includes a substrate, a first conductivity type nitride semiconductor layer disposed on the substrate and including a plurality of V-pits placed in a top surface thereof, a silicon compound formed in the vertex region of each of the V-pits, an active layer disposed on the first conductivity type nitride semiconductor layer and including depressions conforming to the shape of the plurality of V-pits, and a second conductivity type nitride semiconductor layer disposed on the active layer. The nitride semiconductor light emitting device, when receiving static electricity achieves high resistance to electrostatic discharge (ESD) since current is concentrated in the V-pits and the silicon compound placed on dislocations caused by lattice defects.
US08030638B2	Quasi single crystal nitride semiconductor layer grown over polycrystalline SiC substrate A compound semiconductor device is manufactured by using a polycrystalline SiC substrate, the compound semiconductor device having a buffer layer being formed on the substrate and having a high thermal conductivity of SiC and aligned orientations of crystal axes. The method for manufacturing the compound semiconductor device includes: forming a mask pattern on a polycrystalline SiC substrate, the mask pattern having an opening of a stripe shape defined by opposing parallel sides or a hexagonal shape having an apex angle of 120 degrees and exposing the surface of the polycrystalline SiC substrate in the opening; growing a nitride semiconductor buffer layer, starting growing on the polycrystalline SiC substrate exposed in the opening of the mask pattern, burying the mask pattern, and having a flat surface; and growing a GaN series compound semiconductor layer on the nitride semiconductor buffer layer.
US08030634B2	Memory array with diode driver and method for fabricating the same A memory array with self-centered diode access devices results from a process in which diodes are formed in the fill material, each diode having a lightly-doped first layer of the same conductivity type as the conductive lines; a heavily doped second layer of opposite conductivity type; and a conductive cap. Self-aligned, and self-centered spacers in the self-aligned vias define pores that expose the conductive cap. Memory material is deposited within the pores, the memory material making contact with the conductive cap. A top electrode is formed in contact with the memory material.
US08030626B2	Apparatus and method for charged-particle beam writing An average write speed M is calculated by averaging write speeds for blocks of a tentative block size La, and write speed variation σ of the blocks with respect to the average write speed M is calculated (Step S12). A maximum speed Vmax is calculated by accelerating and then decelerating (or decelerating and then accelerating) a stage when moving the stage by the width of one of the blocks of the tentative block size La (Step S13). When the relationship “Vmax−M≧σ” does not hold, the tentative block size La is increased (Step S15). When the relationship “Vmax−M≧σ” holds, the tentative block size La is set as an optimal block size Lb (Step S16).
US08030619B2	Radiation sensor array using conductive nanostructures A system may include a conductive substrate, a plurality of conductive nanostructures disposed on a first side of the conductive substrate, an insulating substrate, and a plurality of electrodes disposed on a first side of the insulating substrate. The first side of the conductive substrate faces the first side of the insulating substrate, and each of the plurality of electrodes is electrically connected to the conductive substrate. In other aspects, a system may include a first insulating substrate and a second insulating substrate, where a first side of the first insulating substrate faces a first side of the second insulating substrate, and each of a first plurality of electrodes is electrically connected to a respective one of a second plurality of electrodes.
US08030618B2	Pellet for use in spectrometry, method of preparing the same, and method of spectrometry A pellet 4 for use in spectrometry includes a first powder 41 of a light transmitting material in a compression-molded form, and a second powder 42 which is hydrophilic and water-insoluble and is dispersedly mixed in the first powder. A sample 40 to be subjected to spectrometry is e.g. in a powdery form and dispersedly mixed in the first and the second powders 41 and 42. When the sample 40 is a hydrate, the second powder 42 exerts the effect of accelerating dehydration of the sample 40, so that stable spectrum data on the sample in the dehydrated state is obtained early. This makes it possible to perform a processing such as identification of the sample 40 early and precisely.
US08030614B2	Charged particle beam apparatus and dimension measuring method There is provided a charged particle beam apparatus which allows implementation of a high-reliability and high-accuracy dimension measurement even if height differences exist on the surface of a sample. The charged particle beam apparatus includes the following configuration components: An acquisition unit for acquiring a plurality of SEM images whose focus widths are varied in correspondence with the focal depths, a determination unit for determining, from the plurality of SEM images acquired, a SEM image for which the image sharpness degree of the partial domain including a dimension-measuring domain becomes the maximum value, and a measurement unit for measuring the dimension of the predetermined domain from the SEM image whose image sharpness degree is the maximum value.
US08030612B2	High resolution excitation/isolation of ions in a low pressure linear ion trap Methods for improved separation of ions from an ion trap employing a combination of low pressure and low amplitude ion excitation, including methods for removing, from an ion trap ion population, ions having a m/z value neighboring that of an ion of interest, mass spectrometry methods providing improved resolution of ion detection, and programmable apparatus programmed with instructions therefor.
US08030611B2	Mass spectrometer, method of mass spectrometry and program for mass spectrometry An object of the present invention is to provide a mass spectrometer, a method of mass spectrometry, and a program for mass spectrometry for narrowing the range in which the mass-to-charge ratio is scanned without the ion peak of the fragment ion becoming out of the range. In order to achieve the above object, a mass spectrometer including a control unit, a display unit provided with an user interface, an ionization chamber, a dissociation chamber, a mass separator, and a detector is provided.
US08030610B2	Chemical noise reduction for mass spectrometry In various aspects, the present teachings provide systems and methods for reducing chemical noise in a mass spectrometry instrument that use a neutral chemical reagent and one or more mass filters to reduce interfering chemical background ion signals that are generated by ionization sources of mass spectrometers. In various embodiments, the neutral chemical reagent belongs to the class of organic chemical species containing a disulfide functionality.
US08030608B2	Backside illuminated imaging device, semiconductor substrate, imaging apparatus and method for manufacturing backside illuminated imaging device A backside illuminated imaging device performs imaging by illuminating light from a back side of a p substrate to generate electric charges in the substrate based on the light and reading out the electric charges from a front side of the substrate. The device includes n layers located in the substrate and on an identical plane near a front side surface of the substrate and accumulating the electric charges; n+ layers between the respective n layers and the front side of the substrate, the n+ layers having an exposed surface exposed on the front side surface of the substrate and functioning as overflow drains for discharging unnecessary electric charges accumulated in the n layers; p+ layers between the respective n+ layers and the n layers and functioning as overflow barriers of the overflow drains; and an electrode connected to the exposed surface of each of the n+ layers.
US08030607B2	Matrix of pixels provided with voltage regulators A matrix microelectronic device comprising: a plurality of cells arranged according to a matrix, one or several conductive lines provided to carry a given potential and to which respectively one or several cells of a row of cells of the matrix are linked, a plurality of voltage regulating elements, wherein said regulating elements are connected respectively between a cell of said plurality of cells and one of said conductive lines, said given potential serving as polarisation potential of said regulating elements, wherein said regulating elements are respectively provided to apply to said given cell a regulated polarisation potential.
US08030600B2	Method of manufacturing a hydrogen separation substrate The hydrogen permeable substrate includes a copper plate, a stainless steel plate, an insulating member, and hydrogen permeable metal. The hydrogen permeable substrate is formed by locating the insulating member between the stainless steel plate and a combined member formed by embedding the hydrogen permeable metal in through-holes made in the copper plate; subjecting the joining face of each component for joining to other components to irradiation with argon ions, to remove the oxide film thereon and activate the surface; and stacking and rolling the components. By so doing, they may be joined at low temperature and low pressure. Once joined, by cutting the hydrogen permeable metal into individual pieces along cut lines, a plurality of hydrogen permeable substrates may be manufactured all at once.
US08030599B2	Substrate processing apparatus, heating device, and semiconductor device manufacturing method Provided are a substrate processing apparatus, a heating device, and a semiconductor device manufacturing method. The substrate processing apparatus comprises a process chamber configured to process a substrate. A heating element is installed at a peripheral side of the process chamber. An annular inner wall is installed at a peripheral side of the heating element. An annular outer wall is installed at a peripheral side of the inner wall with a space being formed therebetween. An annular cooling member is installed at the space for cooling. An actuating mechanism moves the cooling member between a contacting position where the cooling member makes contact with at least one of the inner wall and the outer wall and a non-contacting position where the cooling member does not make contact with any one of the inner wall and the outer wall. A control unit controls at least the actuating mechanism.
US08030597B2	Partition-type heating apparatus A partition-type heating apparatus has advantageous effects in that a material to be heated, i.e., a reaction gas used in a chemical vapor deposition (CVD) process, is pre-heated and the pre-heated reaction gas flows through a flow channel defined by the vertical and horizontal partitions so that the flowing reaction gas is heated by the transfer of heat generated from a hot wire during the flow of the reaction gas, thereby securing heating performance required for a small-sized heating apparatus.
US08030587B2	Rotary control device for moving vehicle remote control The invention concerns rotary control device for remote control of a moving vehicle, particularly a civil engineering works vehicle, an agricultural implement or a goods handling vehicle comprising two parts rotatably mobile relative to one another about an axis (A) and formed of a body (2) intended to be fixed to the handle of the remote control and an actuating part (6), the device also comprising first elastic means (13) including a winding (14) and two mobile branches (15, 16), the first actuating part being immobilized, in a position of equilibrium (P), with respect to a first member (2, 6). The device further comprises second elastic means (22) supported, on a mobile branch (15, 16) of the first elastic means (13) and, designed, in the position of equilibrium, to bear against a support portion (24) of the second member (2, 6).
US08030585B2	Press-key structure A press-key structure is disclosed, which comprises: a keycap, configured with a bottom surface; a substrate, being disposed under the keycap; and a pressing part, being arranged between the keycap and the substrate. In an exemplary embodiment, the pressing part further comprising: a frame, disposed on the bottom surface to be used for sustaining a pressing force from the keycap directly; and a plurality of supporting legs, being arranged surrounding the edges of the frame while extending outwardly from the same; wherein by connecting the outward-extending ends of the plural supporting legs to the substrate, the frame is supported and propped up by a specific height.
US08030582B2	Bottoming detection weighing scale and method of controlling weighing scale A body weighing machine (100) is provided with a distance measuring sensor (30) at the central position (C) of a base plate unit (50). A CPU (10) measures the body weight of a human subject. The CPU (10) then drives the distance measuring sensor (30) to measure a distance (Dm) between the sensor and a floor surface and determines whether a minimum distance (D) between the base plate unit (50) and the floor surface is zero. The CPU (10) displays via a display unit (15) a message indicating that an error has occurred in a case in which the minimum distance (D) is zero, and otherwise displays the measured body weight on the display unit (15).
US08030579B2	Multilayer printed wiring board An object of the present invention is to provide a multilayered printed circuit board having a short wiring distance of the conductor circuits, wide option of the design of the conductor circuits and additionally excellent in reliability since cracking scarcely takes place in the interlaminar resin insulating layers in the vicinity of via-holes. The present invention is a multilayered printed circuit board comprising: a conductor circuit and an interlaminar resin insulating layer serially formed on a substrate in alternate fashion and in repetition, wherein a connection of the conductor circuits through the interlaminar resin insulating layers is performed by a via-hole, wherein via-holes in different level layers among the via-holes are formed so as to form a stack-via structure, and wherein at least one of the land diameters of the above-mentioned via-holes in different level layers having the stack via structure is different from the land diameters of other via-holes.
US08030576B2	Wired circuit board with interposed metal thin film and producing method thereof A wired circuit board includes an insulating base layer, a conductive pattern formed on the insulating base layer and including a wire and a terminal portion, an insulating cover layer formed on the insulating base layer and having an opening portion to expose the terminal portion, and a metal thin film including a protecting portion interposed between the wire and the insulating cover layer, and an exposed portion formed continuously from the protecting portion on a peripheral end portion of the terminal portion exposed from the opening portion.
US08030574B2	Flexible printed circuit A flexible printed circuit includes a flexible substrate, a plurality of first conductive wires, and a plurality of second conductive wires. The flexible substrate includes a first surface and a second surface facing the first surface. The first conductive wires are provided on the first surface. The first conductive wires extend from an edge of the flexible substrate to another edge of the flexible substrate. The second conductive wires are provided on the second surface. The second conductive wires extend from an end of the flexible substrate to a predetermined portion of the flexible substrate. A part of each second conductive wire at the predetermined portion of the flexible substrate is electrically connected with the first conductive wire via a conductive structure.
US08030570B2	Cover assemblies for cables and electrical connections and methods for making and using the same An integral, unitary cover assembly for covering an electrical connection between first and second electrical cables each having a primary conductor and a neutral conductor includes an inner elastomeric sleeve, an outer elastomeric sleeve and an integral jumper assembly. The inner sleeve defines a cable passage to receive the electrical connection and the primary conductors of the first and second cables. The outer sleeve surrounds the inner sleeve. The jumper assembly includes an electrically conductive jumper conductor, a first jumper connector and a second jumper connector. The jumper conductor is interposed between the inner and outer sleeves and has first and second opposed ends. The first jumper connector is mounted on the first end of the jumper conductor and is configured to mechanically and electrically couple the neutral conductor of the first cable to the jumper conductor. The second jumper connector is mounted on the second end of the jumper conductor and configured to mechanically and is electrically couple the neutral conductor of the second cable to the jumper conductor.
US08030569B2	Light receiving or light emitting semiconductor module Multiple semiconductor elements in a semiconductor module in which multiple spherical light receiving or emitting semiconductor elements are installed can easily be retrieved, reused, or repaired. In a semiconductor module 60, two segment modules 61 are serially arranged in a storage casing 62. The segment modules 61 are each formed by molding solar battery cells 10 arranged in a matrix of multiple rows and columns, and a conductive connection mechanism serially-connecting the solar battery cells 10 in each column and parallel-connecting the solar battery cells 10 in each row in a synthetic resin with connection conductors 67 protruding at the ends. Conductive corrugated springs 70 and external terminals 76 are provided at the ends of the storage casing 62. The mechanical pressing force of the conductive corrugated springs 70 ensures that the two segment modules 61 are serially connected.
US08030568B2	Systems and methods for improving the similarity of the output volume between audio players A method for improving the similarity of the volumes in different audio players is described. First player metrics for one or more Musical Instrument Digital Interface (MIDI) instruments may be determined. A digital music file that uses the MIDI protocol may be received. A note parameter or channel parameter may be adjusted for notes in the digital music file based on the first player metrics.
US08030567B2	Generalized electronic music interface A generalized interface for interconnecting a wide range of electronic musical instruments and signal processing systems includes an outgoing multi-channel audio interface and an outgoing control interface. The outgoing multi-channel audio interface receives instrument audio signals generated by an external musical instrument, while the outgoing control interface receives MIDI control signals generated by the same external musical instrument. The outgoing multi-channel audio interface and the outgoing control interface respectively communicate audio signals and MIDI control signals to the external signal processing system. Variations include the addition of multi-channel audio paths to the instrument using drive transducer signals to excite instrument vibrating elements; the use of control paths to the instrument to control on-instrument lighting, signal processing, drive transducers, controller interpretation, etc.; non-MIDI control paths out of the instrument; providing the instrument with expanded power to supporting on-instrument lighting, video devices, and other auxiliary systems; video signals out of the instrument; and video signals to the instrument to support on-instrument video display.
US08030566B2	Envelope-controlled time and pitch modification This invention provides a signal processing and signal synthesis technique from a family of signal processing and signal synthesis techniques designed to readily interwork or be used individually in creating new forms of rich musical timbres. Amplitude-envelope controlled time-modulation and pitch-modulation are employed to add rich and attention-getting aspects to solo lines and chords. The amplitude envelope may be measured from the signal being modulated, a delayed version of this signal, or another signal source. Modulation characteristics and parameters may be recalled from stored program control or modulated in real-time by arbitrary control signals, including those derived from the original input signal. The invention may be used individually or in conjunction with other signal processing and signal synthesis techniques in creating new forms of rich musical timbres. The invention may also be used in spatially-distributed timbre construction.
US08030554B2	Soybean variety XB07S09 According to the invention, there is provided a novel soybean variety designated XB07S09. This invention thus relates to the seeds of soybean variety XB07S09, to the plants of soybean XB07S09 to plant parts of soybean variety XB07S09 and to methods for producing a soybean plant produced by crossing plants of the soybean variety XB07S09 with another soybean plant, using XB07S09 as either the male or the female parent.
US08030552B1	Soybean variety RJS35005 According to the invention, there is provided a novel soybean variety designated RJS35005. This invention thus relates to the seeds of soybean variety RJS35005, to the plants of soybean RJS35005 to plant parts of soybean variety RJS35005 and to methods for producing a soybean plant produced by crossing plants of the soybean variety RJS35005 with another soybean plant, using RJS35005 as either the male or the female parent.
US08030550B2	Broccoli plants tolerant to hollow/split stem disorder The invention provides broccoli seed and plants that combine high yield and quality with tolerance to hollow/split stem disorder. The invention further provides seed and plants of the broccoli lines designated BRM53-3915 and BRM53-3916 and progeny produced with at least one of these plants as a parent. The invention also relates to the plants, seeds and tissue cultures of hybrid broccoli variety RX05951180.
US08030549B2	Broccoli type adapted for ease of harvest A broccoli plant characterized in having an exerted head having a crown higher than the leaf canopy and a harvestable head of at least about 200 grams when planted at a density of 40,000 plants per hectare, where the harvestable head comprises the top 25 centimeters of said stalk.
US08030536B2	Absorbent articles with sublayer A diaper or adult incontinence garment including a backsheet and a sublayer. The sublayer may include one or more acquisition layers and one or more regions having a multitude of through or blind holes. The sublayer may isolate feces away from the skin and at the same time provide liquid acquisition. Certain regions of the sublayer may have a total open area of from 10% to 50% of the total surface area of the sublayer. The holes have an average smallest dimension of at least 3 mm. The sublayer has an average caliper of from 2 mm to 6, and an average caliper loss after wetting and under pressure of 0.3 psi of less than 20%.
US08030533B2	Method for combined production of paraxylene and benzene with improved productivity A process for the combined production of para-xylene and benzene comprises: separating a first feed, by adsorption in a simulated moving bed SMB, to produce an extract E rich in para-xylene and at least one raffinate R which is depleted in para-xylene; converting a secondary feed of toluene by selective disproportionation to produce benzene and xylenes; a) at the start of the cycle, producing a supplemental quantity of para-xylene in a crystallization unit supplied with the xylenes from the disproportionation; b) at the end of the cycle, when the adsorbant has aged: dividing the distilled extract E into a first fraction Ea and a complementary second fraction Eb; replacing the feed to the initial crystallization by the stream Ea; and recycling the xylenes from the disproportionation to the SMB. The invention enables para-xylene and benzene production to be maintained despite ageing of the SMB absorbent.
US08030529B2	Process for the preparation of intermediates The present invention provides a process for the production of intermediate compounds of formula (I), wherein the substituents are as defined herein. The process comprises reacting a substituted aniline with aqueous HX, followed by removal of water by azeotropic distillation and diazotization and pyrolysis with an organic nitrite at elevated temperatures in the absence of a copper catalyst. Alternatively, gaseous HX can be used to substitute aqueous HX in the process. Consequently, a step of water removal by azeotropic distillation can be eliminated. The intermediate compounds of formula I are suitable as intermediates in the preparation of herbicidally active 3-hydroxy-4-aryl-5-oxopyrazoline derivatives.
US08030519B2	Method for producing acetoacetic acid arylamides Acetoacetic acid arylamides are continuously produced from diketene and primary or secondary aromatic amines under the conditions of a reactive distillation in the presence of water. The continuous method provides a high purity of the products, nearly quantitative yields and a high rate of throughput.
US08030517B2	CCR9 inhibitors and methods of use thereof The invention relates to compounds represented by Structural Formula I, which can bind to CCR9 receptors and block the binding of a ligand (e.g., TECK) to the receptors. The invention also relates to a method of inhibiting a function of CCR9, and to the use compounds represented by Structural Formula I in research, therapeutic, prophylactic and diagnostic methods.
US08030514B2	Processes and intermediates for the preparations of prostaglandins The present invention provides novel processes for the preparation of a cyclopentanone of Formula II and a lactone of Formula I, which are useful in the production of prostaglandins: wherein Z, R2, R3, X1, X2, and are as defined in the specification. The invention also provides novel enantiomerically enriched compounds.
US08030512B2	Polycyclic pentafluorosulfanylbenzene compound and process for producing the compound A polycyclic pentafluorosulfanylbenzene compound represented by the following general formula (1) and a process for producing the polycyclic pentafluorosulfanylbenzene compound which comprises reacting a specific pentafluorosulfanylbenzene compound with a specific boronic acid compound are provided. The polycyclic pentafluorosulfanylbenzene compound is a novel compound and can be produced by the process industrially advantageously. (R1 to R4 each independently represent hydrogen atom or fluorine atom, R5 represents a hydrocarbon group having at least two cyclic structures which may have substituents, and Z represents keto group, thioketo group, methylene group or difluoromethylene group.)
US08030510B2	Process for the direct synthesis of alkylhalosilanes Process for preparing alkylhalosilanes are provided. The process involve reacting an alkyl halide with a solid body formed of silicon and a catalytic system.
US08030508B2	Porous zeolite of organosilicon, a method for preparing the same and the use of the same The present invention relates to an organosilicon porous zeolite, preparation of the same, and use of the same. The organosilicon porous zeolite of the invention has the following composition on molar basis: (1/n)Al2O3:SiO(2-m/2):mR:xM, wherein n=5 to 1000, m=0.001 to 1, x=0.005 to 2, R is at least one selected from the group consisting of alkyl, alkenyl and phenyl and connected to a silicon atom in the framework of the zeolite, and M is an organic amine templating agent, wherein a solid Si29NMR spectrum of the zeolite has at least one Si29 nuclear magnetic resonance peak in the range of from −80 to +50 ppm, and wherein a X-ray diffraction pattern of the zeolite exhibits diffraction peaks corresponding to d-spacing of 12.4±0.2, 11.0±0.3, 9.3±0.3, 6.8±0.2, 6.1±0.2, 5.5±0.2, 4.4±0.2, 4.0±0.2 and 3.4±0.1 Å. The porous zeolite can be used as an adsorbent or as a component of a catalyst for the conversion of an organic compound.
US08030506B2	Tumor selective and biodegradable cyclotriphosphazene-platinum(II) conjugate anticancer agent, and preparation method thereof Disclosed are a novel cyclotriphosphazene-platinum(II) complex conjugate anticancer agent, showing high selectivity to tumor tissues due to the enhanced permeability and retention effect in tumor tissues and a preparation method thereof.
US08030505B2	Biodiesel production method A process for producing lower alkyl esters of higher fatty acids from an oil phase and lower alcohols, in a catalytic transesterification process in the presence of an alkaline catalyst. A reaction mixture is provided by mixing oil-phase fatty acids with a solution comprising methanol and an alkaline catalyst comprising sodium methylate. The transesterification reaction of the reaction mixture is accelerated by subjecting the reaction mixture to a temperature above the boiling point of methanol and pressurizing the reaction mixture sufficiently to prevent boil-off. A centrifugal separator separates glycerin phase from biodiesel phase of a resulting reaction product stream. The biodiesel phase is washed by counter-current extraction.
US08030504B2	Antagonists of the TRPV1 receptor and uses thereof The present application is directed to compounds that are TRPV1 antagonists and have formula (I) wherein variables Ar1, L1, R1, R2, R3, R4, R5, Y1, Y2, and Y3, are as defined in the description, which are useful for treating disorders caused by or exacerbated by vanilloid receptor activity.
US08030502B2	Substituted 4-amino-1-(pyridylmethyl)piperidine and related compounds This invention provides 4-amino-1-(pyridylmethyl)piperidine and related compounds and pharmaceutically acceptable salts thereof which are useful as muscarinic receptor antagonists. This invention also provides pharmaceutical compositions containing such compounds; processes and intermediates useful for preparing such compounds; and methods for treating disease conditions mediated by muscarinic receptors, such as overactive bladder, irritable bowel syndrome and chronic obstructive pulmonary disease, using such compounds.
US08030500B2	Substituted isoindoles for the treatment and/or prevention of Aβ- related pathologies The present invention relates to novel compounds of formula (I) and their pharmaceutical compositions. In addition, the present invention relates to therapeutic methods for the treatment and/or prevention of Aβ-related pathologies such as Downs syndrome, β-amyloid angiopathy such as but not limited to cerebral amyloid angiopathy or hereditary cerebral hemorrhage, disorders associated with cognitive impairment such as but not limited to MCI (“mild cognitive impairment”), Alzheimer Disease, memory loss, attention deficit symptoms associated with Alzheimer disease, neurodegeneration associated with diseases such as Alzheimer disease or dementia including dementia of mixed vascular and degenerative origin, pre-senile dementia, senile dementia and dementia associated with Parkinson's disease, progressive supranuclear palsy or cortical basal degeneration.
US08030493B2	Monovalent and divalent salts of N-(5-hydroxynicotinoil) -L-glutamic acid exhibiting psychotropic (antidepressant and anxiolytic), neuroprotective, geroprotective and cerebroprotective action The invention relates to medicine, in particular to mono- and divalent salts of N-(5-hydroxynicotinoil)-L-glutaminic acid exhibiting psychotropic antidepressant, anxiolytic, heroprotective, neuroprotective, antihypoxia cerebroprotective and nootropic action. The novel compounds differ from the known preparations, including the closest prior art in the form of a N-(5-hydroxynicotinoil)-L-glutaminic acid base (nooglucotyl), in that they produce psychotropic effects, namely antidepressant, anxiolytic, neuroprotective and heroprotective actions, in such a way that lesion focuses caused by apoplectic attacks are reduced and age-specific neurological deficiencies and intellectual and physical work capacities are improved.
US08030491B2	Process and intermediate for preparation of donepezil The invention relates to new compounds of formula (III): wherein R is a C1-C4 linear or branched alkyl group. The invention also relates to new compounds of formula (IV) wherein M is a metal. The invention also relates to methods of making compounds of formulas (III) and (IV) and to methods of making donepezil and pharmaceutically acceptable salts thereof, such as donepezil hydrochloride, using the compounds.
US08030490B2	Phosphorescent iridium complex with non-conjugated cyclometalated ligands, synthetic method of preparing the same and phosphorescent organic light emitting diode thereof The present invention discloses a phosphorescent tris-chelated transition metal complex comprising i) two identical non-conjugated cyclometalated ligands being incorporated into a coordination sphere thereof with a transition metal, and one ligated chromophore being incorporated into the coordination sphere; or ii) one non-conjugated cyclometalated ligand forming a coordination sphere thereof with a transition metal, and two ligated chromophores being incorporated into the coordination sphere, wherein the metal is iridium, platinum, osmium or ruthenium, and the ligated chromophore possesses a relatively lower energy gap in comparison with that of the non-conjugated cyclometalated ligand, the latter afforded an effective barrier for inhibiting the ligand-to-ligand charge transfer process, so that a subsequent radiative decay from an excited state of these transition complexes will be confined to the single ligated chromophore. The architecture and energy gap of the ligated chromophore are suitable for generation of high efficiency blue, green and even red emissions.
US08030489B2	Ornithine derivative Provided is a compound which is useful as a therapeutic agent for chronic renal insufficiency and a therapeutic agent for diabetic nephropathy.The present inventors have made extensive studies on an ornithine derivative having an antagonistic action against an EP4 receptor, and as a result, they have found that by introducing cycloalkanediyl at a C terminal of the ornithine part of the compound of the present invention, the physicochemical properties such as solubility, and the like can be improved, thereby giving further preferred properties as a pharmaceutical. Therefore, they have completed the present invention.The compound of the present invention exhibits a good antagonistic action against an EP4 receptor, and thus, it is useful as a therapeutic agent for chronic renal insufficiency and diabetic nephropathy.
US08030484B2	Substituted triazines as prion protein ligands and their use to detect or remove prions Compounds of formula (I) wherein R1 and R2 are the same or different and are each optionally substituted alkyl, optionally substituted cycloalkyl, optionally substituted aryl or optionally substituted heteroaryl groups; R3 is hydrogen or an aryl group substituent or R3 is a solid support optionally attached via a spacer; Z represents an oxygen atom, a sulphur atom or NR4; Y represents an oxygen atom, a sulphur atom or NR5; in which R4 and R5, which may be the same or different, represent hydrogen, optionally substituted alkyl containing 1 to 6 carbon atoms, optionally substituted phenyl, optionally substituted benzyl or optionally substituted β-phenylethyl; and one of X1 and X2 represents a nitrogen atom and the other of X1 and X2 represents a nitrogen atom or CR6, in which R6 represents hydrogen or an aryl group substituent; are useful for the affinity binding of a prion protein.
US08030475B2	Inhibitors of retroviral reverse transcriptase Disclosed are nucleic acid molecules, and methods of their use, which have a specific structure including a double helical domain and a G-quadruplex domain physically connected by a linker domain which may be nucleosidic or non-nucleosidic. These aptamers demonstrate potent inhibition of phylogenetically diverse primate lentiviral reverse transcriptases, which effect is largely independent of aptamer sequence provided that the aptamer has the specified structure.
US08030474B2	siRNA targeting cyclin-dependent kinase 4 (CDK4) Efficient sequence specific gene silencing for cyclin-dependent kinase 4 is possible through the use of siRNA technology. By selecting particular siRNAs by rational design, one can maximize the generation of an effective gene silencing reagent, as well as methods for silencing genes. Methods, compositions, and kits generated through rational design of siRNAs are disclosed.
US08030470B2	Isolated nucleic acids encoding farnesyltransferase polypeptides The present invention provides isolated polynucleotides encoding farnesyltransferase polypeptides, vectors, and cells transformed with farnesyltransferase polynucleotides.
US08030466B2	3′-o-fluorescently modified nucleotides and uses thereof The present invention relates to a DNA sequencing method using a nucleoside triphosphate with a fluorescent blocking group on its 3′-OH end as a reversible terminator. Further, the present invention relates to sequencing-by-synthesis method using the mono-modified reversible terminator (MRT), the novel nucleotide monomer having a reversible fluorescent blocking group removable chemically or enzymatically at its 3′-OH end. The sequencing method of the present invention facilitates sequencing of bases inserted by terminating extension of a nucleotide chain by the nucleotide monomer and then detecting fluorescence signal from 3′-OH end. At this time, after analyzing the fluorescence signal, the blocking group conjugated to the 3′-OH end can be effectively removed, indicating that a free 3′-OH functional group can be successfully restored, so that the next monomer insertion is possible, making continuous sequencing possible.
US08030463B2	Method for detecting and quantifying endogenous wheat DNA sequence A circular DNA is provided comprising endogenous DNA common to both genetically modified wheat and non-genetically modified wheat along with one or more pieces of DNA each having a sequence present specifically in a strain of genetically modified wheat. Also provided is a method for determining a mix rate of genetically modified wheat in a test sample.
US08030457B2	Antigen binding proteins to proprotein convertase subtilisin kexin type 9 (PCSK9) Antigen binding proteins that interact with Proprotein Convertase Subtilisin Kexin Type 9 (PCSK9) are described. Methods of treating hypercholesterolemia and other disorders by administering a pharmaceutically effective amount of an antigen binding protein to PCSK9 are described. Methods of detecting the amount of PCSK9 in a sample using an antigen binding protein to PCSK9 are described.
US08030453B2	Methods of making an antibody that binds a chemerin polypeptide The present invention relates to a G-protein coupled receptor and a novel ligand therefor. The invention provides screening assays for the identification of candidate compounds which modulate the activity of the G-protein coupled receptor, as well as assays useful for the diagnosis and treatment of a disease or disorder related to the dysregulation of G-protein coupled receptor signaling.
US08030450B2	Canine RANKL and methods for preparing and using the same The present invention provides isolated nucleic acid molecules that encode a substantial part of canine RANKL polypeptide, including the extracellular domains of that polypeptide, the polypeptide and fragments thereof. Vectors and host cells encoding and expressing canine RANKL polypeptide are provided, as well as antibodies that bind to RANKL and that inhibit RANKL activity. Also provided are methods of treating an animal to inhibit or treat the loss of bone minerals.
US08030445B2	Glycopeptide derivative Disclosed are derivatives of glycopeptide compounds having at least one substituent of the formula: —Ra—Y—Rb—(Z)x where Ra, Rb, Y, Z and x are as defined, and pharmaceutical compositions containing such glycopeptide derivatives. The disclosed glycopeptide derivatives are useful as antibacterial agents.
US08030444B2	Microbicidal compositions comprising human CD38 polypeptides derived from the extracellular membrane-proximal region Peptides representing sequences from region 45-74 of the human CD38 leukocyte surface antigen (SEQ ID NO:1) are provided which may be used to inhibit or prevent transmission or replication of the HIV virus. The peptides have from 13 to 30 amino acids and include the amino acid sequence GPGTTK (SEQ ID NO:18) for topical application to inhibit or prevent transmission of the HIV virus.
US08030435B2	Solid state polymerization process for polyester with phosphinic acid compounds Disclosed is a method for increasing the solid state polymerization (SSP) rates of metal catalyzed polyesters. The method comprises in a first step, reacting a dicarboxylic acid or a C1-C4 dicarboxylic diester with a diol at a suitable temperature and pressure to effect esterification or transesterification to prepare a precondensate and in a second step, reacting the precondensate to effect polycondensation at a suitable temperature and pressure to prepare a high molecular weight polyester and in a third step, further increasing the molecular weight and viscosity of the polyester under SSP conditions of a suitable temperature and pressure, where a metal catalyst is added in the first step or in the second step as a reaction catalyst, and where a certain phosphinic acid compound is added in the first step, in the second step or just prior to the third step. The polyester product exhibits low aldehyde formation during melt processing steps as well as excellent color.
US08030434B2	Polyester film, process for producing the same and use thereof The present invention relates to a polyester film produced by melt-extruding a polyester composed of a dicarboxylic acid unit and a diol unit, wherein 1 to 80 mol % of the diol unit is a unit containing a cyclic acetal skeleton, and the polyester film has an in-plane retardation of 20 nm or less at a wavelength of 550 nm. The polyester film is an optically isotropic polyester film which is easily produced by an extrusion-molding method and has an economical advantage. The polyester film is useful for production of optical members or optical products such as phase difference films, protective films for polarizing plates, light diffusion films, lens sheets, anti-reflection films and optical information recording media.
US08030428B2	Curable composition To provide a curable composition which has a high curing rate and can provide a cured product having good durability.A curable composition comprising an oxyalkylene polymer (A) having a reactive silicon group represented by the following formula (1), and a quaternary ammonium salt (B): —SiX1aR13-a (1) wherein R1 is a C1-20 monovalent organic group which may have a substituent, X1 is a hydroxyl group or a hydrolyzable group, and a is an integer of from 1 to 3; provided that when plural R1s are present, they may be the same or different from one another, and when plural X1s are present, they may be the same or different from one another.
US08030424B2	Cyclobutene polymers and methods of making the same Described is a cyclobutene polymer comprising: monomeric units of cyclobutene, said cyclobutene having at least one fused ring system substituted thereon, said polymer comprising not more than 10 mol percent ring-opened units of said cyclobutene; and said polymer having a molecular weight of at least 1,000; said polymer optionally copolymerized with a comonomer to form a copolymer therewith. Compositions thereof and methods of making the same are also described.
US08030421B2	Process for the polymerization of 1-butene A process for polymerizing 1-butene comprising the step of contacting under polymerization conditions 1-butene and optionally from 0 to 20% by mol of an alpha olefin with a catalyst system obtainable by contacting a bridged metallocene compound of formula (I) wherein R1 and R2 are an hydrocarbon radical A is a carbon atom, a germanium atom or a silicon atom; m is 1, 2; M is a metal of group 4 of the Periodic Table of the Elements; X, is hydrogen, a halogen atom, or a group R, OR, OSO2CF3, OCOR, SR, NR2 or PR2, wherein the substituents R are hydrocarbon radical; L is a moiety of formula (IIa) or (IIb) wherein T is an oxygen (O) or sulphur (S) atom or a CH2 group; and R3 and R4 are hydrogen atoms or hydrocarbon radicals; one or more alumoxanes or compounds able to form an alkylmetallocene cation; and optionally an organo aluminum compound.
US08030418B2	Modified hydrocarbylphenol-aldehyde resins for use as tackifiers and rubber compositions containing them The invention relates to a modified hydrocarbylphenol-aldehyde resin prepared by reacting a hydrocarbylphenol-aldehyde resin with a primary or secondary amine and further with an epoxide. The invention also provides a process for preparing a modified, hydrocarbylphenol-aldehyde resin and a rubber composition containing such resin.
US08030417B2	Process for producing polyester-polycarbonate type thermoplastic polyester elastomer and polyester-polycarbonate type thermoplastic polyester elastomer The present invention is a process for producing a polyester-polycarbonate type thermoplastic polyester elastomer in which a hard segment consisting of a polyester constructed of aromatic dicarboxylic acid, and an aliphatic or alicyclic diol, and a soft segment consisting mainly of aliphatic polycarbonate are connected, comprising at least a step of increasing the molecular weight of an aliphatic polycarbonate diol by a reaction of an aliphatic polycarbonate diol and a chain extender, and a step of reacting aliphatic polycarbonate and a polyester constructed of aromatic dicarboxylic acid and an aliphatic or alicyclic diol in the molten state.
US08030414B2	Oligomers and polymers containing sulfinate groups and method for the production thereof The invention relates to novel polymers or oligomers containing at least sulfinate groups (P—(SO2)nX, X=1-(n=1), 2-(n=2) or 3-(n=3) valent metal cation or H+ or ammonium ion NR4+ where R=alkyl, aryl, H), which are obtained by completely or partially reducing polymers or oligomers containing at least SO2Y-groups (Y═F, Cl, Br, I, OR, NR2 (R=alkyl and/or aryl and/or H), N-imidazolyl, N-pyrazolyl) by means of suitable reducing agents in a suspension or in a solution form.Polymer and polymer(blend)membranes which are obtained by further reacting the received sulfinated polymers, especially by alkylation of the sulfinate groups with mono- di- or oligo functional electrophiles. The invention further relates to methods for producing the sulfinated polymers and for further reacting the sulfinated polymers with electrophiles by S-alkylation.
US08030412B2	Active-energy-ray-curable coating composition, cured product thereof, and novel curable resin The present invention relates to an active-energy-ray-curable coating composition containing, as essential components, a radical-polymerizable resin (I) containing a polymer structure (α) of a radical-polymerizable unsaturated monomer and a poly(perfluoroalkylene ether) chain (β), and having a resin structure in which a plurality of the polymer structures (α) are linked to each other with the poly(perfluoroalkylene ether) chain (β) therebetween and the polymer structures (α) each have a radical-polymerizable unsaturated group at a side chain thereof; and a polymerization initiator (II).The active-energy-ray-curable coating composition can be used as a coating material that imparts surface properties such as stain-proof properties.
US08030411B2	Polymer compositions comprising peptizers, sports equipment comprising such compositions, and method for their manufacture Embodiments of the disclosed polymer composition comprise a first unsaturated polymer or polymer precursor, and an effective amount of a peptizer. The peptizer typically comprises a heteroaryl or a heterocyclic compound, other than morpholine as disclosed in assignee's prior applications. Disclosed polymer compositions are useful for making sports equipment, such as at least one layer of a golf ball, often a core. Because the compositions are useful for making golf balls, materials commonly known for making such golf balls can be used in combination with the polymer composition. A method for forming a golf ball also is disclosed. The method comprises providing disclosed compositions and then forming at least one component of a golf using the composition.
US08030409B2	Block copolymers containing functional groups The present invention provides a block copolymer of styrene and an unsaturated cyclic anhydride, such as maleic anhydride, a process for making a copolymer using controlled free radical polymerization in which certain parameters are adjusted to control the microstructure and molecular weight of the copolymer, and a method for using the block copolymer, including as a compatibilizer. Microstructure and molecular weight in the block copolymer can be controlled by adjusting the ratio of stable free radical to initiator. The copolymer can be made in a one step process and has a controlled microstructure that allows one block to be reactive toward several chemical moieties available in engineering polymers and the other block to be fully miscible with polystyrene or polymers miscible with polystyrene or polymers miscible with polystyrene such as polyphenylene ether.
US08030407B2	Activated carbon fibers and precursor material thereof An activated carbon fiber for fabricating a supercapacitor electrode and its precursor material are provided. The precursor material of the activated carbon fiber includes polyacrylonitrile (PAN) and a polymer having formula (I): wherein R1 is cyano, phenyl, acetate, or methoxycarbonyl, R2 is R3 is C1-7 alkyl, X is chlorine, bromine, tetrafluoroborate (BF4), hexafluorophosphate (PF6), or NH(SO2CH3)2, and m/n is 1-99/99-1.
US08030403B2	Transparent polypropylene composition The present invention relates to a composition, in particular to a polypropylene composition, and articles thereof, having an optimal balance between mechanical properties and transparency and thus the composition is particular suitable for packaging applications.
US08030389B2	Thermal insulation composition A thermal insulation composition comprising: aqueous base; one or more primary viscosifier comprising a quantity of clay; and, an amount of one or more polymeric viscosifier comprising sulfonate moiety.
US08030388B2	Vibration-damping material Provided is a vibration damping material, which includes a resin composition obtained by dispersing titanium dioxide (Y) and a mica flake (Z) in a polyester resin (X) containing dicarboxylic acid constitutional units an diol constitutional units, in which: (1) in the polyester resin (X), a ratio of a total of a number of the dicarboxylic acid constitutional units (A1) having an odd number of carbon atoms in a main chain and a number of the diol constitutional units (B1) having an odd number of carbon atoms in a main chain with respect to a total of a number of total dicarboxylic acid constitutional units (A0) and a number of total diol constitutional units (B0), i.e., [(A1+B1)/(A0+B0)] is in a range of 0.5 to 1; and (2) a mass ratio (X:Y:Z) of the polyester resin (X), the titanium dioxide (Y), and the mica flake (Z) is in a range of 15 to 40:5 to 30:30 to 80. The vibration damping material is light, has a high vibration damping ability, and exhibits a higher vibration damping ability in a particularly wide range of frequency. Because the vibration damping material does not require use of a carbon powder or the like, the material can also be used in applications and parts that require various color tones, and has high versatility.
US08030378B2	Heat curing silicone rubber compound composition The present invention provides a silica-containing heat curing silicone rubber compound composition which can be produced safely and hardly suffers from inclusion of foreign substances. More specifically, when (A) 100 parts by weight of a polyorganosiloxane base polymer and (B) 1 to 100 parts by weight of a reinforcing silica are mixed together, (C) 0.05 to 80 ppm of an ionic liquid whose anionic component is bis(trifluoromethanesulfonyl)imide is added thereto.
US08030373B2	Pigment distribution system and method of encapsulating pigment Provided is a pigment distribution system. The pigment distribution system includes a pigment encapsulated by physically adsorbing a diblock copolymer to the pigment. The diblock copolymer is represented by Formula 1 below: where -A- denotes a hydrophilic monomer, -B- denotes a hydrophobic monomer, m denotes an integer ranging from 1 to 10, and n denotes an integer ranging from 3 to 30, wherein hydrophilic monomers of neighboring diblock copolymer chains are crosslinked using a crosslinker.
US08030369B2	Contact lenses with improved wearing comfort The invention relates to a biomedical molding, in particular a contact lens, which is obtainable by crosslinking, in a mold, an aqueous solution of a crosslinkable polyvinyl alcohol (PVA) prepolymer comprising at least 0.5 weight-%, based on the entire formulation, of a non-reactive PVA, wherein the number-average molecular weight of the non-reactive PVA is higher than that of the crosslinkable PVA. A contact lens of the invention has an improved wearing comfort.
US08030368B2	Photoinitiated reactions Photoinitiated reactions especially in photopolymer technology, as well as photoinitiated color forming reactions are achievable by applying a reactive substrate selected from a polymerisable and/or crosslinkable composition and a color changing substance to a support, activating a latent photoinitiator applied with the reactive substance and subsequently exposing the reactive substrate with the resulting photoinitiator therein to photoreaction conditions wherein actinic radiation causes the substrate to undergo polymerization and/or crosslinking or color change respectively, the substrate being locally modified in its constitution as a result of its exposure to actinic radiation at least one stage of the method, so that the resulting polymerised and/or crosslinked composition or color changed substance corresponds in its distribution on the support to the locations of the modification of the substrate.
US08030365B2	Compositions containing expandable microspheres and an ionic compound as well as methods of making and using the same This invention relates to composition containing expandable microspheres and at least one ionic compound and having a zeta potential that is greater than or equal to zero mV at a pH of about 9.0 or less at an ionic strength of from 10−6 M to 0.1M., as well as methods of making and using the composition.
US08030360B2	Anti-wrinkle agent A medicament having an anti-wrinkle action, which comprises as an active ingredient a retinoid having a fundamental structure of a phenyl substituted carbamoyl benzoic acid or a phenyl substituted carboxamide benzoic acid (for example, 4-(3,5-bis(trimethylsilyl)phenylcarboxamide) benzoic acid, 4-[(5,6,7,8-tetrahydro-5,5,8,8-tetramethyl-2-naphthalenyl)carbamoyl]benzoic acid, or the like).
US08030357B2	Use of bupropion metabolites for the treatment of inflammatory disorders Compounds that may be used for the treatment or prevention of a condition associated with T-cell proliferation or that is mediated by pro-inflammatory cytokines are of formula (I) or a salt thereof.
US08030355B2	Tablet composition with a prolonged release of tamsulosin A tamsulosin controlled release tablet is formed using a water-swellable matrix-forming composition as a release controlling mechanism. The matrix forming composition comprises (i) a pH-sensitive swellable hydrophilic polymer, which is a cross-linked polyacrylic acid polymer, and (ii) a pH-insensitive swellable hydrophilic polymer. The tablet optionally contains a water insoluble binder as well.
US08030353B2	Preparation of the formaurindicarboxylic acid base and its derivations and use A pharmaceutical composition comprising at least 0.1 μmol of formaurindicarboxylic acid or its derivatives in 1 kg of pharmaceutically acceptable carrier. The pharmaceutical composition of claim 1 wherein the composition is in the form of solution prepared using aqueous alcali or water.
US08030352B2	Method of producing retinyl esters A method of producing a retinyl ester compound comprising subjecting a composition comprising retinyl or a retinyl ester and a fat or oil of animal or vegetable origins to enzyme catalysed trans-esterification in solvent free conditions to produce a retinyl ester.
US08030349B2	Method for prevention of degradation of thermally unstable medicament The present invention provides a method for preventing the degradation of a thermally unstable medicament in an eye drop containing the medicament thereby to stabilize the eye drop. By adding an organic amine to an eye drop containing a thermally unstable medicament, the degradation of the medicament in the eye drop can be effectively prevented, and therefore the eye drop can be stably stored.
US08030348B2	Natural marine source phospholipids comprising polyunsaturated fatty acids and their applications A phospholipid extract from a marine or aquatic biomass possesses therapeutic properties. The phospholipid extract comprises a variety of phospholipids, fatty acid, metals and a novel flavonoid.
US08030347B2	Cylopenta[b]benzofuran derivatives and the utilization thereof The present application relates to a novel cyclopenta[b]benzofuran derivatives, processes for their preparation and their use for the manufacture of medicaments, in particular for the prophylaxis and/or therapy of acute or chronic disorders characterized by elevated cellular stress, by local or systemic inflammatory processes or by hyperproliferation.
US08030341B2	Dmt-derivative compounds and related compositions and methods of use The present invention relates to symmetric and asymmetric dimeric Dmt (2′,6′-ditnethyl) compounds and Dmt derivative compounds with dual δ and μ opioid receptor antagonist activity. Also, the present invention provides compositions comprising these compounds and it provides methods of using these compounds.
US08030338B2	Method for producing 2-nitroimidazole derivative It is an object to provide a method for producing a 2-nitroimidazole derivative having an acyclic sugar chain in a side chain, which is suitable for production of a derivative having a radioisotope.A method for producing 1-(1-benzoyloxymethyl-2-hydroxyethyl)oxymethyl-2-nitroimidazole, characterized by reacting glycerin with a benzoylating agent to obtain 1-O-benzoylglycerin, reacting 1-O-benzoylglycerin with dimethoxymethane in the presence of a dehydrating agent to obtain 4-benzoyloxymethyl-1,3-dioxolane, and then reacting this product with 2-nitroimidazole or 2-nitro-1-trialkylsilylimidazole in the presence of a Lewis acid.
US08030334B2	Organic compounds The present invention provides novel organic compounds of Formula I: methods of use, and pharmaceutical compositions thereof.
US08030333B2	Benzimidazole compound crystal A novel crystal of (R)-2-[[[3-methyl-4-(2,2,2-trifluoroethoxy)-2-pyridinyl]methyl]sulfinyl]-1H-benzimidazole or a salt thereof of the present invention is useful for an excellent antiulcer agent.
US08030328B2	Imidazolone phenylalanine derivatives Disclosed are compounds of the formula: and the pharmaceutically acceptable salts thereof wherein the variables A, n, R5, R21-R24 and Q are defined herein. These compounds bind VLA-4. Certain of these compound also inhibit leukocyte adhesion and, in particular, leukocyte adhesion mediated by VLA-4. Such compounds are useful in the treatment of inflammatory diseases in a mammalian patient, e.g., human, such as asthma, Alzheimer's disease, atherosclerosis, AIDS dementia, diabetes, inflammatory bowel disease, rheumatoid arthritis, tissue transplantation, tumor metastasis and myocardial ischemia. The compounds can also be administered for the treatment of inflammatory brain diseases such as multiple sclerosis.
US08030327B2	Fused imidazole derivative The present invention relates to a compound represented by the Formula [I]: Wherein: the A ring is a 5-membered aromatic heterocyclic group containing at least one hetero atom selected from a nitrogen atom, and the like; A1 and A2, are each a nitrogen atom, and the like; X2, X3, X4, and X5 are all carbon atoms, or alternatively any one of X2, X3, X4, and X5 is a nitrogen atom and the rest are all carbon atoms; R1 is a hydrogen atom, or the like; R2, R3, R4, and R5, are each a hydrogen atom, or the like; R6 and R6′, are each a hydrogen atom, and the like; R7 is an aryl group and the like; and R8 is an amino group or a hydroxy group, or a pharmaceutically acceptable salt or ester thereof.
US08030324B2	Pyridine derivatives for the treatment of metabolic disorders related to insulin resistance or hyperglycemia The present invention provides novel compounds represented by the general formula (I): their stereoisomers, pharmaceutically acceptable salts and their pharmaceutically acceptable solvates thereof, which are useful in treating metabolic disorders related to insulin resistance or hyperglycemia. The invention also relates to a process for the manufacture of compounds of formula (I) and pharmaceutical compositions containing them.
US08030318B2	Fused bicyclic inhibitors of HCV Substituted fused bicyclic pyrimidine compounds having an amide-substituted pyridylamine group at C-4 of the pyrimidine ring are useful in the treatment of conditions associated with HCV.
US08030316B2	Malate salt of (2R)-methyl-1-{3-[2-(3-pyridinyloxy)ethoxy]-2-pyrazinyl}piperazine The present invention relates to a process for the preparation of compounds which are therapeutically active in the central nervous system.In one aspect, the invention relates to a process for the preparation of compounds of the general formula (I): wherein HA is a pharmaceutically acceptable acid and R1-R4 are each independently selected from the group consisting of hydrogen, halogen, C1-C6-alkyl, C1-C6-alkoxy, and di-C1-C6-alkylamino-C2-C6-alkoxy. The invention also relates to the use of said compound to manufacture a medicament for the treatment of a serotonin-related disorder.
US08030314B2	Use of 2h-benzimidazol-2-one, 1,3-dihydro-1-(2{4-[3-(trifluoromethyl)phenyl]-1-piperazinyl}ethyl)-and its physiologically acceptable acid addition salts Use of 2H-benzimidazol-2-one, 1,3-dihydro-1-(2{4-[-(trifluoromethyl)phenyl]-1-piperazinyl}ethyl)- or a physiologically acceptable acid addition salt thereof, for the manufacture of a medicament for the treatment of extrapyramidal movement disorders. These extrapyramidal movement disorders may result from idopathic Parkinson's disease, from the adverse effects of the administration of anti-Parkinson drugs in idiopathic Parkinson's disease, from dyskinesias caused by idiopathic Parkinson's disease and/or long-term administration of anti-Parkinson drugs, from Parkinson-like or Parkinson-related syndromes of from Parkinsonoid symptoms. Another aspect of the present invention concerns a pharmaceutical composition comprising, as active ingredients-(I) 2H-benzimidazol-2-one, 1,3-dihydro-1-(2-{4-[3-(trifluoromethyl)phenyl]-1-piperazinyl}ethyl)-or a physiologically acceptable acid addition salt thereof, and (II) at least one anti-Parkinson drug, in combination with one or more pharmaceutically acceptable excipients.
US08030313B2	Controlled release sterile injectable aripiprazole formulation and method A controlled release sterile freeze-dried aripiprazole formulation is provided which is formed of aripiprazole of a desired mean particle size and a vehicle therefor, which upon constitution with water and intramuscular injection releases aripiprazole over a period of at least about one week and up to about eight weeks. A method for preparing the controlled release freeze-dried aripiprazole formulation, and a method for treating schizophrenia employing the above formulation are also provided.
US08030311B2	Phenylacetamides suitable as protein kinase inhibitors The invention relates to compounds of the formula (I) wherein the moieties R1, R2, R3, R9, R10 and Q and X, Y and Z are as defined in the specification, and salts thereof, as well as their use, methods of use for them and method of their synthesis, and the like. The compounds are protein kinase inhibitors and can, inter alia, be used in the treatment of various proliferative diseases.
US08030308B2	Bicyclic sulfonamide derivatives which are L-CPT 1 inhibitors The invention is concerned with novel heterobicyclic derivatives of formula (I) wherein R1, R2, R3, R4, R5, R6, V, W, X and Y are as defined in the description and in the claims, as well as physiologically acceptable salts and esters thereof. These compounds inhibit L-CPT1 and can be used as medicaments.
US08030303B2	Salt of morpholine compound (2S)-[4-(Carboxymethyl)thiazol-2-ylthio]-N-{[4-(3,4-dichlorobenzyl)morpholin-2-yl]methyl}acetamide hydrobromide and a crystal thereof, which resist easy weight change caused by vapor sorption as compared to a free form, and are superior as drug substances of pharmaceutical products, and a production intermediate therefor are provided.
US08030299B2	Palladium complexes inhibit N-myristoyltransferase activity in vitro and cancer growth in vivo Melanoma is a solid tumor that is notoriously resistant to chemotherapy, and its incidence is rapidly increasing. Recently, several signaling pathways have been demonstrated to contribute to melanoma tumorigenesis, including constitutive activation of MAP kinase, Akt and stat-3. The activation of multiple pathways may account in part for the difficulty in treatment of melanoma. In a recent screen of compounds, we found that an organopalladium complex showed significant antiproliferative activity against melanoma cells. This complex, tris(dibenzylideneacetone)dipalladium (Tris DBA), has activity against B16 murine and A375 human melanoma in vivo. Tris DBA inhibits several signaling pathways including activation of MAP kinase, Akt, stat-3 and S6 kinase activation. Tris(dibenzylideneacetone)dipalladium is thus a novel compound that is a member of a class of noble metal complexes with potential antitumor activity. Further preclinical evaluation of TrisDBA and related complexes is warranted.
US08030297B2	Controlled release corticosteroid compositions and methods for the treatment of OTIC disorders Disclosed herein are compositions and methods for the treatment of otic disorders with steroid, NSAID, and/or adenosine triphosphatase (“ATPase”) modulator agents. In these methods, the steroidal, NSAID, and/or ATPase compositions and formulations are administered locally to an individual afflicted with an otic disorder, through direct application of these compositions and formulations onto or via perfusion into the targeted auris structure(s).
US08030295B2	19,26,27-trinor-1α,25-dihydroxyvitamin D3 compounds Compounds of formula 1 are provided where X1, X2, and X3 are independently selected from H or hydroxy protecting groups, and R1 and R2 have the definitions provided herein. Such compounds may be used in preparing pharmaceutical compositions and are useful in treating a variety of biological conditions.
US08030294B2	Compounds for the treatment of psychiatric or substance abuse disorders The invention provides methods for treating or preventing psychiatric and substance abuse disorders, involving administration of a therapeutically-effective amount of a cytosine-containing or cytidine-containing compound, creatine-containing compound, adenosine-containing, or adenosine-elevating compound to a mammal.
US08030292B2	Antisense antiviral compounds and methods for treating a filovirus infection The invention provides antisense antiviral compounds and methods of their use and production in inhibition of growth of viruses of the Filoviridae family, and in the treatment of a viral infection. The compounds and methods relate to the treatment of viral infections in mammals including primates by Ebola and Marburg viruses. The antisense antiviral compounds are morpholino oligonucleotides having: a) a nuclease resistant backbone, b) 15-40 nucleotide bases, and c) a targeting sequence of at least 15 bases in length that hybridizes to a target region selected from the following: i) the Ebola virus AUG start site region of VP24; ii) the Ebola virus AUG start site region of VP35; iii) the Marburg virus AUG start site region of VP24; or iv) the Marburg virus AUG start site region of NP.
US08030290B2	Cell-type specific aptamer-siRNA delivery system for HIV-1 Therapy The present invention relates to compositions and methods for delivery of siRNA to specific cells or tissue. More particularly, the present invention relates to compositions and methods for cell type-specific delivery of anti-HIV siRNAs via fusion to an anti-gp120 aptamer.
US08030289B2	Oligonucleotide and use thereof An oligonucleotide with a nucleotide sequence of 5′-cctcctcctcctcctcctcctcct-3′ (SEQ ID NO: 1) inhibits proliferation of human PBMC activated by TLR9 agonist and interferon production from human PBMC induced by TLR9 agonist, HSV-1, flu virus and serum from SLE patients, and rescues the mice from cytokine-mediated lethal shock. This oligonucleotide can be used as a remedy for the treatment of systemic lupus erythematosus (SLE), sepsis, multiple organ dysfunction syndromes and other immune-mediated disorders.
US08030287B2	DNA vaccine against North American spring viremia of carp virus In this application is described a novel DNA vaccine for Spring viremia of carp virus. The candidate vaccine a SVCV glycoprotein (G) gene from the North Carolina isolate. The DNA vaccine provides protection in vaccinated fish against challenge with the SVCV.
US08030284B2	Treatment of eye disorders characterized by an elevated intraocular pressure by siRNAs Sequences and protocols for treatment of eye conditions by use of RNA interference are disclosed. Target genes are selected from those responsible for aqueous flow or aqueous outflow, while particularly preferred conditions to be treated include glaucoma and uveitis.
US08030280B2	Melanoma antigens and their use in diagnostic and therapeutic methods The present invention provides an isolated or purified immunogenic peptide comprising 8-15 contiguous amino acids of gp100 (SEQ ID NO: 121) and related nucleic acids, expression vectors, host cells, populations of cells, and methods of use. The invention further provides immunogenic peptides derived from gp100 which have been modified to enhance their immunogenicity and related nucleic acids, expression vectors, host cells, populations of cells, and methods of use.
US08030279B2	Tamandarin analogs and fragments thereof and methods of making and using The present invention is directed to a compound of Formula I wherein R1, R2, R3, R4, R5, R6, W, X, Y, and Z are defined herein. The compounds of the present invention are useful as anticancer agents. Specifically, the compounds are useful for treating or preventing cancer and tumor growth. The present invention is also directed to compositions comprising a compound according to the above formula. The present invention is also directed to methods of using a compound according to the above formula.
US08030274B2	Method for treating asthma and chronic obstructive pulmonary disease (COPD) comprising administering FGF2 The present invention relates an agent comprising FGF2 (Fibroblast Growth Factor-2 or basic Fibroblast Growth Factor (bFGF)) as an effective ingredient for treatment or prevention of Asthma and Chronic Obstructive Pulmonary Disease (COPD). Also, The present invention relates Th1 asthma and COPD mouse animal model induced by Ovalbumin and double strand RNA. The therapeutic agent comprising FGF2 of the present invention can be used for treatment or prevention for airway fibrosis, airway inflammation, airway hyperresponsiveness, airway remodeling, asthma and COPD. Also, Th1 asthma and COPD mice animal model induced by Ovalbumin and double strand RNA can be used for development of therapeutic agent for asthma and COPD.
US08030272B2	Lactoferrin compositions and methods of wound treatment The present invention relates to lactoferrin compositions and methods of using the compositions to treat wounds. The compositions can be administered alone or in combination with other standard wound healing therapies.
US08030266B2	Method for production of pearlescent composition comprising a fatty acid glycol ester mixture A method for producing a pearly luster composition containing pearly luster particles (A) containing a fatty acid glycol ester (a1) and a fatty acid glycol ester (a2) having a melting point higher than the melting point of the fatty acid glycol ester (a1), and a surfactant (B), wherein the method includes the steps of (i) solubilizing the fatty acid glycol ester (a2) in the presence of the surfactant (B); (ii) mixing the solubilized solution obtained in the step (i) with a molten fatty acid glycol ester (a1), to emulsify the mixture; and (iii) cooling the emulsified mixture obtained in the step (ii), to precipitate the pearly luster particles (A); a pearly luster composition obtained by the method; and a shampoo containing the pearly luster composition. The pearly luster composition obtained by the present invention is suitably used for shampoos, conditioners, body shampoos, liquid detergents, and the like.
US08030263B2	Composition for stripping and cleaning and use thereof A composition comprising one or more water soluble organic solvents comprising a glycol ether; water; a fluoride containing compound provided that if the fluoride containing compound is ammonium fluoride than no additional fluoride containing compound is added to the composition; optionally a quaternary ammonium compound; and optionally a corrosion inhibitor is disclosed herein that is capable of removing residues from an article such as photoresist and/or etching residue. Also disclosed herein is a method for removing residues from an article using the composition disclosed herein.
US08030262B2	Methods of cleansing dyed hair Provided are methods of cleansing dyed hair comprising applying to dyed hair a composition comprising anionic surfactant and a hydrophobically-modified polymer capable of binding surfactant thereto.
US08030259B2	Alkylated PANA and DPA compositions The invention relates to a composition comprising a mixture of alkylated N-α-naphthyl-Nphenylamine (PANA) and alkylated diphenylamine (DPA), the product obtainable by alkylating PANA or a mixture of PANA and DPA with alkenes and the process for alkylating PANA or a mixture of PANA and DPA with alkenes. The compositions according to the present invention have an outstanding anti-oxidative action, which can be demonstrated by established test methods.
US08030256B2	Amine tungstates and lubricant compositions This invention relates to lubricating oil additives, and to lubricating oil compositions, their method of preparation, and use. More specifically, this invention relates to several novel lubricating oil additives and compositions which contain a tungsten compound and an antioxidant, namely aminic antioxidants such as a secondary diarylamine or an alkylated phenothiazine. The use of the tungsten compound with the secondary diarylamine and/or the alkylated phenothiazine provides improved oxidation and deposit control to lubricating oil compositions. The lubricating oil compositions of this invention are particularly useful as crankcase and transmission lubricants, gear oils and other high performance lubricant applications.
US08030253B2	Foamed cement compositions comprising oil-swellable particles Of the many compositions provided herein, an embodiment includes a foamed cement composition comprising a cementitious component, an oil-swellable particle comprising at least one swellable elastomer selected from the group consisting of acrylate butadiene rubber, polyacrylate rubber, isoprene rubber, choloroprene rubber, butyl rubber, brominated butyl rubber, chlorinated butyl rubber, chlorinated polyethylene, neoprene rubber, styrene butadiene block copolymer, sulphonated polyethylene, ethylene acrylate rubber, epichlorohydrin ethylene oxide copolymer, ethylene-propylene rubber, ethylene vinyl acetate copolymer, fluorosilicone rubber, silicone rubber, and combinations thereof, a foaming and stabilizing surfactant, gas, and water. Another embodiment includes a foamed cement composition comprising a cementitious component, an oil-swellable particle comprising a block copolymer of styrene butadiene rubber, a foaming and stabilizing surfactant, and gas.
US08030250B2	Method of treating subterranean formations with carboxylated guar derivatives The production of hydrocarbons from a subterranean formation is enhanced by use of a well treatment fluid which contains a carboxylated guar which may be prepared by reacting a guar source and a derivatizing agent of the formula X(CH2)nCOOH or alkali salts thereof, wherein X is selected from the group consisting of —OSO2CH3; —OSO2C2H5; —OTs, —Br, and —I and n is between from 1 to 4. The intrinsic viscosity of the carboxylated guar in 2% KCl at 27° C. is at least 750 mL/g and the degree of substitution (DS) of the carboxylated guar is typically between from about 0.02 to about 0.15.
US08030249B2	Methods and compositions relating to the hydrolysis of water-hydrolysable materials Methods relating to the hydrolysis of water-hydrolysable materials are provided. In one embodiment, a method of treating at least a portion of a subterranean formation is provided, the method comprising: providing a water-hydrolysable material; introducing the water-hydrolysable material into a well bore penetrating the subterranean formation; providing a treatment fluid comprising an aqueous liquid and a water-miscible solvent; introducing the treatment fluid into the well bore so as to contact the water-hydrolysable material; and allowing the water-hydrolysable material to hydrolyze. Methods of completing a well also are provided.
US08030238B2	Catalyst and process for the preparation of alkylated aromatic hydrocarbons The present invention relates to a new zeolite having a beta-type crystalline structure, characterized by a distribution of the Lewis acid sites and Brønsted acid sites corresponding to a molar ratio [Lewis sites] [Brønsted sites] equal to or higher than 1.5. This new zeolite is useful in preparation processes of alkylated aromatic hydrocarbons through the alkylation and/or transalkylation of aromatic compounds. The preparation method of the new zeolite is also object of the present invention.
US08030236B2	Fire-resistant ordinary ceramic batch, and fire-resistant product therefrom Disclosed are a fire-resistant ordinary ceramic batch and a fire-resistant product predominantly comprising a) at least one granular, fire-resistant, mineral, alkaline main component made of an MgO-based or MgO and CaO-based fire-resistant material that is based on at least one alkaline fire-resistant raw material, and b) at least one granular, fire-resistant, mineral, MgO-based, additional elasticator in the form of a forsterite material or a mixture forming forsterite material preferably as small molded articles, such as pellets or granulate that is comminuted from compacts. The small molded articles have a grain size ranging from 0.3 to 8 mm while being advantageously provided with a binder at an amount that elasticates the main component.
US08030233B2	Optical glass An optical glass having optical constants of a refractive index (nd) of 1.78 or over, an Abbe number (νd) of 30 or below, and a partial dispersion ratio (θg, F) of 0.620 or below comprises SiO2 and Nb2O5 as essential components, wherein an amount of Nb2O5 in mass % is more than 40%. The optical glass further comprising, in mass % on oxide basis, less than 2% of K2O and one or more oxides selected from the group consisting of B2O3, TiO2, ZrO2, WO3, ZnO, SrO, Li2O and Na2O wherein a total amount of SiO2, B2O3, TiO2, ZrO2, Nb2O5, WO3, ZnO, SrO, Li2O and Na2O is more than 90% and TiO2/(ZrO2+Nb2O5) is less than 0.32.
US08030232B2	Titanium-containing oxide glass and method for production thereof A titanium-containing oxide glass having a bulky form and substantially having a chemical composition represented by the formula: (M1)1-x(M2)x(Ti1-y1(M3)y1)y2O2 [wherein M1 represents an element selected from Ba, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Na and Ca; M2 represents at least one element selected from Mg, Ba, Ca, Sr, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Na, Sc, Y, Hf, Bi and Ag; M3 represents at least one element selected from V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Zr, Nb, Mo, Ru, Rh, Pd, Al, Si, P, Ga, Ge, In, Sn, Sb and Te; and x, y1, y2 and z satisfy the following requirements: 0≦x≦0.5, 0≦y1<0.31, 1.4
US08030230B2	Flame-retardant leather-like sheet and process for producing the same The present invention relates to a flame-retardant leather-like sheet having a soft hand, excellent surface touch and excellent appearance, which includes an entangled nonwoven fabric of microfine polyester fibers having an average single-fiber fineness of 0.5 dtex or less, and an elastic polymer contained inside the nonwoven fabric, wherein a flame-retardant is exhausted into the elastic polymer and wherein a flame retarder solution containing bubbles forcibly formed is applied to a back surface of the leather-like sheet so that the flame retarder is present in a region extending from the back surface to an inside of the leather-like sheet but is not present on side of a front surface of the leather-like sheet.
US08030227B2	Photocurable fixture for orthopedic surgery A photocurable fixture for orthopedic surgery has a base material and a photocurable resin retained in the base material and containing a urethane (meth)acrylate oligomer and a photopolymerization initiator which absorbs a light within a range of 400 to 700 nm. The urethane (meth)acrylate oligomer being represented by the following formula (I), where A denotes a diisocyanate residue, and each of X and Y denotes a residue obtained by removing a hydroxy group from a (meth)acrylate having a hydroxy group. In formula (I) at least 40 mol % of X and Y is a residue obtained by removing a hydroxy group from a (meth)acrylate having a hydroxy group represented by the following formula (II), where in Formula (II) each of R1 to R6 denotes a hydrogen atom or a methyl group.
US08030226B2	Wet wipes having a liquid wipe composition with anti-adhesion component The present disclosure generally relates to wet wipes having liquid wipe compositions that including an anti-adhesion component that reduces sheet-to-sheet adhesion, improves the stack height, increases flexibility and maintains strength in the wet wipe. The liquid wipe compositions include an organopolysiloxane having the following structure: wherein p+q=0 to 2000, R1 is independently selected from a monovalent hydrocarbon group or hydroxyl group, and R2 and R3 are independently selected from a monovalent hydrocarbon group, a hydroxyl group, a monovalent hydrocarbon group functional in amine, a monovalent hydrocarbon group functional in polyether, a monovalent hydrocarbon group functional in quaternary, and a monovalent hydrocarbon group functional in polyampholyte.
US08030224B2	Manufacturing method of semiconductor device, semiconductor device, communication apparatus, and semiconductor laser A method of manufacturing a semiconductor device including a semiconductor layer and a dielectric layer deposited on the semiconductor layer, including: forming the semiconductor layer; performing a surface treatment for removing a residual carbon compound, on a surface of the semiconductor layer formed; forming a dielectric film under a depositing condition corresponding to a surface state after the surface treatment, on at least a part of the surface of the semiconductor layer on which the surface treatment has been performed; and changing a crystalline state of at least a partial region of the semiconductor layer by performing a heat treatment on the semiconductor layer on which the dielectric film has been formed.
US08030220B2	Plasma treatment of a semiconductor surface for enhanced nucleation of a metal-containing layer A method for forming a dielectric layer is provided. The method may include providing a semiconductor surface and etching a thin layer of the semiconductor substrate to expose a surface of the semiconductor surface, wherein the exposed surface is hydrophobic. The method may further include treating the exposed surface of the semiconductor substrate with plasma to neutralize a hydrophobicity associated with the exposed surface, wherein the exposed surface is treated using plasma with a power in a range of 100 watts to 500 watts and for duration in a range of 1 to 60 seconds. The method may further include forming a metal-containing layer on a top surface of the plasma treated surface using an atomic layer deposition process.
US08030217B2	Simplified pitch doubling process flow A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.
US08030211B2	Methods for forming bit line contacts and bit lines during the formation of a semiconductor device A method for forming a semiconductor device comprises forming first and second bit lines at different levels. Forming the bit lines at different levels increases processing latitude, particularly the spacing between the bit lines which, with conventional processes, may strain photolithographic limits. A semiconductor device formed using the method, and an electronic system comprising the semiconductor device, are also described.
US08030208B2	Bonding method for through-silicon-via based 3D wafer stacking There is described a bonding method for through-silicon-via bonding of a wafer stack in which the wafers are formed with through-silicon-vias and lateral microchannels that are filled with solder. To fill the vias and channels the wafer stack is placed in a soldering chamber and molten solder is drawn through the vias and channels by vacuum. The wafers are held together by layers of adhesive during the assembly of the wafer stack. Means are provided for local reheating of the solder after it has cooled to soften the solder to enable it to be removed from the soldering chamber.
US08030203B2	Method of forming metal line of semiconductor device A semiconductor device and a method of forming a metal line of a semiconductor device includes a first insulating layer formed over a semiconductor substrate an etch-stop layer formed over the first insulating layer, contact holes formed by etching the etch-stop layer and the first insulating layer, Contact plugs formed within the contact holes and a second insulating layer formed over the contact plugs and the etch-stop layer. The second insulating layer is etched in order to form trenches through which the contact plugs are exposed. Metal lines are formed within the trenches. Accordingly, since a hard mask with a high dielectric constant does not remain between the metal lines, the capacitance of the metal lines can be reduced.
US08030202B1	Temporary etchable liner for forming air gap An exemplary method lines the sidewalls of a first opening with a sacrificial material and then fills the first opening with a metallic conductor in a manner such that the metallic conductor contacts the substrate. Next, the method selectively removes the sacrificial material, to create at least one “second” opening along the metallic conductor within the first opening. The method selectively removes portions of the first insulator layer through the second opening to leave at least one air gap between the metallic conductor and the first insulator layer in the lower region of the second opening.
US08030201B2	Semiconductor device and method of manufacturing the same A first electronic circuit component and a second electronic circuit component are electrically connected to an electro-conductive member via a first solder and a second solder, respectively. The electro-conductive member is formed in a resin film. The electro-conductive member is configured as containing a second diffusion barrier metal film. The second diffusion barrier metal film prevents diffusion of the second solder. Between the electro-conductive member and the first solder, a first diffusion barrier metal film is provided. The first diffusion barrier metal film prevents diffusion of the first solder. On the first surface of the resin film and on the electro-conductive member, an adhesive metal film is formed so as to contact with the resin film and the electro-conductive member. The adhesive metal film has stronger adhesiveness to the resin film than either of those of the first solder and the first diffusion barrier metal film.
US08030199B2	Transistor fabrication method A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. A variety of silicided and non-silicided) structures may be formed.
US08030197B2	Recessed channel array transistor (RCAT) in replacement metal gate (RMG) logic flow Embodiments of the invention relate to a method of fabricating logic transistors using replacement metal gate (RMG) logic flow with modified process to form recessed channel array transistors (RCAT) on a common semiconductor substrate. An embodiment comprises forming an interlayer dielectric (ILD) layer on a semiconductor substrate, forming a first recess in the ILD layer of a first substrate region, forming a recessed channel in the ILD layer and in the substrate of a second substrate region, depositing a first conformal high-k dielectric layer in the first recess and a second conformal high-k dielectric layer in the recessed channel, and filling the first recess with a first gate metal and the recessed channel with a second gate metal.
US08030195B2	TFT substrate and method for manufacturing TFT substrate An object of the invention is to provide a TFT substrate and a method for producing a TFT substrate which is capable of drastically reducing the production cost by decreasing the number of steps in the production process and improving production yield. A TFT substrate includes: a substrate; a gate electrode and a gate wire formed above the substrate; a gate insulating film formed above the gate electrode and the gate wire; a first oxide layer formed above the gate insulating film which is formed at least above the gate electrode; and a second oxide layer formed above the first oxide layer; wherein at least a pixel electrode is formed from the second oxide layer.
US08030194B2	Spray method for producing semiconductor nano-particles A method is provided for producing semiconductor nanoparticles comprising: (i) dissolving a semiconductor compound or mixture of semiconductor compounds in a solution; (ii) generating spray droplets of the resulting solution of semiconductor compound(s); (iii) vaporizing the solvent of said spray droplets, consequently producing a stream of unsupported semiconductor nanoparticles; and (iv) collecting said unsupported semiconductor nanoparticles on a support.
US08030191B2	Method of manufacturing micro structure, and method of manufacturing mold material Disclosed herein are a method of producing microstructure and a method of producing mold, the methods permitting production of much smaller pores than before in an atmosphere where impurities are negligible and also permitting production of microstructures having a smaller size and a higher crystallinity than before with the help of the pores. The method of producing microstructure comprises a step of making pores (4) in a substrate (1) to become a mold (5) by irradiation with a focused energy beam (3) and a step of growing a microstructure (8) in the thus made pores (4). The method of producing a mold includes a step of making pores (4) by irradiating a substrate (1) to become a mold (5) with a focused energy beam (3).
US08030188B2	Methods of forming a compound semiconductor device including a diffusion region Provided is a method of forming a compound semiconductor device. In the method, a dopant element layer is formed on an undoped compound semiconductor layer. An annealing process is performed to diffuse dopants in the dopant element layer into the undoped compound semiconductor layer, thereby forming a dopant diffusion region. A rapid cooling process is performed using liquid nitrogen with respect to the substrate having the dopant diffusion region.
US08030187B2	Method for manufacturing semiconductor device A substrate is exposed to a plasma generated from a gas containing an impurity, thereby doping a surface portion of the substrate with the impurity and thus forming an impurity region. A predetermined plasma doping time is used, which is included within a time range over which a deposition rate on the substrate by the plasma is greater than 0 nm/min and less than or equal to 5 nm/min.
US08030186B2	Large-area nanoenabled macroelectronic substrates and uses therefor A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.
US08030180B2	Method of manufacturing a semiconductor device A semiconductor device is manufactured in a silicon-on-insulator (SOI) wafer having an silicon active layer, a buried oxide layer, and a supporting substrate layer. Before the wafer is diced into chips along scribe lines, the silicon active layer is selectively etched to form trenches surrounding the scribe lines. The wafer is then diced using a dicing apparatus having a blade width smaller than the width of the trenches. The dicing blade accordingly does not make contact with the silicon active layer, which is particularly vulnerable to chipping.
US08030175B2	Method of bonding selected integrated circuit to adhesive substrate A method of bonding an integrated circuit to an adhesive substrate. The integrated circuit is one of a plurality of integrated circuits, each having a respective frontside releasably attached to a film frame tape supported by a wafer film frame. The method includes the steps of: (a) selecting one of the integrated circuits for bonding to the adhesive substrate; (b) positioning the adhesive substrate at a backside of the selected integrated circuit; (c) positioning a bonding tool on a zone of the film frame tape, the zone being aligned with the selected integrated circuit; and (d) applying a bonding force from the bonding tool through the film frame tape and the selected integrated circuit onto the adhesive substrate, so as to bond the backside of the selected integrated circuit to the substrate.
US08030169B2	SOI substrate and manufacturing method thereof An object is to provide an SOI substrate provided with a semiconductor layer which can be used practically even when a glass substrate is used as a base substrate. Another object is to provide a semiconductor device having high reliability using such an SOI substrate. An altered layer is formed on at least one surface of a glass substrate used as a base substrate of an SOI substrate to form the SOI substrate. The altered layer is formed on at least the one surface of the glass substrate by cleaning the glass substrate with solution including hydrochloric acid, sulfuric acid or nitric acid. The altered layer has a higher proportion of silicon oxide in its composition and a lower density than the glass substrate.
US08030167B2	Varied impurity profile region formation for varying breakdown voltage of devices Methods are disclosed for forming a varied impurity profile for a collector using scattered ions while simultaneously forming a subcollector. In one embodiment, the invention includes: providing a substrate; forming a mask layer on the substrate including a first opening having a first dimension; and substantially simultaneously forming through the first opening a first impurity region at a first depth in the substrate (subcollector) and a second impurity region at a second depth different than the first depth in the substrate. The breakdown voltage of a device can be controlled by the size of the first dimension, i.e., the distance of first opening to an active region of the device. Numerous different sized openings can be used to provide devices with different breakdown voltages using a single mask and single implant. A semiconductor device is also disclosed.
US08030165B2	Poly gate etch method and device for sonos-based flash memory A method for forming flash memory devices is provided. The method includes providing a semiconductor substrate, which comprises a silicon material and has a periphery region and a cell region. The method further includes forming an isolation structure between the cell region and the periphery region. Additionally, the method includes forming an ONO layer overlying the cell region and the periphery region. Furthermore, the method includes removing the ONO layer overlying the periphery region to expose silicon material in the periphery region. The method also includes forming a gate dielectric layer overlying the periphery region, while protecting the ONO layer in the cell region. In addition, the method includes forming a polysilicon layer overlying the cell region and the periphery region.
US08030164B2	Compound semiconductor structure A method for manufacturing a compound semiconductor structure, includes (a) selecting a conductive SiC substrate in accordance with color and resistivity and (b) epitaxially growing a GaN series compound semiconductor layer on the selected conductive SiC substrate. The step (a) preferably selects a conductive SiC substrate whose main color is green, whose conductivity type is n-type and whose resistivity is 0.08 Ωcm to 1×105 Ωcm, or whose main color is black, whose conductivity type is p-type and whose resistivity is 1×103 Ωcm to 1×105 Ωcm, or whose main color is blue, whose conductivity type is p-type and whose resistivity is 10 Ωcm to 1×105 Ωcm. The step (b) preferably includes (b-1) growing an AlInGaN layer having a thickness not thinner than 10 μm on the conductive SiC substrate by hydride VPE.
US08030162B2	Silicon carbide semiconductor device and manufacturing method thereof A silicon carbide semiconductor device is fabricated by forming an amorphous layer in a semiconductor layer of a silicon carbide substrate at a boundary between a cell forming area and an outer peripheral area, forming an outer peripheral insulating film over the semiconductor layer in the outer peripheral area, and thermally oxidizing an upper surface of the semiconductor layer in the cell forming area and at least a portion of the amorphous layer exposed by the outer peripheral insulating film to form a gate oxide film including a stepped portion of increased thickness adjacent the outer peripheral insulating film. The gate electrode layer is then formed which extends from the gate oxide film to above the outer peripheral insulating film.
US08030160B2	Methods of forming NAND flash memory with fixed charge A string of nonvolatile memory cells connected in series includes fixed charges located between floating gates and the underlying substrate surface. Such a fixed charge affects distribution of charge carriers in an underlying portion of the substrate and thus affects threshold voltage of a device. A fixed charge layer may extend over source/drain regions also.
US08030158B2	Method for fabricating contacts in semiconductor device Disclosed is a method for fabricating a contact in a semiconductor device, including: obtaining a pattern layout including bit lines arranged across a cell matrix region of a semiconductor substrate, cell storage node contacts arranged to pass through a portion of a first interlayer insulation layer between the bit lines, and dummy storage node contacts additionally arranged in an end of the arrangement of the cell storage node contacts; and forming the cell storage node contacts and the dummy storage node contacts using the pattern layout.
US08030155B2	Schottky diode with minimal vertical current flow A method of forming a rectifying diode. The method comprises providing a first semiconductor region of a first conductivity type and having a first dopant concentration and forming a second semiconductor region in the first semiconductor region. The second semiconductor region has the first conductivity type and having a second dopant concentration greater than the first dopant concentration. The method also comprises forming a conductive contact to the first semiconductor region and forming a conductive contact to the second semiconductor region. The rectifying diode comprises a current path, and the path comprises: (i) the conductive contact to the first semiconductor region; (ii) the first semiconductor region; (iii) the second semiconductor region; and (iv) the conductive contact to the second semiconductor region. The second semiconductor region does not extend to a layer buried relative to the first semiconductor region.
US08030152B2	Method of fabricating trench-constrained isolation diffusion for semiconductor devices A semiconductor substrate includes a pair of trenches filled with a dielectric material. Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices can be spaced more closely together on the substrate, and the packing density of the devices can be increased. Also trench constrained doped region diffuse faster and deeper than unconstrained diffusions, thereby reducing the time and temperature needed to complete a desired depth diffusion. The technique may be used for semiconductor devices such as bipolar transistors as well as isolation regions that electrically isolate the devices from each other. In one group of embodiments, a buried layer is formed at an interface between an epitaxial layer and a substrate, at a location generally below the dopant in the mesa. When the substrate is subjected to thermal processing, the buried layer diffuses upward, the dopant in the mesa diffuses downward until the two dopants merge to form an isolation region or a sinker extending downward from the surface of the epitaxial layer to the buried layer. In another embodiment, dopant is implanted between dielectrically filled trenches at a high energy up to several MeV, then diffused, combining the benefits of deep implantation and trenched constrained diffusion to achive deep diffusions with a minimal thermal budget.
US08030150B2	Method of fabricating non-volatile memory integrated circuit device and non-volatile memory integrated circuit device fabricated using the same A method of fabricating a non-volatile memory integrated circuit device and a non-volatile memory integrated circuit device fabricated by using the method are provided. A device isolation region is formed in a substrate to define a cell array region and a peripheral circuit region. A plurality of first and second pre-stacked gate structures is formed in the cell array region, and each has a structure in which a lower structure, a conductive pattern and a first sacrificial layer pattern are stacked. Junction regions are formed in the cell array region. Spacers are formed on side walls of the first and second pre-stacked gate structures. A second sacrificial layer pattern filling each space between the second pre-stacked gate structures is formed. The first sacrificial layer pattern is removed from each of the first and second pre-stacked gate structures. A damascene metal layer pattern is formed in each of spaces of the first and second pre-stacked gate structures from which the first sacrificial layer pattern is removed, thus completing first and second stacked gate structures. The second sacrificial layer pattern is removed. A stop layer is formed on top surfaces of the first stacked gate structures, top surfaces and side walls of the second stacked gate structures, and a top surface of the substrate.
US08030149B2	Method for manufacturing semiconductor device Embodiments relate to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device capable of simplifying a silicide manufacturing process using a photo resist overhang structure. According to embodiments, a surface is subjected to a monochlorobenzene coating processing to cure the surface of the exposed photo resist so as not to react with developing solution and such a processed photo resist is developed to make the lower of the photo resist in the overhang structure so as to form an accurate pattern according to the clear removal of the oxide film, making it possible to simply manufacture the silicide and the non-silicide without performing an etching process by a subsequent cobalt deposition process.
US08030148B2	Structured strained substrate for forming strained transistors with reduced thickness of active layer In a strained SOI semiconductor layer, the stress relaxation which may typically occur during the patterning of trench isolation structures may be reduced by selecting an appropriate reduced target height of the active regions, thereby enabling the formation of transistor elements on the active region of reduced height, which may still include a significant amount of the initial strain component. The active regions of reduced height may be advantageously used for forming fully depleted field effect transistors.
US08030147B2	Method for manufacturing thin film transistor and display device including the thin film transistor To provide a method for manufacturing a thin film transistor with excellent electric characteristics and high reliability and a display device including the thin film transistor. A gate insulating film is formed over a gate electrode, crystal nuclei is formed over the gate insulating film using fluorosilane and silane, and crystal growth is generated using the crystal nuclei as nuclei to form a microcrystalline semiconductor film, so that crystallinity at an interface between the gate insulating film and the microcrystalline semiconductor film is improved. Next, a thin film transistor is manufactured using the microcrystalline semiconductor film having crystallinity improved at the interface between the gate insulating film and the microcrystalline semiconductor film as a channel formation region.
US08030146B2	Organic light emitting diode (OLED) display panel and method of forming polysilicon channel layer thereof An organic light emitting diode (OLED) display panel and a method of forming a polysilicon channel layer thereof are provided. In the method, firstly, a substrate having a polysilicon layer disposed thereon is provided. Then, a dopant atom not selected from the IIIA group and the VA group is doped inside the polysilicon layer to form a polysilicon channel layer.
US08030137B2	Flexible interposer for stacking semiconductor chips and connecting same to substrate A semiconductor device with a first (101) and a second (111) semiconductor chip assembled on an insulating flexible interposer (120). The interposer, preferably about 25 to 50 μm thick, has conductive traces (121), a central planar rectangular area and on each side of the rectangle a wing bent at an angle from the central plane. The central area has metal studs (122, 123) on the top and the bottom surface, which match the terminals of the chips, further conductive vias of a pitch center-to-center about 50 μm or less. The side wings have contact pads (130) with metallic connectors (131) on the bottom surface; the connectors may be solder balls, metal studs, or anisotropic conductive films. The second chip is adhesively attached to a substrate, whereby the interposer faces away from the substrate. The interposer side wings have a convex bending (150) downwardly along the second chip and a concave bending (151) over the substrate; the side wing connectors are attached to the matching substrate sites.
US08030136B2	Semiconductor device and method of conforming conductive vias between insulating layers in saw streets A semiconductor device is made by disposing a plurality of semiconductor die on a carrier and creating a gap between each of the semiconductor die. A first insulating material is deposited in the gap. A portion of the first insulating material is removed. A conductive layer is formed over the semiconductor die. A conductive lining is conformally formed on the remaining portion of the first insulating material to form conductive via within the gap. The conductive vias can be tapered or vertical. The conductive via is electrically connected to a contact pad on the semiconductor die. A second insulating material is deposited in the gap over the conductive lining. A portion of the conductive via may extend outside the first and second insulating materials. The semiconductor die are singulated through the gap. The semiconductor die can be stacked and interconnected through the conductive vias.
US08030133B2	Method of fabricating a bonded wafer substrate for use in MEMS structures A method of manufacturing a semiconductor device includes providing first and second semiconductor substrates, each having first and second main surfaces opposite to one another. A roughened surface is formed on at least one of the first main surface of the first semiconductor substrate and the second main surface of the second semiconductor substrate. A dielectric layer is formed on the first main surface of the semiconductor substrate and the second semiconductor substrate is disposed on the dielectric layer opposite to the first semiconductor substrate. The second main surface of the second semiconductor substrate contacts the dielectric layer.
US08030130B2	Phase change memory device with plated phase change material A method for fabricating a phase change memory device including memory cells includes patterning a via to a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, lining each via with a conformal conductive seed layer to the contact surface, forming a dielectric layer covering the conductive seed layer, and etching a center region of each via to the contact surface to expose the conformal conductive seed layer at the contact surface. The method further includes electroplating phase change material on exposed portions of the conformal conductive seed layer, recessing the phase change material within the center region forming a conductive material that remains conductive upon oxidation, on the recessed phase change material, oxidizing edges of the conformal conductive seed layer formed along sides of each via, and forming a top electrode over each memory cell.
US08030129B2	Method of fabricating nonvolatile memory device A method of manufacturing a nonvolatile memory device including forming on a lower insulating layer a first sacrificial pattern having first openings extending in a first direction, forming a second sacrificial pattern having second openings extending in a second direction on the lower insulating layer and the first sacrificial pattern wherein the second openings intersect the first openings, etching the lower insulating layer using the first and second sacrificial patterns to form a lower insulating pattern having contact holes defined by a region where the first and second openings intersect each other, forming a bottom electrode in the contact holes, and forming a variable resistance pattern on the lower insulating pattern so that a portion of the variable resistance pattern connects to a top surface of the bottom electrode.
US08030126B2	Printing process for enhanced jetted performance of semiconductor layer Exemplary embodiments provide materials and processes for forming organic semiconductor features by heating a liquid composition containing semiconductor particles into a Newtonian solution for a uniform deposition.
US08030125B2	Organic thin-film transistor substrate, its manufacturing method, image display panel, and its manufacturing method The present invention is a method for manufacturing an organic thin-film transistor substrate including an organic thin-film transistor as a transistor element, and an object of the invention is to provide a manufacturing method capable of forming a bank in a smaller number of steps. The method for manufacturing the organic thin-film transistor substrate of the present invention, in which an organic thin-film transistor is formed in a first region on a substrate, a second region for forming a light-emitting element in abutment with the first region is included, and a bank part is formed in a peripheral part of the second region, is characterized by including: a first step of forming the organic thin-film transistor in the first region on the substrate and forming at least one of the gate insulation layer and the organic semiconductor layer included by this organic thin-film transistor as far as the second region, thereby forming, in the second region, a bank precursor layer composed of a laminated structure formed on the second region; and a second step of removing the regions of the bank precursor layer other than the peripheral part, thereby forming the bank part made of the remaining bank precursor layer.
US08030122B1	Method and apparatus for reduction of non-adaptive signals in photo-EMF sensors A method and apparatus for a photoinduced electromotive force sensor. The sensor has an active substrate formed of a semi-insulating photoconductor with sufficient carrier trap density to form an effective charge grating and pairs of electrodes disposed on the active substrate, where the sensor is configured to reduce the photovoltaic effect caused by the incident light in the vicinity of the electrodes. The shape or composition of the electrodes may be selected to reduce the photovoltaic effect or the electrodes may be disposed on the substrate to average out the photovoltaic effect arising from each one of the electrodes.
US08030121B2	Manufacture of photovoltaic devices A method and apparatus for depositing a film on a substrate includes subjecting material to an energy beam.
US08030120B2	Hybrid window layer for photovoltaic cells A novel photovoltaic solar cell and method of making the same are disclosed. The solar cell includes: at least one absorber layer which could either be a lightly doped layer or an undoped layer, and at least a doped window-layers which comprise at least two sub-window-layers. The first sub-window-layer, which is next to the absorber-layer, is deposited to form desirable junction with the absorber-layer. The second sub-window-layer, which is next to the first sub-window-layer, but not in direct contact with the absorber-layer, is deposited in order to have transmission higher than the first-sub-window-layer.
US08030119B2	Integrated method and system for manufacturing monolithic panels of crystalline solar cells A method for fabricating a photovoltaic (PV) cell panel wherein all PV cells are formed simultaneously on a two-dimensional array of monocrystalline silicon mother wafers affixed to a susceptor is disclosed. Porous silicon separation layers are anodized in the surfaces of the mother wafers. The porous film is then smoothed to form a suitable surface for epitaxial film growth. An epitaxial reactor is used to grow n- and p-type films forming the PV cell structures. Contacts to the n- and p-layers are deposited, followed by gluing of a glass layer to the PV cell array. The porous silicon film is then separated by exfoliation in a peeling motion across all the cells attached together above, followed by attaching a strengthening layer on the PV cell array. The array of mother wafers may be reused multiple times, thereby reducing materials costs for the completed solar panels.
US08030116B2	CMOS image sensor and method for fabricating the same A CMOS image sensor and a method for fabricating the same are disclosed. The method includes forming a plurality of color filters on a substrate, each color filter having a curvature, and forming microlenses on the color filters that each has a radius of curvature that varies with the wavelength of the color filter on which it is formed.
US08030114B2	Method and structure to reduce dark current in image sensors A method to fabricate an image sensor includes providing a semiconductor substrate having a pixel region and a periphery region, forming a light sensing element on the pixel region, and forming at least one transistor in the pixel region and at least one transistor in the periphery region. The step of forming the at least one transistor in the pixel region and periphery region includes forming a gate electrode in the pixel region and periphery region, depositing a dielectric layer over the pixel region and periphery region, partially etching the dielectric layer to form sidewall spacers on the gate electrode and leaving a portion of the dielectric layer overlying the pixel region, and forming source/drain (S/D) regions by ion implantation.
US08030110B2	Nitride semiconductor light-emitting device and method for fabrication thereof A nitride semiconductor laser device uses a substrate with low defect density, contains reduced strains inside a nitride semiconductor film, and thus offers a satisfactorily long useful life. On a GaN substrate (10) with a defect density as low as 106 cm−2 or less, a stripe-shaped depressed portion (16) is formed by etching. On this substrate (10), a nitride semiconductor film (11) is grown, and a laser stripe (12) is formed off the area right above the depressed portion (16). With this structure, the laser stripe (12) is free from strains, and the semiconductor laser device offers a long useful life. Moreover, the nitride semiconductor film (11) develops reduced cracks, resulting in a greatly increased yield rate.
US08030108B1	Epitaxial growth of in-plane nanowires and nanowire devices Exemplary embodiments provide semiconductor nanowires and nanowire devices/applications and methods for their formation. In embodiments, in-plane nanowires can be epitaxially grown on a patterned substrate, which are more favorable than vertical ones for device processing and three-dimensional (3D) integrated circuits. In embodiments, the in-plane nanowire can be formed by selective epitaxy utilizing lateral overgrowth and faceting of an epilayer initially grown in a one-dimensional (1D) nanoscale opening. In embodiments, optical, electrical, and thermal connections can be established and controlled between the nanowire, the substrate, and additional electrical or optical components for better device and system performance.
US08030107B2	Electro-luminescent device and method for manufacturing the same An electro-luminescent device includes a transparent substrate, a black matrix on the transparent substrate defining a plurality of spaces, a plurality of color representing layers each arranged in respective ones of the spaces, an overcoat layer on the black matrix and the color representing layers, a plurality of first electrodes disposed on the overcoat layer in a first direction with respect to the color representing layers, a phosphor layer formed on the plurality of first electrodes, an insulating film on the phosphor layer, and a plurality of second electrodes disposed on the insulating film in a second direction perpendicular to the first direction.
US08030105B1	Method of fabricating a light emitting diode chip having phosphor coating layer A method of fabricating light emitting diode chips having a phosphor coating layer comprises providing a substrate having a plurality of light emitting diodes formed thereon; forming a conductive bump on at least one of the plurality of light emitting diodes; forming a phosphor coating layer over the substrate and the light emitting diodes; cutting the phosphor coating layer by a point cutter to remove an upper portion of the phosphor coating layer, so as to reduce a thickness of the phosphor coating layer and expose the conductive bump; and forming a plurality of individual light emitting diode chips having the phosphor coating layer by separating the plurality of light emitting diodes.

1 2 3 4 5 6 7 8 9 10