| Document | Document Title |
|---|---|
| US07969895B2 |
Switch apparatus and network system
A switch apparatus providing with a loop detection function sets a port identification to a port which activates the loop detection function, only receives the loop detection frame by a high-order port in the switch apparatus connected with a backbone network or a high-order switch apparatus on the basis of the port identification set previously, and controls an inactivation of a sending source low-order port that sent the loop detection frame, when the loop detection frame is received by the high-order port. |
| US07969892B2 |
Tunneling loop detection control apparatus
Disclosed is a technique whereby a tunnel entry point, which encapsulates a packet (generates a tunnel packet), can detect the presence of a tunneling loop causing a packet to loop the same path while encapsulated. According to this technique, upon receipt of a packet from a source node (source) 1100, TEP (tunnel entry point) 1120 inserts it into a tunnel packet header for encapsulation. Upon receipt of tunnel packets from TEP 1120 and TEP 1140, each of TEP 1140 and TEP 1160 copies the identifier of the original tunnel packet header to a new tunnel packet header for encapsulation. When this tunnel packet returns to TEP 1120 due to a tunneling loop, the tunneling loop is detected by referring to the identifier in the received tunnel packet. |
| US07969889B2 |
Route and link evaluation in wireless mesh communications networks
Methods and systems for providing a network and routing protocol for utility services are disclosed. A method includes discovering a utility network. Neighboring nodes are discovered and the node listens for advertised routes for networks from the neighbors. The node is then registered with one or more utility networks, receiving a unique address for each network registration. Each upstream node can independently make forwarding decisions on both upstream and downstream packets, i.e., choose the next hop according to the best information available to it. The node can sense transient link problems, outage problems and traffic characteristics. Information is used to find the best route out of and within each network. Each network node maintains multi-egress, multi-ingress network routing options both for itself and the node(s) associated with it. The node is capable of several route maintenance functions utilizing the basic routing protocol and algorithms. |
| US07969886B1 |
Bandwidth allocation for hierarchical telecommunications networks
A method and system for bandwidth allocation over a hierarchical telecommunications network having a first hierarchical level of at least two trunks and a second hierarchical level of at least two flows in each trunk, the method including allocating bandwidth to each of the trunks; and separately allocating the bandwidth allocated to each trunk to the flows in that trunk. |
| US07969885B2 |
Adjusting the degree of filling of a jitter buffer
A method and arrangement for adjusting the degree of filling of a jitter buffer in a network element receiving digital data. To the jitter buffer, there is connected a read-out unit for reading digital data from the jitter buffer. In the method, there is composed a time reserve indicator for the received protocol unit, the time reserve indicator being essentially the difference of an order indicator connected to the protocol unit and an order indicator connected to the operational cycle of the read-out unit. The time reserve indicator of the protocol unit indicates whether the protocol unit was received in good time, in order to ensure that the digital data is in the jitter buffer when the digital data is in turn to be read out. The degree of filling of a jitter buffer is adjusted on the basis of time reserve indicators composed for the received protocol units. |
| US07969882B2 |
Packet transfer rate monitoring control apparatus, method, and program
In a packet communication network in which the minimum guaranteed rate and maximum limiting rate of packet transfer are contracted for each service, this invention classifies flows corresponding to received packets into group 1 to which a flow whose packet transfer rate is less than the minimum guaranteed rate belongs, group 2 to which a flow whose packet transfer rate is equal to or higher than the minimum guaranteed rate and less than the maximum limiting rate belongs, and group 3 to which a flow whose packet transfer rate exceeds the maximum limiting rate belongs. |
| US07969879B2 |
Supporting network self-healing and optimization
A method of managing a network includes configuring nodes and applications of the network to refer to the same framework of predefined network capabilities. Each of the applications is configured to implement one or more of the capabilities. Each of the applications also is configured to negotiate, as to each of the capabilities, with the nodes to obtain a network resource to support the capabilities. Each node is configured to negotiate, after an application obtains a network resource, with other nodes to optimize network resource allocation. This method provides a framework for application self-healing and network optimization that can improve network performance. |
| US07969876B2 |
Method of determining path maximum transmission unit
Network endpoints using TCP/IP operate to determine the maximum transmission unit (MTU) of the path between them. This determination is done so as to avoid the expensive IP fragmentation that will occur when transmitting links with a smaller MTU size. The standard method of determining the path MTU (PMTU) has several known deficiencies, including: inefficient use of bandwidth as proper operation will likely result in the loss of one or more packets and difficulty of implementation as the reverse channel communication mechanism, reception of ICMP messages indicating the discarding of unfragmentable packets, is frequently blocked by firewalls and other security apparatus.A method of determining the PMTU between intermediate proxies is disclosed that does not require reception of ICMP messages or the inefficient use of bandwidth due to the presumed dropping of packets with valid data. |
| US07969870B2 |
Line accommodating device
A line accommodating device for accommodating lines of a first communication network and a second communication network, the line accommodating device includes an interface connecting to the first communication network; a connecting block for connecting to the interface; and a plurality of relay modules connecting to the connecting block and the second communication network, respectively, each of the relay module including a reporting unit for notifying the connected relay modules via the connecting block of identification information of the relay module's own, an obtaining unit for obtaining identification information of the connected relay modules via the connecting block, and a controller including processes of determining at least one connection target of the relay module in the properly obtained identification information of the relay module by the obtaining unit, and controlling for switching the connection target of the relay module in accordance with a determined result of the determining. |
| US07969865B2 |
Network system of recovering routing information
When protection processing is applied after a fault in the optical switching unit while the path control unit is restarting. In network systems comprising a path control unit for setting the paths, and a data transmission unit coupled to the path control unit; the data transmission unit changes the path information, stores path information before and after the fault was detected, and transmits the path information from before or after fault detection to the path control unit, and decides either of the transmitted path information based on an internal status; and the path control unit stores the path information sent from the data transmission unit, and after restarting, receives path information from the data transmission unit and, acquires path information stored in the path control units controlled by the adjacently connected data transmission units and is restored to operation with path information from before restarting. |
| US07969863B2 |
Directed cost protocol
One embodiment disclosed relates to a method of cost determination for paths between switches in a mesh. A set of paths between each pair of the mesh switches is defined, and start-up costs for the paths are calculated. The costs for the previously defined paths are subsequently recalculated using a directed cost protocol. The directed cost protocol may include generating at a first switch a cost packet with path information associated with a specific path, and unlasting the cost packet via the specific path to a second switch. |
| US07969862B1 |
Cycle-based restoration in mesh networks utilizing bandwidth and flow considerations
A two step method for determining restoration cycles for a mesh network includes generating a set of possible restoration cycles, and selecting a subset of low-cost restoration cycles on the network. The cost of a restoration cycle may be based, in part, on the availability of capacity on the link to restore traffic with and/or without interference, and network policy. Enabling the restoration cycles to be determined based on the bandwidth capacity of the restoring link, the flows carried by the other link, and other network policy considerations enables embodiments of the invention to account for traffic class, priority, and other traffic considerations when selecting restoration cycles on the network. Identifying arcs on the network with relatively high cost restoration cycles allows portions of the network to be targeted for increased capacity. |
| US07969861B2 |
Method of transmitting control signals in wireless communication system
A method of transmitting control signals in a wireless communication system is provided. The method comprises allocating at least one control signal in a control channel region comprising a plurality of tiles, each tile consisting of a plurality of consecutive subcarriers in a frequency domain on a plurality of orthogonal frequency division multiplexing (OFDM) symbols in a time domain and transmitting the at least one control signal, wherein the number of the at least one control signal is determined based on the number of available sequences for the control channel region and the number of bit carried by each control signal. |
| US07969858B2 |
Wireless terminal methods and apparatus for use in wireless communications systems supporting different size frequency bands
More efficient utilization of available bandwidth is implemented in an OFDM wireless communication system. The partitions of bandwidth may be of different sizes and may be different from the original system design parameters. Basic system structure such as the number of tones used and the number of OFDM symbol times in a slot is maintained throughout the system. Bandwidth is varied by adjusting the inter-tone spacing or bandwidth associated with a single tone. As the inter-tone spacing is increased, the OFDM symbol transmission time is decreased following an inverse proportional relationship. A wireless communications device, during a first period of time transmits signals using a first uplink frequency band of a first number of uniformly distributed tones and during a second period of time transmits signals using a second uplink frequency band of a second number of uniformly distributed tones, the second number being the same as the first number, the second frequency band being wider than the first frequency band. |
| US07969856B2 |
Optical encoding disc having light converging portions and light diverging portions
An exemplary optical encoding disc includes a plurality of concentric annular tracks. Each track includes a plurality of coding units. Each coding unit includes a light converging portion and a light diverging portion. The light converging portions and the light diverging portions are arranged alternately along a circumferential direction of the optical encoding disc. |
| US07969855B2 |
Read-only optical disc medium and method of fabricating the same
A read-only optical disc medium is disclosed. The disc medium includes: an information recording area in which information is recorded by means of an embossed pit array formed in a convexo-concave shape having a reflective layer deposited thereon; a test writing area which is used for test write recording of a mark formed by dissipating or decreasing the reflective layer; and an additional write area in which a record data string is formed of a mark by dissipating or decreasing the reflective layer under a recording condition decided in accordance with a result of test write recording performed in the test writing area. |
| US07969850B2 |
Optical element, optical pickup device comprising the same, and unnecessary light elimination method
The optical element comprises a first diffraction structure for generating three beams by diffracting light from a light source and a second diffraction structure that exhibits structural birefringence for a prescribed polarized light returning to the light source. The first diffraction structure is formed on a first face of a translucent optical base material and the second diffraction structure is formed on a second face of the optical base material. The optical base material, the first diffraction structure and the second diffraction structure are formed of a single material. |
| US07969849B2 |
Method of reading a fourier hologram recorded on a holographic storage medium and a holographic storage system
The invention relates to a method for reading a Fourier hologram recorded on a holographic storage medium with a holographic storage system. The method comprises the steps of: —calculating a characteristic value from a detected image of a reconstructed Fourier hologram in at least two relative positions of a reference beam and said storage medium, each of the characteristic values being indicative of a misalignment of the reference beam and said storage medium at the respective relative position, —calculating a servo value from the measured characteristic values, —determining an aligned relative position of said reference beam and said storage medium by means of a predetermined servo function using the calculated servo value, —setting the relative position of the reference beam and said storage medium to said aligned relative position, and—detecting an image at said aligned relative position. The invention also relates to a holographic storage system for reading a Fourier hologram recorded on a holographic storage medium, said system comprising reference beam generating means, storage medium receiving means and a detector for detecting a reconstructed hologram. The system further comprises a servo control unit for executing the method according to the invention. |
| US07969847B2 |
Disc apparatus
A disc apparatus comprising: a jitter-value detection unit configured to detect a jitter value based on a signal to be read from a medium; a defocus-value setting unit configured to set a defocus value for focusing an objective lens in the medium based on the jitter value; and a defocus-value adjusting unit configured to detect the jitter value every time the defocus value is changed stepwise within a predetermined range of the defocus value including a reference value of the defocus value, to obtain an optimum defocus value to be set for the defocus-value setting unit within a predetermined time period, based on a maximum jitter value and a minimum jitter value of the detected jitter values. |
| US07969846B2 |
Hologram recording and reproducing device and method for recording hologram
A hologram recording and reproducing device controls an optical beam output from an external cavity semiconductor laser to improve a diffraction efficiency. The hologram recording and reproducing device includes an external cavity laser, a photodiode, a laser drive circuit and a laser diode controller. The external cavity laser has a laser diode adapted to emit an optical beam that is used to generate data light and reference light with which a hologram recording medium is irradiated. The photodiode detects the amount of the optical beam output from the external cavity laser. The laser drive circuit supplies a current to the external cavity laser. The laser diode controller controls the laser drive circuit to ensure that a value obtained by integrating the detected intensity of the optical beam with respect to time over a predetermined period is equal to predetermined recording energy. |
| US07969841B2 |
Method and apparatus for recording management information medium and the recording medium
The write-once recording medium has a data structure for managing temporary defect management areas, TDMAs, of the recording medium, where each TDMA is for at least storing temporary defect management information. In one embodiment, the recording medium includes a TDMA access indicator, TAI, area for selectively storing data indicating which one of the TDMAs is currently in use. |
| US07969840B2 |
Recording method for optimizing an optimal recording power
A recording method for an optical disc having at least three recording layers (11, 12, 13, 14), in which test recording areas are formed in the odd-numbered recording layers (11, 13) and the even-numbered recording layers (12, 14) in positions that are mutually non-overlapping in the thickness direction of the optical disc, the test recording areas in the odd-numbered recording layers are formed in positions mutually aligned in the thickness direction, and the test recording areas in the even-numbered recording layers are formed in positions mutually aligned in the thickness direction. The time for test recording for determining the optimal recording power can be shortened. |
| US07969839B2 |
Apparatus and method for detecting an optimal writing power
A method and apparatus for accomplishing an OPC (optimal power calibration) at a test area secured in data recording area of a writable optical recording medium and detecting an optimal writing power appropriate to the test area. The method searches for a marginal area adjacent to a data section recorded on an optical recording medium, records test data on the marginal area discovered in the searching step while changing a writing power; and reproduces the test data recorded on the marginal area and determining an optimal writing power based upon the characteristics of the reproduction signal. The method and system can reduce delay time required to move an optical pickup inward and outward to accomplish the OPC operation and enhances writing characteristics since an optimal writing power is obtained from a test area which is very close to data area to record input data. |
| US07969838B2 |
Optical disk apparatus
An optical disk apparatus is provided which can: prevent an SNR deterioration attributable to an increase in read speed; overcome difficulty in separating a read signal and HF signal components; reduce laser noise; and maintain high reliability even during a high-speed read operation. An optical disk is irradiated with laser light pulsed by a high-frequency signal generated by a HF oscillator. The output of an optical detector which receives laser light reflected from the optical disk is converted into an electric pulse read signal using a current amplifier. The pulse read signal is converted into a temporally continuous read signal using a combination of an AD converter and a DA converter. |
| US07969836B2 |
Optical pickup apparatus
An optical pickup apparatus reads an information signal recorded on a recording surface of an optical disk along a track by projecting a light beam. Said optical pickup apparatus has: an objective lens for converging said light beam onto said recording surface; an objective lens moving device for moving said objective lens in a radial direction of said optical disk; and a divisional photosensing device for receiving return light reflected by said optical disk, in a plurality of divided regions. Said divisional photosensing device has: a first divisional photosensing device for dividing a first region including both edge portions in said radial direction of said return light, in two divided areas in said radial direction; a second divisional photosensing device for receiving a second region including both edge portions in a direction which perpendicularly crosses said radial direction of said return light, in two divided areas in said radial direction; and a third divisional photosensing device for receiving a third region including an almost center portion of said return light, in two divided areas in said radial direction. |
| US07969834B2 |
Optical pickup device having a structure providing efficient light usage
The optical pickup device according to the present invention includes: a light source which emits light at first, second and third wavelengths; an optical path combining unit which combines vectors of the light at the first, second and third wavelengths which is emitted by the light source, and matches optical axes of the light at the first wavelength and the light at the third wavelength; a light condensing unit which condenses the light from the optical path combining unit onto the optical information storage medium; a diffraction element which diffracts light at the first, second and third wavelength which is reflected from the optical information storage medium, in a first direction and a second direction respectively; a first photo detector which receives light at the first, second and third wavelength that is diffracted in the first direction by the diffraction element; a second photo detector which receives light at the first and third wavelength that is diffracted in the second direction by the diffraction element; and a third photo detector which receives light at the second wavelength that is diffracted in the second direction by the diffraction element. |
| US07969825B2 |
Backlash-compensating toothed moving part, gear assembly and use of this gear assembly
The invention relates to a backlash-compensating toothed moving part, for a precision gear assembly, particularly in clock-making, in which the backlash-compensating teeth each have a section extending symmetrically to both sides of the radius of said mobile passing the tip of said teeth with an elastic connection to said mobile to give said teeth a freedom of movement in the plane of the mobile, at least one tooth in two being a backlash-compensating tooth comprising stop means arranged to limit the freedom of movement as a function of the backlash in the gear assembly to be compensated for. |
| US07969824B2 |
Timepiece movement for driving a display element along a complex path and timepiece comprising such a movement
A timepiece, includes a frame supporting a drive element, a time base and drive trains pivotably mounted on the frame and arranged so as to drive at least one display train intended to carry an element displaying information, such as the time. The movement also includes a fixed gear, firmly attached to the frame, with which a toothed element of the display train is arranged to mesh, and a drive element having first and second kinematic links, respectively, with one of the drive trains and with the toothed element so as to drive the latter in translation in a first direction along the fixed gear. Preferably, the drive element is embodied in the form of a deformable element, and the movement also includes a retrograde mechanism for driving the toothed element rapidly in the opposite direction by means of the drive element. |
| US07969821B2 |
Method and system for locating a wave source within a defined area
A method and system for locating a sound source within a defined area in which the sound data is collected with a plurality of spaced apart microphones. The sound data received by the microphones is processed to form a cross spectral density matrix containing vectors of cross correlations and auto correlations of the sound data. A replica vector matrix containing sound data from at least one test sound at a plurality of predetermined locations within the defined area is then constructed. The sound data vectors in the cross spectral density matrix are then projected on the replica vectors in the replica vector matrix to obtain a probability of the location of the sound source at each predetermined location within the defined area. These probabilities form a distribution within the defined area in which the largest probability distribution correlates with the location of the sound source. |
| US07969812B2 |
Semiconductor control line address decoding circuit
Apparatus and method for decoding addresses of control lines in a semiconductor device, such as a solid state memory (SSM). In accordance with some embodiments, a switching circuit includes an array of switching devices coupled to 2N output lines and M input lines, wherein M and N are respective non-zero integers and each output line has a unique N-bit address. A decoder circuit coupled to the switching circuit divides the N-bit address for a selected output line into a plurality of multi-bit subgroup addresses, and asserts the M input lines in relation to respective bit values of said subgroup addresses to apply a first voltage to the selected output line and to concurrently apply a second voltage to the remaining 2N-1 output lines. |
| US07969810B2 |
256 Meg dynamic random access memory
A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes. |
| US07969809B2 |
Power consumption-oriented management of a storage system
A method of managing operation of a plurality of devices that includes receiving operational information that pertains to each of a plurality of device and managing operation of at least one of the plurality of devices. Each of the plurality of devices is configured to perform operations, the operations including sub-operations. The operation management includes associating parameters for a given sub-operation of a device based on 1) operational information pertaining to at least one of the plurality of devices and on 2) a maximum allowable current consumption level. Also provided is a system that includes a plurality of devices and a controller that is operationally connected to each of the plurality of devices for setting values for parameters of a device for a given sub-operation based on 1) operational information pertaining to at least one of the devices and on 2) a maximum allowable current consumption level of the system. |
| US07969808B2 |
Memory cell structures, memory arrays, memory devices, memory controllers, and memory systems, and methods of manufacturing and operating the same
Example embodiments are directed to memory cell structures, memory arrays, memory devices, memory controllers, and memory systems using bipolar junction transistor (BJT) operation. |
| US07969807B2 |
Memory that retains data when switching partial array self refresh settings
A memory including an array of memory cells and a control circuit. The control circuit is configured to control partial array self refreshes and to switch from one partial array self refresh to another partial array self refresh. Data in memory cells that are refreshed via the one partial array self refresh and refreshed via the other partial array self refresh is retained in the memory cells from before a first switch from the one partial array self refresh to the other partial array self refresh to after the first switch. |
| US07969803B2 |
Method and apparatus for protection of non-volatile memory in presence of out-of-specification operating voltage
A method and apparatus for protecting non-volatile memory is described. A write command is processed only when an operating voltage is between specified operating limits and when a data pattern stored in the non-volatile memory is repeatedly read successfully. |
| US07969801B2 |
Data input circuit and nonvolatile memory device including the same
A data input circuit includes a first data input unit, a second data input unit, and a clock unit. The first data input unit is configured to receive external data at rising edges of a data strobe signal and output the external data as first internal data in response to an internal clock. The second data input unit is configured to receive the external data at falling edges of the data strobe signal and output the external data as second internal data in response to the internal clock. The clock unit is configured to generate the internal clock using an external clock signal. |
| US07969800B2 |
Semiconductor memory apparatus
A semiconductor memory apparatus includes a row path activating unit configured to generate a line connection control signal according to a received address and active command. The semiconductor memory apparatus also includes a cell array circuit unit including an input/output line switch for connecting a first input/output line in a cell block and a second input/output line extending to the outside of the cell block. The cell array also including a bit line switch for connecting a bit line pair to each other. The input/output line switch and the bit line switch are further controlled by the line connection control signal from the row path activating unit. |
| US07969799B2 |
Multiple memory standard physical layer macro function
A memory interface physical layer macro including one or more embedded input/output (I/O) buffers, one or more memory interface hardmacros and control logic. The one or more embedded input/output (I/O) buffers support a plurality of I/O supply voltage levels. The one or more memory interface hardmacros are coupled to the one or more embedded I/O buffers. The control logic controls the one or more hardmacros and the one or more I/O buffers. |
| US07969794B2 |
One-transistor type DRAM
A one-transistor type DRAM including a floating body storage element connected between a bit line and a source line and controlled by a word line comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a plurality of clamp bit lines and reference bit lines arranged in a column direction, a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a clamp cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a reference cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, and a sense amplifier and a write driving unit connected to the bit line and configured to receive a clamp voltage and a reference voltage. |
| US07969784B2 |
Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells
Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used. |
| US07969783B2 |
Memory with correlated resistance
A system or device including a memory device, as well as a method of operating the memory device. Such a method includes writing a plurality of data values to a plurality of data locations. The plurality of data locations may be coupled to one another in a series, and the plurality of data values may be sequentially written to the plurality of data locations, starting with the data location at an end of the series and then sequentially writing to each adjacent data location. |
| US07969773B2 |
Computer system with addressable storage medium
A computer system with an addressable medium is disclosed. The computer system comprises an addressable medium subsystem, a microprocessor and at least one input/output device. The addressable medium subsystem includes: a control logic which has a control circuit with an address table for storing a plurality of addresses, and an access logic with a storage medium layer and an electromagnetic induction circuit. The electromagnetic induction circuit includes a plurality of coils and a plurality of rods. Each rod is surrounded by one of the coils and corresponds to one of a plurality of regions on the storage medium layer. The access logic controls the coils to access the data stored on the regions for the control logic. Each region corresponds to one of the addresses on the address table. The microprocessor and the input/output device electrically couple with the control logic. Both the microprocessor accesses instructions for executing and the input/output device accesses data via the control logic. |
| US07969771B2 |
Semiconductor device with thermally coupled phase change layers
Various embodiments of the present invention are generally directed to an apparatus and method associated with a semiconductor device with thermally coupled phase change layers. The semiconductor device comprises a first phase change layer selectively configurable in a relatively low resistance crystalline phase and a relatively high resistance amorphous phase, and a second phase change layer thermally coupled to the first phase change layer. The second phase change layer is characterized as a metal-insulator transition material. A programming pulse is applied to the semiconductor device from a first electrode layer to a second electrode layer to provide the first phase change layer with a selected resistance. |
| US07969767B2 |
Spin transfer torque—magnetic tunnel junction device and method of operation
A method is disclosed that includes controlling current flow direction for current sent over a source line or a bit line of a magnetic memory device. A current generated magnetic field assists switching of a direction of a magnetic field of a free layer of a magnetic element within a spin transfer torque magnetic tunnel junction (STT-MTJ) device. |
| US07969765B2 |
Sense amplifier for semiconductor memory device
A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made. |
| US07969755B2 |
Apparatus for electrical power transmission
A device for the transmission of electrical energy includes at least one current converter. Each current converter has phase elements with respective arrangements of circuit elements that comprise at least two switchable power semiconductors each and at least two free-wheeling diodes, each connected in parallel thereto, and energy storing means. The transfer properties in or between power distribution networks are improved with the novel device. The device is provided with means for controlling the current converter in such a manner that the zero crossing, the amplitude and/or the instantaneous values of an alternating current of a transfer network that can be connected to the device and/or the direct current of a direct current line that connects at least one current converter to a direct current source, and/or the direct voltage and the direct current of at least three interconnected current converters can be controlled. |
| US07969752B2 |
Switching power supply device using current sharing transformer
In accordance with the present invention, the switching power supply device using a current sharing transformer includes an inverter switching unit for switching an input voltage; a set of share inductors connected to the inverter switching unit for distributing a current applied by the inverter switching unit; first and second transformers of which each primary side connected to the set of share inductors is connected in parallel to each other; and a rectifying unit connected to secondary sides of the first and second transformers. |
| US07969751B2 |
High-speed signal transmission apparatus
A high-speed signal transmission apparatus comprises: a housing; a plurality of daughter boards juxtaposed to one another in the housing; board-side connectors each provided on corresponding each of the juxtaposed daughter boards; and cable-side connectors fixed in the housing; wherein each of the board-side connectors is insertable/removable into/from corresponding each of the cable-side connectors, and wherein a cable group whose impedance matching can be achieved makes connection between the predetermined cable-side connectors. |
| US07969748B2 |
EMI shielding slide assemblies for slidably opening and closing portable electronic devices and for providing EMI shielding for board-mounted electronic components
According to various aspects, exemplary embodiments are provided of slide assemblies for slidably opening and closing portable communications terminals, which also are configured to provide electromagnetic interference (EMI) shielding for electronic components of a substrate, such as board-mounted electronic components on a printed circuit board (PCB) of a cellular phone, etc. In one exemplary embodiment, a slide assembly generally includes first and second slide members slidably coupled so as to allow the first slide member to be slidably moved relative to the second slide member. EMI shielding structure is along at least one surface of at least one of the first and second slide members. The EMI shielding structure and the at least one of the first and second slide members are operable for cooperatively providing EMI shielding for one or more board-mounted electronic components of a substrate when disposed within the interior cooperatively defined by the EMI shielding structure, the at least one of the first and second slide members, and the substrate. |
| US07969745B2 |
Circuit board structure having electronic components integrated therein
The present invention provides a circuit board having electronic components integrated therein, including a carrier board having an metallic oxide layer formed on each two surfaces of a metal layer, and having at least one through cavity; at least a semiconductor chip hold in the opening; at least a capacitor disposed on one surface of the carrier board, wherein the surface with the capacitor disposed thereon is at the same side with the active surface of the semiconductor chip. The capacitor is constituted of a first electrode plate disposed on partial surface of one side of the carrier board, a high dielectric material layer disposed on the surface of the first electrode plate, and a second electrode plate, paralleling and corresponding to the first electrode plate, disposed on the surface of the high dielectric material. The metal layer and the oxidation layer of the carrier board can enhance rigidity as well as tenacity and also integrate semiconductor chips and capacitors in the circuit board structure. |
| US07969740B2 |
Metal-based print board formed with radiators
In a metal-based print board formed with radiators, a metal foil is affixed to a front surface of a metal plate having good thermal conductivity, an insulating adhesive layer interposed therebetween. A radiator is integrally provided on a reverse surface of the metal plate, the radiator having a plurality of thin radiating fins formed upright in a tabular shape due to having been dug out by an excavating tool. The radiating fins give the radiator a large area over which heat can be released. The thickness of a first metal plate portion formed between adjacent radiating fins is less than the original thickness of the metal plate. Heat generated by an electronic component or another component provided on a side of the front surface of the metal plate is rapidly transmitted from the reduced-thickness first metal plate portion of the metal plate to each of the radiating fins of the radiator on the reverse surface side, and efficiently released from each of the radiating fins, which have a large area over which heat is radiated. |
| US07969738B2 |
Computer
A computer includes a casing in which an opening is formed, a heat generating element which is provided inside of the casing, a main cooling unit which is disposed between the opening of the casing and the heat generating element and cools heat which is generated from the heat generating element, and an auxiliary cooling unit which is provided inside of the casing and additionally cools inside air directed to the main cooling unit. |
| US07969735B2 |
Power converter
The object is to provide a power converter which is capable of minimizing an extent to which the power converter components other than the semiconductor module are thermally affected by the heat originating from the semiconductor module.A casing houses: semiconductor modules 20, 30 constituting a main circuit for power conversion; a capacitor 50 electrically connected to the main circuit; drive circuits 70, 71 that provide the main circuit with a drive signal used in power conversion operation; a control circuit 74 that provides the drive circuit with a control signal used to prompt the drive circuit to provide the drive signal. Within the casing, a cooling chamber including a coolant passage 28 is formed, and a chamber wall of the cooling chamber is formed with a thermally conductive material. At least the semiconductor modules 20, 30 are housed inside the cooling chamber, and at least the capacitor 50 and the control circuit 74 are disposed outside the cooling chamber. |
| US07969733B1 |
Heat transfer system, method, and computer program product for use with multiple circuit board environments
A heat transfer system, method, and computer program product are provided for use with multiple circuit board environments. In use, a heat transfer component configured to be situated between a first circuit board and a second circuit board is provided. Such heat transfer component is in thermal communication with a first processor of the first circuit board and a second processor of the second circuit board. Furthermore, the heat transfer component is situated between the first circuit board and the second circuit board. |
| US07969727B2 |
Cooling
According to one embodiment, an equipment enclosure includes a plurality of equipment elements, each element having one or more heat generating sources. A heat exchanger is mounted towards the top of the equipment enclosure. The heat exchanger is thermally coupled to at least some of the heat generating sources. The enclosure includes an exhaust vent through which air heated by the heat exchanger may be evacuated, and an inlet vent through which air from outside the equipment enclosure may be drawn into the equipment enclosure to cool the heat exchanger by stack effect ventilation. |
| US07969724B2 |
Data storage assembly
A data storage assembly includes a bracket, a data storage device, a driving member and a locking member. The bracket includes a sidewall. The data storage device is moveably received in the bracket along a first direction parallel to the sidewall. The driving member is moveable along the first direction and includes a driving portion. The locking member includes a resisting portion corresponding to the driving portion of the driving member. The driving portion is capable of urging the resisting portion to move the locking member along a second direction perpendicular to the first direction. The storage device is secured in the bracket in a locking position along a first direction by the locking member. |
| US07969723B2 |
Electroactive actuator for portable communication devices
The invention relates to a portable communication device which comprises a first part, a second part, and one or more electroactive polymer actuators, where the electroactive polymer actuator is connected to the first part and to the second part. The invention also comprise a control unit, where the electroactive polymer actuator is adapted to move the first part in relation to the second part, and that the control unit is adapted to control the electroactive polymer actuator. |
| US07969720B2 |
Display apparatus with on screen display controller
An exemplary display apparatus (2) includes a front cover (21) having an opening (210) and a peripheral side (211) beside the opening; an on screen display button board (22) having a main body (223) with locating holes (2234); and a display panel (23) having a display area (231) corresponding to the opening of the front cover and a peripheral area (232) around the display area. Locating pins (216) are provided on a rear face (215) of the peripheral side, and the locating pins pass through the locating holes of the main body, as well as part of the peripheral area of the display panel is overlapped with the main body, thereby, the main body of the on screen display button board is sandwiched between the rear face of the peripheral side of the front cover and the display panel. |
| US07969718B2 |
Computer keyboard with transparent covers for protecting key characters
A computer keyboard in one embodiment includes a plurality of keys, each of the keys including a suspension structure and a key body supported by the suspension structure, the key body comprising a color body member, a transparent colorless protective cover formed on the body member, and at least one character formed on the body member by laser engraving through the protective cover onto the body member wherein the body member has a flat top. |
| US07969715B2 |
Power supply for a tattoo machine
A power supply that includes a housing for retaining the electronic components needed to operate a tattoo machine. The housing includes a first region in which the tattooing controls are located and a second region that includes a display screen. The first and second regions are separated from each so that a plastic covering can be drawn over only the first region to protect the tattooing controls while leaving the display screen unobscured. |
| US07969710B2 |
Solid electrolytic capacitor and method of manufacturing the same
Provided is a solid electrolytic capacitor including a capacitor element with a positive polarity; an anode wire of which one side is inserted into the capacitor element and the other side projects outward from the capacitor element; a cathode extraction layer formed on the capacitor element; a plurality of conductive bumps formed on the cathode extraction layer; an anode lead frame fixed to the side of the capacitor element, where the anode wire projects outward, and having an insertion portion into which the projecting end of the anode wire is inserted; a molding portion formed to surround the capacitor element and exposing the projecting end of the anode wire, the outer surface of the anode lead frame, and ends of the conductive bumps; an anode lead terminal provided on the molding portion so as to be electrically connected to the exposed end of the anode wire and the anode lead frame; and a cathode lead terminal provided on the molding portion so as to be electrically connected to the exposed ends of the conductive bumps. |
| US07969701B1 |
Fast react protection circuit for switched mode power amplifiers
A protection circuit includes a diode chip, and a switching device integrated with the diode chip, the switching device being isolated, optically triggered, optically powered, and the diode chip connected between a high side terminal of the switching device and an input to a first inverting amplifier, the diode chip further supplying a current when an overvoltage occurs between a drain and a source of the switching device. |
| US07969700B2 |
Electrical circuit for protecting photovoltaic systems
The object of the present invention is to provide a structure for the electrical protection of photovoltaic facilities in the event a photovoltaic generator (G1-Gp) is connected with its polarity reversed, for what it includes a protection cell that comprises two connection points (1, 2) at which the photovoltaic generator is connected (G1-Gp), at least one device (D) in charge of reducing the voltage of the photovoltaic generator (G1-Gp) in the event of polarity reversion, which is connected in parallel between the aforementioned two connection points, at least one element (M) of breakage and/or protection of the photovoltaic generator (G1-Gp) serially connected to the preceding elements, minimizing the loading on the aforementioned break and/or protection elements. |
| US07969697B2 |
Low-voltage CMOS space-efficient 15 KV ESD protection for common-mode high-voltage receivers
An electrostatic discharge protection device is disposed between true-complement input pins of a differential signal pair and a ground node. A common node couples the three diode stacks together. A first and a second diode stack each connect to one of the differential signal pair input pins. The third diode stack couples to the ground node. Each of the diode stacks is fabricated by a pair of high concentration p-type contact dopant regions within a low concentration n-well region. Each of the p-type contact dopant regions is configured to form back-to-back diodes connected in series with cathodes in common. In protecting common mode receivers, current from an ESD event is channeled to ground rather than to the complementary receiver node. The diode stacks are capable of withstanding a 15 kV incident and save up to 25% in area compared to a fully parallel configuration for differential signal pairs. |
| US07969696B2 |
Ground fault detection and localization in an ungrounded or floating DC electrical system
An ungrounded or floating DC electrical power distribution system may experience a single line to ground fault. Such a fault may not disrupt operation of the system, but its presence may raise a risk of additional problems if left uncorrected. A system for progressively grounding the ungrounded system may be initiated when a line to ground fault is suspected based on the voltage difference measured to a common chassis point. As grounding through successively lower impedance proceeds, fault current may increase and detection of severity of the line to ground fault may be more readily achieved, thus facilitating localization of the fault. Localization may be achieved through an analysis of direction of capacitive currents in isolatable zones of the system. |
| US07969691B2 |
Magnetic head and magnetic disk system having a read sensor and a sensing current
A read sensor is disposed near a main pole, thereby reducing the distance between the read sensor and a write sensor. In this case, however, a magnetic field generated from the main pole affects magnetization of a free layer and a pinned layer of a magnetoresistive film, thereby causing the magnetizing directions to rotate, a magnetic barrier to be generated, and the read property to be degraded. According to the present invention, a main pole and a yoke configure a magnetic circuit together with a sub-pole and a soft magnetic under layer of the magnetic disk and an exciting coil magnetizes the magnetic circuit, thereby a recording magnetic field is applied to a recording layer to record information bits on the layer. And in order to sharpen the magnetic field distribution generated by the main pole, a trailing shield made of a ferromagnetic material is disposed at the trailing side of the main pole adjacently. And a read sensor (magnetoresistive element) for reading bit information is provided between the trailing shield and the main pole. |
| US07969689B2 |
Spacer keys with pivoting supports
An apparatus for attaching one or more HGAs to an actuator assembly including one or more actuator arms comprises a set of pivoting supports corresponding to the one or more HGAs and mechanisms that pivot each of the pivoting supports between open positions and closed positions. For each of the set of pivoting supports, in the open position, a gap adjacent to the pivoting support is sufficiently large to receive both a mounting platform of one of the actuator arms and a baseplate of one of the HGAs positioned in alignment with the mounting platform of the one of the actuator arms, and, for each of the set of pivoting supports, in the closed position, the gap is sufficiently small to constrain the baseplate of the one of the HGAs against the mounting platform of the one of the actuator arms. |
| US07969686B2 |
Self-assembly structures used for fabricating patterned magnetic media
Methods of defining servo patterns and data patterns for forming patterned magnetic media are described. For one method, a lithographic process is performed to define a servo pattern in servo regions on a substrate. The lithographic process also defines a first data pattern in data regions of the substrate. The first data pattern is then transferred to (i.e., etched into) the data regions. Self-assembly structures are then formed on the data pattern in the data regions to define a second data pattern. The servo pattern is then transferred to the servo regions and the second data pattern is transferred to the data regions. Thus, the servo pattern is defined through lithographic processes while the data pattern is defined by a combination of lithographic processes and self-assembly. |
| US07969680B2 |
Magnetic tape on which a servo pattern is formed
A magnetic tape of the present invention includes a plurality of data bands in which a data signal can be recorded and servo pattern portions composed of a burst signal. The servo pattern portions are formed at a predetermined interval in a longitudinal direction of the magnetic tape in a plurality of data bands, and positions of the servo pattern portions formed in the respective data bands in the longitudinal direction of the magnetic tape vary. According to such a configuration, a magnetic tape can be provided, which is traced stably by the magnetic head even if the magnetic tape is deformed due to temperature and humidity. |
| US07969678B2 |
Magnetic disk drive having assisted recording and methods of recording data thereto
In one embodiment, a magnetic disk drive includes a magnetic disk, a head slider for flying above the spinning magnetic disk, a pattern analyzer for analyzing a data pattern of data to be recorded on the magnetic disk to determine a recording current reversal timing and a recording assistance area in accordance with the analysis so that the rear end of the determined recording assistance area is shifted forward if the determined recording current reversal timing is earlier than a criterion, or the rear end of the determined recording assistance area is shifted backward if the determined recording current reversal timing is later than the criterion, a recording assistance element on the slider for forming the determined recording assistance area on the magnetic disk, and a recording element for recording the data on the magnetic disk using the recording current in accordance with the determined recording current reversal timing. |
| US07969676B2 |
Interspersed phase-locked loop fields for data storage media synchronization
Techniques are described for providing media-referenced timing for operations on a data storage medium. In particular, Phase-Locked Loop (PLL) synchronization fields may be interspersed within data fields of the medium and may be read to obtain timing measurements. The PLL fields are illustratively pre-recorded at predetermined intervals on the medium and have a fixed number of dots of the bit patterned medium between the PLL fields. Phase and frequency of a write clock may be controlled based on the read PLL fields to translate the timing measurements from the PLL fields into phase and frequency corrections to synchronize the write clock to the data storage medium. |
| US07969675B2 |
Determination of the quality of an erase process for perpendicular magnetic recording disks
Methods and test systems are disclosed for determining the quality of an erase process for perpendicular magnetic recording (PMR) disks. After performing an erase process on a PMR disk and before the PMR disk is assembled into a hard disk drive, a first test pattern of magnetization pulses is written to a region of the PMR disk. A second test pattern is subsequently read from the region of the PMR disk. The second pattern of magnetization pulses is analyzed in relation to the first test pattern and measured to determine the quality of the erase process. |
| US07969674B2 |
Data transfer assembly performance characteristics testing
An apparatus is provided having a data transfer member, and a medium supported by a base adjacent the data transfer member. A medium tilting device supports the base and is selectively positionable to tilt the medium with respect to the data transfer member to simulate presenting the head to the medium at a desired angular orientation. A sensor measures a characteristic associated with a data transfer relationship between the data transfer member and the medium. |
| US07969670B2 |
Lens driving module
Provided is a lens driving module including a housing that has a lens barrel housing portion provided therein; a lens barrel that has a bearing contact portion and a guide portion formed on the outer circumferential surface thereof and is mounted in the lens barrel housing portion of the housing; a piezoelectric motor that is mounted in one outer corner of the housing, which corresponds to the guide portion of the lens barrel, among the outer corners of the housing, and provides a driving force to the lens barrel; and a power connection member that is bent so as to cover the piezoelectric motor and the outer circumferential surface of the housing and is coupled to the housing. |
| US07969668B2 |
Lens arrangement and lens module using same
A lens arrangement includes two lenses. Each lens includes an optical portion having an optical axis, a non-optical portion surrounding the optical portion, and an engagement portion extending along the optical axis from the non-optical portion. One of the engagement portions includes an outer wall and an inner wall parallel to the outer wall with an annular groove defined therebetween, while the other engagement portion defines a corresponding annular space for receiving the outer wall and the inner wall therein, therefore the engagement portions are interferentially engaged with each other. |
| US07969667B2 |
Lens assembly
A lens assembly comprises a lens group M and a lens frame 1 for retaining the lens group M. In this lens assembly, the lens frame 1 has an entire circumference support 2b for supporting the rim on the subject side, of each lens M, across the entire circumference thereof, and an end face support 2a for supporting the lens M on the image side. Each lens M comprises a chamfer 3b formed at a rim of a lens surface on the subject side across the entire circumference thereof, and the entire circumference support 2b supports the chamfer 3b such that the entire circumference support 2b is continuous with the lens surface at substantially the same radius of curvature with the lens surface. According to the present invention, there is provided a lens assembly which can reduce size and cost and has stable lens retaining ability. |
| US07969665B2 |
Lens adjusting device of projector
A lens adjusting device of a projector is provided. The lens adjusting device has a base, a frame, and at least one positioning structure. A lens is fixed on the frame. The positioning structure is utilized for movably setting the frame on the base. The positioning structure has a groove, a slider, and a positioning unit. The groove is disposed on the frame. The slider is disposed in the groove and has a guiding hole defined therein. The extending direction of the guiding hole is substantially perpendicular to the extending direction of the groove. The positioning unit is slidably disposed in the guiding hole and penetrates the guiding hole to set the frame and the slider on the base. |
| US07969653B2 |
Laser microscope and control method for the same
It is possible to achieve a required field number and numerical aperture for microscope observation at a scanning speed equal to video-rate or higher and also to change the scanning speed with a simple configuration. The invention provides a laser microscope including a laser light source; a scanning unit configured to scan a specimen with laser light emitted from the laser light source; and an objective lens configured to focus the laser light scanned by the scanning unit on the specimen. The scanning unit is provided with an electro-optical deflecting element including an electro-optical crystal in which a refractive index gradient is induced by injecting electric current. |
| US07969652B2 |
Microscope device and image processing method
A diffraction grating produces first diffraction light in a symmetrical direction with respect to the 0-th diffraction light and the optical axis. Each light flux forms two flux interference patterns on a sample surface through first and second objective lenses. A sample is illuminated by spatially modulated illumination light. Fluorescence is generated on the sample by structured illumination light as excitation light. The fluorescence caught by the first objective lens forms a modulated image of the sample on a sample conjugate surface through an objective optical system including the first and second objective lenses. The modulated image is further modulated through the diffractive grating. Fluorescence from the further modulated image passes through a lens and a dichroic mirror, enters into a single light path of an observation optical system, passes through a fluorescent filter, and forms an enlarged image of the further modulated image through a lens. |
| US07969648B2 |
Gain and signal level adjustments of cascaded optical amplifiers
An optical amplification device which includes first and second optical amplifiers, and a controller. The first optical amplifier receives a light and amplifies the received light. The second optical amplifier receives the light amplified by the first optical amplifier, and amplifies the received light. When a level of the light received by the first optical amplifier changes by Δ, the controller controls a level of the light received by the second optical amplifier to change by approximately −Δ. In various embodiments, the controller causes the sum of the gains of the first and second optical amplifiers to be constant. In other embodiments, the optical amplification device includes first and second optical amplifier and a gain adjustor. The gain adjustor detects a deviation in gain of the first optical amplifier from a target gain, and adjusts the gain of the second optical amplifier to compensate for the detected deviation. |
| US07969644B2 |
System and method for despeckling an image illuminated by a coherent light source
A method and system for reducing speckle in an image produced from a coherent source of radiation is provided. The method includes coupling a source beam received from a coherent optical source into an optical fiber. A position of at least a portion of the fiber may be modulated using a ditherer. The source beam may be refracted by a lens after it is decoupled from the optical fiber, such that the source beam is aimed at a microlens diffuser. In accordance with a particular embodiment, the source beam may be projected from the microlens diffuser onto a spatial modulator. The spatial modulator may be positioned to project the source beam via an imaging lens, to a target. |
| US07969643B2 |
Display particles for image display apparatus and image display apparatus loaded with the same
Display particles for an image display apparatus, wherein the image display apparatus comprises two substrates at least one of which is transparent, with the display particles being sealed between the substrates in a powder state, so that by generating an electric field between the substrates, the display particles are moved to display an image, wherein the display particles are formed through processes in which at least a binder resin and a colorant are kneaded and pulverized to give core particles, resin fine particles are fixed and fused on surfaces of the core particles, and then the core particles on which the resin fine particles are fixed and fused are sphered to give an average degree of roundness of 0.960 or more, and wherein a ratio of use of the resin fine particles is set in the range from 100 to 300% in the rate of the total projection area of the resin fine particles relative to the total surface area of the core particles, as well as an image display apparatus loaded with the display particles. |
| US07969640B2 |
Color display system
An image display apparatus is disclosed in this invention. The image display apparatus includes a light source for emitting an illumination light, at least one spatial light modulator for receiving and applying an image signal for modulating illumination light from the light source, and a control circuit for controlling the light source and/or the spatial light modulator to project a modulated light for image display having different gray scale characteristics between at least two successive frames. |
| US07969639B2 |
Optical modulator
A micro-opto-electro-mechanical systems (MOEMS) electro optical modulator (2) having an electrically tuneable optical resonator comprising an asymmetric Fabry-Perot etalon incorporating a mirror (10) resiliency biased with respect to a substrate (13) and moveable in relation thereto in response to a voltage applied there-between. The optical modulator (2) is capable of modulating electromagnetic radiation having a plurality of wavelengths. The modulator is adapted to modulate the transmission of short wave infrared radiation (SWIR), medium wave infrared radiation (MWIR) and long wave infrared radiation (LWIR) and the reflection of visible radiation. A spatial optical modulator having a plurality of said MOEMS optical modulators (2). A method of addressing said spatial optical modulator. |
| US07969636B2 |
Laser direct imaging apparatus
A laser direct imaging apparatus which can expose photosensitive materials having various sensitivities and which can correct an imaging position in accordance with deformation of a workpiece. In the laser direct imaging apparatus, the workpiece is moved in a sub-scanning direction while a cylindrical lens is used to converge a laser beam, which has been modulated based on raster data, in the sub-scanning direction and deflect the laser beam toward a main scanning direction so as to image a desired pattern on the workpiece. The cylindrical axis of the cylindrical lens is designed to be able to rotate horizontally and to be able to change an angle with respect to the main scanning direction. |
| US07969634B2 |
Optical scanning device and image forming apparatus
An optical scanning device includes a light source, a deflector, and an image-forming optical system. The deflector includes a deflecting surface for deflecting light beams in a main scanning direction. The image-forming optical system includes two relay lenses having a positive power in the main scanning direction. The relay lenses cause main light beams of light beams emitted from the light source to cross near the deflecting surface in the main scanning direction. |
| US07969630B2 |
Image forming apparatus for security transmission of data and method thereof
In an image forming apparatus and a data transmission method thereof, text data are extracted and transmitted for the purpose of the security management of data so that time and management cost of security violation are reduced. The image forming apparatus for security transmission of data includes a text extractor to extract text data from the data and a transmitter to transmit the text data to a management server to obtain transmission permission and then to transmit the data to a transmission target. |
| US07969623B2 |
Image-capturing apparatus
Image-capturing apparatus meeting demands for high-image resolution and high-speed data capture during both still- and moving-document data-capture modes. Includes: a reading unit having first and second linear photoreceptors arrayed along an data capture sub-scanning direction, a delay circuit delaying output from the first photoreceptor, and an adding circuit adding delayed first-photoreceptor output to second-photoreceptor output; and a scanning unit illuminating from underneath the platen, and shiftable along it to guide linear reflected light from a document to the first and second photoreceptors. During a moving-document data-capture mode, the scanning unit is disposed in a data-capture position established at one edge of the platen to scan a document being conveyed, and when in a still-original data-capture mode, it is shifted from along the platen's opposite edge toward the one edge thereof to scan a stationary document. |
| US07969621B2 |
Scanning device
A scanning device may include a first structural member and a second structural member, a movable body that is configured to reciprocate between the first structural member and the second structural member, and a cable of which a first end is fixed to one of the first and second structural members and a second end fixed to the movable body. The cable may have a curved portion between the first end and the second end thereof. The scanning device may further include an elastic member of which a first end portion is fixed to one of the first and second structural members to which the first end of the cable is fixed, and a second end portion is engaged to the curved portion. The elastic member may be configured to elastically urge the cable in a direction opposite to the curving direction of the curved portion. |
| US07969615B2 |
Image forming apparatus and image processing apparatus
An image forming apparatus forms an image for a latent image portion of which density is relatively higher with a dark color image forming portion, and forms an image for a background portion of which density is relatively decreased or of which image disappears, with a light color image forming portion, with respect to portions of forgery-preventing pattern image in which the density contrasts for the portions mutually differ after copying. |
| US07969613B2 |
Print control system with predictive image
A print control system is provided. The print control system comprises an image capturing device configured to capture an image of at least a portion of a printed image on a printed product of a print device. The print control device further comprises a control system comprising an input device and a module. The input device is configured to allow a user to vary a print parameter. The module is configured to calculate a predictive image based on the print parameter variation from the input device. The predictive image is representative of a resultant image on the printed product following implementation of the print parameter variation on the print device. |
| US07969611B2 |
Display system and method of controlling same
A display system and display control method for displaying an image based upon image data supplied from an image supply device or external storage unit. Information indicating whether editing of image data is allowed or not is appended to an image, the information is discriminated and display areas of images corresponding to the image data are displayed on a screen upon making the display areas appear different from each other in accordance with the information discriminated. |
| US07969609B2 |
Method, system and computer program for the generation of an electronic document from scanned image data
According to the method and system for display screen-aided generation of an electronic document from rastered image data, a group of image data per page and comprising multiple pages is stored. Symbols for associated pages of the group per associated page are displayed in an organized structure in the first screen region. Per page or per region, the image data is separately selected for full display in a second screen display region so that the associated page is accessible for additional processing steps with respect to at least one of the elements selected from the group consisting of a pixel processing and a page processing. Upon touching a symbol of the group with a selection member, a content of the associated page of the group is displayed in an automatically opening, separate display region. |
| US07969604B2 |
Systems and methods for printing artwork containing transparency
Systems and methods provide a mechanism to print documents having transparent artwork that overlaps other artwork. One aspect of the systems and methods includes sending the document to a printer control system coupled to a printer. The printer control system detects overlapping areas, and processes the artwork into separate atomic regions. Objects contributing to the atomic region are placed in an object stack. A rasterizer having knowledge of the printer characteristics creates object raster buffers for the portions of the objects that contribute to the atomic region. The object raster buffers are then blended according to transparency values associated with the object to create an atomic region raster buffer. The atomic region raster buffer is combined with other atomic region raster buffers and raster images for other non-overlapping objects into a printer raster buffer that may be processed by the printer to produce a page. |
| US07969603B2 |
Print driver based marketing system and method
A method of providing access to an online marketplace via a printer driver that is in communication with a networked printing device. The marketplace offers printer capabilities which are compatible with the networked printing device. The computing device receives a request to purchase one of the printer capabilities for the networked printing device. The printer driver associates the purchased printer capability with the computing device. |
| US07969599B2 |
Device managing system, information process apparatus, and control method thereof
A method of controlling an information processing apparatus, which counts process amounts in the device for each user, in a system for processing print jobs within a range of access limitation information. The information processing apparatus specifies a user who requests access authority information for a job, and a job whose access authority information is issued to that user. The apparatus checks if a process of the job is completed. The apparatus determines a printable page count of the specified user using an output process amount value of the job issued by the user, when the specified job is complete. The apparatus notifies a managing apparatus, which issues access authority information, of the printable page. |
| US07969597B2 |
Printing system that outputs a photographic print from acquired image data
A printing system comprises a processing unit provided in a printing portion B for performing print processing by transmitting image data acquired by a receiving terminal A to the printing portion B. The necessary present processing can be performed by logging on to the present system by inputting authentication information from a keyboard 12 and mouse 13 provided as an input terminal in the receiving terminal A to the processing unit 25 of the printing portion B. The print processing can be executed also when an operator is not logged in to the present system. |
| US07969596B2 |
Methods and systems for imaging device document translation
Aspects of the present invention relate to systems, methods and devices for translating documents through the use of an imaging device. Some aspects relate to the receipt of a document at an imaging device, in some cases in conjunction with language selection parameters, and the transmission of that document and any accompanying language parameters to a remote computing device at which the document is translated and then sent to a destination. |
| US07969594B2 |
Information processing apparatus, information processing system, and proxy method for connection of information processing apparatuses
An object of this invention is to implement a user-friendly proxy process in a network system in which a plurality of devices connect to each other. According to this invention, an information processing method for an information processing apparatus which manages a license for a job process and communicably connects to a plurality of devices that are to execute a process for a job whose license is held includes a step of selecting, from the plurality of devices, a device which is to execute a proxy process of a job, a step of, when the selected device does not have a license to execute the process of the job, outputting the license as a file, and a step of monitoring whether the selected device has executed the proxy process of the job using the file, and when the proxy process is complete, requesting return of the output file. |
| US07969592B2 |
Printing and copying fault monitoring using cover sheets
The disclosed method identifies potentially faulty sheets that were printed when the parameters were outside the predetermined normal parameter range and maintains one or more locations of the potentially faulty sheets within the stacks of sheets. If one or more of the stacks of sheets contain one or more of the potentially faulty sheets, the method prints one or more printing fault cover sheets and outputs the printing fault cover sheets to the stacks of sheets that contain the potentially faulty sheets. The printing fault cover sheets identify the locations of the potentially faulty sheets within the stacks of sheets. By providing the printing fault cover sheets and continuing the printing operation, the method can be set to stop the printing only for printing parameters that physically prevent printing, and not for printing parameters that only affect printing quality, thereby maintaining high productivity while still allowing the user to easily locate sheets that potentially have printing faults. |
| US07969586B2 |
Electronic leveling apparatus and method
An electronic leveling apparatus for optically measuring a height difference relative to a leveling staff comprises a telescope, a camera fixed to the telescope, a first actuator for rotating both said telescope and said camera in a horizontal plane about a fixed vertical axis of the apparatus, and a controller. The camera has a depth of focus that is at least twice a depth of focus of the telescope. The controller uses a first output signal from said telescope to output a leveling signal representing a detected height difference. The controller uses a second output signal from said camera to identify a representation of a leveling staff and to control the first actuator based on the identified representation of the leveling staff. Furthermore a method for optically measuring a height difference of an electronic leveling apparatus relative to a leveling staff is provided. |
| US07969584B2 |
Measuring method including measuring angle of concave portion and irradiating light over concave portion
The measuring method for providing a precise determination of a geometry of a concave portion is provided. The measuring method includes: measuring an angle of a side wall of a concave portion with a bottom surface thereof formed in an insulating film (operation S1); defining a plurality of parameter groups including an angle of the side wall of the concave portion with the bottom surface, a dimensional width and a dimensional depth and preparing library containing a plurality of waveforms of reflected lights respectively correlated with such plurality of parameter groups (operation S2); an operation of irradiating light over the concave portion (operation S4); an operation of detecting reflected light (operation S5); referencing the waveform of reflected light with the waveform selected from the library (operation S6); and when a difference between the waveform of reflected light and the waveform selected from the library is lower than a specified value, then assigning the parameter such as the dimensional width of the concave portion and the like correlated with the selected waveform for an optimum value to determine the geometry of the concave portion. The angle of the side wall of the concave portion with the bottom surface thereof in the parameter groups of the library is a measured angle in the operation S1. |
| US07969583B2 |
System and method to determine an object distance from a reference point to a point on the object surface
A system for determining an object distance z includes a plurality of light emitters. A group of at least one of the plurality of light emitters includes an emitter group, and the pattern projected when one emitter group is emitting includes a fringe set. The light pattern of one fringe set exhibits a phase-shift relative to the light patterns of the other fringe sets, and the phase-shift varies as the distance from the origin of the plurality of fringe sets varies. The system further includes a processing unit that is configured to compute a ripple metric value associated with each of a plurality of possible z values. The processing unit is further configured to determine an approximated z value using the computed ripple metric values. A probe system is also provided. The probe system is configured to project a plurality of fringe sets from the probe onto an object. The light pattern of one fringe set exhibits a phase-shift relative to the light patterns of the other fringe sets, and the phase-shift varies as the distance from the origin of the plurality of fringe sets varies. The probe system is further configured to compute a ripple metric value associated with each of a plurality of possible z values, where z is an object distance. The probe system is also configured to determine an approximated z value using the computed ripple metric values. A method for determining an object distance z is also provided. |
| US07969580B2 |
Method and system for step-and-align interference lithography
A method for step-and-align interference lithography is provided in the present invention, by which a displacement error relating to the moving of an interference light beam as the source of the interference light beam is being carried to move by a carrier is measured before interference lithography, and then the displacement error is used as a reference to compensate a positioning error between adjacent interference patterns during step-and-align interference lithography. Besides, the present invention further provides a system for step-and-align interference lithography, which is capable of compensating the positioning error caused by a stepping movement control used for moving a substrate or the light beams in a stepwise manner to form interference-patterned regions by interference lithography and thus the so-generated interference-patterned regions are accurate aligned with one another on a two-dimensional plane for preparing the same to be stitched together to form a two-dimensional large-area periodic structure. |
| US07969578B2 |
Method and apparatus for performing optical imaging using frequency-domain interferometry
An apparatus and method are provided. In particular, at least one first electro-magnetic radiation may be provided to a sample and at least one second electro-magnetic radiation can be provided to a non-reflective reference. A frequency of the first and/or second radiations varies over time. An interference is detected between at least one third radiation associated with the first radiation and at least one fourth radiation associated with the second radiation. Alternatively, the first electro-magnetic radiation and/or second electro-magnetic radiation have a spectrum which changes over time. The spectrum may contain multiple frequencies at a particular time. In addition, it is possible to detect the interference signal between the third radiation and the fourth radiation in a first polarization state. Further, it may be preferable to detect a further interference signal between the third and fourth radiations in a second polarization state which is different from the first polarization state. The first and/or second electro-magnetic radiations may have a spectrum whose mean frequency changes substantially continuously over time at a tuning speed that is greater than 100 Tera Hertz per millisecond. |
| US07969577B2 |
Inspection apparatus, an apparatus for projecting an image and a method of measuring a property of a substrate
When using a scatterometer different portions of a target area may be at different focal depths. When the whole area is measured this results in part of it being out of focus. To compensate for this an array of lenses is placed in the back focal plane of the high numerical aperture lens. |
| US07969576B1 |
Optical sensing based on wavelength modulation spectroscopy
Techniques, apparatus and systems for using Wavelength Modulation Spectroscopy measurements to optically monitor gas media such as gases in gas combustion chambers. |
| US07969575B2 |
Method and apparatus for measuring light absorption of liquid samples
Techniques for measuring light absorption of liquid samples are described herein. According to one embodiment, an apparatus includes an upper arm having a first measuring surface and a lower arm having a second measuring surface coupled to the lower arm via a hinge. The upper arm is capable of swinging via the hinge. One of the measuring surfaces is coupled to a light source while the other is coupled to a detector. The apparatus further includes an actuator configured to position the upper arm into a first measuring position. The first measuring surface of the upper arm and the second measuring surface of the lower arm are spaced approximately to contact and sandwich a liquid sample in between to form an optical path, such that light generated from the light source is received and detected through the light path by the detector for measuring light absorption by the liquid sample. Other methods and apparatuses are also described. |
| US07969574B2 |
Apparatus for monitoring the cure of a bone cement material
Apparatus for monitoring the cure of a bone cement material which is provided in a container. The apparatus includes a radiation source from which radiation is directed towards cement in the container and a sensor for detecting radiation from the radiation source which has passed through cement in the container, and for generating a signal according to the intensity of the detected radiation. A data processor is used in monitoring changes in the intensity of radiation that is detected by the sensor due to changes in the opacity of cement in the container to radiation from the source as the cement cures. |
| US07969573B2 |
Method and system for obtaining n and k map for measuring fly-height
A method for obtaining a refractive index (n) and extinction coefficient (k) map of a slider surface, the method comprising the steps of processing an image of the slider surface to obtain spatially resolved normalized intensity data of the slider surface; measuring n and k values of the slider surface at different areas of the slider surface to obtain reflectivity data of the slider surface; mapping a distribution of the normalized intensity data to a distribution of the reflectivity data for deriving the n and k map of the slider surface. |
| US07969570B2 |
Applications of laser-processed substrate for molecular diagnostics
A method for performing a diagnostic assay of an analyte, wherein the method comprises providing a base that has been structured using laser processing so as to provide a substrate with at least one patterned surface, wherein the laser processing comprises the selective application of pulsed laser energy to the base, whereby to melt a surface layer of the base which resolidifies, whereby to create the at least one patterned surface; applying a metal to the at least one patterned surface so as to provide at least one metalized patterned surface; positioning the analyte on the at least one metalized patterned surface; and performing a diagnostic assay of the analyte. |
| US07969567B2 |
Method and device for detecting shape of surface of medium
A defect generated during a nano-imprint process is inspected by a scatterometry method. The scatterometry method is to illuminate the surface of a medium with light having a plurality of wave lengths by means of a first illuminator through a half mirror and an objective lens and cause light reflected on the medium to be incident on a spectrometer through the objective lens and the half mirror. A second illuminator illuminates a foreign material or scratch on the surface of the medium from an oblique direction with respect to the surface of the medium. Light is scattered from the foreign material or scratch and detected by first and second detectors. The first detector is placed in a direction defining a first elevation angle with the surface of the medium. The second detector is placed in a direction defining a second elevation angle with the surface of the medium. When coordinates of a defect that are obtained by the scatterometry method match coordinates of the foreign material or scratch, an inspection device determines that the defect is not generated during the nano-imprint process. When the matching is negative, the inspection device determines that the defect is generated during the nano-imprint process. |
| US07969565B2 |
Device for inspecting a surface
A device that is usable to inspect the surface of a material uses an inspection system which includes an optical unit. That optical unit can register the light which is reflected by the surface to be inspected. An illumination system, that uses at least two light sources, provides the light. The optical unit and the illumination system are connected to a control unit. The at least two light sources are arranged spaced at a distance from each other and both emit light directed to a recording region of the optical unit. The optical unit is oriented toward the surface to be inspected and at least one of the illumination light sources can be subdivided into several individual light sources. The control unit controls at least two of the illumination system light sources that are arranged at a distance from each other or the respective individual light sources of at least one of the illumination sources both selectively and independently of each other. The recording region of the optical unit lies on a displacement plane of the surface to be inspected with that surface being displaced through the recording region in relation to the inspection system. The distance between the light sources of the illumination system extends in the displacement direction of the surface to be inspected. The individual light sources of at least one of the sources are arranged transversely to the displacement direction of the surface to be inspected. |
| US07969561B2 |
Apparatus and method for monitoring extinction ratio of optical signals
An apparatus for monitoring extinction ratio (ER) of optical signals comprises an optical spectrum analyzing unit, an ER monitoring control unit and an ER monitoring output unit. The optical spectrum analyzing unit measures two peak values corresponding to level one and level zero of optical signals from an optical coupler, and obtains two wavelengths for the two peak values. The ER monitoring output unit outputs the difference of the two wavelengths to the ER monitoring control unit. With a relation formula of the wavelength difference, the ER monitoring control unit estimates an optimal resolution bandwidth for setting up the optical spectrum analyzing unit. As such, the optical spectrum analyzing unit measures two optical powers corresponding to level one and level zero of optical signals. With the two optical powers, the ER monitoring output unit computes an ER value. |
| US07969556B2 |
Illumination optical system for microlithography and illumination system and projection exposure system with an illumination optical system of this type
An illumination optical system for microlithography is used to guide an illumination light bundle from a radiation source to an object field in an object plane. A field facet mirror has a plurality of field facets to predetermine defined illumination conditions in the object field. A following optical system is arranged downstream of the field facet mirror to transfer the illumination light into the object field. The following optical system has a pupil facet mirror with a plurality of pupil facets. Some of the field facets are divided into individual mirrors, which predetermine individual mirror illumination channels. The latter illuminate object field portions, which are smaller than the object field. At least some of the individual mirrors are configured as individual correction mirrors. The latter can be tilted between at least two tilting positions, a central region illumination taking place in a basic tilting position and a surrounding region illumination of the object field taking place in a correction tilting position. An illumination optical system is the result, with which a correction of undesired variations of illumination parameters, in particular an illumination intensity distribution over the object field, is possible without loss of light. |
| US07969550B2 |
Lithographic apparatus and device manufacturing method
A lithographic apparatus includes an illumination system configured to condition a radiation beam; a support constructed to support a patterning device, the patterning device being capable of imparting the radiation beam with a pattern in its cross-section to form a patterned radiation beam; a substrate table constructed to hold a substrate; a projection system configured to project the patterned radiation beam onto a target portion of the substrate, and a shield device arranged between a source of air flows and/or pressure waves and an element sensitive for the air flows and/or pressure waves. |
| US07969548B2 |
Lithographic apparatus and lithographic apparatus cleaning method
An immersion lithographic projection apparatus having a megasonic transducer configured to clean a surface and a method of using megasonic waves to clean a surface of an immersion lithographic projection apparatus are disclosed. |
| US07969546B2 |
Liquid crystal display panel
A liquid crystal display panel and a method of fabricating the same are provided. In the method, a first substrate is provided, and gates and scan lines are formed. An insulation layer covering the gates and the scan lines is formed, and a channel layer is formed on the insulation layer. A source and a drain are formed on each channel layer, and a data line electrically connected to each source is formed. A plurality of pixel electrodes are then formed, and a second substrate is provided. A plurality of pillar spacers are formed on the second substrate, and the first substrate and the second substrate are assembled. A liquid crystal layer then fills between the first substrate and the second substrate. |
| US07969545B2 |
Liquid crystal display and manufacturing method thereof
A method for manufacturing a liquid crystal display device includes forming a black matrix layer on a first substrate, forming a groove on the first substrate, forming a color filter layer having a red resin, a green resin, and a blue resin on the first substrate, forming a common electrode on the color filter layer, and disposing spacers on the first substrate. |
| US07969534B2 |
Polarizing element, polarizing element manufacturing method, liquid crystal device, and projection display
A polarizing element manufacturing method includes (a) forming a plurality of fine metal wires by forming a metal film on a substrate and patterning the metal film, (b) applying, onto a base material, a glass precursor solution for forming a protective layer for protecting the fine metal wires, (c) placing the substrate on the base material so that ends of the fine metal wires are immersed in the glass precursor solution, and (d) forming the protective layer by drying the glass precursor solution, and bonding together the base material and the substrate with the protective layer therebetween. |
| US07969525B2 |
Liquid crystal display device
There is provided a light source, which can efficiently be housed even if the area of the substrate increases while giving extra consideration to the heat radiation of the light emitting diodes in a liquid crystal display device using the light emitting diodes as a light source. A plate-like light source section is formed by arranging the light emitting diodes on a metal substrate. The plate-like light source section is formed to have a larger area than an entrance surface of a light guide plate, and is disposed so as to face the entrance surface of the light guide plate. The light guide plate and the plate-like light source section are housed in a housing case, and the housing case is formed to have a larger depth in a part for housing the plate-like light source section than in a part for housing the light guide plate. A cushion member is provided between the light guide plate and the housing case to prevent the light guide plate from being moved by vibrations. |
| US07969517B2 |
Electrically-driven liquid crystal lens and stereoscopic display device using the same
An electrically-driven liquid crystal lens wherein an electrode is defined with a vertical or horizontal rubbing direction, achieving an improved lens profile effect, and a stereoscopic display device using the same are disclosed. The liquid crystal lens includes first and second substrates arranged opposite each other and each including a plurality of lens regions, a plurality of first electrodes formed on the first substrate to correspond to the respective lens regions while being spaced apart from one another, to which voltages gradually increasing from the center to the edge of each lens region are applied, a second electrode formed over the entire surface of the second substrate, a first alignment film formed over the entire surface of the first substrate including the first electrodes and having an alignment direction parallel to or perpendicular to a longitudinal direction of the first electrodes, a second alignment film formed on the second electrode and having an anti-parallel alignment direction relative to the first alignment film, and a liquid crystal layer filled between the first substrate and the second substrate. |
| US07969515B2 |
Video display apparatus and method
A video display apparatus displays videos corresponding to a plurality of observers respectively and comprises a display device. A control unit controls a scan timing so that a sum of a video scanning period from an upper end to a lower end of the display device concerning one video input into the display device and a response period in the lower end of the display device is smaller than a field period of the video. The control unit allows an illumination system to emit light between the end of the response period of the lower end and the start of scanning of the next video in the upper end of the display device. |
| US07969512B2 |
Memory bandwidth amortization
A system for processing video information, the system including a memory configured to store video information, a memory controller coupled to the memory and configured to receive memory requests for the video information, a first video signal processing client coupled to the memory controller. The first video signal processing client including a video signal processor, a buffer coupled to the video signal processor, and a memory request module coupled to the memory controller and to the buffer, the memory request module being configured to submit amortized memory requests to the memory controller. |
| US07969511B2 |
Method and apparatus for improving quality of composite video signal and method and apparatus for decoding composite video signal
A method and apparatus for improving the quality of a composite video signal and a method and apparatus for decoding the composite video signal. The method for improving the quality of the composite video signal respectively detects edges from a luminance information signal and a chrominance information signal separated from the composite video signal, detects an artifact region using the detected edges, and filters the detected artifact region. Accordingly, an artifact can be effectively removed while preserving edge information and detail information of an image to improve picture quality. |
| US07969510B2 |
Video processing system and method with recursive and non-recursive filtering in separate high frequency bands
A video noise reducer divides a signal into spatial frequency bands and derives both recursively and non-recursively filtered signals for each band. Both signals are processed non-linearly. These signals are combined in ways that vary between the bands to provide a noise signal and a detail signal. A clean video signal with all noise removed is used in the recursive loop. The output signal includes detail enhancement and may have a subjectively pleasant amount of noise added back. |
| US07969509B2 |
Aspect ratio enhancement
An adaptive compensation system for aspect ratio conversion. Video information, intended for her first aspect ratio display, e.g. the standard NTSC aspect ratio, is processed to determine additional information that can enable that video to be displayed and fill a wider aspect ratio screen. The processing can be a calculation which calculates, for example, texture, color and/or brightness of the edge portions, and automatically calculates video information to match the texture, brightness or color. The processing can be a database lookup, which automatically looks up likely portions from a database. The processing can also be an adaptive determination of what vertical portions of the image can be stretched without affecting the viewability, and then an adaptive stretching of different portions by different amounts. |
| US07969507B2 |
Video signal receiver including display synchronizing signal generation device and control method thereof
A video signal receiver including a display synchronizing signal generation device and control method are disclosed. The video signal receiver includes: a video processor converting an input analog video signal into a digital signal; a display processor scaling the video signal converted at the video processor with an output resolution; a displaying unit displaying the video signal scaled by the display processor; a detecting unit detecting whether an input vertical synchronization signal (In V-sync) and an output vertical synchronization signal of the analog video signal match; a PLL (Phase Locked Loop) adjusting a pixel clock according to a detection result of the detecting unit; and a timing generating unit generating an output horizontal synchronization signal and the output vertical synchronization signal by use of the pixel clock adjusted by the PLL, and providing the generated output horizontal and output vertical synchronization signals to the display processor and the detecting unit. Accordingly, it is possible to prevent twitching and freezing of a screen, even though input and output frame rates do not correspond. |
| US07969504B2 |
Camera system and camera
A camera system including a camera having an image displaying unit that displays various images and an external flash device that is connected to the camera when in use. To the camera is connectable either a first external flash device whose light emission amount is settable according to an operation input to the first external flash device by a user or a second external flash device whose light emission amount is settable based on information on a light emission amount transmitted from the camera as the external flash device. The camera displays an image having a different content on the image display unit between when the first external flash device is connected thereto and when the second external flash device is connected thereto. |
| US07969503B2 |
Portable electronic device for capturing images
A portable electronic device having a main body, the device including a camera arrangement for capturing images in a plurality of directions relative to the main body of the device; a lighting element; and a reflector, at least a portion of which is movable about the lighting element to change the direction of light reflected from the lighting element. |
| US07969497B2 |
Image capturing apparatus having a movable display screen
An image capturing apparatus includes a camera body having an image-capturing lens for receiving light to form an image of a subject and a display unit having a display screen for displaying the image. The display unit is slidably supported by the camera body. A surface of the display unit opposite a surface having the display screen disposed thereon faces a surface of the camera body opposite a surface having the image-capturing lens disposed thereon. An image capture button is disposed on the surface of the camera body opposite the surface having the image-capturing lens disposed thereon. The image capture button is exposed when the display unit is slid over the camera body in a first direction and the image capture button is covered by the display unit when the display unit is slid over the camera body in a second direction opposite the first direction. |
| US07969494B2 |
Imager and system utilizing pixel with internal reset control and method of operating same
A pixel having no dedicated reset control line. By using the voltage on the column line to control the gate of the reset transistor, there is no need to provide a dedicate reset control line. |
| US07969491B2 |
Light detection apparatus
An amount of charges consonant with the intensity of the light entering photodiodes is generated, and the level of the charges is determined by a charge level determination circuit. Based on this determined charge level, a capacitance setting circuit sets a capacitance of an integrating capacitor unit in an integrating circuit. Thereafter, in the integrating circuit, the charges generated by the photodiodes are integrated in the integrating capacitor unit, and a voltage having a value consonant with the amount of the integrated charges is output. When background light is strong and the overall intensity of incident light is high, a comparatively large capacitance is set for the variable capacitor unit of the integrating circuit, and the intensity of the incident light is detected without saturation. When background light is weak and the overall intensity of incident light is low, a comparatively small capacitance is set for the variable capacitor unit of the integrating circuit, and the intensity of the incident light is detected at high sensitivity, regardless of the surrounding conditions. |
| US07969484B2 |
Solid-state image sensing device
There is provided a solid-state image sensing device including a pixel section in which cells are arrayed, each cell including a photoelectric conversion unit, a reading circuit reading out, to a detection unit, signal charges obtained by the photoelectric conversion unit, an amplifying circuit amplifying and outputting a voltage corresponding to the signal charges, and a reset circuit resetting the signal charges, an exposure time control circuit controlling an exposure time and controlling the exposure time to be equal for all cells, an A/D conversion circuit A/D-converting a signal output from the pixel section by changing a resolution of a signal level, line memories storing an A/D-converted signal, and a signal processing circuit processing output signals from the line memories to have a linear gradient with respect to an optical input signal amount by controlling an amplification factor in accordance with a resolution of a pixel output signal after A/D-conversion. |
| US07969480B2 |
Method of controlling auto white balance
There is provided a method of controlling auto white balance that can be appropriately used for a camera of an electric device that uses a wide-angle or a super wide-angle lens. A method of controlling auto white balance according to an aspect of the invention may include: converting a color space of an input image from an RGB color space into a YCbCr color space; dividing the input image into a plurality of divided regions; selecting a predetermined number of divided regions in order determined by mean values of Y of pixels included in the plurality of divided regions; comparing a predetermined threshold value with the number of pixels having values of Cb and Cr within a predetermined Cb-Cr range among the pixels included in the selected divided regions in order to determine a white area; and calculating auto white balance gains by using mean values of Y, mean values of Cb, and mean values of Cr of the pixels included in each of the selected divided regions when the number of pixels within the predetermined Cb-Cr range is greater than the threshold value. |
| US07969476B1 |
Method for accessing a pixel and a device having pixel access capabilities
A method for accessing a pixel, the method includes: providing a fixed reference current to a readout circuit that is coupled to a pixel, wherein the fixed reference current is indifferent to changes in a pixel output current drained by the pixel; wherein a value of the pixel output current is responsive to light impinging on the pixel during an integration period; and sampling a difference signal that is responsive to a different between the fixed reference current and the pixel output current while providing the fixed reference current to the readout circuit. |
| US07969473B2 |
Image-pickup apparatus
Image-pickup sections and an image-communicating/processing section 138 are connected by a single bus. Following the output of the image data, an output-controlling section in one of the image-pickup sections outputs an image-data-ending pattern, which indicates the end of outputting the image data, to a bus. An ending-pattern-detecting section in another image-pickup section detects the image-data-ending pattern, and outputs an image-pickup-operation-starting signal. The another image-pickup section starts an image-pickup operation and output of the image data based on the image-pickup-operation-starting signal. |
| US07969471B2 |
Control apparatus and control method
A control apparatus receives a third command from a remote control apparatus. The control apparatus determines which of the first interface unit and the second interface unit is used to connect an image capture apparatus and the control apparatus, if a mode of the image capture apparatus is not the same as a mode designated by the third command. If the first interface unit is used to connect the image capture apparatus and the control apparatus is determined, the third command is converted into a first command for changing the mode of the image capture apparatus to the mode designated by the third command. If the second interface unit is used to connect the image capture apparatus and the control apparatus is determined, the third command is converted into a second command for changing the mode of to the image capture apparatus to the mode designated by the third command. |
| US07969467B2 |
Printing system, printing device, imaging device, printing method and image-transmitting method
A printing system of the present invention connects an imaging device and a printing device logically, decides an amount of data of an image suitable for communication according to a speed of the communication; and changes the amount of data of the image to be transmitted and received according to the decision. |
| US07969465B2 |
Method and apparatus for substrate imaging
The invention provides a substrate surface imaging method and apparatus that compensates for non-linear movement of the substrate surface during an imaging sequence. In one aspect of the invention, the imaging method and apparatus compensate for the non-linear substrate surface movement by adjusting the image receiver trigger points to correspond to image positions on the substrate surface. In another aspect, the invention provides synchronous imaging where the distance between each image position is determined by counting the number of stepper motor steps between image positions. In still another aspect, the invention provides for asynchronous substrate imaging by determining an image trigger time between each image position and using the image trigger time to trigger the receiver at the appropriate time to accurately image the substrate surface. |
| US07969461B2 |
System and method for exchanging connection information for videoconferencing units using instant messaging
A videoconferencing system includes a first videoconferencing unit coupled to a network and associated with a first instant messaging identity. The first videoconferencing unit obtains a second instant messaging identity and automatically sends a request instant message requesting videoconferencing connection information to the second instant messaging identity. A second videoconferencing unit is coupled to the network and is associated with the second instant messaging identity. The second videoconferencing unit receives the request instant message and automatically returns a response instant message including videoconferencing connection information to the first instant messaging identity. The first videoconferencing unit receives the response instant message and automatically obtains the videoconferencing connection information from the response instant message. Using the videoconferencing connection information, the first videoconferencing unit initiates a videoconference call with the second videoconference unit. |
| US07969459B2 |
Thermal print head
A thermal printhead (A) includes an insulating substrate (1), a heating resistor (2) provided on the substrate (1) and a protective film (4) covering the heating resistor (2). The protective film (4) is made up of a first layer (41), a second layer (42) and a third layer (43). The first layer (41) is held in contact with the heating resistor (2). The second layer (42) covers the first layer (41). The second layer (42) is harder than the first layer (41) and has a higher thermal conductivity than that of the first layer (41). The third layer (43) is the outermost layer and covers the second layer (42). The third layer (43) is harder than the second layer (42) and thinner than the second layer (42). |
| US07969456B2 |
Methods and systems for sub-pixel rendering with adaptive filtering
Processing data for a display including pixels, each pixel having color sub-pixels, comprises receiving pixel data, and converting the pixel data to sub-pixel rendered data. In one embodiment, the conversion generates the sub-pixel rendered data for a sub-pixel arrangement including alternating red and green sub-pixels on at least one of a horizontal and vertical axis. Processing the pixel data for the display also includes correcting the sub-pixel rendered data if a condition exists and outputting the sub-pixel rendered data. |
| US07969453B2 |
Partial display updates in a windowing system using a programmable graphics processing unit
Techniques to generate partial display updates in a buffered window system in which arbitrary visual effects are permitted to any one or more windows (e.g., application-specific window buffers) are described. Once a display output region is identified for updating, the buffered window system is interrogated to determine which regions within each window, if any, may effect the identified output region. Such determination considers the consequences any filters associated with a window impose on the region needed to make the output update. |
| US07969452B2 |
Reporting fixed-point information for a graphical model
A graphical modeling environment is provided for a user to build a model in which signals and/or block parameters can be represented using a fixed-point data type. When the graphical model is executed, the graphical model may generate fixed-point data type signals. An exemplary embodiment may information about fixed-point data type signals on the graphical model. Based on the information provided on the graphical model, the user may be able to determine whether an appropriate number of bits are allocated to the integer part of the fixed-point data type signals and/or whether the total number of bits, i.e., the word length is adequate or over-engineered. |
| US07969450B2 |
Method for optimizing display colors of a digital light processing projector
A system for optimizing display colors of a digital light processing projector includes a color analyzer, and a central processing module. The color analyzer is configured for detecting a first image produced by the projector to obtain actual brightness proportions of red, green, and blue light components associated with the first image, and obtaining a color coordinate of the first image at the actual brightness proportions. The central processing module is configured for adjusting the actual brightness proportions to pre-set brightness proportions to form a second image. The color analyzer detects the second image to obtain a color coordinate thereof. The central processing module adjusts the color coordinate of the second image to a pre-set standard color coordinate, and changes the first gamma curve of the projector to a second gamma curve according to the adjusted color coordinate of the second image. |
| US07969449B2 |
Systems and methods for color control of display devices
Various techniques for implementing aspects of color control in display devices are disclosed. One exemplary technique includes measuring an input/output profile of a display, then applying a mathematical model to the display's measured profile to generate color control tables. One exemplary technique may include tracking a first color temperature below a high-luminosity transition point and gradually transitioning to tracking a second color temperature above the high-luminosity transition point. One exemplary technique may also include gradually transitioning from tracking a darklight color temperature below a low-luminosity transition point to tracking the first color temperature above the low-luminosity transition point. Another exemplary technique may include tracking a response curve for a specified chromaticity above a low-luminosity transition point. |
| US07969448B2 |
Apparatus and method of converting image signal for six color display device, and six color display device having optimum subpixel arrangement
A method of converting image signals for a display device including six-color subpixels is provided, which includes: classifying three-color input image signals into maximum, middle, and minimum; decomposing the classified signals into six-color components; determining a maximum among the six-color components; calculating a scaling factor; and extracting six-color output signals. |
| US07969447B2 |
Dynamic wrinkle mapping
A method for a computer system includes retrieving a plurality of base poses for an object, retrieving a plurality of base texture maps associated with the plurality of base poses, receiving a desired pose for the object, determining a plurality of coefficients associated with the plurality of base poses in response to the desired pose and to the plurality of base poses, and determining a desired texture map in response to the plurality of coefficients and to the plurality of base texture maps. |
| US07969446B2 |
Method for operating low power programmable processor
A graphics processor is disclosed having a programmable Arithmetic Logic Unit (ALU) stage for processing pixel packets. Scalar arithmetic operations are performed in the ALUs to implement a graphics function. |
| US07969445B2 |
System, method, and computer program product for broadcasting write operations
A system, method, and computer program product are provided for broadcasting write operations in a multiple-target system. In use, a write operation is received at one of a plurality of apertures of an address space. Such write operation is then replicated to produce a plurality of write operations. To this end, the write operations may be broadcasted to a plurality of targets. At least one of the targets includes another one of the apertures that produces at least one additional write operation. |
| US07969437B2 |
Method and apparatus for triangle representation
Embodiments of the invention provide for accelerated polygon intersection testing of rays against a set of polygons. The amount of computation required in the rendering process is reduced by preprocessing the scene into a data structure that can be more efficiently traversed. During the preprocessing stage, triangles such as triangle may be converted into vertex and edge representation. |
| US07969432B2 |
Providing for application integrity, improved start-up time, and reduced memory utilitization in a safety-critical graphics processing environment
At least one of graphics operation description information or graphics object description information (106) is included within application logic (102). At least one of the graphics operation description information or graphics object description information (106) is included in the program address space of a graphics driver (108). |
| US07969431B2 |
Graphical program node for generating a measurement program
A system and method for performing a measurement task. A node is displayed in a graphical program, and configured to receive a measurement task specification (MTS). The node may be coupled to an MTS node, or to a configuration node which constructs the MTS at run time. When the program executes, the node receives the MTS, invokes an expert system to analyze the MTS, optionally validate the MTS, generates a run-time specification for the task. The node them invokes a run-time builder to analyze the run-time specification and generate a run-time based on the run-time specification, where the run-time is executable to perform the measurement task. The node may be a read node, a write node, or a start node connected to a read or write node. Additional operations may be performed prior to or during the first iteration, and/or during or after the last iteration, of the task. |
| US07969430B2 |
Voltage controlled backlight driver
A system for powering and controlling an LED backlight, the system comprising: a control circuitry; a controllable power source responsive to the control circuitry; and a plurality of LED strings receiving power from the controllable power source, the control circuitry being operative to control the output voltage of the controllable power source responsive to a function of an electrical characteristic of at least one of the plurality of LED strings. |
| US07969429B2 |
Sustain driver, sustain control system, and display device
The collector, emitter, and base of a bipolar transistor circuit are connected to a high side power supply terminal, the drain of a level shift transistor, and a floating power supply terminal, respectively. When a high side output transistor is on, the floating power supply terminal is at the potential of a high potential power supply terminal. The high side power supply terminal is at a potential higher than the potential of the floating power supply terminal by a constant voltage. Turning the level shift transistor on, its drain potential drops below the potential of the floating power supply terminal; The base current flows through the bipolar transistor circuit and the drain potential of the level shift transistor is clamped near the potential of the floating power supply terminal; The bipolar transistor circuit is turned on and its collector current supplies the drain current of the level shift transistor. |
| US07969420B2 |
Handheld electronic device having facilitated input and associated method
An improved handheld electronic device and an improved method facilitate the entry of data when the data is provided in a predetermined data format. In the depicted exemplary embodiment, the handheld electronic device includes a user interface that facilitates the entry of data having a predetermined data format. |
| US07969411B2 |
Operating panel
The present invention provides an input device where the input, is created by translating a front plate in relation to the chassis such that the translation movement may easily be controlled, and at the same time, due to the freedom built into the device, any level of menu control and selection criteria may be provided. |
| US07969410B2 |
Optically detecting click events
Apparatus and method of optically detecting click events are described. Images of a contact surface are captured at respective capture times. The captured images are convolved with a two-dimensional circularly symmetric spatial bandpass filter to produce corresponding filtered images each including a set of pixels with respective pixel value magnitudes. Based on the pixel value magnitudes of the corresponding filtered images, each of the capture times is assigned to one of an in-contact time class during which the contact surface is determined to be in-contact with a user's finger and an out-of-contact time class during which the contact surface is determined to be out-of-contact with the user's finger. A select signal indicating that the contact surface has been touched to make a selection is generated based on a click event predicate defining at least one condition on the time classes respectively assigned to successive ones of the capture times. |
| US07969407B2 |
Backlight driving circuit with follower and liquid crystal display using same
An exemplary backlight driving circuit (20) a first power supply (260); a second power supply (270); a signal output terminal (280); an AND gate (210); a follower (220); a capacitor (290); a reverser (230); a first transistor (240), which is a N-Channel mode metal-oxide-semiconductor field-effect transistor (N-MOSFET), having a gate electrode connected to an output end of the AND gate through the follower, a source electrode connected to the signal output terminal, a drain electrode connected to the first power supply; and a second transistor (250), which is a N-Channel mode metal-oxide-semiconductor field-effect transistor (N-MOSFET), having a gate electrode connected to the output end of the AND gate through the reverser, a source electrode connected to the ground, a drain electrode connected to the signal output terminal. |
| US07969406B2 |
Backlight driving system for a liquid crystal display device
A backlight driving system for a backlight unit for a liquid crystal display device using a field sequential driving scheme, the backlight unit including a plurality of first color (C1), second color (C2), and third color (C1) organic light emitting diodes (OLEDs), a first switch unit including first, second and third color switches, the first switch unit adapted to supply one of a first voltage and a ground voltage to cathodes of respective C1, C2 and C3 OLEDs, and a light source controller adapted to supply independent first, second and third color second voltages to anodes of respective C1, C2 and C3 OLEDs. |
| US07969405B2 |
Double-sided LCD panel
There is disclosed a double-sided liquid crystal display (LCD) panel which includes a first polymer dispersed liquid crystal (PDLC) layer configured to be responsive to an applied DC voltage for making the first PDLC layer substantially transparent; a center liquid crystal cell layer; a second PDLC layer configured to be responsive to an applied DC voltage for making the second PDLC layer substantially transparent; and an LCD control module configured to control the first and second PDLC layers such that the center liquid crystal cell layer is viewable from a selected viewing side. Depending on the selected viewing side, the LCD control module is configured to select one of the first and second PDLC layers to make substantially transparent, and the other of the first and second PDLC layers to make substantially translucent. A light source may be applied to a side of a translucent one of the PDLC layers to provide a backlight for the center liquid crystal layer. |
| US07969403B2 |
Driving circuit, driving method, and liquid crystal display using same
An exemplary driving circuit (20) includes: gate lines (23); data lines (24); pixel units (240); a gate driving circuit (21); a data driving circuit (22); a signal output circuit configured for providing a set of signals in each frame, each signal in the set of signals selectively being a black signal or a white signal; and a select output circuit (26) configured for receiving the data signals from the data driving circuit and the set of signals from the signal output circuit. When a signal of the set of signals provided by the signal output circuit is a black signal, the select output circuit provides the black signal to a corresponding data line. When a signal of the set of signals provided by the signal output circuit is a white signal, the select output circuit provides a corresponding one of the data signals to the corresponding data line. |
| US07969402B2 |
Gate driving circuit and display device having the same
A gate driving circuit and a display device having the same, in which the gate lines can be divided into p groups using p shift registers and p-time gate lines can be driven using a signal shifted by 1/p, wherein p is an arbitrary natural number of three or more. Accordingly, since a number of gate lines can be driven using the plurality of shift registers, high-resolution display devices can be manufactured at a low cost. |
| US07969398B2 |
Display drive apparatus and display apparatus
A display pixel including a light-emitting element and a drive element for supplying current flowing in a current path to the light-emitting element is applied with a detection voltage based on a predetermined unit voltage. Based on a value of current flowing in the current path of the drive element, a specific value corresponding to an element characteristic of the drive element is detected. A gradation voltage corresponding to a luminance gradation of display data is generated. Based on the specific value and the unit voltage, a compensated voltage is generated. By compensating the gradation voltage based on the compensated voltage, a compensated gradation voltage is generated. And the compensated gradation voltage is supplied to the display pixel. |
| US07969395B2 |
Spatial light modulator and mirror device
The present invention discloses a spatial light modulator includes a plurality of pixel elements disposed on a substrate. Each of the pixel elements comprises a deflectable micromirror. Specifically, instead of SRAM, the spatial light modulator is implemented with a DRAM in each of the pixel elements. The DRAM in each of the pixel elements has a smaller number of transistors than SRAM. The spatial light modulator can be manufactured with smaller pixel size and circuit configuration with improved withstand voltage. Further improvements can also be achieved for manufactured the spatial light modulator with smaller capacitor with better layout configuration for wire connections and control signal transmissions. |
| US07969390B2 |
Display device and driving method thereof
To solve the lack of program time, which is a problem of a display device including an EL element, and to provide a display device including a pixel circuit with a high aperture ratio and a driving method thereof. In a circuit including a driving transistor, a capacitor, a display element which can be used as a capacitor, a first power supply line and a second power supply line, potentials of the first power supply line and the second power supply line are set to be almost the same, thereby a threshold voltage of the driving transistor is held in the display element, and after that, a charge is divided into the display element and the capacitor. |
| US07969389B2 |
Pixel circuit for a current-driven light emitting element
Pixel circuit 210 includes a current programming circuit 240 and voltage programming transistors 251 and 252. In order to set the tone of the light emission from the organic EL element 220, the first and second voltage programming transistors 251 and 252 are set to the OFF and ON state, respectively, and voltage programming is carried out using a voltage signal Vout. Next, the states of the first and second voltage programming transistors 251 and 252 are switched, and current programming is carried out using a current signal Iout. |
| US07969386B2 |
Plasma display apparatus having separated electrodes and method of driving plasma display
A plasma display apparatus and a method of driving the plasma display apparatus are provided. The plasma display apparatus includes a plasma display panel including a first electrode and a second electrode, a first electrode driver, and a second electrode driver. The first electrode driver supplies a first falling signal of a voltage magnitude, that is more than a voltage magnitude of a scan signal supplied during an address period, to the first electrode before the supply of a rising signal with a gradually rising voltage in at least one subfield of several subfields of a frame. The second electrode driver supplies a second signal having a polarity opposite a polarity of the first falling signal to the second electrode during the supply of the first falling signal. |
| US07969384B2 |
Deformable micromirror device
A micromirror device, which makes an image display with digital image data, comprises pixel elements each of which makes pulse width modulation (PWM) for incident light depending on the deflection state of light and which are arranged in the form of a matrix. Each of the pixel elements has a mirror, at least one memory cell comprising a transistor and a capacitor, and an electrode connected to each transistor. Memory cells arranged successively in a ROW direction are connected by a ROW line. The image data is loaded at a time interval during which the voltage of the electrode can hold the deflection state of a pixel element. |
| US07969380B2 |
Antenna gasket for process housings
A method and apparatus for providing wireless communication and optionally power to the interior of a housing assembly is disclosed. In one embodiment, an antenna is molded within a gasket material, such as silicon, so as to be completely encapsulated. The gasket preferably includes at least one support arm, which holds the antenna toward the middle of the housing, so as to minimize interference from the metal housing. In further embodiments, an inductive coil is encapsulated in the gasket. An alternating current is passed through this coil to create a changing magnetic field, which can then be used to create electrical power in physically separate components, such as filtering elements. In certain embodiments, multiple loops are molded to correspond to multiple filtering elements within the housing. |
| US07969375B2 |
Spherical motor positioning
According to the invention, a system for rotating a parabolic antenna about a central point is disclosed. The system may include a support member, a spherical structure, and at least one arm. The support member may be coupled with a surface and may also be coupled with the support member. The spherical structure may be at least partially spherical in shape about the central point. The spherical structure may include a first plurality of magnets. The at least one arm may be in proximity to the spherical structure and may also include a second plurality of magnets. The at least one arm may be coupled with the parabolic antenna, and at least a portion of the magnets in either one of, or both of, the first plurality of magnets and the second plurality of magnets may be configured to be selectively activated to rotate the arms about the central point. |
| US07969374B1 |
Multipath manipulator
A multipath enhancer is disclosed ias including more than one antenna. At least one of a receiver and a transmitter is coupled to the more than one antenna. A selectively reflective surface is adjacent the more than one antenna. A controller is configured to alter the reflectivity of the selectively reflective surface. |
| US07969373B2 |
UHF/VHF planar antenna device, notably for portable electronic equipment
A planar antenna device (AD) for a TV receiver (R) comprises i) a loop antenna (LA) comprising first (E1) and second (E2) ends spaced one from the other, ii) a tuning means (TM) connected to the first (E1) and second (E2) ends of the loop antenna (LA) and arranged to control the frequency of the VHF TV signals this loop antenna (LA) is able to receive from command signals, iii) a first ground plane (GP1) cooperating with the loop antenna (LA) in order to act as a UHF monopole in receiving TV signals with UHF frequencies, iv) a first coupling means (CM1) coupled to the loop antenna (LA) at a first chosen location and arranged to deliver the received VHF signals, v) a second coupling means (CM2) coupled to the loop antenna (LA) at a second chosen location and arranged to deliver the received UHF signals, vi) an amplification means (AM) coupled to the first ground plane (GP1) and arranged to amplify TV signals, and vii) a switching means (SM) arranged to couple the amplification means (AM) to the first coupling means (CM1) and/or to the second coupling means (CM2) in dependence on command signals in order that the amplification means deliver amplified selected TV signals with VHF and/or UHF frequencies to an output. |
| US07969369B2 |
Body-worn antenna fastening device and method
A fastening device (200) for releasably securing an antenna assembly (100) on at least one garment (15) of a user (10) is provided. The antenna assembly (100) is part of a portable communication system (50) which includes a portable communication device (125) that is also worn on the garment (15) of the user (10). The fastening device (200) is comprised of a body portion (205) and an elongated receiver portion (210). The elongated receiver portion (210) defines an elongated channel (211) and a pair of resilient undulations (215, 216) which define an elongated opening (212). The pair of resilient undulations (215, 216) serve to guide a segment (110a) of the antenna assembly (100) through the elongated opening (212) and into the elongated channel (211). Once the segment (110a) is urged into the elongated channel (211), the undulations (215, 216) return to the normal position thereby securing the segment (110a) in the elongated channel (211). The fastening device (200) is attached to a loop (16) on the at least one garment (15) of the user (10) with straps using hook and loop fasteners, a pair of slide keeper clips, or a carabineer clip. |
| US07969368B2 |
Wideband structural antenna operating in the HF range, particularly for naval installations
A structural antenna system for operation in the HF frequency range, particularly for naval communications, is described, comprising at least one linear radiating arrangement (14) adapted to be operatively associated with a ground conductor (GND) and at least one electrical impedance device (Z1-Z4), in which the aforesaid linear radiating arrangement (14) is coupled to a pre-existing naval structure which has a predominantly vertical extension and is electrically conducting, such as a funnel (F). A structural antenna system with multiple feed comprises a plurality of linear radiating arrangements (114) positioned in meridian planes of the naval structure of the funnel type (F), spaced at equal angular intervals. |
| US07969367B2 |
Antenna coupler
An antenna coupler for testing a transmitter and/or receiver device for wireless communication, in particular, a mobile telephone, comprises a holding element for the transmitter and/or receiver device and several antenna elements, which are arranged in such a manner that the directions of maximum radiation or respectively directions of maximum sensitivity of the antenna elements are oriented differently relative to one another in space. |
| US07969362B2 |
Super wide bandwidth coupling antenna
A super wide bandwidth coupling antenna comprises a first radiation portion made of electric conductor; the first radiation having a body and a feeding frame extending from a body of the first radiation portion; a second radiation portion formed by an electric conductor; a supporting frame extending from a body of the second radiation portion; a ground portion made of electric conductor; one end of the ground portion being connected to the supporting frame of the second radiation portion; a signal feeding wire having a main signal end wire which is electrically connected to the feeding frame of the first radiation portion; a ground end wire of the signal feeding wire being electrically connected to the ground portion; an isolation post for positioning the first radiation portion and second radiation portion with an insulating gap between the first radiation portion and second radiation portion. |
| US07969360B2 |
High resolution, arbitrary-even-order direction finding method and device
Method of high-resolution direction finding to an arbitrary even order, 2q (q>2), for an array comprising N narrowband antennas each receiving the contribution from P sources characterized in that the algebraic properties of a matrix of cumulants of order 2q, C2q,x(l), whose coefficients are the circular cumulants of order 2q, Cum[xi1(t), . . . , xig(t), xiq+1(t)*, . . . , xi2q(t)*], of the observations received on each antenna, for cumulant rankings indexed by l, are utilized to define a signal subspace and a noise subspace. |
| US07969355B2 |
Methods and apparatus for obtaining accurate GNSS time in a GNSS receiver
A method for obtaining GNSS time in a GNSS receiver includes: deriving a relationship between a first clock signal and the received GNSS time; latching a second clock signal and the first clock signal at a first latching point to obtain a clock value A1 of the first clock signal and a clock value B1 of the second clock signal; calculating a GNSS time C1 corresponding to the clock value A1 according to the relationship; latching the first clock signal and the second clock signal at a second latching point to obtain a clock value A2 of the first clock signal and a clock value B2 of the second clock signal; and calculating a GNSS time C2 corresponding to the clock value A2 according to the GNSS time C1, the clock value B1, and the clock value B2. |
| US07969352B2 |
Global positioning system accuracy enhancement
Methods and systems enhance the accuracy of the global positioning system (GPS) using a low earth orbiting (LEO) satellite constellation. According to embodiments described herein, GPS data is received from GPS satellites at a GPS control segment and is used to create GPS correction data to be utilized by user equipment to correct errors within the GPS data. The GPS correction data is transmitted from the GPS control segment to a LEO ground segment, where it is uplinked to the LEO satellite constellation. To account for bandwidth constraints and minimize any performance degradation of the LEO satellites, the GPS correction data is broadcast to earth on a subset of the total number of available spot beams. The subset of spot beams is selected in part according to satellite angular velocity, bandwidth constraints, and message latency estimates. |
| US07969349B2 |
System and method for suppressing close clutter in a radar system
A system for processing electromagnetic waves in a radar system is disclosed. The system includes a transmitter operable to transmit operating waves and calibration waves, one or more receivers operable to receive reflected calibration waves and operating waves, and a system controller operable to process the received calibration waves and operating waves. The system controller may process the received waves by generating a threshold signal based on the calibration waves, and comparing the threshold signal to the operating waves. The system controller may also process operating waves and calibration waves in accordance with one or more signal conditioning algorithms. Additionally, the system controller may display an image representing a target on a display by comparing received operating waves with the generated threshold signal. |
| US07969347B2 |
Method for measuring distance and position using spread spectrum signal, and an equipment using the method
By using the delay profile created by delay profile creating section 102 and the first threshold value 330 received from the first threshold value calculation 105, the first threshold value timing detection section 103 selects only the earliest receive timing exceeding the first threshold value, from all the timing that the correlation value in the delay profile becomes a maximum. By using the receive timing and the second threshold value 331 received from the second threshold value calculation section 107, reference timing calculation section 106 selects the reference timing required for calculating the receive timing for the incoming wave of the minimum propagation delay time. The timing delayed by previously set timing behind said reference timing is sent from receive timing calculation section 108 as the receive timing 113 of the incoming wave of the minimum propagation delay time. |
| US07969346B2 |
Transponder-based beacon transmitter for see and avoid of unmanned aerial vehicles
A transponder-based beacon transmitter system in an unmanned aerial vehicle is provided. The transponder-based beacon transmitter system comprises a global positioning system interface communicatively coupled to receive position information indicative of a current location of the unmanned aerial vehicle, a message formatter communicatively coupled to the global positioning system interface, and a transponder-based beacon transmitter. The message formatter formats vehicle identification of the unmanned aerial vehicle and the position information indicative of the current location of the unmanned aerial vehicle into an automatic dependent surveillance broadcast mode-select squitter message. The message formatter operates in one of a military mode, a National Airspace System mode, and a combined military/National Airspace System mode. The transponder-based beacon transmitter transmits the automatic dependent surveillance broadcast mode-select squitter messages from the unmanned aerial vehicle. Receivers in the vicinity of the unmanned aerial vehicle receive unsolicited vehicle identification and location of the unmanned aerial vehicle. |
| US07969341B2 |
Sigma-delta modulator including truncation and applications thereof
A multi-stage sigma-delta modulator including bit truncation between stages. The bit truncation reduces the number of bits that must be processed in subsequent stages and thus allows for faster response times. In some embodiments, the gain of a feedback loop is selected to compensate for the bit truncation such that the sigma-delta modulator operates in a stable state. |
| US07969338B2 |
Decoding circuit for flat panel display
The present invention relates to a decoding circuit for a flat panel display, and more particularly to a decoding circuit for a flat panel display wherein a miniaturization is possible by reducing an area of the circuit. There is provided a decoding circuit comprising: a first decoder for selecting a predetermined number of gradation voltages from a plurality of gradation voltages according to a least significant bit or least significant bits of an image data; a second decoder for selecting one of the selected gradation voltages to be outputted to an output terminal according to a plurality of selection signals; and a third decoder for outputting the plurality of the selection signals according to a most significant bit or most significant bits of the image data, wherein a minimum length of gates of a plurality of MOSFETs included in the first decoder is shorter than that of a plurality of MOSFETS included in the second decoder. |
| US07969337B2 |
Systems and methods for two tier sampling correction in a data processing circuit
Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes an analog to digital converter, a digital interpolation circuit, a phase error circuit, and a phase adjustment control circuit. The analog to digital converter samples an analog data input at a sampling phase governed at least in part by a coarse control, and provides a series of digital samples. The digital interpolation circuit interpolates between a subset of the series of digital samples based at least in part on a fine control. The phase error circuit calculates a phase error value. The phase adjustment control circuit is operable to determine the coarse control and the fine control based at least in part on the phase error value. |
| US07969336B2 |
Sample-hold circuit having spreading switch and analog-digital converter using same
A sample-hold circuit includes a voltage-current converter, having a first input terminal pair to which an input differential signal is input and a first output terminal pair which outputs current according to the voltage of the input differential signal, a spreading switch having a switch group which switches the first output terminal pair to inverting or non-inverting states, and an integrator having a second input terminal pair coupled to the first output terminal pair via the spreading switch, an output amplifier which outputs to a second output terminal pair an output differential signal amplified according to the differential signal at the second input terminal pair, a capacitor pair which is provided respectively between the second input terminal pair and second output terminal pair, and which is charged or discharged by current input to the second input terminal pair, and a reset circuit which resets charge states of the capacitor pair. |
| US07969333B2 |
Complexity-aware encoding
Techniques for encoding data based at least in part upon an awareness of the decoding complexity of the encoded data and the ability of a target decoder to decode the encoded data are disclosed. In some embodiments, a set of data is encoded based at least in part upon a state of a target decoder to which the encoded set of data is to be provided. In some embodiments, a set of data is encoded based at least in part upon the states of multiple decoders to which the encoded set of data is to be provided. |
| US07969327B2 |
Device for managing the waking up phase of an aircraft pilot
A device for managing an awakening phase, in flight, of a pilot in the cockpit of an airplane, following a rest period, to guarantee his or her return to a state estimated compatible with flying operations, also called state of vigilance, wherein it includes management means for inducing progressive physical stimuli for generating an awareness by the resting pilot that his or her rest period is over, starting a procedure in the form of actions to be carried out by the pilot, means for displaying the procedure drawn up by the management means. The management device includes a warning device in case a state of hypo-vigilance is detected in the pilot, which is activated when the pilot is assumed to be in a state of vigilance. |
| US07969326B2 |
Parking assist method and parking assist apparatus
A parking assist apparatus outputs display of a synthesized image of the periphery of a vehicle as a bird's-eye view image, and superimposes, on the synthesized image, turning guide lines based on the current steering angle of the vehicle and straight driving guide lines, along which the vehicle drives in a straight line after turning in accordance with the turning guide lines. |
| US07969323B2 |
Instrumented component for combustion turbine engine
An instrumented component (18, 19) for use in various operating environments such as within a combustion turbine engine (10). The component (18, 19) may have a substrate, a sensor (50, 94, 134) connected with the substrate for sensing a condition of the component (18, 19) during operation of the combustion turbine (10) and a connector (52, 92, 140) attached to the substrate and in communication with the sensor (50, 94, 134) for routing a data signal from the sensor (50, 94, 134) to a termination location (53). The component (18, 19) may include a wireless telemetry device (54, 76, 96) in communication with the connector (52, 92, 140) for wirelessly transmitting the data signal. Recesses (114, 116) may be formed with a root portion (112, 132) of components (18, 19) within which wireless telemetry device (54, 76, 96) may be affixed. |
| US07969322B2 |
Processor
A processing apparatus that is connected with another processing apparatus via a network, receives a request for a processing from the other processing apparatus, executes the requested processing while not performing an originally intended process of the processing apparatus, and indicates that the processing apparatus is executing the requested processing, by causing an indicator to blink on and off. |
| US07969320B2 |
Systems and methods for detecting a patch cord end connection
Systems and methods for detecting a patch cord connection are presented. The insertion of a patch cord into a device jack physically closes a circuit, thereby permitting determination of the patch cord connection. The connection of only one side of a patch cord to a jack is able to be determined. In addition, a particular jack with which a patch cord is connected is able to be determined. |
| US07969318B2 |
Flow detector with alarm features
The disclosed invention relates to detecting a flow condition in a fluid supply system. The invention is particularly useful for detecting flow in a toilet system. The flow detection device comprises a processor associated with a flow sensor. Predefined flow criteria are stored in a memory associated with said processor. When the processor detects flow through the fluid supply system, the processor uses the flow criteria to characterize the detected flow. If such flow complies with predefined flow conditions, a flow event is noted and an alert is issue. Such alert is configured according to predefined alert-criteria stored in a memory. |
| US07969315B1 |
Sensor device and method for monitoring physical stresses placed upon a user
A sensor device for monitoring physical stresses placed on a user has a sensor body with pressure sensors for sensing pressure and generating a pressure data signal indicating the pressures sensed. An alert mechanism functions to alert the user when the pressure sensed by the pressure sensors exceeds predetermined threshold force levels. The sensor device is utilized to enable a method of monitoring the physical stresses and alerting the user when the predetermined threshold force levels are exceeded. |
| US07969308B2 |
Seal arrangement
A seal arrangement having monitoring means and a seal portion. The monitoring means includes means for determining the integrity of the seal portion, the determining means being arranged to deliver a signal to radio frequency identification (RFID) means for producing an output signal in response to the integrity of the seal portion as determined by the means for determining. The present invention also provides a container, a pipe section, a pipeline and a closure member provided with such a seal arrangement. |
| US07969304B2 |
Secured bag locking and tracking device
A secure container for controlling and monitoring access to at least one secured bag locking device is disclosed. The secure container is lockable to prevent access by unauthorized parties, and may include any feature of prior art secure containers, such as shock detection or a camera to photograph access. The secure container contains a number of rails to provide power to and monitor the status of docked secured bag locking devices. In addition, the secure container includes an antenna to allow secured devices to be tethered to it via communications with an active radio frequency identification tag secured to the tethered device. |
| US07969302B2 |
System and method for dynamic association of security levels and enforcement of physical security procedures
A method and system for dynamic association of security levels and enforcement of security procedures. A secure object can be tracked across a building or complex, and security levels may be dynamically updated to reflect the new security requirement. In response to the security level adjustment, security measures and protocols may be implemented dynamically. The system comprises a sensitivity index assigned to each of a plurality of secure objects, a scanner for detecting the sensitivity index, and a logic unit in communication with the scanner for determining a security level for the secure area based on the sensitivity indices of the plurality of secure objects within the secure area. The method comprises detecting a plurality of secure objects within a secure area, each secure object having a sensitivity index, and determining a security level for the secure area based on the sensitivity indices of the plurality of secure objects within the secure area. |
| US07969301B2 |
Personal radio location system
Methods and apparatus for using an energy emanating device to find a person (17a,b) or an object based on preselected attributes (33) stored in the energy emanating device (10) are disclosed. |
| US07969296B1 |
Method and system for fire detection
A method and system are provided, which provides reliable fire detection. In one implementation, the automated system includes a combination of sensors configured to measure various factors associated with a hazard, such as a fire or gas leakage, and generate sensor readings. Factors measured can include smoke, carbon monoxide and heat. The system further includes a detection device that is configured to determine whether a hazard or fire exists by performing a fuzzy analysis of sensor readings. The fuzzy analysis includes categorizing respective sensor readings into fuzzy sets, and determining whether the hazard exists based on a combination of the categorizations. In addition the size and direction of a fire can be determined from multiple sensors. |
| US07969293B2 |
Integrated read station for a wheel-mounted vehicle
A read station and method for a vehicle includes a support pad for admitting and exiting a vehicle onto an upper pad surface; two or more data-receiving systems, one or both of such systems receiving a data transmission from a vehicle situated on the read station pad surface. The data-receiving systems include an identification-data transmission system and a monitored parameter-data transmission system. One or more of the read station data-receiving systems may be configured to effect data transmission from the vehicle as the vehicle moves across the support pad. The information-data transmission system couples a vehicle wheel unit based RFID tag with an electric field established by one or more system antennae disposed on the support pad. The monitored parameter-data communication system includes one or more wheel-unit mounted monitoring device(s) transmitting data to one or more receivers disposed within the read station and an initiator sub-system that transmits a signal from pad based antenna(s) to initiate a data transmission sequence. |
| US07969288B2 |
Force feedback system including multi-tasking graphical host environment and interface device
A force feedback system provides components for use in a force feedback system including a host computer and a force feedback interface device. An architecture for a host computer allows multi-tasking application programs to interface with the force feedback device without conflicts. One embodiment of a force feedback device provides both relative position reporting and absolute position reporting to allow great flexibility. A different device embodiment provides relative position reporting device allowing maximum compatibility with existing software. Information such as ballistic parameters and screen size sent from the host to the force feedback device allow accurate mouse positions and cursor positions to be determined in the force feedback environment. Force feedback effects and structures are further described, such as events and enclosures. |
| US07969287B2 |
Haptic effect control system
A haptic effect control system includes: a user interface adapted to receive a user-provided input and transmit a control signal representing the user-provided input; a controller in communication with the user interface and adapted to receive the control signal, analyze the control signal, and generate and transmit a first haptic-audio signal in response to the analysis of the control signal, wherein the first haptic-audio signal represents a first audio output for creating a desired sound pressure deviation from the ambient pressure of the user's environment; and an audio system including a device capable of producing the first audio output having a desired sound pressure level, wherein the audio system is adapted to receive the first haptic-audio signal and transmit the first audio output in response to the first haptic-audio signal. |
| US07969282B2 |
Optimized operation of a dense reader system
Methods, systems and apparatuses for RFID readers forming a reader network are described. In an aspect of the present invention, a plurality of RFID readers are configured to interrogate tags. Furthermore, the readers are configured to communicate with one another. Each of the readers include a ID number which identifies that particular reader within a reader network during communications. Each reader includes a network interface module and an optimization module to receive and process statistical data obtained from other readers in the network. Aspects of the present invention include a ‘primary/secondary’ reader network configuration, as well as a ‘distributed elements’ reader network configuration. A set of operational rules for the environment is indicated, and tag interrogations are optimized according to the rules. Readers may communicate according to a “Listen Before Talk” (LBT) protocol to avoid undesirable interference. Individual readers are capable of dynamically establishing and joining a network, and leaving the network in a self-configured and semi-autonomous or autonomous manner. |
| US07969279B2 |
Remote control system and presetting method for remote commander
Disclosed herein is a remote control system including a remote commander and a main device having a capability to connect with a subordinate device. The main device includes: a display; a first storage device for storing a plurality of sets of remote control codes; a first signal reception circuit; a first signal transmission circuit for, e.g., transmitting to the remote commander a set of remote control codes corresponding to a subordinate device; and a control unit. The remote commander includes: a second signal reception circuit for receiving the set of remote control codes; a second storage device for storing the set of remote control codes; a second signal transmission circuit; and an operation section for transmitting a remote control code transmission control signal for causing the control unit to perform remote control code transmission control for selecting the set of remote control codes and transmitting the set of remote control codes. |
| US07969276B2 |
Thin film varistor array
A method of forming a thin film varistor array includes creating a metal-metal oxide-metal layer stack without breaking vacuum. The stack is patterned as a plurality of bus lines, each having a plurality of varistor islands formed thereon. |
| US07969275B2 |
Fuse assembly with integrated current sensing
A fuse assembly includes a main component partially encased in a protective sheath. The main component includes a pair of connectors formed of an electrically conductive material to allow the fuse assembly to be electrically connected into an electric vehicle drive system. A fusible link is electrically connected between the connectors and is preferably encased in the protective sheath. The fusible link reacts to current flowing through the fuse assembly in excess of a predetermined current for a predetermined time, as is well known to those skilled in the art. |
| US07969268B2 |
Ignition coil with spaced secondary sector windings
An ignition coil configured for electrical communication with a spark plug of an internal combustion engine has a primary spool and a secondary spool. The primary spool has a bore and an outer surface with a low-voltage winding supported thereon. The secondary spool has a cavity with a magnetic core received therein and a substantially cylindrical outer surface. The secondary spool is received at least partially in the bore of the primary spool. A high-voltage winding is supported on the outer surface of the secondary spool. The high-voltage winding has discrete winding sectors spaced from one another along a length of the secondary spool. |
| US07969267B2 |
Reinforced fluoropolymer plates, production methods thereof, corrosion-resistant reactors containing said plates, production methods of same and fluorination methods performed in said reactors
The invention relates to a reinforced fluoropolymer plate comprising a fluoropolymer layer on one of the faces thereof and a carbon fiber sheet on the other face of same, whereby at least part of the carbon fiber sheet is impregnated with fluoropolymer. The invention also relates to an acid-corrosion-resistant chemical reactor comprising said plates, the production methods thereof and the uses of same in processes in superacid media. |
| US07969266B2 |
Inductor
Provided is an inductor capable of adjusting an inductance in dozens of nH increments without requiring a large number of components. The inductor includes: a conductor; a first core body and a second core body each having an opposed surface, the opposed surface of the first core body and the opposed surface of the second core body facing each other so as to enclose the conductor; and a holding part provided with a slide surface for varying an opposed area of the opposed surfaces of the first core body and the second core body, for holding at least one of the first core body and the second core body at a desired position. |
| US07969261B2 |
Transmission line substrate having overlapping ground conductors that constitute a MIM capacitor
A transmission line substrate includes: a dielectric substrate; a signal line disposed on the upper surface of the dielectric substrate; first and second ground conductors disposed on the upper surface of the dielectric substrate, field-coupled to the signal line, having potentials different from each other; a dielectric film disposed between an overlapping part of the first ground conductor and a part of the second ground conductor at which the first and second ground conductors overlap each other, to constitute a MIM capacitor; a capacitor connected between the first ground conductor and the second ground conductor in parallel with the dielectric film; and a resistor connected between the first ground conductor and the second ground conductor in series with the capacitor. |
| US07969260B2 |
Variable radio frequency band filter
A variable radio frequency band filter includes a housing with a plurality of cavities, a plurality of resonators, wherein one resonator is arranged in each cavity, and a tuning arrangement having a plurality of tuning structures. One of the tuning structures is arranged in each of the cavities. The tuning structures of multiple cavities are mechanically connected such that the tuning structures may be shifted simultaneously in order to simultaneously vary the resonance frequencies of the cavities. Each tuning structure includes at least one first metallic surface facing the resonator and at least one second metallic surface facing a wall of the cavity, the first and second metallic surfaces being conductively connected. The second metallic surface is arranged such that a small and essentially uniform gap is formed between the second metallic surface and the wall to achieve a virtual grounding of the metallic surfaces. |
| US07969257B2 |
Tunable microwave devices with auto-adjusting matching circuit
An embodiment of the present invention provides an apparatus, comprising a power amplifier with a tunable impedance matching circuit including a plurality of tunable dielectric varactors and a DC voltage source interface capable of providing voltage to said plurality of saud tunable dielectric varactors. |
| US07969256B2 |
Signal transmission circuit and signal transmission system with reduced reflection
A signal transmission circuit includes a transmitting circuit for outputting a transmitting signal to a transmission line, a parallel circuit including a capacitor and a first resistance connected between an output terminal of the transmitting circuit and the transmission line, and a series circuit including an inductor and a second resistance connected between an output side of the parallel circuit and a ground. |
| US07969254B2 |
I/Q impairment calibration using a spectrum analyzer
A quadrature modulator (QM) may be calibrated by determining total equivalent offsets in the I- and Q-channels, a total equivalent gain imbalance between the I- and Q-channels, and a total equivalent phase skew between the I- and Q-channels. These values may be obtained by taking various scalar measurements of the image to signal ratio (ISR) and carrier to signal ratio (CSR) of the QM, while alternatively altering the system gain imbalance, system phase skew, I-channel offset and Q-channel offset using a respective gain parameter, phase parameter, I-channel offset parameter, and Q-channel parameter. The gain and phase parameters may be defined in terms of the ISR, and the channel offset parameters may be defined in terms of the CSR. The system gain imbalance, system phase skew, and total offset in the channels may then be calculated based on the various ISR and CSR measurements. |
| US07969253B2 |
VCO with stabilized reference current source module
A VCO includes a reference current module and a clock signal generating module. The reference current module generates a reference current according to a reference voltage. The clock signal generating module generates a clock signal according to the reference current. The reference current module utilizes the negative feed-back mechanism to keep the generated reference current at the predetermined size without being changed with the variation of the process and the bias source. |
| US07969248B1 |
Oscillator tuning for phase-locked loop circuit
In one example, a method of tuning an oscillator of a phase-locked loop (PLL) circuit includes adjusting a coarse control signal to select one of a plurality of frequency tuning curves of the oscillator. The method includes adjusting a fine control signal to select a position on the selected frequency tuning curve. A frequency of the oscillator is determined by the coarse control signal and the fine control signal. The method includes attempting to detect a lock between a feedback signal and a reference signal. A frequency of the feedback signal is determined by the frequency of the oscillator. The method includes comparing the fine control signal to a reference value if the lock is detected. The method includes adjusting the coarse control signal to select a different one of the frequency tuning curves if the selected position on the selected frequency tuning curve is outside a desired tuning range. |
| US07969246B1 |
Systems and methods for positive and negative feedback of cascode transistors for a power amplifier
Systems and methods are provided for positive and negative feedback of cascode transistors for a power amplifier. The systems and methods may include a first cascode stage comprising a first common-source device and a first common-gate device; a second cascode stage comprising a second common-source device and a second common-gate device; a first degenerative element or block provided for the first common-source device; a second degenerative element or block provided for the second common-source device; a first positive feedback block or element that connects a first gate of the first common-source device with a second drain of the second common-source device; and a second positive feedback block or element that connects a second gate of the second common-source device with a first drain of the first common-source device. |
| US07969245B2 |
Millimeter-wave monolithic integrated circuit amplifier with opposite direction signal paths and method for amplifying millimeter-wave signals
Embodiments of a high-frequency millimeter-wave amplifier are generally described herein. The high-frequency millimeter-wave amplifier may be constructed on a substrate to operate at a frequency of at least 75 GHz. In some embodiments, the millimeter-wave amplifier may include at least first, second, third and fourth amplifier stages coupled in series. A single drain bias bond pad provided on the substrate to provide a drain bias voltage to the drains of the first, second, third and fourth amplifier stages. Drain bias lines may be electrically coupled to the single drain bias bond pad and extend at least partially alongside and between some of the amplifier stages. A signal path through the second amplifier stage extends in a direction opposite of signal paths through the first and third amplifier stages. In some embodiments, a 95 GHz amplifier is provided and configured occupy an area on the substrate of no greater than approximately four square millimeters. |
| US07969242B2 |
Switching power amplifier for quantized signals
An apparatus and method for communications are disclosed. The apparatus may include an a quantizer having three levels, and a switching power amplifier configured to drive a load having first and second terminals, wherein the switching power amplifier is further configured to switch the first and second terminals between first and second power rails only if the output from the quantizer is at one of the three levels. |
| US07969238B2 |
Active filter having a multilevel topology
A cost-effective device for influencing the transmission of electrical energy of an alternating voltage line with a plurality of phases has phase modules, which each have an alternating voltage terminal for connecting to a phase of the alternating voltage line and two connecting terminals. A phase module branch extends between each connecting terminal and each alternating voltage terminal. The phase module branch is formed of a series connection of sub-modules, each having a power semiconductor circuit and an energy accumulator connected in parallel to the power semiconductor circuit. The connecting terminals are connected to one another. The power semiconductor circuit is equipped with power semiconductors that can be switched off and are connected to each other in a half bridge. |
| US07969234B2 |
Clock control circuit and voltage pumping device using the same
A clock control circuit is provided. The clock control circuit includes a voltage supplier for supplying a first voltage in response to a first clock signal, a voltage booster for boosting the first voltage in response to the first clock signal input to the voltage booster, and a clock generator for generating a second clock signal having a voltage level equal to the boosted first voltage in response to the first clock signal. |
| US07969233B2 |
Boosting charge pump circuit
In order to resolve a problem of the conventional technique in which there is a charge pump capacitance which is not used when a boosting method of the charge pump is changed, in a charge pump circuit unit, a connection switching terminal selects a power source voltage, a logically-inverting buffer gate and a capacitor to conduct an operation of boosting the power source voltage so as to be twice the power source voltage, and a connection switching terminal outputs the boosted voltage as a boost control voltage. In a charge pump circuit unit, a connection switching terminal selects the boost control voltage outputted from the charge pump circuit unit, and a logically-inverting buffer gate and a capacitor conduct an operation of boosting the inputted voltage so as to be 3×VRD. An internal voltage is generated by outputting the boosted voltage to an internal power line via a NMOS transistor. |
| US07969230B2 |
Voltage generating circuit
A charge pump provides high boosting efficiency with low power loss even with a heavy load. Plural charge transfer switches are connected in series forming two lines of charge transfer circuits operated by out-of-phase clock signals. Capacitors are connected to each of nodes in the charge transfer circuits. The charge transfer circuits include a first control unit, a second control unit, and a voltage comparison output unit. The second control unit includes a switch unit configured to selectively feed a signal from a previous-stage node or a later-stage node to the gate of a charge transfer switch in the second control unit, depending on the phase of the clock signal. |
| US07969226B2 |
High temperature gate drivers for wide bandgap semiconductor power JFETs and integrated circuits including the same
Gate drivers for wide bandgap (e.g., >2 eV) semiconductor junction field effect transistors (JFETs) capable of operating in high ambient temperature environments are described. The wide bandgap (WBG) semiconductor devices include silicon carbide (SiC) and gallium nitride (GaN) devices. The driver can be a non-inverting gate driver which has an input, an output, a first reference line for receiving a first supply voltage, a second reference line for receiving a second supply voltage, a ground terminal, and six Junction Field-Effect Transistors (JFETs) wherein the first JFET and the second JFET form a first inverting buffer, the third JFET and the fourth JFET form a second inverting buffer, and the fifth JFET and the sixth JFET form a totem pole which can be used to drive a high temperature power SiC JFET. An inverting gate driver is also described. |
| US07969216B2 |
System and method for improved timing synchronization
Embodiments of a method and system for both open-loop and closed-loop timing synchronization are provided in which a master clock signal, and a plurality of signals that define greater periods of time, are distributed to a plurality of host devices. A frame-sync signal is used to define a “frame” consisting of a predetermined number of clock periods, and a reset signal is used to define a larger period consisting of a predetermined number of frames. Due to a variety of system parameters, the innate delay time associated with each respective timing distribution path may differ. The system is operable to adjust the timing signals propagated to the plurality of host devices along each respective timing distribution path to compensate for these differences so that each host device remains synchronized with all other host devices. |
| US07969211B2 |
Power detecting device, power supply device using the same and reference voltage generator
A power detecting device, a power supply device using the same, and a reference voltage generator are provided. The power detecting device adapted to detect a power voltage of a display device includes a bandgap voltage generating circuit, a voltage regulating circuit, and a power-on reset circuit. The bandgap voltage generating circuit provides a reference voltage via an output terminal thereof. The voltage regulating circuit and the power-on reset circuit are coupled to the output terminal of the bandgap voltage generating circuit. When the power voltage doesn't reach a threshold voltage, the voltage regulating circuit increases the reference voltage referred by the power-on reset circuit. When the power voltage reaches the reference voltage, the power-on reset circuit generates a reset signal to reset the display device. Therefore, when the power voltage doesn't reach a stable, the power-on reset circuit will not be incorrectly started by increasing the reference voltage. |
| US07969209B2 |
Frequency divider circuit
Fractional frequency division is performed by sequentially selecting phase signals for division, where transitioning from a previous phase signal to a next phase signal for division occurs in response to not only the frequency-divided previous phase signal but also a second one of the phase signals. A phase transition that is triggered at least in part in response to a second phase signal having a phase that is greater (with respect to the phase signal sequence) than the phase of the next phase signal can aid minimization of signal glitches. The first frequency-divided signal can be further divided to produce a second frequency-divided signal having a 50-percent duty cycle. |
| US07969205B2 |
Peak power reduction method
A technique wherein when signals, the modulation schemes of which are different, are to be combined, performing the peak suppression using amounts of the respective modulation schemes can effectively reduce the PAPR of a resulting combined signal. A peak suppressing method for use in a peak suppressing circuit, which combines input signals of different modulation schemes in a time domain to provide a combined signal, comprises detecting, as a peak, that portion of the combined signal which excesses a threshold value to generate a peak signal in accordance with the peak; converting the peak signal into a frequency domain signal and then dividing it into signals originating from the input signals to use these input-signal-originated signals as respective suppression signals; and adding, to the input signals, the suppression signals having different suppression amounts for the respective modulation schemes, thereby performing the peak suppression. |
| US07969202B2 |
Fractional-N frequency synthesizer
A circuit, with applications to phase-locked loops and frequency synthesis, where a divider circuit shuffles between dividing the output of a voltage-controlled oscillator by N or N+1, where N is an integer, and where a phase frequency detector provides three logic signals to a charge pump so that one of three values of current may be sourced to a loop filter, with the result that the circuit behaves as a conventional phase-locked loop having a fictitious divider circuit that is capable of dividing the output of the voltage-controlled oscillator by a non-integral value. |
| US07969201B2 |
Decoder circuit
A decoder circuit that can prevent the delay of decoder output includes a switch that is put into an ON state when a node A of an NMOS region is not an output channel of a selected gradation voltage. The switch is connected to the node A. Thus, a voltage raised by electric charges accumulated by a coupling capacity C1 caused in the node A when the gradation voltage is outputted from an output terminal of the decoder output can be discharged by the switch in the ON state. |
| US07969200B2 |
Decoder circuit
A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal. |
| US07969199B1 |
Pattern controlled IC layout
The invention provides a reduced complexity layout style based on applying a limited set of changes to an underlying repeated base template. With the templates properly defined in accordance with the characteristic features disclosed, the invention enables efficient implementation of logic circuitry, with a dramatic reduction in the pattern complexity (or number of unique layout patterns at each mask level) for realistically sized designs. This reduction in pattern complexity that the invention provides is particularly important for advanced and emerging semiconductor processes, because it enables effective use of SMO and full-chip mask optimization. |
| US07969195B1 |
Active biasing in metal oxide semiconductor (MOS) differential pairs
Apparatus and methods advantageously maintain transistors of open-drain differential pairs biased in the saturation region when “active,” rather in than the triode or linear region. The biasing techniques are effective over a broad range of process, voltage, and temperature (PVT) variations. By controlling a high voltage level used to drive the gate of a transistor of the differential pair, the biasing of the transistor in the saturation region is maintained. In one embodiment, the low voltage level used to cut off the transistor of the differential pair is also controlled. These techniques advantageously permit differential drivers to exhibit relatively large output swings, relatively high edge rates, relatively high return loss, and relatively good efficiency. |
| US07969189B2 |
Method and system for improved phase noise in a BiCMOS clock driver
System and method for a clock driver. An input taking circuit is used for receiving small-signal logic inputs. A voltage follower circuit is coupled to the input taking circuit and used to generate a set of voltage follower outputs. An output circuit is coupled to the voltage follower circuit to receive the set of voltage follower outputs as inputs and generate output signals. The voltage follower circuit is coupled to a switching circuit, that is connected to the set of voltage follower outputs and is deployed for reducing the phase noise level of the output signals. |
| US07969187B1 |
Hardware interface in an integrated circuit
A hardware interface in an integrated circuit is disclosed. The hardware interface comprises data storage coupled to store and provide data; a data shifter coupled to the data storage to at least bit shift the data obtained from the data storage; and a control circuit coupled to the data storage and the data shifter for controlling a transfer of the data from the data storage and the data shifter. The control circuit comprises a state machine for controlling operation of the data storage and the data shifter; and the state machine is programmable responsive to code executable by a processor coupled to an auxiliary processing unit to adapt to the auxiliary processing unit. |
| US07969183B2 |
Semiconductor device
The present invention is directed to adjust a resistance value of an output buffer on the basis of a resistance value of an external resistor. A potential according to a resistance ratio between an external resistor and each of resistance adjusters is detected by a code generator. In the code generator, code signals for adjusting resistance are adjusted in accordance with the detection result. The resistance value of each of the resistance adjusters is adjusted to an external resistor. Further, by code signals with which the resistance value of each of the resistance adjusters is adjusted to the resistance value of the external resistor, the resistance of the resistance value of an output buffer is adjusted. |
| US07969182B2 |
Semiconductor devices having ZQ calibration circuits and calibration methods thereof
Provided is a semiconductor device for performing a calibration operation without an external ZQ calibration command and a calibration method thereof. The semiconductor device includes a calibration circuit for performing a pull-down calibration operation in response to a pull-down calibration enable signal and a command control unit for generating the pull-down calibration enable signal in response to a DLL reset signal. The calibration method includes adjusting an impedance of a first pull-up resistance structure in response to pull-up calibration codes having a default value. A pull-down calibration enable signal may be generated in response to a DLL reset signal. A voltage of the first node and a reference voltage are compared by a comparator. The comparator outputs pull-down calibration codes based on the comparison. An impedance of a pull-down resistance structure is adjusted, so a resistance of the pull-down resistance structure is equal to a resistance of the first pull-up resistance structure. |
| US07969181B1 |
Device and method for adjusting an impedance of an output driver of an integrated circuit
A device and method for adjusting an impedance of an output driver of an integrated circuit; the method includes: (i) receiving, by the output driver, a first square wave signal that should be driven by the output driver to provide a second signal; (ii) monitoring, by a monitoring circuit included in the integrated circuit, the second signal during an output driver transient period resulting from a first square wave signal transient to provide a monitoring result; (iii) determining whether to adjust the impedance of the output driver in response to the monitoring result; and (iv) adjusting the impedance of the output driver in response to the determination. |
| US07969178B2 |
Method and apparatus for controlling qubits with single flux quantum logic
In one embodiment, the disclosure relates to a method and apparatus for controlling the energy state of a qubit by bringing the qubit into and out of resonance by coupling the qubit to a flux quantum logic gate. The qubit can be in resonance with a pump signal, with another qubit or with some quantum logic gate. In another embodiment, the disclosure relates to a method for controlling a qubit with RSFQ logic or through the interface between RSFQ and the qubit. |
| US07969173B2 |
Chuck for holding a device under test
A chuck for a probe station. |
| US07969170B2 |
Microcontactor probe with reduced number of sliding contacts for Conduction, and electric probe unit
In order for a conduction path to have a reduced number of sliding portions for conduction, without increase in inductance nor resistance, thereby permitting an enhanced accuracy of inspection, a pair of plungers (3, 4) biased in opposite directions by a coil spring (2), to be electrically connected to a wiring plate (10), have electrical connections in which, in a tubular portion (15) as a tight wound spiral portion (15a) fixed on one plunger (4) to allow linear flow of electrical signal, the other plunger (3) is brought into slidable contact. |
| US07969169B2 |
Semiconductor integrated circuit wafer, semiconductor integrated circuit chip, and method of testing semiconductor integrated circuit wafer
A semiconductor integrated circuit wafer includes: a plurality of semiconductor integrated circuit regions each of which includes a semiconductor integrated circuit formed thereon; a scribe region which separates the semiconductor integrated circuit regions adjacent to each other; a build in self test (BIST) circuit which is provided in the scribe region and inspects the semiconductor integrated circuit; a connection wiring which is formed ranging from the scribe region to the semiconductor integrated circuit region and connects the semiconductor integrated circuit and the BIST circuit; a BIST switching signal input pad which is provided in the semiconductor integrated circuit region; and a BIST switching circuit which is provided in the semiconductor integrated circuit region and is driven by a driving signal input from the BIST switching signal input pad, the BIST switching circuit including: an input-output pad which connects with the semiconductor integrated circuit; a circuit wiring which connects the input-output pad with the semiconductor integrated circuit; and a switch element which is provided at a middle position of the circuit wiring and is driven by the driving signal input from the BIST switching signal input pad. |
| US07969167B2 |
Capacitance-to-voltage interface circuit with shared capacitor bank for offsetting and analog-to-digital conversion
A capacitance-to-voltage interface circuit includes a capacitive sensing circuit, an amplification circuit adapted for selective coupling to the capacitive sensing circuit, a capacitor bank comprising a plurality of binary-weighted capacitors, and a switching architecture associated with the capacitive sensing circuit, the amplification circuit, and the capacitor bank. The switching architecture reconfigures the capacitance-to-voltage interface circuit for operation in a plurality of different phases, including an amplification phase and an analog-to-digital conversion phase. During the amplification phase, the capacitor bank is utilized for offsetting capacitance of the amplification circuit. During the analog-to-digital conversion phase, the capacitor bank is utilized in a successive approximation register. |
| US07969162B2 |
Method and device for dynamic adjustment of network operating voltage
The present invention is to provide a method and device of dynamically adjusting the operating voltage of a network integrated circuit including the steps of detecting and ranking the signal-to-noise ratio of N ports to single out a port for arbitration, dynamically controlling the operating voltage according to the signal-to-noise ratio of the port for arbitration, decreasing the operating voltage by a voltage unit when the signal-to-noise ratio of the port for arbitration is greater than a first threshold, increasing the operating voltage to a default operating voltage when the signal-to-noise ratio of the port for arbitration is smaller than the first threshold, decreasing the operating voltage by a voltage unit when the signal-to-noise ratio of the port for arbitration is greater than a second threshold, and increasing the operating voltage by a voltage unit when the signal-to-noise ratio of the port for arbitration is smaller than the second threshold. |
| US07969152B2 |
Systems and methods for measuring sea-bed resistivity
A method for measuring the resistivity of sea-bed formations is described. An electromagnetic field is generated using at least one stationary long-range transmitter. The frequency of the electromagnetic field is between and/or including the ULF/ELF range. At least one component of the electromagnetic field is measured. A conductivity distribution is determined based on the at least one measured component. The determined conductivity distribution is correlated with geological formations and/or hydrocarbon deposits. |
| US07969150B2 |
Demagnetizer to eliminate residual magnetization of wellbore wall produced by nuclear magnetic resonance logs
An apparatus and method is disclosed for measuring a parameter of an earth formation surrounding a wellbore. A Nuclear Magnetic Resonance (NMR) tool and at least one second tool are conveyed in the wellbore on a wireline, the NMR tool having a magnetic influence on a region of the wellbore. The magnetic influence of the NMR tool is removed from the region of the wellbore using a demagnetizing device. The parameter of the earth formation is measured using the at least one second tool. A second demagnetizing device may be used to remove the magnetic influence of the at least one second tool from the region of the wellbore. |
| US07969148B2 |
Magnetic sensor device, magnetic encoder device and magnetic scale manufacturing method
A magnetic sensor device may include “A”-phase magnetic resistance pattern and “B”-phase magnetic resistance pattern which are provided with a phase difference of 90° from each other; wherein the “A” pattern is provided with “+a” phase magnetic resistance pattern and “−a” phase magnetic resistance pattern with a phase difference of 180° from each other for detecting movement of a magnetic scale, and the “B” pattern is provided with “+b” phase magnetic resistance pattern and “−b” phase magnetic resistance pattern with a phase difference of 180° from each other for detecting movement of the magnetic scale, and the “+a” pattern, the “−a” pattern, the “+b” pattern and the “−b” pattern are formed on a same face of one piece of board so that the “+a” pattern and the “−a” pattern are diagonally located and the “+b” pattern and the “−b” pattern are diagonally located. |
| US07969146B2 |
Displacement measurement device
An displacement measurement device and associated method where displacement measurements of a movable member are obtained by an electromagnetic field sensor that need not move relative to the magnet or other electromagnetic field source. The electromagnetic field sensor senses disruptions in the electromagnetic field caused by movement of the movable member to provide an output indicative of the position of the actuator. |
| US07969144B2 |
Sensor device for measuring a magnetic field
A sensor device for measuring a magnetic field in the region of a primary part of a permanently excited electrical machine or a corresponding primary part having teeth includes a sensor metal plate for conducting a magnetic field, a spacer, and a sensor for measuring a magnetic field. A distance between the sensor metal plate and a flank of a tooth of the primary part can be created by the spacer. The sensor may be a Hall sensor and is arranged in a region of the sensor metal plate between the sensor metal plate and the primary part. |
| US07969142B2 |
System and method for magnetic tracking of a sensor having an asymmetric magnetic core
A system and method for determining the location of a remote object connected to an induction coil using a magnetic tracking sensor. The system and method include locating a magnetic core asymmetrically disposed within the induction coil located near the remote object, and operably connecting a single DC electrical circuit o ends defining the induction coil. The DC electrical circuit provides a DC current to the induction coil while the induction coil is disposed in an external AC magnetic field. The DC current adjusts the level of saturation of the magnetic core, and hence varies a response signal of the induction coil disposed in the external AC magnetic field to provide magnetic tracking of the induction coil. |
| US07969132B2 |
Switching power supply unit and control method of switching power supply unit
Decrease in a voltage supplied to a load caused by load fluctuations is minimized. A pulse frequency modulated signal generating unit 13 outputs a signal PFMOUT having a pulse frequency modulated according to a voltage supplied to the load 20. A pulse width modulated signal generating unit 14 outputs a signal PWMOUT having a pulse width modulated according to a voltage supplied to the load 20. In a state where the signal PFMOUT is selected, a selection unit 17 refers to a determination result of a frequency determining unit 15 and selects the signal PWMOUT as on/off signal for a semiconductor switch 11 when a low-level period in one cycle of the signal PFMOUT is not more than a predetermined time period. In a state where the signal PWMOUT is selected, the selection unit 17 selects the signal PFMOUT as on/off signal for the semiconductor switch 11 when a voltage determining unit 16 detects that a DC voltage (VOUT) at the load 20 exceeds a predetermined voltage. |
| US07969131B2 |
Converter circuit with forward and backward control
The present invention relates to a converter circuit and a conversion method for converting an input signal of a first value to an output signal of a second value based on a switched operating mode, wherein an output feedback loop (40) and an additional input forward control loop (60) are provided. The additional input forward control loop (60) serves to correctly control a switching parameter not only with respect to the output load but also over a wide input voltage range. This leads to an improved power efficiency and reliability of the converter circuit. |
| US07969125B2 |
Programmable power control system
A power control system includes a switching power converter and a programmable power factor correction (PFC) and output voltage controller. The programmable PFC and output voltage controller generates a control signal to control power factor correction and voltage regulation of the switching power converter. In at least one embodiment, the control signal is a pulse width modulated signal. The programmability of the PFC and output voltage controller provides the programmable PFC and output voltage controller flexibility to operate in accordance with programmable parameters, to adapt to various operating environments, and to respond to various operating exigencies. In at least one embodiment, the programmable PFC and output voltage controller includes a state machine to process one or more programmable, operational parameters to determine the period and pulse width states of the control signal. |
| US07969123B2 |
Exciter assemblies
An exciter assembly for supplying a field current to the rotor windings of a superconducting synchronous machine includes a pulse transformer having a stationary primary winding and a secondary winding that is mounted to the rotor of the superconducting synchronous machine for rotation therewith. A switched mode power supply supplies a pulsed voltage to the primary winding of the pulse transformer. The pulsed voltage developed at the secondary winding of the pulse transformer is supplied to the rotor windings through a rectifier semiconductor device and a pair of transfer leads. The rotor windings and a flywheel semiconductor device are located inside a cryogenic chamber or cryostat. The flywheel semiconductor device is connected in parallel with the rotor windings and operates in unison with the rectifier semiconductor device in order to provide synchronous rectification of the switched mode power supply output. The switched mode power supply and both the primary and secondary windings of the pulse transformer are located outside the cryostat. |
| US07969111B2 |
Numerical controller for controlling a five-axis machining apparatus
A numerical controller capable of moving a tool end point position to an accurate position in a five-axis machining apparatus. Compensation amounts are set, which correspond to respective ones of a linear axis-dependent translational error, a rotary axis-dependent translational error, a linear axis-dependent rotational error, and a rotary axis-dependent rotational error, which are produced in the five-axis machining apparatus. A translational/rotational compensation amount Δ3D is determined from these compensation amounts and added to a command linear axis position Pm. As the compensation amounts, there is used a corresponding one of six-dimensional lattice point compensation vectors, which are determined in advance as errors due to the use of a mechanical system and measured at lattice points of lattices into which the entire machine movable region is divided. |
| US07969107B2 |
Motor control device
A microcomputer compares a low voltage LV and a middle voltage MV to a predetermined voltage Vth set at a value in the vicinity of the grounded voltage (0 V) on the basis of detected phase voltages Vu, Vv and Vw, and thus, detects a break in a power supply line. |
| US07969106B2 |
Vector controller for permanent-magnet synchronous electric motor
A method of controlling a current command by comparing voltage with a set value needs to vary the set value depending on voltage fluctuation, which involves taking a complicated control. A vector controller for a permanent-magnet synchronous electric motor, according to the present invention, can realize with a simplified configuration a field-weakening operation in a one-pulse mode in a high speed range by providing a current command compensator that corrects a current command by a corrected current command calculated based on a modulation index. |
| US07969105B2 |
Capacitor based energy storage
An electrical storage device comprises a capacitor or capacitor bank capable of storing significant quantities of electricity. An inverter in circuit with the capacitor converts direct energy of the capacitor into alternating current. A variable ratio transformer is in circuit with the output of the inverter to produce an alternating current output of controlled voltage. The impedance of the transformer acts to prolong discharge of the capacitor over a significant time period. To further control the rate of discharge of the energy storage capacitor, an additional capacitor may be provided in the transformer circuit. |
| US07969103B2 |
Block switching transient minimization for linear motors and inductive loads
A block switch controller for a linear motor is disclosed, the block switch controller having a motor current threshold profile controlling the switching of a plurality of block switches in a linear motor. Also, a block switch controller for a linear motor comprising a closed loop vector current controller that incorporates a delay state having a feedback gain is disclosed. Additionally, a method of switching a plurality of block switches that minimizes switching transients is provided. Finally, an article of manufacture containing computer code implementing a modeling and simulation program for modeling a linear motor system is provided. |
| US07969097B2 |
Lighting device with color control, and method of lighting
A lighting device comprising a group of one of more illumination solid state light emitters, a reference solid state light emitter and a reference sensor which detects an intensity of the reference solid state light emitter. Each of the emitters (1) has an illumination which is spaced from a first point by a delta u′, v′ distance on a 1976 CIR diagram of not more than 0.015, and/or (2) has a forward voltage temperature dependence which is within 5% of a first forward voltage temperature dependence. In addition, a lighting device comprising one or more illumination solid state light emitters, a reference solid state light emitter and a sensor which comprises at least two areas of individual sensors. Also, methods of lighting. |
| US07969092B1 |
Gas discharge display
A single substrate AC and/or DC gas discharge (plasma) display device comprised of hollow microspheres containing ionizable gas at a predetermined pressure, each microsphere being positioned on the surface of the substrate or within a substrate cavity, well, or hollow. Each microsphere is in electrical contact with 2, 3, or more electrodes. The AC or DC gas discharge within each microsphere emits photons in the visible and/or invisible range. In one embodiment, photons from the gas discharge within a microsphere excite a luminescent substance or material such as a phosphor that emits photons in the visible and/or invisible spectrum. The microsphere may contain the luminescent substance or the substance may be located separately from, but in close proximity to, the microsphere. |
| US07969090B2 |
Light emitting device and display
A light emitting device containing a semiconductor light emitting component and a phosphor, the phosphor is capable of absorbing a part of light emitted by the light emitting component and emitting light of a wavelength different from that of the absorbed light, is provided. A straight line connecting a point of chromaticity corresponding to a spectrum generated by the light emitting component and a point of chromaticity corresponding to a spectrum generated by the phosphor is substantially along a black body radiation locus in a chromaticity diagram. |
| US07969088B2 |
Method of using silicon molecular components for controlling charge migration and light emission of organic light-emitting diodes
New organic light-emitting diodes and related electroluminescent devices and methods for fabrication, using siloxane self-assembly techniques. |
| US07969087B2 |
Organic light emitting diode display and method for manufacturing the same
An organic light emitting device including a first pixel, a second pixel, and a third pixel displaying different colors from each other according to the present invention is disclosed, wherein the organic light emitting device includes a substrate, a pixel electrode formed on the substrate, a reflecting electrode facing the pixel electrode, an emission layer disposed between the pixel electrode and the reflecting electrode, and a transflective member forming a micro-cavity along with the reflecting electrode, wherein a optical path length is a distance between the reflecting electrode and the transflective member, and the optical path lengths of at least two pixels among the first pixel, the second pixel, and the third pixel are the same, and the transflective member is removed in the white pixel. |
| US07969085B2 |
Color-change material layer
A color-change material layer comprising: a color-change material that converts light of a second frequency range higher than a first frequency range to light of the first frequency range; and a transparent material having a refractive index of at least 1.6 intermixed with the color-change material, wherein the layer is substantially non-scattering to light of the first frequency range. |
| US07969082B2 |
Electron beam apparatus
It aims to improve electron emission efficiency in an electron beam apparatus which includes laminated electron-emitting devices. To achieve this, there are provided an insulating member which has a concave portion on its surface, a cathode which is positioned astride a side surface of the insulating member and an inner surface of the concave portion, a gate which is positioned opposite to the cathode, and a protruding portion which is formed on the gate. In this constitution, the low potential surface of the cathode which is positioned inside the concave portion is inclined to the side of the gate from the entrance toward the interior of the concave portion. |
| US07969080B2 |
Electron source
The present invention provides an electron source that can produce a stable electron beam even if an apparatus employing the electron source receives vibration from the outside. An electron source comprising an insulator, a pair of conductive terminals attached to the insulator, a filament tensed between the pair of conductive terminals, a rod-shaped cathode having a sharp end portion performing as an electron emitting portion and joined with the filament, wherein the cathode has another end portion different from the electron emitting portion, fixed to the insulator. It is preferred that said another end portion of the cathode other than the electron emitting portion, is fixed to the insulator via a metal pin brazed with the insulator. |
| US07969076B2 |
LED lamp and adjustable lamp cap thereof
An LED lamp includes a cooling member, a light source, a lamp cover and a pair of lamp caps arranged at opposite ends of the cooling member. The cooling member has an elongated heat absorbing plate forming a heat absorbing surface at one outer side thereof. The light source includes a plurality of LEDs arranged on the heat absorbing surface. The lamp cover covers the LEDs therein and engages with the cooling member. Each lamp cap includes an end cap fixed on the cooling member and a connector rotatably connected with the end cap. The connector includes a pair of poles being electrically connected to the LEDs and extending outwardly therefrom for inserting into a lamp holder to get a power for the LEDs. |
| US07969075B2 |
Thermal storage system using encapsulated phase change materials in LED lamps
A phase change material (PCM) is used as thermal storage for lighting systems. The PCM is placed in a thermally conductive container in close contact with the lighting system. As the PCM absorbs heat, it changes from a solid to a liquid state, but the temperature of the PCM is clamped at its melting point temperature. For LED-based systems, the PCM is selected to have a melting point such that the junction temperatures of the LEDs in the system are maintained at approximately their optimum operating temperature inside the lighting system housing. Because the thermal conductivity of the molten PCM is poor, a low thermal resistance heat flow path is provided from the PCM to the container. |
| US07969072B2 |
Electronic device and manufacturing method thereof
An electronic device includes: a package including a lid and a package base, the package being formed by bonding the lid to a joint surface of the package base using a bonding material; and a resin portion covering the package. The resin portion covers at least the package base and the bonding material, and at least a part of the resin portion has a section outline. The section outline has an outermost portion thereof in a direction parallel with a mount surface of the electronic device. The outermost portion is located below a lower surface of the lid in a direction perpendicular to the mount surface of the electronic device. |
| US07969070B2 |
Electroactive polymer transducer
An electroactive polymer transducer comprising a membrane formed of an approximately rectangular electroactive polymer portion surrounded by two electrodes, at least two points of the membrane being connected to rigid supports, and comprising at least one deformable element for limiting the deformations that the membrane may undergo, the limiting element having a meandering form and being connected to the membrane in several approximately distributed points. |
| US07969062B2 |
Energy converting apparatus, generator and heat pump provided therewith and method of production thereof
A high-efficiency thermionic energy converter comprises a multilayer vacuum diode, the layers of which are very thin and the intermediate spaces between the layers are several nanometers thick. The layers are held at a distance from each other by arranging insulator elements embedded in the layers. One of the intermediate spaces is provided with a thin, open conductive elastic foam plate which fills the spaces possibly occurring due to deformation of an upper electrode. On the cold side the distance between the layers must be so small that here the thermionically generated current is increased by tunneling of electrons from layer to layer. The partial efficiency per layer is as optimal as possible by means of the choice of the geometry and the material. For the purpose of pumping heat from for instance the thick electrode to the other thick electrode of the converter, or vice versa, in accordance with the Peltier effect, a current is conducted through the converter which is increased by tunneling of electrons. Cooling or heating takes place subject to the current direction. |
| US07969058B2 |
Permanent magnet motor with stator having asymmetric slots for reducing torque ripple
Permanent magnet motors with improved torque ripple and methods for designing the same have been provided. The permanent magnet motor can include a stator having a hollow core and defining a plurality of slots; a winding disposed in each of the slots; a rotor rotatably disposed inside the hollow core of the stator; and a plurality of permanent magnets supported by the rotor. Each of the slots has a slot opening, and at least one of the slot openings can be off-center with respect to the respective slot. |
| US07969056B2 |
Rotating electric motor
A rotating electric motor includes a stator core, a rotational shaft capable of rotation, a field yoke allowing a flow of magnetic flux in an axial direction, first and second rotor cores fixedly installed on the rotational shaft, a first magnet fixedly installed between the first rotor core and the second rotor core, a first rotor teeth formed at the first rotor core, a second magnet provided alongside of the first rotor teeth in the circumferential direction of the first rotor core, a second rotor teeth formed at the outer surface of the second rotor core, protruding outwardly in the radial direction, a third magnet provided alongside of the second rotor core in the axial direction, and windings that can control the density of magnetic flux between at least one of the first rotor core and second rotor core and the stator core. |
| US07969052B2 |
Bus bar structure and inverter-integrated electric compressor
A bus bar structure and an inverter-integrated electric compressor that absorb an impact while ensuring vibration resistance are provided. A bus bar structure used for an inverter-integrated electric compressor having a compressor; an electric motor for driving the compressor; an inverter device for converting DC power from a high-voltage power supply to AC power and supplying it to the motor; and a housing for accommodating the compressor, the electric motor, and the inverter device, the inverter device being formed of a circuit board and an electrical component, and an insulating resin for connecting and wiring the circuit board and the electrical component being applied. The bus bar structure is formed of a main body, which is integrally formed of the insulating resin, and an external connecting portion exposed from the insulating resin, the external connecting portion has a bent extending portion that is bent and extends with respect to the main body, and an elastic portion for absorbing vibration of the bus bar structure is formed in part of the bent extending portion. |
| US07969050B2 |
External rotor and housing therefor
A housing for an external rotor with a side wall; an end cover directly connected to the side wall; a cavity formed between the side wall and the end cover; a plurality of openings formed in the side wall; a plurality of wind wheels; a plurality of air inlets, each of the air inlets disposed one between adjacent wind wheels; a base disposed at the center of the end cover and connected to the side wall via the wind wheels; and a center hole disposed at the center of the base, the center hole for forming connection to a drive shaft of the external rotor. An external rotor with the housing, a magnetic conductive housing; and a plurality of magnetic tiles. |
| US07969048B2 |
Can stack linear actuator
A linear actuator motor design including a rotor assembly that has an insert molded into a non-magnetic sleeve through a plurality of openings, which is kept from rotating within the non-magnetic sleeve by at least one opening arranged along the length of the non-magnetic sleeve which corresponds to at least one tab formed by the molded material of the insert and a stator assembly having a plurality of symmetrical and interchangeable magnetic pole plates. Each of the plurality of magnetic pole plates comprises a substantially planar plate portion with a central opening therein and a plurality of prongs extending from the central opening and substantially perpendicular to the plate portion. The prongs of the plurality of magnetic pole plates create an opening that is dimensioned to receive the rotor assembly therein. A non-conductive material is the molded over the plurality of magnetic pole plates. |
| US07969040B2 |
Dual battery vehicle electrical systems
A dual battery electrical system for a vehicle having an engine comprises a primary load and a secondary load and is switchable between an ON state in which the engine is running, an OFF state in which the engine is not running, a START state in which the primary load requires power to start the engine, and a PAUSE state in which the engine is not running. A first battery powers the primary load, a second battery powers the secondary load, a battery switch is closable to connect the first battery to the second battery such that both batteries can provide power to both loads. The transition to and from the OFF state is via a user activated mechanism and transition to and from the PAUSE state is via a user-independent mechanism. A controller controls operation of the battery switch when the system enters and/or leaves the PAUSE state. |
| US07969038B2 |
Power regeneration management system
Properly managing surges of regenerative power is needed in systems where power is generated and distributed to mechanical and electrical loads to protect them from overvoltage. A controller provides protection against excess regenerative power when these systems operate at a wide range of speeds. Controller functions and control methods for overvoltage protection may include an added control loop for detecting an overvoltage condition, calculating a power factor and generating a gating signal to transition the controller into a motoring mode that converts the excess regenerative power into mechanical power. |
| US07969037B2 |
Configuration of a wind turbine nacelle
A wind turbine nacelle configuration includes a frame structure configured for mounting atop a wind turbine tower. The frame structure includes a base, side support members, and top support members. A shell is attached to the frame structure to enclose the nacelle. A drive train may be housed within the frame structure and includes a low speed rotor shaft connected to a gearbox, and a high speed shaft connecting the gearbox to a generator. The frame structure is configured so that at least one component of the drive train is suspended from the top support members within the frame structure. |
| US07969032B2 |
Windmill rotation detection/management device and wind power generation system
An apparatus comprising: a first input that receives a first rotational speed information of a windmill mechanically generated by a mechanical rotation detection unit; a second input that receives a second rotational speed information of the windmill based on an alternating current output of a generator attached to the windmill; and a controller configured to compare the first and second rotational speed information, to determine whether a difference between the first and second rotational speed information is greater than a predetermined value and to execute a predetermined anomaly processing in response to the difference being greater than the predetermined value. |
| US07969030B2 |
Power generation systems and methods of generating power
A power generation system is provided that includes an internal combustion engine configured to provide rotational mechanical energy. A generator is configured to receive the rotational mechanical energy and generate electrical power in response to the rotational mechanical energy. A fluid medium is provided to the internal combustion engine and to the generator for removing thermal energy from the internal combustion engine and from the generator. |
| US07969019B2 |
Module with stacked semiconductor devices
Semiconductor device 1 includes: first wiring board 5 provided with a plurality of external terminals 9 on the under surface thereof; first semiconductor chip 3 with the under surface thereof mounted on the upper surface of first wiring board 5; and second semiconductor chip 10 with the under surface thereof mounted on the upper surface of first semiconductor chip 3. On the upper surface of first wiring board 5, connecting pad 6a and connecting pad 6b are provided, while connecting pad 6a is electrically connected with the under surface of first semiconductor chip 3 and connecting pad 6b is arranged closely to an end portion of first semiconductor chip 3. Connecting pad 6a and connecting pad 6b are electrically connected with external terminals 9. Semiconductor device 1 further includes: connecting pad 6c provided as contacting or as being close to an upper end portion of second semiconductor chip 10 while being electrically connected with the upper surface of second semiconductor chip 10, and wire 12 which electrically connects connecting pad 6b and connecting pad 6c. |
| US07969014B2 |
Power layout of integrated circuits and designing method thereof
The invention discloses a technique for designing the power layout of an integrated circuit. The power layout design forms a power mesh and a power ring with a plurality of metal trunks with uniform line width. In particular, the power ring includes a plurality of metal rings, which are formed by arranging denser layout of the metal trunks with uniform line width. The power ring serves as a function of receiving and providing a power source to the elements of the integrated circuit. |
| US07969013B2 |
Through silicon via with dummy structure and method for forming the same
A through silicon via structure includes a top pad and a vertical conductive post that is connected to the top pad. The top pad covers a wider area than the cross section of the vertical conductive post. An interconnect pad is formed at least partially below the top pad. An under layer is also formed at least partially below the top pad. At least one dummy structure connects the top pad and the under layer to fasten the top pad and the interconnect pad. |
| US07969008B2 |
Semiconductor device with improved pads
A semiconductor device has: a circuit portion having semiconductor elements formed on a semiconductor substrate; insulating lamination formed above the semiconductor substrate and covering the circuit portion; a multilevel wiring structure formed in the insulating lamination and including wiring patterns and via conductors; and a pad electrode structure formed above the semiconductor substrate and connected to the multilevel wiring structure. The pad electrode structure includes pad wiring patterns and pad via conductors interconnecting the pad wiring patterns, the uppermost pad wiring pattern includes a pad pattern and a sealing pattern surrounding the pad pattern in a loop shape. Another pad wiring pattern has continuous extended pad pattern of a size overlapping the sealing pattern. The pad via conductors include a plurality of columnar via conductors disposed in register with the pad pattern and a loop-shaped wall portion disposed in register with the sealing pattern. |
| US07969004B2 |
Semiconductor device, method for mounting semiconductor device, and mounting structure of semiconductor device
In order to realize a semiconductor device which is easily mounted on a circuit board and which has high mounting reliability, a semiconductor device 1 of the present invention includes: a semiconductor substrate 2; and an Au bump 3 provided on an electrode 21. The Au bump 3 is provided with a projection 3a. Also, on a surface of the Au bump 3, a solder layer 32 is formed via a Ni layer 31. The projection 3a makes it possible to easily mount the semiconductor device 1 by applying a small weight. Further, even if the amount of solder 62 supplied on an electrode 61 on a circuit board 6 is reduced, it is possible to bond the semiconductor device with a sufficient amount of solder during mounting. Furthermore, because a Ni layer 31 prevents dissolution of the bump, it is possible to ensure high mounting reliability. |
| US07969003B2 |
Bump structure having a reinforcement member
A manufacturing method of a bump structure having a reinforcement member is disclosed. First, a substrate including pads and a passivation layer is provided. The passivation layer has first openings, and each first opening exposes a portion of the corresponding pad respectively. Next, an under ball metal (UBM) material layer is formed on the substrate to cover the passivation layer and the pads exposed by the passivation layer. Bumps are formed on the UBM material layer and the lower surface of each bump is smaller than that of the opening. Each reinforcement member formed on the UBM material layer around each bump contacts with each bump, and the material of the reinforcement member is a polymer. The UBM material layer is patterned to form UBM layers and the lower surface of each UBM layer is larger than that of each corresponding opening. Hence, the bump has a planar upper surface. |
| US07968999B2 |
Process of grounding heat spreader/stiffener to a flip chip package using solder and film adhesive
A method of grounding a heat spreader/stiffener to a flip chip package comprising the steps of attaching an adhesive film to a substrate and attaching a stiffener to the adhesive film. The adhesive film may have a number of first holes corresponding with a number of grounding pads on the substrate. The grounding pads may be configured to provide electrical grounding. The stiffener may have a number of second holes corresponding with the number of first holes of the adhesive film and number the grounding pads of the substrate. The grounding pads are generally exposed through the first and the second holes. |
| US07968997B2 |
Semiconductor device
A semiconductor device includes a wring board having a first surface with external connection terminals and a second surface with internal connection terminals. On the second surface of the wiring board, a semiconductor chip having electrode pads is mounted. The electrode pads of the semiconductor chip and the internal connection terminals of the wiring board are electrically connected via connecting members. The external connection terminals are arranged along two opposite outer sides of the wiring board and each have a rectangular shape elongated in a direction toward the outer side. |
| US07968995B2 |
Integrated circuit packaging system with package-on-package and method of manufacture thereof
A method of manufacture an integrated circuit packaging system includes: providing a base substrate; mounting a first base integrated circuit over the base substrate; mounting a second base integrated circuit over the first base integrated circuit; attaching a stacking interconnect to the base substrate and adjacent to the first base integrated circuit; and forming a base encapsulation, having a recess portion from a corner of the base encapsulation and a step portion adjacent to the recess portion, with the step portion over the second base integrated circuit and the recess portion exposing the stacking interconnect. |
| US07968994B2 |
Memory modules and systems including the same
Provided is a memory module. The memory module may include a mounting substrate including a plurality of first substrate pads disposed on a top surface of the mounting substrate, a first semiconductor package disposed on a top surface of the mounting substrate, the first semiconductor package having a first frame and first external connection terminals which extend through the outside of the first frame and are disposed on the first substrate pads, a first connection member including first connection terminals disposed between the first external connection terminals and the first substrate pads and a pressure fixing member compressing the first connection member to electrically connect the first external connection terminals and the first substrate pads by the medium of the first connection terminals. |
| US07968987B2 |
Carbon dioxide gettering for a chip module assembly
A chip module assembly includes a CO2 getter exposed through a gas-permeable membrane to a chip cavity of a chip module. One or more chips is/are enclosed within the cavity. The CO2 getter comprises a liquid composition including 1,8-diaza-bicyclo-[5,4,0]-undec-7-ene (DBU) in a solvent that includes an alcohol, preferably, 1-hexanol. In one embodiment, a sheet of gas-permeable membrane is heat-welded to form a pillow-shaped bag in which the liquid composition is sealed. The pillow-shaped bag containing the liquid composition is preferably disposed in a recess of a heat sink and exposed to the cavity through a passage between the recess and the cavity. The CO2 getter can remove a relatively large amount of carbon dioxide from the cavity, and thus effectively prevents solder joint corrosion. For example, based on the formula weights and densities of the DBU and 1-hexanol, 200 g of the liquid composition can remove over 34 g of carbon dioxide. |
| US07968986B2 |
Lid structure for microdevice and method of manufacture
A system and a method are described for forming features at the bottom of a cavity in a substrate. Embodiments of the systems and methods provide an infrared transmitting, hermetic lid for a microdevice. The lid may be manufactured by first forming small, subwavelength features on a surface of an infrared transmitting substrate, and coating the subwavelength features with an etch stop material. A spacer wafer is then bonded to the infrared transmitting substrate, and a device cavity is etched into the spacer wafer down to the etch stop material, exposing the subwavelength features. The etch stop material may then be removed, and the microdevice enclosed in the device cavity, by bonding the device wafer to the lid. |
| US07968982B2 |
Thermal enhanced upper and dual heat sink exposed molded leadless package
A semiconductor package includes a semiconductor device 30 and a molded upper heat sink 10. The heat sink has an interior surface 16 that faces the semiconductor device and an exterior surface 15 that is at least partially exposed to the ambient environment of the packaged device. An annular planar base 11 surrounds a raised or protruding central region 12. That region is supported above the plane of the base 11 by four sloped walls 13.1-13.4. The walls slope at an acute angle with respect to the planar annular base and incline toward the center of the upper heat sink 10. Around the outer perimeter of the annular base 11 are four support arms 18.1-18.4. The support arms are disposed at an obtuse angle with respect to the interior surface 16 of the planar annular base 11. |
| US07968980B2 |
Support member for mounting a semiconductor device, conductive materials, and its manufacturing method
A semiconductor device comprises a support member having a pair of first conductive materials and a pair of second conductive materials on an insulating substrate, and a sealing member covering a semiconductor element arranged on the support member, wherein the support member has an insulating portion where the insulating substrate is exposed between the pair of the first conductive materials, and at least one of the pair of the second conductive materials is arranged along the side of the insulating portion, and the sealing member is disposed so that the sealing member is over at least a part of at least one of the first conductive materials and the second conductive materials. |
| US07968979B2 |
Integrated circuit package system with conformal shielding and method of manufacture thereof
An integrated circuit package system includes: providing a substrate with an integrated circuit mounted thereover; mounting a structure, having ground pads, over the integrated circuit; encapsulating the integrated circuit with an encapsulation while leaving the structure partially exposed; and attaching a conformal shielding to the encapsulation and electrically connected to the grounding pads. |
| US07968977B2 |
Dicing film having shrinkage release film and method of manufacturing semiconductor package using the same
The present invention relates to a dicing film having an adhesive film for dicing a wafer and a die adhesive film, which are used for manufacturing a semiconductor package, and a method of manufacturing a semiconductor package using the same. More particularly, the present invention relates to a dicing film wherein a shrinkage release film is inserted between an adhesive film for dicing a wafer and a die adhesive film so that the die adhesive film and a die can be easily separated from the adhesive film for dicing a wafer when picking up a semiconductor die, and a method of manufacturing a semiconductor package using the same. |
| US07968972B2 |
High-frequency bipolar transistor and method for the production thereof
A high-frequency bipolar transistor includes an emitter contact adjoining an emitter connection region, a base contact adjoining a base connection region, and a collector contact adjoining a collector connection region. A first insulation layer is disposed on the base connection region. The collector connection region contains a buried layer, which connects the collector contact to a collector zone. A silicide or salicide region is provided on the buried layer and connects the collector contact to the collector zone in a low-impedance manner. A second insulation layer is disposed on the collector connection region but not on the silicide region. |
| US07968971B2 |
Thin-body bipolar device
A thin-body bipolar device includes: a semiconductor substrate, a semiconductor fin constructed over the semiconductor substrate, a first region of the semiconductor fin having a first conductivity type, the first region serving as a base of the thin-body bipolar device, and a second and third region of the semiconductor fin having a second conductivity type opposite to the first conductivity type, the second and third region being both juxtaposed with and separated by the first region, the second and third region serving as an emitter and collector of the thin-body bipolar device, respectively. |
| US07968969B2 |
Electrical components for microelectronic devices
Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing an underlying layer onto a workpiece, and forming a conductive layer on the underlying layer. The method can continue by disposing a dielectric layer on the conductive layer. The underlying layer is a material that causes the dielectric layer to have a higher dielectric constant than without the underlying layer being present under the conductive layer. For example, the underlying layer can impart a structure or another property to the film stack that causes an otherwise amorphous dielectric layer to crystallize without having to undergo a separate high temperature annealing process after disposing the dielectric layer onto the conductive layer. Several examples of this method are expected to be very useful for forming dielectric layers with high dielectric constants because they avoid using a separate high temperature annealing process. |
| US07968965B2 |
Semiconductor device and method for fabricating the same
Embodiments relate to a semiconductor device and a method for fabricating the same. According to embodiments, a semiconductor device may include a first device, a silicon epitaxial layer formed on and/or over the first device, a second device formed on and/or over the silicon epitaxial layer, and a connection via formed through the silicon epitaxial layer, which may electrically interconnect the first device and the second device. According to embodiments, a method for fabricating a semiconductor device may include forming a first device, forming a silicon epitaxial layer on and/or over the first device, forming a connection via through the silicon epitaxial layer, and forming a second device on and/or over the silicon epitaxial layer such that the second device may be electrically connected to the connection via. |
| US07968957B2 |
Transistor gate electrode having conductor material layer
Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material. |
| US07968955B2 |
Gate in semiconductor device and method of fabricating the same
A gate of a semiconductor device includes a substrate, and a polysilicon layer over the substrate, wherein the polysilicon layer is doped with first conductive type impurities having a concentration that decreases when receding from the substrate and counter-doped with second conductive type impurities having a concentration that increases when receding from the substrate. |
| US07968953B2 |
Semiconductor device including schottky barrier diode and method of manufacturing the same
A semiconductor device includes a substrate, a plurality of first columns having a first conductivity type, a plurality of second columns having a second conductivity type, a first electrode, and a second electrode. The first columns and the second columns are alternately arranged on the substrate to provide a super junction structure. The first electrode is disposed on the super junction structure, forms schottky junctions with the first columns, and forms ohmic junctions with the second columns. The second electrode is disposed on the substrate on an opposite side of the super junction structure. At least a part of the substrate and the super junction structure has lattice defects to provide a lifetime control region at which a lifetime of a minority carrier is controlled to be short. |
| US07968951B2 |
Interconnecting bit lines in memory devices for multiplexing
An embodiment of a memory device has a plurality of conductive plugs formed on a semiconductor substrate and a pair of successively adjacent first and second bit lines overlying and in contact with each of the conductive plugs. |
| US07968950B2 |
Semiconductor device having improved gate electrode placement and decreased area design
A semiconductor device includes a gate electrode having ends that overlap isolation regions, wherein the gate electrode is located over an active region located within a semiconductor substrate. A gate oxide is located between the gate electrode and the active regions, and source/drains are located adjacent the gate electrode and within the active region. An etch stop layer is located over the gate electrode and the gate electrode has at least one electrical contact that extends through the etch stop layer and contacts a portion of the gate electrode that in one embodiment overlies the active region, and in another embodiment is less than one alignment tolerance from the active region. |
| US07968948B2 |
Trench isolation structure in a semiconductor device and method for fabricating the same
A trench isolation structure in a semiconductor device is provided. A semiconductor substrate has cell regions and peripheral circuit regions. First trenches have a predetermined depth and are formed in the semiconductor substrate at the cell regions. A first sidewall oxide film is formed overlying the first trenches. A first liner nitride film is formed overlying the first sidewall oxide film. Second trenches have a predetermined depth and are formed in the semiconductor substrate at the peripheral circuit regions. A second sidewall oxide film is formed overlying the second trenches. An oxide film fills the first overlying second trenches. A second liner nitride film formed on the filling oxide film. The second liner nitride film is separated from the sidewalls of the first and second trenches. |
| US07968947B2 |
Semiconductor device and manufacturing process therefor
This invention provides a semiconductor device that can prevent a deviation of work function by adopting a gate electrode having a uniform composition and exhibits excellent operating characteristics by virtue of effective control of a Vth. The semiconductor device is characterized by comprising a PMOS transistor, an NMOS transistor, a gate insulating film comprising an Hf-containing insulating film with high permittivity, a line electrode comprising a silicide region (A) and a silicide region (B), one of the silicide regions (A) and (B) comprising a silicide (a) of a metal M, which serves as a diffusing species in a silicidation reaction, the other silicide region comprising a silicide layer (C) in contact with a gate insulating film, the silicide layer (C) comprising a silicide (b) of a metal M, which has a smaller atom composition ratio of the metal M than the silicide (a), and a dopant which can substantially prevent diffusion of the metal M in the silicide (b). |
| US07968944B2 |
Integrated circuit chip with FETs having mixed body thicknesses and method of manufacture thereof
An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI FETs may include Partially Depleted SOI (PD-SOI) FETs and Fully Depleted SOI (FD-SOI) FETs and the chip may include bulk FETs as well. The FETs are formed by contouring the surface of a wafer, conformally implanting oxygen to a uniform depth, and planarizing to remove the Buried OXide (BOX) in bulk FET regions. |
| US07968939B2 |
Semiconductor device and method of manufacturing the same
A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique. |
| US07968934B2 |
Memory device including a gate control layer
An integrated memory device, an integrated memory chip and a method for fabricating an integrated memory device is disclosed. One embodiment provides at least one integrated memory device with a drain, a source, a floating gate, a selection gate and a control gate, wherein the conductivity between the drain and the source can be controlled independently via the control gate. |
| US07968932B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device which is formed in a self-aligned manner without causing a problem of misalignment in forming a control gate electrode and in which a leak between the control gate electrode and a floating gate electrode is not generated, and a manufacturing method of the semiconductor device are provided. A semiconductor device includes a semiconductor film, a first gate insulating film over the semiconductor film, a floating gate electrode over the first gate insulating-film, a second gate insulating film which covers the floating gate electrode, and a control gate electrode over the second gate insulating film. The control gate electrode is formed so as to cover the floating gate electrode with the second gate insulating film interposed therebetween, the control gate electrode is provided with a sidewall, and the sidewall is formed on a stepped portion of the control gate-electrode, generated due to the floating gate electrode. |
| US07968931B2 |
Non-volatile semiconductor memory devices
A non-volatile memory device includes a tunneling insulating layer on a semiconductor substrate, a charge storage layer, a blocking insulating layer, and a gate electrode. The charge storage layer is on the tunnel insulating layer and has a smaller band gap than the tunnel insulating layer and has a greater band gap than the semiconductor substrate. The blocking insulating layer is on the charge storage layer and has a greater band gap than the charge storage layer and has a smaller band gap than the tunnel insulating layer. The gate electrode is on the blocking insulating layer. |
| US07968930B2 |
Finned memory cells
For an embodiment, a memory array has a plurality fins protruding from a substrate. A tunnel dielectric layer overlies the fins. A plurality floating gates overlie the tunnel dielectric layer, and the floating gates correspond one-to-one with the fins protruding from the substrate. An intergate dielectric layer overlies the floating gates. A control gate layer overlies the intergate dielectric layer. Each fin includes an upper surface rounded by isotropic etching. |
| US07968927B2 |
Memory array for increased bit density and method of forming the same
A memory array having a plurality of resistance variable memory units and method for forming the same are provided. Each memory unit includes a first electrode, a resistance variable material over the first electrode, and a first second-electrode over the resistance variable material. The first second-electrode is associated with the first electrode to define a first memory element. Each memory unit further includes a second second-electrode over the resistance variable material. The second-second electrode is associated with the first electrode to define a second memory element. |
| US07968925B2 |
Power semiconductor module for inverter circuit system
A double-face-cooled semiconductor module with an upper arm and a lower arm of an inverter circuit includes first and second heat dissipation members, each having a heat dissipation surface on one side and a conducting member formed on another side through an insulation member. On the conducting member on the first dissipation plate is provided with a fixing portion that fixes a collector surface of the semiconductor chip and a gate conductor connected to a gate terminal of the semiconductor module. The gate electrode terminal and the gate conductor are wire bonded. The conducting member on the second heat dissipation member is connected to an emitter surface of the semiconductor chip connected to the first heat dissipation member. The productivity and reliability are improved by most of formation operations for the upper and lower arms series circuit on one of the heat dissipation member. |
| US07968921B2 |
Asymmetric field-effect transistor having asymmetric channel zone and differently configured source/drain extensions
An asymmetric insulated-gate field-effect transistor (100) has a source (240) and a drain (242) laterally separated by a channel zone (244) of body material (180) of a semiconductor body. A gate electrode (262) overlies a gate dielectric layer (260) above the channel zone. A more heavily doped pocket portion (250) of the body material extends largely along only the source. Each of the source and drain has a main portion (240M or 242M) and a more lightly doped lateral extension (240E or 242E). The drain extension is more lightly doped than the source extension. The maximum concentration of the semiconductor dopant defining the two extensions occurs deeper in the drain extension than in the source extension. Additionally or alternatively, the drain extension extends further laterally below the gate electrode than the source extension. These features enable the threshold voltage to be highly stable with operational time. |
| US07968920B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device and manufacturing method thereof capable of improving an operating speed of a MOSFET using an inexpensive structure. The method comprises the steps of forming a stress film to cover a source, drain, sidewall insulating layer and gate of the MOSFET and forming in the stress film a slit extending from the stress film surface toward the sidewall insulating layer. As a result, an effect of allowing local stress components in the stress films on the source and the drain to be relaxed by local stress components in the stress film on the gate is suppressed by the slit. |
| US07968915B2 |
Dual stress memorization technique for CMOS application
A stress-transmitting dielectric layer is formed on the at least one PFET and the at least one NFET. A tensile stress generating film, such as a silicon nitride, is formed on the at least one NFET by blanket deposition and patterning. A compressive stress generating film, which may be a refractive metal nitride film, is formed on the at least one PFET by a blanket deposition and patterning. An encapsulating dielectric film is deposited over the compress stress generating film. The stress is transferred from both the tensile stress generating film and the compressive stress generating film into the underlying semiconductor structures. The magnitude of the transferred compressive stress from the refractory metal nitride film may be from about 5 GPa to about 20 GPa. The stress is memorized during an anneal and remains in the semiconductor devices after the stress generating films are removed. |
| US07968911B2 |
Relaxation of a strained layer using a molten layer
A crystalline wafer comprising of a support substrate, a first layer and an interface layer. The first layer is of a first material in a relaxed state having a lattice parameter that is substantially equal to the nominal lattice parameter of the first material. The interface layer is in an at least partially molten state disposed between the support substrate and the first layer. The first material is preferably silicon germanium, and the interface layer includes germanium in a higher concentration than that of first material. |
| US07968907B2 |
Low capacitance over-voltage protection thyristor device
An over-voltage protection thyristor has reduced junction capacitance making it suitable for use in high bandwidth applications. The reduced capacitance is achieved through the introduction of a deep base region. The deep base region has a graded doping concentration which reduces with depth into the substrate. The thyristor is useful for protecting sensitive electrical equipment from transient surges. |
| US07968906B2 |
Substrate-triggered bipolar junction transistor and ESD protection circuit
An ESD protection circuit using a novel substrate-triggered lateral bipolar junction transistor (STLBJT) for providing a discharging path between power rails. The ESD protection circuit comprises an ESD detection circuit and a STLBJT device. The STLBJT device formed in a P-type substrate includes N-type collector and emitter regions coupled to the power rails, respectively. The substrate region between the collector and emitter regions, on which there is no field oxide device, serves as a base of the STLBJT device. The STLBJT device further includes a first P-type region coupled to the ESD detection circuit and a second P-type region coupled to one of the power rails, which are spatially separated from the collector/emitter regions, respectively. The STLBJT device is turned on by substrate-triggering responsive to the signal coming from the ESD detection circuit and establishes the discharging path between the power rails. |
| US07968903B2 |
Light emitting device
A light emitting device has a semiconductor multilayer structure having a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type different from the first conductivity type, and an active layer sandwiched between the first semiconductor layer and the second semiconductor layer, a narrow electrode having a current feeding part provided on a region of a part above of the first semiconductor layer for supplying an electric current from outside to the semiconductor multilayer structure, and a narrow electrode provided adjacent to the current feeding part for reflecting a light emitted from the active layer, and a surface center electrode part electrically connected to the narrow electrode, and provided above the first semiconductor layer via a transmitting layer for transmitting the light. |
| US07968901B2 |
Light emitting unit
A light emitting unit includes at least one electrode member having high thermal conductivity and low resistance, and one or more flip-chip-type light emitting device of which an anode electrode side or a cathode electrode side is connected to the electrode member, and wherein the electrode member extends in a longitudinal direction thereof, and heat generated in the light emitting device is to be released along the longitudinal direction of the electrode member. |
| US07968896B2 |
Separate optical device for directing light from an LED
Embodiments of the present invention provide separate optical devices operable to couple to a separate LED, the separate optical device comprising an entrance surface to receive light from a separate LED when the separate optical device is coupled to the separate LED, an exit surface opposite from and a distance from the entrance surface and a set of sidewalls. The exit surface can have at least a minimum area necessary to conserve brightness for a desired half-angle of light projected from the separate optical device. Furthermore, each sidewall is positioned and shaped so that rays having a straight transmission path from the entrance surface to that sidewall reflect to the exit surface with an angle of incidence at the exit surface at less than or equal to a critical angle at the exit surface. |
| US07968895B2 |
Conductor structure, pixel structure, and methods of forming the same
A method for forming a conductor structure is provided. The method comprises: (1) providing a substrate; (2) forming a patterned dielectric layer with a first opening which exposes a portion of the substrate; forming a patterned organic material layer on the dielectric layer with a second opening which corresponds to the first opening and expose the exposed portion of the substrate; (3) forming a first barrier layer on the organic material layer and the exposed portion of the substrate; (4) forming a metal layer on the first barrier layer; and (5) removing the organic material layer, the first barrier layer thereon and the metal layer thereon. |
| US07968887B2 |
Active matrix circuit substrate, method of manufacturing the same, and active matrix display including the active matrix circuit substrate
An active matrix circuit substrate including data lines, select lines, and pixel circuits electrically coupled with a data line and two adjacent select lines. The pixel circuits include a thin film transistor having a gate electrode coupled with one of the two adjacent select lines and a storage capacitor having a second electrode coupled with the other select line adjacent to the select line to which the gate electrode is coupled. The gate electrode of a first pixel circuit and the second electrode of the storage capacitor of the adjacent pixel circuit are the same structure having a line shape. |
| US07968885B2 |
Display device and manufacturing method thereof
To provide a display device having a thin film transistor with high electric characteristics and excellent reliability and a manufacturing method thereof. A gate electrode, a gate insulating film provided over the gate electrode, a first semiconductor layer provided over the gate insulating film and having a microcrystalline semiconductor, a second semiconductor layer provided over the first semiconductor layer and having an amorphous semiconductor, and a source region and a drain region provided over the second semiconductor layer are provided. The first semiconductor layer has high crystallinity than the second semiconductor layer. The second semiconductor layer includes an impurity region having a conductivity type different from a conductivity type of the source region and the drain region between the source region and the drain region. |
| US07968883B2 |
Image detector
An image detector which includes an active matrix substrate and a protection substrate bonded to the active matrix substrate by an insulating bonding member, in which the insulating bonding member is bonded to the active matrix substrate through an inorganic insulating film disposed in an area around the periphery of the semiconductor layer. |
| US07968881B2 |
Thin film transistor substrate and display device having electrode plates on storage capacitors
The invention relates to a thin film transistor substrate and a display device including the same, and provides a thin film transistor substrate and a display device including the same, which can prevent damage of elements due to static electricity by forming, in each unit pixel region where a pair of first and second pixel electrodes, a pair of first and second drain electrode plates that are connected to the first and second pixel electrodes and to connected to drain terminals of thin film transistors, and can obtain a dot inversion driving effect through line inversion driving by connecting the first drain electrode in one pixel region to the first drain electrode plate, connecting the second drain electrode in the one unit pixel region to the second drain electrode plate, connecting a first drain electrode in another unit pixel region neighboring the one unit pixel region to the second drain electrode plate, and connecting a second drain electrode in another unit pixel region to the first drain electrode plate. |
| US07968880B2 |
Thin film transistor and display device
To improve problems with on-state current and off-state current of thin film transistors, a thin film transistor includes a pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added, provided with a space therebetween; a conductive layer which is overlapped, over the gate insulating layer, with the gate electrode and one of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added; and an amorphous semiconductor layer which is provided successively between the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added in such a manner that the amorphous semiconductor layer extends over the gate insulating layer from the conductive layer and is in contact with both of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added. |
| US07968878B2 |
Electrical test structure to detect stress induced defects using diodes
A serpentine double gated diode array for monitoring stress induced defects is disclosed. The diode array is configured with adjacent gate segments and gate loops in close proximity to active areas to maximize a sensitivity to stress induced defects. The diode array is compatible with conventional electrical testing. Scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy (SSRM) may be used to isolate individual stress induced defects. Variations in the gate configuration allow estimation of effects of circuit layout on formation of stress induced defects. |
| US07968876B2 |
Phase change memory cell having vertical channel access transistor
Memory devices are described along with methods for manufacturing. A device as described herein includes a substrate having a first region and a second region. The first region comprises a first field effect transistor comprising first and second doped regions separated by a horizontal channel region within the substrate, a gate overlying the horizontal channel region, and a first dielectric covering the gate of the first field effect transistor. The second region of the substrate includes a second field effect transistor comprising a first terminal extending through the first dielectric to contact the substrate, a second terminal overlying the first terminal and having a top surface, and a vertical channel region separating the first and second terminals. The second field effect transistor also includes a gate on the first dielectric and adjacent the vertical channel region, the gate having a top surface that is co-planar with the top surface of the second terminal. A second dielectric separates the gate of the second field effect transistor from the vertical channel region. |
| US07968875B2 |
Organic photosensitive optoelectronic device
An organic photosensitive optoelectronic device includes an anode, an organic photosensitive layer formed on the anode and having a donor portion and an acceptor portion, a hole blocking layer formed on the organic photosensitive layer so as for the organic photosensitive layer to be sandwiched between the anode and the hole blocking layer, and a cathode formed on the hole blocking layer so as for the hole blocking layer to be sandwiched between the cathode and the organic photosensitive layer. The highest occupied molecular orbitals (HOMO) of the hole blocking layer is at least 0.3 eV higher than that of the donor portion. Therefore, the optoelectronic device efficiently suppresses dark current so as to enhance sensitivity when applied to a detector. |
| US07968874B2 |
Organic electroluminescent device material and organic electroluminescent device
Disclosed is an organic electroluminescent device (organic EL device) that utilizes phosphorescence and is improved in luminous efficiency and fully secured of driving stability. The organic EL device comprises an anode, an organic layer containing a hole-transporting layer, a light-emitting layer, and an electron-transporting layer, and a cathode piled one upon another on a substrate while the hole-transporting layer is disposed between the light-emitting layer and the anode and the electron-transporting layer is disposed between the light-emitting layer and the cathode. The light-emitting layer comprises an aluminum heterocomplex or dimeric complex of deuterated substituted or unsubstituted 2-methyl-8-hydroxyquinoline (Me8HQ-D) in which the hydrogen atoms in the methyl group of substituted or unsubstituted 2-methyl-8-hydroxyquinoline (Me8HQ) are deuterated as a host material and an organic metal complex containing at least one metal selected from groups 7 to 11 of the periodic table as a guest material. |
| US07968871B2 |
Organic thin film transistor
Organic thin film transistors with improved mobility are disclosed. The semiconducting layer comprises a semiconductor material of Formula (I): wherein R1 and R2 are independently selected from alkyl, substituted alkyl, aryl, and substituted aryl; and R3 and R4 are independently selected from hydrogen, alkyl, substituted alkyl, aryl, and substituted aryl. A silanized interfacial layer is also present which has alkyl sidechains extending from its surface towards the semiconducting layer. |
| US07968868B2 |
Optical semiconductor device and manufacturing method of the same
A side barrier is provided between columnar dots each constituted by directly stacking respective quantum dots in seven or more layers. Out of respective side barrier layers composing the side barrier, each of the lower side barrier layers (four layers of the undermost layer to the fourth layer from the bottom) is formed as a first side barrier layer into which a tensile strain is introduced, and each of the upper side barrier layers (three layers of the fifth layer to the uppermost layer from the bottom) is formed as a second side barrier layer which has no strain. |
| US07968866B2 |
Light emitting device and display
A light emitting diode comprising a lead, an LED chip mounted on said lead, said LED chip having a substrate and semiconductor layers formed on said substrate, a transparent material covering said LED chip, and a phosphor contained in said transparent material and absorbing a part of light emitted by said LED chip and emitting light of wavelength different from that of the absorbed light, wherein the main emission peak of said LED chip is within the range from 400 nm to 530 nm, and said LED chip is mounted on said lead with substrate-side up and is electrically connected with said lead by a metallic bump. |
| US07968864B2 |
Group-III nitride light-emitting device
A group-III nitride light-emitting device is provided. An active layer having a quantum well structure is grown on a basal plane of a gallium nitride based semiconductor region. The quantum well structure is formed in such a way as to have an emission peak wavelength of 410 nm or more. The thickness of a well layer is 4 nm or more, and 10 nm or less. The well layer is composed of InXGa1-XN (0.15≦X<1, where X is a strained composition). The basal plane of the gallium nitride based semiconductor region is inclined at an inclination angle within the range of 15 degrees or more, and 85 degrees or less with reference to a {0001} plane or a {000-1} plane of a hexagonal system group III nitride. The basal plane in this range is a semipolar plane. |
| US07968863B2 |
Optical device having a quantum-dot structure
Method of manufacturing an optical device, and an optical device, the optical device having one or more layers (13) of quantum-dots located in-between barrier layers (12). A spacer layer (15) is grown on a barrier layer (12), such that the spacer layer (15) is adapted for substantially blocking strain fields induced by quantum-dot layers, thereby producing a smooth growth front for a subsequent barrier layer (12). |
| US07968847B2 |
Identification mechanism for a component attached to a medical device
The invention relates to the identification of a component of a medical device. The medical device is realized for the alternative attachment of a plurality of components. By means of infrared reflection sensors an emitted signal that is reflected by an attached component is detected. The reflected signal has a shape that is characteristic of the component. The component is identified through determination by the infrared reflection sensors that detect a reflected signal. The invention allows for alternative components that can be attached to be identified efficiently and with little outlay. |
| US07968846B2 |
Tunable finesse infrared cavity thermal detectors
A cavity thermal detector assembly is presented that allows both tunable narrowband and broadband operation. This allows for high light efficiency, low thermal time constant, and flexibility in designing the optical path. The thermal detector/filter layers are part of the top mirror or mirrors of a Gires-Tournois-type optical cavity and provide absorption and reflection that can be adjusted to the desired width and position of the detected band. Tuning, if desired, can be achieved by applying micromechanical methods. Broadband operation may be achieved by bringing the sensor close to the bottom mirror. In this mode, the sensor or its supports may or may not touch over a small area. |
| US07968845B1 |
System for producing enhanced thermal images
An imaging device has a thermal sensor to remotely measure respective temperatures of regions within an imaging field and to generate temperature information signals. A motion tracking system tracks motion of the thermal sensor and generates position information signals representing positions of the thermal sensor during the temperature measurements. An image construction processor uses the position and temperature information signals to generate a two-dimensional image representative of the imaging field including respective temperature indications at different locations within the two-dimensional image, and stores the two-dimensional image within a memory. The two-dimensional image may be used as an output image for display to a user. |
| US07968843B2 |
Method and apparatus for simultaneous SEM and optical examination
Method and apparatus capable of observing a liquid sample. An optical image of the sample and an image using a primary beam, such as an electron beam or charged-particle beam, can be obtained at the same time. The apparatus has a film including a first surface on which the liquid sample is held. The primary beam irradiation column and optical image acquisition viewer are located on opposite sides of the film that acts to block light. |
| US07968842B2 |
Apparatus and systems for processing samples for analysis via ion mobility spectrometry
The invention provides an interface assembly for delivering an ionized analyte from an ionization apparatus into an ion mobility spectrometer. This allows analysis of biological and non-biological samples, even non-volatile solids, via differential mobility spectrometry, without fragmentation of molecules. The invention also provides portable sample analysis systems that operate at ambient pressure. Systems of the invention may be used for high molecular weight species detection, for example, drinking water contaminants, pathogenic biological agents, bio-organic substances, non-biological material, peptides, proteins, oligonucleotides, polymers, bacteria, and hydrocarbons. |
| US07968840B2 |
Optical phase reference
A validation apparatus for testing the measurement accuracy of a phase fluorimeter comprising: i) a photodetector responsive to the excitation light emitted by a phase fluorimeter; ii) electronics connected to the detector which calculates the phase of the light emitted by the phase fluorimeter and causes a light source in the validation apparatus to emit light of a wave length which will stimulate the detector of the phase fluorimeter but which is phase shifted relative to the light emitted by the phase fluorimeter. |
| US07968839B2 |
Miniaturized optical tweezers based on high-NA micro-mirrors
The invention relates to an optical tweezer device including at least one light source and one three-dimensional optical trap, said optical trap comprising one focusing micro-mirror which is adapted to reflect and focus at least a portion of the light emitted by said light source. |
| US07968838B2 |
Apparatus and process for generating a neutron beam
A process is disclosed for generating particles with a high degree of anisotropy in the direction of emission. |
| US07968834B2 |
Response-enhanced monolithic-hybrid pixel
A light-sensing pixel is described that includes more than one detector element, each of which is sensitive to a range of wavelengths of the electromagnetic spectrums. The detectors are arranged in a readout circuit that can be constructed on a monolithic semiconductor product such that one or more of the detectors can be switched on or off to include or exclude an output contribution from said detectors and enhance the response of the pixel. Also, the detectors can included a laser-treated semiconductor sensor for efficient sensing of radiation in one or more regions of the spectrum. Arrays and imaging products using such pixels are disclosed. |
| US07968831B2 |
Systems and methods for optimizing the aimpoint for a missile
Methods and systems are disclosed that automatically display an optimized aimpoint on a target image in received seeker data. In one embodiment, a method receives missile seeker target data. A seeker mode data is extracted from the received missile seeker target data. The location of a most vulnerable spot on a target is identified based on a comparison of target library data with seeker image data. A marker is generated at the location of the optimized aimpoint and output to a display. |
| US07968815B2 |
Resistance spot welder and a bearing/spindle arrangement for the resistance spot welder
A resistance spot welder including a first plate, a second plate rotatably connected to the first plate through a shaft and driven on the shaft by an actuator, gun arms removably fixed on and electrically insulated with the first and second plates, and electrode tips confronting each other and fixed on the gun arms. |
| US07968813B2 |
Switching device contact arm and armature plate
A control module for selectively switching electrical power from an electrical power source to a load circuit comprises a housing. An electromechanical actuator in the housing has a movable plunger. A fixed contact is fixedly mounted in the housing and is electrically connected to a first electrical terminal. A conductive contact arm in the housing comprises an elongate bar having a turn defining opposite first and second legs. The contact arm is pivotally mounted in the housing proximate the turn and is operatively connected to the plunger to be selectively positioned thereby. The contact arm further comprises a conductor tab proximate the turn. The first leg includes a movable contact for selectively electrically contacting the fixed contact. The second leg includes a user interface operator. |
| US07968811B2 |
Integrated ignition and key switch
An ignition and key switch assembly for a motorcycle includes a cover having a front surface, a rear surface, a first cover portion and a second cover portion, an ignition coil located in the first cover portion, the ignition coil being held in the first cover portion by a protective layer, and a key switch received within the second cover portion and being accessible at the cover front surface. A mounting bracket is provided for mounting the cover to the key switch and an aligning feature is provided for aligning the cover to the key switch. |
| US07968808B2 |
Compound operation input device
A compound operation input device of the invention includes: a body; a switch being disposed in the body and including a contact in an arcuate cross-sectional shape; and a lever. The lever includes: a basal portion disposed on a vertex of the contact; and an operating portion being swingable in swing directions and being depressible toward the switch from a predetermined position on a swing path. The body includes an arcuate abutting portion. The lever has a protrusion being disposed above the abutting portion. The abutting portion has a recess at a position thereof corresponding to the predetermined position. When the lever makes a depressing movement from a position other than the predetermined position, the protrusion abuts against the abutting portion. When the lever makes a depressing movement from the predetermined position, the protrusion is received in the recess such that the basal portion presses the vertex of the contact. |
| US07968807B2 |
Package having a plurality of mounting orientations
A package apparatus has a base coupled with a lid to form a leadframe package. The package has first and second exterior surfaces with respective first and second contact patterns. The first and second contact patterns are substantially electrically identical to permit the package to be either vertically or horizontally mounted to an underlying apparatus. |
| US07968804B2 |
Methods of patterning a deposit metal on a substrate
An article includes a polymeric film having a major surface, a discontinuous layer of a catalytic material on the major surface, and a metal pattern on the catalytic material. The discontinuous layer of catalytic material has an average thickness of less than 200 angstroms. Methods of forming these articles are also disclosed. |
| US07968799B2 |
Interposer, electrical package, and contact structure and fabricating method thereof
A contact structure on a substrate which has at least one contact is provided. The contact structure includes a compliant layer, at least one solder pad, at least one conductive via, and at least one conductive arm. The compliant layer is disposed on the substrate and covers the contact. The solder pad is disposed on the surface of the compliant layer which is at the opposite side of the substrate. The conductive via is disposed in the compliant layer and is connected to the contact. The conductive arm is disposed on the surface of the compliant layer in opposite to the substrate, and two ends of the conductive arm are respectively connected to the conductive via and the solder pad. Furthermore, a method for fabricating the contact structure, an interposer and an electrical package using the contact structure are provided. |
| US07968797B2 |
Modular electric fence system and assembly
A modular insulator system and assembly for attaching a conductor to a support member. The modular insulator assembly includes an insulator body attachable to a support member. A conductor retainer is attachable to the insulator body in a manner that forms a conductor passage between the conductor retainer and the insulator body. The modular insulator system includes an insulator body selected from a top-mount insulator body, a support passage insulator body, an insulator body including an extended neck, a surface mount insulator body and a combination surface/T-post mount insulator body the insulator body attachable to the support member and a conductor retainer selected from a group of conductor retainers including a bare conductive wire retainer, a narrow gage conductive tape retainer and a wide gage conductive tape retainer, the selected insulator body attachable to a support member and the selected conductor retainer attachable to the selected insulator body. |
| US07968793B2 |
Solar cell
A solar cell includes a back metal-contact layer, a P-type semiconductor layer, a P-N junction layer, an N-type semiconductor layer and a transparent electrically conductive layer. The P-type semiconductor layer is formed on the back metal-contact layer. The P-type semiconductor layer is comprised of nano particles of a P-type semi-conductive compound. The P-N junction layer is formed on the P-type semiconductor layer. The N-type semiconductor layer is formed on the P-N junction layer. The N-type semiconductor layer is comprised of nano particles of an N-type semi-conductive compound. The transparent electrically conductive layer is formed on the N-type semiconductor layer and functions as a front contact layer. |
| US07968788B2 |
Electronic keyboard instrument
An electronic keyboard instrument in which the efficiency of sound emission is enhanced by preventing a soundboard portion having a large vibration amplitude from being hidden by a musical score plate to make sound emission of the soundboard to be hardly hindered by the musical score plate. A musical stand device is disposed rearward of a key-depression part of a keyboard and right above the soundboard, and has a musical score plate disposed close to and parallel to an upper surface of the soundboard when the musical score plate is in a fallen state. The soundboard is excited for sound production by transducers disposed on a lower surface of the soundboard. The transducers are disposed at positions where the transducers do not overlap, as viewed in plan, the musical score plate which is in the fallen state. |
| US07968786B2 |
Volume adjusting apparatus and volume adjusting method
A volume adjusting apparatus includes a sound collecting unit configured to collect noise data of a surrounding environment, an analyzing unit configured to extract a feature value indicating a feature of the noise data collected by the sound collecting unit and a feature value indicating a feature of supplied musical tune data, and a control unit configured to generate volume adjustment information for adjusting playback volume of the musical tune data based on the feature value of the noise data and the feature value of the musical tune data and adjusts the playback volume of the musical tune data based on the volume adjustment information. |
| US07968784B2 |
Performance device systems and methods
A timer may be for timing a current time period corresponding to an amount of time since a previous operation of an operator. Circuitry may be for processing data to carry out a performance based on a set tempo. The circuitry may be configured to change a position of the performance to a specified position of the performance in a case where the operator is operated and the current time period equals or exceeds a specified time period. The circuitry may be configured to change the tempo based on the current time period in a case where the operator is operated and the current time period is less than the specified time period. |
| US07968779B2 |
Stringed instrument conditioning device
An device for accelerating the conditioning process of a stringed musical instrument by causing such instrument to be continuously strummed and vibrated, whereby such vibrations are transmitted to the wooden body of the instrument, which causes the instrument to be prematurely aged and over time improves the consistency, richness, and quality of the sound produced by the instrument when played. |
| US07968778B2 |
Tuner with capo
A combination of a capo with attached tuner having a sensor that picks up vibrations through the capo. The capo and tuner are connected together as a unitary accessory that is attachable along the neck of the guitar, in the manner of a conventional capo, but with the significant advantage of automatic and continuous visibility of the tuner display while tuning at a particular capo position and while pausing between songs. |
| US07968777B1 |
Guide for stringed instrument and method
A guide for stringed instrument and method. The guide comprises a mast slidably and rotatably attached to a clamp, an arm slidably and rotatably attached to and end of the mast opposite the clamp, and an up-stop rigidly attached to an end of the arm opposite the mast. Padding may be attached to the clamp to cushion the attachment between the clamp and a stringed plucked instrument. Method steps included removably attaching the clamp to a stringed instrument, setting a height of the up-stop over the instrument strings to substantially equal the sum of a player's middle finger distal phalangeal joint length plus the player's middle finger middle phalangeal joint length, positioning the player's index and middle fingers substantially under the up-stop, and plucking the strings. The guide may also be used to properly position a bow in a rest position, resting against the up-stop, pending being used to play the instrument. |
| US07968776B1 |
Maize variety PHHEN
A novel maize variety designated PHHEN and seed, plants and plant parts thereof. Methods for producing a maize plant that comprise crossing maize variety PHHEN with another maize plant. Methods for producing a maize plant containing in its genetic material one or more traits introgressed into PHHEN through backcross conversion and/or transformation, and to the maize seed, plant and plant part produced thereby. Hybrid maize seed, plant or plant part produced by crossing the variety PHHEN or a trait conversion of PHHEN with another maize variety. Inbred maize varieties derived from maize variety PHHEN, methods for producing other inbred maize varieties derived from maize variety PHHEN and the inbred maize varieties and their parts derived by the use of those methods. |
| US07968772B2 |
Cotton cultivar DP 110 RF
A cotton cultivar, designated DP 110 RF, is disclosed. The invention relates to the seeds of cotton cultivar DP 110 RF, to the plants of cotton DP 110 RF and to methods for producing a cotton plant produced by crossing the cultivar DP 110 RF with itself or another cotton variety. The invention further relates to hybrid cotton seeds and plants produced by crossing the cultivar DP 110 RF with another cotton cultivar. |
| US07968770B2 |
Methods for improving yield using soybean event 3560.4.3.5
Compositions and methods related to transgenic glyphosate/ALS inhibitor-tolerant soybean plants are provided. Specifically, soybean plants having a 3560.4.3.5 event which imparts tolerance to glyphosate and at least one ALS-inhibiting herbicide are provided. The soybean plant harboring the 3560.4.3.5 event at the recited chromosomal location comprises genomic/transgene junctions having at least the polynucleotide sequence of SEQ ID NO:10 and/or 11. The characterization of the genomic insertion site of the 3560.4.3.5 event provides for an enhanced breeding efficiency and enables the use of molecular markers to track the transgene insert in the breeding populations and progeny thereof. Various methods and compositions for the identification, detection, and use of the soybean 3560.4.3.5 events are provided. Methods and compositions for increasing yield are also provided. |
| US07968766B2 |
Plant UDP-galatose epimerases
This invention relates to an isolated nucleic acid fragment encoding a UDP-galactose 4-epimerase. The invention also relates to the construction of a chimeric gene encoding all or a portion of the UDP-galactose 4-epimerase, in sense or antisense orientation, wherein expression of the chimeric gene results in production of altered levels of the UDP-galactose 4-epimerase in a transformed host cell. |
| US07968763B2 |
QTL controlling sclerotinia stem ROT resistance in soybean
Markers associated with Sclerotinia stem rot resistance are provided. Methods of identifying resistant, and susceptible plants, using the markers are provided. Methods for identifying and isolating QTL are a feature of the invention, as are QTL associated with Sclerotinia stem rot resistance. |
| US07968760B2 |
Treatment of particulate biodegradable organic waste by thermal hydrolysis using condensate recycle
A method of treating particulate biodegradable organic waste by thermal hydrolysis. The method includes subjecting a quantity of the particulate biodegradable waste to thermal hydrolysis at a temperature above about 130° C. and a pressure at or above the saturated water vapor pressure to produce a slurry. The slurry will include solubilized organic material and unhydrolyzed residual solids. The method further includes decreasing the pressure at which the slurry is maintained. Typically, the step of decreasing slurry pressure will occur in a flash tank, which allows the separation of an organic acid-rich steam from other hydrolysis products. The method further includes capturing the steam or other condensable gases released when pressure is decreased and condensing the steam or other condensable gases into a condensate. The captured condensate may then be added to a quantity of particulate biodegradable waste prior to thermal hydrolysis. Also disclosed is an apparatus for practicing the method described above. |
| US07968746B2 |
4-(p-quinonyl)-2-hydroxybutanamide derivatives for treatment of mitochondrial diseases
Methods of treating or suppressing mitochondrial diseases, such as Friedreich's ataxia (FRDA), Leber's Hereditary Optic Neuropathy (LHON), mitochondrial myopathy, encephalopathy, lactacidosis, and stroke (MELAS), Kearns-Sayre Syndrome (KSS), are disclosed, as well as compounds useful in the methods of the invention, such as 4-(p-quinolyl)-2-hydroxybutanamide derivatives. Methods and compounds useful in treating other disorders such as amyotrophic lateral sclerosis (ALS), Huntington's disease, Parkinson's disease, and pervasive developmental disorders such as autism are also disclosed. Energy biomarkers useful in assessing the metabolic state of a subject and the efficacy of treatment are also disclosed. Methods of modulating, normalizing, or enhancing energy biomarkers, as well as compounds useful for such methods, are also disclosed. |
| US07968739B2 |
Method for electrochemical production of a crystalline porous metal organic skeleton material
A method of electrochemically preparing a crystalline, porous, metal-organic framework material comprising at least one at least bidentate organic compound coordinately bound to at least one metal ion, in a reaction medium comprising the at least one bidentate organic compound, wherein at least one metal ion is provided in the reaction medium by the oxidation of one anode comprising the corresponding metal. |
| US07968738B2 |
Compounds and methods for the treatment of cancer
The present invention provides organic arsenicals. Many of these compounds have potent in vitro cytotoxic activity against numerous human tumor cell lines, both of solid and hematological origin, as well as against malignant blood cells from patients with leukemia. |
| US07968732B1 |
Process for the preparation of 5-benzyloxy-2-(4-benzyloxyphenyl)-3-methyl-1H-indole
The present invention is related to a process for the preparation of 5-benzyloxy-2-(4-benzyloxyphenyl)-3-methyl-1H-Indole (formula-1, a useful intermediate for the synthesis of bazedoxifene) using 4-benzyloxy propiophenone and 4-benzyloxy phenyl hydrazine hydrochloride. |
| US07968724B2 |
Ester derivatives as phosphodiesterase inhibitors
The invention provides inhibitors of the phosphodiesterase 4 (PDE4) enzyme. More particularly, the invention relates to compounds that are new ester derivatives, methods of preparing such compounds, compositions containing them, and therapeutic uses thereof. |
| US07968719B2 |
Indazole derivatives as inhibitors of hormone sensitive lipase
The present invention relates to indazole derivatives of the general formulae I or II having the meanings indicated in the description, to the pharmaceutically useful salts thereof and the use thereof as drugs. |
| US07968716B2 |
Caspase inhibitors and uses thereof
This invention provides novel caspase inhibitors of formula I: wherein R1 is hydrogen, CHN2, R, or —CH2Y; R is an aliphatic group, an aryl group, an aralkyl group, a heterocyclyl group, or a heterocyclylalkyl group; Y is an electronegative leaving group; R2 is CO2H, CH2CO2H, or esters, amides or isosteres thereof; X2—X1 is N(R3)—C(R3), C(R3)2—C(R3), C(R3)2—N, N═C, C(R3)═C, C(═O)—N, or C(═O)—C(R3); each R3 is independently selected from hydrogen or C1-6 aliphatic; Ring C is a fused aryl ring; n is 0, 1 or 2; and each methylene carbon in Ring A is optionally and independently substituted by ═O, or one or more halogen, C1-4 alkyl, or C1-4 alkoxy. The compounds are useful for treating caspase-mediated diseases. |
| US07968714B2 |
Optical determination of glucose utilizing boronic acid adducts
The present invention concerns an improved optical method and optical sensing device for determining the levels of polyhydroxyl-substituted organic molecules in vitro and/or in vivo in aqueous media. The range of detection is between about 400 and 800 nm. In particular, a sensory devise is implemented in a mammal to determine sugar levels. Specifically, a dye is combined with a conjugated nitrogen-containing heterocyclic aromatic boronic acid-substituted bis-onium compound in the presence of a sugar, such as fructose or glucose. The viologens are preferred as the aromatic conjugated nitrogen-containing boronic acid substituted compounds. The method is useful to determine sugar levels in a human being. |
| US07968713B2 |
Method of synthesizing quinoxaline derivative by microwave irradiation
There is disclosed a method of synthesizing a quinoxaline derivative in which toxicity, corrosiveness and permeation are low and which is excellent in safety and which attains a reduced reaction time, a greatly improved yield and excellent economical efficiency. The object is achieved by a method of synthesizing a quinoxaline derivative which comprises adsorbing a benzofuroxan derivative and a β-diketone derivative on a solid support, and then heating the derivatives in a solid state by microwave irradiation to dehydrocyclize them. An example of a quinoxaline derivative is a compound of formula (4): |
| US07968711B2 |
Abnormal cannabidiols as agents for lowering intraocular pressure
The present invention provides a method of treating glaucoma or ocular hypertension which comprises applying to the eye of a person in need thereof an amount sufficient to treat glaucoma or ocular hypertension of a compound of formula I wherein Y, Q, Z, R, R1 and R2 are as defined in the specification. The present invention further comprises pharmaceutical compositions, e.g. ophthalmic compositions, including said compound. |
| US07968705B2 |
Production of 5'-ribonucleotides
The present invention describes a composition comprising at least 55% w/w (on sodium chloride free dry matter weight) of 5′-ribonucleotides and a process for the production of this composition comprising the steps of: (i) treating microbial cells to release the cell contents comprising RNA; (ii) separating the RNA present in the released cell content from other soluble cell material; and (iii) converting the separated RNA into 5′-ribonucleotides. |
| US07968704B2 |
Process for the production of sugar alcohols
Disclosed is a method for producing polyalcohols in the form of sugar alcohols from the group comprising sorbitol and mannitol and other optional C2 to C6 polyols. According to said method, a monosaccharide, disaccharide, oligosaccharide, or polysaccharide containing at least one glucose unit and/or at least one fructose unit is continuously reacted with hydrogen at an elevated temperature and at a great pressure in an aqueous phase in the presence of a hydrogenating catalyst based on ruthenium or ruthenium oxide so as to obtain the inventive polyalcohols. The minimum temperature is set at 100° C. while the minimum pressure is set at 150 bar and the maximum dwell time of the reactants during catalytic hydrogenation is set at 600 s. The inventive method is particularly suitable for producing the sugar alcohols sorbitol and/or mannitol or C2 to C6 polyols from glucose, fructose, or disaccharides, oligosaccharides, or polysaccharides containing glucose units or fructose units, especially saccharose, practically all the used saccharides being reacted without turning into caramel. Furthermore, the yield of said sugar alcohols or C2 to C6 polyols is exceptionally high while the selectivity for the desired products can be varied in a simple manner within broad boundaries. |
| US07968703B2 |
Process and methods for the preparation of optically active cis-2-hydroxymethyl-4- (cytosin-1'-yl)-1,3-oxathiolane or pharmaceutically acceptable salts thereof
There is provided a method for resolving a compound of formula III, in the cis configuration: There is also provided a process for producing optically active compound of formula I or II: wherein: R1, R2, R3 are as defined herein, the method and process involving the production, recovery and conversion of diastereomeric salts. |
| US07968702B2 |
Labeled reactants and their uses
Labeled reactant compositions, and particularly labeled nucleic acid reaction compositions, that include structural components that maintain potentially damaging labeling components sufficiently distal from the reactant portion of the molecule such that damaging effects of the label group on other reaction components, such as enzymes, are reduced, minimized and/or eliminated. |
| US07968700B2 |
Expression augmenting DNA fragments, use thereof, and methods for finding thereof
The invention provides recombinant DNA molecules comprising novel expression augmenting DNA fragments and an expression cassette, said expression cassette comprising a heterologous promoter linked to a nucleic acid of interest. The invention further provides uses of the novel expression augmenting DNA fragments. The invention further provides methods for obtaining novel expression augmenting DNA fragments. |
| US07968697B2 |
Hepatitis C virus non-structural NS3/4A fusion gene
The creation of mutant hepatitis C virus (HCV) NS3/4A genes encoding proteins with altered protease activity is disclosed. Embodiments include these NS3/4A genes, HCV peptides encoded by these nucleic acids, nucleic acids encoding these HCV peptides, antibodies directed to these peptides, compositions containing these nucleic acids and peptides, as well as methods of making and using these compositions including, but not limited to, diagnostics and medicaments for the treatment and prevention of HCV infection. |
| US07968695B2 |
Nucleic acids encoding recombinant 56 and 82 kDa antigens from gametocytes of Eimeria maxima and their uses
The present invention provides the recombinant cloning and sequencing of two of the major Eimeria maxima gametocyte antigens having molecular weights of 56 and 82 kDa and the expression of these recombinant antigens in an E. coli expression system using the plasmid pTrcHis. The subject invention also provides a vaccine against coccidiosis comprising the recombinant 56 kDa or 82 kDa antigen. The subject invention also provides two 30 kDa proteins and three 14 kDa proteins from Eimeria maxima gametocytes having at the N-terminal end the amino acid sequence described herein. The subject invention also provides a vaccine against coccidiosis comprising the recombinant 56 kDa or 82 kDa antigen and any of the aforementioned proteins. Additionally, the subject invention also provides a method of immunizing a subject against infection by Eimeria tenella, Eimeria maxima, Eimeria acervulina, Eimeria necatrix, Eimeria praecox, Eimeria mitis or Eimeria brunetti, or a microorganism expressing an immunologically cross-reactive antigen, comprising the step of administering to the subject any of the aforementioned vaccines. |
| US07968693B2 |
Human T2R51 nucleic acid sequences and polypeptides
Newly identified mammalian taste-cell-specific G Protein-Coupled Receptors and the genes encoding said receptors are described. Specifically, T2R taste G Protein-Coupled Receptors that are believed to be involved in bitter taste sensation, and the genes encoding the same, are described, along with methods for isolating such genes and for isolating and expressing such receptors. Methods for representing taste perception of a particular tastant in a mammal are also described, as are methods for generating a novel molecules or combinations of molecules that elicit a predetermined taste perception in a mammal, and methods for simulating one or more tastes. |
| US07968686B2 |
Glucagon receptor antagonists
The present invention relates to glucagon receptor polypeptide antagonists which inhibit the binding of the hormone glucagon to its receptor. More particularly, the present invention relates to high affinity glucagon receptor antibodies or Fab fragments thereof that inhibit binding of glucagon to its receptor and their use in the treatment or prevention of type 2 diabetes (NIDDM) and related disorders in mammalian species. |
| US07968683B1 |
Factor IXa crystals, related complexes and methods
The present invention relates to factor IXa complexes and crystals thereof as well as methods for identifying inhibitors of factor IXa. |
| US07968672B2 |
Phenolic resin, process for production thereof, epoxy resin, and use thereof
A phenol aralkyl type phenolic resin represented by the general formula (1), wherein the total content of the compounds represented by formulae (2) to (4) is 58 to 92% as determined by GPC and the contents of the compounds represented by formulae (2) to (4) as determined by HPLC satisfy the following relationship: 0.60≦(2a+b)/(2a+2b+2c)≦0.90 wherein a is the content of the compound of formula (2); b is the content of the compound of formula (3); and c is the content of the compound of formula (4). |
| US07968667B2 |
Adhesive compositions for optical fibers
To provide adhesive compositions for optical fibers which are curable with moisture and excellent in adhesiveness and resistance to moist heat.An Adhesive composition for optical fibers containing (A) a component having a reactive silicon containing group which contains (e) a compound obtained by reacting (a) an epoxy compound having at least one epoxy group with (b) a silane coupling agent having both a reactive silicon containing group and an epoxy-reactive group, wherein the component (A) has a molecular weight of 1000 or below per reactive silicon containing group; and an adhesive composition for optical fibers containing an alkylsilyl ester and (B) a compound other than the alkylsilyl ester which has at least one reactive silicon containing group. |
| US07968665B2 |
Highly flowable 1-butene polymer and process for producing the same
A 1-butene polymer satisfying the following (1), (2) and either (3) or (3′): a process for producing the polymer; a resin modifier comprising the polymer; and a hot-melt adhesive containing the polymer. (1) The intrinsic viscosity [η] as measured in tetralin solvent at 135° C. is 0.01 to 0.5 dL/g. (2) The polymer is a crystalline resin having a melting point (Tm-D) of 0 to 100° C., the melting point being defined as the top of the peak observed on the highest-temperature side in a melting endothermic curve obtained with a differential scanning calorimeter (DSC) in a test in which a sample is held in a nitrogen atmosphere at −10° C. for 5 min and then heated at a rate of 10° C./min. (3) The stereoregularity index {(mmmm)/(mmrr+rmmr)} is 30 or lower. (3′) The mesopentad content (mmmm) determined from a nuclear magnetic resonance (NMR) spectrum is 68 to 73%. |
| US07968663B2 |
Anion exchange polymers, methods for making and materials prepared therefrom
A novel anion exchange polymer is provided. A method of making the anion exchange polymer includes reacting a tertiary amine, an acid inhibitor and a polyepoxide to form a quaternary ammonium monomer and polymerizing the quaternary ammonium monomer in the presence of a catalyst. The exchange polymer is prepared without using alkyl halides and can be used to make improved ion exchange materials that are chemically resistant and non-fouling. |
| US07968658B2 |
Method for producing polymers by dispersion polymerization
Process for producing polymers by spray polymerization wherein the monomer solution is dispersed in a hydrophobic liquid, the use of the polymers for thickening liquids and also an apparatus for producing polymers by spray polymerization. |
| US07968653B2 |
Modification process for polymer surfaces, notably for hydroxylation of polymer surfaces and products so obtained
The present invention concerns the use of RO. radicals, R being a hydrogen, an alkyl group having 2 to 15 carbons, an acyl group —COR′ in which R′ represents an alkyl group having 2 to 15 carbons, or an aroyl group —COAr in which Ar represents an aromatic group having 6 to 15 carbons, for the hydroxylation, alkoxylation or oxycarbonylation of polymer surfaces, the said polymers being different from polymers chosen from: polymethylmethacrylate (PMMA) and fluorocarbon polymers when R represents a hydrogen, or of polymer mixture surfaces, notably hydrophobic ones, the said polymers consisting in monomeric units of which at least 50% among these are aliphatic units, and the said RO. radicals being generated by electrochemical or photochemical means. |
| US07968652B2 |
Modified conjugated diene copolymer, rubber compositions and tires
The present invention provides a modified conjugated diene polymer that is prepared by polymerization of a conjugated diene compound using a catalyst containing a lanthanoid rare earth element compound in an organic solvent and then modifying the resulting polymer having an active organic metal site with a modifier, wherein the modification efficiency is not less than 15% and the cis-1,4 bond content in the conjugated diene moiety measured by Fourier transform infrared spectroscopy satisfies the relationship (I): cis-1,4 bond content≧98.00(%) (I), or the modification efficiency is not less than 75% and the cis-1,4 bond content in the conjugated diene moiety measured by Fourier transform infrared spectroscopy satisfies the relationship (II): 94.00(%)≦cis-1,4 bond content<98.00(%) (II). The invention further provides a rubber composition containing the modified conjugated diene polymer and giving a tire exhibiting low heat build-up, satisfactory failure characteristics, and high abrasion resistance, and a tire composed of the rubber composition and exhibiting these characteristics. |
| US07968646B2 |
Method of in situ bioproduction and composition of bacterial cellulose nanocomposites
Provided are novel methods for making cellulose nanocomposites, comprising biosynthesis of cellulose fibrils in situ using a growth medium comprising a polymer matrix material, under conditions suitable to provide for dispersion of the fibril throughout the growth medium as the fibrils are being formed to provide a cellulose nanocomposite material or film wherein the cellulose fibrils are highly or uniformly dispersed in the cellulose nanocomposite material, and wherein fibril structure and/or nanocomposite composition is customizable. Certain method aspects further comprise removing or separating the cellulose nanocomposite material or film from the medium, and may further comprise washing the cellulose nanocomposite material or film to remove residual medium. Particular aspects further comprise freeze-drying the cellulose nanocomposite material or film, and/or further comprise forming a molded product using the cellulose nanocomposite material or film. Compositions made by the methods are provided. |
| US07968641B2 |
Water-dispersible polyurethane-vinyl polymer compositions
A polyurethane dispersion is prepared by reacting a hydroxy-functional sulfonated unsaturated alkyd with an isocyanate in the presence of one or more vinyl monomers to form a blend containing the vinyl monomers and a sulfonated polyurethane polymer containing ethylenic groups. The blend is dispersed in water and the vinyl monomers are reacted by free radical polymerization. |
| US07968634B2 |
Tire compositions and components containing silated core polysulfides
Sulfur-containing silane coupling agents, and organic polymers containing carbon-carbon double bonds. These silanes can be carried on organic and inorganic fillers. The invention also relates to tire compositions and articles of manufacture, particularly tires, made from elastomer compositions. |
| US07968633B2 |
Tire compositions and components containing free-flowing filler compositions
Free-flowing filler compositions containing sulfur-containing silane coupling agents, and a tire composition containing the filler composition, for use in the manufacture of tires. |
| US07968632B2 |
Polycarbonate resin composition and process for producing thereof
There is provided an antistatic polycarbonate resin composition and molded product formed by melt-molding the said resin composition, which resin composition has totally well balanced excellent properties including heat resistance, in which yellow- or brown-coloring can be prevented even though under melt-kneading step, molding step and such a circumstance that it is used at high temperature for long times, and the fluidity is improved without notably deterioration of mechanical strengths and transparency.A polycarbonate resin composition comprising 100 parts by weight of polycarbonate resin, 0.1 to 5.0 parts by weight of phosphonium sulfonate (A) represented by the following chemical formula (1), 0.1 to 10 parts by weight of aromatic polycarbonate resin oligomer (B) and 0.01 to 8 parts by weight of caprolactone-based polymer (C); and a molded product produced by melt-molding the said polycarbonate resin. |
| US07968629B2 |
Flame retardant polyamide resin composition and molded article
A flame retardant polyamide resin composition having excellent extrudability and moldability, being free of generating a highly corrosive hydrogen halide gas upon combustion, exhibiting very high flame retardancy, having excellent mechanical properties and electrical properties and being suited for use in electrical and electronic parts and parts for automobile electrical equipments, and a molded article thereof are provided. A polyamide resin composition comprising 100 parts by weight of an aliphatic polyamide resin (A) having a viscosity number of 70 to 200 ml/g, 0.1 to 30 parts by weight of a polyphenylene ether-based resin (B), and 5 to 100 parts by weight of flame retardant agent (C) comprising at least the following components (a), (b) and (c); (a) a reaction product of a melamine and a phosphoric acid, (b) a phosphinic acid salt and/or a diphosphinic acid salt, and (c) a metal salt of boric acid, wherein a compounding weight ratio (a):(b):(c) of the flame retardant agent components is 1:(0.5 to 2.5):(0.01 to 1). |
| US07968621B2 |
Pigment dispersed liquid, production method for the same, and light curable ink composition using the pigment dispersed liquid
Pigment dispersed liquid contains, at least: a colorant; a dispersant; and a polymerizable compound, the pigment dispersed liquid contain a substantial amount of a polymerization inhibitor. |
| US07968619B2 |
Composition for polyester fabric treatment
A composition useful for treating fabrics. The composition contains a silver-containing copolymer having polymerized units of a monomer X and a monomer Y; wherein monomer X is an ethylenically unsaturated compound having a substituent group selected from an unsaturated or aromatic heterocyclic group having at least one nitrogen atom; wherein monomer Y is selected from carboxylic acids, carboxylic acid salts, carboxylic acid esters, organosulfuric acids, organosulfuric acid salts, sulfonic acids, sulfonic acid salts, phosphonic acids, phosphonic acid salts, vinyl esters, (meth)acrylamides, C8-C20 aromatic monomers containing at least one exocyclic ethylenic unsaturation and combinations thereof. |
| US07968618B2 |
One-component dental adhesive compositions and method of use
A one-component self-etching self-priming dental adhesive composition is disclosed. The composition comprises glycerol phosphate di(meth)acrylate monomer, at least one mono-functional polymerizable monomer having just one ethylenically unsaturated group, at least one multi-functional polymerizable monomer having at least two ethylenically unsaturated groups, at least one aprotic solvent, at least one protic solvent, and at least one polymerization initiator. |
| US07968616B2 |
Bone cement composition and method
The disclosure is directed to a composition includes a first component and a second component. The first component includes a poly(methyl methacrylate) (PMMA), a contrast agent, and a radical donor. The second component includes methyl methacrylate (MMA), a radical scavenger, and a polymerization accelerator. The composition has an average setting time of about 13 minutes. The disclosure is further directed to a kit and a method of making the above-mentioned composition. |
| US07968614B2 |
Macromer composition including light activated initiator
The invention provides compositions that include macromers and visible light-activated polymerization initiators, and methods for forming a matrix using these compositions in conjunction with a light source that emits light primarily in the visible light spectrum. |
| US07968609B2 |
Mixtures of nanoparticles
Methods of sol-gel processing for the preparation of mixed gels and nanoparticles are described. Further, mixed gels and nanoparticles obtained by the method are also disclosed. More specifically, a process for mixture of NiO nanoparticles and Yttria stabilized Zirconia nanoparticles obtained by only one sol-gel process is described. |
| US07968606B2 |
Perfume composition having sedative effect
The present invention provides a perfume composition, which comprises at least one trimethoxybenzene in an amount of less than 0.5% by weight based on the total weight of the perfume composition. The present invention also provides a method for providing sedation in a subject, which comprises applying a perfume composition comprising at least one trimethoxybenzene in an amount of less than 0.5% by weight based on the total weight of the perfume composition to the subject. |
| US07968605B2 |
Methods for treating inflammatory disease by administering aldehydes and derivatives thereof
A method is disclosed for treating inflammatory disease in an animal in need thereof by administering to the animal a pharmaceutical composition containing an anti-inflammatory effective amount of an organic aldehyde compound or a derivative thereof in a pharmaceutically acceptable vehicle. |
| US07968604B2 |
Pharmaceutical composition for prevention and treatment of drug or alcohol addiction or bipolar disorder using sodium phenylbutyrate
Provided is a pharmaceutical composition for prevention and treatment of drug or alcohol addiction or bipolar disorder, comprising sodium phenylbutyrate (PBA). The pharmaceutical composition for prevention and treatment of drug or alcohol addiction or bipolar disorder in accordance with the present invention provides effects capable of inhibiting increases in locomotor activity which is a behavioral indicator of drug or alcohol addiction or bipolar disorder, by controlling a level of a neurotransmitter via regulation of expression of a neurotransmitter transporter. |
| US07968601B2 |
Adamantyl acetamides as 11-β hydroxysteroid dehydrogenase inhibitors
the N-oxide forms, the pharmaceutically acceptable addition salts and the stereochemically isomeric forms thereof, wherein n represents an integer being 1 or 2; R1 and R2 each independently represents hydrogen C1-4alkyl, NR9R10, C1-4alkyloxy; or R1 and R2 taken together with the carbon atom with which they are attached form a C3-6cycloalkyl; and where n is 2, either R1 or R2 may be absent to form an unsaturated bond; R3 represents a C6-12cycloalkyl, preferably selected from cylo-octanyl and cyclohexyl or R3 represents a monovalent radical having one of the following formulae wherein said C6-12cycloalkyl or monovalent radical may optionally be substituted with one, or where possible two, three or more substituents selected from the group consisting of C1-4alkyl, C1-4alkyloxy, halo or hydroxy; Q represents Het1 or Ar2 wherein said C3-8cycloalkyl, Het1 or Ar2 are optionally substituted with one or where possible two or more substituents selected from halo, C1-4alkyl, C1-4alkyloxy, hydroxy, nitro, NR5R6, C1-4alkyloxy substituted with one or where possible two, three or more substituents each independently selected from hydroxycarbonyl, Het2 and NR7R8, and C1-4alkyl substituted with one or where possible two or three halo substituents, preferably trifluoromethyl; R5 and R6 each independently represent hydrogen, C1-4alkyl, or C1-4alkyl substituted with phenyl; R7 and R8 each independently represent hydrogen or C1-4alkyl; R9 and R10 each independently represent hydrogen, C1-4alkyl or C1-4alkyloxycarbonyl; L represents C1-4alkyl; Het1 represents a heterocycle selected from pyridinyl, thiophenyl, or 1,3-benzodioxolyl; Het2 represents piperidinyl, pyrrolidinyl or morpholinyl; Ar2 represents phenyl, naphtyl or indenyl. |
| US07968585B2 |
Inhibitors of 11-beta-hydroxysteroid dehydrogenase 1
The present invention discloses novel compounds of Formula (I): having 11β-HSD type 1 antagonist activity, as well as methods for preparing such compounds. In another embodiment, the invention discloses pharmaceutical compositions comprising compounds of Formula I, as well as methods of using the compounds and compositions to treat diabetes, hyperglycemia, obesity, hypertension, hyperlipidemia, metabolic syndrome, and other conditions associated with 11β-HSD type 1 activity. |
| US07968581B2 |
Imidazolidine compounds as androgen receptor modulators
Novel compounds are disclosed that have a Formula represented by the following: wherein X, R1, R2a, R2b, R2c, R3a R3b, R4a, R4b, R4c, and m1 are as described herein. The compounds may be prepared as pharmaceutical compositions, and may be used for the prevention and treatment of a variety of conditions in mammals including humans, including by way of non-limiting example, cachexia, osteoporosis, sarcopenia, a decline in libido and/or sexual dysfunction. |
| US07968573B2 |
Hydrazide compound and pesticidal use of the same
A hydrazide compound represented by the formula (1): (wherein R1, R2, R3, R4, A1, A2, J, Q and n are defined in the specification) has excellent pesticidal activity. |
| US07968570B2 |
Isoindolone compounds and their use as metabotropic glutamate receptor potentiators
The present invention is directed to compounds of formula I: wherein R1, R2, R3, R4, R5, R6, R7, R8, R9 and n are as defined for formula I in the description. The invention also relates to processes for the preparation of the compounds and to new intermediates employed in the preparation, pharmaceutical compositions containing the compounds, and to the use of the compounds in therapy. |
| US07968567B2 |
Compounds for the modulation of PPARγ activity
Modulators of PPARγ activity are provided which are useful in pharmaceutical compositions and methods for the treatment of conditions such as type II diabetes and obesity. |
| US07968564B2 |
HIV integrase inhibitors
Tricyclic compounds of Formula I are inhibitors of HIV integrase and inhibitors of HIV replication: wherein bond a, ring A, R1, R2 and R3 are defined herein. The compounds are useful for the prophylaxis or treatment of infection by HIV and the prophylaxis, treatment, or delay in the onset of AIDS. The compounds are employed against HIV infection and AIDS as compounds per se or in the form of pharmaceutically acceptable salts. The compounds and their salts can be employed as ingredients in pharmaceutical compositions, optionally in combination with other antivirals, immunomodulators, antibiotics or vaccines. |
| US07968563B2 |
Oxime and hydroxylamine substituted imidazo[4,5-c] ring compounds and methods
Imidazo[4,5-c] ring compounds, (e.g. imidazo[4,5-c]pyridines, imidazo[4,5-c]quinolines, 6,7,8,9-tetrahydro imidazo[4,5-c]quinolines, imidazo[4,5-c]naphthyridine, and 6,7,8,9-tetrahydro imidazo[4,5-c]naphthyridine compounds) having an oxime or hydroxylamine substituent at the 2-position, pharmaceutical compositions containing the compounds, intermediates, and methods of making and methods of use of these compounds as immunomodulators, for modulating cytokine biosynthesis in animals and in the treatment of diseases including viral and neoplastic diseases are disclosed. |
| US07968562B2 |
Pharmaceutical formulations comprising an immune response modifier
Pharmaceutical formulations comprising an immune response modifier (IRM) chosen from imidazoquinoline amines, imidazotetrahydroquinoline amines, imidazopyridine amines, 6,7-fused cycloalkylimidazopyridine amines, 1,2-bridged imidazoquinoline amines, thiazolo-quinolineamines, oxazolo-quinolinamines, thiazolo-pyridinamines, oxazolo-pyridinamines, imidazonaphthyridine amines, tetrahydroimidazonaphthyridine amines, and thiazolonaphthyridine amines; a fatty acid; and a hydrophobic, aprotic component miscible with the fatty acid are useful for the treatment of dermal associated conditions. Novel topical formulations are provided. In one embodiment, the topical formulations are advantageous for treatment of actinic keratosis, postsurgical scars, basal cell carcinoma, atopic dermatitis, and warts. |
| US07968553B2 |
Tetrahydro-4H-pyrido[1,2-a] pyrimidines useful as HIV integrase inhibitors
Tetrahydro-4H-pyrido[1,2-a]pyrimidines and related compounds of Formula A: are described as inhibitors of HIV integrase and inhibitors of HIV replication, wherein n is an integer equal to zero, 1, 2 or 3, and R1, R3, R4, R12, R14, R16, R30, R32, R34 and R36 are defined herein. These compounds are useful in the prevention and treatment of infection by HIV and in the prevention, delay in the onset, and treatment of AIDS. The compounds are employed against HIV infection and AIDS as compounds per se or in the form of pharmaceutically acceptable salts. The compounds and their salts can be employed as ingredients in pharmaceutical compositions, optionally in combination with other antivirals, immunomodulators, antibiotics or vaccines. |
| US07968552B2 |
Oxadiazolidinedione compound
A compound which can be used as a pharmaceutical, particularly a insulin secretion promoter or a agent for preventing/treating disease in which GPR40 is concerned such as diabetes or the like, is provided.It was found that an oxadiazolidinedione compound which is characterized by the possession of a benzyl or the like substituent binding to the cyclic group via a linker at the 2-position of the oxadiazolidinedione ring, or a pharmaceutically acceptable salt thereof, has excellent GPR40 agonist action. In addition, since the oxadiazolidinedione compound of the present invention showed excellent insulin secretion promoting action and blood glucose level-lowering action, it is useful as an insulin secretion promoter or an agent for preventing/treating diabetes. |
| US07968549B2 |
Diarylmethylpiperazines as therapeutic agents for viral myocarditis
To provide a therapeutic agent for viral myocarditis and viral myocarditis-related viral diseases by treating the occurrence of cell damage in various organs regardless of the type of virus. A therapeutic agent for viral myocarditis and viral myocarditis-related viral diseases is provided that has as an active ingredient 2-[4-(dipehnylmethyl)-1-piperazinyl]-acetic acid, amide derivative, individual optical isomer or pharmaceutically acceptable salt thereof. |
| US07968544B2 |
Modulators of toll-like receptor 7
The present application includes a compound of Formula I or II: or a pharmaceutically acceptable-salt, solvate, and/or ester thereof, compositions containing such compounds, therapeutic methods that include the administration of such compounds, and therapeutic methods that include the administration of such compounds with at least one additional active agent. |
| US07968541B2 |
Crystalline form of N-[[4-fluoro-2-(5-methyl-1H-1,2,4-triazol-1-yl)phenyl]methyl]-4,6,7,9-tetrahydro-3-hydroxy-9,9-dimethyl-4-oxo-pyrimido[2,1-C][1,4]-oxazine-2-carboxamide, sodium salt monohydrate
Disclosed is a crystalline form of N-[[4-fluoro-2-(5-methyl-1H-1,2,4-triazol-1-yl)phenyl]methyl]-4,6,7,9-tetrahydro-3-hydroxy-9,9-dimethyl-4-oxo-pyrimido[2,1-c][1,4]oxazine-2-carboxamide, sodium salt monohydrate. Also disclosed are at least one pharmaceutical composition comprising at least one crystalline form of N-[[4-fluoro-2-(5-methyl-1H-1,2,4-triazol-1-yl)phenyl]methyl]-4,6,7,9-tetrahydro-3-hydroxy-9,9-dimethyl-4-oxo-pyrimido[2,1-c][1,4]oxazine-2-carboxamide, sodium salt monohydrate, and at least one method of using at least one crystalline form of N-[[4-fluoro-2-(5-methyl-1H-1,2,4-triazol-1-yl)phenyl]methyl]-4,6,7,9-tetrahydro-3-hydroxy-9,9-dimethyl-4-oxo-pyrimido[2,1-c][1,4]oxazine-2-carboxamide, sodium salt monohydrate to treat AIDS or HIV infection. |
| US07968539B2 |
Quinoline derivatives and uses thereof
This disclosure provides a new class of compounds referred to as “reversed chloroquines” (RCQs), which are highly effective against CQR and CQS malaria parasites. RCQs are hybrid molecules, which include an antimalarial quinoline analog (such as chloroquine) moiety and a CQR reversal moiety. Exemplary RCQ chemical structures are provided. Also provided are pharmaceutical compositions including the disclosed RCQ compounds, and methods of using such compounds and compositions for the treatment of malaria and inhibition of CQR or CQS Plasmodium sp. (such as P. falciparum). |
| US07968532B2 |
Treatment of gynecomastia with 4-hydroxy tamoxifen
The present invention provides methods for treating and preventing gynecomastia by administering 4-hydroxy tamoxifen to a patient. When percutaneously administered to a patient's breasts, 4-hydroxy tamoxifen concentrates locally, and exerts an anti-estrogenic effect. In patients with gynecomastia, this reduces the effective estrogen-androgen ratio in the breast tissue, thereby reducing ductal proliferation, epithelial and stromal hyperplasia, and pain. In patients at risk for developing gynecomastia, 4-hydroxy tamoxifen's anti-estrogenic effect prevents tissue proliferation and its accompanying pain. |
| US07968528B2 |
Choline-silicic acid complex with osmolytes and divalent trace elements
The invention relates to a biological preparation comprising orthosilicic and silicic acid, a primary (“constant/first”) osmolyt choline and a weak alkalinizing agent without free hydroxyl groups and to a method for preparing the preparation, comprising: i) hydrolysing a silicon comprising choline solution thereby forming a choline stabilized orthosilicic acid and oligomers solution; ii) alkalizing the choline orthosilicic acid and oligomers solution by adding a weak alkalizing agent without hydroxyl groups; and iii) optionally adding a divalent trace element and/or secondary osmolyte, to biological preparation obtainable and its uses. |
| US07968525B1 |
Use of RNA interference to validate new termiticide target sites and a method of termite control
Methods, matrix compositions and kits for increasing the mortality of termites (R. flavipes) and interfering with termite development using RNA interference techniques to target cellulase, lignocellulase, hexamerin, broad, farnesoic acid methyl transferase, cytochrome P450 and vitellogenin activity are provided. |
| US07968519B2 |
Methods and compositions for controlled polypeptide synthesis
Methods and compositions for the generation of polypeptides having varied material properties are disclosed herein. Methods include means for initiating the polymerization of aminoacid-N-carboxyanhydride (NCA) monomer by combining the monomer with an amido-containing metallacycle, for making self assembling amphiphilic block copolypeptides and related protocols for adding oligo(ethyleneglycol) functionalized aminoacid-N-carboxyanhydrides (NCAs) to polyaminoacid chains. Additional methods include means of adding an end group to the carboxy terminus of a polyaminoacid chain by reacting an alloc-protected amino acid amide with a transition metal-donor ligand complex to forming an amido-amidate metallacycle for use in further polymerization reactions. Novel compositions for use in peptide synthesis and design including five and six membered amido-containing metallacycles and block copolypeptides are also disclosed. |
| US07968518B2 |
Use of modified cyclosporins for the treatment of HCV disorders
Disclosed are non-immunosuppressive cyclophilin-binding cyclosporins, e.g., of formula (I, Ia or II) as defined herein, having useful properties in the prevention of Hepatitis C infections. |
| US07968509B2 |
Softening detergent composition comprising a glyceryl monoether
The present invention relates to a softening detergent composition containing a glyceryl monoether represented by formula (I) and (b) a clay mineral: R—O—(C3H6O2)n—H (I) wherein R represents a hydrocarbon group having 6 to 22 carbon atoms and n represents the degree of condensation of glycerin and denotes a number from 3 to 5. |
| US07968508B2 |
Benzophenone or benzoic acid anilide derivatives containing carboxyl groups as enzyme stabilizers
Washing and cleaning agents containing benzophenone or benzole anilide derivatives containing carboxyl groups, which function as protease inhibitors and are suitable as enzyme stabilizers. Additional subjects are the use of such compounds as reversible inhibitors of a protease and consequently for a washing or cleaning agent formulation, and additional methods and uses relating thereto. |
| US07968506B2 |
Wet cleaning stripping of etch residue after trench and via opening formation in dual damascene process
After trench line pattern openings and via pattern openings are formed in a inter-metal dielectric insulation layer of a semiconductor wafer using trench-first dual damascene process, the wafer is wet cleaned in a single step wet clean process using a novel wet clean solvent composition. The wet clean solvent effectively cleans the dry etch residue from the plasma etching of the dual damascene openings, etches back the TiN hard mask layer along the dual damascene openings and forms a recessed surface at the conductor metal from layer below exposed at the bottom of the via openings of the dual damascene openings. |
| US07968501B2 |
Crosslinker suspension compositions and uses thereof
A delayed crosslinker system useful in downhole treatment fluids is disclosed. The crosslinker system comprises water-reactive solids, a non-aqueous, non-oily, hygroscopic liquid, a suspension aid, and an optional polyol. The crosslinker system may be prepared at a remote location and transported to the site of its intended use. There it may be pumped into a formation and activated when a gel fluid is introduced into the wellbore, only then forming a high viscosity treatment fluid. Thus, the amount of energy required for pumping is reduced. The optional polyol component increases crosslink delay and enhances the rate of viscosity after high shear (shear recovery). |
| US07968494B2 |
Heat-sensitive recording material
A heat-sensitive recording material including: a substrate; a heat-sensitive color developing layer over the substrate, the heat-sensitive color developing layer composed mainly of a leuco dye and a color developer that develops color of the leuco dye upon heating; and a protective layer over the heat-sensitive color developing layer, the protective layer composed mainly of a water-soluble resin and a crosslinking agent, wherein the protective layer contains diacetone-modified polyvinyl alcohol as the water-soluble resin, and N-aminopolyacrylamide as the crosslinking agent. |
| US07968491B2 |
Multi-layer catalyst for producing phthalic anhydride
The present invention relates to a catalyst for preparing phthalic anhydride by gas phase oxidation of o-xylene and/or naphthalene, comprising at least three catalyst zones which have different compositions and, from the gas inlet side toward the gas outlet side, are referred to as first, second and third catalyst zone, the catalyst zones having in each case an active composition comprising TiO2 with a content of Na of less than 0.3% by weight, and the active composition content decreasing from the first catalyst zone disposed toward the gas inlet side to the third catalyst zone disposed toward the gas outlet side, with the proviso that (a) the first catalyst zone has an active composition content between about 7 and 12% by weight, (b) the second catalyst zone has an active composition content in the range between 6 and 11% by weight, the active composition content of the second catalyst zone being less than or equal to the active composition content of the first catalyst zone, and (c) the third catalyst zone has an active composition content in the range between 5 and 10% by weight, the active composition content of the third catalyst zone being less than or equal to the active composition content of the second catalyst zone. Also described is a preferred process for preparing such a catalyst and the preferred use of the titanium dioxide used in accordance with the invention. |
| US07968485B2 |
Ceramic powder, ceramic layer and layer system of two pyrochlore phases and oxides
There is described a Ceramic Powder, a Ceramic Layer and a Layer System of Two Pyrochlore Phases and Oxides. Besides a good thermal insulation property, thermal insulation layer systems must also have a long lifetime of the thermal insulation layer. The layer system has a ceramic layer, which comprises a mixture of two pyrochlore phases. |
| US07968482B2 |
Glass substrate
Provided is a glass substrate, which has a substrate size of 1,100 mm×1,250 mm or more, and a transmittance at a wavelength of 500 to 800 nm and at a route length of 50 mm of 80% or more. |
| US07968478B2 |
Continuous cross-plied material and method of manufacturing same
A novel cross-plied material is formed of portions of a ply of a ballistic-resistant structure composed of unidirectionally-oriented bundles of high strength filaments laminated between opposing thermoplastic films which portions are cross-plied with portions of a continuous ply of a similar ballistic-resistant structure with a plurality of yarns laterally spaced into a linear array corresponding to the width of the continuous ply along the ply direction. Substantially continuous coatings or deposits of a bonding or coupling agent on the yarns cause a plurality of substantially continuous bonding strips to be formed between the continuous ply and the portions of cross-ply, with the bonding strips being laid in a laterally spaced linear array corresponding to the yarns. The bonding strips couple the cross-ply portions with consecutive portions of the continuous ply, whereby the continuous ply and the cross-ply portions are adhered sufficiently to prevent their being pulled apart. |
| US07968477B1 |
Fabric assembly suitable for resisting ballistic objects and method of manufacture
A fabric assembly particularly useful as soft body armor has two separate sections each containing a number of fabrics made from yarns having a tenacity of at least 7.3 grams per dtex and a modulus of at least 100 grams per dtex. Compressed fabrics in the first section are employed and are connected by connectors that have a force to break in tension not greater than 65N and define areas on the outer surfaces of the compressed fabric in a range from 15 to 350 square mm. Fabrics in the second section have at most a small amount of compression and are not joined other than to prevent slippage of the fabrics relative to one another. |
| US07968474B2 |
Methods for nanowire alignment and deposition
The present invention provides methods and systems for nanowire alignment and deposition. Energizing (e.g., an alternating current electric field) is used to align and associate nanowires with electrodes. By modulating the energizing, the nanowires are coupled to the electrodes such that they remain in place during subsequent wash and drying steps. The invention also provides methods for transferring nanowires from one substrate to another in order to prepare various device substrates. The present invention also provides methods for monitoring and controlling the number of nanowires deposited at a particular electrode pair, as well as methods for manipulating nanowires in solution. |
| US07968472B2 |
Film forming method and film forming apparatus
The invention includes inserting an object to be processed into a processing vessel, which can be maintained vacuum, and making the processing vessel vacuum; performing a sequence of forming a ZrO2 film on a substrate by alternately supplying zirconium source and an oxidizer into the processing vessel for a plurality of times and a sequence of forming SiO2 film on the substrate by alternately supplying silicon source and an oxidizer into the processing vessel for one or more times, wherein the number of times of performing each of the sequences is adjusted such that Si concentration of the films is from about 1 atm % to about 4 atm %; and forming a zirconia-based film having a predetermined thickness by performing the film forming sequences for one or more cycles, wherein one cycle indicates that each of the ZrO2 film forming sequences and the SiO2 film forming sequences are repeated for the adjusted number of times of performances. |
| US07968470B2 |
Plasma nitriding method, method for manufacturing semiconductor device and plasma processing apparatus
A nitriding process is performed at a process temperature of 500° C. or more by causing microwave-excited high-density plasma of a nitrogen-containing gas to act on silicon in the surface of a target object, inside a process container of a plasma processing apparatus. The plasma is generated by supplying microwaves into the process container from a planar antenna having a plurality of slots. |
| US07968463B2 |
Formation method of metallic compound layer, manufacturing method of semiconductor device, and formation apparatus for metallic compound layer
A formation method of a metallic compound layer includes preparing, in a chamber, a substrate having a surface on which a semiconductor material of silicon, germanium, or silicon germanium is exposed, and forming a metallic compound layer, includes: supplying a raw material gas containing a metal for forming a metallic compound with the semiconductor material to the chamber; heating the substrate to a temperature at which the raw material gas is pyrolyzed; and forming a metallic compound layer by reaction of the metal with the semiconductor material so that no layer of the metal is deposited on the substrate. A manufacturing method of a semiconductor device employs this formation method of a metallic compound layer. |
| US07968460B2 |
Semiconductor with through-substrate interconnect
Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via. |
| US07968456B2 |
Method of forming an embedded barrier layer for protection from chemical mechanical polishing process
A semiconductor interconnect structure and method providing an embedded barrier layer to prevent damage to the dielectric material during or after Chemical Mechanical Polishing. The method employs a combination of an embedded film, etchback, using either selective CoWP or a conformal cap such as a SiCNH film, to protect the dielectric material from the CMP process as well as subsequent etch, clean and deposition steps of the next interconnect level. |
| US07968455B2 |
Copper deposition for filling features in manufacture of microelectronic devices
A method for plating copper onto a semiconductor integrated circuit device substrate by forming an initial metal deposit in the feature which has a profile comprising metal on the bottom of the feature and a segment of the sidewalls having essentially no metal thereon, electrolessly depositing copper onto the initial metal deposit to fill the feature with copper. A method for plating copper onto a semiconductor integrated circuit device substrate by forming a deposit comprising a copper wettable metal in the feature, forming a copper-based deposit on the top-field surface, and depositing copper onto the deposit comprising the copper wettable metal to fill the feature with copper. |
| US07968454B2 |
Method of forming pattern structure
A method of forming a pattern structure includes forming a thin film pattern on a substrate, the thin film pattern including depression portions with first bottom widths, forming a protection layer on the thin film pattern by implanting ions into the thin film pattern, and etching a lower portion of the thin film pattern selectively using the protection layer as a mask to increase the first bottom widths of the depression portions into second bottom widths. |
| US07968449B2 |
Method for manufacturing printed wiring board
A method for manufacturing a printed wiring board having one or more layers of a conductive pattern and an insulating pattern, including forming an insulating pattern on an insulating substrate; semi-hardening at least one of the insulating substrate and the insulating pattern; forming a conductive pattern on the insulating substrate and/or the insulating pattern, thereby providing a stack structure; performing a thermal treatment on the stack structure to fully harden the semi-hardened insulating substrate and/or insulating pattern; and firing the conductive pattern. In the method, the conductive pattern and the insulating pattern are simultaneously formed on the same layer using an inkjet process. |
| US07968445B2 |
Semiconductor package with passivation island for reducing stress on solder bumps
A flip chip style semiconductor package has a substrate with a plurality of active devices formed thereon. A contact pad is formed over the substrate. An under bump metallization (UBM) layer is in electrical contact with the contact pad. A passivation layer is formed over the substrate. In one case, the UBM layer is disposed above the passivation layer. Alternatively, the passivation layer is disposed above the UBM layer. A portion of the passivation layer is removed to create a passivation island. The passivation island is centered with respect to the contact pad with its top surface devoid of the UBM layer. A solder bump is formed over the passivation island in electrical contact with the UBM layer. The passivation island forms a void in the solder bump for stress relief. The UBM layer may include a redistribution layer such that the passivation island is offset from the contact pad. |
| US07968444B2 |
Lead-free tin alloy electroplating compositions and methods
Disclosed are electrolyte compositions for depositing a tin alloy on a substrate. The electrolyte compositions include tin ions, ions of one or more alloying metals, a flavone compound and a dihydroxy bis-sulfide. The electrolyte compositions are free of lead and cyanide. Also disclosed are methods of depositing a tin alloy on a substrate and methods of forming an interconnect bump on a semiconductor device. |
| US07968442B2 |
Fin field effect transistor and method of fabricating the same
A fin field effect transistor includes a fin protruding from a semiconductor substrate, a gate insulating layer formed so as to cover upper and lateral surfaces of the fin, and a gate electrode formed across the fin so as to cover the gate insulating layer. An upper edge of the fin is rounded so that an electric field concentratedly applied to the upper edge of the fin through the gate electrode is dispersed. A thickness of a portion of the gate insulating layer formed on an upper surface of the fin is greater than a thickness of a portion of the gate insulating layer formed on a lateral surface of the fin, in order to reduce an electric field applied through the gate electrode. |
| US07968441B2 |
Dopant activation anneal to achieve less dopant diffusion (better USJ profile) and higher activation percentage
A method and apparatus for forming a semiconductor device. A semiconductor substrate is implanted with dopants. The substrate is subjected to a cleaning process employing electrically neutral nitrogen and fluorine radicals to produce an oxygen-free surface having dangling bonds. Before any further exposure to oxidizing gases, the substrate is annealed by thermal treatment to activate and distribute the dopants. A gate oxide layer is formed over the annealed surface. The apparatus performs all such treatments without breaking vacuum. |
| US07968439B2 |
Plasma immersion ion implantation method using a pure or nearly pure silicon seasoning layer on the chamber interior surfaces
Plasma immersion ion implantation employing a very high RF bias voltage on an electrostatic chuck to attain a requisite implant depth profile is carried out by first depositing a partially conductive silicon-containing seasoning layer over the interior chamber surfaces prior to wafer introduction. |
| US07968438B2 |
Ultra-thin high-quality germanium on silicon by low-temperature epitaxy and insulator-capped annealing
Exemplary embodiments provide semiconductor devices with a high-quality semiconductor material on a lattice mismatched substrate and methods for their manufacturing using low temperature growth techniques followed by an insulator-capped annealing process. The semiconductor material can have high-quality with a sufficiently low threading dislocation (TD) density, and can be effectively used for integrated circuit applications such as an integration of optically-active materials (e.g., Group III-V materials) with silicon circuitry. In an exemplary embodiment, the high-quality semiconductor material can include one or more ultra-thin high-quality semiconductor epitaxial layers/films/materials having a desired thickness on the lattice mismatched substrate. Each ultra-thin high-quality semiconductor epitaxial layer can be formed by capping a low-temperature grown initial ultra-thin semiconductor material, annealing the capped initial ultra-thin semiconductor material, and removing the capping layer. |
| US07968434B2 |
Method of forming of a semiconductor film, method of manufacture of a semiconductor device and a semiconductor device
This invention provides a method of forming semiconductor films on dielectrics at temperatures below 400° C. Semiconductor films are required for thin film transistors (TFTs), on-chip sensors, on-chip micro-electromechanical systems (MEMS) and monolithic 3D-integrated circuits. For these applications, it is advantageous to form the semiconductor films below 400° C. because higher temperatures are likely to destroy any underlying devices and/or substrates. This invention successfully achieves low temperature growth of germanium films using diboran. First, diboran gas is supplied into a reaction chamber at a temperature below 400° C. The diboran decomposes itself at the given temperature and decomposed boron is attached to the surface of a dielectric, for e.g., SiO2, forming a nucleation site and/or a seed layer. Second, source gases for semiconductor film formation, for e.g., SiH4, GeH4, etc., are supplied into the chamber, thereby forming a semiconductor film. |
| US07968433B2 |
Fabrication of nanowires and nanodevices
Methods of fabricating nanowire structures and nanodevices are provided. The methods involve photolithographically depositing a nucleation center on a crystalline surface of a substrate, generating a nanoscale seed from the nucleation center, and epitaxially growing a nanowire across at least a portion of the crystalline surface starting at a nucleation site where the nanoscale seed is located. |
| US07968432B2 |
Laser processing apparatus and laser processing method
A laser processing apparatus has one laser light source that simultaneously radiates laser beams with two wavelengths. Depth positions of focusing points for laser beams are gradually changed in a wafer. Three sets of modifying region groups, i.e., six layers of modifying region groups, are successively formed. One set of modifying region groups constitutes two layers and is formed at a time. The modifying region groups are separated, adjoined, or overlapped with each other along an estimated cut line of the wafer in a depth direction from a surface thereof. |
| US07968429B2 |
Method of manufacturing a semiconductor photodetector device by removing the semiconductor substrate on one surface after forming the light-transmitting layer on the opposing surface
A semiconductor photodetector device (PD1) comprises a multilayer structure (LS1) and a glass substrate (1) optically transparent to incident light. The multilayer structure includes an etching stop layer (2), an n-type high-concentration carrier layer (3), an n-type light-absorbing layer (5), and an n-type cap layer (7) which are laminated. A photodetecting region (9) is formed near a first main face (101) of the multilayer structure, whereas a first electrode (21) is provided on the first main face. A second electrode (27) and a third electrode (31) are provided on a second main face (102). A film (10) covering the photodetecting region and first electrode is formed on the first main face. A glass substrate (1) is secured to the front face (10a) of this film. |
| US07968422B2 |
Method for forming trench isolation using a gas cluster ion beam growth process
A method of forming shallow trench isolation on a substrate using a gas cluster ion beam (GCIB) is described. The method comprises generating a GCIB, and irradiating the substrate with the GCIB to form a shallow trench isolation structure by growing a dielectric layer in at least one region on the substrate. |
| US07968421B2 |
Method for manufacturing SOI structure in desired region of a semiconductor device
Manufacturing a semiconductor device includes defining bulb-type trenches having spherical portions in a silicon substrate. Oxide layers are formed in surfaces of spherical portions of the bulb-type trenches by conducting an oxidation process for the silicon substrate having the bulb-type trenches defined therein. An insulation layer is formed on the entire surface of the silicon substrate including the surfaces of the bulb-type trenches, which have the oxide layers formed in the surfaces of the spherical portions thereof. Isolation trenches are defined by etching the insulation layer, whereby SOI structures having the oxide layers interposed between portions of the silicon substrate are formed. |
| US07968420B2 |
Manufacturing semiconductor device and method of manufacturing electronic apparatus
A method for manufacturing a semiconductor device, includes: forming an insulating film on a substrate; selectively removing the insulating film, so as to form a groove including a first groove area having a first depth and a second groove area having a second depth, the second depth being smaller than the first depth; infusing a conductive liquid material into the first groove area and the second groove area; treating the conductive liquid material, so as to form a first conductive film in the first groove area and a second conductive film in the second groove area; and forming a second insulating film on the first and the second conductive films, followed by forming a third conductive film on the second insulating film. |
| US07968418B1 |
Apparatus and method for isolating integrated circuit components using deep trench isolation and shallow trench isolation
An isolation trench structure includes both a deep trench isolation (DTI) trench and a shallow trench isolation (STI) trench. The DTI trench can be formed by etching a deeper, narrower trench in a substrate and filling the deeper trench with one or more materials (such as an oxide). The STI trench can be formed by etching a shallower, wider trench in the substrate and filling the shallower trench with one or more materials (such as an oxide). The STI trench surrounds a portion of the DTI trench, such as by completely encircling an upper portion of the DTI trench. The DTI and STI trenches are filled during different operations, and the DTI and STI trenches can be filled with the same material(s) or with different material(s). |
| US07968415B2 |
Transistor with reduced short channel effects and method
A method of fabricating a transistor (10) comprises forming source and drain regions (46) and (47) using a first sidewall (42) and (43) as a mask and forming a deep blanket source and drain regions (54) and (56) using a second sidewall (50) and (51) as a mask, the second sidewall (50) and (51) comprising at least part of the first sidewall (42) and (43). |
| US07968413B2 |
Methods for forming a transistor
Methods are provided for depositing materials in forming semiconductor devices on a substrate, such as metal oxide transistors. In one embodiment, the invention generally provides a method of processing a substrate including forming a gate dielectric on a substrate having a first conductivity, forming a gate electrode on the gate dielectric, forming a first pair of sidewall spacers along laterally opposite sidewalls of the gate electrode, etching a pair of source/drain region definitions on opposite sides of the electrode, depositing a silicon-germanium material selectively in the source/drain region definitions, and implanting a dopant in the deposited silicon-germanium material to form a source/drain region having a second conductivity. |
| US07968412B2 |
Manufacturing process of a vertical-conduction MISFET device with gate dielectric structure having differentiated thickness and vertical-conduction MISFET device thus manufacture
According to an embodiment of a method for manufacturing a MISFET device, in a semiconductor wafer, a semiconductor layer is formed, having a first type of conductivity and a first level of doping. A first body region and a second body region, having a second type of conductivity, opposite to the first type of conductivity, and an enriched region, extending between the first and second body regions are formed in the semiconductor layer. The enriched region has the first type of conductivity and a second level of doping, higher than the first level of doping. Moreover, a gate electrode is formed over the enriched region and over part of the first and second body regions, and a dielectric gate structure is formed between the gate electrode and the semiconductor layer, the dielectric gate structure having a larger thickness on the enriched region and a smaller thickness on the first and second body regions. To form the enriched region, a first conductive layer is made on the semiconductor layer, an enrichment opening is formed in the first conductive layer, and a dopant species is introduced into the semiconductor layer through the enrichment opening. Furthermore, the formation of the dielectric gate structure envisages filling the enrichment opening with dielectric material, prior to forming the first body region and the second body region. |
| US07968402B2 |
Method for forming a high-performance one-transistor memory cell
One aspect of this disclosure relates to a memory cell. In various embodiments, the memory cell includes an access transistor having a floating node, and a diode connected between the floating node and a diode reference potential line. The diode includes an anode, a cathode, and an intrinsic region between the anode and the cathode. A charge representative of a memory state of the memory cell is held across the intrinsic region of the diode. In various embodiments, the memory cell is implemented in bulk semiconductor technology. In various embodiments, the memory cell is implemented in semiconductor-on-insulator technology. In various embodiments, the diode is gate-controlled. In various embodiments, the diode is charge enhanced by an intentionally generated charge in a floating body of an SOI access transistor. Various embodiments include laterally-oriented diodes (stacked and planar configurations), and various embodiments include vertically-oriented diodes. Other aspects and embodiments are provided herein. |
| US07968400B2 |
Short channel LV, MV, and HV CMOS devices
Low voltage, middle voltage and high voltage CMOS devices have upper buffer layers of the same conductivity type as the sources and drains that extend under the sources and drains and the gates but not past the middle of the gates, and lower bulk buffer layers of the opposite conductivity type to the upper buffer layers extend from under the upper buffer layers to past the middle of the gates forming an overlap of the two bulk buffer layers under the gates. The upper buffer layers and the lower bulk buffer layers can be implanted for both the NMOS and PMOS FETs using two masking layers. For middle voltage and high voltage devices the upper buffer layers together with the lower bulk buffer layers provide a resurf region. |
| US07968399B2 |
Semiconductor device and method of manufacturing the same
Disclosed is a semiconductor device comprising a semiconductor substrate including first and second element-formation regions partitioned by an isolation trench, first and second lower gate insulating films formed on the first and second element-formation regions, first and second floating gates formed on the first and second lower gate insulating films, an isolation insulating film formed at least in the isolation trench and has a depression formed in an upper surface thereof, an upper gate insulating film formed on the first and second floating gates, and a control gate line including an opposed portion opposed to the first and second floating gates, with the upper gate insulating film being interposed, and a portion located inside the depression, the first floating gate including a side surface opposed to the second floating gate and entirely aligns with a side surface included in the first element-formation region and defined by the isolation trench. |
| US07968397B2 |
Semiconductor device and method of manufacturing the same
A semiconductor device according to the present invention comprises a semiconductor substrate, a gate insulating film which is composed of a material whose main component is a tetravalent metal oxide, a mixture of a tetravalent metal oxide and SiO2, or a mixture of a tetravalent metal oxide and SiON and which containing B when it is in an nMOS structure on the semiconductor substrate or containing at least one of P and As when it is in a pMOS structure on the semiconductor substrate, and a gate electrode made of a metal having a work function of 4 eV to 5.5 eV. |
| US07968396B2 |
Semiconductor device and manufacturing method of the semiconductor device
A semiconductor device includes a semiconductor layer formed on an insulating layer; a gate electrode disposed on said semiconductor layer via a gate insulating film; a source/drain layer composed by including an alloy layer or a metal layer with a bottom surface in contact with the insulating layer, with joint surfaces to a channel region disposed along crystal orientation faces of said semiconductor layer; and impurity-doped layers formed in a self-aligned manner along interfaces of the alloy layer or the metal layer, and said semiconductor layer. |
| US07968392B2 |
Tri-gate integration with embedded floating body memory cell using a high-K dual metal gate
Dual-gate memory cells and tri-gate CMOS devices are integrated on a common substrate. A plurality of silicon bodies are formed from a monocrystalline silicon on the substrate to define a plurality of transistors including dual-gate memory cells, PMOS transistors, and NMOS transistors. An insulative layer is formed overlying the silicon body of the memory cell. A layer of a high-k dielectric and at least a metal layer cover the silicon bodies and their overlying layers. Next, gain regions of the transistors are filled with polysilicon. Thus, a gate is formed on the top surface and both sidewalls of a tri-gate transistor. Thereafter, the high-k dielectric and the metal layer overlying the insulative layer of the memory cell are removed to expose the insulative layer. Thus, two electrically-isolated gates of the memory cell are formed. |
| US07968387B2 |
Thin film transistor and method of fabricating thin film transistor substrate
Provided are a thin film transistor (TFT) capable of increasing ON current and decreasing OFF current values, a TFT substrate having the polysilicon TFT, a method of fabricating the polysilicon TFT, and a method of fabricating a TFT substrate having the polysilicon TFT. The polysilicon TFT substrate includes a gate line and a data line defining a pixel region, a pixel electrode formed in the pixel region, and a TFT including a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode connected to the pixel electrode, and a polysilicon active layer forming a channel between the source and drain electrodes. The polysilicon active layer includes a channel region on which the gate electrode is superposed, source and drain regions connected to the source and drain electrode, respectively, and at least two lightly doped drain (LDD) regions y formed between the source region and the channel region and between the drain region and the channel region. The LDD regions have an impurity concentration different from each other. |
| US07968383B2 |
Electronic device and method of manufacturing the same
A method of manufacturing an electronic device comprising the subsequent steps of: providing a thermal conversion material or an area comprising the thermal conversion material and, in an adjoining area or in a vicinity of the thermal conversion material or the area comprising the thermal conversion material, a material having an electromagnetic wave absorbing function or an area comprising the material having the electromagnetic wave absorbing function, in at least a portion on a substrate; and irradiating the substrate with an electromagnetic wave to transform the thermal conversion material into a functional material using a heat generated by the material having the electromagnetic wave absorbing function. |
| US07968378B2 |
Electronic device
One embodiment provides a method of manufacturing semiconductor devices. For example, a sawn and expanded wafer is utilized having dielectrical material deposited between the diced and deposited chips. The method includes placing at least two chips on a metallic layer, depositing mold material on the metallic layer and between the chips, and selectively removing a portion of the mold material from the metallic layer to selectively expose a portion of the metallic layer. The method additionally includes covering the selectively exposed portion of the metallic layer with a conductive material, and singulating the at least two chips. |
| US07968368B2 |
Method of manufacturing a field effect transistor having an oxide semiconductor
A method of manufacturing a field effect transistor, which has high alignment accuracy between a gate electrode and source and drain electrodes and can provide a transparent device at a low cost. Since a patterned light blocking film is formed on the rear side of a substrate and used as a photomask for forming a gate electrode pattern and a source and drain electrode pattern on the front side of the substrate, the number of photomasks is reduced, and self-alignment between the gate electrode and the source and drain electrodes is carried out, thereby improving the alignment accuracy of these electrodes. Thereby, a method of manufacturing a high-accuracy low-cost field effect transistor can be provided. |
| US07968365B2 |
Method for manufacturing solid-state imaging device
A method for manufacturing a solid-state imaging device in which a charge generator that detects an electromagnetic wave and generates signal charges is formed on a semiconductor substrate and a negative-charge accumulated layer having negative fixed charges is formed above a detection plane of the charge generator, the method includes the steps of: forming an oxygen-feed film capable of feeding oxygen on the detection plane of the charge generator; forming a metal film that covers the oxygen-feed film on the detection plane of the charge generator; and performing heat treatment for the metal film in an inactive atmosphere to thereby form an oxide of the metal film between the metal film and the oxygen-feed film on the detection plane of the charge generator, the oxide being to serve as the negative-charge accumulated layer. |
| US07968356B2 |
Light-emitting element with improved light extraction efficiency, light-emitting device including the same, and methods of fabricating light-emitting element and light-emitting device
Provided are a light-emitting element, a light-emitting device including the same, and methods of fabricating the light-emitting element and the light-emitting device. The light-emitting element includes a substrate on which a dome pattern is formed and a light-emitting structure conformally formed on the dome pattern. The light-emitting structure includes a first conductive layer of a first conductivity type, a light-emitting layer, and a second conductive layer of a second conductivity type sequentially stacked on the substrate. The light-emitting element also includes a first electrode formed on the first conductive layer and a second electrode formed on the second conductive layer. |
| US07968354B1 |
Methods for correlating backside and frontside defects detected on a specimen and classification of backside defects
Computer-implemented methods that include correlating a backside defect with a frontside defect detected on a specimen are provided. The defects are correlated if a portion of the backside defect on the backside of the specimen is opposite to a portion of the frontside defect on the frontside of the specimen. In particular, the defects are correlated if the portion of the backside defect is aligned with the portion of the frontside defect along an axis perpendicular to the frontside and the backside of the specimen. The method may also include altering a parameter of a process tool in response to the backside defect to reduce frontside defects on additional specimen processed in the process tool. Computer-implemented methods for analyzing data representing spatial characteristics of backside defects detected on a specimen to classify the backside defects are also provided. Analyzing the data may include spatial signature analysis of the data. |
| US07968350B2 |
Characterization of molecules
The invention involves obtaining signatures of species (including chemical, biological, or biochemical molecules) and/or signatures of interactions between species and using them to characterize species, characterize interactions, and/or identify species that could be useful in a variety of settings. Signatures can be obtained using aqueous multi-phase partitioning and can be used to predict molecular interactions for applications such as drug discovery. A plurality of aqueous multi-phase partitioning arrangements can define an overall system providing an information-intensive signature, maximizing precision and sensitivity. |
| US07968345B2 |
Permethylation of oligosaccharides
A solid-phase permethylation procedure is described. For example, solid-phase permethylation can be utilized to prepare permethylated linear and branched, neutral and sialylated oligosaccharides, which can be analyzed by MALDI-MS. |
| US07968344B2 |
Automated protein analyzer
A protein analysis kit is disclosed. The kit includes a sample cup for mixing a protein sample with a dye-binding solution and a filter holder for being positioned in the sample cup. The filter holder includes a filter media and a depending spout below the filter media that reaches bottom portions of the cup when the filter media is positioned above the cup. |
| US07968339B2 |
Method of inducing genome reorganization via intracellular activation of thermostable multifrequency DNA-cleaving enzyme
The present invention relates to a method for increasing genetic recombination frequency in a genomic DNA and a method for inducing genome rearrangement. Specifically, according to the present invention there are provided: the method for increasing genetic recombination frequency in a cell in which genetic recombination takes place at any sites in the genome, comprising causing a restriction enzyme to be expressed in the cell, inducing transient activation of the restriction enzyme, and then introducing 2 or more double strand cleavages into any genomic DNA of the cell, so as to increase the genetic recombination frequency; the method for inducing genome rearrangement through the use of the above method; and cells each prepared through the use of the above 2 methods. |
| US07968336B2 |
Methods of isolation, expansion and differentiation of fetal stem cells from chorionic villus, amniotic fluid, and placenta and therapeutic uses thereof
The present invention is directed to pluripotent fetal stem cells derived from chorionic villus, amniotic fluid, and placenta and the methods for isolating, expanding and differentiating these cells, and their therapeutic uses such as manipulating the fetal stem cells by gene transfection and other means for therapeutic applications. |
| US07968334B2 |
Expression of apoAI and variants thereof using spliceosome mediated RNA trans-splicing
Methods and compositions for generating novel nucleic acid molecules through targeted spliceosome mediated RNA trans-splicing that result in expression of a apoAI protein, an apoAI variant, the preferred embodiment referred to herein as the apoAI Milano variant, a pre-pro-apoAI or an analogue of apoAI. The methods and compositions include pre-trans-splicing molecules (PTMs) designed to interact with a target precursor messenger RNA molecule (target pre-mRNA) and mediate a trans-splicing reaction resulting in the generation of a novel chimeric RNA molecule (chimeric RNA) capable of encoding apoAI, the apoAI Milano variant, or an analogue of apoAI. The expression of this apoAI protein results in protection against vascular disorders resulting from plaque build up, i.e., atherosclerosis, strokes and heart attacks. |
| US07968333B2 |
Adenovirus vectors containing cell status-specific response elements and methods of use thereof
The present invention provides adenoviral vectors comprising cell status-specific transcriptional regulatory elements which confer cell status-specific transcriptional regulation on an adenoviral gene. A “cell status” is generally a reversible physiological and/or environmental state. The invention further provides compositions and host cells comprising the vectors, as well as methods of using the vectors. |
| US07968330B2 |
Culture observation equipment
The present application includes a culture chamber, an observation chamber having an optical system of observation to observe samples to be cultured in the culture chamber, and a movement stage provided at a boundary which separates the culture chamber and the observation chamber, functioning as a wall to maintain an environment of both of the chambers, bearing the samples, and moving the samples on a light axis of observation of the optical system of observation. Due to such an arrangement, a culture observation equipment which has good response and excellent environmental resistance can be achieved, preventing problems such as the overall size of the device became large, maintenance work was difficult, and device cost became expensive. |
| US07968327B2 |
Nucleic acid quantitation from tissue slides
This invention provides methods of quantitating nucleic acids from problematic samples, such as aged samples, formalin fixed samples, paraffin embedded samples, samples with aneuploid cells, and cells with fragmented nucleic acids. Methods include techniques to efficiently solublize the nucleic acids under non-denaturing conditions from preserved clinical samples without resort to organic extractions, to normalize cell counts regardless of aneuploidy, to access the fragmentation state of the nucleic acids, and to provide standard curves for degraded nucleic acid samples. |
| US07968325B2 |
Methods for the biosynthesis of polyesters
Coexpression of a polyhydroxyalkanoic acid synthase and a either a fatty acid:acyl-CoA transferase or an acyl-CoA synthetase in cells enables the biosynthesis of polyester materials. Plasmids, bacteria, materials, and methods for the preparation of polyesters are disclosed. |
| US07968317B2 |
Detection of 5T4 RNA in plasma and serum
This invention provides methods for detecting the presence of malignant or premalignant cells, or trophoblastic cells in a human wherein the malignant, premalignant or trophoblastic cells express 5T4. The methods of the invention detect 5T4 RNA in blood, blood plasma, serum, and other bodily fluids. The inventive methods are useful for detection, diagnosis, monitoring, treatment, or evaluation of neoplastic disease, and for the detection and evaluation of placental tissue in pregnant women. |
| US07968316B2 |
Method for the mass production of immunoglobulin Fc region deleted initial methionine residues
Disclosed is a method for the mass production of a monomeric or dimeric immunoglobulin Fc region, free of initial methionine residues, using a recombinant expression vector comprising a nucleotide sequence coding for a recombinant immunoglobulin Fc region comprising an immunoglobulin Fc region linked at the N-terminus thereof to an immunoglobulin Fc region via a peptide bond. |
| US07968311B2 |
Direct expression of peptides into culture media
Expression systems are disclosed for the direct expression of peptide products into the culture media where genetically engineered host cells are grown. High yield was achieved with novel vectors, a special selection of hosts, and/or fermentation processes which include careful control of cell growth rate, and use of an inducer during growth phase. Special vectors are provided which include control regions having multiple promoters linked operably with coding regions encoding a signal peptide upstream from a coding region encoding the peptide of interest. Multiple transcription cassettes are also used to increase yield. The production of amidated peptides using the expression systems is also disclosed. |
| US07968307B2 |
Serpentine transmembrane antigens expressed in human cancers and uses thereof
Described is a novel family of cell surface serpentine transmembrane antigens. Two of the proteins in this family are exclusively or predominantly expressed in the prostate, as well as in prostate cancer, and thus members of this family have been termed “STEAP” (Six Transmembrane Epithelial Antigens of the Prostate). Four particular human STEAPs are described and characterized herein. The prototype member of the STEAP family, STEAP-1, appears to be a type IIIa membrane protein expressed predominantly in prostate cells in normal human tissues. Structurally, STEAP-1 is a 339 amino acid protein characterized by a molecular topology of six transmembrane domains and intracellular N- and C-termini, suggesting that it folds in a “serpentine” manner into three extracellular and two intracellular loops. STEAP-1 protein expression is maintained at high levels across various stages of prostate cancer. Moreover, STEAP-1 is highly over-expressed in certain other human cancers. |
| US07968304B2 |
Determining and reducing immunoresistance to a botulinum toxin therapy using botulinum toxin B peptides
The present invention provides BoNT/B peptides, BoNT/B peptide compositions, tolerogizing compositions, immune response inducing compositions, as well as methods of determining immunoresistance to botulinum toxin therapy in an individual, methods of treating immunoresistance to botulinum toxin therapy in an individual, methods of reducing anti-botulinum toxin antibodies in an individual and methods of inducing a BoNT/B immune response an individual. |