Document Document Title
US07873216B2 Distortion correction of a scanned image
Disclosed are embodiments of systems and methods for eliminating or reducing the distortion in a scanned image. In embodiments, the image is segmented into foreground and background pixels. Foreground pixels may be grouped into “letters.” Using index-based searching, “letters” may be grouped into “words” and “words” may be grouped into baselines. One or more dominant baselines may be selected and the characteristics of the dominant baseline or baselines may be used to unwarp the image.
US07873212B2 Compression of images for computer graphics
A method for encoding an image having color components of each image pixel represented by a value of a high dynamic range, the method comprising: decomposing the image into a plurality of image blocks; separating, from the high dynamic range value of each pixel, color information and intensity information of the pixels in said image blocks; and compressing the color information of the pixels in said image blocks and the intensity information of the pixels in said image blocks independently of each other to provide compressed image data.
US07873209B2 Segment-discriminating minimum classification error pattern recognition
Pattern model parameters are updated using update equations based on competing patterns that are identical to a reference pattern except for one segment at a time that is replaced with a competing segment. This allows pattern recognition parameters to be tuned one segment at a time, rather than have to try to model distinguishing features of the correct pattern model as a whole, according to an illustrative embodiment. A reference pattern and competing patterns are divided into pattern segments. A set of training patterns are generated by replacing one of the pattern segments in the reference pattern with a corresponding competing pattern segment. For each of the training patterns, a pattern recognition model is applied to evaluate a relative degree of correspondence of the reference pattern with the pattern signal compared to a degree of correspondence of the training patterns with the pattern signal.
US07873206B2 Registration detection system
A registration detection system performing registration-detecting each substrate in a lot without lowering an original throughput of a lithography system and maintaining high accuracy usable for the correction of an exposure process. Therefore, registration detection 5 system includes: the first detection apparatus installed on a pathway to a collection in a transport container of substrates taken out of transport container, after passing at least exposure process and a development process, registration-detects substrates after passing development process, according to stipulated criteria, and outputs results of registration detection for use in correction of exposure process; the second detection apparatus outside 10 the pathway, and registration-detecting substrate when substrate after passing the first detection apparatus and collected in the transport container is taken out of transport container again; and a correction unit comparing detection results by the first and the second detection apparatuses to correct registration detection criteria in the first detection apparatus.
US07873205B2 Apparatus and method for classifying defects using multiple classification modules
A classification model optimum for realization of a defect classification request by a user is not known by the user. Then, the user sets a classification model which is not necessarily suitable and makes classification, resulting in degradation in classification performance. Therefore, the present invention automatically generates plural potential classification models and combines class likelihoods calculated from the plural classification models to classify. To combine, an index about the adequacy of each model, in other words, an index indicating a reliable level of likelihood calculated from the each potential classification model, is also calculated. Considering the calculated result, the class likelihoods calculated from the plural classification models are combined to execute classification.
US07873204B2 Method for detecting lithographically significant defects on reticles
A method for identifying lithographically significant defects. A photomask is illuminated to produce images that experience different parameters of the reticle as imaged by an inspection tool. Example parameters include a transmission intensity image and a reflection intensity image. The images are processed together to recover a band limited mask pattern associated with the photomask. A model of an exposure lithography system for chip fabrication is adapted to accommodate the band limited mask pattern as an input which is input into the model to obtain an aerial image of the mask pattern that is processed with a photoresist model yielding a resist-modeled image. The resist-modeled image is used to determine if the photomask has lithographically significant defects.
US07873203B2 Method of design analysis of existing integrated circuits
The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.
US07873202B2 Method and apparatus for reviewing defects of semiconductor device
An apparatus for reviewing defects of a semiconductor device is provided to review a lot of defects in a short period of time thereby to improve the efficiency of defect review. A method for reviewing defects of a semiconductor device includes obtaining an image including a defect on the semiconductor device detected by a detection device by use of a scanning electron microscope at a first magnification, making a reference image from the image including the defect obtained at the first magnification, detecting the defect by comparing the image including the defect obtained at the first magnification to the reference image made from the image including the defect at the first magnification, and taking an image of the detected defect at a second magnification that is larger than the first magnification.
US07873200B1 Systems and methods for remote deposit of checks
Remote deposit of checks can be facilitated by a financial institution. A customer's general purpose computer and image capture device may be leveraged to capture an image of a check and deliver the image to financial institution electronics. Additional data for the transaction may be collected as necessary. The transaction can be automatically accomplished utilizing the images and data thus acquired.
US07873193B2 Serial section analysis for computer-controlled microscopic imaging
Automated projection of serial section images in microscopic imaging systems. A computer-controlled microscope that is connected electrically to a controller that has a display device. A batch of serial section slides includes a series of serial section slides, each of which has a microscope slide, a sample, and an interesting area. If one of the images is misregistered, then the images may be transformed.
US07873191B2 Capacitive array
A capacitive array comprising at least two capacitive entities, comprising a substrate layer. The substrate layer comprises a comb comprising at least four substantially identical teeth, and, for each capacitive entity, a set of fingers comprising one or more interlinked fingers. At least two sets of fingers comprise a different number of fingers, each finger being nested between two teeth of the comb and being substantially identical to the other fingers. The fingers of each set of fingers are substantially distributed symmetrically relative to a median axis of the comb. The comb and the fingers are integrated in a single block.
US07873189B2 Face recognition by dividing an image and evaluating a similarity vector with a support vector machine
A face recognition and apparatus are provided. According to the method, an SVM classifier is created through machine learning on the basis of a degree of similarity of a divided facial image, and a facial image to be authenticated is normalized to a predetermined size using a center between two eyes. The normalized image is divided into more than one image in horizontal and vertical directions, respectively. Next, predetermined characteristic vectors from the divided images are extracted and a similarity vector based on a degree of similarity with respect to a registered characteristic vector is created. The similarity vector is input to the SVM classifier, so that authentication is performed.
US07873188B2 Device for measuring visibility distance
The invention relates to a device for determining visibility distance in a landscape. The device comprises a camera for taking an image of said landscape; means for storing said image; means for associating each pixel of the image with information representative of the distance between the camera and the point in the landscape corresponding to said pixel, thereby obtaining a map of distances; means for processing the image to detect whether a pixel of the image presents contrast greater than a predetermined value relative to at least some adjacent pixels; means for applying said processing for detecting contrast successively to the pixels of the image beginning from the pixel corresponding to the greatest distance and continuing to the first pixel found to satisfy the contrast condition; and means for associating said pixel with distance information from said map of distances.
US07873186B2 Target-image detecting apparatus and method of controlling same
In the detection of face images, features for the purpose of detecting face images can be added on to supplement existing features. A face detecting apparatus includes a ROM, which stores data representing features for detecting face images having inclination angles at increments of 90° in the image of a subject. The face detecting apparatus is further provided with a connection terminal to which a flash ROM can be removably connected. The flash ROM stores data representing features for detecting face images having inclination angles finer than those of the images of the faces having inclination angles capable of being detected by the data representing the features that have been stored in the ROM. Face images can be detected more accurately by connecting the flash ROM to the face detecting apparatus.
US07873185B2 Method for detection and tracking of deformable objects
A method for detecting and tracking a deformable object having a sequentially changing behavior, comprising: developing a temporal statistical shape model of the oscillatory behavior of the embedding function representing the object from prior motion; and then applying the model against future, sequential motion of the object in the presence of unwanted phenomena by maximizing the probability that the developed statistical shape model matches the sequential motion of the object in the presence of unwanted phenomena.
US07873183B2 Embedding and detecting watermarks based on embedded positions in document layout
A watermark embedding method for embedding a secret message sequence in a document. The techniques include obtaining layout information of the document, extracting a digest of the document by using a Hash function, calculating embedded positions where the secret message sequence is embedded in the document, and dispersedly hiding the secret message sequence in each of the calculated embedded positions by altering the layout of the document. Also provided is a watermark embedding apparatus, a corresponding watermark detecting method and apparatus, and a method and system for detecting document integrity. The integrity of documents in various forms can be detected, and secret information to be hidden can be embedded therein and extracted therefrom. The techniques described are not limited to the document either in soft copy or in hard copy and have good robustness.
US07873173B2 Active vibratory noise control apparatus
A cosine wave over one period is stored as waveform data in a memory, and address shift values based on a phase lag in transfer characteristics from a speaker to a microphone are stored in a memory. An address shift value is read from the memory by referring to the frequency, and waveform data are read from the memory at addresses that are produced by shifting the addresses from which the reference cosine wave signal and the reference sine wave signal are read, by the address shift value. The read waveform data are used as a first reference signal and a second reference signal, which are applied to adaptive notch filters, to suppress vibratory noise.
US07873167B2 System and method for effectively pre-distributing key for distributed sensor network
A system for effectively pre-distributing keys for a distributed sensor network is disclosed, The system includes: a plurality of sensor nodes, each of which has a sensing function, a calculation function, and a wireless communication function; and a base station which is connected to the sensor nodes over a wireless network, receives data from the sensor nodes, acts as a data central station, and distributes keys for inter-sensornode security authentication to the sensor nodes. A key management unit contained in the base station, generates a set of the sensor nodes used for security authentication between the sensor nodes, decomposes the set of the sensor nodes into a plurality of matrices, distributes the matrices to the sensor nodes, and allows the sensor nodes to search for a common private key required for the security authentication using the received matrices. Therefore, the system can always search for a common private key between the sensor nodes.
US07873165B2 Tactical radio with integrated satcom capability
A multi-band radio having seamless satellite communication capability is provided. The radio includes: a user interface for controlling operations of the radio; an encryption module; a LOS wireless transceiver for transmitting encrypted data at a frequency in the radio frequency spectrum; a BLOS wireless transceiver for transmitting encrypted data at a frequency in the microwave frequency spectrum; and a router for routing the encrypted data to at least one of the LOS transceiver and the BLOS transceiver.
US07873161B2 Small hardware implementation of the subbyte function of rijndael
A small hardware implementation is provided for the Advanced Encryption Standard SubByte function that implements the affine transform and inverse transform in a single Affine-All transform using a multiplicative inverse ROM. The logic is greatly reduced and the maximum path delay is reduced compared to a multiplexor implementation and is slightly greater than a ROM implementation.
US07873156B1 Systems and methods for analyzing contact center interactions
Systems and methods for analyzing contact center interactions are provided. In this regard, a representative method includes: receiving information corresponding to an interaction between a contact center agent and a customer; and assessing quality of the interaction based, at least in part, on information corresponding to at least one of: a history of the customer; and an event corresponding to the customer and occurring subsequent to the interaction.
US07873155B2 Method and device for estimating work skills, and computer product
In a work skill estimating device, an item information receiving unit receives, as item information, duration information of each dealing sequence in a customer call. A dealing duration estimating unit estimates a dealing duration of an item based on the item information received. A work skill estimating unit estimates an operator's work skill based on the dealing duration estimated. A skill map creating unit creates a skill map to comprehend the operator's work skill estimated.
US07873153B2 Priority task list
Tasks for managing a network can be displayed in a priority task list. Tasks can be selected for inclusion based on rules, such as rules relating to best practices. The rules can be applied against network status, usage status, user profiles, and the like. Upon selection of a user interface element in the priority task list, an appropriate user interface for accomplishing the task can be displayed.
US07873150B2 Telephone call dialing
A communications device such as a mobile telephone (1) responds to the input of a dialed number for a call destination (2) by generating and outputting a request message transmitted to a control centre (7) via a telecommunications system (3). The device receives a response message from the control centre containing routing data and credit data representing remaining credit within an account limit of the subscriber. An outgoing communications session is then initiated using the routing data which may for example enable a dialed telephone number to be modified to achieve optimum routing to the call destination via one or more preferred networks. The device also includes a credit control application (83) for limiting the duration of the communication in accordance with the credit data. Mobile telephones may thereby be used with a prepayment subscription account even during roaming operation in which the mobile telephone registers with a network other than the subscriber's home network.
US07873149B2 Systems and methods for gathering information
A method for retrieving information may include receiving a telephone call from a caller and identifying a telephone number from which the telephone call was made. The method may also include retrieving information from a database based on the identified telephone number. The method may further include providing an audible message to the caller to verify whether the retrieved information is correct.
US07873147B2 Radiostereometric calibration cage
A calibration cage for use in Roentgen Stereophotogrammetric Analysis (RSA), comprising a biplanar configuration of two compartments, each with a fiducial plate at the bottom and a control plate at the top and parallel thereto, the fiducial and control plates of one compartment being oriented at approximately 90° to fiducial and control plates of the other compartment such that a region of interest is positioned on one side of the fiducial and control plates of both compartments.
US07873146B2 Multi X-ray generator and multi X-ray imaging apparatus
A compact apparatus can form multi X-ray beams with good controllability. Electron beams (e) emitted from electron emission elements (15) of a multi electron beam generating unit (12) receive the lens effect of a lens electrode (19). The resultant electron beams are accelerated to the final potential level by portions of a transmission-type target portion (13) of an anode electrode (20). The multi X-ray beams (x) generated by the transmission-type target portion (13) pass through an X-ray shielding plate (23) and X-ray extraction portions (24) in a vacuum chamber and are extracted from the X-ray extraction windows (27) of a wall portion (25) into the atmosphere.
US07873145B2 Wireless digital image detector
A digital detector of a digital imaging system is provided. In one embodiment, the digital detector includes a flat-panel detector having a detector array for converting X-ray radiation into image data. The digital detector may also include a plurality of antennas, and the digital detector may be configured to transmit the image data via one or more antennas of the plurality of antennas. Additional systems, methods, and devices are also disclosed.
US07873144B2 Pulsed x-ray for continuous detector correction
A radiographic imaging apparatus (10) comprises a primary radiation source (14) which projects a beam of radiation into an examination region (16). A detector (18) converts detected radiation passing through the examination region (16) into electrical detector signals representative of the detected radiation. The detector (18) has at least one temporally changing characteristic such as an offset B(t) or gain A(t). A grid pulse means (64) turns the primary radiation source (14) ON and OFF at a rate between 1000 and 5000 pulses per second, such that at least the offset B(t) is re-measured between 1000 and 5000 times per second and corrected a plurality of times during generation of the detector signals. The gain A(t) is measured by pulsing a second pulsed source (86, 100, 138) of a constant intensity (XRef) with a second pulse means (88). The gain A(t) is re-measured and corrected a plurality of times per second during generation of the detector signals.
US07873142B2 Distortion correction method for linear scanning X-ray system
Imaging apparatus comprises a radiation source arranged to generate a divergent imaging beam and an associated radiation detector mounted on a C-arm which can rotate. A first drive is arranged to move the radiation source and the detector relative to a subject in a scanning direction to generate output signals from the detector, thereby performing a scan generating image data containing distortion in a direction transverse to the scanning direction. A second drive is arranged to rotate the C-arm, to change the orientation of the radiation source in a direction transverse to the scanning direction incrementally between repeated scans, thereby to generate a plurality of sets of image data. A processor, which can be a PC or a dedicated processor, is provided for processing each set of image data to obtain equivalent parallel imaging beam data therefrom, corresponding to a given angle in the divergent imaging beam, and for combining a plurality of said equivalent parallel imaging beam data to generate a synthesized parallel imaging beam image. The apparatus includes a display for generating a visual display of the synthesized parallel imaging beam image. The resulting synthesized image has the distortion removed and measurements can be made from the image. The invention extends to a method carried out with the apparatus.
US07873140B2 Shift register
A shift register is disclosed. The shift register includes a plurality of stages for sequentially outputting scan pulses, wherein each of the stages includes a scan pulse output unit controlled according to voltage states of a set node and reset node for outputting a corresponding one of the scan pulses and supplying the corresponding scan pulse to a corresponding gate line, a carry pulse output unit controlled according to the voltage states of the set node and reset node for outputting a carry pulse and supplying it to an upstream one of the stages and a downstream one of the stages, a first node controller for controlling the voltage states of the set node and reset node according to a carry pulse from the upstream stage, a carry pulse from the downstream stage and a first control signal externally supplied thereto, an all-drive signal output unit controlled according to voltage states of a control node and reset control node for outputting an all-drive signal and supplying it to the corresponding gate line, and a second node controller for controlling the voltage states of the control node and reset control node according to the voltage state of the set node, the voltage state of the reset node, and a start pulse and second control signal externally supplied thereto.
US07873138B2 Structure and method for bolting neutron reflector
A neutron reflector bolt fastening structure is disclosed in which even upon relaxation in the fastening forces thereof being generated in tie rods for divided stage portions as a result of neutron irradiation, it is possible to press the neutron reflector firmly against a core vessel. The neutron reflector bolt fastening structure includes: a neutron reflector which includes of a plurality of divided stage portions and situated in a core vessel in a reactor vessel; a plurality of tie rods for fixing the neutron reflector to the core vessel; and a plurality of bolts for exclusively fixing the lowermost stage portion of the plurality of stage portions of the neutron reflector to the core vessel.
US07873136B2 Injection system and associated operating method
A feeding system for an absorber liquid containing a neutron poison, in particular for a quick shut-down of a nuclear reactor, has a storage container for the absorber liquid and is configured for high operational reliability with simple construction. In particular, a chemical decomposition of the absorber liquid or corrosion of the container wall of the storage container is to be excluded. For this purpose, the storage container is connected to a pressure container via an overflow line, wherein the pressure container is filled with a motive fluid.
US07873134B2 Clock generation system
Disclosed herein are clock generator systems comprising first and second stage PLLs thereby allowing for both lower PLL bandwidth filtering and higher bandwidth response, in accordance with some embodiments. Other systems may be disclosed and/or described herein.
US07873133B2 Recovery of client clock without jitter
The present invention provides a system, apparatus and method for recovering a client signal clock. The present invention is able to more effectively remove jitter within a clock signal by providing a phase shifting element in the feedback of a PLL system to compensate for sudden changes in an input reference clock. The PLL system provides flexible clock recovery so that it can accommodate various payload types because it extracts a client clock signal independent of a corresponding justification count number.
US07873132B2 Clock recovery
A method and apparatus of recovering a clock signal from an input data signal consistent with certain embodiments, where the clock signal has a clock cycle equal to one data bit period, involves identifying an earliest transition time position in a sequence of data signal transitions; identifying a latest transition time position in the sequence of data signal transitions; calculating an approximate average transition time of the sequence of clock transitions; calculating a sampling time for sampling data in the input data signal as the approximate average transition time plus one half clock cycle; and adjusting a sampling clock time to approximate the sampling time. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.
US07873130B2 Frequency comparator utilizing enveloping-event detection via symbolic dynamics of fixed or modulated waveforms
Systems, algorithms, circuits, and methods for pattern detection of signature events in signal dynamics defined by instantaneous states of applied square-wave signals. Selected patterns may be recognized individually or in equivalence classes, and detection may be implemented via state or transition analysis. Varieties of conditions may be detected in parallel, including phase, ambiguity states, and frequency comparison. One embodiment realizes a real-time frequency comparator for asynchronous square-wave signals. Realizations detect various classes of symmetry conditions unique to enveloping events occurring for these classes of square-wave signal pairs. This approach provides feedback-free implementations operating over an extremely wide frequency range and does not require signals of quadrature form. A typical logic circuit implementation involves two to four flip-flops, or two-stage two-bit shift registers, and modest combinational logic. The resulting system can be readily implemented as a utility integrated circuit of modest scale or as a small-scale “IP core” within larger system-on-a-chip (SoIC) devices.
US07873129B2 PHY clock synchronization in a BPL network
A method and a communication modem for broadband communication over power transmission lines. The modem includes a coarse level synchronization mapping unit which maintains a regularly updated coarse level clock synchronization map of neighboring communication units with which it is likely to exchange communications; and a second level synchronization unit which utilizes session handshakes and session data capacity to increase the synchronization level with a neighboring communication unit to allow a communication session to be held at a higher modulation level than the coarse level synchronization is able to support.
US07873128B2 Method and system for equalization in a communications system
Aspects for equalization in a communications system are described. The aspects include utilizing a block code based error correction scheme in a modulation system of the communication system, and removing cursor inter-symbol interference within an error correction code word to make code word decision with minimum error power-based criteria in the block code based error correction scheme.
US07873124B2 Method for digital wireless communications
In a multivalue modulation type with one pilot symbol inserted for every 3 or more symbols, signal points of each one symbol immediately before and after a pilot symbol are modulated using a modulation type different from that for pilot symbols. In this way, it is possible to suppress deterioration of the accuracy in estimating the reference phase and amount of frequency offset by pilot symbols and improve the bit error rate characteristic in the signal to noise ratio in quasi-coherent detection with symbols whose symbol synchronization is not completely established.
US07873122B2 Methods and devices for wireless chip-to-chip communications
Wireless chip-to-chip communications are methods and devices are disclosed. In an example, a wireless chip-to-chip communication device includes a plurality of chips, each of the plurality of chips having at least one antenna and formed on a multi-layered structure. The multi-layered structure includes first and second absorption layers. The first and second absorption layers are configured to enclose a propagation medium having a given dielectric constant. The plurality of chips are configured to wirelessly communicate with each other via the respective antennas in accordance with a given wireless communication protocol via a direct propagation path within the propagation medium.
US07873120B2 Forward error correction coding for AM 9kHz and 10kHz in-band on-channel digital audio broadcasting systems
A method of broadcasting an AM compatible digital audio broadcasting signal includes: producing an analog modulated carrier signal centrally positioned in a radio channel, wherein the analog modulated carrier signal is modulated by an analog signal, producing a plurality of digitally modulated subcarrier signals in the radio channel, wherein the digitally modulated subcarrier signals are modulated using complementary pattern-mapped trellis code modulation (CPTCM) including a code mapped to overlapping partitions including an upper main partition, a lower main partition, an upper backup partition and a lower backup partition, and a non-overlapping tertiary partition, and transmitting the analog modulated carrier signal and the plurality of digitally modulated subcarrier signals. Transmitters that broadcast the signal and receivers that receive the signal, and the reception method are also included.
US07873118B2 Apparatus and method for controlling peak to average power ratio (PAPR)
An apparatus for controlling PAPR in an OFDM communication system and method thereof are disclosed, by which implementation is simplified and enhanced PAPR characteristics are provided. The present application includes outputting GNb data symbols by oversampling Nb parallel data symbols, spreading the oversampled data symbols using DFT, and mapping the spread signal to subcarriers.
US07873117B2 Wireless communication base station apparatus and wireless communication method in multicarrier communication
A base station apparatus wherein the interference suppression symbol combination can be performed in a case of using the repetition technique in a multicarrier communication. In a base station (100), a repetition part (103) repeats or copies each of data symbols received from a modulating part (102) to create a plurality of same data symbols. A phase rotating part (106) imparts, in accordance with a phase rotation angle set by a setting part (107), phase rotations to the pilot and data symbols received from a multiplexing part (105). At this moment, the phase rotating part (106) imparts the phase rotations of the same angle to the pilot and data symbols assigned to the same subcarrier. Further, the phase rotating part (106) causes the phase rotation difference between the same data symbols in a cell to be different from the phase rotation difference between the same symbols in an adjacent cell.
US07873115B2 Selectable-tap equalizer
A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.
US07873105B2 Hardware implementation of optimized single inverse quantization engine for a plurality of standards
Presented herein are optimized single inverse quantization engines for a plurality of standards. In one embodiment, there is presented a system for inverse quantizing quantized frequency coefficients. The system comprises an inverse quantizer for inverse quantizing video data encoded in accordance with a first encoding standard and for inverse quantizing video data encoded in accordance with a second encoding standard. In another embodiment, there is presented a decoder for decoding video data. The decoder comprises an inverse quantizer operable to inverse quantize video data encoded in accordance with a first encoding standard and for inverse quantizing video data encoded in accordance with a second encoding standard.
US07873098B2 Robust multicode detector for HSDPA
Detecting a symbol of interest comprises despreading a received signal to obtain despread values corresponding to the symbol of interest and to one or more interfering symbols, combining the despread values to generate combined values for the symbol of interest and the interfering symbols, computing spreading waveform correlations between the spreading waveform for the symbol of interest and the spreading waveforms for the interfering symbols, computing interference rejection terms representing the interference present in the combined value for the symbol of interest attributable to the interfering symbols based on the spreading waveform correlations, and generating an estimate of the symbol of interest by combining the combined values with the interference rejection terms. The interference rejection terms are computed by scaling the spreading waveform correlations by corresponding signal powers and compensating the estimates for noise. This provides a robust interference model that avoids numerical problems associated with conventional joint detection.
US07873089B2 Distributed feedback semiconductor laser based on reconstruction-equivalent-chirp technology and the manufacture method of the same
Using sampled Bragg grating structure, the present invention proposes a distributed feedback (DFB) semiconductor laser based on reconstruction-equivalent-chirp technology. Namely, the Bragg grating in the said DFB semiconductor laser cavity is a sampled Bragg grating, in which there is an equivalent grating corresponding to the original ordinary DFB grating as feedback for lasing. The laser wavelength of the said semiconductor laser located within the operation bandwidth of the said equivalent grating. The said equivalent grating is designed and fabricated using REC technology and has equivalent chirps, one equivalent phase shift or multiple equivalent phase shifts. The said sampled Bragg grating has multiple ghost gratings and the wavelength spacing between neighboring ghost gratings is inversely proportional to the sampling period and the effective refractive index of the said semiconductor laser. Only one ghost grating except the ghost grating related to the center wavelength is selected to be as equivalent grating. In semiconductor laser fields, only based on sub-micron precision, the present invention provides a method to realize various complex equivalent chirps and equivalent phase shifts in the resonant cavity of the said semiconductor laser. These equivalent chirps and equivalent phase shifts have the same functions with the corresponding true chirps and true phase shifts, so as to avoid the processes of fabrication of grating structure with complex true chirps and true phase shifts.
US07873088B2 Group III nitride semiconductor element and epitaxial wafer
A primary surface 23a of a supporting base 23 of a light-emitting diode 21a tilts by an off-angle of 10 degrees or more and less than 80 degrees from the c-plane. A semiconductor stack 25a includes an active layer having an emission peak in a wavelength range from 400 nm to 550 nm. The tilt angle “A” between the (0001) plane (the reference plane SR3 shown in FIG. 5) of the GaN supporting base and the (0001) plane of a buffer layer 33a is 0.05 degree or more and 2 degrees or less. The tilt angle “B” between the (0001) plane of the GaN supporting base (the reference plane SR4 shown in FIG. 5) and the (0001) plane of a well layer 37a is 0.05 degree or more and 2 degrees or less. The tilt angles “A” and “B” are formed in respective directions opposite to each other with reference to the c-plane of the GaN supporting base.
US07873084B2 Arrangement and method for preventing the depolarization of linear-polarized light during the transmission of light through crystals
A process and a device is described to avoid the depolarization of linear-polarized light during the transmission of light through crystals exhibiting a {111} or {100} crystal plane, respectively, and a <100> or <111> crystal axis, respectively. The device is characterized in that the linear-polarized light meets the surface of the crystals in an angle of 45-75°, whereby the surface is formed by the {111} or the {100} plane. The crystal is arranged in such a way that upon entering the crystal, the light spreads along the <100> or <111> crystal axis, respectively, as parallel as possible, and/or that the device comprises a unit for temperature equalization to avoid a thermal gradient in the crystal. Preferably the device is used in DUV lithography, in particular in steppers and excimer lasers, as well as for the production of integrated circuits, computer chips as well as electronic devices such as computers, and other devices that comprise chip-type integrated circuits, as well as for flat screens.
US07873083B2 System, method, and apparatus to provide laser beams of two or more wavelengths
A system, apparatus, and method may provide laser beams of two or more wavelengths from diode pumped solid-state laser sources (220, 222, 224). The beam paths of these laser beams with different wavelengths, which are generated by the laser sources (220, 222, 224), may be aligned along a common optical axis 280 by an optical configuration, to treat at least one target area. Frequency-doubled laser beams, output from a plurality of diode pumped solid state laser cavities, may be passed through fold mirrors (M2, M5, M8), and combined on a common optical axis 280, using one or more combiner mirrors (M10, M11, M12), to unify the beam paths. Selected laser beams may be delivered to a target using one or more delivery systems.
US07873078B2 Screen multiplexing
There is provided a screen multiplexor for processing graphical display data and an associated distribution method. A plurality of graphical display data streams is received at the multiplexor, processed and directed to one or more network-connected display devices. The network is a general purpose data network and may be wireless. The directed data streams can be spatially multiplexed, temporally multiplexed, and/or multiplexed in such a way that data from one stream is overlaid on data from another stream. The distribution method and screen multiplexor thus allow a flexible relationship between the number of screens and the sources of the information to be displayed thereon.
US07873076B2 Mapping of block-encoded data formats onto a bit/byte synchronous transport medium
A fiber channel (FC) signal representing block encoded data is applied to a block decoder, which removes the block encoding from the data. The data is then applied to a simplified data link (SDL) protocol encoder, which maps the data into an SDL protocol packet for transmission over a SONET (Synchronous Optical Network)-based transport medium.
US07873071B2 Multiple level security adapter
In exemplary embodiments, data with a format compatible with a first protocol standard is received on behalf of a first application. When the format of the data is not compatible with a second protocol standard, the format of the data is automatically transformed to a format that is compatible with the second protocol standard. The data is transmitted to a second application service using the second protocol standard. The data may be received from the second application. When the format of the data is not compatible with a third protocol standard, the format of the data is automatically transformed to a format that is compatible with the third protocol standard. The data is transmitted on behalf of a third application using the third protocol standard. The first and third applications may be in first and second protected enclaves. The second application may include a security gateway service.
US07873070B2 Determining a number of automatic request retransmissions based on block size
The present invention provides a method of wireless telecommunication of a message having a block size. The method includes determining a number of retransmissions of the message based upon the block size.
US07873069B2 Methods and apparatus for controlling audio characteristics of networked voice communications devices
Methods and apparatus for controlling the audio characteristics of a networked voice communications device (NVCD) are presented. One method presented includes receiving a settings file, extracting at least one audio control parameter from the settings file, deriving audio processing parameters based upon a value selected from the at least one audio control parameter, and controlling the audio characteristics of the networked voice communications device using the audio processing parameters and the at least one audio control parameter. A method for providing audio parameters to an NVCD is also presented which includes establishing a settings file, which includes at least one audio control parameter, receiving a request to send the settings file, and sending the settings file over a network to the networked voice communications device.
US07873066B2 Streaming direct inter-thread communication buffer packets that support hardware controlled arbitrary vector operand alignment in a densely threaded network on a chip
A computer-implemented method, system and computer program product for arbitrarily aligning vector operands, which are transmitted in inter-thread communication buffer packets within a highly threaded Network On a Chip (NOC) processor, are presented. A set of multiplexers in a node in the NOC realigns and extracts data word aggregations from an incoming compressed inter-thread communication buffer packet. The extracted data word aggregations are used as operands by an execution unit within the node.
US07873063B2 Cell management method and apparatus
In a cell management method and apparatus which can prevent a call loss generated in association with an increase of cell usage rate independent of a protection frequency bandwidth, cell usage rates of operating cells (at frequency Fo) are acquired. Narrower nonoperating cells (at frequency Fo) of the operating cell in which the cell usage rate indicates a high-load state are rendered an addition candidate and the operating cell is rendered a deletion candidate. A broader nonoperating cell (at frequency Fo) of the operating cell in which the cell usage rate indicates a low-load state is rendered an addition candidate, and the operating cell and other narrower operating cells belonging to the nonoperating cell are rendered deletion candidate. From among the nonoperating cells that are the addition candidate and the operating cells that are the deletion candidates, a nonoperating cell(s) to be switched over to an operating cell(s) and an operating cell(s) to be switched over to a nonoperating cell(s) is determined.
US07873061B2 System and method for aggregation and queuing in a wireless network
A technique for improved throughput at an access point (AP) involves when frames are received for transmission by the AP, queuing the frames for a particular station. A system constructed according to the technique may include an aggregation and queuing layer. Station queues may be processed by the aggregation and queuing layer before being given to radio hardware for transmission. In an illustrative embodiment, when frames are received by the aggregation and queuing layer, the packet will be assigned a target delivery time (TDT) and an acceptable delivery time (ADT). The TDT is the “ideal” time to transmit a frame, based on its jitter and throughput requirements. Frames are mapped on to a time axis for transmission by TDT. In an illustrative embodiment, each frame is mapped by priority, so that there are separate maps for voice, video, best effort, and background frames. There will be gaps between frames for transmission that can be used for aggregation.
US07873060B2 Accelerating data communication using tunnels
Methods and systems are provided for increasing application performance and accelerating data communications in a WAN environment. According to one embodiment, a method is provided for securely accelerating network traffic. One or more tunnels are established between a first wide area network (WAN) acceleration device, interposed between a public network and a first local area network (LAN), and a second WAN acceleration device, interposed between a second LAN and the public network. Thereafter, network traffic exchanged between the first LAN and the second LAN is securely accelerated by (i) multiplexing multiple data communication sessions between the first LAN and the second LAN onto the one or more tunnels, (ii) performing one or more of application acceleration, transport acceleration and network acceleration on the data communication sessions and (iii) performing one or more security functions on the data communication sessions.
US07873056B2 Switch device, switching method and switch control program
A switch device is composed of a switch portion 1-1, input side port mapping blocks 1-4-1 to 1-4-P, output side port mapping blocks 1-5-1 to 1-5-P, and a virtualization controller (central controller) 1-0 so that the switch device can be logically divided into a plurality of switches each having a capacity smaller than a physical switch capacity or the divided switches can be logically integrated. The switch portion has a plurality of first input ports and a plurality of first output ports. Each of the input side port mapping blocks has a plurality of second input ports and inputs the signals input to the plurality of second input ports to the first input ports of the switch portion. Each of the output side port mapping blocks has a plurality of second output ports and outputs the signals output to the first output ports of the switch portion from the plurality of second output ports.
US07873055B2 Scheduling user transmissions of mobile stations on a reverse link of a spread spectrum cellular system
The present invention provides a method and an apparatus for wireless communication between a base station and at least two mobile stations in a cellular system. The method comprises sending on a forward link at least one of a first and a second command to the at least two mobile stations that the base station is serving on a reverse link. The method further comprises controlling a transmission in at least one of a first and a second transmission mode of at least one mobile station among the at least two mobile stations on the reverse link based on the at least one of the first and second commands. Each of at least two mobile stations may determine a change of transmission mode between an orthogonal or a non-orthogonal transmission mode on a reverse link based on a message on a forward link. A scheduler at a serving base station may match scheduling or transmission resources to the transmissions on the reverse link. The mobile stations being served may use orthogonal and non-orthogonal transmission modes for the transmissions in a non-overlapping fashion in any combination of time, frequency and spatial domains. By selectively assigning a set of mobile stations to the orthogonal or non-orthogonal modes of transmission, the serving base station may enable fairness across the mobile stations.
US07873052B2 System and method for controlling process end-point utilizing legacy end-point system
Embodiments in accordance with the present invention allow a second end-point determination (EPD) system to actively control the end-pointing of a semiconductor process chamber, by leveraging a legacy EPD system that is already integrated with the chamber. In one embodiment, the second EPD system controls a shutter that regulates the amount of light transmitted between a plasma light source and an optical emission spectroscopy (OES) sensor of the legacy OES EPD system. In this embodiment, the legacy OES EPD system is pre-configured to call end-point when an artificial end-point condition occurs, i.e. the intensity of light falls below a pre-set threshold. When the second EPD system determines an actual end-point condition has been reached, it closes the shutter which, causes the light intensity being read by the OES sensor to fall below the pre-set threshold. This in turn triggers an end-point command to the chamber from the legacy OES EPD system.
US07873046B1 Detecting anomalous network activity through transformation of terrain
Detecting anomalous network activity through transformation of a terrain is disclosed. A set of network properties is mapped into a multidimensional terrain. The terrain is transformed into an observation domain in which data events of interest are amplified relative to other data comprising the terrain. The transformed terrain is evaluated for anomalous network activity.
US07873029B2 System and method of providing multimedia communication services
A system and method of providing multimedia communication services is disclosed. In a particular embodiment, the method includes receiving contextual information including a subscriber identification associated with a wireline communication device at an intelligent service switch (ISS) of an integrated wireline-wireless (IWW) network from a network edge device, where the network edge device has detected a service request at the wireline communication device. The method also includes determining at least one multimedia communication service based on the contextual information and at least one service filter associated with the subscriber identification.
US07873027B2 Database management system and method of using it to transmit packets
A forwarding table, in a network device such as a router, used to forward packets in a communications network includes indicia whose state determine whether information contained in the forwarding table or information contained in the header portion of a packet is to be used to forward the packet to the next hop (i.e. next point in the route).
US07873025B2 Network device that determines application-level network latency by monitoring option values in a transport layer message
A data processing apparatus in a network receives packet flows that are communicated between a first network node and a second network node, and comprises a clock and latency analysis logic configured for receiving a first data segment that has been communicated from the first node and forwarding the first data segment to the second node; storing a first time value of the clock in association with a first timestamp value obtained from the first data segment; receiving a second data segment that has been communicated from the second node and forwarding the second data segment to the first node; retrieving the first time value based on the first timestamp value; determining a second time value of the clock; and determining a first latency value by computing a difference of the second time value and the first time value. Thus end-to-end packet latency is determined by passively observing timestamp values.
US07873024B1 Synchronization of computer system clock using a local gateway
Methods and apparatuses for synchronizing a system clock of a computer via a local gateway are described herein. In one embodiment, a local clock of a gateway device is periodically synchronized with a remote time service facility over an external network. The synchronized local clock of the gateway device is then used to synchronize a system clock of one or more clients over a local network without having the clients individually to access the remote time service facility. Other methods and apparatuses are also described.
US07873022B2 Multiple input multiple output wireless local area network communications
A wireless local area network (WLAN) transmitter includes a MAC module, a PLCP module, and a PMD module. The Medium Access Control (MAC) module is operably coupled to convert a MAC Service Data Unit (MSDU) into a MAC Protocol Data Unit (MPDU) in accordance with a WLAN protocol. The Physical Layer Convergence Procedure (PLCP) Module is operably coupled to convert the MPDU into a PLCP Protocol Data Unit (PPDU) in accordance with the WLAN protocol. The Physical Medium Dependent (PMD) module is operably coupled to convert the PPDU into a plurality of radio frequency (RF) signals in accordance with one of a plurality of operating modes of the WLAN protocol, wherein the plurality of operating modes includes multiple input and multiple output combinations.
US07873020B2 CAPWAP/LWAPP multicast flood control for roaming clients
A method, an apparatus, a system, and logic encoded in one or more computer-readable tangible medium to carry out a method. The method includes maintaining the state of clients of an access point controlled by a controller in the controller of the access point, including multicast group information, and updating the access point with multicast group identification for the clients, such that the controller in combination with the access point can forward packets, and such that multicast group information for a roaming client of the access point is maintained.
US07873015B2 Method and system for registering an unlicensed mobile access subscriber with a network controller
Redirection of mobile subscriber registrations using location information is described. In one embodiment, the invention includes establishing a data communications connection with a mobile station at a data communications network controller, receiving location information from the mobile station, and redirecting the mobile station to a different network controller based on the received location information.
US07873010B2 Control signaling resource assignment in wireless communication networks
A method in a wireless communication network scheduling entity including allocating time-frequency radio resources in a sub-frame to a particular wireless communication device, wherein the sub-frame has a time dimension and a frequency dimension spanning a spectrum allocation, and wherein the time-frequency radio resource allocation includes a contiguous set of control channel resources extending from at least one edge of the spectrum allocation toward a medial portion of the spectrum allocation.
US07873009B2 Method and system of radio communications of traffic with different characteristics
The present invention relates to communications. More especially it relates to communications over radio links subject to fading or otherwise intermittently unreliable. Particularly it relates to high data rate communications and combinations of conventional and opportunistic communications within a communications system.
US07873008B2 Method for setting user equipment identifier in radio communication system
The present invention is directed to a method for setting a user equipment identifier as user equipment identification information used when data received through a dedicated logical channel is transmitted through a common transport channel. The method includes transmitting data and a message type indicator as user equipment identification information from a RRC layer to an RLC layer; setting a user equipment identifier indicator according to the received message type indicator in the RLC layer and transmitting it with the data to a MAC layer; and selecting a user equipment identifier type and a user equipment identifier according to the set user equipment indication identifier, adding it to a header of a MAC SDU in the MAC layer and transmitting it to a corresponding MAC layer in a receiving device.
US07873006B2 Method for transmitting data of radio bearer having priority in wireless communication system
A method of allocating resources in a wireless communication system including configuring priorities for a plurality of logical channels according to a first criterion, wherein each of the plurality of logical channels has each priority and allocating resources to a subset of the plurality of logical channels according to a second criterion to transfer data through a transport channel, wherein the subset of the plurality of logical channels is configured with same priority. It is possible to reliably provide various services through a method of processing radio bearers having the equal priorities.
US07873005B2 Method for resolving collision of uplink signals
A method for processing data in a wireless communication system is provided. The method includes receiving a first uplink scheduling command indicating a first radio resource, receiving a second uplink scheduling command indicating a second radio resource through a random access response, and stopping a procedure associated with the second uplink scheduling command when the first radio resource and the second radio resource collide.
US07872995B2 Communication system, communication device, notification method, recording medium, and program
A communication system includes first and second communication devices that carry out wireless communication. The first communication device includes a setter configured to set a first indication mode and a corresponding second indication mode, a sender configured to send data representing the second indication mode to the second communication device when communication has been established with the second communication device, and a first indicator configured to indicate the establishment of communication in the first indication mode, correspondingly to indication in the second indication mode by the second communication device. The second communication device includes a receiver configured to receive the data representing the second indication mode, and a second indicator configured to indicate the establishment of communication in the second indication mode, correspondingly to the indication in the first indication mode by the first communication device.
US07872994B2 SIP out-of-dialog REFER mechanism for handoff between front-end and back-end services
In one embodiment, a method includes steps of verifying, by a first server, that a user associated with an endpoint is authorized to access a service provided by a second server. The first server then sends a Session Initiation Protocol (SIP) out-of-dialog REFER with a Replaces header to the second server. A dialog identification ID of a session between the endpoint and the first server is embedded within the Replaces header. The SIP out-of-dialog REFER causes the second server to send a SIP INVITE with the Replaces header to the endpoint to establish a new session between the endpoint and the second server. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
US07872993B2 Method and system for classifying data packets
Embodiments of the invention provide a method for building a classification tree based on a plurality of rules. Each rule includes multiple fields having different priority levels. The classification tree is built to provide for single pass classification of a received packet according to the multiple rules. The classification tree is built level-by-level, where each level represents one of the priority levels. Building a single level of the classification tree includes: creating, for each of the logical decision paths received from a next higher priority level, a respective sub-tree. The sub-tree includes only nodes and related logical decision paths that are necessary to satisfy rules associated with a respective next higher priority level node. Building of the single level further includes: creating, for each non-lowest priority level, logical decision paths from nodes within the current priority level to a next lower priority level.
US07872992B2 Network system and relay device
When a network system of the present invention performs a bandwidth-guaranteed communication, a terminal device collects information on one or more relay devices on a path to another terminal device via a bandwidth request packet transmitted to the another terminal. When the bandwidth cannot be allocated, a detour path is searched according to the collected relay device information so as to perform the bandwidth-guaranteed communication via the detour path.
US07872991B2 Methods and systems for providing MPLS-based layer-2 virtual private network services
Methods and systems for forwarding packets over Label Switched Paths (LSPs) in a Virtual Private Network (VPN) are implemented within a Layer-2 architecture. A system includes a number of multi-purpose nodes connected by a number of multi-protocol label switching (MPLS) LSP links. Each multi-purpose node contains at least one bridging module (BM) that runs an extension of a bridging protocol (BP) contained in the IEEE 802.1d standard. The BP is used to establish MPLS LSPs between the BMs. The BP then generates a spanning tree using a spanning tree program to establish an optimal number of active LSPs. The remaining LSPs are then set to “inactive” The BM de-allocates the resources assigned to inactive LSPs and makes the resources available to other active LSPs.
US07872989B1 Full mesh optimization for spanning tree protocol
An optimized spanning tree protocol (OSTP) minimizes latency and provides high throughput in a full-mesh portion of a network, and is compatible with external networks where a standard spanning tree protocol is used. The OSTP enables traffic traversing the full-mesh portion to take a shortest path from source to destination through use of full-mesh connectivity. In some embodiments, a cluster includes a plurality of servers connected in a full mesh, and the OSTP is used on internal ports of the servers. In some embodiments, the OSTP is configured on a per-VLAN basis. In some embodiments, the servers exchange special messages enabling determination of full-mesh connectivity. In further embodiments, sending of the special messages is suppressed on certain port types, such as external ports. In some embodiments, determination of the full-mesh connectivity disables use of a standard spanning tree protocol and/or enables use of OSTP on the full-mesh portion.
US07872987B1 Methods and apparatuses for generating network test packets and parts of network test packets
Some aspects of the technology relate to the generation for test purposes of test packet ingredients by a microprocessor, ongoing with the generation for test purposes of test packets incorporating the test packet ingredients by a high-speed FPGA. Some aspects of the technology relate to the generation of outgoing test packets incorporating the test packet ingredients, at a programmable logic device such as an FPGA. These aspects are implemented as an apparatus, a method, computer readable medium, and a data structure.
US07872986B2 Method for transitioning between multiple reception levels
There is provided a method for enabling a user equipment (UE) to transition between a non-discontinuous reception (Non-DRX) level and at least one discontinuous reception (DRX) level. The UE in a DRX level wakes up periodically to monitor a scheduling channel. The method includes receiving a DRX indicator in a Non-DRX level with continuously monitoring the scheduling channel and transitioning from the Non-DRX level to a DRX level indicated by the DRX indicator. The UE can transition between multiple DRX levels by an explicit command/signaling.
US07872982B2 Implementing an error log analysis model to facilitate faster problem isolation and repair
A system, method, and computer-readable medium for detecting errors on a network. According to a preferred embodiment of the present invention, a network error manager retrieves a network topology from a master subnet manager, wherein the network includes a collection of devices coupled by a first interconnect type. When a connectivity failure is detected in the first interconnect type, the network error manager receives from the master subnet manager at least one event notification via a second interconnect type. An error log analysis component identifies at least one device among the collection of devices as a possible cause of the connectivity failure in the first interconnect type. The network error manager retrieves events from at least one device among the collection of devices that can influence a state of the first interconnect type.
US07872979B1 System and method to access and address high-speed interface converter devices
High-speed transceiver devices, such as GBIC-type transceivers, are accessed and addressed. Identification information (including manufacturer name, model, compliance codes) is placed in data fields of the transceivers. An algorithm checks each port in each module of a host system to determine if a transceiver is present. If a particular transceiver is present, then algorithms store the port address of the transceiver in memory and enable the transceiver to be read from or written to. Reading from the transceiver includes reading the identification information, and writing to the transceiver includes writing the identification information. If a transceiver is initially determined not to be present or if the reading/writing/enabling processes fail, then a recovery process determines if the transceiver was present the last time it was checked. If it was present the last time, then the process continues to try to recover the transceiver data—otherwise, the port is marked as empty.
US07872974B2 System and method for handling or avoiding disruptions in wireless communication
A wireless communication method comprises selecting a cause of a disruption from two or more potential causes of disruptions by associating at least one characteristic of a communication with a device with the selected cause of a disruption and changing a data rate for the communication from an existing data rate to a new data rate based upon the at least one characteristic of the communication.
US07872973B2 Method and system for using a queuing device as a lossless stage in a network device in a communications network
A method for incorporating a queuing device as a lossless processing stage in a network device in a communications network, comprising: monitoring a depth of a queue in the queuing device, the queue for receiving packets from an upstream device within the network device, the queuing device acting as a discard point by discarding packets when the queue is full; and, if the depth passes a predetermined threshold, sending a message to the upstream device to reduce a rate at which packets are sent to the queuing device to prevent the queue from filling and thereby preventing packet discarding and loss by the queuing device.
US07872970B2 Method for selecting a determinator of priority to access a network
The present invention relates to technology for determining priority when an access to a network, e.g., UPnP-based home network is requested. An illustrative method according to the present invention sets one priority determinator among a plurality of determinators to default one, and asks the default priority determinator priority information on a connection for traffic when the connection is requested to be allowed.
US07872967B2 Apparatus and method for multi-protocol label switching label-switched path protection switching
Provided are system and method for multi-protocol label switching (MPLS) label-switched path (LSP) protection switching in an MPLS system employing a working LSP and a protection LSP in a 1:1 mode, The system includes: an ingress node multicasting input MPLS traffic through the working LSP and the protection LSP using a fed-back BDI signal; a transit node relaying the MPLS traffic input from the ingress node, and generating a FDI signal when the failure occurs; and an egress node extracting the MPLS traffic from the MPLS LSP input from the transit node, and when the FDI signal is detected, inserting and feeding back the BDI signal to the ingress node through a return path and performing switching to the protection LSP.
US07872962B1 System and method for producing weighted signals in a diversity communication system
The disclosed technology relates to a communication system and method in which multiple versions of a signal are processed to detect the signal. The communication system can include transmitters that communicate different versions of a signal to a receiver. The different versions are weighted versions of the signal and are communicated on different channels. The weight for a weighted signal is based on an inverse of an estimate of the phase shift of the particular channel to which the weighted signal will be communicated. The weights are also based on a unity gain such that each weighted signal has the same magnitude as the original signal. A receiver that receives the weighted signals processes the received signals to detect the original signal.
US07872961B2 Orthogonal frequency division multiple access message processing method and apparatus
A base station receives (201) OFDMA messages from a plurality of end user platforms that share all used tones within at least one OFDMA symbol. By one approach this base station then uses (202) a fixed starting time to select contiguous samples from received aggregate multi-user signals wherein the fixed starting time is offset from a reference time that comprises a time at which the base station expects to be receiving the signals from all end users. In combination with the time offset approach noted above or in lieu thereof the base station can process (204) selected contiguous samples using fast Fourier transform and then provide (205) phase rotation with respect to those processed samples. When applying phase rotation, by one approach a phase rotation can be applied (401) to the aggregate multi-user signal and, in addition, individual phase rotation can be applied (402) as determined on a user-by-user basis.
US07872954B2 Method and apparatus for writing data to an optical disc
The invention provides for a method and apparatus for writing data to an optical disc and comprising recovering an output signal from optical reading head, scaling the said output signal responsive to secondary data derived from the disc by way of the optical reading head and deriving a Land Pre Pits (LPP) signal for use during recording to the disc from the said scaled output signal wherein the said scaling is arranged to increase the LPP signal when the LPP is identified as located adjacent a mark on the disc of low light reflectivity.
US07872952B2 Optical disc drive
An optical disk apparatus according to the present invention includes: a light emission section for emitting laser light; an optical system for irradiating the optical disk medium with the laser light; and an aberration control section for controlling aberration of the laser light. In one embodiment, the aberration control section repeatedly switches between a plurality of aberration setting states in a focus lock-in operation. In another embodiment, the aberration control section simultaneously sets a plurality of aberration setting states in a focus lock-in operation. As a result, a plurality of aberration setting states can be allowed to substantially coexist within a single optical system.
US07872947B2 System and method for underwater wireless communication
An underwater wireless communication system and method includes a sensor node for transforming measured underwater data into ultrasound signals, and transmitting the transformed ultrasound signals and receiving other ultrasound signals.
US07872946B1 Autonomous waterproof electronic signaling device
The autonomous waterproof electronic signaling device disclosed comprises an activator; a signal emitter, said signal emitter to emit a primary signal upon activation of said activator, said signal emitter comprising one or more of the following: a hydrophone, a siren, a speaker, or a transducer; and a head assembly, said head assembly positioned so as to alter at least a portion of said primary signal producing a notification signal.
US07872945B2 Dynamic efficiency optimization of piezoelectric actuator
This invention applies to the means whereby capacitance changes due to varying temperature and/or pressure in a piezoelectric transducer used for acoustic telemetry in a drilling environment is dynamically offset by modifying one or more parameters associated with the drive or control circuitry of said transducer. The object of the invention is to closely maintain the transducer in a resonant mode, thereby ensuring optimum energy consumption.
US07872941B2 Nonvolatile memory device and method of operating the same
A nonvolatile memory device comprises a page buffer unit, first to kth logic combination units, and a control unit. The page buffer unit includes first to Nth page buffer blocks. N and k are natural numbers. Each of the first to Nth page buffer blocks comprises m page buffers, divided into first to kth page buffer groups, and first to kth pass/fail check units configured to output respective verification signals, each indicative of a program pass or a program fail, according to data stored in latches of the page buffers included in each of the page buffer groups. The first to kth logic combination units are each configured to output respective first to kth pass/fail determination signals.
US07872939B2 Semiconductor memory device
A semiconductor memory device includes: a first address buffer configured to be used in a test mode and a normal mode and to receive more addresses in the test mode than in the normal mode; and a second address buffer configured to be used in the normal mode and disabled in the test mode.
US07872937B2 Data driver circuit for a dynamic random access memory (DRAM) controller or the like and method therefor
A data driver includes a first latch (322), an extension logic circuit (324), and a second latch (330). The first latch (322) has an input for receiving an input data signal, a clock input for receiving a first clock signal, and an output. The extension logic circuit (324) has an input coupled to the output of the first latch (322), a control input for receiving a control signal, and an output. The extension logic circuit (324) selectively delays the output of the first latch (322) in response to the control signal. The second latch (330) has an input coupled to the output of the extension logic circuit (324), a clock input for receiving a second clock signal, and an output for providing an output data signal.
US07872936B2 System and method for packaged memory
In one embodiment, a memory system is disclosed. The memory system has at least one memory chip having an address and data interface coupled to an internal address and data bus, and a memory controller and interface chip also having a an address and data interface coupled to the address and data interface of the at least one memory chip via an internal address and data bus. The at least one memory chip, the memory controller and interface chip and the internal address and data bus are disposed within a common chip package. The memory controller and interface chip has an external interface configured to be coupled to a standard memory bus via external contacts of the common chip package.
US07872935B2 Memory cells with power switch circuit for improved low voltage operation
Static random access memory (SRAM) cells and methods of operation are provided which may be used to provide improved writeability and stability to support low voltage operation of memory devices. For example, in one implementation, by temporarily interrupting the connection between portions of an SRAM cell and a power source such as a reference voltage or current source, the writeability of SRAM cells can be improved. Additional read port implementations are also provided to facilitate low voltage operation. In another implementation, a power switch circuit responsive to a word line and logic signals may be used to provide such interruptions.
US07872933B2 Memory driving method and semiconductor storage device
This disclosure concerns a method of driving a memory including memory cells, bit lines, and word lines, each memory cell having a source, a drain, and a floating body, the method comprising performing a refresh operation for recovering deterioration of first logical data of the memory cells and deterioration of second logical data of the memory cells, wherein in the refresh operation, the number of the carriers injected into the floating body is larger than the number of the carriers discharged from the floating body when a potential at the floating body is larger than a critical value, and the number of the carriers injected into the floating body is smaller than the number of the carriers discharged from the floating body when the potential at the floating body is smaller than the critical value.
US07872928B2 Write control signal generation circuit, semiconductor IC having the same and method of driving semiconductor IC
A write control signal generation circuit includes a delay/comparison/transmission block that outputs one of a delayed write command signal and a write command signal according to a test mode signal, and a control signal generation unit that generates a write control signal by delaying the output of the delay/comparison/transmission block corresponding to a variable amount of delay.
US07872923B2 Low voltage sensing scheme having reduced active power down standby current
A low voltage sensing scheme reduces active power down standby leakage current in a memory device. During memory's active power down state, the leak current may increase because of the use of P and Nsense amplifiers having low threshold voltages (Vth) for low Vcc sensing of data signals. A clamping device or diode is used between a Psense amplifier control line (e.g. ACT) and Vcc and/or between an Nsense amplifier control line (e.g. RNL*) and Vss (ground potential). The clamping diode is not enabled during normal memory operations, but is turned on during active power down mode to reduce leakage current through ACT and/or RNL* nodes. The clamping device connected to the ACT node may reduce the voltage on the ACT line during power down mode, whereas the clamping device connected to the RNL* node may increase the voltage on the RNL* line during power down mode to reduce sense amplifier leakage current through these nodes. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
US07872921B2 Non-volatile semiconductor memory with page erase
In a nonvolatile memory, less than a full block may be erased as one or more pages. A select voltage is applied through pass transistors to each of plural selected wordlines and an unselect voltage is applied through pass transistor to each of plural unselected wordlines of a selected block. A substrate voltage is applied to the substrate of the selected block. A common select voltage may be applied to each selected wordline and the common unselect voltage may be applied to each unselected wordline. Select and unselect voltages may be applied to any of the wordlines of a select block. A page erase verify operation may be applied to a block having plural erased pages and plural nonerased pages.
US07872918B2 Nonvolatile memory device and program or erase method using the same
A nonvolatile memory device includes a comparison unit configured to compare a reference voltage and a voltage of each of a plurality of nodes of a sample memory cell string, a state storage unit configured to store state information of each of memory cells depending on the corresponding comparison result of the comparison unit, and a high voltage generation unit configured to change a program start voltage depending on data stored in the state storage unit.
US07872917B2 Non-volatile semiconductor memory device and memory system including the same
Provided is a non-volatile semiconductor device. The non-volatile semiconductor memory devices including: first and second word line groups disposed in parallel; dummy word lines disposed between the first and second word line groups; a first bit line group intersecting the first word line group; and a second bit line group intersecting the second word line group, wherein the first and second word line groups, the first and second bit line groups, and the dummy word lines are disposed on a same well.
US07872916B2 Deterministic-based programming in memory
Systems, methods, and devices that employ deterministic programming techniques to facilitate efficient programming of memory elements in a memory are presented. A memory component comprises an optimized program component that can divide a group of memory elements selected for programming into a desired number of subgroups based in part on respective current threshold voltage levels (Vt) of the memory elements; apply respective program pulses to each memory element in respective subgroups; measure respective Vt levels of memory elements after the pulse; and verify as passed memory elements that meet a target Vt. The optimized program component can divide a subset of memory elements that do not meet the target Vt into a desired number of subgroups based in part on respective current Vt levels of the memory elements and can continue to perform this deterministic programming process until all memory elements are verified as passing for the target Vt.
US07872915B2 Nonvolatile memory device and reading method thereof
A nonvolatile memory device can improve its operation characteristic by reducing leakage current of a bit line in a read operation. The nonvolatile memory device includes a plurality of word lines, a plurality of main bit lines intersecting with the plurality of word lines, a plurality of cell blocks each including a plurality of cell strings, each of the cell strings including first and second select transistors and a plurality of memory cells, a plurality of sub bit lines commonly connected to the respective cell strings in same group, the cell blocks being grouped into a plurality of groups whose number is identical to or smaller than the number of the cell blocks, a plurality of group selectors configured to selectively connect the main bit lines to the sub bit lines of a selected group, and a plurality of page buffers configured to sense data of the memory cells through the main bit lines.
US07872914B2 Monitor structure for monitoring a change of a memory content
A monitor structure for monitoring a change of a memory content in a memory field of a non-volatile memory comprising a reference transistor in the memory field and a monitor transistor. The monitor transistor and the reference transistor comprise a common floating gate. Moreover, the memory field is arranged in a first well, and the monitor transistor in a second well. The first well and the second well are of different doping types.
US07872913B2 Nonvolatile analog memory
A nonvolatile analog memory has a floating gate point. The nonvolatile analog memory includes a capacitor, a first current source, a second current source and a current adjuster. The first current source controlled by a voltage value at the floating gate point and generates a first current. The second current source controlled by the voltage value at the floating gate point and generates a second current. The current adjuster receives the output voltage and a reference voltage and adjusts the first current and the second current based on the output voltage and the reference voltage. The current adjuster charges or discharges the capacitor to equalize the output voltage to the reference voltage.
US07872912B2 M+N bit programming and M+L bit read for M bit memory cells
A memory device and programming and/or reading process is described that programs and/or reads the cells in the memory array with higher threshold voltage resolution than required. In programming non-volatile memory cells, this allows a more accurate threshold voltage placement during programming and enables pre-compensation for program disturb, increasing the accuracy of any subsequent read or verify operation on the cell. In reading/sensing memory cells, the increased threshold voltage resolution allows more accurate interpretations of the programmed state of the memory cell and also enables more effective use of probabilistic data encoding techniques such as convolutional code, partial response maximum likelihood (PRML), low-density parity check (LDPC), Turbo, and Trellis modulation encoding and/or decoding, reducing the overall error rate of the memory.
US07872900B2 Correlated electron memory
A non-volatile resistive switching memory that includes a homogeneous material which changes between the insulative and conductive states due to correlations between electrons, particularly via a Mott transition. The material is crystallized into the conductive state and does not require electroforming.
US07872899B2 Semiconductor memory device
The memory cell array includes a memory cell, the memory cell including a ferroelectric capacitor and a transistor. The memory cell array includes a word line selecting the memory cell, a plate line applying a drive voltage to the ferroelectric capacitor, and a bit line reading data from the ferroelectric capacitor. A selection transistor selectively connects the memory cell to the bit line. A dummy cell provides a reference potential, the reference potential being referred to for a potential read from the memory cell. A sense amplifier circuit includes a plurality of amplification circuits amplifying the potential difference between a bit-line pair. A decoupling circuit electrically cuts off the bit line between the amplification circuits.
US07872898B2 One time programmable read only memory and programming method thereof
A one time programmable read only memory disposed on a substrate of a first conductive type is provided. A gate structure is disposed on the substrate. A first doped region and a second doped region are disposed in the substrate at respective sides of the gate structure, and the first doped region and the second doped region are of a second conductive type which is different from the first conductive type. A third doped region of the first conductive type is disposed in the substrate and is adjacent to the second doped region, and a junction is formed between the third doped region and the second doped region. A metal silicide layer is disposed on the substrate. An clearance is formed in the metal silicide layer, and the clearance at least exposes the junction.
US07872897B2 Programmable semiconductor device
A programmable device includes a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end (12a) is substantially wider than the second end (12b), and a metallic material is disposed on the upper surface; the metallic material being physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and the metallic material.
US07872896B2 Magnetic shift register and operation method thereof
A magnetic shift register includes at least a magnetic memory track of which several walls separate the memory track into multiple magnetic domains to serve as magnetic binary memory cells. The magnetic memory track includes multiple data regions. Each data region has multiple of the magnetic binary memory cells for storing bit data at a quiescent state and registering at least one of the bit data shifted from the adjacent data region at a shifting state. Wherein, the bit data of the magnetic binary memory cells is shifted between the adjacent two data region under an operation current.
US07872895B2 Semiconductor device with non-volatile memory and random access memory
A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.
US07872893B2 Semiconductor memory device
A semiconductor memory device having a hierarchical bit line structure includes memory cells and an amplification circuit for amplifying a signal read from one of the memory cells via a bit line. A cell N-well region in which the P-channel transistors of the memory cell are formed and an amplification-circuit N-well region in which the P-channel transistors of the amplification circuit are formed are formed continuously.
US07872892B2 Identifying and accessing individual memory devices in a memory channel
In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register.
US07872888B2 Electric power conversion system
An electric power conversion system includes a DC power supply, plural main circuit switching devices bridge-connected to carry out DC/AC convert, having freewheeling diodes connected in reverse parallel thereto, respectively, and a reverse voltage application circuit for applying a reverse voltage smaller than the DC power supply to each freewheeling diode, upon a cutoff of back-flow current of the freewheeling diode, the reverse voltage application circuit being composed of a series connection of a low-voltage DC power supply, a reverse voltage application switching device having a lower withstand voltage than the main circuit switching devices and adapted to turn on upon a reverse recovery of the freewheeling diode, and an auxiliary diode having a shorter reverse recovery time than the freewheeling diode, the reverse voltage application switch being a device having holes as a majority carrier.
US07872887B2 DC-AC inverter powering a single phase commercial power system
A grounding wire from a commercial power system is connected to a series-connection end of a series connection between two capacitors connected in series between a positive electrode and a negative electrode. A current detector monitors an output current of an inverter unit in which four switching elements and two diodes convert voltages at both ends of the series circuit of the capacitors at three levels. An operation control circuit controls a generation of a PWM signal to be applied to the four switching elements, to minimize a difference between a current value detected by the current detector and a target current value.
US07872883B1 Synchronous buck power converter with free-running oscillator
In one embodiment, a power converter system includes a switching circuitry having a plurality of switches operable to be turned on and off to cause current to flow to deliver power to a load. A driver circuitry is responsive to an oscillation signal and generates control signals for turning on and off the switches in the switching circuitry. A free-running oscillator circuitry provides the oscillation signal to the driver circuitry. The free-running oscillator circuitry has an operational amplifier. A frequency of the oscillation signal will be higher if the operational amplifier outputs a first value, and the frequency of the oscillation signal will be lower if the operational amplifier outputs a second value.
US07872880B2 Switch mode power supply
A switch mode power supply according to the invention that can improve the reliability thereof includes a series circuit connected between the positive and negative electrodes of a DC power supply 3, the series circuit including a capacitor 4, a main switching device 1, and a subsidiary switching device 2; a main control circuit 13; a subsidiary control circuit 10; control circuits 13 and 10 turning main switching device 1 and subsidiary switching device 2 alternately ON and OFF to obtain a DC output via a transformer 6; and subsidiary control circuit 10 preventing a voltage exceeding the gate breakdown voltage of subsidiary switching device 2 from being applied to the gate electrode of subsidiary switching device 2.
US07872873B2 Extended COB-USB with dual-personality contacts
A dual-personality extended USB (EUSB) system supports both USB and EUSB memory cards using an extended 9-pin EUSB socket. Each EUSB memory card includes a PCBA having four standard USB metal contact pads disposed on an upper side of a PCB, and several extended purpose contact springs that extend through openings defined in the PCB. Passive components are mounted on a lower surface of the PCB using SMT methods, and IC dies are mounted using COB methods, and then the components and IC dies are covered by a plastic molded housing. The extended 9-pin EUSB socket includes standard USB contacts and extended use contacts that communicate with the PCBA through the standard USB metal contacts and the contact springs. The PCBA includes dual-personality electronics for USB and EUSB communications.
US07872871B2 Molding methods to manufacture single-chip chip-on-board USB device
A low-profile Universal-Serial-Bus (USB) device includes a PCBA in which all passive components and unpackaged IC chips are attached to a single side of a PCB opposite to the metal contacts. The IC chips include, for example, a USB controller chip and a flash memory chip, or a single-chip (combined USB controller/flash memory) chip. Multiple flash IC chips are optionally stacked to increase storage capacity. The IC chip(s) are attached to the PCB by wire bonding or other chip-on-board (COB) technique. The passive components are attached by conventional surface mount technology (SMT) techniques. A molded housing is then formed over the IC chips and passive components such that the device has a uniform thickness. The low-profile USB device is optionally used as a modular insert that is mounted onto a metal case to provide a USB assembly having a plug shell similar to a standard USB male connector.
US07872867B2 Cooling system for an electronic component system cabinet
An electronic component system cabinet includes a plurality of electronic component system bays, and a plurality of electronic component systems mounted in respective ones of the plurality of electronic component system bays. The electronic component system cabinet further includes a cooling system including a plurality of coolant reservoirs. Each of the plurality of coolant reservoirs is associated with at least one of the plurality of electronic component system bays. The cooling system further includes at least one pump fluidly connected to each of the plurality of coolant reservoirs. The at least one pump is selectively operated to circulate a supply of coolant to each of the plurality of coolant reservoirs.
US07872862B2 Fixing device
A fixing device for detachably fastening an electronic element inside thereof is described. Two fastening modules are respectively disposed on the two opposite inner walls of a housing. A positioning disk is rotatably connected with the positioning frame and has a concave section with a pair of inner side surfaces. The positioning disk is disposed between the first pair of positioning surfaces while the positioning disk is disposed between the second pair of positioning surfaces. When the positioning disk is at a first position, the pair of inner side surfaces is aligned with the first pair of positioning surfaces to allow the electronic element to be inserted between. When the positioning disk is rotated from the first position to the second position, the pair of inner side surfaces is aligned with the second pair of positioning surfaces, and the first and second connection members engage each other to fasten the electronic element.
US07872861B2 Portable electronic device
A portable electronic device has a lower body, an upper body, and a moving assembly installed between the parts. The moving assembly has a lower base fixed to the lower body, a middle base pivoted to the lower base along a first axis, and an upper base pivoted to the middle base along a second axis that is substantially paralleled to the first axis and slidably connected to the upper body.
US07872858B2 Method for manufacturing electrolytic capacitor and electrolytic capacitor
A method for manufacturing an electrolytic capacitor comprising the steps of: forming a capacitor element having a pair of electrode foils wound with a separator interposed therebetween; impregnating the capacitor element with a dispersion solution containing particles of an electrically conductive solid or aggregates thereof and a solvent to form a planar electrically conductive solid layer having the particles of the electrically conductive solid or the aggregates thereof on the surfaces of the electrode foils and the separator; and impregnating the capacitor element having the electrically conductive solid layer with an electrolytic solution.
US07872850B2 Wall crawling robots
Described herein is electroadhesion technology that permits controllable adherence between two objects. Electroadhesion uses electrostatic forces of attraction produced by an electrostatic adhesion voltage, which is applied using electrodes in an electroadhesive device. The electrostatic adhesion voltage produces an electric field and electrostatic adherence forces. When the electroadhesive device and electrodes are positioned near a surface of an object such as a vertical wall, the electrostatic adherence forces hold the electroadhesive device in position relative to the surface and object. This can be used to increase traction or maintain the position of the electroadhesive device relative to a surface. Electric control of the electrostatic adhesion voltage permits the adhesion to be controllably and readily turned on and off.
US07872839B2 Systems, methods, and devices for controlling a serial arc fault in an electrical circuit
Methods, systems, and devices for controlling a serial arc fault in an electrical circuit are disclosed. In some embodiments, the methods include the following: a. measuring a current in the circuit; b. determining whether the current is below a predetermined value; c. if the current is below ten percent of the predetermined value, determining whether a countdown timer value indicated by a cell pointer value is equal to zero; d. if the countdown timer value is equal to zero, starting a countdown timer, advancing the cell pointer value by one, and restarting the method at step a.; e. if the countdown timer value is not equal to zero, determining whether the interruptions in the current are periodic; f. if the interruptions in the current are not periodic, checking whether an arc event countdown timer is running; and g. if the arc event countdown timer is running, tripping a circuit breaker.
US07872835B2 Optimized write pole flare angle for side shield or semi side shield PMR writer application
Improved writability and a reduction in adjacent track erasure are achieved in a PMR writer with a large flare angle of 45 and 90 degrees in the main write pole and a full side shield or partial side shield configuration around the narrow write pole section and write pole tip. A trailing shield is formed above the write pole's top surface and a full or partial side shield section is spaced a certain distance from each side of the write pole. The partial side shield has a thickness less than that of the write pole and a top or bottom surface about coplanar with the pole tip's top or bottom edge, respectively. The partial side shield may include two sections on each side of the write pole wherein the bottom surface of a top section is separated by a certain distance from the top surface of a bottom section.
US07872829B2 Method and apparatus for offset control in a disk drive
According to one embodiment, there is provided a disk drive that can perform dynamic offset control (DOC). The disk drive has a magnetic head, a disk, and offset calculating modules. The magnetic head has read head. Offset-measuring position data is written in a non-servo area provided in the disk. The read head reads the offset-measuring position data from the disk. Based on the offset-measuring position data thus read, the offset calculating modules calculate an offset value that changes during a one-rotation period of the disk.
US07872812B2 Emitting and focusing apparatus, methods, and systems
Apparatus, methods, and systems provide emitting, field-adjusting, and focusing of electromagnetic energy. In some approaches the field-adjusting includes providing an extended depth of field greater than a nominal depth of field. In some approaches the field-adjusting includes field-adjusting with a transformation medium, where the transformation medium may include an artificially-structured material such as a metamaterial.
US07872810B2 Light shielding structure of an optical device
A light shielding structure of an optical device includes outer and inner annular members which move relative to each other in an axial direction, small and large diameter outer peripheral portions formed on the inner annular member, and a light shielding ring positioned inside the outer annular member and supported thereby. The light shielding ring does not contact the small-diameter outer peripheral portion of the inner annular member. The light shielding ring and the large-diameter outer peripheral portion of the inner annular member coincide with each other in the axial direction in an operating state of the optical device whereby a clearance between the outer annular member and the inner annular member is made light-tight. The light shielding ring and the small-diameter outer peripheral portion of the inner annular member coincide with each other in the axial direction in a non-operating state of the optical device.
US07872806B2 Electronic image pickup system
The invention relates to an electronic image pickup system whose depth dimension is extremely reduced, taking advantage of an optical system type that can overcome conditions imposed on the movement of a zooming movable lens group while high specifications and performance are kept. The electronic image pickup system comprises an optical path-bending zoom optical system comprising, in order from its object side, a 1-1st lens group G1-1 comprising a negative lens group and a reflecting optical element P for bending an optical path, a 1-2nd lens group G1-2 comprising one positive lens and a second lens group G2 having positive refracting power. For zooming from the wide-angle end to the telephoto end, the second lens group G2 moves only toward the object side. The electronic image pickup system also comprises an electronic image pickup device I located on the image side of the zoom optical system.
US07872802B2 Reinforced retractable projection screen with a tab tensioning system and a border
Various embodiments of this invention disclose a retractable projection screen with a tab tensioning system, a textured textile border that is made from a different material as the screen, an adjustable coupling means, and a metal strip.
US07872801B2 Fresnel lens sheet, light-transmission screen, and projection image display apparatus
The Fresnel lens sheet according to the present invention has a plurality of prismatic Fresnel lens elements including a Fresnel facet, a riser facet, and a top facet crossing the facet and the riser facet on an entrance surface. An angle of the top facet of each Fresnel lens element constituting the lens relative to the an exit surface, δ1, is determined so that an exit angle of the light that has entered each of the top facets and exits from the exit surface, β, is greater than 35 degrees.
US07872799B2 Device for controlling light radiation
Device for controlling light radiation, which is excited in a specimen and/or which is backscattered and/or reflected and which contains one or more wavelengths, at a plurality of light outlets, wherein a separation of the light radiation into differently polarized components is carried out; and the components of the excitation radiation and/or detection radiation are affected in their polarization by means of a preferably birefringent, preferably acousto-optic or electro-optic medium, which changes the ordinary and extraordinary refractive index.
US07872797B2 Device for placing microscope slides in slide trays
A device for histological research includes at least one container with shelves for slide trays connected to a flexible drive enabling reciprocating vertical motion of the container. The drive comprises a circular drive cable, a motor and at least one pulley. The device also includes a horizontal pusher provided on the working end with a tool for gripping the slide tray and moving it into the working zone outside the container and then back into the container, as well as a slide gripper capable of moving horizontally over the working zone in the direction perpendicular to that of the horizontal pusher.
US07872795B2 Laminated body for optical purposes that includes a melanin-containing layer and an optical product which includes the laminate
A laminated body of the present invention includes a melanin-containing layer, wherein the melanin-containing layer is formed by curing a composition that includes at least a melanin, a polymerizable monomer, and a urethane-derived composition. The composition for the laminated body of the present invention is used for producing the laminated body and includes at least a melanin, a polymerizable monomer, and a urethane-derived composition. The optical product of the present invention is formed including the laminated body.
US07872792B2 Method and device for modulating light with multiple electrodes
Improvements in an interferometric modulator that has a cavity defined by two walls.
US07872787B2 Holographic multiplex recording method, holographic recording apparatus and holographic recording medium employing the method using interference fringes
A holographic multiplex recording method which can keep a recording data rate constant and equalize nonuniformity in recording due to vibrations or the like, and a holographic recording apparatus and a holographic recording medium, which employ the method. In a process of multiplex-recording information, the time of exposure to a laser beam per data page is kept constant, and the laser output power of the laser beam is increased in accordance with a decrease in recording sensitivity of the holographic recording medium.
US07872784B2 Image reading apparatus and image processing method
Upon reading images of both sides of a document sheet, the color reproducibilities of identical background images read from the two faces of each document sheet over a large number of pages are adjusted. Hence, a first background color read by a first reader, and a second background color read by a second reader are respectively extracted, and color processing parameters of a first or second color processor are adjusted, so as to make the output from the first color processor for the first background color be approximately equal to the output from a second color processor for the second background color.
US07872783B2 Image reading apparatus
An image reading apparatus includes a feeding unit, a conveying unit, a primary stacking unit, a secondary stacking unit, and a path switching unit. The path switching unit switches between a first conveying path including a bend section for normal conveying mode and a second conveying path for reverse conveying mode. In the normal conveying mode, the conveying unit conveys a sheet fed from the feeding unit to the primary stacking unit through the first conveying path. In the reverse conveying mode, the conveying unit conveys a sheet fed from the primary stacking unit to the secondary stacking unit through the second conveying path bypassing the bend section.
US07872778B2 Image forming apparatus, image forming method, and storage medium storing program for forming image
An image forming apparatus includes a screen processing part that performs a screen processing on image data, a correction processing part that divides the image data subjected to the screen processing into plural regions, determines a correction parameter for each of the regions in response to a characteristic of the screen processing, and performs the correction processing, and an image formation part that forms an image based on the image data subjected to correction processing.
US07872777B2 Document optimization using solid monochrome colors and outlining
Methods of the present invention allow for optimization of color and shades of gray documents prior to their conversion to a monochrome format. If color/gray elements are identified in the document, the distance between them and their intensity is determined. If there are elements with the same or similar intensity in close proximity to each other, colors of some of the elements may be replaced with solid monochrome colors, and/or dithered surfaces, and/or monochrome patterns. Further, the elements may be outlined. These improvements make elements in the document more distinguishable after its conversion to a monochrome format. The described color optimization and outlining may have wide applicability in the Internet Fax technology.
US07872774B2 Image processing apparatus having an energization switching unit and control information updating unit
An image processing apparatus executes the processing of updating control information kept in the controlling units included in it without suspending an on-going processing and delaying the execution of a new processing request with less power consumption. When the controlling units are in a sleep mode or in non-energized state, NIC determines whether or not updating of firmware kept in each controlling unit is necessary by communicating with the information delivery server. The NIC controls an energization switching circuit to start up exclusively the controlling unit keeping the firmware determined necessary to be updated and replaces the firmware kept in the started controlling unit with the latest version of firmware obtained from the information delivery server.
US07872770B2 Printing system and method for combining multiple print jobs into a single compound print job
A printing system includes a printer and at least one workstation operatively connected to the printer. The work station comprises at least one input/output device connecting the workstation to the printer, a controller connected to the at least one input/output device, and a memory connected to the controller. The workstation further includes an operating system, a first application, a second application, and a print driver, all residing on the memory. A first item of the first application and a second item of the second application are both receivable by the print driver. The print driver is selectively able to concatenate the first and second items into a compound print set, able to receive a selected number of copies to be printed of the compound print set entered through the at least one input/output device and able to submit the compound print set and the selected number of copies as a single print job to the printer. Finishing attributes are able to be applied to the compound print set for processing by the printer.
US07872769B2 Divided job scheduler
In a computer system including a job scheduler which divides an input job and determines a client apparatus to assign the divided job, and a task manager which transmits the divided job to the client apparatus determined by the job scheduler, the job scheduler assigns the same job to a plurality of client apparatuses when the number of client apparatuses is larger than the number of divided jobs, and when the job is finished in one of the plurality of client apparatuses assigned the same job, execution of the job in the remaining client apparatuses is canceled so that the time until all jobs are finished is shortened.
US07872766B2 Image processing apparatus and image forming apparatus
An FPGA functions as an activation mode setting circuit for loading activation data stored on a PROM into a circuit setting memory and setting an activation mode when activating the CPU. The FPGA outputs an activation mode setting signal to the CPU, and the CPU is activated in the set activation mode. After the CPU is activated, it follows predetermined processing steps, and performs a control operation to load the circuit setting data stored in a storage section into the circuit setting memory. Thus, the FPGA is constructed as a circuit having a desired function, and also constructed as an activation mode setting circuit when activating the CPU.
US07872765B2 Non-postscript printer description file generating tool
A method for automatically generating a custom printer description file is disclosed. The custom printer description file enables a computer's printing system to insert, into a print data stream, commands (e.g., PCL, PJL, JCL, JDF, or PJTF commands) that cause a non-Postscript-enabled printing device (e.g., a non-Postscript printer) to perform operations in accordance with a user's specified desires. The custom printer description file is automatically generated based on an existing PPD file, which already indicates the features that the user's printing device supports. According to one aspect, an automated tool reads both an existing PPD file and translation data. Using the translation data, the automated tool generates a custom printer description file that contains appropriate non-Postscript commands for each feature/option combination that the printing device supports.
US07872764B2 Machine vision for predictive suspension
A predictive suspension system for a vehicle includes an imaging sensor, and energy source and a control. The imaging sensor is disposed at a vehicle and has a generally downward field of view, with the field of view encompassing an area forward of a tire of the vehicle. The energy source is operable to emit illumination in at least one linear pattern so that the linear pattern is projected onto a portion of the area forward of the tire of the vehicle that is encompassed by the field of view of the imaging sensor. The control processes image data captured by the imaging sensor and detects surface irregularities on a surface in front of the vehicle tire in response to the image processing.
US07872762B2 Optical position measuring arrangement
An arrangement for generating phase-shifted incremental signals characterizing relative positions of two objects moving with respect to each other along a measuring direction. The measuring arrangement includes a light source emitting bundles of beams, a measurement grating, a plurality of optional gratings and a scanning unit. The scanning unit includes a grating in a scanning plane, wherein the grating includes a plurality of blocks arranged periodically along the measuring direction with a grating periodicity equaling a fringe pattern periodicity, and each block includes n grating sections arranged along the measuring direction, each of the n grating sections having a periodic grating structure, deflecting the bundles of beams propagated through each of the n grating sections in several different spatial directions. The scanning unit further includes a plurality of detector elements arranged downstream of the grating, wherein the detector elements are arranged in the spatial directions in the detector plane, and wherein the detector plane is located where the bundles of beams coming from the grating are spatially separated. The fringe pattern is formed in the scanning plane by the bundles of beams emitted by the light source interacting with the measurement grating and the optional gratings.
US07872759B2 Arrangements and methods for providing multimodality microscopic imaging of one or more biological structures
Method and apparatus according to an exemplary embodiment of the present invention can be provided. For example, first data associated with a first signal received from at least one region of at least one sample can be provided based on a first modality, and second data associated with a second signal received from the at least one sample can be provided based on a second modality which is different from the first modality. Third data associated with a reference can be received. Further data can be generated based on the first, second and third data. In addition, third data associated with a second signal received from the at least one sample can be obtained. Each of the third data can be based on a further modality which is different from the first modality and the second modality, and the further data can be further determined based on the third data. Further, the first modality can be a spectral-encoded modality, and the second modality can be a non-spectral-encoding modality.
US07872756B2 Gas measuring apparatus and gas measuring method
A gas measuring apparatus includes: an infrared detecting section that receives an infrared ray from a measurement area and outputs infrared spectrum data relating to the infrared ray; a variation detecting section that detects, by using the infrared spectrum data, a variation in intensity of the infrared ray, which is caused in the infrared ray that radiates from the measurement area and which is caused by a measuring object gas in the measurement area; a converting section that converts the infrared spectrum data to radiance temperature spectrum data which represent wavelengths in an infrared region and radiance temperatures at each wavelength; a background temperature detecting section that detects, as background temperature of the measuring object gas, a maximum radiance temperature from among radiance temperatures represented by the radiance temperature spectrum data; a gas temperature detecting section that detects the temperature of the measuring object gas by using a radiance temperature in a wavelength band included in the water vapor absorption band in the infrared region from among the radiance temperatures represented by the radiance temperature spectrum data; and a computing section that computes surface density of the measuring object gas on the basis of the variation in intensity of the infrared ray, the background temperature of the measuring object gas, and the temperature of the measuring object gas.
US07872746B2 Single light source uniform parallel light curtain
A continuous high resolution fluid level monitoring system is provided by embodiments of the present invention. This continuous high resolution fluid level monitoring system includes a unique fluid level sensor having a point light source, parabolic reflector, sensor array, and detection, processing and control system. The point light source illumines a parabolic reflector wherein the point light source is located at the focus of the parabolic reflector. The parabolic reflector reflects light from the point light source to produce a parallel light curtain. This parallel light curtain is parallel to an axis of symmetry of the parabolic reflector. The parallel light curtain illumines a chamber such as a chamber in an ophthalmic surgical device used to contain surgical fluid. The sensor array coupled to the chamber detects the parallel light curtain illuminating the chamber. The sensor array provides an output to a detection/processing/control system in order to determine the fluid level within the chamber. This optical method of determining the surgical fluid levels may be advantageous in that it prevents physical contamination of the surgical fluids.
US07872743B2 Defect inspection system
In a defect inspection system using a plurality of detectors such as an upright detector and an oblique detector, if illumination light and wafer height are adjusted to the detection field of view of one detector, a defocused image is detected by other remaining detectors, resulting in degradation of the detection sensitivity. The present invention solves this problem.When a plurality of detectors such as an upright detector and an oblique detector are used in the defect inspection system, the reduction of the inspection sensitivity can be prevented by correcting the field positions of the other remaining detectors with respect to the field of view of the one detector. Further, the variation in optical axis for each inspection system due to the variation in parts and assembly errors can be reduced.
US07872742B2 Surface inspection method and surface inspection apparatus
A surface inspection apparatus capable of acquiring scattered light intensity distribution information for each scattering azimuth angle, and detecting foreign matters and defects with high sensitivity. A concave mirror for condensation and another concave mirror for image formation are used to cope with a broad cubic angle. Since mirrors for condensation and image formation are used, a support for clamping the periphery of a lens is unnecessary, and an effective aperture area does not decrease. A plurality of azimuth-wise detection optical systems is disposed and reflected light at all azimuths can be detected by burying the entire periphery without calling for specific lens polishing. A light signal unification unit sums digital data from a particular system corresponding to a scattering azimuth designated in advance in the systems for improving an S/N ratio.
US07872741B2 Method and apparatus for scatterfield microscopical measurement
A method and an apparatus are disclosed for scatterfield microscopical measurement. The method integrates a scatterometer and a bright-field microscope for enabling the measurement precision to be better than the optical diffraction limit. With the aforesaid method and apparatus, a detection beam is generated by performing a process on a uniform light using an LCoS (liquid crystal on silicon) or a DMD (digital micro-mirror device) which is to directed to image on the back focal plane of an object to be measured, and then scattered beams resulting from the detection beam on the object's surface are focused on a plane to form an optical signal which is to be detected by an array-type detection device. The detection beam can be oriented by the modulation device to illuminate on the object at a number of different angles, by which zero order or higher order diffraction intensities at different positions of the plane at different incident angles can be collected.
US07872740B2 Motion-compensated light-emitting apparatus
A light-emitting apparatus, for enabling a beam of light to be projected on a desired target located a distance away to project the beam on the desired target without any or substantially any undesired movement. The apparatus may include a housing, a light generating device located within the housing and operable to generate a beam of light, a sensing device or devices for sensing an undesired action of the housing, a control circuit operable to provide a control signal corresponding to the sensed undesired action, and a drive device operable to counter act all or at least some of the undesired action of said housing in accordance with said control signal. The sensing device or devices may be one or more gyroscopes, accelerometers or other such devices.
US07872731B2 Lithographic apparatus and device manufacturing method
A lithographic apparatus includes a polarization changing element including at least two wedge-shaped optically active members configured to rotate the polarization direction of at least a portion of the radiation beam with a predetermined angle with respect to the first direction and an optical propagation length adaptor associated with the wedge-shaped optically active members to adjust the predetermined angle.
US07872725B2 Liquid crystal display device
A liquid crystal display device with a pair of substrates which are arranged to face each other with liquid crystal therebetween, columnar spacers having the substantially equal height formed on a liquid-crystal-side surface of one substrate, and the columnar spacers include the columnar spacer which is contact with a liquid-crystal-side surface of another substrate and the columnar spacer which is not contact with the liquid-crystal-side surface of another substrate.
US07872722B2 Liquid crystal display device and electronic device
To provide a semiconductor device, a liquid crystal display device, and an electronic device which have a wide viewing angle and in which the number of manufacturing steps, the number of masks, and manufacturing cost are reduced compared with a conventional one. The liquid crystal display device includes a first electrode formed over an entire surface of one side of a substrate; a first insulating film formed over the first electrode; a thin film transistor formed over the first insulating film; a second insulating film formed over the thin film transistor; a second electrode formed over the second insulating film and having a plurality of openings; and a liquid crystal over the second electrode. The liquid crystal is controlled by an electric field between the first electrode and the second electrode.
US07872720B2 Liquid crystal device and projector
A liquid crystal device includes a pair of substrates facing each other, and a liquid crystal layer sandwiched between the pair of substrates. One of the pair of substrates includes data lines and scanning lines that intersect each other, pixels arranged in a matrix, at least one first electrode, and at least one second electrode that applies an electric field generated between the first electrode and the second electrode to the liquid crystal layer. Each of the first electrode and the second electrode includes a plurality of electrode portions, and a joint portion for connecting the plurality of electrodes. At least a portion of the joint portion of the first electrode and at least a portion of the joint portion of the second electrode are arranged so as to overlap at least the data lines or the scanning lines, and are aligned in a line extending along the at least the data lines or the scanning lines.
US07872710B2 Liquid crystal display device with shielding pattern
Disclosed is an LCD device and a method for fabricating the same, capable of preventing defects derived from a defective UV-curing of a sealant while employing one-drop fill technology. The LCD device includes an array substrate having a metal signal line, a thin film transistor and a pixel electrode, a color filter substrate having a light shielding pattern and a color filter, a sealant interposed between the substrates and cured in order to fixedly combine the array substrate with the color filter substrate, and a liquid crystal layer interposed between the array substrate and the color filter substrate through one-drop fill technology. The shielding pattern is made of resin including a transparent heat-sensitive pigment, in which a color of the heat-sensitive pigment is changed to black through a heat-sensitive reaction and UV light passes through the heat-sensitive pigment.
US07872708B2 Liquid crystal display device and projection-type display device
The problem to be solved is to suppress image quality degradation caused by polarizers and provide improved light fastness.To solve the above problem, the embodiment of the present invention is a liquid crystal display device. The liquid crystal display device includes a driving-side substrate 1 on which a drive transistor 5, pixel electrode 6 and orientation film are formed. The liquid crystal display device further includes an opposed-side substrate 2 on which an opposed electrode and orientation film are formed. The liquid crystal display device still further includes liquid crystal 4 filled between the pixel electrode 6 of the driving-side substrate 1 and opposed electrode of the opposed-side substrate 2. The liquid crystal display device still further includes a reflective inorganic polarizer 3 formed between the drive transistor 5 and pixel electrode 6 of the driving-side substrate 1. The embodiment of the present invention is also a projection-type display device using the liquid crystal display device.
US07872707B1 Method for controlling an index modulation of a switchable polymer dispersed liquid crystal optical component
Described herein are the materials, mechanisms and procedures for optimizing various performance parameters of HPDLC optical devices in order to meet differing performance requirements. These optimization tailoring techniques include control and independent optimization of switchable HPDLC optical devices to meet the demanding requirements of anticipated applications for, inter alia, the telecommunications and display industries. These techniques include optimization of diffraction efficiency, i.e., index modulation, polarization dependence control, haze, cosmetic quality, control of response and relaxation time, voltage driving for on and off switching, and material uniformity. This control and independent optimization tailors properties of switchable HPDLC optical devices according to the specific requirements of the application of the switchable HPDLC optical device. The invention disclosed herein retains the desirable attributes of the multi-functional acrylate system for forming HPDLC optical devices, but adds new materials to the acrylate system and/or new process control to the recording to optimize performance parameters as may be needed for specific applications. This results in high optical quality switchable holograms with good diffraction efficiency and low, stable switching voltage.
US07872701B2 Method for fixing FPC of display
A method for fixing a flexible circuit board (FPC) of a display module includes providing a housing having at least a fixing pin, providing a display panel and an FPC having at least a fixing hole corresponding to the fixing pin, disposing the display panel and the FPC on the housing and folding back the FPC on another side of the housing such that the fixing pin passes through the fixing hole, and performing a hot mounting process to the fixing pin to enlarge the top end of the fixing pin to press the FPC onto the housing.
US07872697B2 Thin film transistor array panel for liquid crystal display capable of achieving an inversion drive
A VA mode LCD obtains a wide viewing angle without forming cutouts or protrusions in the common electrode. A pixel electrode has a cutout; a direction control electrode overlaps the cutout; a first storage electrode overlaps the pixel electrode; and a second storage electrode overlaps the direction control electrode. The pixel electrode has plurality of partitions, each partition has two major edges that are parallel to each other. In the present invention, the electric field generated by the direction control electrode pre-tilts the LC molecules by maintaining the direction control electrode voltage with respect to the common voltage higher than the pixel electrode voltage with respect to the common voltage. The LC molecules in each partition receive horizontal components of electric fields that are substantially perpendicular to the major edges thereby sorting the LC molecules into four tilt directions and thus widening the reference viewing angle according to the tilt directions of the LC molecules.
US07872694B2 Electrically-driven liquid crystal lens and stereoscopic display device using the same
An electrically-driven liquid crystal lens, which can achieve not only a gentle parabolic lens plane when being realized via alignment of liquid crystals based on a changed electrode configuration, but also a reduced cell gap of a liquid crystal layer and a stable profile even in a large-area display device, and a stereoscopic display device using the same are disclosed.
US07872688B2 Selectively applying spotlight and other effects using video layering
A video layer effects processing system which receives normal video and special effects information on separate layers has been presented. The system selectively mixes various video layers to transmit a composite video signal for a video display such as a television, or a virtual reality system. Special effects include spotlights, zooming, etc. Additional special effects such as shaping of objects and ghost effects are created by masking and superimposing selected video layers. The selective mixing, for example, to enable or disable, strengthen or weaken, or otherwise arrange special effects, can be directed from a remote source or locally by a user through real-time control or prior setup. The video layer effects processing system can also be incorporated into a set-top-box or a local consumer box.
US07872687B2 Scanning-line interpolating circuit, scanning-line interpolating method to be used in same circuit, and image display device provided with same circuit
A scanning-line interpolating circuit is provided which is capable of reducing jaggies on slanting lines and of keeping smoothness of interpolating signals achieved by using slanting lines having multiple angles for interpolation and of suppressing failures in displaying caused by erroneous judgement. When it is judged that there is matching in pixel data between three pixels or more on an upper line and three pixels or more on a lower line, an interpolating angle judging signal is corrected to be another interpolating angle judging signal corresponding to interpolation in up-and-down directions and isolated point is removed and another interpolating angle judging signal is output. Interpolating signals are blended with other interpolating signals corresponding to interpolation in same directions and at different angles and another interpolating signals are produced. One of second interpolating signals is selected based on the interpolating angle judging signal and an interpolating signal is produced.
US07872685B2 Camera module with circuit board
A camera module includes an image sensor, a lens module and a circuit board. The lens module is disposed at an object side of the image sensor and has a plurality of electrical connection points thereon. The circuit board includes a main body and a bent portion electrically connecting with the main body. The image sensor is mounted on the main body and received between the lens module and the main body. The bent portion extends from a side surface of the main body and a plurality of electrical connection points is formed on the bent portion corresponding to the electrical connection points of the lens module. The electrical connection points of the bent portion are configured for connecting with the electrical connection points of the lens module to supply power to the lens module.
US07872680B2 Method and imaging apparatus for correcting defective pixel of solid-state image sensor, and method for creating pixel information
In a solid-state image sensor in which a large number of pixel cells each comprised of a combination of a main photosensitive pixel having a relatively large area and a subsidiary photosensitive pixel having a relatively small area are arranged, if the subsidiary photosensitive pixel has a defect for any pixel cell, division photometry data during AE processing is read, and the defective pixel is replaced with a value obtained by dividing the output value of the main photosensitive pixel at the same position by a sensitivity ratio only for a section for which it is determined that the main photosensitive pixel is not saturated. Thus, the pixel value of a defective pixel can be accurately corrected without causing a reduction in resolution sensitivity compared to a conventional method of correcting a defective pixel using surrounding pixel information.
US07872677B2 Solid-state imaging apparatus
A solid-state imaging apparatus includes: a pixel section where a plurality of pixels for effecting photoelectric conversion are two-dimensionally arranged, having an effective pixel section consisting of pixels for receiving object light and a reference pixel section consisting of pixels shielded from light; a first scanning circuit for sequentially setting to the pixel section the pixels to be read out a signal; a noise suppressing circuit for suppressing noise components of signals from the pixels based on a first control signal associated with sampling and holding of signals from the pixels and a second control signal associated with setting of clamping potential that are applied at respective predetermined timings; a second scanning circuit for sequentially reading signals of each pixel suppressed of the noise components; and a reference signal control section for applying the first and second control signals to the noise suppressing circuit so that it is brought into one or the other of a first condition where signals of the pixels shielded from light are inputted and a second condition where inputting of signals of the pixels shielded from light is lacked without changing an order according to which a release of sampling by the first control signal and a release of setting of clamping potential by the second control signal are effected, causing a generation of a first reference signal obtained in the first condition or a second reference signal obtained in the second condition as a signal corresponding to an optical black level.
US07872675B2 Saved-image management
Embodiments include an apparatus, device, system, computer-program product, and method. In an embodiment, a device includes a user-accessible digital storage medium, and a storage medium manager module. The storage manager module includes a storage manager module operable to save a digital image in a form in the user-accessible digital storage medium, and then alter the form of the saved digital image if a condition is met.
US07872674B2 Solid-state imaging device and method of operating solid-state imaging device
A solid-state imaging device has: a photo-detection unit; a charge transfer unit transferring charges generated by the photo-detection unit in response to a first and a second clock generated by a clock supply circuit. The charge transfer unit includes: a first charge transfer element; a second charge transfer element adjacent to the first charge transfer element; and a charge transfer element group adjacent to the second charge transfer element and including a plurality of charge transfer elements. In a time period, the clock supply circuit supplies the first clock to the first charge transfer element, the second clock to the second charge transfer element, and constant potentials to respective the plurality of charge transfer elements.
US07872672B2 Method and apparatus for automatic white balance
A method of automatic white balance for an image capture system is disclosed. The automatic white balance mechanism ascertains the illuminant source of an image by analyzing the number of white pixels within a predefined white area in a color space diagram. The automatic white balance mechanism also determines gain adjustments based on the evaluating the average RGB values to achieve white balance.
US07872670B2 Camera performing photographing in accordance with photographing mode depending on object scene
A camera includes a CPU. The CPU individually detects a ratio of an object which exceeds a threshold value in a moving amount to a center area of an object scene and a ratio of an object which exceeds the threshold value in the moving amount to a peripheral area of the object scene. If differences between the respective detected ratios are large, the CPU sets a photographing mode to a sports mode. When a shutter button is operated, the object scene is photographed in accordance with a set photographing mode.
US07872666B2 Automatic polarizer for CCTV applications
The invention is related to a camera device (10) for CCTV applications. The camera device (10) comprises a sensor (12) comprising a lens (14) for monitoring the scene in front of the camera device (10). At least one polarizer element (16) is assigned to said sensor (12), the at least one polarizer element (16) being rotatably mounted with respect to said sensor (12), or said polarizer element (16) uses opto-electric effects.
US07872660B2 Electro-wetting-on-dielectric printing
An electro-wetting-on-dielectric printing system includes a drum and an electrode array disposed on a surface of the drum, which is made up of individually addressable electrodes and an ink-phobic coating overlaying the electrodes. Electrically charging a portion of the electrodes allows ink to adhere to a portion of the ink-phobic coating in proximity to the charged electrodes. A method for electro-wetting-on-dielectric printing includes selectively charging individually addressable electrodes within an electrode array, and passing the electrode array through an ink bath, wherein ink adheres areas proximate to charged electrodes to form an image. The image is then transferred to the substrate.
US07872658B2 Method and apparatus for generating characteristic data of illumination around image display device
A method of generating illumination characteristic data around an image display device, includes making predetermined illumination characteristic data around the image display device into a data format comprising a type block and an illuminance block. The type block indicates information on a type of illumination, and the illuminance block indicates information on the illuminance of illumination.
US07872649B1 Filtered specular reflection of linear light sources
An image rendering method for a computer system includes identifying a point in space to be illuminated from at least one line light for the point, and determining an illumination direction of the line light. The method further includes generating a plane passing through the point, and projecting the line light onto the plane. The method further includes determining a brightness contribution for the point responsive to a function characterizing the brightness contribution.
US07872648B2 Random-access vector graphics
A “Vector Graphics Encoder” encodes vector graphics in a randomly accessible format. This encoding format enables particular portions of encoded images to be directly accessed, at any desired level of zoom, without processing or otherwise decoding the entire image. This random-access format is based on a coarse image grid of partially overlapping cells wherein each cell is defined by a “texel program.” Unlike fixed-complexity cells used by conventional vector images, each cell defined by a texel program is locally specialized without requiring global constraints on the complexity of each cell. The texel program for each cell is provided as a variable-length string of tokens representing a locally specialized description of one or more of layers of graphics primitives overlapping the cell. Images are then rendered by interpreting the texel programs defining one or more cells.
US07872646B2 Power supply generating circuit, display apparatus, and portable terminal device
A power supply generating circuit, a display apparatus incorporating the same, and a portable terminal device using the display apparatus as an output display unit are provided. In a DC-DC converter having a charge pump circuit (31), a voltage dividing circuit (32), and a regulation circuit (33), p-channel MOS transistors (Qp21, Qp22, Qp31) are turned on/off based on an enable pulse enb to make the voltage dividing circuit (32) and a comparator (41) active only for a period of regulation time and inactive otherwise. This can cause a current to flow in voltage-divider resistors (R1, R2) and the comparator (41) only for a certain period of time required for the regulation operation, thus reducing the power consumption loss caused by a constant current flow in the voltage-divider resistors (R1, R2) and the comparator (41).
US07872645B2 On-chip test system and method for active pixel sensor arrays
An image sensing chip includes an active pixel sensor array including a plurality of pixels arranged in rows and columns. A built in self test circuit is coupled to the active pixel sensor array. The built in self test circuit includes an output port adapted to be coupled to external circuitry and the built in self test circuit is operable to test the active pixel sensor array and provide the results of the test on the output port.
US07872640B2 Constraining display motion in display navigation
Navigating on a display includes tracking motion of an input tool on a display, comparing a motion of the input tool to a threshold, and changing a position of the visible portion of a page of information on the display if the input tool motion exceeds the threshold. The position of the visible portion of the page of information on the display is constrained if the motion does not exceed the threshold.
US07872635B2 Foveated display eye-tracking system and method
A system for detecting and recording eye-tracking data by presenting to an observer a display image with an area in focus surrounded by blurred areas. The observer may shift the focus area within the image by head movements which are wirelessly transmitted to a receiver and used to modify the displayed image. This system solves that part of the eye-tracking problem that is most critical for measuring cognitive processes.
US07872632B2 Information processing apparatus and luminance control method
An information processing apparatus may include a light source which illuminates a display panel and a first area in which a first red element, first green element and first blue element and a second area which is arranged in one direction with respect to the first area and in which a second red element, a second green element connected in series to the first green element and a second blue element, a first control circuit which is connected to an anode of the first red element and a cathode of the second red element, a second control circuit which is connected to an anode of the first green element and a cathode of the second green element, and a third control circuit which is connected to an anode of the first blue element and a cathode of the second blue element.
US07872624B2 Liquid crystal display device
A liquid crystal display device includes a liquid crystal display element section that is initialized such that the alignment state of liquid crystal molecules is transitioned from a splay alignment to a bend alignment capable of displaying an image, and a driving circuit that applies, in the initialization, a transition voltage, which causes the alignment state of the liquid crystal molecules to be transitioned from the splay alignment to the bend alignment, to the liquid crystal display element section. In particular, the driving circuit includes a transition voltage setting unit that alternately sets the transition voltage at a first polarity and a second polarity that is opposite to the first polarity.
US07872619B2 Electro-luminescent display with power line voltage compensation
An active matrix electro-luminescent display system, comprising: a display composed of an array of regions of light-emitting elements, pixel driving circuits for independently controlling the current to each light-emitting element, one or more display drivers for receiving an input image signal for data to drive the pixel driving circuits and generating a converted image signal for driving the light emitting elements in each region of the display through signals provided through data lines and select lines, wherein the one or more display drivers sequentially receive the input image signal for driving the light emitting elements within each region of the array of regions, analyzes the input image signal received for each region to estimate the current that would result at, at least, one point along at least one power line providing current to each region, if employed without further modification, based upon device architecture and material and performance characteristics of device components, and sequentially generates a converted image signal for driving the light emitting elements in each region as a function of the input image signal and the estimated currents.
US07872617B2 Display apparatus and method for driving the same
A display apparatus includes a matrix display unit including light-emitting devices that emit light of one of a plurality of colors with a brightness corresponding to a current and pixel circuits that drive the light-emitting devices, a plurality of column control circuits that receive input image signals and generate and output current-data signals, and a plurality of data lines each provided for each column of the matrix display unit to transfer the current-data signal output from the column control circuit to one of the pixel circuits in the column. The light-emitting devices have different current-luminance efficiencies depending on colors of emitted lights, and the plurality of data lines are divided into sets of data lines, each set of data lines transferring the current-data signals of the plurality of colors to the pixel circuits, and the number of data lines in the set of data lines is equal to the number of colors. In addition, one set of the column control circuits, comprised of a number larger than a number of colors of the display unit, is provided for one set of the data lines, comprised of a number equal to the number of colors.
US07872614B2 System and method for providing a deployable phasing structure
A deployable microwave phasing structure having a plurality of sub-panels forming a non-planar reflective surface when in a deployed state. In one embodiment, the phasing structure includes a plurality of joints configured to inter-connect the plurality of sub-panels. In one embodiment, the deployable microwave phasing structure includes a folding means for arranging the phasing structure into a plurality of states, the plurality of states including the deployed state and a collapsed state, wherein the collapsed state is characterized by a substantially planar profile.
US07872613B2 Enhanced implantable helical antenna system and method
As described herein vascular anchoring systems are used to position an implant in a vascular area such as a bifurcated vasculature with relatively high fluid flow, for instance, in an area of a pulmonary artery with associated left and right pulmonary arteries. Implementations include an anchoring trunk member having a first anchoring trunk section and a second anchoring trunk section. Further implementations include a first anchoring branch member extending from the anchoring trunk member. Still further implementations include a second anchoring branch member extending from the anchoring trunk member.
US07872612B2 Antenna apparatus utilizing aperture of transmission line
An antenna apparatus utilizing an aperture of transmission line, which is connected to a first transmission line having a predetermined characteristic impedance, includes a tapered line portion, and an aperture portion. The tapered line portion is connected to one end of the transmission line, and the tapered line portion includes a second transmission line including a pair of line conductors. The tapered line portion keeps a predetermined characteristic impedance constant and expands at least one of a width of the transmission line and an interval in a tapered shape at a predetermined taper angle. The aperture portion has a radiation aperture connected to one end of the tapered line portion. A size of one side of the aperture end plane of the aperture portion is set to be equal to or higher than a quarter wavelength of the minimum operating frequency of the antenna apparatus.
US07872609B2 Circular waveguide antenna and circular waveguide array antenna
A low-cost, compact circular waveguide array antenna which improves an antenna reflection loss characteristic and enables an improvement in radiation characteristics, particularly radiation gain. The circular waveguide array antenna includes feeding portions which feed electromagnetic waves to one ends of circular waveguides and radiation apertures which radiate the electromagnetic waves at the opposite ends. Each circular waveguide includes a conical horn, with a diameter of a feeding side aperture at the feeding portion end being a, a diameter of the radiation aperture being d, which is larger than the diameter a of the feeding side aperture, and an opening angle being 2α. If a wavelength of a central frequency of an employed frequency band is λ, then a value of α, which is half of the opening angle 2α, is set between 0.8×Arcsin(0.1349114/(d/λ)) and 1.2×Arcsin(0.1349114/(d/λ)).
US07872608B2 Dual band WLAN antenna
An antenna system includes first, second and third antennas that are arranged on a substrate. The first, second and third antennas include an arc-shaped element having a concave side and a convex side and a conducting element that extends substantially radially from a center of said concave side.
US07872602B2 Time to digital converting circuit and related method
A TDC circuit includes: a first delay circuit, including at least one first delay stage for delaying a first input signal to generate a first output signal; a second delay circuit, including at least one second delay stage for delaying a second input signal to generate a second output signal; a first counter, for computing the first output signal to generate a first counter value; a second counter, for computing the second output signal to generate a second counter value; and a comparator, for comparing the first counter value and the second counter value to generate a comparing result signal; wherein the first delay stage has a larger delay amount than the second delay stage, the first counter starts before the second counter, and the comparator outputs the comparing result signal when the second counter value falls within a predetermined range of the first counter value.
US07872601B2 Pipeline analog-to-digital converter
Disclosed is a designed and implemented 12-bit 70 Msps pipeline analog-to-digital converter. Two adjacent blocks operate at opposite clock phases to reduce the chip size and power consumption. Since the opposite clock phases are designed to be provided by external devices, the timing between these two clock phases must be accurate. Note that the architecture of pipeline ADC consists of four stages, divided into two groups, wherein two adjacent stages in each group share one 3-bit flash ADC, hence only two 3-bit flash ADCs are required in this scheme. Therefore, there are 6-bit signal produced from each 3-bit flash ADC within one clock phase which consists of two opposite clock phases. And within the same period, the total output of the pipeline analog-to-digital converter would be 12-bit. From the simulation results, when the sampling rate is 70 Msps, this converter consumes 155 mW (TBV) at a ±1.8 V supply.
US07872600B2 Low cost analog to digital converter and a method for converting an analog signal to a digital signal
The present invention relates to a low cost analog to digital converter (ADC) and a method for converting an analog signal to a digital signal. The method includes the steps of: outputting a pulse modulation signal according to a digital value; performing a low-pass filtering to the pulse modulation signal to obtain a pulse averaged voltage; mixing a first proportion of the pulse averaged voltage and a second proportion of a voltage under test to obtain a composite voltage; comparing the composite voltage with a threshold voltage and adjusting the first digital value such that the composite voltage approaches the threshold voltage; and performing a complement operation to the digital value to obtain an analog to digital value corresponding to the voltage under test.
US07872596B2 Dictionary-based compression
A method and apparatus for compressing data is described. A compressor builds a dictionary associated with the characters in the input string. A table in the dictionary is generated by looking backward from a current character being encoded in the input string to determine the last time the most recent one or more characters have occurred. The compressor determines whether the following characters at a point of encoding matches the next character being encoded.
US07872595B2 Method and apparatus for inputting an alphabet character in a terminal with a keypad
A terminal with a keypad enables a user to input an alphabet character through the keypad at high speed without modification of the keypad. The terminal comprises receiving a first input character in an alphabet input mode; waiting for a key input for at least one second input character succeeding the first input character; upon receiving a key input for the second input character, searching for a priority table in which a displaying order of a succeeding alphabet character is designated; and controlling a displaying order of the second input character according to the priority table.
US07872589B2 Apparatus and method for controlling flight deck light intensity
A system for controlling lighting of an instrument panel has a sensor for monitoring activity near the instrument panel. A lighting control unit is coupled to the sensor and a lighting system of the instrument panel. The lighting control unit controls the light intensity of the lighting system. The lighting control unit increases the intensity of the lighting system when the sensor monitors activity near the instrument panel.
US07872587B2 Display system for an agricultural harvesting machine
A control system for a combine harvester having a crop processing system with a control panel for enabling an operator of the combine harvester to set a plurality of operating parameters of the crop processing system that affect the harvesting performance, and a plurality of sensors for determining prevailing values of crop quality parameters. The control system includes a data processor having a display for communicating information visually to the operator and acts to determine when a crop quality parameter exceeds an unacceptability threshold. Following such determination, the control system displays to the operator an operating parameter of which adjustment is recommended in order to restore the crop quality parameter to an acceptable value. The recommended operating parameter is derived from data stored in a look-up table within the data processor.
US07872582B1 RFID tag chips and tags with alternative memory lock bits and methods
RFID tag circuits, tags, and methods are provided for using alternative memory lock bits. A pointer in tag memory is configured to point to one or the other of the alternative lock bits associated with a section of the memory for performing a function in response to a reader command. Upon receiving the reader command, the tag first checks the pointer and performs the function based on which lock bit(s) is selected.
US07872576B2 Switching device and method
Embodiments of the present invention are directed to a method and device for operating a circuit. In particular, embodiments of the present invention are directed to a method and device that may allow an observant Jew to operate a circuit on the Sabbath or on the Jewish holidays. Embodiments of the present invention may include a combination of mitigating factors which may allow an observant Jew to operate a circuit on the Sabbath or on a Jewish holiday.
US07872573B2 Apparatus and method for providing weather and other alerts
An apparatus for providing location-specific alert information associated with an alert condition relevant to a geographical area may include a receiver adapted to receive transmissions comprising formatted text on a communication channel of a wireless bi-directional communication network; a peripheral device operable to indicate an alert condition, including displaying the formatted text; and a controller communicatively coupled to the receiver and the peripheral device. The controller is operable to monitor a communication channel of the network for the receipt of a transmission of location-specific alert information from a transmitter servicing a geographical area and to operate the peripheral device in response to the reception of the transmission of the location-specific alert information to display the formatted text. The location-specific alert information is broadcast within the geographical area by at least one transmitter of the wireless bi-directional communication network having communication channels and transmitters which are each positioned to provide communication services to specific geographical areas serviced by the communication network.
US07872570B2 Informational display for rapid operator perception
The present invention is an informational display that utilizes cognitive science in the appearance and geographical location of a plurality of gauges and indicators located within the display. Through the use of color, size, depth, location and appearance, information transmitted to an operator through the present invention is rapidly perceived and interpreted. Such rapid interpretation of information by the present invention allows an operator to use a vehicle or the like in a more safe and lawful manner than that of traditional dashboard displays.
US07872566B1 Radio frequency identification device power-on reset management
Apparatus, systems, and methods may include providing a power-on reset function to many types of receiving circuitry, including radio frequency identification (RFID) tag processing circuitry. Thus, the power-on reset function may be realized by applying a supply voltage to a power-on reset circuit coupled to RFID tag processing circuitry. Operations may include sensing a first current substantially independent of the supply voltage, sensing a second current substantially dependent on the supply voltage, and indicating a power-on reset condition based on a comparison between the first current and the second current. Additional apparatus, systems, and methods are disclosed.
US07872561B2 Composite transformer and insulated switching power source device
An E-shaped transformer core has a middle leg and one pair of outer legs and on opposite sides with respect to the middle leg. A first pair of coils including at least two coils are wound around the middle leg so that a power transmission transformer unit is formed. The outer leg is divided into two outer leg portions and with a space therebetween allowing coil wiring therebetween, and a second pair of coils including two coils are respectively wound around the respective two outer leg portions and so as to have mutually opposite winding directions, so that a signal transmission transformer unit is formed.
US07872560B2 Independent planar transformer
A high-efficiency independent planar transformer comprises a pair of up-and-down symmetrical soft ferrite magnetic cores; a primary winding comprising at least one printed circuit board each having a multi-layer structure having at least two layers to form the inductor winding with at least four turns; and two secondary windings comprising at least two planar copper plates or two printed circuit boards. The primary winding and the secondary windings are electrically connected to the main circuit board via terminals. By means of the unique output structure, in the primary winding, two kinds of different output connection structures of the inductor winding can be formed by upward disposing the component side or the solder side of the printed circuit board. In the secondary winding, the inductor winding outputs in series and parallel connections can be accomplished by means of the output terminals or the short-circuit connection with the main circuit board.
US07872559B2 Winding method and coil unit
A rectangular coil unit 1 is manufactured in such a manner that four wires 2 are simultaneously regularly wound on four outer surfaces of a bobbin 3 having a rectangular section so that the wires 2 advance obliquely together for a lane change corresponding to 0.5 wire on one (a lower surface side) of a pair of parallel surfaces of the four outer surfaces of the bobbin 3 and for a lane change corresponding to 3.5 wires on the other one (an upper surface side) of the parallel surfaces.
US07872556B2 Magnetic element
A magnetic assembly includes a mounting substrate and a magnetic element mounted on the mounting substrate. The magnetic element includes a drum core provided with a flange portion at each end of a winding shaft, a coil wound on the winding shaft, and a shield core engaged with the drum core, the shield core including an engagement portion having a shape that corresponds to the shape of a portion of the outer circumference of at least one of the flange portions so that the engagement portion mates with the at least one flange portion.
US07872553B2 Magnetic bearing element
The invention relates to a magnetic bearing element having at least one annular permanent magnet (2, 3) that is surrounded by an annular binding band (5), which element is characterized in that the permanent magnet (2, 3) is divided at least one location (4) and spaced apart there.
US07872552B2 Method and device for the secure operation of a switching device
A method and a device for the secure operation of a switching device are disclosed, including at least one main contact which can be switched on and off and which includes contact pieces and a displaceable contact bridge, and also at least one control magnet which includes a displaceable anchor. The anchor acts upon the contact bridge when it is switched on or off such that the corresponding main contact is opened and closed. In at least one embodiment, the method includes: a) the displaceable contact bridge of the at least one main contact recognizes when an opening point has been exceeded after being switched off, and b) the additional operation of the switching device is interrupted, according to a predetermined duration of time, when the opening point is not exceeded.
US07872550B2 Vertical coupling structure for non-adjacent resonators
A vertical coupling structure for non-adjacent resonators is provided. The vertical coupling structure has a first resonator and a second resonator. At least one side of the first resonator is formed as a first bent extension structure, and the first bent extension structure includes a slot. The second resonator is not adjacent to the first resonator, and the side of the second resonator opposite to the first bent extension structure of the first resonator further includes a slot, such that the two sides are electrically connected.
US07872546B1 Multi mode modulator and method with improved dynamic load regulation
A dual mode modulator is proposed for driving a power output stage having a serial connection of high-side power FET and low-side power FET. The dual mode modulator includes a PWM modulator operating under a PWM-frequency and a PFM modulator for controlling the power output stage. To improve the dynamic load regulation of the dual mode modulator, a dynamic frequency booster can be added to the dual mode modulator to boost up the PWM-frequency from its normal operating frequency during a PFM-to-PWM mode transition period. Secondly, a dynamic slew rate booster can be added to boost up an error amplifier slew rate of the PWM modulator from its normal operating slew rate during the mode transition period. Thirdly, a dynamic turn-off logic circuit can be added to turn off the low-side power FET during the mode transition period.
US07872544B2 Modulation/demodulation apparatus and modulation/demodulation method
A modulation/demodulation apparatus according to an embodiment of the present invention includes a sine wave generating circuit configured to output two sine waves which are orthogonal to each other and have equal amplitude, an orthogonal modulator connected to the sine wave generating circuit and configured to modulate the sine waves to generate a modulated signal, a detecting section configured to detect amplitude fluctuation in the modulated signal, a multiplying section configured to multiply the modulated signal and the amplitude fluctuation detected by the detecting section together, and an orthogonal demodulator configured to demodulate the modulated signal multiplied with the amplitude fluctuation by the multiplying section to generate a demodulated signal.
US07872543B2 Bi-polar modulator
A bi-polar modulator that can perform quadrature modulation using amplitude modulators is described. In one design, the bi-polar modulator includes first and second amplitude modulators and a summer. The first amplitude modulator amplitude modulates a first carrier signal with a first input signal and provides a first amplitude modulated signal. The second amplitude modulator amplitude modulates a second carrier signal with a second input signal and provides a second amplitude modulated signal. The summer sums the first and second amplitude modulated signals and provides a quadrature modulated signal that is both amplitude and phase modulated. The first and second input signals may be obtained based on absolute values of first and second modulating signals, respectively. The first and second carrier signals have phases determined based on the sign of the first and second modulating signals, respectively. Each amplitude modulator may be implemented with a class-E amplifier.
US07872542B2 Variable capacitance with delay lock loop
An integrated circuit includes a delay lock loop (DLL) circuit that generates incremental delay line signals and a delay line output signal based on a received clock signal. A pulse-width modulation (PWM) control module generates a PWM control signal. A tunable circuit having variable capacitance is controlled based on the delay line output signal, the PWM control signal, and one of the incremental delay line signals.
US07872540B2 Oscillator device and transmitter module using same
An oscillator device includes a resonator including a coil and a capacitor connected to the coil in parallel; and an oscillator connected to the resonator. Electric waves are emitted from the coil to at least one receiving antenna of the receiver while the oscillator device changes position and direction over time. The coil has an outer diameter and a total length which is approximately the same as the outer diameter.
US07872539B1 Energy efficient waveform generation using tuned resonators
A power source, a primary inductor, a load capacitance, and one or more tuned branch resonators and switching devices are coupled to generate pulses which represent a superposition of sinusoidal waveforms. The primary inductor is connected between the power source and the load. At the start of each cycle the load is coupled to ground and each tuned-branch resonators is reinitialized to re-energize the circuits and to stabilize the waveform when the frequencies of the sinusoidal waveforms are non-periodic.
US07872536B2 Variance correction method, PLL circuit and semiconductor integrated circuit
A variance correction method includes generating a reference current depending on a resistance within a lowpass filter and outputting the reference current to a voltage controlled oscillator, and correcting characteristics of the lowpass filter and a gain of the voltage controlled oscillator based on an output clock of the voltage controlled oscillator.
US07872533B2 Leakage current reduction in a power regulator
A regulator with decreased leakage and low loss for a power amplifier is described. Switching circuitry is used to connect the regulator input bias to a bias control voltage when the power amplifier is to be operated in an on condition or to a voltage generator when the power amplifier is to be operated in an off condition.
US07872526B2 Balanced amplifying device having a bypass branch
A balanced amplifier includes a bypass branch (19), termination elements (TE1, TE2) and an amplifying section (10). The section (10) includes amplifiers (A1, A2), first coupling/splitting unit (14) having a first input signal receiving port (14a), a second port (14b) connected to a termination element (TE1), a third port (14c) connected to a first amplifier (A1), and a fourth port (14d) connected to a second amplifier (A2). The section (10) also includes second coupling/splitting unit (16) having a first port (16a) connected to first amplifier (A1), a second port (16b) connected to second amplifier (A2) and a third port (16c) connected to a termination element (TE2). The second coupling/splitting unit (16) combines signals from amplifiers (A1, A2) as output signals on a fourth port (16d) for supply to a signal output (O). The branch (18) is connected to the second port (14b) of the first coupling/splitting unit (14) and provides bypass signals to output (O).
US07872520B2 Semiconductor integrated circuit device
A semiconductor integrated circuit device which substantially reduces drop in a supply voltage generated by a regulator and ensures stable supply of a supply voltage with high efficiency and high accuracy. In the device, a memory power supply includes a plurality of transistors and an error amplifier. In the transistors, source pads and drain pads are alternately arranged in a row along one edge of a semiconductor chip in a peripheral area of the chip. Transistor gates are formed in parallel with the alternately arranged source pads and drain pads (so that the longitudinal direction of the gates is parallel to the direction of the arrangement of the source pads and drain pads). Consequently, the length of wirings coupled to drains and sources is shortened and the sheet resistance is decreased.
US07872519B2 Voltage divider circuit
Provided is a voltage divider circuit for dividing an input voltage in accordance with a predetermined ratio with high accuracy, in which a source current does not flow from a voltage source and a sink current does not flow into the voltage source. The voltage divider circuit according to the present invention includes: a first resistor; a constant current circuit for outputting a current flowing through the first resistor correspondingly to an input voltage as a constant current; a first current mirror circuit, in which the constant current becomes an input current, for outputting a first output current; a second current mirror circuit, in which the first output current becomes an input current, for outputting a second output current; and a second resistor connected to an output terminal to which the second output current of the second current mirror circuit is output, in which a divided voltage, which is a potential difference between both ends of the second resistor, is adjusted by a current mirror ratio between the first current mirror circuit and the second current mirror circuit, and a resistance ratio between the second resistor and the first resistor.
US07872510B2 Duty cycle correction circuit of semiconductor memory apparatus
A duty cycle correction circuit of a semiconductor memory apparatus includes a duty ratio correcting unit configured to correct a duty ratio of a clock signal according to levels of a first reference voltage and a second reference voltage, and to output the clock signal as a correction clock signal, a duty ratio detecting unit configured to count first and second counting signals in response to a duty ratio of the correction clock signal when a pump enable signal is enabled, a pump enable signal generating unit configured to generate the pump enable signal in response to the duty ratio of the correction clock signal, and a reference voltage generating unit configured to generate the first and second reference voltages in response to the first and second counting signals.
US07872504B2 Inverter and logic device comprising the same
The inverter includes a driving transistor and a loading transistor having channel regions with different thicknesses. The channel region of the driving transistor may be thinner than the channel region of the load transistor. A channel layer of the driving transistor may have a recessed region between a source and a drain which contact both ends of the channel layer. The driving transistor may be an enhancement mode transistor and the load transistor may be a depletion mode transistor.
US07872503B2 Combinatorial logic circuit
It is disclosed a combinatorial logic circuit comprising a first logic block (B1) coupled to a supply terminal (VDD) via a first resistor means (RI) and via a second resistor means (R2) for receiving respective first and second supply currents (111, 112). The circuit further comprises a second logic block (B2) coupled to the supply terminal (VDD) via the first resistor means (R1) and via the second resistor means (R2) for receiving respective third and fourth supply currents (122, 121). A first output terminal (Q−) coupled to the first block (B1) and to the first resistor means (R1). A second output terminal (Q+) coupled to the second logic block (B2) and to the second resistor means (R2). A first current source (I0) coupled to at least one of the first output terminal (Q−) and/or second output terminal (Q+) for providing a first supply current (I1) through the first resistor means (R1), which is substantially equal to a second supply current (I2) through the second resistor means (R2).
US07872501B2 Device for transforming input in output signals with different voltage ranges
Arrangement for accepting an input signal in a first voltage range and producing an output signal in a second voltage range. A transition detection circuit (230) detects a transition from a high level to a low level of the input signal and a control circuit (245) operates a first FET to produce the low level of the output signal. A second FET is operated by the high level of the input signal to output the high level of the output signal.
US07872499B2 Level shift circuit, and driver and display system using the same
Disclosed is a level shift circuit that includes a first level shifter which is connected between an output terminal and a first power supply terminal that supplies a first voltage and sets the output terminal to a level of the first voltage when an input signal received at an input terminal assumes a first value; a second level shifter which is connected between the output terminal and a second power supply terminal that supplies a second voltage and sets the output terminal to a level of the second voltage when the input signal assumes a complementary value of the first value; and a feedback control unit that performs control of deactivating the first level shifter during a predetermined time interval including a point of time when the input signal is supplied when it is detected that the output terminal immediately before the input signal is received at the input terminal assumes the first voltage level. When the input signal supplied in the predetermined time interval assumes a value that sets the output terminal to the second voltage level, the second level shifter sets the output terminal to the second voltage level with the first level shifter deactivated.
US07872496B2 Method of mapping a user design defined for a user design cycle to an IC with multiple sub-cycle reconfigurable circuits
Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes a logic circuit for receiving input data sets and configuration data sets and performing several functions on the input data sets. Each configuration data set specifies a particular function that the logic circuit has to perform on the input data set. The IC also includes a connection circuit for supplying sets of the configuration data to the logic circuit at a particular rate for at least a particular time period. At least two supplied configuration data sets are different and configure the logic circuit to perform two different functions on the input data.
US07872495B1 Programmable termination
A unit cell for a programmable termination circuit in an integrated circuit and a method for programming such termination circuit are described. In an embodiment, such unit cells may have three n-type and three p-type transistors. A first transistor is coupled to receive a first float control signal. A second transistor is coupled to receive a second float control signal. The third and fourth transistors are coupled to receive a first termination voltage control signal. The fifth and sixth transistors are coupled to receive a second termination voltage control signal. The first float control signal and the second float control signal are a pair of complementary signals.
US07872494B2 Memory controller calibration
Components of a memory controller are calibrated in a select sequence to compensate for variances in skew and signal level variations. The offset bias of the receiver of the I/O cell and the termination resistance of the I/O cell are calibrated. The duty cycles of the transmit path and receive path associated with the I/O cell can be calibrated using the calibrated receiver. In one aspect, the driver of the I/O cell can be calibrated prior to calibrating the receiver. Performing the calibration processes of the memory controller in one of the particular sequences described herein improves the timing budgets for the signaling conducted by the memory controller.
US07872491B2 Noise filter circuit, dead time circuit, delay circuit, noise filter method, dead time method, delay method, thermal head driver, and electronic instrument
A noise filter circuit includes a first inverter circuit that receives a signal based on an input signal, a second inverter circuit that receives a signal based on the input signal, and a latch circuit that receives signals based on a signal output from the first inverter circuit and a signal based on a signal output from the second inverter circuit as a set signal and a reset signal. Each of the first inverter circuit and the second inverter circuit includes a first-conductivity-type transistor and a second-conductivity-type transistor, the capability of one of the first-conductivity-type transistor and the second-conductivity-type transistor being lower than the capability of the other of the first-conductivity-type transistor and the second-conductivity-type transistor.
US07872488B2 Tester for testing semiconductor device
A tester for testing a semiconductor device is disclosed. In accordance with the tester of the present invention, the tester is configured to have different drive signal path and input/output signal path wherein the drive signal path has a fly-by structure, i.e. a daisy chain structure and the input/output signal path has a star-stub structure such that more DUTs may be tested simultaneously and an integrity of the signals is secured.
US07872487B2 Semiconductor wafer having a multitude of sensor elements and method for measuring sensor elements on a semiconductor wafer
In the measurement of sensor elements in a wafer composite, whereby non-electric stimuli are to be applied to the sensor elements, a semiconductor wafer having a multitude of sensor elements, each sensor element having a voltage supply connection, a grounded connection, and at least one sensor signal output, is configured such that a bus system is integrated in the semiconductor wafer, to which bus system at least the grounded connections of the sensor elements are connected and via which a supply voltage may be applied to the sensor elements, and that each sensor element is equipped with at least one controllable switching element for selecting the sensor element, so that only a selected sensor element supplies a sensor signal to a diagnosis device.
US07872485B2 System and method for use in functional failure analysis by induced stimulus
A scanning/imaging system wherein an external stimulus is used for exciting a device under test (DUT). A stimulus source is included for providing a stationary stimulus with a controllable spot size to a device under test (DUT), the controllable spot size covering a portion of the DUT for excitation by the stationary stimulus. A sensor is operable for capturing at least one of a functional response signal and an optical image signal emanating from the DUT portion. A linear positioning device is operable to facilitate scanning of remaining portions of the DUT until a predetermined area thereof has been traversed. A controller is operably coupled to the linear positioning device, stimulus source and the sensor for providing the overall control thereof.
US07872484B2 Chip pin test apparatus
A test apparatus includes a printed circuit board, a chip carrier socket, and a display circuit. The chip carrier socket includes a space to receive a chip including a plurality of pins, a plurality of contact terminals, and a grounded ground portion. The display circuit includes a power supply and a plurality of light-emitting elements. When the chip is received in the space, the ground portion contacts a middle portion of each pin. When a pin of the chip is normal, a distal end of the normal pin contacts a corresponding contact terminal to connect a corresponding light-emitting element to the ground portion, causing the light-emitting element to light up. When a pin of the chip is askew, a distal end of the askew pin cannot contact a corresponding contact terminal, the corresponding light-emitting element will not light up.
US07872479B2 Leak testing and leak localization arrangement for leak testing and leak localization for flat roofs or the like
In a leak testing and leak localization arrangement for leak testing and localization for flat roofs or the like which are sealed by at least one electrically insulating sealing web (6), at least one voltage source (12) is applied between an upper side of the sealing web and below an underside of the sealing web. The upper side of the sealing web is sampled by means of a measuring device (9) provided with two measurement sensors (10, 11). In order to achieve reliable leak testing and precise leak localization with contact being made in an uncomplicated manner with the voltage source (12), web-shaped electrically conductive material is arranged on the underside of the sealing web (6) and is connected to one terminal of the voltage source (12). For this purpose, at least one metal grating web is provided as the web-shaped electrically conductive material, which web can be laid easily and is non-combustible and durable.
US07872475B2 MR imaging with an RF pulse producing reduced magnetization transfer
A system and method are provided herein for designing and transmitting RF pulses which cause a reduced off-resonance magnetization transfer saturation. An RF pulse shape may be optimized according to a set of Bloch solutions defining a desired magnetization profile. An RF pulse may be transmitted according to this optimized shape according to a k-space trajectory which traverses a high amplitude portion of the RF pulse more times than one or more low amplitude portions. In addition, a generally alternating slice select gradient may be applied during transmission of the RF pulse.
US07872473B2 Compact atomic magnetometer and gyroscope based on a diverging laser beam
An atomic magnetometer that simultaneously achieves high sensitivity, simple fabrication and small size. This design is based on a diverging (or converging) beam of light that passes through an alkali atom vapor cell and that contains a distribution of beam propagation vectors. The existence of more than one propagation direction permits longitudinal optical pumping of atomic system and simultaneous detection of the transverse atomic polarization. The design could be implemented with a micro machined alkali vapor cell and light from a single semiconductor laser. A small modification to the cell contents and excitation geometry allows for use as a gyroscope.
US07872470B2 Motor speed sensor assembly for detecting rotational direction and speed
A drive assembly for a vehicle door is provided. The drive assembly includes a motor having a driving member. The drive assembly further includes a housing having a shaft rotatably received therein. The drive assembly further includes an input member being rotatably received upon the shaft. The input member is operatively associated with the driving member. The drive assembly further includes a rotor fixedly secured to the shaft. The drive assembly further includes first and second Hall effect sensor modules mounted to the housing in a facing spaced relationship with respect to the plurality of teeth of the rotor that generate first and second signals, respectively. The first and second signals have a quadrature relationship with respect to one another and indicate a rotational direction of the rotor when the plurality of teeth are rotating past the first and second Hall effect sensor modules.
US07872464B2 Hand held arc fault testing system
A testing system includes a hand-held transmitter that plugs into a receptacle electrically coupled to a selected branch circuit. The transmitter includes a circuit effective to test an arc fault circuit interrupter electrically coupled to the branch circuit by creating a first pulse on the branch circuit that is effective to trip the arc fault circuit interrupter. The transmitter can perform at least one additional test including: determining whether the receptacle is wired properly; determining a location of a circuit interrupting device electrically coupled to the branch circuit by creating a second pulse on the branch circuit that can be sensed by a receiver located proximately to the respective circuit interrupting device and broadly tuned about a frequency of the second pulse; and testing a ground fault circuit interrupter electrically coupled to the branch circuit by creating a third pulse on the branch circuit that is effective to trip the ground fault circuit interrupter.
US07872461B2 Reverse current stopping circuit of synchronous rectification type DC-DC converter
A reverse current stopping circuit includes a synchronous rectification device, a comparator for detecting a reverse current of an inductor, the synchronous rectification device being turned off when the reverse current is detected by the comparator, a reverse current detector circuit for detecting a switching terminal voltage after the synchronous rectification device is turned off, thereby determining a value of the inductor current to decide whether the inductor current is flowing in a reverse direction or a forward direction, and a memory unit for receiving a predetermined output signal from the reverse current detector circuit in accordance with a result of the reverse current detector circuit, and outputting a control signal for an offset voltage in accordance with the predetermined output signal. The offset voltage is changed in accordance with the control signal so as to adjust the inductor current to zero when the synchronous rectification device is turned off.
US07872456B2 Discontinuous conduction mode pulse-width modulation
One embodiment of the invention includes a power regulator system. The system includes a switching system configured to generate an output voltage across a load based on a high-side switch coupling a power voltage to an output at an edge-trigger of a PWM control signal having an activation pulse-width of the high-side switch. The system also includes a switch driver system configured to set a duty-cycle of the PWM control signal such that the activation pulse-width of the PWM control signal is based on the power regulator system operating in one of a continuous conduction mode (CCM) and a discontinuous conduction mode (DCM). The edge-trigger of the PWM control signal can occur based on a relative magnitude of the output voltage and the power voltage while operating in the DCM.
US07872455B2 Low-power voltage reference
A circuit provides a voltage reference using very low power. It can also be used as a shut regulator for a quiescent current as low as 1.5 μA. It includes a transconductance amplifier, a gain stage, and a power transistor. One embodiment of this invention utilizes a work function difference between p+ gate and n+ gate to generate a predetermined reference voltage. In another embodiment of this invention, the predetermined reference voltage can be pre-adjusted using gate materials with different work functions.
US07872454B2 Digital low dropout regulator
A low dropout (LDO) regulator for generating an output voltage on an output from an input voltage of an input source. The LDO regulator including a switch module to generate the output voltage. The switch module including at least two parallel connected switches responsive to corresponding switch control signals to regulate a flow of energy from the input source to the output. Each of the switches having an on-state and an off-state. A digital controller to sense the output voltage and in response to generate the switch control signals such that the output voltage is regulated to a predetermined amplitude.
US07872451B2 Apparatus for charging on-vehicle battery and apparatus for controlling generating operation of on-vehicle generator
An on-vehicle charging apparatus charges a battery mounted on the vehicle. In the apparatus, a generator generates electric power to output voltage for charging the battery and a controller, which is located outside the generator, outputs a pulse signal for controlling a generated state of the generator. A reception device receives the pulse signal outputted from the controller. The received signal is subjected to filtering at a filter, where pulse signals whose cycles are different from a predetermined cycle are removed. Further, using the outputted pulse signal from the filter, a duty ratio of the pulse signal is calculated. A voltage outputted from the generator is regulated based on the calculated duty ratio.
US07872448B2 Power supply system and portable equipment using the same
A power supply system for portable equipment has a lithium-ion secondary battery as a power supply, a temperature detection portion for detecting a temperature of the power supply, a voltage detection portion for detecting a voltage of the power supply, a memory portion, and a forced discharge portion. The memory portion stores a control operating temperature, a control operating voltage and a control termination voltage. The forced discharge portion recognizes an abnormality of the power supply when the temperature of the power supply is at least the control operating temperature and the voltage of the power supply is at least the control operating voltage. Then, the forced discharge portion electrifies the notification portion and makes it inform a message indicating that the abnormality is being avoided. The forced discharge portion forcedly discharges the power supply until the voltage of the power supply reaches the control termination voltage.
US07872445B2 Rechargeable battery powered portable electronic device
There is provided a planar inductive battery charging system designed to enable electronic devices to be recharged. The system includes a planar charging module having a charging surface on which a device to be recharged is placed. Within the charging module and parallel to the charging surface is at least one and preferably an array of primary windings that couple energy inductively to a secondary winding formed in the device to be recharged. The invention also provides secondary modules that allow the system to be used with conventional electronic devices not formed with secondary windings.
US07872440B2 Controller of electric motor
A controller of an electric motor for improving operation efficiency in performing electric conducting control of the electric motor of an axial air-gap type is provided. Therefore, the controller of the electric motor (3) of the axial air-gap type including a rotor (11) having a permanent magnet, a first stator (12a) and a second stator (12b) oppositely arranged through the rotor (11) in a rotation axis direction of the rotor (11), and armature windings (13a, 13b) mounted to the first stator (12a) and the second stator (12b) has an electric current command determining section (30) for switching between a both-side stator driving mode for conducting a driving electric current to both the armature winding (13a) of the first stator (12a) and the armature winding (13b) of the second stator (12b), and a one-side stator driving mode for conducting the driving electric current to only the armature winding (13a) of the first stator (12a) in accordance with a request value Tr_c of output torque of the electric motor (3).
US07872438B2 Initial pole position estimating apparatus and method for AC synchronous motor
The present invention provides an initial pole position estimating apparatus and method for an AC synchronous motor without using magnetic pole detector. The initial pole position estimating apparatus includes a thrust force or torque pattern generating portion for generating a thrust force or torque pattern, a pole position command generating portion for generating a pole position command, and a position detecting portion for detecting a position of the AC synchronous motor. The initial pole position estimating apparatus can estimate an initial pole position in a short time with high precision without depending on a fluctuation in a load. The initial pole position estimating apparatus further includes a pole position correcting portion (8) for correcting the pole position command and a thrust force or torque pattern correcting portion (9) for correcting the thrust force or torque pattern, and an initial pole position is estimated through a repetitive correction.
US07872436B2 Control method for a robot
An apparatus, a method and a control system for controlling an industrial robot with at least one axis of rotation and/or translation. The robot includes at least one actuator or motor at each of the axes for driving a movement of an arm of the robot and at least one sensor at each of the rotatable shafts. A dither-signal generator for generation of a periodic signal is used to provide a varying dither signal to a servo of the actuator. Automatic adaption of the dither signal is provided. A computer program for carrying out the method and a graphical user interface.
US07872430B2 Solid state lighting panels with variable voltage boost current sources
A lighting panel system includes a lighting panel having a string of solid state lighting devices and a current supply circuit having a voltage input terminal, a control input terminal, and first and second output terminals coupled to the string of solid state lighting devices. The current supply circuit is configured to supply an on-state drive current to the string of solid state lighting devices in response to a control signal. The current supply circuit includes a charging inductor coupled to the voltage input terminal and an output capacitor coupled to the first output terminal. The current supply circuit is configured to operate in continuous conduction mode in which current continuously flows through the charging inductor while the on-state drive current is supplied to the string of solid state light emitting devices.
US07872418B2 Light emitting device and method for manufacturing the same
By using a light emitting device including a substrate and a light emitting unit, the light emitting unit including: a plurality of light emitting elements that are mounted on substrate and electrically connected to external electrodes; a first sealing member layer containing a first fluorescent material, formed to cover light emitting elements; and a second sealing member layer containing a second fluorescent material, formed on first sealing member layer, as well as a method for manufacturing thereof, it becomes possible to provide a light emitting device capable of suppressing color shifts and the like by the fluorescent materials, and of being easily manufactured, as well as a method for manufacturing the same.
US07872411B2 Organic electroluminescence device using a copolymer and a phosphorescent compound
An organic electroluminescence device including one layer or two or more layers of organic layer sandwiched between an anode and a cathode. At least one of the organic layers includes a phosphorescent compound and a polymer. The polymer has a structural unit derived from a monomer represented by formula (1) as defined herein, and a structural unit derived from a monomer having heterocycle(s) containing two or more heteroatoms.
US07872409B2 White light LED
A white light LED is disclosed. The white light LED includes a dual-wavelength chip and an optical thin film. The dual-wavelength chip generates a first wavelength light and a second wavelength light. The optical thin film is disposed above the dual-wavelength chip. The optical thin film can partially be a quantum well thin film. Therefore, the quantum well thin film can be excited by the first wavelength light and/or second wavelength light to generate a third wavelength light. The optical thin film further comprises a plurality of windows to let the first and second wavelength lights pass through. By predetermining a ratio of the quantum well thin film area and the window area that belong to the optical thin film, a lumen ratio of the first, the second, and the third wavelength lights can be adjusted to realize white lights of different color temperatures.
US07872405B2 Low cost spark plug manufactured from conductive loaded ceramic-based materials
Spark plug devices are formed of a conductive loaded resin-based material. The conductive loaded resin-based material comprises micron conductive powder(s), conductive fiber(s), or a combination of conductive powder and conductive fibers in a base resin host. The percentage by weight of the conductive powder(s), conductive fiber(s), or a combination thereof is between about 20% and 50% of the weight of the conductive loaded resin-based material. The micron conductive powders are metals or conductive non-metals or metal plated non-metals. The micron conductive fibers may be metal fiber or metal plated fiber. Further, the metal plated fiber may be formed by plating metal onto a metal fiber or by plating metal onto a non-metal fiber. Any platable fiber may be used as the core for a non-metal fiber. Superconductor metals may also be used as micron conductive fibers and/or as metal plating onto fibers in the present invention.
US07872403B2 Method for manufacturing piezoelectric film element, and piezoelectric film element
A method for manufacturing a piezoelectric film element includes foursteps. The first is to form a bottom electrode on a Si substrate. The second is to form a seed layer with a layered perovskite structure on the bottom electrode. The third is to form a Bi4Ti3O12—BaBi4Ti4O15 based piezoelectric film on the seed layer. The final step is to form an top electrode on the piezoelectric film.
US07872402B2 Perovskite-oxide laminates, and piezoelectric devices, and liquid discharge devices containing the same
A perovskite-oxide lamination constituted by a substrate and one or tore first films of a first oxide of a perovskite type and one or more second films of a second oxide which are alternately formed over the substrate. The first oxide has a composition expressed as ABO3, the second oxide has a composition expressed as CDO3, each of A and C represents one or more A-site elements which are one or more metal elements, each of B and D represents one or more B-site elements which are one or more metal elements, O represents oxygen, and the second oxide is unable to be formed to have a perovskite crystal structure at normal pressure without a thickness limitation. The one or more first films and the one or more second films may contain inevitable impurities.
US07872401B2 Piezoelectric vibrator with hermetically closed casing and filler comprising non-spherical conductive particles
There is provided a piezoelectric vibrator 1 that includes a base substrate 2, a lid substrate 3, a piezoelectric vibrating reed 4, a pair of external electrodes 38 and 39, a pair of through electrodes 32 and 33, and routing electrodes 36 and 37. Both surfaces of the base substrate 2 are polished. The lid substrate 3 includes a recess 3a for a cavity C and is bonded to the base substrate. The piezoelectric vibrating reed 4 is bonded to the upper surface of the base substrate so as to be received in a cavity that is formed between the base substrate and the lid substrate. The pair of external electrodes 38 and 39 is formed on the lower surface of the base substrate. The pair of through electrodes 32 and 33 is formed so as to pass through the base substrate, maintains airtightness in the cavity, and is electrically connected to the pair of external electrodes, respectively. The routing electrodes 36 and 37 are formed on the upper surface of the base substrate and electrically connect the pair of through electrodes to the bonded piezoelectric vibrating reed. The through electrodes are formed by the hardening of paste that contains a plurality of nonspherical metal fine particles.
US07872400B2 Ultrasonic device with a disk-shaped resonator
The present invention refers to an ultrasonic device comprising an ultrasound transducer; and a disk-shaped metallic low-frequency ultrasound (NFLUS) resonator being mechanically connected with the ultrasound transducer on one side of the resonator; a container with an opening on its bottom side and being arranged on the other side of the disk-shaped resonator such that the opening is facing the disk-shaped resonator; an elastic sealing element arranged between the disk-shaped resonator and the container for sealing the container around the opening; and means for supplying a pressing force such that the container is tightened on the resonator during ultrasonication, but can be repeatedly disassembled and assembled after ultrasonication.
US07872399B2 Ultrasonic probe and ultrasonic diagnosis apparatus
A variance in transmitting/receiving sensitivity between multiple vibrational elements or transducers included in an ultrasonic probe is corrected. An ultrasonic probe in accordance with the present invention has multiple transducers, each of which includes multiple vibrational elements that each transmit or receive ultrasonic waves by converting ultrasonic waves and an electric signal into each other with a bias voltage applied thereto, set in array. The ultrasonic prove includes a transmitting/receiving sensitivity correction means that independently adjusts the bias voltage to be applied to at least two vibrational elements among the multiple vibrational elements so as to correct a variance in transmitting/receiving sensitivity between the at least two vibrational elements.
US07872397B2 Electrical to mechanical energy converter
An energy conversion apparatus having a pair of flexible beams that are supported at first ends thereof from a base. The beams each include at least one piezoelectric material layer. Second ends of each of the beams are operatively coupled to rigid links. The rigid links are in turn operatively coupled to a working element that may form, in one application, a drive member for a motor, or in a second application form a valve element for an electronic fuel injection system, or in a third application form a piston for a fluid pump. The working element is free to move linearly in a path generally parallel to the longitudinal axes of the flexible beams. As electrical signals are applied to and removed from the piezoelectric material layer(s) of each flexible beam, the beams flex repeatedly and uniformly over their full lengths. This causes a linear movement of the working element that can be used to help form a rotational motor output or a linearly moving fluid control element.
US07872396B2 Electrochemical actuator
The present invention provides systems, devices, and related methods, involving electrochemical actuation. In some cases, application of a voltage or current to a system or device of the invention may generate a volumetric or dimensional change, which may produce mechanical work. For example, at least a portion of the system may be constructed and arranged to be displaced from a first orientation to a second orientation. Systems such as these may be useful in various applications, including pumps (e.g., infusion pumps) and drug delivery devices, for example.
US07872395B2 Actuator with symmetric positioning
An actuator 1 according to the present invention includes: a first movable section 5; a second movable section 6 supporting the first movable section 5; and a stationary section 13 supporting the second movable section 6. The second movable section 6 includes: a first conductive portion 6a for applying a first voltage to the first movable section 5; a second conductive portion 6b to which a second voltage is applied; and backlining 15 for stabilizing the first conductive portion 6a and the second conductive portion 6b to each other in an electrically insulated state. The backlining 15 stabilizes the first conductive portion 6a and the second conductive portion 6b from a face of the actuator 1 opposite from the face on which the mirror section 34 is provided.
US07872391B2 Stator core
A stator core is disclosed. The stator core is constructed in a structure in which stress and spring back of the stator core are minimized when a stator is manufactured in a spiral fashion, whereby workability is improved. The stator core includes a yoke formed in the shape of a band, a plurality of teeth protruding outward from one side of the yoke, the teeth being arranged at predetermined intervals in the longitudinal direction of the yoke, a plurality of notches formed at the inside of the yoke in the shape of a cutout such that the notches are arranged at equal intervals, and guide holes formed in the longitudinal direction of the yoke. The guide holes include holes formed at positions corresponding to the respective teeth and holes formed between the respective teeth.
US07872390B2 Method for manufacturing a conductor bar of a rotating electrical machine and a conductor bar manufactured according to this method
A method for manufacturing a conductor bar of a rotating electrical machine includes providing a conductor defining a longitudinal direction and having a rectangular cross section, and building up an insulation to a thickness d around the conductor by progressively winding an insulating tape around the conductor a plurality of times in the form of a spiral in the longitudinal direction. The building up of the insulation includes winding the insulation tape around the conductor using parallel winding up to a first partial thickness, and winding the insulating tape around the conductor using non-parallel winding from the first partial thickness.
US07872388B2 Rotor for an electrical machine with improved temperature stability
The present invention relates to an electrical machine including a rotor shaft, a hollow-cylindrical magnet element, a first covering disk, and a second covering disk, in which the first and second covering disks are secured to the rotor shaft, and the magnet element is secured on its first axial end to the first covering disk and on its second axial end to the second covering disk.
US07872387B2 Motor with single bearing
A motor with single bearing comprises a fan blade set, a motor set and a fan blade base. The fan blade set has a fan blade hub to join with a spindle fitting with a bearing. The motor set is attached to the fan blade base and a hollow axial seat is provided in the fan blade base to receive the bearing. Further, an elastic element or magnetic element is disposed at the axial seat to avoid internal clearance being created by lacking preset pressure acing to the bearing casing and balls therein. The balls and the bearing itself can run successfully to enhance operation of the motor effectively.
US07872385B2 Electric motor power connection assembly
An electric motor power connection assembly diverts heat from an electrical conductor that carries electrical current between a power source and an electric motor. The electrical conductor is characterized by an effective cross-sectional area perpendicular to the direction of current flow and a length in the direction of current flow that is greater than the radius of a circle having the effective cross-sectional area. The “effective cross-sectional area” is the area perpendicular to the direction of current flow over which current is carried and thus depends on the cross-sectional shape and number of conductive components of the electrical conductor, which could be one or more wires. A heat diverting mechanism is positioned in thermal contact along the length of the electrical conductor to divert heat from the electrical conductor. The electric motor power connection assembly is suitable for use in a hybrid electro-mechanical transmission.
US07872384B2 Shaft cover structure for use in an exciter
A shaft cover structure for use in an exciter is provided. The shaft cover structure comprises at least two sections located about a selected portion of a rotatable shaft. The sections are positioned such that adjacent circumferential ends of the at least two sections are spaced apart to define gaps therebetween. A recess extends from each circumferential end such that adjacent recesses define a slot. A spanning member is disposed in each of the slots such that the sections and the spanning members cooperate to form a continuous cover member that surrounds the selected portion of the shaft. A first holding structure secures the continuous member on the selected portion of the shaft.
US07872380B2 Apparatus and method for generating rotary oscillations
An apparatus and method for generating rotary oscillation with two shafts pivotable relative to each other. An end section of a first shaft is accommodated in an end section of a second shaft so as to form an air gap. One of the two shafts has a magnetic field generator of substantially constant field strength, and the other shaft has conductors which generate a magnetic field and to which current has been variably applied to pivot the shafts relative to each other.
US07872377B2 Communications in multiple-switch electrical circuits
A system, device and method to allow communications between switches in an electrical circuit containing three-way and four-way switches. The system, device and method allow any switch in an electrical circuit using conventional wiring for three-way and four-way switches to indicate when voltage is being supplied to the electrical load device in the electrical circuit; if a dimmer is present in the electrical circuit, to indicate the dim level of the load device in the electrical circuit and to command to dim level from any switch; and if a timer is present, to allow any switch to provide a warning indication prior to the timer shutting off the load device, and to allow any switch to reset the timer, preventing the shutoff.
US07872375B2 Multiple bi-directional input/output power control system
A multiple bi-directional input/output power control system includes a network of functional blocks housed in a single enclosure, providing DC power to one or more DC loads, and providing control and internal pathways, sharing one or more AC and/or DC power inputs. The system feeds back AC power from the DC power source into an AC input connection, and the fed-back AC power is shared by other AC loads. The system operates at least one alternative source of DC in a dynamic manner, allowing maximization of power generating capability at respective specific operating conditions of the moment. Power isolation may be handled by an AC isolation block right at a power input. Therefore all other blocks within a multi-function power control unit (MFPCU) are isolated from AC ground.
US07872374B2 Battery communication system
An uninterrupted power supply (“UPS”) system is disclosed which uses a battery communication system to communicate to a UPS processor information concerning the status of a battery pack in an array of parallel coupled battery packs. The battery packs provide back-up power for the UPS system. Information about the battery packs is collected by a monitor associated with each of the battery packs. The monitors measure battery pack voltage, currents and temperature and compile information about the battery pack from the measured values. Each monitor prepares a data word representing information about its battery pack. The data words are transmitted to the UPS in response to commands issued by the UPS processor to the monitors.
US07872367B2 Method and device for redundantly supplying several electric servomotors or drive motors by means of a common power electronics unit
A method and a device for redundantly supplying several electric servomotors or drive motors by a common power electronics unit, particularly in an aircraft, wherein the power electronics unit contains a number of electronic motor control units, and wherein the electric motors are operated with nominal power if the electronic motor control units are fully functional. The motors are operated with the available residual power of the motor control units if partial failure of the motor control units occurs. The motors may be operated sequentially or simultaneously.
US07872365B2 Wave powered electrical generator
A wave powered electrical generator includes: a first floating unit that accommodates a power generator therein and adapted to float in water, a second floating unit adapted to float in the water in the vicinity of the first floating unit; and a spring line, one end of which being attached to the second floating unit and the other end of which being operatively connected to the power generator, such that a relative movement between the first floating unit and the second floating unit causes the spring line to rotate a shaft of the generator and generates electrical power.
US07872360B2 Semiconductor device and method of manufacturing the same
A semiconductor device is disclosed that includes a wiring board having a via formed therein; a semiconductor element provided on the wiring board; a resist layer covering a surface of the wiring board, the resist layer having an opening in a part thereof positioned on the via; and a sealing resin covering the surface of the via in the opening and the resist layer, and sealing the semiconductor device.
US07872357B2 Protection for bonding pads and methods of formation
The formation of bonding pad protective layer over exposed bonding pad materials between stacked integrated circuit (IC) dies or wafers is described in preferred embodiments in which the bonding pad protective layer is formed in the integrated process of forming wafer bonding pads. The bonding pad protective layer prevents the exposed bonding pad materials from oxidation and corrosion in open-air or other harsh environments. By providing a bonding pad protective layer on exposed bonding pad materials, significant product reliability improvement is expected on ICs having a three-dimensional “stacked-die” configuration.
US07872355B2 Semiconductor integrated circuit and method of designing semiconductor integrated circuit
A semiconductor integrated circuit has: a power pad placed on a chip; and a circuit group connected to the power pad through a power wiring structure. The power wiring structure includes: a plurality of first power wirings and a plurality of second power wirings that are formed in different wiring layers and overlap with each other at a plurality of intersections; and vias connecting the plurality of first power wirings and the plurality of second power wirings. The circuit group includes a first functional block placed on a first region. The vias are not placed at a part of the plurality of intersections within a second region located between the first region and the power pad.
US07872353B2 Semiconductor device
A semiconductor device including at least two layers of interlayer-insulator-films stacked above a substrate and at least partially formed by a low-relative-dielectric-constant-film having a relative-dielectric-constant of 3.4 or less respectively, a plurality of wirings provided at least one within each of the interlayer-insulator-film and at least partially located within the low-relative-dielectric-constant-films, a plurality of plugs provided at least one within each of the interlayer-insulator-film and connected to a lower part of the wirings, and a plurality of reinforcement members provided at least one within each of the interlayer-insulator-film with being separated from the wirings at a predetermined interval, electrically cut from the wirings and the plugs, and at least partially located within the low-relative-dielectric-constant-films, and wherein, the interlayer-insulator-films, the wirings, the plugs, and the reinforcement members satisfy a predetermined relation for each of the interlayer-insulator-film.
US07872352B2 Carbon nanotube bond pad structure and method therefor
A bond pad structure (300) for an integrated circuit (IC) device uses carbon nanotubes to increase the strength and resilience of wire bonds (360). In an example embodiment there is, a bond pad structure (300) on an IC substrate, the bond pad structure comprises, a first conductive layer (310) having a top surface and a bottom surface, the bottom surface attached to the IC substrate. A dielectric layer (320) is deposited on the top surface of the first conductive layer (310), the dielectric layer having an array of vias (325), the array of vias filled with a carbon nanotube material (325), the carbon nanotube material (325) is electrically coupled to the first conductive layer (310). There is a second conductive layer (330) having a top surface and a bottom surface, the bottom surface of the second conductive layer is electrically coupled to the carbon nanotube material (325). A feature of this embodiment may include the first (410,510) or second (430, 530) conductive layer being comprised of carbon nanotube material, as well.
US07872351B2 Multi-layered metal line of semiconductor device for preventing diffusion between metal lines and method for forming the same
A multi-layered metal line of a semiconductor device includes a semiconductor substrate; a lower metal line formed on the semiconductor substrate and recessed on a surface thereof; an insulation layer formed on the semiconductor substrate including the lower metal line and having a damascene pattern for exposing a recessed portion of the lower metal line and for delimiting an upper metal line forming region; a glue layer formed on a surface of the recessed portion of the lower metal line; a first diffusion barrier formed on the glue layer to fill the recessed portion of the lower metal line; a second diffusion barrier formed on the glue layer and the first diffusion barrier; a third diffusion barrier formed on the second diffusion barrier and a surface of the damascene pattern; and an upper metal line formed on the third diffusion barrier to fill the damascene pattern.
US07872350B2 Multi-chip module
A multi-chip module includes at least one integrated circuit chip that is electrically connected to first external terminals of the multi-chip module and at least one power semiconductor chip that is electrically connected to second external terminals of the multi-chip module. All first external terminals of the multi-chip module are arranged in a contiguous region of an terminal area of the multi-chip module.
US07872348B2 Semiconductor device
A semiconductor device formed by using semiconductor packages is provided. The semiconductor device includes two semiconductor packages adjacently arranged in opposite directions on an inductive conductor. Terminals of the two semiconductor packages are joined by a third lead. the third lead is arranged substantially in parallel to the inductive conductor. Leads at the joint portions have, for example, a bent structure, and the third lead is arranged to be close to the inductive conductor.
US07872338B2 Microelectromechanical device packages with integral heaters
A microelectromechanical device package with integral a heater and a method for packaging the microelectromechanical device are disclosed in this invention. The microelectromechanical device package comprises a first package substrate and second substrate, between which a microelectromechanical device, such as a micromirror array device is located. In order to bonding the first and second package substrates so as to package the microelectromechanical device inside, a sealing medium layer is deposited, and heated by the heater so as to bond the first and second package substrates together.
US07872328B2 Capacitor electrode that contains oxygen and nitrogen
A capacitor electrode includes a first surface and a second surface which are arranged opposite each other. The capacitor electrode contains an oxygen atom and a nitrogen atom. The capacitor electrode includes a position A where the oxygen atom exhibits a largest concentration value, between the first surface and the second surface in a thickness direction. The nitrogen atom is present only in an area closer to the first surface than the position A.
US07872326B2 Array of vertical bipolar junction transistors, in particular selectors in a phase change memory device
A process for manufacturing an array of bipolar transistors, wherein deep field insulation regions of dielectric material are formed in a semiconductor body, thereby defining a plurality of active areas, insulated from each other and a plurality of bipolar transistors are formed in each active area. In particular, in each active area, a first conduction region is formed at a distance from the surface of the semiconductor body; a control region is formed on the first conduction region; and, in each control region, at least two second conduction regions and at least one control contact region are formed. The control contact region is interposed between the second conduction regions and at least two surface field insulation regions are thermally grown in each active area between the control contact region and the second conduction regions.
US07872325B2 Reduced-crosstalk wirebonding in an optical communication system
Wirebonds are formed to couple an opto-electronic device chip having two or more opto-electronic devices to a signal processing chip. Two or more mutually adjacent wirebond groups, each corresponding to one of the opto-electronic devices, are formed. For example, each wirebond group can include a first wirebond coupling a P-terminal of the opto-electronic device of the wirebond group to the signal processing chip, a second wirebond coupling an N-terminal of the opto-electronic device of the wirebond group to the signal processing chip, and a third wirebond coupling the opto-electronic device chip to the signal processing chip.
US07872320B2 Micro-electro-mechanical device and method of manufacturing the same
The present invention improves mechanical strength of a micro-electro-mechanical device (MEMS) having a movable portion to improve reliability. In a micro-electro-mechanical device (MEMS) having a movable portion, a portion which has been a hollow portion in the case of a conventional structure is filled with a filler material. As the filler material, a block copolymer that is highly flexible is used, for example. By filling the hollow portion, mechanical strength improves. Besides, warpage of an upper portion of a structure body in the manufacture process is prevented, whereby yield improves. A micro-electro-mechanical device thus manufactured is highly reliable.
US07872313B2 Semiconductor device having an expanded storage node contact and method for fabricating the same
A semiconductor device is disclosed that stably ensures an area of a storage node contact connected to a junction region in an active region of the semiconductor device and is thus able to improve the electrical properties of the semiconductor device and enhance a yield, and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having an active region including a gate, a storage node contact region, and an isolation region that defines the active region. A passing gate and an isolation structure surrounding the passing gate are formed in the isolation region. A silicon epitaxial layer is selectively formed over an upper portion of the passing gate to expand the storage node contact region.
US07872312B2 Semiconductor device comprising a high dielectric constant insulating film including nitrogen
A semiconductor device includes a first gate electrode formed in a first region on a semiconductor substrate with a first gate insulating film sandwiched therebetween; and a second gate electrode formed in a second region on the semiconductor substrate with a second gate insulating film sandwiched therebetween. The first gate insulating film includes a first high dielectric constant insulating film with a first nitrogen concentration and the second gate insulating film includes a second high dielectric constant insulating film with a second nitrogen concentration higher than the first nitrogen concentration.
US07872310B2 Semiconductor structure and system for fabricating an integrated circuit chip
A semiconductor structure and a system for fabricating an integrated circuit chip. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa. The system for fabricating an integrated circuit chip enables: providing a buried oxide layer on and in direct mechanical contact with a semiconductor wafer; and concurrently forming at least one fin-type field effect transistor and at least one thick-body device on the buried oxide layer.
US07872309B2 Self-aligned lightly doped drain recessed-gate thin-film transistor
A recessed-gate thin-film transistor (RG-TFT) with a self-aligned lightly doped drain (LDD) is provided, along with a corresponding fabrication method. The method deposits an insulator overlying a substrate and etches a trench in the insulator. The trench has a bottom and sidewalls. An active silicon (Si) layer is formed overlying the insulator and trench, with a gate oxide layer over the active Si layer. A recessed gate electrode is then formed in the trench. The TFT is doped and LDD regions are formed in the active Si layer overlying the trench sidewalls. The LDD regions have a length that extends from a top of the trench sidewall, to the trench bottom, with a doping density that decreases in response to the LDD length. Alternately stated, the LDD length is directly related to the depth of the trench.
US07872308B2 Semiconductor device
A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type provided on a main surface of the first semiconductor layer and having a lower impurity concentration than that of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer; a fourth semiconductor layer of the first conductivity type selectively provided on the third semiconductor layer; a gate electrode provided in a trench passing through the third semiconductor layer and reaching the second semiconductor layer; a first main electrode contacting the fourth semiconductor layer and contacting the third semiconductor layer through a contact groove provided to pass through the fourth semiconductor layer between the contiguous gate electrodes; a second main electrode provided on an opposite surface to the main surface of the first semiconductor layer; and a fifth semiconductor layer of the second conductivity type provided in an interior portion of the second semiconductor layer corresponding to a part under the contact groove. An uppermost portion of the fifth semiconductor layer contacts the third semiconductor layer, a lowermost portion of the fifth semiconductor layer has a higher impurity concentration than that of the other portion in the fifth semiconductor layer and is located in the second semiconductor layer and not contacting the first semiconductor layer, and the fifth semiconductor layer is narrower from the uppermost portion to the lower most portion.
US07872307B2 Power MOSFET array
A power metal-oxide-semiconductor field-effect transistor (MOSFET) array structure is provided. The power MOSFET array is disposed under a gate pad, and space under the gate pad can be well used to increase device integration. When the array and the conventional power MOSFET array disposed under the source pad are connected to an array pair by using circuit connection region, the same gate pad and source pad can be shared, so as to achieve an objective of increasing device integration.
US07872299B2 Nonvolatile memory devices and methods of fabricating the same
Provided are nonvolatile memory devices and methods of fabricating the same which may prevent or reduce deterioration of device characteristics and deterioration of a breakdown voltage. The nonvolatile memory device may include a semiconductor substrate, a charge-trap insulation layer on the semiconductor substrate and having a first region and second regions having a lower density of charge-trap sites than the first region, and a gate electrode on the charge-trap insulation layer, wherein the first region is overlapped by the gate electrode and the second regions are outside of the first region.
US07872294B2 Semiconductor device having a capacitance element and method of manufacturing the same
A dielectric film is formed by depositing an amorphous strontium oxide film to a thickness of one to several atomic layers on a first electrode layer, then depositing an amorphous titanium oxide film to a thickness of one to several atomic layers on the amorphous strontium oxide film, and then heat-treating a laminated film of the amorphous strontium oxide film and the amorphous titanium oxide film at a temperature close to a crystallization start temperature, thereby converting the laminated film to a single-layer amorphous strontium titanate film containing a plurality of crystal grains therein. The laminated film may have a plurality of amorphous strontium oxide films and a plurality of amorphous titanium oxide films that are alternately laminated. A semiconductor device includes a capacitor having as its dielectric film a single-layer amorphous strontium titanate film containing a plurality of crystal grains therein.
US07872292B2 Capacitance dielectric layer and capacitor
A capacitance dielectric layer is provided. The capacitance dielectric layer includes a first dielectric layer, a second dielectric layer and a silicon nitride stacked layer. The silicon nitride stacked layer is disposed between the first dielectric layer and the second dielectric layer. The structure of the capacitance dielectric layer permits an increase in the capacitance per unit area by decreasing the thickness of the capacitance dielectric layer and eliminates the problems of having a raised leakage current and a diminished breakdown voltage.
US07872288B2 Organic light-emitting display device
An organic light-emitting display device includes a substrate, a first buffer layer and a second buffer layer on the substrate, a thin film transistor on the second buffer layer, an organic light-emitting diode electrically connected with the thin film transistor, and a photo sensor with an intrinsic region on the second buffer layer, wherein the photo sensor is capable of absorbing red light from the organic light-emitting diode and of exhibiting quantum efficiency of from about 50% to about 90%.
US07872287B2 Solid-state imaging device
It is an object of the present invention to provide an image sensor having a high ratio of a surface area of a light receiving element to a surface area of one pixel. The above-described object is achieved by an inventive solid-state imaging device unit comprising solid-state imaging devices arranged on a substrate according to the present invention. The solid-state imaging device comprises a signal line formed on the substrate, an island shaped semiconductor placed over the signal line, and a pixel selection line connected to an upper portion of the island shaped semiconductor. The island shaped semiconductor comprises a first semiconductor layer disposed in a lower portion of the island shaped semiconductor and connected to the signal line, a second semiconductor layer disposed adjacent to an upper side of the first semiconductor layer, a gate connected to the second semiconductor layer via an insulating film, an electric charge accumulator comprising a third semiconductor layer connected to the second semiconductor layer and carrying a quantity of electric charges which varies in response to a light reception, and a fourth semiconductor layer disposed adjacent to an upper side of the second semiconductor layer and the third semiconductor layer and connected to the pixel selection line. The solid-state imaging devices are arranged on the substrate in a honeycomb configuration.
US07872285B2 Vertical gallium nitride semiconductor device and epitaxial substrate
Affords epitaxial substrates for vertical gallium nitride semiconductor devices that have a structure in which a gallium nitride film of n-type having a desired low carrier concentration can be provided on a gallium nitride substrate of n type. A gallium nitride epitaxial film (65) is provided on a gallium nitride substrate (63). A layer region (67) is provided in the gallium nitride substrate (63) and the gallium nitride epitaxial film (65). An interface between the gallium nitride substrate (43) and the gallium nitride epitaxial film (65) is positioned in the layer region (67). In the layer region (67), a peak value of donor impurity along an axis from the gallium nitride substrate (63) to the gallium nitride epitaxial film (65) is 1×1018 cm−3 or more. The donor impurity is at least either silicon or germanium.
US07872281B2 Glass-coated light-emitting element, light-emitting element-attached wiring board, method for producing light-emitting element-attached wiring board, lighting device and projector
A glass-coated light-emitting element 10 of the invention has a semiconductor light-emitting element 2 having a surface on which no electrode is formed is coated with a glass 1, in which a surface of the glass 1 constitutes a part of a spherical surface broader than a hemispherical surface, the refractive index of the glass 1 at an emission peak wavelength of the semiconductor light-emitting element 2 is 1.7 or more, and the ratio of the diameter of the above-mentioned spherical surface to the maximum diameter of a surface of the semiconductor light-emitting element 2 on which electrodes are formed is 1.8 to 3.5, whereby light emitted from the light-emitting element can be efficiently introduced into a light control unit, and alignment with a lens or a light pipe, which has hitherto been made, becomes unnecessary.
US07872279B2 Light-emitting diode package
A light-emitting diode (LED) package including a carrier, a pair of conductive wire units, an LED chip, and a control circuit module is provided. The carrier has a carrying portion and a ring frame connected to the periphery of the carrying portion. The carrying portion has a dome-like upper surface and a pair of through holes. The pair of conductive wire units is disposed inside the through holes respectively, and each of the conductive wire units has a conductive wire and an insulating material encapsulating the conductive wire. The LED chip is disposed on the upper surface of the carrier and is electrically connected to the conductive wires. The control circuit module is disposed at a bottom of the carrier and is electrically connected to the conductive wires for controlling the operation of the LED chip.
US07872276B2 Vertical gallium nitride-based light emitting diode and method of manufacturing the same
A method of manufacturing a vertical GaN-based LED comprises forming a light emission structure in which an n-type GaN-based semiconductor layer, an active layer, and a p-type GaN-based semiconductor layer are sequentially laminated on a substrate; etching the light emission structure such that the light emission structure is divided into units of LED; forming a p-electrode on each of the divided light emission structures; filling a non-conductive material between the divided light emission structures; forming a metal seed layer on the resulting structure; forming a first plated layer on the metal seed layer excluding a region between the light emission structures; forming a second plated layer on the metal seed layer between the first plated layers; separating the substrate from the light emission structures; removing the non-conductive material between the light emission structures exposed by separating the substrate; forming an n-electrode on the n-type GaN-based semiconductor layer; and removing portions of the metal seed layer and the second plated layer between the light emission structures.
US07872275B2 Light-emitting diode arrangement
A light-emitting diode arrangement includes one or more LED crystal pieces that are mechanically held by leads and connecting lines.
US07872274B2 n-Electrode for III group nitride based compound semiconductor element
An object of the present invention is to obtain greater reduction in resistance between an n-electrode and an n-type layer made of a Group III nitride compound semiconductor. According to the present invention, the n-electrode is formed with a first electrode material made of at least one member selected from the group consisting of vanadium (V), titanium (Ti), zirconium (Zr) and tungsten (W), a second electrode material made of at least one member selected from the group consisting of palladium (Pd), platinum (Pt), gold (Au), silver (Ag) and copper (Cu), and a third electrode material made of at least one member selected from the group consisting of aluminum (Al), silicon (Si) and germanium (Ge).
US07872273B2 Light emitting device
A light emitting device includes a leadframe, a light emitting unit, a transparent encapsulant, and a fluorescent colloid layer. The light emitting unit is disposed on the leadframe. The transparent encapsulant covers the light emitting unit, wherein the transparent encapsulant has a concave on which at least one reflective surface is disposed. The fluorescent colloid layer is disposed outside the transparent encapsulant, wherein a chamber is formed between the fluorescent colloid layer and the transparent encapsulant. The light generated by the light emitting unit is reflected by the reflective surface and guided to a side wall of the fluorescent colloid layer.
US07872271B2 Flip-chip light emitting diodes and method of manufacturing thereof
Provided are a flip-chip nitride-based light emitting device having an n-type clad layer, an active layer and a p-type clad layer sequentially stacked thereon, comprising a reflective layer formed on the p-type clad layer and at least one transparent conductive thin film layer made up of transparent conductive materials capable of inhibiting diffusion of materials constituting the reflective layer, interposed between the p-type clad layer and reflective layer; and a process for preparing the same. In accordance with the flip-chip nitride-based light emitting device of the present invention and a process for preparing the same, there are provided advantages such as improved ohmic contact properties with the p-type clad layer, leading to increased wire bonding efficiency and yield upon packaging the light emitting device, capability to improve luminous efficiency and life span of the device due to low specific contact resistance and excellent current-voltage properties.
US07872264B2 Light-emitting device and electronic apparatus
A light-emitting device includes a power feeding line to which a predetermined voltage is supplied; a light-emitting element formed of a first electrode, a second electrode, and a light-emitting layer interposed between the first electrode and the second electrode; and a driving transistor that controls the amount of current supplied to the light-emitting element from the power feeding line. The power feeding line includes a portion interposed between the first electrode and the driving transistor.
US07872260B2 Fabrication method of pixel structure and thin film transistor
A method of fabricating a thin film transistor is disclosed. First, a substrate is provided and a patterned polysilicon layer is formed on the substrate. A metal layer is formed on the patterned polysilicon layer. Then, a portion of the metal layer is removed so that the remaining metal layer beside the patterned polysilicon layer forms a source and a drain. A gate insulation layer is formed on the substrate to cover the source, the drain and the patterned polysilicon layer. A gate is formed on the gate insulation layer over the patterned polysilicon layer.
US07872257B2 Organic thin film transistor array and method of manufacturing the same
An n-type TFT and a p-type TFT are realized by selectively changing only a cover coat without changing a TFT material using an equation for applying the magnitude of a difference in the Fermi energy between an interface of semiconductor and an electrode and between an interface of semiconductor and insulator. At this time, in order to configure a predetermined circuit, the process is performed, as a source electrode and a drain electrode of the p-type TFT and a source electrode and a drain electrode of the n-type TFT being connected all, respectively, and an unnecessary interconnection is cut by irradiating light using a scanning laser exposure apparatus or the like.
US07872256B2 Organic light emitting display and fabrication method of the same
An organic light emitting display that includes a substrate, a plurality of first electrodes arranged in a corresponding plurality of pixels, the plurality of pixels including red pixels, blue pixels and green pixels, a hole injection layer arranged on the first electrodes arranged on the substrate, the hole injection layer having different respective thicknesses in correspondence with the pixels, a hole transport layer entirely covering the hole injection layer, a white light emitting layer entirely covering the hole transport layer, an electron transport layer arranged on the white light emitting layer, a second electrode arranged on the electron transport layer and a color filter arranged on the second electrode.
US07872254B2 Wiring and organic transistor, and manufacturing method thereof
An organic transistor is formed with a low material cost and low manufacturing cost while still providing high performance and a low contact resistance with an organic semiconductor of the transistor. The organic transistor has electrodes whose bodies are formed mainly of an inexpensive first metal and whose surfaces are formed of a second metal that is expensive but provides high performance properties. To obtain stability of this structure with a low cost, a property of the second metal is used in which the second metal is easily segregated on the surface of the first metal in an alloy of the first metal and the second metal.
US07872253B2 Thermoelectric material, infrared sensor and image forming device
A thermoelectric conversion material includes a superlattice structure produced by laminating a barrier layer containing insulating SrTiO3, and a quantum well layer containing SrTiO3 which has been converted into a semiconductor by doping an n-type impurity therein. The quantum well layer has a thickness 4 times or less the unit lattice thickness of SrTiO3 which has been converted into a semiconductor by doping an n-type impurity therein.
US07872246B2 Laser annealing method and semiconductor device fabricating method
When the second harmonic of a YAG laser is irradiated onto semiconductor films, concentric-circle patterns are observed on some of the semiconductor films. This phenomenon is due to the non-uniformity of the properties of the semiconductor films. If such semiconductor films are used to fabricate TFTs, the electrical characteristics of the TFTs will be adversely influenced. A concentric-circle pattern is formed by the interference between a reflected beam 1 reflected at a surface of a semiconductor film and a reflected beam 2 reflected at the back surface of a substrate. If the reflected beam 1 and the reflected beam 2 do not overlap each other, such interference does not occur. For this reason, a laser beam is obliquely irradiated onto the semiconductor film to solve the interference. The properties of a crystalline silicon film formed by this method are uniform, and TFTs which are fabricated by using such crystalline silicon film have good electrical characteristics.
US07872242B2 Charged particle extraction device and method of design there for
The present invention provides a method for extracting a charged particle beam from a charged particle source. A set of electrodes is provided at the output of the source. The potentials applied to the electrodes produce a low-emittance growth beam with substantially zero electric field at the output of the electrodes.
US07872240B2 Corrector for charged-particle beam aberration and charged-particle beam apparatus
In a charged-particle beam apparatus having a high-accuracy and high-resolution focusing optical system for charged-particle beam, a group of coils are arranged along a beam emission axis to extend through the contour of radial planes each radiating from the beam emission axis representing a rotary axis and each having a circular arc which subtends a divisional angle resulting from division of a circumferential plane by a natural number larger than 2 so that a superposed magnetic field may be generated on the incident axis of the charged-particle beam and the trajectory of the charged-particle beam may be controlled by the superposed magnetic field.
US07872239B2 Electrostatic lens assembly
A lens assembly having an electrostatic lens component for a charged particle beam system is provided. The assembly includes: a first electrode having a conically shaped portion, a second electrode having a conically shaped portion, and a first insulator having a conically shaped portion, wherein the first insulator comprises two extending portions towards each of its ends, and wherein the two extending portions are formed to generate a gap between the insulator and each of the adjacent electrodes.
US07872237B2 Circuit substrate and method
Embodiments of the invention are concerned with semiconductor circuit substrates for use in a radiation detection device, said radiation detection device comprising a detector substrate having a plurality of detector cells arranged to generate charge in response to incident radiation, each of said detector cells including at least one detector cell contact for coupling charge from said detector cell to said semiconductor circuit substrate. More particularly, in embodiments of the invention the semiconductor circuit substrate comprises: a plurality of cell circuit contacts, each of which is configured to receive charge from a corresponding detector cell contact, cell circuitry associated with said plurality of cell circuit contacts; one or more conductive pathways arranged to carry at least one of control, readout and power supply signals to and/or from said cell circuitry; and one or more signal pathways extending through said semiconductor circuit substrate, said one or more signal pathways being electrically coupled to said conductive pathways so as to provide an external signal interface for said cell circuitry. Embodiments in accordance with the present invention thus provide a means of routing signals through the semiconductor circuit substrate to an electrical contact on a surface of the semiconductor circuit substrate. The electrical contact on the surface of the circuit substrate can then be directly coupled to a corresponding electrical contact on a mount.
US07872235B2 Multi-dimensional image reconstruction and analysis for expert-system diagnosis
An electronic storage medium that comprises at least one radiopharmaceutical identity, SPECT measured values of at least one radiopharmaceutical kinetic parameter of a flow rate across a tissue membrane, for the radiopharmaceutical, and a set of instructions for associating the at least one radiopharmaceutical kinetic parameter with a disease signature.
US07872230B2 Micro-sample processing method, observation method and apparatus
As sample sizes have decreased to microscopic levels, it has become desirable to establish a method for thin film processing and observation with a high level of positional accuracy, especially for materials which are vulnerable to electron beam irradiation. The technological problem is to judge a point at which to end FIB processing and perform control so that the portion to be observed ends up in a central portion of the thin film. The present invention enables display of structure in cross-section by setting a strip-like processing region in an inclined portion of a sample cross-section and enlarging the display of the strip-like processing region on a processing monitor in a short-side direction. It is then possible to check the cross-sectional structure without additional use of an electron beam. Since it is possible to check the processed section without using an electron beam, electron beam-generated damage or deformation to the processed section is avoided. Further, performing the observation using a high-speed electron beam after forming the thin film enables observation with suppressed sample damage. Processing of even thinner thin films using the FIB while observing images of the sample generated using an electron beam is then possible.
US07872229B2 Three-dimensional RF ion traps with high ion capture efficiency
In a three-dimensional Paul RF ion trap at least one of the ring electrode and end cap electrodes is structured to produce a high capture efficiency for analyte ions introduced into the trap. The electrode structuring may be produced by an electrode surface profile having edges or protrusions, resulting in a scattering reflection of the introduced ions. Alternatively, at least one electrode may be formed by physically separate electrode components. In one embodiment, the trap can be switched between operating as a linear ion trap with good capture efficiency and operating as a three-dimensional ion trap with good ion reaction conditions.
US07872224B2 Apparatus and method for positioning a discharge tube with respect to an orifice
Embodiments of the present invention facilitate servicing or changing a discharge tube or modifying the position of a discharge tube with respect to a orifice of a detector and/or a nebulizing gas conduit. The apparatus features a discharge tube housing that slidably receives a discharge tube. A union coupling the discharge tube to a source of fluid is slidably mounted to a mounting assembly holding the tube housing.
US07872223B2 Mass spectrometer
A laser light is linearly delivered onto the sample 4. The ions generated from the irradiated area are collected, mass-separated in the mass separator 27, and detected by the detector 28. A mass analysis is repeated while moving the sample stage 3 by a predetermined step width in the x-axis direction so that the one-dimensional mass spectrum information of the sample 4 at a certain rotational position is obtained. Additionally, while the sample 4 is rotated by a predetermined angle, the same measurement is repeated for the entire perimeter, so that the one-dimensional mass spectrum information at each rotational position is obtained. Based on the data obtained in this manner, a reconstruction computational processing is performed by the CT method to reconstruct the two-dimensional distribution image for a substance having a certain mass for example and the image is displayed on the display 35.
US07872219B2 Illumination device with plural color light sources and first and second integrators
An illumination apparatus includes a light source (1), a first integrator (11) into which light from the light source (1) enters, and a second integrator (33) into which light exiting from the first integrator (11) enters. Accordingly, the aperture shape of the first integrator (11) can be optimally designed, so that the light utilization efficiency can be increased. Furthermore, even when the length of the first integrator (11) is reduced, a deficiency in the light uniformity due to the first integrator (11) is compensated for by the second integrator (33), so that high uniformity can be secured at the surface to be illuminated.
US07872214B2 Kitchen appliance for cooling and/or heating foodstuff
A kitchen appliance for cooling and heating foodstuff including a housing that defines a cooling and heating cavity within the housing. A container is removably mountable within the cooling and heating cavity of the housing and the container is capable of retaining foodstuff therein. A conduction plate is disposed within the housing. The conduction plate is in thermal engagement with the container when the container is mounted within the housing. A heating element is disposed within the housing and is in thermal engagement with a conduction plate to heat the cooling and heating cavity. A cooling element is disposed within the housing and is in thermal engagement with the conduction plate to cool the cooling and heating cavity.
US07872210B2 Method for the connection of two wafers, and a wafer arrangement
A method for the connection of two wafers (11, 12), in which a contact area (15) is formed between the wafers (11, 12) by placing the two wafers one on top of the other, and in which the contact area (15) is heated locally and for a limited time. A wafer arrangement is also described in which two wafers (11, 12) which have been placed one on top of the other and between whose opposite surfaces a contact area (15) is located. The wafers are connected to one another at selected areas (21) of their contact area.
US07872206B2 Power supply circuit connector and method of connecting power supply circuit
A power supply circuit connector includes: a first housing including: a pair of main circuit terminals connected with each other via a first switch terminal, and a pair of mated state sensor terminals connected with each other; a second housing mated with or detached from first housing, second housing including: first switch terminal for connecting the pair of main circuit terminals by a lever rotated to a first certain position; the lever rotatably supported to second housing and including: a second switch terminal for making the following operation: with the pair of main circuit terminals kept connected with each other, connecting the pair of mated state sensor terminals with each other by lever rotated to a second certain position after first certain position; and a mating-detaching mechanism for making the following operations by rotated lever: mating second housing with the first housing, and detaching second housing from the first housing.
US07872193B2 Solar panel and production method therefor
A method is provided for producing a solar panel, which is made by building up a solar cell layer on a glass base as a covering glass, having a good performance in sealing the solar panel. A solar panel produce by the method is also provided. The production method of the present invention comprises a step of building up a solar cell layer which consists of a plurality of films on a glass substrate which is used as a covering glass, a step of removing a part of the solar cell layer which is built up on the glass substrate, a step of sealing the solar cell layer by using a face, which is exposed by the removing of the part of the solar cell layer, for adhering a sealing material.
US07872189B2 Electronic musical sound generator
An electronic musical sound generator prevents a sound production sequence to be stopped from continuing to be produced even through the key is released. Even if an erroneous instruction is sent to prevent identification data from being compared, in other words, if a sound production sequence which should be stopped, continues to be produced because of failure to find the sound production sequence to be stopped, the production of the musical sound can be stopped due to the key release because a second decision block searches data in a storage block, regards a key having identification data different from the one sent as the released key, according to the sequence being produced and the key is number, and determines the sound production sequence to be stopped.
US07872188B2 Method and apparatus for personal exercise trainer
Determining a plurality of heart rate sections for an individual, and selecting a plurality of songs, wherein each of the plurality of songs has an average beats per minute approximately equal to an average beats per minute of one of the plurality of heart rate sections, and playing the plurality of songs in a sequence on a song playing device. The plurality of songs includes a middle song, which has an average beats per minute which is greater than the average beats per minute of all of the other songs of the plurality of songs. The plurality of songs includes one or more preceding songs which precede the middle song, and each of which has an average beats per minute which is less than the average beats per minute of the middle song. The plurality of songs includes one or more succeeding songs which succeed the middle song, and each of which has an average beats per minute which is less than the average beats per minute of the middle song.
US07872181B2 Plants and seeds of corn variety CV135273
According to the invention, there is provided seed and plants of the corn variety designated CV135273. The invention thus relates to the plants, seeds and tissue cultures of the variety CV135273, and to methods for producing a corn plant produced by crossing a corn plant of variety CV135273 with itself or with another corn plant, such as a plant of another variety. The invention further relates to corn seeds and plants produced by crossing plants of variety with plants of another variety, such as another inbred line. The invention further relates to the inbred and hybrid genetic complements of plants of variety CV135273.
US07872178B2 Plants and seeds of hybrid corn variety CH929154
According to the invention, there is provided seed and plants of the hybrid corn variety designated CH929154. The invention thus relates to the plants, seeds and tissue cultures of the variety CH929154, and to methods for producing a corn plant produced by crossing a corn plant of variety CH929154 with itself or with another corn plant, such as a plant of another variety. The invention further relates to genetic complements of plants of variety CH929154.
US07872173B2 Plants having increased yield and method for making the same
The present invention concerns a method for increasing plant yield in plants grown under non-stress growth conditions relative to yield in corresponding wild type plants grown under comparable conditions, the method comprising preferentially increasing activity in the cytosol of a plant cell of a type I DnaJ-like polypeptide or a homologue thereof. One such method comprises introducing and/or expressing in a plant, plant part or plant cell a type I DnaJ-like nucleic acid or variant thereof. The invention also relates to transgenic plants grown under non-stress conditions having introduced and/or expressed therein a type I DnaJ-like nucleic acid or variant thereof, which plants have increased plant yield relative to corresponding wild type plants grown under comparable conditions. The present invention also concerns constructs useful in the methods of the invention.
US07872168B2 Stretchable absorbent article
An absorbent article having a stretchable substrate and an absorbent composite comprising a layer of adhesive composition in contact with the stretchable substrate. A layer of particulate superabsorbent material is applied to and held by the adhesive composition. The absorbent composite is secured to the substrate by the adhesive composition. The stretchable substrate has a recovery in at least one of the lateral direction and the longitudinal directions of the article as determined by an Elongation and Recovery Test, and the absorbent article has a recovery in the at least one of the lateral direction and the longitudinal direction as determined by the Elongation and Recovery Test that is at least about 60 percent of the recovery of the substrate in the at least one of the lateral direction and the longitudinal direction.
US07872167B2 Moisture-activatable adhesives for medical application purposes
An adhesive for medical patches or for transdermal therapeutic systems which contains a component or a combination of at least two components, such as (a) polyvinyl alcohols, (b) cellulose derivatives, (c) polyethers, (d) acid anhydrides and their acids and salts, as well as (e) non-pressure-sensitive adhesive polyacrylates. The adhesive has a tackiness which is activated and/or increased by contact with moisture or by absorption of moisture.
US07872165B2 Methods of hydrotreating a mixture made up of oils of animal or vegetable origin and of petroleum cuts with intermediate stripping
A hydrotreating method (HDT) utilizes two plants working under different operating conditions with an intermediate stripping for co-treating a mixture made up of oils of vegetable or animal origin and petroleum cuts (gas oil cuts (GO) and middle distillates) in order to produce gas oil fuel bases meeting specifications. The first plant (HDT1) is more particularly dedicated to the reactions concerning oils of vegetable or animal origin in comixture while pretreating the hydrocarbon feed, whereas the second plant (HDS2) works under more severe conditions to obtain diesel fuel according to standards, in particular in terms of effluent sulfur content, density and cold properties.
US07872164B2 Process for producing 4,9-dibromodiamantane
A process for selectively producing 4,9-dibromodiamantane includes a step of reacting diamantane with bromine in the presence of a Lewis acid and a solvent, wherein the solvent comprises a substituted or unsubstituted, straight-chain, branched-chain or cyclic saturated hydrocarbon containing from 3 to 10 carbon atoms, and a reaction solution after the step satisfies Formula (1): A/(A+B+C+D+E)>0.80   Formula (1) wherein A represents an area ratio (%) of 4,9-dibromodiamantane obtained by gas chromatography of the reaction solution, B represents an area ratio of diamantane, C represents a sum of an area ratio of 1-bromodiamantane and an area ratio of 4-bromodiamantane, D represents an area ratio of tribromodiamantane, and E represents a sum of an area ratio of 1,6-dibromodiamantane and an area ratio of 1,4-dibromodiamantane.
US07872161B2 Process for producing 2,3,3,3-tetrafluoropropene
A process is disclosed for making CF3CF═CH2 The process involves (i) contacting CHCl2CF2CF3 in a reaction zone in the presence of a catalytically effective amount of a dehydrofluorination catalyst to produce CCl2═CFCF3; (ii) contacting CCl2═CFCF3 with H2 formed in (i) in a reaction zone in the presence of a catalyst comprising a catalytically effective amount of palladium supported on a support selected from the group consisting of alumina fluorided alumina, aluminum fluoride and mixtures thereof, to produce a product mixture comprising CF3CF═CH2, wherein the mole ratio of H2 to CCl2═CFCF3 fed to the reaction zone is between about 1:1 and about 4:1 and (iii) recovering CF3CF═CH2 from the product mixture formed in (ii).
US07872153B2 Salt of aliskiren with sulfuric acid
The invention relates to a new salt of aliskiren, the respective production and usage, and pharmaceutical preparations containing such a salt.
US07872150B2 Process for the preparation of an oxaliplatin
The present invention relates to an improved process for the preparation of oxaliplatin, the obtained oxaliplatin preparation and its use in cancer therapy.
US07872148B2 Cage-shaped cyclobutanoic dianhydrides and process for production thereof
A process which comprises reacting a 1,2,3,4-cyclobutanetetracarboxylic-1,2:3,4-dianhydride [1] with an alcohol [2] in the presence of an acid catalyst to obtain a compound [3], isomerizing the compound [3] with a base catalyst into a compound [4], reacting the compound [4] with an organic acid to obtain a compound [5], and reacting the compound [5] with a dehydrating agent to obtain a 1,2,3,4-cyclobutanetetracarboxylic-1,3:2,4-dianhydride: wherein R1 and R2 are each independently hydrogen, halogeno, alkyl of 1 to 10 carbon atoms, halogenated alkyl of 1 to 10 carbon atoms, cycloalkyl of 3 to 8 carbon atoms, phenyl, or cyano; and R3 is alkyl of 1 to 10 carbon atoms.
US07872144B2 Process for producing biphosphonic acids and forms thereof
Disclosed herein is a process for producing bisphosphonic acids and salts thereof. The process comprising reacting a carboxylic acid of Formula [I] with phosphorous acid and halophosphorus compound in the presence of a solvent selected from aliphatic hydrocarbon or water miscible cyclic ether. Further, the present invention also provides novel forms of bisphosphonic acids and process for preparation thereof.
US07872143B2 Facile synthesis of a series of liquid crystalline 2-(4′-alkoxyphenyl)-5-cyanopyridines
The invention relates to a facile synthesis of a series of 2-(4′-alkoxyphenyl)-5-cyanopyridine liquid crystal compounds which are represented by the following formula (I): wherein CnH2n+1 is a linear alkyl group having 2-12 carbon atoms. The synthesis of the liquid crystalline 2-(4′-alkoxyphenyl)-5-cyanopyridine is completed in a two-step reaction. First, a Grignard reagent (such as 4-alkoxyphenylmagnesium bromide) is added to a 3-cyanopyridinium salt (such as N-phenyloxycarbonyl-3-cyanopyridinium chloride) to get a 1,2-dihydropyridine. Then, the 1,2-dihydropyridine is oxidized with o-chloronil to obtain the 2-(4′-alkoxyphenyl)-5-cyanopyridine.
US07872139B2 Heteroaryl-ureas and their use as glucokinase activators
This invention relates to compounds of formula (I) which are activators of glucokinase and thus may be useful for the management, treatment, control, or adjunct treatment of diseases, where increasing glucokinase activity is beneficial.
US07872133B2 Tricyclic heterocycle compound
The present invention relates to the compound represented by formula (I) A-X—Y—Z—B  (I) (wherein A is a cyclic group which may have a substituent(s); X is a single bond or a spacer; Y is a single bond or a spacer; Z is a single bond or a spacer; B is a hydrocarbon group which may have a substituent(s) or a cyclic group which may have a substituent(s)), a salt thereof, a solvate thereof or a prodrug thereof. The compound represented by formula (I), a salt thereof, a solvate thereof or a prodrug thereof is useful for preventive and/or therapeutic agent for a disease caused by stress.
US07872129B2 Compositions useful as inhibitors of GSK-3
The present invention provides a compound of formula I: or a pharmaceutically acceptable derivative thereof. These compounds are inhibitors of protein kinases, particularly inhibitors of GSK3 mammalian protein kinase. The invention also provides pharmaceutically acceptable compositions comprising the compounds of the invention and methods of utilizing those compounds and compositions in the treatment of various protein kinase mediated disorders.
US07872125B2 Phenylalanine derivatives
Specified phenylalanine derivatives and analogues thereof have an antagonistic activity to α4 integrin. They are used as therapeutic agents for various diseases concerning α4 integrin.
US07872123B2 Process of making α-aminooxyketone/α-aminooxyaldehyde and α-hydroxyketone/α-hydroxyaldehyde compounds and a process making reaction products from cyclic α,β-unsaturated ketone substrates and nitroso substrates
The present invention is directed to a process of making α-aminooxyketone and α-hydroxyketone compounds. The synthetic pathway involves reacting an aldehyde or ketone substrate and a nitroso substrate in the presence of a catalyst of the formula (IV): wherein Xa-Xc represent independently nitrogen, carbon, oxygen or sulfur and Z represents a 4 to 10-membered ring with or without a substituent and optionally a further step to convert the α-aminooxyketone compound formed to the α-hydroxyketone compound which results in α-aminooxyketone and α-hydroxyketone compounds with high enantioselectivity and high purity. The present invention is also directed to a catalytic asymmetric O-nitroso Aldol/Michael reaction involving a cyclic α,β-unsaturated ketone substrate and a nitroso substrate. This methodology involves reacting the cyclic α,β-unsaturated ketone substrate and the nitroso substrate in the presence of a proline-based catalyst, to provide a heterocyclic product.
US07872121B2 Process for the removal of exocyclic base protecting groups
Nitrogen-protecting groups are removed from the exocyclic nucleobase portion of a 2′-O protected nucleotide or 2′-halo nucleotide by contacting the nucleotide with an inorganic base. Typical is the removal of t-butylphenoxyacetyl protecting groups from the nucleobase portion of a 2′-O protected nucleotide on which the 2′-O protecting group is t-butyldimethylsilyl, removal or deprotection being accomplished by contact with a potassium carbonate solution.
US07872118B2 siRNA and methods of manufacture
Double-stranded RNA of about 19 to about 25 nucleotides in length capable of regulating gene expression by RNA interference is provided. Such double-stranded RNA are particularly useful for treating disease or conditions associated with a target mRNA or gene. Methods of manufacture and methods of use of the double-stranded RNA are also provided.
US07872117B2 c-met siRNA adenovirus vectors inhibit cancer cell growth, invasion and tumorigenicity
Suppression of the Hepatocyte growth factor/scatter factor (HGF/SF)-Met signaling pathway by targeting the Met protein tyrosine kinase was tested as strategy for suppressing tumor growth. Using RNA interference (RNAi) technology and adenoviruses carrying siRNA (Ad Met siRNA) target sequences dramatically reduced Met expression in mouse, dog and human tumor cells. Met was suppressed using Ad Met siRNA in mouse mammary tumor (DA3) cells and Met-transformed (NIH3T3 (M114) cells as well as human prostate cancer, sarcoma, glioblastoma, gastric and ovarian cancer cells. Furthermore, the Ad Met siRNA infection reversed transformed cell morphology. Ad Met siRNA killed cancer cells by inducing apoptosis. RNAi targeting Met suppressed HGF/SF-mediated scattering as well as ligand-mediated invasion activity and growth of tumor cells. Met siRNA infection also abrogated downstream Met signaling to molecules such as Akt and p44/42 MAPK. Importantly, the Met siRNA triggered apoptosis was correlated to suppressed tumorigenicity in vivo. Intro-tumoral infection with c-met siRNA adenovirus vectors produced significant reduction in tumor growth. Thus Met RNAi is an effective weapon for targeting Met expression and for treating c-Met+ cancers.
US07872113B2 Nucleic acids encoding antibodies that bind interleukin-4 receptor
The present invention relates to antibodies that bind to the IL-4 receptor, fragments, muteins, and derivatives of such antibodies, nucleic acids encoding such antibodies, fragments, muteins and derivatives, and methods of making and using such antibodies, fragments, muteins, derivatives and nucleic acids. Methods for treating medical conditions induced by interleukin-4 involve administering an IL-4 receptor binding antibody, or an IL-4 receptor binding fragment, mutein, or derivative of an IL-4 receptor binding antibody, to a patient afflicted with such a condition. Particular antibodies provided herein include human monoclonal antibodies. Certain of the antibodies inhibit both IL-4-induced and IL-13-induced biological activities.
US07872111B2 Process for producing protein with reduction of acidic sugar chain and glycoprotein produced thereby
A protein participating in the addition of mannose phosphate to a sugar chain of a glycoprotein originating in a yeast belonging to the genus Pichia; a gene coding this protein; a mutant of this gene; a vector carrying the mutant gene; a yeast strain belonging to the genus Pichia having been transformed by this vector; a process for producing a protein with reduction of an acidic sugar chain by using the transformed yeast strain; and a glycoprotein thus produced, are described.
US07872108B2 Processes for isolating proteon nucleation centers (PNCs) from a biological sample obtained from an animal
Compositions and methods for the isolation and manipulation of misfolded, or partially misfolded, proteins present in blood and other biological materials are provided. In one aspect of the invention, the compositions, hereinafter termed “proteons” are comprised of misfolded proteins. Also provided are compositions and methods for the isolation and manipulation of proteon nucleation centers (PNCs) upon which the proteons of the present in blood and other biological materials form. In another aspect of the invention, the PNCs are comprised of metallic nanoclusters.
US07872106B2 Sclerostin-binding antibodies
Compositions and methods relating to epitopes of sclerostin protein, and sclerostin binding agents, such as antibodies capable of binding to sclerostin, are provided.
US07872104B2 Antibody, immunoassay and method for prostate cancer detection
This invention concerns an antibody which binds with high affinity to human single-chain intact, i.e. not internally cleaved, mature and/or zymogen forms of prostate specific antigen (SCINT PSA). The antibody does not bind to a nicked PSA (PSA-N), wherein said PSA-N has been formed by internal peptide bond cleavage(s) of SCINT PSA resulting in two-chain or multi-chain PSA. This invention further concerns an immunoassay and a method for differentiating patients with cancer of the prostate (PCa) from patients with benign prostatic hyperplasia (BPH) and/or healthy male subjects without PCa, patients with aggressive PCa from patients with indolent PCa and/or patients with clinically localized and/or organ confined PCa from patients with extraprostatic extension of PCa and/or PCa with metastatic spread to lymph nodes or bone marrow using said antibody.
US07872101B1 Modulators of the orphan G protein-coupled receptors GPR78 and GPR26
The invention relates to the use of the interaction between the GPR78 polypeptide or the GPR26 polypeptide and their identified ligands and antagonists as the basis for screening methods for the identification of agents that modulate the activity of these receptors, and for diagnostic and therapeutic purposes. The agents identified by the screening methods of the invention have use in the treatment of GPR78- and/or GPR26-mediated disorders, including, but not limited to, neurological disorders (such as anxiety disorders), metabolic disorders, cardiovascular disorders, hormone-related disorders, vascular disorders and hyperproliferative disorders (such as cancer).
US07872100B2 Nitrile hydratases from metagenome libraries
The present invention is concerned with the preparation of novel nitrile hydratases. These latter are preferably obtained from nonculturable organisms by means of a PCR-based screening, in metagenome DNA libraries, using special degenerate primers.
US07872097B2 Cyclic peptide compounds
The present invention relates to a new cyclic peptide compound or a salt thereof, which has anti-hepatitis C virus activities based on inhibitory activity against the RNA replication of hepatitis C virus replicon, to a process for preparation thereof comprising a rearrangement reaction under a mild acidic condition and the following amino acid changing reactions etc., to a pharmaceutical composition comprising the same, and to a method for prophylactic and/or therapeutic treatment of hepatitis C in a human being or an animal.
US07872093B2 Method for producing polythiourethane resin
A process for producing a polythiourethane resin which comprises (A) a step of synthesizing a polythiol oligomer having disulfide bond by reaction of a polythiol compound having a functionality of two or greater and sulfur and (B) a step of bringing the polythiol oligomer obtained in step (A) and a compound having poly(thio)isocyanate groups into reaction with each other, wherein step (A) is conducted in the absence of solvents using no catalysts or a catalyst substantially inert to the compound having poly(thio)isocyanate groups. A polythiol oligomer exhibiting a greater refractive index than that of the polythiol compound having a functionality of two or greater used as the starting material is produced at a low cost, and a process for producing a practically useful polythiourethane resin exhibiting a stable great refractive index and a great Abbe number is provided.
US07872091B2 Electrical insulation system based on poly(butylene terephthalate)
An electrical insulation system and method are disclosed which are based on poly(butylene terephthalate), wherein the poly(butylene terephthalate) contains a polymerized cyclic low molecular weight oligomeric poly(butylene terephthalate) resin. At least one filler material or a mixture of filler materials can be included. At least one hydrophobic compound or a mixture of hydrophobic compounds can also be included.
US07872085B2 Biaxially oriented polyproplyene film
The present invention relates to a biaxially oriented polypropylene film containing: a polypropylene resin as a main component thereof, having a weight average molecular weight of 100,000 or more and 500,000 or less, the weight average molecular weight being determined by gel permeation chromatography, wherein at least one surface of the biaxially oriented polypropylene film has a protrusion volume of 2.0×104 μm3 or more and 3.0×104 μm3 or less, the protrusion volume being determined in an area of 560 μm×745 μm using a super-depth surface profile measurement microscope by determining an average plane of the surface based on distances between plural points on the surface and an irradiation source of the super-depth surface profile measurement microscope and measuring a volume of protrusions projecting from the average plane.
US07872081B2 Melt-processible poly(tetrafluoroethylene)
Melt-processible, thermoplastic poly(tetrafluoroethylene) (PTFE) compositions are disclosed and methods for making and processing same. Additionally, products comprising these compositions are described.
US07872078B2 Curable film-forming compositions demonstrating self-healing properties
The present invention is directed to curable film-forming compositions comprising: (a) a polymeric binder comprising a polyester having hydroxyl functional groups; and (b) a curing agent comprising a polyisocyanate having at least three isocyanate functional groups. In certain embodiments, after application to a substrate as a coating and after curing, the compositions demonstrate a Fisher microhardness of at least 120 at ambient temperatures of 15 to 25° C. and a softening point greater than or equal to 35° C. Additionally, in certain embodiments, after application to a substrate as a coating and after curing, the compositions demonstrate a 20° gloss recovery of at least 75% when subjected to the DRY ABRASION TEST METHOD.
US07872076B2 Particulate water-absorbent resin composition and its production process
An object of the present invention is to provide a particulate water-absorbent resin composition and its production process, wherein the particulate water-absorbent resin composition is an enhanced one in both of the “liquid permeability” and “liquid-sucking-up property” (which have hitherto been antithetical physical properties) of the water-absorbent resin. As a means of achieving this object, a first particulate water-absorbent resin composition according to the present invention is a particulate water-absorbent resin composition comprising a water-absorbent resin (A) of a crosslinked structure obtained by polymerizing an acid-group-containing unsaturated monomer, with the composition being characterized by: having a particle size such that particles in the range of 850 to 150 μm (but not including 850 μm) account for not less than 90 weight % of the entirety; and containing a tetra- or more functional polyol (B) at least on surfaces.
US07872071B2 Polyethylene molding composition for coating steel pipes
The invention relates to a polyethylene molding composition which has a multimodal molar mass distribution and is particularly suitable for producing protective coatings on steel pipes. The molding composition has a density at a temperature of 23° C. in the range from 0.94 to 0.95 g/cm3 and an MFI190/5 in the range from 1.2 to 2.1 dg/min. It comprises from 45 to 55% by weight of a low molecular weight ethylene homopolymer A, from 30 to 40% by weight of a high molecular weight copolymer B of ethylene and another olefin having from 4 to 8 carbon atoms and from 10 to 20% by weight of an ultra high molecular weight ethylene copolymer C.
US07872069B2 Coated substrates and polymer dispersions suitable for use in making the same
A coated substrate comprises a substrate and a coating on at least one surface of the substrate. The coating comprises a prepolymer, polymer, or resin produced, for example, by the reaction of (i) an isocyanate (e.g., a polyisocyanate), (ii) an active hydrogen-terminated colorant, and optionally (iii) at least one reactant selected from the group consisting of chain extenders, polyols, internal surfactants, and combinations thereof. Polymer dispersions suitable for use in making such coated substrates comprise such a prepolymer, polymer, or resin.
US07872067B2 Amphiphilic polymer compositions and their use
The present invention relates to amphiphilic polymer compositions, to a process for their preparation and to their use for preparing aqueous active compound compositions of water-insoluble active compounds, in particular active compounds for crop protection.The amphiphilic polymer compositions can be obtained by reacting a) at least one hydrophobic polymer P1 which carries functional groups R1 which are reactive toward isocyanate groups and which is constructed of ethylenically unsaturated monomers M1, comprising: a1) at least 10% by weight, based on the total amount of monomers M1, of monomers M1a of the formula I  in which X is oxygen or a group N—R4; R1, R2, R3 and R4 are as defined in the claims and the description; a2) up to 90% by weight, based on the total amount of monomers M1, of neutral monoethylenically unsaturated monomers M1b whose solubility in water at 25° C. is less than 50 g/l and which are different from the monomers M1a; and a3) up to 30% by weight, based on the total amount of monomers M1, of ethylenically unsaturated monomers M1c which are different from the monomers M1a and M1b, b) at least one hydrophilic polymer P2 which carries functional groups R2 which are reactive toward isocyanate groups, c) with at least one compound V which contains isocyanate groups and, with respect to the isocyanate groups, has a functionality of at least 1.5.
US07872066B2 Rubber composition for belt use and rubber belt
The invention provides a rubber composition for belt use suitable for industrial rubber belts with less energy loss and excellent durability such resistance to flex crack growth.The rubber composition for belt use comprises (A) 90-5 mass % of a vinyl-cis-polybutadiene rubber including (b) 1-30 mass % of specific syndiotactic 1,2-polybutadiene crystal fibers having an average fiber length of crystal fibers equal to 200 nm or below, an average aspect ratio of 10 or lower, the number of crystal fibers having a fiber length of 200 nm or below equal to 90 or more per 25 μm2, and a melting point of 170° C. or higher, and (a) 99-70 mass % of a cis-polybutadiene rubber; (B) 10-95 mass % of a diene-based rubber other than (A); and (C) 20-70 parts by mass of a rubber reinforcing agent compounded on the basis of 100 parts by mass of the rubber components (A)+(B), wherein the rubber reinforcing agent (C) contains at least carbon black and silica, wherein the compounding amount of the silica in the rubber reinforcing agent is 70 mass % or less.
US07872062B2 Control of pH in formaldehyde-free binder systems
A system for controlling the pH of a formaldehyde-free aqueous binder composition used in the manufacture of glass fiber products. Following the formation of an aqueous binder composition, acid is added to the composition to reduce the pH to less than about 3.4. After the acid is combined with the aqueous binder composition, the pH of the composition is measured and then compared within a pre-set set point. The rate of acid addition is then adjusted thereby adjusting the pH of the composition such that the measured pH equals the set point pH. The pH measurement is preferably done before the addition of other additives to avoid interference by those additives.
US07872059B2 Composition for use in laser decomposition and pattern-forming material using the same
A composition for use in laser decomposition includes (A) at least one of a polymer having a nitrogen atom-containing hetero ring and a polymerizable compound having a nitrogen atom-containing hetero ring; and (B) a metal ion.
US07872057B2 Dual cure composition
A liquid radiation and thermally curing composition characterized in, that said composition comprises at least one ester between at least one tri or polyalcohol and acrylic and/or methacrylic acid, which ester has at least two hydroxyl groups, at least one acrylic or methacrylic double bond, a hydroxyl value of 50-500 mg KOH/g and a double bond concentration of 1-10 mmoles/g, at least one crosslinking agent for hydroxyl functional compounds, which crosslinking agent optionally has at least one olefinic double bond, and an additive package comprising at least one photoinitiator, radical scavenger, light stabilizer, wetting agent and/or leveling agent, and optionally at least one monomeric or oligomeric reactive diluent.
US07872056B2 Polymer blends of biodegradable or bio-based and synthetic polymers and foams thereof
The present invention relates to compositions comprising blends of alkenyl aromatic polymers such as styrenic polymers (i.e. PS and HIPS) and bio-based or biodegradable polymers (i.e. PLA, PGA, PHA, PBS, PCL) compatibilized with styrene-based copolymers (i.e. styrene-ethylene-butylene-styrene (SEBS) block copolymers, maleated SEBS, styrene-maleic anhydride (SMA) copolymer, styrene-methyl methacrylate (SMMA) copolymer) or a mixture of two or more styrene-based copolymers such as SEBS and SMA. These novel compositions can be extruded and thermoformed to produce very low density food service and consumer foam articles such as plates, hinged lid containers, trays, bowls, and egg cartons with good mechanical properties.
US07872055B2 Catalyst composition for water blown, low density, rigid polyurethane foam
A method for preparing a water blown, low density, rigid polyurethane foam which comprises contacting at least one polyisocyanate with at least one polyol, at an Isocyanate Index of 70 to 200, in the presence of a blowing agent composition comprising at least 75 wt % water and an effective amount of a catalyst composition comprising a gelling catalyst which is bis-(N,N-dimethylaminopropyl)amine and a blowing catalyst which is N,N-dimethylaminoethyl-N′-methyl-ethanolamine, the foam having a density of 6 to 16 Kg/m3.
US07872054B2 Method for producing bio-fuel that integrates heat from carbon-carbon bond-forming reactions to drive biomass gasification reactions
A low-temperature catalytic process for converting biomass (preferably glycerol recovered from the fabrication of bio-diesel) to synthesis gas (i.e., H2/CO gas mixture) in an endothermic gasification reaction is described. The synthesis gas is used in exothermic carbon-carbon bond-forming reactions, such as Fischer-Tropsch, methanol, or dimethylether syntheses. The heat from the exothermic carbon-carbon bond-forming reaction is integrated with the endothermic gasification reaction, thus providing an energy-efficient route for producing fuels and chemicals from renewable biomass resources.
US07872053B2 Surface active organosilicone compounds
The present invention relates to new organodisilanes or carbodisilanes, a process for manufacturing the same and their use, in particular, as surface active agents, especially as spreading agents.
US07872049B2 Long-term stable pharmaceutical preparation containing the active ingredient glyceryl trinitrate
A pharmaceutical preparation containing the active substance glyceryl trinitrate having improved storage stability in a container. The improved storage stability is achieved by the addition of a proton-absorbing substance either as part of the preparation as placed into the container or applied to the surface of the preparation's storage container before the remaining components of the preparation are placed into the container. The preparation can preferably be filled into a plastic bottle having a spray pump.
US07872046B2 Crystalline form of a (3S)-aminomethyl-5-methyl-hexanoic acid prodrug and methods of use
A crystalline form of a (3S)-aminomethyl-5-hexanoic acid prodrug and methods of preparing a crystalline form of a (3S)-aminomethyl-5-hexanoic acid prodrug, and methods of using a crystalline form of a (3S)-aminomethyl-5-hexanoic acid prodrug are provided.
US07872045B2 Combination therapy for glaucoma treatment
A method is disclosed herein comprising administering a compound and a second drug to an eye of a mammal for the treatment of glaucoma or the reduction of intraocular pressure, said compound represented by the general formula I; wherein A, B, D, X, Y, Z, R1, R3 and R4 are as defined in the specification.
US07872044B2 Inhibitors of chymase
The present invention is directed to a compound of Formula (I): or an enantiomer, diastereomer, polymorph or pharmaceutically acceptable salt thereof and methods for preparing said compounds and compositions, intermediates and derivatives thereof, and methods for treating inflammatory or serine protease mediated disorders.
US07872043B2 Use of furan alkyls for a cellulite cosmetic treatment
The invention relates to the use of one or several synthetic or natural furan alkyls for cosmetically treating cellulite. Said furan alkyls preferably correspond to formula (I), wherein identical or different R1, R2, R3et R4 are independently of each other a hydrogen atom, a C1-C35alkyl radical, C1-C35 alcenyl radical or a C1-C35 alcynyl radical, preferably C10-C22, wherein said alkyl, alcenyl and alcynyl radicals are substitutable and R1, R2, R3 are preferably a hydrogen atom.
US07872040B2 Receptor blocker and vasodilator comprising indole derivative as active ingredient
It is intended to find a compound that is structurally simpler than yohimbine, a pentacyclic condensed heterocyclic compound, and has an effect similar to that of yohimbine.The present invention relates to a pharmaceutical or food composition for α2 receptor blockage comprising a compound represented by the formula (I) or a pharmaceutically acceptable salt thereof: (wherein R1 represents a hydrogen, alkyl group, alkenyl group, alkynyl group, aromatic group, aralkyl group, acyl group, arylsulfonyl group, alkylsulfonyl group, or hydroxyl group; R2 represents a hydrocarbon group; R3, R4, R5, R6, and R7 are the same or different and represent a hydrogen, halogen, alkyl group, or alkoxy group; R8 represents a hydrogen or acyl group; n represents an integer of 1 to 6; and a and b are the same or different and represent 1 or 0).
US07872036B2 3-triazolylphenyl sulfide derivative and insecticide, miticide and nematicide containing it as an active ingredient
To provide novel 3-triazolylphenyl sulfide derivatives having excellent soil treatment activity as insecticides, miticides or nematicides for agricultural and horticultural plants.3-Triazolylphenyl sulfide derivatives represented by the formula [1]: wherein R is a cyclopropylmethyl group or a trifluoroethyl group, B2 is a hydrogen atom, a halogen atom or a methyl group, B4 is a halogen atom, a cyano group, a nitro group or a C1-C6 alkyl group, and each of A1 and A3 is a hydrogen atom, a halogen atom, a C1-C6 alkyl group which may be substituted or an amino group which may be substituted.
US07872035B2 Angiotensin II antagonists
The present invention relates to the use of an angiotensin II type 1 receptor antagonist of the general formula (I) in the manufacture of a medicament for the prophylactic and/or therapeutic treatment of a vascular headache condition such as migraine, in a subject suffering from, or susceptible to, such a vascular headache condition. A further aspect of the invention is a pharmaceutical formulation useful in any one of said vascular headache conditions, as well as a method of treatment thereof.
US07872031B2 c-MET protein kinase inhibitors
The present invention relates to compounds useful of inhibitors of protein kinases. The invention also provides processes for preparing the compounds of this invention, pharmaceutically acceptable compositions comprising the compounds of the invention, and methods of using the compositions in the treatment of various disorders.
US07872030B2 Use of 2-[5-(4-fluorophenyl)-3-pyridylmethylaminomethyl]-chromane and its physiologically acceptable salts
(R/S)-(−/+)-2-[5-(4-fluorophenyl)-3-pyridylmethylaminomethyl]-chromane or a physiologically acceptable salt thereof and/or (S)-(+)-2-[5-(4-fluorophenyl)-3-pyridylmethylaminomethyl]-chromane or a physiologically acceptable salt thereof are used for the manufacture of a medicament for the treatment of extrapyramidal movement disorders and/or adverse effects in extrapyramidal movement disorders.
US07872026B2 Ligand activators of the RAR receptors and pharmaceutical/cosmetic applications thereof
Novel ligand compounds having the structural formula (I): in which: Ar is a radical selected from among the radical of formulae (a) to (c) below: are formulated into pharmaceutical compositions suited for administration in human or veterinary medicine, or, alternatively, into cosmetic compositions.
US07872024B2 Benzothiophene hydroxamic acid derivatives with carbamate, urea, amide and sulfonamide substitutions
The present invention relates to a novel class of hydroxamic acid derivatives carbamate, urea, amide and sulfonamide substitutions. The hydroxamic acid compounds can be used to treat cancer. The hydroxamic acid compounds can also inhibit histone deacetylase and are suitable for use in selectively inducing terminal differentiation, and arresting cell growth and/or apoptosis of neoplastic cells, thereby inhibiting proliferation of such cells. Thus, the compounds of the present invention are useful in treating a patient having a tumor characterized by proliferation of neoplastic cells. The compounds of the invention are also useful in the prevention and treatment of TRX-mediated diseases, such as autoimmune, allergic and inflammatory diseases, and in the prevention and/or treatment of diseases of the central nervous system (CNS), such as neurodegenerative diseases. The present invention further provides pharmaceutical compositions comprising the hydroxamic acid derivatives and safe dosing regimens of these pharmaceutical compositions, which are easy to follow, and which result in a therapeutically effective amount of the hydroxamic acid derivatives in vivo.
US07872020B2 TGF-β inhibitors
The present invention provides crystalline 2-(6-methyl-pyridin-2-yl)-3-[6-amido-quinolin-4-yl)-5,6-dihydro -4H-pyrrolo[1,2-b]pyrazole monohydrate.
US07872016B2 Method for treating skeletal disorders resulting from FGFR malfunction
The invention provides materials, reagents, systems, and methods for identifying agents useful for treating diseases resulting from abnormal (e.g., excessive) FGF receptor signaling. The invention also provides (therapeutic) agents thus identified, and methods of using such agents in treating such diseases. In certain embodiments, the invention relates to the treatment of various craniofacial disorders, or Craniosynostosis, that result from FGFR (e.g. FGFR2) malfunction, such as Crouzon, Apert, Jackson-Weiss, Pfeiffer Syndromes, Crouzon+acanthosis nigricans, Beare-Stevenson cutis gyrata, and non-syndromic craniosynostosis (NS). The methods comprise administering to the individuals a therapeutically effective amount of an inhibitor of the FGFR2c-FRS2 signaling. The inhibitor inhibits signaling by antagonizing FGFR2c-FRS2 interaction, inhibiting the expression and/or subcellular localization of wild-type or mutant FGFR2c and/or FRS2, inhibiting the kinase activity of FGFR2c (e.g. for autophosphorylation and/or phosphorylation of FRS2), and/or inhibiting downstream signaling of FRS2 (such as Sos-Ras-MAPK, Shp2, and/or Gab 1-PI3K pathways).
US07872013B2 Preparation and utility of opioid analgesics
The present disclosure is directed to modulators of opiate- and/or NMDA receptors and pharmaceutically acceptable salts and prodrugs thereof, the chemical synthesis thereof, and the use of such compounds for the treatment and/or management of pain, anxiety, neurodegeneration, drug dependence, coughing, muscular tension, and/or glaucoma and any other condition in which it is beneficial to modulate an opiate- and/or NMDA receptor.
US07872010B2 Substituted diazabicycloalkane derivatives having affinity for nicotinic acetylcholine receptors
Provided herein are compositions of a class of substituted diazabicycloalkane derivative compounds, which are useful as modulators of nicotinic acetylcholine receptors. The compounds are useful in treating conditions and disorders prevented by, or ameliorated by, nicotinic acetylcholine receptors.
US07872008B2 Method for treating insulin resistance, abdominal obesity, hypertension, hyperinsulinemia, and elevated blood lipids with a cortisol inhibitor
The invention concerns the use of ketoconazole and derivatives having a corresponding biological activity, and combinations thereof, in the treatment of abdominal obesity, hypertension, hyperinsulinemia, and elevated blood lipids.
US07872005B2 2-substituted heteroaryl compounds
This invention relates to compounds of formula (I): or pharmaceutically acceptable salts, solvate, clathrates hydrates or polymorphs thereof, their compositions and methods of use and methods of making thereof. The compounds (and compositions) are useful in modulating IL-12 production and processes mediated by IL-12.
US07872004B2 6-(heterocyclyl-substituted benzyl)-4-oxoquinoline compound and use thereof as HIV integrase inhibitor
The present invention relates to a compound represented by the following formula [I] wherein each symbol is as defined in the specification, or a pharmaceutically acceptable salt thereof, or a solvate thereof, and a pharmaceutical composition, an anti-HIV agent and an HIV integrase inhibitor containing such compound. The compound of the present invention has an HIV integrase inhibitory activity, and is useful as an anti-HIV agent, or as an agent for the prophylaxis or treatment of AIDS. In addition, by the combined use with other anti-HIV agents such as a protease inhibitor, a reverse transcriptase inhibitor and the like, it can be a more effective anti-HIV agent. Because it shows integrase-specific high inhibitory activity, the compound can be a pharmaceutical agent safe on human body, which causes only a fewer side effects.
US07872001B2 Gamma d-crystalline form of ivabradine hydrochloride, a process for its preparation and pharmaceutical compositions containing it
A γd-Crystalline form of ivabradine hydrochloride of formula (I): characterised by its powder X-ray diffraction data. Medicinal products containing the same which are useful as bradycardics.
US07871999B2 Substituted thiazoles and their use for producing drugs
The present invention relates to substituted thiazoles, to methods for the production thereof, to medicaments containing these compounds and to the use thereof for producing medicaments.
US07871995B2 Drug delivery system comprising a tetrahydroxylated estrogen for use in hormonal contraception
A method of contraception in mammalian females, which method comprises the parenteral or rectal administration of an estrogenic component and a progestogenic component to a female of childbearing capability in an amount effective to inhibit ovulation, wherein the estrogenic component is selected from the group consisting of substances represented by the following formula (1) in which R1, R2, R3, R4 independently are a hydrogen atom, a hydroxyl group or an alkoxy group with 1-5 carbon atoms; each of R5, R6, R7 is a hydroxyl group; and no more than 3 of R1, R2, R3, R4 are hydrogen atoms; precursors capable of liberating a substance according to the aforementioned formula when used in the present method; and mixtures of one or more of the aforementioned substances and/or precursors. Another aspect of the invention concerns a drug delivery system for parenteral or rectal administration that contains the aforementioned estrogenic component and a progestogenic component, said drug delivery system being selected from the group consisting of suppositories, systems for intravaginal delivery, inhalers, nasal sprays and transdermal delivery systems.
US07871991B2 Phosphonate analogs of HIV inhibitor compounds
The invention is related to phosphorus substituted anti-viral inhibitory compounds, compositions containing such compounds, and therapeutic methods that include the administration of such compounds, as well as to processes and intermediates useful for preparing such compounds.
US07871988B1 Nanoparticles for protein drug delivery
The invention discloses the nanoparticles composed of chitosan, poly-glutamic acid, and at least one protein drug or bioactive agent characterized with a positive surface charge and their enhanced permeability for paracellular protein drug and bioactive agent delivery.
US07871985B2 Compositions and methods for inhibiting expression of factor VII gene
The invention relates to a double-stranded ribonucleic acid (dsRNA) for inhibiting the expression of the Factor VII gene.
US07871980B2 Method of treating mouse carrying human hepatocytes
Human adult hepatocytes are transplanted into an immunodeficient hepatopathy mouse and then human growth hormone is administered to the mouse to thereby elevate twice or more the replacement ratio by the human adult hepatocytes having been transplanted. Further, human growth hormone is administered to an immunodeficient hepatopathy mouse carrying human young hepatocytes transplanted thereinto so as to improve fatty liver of the mouse in which about 70% or more of the hepatocytes have been replaced by the human hepatocytes.
US07871978B2 Bone tropic peptides
The present invention is directed to the use of bone tropic peptides identified through the use of a phage display library. More particularly, the invention is directed to compositions comprising the bone tropic peptides and methods for using such compositions to regulate osteogenesis, cell adhesion and angiogenesis, and diseases and disorders thereof, and to inhibit cancer cell metastasis and growth.
US07871977B2 Process for producing sterile suspensions of slightly soluble basic peptide complexes, sterile suspensions of slightly soluble basic peptide complexes, pharmaceutical formulations containing them, and the use thereof as medicaments
The present invention provides a novel process for producing sterile suspensions of slightly soluble basic peptide complexes. The present invention further provides a novel process for producing sterile lyophilizates of slightly soluble basic peptide complexes. In addition, a novel process for producing sterile suspensions suitable for the parenteral administration of slightly soluble basic peptide complexes is provided. The invention moreover provides sterile suspensions and sterile lyophilizates of slightly soluble basic peptide complexes, and pharmaceutical formulations comprising them. The provided sterile suspensions, sterile lyophilizates and pharmaceutical formulations comprising them are particularly suitable for use in a parenteral dosage form as medicaments for the treatment and prophylaxis of diseases and pathological states in mammals, especially in humans.
US07871976B1 Laundry scent additive
A laundry scent additive having polyethylene glycol and perfume. The laundry scent additive enables consumers to control the amount of scent imparted to their laundry.
US07871974B2 Process for making bleach particles
A process for making bleach granules comprising a bleach selected from the group of diacyl, tetraacyl peroxide and mixtures thereof, selected from diacyl peroxides of the general formula: R1—C(O)—OO—(O)C—R2 in which R1 represents a C6-C18 alkyl group and R2 represents an aliphatic group compatible with a peroxide moiety, such that R1 and R2 together contain a total of 8 to 30 carbon atoms; the tetraacyl peroxide is selected from tetraacyl peroxides of the general formula: R3—C(O)—OO—C(O)—(CH2)n-C(O)—OO—C(O)—R3 in which R3 represents a C1-C9 alkyl group and n represents an integer from 2 to 12, wherein the process comprises the step of dry granulating the diacyl and/or tetraacyl peroxide.
US07871973B1 Highly branched primary alcohol compositions, and biodegradable detergents made therefrom
There is provided a new branched primary alcohol composition and the sulfates thereof exhibiting good cold water detergency and biodegradability. The branched primary alcohol composition has an average number of branches per chain of at least 0.7, having at least 8 carbon atoms and containing both methyl and ethyl branches. The primary alcohol composition may also contain less than 0.5 atom % of quaternary carbon atoms, and a significant number ethyl branches, terminal isopropyl branches, and branching at the C3 position relative to the hydroxyl carbon. The process for its manufacture is by skeletally isomerizing an olefin feed having at least 7 carbon atoms followed by conversion to an alcohol, as by way of hydroformylation, and ultimately, sulfation to obtain a detergent surfactant. Useful catalysts include the zeolites having at least one channel with a crystallographic free diameter along the x and/or y planes of the [001] view ranging from greater than 4.2 Å and less than 7 Å. but allows one to skeletally isomerize the olefin to produce a variety of branches, while retaining ready biodegradability and good cold water detergency.
US07871970B2 Formulations of carboxylic acid diesters useful for treating/cleaning textile and other materials
Carboxylic acid diesters are employed for treating, in particular for cleaning textile and other materials, and more particularly for removing paint stains from textile fibers to improve the cleaning thereof; the subject formulations contain at least one dicarboxylic acid diester having the formula (I), R1—OOC-A-COO—R2, in which R1 and R2, which may be the same or different, are each a linear or branched, cyclic or non-cyclic C1-C20 alkyl, aryl, alkyaryl, or arylalkyl radical; and the group A is a branched divalent alkylene radical; and including at least one nonionic polyalkoxylated terpene surfactant.
US07871969B2 Mild cleansing soap bars
A personal cleansing composition in solid or bar form which is mild to the skin and very effective in removing dirt and grime from the body, particularly the hands. Importantly, such soap bars do not have a noticeable abrasive feel when in contact with the skin. Another feature is that the bar exhibits a so called “drag effect” when the soap bar is used for washing.
US07871968B2 Medicinal soap comprising sapropel
The present invention provides soap, including glycerine and sapropel. It also provides therapeutic uses thereof.
US07871966B2 Lubricating oil composition
The present invention provides a lubricating oil composition, which is capable to maintain sufficient low-friction (i.e. fuel saving performance) even when the lubricating oil is contaminated with soot and metal abrasion powder, which is excellent in durability with regard to anti-wear property and detergency, as well as oxidation stability, and which is capable to lower the ash content and to sufficiently maintain the performance of exhaust-gas after-treatment device for a long term. The lubricating oil composition comprises a lubricant base oil containing a base oil (X) of which % CP is 70 or more, % CA is 1 or less, viscosity index is 115 or more, and CCS viscosity at −35° C. is 3000 mPa·s or less, wherein the lubricant base oil, to total mass of the composition, contains following components (A)˜(D):(A) 0.01˜10 mass % of ashless friction modifier;(B) 0.01˜0.2 mass % of phosphorus-containing anti-wear agent as phosphorous content;(C) 0.01˜1 mass % of metallic detergent as metal content; and(D) 0.01˜0.4 mass % of ashless dispersant having 3000˜20000 of weight-average molecular weight as nitrogen content.
US07871964B2 Compositions and methods for mitigating or preventing emulsion formation in hydrocarbon bodies
A composition for mitigating or preventing the formation of an emulsion between naphthenic acid and metal cations in a hydrocarbon body, the composition including at least one alkoxylated amine and at least one acid and/or alcohol is disclosed.
US07871963B2 Tunable surfactants for oil recovery applications
The systems and methods described herein provide for modified lignins and other compositions that may be useful as surfactants. These compositions have particular utility for energy-related applications. In embodiments, they may be useful for enhanced oil recovery. In embodiments, they may be useful for extracting bitumen from oil sands. In embodiments, they may be useful for environmental remediation.
US07871959B2 Heat-sensitive transfer image-receiving sheet
A heat-sensitive transfer image-receiving sheet, having a support and a receptor layer containing at least one polymer selected from the group consisting of polyester polymers and polycarbonate polymers, and further having between the support and the receptor layer an intermediate layer containing hollow polymer particles.
US07871958B2 Catalyst carrier
A catalyst carrier includes a honeycomb structure where cells extending in a longitudinal direction are divided by cell walls; and a coating layer provided at a peripheral part of the honeycomb structure. The honeycomb structure and the coating layer contain at least one of inorganic fibers and whiskers. At least one of the inorganic fiber and whisker contained in the honeycomb structure is oriented mainly in a first direction. At least one of the inorganic fiber and whisker contained in the coating layer is oriented mainly in a second direction. The first direction and the second direction cross at substantially right angles to each other.
US07871956B2 Cerium/zirconium-base composite oxide, method for producing the same, oxygen storage/release component using said cerium-zirconium-base composite oxide, exhaust gas purification catalyst, and exhaust gas purification method using the same
This invention relates to a cerium-zirconium-base composite oxide, which is useful, e.g., for the purification of exhaust gas discharged from combustion engines such as internal combustion engines and boilers and can release a high level of oxygen in a low temperature region, a method for producing the same, an oxygen storage/release component using the same, an exhaust gas purification catalyst, and an exhaust gas purification method. The cerium-zirconium-base composite oxide satisfies requirements (1) that the oxygen release initiation temperature is 380° C. or below, (2) that the oxygen release amount is not less than 485 μmol/g, and further (3) that the oxygen release amount at 400° C. is not less than 15 μmol/g. The cerium-zirconium-base composite oxide can be produced, for example, by mixing a starting material for cerium and a starting material for zirconium at a predetermined mixing ratio together, melting the starting material mixture at a temperature at or above the melting point, then cooling the melt to form an ingot, then optionally grinding the ingot to prepare powder, subsequently removing strain within powder crystal grains under heating, and then grinding to a further fine state.
US07871954B2 Synthesis of carbon supported platinum-tungsten electrocatalysts
The present teachings are directed toward methods of producing electrocatalyst compositions of platinum and tungsten through the thermal decomposition of carbonyl-containing complexes of the two metals.
US07871951B2 Magnesium compound, solid catalyst component, catalyst for olefin polymerization and method of producing polyolefin
A method for producing magnesium compound represented by formula (I): Mg(OEt)2-n(OMe)n  (I) where Et is an ethyl group, Me is a methyl group and n is a numerical value of from 0.001 to 1, by reacting metal magnesium, ethanol, methanol and a halogen and/or a halogen-containing compound containing at least 0.0001 gram atom of a halogen atom relative to one gram atom of the metal magnesium. A method of producing a solid catalyst component.
US07871950B2 Colored zirconia-based sintered body and manufacturing method thereof and decorative member
This invention provides a colored zirconia-based sintered body, mainly composed of zirconia containing a stabilizer, which contains alumina and nickel spinel, and has a novel color tone, and a method for manufacturing such a zirconia-based sintered body. The colored zirconia-based sintered body is applicable not only to a highly decorative product such as a watch, but also to knives, tweezers, machining jigs and holding jigs for electronic parts, and sliding members.
US07871949B2 Glass plate with glass frit structure
A light emitting device includes: a first substrate; a second substrate; a light emitting unit interposed between the first substrate and the second substrate; and a sealing material bonding the first substrate to the second substrate and sealing the light emitting unit. The sealing material comprises V+4. In addition, a glass frit, a composition for forming a sealing material, and a method of manufacturing a light emitting device using the composition for forming a sealing material are provided to obtain the light emitting device. The sealing material of the light emitting device can be easily formed by coating and irradiation of electro-magnetic waves, so that manufacturing costs are low and deterioration of the light emitting unit occurring when sealing material is formed can be substantially prevented. The sealing material has good sealing properties and thus a light emitting device including the sealing material has a long lifetime.
US07871948B2 Lithium silicate glass ceramic
Lithium silicate materials are described which can be easily processed by machining to dental products without undue wear of the tools and which subsequently can be converted into lithium silicate products showing high strength.
US07871944B2 Process for applying interface coatings and manufacturing composite materials using same
A process for applying an interface coating includes the step of applying an interface coating material upon at least one surface of a fiber-based substrate. The interface coating material may be composed of a sizing agent, a ceramic powder and optionally at least one of the following agents: a dispersing agent, a deflocculating agent or a surface wetting agent.
US07871943B2 Method of making transistor gates with controlled work function
Embodiments of the invention provide methods for making an integrated circuit comprising providing a substrate, forming a structured layer stack on the substrate comprising a dielectric layer located on the substrate and an oxide-free metallic layer located on the dielectric layer, wherein the metallic layer comprising a transition metal. The method further comprises oxidizing the metallic layer, thereby increasing a work function of the metallic layer. Moreover, a substrate for making an integrated circuit is described.
US07871939B2 Method for manufacturing semiconductor device using a free radical assisted chemical vapor deposition nitrifying process
A method for manufacturing a semiconductor device for use in avoiding unwanted oxidation along exposed surfaces and for use in relieving etching damage is presented. The method includes step of forming sequentially a gate insulation layer, a polysilicon layer, a barrier layer, a metallic layer and a hard mask layer over a semiconductor substrate. The method also includes a step of etching the hard mask layer, the metallic layer, the barrier layer, the polysilicon layer and the gate insulation layer to form a gate. The method also includes a nitrifying step which uses a free radical is assisted chemical vapor deposition (RACVD) nitrifying process on surfaces of the layers forming the gate and a surface of the semiconductor substrate. The method also includes a step of subsequently performing a reoxidation process to the semiconductor substrate resultant that the RACVD nitrifying process is performed.
US07871937B2 Process and apparatus for treating wafers
Methods and systems are provided for low pressure baking to remove impurities from a semiconductor surface prior to deposition. Advantageously, the short, low temperature processes consume only a small portion of the thermal budget, while still proving effective at removing interfacial oxygen from the semiconductor surface. The methods and systems are particularly well suited for treating semiconductor surfaces before epitaxy.
US07871934B2 Method for an integrated circuit contact
A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multilevel metal integrated circuits.
US07871925B2 Stack package and method for manufacturing the same
A stack package comprises a substrate having a circuit pattern; at least two semiconductor chips stacked on the substrate, having a plurality of through-via interconnection plugs and a plurality of guard rings which surround the respective through-via interconnection plugs, and connected with each other by the medium of the through-via interconnection plugs; a molding material for molding an upper surface of the substrate including the stacked semiconductor chips; and solder balls mounted to a lower surface of the substrate.
US07871924B2 Semiconductor device having copper wiring
A first interlayer insulating film made of insulting material is formed over an underlying substrate. A via hole is formed through the first interlayer insulating film. A conductive plug made of copper or alloy mainly consisting of copper is filled in the via hole. A second interlayer insulating film made of insulating material is formed over the first interlayer insulating film. A wiring groove is formed in the second interlayer insulating film, passing over the conductive plug and exposing the upper surface of the conductive plug. A wiring made of copper or alloy mainly consisting of copper is filled in the wiring groove. The total atom concentration of carbon, oxygen, nitrogen, sulfur and chlorine in the conductive plug is lower than the total atom concentration of carbon, oxygen, nitrogen, sulfur and chlorine in the wiring.
US07871922B2 Methods for forming interconnect structures that include forming air gaps between conductive structures
A method for forming a semiconductor structure includes forming a sacrificial layer over a substrate. A first dielectric layer is formed over the sacrificial layer. A plurality of conductive structures are formed within the sacrificial layer and the first dielectric layer. The sacrificial layer is treated through the first dielectric layer, at least partially removing the sacrificial layer and forming at least one air gap between two of the conductive structures. A surface of the first dielectric layer is treated, forming a second dielectric layer over the first dielectric layer, after the formation of the air gap. A third dielectric layer is formed over the second dielectric layer. At least one opening is formed within the third dielectric layer such that the second dielectric layer substantially protects the first dielectric layer from damage by the step of forming the opening.
US07871920B2 Semiconductor chips with reduced stress from underfill at edge of chip
Structures and methods for forming the same. A semiconductor chip includes a semiconductor substrate and a transistor on the semiconductor substrate. The chip further includes N interconnect layers on top of the semiconductor substrate and being electrically coupled to the transistor, N being a positive integer. The chip further includes a first dielectric layer on top of the N interconnect layers, and a second dielectric layer on top of the first dielectric layer. The second dielectric layer is in direct physical contact with each interconnect layer of the N interconnect layers. The chip further includes an underfill layer on top of the second dielectric layer. The second dielectric layer is sandwiched between the first dielectric layer and the underfill layer. The chip further includes a laminate substrate on top of the underfill layer. The underfill layer is sandwiched between the second dielectric layer and the laminate substrate.
US07871917B2 Semiconductor device and manufacturing method for the same
To provide a low-cost, easy-to-use, and efficient method for manufacturing a semiconductor device, which eliminates the need for the formation or removal of barrier metals upon formation of bumps, and a high-performance semiconductor device with fine bumps arranged at a narrow pitch. The method includes: forming a plurality of electrode pads 12 on one surface of a semiconductor substrate 10; forming insulating layers (e.g., inorganic insulating layer 14 and organic insulating layer 16) to cover the perimeter of each electrode pad 12; selectively forming a mask layer 20 on the insulating layers 14 and 16; cleaning the surface of the electrode pads 12 which is not covered with the insulating layers 14 and 16; forming external terminals 46 in regions defined by the insulating layers 14 and 16 and mask layer 20 so that they are in contact with the electrode pads 12; and removing the mask layer 20.
US07871915B2 Method for forming metal gates in a gate last process
The present disclosure provides a method of fabricating a semiconductor device that includes providing a substrate having a first region and a second region, forming first and second gate stacks in the first and second regions, respectively, the first gate stack including a first dummy gate and the second gate stack including a second dummy gate, removing the first dummy gate in the first gate stack thereby forming a first trench and removing the second dummy gate in the second gate stack thereby forming a second trench, forming a first metal layer in the first trench and in the second trench, removing at least a portion of the first metal layer in the first trench, forming a second metal layer in the remainder of the first trench and in the remainder of the second trench, reflowing the second metal layer, and performing a chemical mechanical polishing (CMP).
US07871912B2 Methods of making semiconductor-based electronic devices by forming freestanding semiconductor structures
Various methods for forming active electronic devices, such as field-effect transistors, and devices made using these methods are disclosed. Some of the methods include growing freestanding nano-, micro- and milli-scale semiconducting structures that are used for the active semiconducting channels of the active electronic devices. Others of the methods include forming strands of active electronic devices along a wire. Yet others of the methods utilize both of these concepts so that the active electronic devices on a particular strand include freestanding semiconducting structures.
US07871905B2 Method for producing semiconductor device
A method for producing a device includes embedding trenches with an epitaxial layer having high crystallinity while a mask oxide film remains unremoved. An n-type semiconductor is formed on the surface of a silicon substrate, and a mask oxide film and a mask nitride film are formed on the surface of the n-type semiconductor. The mask laminated film is opened by photolithography and etching, and trenches are formed in the silicon substrate. The width of the remaining mask laminated film is narrowed, whereby portions of the n-type semiconductor close to the opening ends of the trenches are exposed. The trenches are embedded with a p-type semiconductor, whereby the surface of the mask laminated film is prevented from being covered with the p-type semiconductor. The p-type semiconductor is grown from the second exposed portions of the n-type semiconductor. V-shaped grooves are prevented from forming on the surface of the p-type semiconductor.
US07871903B2 Method and system for high-speed, precise micromachining an array of devices
A method and system for high-speed, precise micromachining an array of devices are disclosed wherein improved process throughput and accuracy, such as resistor trimming accuracy, are provided. Beam scanning and deflection are both used to distribute beam spots to elements of an array of elements for selective processing. The deflection can be performed with a solid state deflector.
US07871899B2 Methods of forming back side layers for thinned wafers
A method of processing a wafer including a plurality of integrated circuit devices on a front side of the wafer, may include thinning the wafer from a back side opposite the front side. After thinning the wafer, a back side layer may be provided on the back side of the thinned wafer opposite the front side, and the back side layer may be configured to counter stress on the front side of the wafer including the plurality of integrated circuit devices thereon. After providing the back side layer, the plurality of integrated circuit devices may be separated. Related structures are also discussed.
US07871897B2 Method of forming shallow trench isolation regions in devices with NMOS and PMOS regions
A mask pattern is formed on a semiconductor substrate in which a cell region, a PMOS region, and an NMOS region are defined. Trenches are formed in the cell region, the PMOS region, and the NMOS region. A sidewall oxide layer and a protection layer are formed in the trenches, and a portion of the protection layer in the PMOS region is removed. A first device isolation insulating layer is formed on the substrate, filling the trenches. Portions of the first device isolation insulating layer are removed to expose the mask pattern and the trenches of the cell region and the NMOS region and to leave a portion of the first device isolation insulating layer in the trench in the PMOS region. A liner is formed on the portion of the first device isolation region in the trench in the PMOS region and conforming to sidewalls of the trenches in the cell region and the NMOS region. A second device isolation insulating layer is formed on the substrate, filling the trenches in the cell region and the NMOS region. Portions of the second device isolation insulating layer are removed to expose the mask pattern and to leave portions of the second device isolation insulating layer in the trenches of the cell region and the NMOS region.
US07871895B2 Method and structure for relieving transistor performance degradation due to shallow trench isolation induced stress
A method of forming shallow trench isolation (STI) regions for semiconductor devices, the method including defining STI trench openings within a semiconductor substrate; filling the STI trench openings with an initial trench fill material; defining a pattern of nano-scale openings over the substrate, at locations corresponding to the STI trench openings; transferring the pattern of nano-scale openings into the trench fill material so as to define a plurality of vertically oriented nano-scale openings in the trench fill material; and plugging upper portions of the nano-scale openings with additional trench fill material, thereby defining porous STI regions in the substrate.
US07871894B2 Process for manufacturing thick suspended structures of semiconductor material
A process for manufacturing a suspended structure of semiconductor material envisages the steps of: providing a monolithic body of semiconductor material having a front face; forming a buried cavity within the monolithic body, extending at a distance from the front face and delimiting, with the front face, a surface region of the monolithic body, said surface region having a first thickness; carrying out a thickening thermal treatment such as to cause a migration of semiconductor material of the monolithic body towards the surface region and thus form a suspended structure above the buried cavity, the suspended structure having a second thickness greater than the first thickness. The thickening thermal treatment is an annealing treatment.
US07871893B2 Method for non-selective shallow trench isolation reactive ion etch for patterning hybrid-oriented devices compatible with high-performance highly-integrated logic devices
Disclosed are embodiments of a hybrid-orientation technology (HOT) wafer and a method of forming the HOT wafer with improved shallow trench isolation (STI) structures for patterning devices in both silicon-on-insulator (SOI) regions, having a first crystallographic orientation, and bulk regions, having a second crystallographic orientation. The improved STI structures are formed using a non-selective etch process to ensure that all of the STI structures and, particularly, the STI structures at the SOI-bulk interfaces, each extend to the semiconductor substrate and have an essentially homogeneous (i.e., single material) and planar (i.e., divot-free) bottom surface that is approximately parallel to the top surface of the substrate. Optionally, an additional selective etch process can be used to extend the STI structures a predetermined depth into the substrate.
US07871890B2 Methods of fabricating semiconductor devices having resistors
A semiconductor device having a resistor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a first circuit region and a second circuit region. A lower interlayer insulating layer is provided over the semiconductor substrate. A first hole passing through the lower interlayer insulating layer in the first circuit region and a second hole passing through the lower interlayer insulating layer in the second circuit region are provided. A first semiconductor pattern and a second semiconductor pattern are sequentially stacked in the first hole. A first resistor having the same crystalline structure as the second semiconductor pattern is provided in the second hole.
US07871888B2 Method of manufacturing semiconductor device
A p− RESURF region is formed as a surface layer in an n− semiconductor layer. Then, trenches, gate insulating films, and a thick insulating film, gate electrodes, and a gate polysilicon interconnection are formed in this order. Subsequently, a p-well region is formed using the gate polysilicon interconnection as a mask. Then n+ source regions are formed. Since the p− RESURF region is formed and the p-well region is formed after forming the gate electrodes and the gate polysilicon interconnection, the severeness of a high-temperature heat history is lowered and the diffusion depth of the p-well region is decreased. The formation of the p− RESURF region and the shallow p-well region makes it possible to reduce the on-resistance while increasing the breakdown voltage, as well as reducing the gate capacitance.
US07871885B2 Manufacturing method of flash memory device
Embodiments relate to a manufacturing method of a flash memory device which improves electrical characteristics by reducing or preventing void generation. A manufacturing method of a flash memory device according to embodiments includes forming a plurality of gate patterns over a semiconductor substrate including a tunnel oxide layer, a floating gate, a dielectric layer, and a control gate. A spacer layer may be formed as a compound insulating layer structure over the side wall of the gate pattern. A source/drain area may be formed over the semiconductor substrate at both sides of the control gate. An insulating layer located at the outermost of the spacer layer may be removed. A contact hole may be formed between the gate patterns by forming and patterning the interlayer insulating layer. A contact plug may be formed in the contact hole.
US07871884B2 Manufacturing method of dynamic random access memory
A method for manufacturing the DRAM includes first providing a substrate where patterned first mask layer and deep trenches exposed by the patterned first mask layer are formed. Deep trench capacitors are formed in the deep trenches and each of the deep trench capacitors includes a lower electrode, an upper electrode, and a capacitor dielectric layer. A device isolation layer is formed in the first mask layer and the substrate for defining an active region. The first mask layer is removed for exposing the substrate, and a semiconductor layer is formed on the exposed substrate. The semiconductor layer and the substrate are patterned for forming trenches, and the bottom of the trench is adjacent to the upper electrodes of the trench capacitor. Gate structures filling into the trenches are formed on the substrate. A doped region is formed in the substrate adjacent to a side of the gate structure.
US07871881B2 Method for fabrication of a capacitor, and a monolithically integrated circuit comprising such a capacitor
A method for fabrication of a monolithically integrated SOI substrate capacitor has the steps of: forming an insulating trench, which reaches down to the insulator and surrounds a region of the monocrystalline silicon of a SOI structure, doping the monocrystalline silicon region, forming an insulating, which can be nitride, layer region on a portion of the monocrystalline silicon region, forming a doped silicon layer region on the insulating layer region, and forming an insulating outside sidewall spacer on the monocrystalline silicon region, where the outside sidewall spacer surrounds the doped silicon layer region to provide an isolation between the doped silicon layer region and exposed portions of the monocrystalline silicon region. The monocrystalline silicon region, the insulating layer region, and the doped silicon layer region constitute a lower electrode, a dielectric, and an upper electrode of the capacitor.
US07871875B2 Fin field effect transistor and method of manufacturing the same
Provided are a FinFET and a method of manufacturing the same. A FinFET may include at least one active fin, at least one gate insulating layer pattern, a first electrode pattern, a second electrode pattern and at least one pair of source/drain expansion regions. The at least one active fin may be formed on a substrate. The at least one gate insulating layer pattern may be formed on the at least one active fin. The first electrode pattern may be formed on the at least one gate insulating layer pattern. Further, the first electrode pattern may be intersected with the at least one active fin. The second electrode pattern may be formed on the first electrode pattern. Further, the second electrode pattern may have a width greater than that of the first electrode pattern. The at least one pair of source/drain expansion regions may be formed on a surface of the at least one active fin on both sides of the first electrode pattern. Thus, the FinFET may have improved capacity and reduced GIDL current.
US07871873B2 Method of forming fin structures using a sacrificial etch stop layer on bulk semiconductor material
A method of manufacturing semiconductor fins for a semiconductor device may begin by providing a bulk semiconductor substrate. The method continues by growing a layer of first epitaxial semiconductor material on the bulk semiconductor substrate, and by growing a layer of second epitaxial semiconductor material on the layer of first epitaxial semiconductor material. The method then creates a fin pattern mask on the layer of second epitaxial semiconductor material. The fin pattern mask has features corresponding to a plurality of fins. Next, the method anisotropically etches the layer of second epitaxial semiconductor material, using the fin pattern mask as an etch mask, and using the layer of first epitaxial semiconductor material as an etch stop layer. This etching step results in a plurality of fins formed from the layer of second epitaxial semiconductor material.
US07871868B2 LCD TFT array plate and fabricating method thereof
Lift-off method and half-tone photolithography are used to fabricate LCD TFT array plate. Only two photo masks are used to respectively define a first and a second metal layers to accomplish the LCD TFT array plate.
US07871867B2 Semiconductor device and method of manufacturing the same
A semiconductor device is disclosed that comprises a high breakdown voltage MOSFET. The MOSFET includes a source region of a second conductivity type and a drain region of the second conductivity type formed apart from each other in a well region of a first conductivity type, a channel region formed between the source region and the drain region, a gate insulation film formed on the channel region, a LOCOS oxide film having greater film thickness than the gate insulation film, and a gate electrode formed across the gate insulation film and the LOCOS oxide film.
US07871866B2 Method of manufacturing semiconductor device having transition metal oxide layer and related device
Provided is a method of manufacturing a semiconductor device having a switching device capable of preventing a snake current. First, a transition metal oxide layer and a leakage control layer are alternately stacked on a substrate 1 to 20 times to form a varistor layer. The transition metal oxide layer is formed to contain an excessive transition metal compared to its stable state. The leakage control layer may be formed of one selected from the group consisting of a Mg layer, a Ta layer, an Al layer, a Zr layer, a Hf layer, a polysilicon layer, a conductive carbon group layer, and a Nb layer.
US07871864B2 Locking feature and method for manufacturing transfer molded IC packages
The invention discloses integrated circuits (ICs), molded IC packages, and to leadframe arrays, package arrays and methods for their manufacture. Leadframe arrays and package arrays used for the manufacture of IC packages by transfer molding processes include a locking feature adapted for encapsulation. The locking feature is situated in a strap of the leadframe array overlying a gate between mold cavities. The strap lock formed by curing encapsulant in the locking feature of the strap strengthens the resulting package array and provides improved mold extraction and handling characteristics.
US07871863B2 Integrated circuit package system with multiple molding
An integrated circuit package system is provided forming a lead from a padless lead frame, and encapsulating the lead for supporting an integrated circuit die with a first molding compound for encapsulation with a second molding compound.
US07871861B2 Stacked integrated circuit package system with intra-stack encapsulation
A stacked integrated circuit package system includes: mounting a first integrated circuit over a first carrier; mounting a second integrated circuit package system having a second carrier with an intra-stack interconnect attached thereto and with the intra-stack interconnect over the first carrier and the first integrated circuit; and forming an intra-stack encapsulation between the first carrier and the second carrier surrounding the intra-stack interconnect.
US07871860B1 Method of semiconductor packaging
The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a chip and a substrate. The method also includes bonding the chip to the substrate. The method also includes, after the bonding the chip, dispensing a sealing material between the chip and the substrate. In accordance with the method, the chip and the substrate are maintained within a temperature range from the bonding the chip to the dispensing the sealing material, and wherein a lower limit of the temperature range is approximately twice a room temperature.
US07871857B1 Methods of forming multi-chip semiconductor substrates
Methods of forming multi-chip semiconductor substrates include forming a first plurality of dicing streets in a first surface of a first semiconductor wafer having a first plurality of bonding sites thereon and forming a second plurality of dicing streets in a first surface of a second semiconductor wafer having a second plurality of bonding sites thereon. The first surfaces of the first and second semiconductor wafers are bonded together so that the first plurality of dicing streets are aligned with the second plurality of dicing streets and the first plurality of bonding sites are matingly received and permanently affixed within the second plurality of bonding sites. A plurality of bonded pairs of semiconductor chips are then formed by planarizing the second surface of the second semiconductor wafer until the second plurality of dicing streets are exposed.
US07871852B2 Method for fabricating carbon-enriched film
A method for fabricating a carbon-enriched film includes the following steps. First, a substrate is provided. Next, a CFx film (fluorinated carbon films) containing carbon-fluoride bonded molecules is formed on the substrate. Next, a treatment process is performed on the CFx film to convert the carbon-fluoride bonded molecules into carbon-carbon bonded molecules.
US07871851B2 Method for integrating nanotube devices with CMOS for RF/analog SoC applications
A method is provided of integrating the formation of nanotube devices on the same substrate or wafer as CMOS devices in a standard CMOS process. During a CMOS formation process, a region of the substrate containing CMOS devices is protected from certain nanotube fabrication processes while fabricating nanotube devices on the substrate. After fabrication of the nanotube devices, the region of the substrate containing the fabricated nanotube devices is then protected from certain CMOS fabrication processes while fabricating CMOS devices on a different region of the same substrate. Through this formation method, a nanotube device based RF/analog system-on-chip (SoC) application can be formed having the superior RF/analog properties of nanotube electronic circuitry and the superior digital properties of silicon CMOS circuitry on the same wafer or substrate.
US07871849B2 Method for manufacturing photoelectric conversion device
A method for manufacturing a photoelectric conversion device typified by a solar cell, having an excellent photoelectric conversion characteristic with a silicon semiconductor material effectively utilized. The point is that the surface of a single crystal semiconductor layer bonded to a supporting substrate is irradiated with a pulsed laser beam to become rough. The single crystal semiconductor layer is irradiated with the pulsed laser beam in an atmosphere containing an inert gas and oxygen so that the surface thereof is made rough. With the roughness of surface of the single crystal semiconductor layer, light reflection is suppressed so that incident light can be trapped. Accordingly, even when the thickness of the single crystal semiconductor layer is equal to or greater than 0.1 μm and equal to or less than 10 μm, path length of incident light is substantially increased so that the amount of light absorption can be increased.
US07871843B2 Method of preparing light emitting device
The object of this invention is to provide a high-output type nitride light emitting device. The nitride light emitting device comprises an n-type nitride semiconductor layer, a p-type nitride semiconductor layer and an active layer therebetween, wherein the light emitting device comprises a gallium-containing nitride semiconductor layer prepared by crystallization from supercritical ammonia-containing solution in the nitride semiconductor layer.
US07871840B2 Method for manufacturing semiconductor optical device using inductive coupled plasma-enhance CVD
The present invention provides a semiconductor laser diode prevents not only the adhesion of the upper electrode but the heat dissipation of the mesa from degrading. The laser diode includes a substrate, portion of which forms a mesa including an active layer, an insulating layer formed so as to bury the mesa, and an electrode formed on the mesa and the insulating layer. This insulating layer may be selected from SiO2, SiON, SiN, Al2O3 or ZrO2 and formed by the inductive coupling plasma-enhanced chemical vapor deposition (ICP-CVD) technique.
US07871835B2 Method for packaging light-emitting diode
Disclosed is a method for packaging an LED by a thermoplastic copolymer. The copolymer is polymerized by 100 parts by weight of an acrylic ester, 0.1 to 30 parts by weight of a hydrogen bond monomer, and 0.1 to 70 parts by weight of a bulky monomer. The copolymer has transparency greater than 90%, thermal resistance greater than 130° C., and moisture absorption less than 0.5 wt %, such that the copolymer may be applied as packaging material for a light emitting device.
US07871834B2 Combined semiconductor apparatus with thin semiconductor films
A semiconductor apparatus includes two thin semiconductor films bonded to a substrate, and a thin-film interconnecting line electrically connecting a semiconductor device such as a light-emitting device in the first thin semiconductor film to an integrated circuit in the second thin semiconductor film. Typically, the integrated circuit drives the semiconductor device. The two thin semiconductor films are formed separately from the substrate. The first thin semiconductor film may include an array of semiconductor devices. The first and second thin semiconductor films may be replicated as arrays bonded to the same substrate. Compared with conventional semiconductor apparatus comprising an array chip and a separate driver chip, the invented apparatus is smaller and has a reduced material cost.
US07871833B2 Determining chip separation by comparing coupling capacitances
A semiconductor die includes proximity connectors proximate to a surface of the semiconductor die. This semiconductor die is configured to communicate signals with another semiconductor die via proximity communication through one or more of the proximity connectors. In particular, the proximity connectors include a first group of proximity connectors that is configured to facilitate determining a first separation between the semiconductor die and the other semiconductor die by comparing coupling capacitances between the semiconductor die and the other semiconductor die. Note that the first group of proximity connectors includes a first proximity connector and a second proximity connector, and the second proximity connector at least partially encloses an in-plane outer edge of the first proximity connector.
US07871829B2 Metal wiring of semiconductor device and method of fabricating the same
A metal wiring forming method in a semiconductor device can include forming an interlayer insulating film on a lower metal wiring, the first interlayer insulating film having a non-planar upper surface; forming a stop layer on the interlayer insulating film and over the lower metal wiring; forming an interlayer insulating film pattern on the stop layer, wherein an upper surface of the interlayer insulating film pattern and an upper surface of the stop layer are substantially coplanar; removing a portion of the stop layer to form a stop layer pattern, wherein a portion of the interlayer insulating film over the lower metal wiring is exposed by the stop layer pattern; and etching the exposed portion of the interlayer insulating film to form a via hole therethrough, wherein the lower metal wiring is exposed by the via hole.
US07871827B2 Methods and devices for removal of organic molecules from biological mixtures using anion exchange
Methods and devices for removing small negatively charged molecules from a biological sample mixture that uses an anion exchange material.
US07871825B2 Test element and method for testing blood
A test for diagnostic tests, particularly for testing blood prior to a transfusion is disclosed. The test element includes at least two test units for carrying out at least two tests. The test element is provided with a fixing means for fixing the test element.
US07871823B2 Method and apparatus for managing denitration catalyst
Data on a secular change of each denitration catalyst is managed based on data obtained by a periodic maintenance and a daily management. Management of a secular change and prediction on performance variations that occur until a next periodic check is performed. It is determined whether the denitration catalyst is deteriorated such that an exhaust-gas denitration system cannot maintain its performance. When the denitration catalyst is deteriorated, regeneration, replacement, or addition of the denitration catalyst is performed, and the denitration catalyst is altered as necessary. When the denitration catalyst is usable, the denitration catalyst is not replaced nor regenerated.
US07871820B2 High frequency of neurexin 1β signal peptide structural variants in patients with autism
The three β-neurexins have similar roles in synaptogenesis and interact with the neuroligins. Mutations located within the gene encoding neurexin 1 have been identified as molecular markers associated with autism and autism-related disorders. The estimated attributable risk is 2%. The invention provides methods of diagnosing or predicting susceptibility to developing autism in an individual by determining the presence or absence of one or more genetic variant of a neurexin 1 gene in an individual.
US07871819B2 Regulatory constructs comprising intron 3 of prostate specific membrane antigen gene
The invention provides a recombinant vector comprising an ovine adenovirus genome and a sequence encoding a heterologous polypeptide, wherein the sequence encoding the heterologous polypeptide is inserted between E4 and E3 transcription units of the ovine adenovirus genome.
US07871814B2 Recombinant bicistronic flaviviruses and methods of use thereof
The present invention provides recombinant bicistronic flaviviruses, particularly live attenuated recombinant bicistronic flavivirus, which comprise, in order from 5′ to 3′, a viral 5′UTR, an ORF encoding all viral proteins, an internal ribosome entry site, an exogenous nucleotide sequence that encodes an exogenous polypeptide, and a viral 3′UTR. Infection of a host cell with a recombinant flavivirus provides for expression of the exogenous nucleic acid in a host cell. Such recombinant flavivirus are useful for delivering a protein to a mammalian host; and for eliciting an immune response to the exogenous polypeptide.
US07871809B2 Production of DHA in microalgae in medium having modified amounts of chloride ion and potassium ion
Methods for production of highly unsaturated fatty acids by marine microorganisms, including the heterotrophic marine dinoflagellate Crypthecodinium, using low levels of chloride ion are disclosed. Specifically, methods of increasing production of highly unsaturated fatty acids by marine microorganisms while growing in low chloride media by manipulating sodium ion and potassium ion levels. The invention also relates to methods of production of highly unsaturated fatty acids by marine organisms at low pH levels, and includes methods for generation of low pH tolerant strains.
US07871804B2 Method for producing polyunsaturated long-chain fatty acids in transgenic organisms
The invention relates to a method for producing polyunsaturated fatty acids in an organism, according to which nucleic acids coding for polypeptides with an acyl-CoA:lysophospholipid-acyltransferase activity are introduced into the organism. Advantageously, the nucleic acid sequences can be expressed in the transgenic organism optionally together with other nucleic acid sequences coding for polypeptides of the fatty acid or lipid metabolism. The invention also relates to the inventive nucleic acid sequences, nucleic acid constructs containing the inventive nucleic acid sequences, vectors containing the inventive nucleic acid sequences and/or the nucleic acid constructs, and transgenic organisms containing the nucleic acid sequences, nucleic acid constructs and/or vectors. The invention further relates to oils, lipids and/or fatty acids produced according to the inventive method, and to the use of the same.
US07871800B2 Polypeptides having glucoamylase activity and polynucleotides encoding same
The present invention relates to polypeptides having glucoamylase activity and isolated polynucleotides encoding said polypeptides preferably derived from a strain of Peniphora rufomarginata. The invention also relates to nucleic acid constructs, vectors, and host cells comprising the polynucleotides as well as methods for producing and using the polypeptides. The invention also relates to the composition comprising a glucoamylase of the invention as well as the use such compositions for starch conversion processes, brewing, including processes for producing fermentation products or syrups.
US07871796B2 Isolation of binding proteins with high affinity to ligands
The invention overcomes the deficiencies of the prior art by providing a rapid approach for isolating binding proteins capable of binding small molecules and peptides via “display-less” library screening. In the technique, libraries of candidate binding proteins, such as antibody sequences, are expressed in soluble form in the periplasmic space of gram negative bacteria, such as Escherichia coli, and are mixed with a labeled ligand. In clones expressing recombinant polypeptides with affinity for the ligand, the concentration of the labeled ligand bound to the binding protein is increased and allows the cells to be isolated from the rest of the library. Where fluorescent labeling of the target ligand is used, cells may be isolated by fluorescence activated cell sorting (FACS). The approach is more rapid than prior art methods and avoids problems associated with the surface-expression of ligand fusion proteins employed with phage display.
US07871793B2 Antimicrobial carbohydrates and methods of using same
Compositions useful for inhibiting the growth of bacteria, including bacteria that can cause gastric ulcers, are provided. In addition, transgenic organism that can produce such compositions are provided. Methods of using the compositions to treat or prevent gastric ulcers in a subject, including a human subject, also are provided.
US07871787B2 Methods for diagnosing endometriosis
Provided herein is a method for diagnosing and monitoring endometriosis in a subject by measuring levels of the β-subunit of fibrinogen.
US07871786B2 GEF-H1b: biomarkers, complexes, assays and therapeutic uses thereof
The present invention relates to diagnosing abnormal cell proliferation in biological samples and screening for drugs which inhibit, reduce or abolish cell growth, especially tumorigenic cell growth, by detecting a phosphovariant isoform of a guanine nucleotide exchange factor biomarker, such as the novel GEF-H1S.
US07871785B2 Use of secretor, Lewis and sialyl antigen levels in clinical samples as predictors of risk for disease
An individual at risk for necrotizing enterocolitis and related disorders can be identified by measuring the level of at least one secretor antigen in a biological sample from the individual and comparing the measured level of the at least one secretor antigen to a predetermined value or a predetermined range of values. Among the secretor antigens which can be measured are: the H-1 , H-2, Lewisb and Lewisy antigens and derivatives thereof (e.g., a sialylated form of Lewis a, Lewis x, Lewis b, Lewis y; H-1, H-2, Lewis a, Lewis x, Lewis b or Lewis y).
US07871782B2 Specific binding members against synaptophysin
The present invention provides specific binding members that bind synaptophysin and which comprise: an antibody VH domain selected from the group consisting of the C1-3 VH domain (SEQ ID NO. 2) and a VH domain comprising a VH CDR3 with the amino acid sequence of SEQ ID NO. 12 and optionally one or more VH CDR's with an amino acid sequence selected from SEQ ID NO. 10 and SEQ ID NO. 11; and/or an antibody VL domain selected front the group consisting of the C1-3 VL domain (SEQ ID NO. 4) and a VL domain comprising one or more VL CDR's with an amino acid sequence selected from SEQ ID NO. 13, SEQ ID NO. 14 and SEQ ID NO. 15. The invention further provides related materials such as nucleic acids, kits and compositions, and also methods of use of the binding member, for instance in targeting entities to hepatic stellate cells which are implicated it liver fibrosis.
US07871780B2 Genomic markers of hepatitis B virus associated with hepatocellular carcinoma
The present invention provides methods of predicting a pre-disposition of HBV-infected individuals to develop hepatacellular carcinoma (HCC).
US07871778B2 Methods of diagnosing endometriosis
The present invention provides biomarkers for the diagnosis and prognosis of endometriosis. Generally, the methods of this invention find use in diagnosing or for providing a prognosis for endometriosis by detecting the expression levels of biomarkers, which are differentially expressed (up- or down-regulated) in endometrial cells from a patient with endometriosis. Similarly, these markers can be used to diagnose reduced fertility in a patient with endometriosis or to provide a prognosis for a fertility trial in a patient suffering from endometriosis. The present invention also provides methods of identifying a compound for treating or preventing endometriosis. Finally, the present invention provides kits for the diagnosis or prognosis of endometriosis.
US07871777B2 Probe for nucleic acid sequencing and methods of use
A nanoprobe for sequencing of nucleic acid molecules is provided, as well as methods for using the nanoprobe. In particular examples, the probe includes a polymerizing agent and one or more molecular linkers that carry a chemical moiety capable of reversibly binding to the template strand of a nucleic acid molecule, without being detached from the linker, by specifically binding with a complementary nucleotide in the target nucleic acid molecule. The reversible binding of the chemical moiety on the linker with a complementary nucleotide in the target nucleic acid molecule is indicated by emission of a characteristic signal that indicates pairing of the chemical moiety on the linker with its complementary nucleotide. An example of such a chemical moiety is a nonhydrolyzable nucleotide analog. In particular examples, the polymerizing agent and the chemical moiety are associated with a tag, such as a donor fluorophore and acceptor fluorophore characteristic of the particular type of chemical moiety.
US07871776B2 Compositions and methods for enhancing the identification of prior protein PrPSc
A method for purifying PrPc, a purified preparation of PrPc and methods and kits for identifying the presence of PrPc are provided.
US07871775B2 Compositions and methods for the identification, assessment, prevention and therapy of human cancers
The present invention is directed to the identification of markers that can be used to determine whether tumors are sensitive or resistant to a therapeutic agent. The present invention is also directed to the identification of therapeutic targets. The invention features a number of “sensitivity markers.” These are markers that are expressed in most or all cell lines that are sensitive to treatment with an agent and which are not expressed (or are expressed at a rather low level) in cells that are resistant to treatment with that agent. The invention also features a number of “resistance markers.” These are markers that are expressed in most or all cell lines that are resistant to treatment with an agent and which are not expressed (or are expressed at a rather low level) in cells that are sensitive to treatment with that agent. The invention also features marker sets that can predict patients that are likely to respond or not to respond to an agent.
US07871770B2 Light transmitted assay beads
A micro bead having a digitally coded structure that is partially transmissive and opaque to light. The pattern of transmitted light is determined by to decode the bead. The coded bead may be structured a series of alternating light transmissive and opaque sections, with relative positions, widths and spacing resembling a 1D or 2D bar code image. To decode the image, the alternating transmissive and opaque sections of the body are scanned in analogous fashion to bar code scanning. The coded bead may be coated or immobilized with a capture or probe to effect a desired bioassay. The coded bead may include a paramagnetic material. A bioanalysis system conducts high throughput bioanalysis using the coded bead, including a reaction detection zone and a decoding zone.
US07871758B2 Process for producing resist pattern and conductor pattern
This process for producing a resist pattern is a process for producing a resist pattern including: the step of laminating (a) a support having an upper surface on which copper exists, (b) an inorganic substance layer consisting of an inorganic substance supplied from an inorganic substance source, and (c) a photoresist layer consisting of a chemically amplified type negative photoresist composition, to obtain a photoresist laminate, the step of selectively irradiating active light or radioactive rays to the photoresist laminate, and the step of developing the (c) photoresist layer together with the (b) inorganic substance layer to form a resist pattern.
US07871755B2 Photosensitive composition
A photosensitive composition is provided, which includes a compound represented by the formula BP; and a photo-acid generator which generates an acid by the action of actinic radiation, wherein R1 is an acid-leaving group, and a part of R1 may be substituted with a hydrogen atom.
US07871749B2 Electrophotographic developing agent
A non-magnetic one-component electrophotographic developing agent is provided having improved properties. The electrophotographic developing agent includes parent toner particles comprising a binder resin, a releasing agent, a colorant, and a charge control agent, and an external additive which is added to a surface of the parent toner particles, wherein the binder resin comprises a high viscosity polyester resin having a weight average molecular weight of about 90,000-140,000 and a gel content of less than about 5% and a low viscosity polyester resin having a weight average molecular weight of about 52,000-65,000 and a gel content of less than about 2%. According to an embodiment of the present invention, an electrophotographic developing agent having improved image gloss and fusing property, while ensuring durability may be prepared by using a blended combination of a high viscosity polyester resin and a low viscosity polyester resin.
US07871747B2 Electrophotographic photoconductor having charge blocking and moire preventing layers
To provide an electrophotographic photoconductor that has a layer containing a compound represented by the following general formula (1), and an image forming apparatus using the electrophotographic photoconductor. where R1 and R2 independently represent any one of a hydrogen atom, substituted or unsubstituted alkyl group, substituted or unsubstituted cycloalkyl group and substituted or unsubstituted aralkyl group, and R3, R4, R5, R6, R7, R8, R9 and R10 independently represent any one of a hydrogen atom, halogen atom, cyano group, nitro group, amino group, hydroxyl group, substituted or unsubstituted alkyl group, substituted or unsubstituted cycloalkyl group and substituted or unsubstituted aralkyl group.
US07871746B2 Thiophthalimides containing photoconductors
A photoconductor that includes, for example, a supporting substrate, a thiophthalimide containing photogenerating layer, and at least one charge transport layer.
US07871738B2 Nanosegregated surfaces as catalysts for fuel cells
A method of preparing a nanosegregated Pt alloy having enhanced catalytic properties. The method includes providing a sample of Pt and one or more of a transition metal in a substantially inert environment, and annealing the sample in such an environment for a period of time and at a temperature profile to form a nanosegregated Pt alloy having a Pt-skin on a surface. The resulting alloy is characterized by a plurality of compositionally oscillatory atomic layers resulting in an advantageous electronic structure with enhanced catalytic properties.
US07871737B2 Metal composite for fuel cell and fuel cell bipolar plate using same, and fabrication method for same
A metal composite for fuel cells according to the present invention, which includes: a core of a metal; cladded layers of a corrosion resistant metal covering both surfaces of the core; and a through-hole formed through the core and cladded layers. The through-hole has, on a hole wall of the core region of the through-hole, a concave portion which is recessed relative to hole walls of the cladded layer regions of the through-hole.