最新美国发明专利第2010-08-31期 - 专利汇|PatentHub专利检索|专利查询网|发明专利查询分析

Document	Document Title
US07787374B2	Derivative packet delay variation as a metric for packet timing recovery stress testing A method and system for analyzing simulated packet delay variation (PDV) using derivative PDV is disclosed. The delay-step method for simulating PDV determines a delay for each packet in a stream of packets generated at a regular interval. Delay target values are randomly selected based on a statistical distribution, such as a Gaussian distribution. Delay-steps are determined for each packet based on the delay target values. The delay-steps can be fixed or variable sized steps which are used to adjust the delay of sequential packets. PDV is generated by delaying each of the packets with the delay determined for that packet. The derivative PDV is calculated to evaluate a delay rate of change on a packet-by-packet basis. The derivative PDV can be used as a metric to specify stresses for adaptive packet timing recovery stress testing.
US07787372B2	Transmission control protocol with performance enhancing proxy for degraded communication channels The integration of an improved retransmission protocol into a performance enhancing proxy (PEP) for degraded communication links. Various embodiments of the invention include congestion control, window size adjustment algorithms, connection negotiation features, and connection establishment acceleration features.
US07787369B2	Flexible Ethernet bridge Congestion is minimized on a desired port in an Ethernet bridge. A packet with a destination address and a source address is received on an incoming port. An address table is search to determine a destination port associated with the destination address. If the destination port is not determined by the search then flooding the packet on all of the ports except the desired port if the incoming port is determined to be equal to the desired port; and flooding the packet on all of the ports except the incoming port and the desired port if the incoming port is determined to be not equal to the desired port.
US07787368B1	In-network per packet cashes Methods, systems, and media are provided for the improved efficiency in bandwidth usage for transmitting repeated packets in a manner that is transparent to users. Fast, in-network per-packet caches (INPPC) at each node of a transmission retain packets for a configurable period of time or a number of packets. Rather than retransmit data from a first node to a second node within the time period for retention, an identifier is sent. The identifier allows the receiving node to access the first packet still in cache memory and reduces the size of the transmission, thereby optimizing bandwidth usage. Signatures that allow for efficient determination of packet redundancy, such as hashes, can be used. Accordingly, less bandwidth is utilized for repeated transmissions, such as transmission control protocol (TCP) retransmissions, or users accessing the same content within close proximity both physically and temporally.
US07787367B2	Method and a system for flow control in a communication network The present invention relates to a method and a system of flow control in a communication network. The method comprises determining if at least one sender buffer has a sufficient number of credits. The sufficient number of credits informs the sender buffer if the receiver buffer has an available buffer space corresponding to at least one data packet. The method further comprises transmitting the at least one data packet to at least one receiver buffer, if the at least one sender buffer has the sufficient number of credits. If the sufficient number of credits in the at least one sender buffer are absent, a data packet is transmitting speculatively to the at least one receiver buffer. If a negative acknowledgement is received for the transmitted data packet, a copy of the data packet can be retransmitted to the receiver buffer.
US07787366B2	Method and apparatus for controlling wireless medium congestion by adjusting contention window size and disassociating selected mobile stations A method and apparatus for alleviating congestion of a wireless medium used by an access point (AP) and a plurality of wireless transmit/receive units (WTRUs) is disclosed. If congestion is determined to exist on the wireless medium, a determination is then made as to whether there are any low priority traffic streams established between the AP and at least one of the WTRUs. If there are no low priority traffic streams established between the AP and at least one of the WTRUs, selected ones of the associated WTRUs are disassociated with the AP based on the amount of time spent by the WTRUs trying to transmit and retransmit unacknowledged packets or on a specific traffic stream access category. If low priority traffic streams have been established, the packet transmission delay associated with the low priority traffic streams is increased when congestion exists. Otherwise, the packet transmission delay is decreased.
US07787361B2	Hybrid distance vector protocol for wireless mesh networks A method of hybrid route discovery in a mesh network is described. The method comprises the optional designation of a root node of the mesh network and formatting a route request message at an originating mesh point, where the route request messages include a hop limit parameter. If a root node has been configured, the route request is responded to with a message that describes the route to the root. If a direct route between two nodes is required, the route request message is broadcast from the originating mesh point, and the hop limit parameter limits the number of times the route request message will be forwarded. The originating mesh point receives a unicast route reply message from a neighboring mesh point, after the neighboring mesh point received the route request message. Finally, a route connecting the originating mesh point and the destination mesh point is established.
US07787359B2	Method and system for data forwarding in label switching network The present invention discloses a method for data forwarding used in label switching networks, with which, at the source node, sequence numbers are added to the data packets forming an original data flow to be forwarded according to the forwarding order, then the data packets are mapped to label switched paths (LSP) for forwarding; at the destination node, the data packets received from the LSPs are merged into the same data flow as the original data flow to be forwarded according to the order of the sequence numbers. Meanwhile, during the data forwarding in accordance with the invention, an alarm mechanism is used to detect a faulted LSP, and the mapping strategy is adjusted timely to avoid the massive loss of the data packets, which guarantees the security of the data forwarding to the greatest extent while a high bandwidth utilization ratio is ensured.
US07787358B2	Uplink inter-carrier interference cancellation of OFDMA systems Inter-carrier interference (ICI) cancellation in an OFDMA receiving signals from two transmitters is performed by identifying the transmitted sub-carriers that cause the largest ICI to sub-carriers received from other transmitters, and removing the ICI contribution from these sub-carriers. This may be accomplished by calculating the ICI terms only based on the interfering sub-carrier and the frequency offset. Alternatively, the transmissions causing the ICI are demodulated, the ICI on other signals is then determined and subtracted, and other signals are then demodulated. Which transmissions cause the largest ICI on others depends on the relative strength of the corresponding sub-carriers and how much orthogonality is lost. The latter might be due to frequency error, Doppler spread, or a combination of both.
US07787355B2	M-ary orthogonal keying system A digital modulation system provides enhanced multipath performance by using modified orthogonal codes with reduced autocorrelation sidelobes while maintaining the cross-correlation properties of the modified codes. For example, the modified orthogonal codes can reduce the autocorrelation level so as not to exceed one-half the length of the modified orthogonal code. In certain embodiments, an M-ary orthogonal keying (MOK) system is used which modifies orthogonal Walsh codes using a complementary code to improve the auto-correlation properties of the Walsh codes, thereby enhancing the multipath performance of the MOK system while maintaining the orthogonality and low cross-correlation characteristics of the Walsh codes.
US07787352B2	Method for processing a MEMS/CMOS cantilever based memory storage device A Seek and Scan Probe (SSP) memory device is disclosed. The memory device includes a moving part having microelectromechanical (MEMS) structures fabricated on a first wafer and CMOS and memory medium components fabricating on a second wafer bonded to the first wafer.
US07787349B2	Optical pickup lens and optical pickup apparatus An optical pickup lens focuses laser beams having different wavelengths λ1, λ2 and λ3 on at least three kinds of optical discs. At least one side of the optical pickup lens has a concentric loop zonal structure for compensating wavefront aberration occurring when recording or reproducing an optical disc having a substrate thickness t1 by the laser beam having the wavelength λ1 and wavefront aberration occurring when recording or reproducing an optical disc having a substrate thickness t2 by the laser beam having the wavelength λ2. When recording or reproducing an optical disc having a substrate thickness t3 by the laser beam having the wavelength λ3, a phase difference given to the laser beam having the wavelength λ3 due to the concentric loop zonal structure is about 0.15λ or smaller.
US07787346B2	Hologram recording method and device, hologram reproduction method and device, and optical recording medium There is provided a hologram recording method, including generating a signal light which is spatially modulated such that digital data is represented by an image of intensity distribution, irradiating the signal light on an optical recording medium after a Fourier transformation of the signal light such that a zero-order component of the signal light comes into focus at a point removed from the optical recording medium, forming a diffraction grating in the optical recording medium by interference between the zero-order component of the signal light and a high-order component thereof, and recording digital data represented by the signal light as a hologram.
US07787341B2	Optical disk device and method for determining disk type An optical disk device includes a pickup head, and a controller which controls the pickup head. The controller subtracting a second measured value determined from an amplitude value of the tracking error signal when the pickup head irradiates a second area of the optical disk with a first DVD laser beam, from a first measured value determined from the amplitude value of the tracking error signal output when the pickup irradiates a first area of the optical disk with the first DVD laser beam, to determine an evaluation value. The controller determining that the optical disk is the first DVD if the evaluation value is smaller than a reference value, and determining that the installed optical disk is a second DVD if the evaluation value is larger than the reference value, the second DVD optical disk having a smaller track width than the first DVD optical disk.
US07787326B1	Programmable logic device with a multi-data rate SDRAM interface Within a programmable logic device, a multi-data rate SDRAM interface such as a DDR SDRAM interface includes in one embodiment a DQS clock tree, a slave delay circuit, and a delay-locked loop (DLL). The slave delay circuit is adapted to shift the phase of the DQS signal relative to the phase of data to provide a phase-shifted DQS signal to the DQS clock tree, and the DLL is adapted to control the slave delay circuit. The DLL includes a delay line comprising a plurality of instantiations of the slave delay circuit and a plurality of facsimiles of the DQS clock tree.
US07787325B2	Row decode driver gradient design in a memory device A memory device using a plurality of enhanced row decode drivers for activating wordlines in a memory array is disclosed. Circuit design attributes of the enhanced row decode drivers are varied as a function of proximity to a source of a row address signal applied to each decode driver. The circuit variations are operable to reduce the leakage power of the driver by degrading performance thereof while maintaining required worst case timing. The worst case timing being defined by the timing and performance requirements for the most distant of the row decode driver circuits relative to the source of the applied row address signals.
US07787323B2	Level detect circuit A detect circuit may be used to detect one or more characteristics corresponding to the fuse being programmed. When the one or more characteristics of the fuse being programmed reach the desired states or values, the programming of the fuse is discontinued. Thus, the programming duration for each fuse is customized for each fuse. As a result, for some embodiments, there may be fewer fuses that have been over-programmed. In addition, for some embodiments, the range of impedances of the programmed fuses have a narrower distribution of impedances due to the use of the detect circuit.
US07787321B2	High performance sense amplifier and method thereof for memory system A system and method for sensing a current. The system includes an operational amplifier including a first input terminal, a second input terminal, and a first output terminal. The first input terminal is biased to a predetermined voltage, and the second input terminal and the first output terminal are directly connected. Additionally, the system includes a switch coupled to the first output terminal and a first node. The switch is controlled by at least a first control signal. Moreover, the system includes a comparator including a third input terminal, a fourth input terminal, and at least a second output terminal. The comparator is configured to receive a first input signal at the third input terminal and a second input signal at the fourth input terminal. The first input signal and the second input signal are associated with the first node and the predetermined voltage.
US07787317B2	Memory circuit and tracking circuit thereof The tracking circuit is coupled between a control circuit and a sense amplifier, delays a word-line pulse signal generated by the control circuit by a delay period to generate a sense amplifier enable signal enabling the sense amplifier to detect data bits output by a memory cell array. In one embodiment, the tracking circuit comprises a plurality of dummy cells, a dummy bit line, and an inverter. At least one of the plurality of dummy cells comprises a plurality of cascaded transistors cascaded between the dummy bit line and a ground voltage for pulling down the voltage of the dummy bit line when the word-line pulse signal is enabled. The dummy bit line is coupled between the dummy cells and the inverter. The inverter inverts the voltage of the dummy bit line to generate the sense amplifier enable signal.
US07787315B2	Semiconductor device and method for detecting abnormal operation A semiconductor device includes a pull-up unit pulling up a voltage of an output node to a first voltage in response to a control signal, a photo sensing unit pulling down a voltage of the output node to a second voltage in response to an incident light, and a CPU, the CPU reset in response to the voltage of the output node produced in response to the incident light.
US07787314B2	Dynamic real-time delay characterization and configuration In mask programmable integrated circuit, such as a structured ASIC, a delay chain provides a delay that is set by a mask programmable switch. The delay chain receives an input to allow the delay mask programmed delay to be overridden using a JTAG controller. This allows testing of different delays. The input may also be provided by a fuse block, so that the fuse block can override the mask programmable switch, thus allowing a delay to be changes after mask programming.
US07787305B2	Flash memory devices and programming methods that vary programming conditions in response to a selected step increment A flash memory device includes a flash memory cell array having flash memory cells arranged with word and bit lines, a word line driver circuit configured to drive the word lines at a selected step increment during a programming operation, a bulk-voltage supply circuit configured to supply a bulk voltage into a bulk of the flash memory cell array and a writing circuit configured to drive the bit lines selected by conditions during a programming operation. A control logic block is configured to control the writing circuit and the bulk-voltage supply circuit during the programming operation. The control logic block is configured to cause the writing circuit and/or the bulk-voltage supply circuit to change at least one of the conditions of the writing circuit and/or the bulk voltage responsive to the selected step increment.
US07787302B2	Flash memory device, method of manufacturing the same, and method of operating the same Provided are a memory device, a method of manufacturing the same, and a method of operating the same. The memory device may include a channel region having an upper end where both sides of the upper end are curved, the curved portions of both sides allowing charges to be injected thereinto in a program or erase voltage such that the curved portions into which the charges are injected are separate from a portion which determines a threshold voltage, and a gate structure on the channel region.
US07787301B2	Flash memory device using double patterning technology and method of manufacturing the same Provided are a flash memory device and a method of manufacturing the same. The flash memory device includes strings. Each of the strings has a string selection line, a ground selection line, and an odd number of word lines formed between the string selection line and the ground selection line.
US07787298B2	Method for preventing memory from generating leakage current and memory thereof A method for preventing a memory from generating a leakage current is disclosed. The memory includes a boundary memory cell and a neighboring memory cell. The neighboring memory cell is adjacent to the boundary memory cell. The method includes the following step. The first terminal of the neighboring memory cell is connected to the second terminal through a metal line.
US07787290B2	Semiconductor device In MRAM using a spin-transfer torque switching, a sufficient writing operation with a small memory cell is realized, and a reading current is enlarged while a reading disturbance is suppressed. In the case where the free layer of the tunnel magneto-resistance element is located on the side of the bit line, using a PMOS transistor, and in the case where the fixed layer of the tunnel magneto-resistance element is located on the side of the bit line, using an NMOS transistor, an anti-parallel writing in a source grounding operation is performed. The reading and writing operation margin is improved by performing a reading operation in an anti-parallel writing direction.
US07787287B2	Magnetic storage device with curved interconnects In an MRAM, a curved region (206) is formed in a bit line (202), and this curved region (206) is in bent shape, with a TMR element (203) serving as a center, in this case, in rough U shape (in the illustrated example, in roughly inverted U shape). The bit line (202) in which the curved region (206) is formed includes the TMR element (203) in a space formed by the curved region (206). Thanks to such relatively simple construction, this construction realizes a highly reliable MRAM which ensures that power is substantially saved during data writing into a memory cell while meeting requirements for further miniaturization of the device.
US07787286B2	SRAM memory with reference bias cell A random access memory microelectronic device, comprising a plurality of cells comprising respectively: a plurality of transistors forming a bistable, a first storage node and a second storage node, a first double gate access transistor to the first storage node and a second double gate access transistor to the second storage node, a first gate of the first access transistor and a first gate of the second access transistor being linked to a first word line, a second gate of the first access transistor and a second gate of the second access transistor being linked to a second word line, the device being moreover equipped: with a reference memory cell provided to deliver a bias potential intended to be applied to one of the respective word lines of one or several given cells of said plurality of cells during reading access of said given cells.
US07787281B2	Writing circuit for a phase change memory A phase change memory writing circuit is provided. The circuit comprises a writing path and a fast write control unit. The writing path further comprises a current driving unit, a first switch device and a phase change memory cell. The current driving unit is coupled to a high voltage source and outputs a driving current. The first switch device is controlled by a first control signal. The fast write control unit is coupled to the writing path to provide a writing voltage to the writing path. When the first switch device is turned off, the fast write control unit outputs the writing voltage to the writing path. When the first switch device is turned on, the fast write control unit stops outputting the writing voltage to the writing path.
US07787278B2	Resistance variable memory device and operating method thereof Provided is a resistance variable memory device and a method for operating same. The resistance variable memory device has a phase change material between a top electrode and a bottom electrode. In the method for operating a resistance variable memory, the write current is applied in a direction from the top electrode to the bottom electrode, and the read current is applied in a direction from the bottom electrode to the top electrode. The phase change material is programmed by applying the write current, and a resistance drift of the phase change material is restrained by applying the read current.
US07787276B2	Memory array using mechanical switch and method for operating thereof A method for controlling a memory array using a mechanical switch according to the present invention, in which the memory array comprises; a plurality of word lines; a plurality of bit lines intersecting each other with the plurality of word lines; a gate electrode connected to each of the word lines; a drain electrode spaced apart from the gate electrode and connected to a capacitor; and a source electrode comprises: an anchor part spaced apart from the gate electrode and connected to each of the bit lines; a mobile part where a dimple is formed, comprises the steps of: applying a first voltage V1 to the bit line selected from the plurality of bit lines; applying a second voltage V2 greater than a sum of the first voltage V1 and a pull-in voltage Vpi to the word lines selected from the plurality of word lines; and applying a voltage smaller than a sum of a erase voltage Verase and the pull-in voltage Vpi and a voltage greater than a difference between a write voltage Vwrite and the pull-in voltage Vpi to the word lines unselected from the plurality of word lines.
US07787274B2	Power supply with adjustable outputted voltage A power supply with adjustable outputted voltage includes a casing, a circuit board, a voltage-adjusting knob and a rotary wheel. The casing is provided thereon with a window, and the circuit board is disposed in the casing. The circuit board is electrically connected to AC/DC power input processing circuit in which only AC (or DC) exists or both AC and DC exist simultaneously. The voltage-adjusting knob is electrically connected on the circuit board. The rotary wheel is provided thereon with a plurality of voltage-adjusting numerals. The voltage-adjusting numerals are located to correspond to the window of the casing and are displayed in the window.
US07787267B2	Active power filter An active power filter includes an energy storage capacitor, an inverter, a filtering circuit and a controller. The inverter is controlled to act as a virtual resister at a fundamental frequency for compensating for the power loss of the active power filter, to act as a virtual capacitor at a fundamental frequency for compensating for a fundamental reactive power of the load, and/or to generate a harmonic current for suppressing the harmonic currents of specific orders of the load.
US07787261B2	Intermediate bus architecture with a quasi-regulated bus converter A dc-dc converter system comprises a quasi-regulated bus converter and plural regulation stages that regulate the output of the bus converter. The bus converter has at least one controlled rectifier with a parallel uncontrolled rectifier. A control circuit controls the controlled rectifier to cause a normally non-regulated mode of operation through a portion of an operating range of source voltage and a regulated output during another portion. The bus converter may be an isolation stage having primary and secondary transformer winding circuits. For the non-regulated output, each primary winding has a voltage waveform with a fixed duty cycle. The fixed duty cycle causes substantially uninterrupted flow of power during non-regulated operation. Inductors at the bus converter input and in a filter at the output of the bus converter may saturate during non-regulated operation.
US07787249B2	Systems and methods for printed board assembly isolated heat exchange Systems and methods for printed board assembly isolated heat exchange are provided. In one embodiment, a printed board assembly comprises: at least one electrical power layer; at least one electrical ground layer; a first signal layer having a first signal routing area providing electrical trace connections for signals and a first heat exchange chassis fill conductor area located adjacent to a periphery of the first signal routing area; at least one thermal interface coupled to a chassis for conducting heat from the printed board assembly to the chassis; and at least one via conductively coupling the first heat exchange chassis fill conductor area to the at least one thermal interface.
US07787246B2	Computer device and cluster server device A computer device includes a plurality of information processing units configured to execute respective information processing functions, a plurality of storage units, one of which is arranged in each of the information processing units, and which are removable, a plurality of storage devices physically dispersed in the storage units, and having a redundant configuration, where one storage unit includes at least two storage devices, and a plurality of controllers configured to be installed in the information processing units, and to access the storage devices, where each information processing unit includes one of the controllers.
US07787244B1	Hard disk adapter A hard disk adapter has a body, a connector, an opening, a plug-in slot and an eSATA connector. The body has a panel and a receiving space. The connector is attached to the body and located in the receiving space. The opening is formed on the panel and communicates with the receiving space. The plug-in slot is formed on the panel beside the opening. The eSATA connector has a receiving end mounted to the plug-in slot.
US07787242B2	Method and apparatus for supporting a display on a chassis A display support apparatus includes a stabilizing member defining a cable passageway, a rotational coupling member coupled to the stabilizing member, and a plurality of supporting arms coupled to the stabilizing member, at least one supporting arm defining a cable-routing channel, whereby the stabilizing member rigidly maintains the plurality of supporting arms in a substantially parallel orientation relative to each other. The display support apparatus may be rotatably coupled to a chassis base and a display may be rotatably coupled to the support arms to provide rigid support for the display on the chassis.
US07787239B2	Housing feature for providing stability for a portable terminal A portable computing device including a housing having a top surface and a bottom surface connected to one another by a pair of sides, a proximal end and a distal end, the top surface including a user interface for operation by a user. The device comprises a planar surface located on the bottom surface at the proximal end, such that the planar surface extends to either side of a centerline of the housing and in a direction towards the distal end. The planar surface defines a plane and the centerline extends in a direction between the proximal end and the distal end. The device has at least one protrusion located on the bottom surface at the distal end, such that the at least one protrusion extends between the bottom surface and the plane, such that the at least one protrusion has a respective peripheral surface lying on the plane on both sides of the centerline. The at least one protrusion and the planar surface provide stability of the device when placed on a surface adjacent to the bottom surface, the stability facilitating operation of the user interface by the user.
US07787233B1	Multi-segment capacitor A multi-segment capacitor fabricated on a semiconductor substrate includes M×N capacitor segments arranged in a matrix of M rows and N columns. Each capacitor segment includes two groups of conductive fingers preferably made of metal wires. The metal wire fingers are distributed within multiple metal layers in such a manner that two neighboring parallel metal wire fingers within a particular metal layer are electrically insulated and connected to different terminals of the capacitor. Further, at least the longitudinal axes of the parallel metal wire fingers within two different metal layers are not parallel to each other within the same capacitor segment.
US07787232B2	Multifunction security device The present invention is directed to an apparatus for providing law enforcement and private citizens with a single device that integrates law enforcement tools and mechanisms for the application of force. An exemplary device features a metal detector, a light emitting source optionally having a strobe feature, an electric stun system, and a debilitating spray dispensing system. Some embodiments of the present invention include an electric stun system comprising a plurality of probes mounted to the distal terminus of the shaft and configured to protrude from the shaft, a plurality of plates configured longitudinally along the outer surface of the shaft, and a stun system switch disposed on the shaft. Some embodiments of the present invention include the debilitating spray dispensing system comprising at least one nozzle and a dispensing switch disposed on the handle. Some embodiments of the present invention include a handle comprising an ergonomic grip and a guard.
US07787227B1	Apparatus and method for electrostatic discharge protection of a transmit integrated circuit An apparatus and method for providing electrostatic discharge protection of a transmit integrated circuit including an ESD protect block coupled to an integrated circuit pad in a package without bond wires, and an ESD clamp circuit coupled between the ESD protect block and ground. During transmission, one or more capacitors within the ESD protect block may charge up to various levels near the peak transmit voltage, which reverse biases one or more diodes in the ESD protect block, thereby buffering the transmit circuit from the capacitive load of the ESD clamp circuit. The ESD protect block may prevent the ESD clamp circuit from activating due to the high peak voltages output from the transmit circuit. An embodiment of the ESD protect block may apply particularly to transmit power amplifier circuits in which the output signal peaks at twice the supply voltage. In one embodiment applicable for lower voltage CMOS processes, the ESD protect block includes a diode and a capacitor. In another embodiment applicable for higher voltage CMOS processes, the ESD protect block includes two diodes, one or two capacitors, and an optional resistor.
US07787219B2	In a disk drive apparatus having a diverter for providing streamlined contour and reduced axial flow at the actuator attachment interface between a flexible cable and flexure An airflow diverter is used to overcome the adverse effect of flow-induced vibration of a disk drive pivot actuator. The diverter may be formed as a separate component or as an integral portion of the flex stiffener or the actuator itself. The invention streamlines the actuator to the incoming airflow and helps reduce the torque disturbance to the actuator as it reduces the sail or parachute effect. This helps reduce power consumption due to a lower drag from the actuator assembly. The contour of the flow deflector is designed to conform closely to the curvature of the disk boundaries when the actuator is rotated to the ID position on the disk. This design serves as a shroud around the disk stack which further helps to reduce power by preserving flow momentum.
US07787217B2	Suspension bend section with stiffness-reducing features An actuator load beam comprising a preload bend section defining an array of differently configured stiffness-reducing features. The stiffness-reducing features are characteristically sized in inverse relation to a respective distance from a longitudinal centerline of the actuator load beam at the preload bend section. An associated method comprising determining a thickness of a preload bend section for an actuator load beam associated with a desired resonant performance; determining a volume of stiffness-reducing features in the preload bend section associated with a desired vertical stiffness; and arranging an array of stiffness-reducing features associated with the determined volume in an array of sequentially smaller size with the largest size of the array being disposed nearest to a longitudinal centerline of the actuator load beam at the preload bend section.
US07787215B2	Thin film magnetic head in which thermal protrusion is suppressed and method of forming the same A thin film magnetic head is provided, in which thermal protrusion can be suppressed. The thin film magnetic head includes a main magnetic pole layer which conducts a magnetic flux into the recording medium so that the recording medium is magnetized in a direction perpendicular to a surface of the recording medium, a first return yoke layer provided in a trailing side of the main magnetic pole layer, and has a recess in a top surface, a second return yoke layer provided so as to fill at least the recess of the first return yoke layer, and a thermal expansion suppression layer provided in a trailing side of the second return yoke layer. Thus, since the thermal expansion suppression layer can be provided on a surface having no recess, a possibility of a crack in the thermal expansion suppression layer can be eliminated.
US07787214B2	Disk device A disk apparatus includes a hub having a disk inserting portion having a cylindrical plane in the outer part of one end and a disk receiving portion having a flat part and being pivotably supported, a head having an inner hole through which the disk inserting portion is fitted, facing toward one face of a disk, levitating and scanning above the disk and reading a signal recorded on the disk or recording a signal on the disk, the disk being held by the disk receiving portion, and a clamp unit holding the disk with the disk receiving portion. In this case, the disk receiving portion has an inclined or declined plane. Thus, the amount and direction of deformation of the disk, which is caused by clamping, are defined, and obtaining a stable amount of head levitation independently of temperature changes can prevent the occurrence of a distortion of the disk.
US07787212B2	Stiffness reducing features in a top layer of a laminated top cover Stiffness reducing features for top covers of data storage systems are provided to prevent delaminating of top layers of the top covers. A top cover for a data storage system includes a bottom layer, a top layer and an adhesive layer that interconnects the top and bottom layers. At least one groove is formed in and extends along the top layer. The at least one groove reduces a thickness of the top layer along the at least one groove.
US07787211B2	Back electromotive force (BEMF) calibration method, method of controlling unloading of disk drive apparatus using BEMF calibration method, and disk drive apparatus using the same A method of calibrating a parameter to measure the back electromotive force (BEMF) of a voice coil motor (VCM), and a method and apparatus to use the calibrating method to perform unloading control. The calibration method includes: reading servo data and measuring a BEMF value while seeking two predetermined points on a disk, and storing the servo data and the BEMF value, generating an actual velocity curve of a head using the stored servo data, and an estimated velocity curve of the head using the stored BEMF value and adjusting a parameter related to a BEMF measurement to align the actual velocity curve of the head with the estimated velocity curve of the head.
US07787209B1	Method and apparatus for compensating for repeatable runout using wide embedded runout correction fields A method and apparatus for compensating for repeatable runout using wide embedded runout correction fields is provided. In one embodiment, a disk surface is provided with a write head associated therewith. The disk surface has a data track having a width. An embedded runout correction (ERC) field is written onto the disk surface, wherein the ERC field has a width that is greater than the width of the data track.
US07787208B2	Bit patterned medium having super-track, method of tracking track of bit patterned medium, head appropriate for bit patterned medium, and information recording/reproducing apparatus including bit patterned medium head Provided are a bit patterned medium having a super-track, a method of tracking a track of the bit patterned medium, a head appropriate for the bit patterned medium, and an information recording/reproducing apparatus including the bit patterned medium and the head. The bit patterned medium includes a substrate, and a recording layer comprised of a plurality of bit cells which are formed on the substrate by being separated from each other, along a plurality of tracks. Each of the plurality of tracks includes a super-track comprised of a plurality of sub-tracks. Bit cells formed on a sub-track from among the plurality of sub-tracks in the super-track are disposed so as to deviate from bit cells formed on another sub-track from among the plurality of sub-tracks in the super-track. A track ID (identification) for recognizing the super-track, and a servo burst generating a position error signal when a head tracks the super-track, are arranged in an area of each of the plurality of tracks. Meanwhile, the head includes a writing head recording information in units of sub-tracks, and a reading sensor reproducing the information in units of super-tracks.
US07787201B2	Method and apparatus for controlling fly-height of a perpendicular-magnetic-recording head in a hard disk drive A method for controlling proximity of a read element of a perpendicular-magnetic-recording (PMR) head to a PMR disk. The method includes: a) writing recorded data with a write element of the PMR head to the PMR disk; b) providing a proximity-control setting to a proximity-control element; c) positioning the read element of the PMR head with the proximity-control element as determined by the proximity-control setting in communication with the PMR disk for reading recorded data back from the PMR disk; d) measuring a resolution of a read-back signal of recorded data on the PMR disk associated with the proximity-control setting; e) determining if the resolution measured for the read-back signal of recorded data on the PMR disk satisfies a criterion for the resolution of the read-back signal of recorded data; and, f) changing the proximity-control setting, and repeating b), c), d) and e), unless the resolution satisfies the criterion.
US07787198B1	Lens barrel assembly Various lens barrels and lenses are provided which may be used in miniature cameras. In one example, a lens barrel assembly includes a substantially cylindrical lens barrel with a first end including a first aperture and a second end including a second aperture. The first end further includes a first substantially annular portion having a first diameter and a first external surface. The first end also includes a second substantially annular portion having a second diameter and a second external surface. The second diameter is smaller than the first diameter and greater than a diameter of the first aperture. The first external surface of the first substantially annular portion is recessed in relation to the second external surface of the second substantially annular portion. The lens barrel assembly may also include a lens having a portion that protrudes from the second aperture of the second end of the housing.
US07787195B2	Illumination lens and endoscope illuminating optical system An endoscope illuminating optical system includes an illumination lens having a positive power. Illumination light rays parallel to each other emitted from an optical fiber bundle enter an incident surface of the illumination lens. The incident surface of the illumination lens is aspherical, and has a reference position vertical to the optical axis. The reference position is the most projecting portion on the incident surface. A shape of the incident surface is expressed by an equation of D=F(H). “H” is a height from the optical axis (0≦H≦Hmax), and “D” is a depth from a reference plane. The reference plane is vertical to the optical axis. The reference position is on the reference plane. A first-order differential value of the function F(H) is more than 0, and a second-order differential value of the function F(H) is 0 at a particular height Hi (0
US07787194B2	Adjustable lens mounting assembly An adjustable lens mounting assembly has a detent system which provides a defined vertical movement of a lens per detent index. A calibration of a lens during assembly of an image sensor is therefore achieved with no moving parts, and generation of foreign material is minimized. Furthermore, gluing of the components can be dispensed with.
US07787193B2	Imaging device and camera The present invention aims to provide an imaging device and a camera realizing simultaneously a high magnification zoom lens system and the miniaturization of the device. The imaging device (2) includes a first lens group (G1), a second group frame unit (42), a first group frame unit (41), a motor unit (32), a third lens group (G3), and a CCD unit (33). The first lens group (G1) takes in a light flux incident along a first optical axis (A1). The second group frame unit (42) bends the light flux incident along the first optical axis (A1) to a direction along a second optical axis (A2). The first group frame unit (41) retains the first lens group (G1), and moves the first lens group (G1) in the direction along the first optical axis (A1). The motor unit (32) drives the first group frame unit (41). The first group frame unit (41) includes a driving frame (51) movable in the direction along the first optical axis (A1), and a first group frame retaining the first lens group (G1) and able to move in the direction along the first optical axis (A1) with respect to the driving frame (51).
US07787191B2	Zoom lens A zoom lens including a first lens group with a negative refractive power and a second lens group with a positive refractive power is provided. The first lens group is composed of a first lens, a second lens, and a third lens. Refractive powers of the first lens, the second lens, and the third lens are respectively negative, negative, and positive. Moreover, the second lens group is disposed between the first lens group and an image side. The second lens group is composed of a fourth lens, a fifth lens, and a sixth lens. Refractive powers of the fourth lens, the fifth lens, and the sixth lens are respectively positive, negative, and positive. The first lens group and the second lens group are capable of moving between an object side and the image side. The zoom lens has advantages of wide angle and small volume.
US07787190B2	Optical element and imaging device An optical element includes a first liquid; a second liquid that is immiscible with the first liquid and that has polarity or electrical conductivity; a first substrate portion; a second substrate portion; a sidewall portion; a second electrode disposed on one of the second substrate portion and the sidewall portion; and an accommodating portion constituted by the first substrate portion, the second substrate portion, and the sidewall portion and sealing the first liquid and the second liquid therein. The optical element further includes a first film disposed on the first substrate portion side of the accommodating portion and having high affinity with the first liquid, a second film disposed on the second substrate portion side of the accommodating portion and having high affinity with the second liquid, and a third film disposed at the center of the second film and having high affinity with the first liquid.
US07787188B2	Image pickup apparatus An image pickup apparatus that comprises: an optical path splitting element; an optical system including a variable-optical-power element which is substantially immobile in an optical axis direction and a reflective surface; and an image pickup surface, the variable-optical-power element, the optical system, and the image pickup surface being arranged so that a ray from an object side is divided into two rays by the optical path splitting element, at least one of the rays enters the optical system, and is reflected by the reflective surface to return to the optical path splitting element, and the ray strikes on the image pickup surface via the optical path splitting element.
US07787182B2	Diffractive optical security device The diffractive optical device (1) can be used as a security device in the fields of authentication, identification and security. It comprises a zero-order diffractive color filter (3). The diffractive color filter may consist of a microstructured high-index layer (32) embedded between two low-index layers (31, 33). A mirror layer (4) for reflecting towards the diffractive color filter (3) at least part of light transmitted through the diffractive color filter (3) are provided beneath the diffractive color filter. Thanks to the mirror layer (4), the device (1) has a much higher reflected intensity and much more complex spectra than prior-art diffractive color filters.
US07787176B2	On-chip optical amplifier An on-chip amplifier includes first element that curtails the velocity of an incoming light to the amplifier. A second element is doped so as to make the frequency of the incoming light equal to the electron frequency in order to allow for electron-photon wave interaction, so that when current flows through the amplifier, electron power is transferred to the incoming light, resulting in amplification of the incoming light.
US07787174B2	Pattern generator The present invention relates to an apparatus for creating a pattern on a workpiece sensitive to radiation, such as a photomask a display panel or a microoptical device. The apparatus may include a source for emitting light flashes, a spatial modulator having modulating elements (pixels), adapted to being illuminated by the radiation, and a projection system creating an image of the modulator on the workpiece. It may further include an electronic data processing and delivery system receiving a digital description of the pattern to be written, converting the pattern to modulator signals, and feeding the signals to the modulator. An electronic control system may be provided to control a trigger signal to compensate for flash-to-flash time jitter in the light source.
US07787173B2	System and method for multi-level brightness in interferometric modulation A display having a plurality of reflective display elements. In one embodiment, the display elements comprise at least one electrode having a plurality of active areas. In one embodiment, at least two of the sizes of the active areas are different with respect to each other, e.g., they are non-uniform in size. The interferometric modulators have a plurality of states, wherein selected ones of the interferometric modulators are configured to be actuated depending differing electrostatic forces in the interferometric modulators. The electrostatic forces in the interferometric modulators are different at least in part due to variations in the sizes of the active areas of the electrodes.
US07787171B2	Human-readable, bi-state environmental sensors based on micro-mechanical membranes An environmental sensing device includes an interferometric modulator which permanently actuates, in a visually-detectable manner, in response to being exposed to a predetermined environmental threshold or condition. The device can include a reactive layer, coating, or proof mass disposed on a movable member of the interferometric modulator. The reactive layer, coating, or proof mass can expand, contract, bend, or otherwise move when exposed to a predefined chemical, level of humidity, temperature threshold, type of radiation, and/or level of mechanical shock, causing the interferometric modulator to collapse and permanently indicate such exposure.
US07787164B2	Apparatus and method to evaluate a holographic data storage medium A method to evaluate a holographic data storage medium, wherein the holographic data storage medium is evaluated by a manufacturer. In certain embodiments, the holographic data storage medium is evaluated by a customer prior to encoding customer information into the storage medium. In certain embodiments, the holographic data storage medium is evaluated by a customer after encoding customer information therein.
US07787161B2	Image reading device and image forming apparatus An image reading device which is capable of reading out image data on an original while conveying the original in a simple construction. A conveying path has a pair of guide members facing each other at a distance and extending in a conveying direction of an original. An original conveying unit conveys the original along the conveyance path. An image reading unit is comprised of a flexible sheet-like substrate on which a plurality of optical sensors are arranged. The sheet-like substrate is inclined with respect to the conveying direction of the original, and fixed to one of the pair of guide members at one end thereof and abuts against the other of the pair of guide members at the other end thereof. The image reading unit reads image data on one side of the original when the original is conveyed along the conveying path and passes through between the other end of the sheet-like substrate and the other of the pair of guide members.
US07787160B2	Driving device and scanner The driving device is provided with a motor, a pinion, a first gear, a second gear, and a frame. The frame has a motor side surface and a gear side surface, and includes a first portion and a second portion. A motor housing of the motor is fixed to and supported at the motor side surface of the first portion. A motor shaft extends from the motor housing, penetrating the first portion from the motor side surface to the gear side surface. The pinion is fixed to the distal end of the motor shaft at the gear side surface. The first gear and the second gear are coaxially disposed and rotatably supported at the gear side surface of the second portion. The driving force of the motor is transmitted to the first gear and the second gear through the pinion. The gear side surface of the second portion is offset toward the motor side than the motor side surface of the first portion.
US07787159B2	Achieving convergent light rays emitted by planar array of light sources Systems and methods are provided for achieving convergent light rays emitted by a planar array of light sources. In one embodiment, an imaging device is provided for inspecting semiconductors or other objects. The imaging device includes one or more imaging lens for imaging light reflected from an object. The imaging device also includes a first light source attached to a planar circuit board and a second light source attached to the planar circuit board. The imaging device further includes a first Fresnel prism for directing light from the first light source toward the object from a first direction and a second Fresnel prism for directing light from the second light source toward the object from a second direction. In one embodiment, the imaging device also includes one or more optical elements for increasing or decreasing the divergence of the light.
US07787156B2	Facsimile device A facsimile device connected to a public line in parallel with an external telephone is provided. The facsimile device includes a facsimile circuit configured to send and receive image data through the public line, a voltage detector that detects a voltage of the public line, a telephone status monitoring unit configured to judge whether the external telephone closes the public line based on the voltage of the public line detected by the voltage detector and a reference voltage, a monitoring operation control unit configured to keep the telephone status monitoring unit in an inactive state until a predetermined time elapses from a time when the facsimile circuit releases the public line, and to activate the telephone status monitoring unit if the predetermined time elapses from the time when the facsimile circuit releases the public line.
US07787150B2	Print data forming apparatus In a print data forming apparatus, a color conversion information storing section stores plural color conversion information, a mode shift detecting section detects a shift to an image converting mode, an image conversion processing section forms plural printer characteristics images based on the stored respective color conversion information from received drawing data, a monitor image conversion processing section converts the printer characteristics images into plural monitor characteristics images which can be displayed on a monitor, and an input section requests a selection of a specific one of the displayed monitor characteristics images. An unnecessary consumption amount of sheets and toner is avoided in color reproducing mode settings of the print data forming apparatus having color conversion tables.
US07787149B2	Method of generating color conversion table, information generation apparatus, recording medium, and image processing apparatus A color conversion table for converting M color signals of an input system into N color signals of an output system is disclosed. The color conversion table is prepared by and obtained based on a calculation target point corrected by moving a position of the maximum gradation of each fundamental color of the output system to a position of the maximum gradation of the fundamental color of the input system and on calculation target points corrected for gradations other then the maximum gradation of each fundamental color by moving positions of the gradations of the fundamental color in output system to the positions of the gradations of the fundamental color in the input system.
US07787147B2	Printing method and apparatus correcting ink ejection in each row region using a combined correction value for certain coexistent row regions A printing method includes determining a first correction value corresponding to a first print mode, determining a second correction value corresponding to a second print mode, and correcting an ink ejection amount of each row region individually, using a combined correction value obtained by combining the first correction value and the second correction value. The first print mode is a print mode that is applied to a front end area, with respect to a transport direction, of a medium. Dot rows are formed extending in a nozzle movement direction that is perpendicular to the transport direction, on a plurality of row regions lined up in the transport direction. The dot rows are formed by repeating a movement ejection operation of ejecting ink onto the medium while moving nozzles in the movement direction, and a transport operation of transporting the medium in the transport direction. The first correction value is for correcting an ejection amount of the ink in each row region individually. The second print mode is a print mode that is applied to a middle area, with respect to the transport direction, of the medium. The second correction value is for correcting an ejection amount of the ink in each row region individually. The correction of the ejection amount using the combined correction value is carried out in a coexistent segment in which certain row regions and another row regions are coexistent. The certain row regions are row regions in which the dot rows are formed by the first print mode. The other row regions are row regions in which the dot rows are formed by the second print mode.
US07787146B2	Method of setting driver program of image processing device and image processing system with transparent function A method of setting a user interface of a driver program of an image processing device includes applying a transparent setting to display the driver program in a transparent state on a display device to the driver program, and displaying the driver program with the applied transparent function on the display device when an application program operates the driver program. The driver program does not block an acquired result of the application program, and a user is able to perform a scanning operation at an optimum environment by adjusting a transparency level of the driver program displayed over the application program.
US07787145B2	Methods for improving print quality in a hand-held printer Method for determining enhanced printing functions on a hand-held inkjet printer having one or more optical sensors configured to measure speed and distance across the page. Collecting a first frame of individual pixel data, mapping the first frame of individual pixel data into a pixel map memory, processing the first frame of individual pixel data to perform additional print quality features. These additional features can be categorized in three main categories: 1) sensing non-printing elements, 2) sensing pre-printed elements, and 3) sensing print elements.
US07787143B2	Job information management method and apparatus This invention increases the job information management precision. To accomplish this, an information processing method of recording or accumulating job information on a job issued from an information processing apparatus connectable to an image forming apparatus including an acquisition step of acquiring the job information from the information processing apparatus or the image forming apparatus, a determination step of determining whether to record or accumulate the job information acquired in the acquisition step, in accordance with a driver which generates data of the issued job, and a recording/accumulation step of recording or accumulating the job information determined in the determination step to be recorded or accumulated.
US07787138B2	Scheduling system A system suited to scheduling print jobs for a printing system includes a first processing component which identifies preliminary attributes of print jobs to be printed on sheets. A job scheduler receives the preliminary attributes and assigns each of the print jobs to one of a plurality of job queues in time order for printing. Print jobs spanning the same time are scheduled for printing contemporaneously. In one mode of operation, the assignment of the print jobs to the job queues is based on their preliminary attributes and on the application of at least one constraint which affects contemporaneous printing of at least two of the plurality of print jobs. A second processing component identifies detailed attributes of the print jobs. A sheet scheduler receives information on the assignments of the print jobs and their detailed attributes and forms an itinerary for each sheet to be printed.
US07787130B2	Human-readable, bi-state environmental sensors based on micro-mechanical membranes An environmental sensing device includes an interferometric modulator which permanently actuates, in a visually-detectable manner, in response to being exposed to a predetermined environmental threshold or condition. The device can include a reactive layer, coating, or proof mass disposed on a movable member of the interferometric modulator. The reactive layer, coating, or proof mass can expand, contract, bend, or otherwise move when exposed to a predefined chemical, level of humidity, temperature threshold, type of radiation, and/or level of mechanical shock, causing the interferometric modulator to collapse and permanently indicate such exposure.
US07787128B2	Transducer for measuring environmental parameters Apparatus, methods, and other embodiments associated with measuring environmental parameters are described herein. In one embodiment, a transducer comprises a tube, an elongated member, a first reflective surface, a second reflective surface, and an optical fiber. The tube has a first end and a second end, and the elongated member also has a first end and a second end, with the first end of the elongated member secured to the tube. The second reflective surface is secured to the second end of said elongated member, and the first reflective surface is spaced apart from the second reflective surface and secured to the second end of the tube. The optical fiber is positioned to direct light towards the first and second reflective surfaces and to collect the reflected light from these two surfaces.
US07787116B2	Cuvette A cuvette capable of suppressing the complication of the structure of each part of an analyzer and enabling the stirring of a specimen in a short time. The cuvette comprises: a first body part positioned on a bottom part side, having inner and outer surfaces of circular shape in horizontal cross section, and receiving a measuring beam; and a second body part positioned on an opening side, having an inner surface of non-circular shape in horizontal cross section and an outer surface of circular shape in horizontal cross section.
US07787111B2	Simultaneous acquisition of fluorescence and reflectance imaging techniques with a single imaging device for multitask inspection A hyperspectral reflectance and fluorescence line-scan imaging system is used for on-line quality and safety inspection of agricultural commodities. The system simultaneously acquires hyperspectral/multispectral combinations of both fluorescence and reflectance images of the agricultural commodities.
US07787109B2	Transmission spectroscopy system for use in the determination of analytes in body fluid A total transmission spectroscopy system for use in determining the analyte concentration in a fluid sample comprises a sample cell receiving area, a light source, a collimating lens, a first lens, a second lens, and a detector. The sample cell receiving area is adapted to receive a sample to be analyzed. The sample cell receiving area is constructed of a substantially optically clear material. The collimating lens is adapted to receive light from the light source and adapted to illuminate the sample cell receiving area with a substantially collimated beam of light. The first lens is adapted to receive regular and scattered light transmitted through the sample at a first angle of divergence. The first lens receives light having a first angle of acceptance. The first lens outputs light having a second angle of divergence. The second angle of divergence is less than the first angle of divergence. The second lens is adapted to receive light from the first lens and adapted to output a substantially collimated beam of light. The detector is adapted to measure the light output by the second lens.
US07787105B2	Taking distance images A system and method for the taking of a large number of distance images having distance picture elements. Electromagnetic radiation is transmitted in the form of transmission pulses at objects, and reflected echo pulses are detected. Measurements are made by determining the pulse time of flight of the distances of objects which respectively form a distance picture element and at which the transmission pulses are reflected. A time measuring device carries out a plurality of associated individual measurements for each distance image to be taken. Stored event lists of all time measuring channels are read out and evaluated in order to convert the respective time information contained in the event lists into distance values corresponding to the distance picture elements.
US07787102B2	Real-time configurable masking Methods, systems, and media to define a portion of a circuit pattern with a source of real-time configurable imaging are disclosed. Embodiments include hardware and/or software for directing a beam through a mask onto a wafer surface to outline a circuit pattern having an undefined area, directing a second beam to the semiconductor wafer surface to define a circuit structure in the undefined area to complete the circuit pattern on the semiconductor wafer surface, and directing the second beam onto a source of real-time configurable imaging. Embodiments may also include a mask to include an undefined area incorporated into the circuit pattern to leave a critical structure of the circuit pattern undefined. Several embodiments include a photolithography system including an exposure tool, a mask, a source of real-time configurable imaging, and addressing circuitry.
US07787099B2	Apparatus and method for washing alignment film printing mask and method for fabricating a liquid crystal display device The present invention relates to an alignment film printing mask, and more particularly, to a jig for an alignment film printing mask. A jig according to the present invention includes a plurality of supporting members each having at least one bent portion, arranged at regular intervals along a width direction of the alignment film printing mask for supporting the alignment film printing mask, at l one connection member for connecting the supporting members, and fastening units for securing the alignment film printing mask supported by the supporting members.
US07787098B2	Manufacturing method of a liquid crystal display device comprising a first photosensitive layer of a positive type and a second photosensitive layer of a negative type A manufacturing method of a liquid crystal display device includes forming a gate line and a data line on a substrate with the gate and data lines crossing each other to define a pixel region; forming a thin film transistor at a crossing portion of the gate and data lines; forming a passivation layer on the substrate and the thin film transistor; forming a transparent conductive layer on the passivation layer; forming a first photosensitive layer on a portion of the transparent conductive layer over the thin film transistor; forming a second photosensitive layer on the transparent conductive layer and the first photosensitive layer; patterning the second photosensitive layer and the first photosensitive layer to form a photosensitive pattern and a columnar spacer exposing a portion of the transparent conductive layer; forming a pixel electrode by patterning the transparent conductive layer exposed by the photosensitive pattern and the columnar spacer; and removing the photosensitive pattern.
US07787097B2	Flexible base material and flexible image-displaying device resistant to plastic deformation An anti-deformation structure is formed on the surface of a flexible plate-shaped part. The anti-deformation structure includes protrusions and depressions formed on the surface of the plate-shaped part. The protrusions and depressions has a shape in which adjacent protrusions become in contact with each other in the state when the plate-shaped part is deformed within a range of elastic deformation, restricting further greater deformation, and thus, preventing excessive deformation leading to permanent deformation and raising the resistance to the stress. The flexible base material can be applied to flexible image-displaying devices.
US07787093B2	Array substrate for a liquid crystal display device with thin film transistor having two drain electrode patterns and manufacturing method of the same An array substrate for a liquid crystal display device includes gate and data lines crossing on a substrate, common lines parallel to and between the gate lines, thin film transistors at crossing portions of the gate and data lines, and a pixel electrode. The common lines define pixel regions, which are each divided into first and second regions by the corresponding gate line. The thin film transistors each include a gate electrode in a first direction, a semiconductor layer on the gate electrode, and source and drain electrodes on the semiconductor layer in a second direction. The source and drain electrodes cross the gate electrode in each of the first and second regions. The pixel electrode is connected to the drain electrode.
US07787092B2	Vertical alignment active matrix liquid crystal display device having particular reflection metal films A liquid crystal display device comprises a TFT substrate, a CF substrate, a liquid crystal with negative dielectric anisotropy filled between the substrates, a pixel electrode provided on the TFT substrate, and an auxiliary electrode formed around the pixel electrode. A slit for segmenting a pixel region into a plurality of sub-pixel regions is formed in the pixel electrode from the center portion of each pixel toward the periphery portion thereof. The auxiliary electrode has a transparent step film formed at a position corresponding to the slit of the pixel electrode in such a way as to overlie the auxiliary electrode. Molecules of the liquid crystal of each sub-pixel region are aligned toward center of the sub-pixel region from the circumference of the sub-pixel region by a horizontal electric filed applied between the pixel electrode and auxiliary electrode, and the shape of the end portion of the transparent step film.
US07787082B2	Photosensor and display device A photosensor including a semiconductor thin film having a light receiving portion includes the following elements. A substrate has a recess with an inclined side wall having a forward tapered shape. A reflective material layer is disposed along the recess of the substrate. An insulating layer covers the substrate having thereon the reflective material layer. The semiconductor thin film is disposed on the insulating layer so as to cross the recess. The light receiving portion of the semiconductor thin film is disposed above the recess.
US07787079B2	Generation of pattern data with no overlapping or excessive distance between adjacent dot patterns A device is disclosed for generating pattern data for unevenness that is randomly arranged on the surface of the reflective substrate of a reflective liquid crystal display device. The number of coordinates, a basic pitch, a movable range, and a dot diameter are entered from a data entry unit. An array generation unit regularly arranges base coordinates in two dimensions in accordance with the basic pitch. Coordinate displacement unit randomly displaces within the movable range at a portion of the basic coordinates to generate a multiplicity of displaced coordinates. Pattern generation unit arranges dot patterns with the dot diameter entered at each of the displaced coordinates generated to generate pattern data.
US07787078B2	LCD device suppressing a parallax problem An LCD device includes front substrate and rear substrate sandwiching therebetween an LC layer, front polarizing film and rear polarizing film disposed on the front side of the front substrate and the rear side of the rear substrate, respectively, and a reflecting film disposed on the rear side of the rear polarizing film. The distance between the LC layer and the reflecting film is set at 0.8 mm or smaller, to solve a parallax problem.
US07787075B2	Liquid crystal display Disclosed herein is a liquid crystal display that compensates an hourglass phenomenon using a backlight unit. The liquid crystal display includes a liquid crystal panel, a polarizer adhered to the liquid crystal panel, and a backlight unit including a diffuser sheet. A predetermined region of the diffuser sheet facing a region of the polarizer, where an hourglass phenomenon occurs, is formed to permit a smaller quantity of light to be transmitted therethrough than other regions of the diffuser sheet. With this construction, the liquid crystal display can avoid the hourglass phenomenon from being observed by a viewer, and prevent non-uniform brightness while improving image quality.
US07787073B2	Backlight unit with a plurality of lamps each including an LED chip with a protecting lens therefor and a semi-transparent material and reflecting substance on the upper part of the lens A backlight unit includes a plurality of lamp array units, each having a plurality of LED lamps evenly arranged in one direction, a reflecting substance formed on an upper surface of each of the LED lamps to reflect light emitted from the corresponding LED lamp in a lateral direction, a light dispersion member provided over the lamp array units, and an outer case supporting the light dispersion member.
US07787067B2	Display substrate and method of manufacturing the same A display substrate includes a first metal pattern, a first insulating layer, a first electrode, and a second metal pattern. The first metal pattern includes a gate line and a signal line. The first insulating layer is disposed on a substrate having the first metal pattern formed thereon. A first opening passes through the first insulating layer to partially expose the signal line. The first electrode is disposed on the first insulating layer corresponding to a unit pixel. The second metal pattern includes a connection electrode contacting the first electrode and the signal line through the first opening and a data line.
US07787058B1	System and method for providing information synchronized to a playlist Information is provided to on-air personnel that is synchronized to a playlist executed by a broadcast automation system. A type is defined within a broadcast automation system and is associated with studio segments and non-studio segments that follow studio segments in a playlist. As the playlist is executed, the broadcast automation system provides a count until the next segment with the specified type. The count is monitored and if the count matches a predetermined value, then a trigger is generated based on the predetermined value and the playlist. Each trigger is associated with a particular action, such as the display of a message on certain display units. Once the trigger is generated, the action is performed. The invention can be used to automatically provide countdown information to on-camera personnel based on the playlist.
US07787056B2	Apparatus and method for restoring DC spectrum for analog television reception using direct conversion tuners A DC compensation circuit restores the frequency spectrum of an input signal at DC (or 0 Hz) by removing or reducing DC offset, 1/f noise, or any other unwanted noise at or near 0 Hz. The DC compensation is performed using direct coupling, as opposed to AC coupling, so that no useful signal information in the active period of the input signal is lost at DC. The DC compensation circuit samples the input signal during an inactive period of the input signal. Afterwhich, the unwanted DC noise is determined from the sampled signal and stored until an active period of the input signal. For example, the sampled signal can be filtered using a passband around DC so as to isolate the signal energy at DC during the inactive period. Since there is no useful signal information present during the inactive period, any signal energy at the output of the filter is necessarily unwanted DC noise. In a feed-forward approach, the unwanted DC noise is then subtracted from the input signal during the active period of the input signal to compensate or cancel the unwanted DC noise. Alternatively, the unwanted DC noise could be sampled and determined during the inactive period and then fed back (after filtering) in order to be subtracted during the active period of the input signal.
US07787055B2	Signal processing method, image display apparatus, and television apparatus A signal processing method comprises the steps of: inputting three signals specifying a color of one pixel; and generating four signals from the input three signals, wherein each of said four signals represents intensities of four different colors to display a color of one pixel by mixing colors, wherein said generating step includes a first converting step of converting the input three signals to two signals representing intensities of two colors among the four colors and a signal representing intensity of a mixed color obtained by mixing (a) the four colors or (b) a plurality of colors among the four colors; and a second converting step of converting the signal representing intensity of the mixed color to a plurality of signals representing intensities of a plurality of colors including at least other two colors different from the two colors.
US07787054B2	VSB reception system with enhanced signal detection for processing supplemental data A VSB reception system includes a sequence generator for decoding a symbol corresponding to the supplemental data and generating a predefined sequence included in the supplemental data at VSB transmission system. The reception system also includes a modified legacy VSB receiver for processing the data received from the VSB transmission system in a reverse order of the VSB transmission system by using the sequence, and a demultiplexer for demultiplexing the data from the modified legacy VSB receiver into the MPEG data and the supplemental data. The VSB reception system also includes a supplemental data processor for processing the supplemental data segment from the demultiplexer in a reverse order of the transmission system, to obtain the supplemental data, thereby carrying out the slicer prediction, decoding, and symbol decision more accurately by using the predefined sequence, to improve a performance.
US07787049B2	Image processing system and method, and image display system There is provided an image processing method capable of improving the picture quality. The image processing method comprises: incorporating input frame pictures to be displayed on a display device, on the basis of an input picture signal and an input synchronizing signal which is synchronized with the input picture signal; recording the incorporated input frame pictures in an input frame memory; and producing output frame pictures from input frame pictures, which have been recorded in the input frame memory, by producing an interpolated picture or inserting a black raster picture or thinning out the frame pictures, between input frame pictures corresponding to a picture information of the input frame picture to be displayed, on the basis of the picture information and the input synchronizing signal and an output synchronizing signal.
US07787047B2	Image processing apparatus and image processing method According to one embodiment, an image processing apparatus includes a resolution increasing module and a moving-image improving module. The resolution increasing module performs, on receipt of a first video signal with first resolution, super resolution conversion on the first video signal to obtain a second video signal with second resolution that is higher than the first resolution by estimating an original pixel value from the first video signal and increasing pixels. The resolution increasing module also performs first correction on the second video signal obtained by the super resolution conversion. The moving-image improving module configured to perform, on the second video signal subjected to the first correction, second correction except for a correction process included in the first correction.
US07787042B2	Image display device for displaying a calendar corresponding to a sensed image A sensed image and shooting time information corresponding to the sensed image are stored on a memory card. A display unit comprises a plurality of display areas at specific consecutive shooting times and displays the shooting time in the display area. A CPU specifies a display area in which a sensed image corresponding to the shooting time as an image-existing area, and enables the display unit to visibly indicate the image-existing area of the display areas specified as the image-existing area, based on a prescribed condition by a cursor. In this case, when the movement of the display area is instructed, the CPU moves only the image-existing area and indicates the existence of an image, by controlling the movement of the cursor.
US07787039B2	MOS sensor and drive method thereof To provide a drive method for finding out an optimum storage period quickly. To provide a drive method for finding out an optimum storage period quickly. In the method for driving the MOS sensor having a plurality of pixels, after all the plurality of pixels are simultaneously reset, signals are then sequentially outputted from said plurality of pixels. The period from the reset time to the time just before said plurality of pixels output saturated signals is termed as the storage period.
US07787033B2	Apparatus and method for determining temperature of an active pixel imager and correcting temperature induced variations in an imager An imager temperature sensor and a current correction apparatus are provided which use dark pixel measurements from an imager chip during operation together with a fabrication process constant as well as a chip dependent constant to calculate chip temperature. The chip temperature may be used to generate a current correction signal. The correction signal is used to tune a current on the imager chip to correct for temperature variations.
US07787032B2	Method and apparatus for dark current reduction in image sensors Methods and apparatuses for dark current reduction by adjustment of electrical characteristics of transfer gates in pixels within an imaging sensor based on image comparisons.
US07787027B2	Information input apparatus and method An electronic camera is capable of recording image, voice, text, line-drawn information and the like. A release switch in the electronic camera is operated to photograph a subject image. When recording voice with the electronic camera, shutter sound effects are not output with the recorded voice. Further, the photographic operation can be indicated to the user by lighting a light-emitting diode in a finder when the release switch is operated.
US07787023B2	Video signal processing apparatus By setting an area for displaying OSD data, a high-intensity part of this area is highlighted and an area which is not to be highlighted is set. Also, by performing translucent display of the OSD data and natural-image data, an area which is not to be highlighted can be set.
US07787021B2	Programmable architecture for flexible camera image pipe processing This invention is a programmable image pipe processing architecture that offers full software flexibility to implement latest and greatest algorithms at fully hardwired performance levels. This invention achieves hardwired image pipe processing performance but offers full flexibility and programmability of software achieving the best of both hardwired and software image pipes processing.
US07787017B2	Digital camera and method for identification of objects The invention concerns a method for identification of stationary or moving objects such as images, texts or physical items on the basis of a digital representation (308), to be learned, of the object or of a part of the object. Within the representation (308) to be learned or within a detail (310), a search window (312) is initially selected here which occurs only once within the representation (308) to be learned or within the detail (310). At least one search detail (314, 316, 318) within the search window (312) is then selected, and forms the basis for the object identification. The invention further relates to a digital camera, in particular for image processing in an industrial environment.
US07787015B2	Apparatus and method for reducing image blur in a digital camera A digital camera delays the capture of a digital image after image capture has been requested until the motion of the digital camera satisfies a motion criterion. The digital camera thereby reduces image blur that would otherwise occur due to camera motion.
US07787014B2	Systems, apparatus and methods for portable imaging In some implementations, a portable imaging system includes a host computer, a docking station connected to the host computer, and a portable imaging device intermittently attached to the docking station and configured to communicate data with the host computer through a wired connection when the portable imaging device is attached to the docking station, and through a wireless connection when detached from the docking station. In some implementations, a method for communicating data between a portable imaging device and a computer is also provided. In some implementations, the method includes determining whether a wired connection is established between the portable imaging device and the computer. In some implementations, if established, the wired connection is used to communicate data between the portable imaging device and the computer. In some implementations, if a wired connection is not established, a wireless connection between the portable imaging device and the computer is established and used to communicate data between the portable imaging device and the computer.
US07787013B2	Monitor system and camera A monitor system which can flexibly deal with changes in the system structure and perform monitoring of high quality includes a plurality of cameras and connected via a communication medium. Each of the plurality of cameras includes: an image capturing device which captures an image of an image capturing area included in a monitoring area and changes the image capturing area; a communication unit which (i) transmits, to another camera via the communication medium, the image capturing characteristics information for identifying the image capturing area and (ii) receives image capturing characteristics information from another camera; and an image capturing characteristics change unit which changes the image capturing area by controlling the image capturing device of the camera based on the image capturing characteristics information of the camera and the image capturing characteristics information of another camera received in the communication unit so that the image capturing area of the camera and the image capturing area of another camera have a predetermined relation.
US07787009B2	Three dimensional interaction with autostereoscopic displays An apparatus and method for 3D interaction with an autostereoscopic display are presented. A motion tracking system may include video cameras that track a 3D motion of a user within an interaction volume defined by the fields-of-view of the video cameras, as the user moves a light source or other optical marker or an anatomical region of the user within the interaction volume. The motion tracking system may generate 3D tracking data containing position information about the 3D motion. An imaging system may create a virtual scene by tracing 3D virtual objects in virtual space, using the position information in the 3D tracking data. The imaging system may synthesize a plurality of views of the virtual scene, and interlace the plurality of views to generate an interlaced image to drive the autostereoscopic display and to be displayed thereon.
US07787004B2	Line head and image forming apparatus using the same A line head includes: a first substrate that includes light-emitting elements formed thereon; and a second substrate that includes focusing lenses, which are inverted optical systems, focusing light emitted from the light-emitting elements, and has a linear expansion coefficient that is smaller than that of the first substrate.
US07787000B2	Exposure adjustment of an image using G+/G− curve An improved exposure adjustment technique for brightening and darkening an image using a modified Gamma-like (G+) function is provided. The G+ function possesses characteristics such that, when applied brightening an image, the darker pixels are not enhanced too quickly when brightening, and the lighter pixels are not decreased too quickly when darkening. Two pertinent characteristics include the fact that the slope of the G+ function is not infinite at the origin, where “origin” corresponds to black pixels, and the slope near the origin, where corresponding to pixels are relatively dark, is lower than the slope of a conventional Gamma-like function.
US07786996B2	System and method for object oriented hardware including cross-point switch interconnecting modules with I/O A system of inter-connectable modules that can be used to build consumer electronic sub-systems and products. Familial features are included for easy setup and control. Data is passed between modules using a common interface to permit easy routing and reconfiguration of data flows.
US07786994B2	Determination of unicode points from glyph elements Systems, methods, and/or techniques (“tools”) for determining Unicode points from glyph elements are provided. The tools may receive indications of commands that relate to text containing glyphs. Responding to the commands, the tools may convert the glyphs to corresponding Unicode representations. The tools may also provide glyph substitution tables that include Unicode fields for storing Unicode representations of characters, along with first and second glyph fields for storing glyphs of the characters. The glyph substitution tables may include links pointing from the second glyph fields to the first glyph fields, and may also include links pointing from the first glyph fields to the Unicode fields. Finally, the tools may provide character mapping tables that include Unicode fields for storing Unicode representations of characters. The character mapping tables may also include glyph fields for storing glyphs of the characters, and may include links pointing from the glyph fields to the Unicode fields.
US07786992B2	Method for rendering multi-dimensional image data A method for rendering multi-dimensional image data having a plurality of objects is disclosed. The method includes the following steps: providing an object database for storing the objects, providing a first pointer storage block, obtaining a depth value of the objects as a pointer which points to an address of the first pointer storage block, storing the pointers of the objects in the object database into the first pointer storage block and according to the depth value, sequentially searching the first pointer storage block to take out the objects from the object database for displaying the image data. The method is able to skip the comparison operations for every object with different depth values as found in the prior art. Therefore, the method can reduce the amount of computation and the occupied memory bandwidth.
US07786990B2	Cursor mode display system and method A cursor mode display system and method for indicating an offset distance between a cursor position on an image and a closest image slice in a corresponding image series. First, the three-dimensional coordinates associated with the cursor position on the image are determined by projecting the cursor position onto a three-dimensional patient coordinate system. The closest image slice is then identified as the image slice in the corresponding image series that is closest to the three-dimensional coordinates of the cursor position. The offset distance between the closest image slice and the three-dimensional coordinates associated with the cursor position is then calculated. If the offset distance does not exceed a threshold value, then the closest image slice is displayed. Otherwise a modified version of the closest image slice is displayed.
US07786986B2	Image display device The invention is to provided an integrated, optical touch panel type image display device free from crosstalk with displayed images. The image display device according to the invention comprises a plurality of pixels having display brightness modulation means controlled with display signals, a display unit in which the plurality of pixels are arrayed, and a plurality of optical detecting means provided within the display unit wherein each of the optical detecting means comprises an optical detection diode for converting incident lights into signal electric-carriers, signal electric-carrier resetting means for resetting the signal electric-carriers, and output impedance modulating means for detecting the signal electric-carriers and modulating output impedances. The output impedance modulating means in the optical detecting elements are connected, in series between each other, to a Y output line and an X output line.
US07786985B2	Semiconductor device, and display device and electronic device utilizing the same A semiconductor device having a normal function means is provided, in which the amplitude of an output signal is prevented from being decreased even when a digital circuit using transistors having one conductivity is employed. By turning OFF a diode-connected transistor 101, the gate terminal of a first transistor 102 is brought into a floating state. At this time, the first transistor 102 is ON and its gate-source voltage is stored in a capacitor. Then, when a potential at the source terminal of the first transistor 102 is increased, a potential at the gate terminal of the first transistor 102 is increased as well by bootstrap effect. As a result, the amplitude of an output signal is prevented from being decreased.
US07786983B2	Apparatus and method for a data input device using a light lamina screen A touch screen or pen-based data entry apparatus and method. The data entry apparatus creates a continuous sheet or “lamina” of light in the free space adjacent a touch screen. An optical position detection device, optically coupled to the lamina of light, is provided to detect data entries to the input device by determining the location of interrupts in the lamina caused when data is entered to the input device. During the method of operation, a user makes a data entry to the device by touching the screen at a predetermined location using an input device, such as a finger, pen or stylus. During the act of touching the screen, the lamina of light in the free space adjacent the screen is interrupted. The optical position detection device detects the position of the input based on the location of the interrupt. Based on the determined position, the data entry is determined.
US07786982B2	Display control device for touch panel-type setting-operation unit, electronic apparatus and image forming apparatus Disclosed is a display control device for a touch panel-type setting-operation unit, which is designed to display a plurality of manually operable keys on a display screen and to perform an input processing corresponding to the operation of one or more of the keys. The display control device is operable, based on an evaluation value representing the operational status of each of the keys, which is derived from the relative operation number of each of the keys in a given period of time, to vary the respective display colors of the display areas for the keys in a stepwise manner using a color gradation from a color with high visibility to a color with low visibility in the order of higher score of the evaluation value.
US07786981B2	Circular touch sensor A circular touch sensor has three or more sensors arranged in an iris pattern. Each pad is defined by continuous edges that spiral outward about a center point. The unique geometric shape allows measurement of relative amounts of contact on adjoining sensors. In one implementation, the sensors measure relative capacitance of two or more sensors, thereby enabling high precision identification of the point of contact. With as few as three pads, the circular touch sensor is less expensive than traditional 12-pad to 16-pad circular sensors.
US07786979B2	Handheld electronic device and method for disambiguation of text input and providing spelling substitution A handheld electronic device includes a reduced QWERTY keyboard and is enabled with disambiguation software that is operable to disambiguate text input. The device is structured to identify and output representations of language objects that are stored in the memory and that correspond with a text input. The device is additionally structured to identify and output representations of language objects that are stored in the memory and that correspond with a known spelling substitution particular to a language active on the handheld electronic device.
US07786973B2	Display device and method A region-based image display device includes a backlight module, a separating unit, a signal-processing unit, and a modulation unit. The backlight module includes several backlight regions. Each backlight region includes an adjustable luminance unit. Each luminance unit has a basis luminance value. The separating unit separates an input image signal into several image region signals corresponding to the backlight regions. The signal-processing unit transforms the image region signals into several output image signals. The modulation unit adjusts the basis luminance values to output luminance values according to the image region signals. Each basis luminance value and the corresponding image region signal on the one hand, and the corresponding output luminance value and output image signal, on the other hand, cooperatively define substantially the same chromaticity and brightness.
US07786972B2	Shift register and organic light emitting display using the same A shift register, including first through third output nodes and first through third input lines for first through third clock signals, a fourth input line adapted to supply a start pulse or an output signal, a voltage level controller coupled between the second and fourth input lines, the voltage level controller being adapted to control voltage levels of the first and second output nodes, a first transistor coupled between a first power supply and the third output node, the third output node being an output node of the stage, a second transistor coupled between the third output node and the third input line, and a third transistor coupled between the first output node and a second power supply.
US07786970B2	Driver circuit of display device A driver circuit of a display device according to an embodiment of the invention includes: a dot-inversion switch selectively supplying a driving voltage generated with an operational amplifier to a first pixel electrode or a second pixel electrode, the dot-inversion switch including: an operational amplifier-side switch and a pixel-side switch supplying the driving voltage to the first pixel electrode or the second pixel electrode; and a common short-circuit switch connected to a node between the operational amplifier-side switch and the pixel-side switch to supply an intermediate potential to the node.
US07786968B2	Pulse output circuit, driving circuit for display device and display device using the pulse output circuit, and pulse output method An output pulse of a flip flop is delayed in a delay inverter circuit before supplied to an input terminal of a level shifter. Then, an output pulse of the next stage flip flop is supplied to a reset terminal of the first flip flop and also to an enable terminal of the level shifter. Further, the level shifter output a sampling pulse with a beginning end equal to the beginning end of the pulse supplied to the input terminal and a terminal and equal to the beginning and of the pulse supplied to the enable terminal. With this arrangement, the subject invention provides a pulse output circuit, a driving circuit for a display device using the pulse output circuit, a display device and a pulse output method, that reduce delay of the terminal end of the pulse in sequentially outputting pulses from plural output terminals.
US07786963B2	Method and apparatus for driving liquid crystal display device having data correction function A method and an apparatus for driving a display device including a histogram calculator to calculate a histogram of pixel data for an input image and a data stretching curve generator, which divides the histogram into n (n being a positive integer above 2) gray level areas to generate a data stretching curve for each gray level area of which a gradient is determined in proportion to a total number of pixel data accumulated for each of the gray level areas, and modulates the pixel data of the input image with the generated data stretching curve.
US07786960B2	Liquid crystal display and driving method thereof A liquid crystal display device includes an integrated circuit, a signal line, an inspection line and a signal generator. The integrated circuit drives a liquid crystal display panel. The signal line applies a driving signal to the integrated circuit. The inspection line detects the driving signal inputted to the integrated circuit. The signal generator supplies a compensation signal corresponding to the detected driving signal from the inspection line.
US07786958B1	EL display device and electronic device In an EL display device in which color purity of each of red, blue and green is different, the EL display device displaying an image of a desired balance of red, blue and green is provided. A video signal supplied to each EL element is gamma (γ)-corrected by a correction circuit, the color purity of each of blue luminescence, green luminescence, and red luminescence is suitably controlled in accordance with the voltage and current of the corrected video signal.
US07786957B2	Plasma display device A plasma display device which generates reset discharge in a reset period prior to an address period in the beginning subfields of a one-field display period, and applies two sustain pulses, which have rising timings different from each other by a predetermined period of time and have partly overlapping application periods, to row electrodes forming each row electrode pair after ending a sustain period in a last subfield of the one-field display period to thereby cause erasure discharge in discharge cells where sustain discharge has been caused in the last subfield.
US07786954B2	Adjustable head-mount type display device A head-mount type display device has a first display unit for left eye, a second display unit for right eye, a guide that guides the first and second display units to slide them in a longitudinal way, and an adjustment mechanism that adjust a distance between the first and second display units. The adjustment mechanism includes a revolving member having a shaft, a left-side arm having a first end that rotatively connects the first display unit and a second end that rotatively connects the revolving member, and a right-side arm having a third end that rotatively connects the second display unit and a fourth end that rotatively connects the revolving member. When the revolving member revolves around the shaft, the first and second display units slide by a same distance from the shaft in the longitudinal way along the guide.
US07786952B2	Auxiliary display unit for a computer system A host computer is provided with a main display unit and an auxiliary display unit. The host computer can free up screen space on the main display screen by routing certain types of display information to the auxiliary display unit for display. Display information can range from notification of events such as receipt of email, appointments, system messages, and information from separate applications. The auxiliary display panel may function as a user interface for audio, video, “push information”, MP3 player or become the hardware equivalent of a multimedia player. The auxiliary display panel may be integrated together with the host computer in the same physical structure or may be part of a standalone display unit that is wired or wirelessly coupled to the host computer.
US07786950B2	Loop antenna and loop antenna manufacturing method A loop antenna is disclosed which can prevent the occurrence of variance in the loop length of the installed loop antenna element, and a method for manufacturing the loop antenna. The loop antenna comprises electrical wires constituting the antenna element and a housing that holds the electrical wires. Furthermore, the housing is formed with first guide grooves that guide the first end portions of the electrical wires and that have wall surfaces against which the tip ends on the side of the first end portions of the electrical wires abut, and second guide grooves that guide the second end portions of the electrical wires and that have wall surfaces against which the tip ends on the side of the second end portions of the electrical wires abut. Moreover, crimp parts with which the end portions of the electrical wires are connected by crimping are provided inside the respective guide grooves. In addition, a pair of contact parts that make contact with external terminals are respectively connected to the crimp parts.
US07786949B2	Antenna An antenna includes inductance elements that are magnetically coupled together, an LC series resonant circuit that includes one of the inductance elements and capacitance elements, and an LC series resonant circuit that includes another of the inductance elements and capacitance elements. The plurality of LC series resonant circuits are used to radiate radio waves and are used as inductances of a matching circuit that matches an impedance when a power supply side is viewed from power supply terminals and a radiation impedance of free space.
US07786947B2	Broadband antenna There is provided a broadband antenna including: an insulating block having opposing first and second main surfaces and a side surface between the first and second main surfaces; a first radiator pattern formed on the first main surface and having a tapered slot with an open end; and a second radiator pattern including two patterns connected to opposing ends of the first radiator pattern, respectively, and extending to the second main surface.
US07786946B2	Hollow dielectric pipe polyrod antenna A waveguide including: a first section including a first surface, a second surface, an upper wall, and a lower wall facing the upper wall; and a second section extending from the second surface; wherein the first section includes an upper ridge on the upper wall of the first section and a lower ridge on the lower wall of the first section, wherein the second section includes an upper conductor extending from a top portion of the second surface and a lower conductor extending from a lower portion of the second surface with a gap between the upper and lower conductors, wherein the upper conductor is electrically connected to the upper ridge, wherein the lower conductor is electrically connected to the lower ridge, and wherein the upper and lower conductors are adapted to propagate a wave and reduce discontinuity of the wave a connection between the first and second sections.
US07786944B2	High frequency communication device on multilayered substrate A communication device (110, 210) has an antenna (150, 152, 250, 252) positioned on a multilayer substrate/printed circuit board (154, 254, 254′). A first high frequency material (116, 216) is disposed over a first side of the substrate (154, 254) characterized for low frequency devices. A conductive layer (118, 218) is patterned over the first high frequency material (116, 216), defining first and second circuit traces (122, 124, 222, 224) and first and second antenna traces (132, 134, 232, 234). The first and second antenna traces (132, 134, 232, 234) define a first slot (116, 216) in the first conductive layer (122, 222), which is aligned with a cutout (162, 262) defined by the substrate (154, 254). One of a transmitter (112, 212) and a receiver (114, 214) are disposed over the high frequency material (116, 216) and coupled to the edge emitting antenna (150, 250) by the first and second circuit traces (122, 124, 222, 224). The other of the transmitter (112) and receiver (114) may be positioned on the same or opposed side (aligned or staggered) of the substrate (254) in a similar manner. One or more layers (262), which may be patterned to provide resonant features, are formed between the substrate (254, 254′) for isolation.
US07786943B2	Antenna device and radio communication system An antenna device includes: a substrate; first and a second antenna units which are wound coaxially on a surface of the substrate, and include a plurality of antenna elements; and a feeder which feeds power only to the first antenna unit. A separation distance between the antenna elements in each of the first and second antenna units is substantially the same.
US07786938B2	Antenna, component and methods An antenna component (and antenna) with a dielectric substrate and a plurality of radiating antenna elements on the surface of the substrate. In one embodiment, the plurality comprises two (2) elements, each of them covering one of the opposite heads and part of the upper surface of the device. The upper surface between the elements comprises a slot. The lower edge of one of the antenna elements is galvanically coupled to the antenna feed conductor on a circuit board, and at another point to the ground plane, while the lower edge of the opposite antenna element, or the parasitic element, is galvanically coupled only to the ground plane. The parasitic element obtains its feed through the electromagnetic coupling over the slot, and both elements resonate at the operating frequency. Omni-directionality is also achieved. Losses associated with the substrate are low due to the simple field image in the substrate.
US07786936B2	Position information detection system and position information detection method An object of the present invention is to achieve a position information detection system with high precision when an obstruction and a reflective object exist. A position information detection system includes a reader/writer whose position is known, a first RF chip whose position is known, and a second RF chip attached to an object to be detected; and calculates a distance between the reader/writer and the second RF chip from a first calculated distance between the reader/writer and the first RF chip, which is calculated from a signal intensity of a communication signal transmitted from the reader/writer, detected by the first RF chip, a second calculated distance between the second RF chip and the reader/writer, which is calculated from a signal intensity of a communication signal transmitted from the reader/writer, detected by the second RF chip, and a distance between the reader/writer and the first RF chip.
US07786934B2	Apparatus and method for removing interference in transmitting end of multi-antenna system An apparatus and method for removing interference in a transmitting end of a multi-antenna system are provided. The method includes receiving channel information for all Receive (Rx) antennas; calculating a beam-forming matrix that maximizes a Signal-to-Interference plus Noise Ratio (SINR) for each Rx antenna by using the received channel information; calculating an integer value which is in proportion to an interference signal for each Rx antenna by using the received channel information and the calculated beam-forming matrix, and performing Dirty Paper Coding (DPC) on a Transmit (Tx) signal by using the calculated integer value; and performing beam-forming by multiplying the Tx signal that has undergone the DPC by the calculated beam-forming matrix. Accordingly, a highest data rate for each user and a highest diversity can be obtained.
US07786932B2	Time-to-first-fix for position determination An improved time-to-first-fix (TTFF) for GPS systems is provided through a comparison of the time-of-week (TOW) to the sub-frame identification (ID). In one embodiment, this comparison comprises dividing the TOW to form a ratio and performing a modulus operation on the ratio to form a remainder, which is then incremented. If the incremented remainder equals the sub-frame ID, the TOW is assumed to be valid, thereby providing a time of transmission. The time of transmission may then be used to calculate pseudoranges and determine a receiver's location.
US07786930B2	Global positioning system log with low power consumption A global positioning system (GPS) log with low power consumption has an antenna, a GPS module, a power control module, a main control module, a power adjusting unit and a memory. The main control module is connected to the GPS module and the power control module to retrieve the computing results of the GPS module and controls the power control module to periodically provide power to the GPS module according to a predetermined and variable power providing period. The power adjusting unit is connected to the main control module, analyzes the computing results of the GPS module and assists the main control module to adjust the power providing period. Since the main control module automatically adjusts the power providing period, the GPS log does not deplete unnecessary power on the GPS module. Therefore, the power consumption of the GPS log is reduced and the GPS operates longer.
US07786929B2	Method and device for predicting GNSS satellite trajectory extension data used in mobile apparatus A method and device for predicting satellite trajectory extension data used in a mobile apparatus. The device in accordance with the present invention comprises an I/O interface and a microprocessor. The input/output (I/O) interface is used for obtaining at least one satellite navigation message for a satellite. The microprocessor is used for determining a propagating condition according to the satellite navigation message, estimating a plurality of parameters of a satellite trajectory prediction model according to the propagating condition, and propagating a set of satellite trajectory extension data by using the satellite trajectory prediction model.
US07786927B2	Radar, radio frequency sensor, and radar detection method In a sensor and a radar for measuring the distance and the moving speed of a target by radiating a radio frequency, particularly a millimeter wave, compatibility between cost reduction and high detection performance has been conventionally a significant problem. In the present invention, the frequency of a transmitted signal changes during a fixed time while performing digitally-frequency-modulation on frequency sweeping straight lines extending, with different slopes relative to the time axis, from plural slightly different initial values serving as starting points, the signal is transmitted after being modulated so as to periodically repeat the sweep time serving as a unit, signal components corresponding to the respective sweeping slopes are digitally sampled, in synchronization with the transmitted modulation signal, from a received signal which is reflected and returned from a target, and the received signal is analyzed.
US07786925B1	Determination of the outline of an elevated object A method and apparatus determines the shape of an orbiting or airborne object. A radar determines the general location and a telescope is directed toward the object to form an image of background stars, which will be occluded by the object. The image is compared with a memorized star map, to identify the region of the image in the map. Stars visible in the map which are not visible in the image are listed. The invisible stars are paired with next adjacent visible stars to form star pairs. The midpoints are identified of lines extending between star pairs. Segment lines are drawn between a midpoint and the next closest midpoint. The segment lines define an outline of the object.
US07786923B2	Interrogator of communication system An interrogator that is to be incorporated in a communication system in which each of at least one transponder is operable, upon reception of a main carrier wave transmitted from the interrogator, to respond to the interrogator with a reflected wave that is generated by modulating the main carrier wave. The interrogator includes: (a) a transmitting portion operable to transmit the main carrier wave; (b) a receiving portion operable to receive the reflected wave as a received signal; (c) at least one first frequency-converter each operable to generate an intermediate frequency signal, by multiplying the received signal with a first local signal that is generated by a first local oscillator; (d) at least one second frequency-converter each operable to generate a demodulated signal, by multiplying the intermediate frequency signal or a converted signal converted from the intermediate frequency signal, with a second local signal that is generated by a second local oscillator; and (d) a phase controller operable to control phase of the second local signal.
US07786921B2	Data processing method, data processing apparatus, semiconductor device, and electronic apparatus In a solid-state imaging device with an AD converter mounted on the same chip, to enable an efficient product-sum operation while reducing the size of the circuit scale and the number of transmission signal lines. A pixel signal during an n-row readout period is compared with a reference signal for digitizing this pixel signal, and a counting operation is performed in one of a down-counting mode and an up-counting mode while the comparison processing is being performed, and then, the count value when the comparison processing is finished is stored. Subsequently, by using the n-row counting result as the initial value, a pixel signal during an (n+1)-row readout period is compared with the reference signal for digitizing this pixel signal, and also, the counting operation is performed in one of the down-counting mode and the up-counting mode, and then, the count value when the comparison processing is finished is stored. If the count mode for the n+1 row is set to be opposite to the count mode for the n row, the count value obtained by the counting operation for the n+1 row is a subtraction result. If the count modes for the n+1 row and the n row are set to be the same, the count value obtained by the counting operation for the n+1 row is an addition result.
US07786920B2	Method and device for controlling a successive approximation register analog to digital converter A method for controlling a successive approximation register analog to digital converter comprising connecting a first side of a capacitor to a first comparator input, during a sampling phase connecting the first side of a capacitor to an input and connecting a second side of the capacitor to a mid-voltage, following the sampling phase disconnecting the first side of the capacitor from the input and disconnecting the second side of the capacitor from the mid-voltage and autozeroing the comparator.
US07786917B2	Digital-to-analog converter A digital-to-analog converter is disclosed for converting a digital signal into its analog equivalent. The digital-to-analog converter includes a two switches capable of coupling circuit nodes to ground, a scaling capacitor having a capacitance value that equals a unit capacitance value, a first array of capacitors coupled to the first circuit node and a first switching array which couples the first array of capacitors to either ground or a reference voltage depending on the digital values of the least significant bits of the digital word being converted, a second array of capacitors coupled to the second circuit node and a second switching array which couples the second array of capacitors to either ground or the reference voltage depending on the digital values of the most significant bits of the digital word being converted.
US07786911B2	Resettable high order delta-sigma analog to digital converter A high-order delta-sigma analog-to-digital converter. A plurality of stages are connected to accept an analog input signal and produce a digital output signal. Each stage has a resettable Δ-Σ converter of second order or higher. Resetting each stage before accepting a new input purges the integrators of any information related to the previous input, allowing step inputs to the system. The stability of the converter is ensured using local feedback loops at each stage. Each stage provides a digital representation of a portion of the analog input signal. A decimation filter receives the digital signals from the stages and arranges them into the digital output signal.
US07786905B2	Modulation coding and decoding Methods and apparatus are provided for partitioning a stream of binary input data into two binary output streams for supply to respective modulation encoders in a modulation coding system. A 4-ary enumerative encoding algorithm is applied to each of a succession of input words in the input bit-stream to produce a succession of 4-ary output symbols from the input word. The 4-ary algorithm simultaneously encodes respective j=∞ Fibonacci codes in the odd and even interleaves of the input word such that the two bit-sequences formed by respective corresponding bits of the succession of output symbols are range-limited codewords. The two binary output streams are then produced by separating the two range-limited codewords generated from each successive input word. The binary output streams can then be independently encoded by respective modulation encoders, and the encoder outputs interleaved to produce a modulation-constrained output stream. Corresponding decoding systems are also provided.
US07786904B1	Voltage level digital system A digital system programmed to accept words wherein each of said words is a collection of “bit” voltage values with each bit value represented by its position in the word and the value of a base raised to a power, said base multiplied by an integer, m.
US07786902B1	Circuits, architectures, systems, methods, algorithms and software for conditional modulation coding Methods, algorithms, software, circuits, architectures, and systems for conditionally encoding information and processing conditionally encoded information. The present invention takes advantage of codes where most randomly selected data units fulfill the coding constraints. Thus, only those data units that need encoding (i.e., that do not fulfill coding constraints) are encoded, and those data units that do not need encoding (i.e., that fulfill coding constraints) are not encoded. By doing so, one may increase the density, bandwidth and/or gain of data communications, increase the error checking and/or correcting capabilities of a data communications system, and/or reduce interference in a multi-user system.
US07786901B2	Key press registration in an electronic device with moveable housings A method for key press registration in an electronic device uses a first key press debounce limit (233) if a first housing of the electronic device has not moved relative to a second housing of the electronic device and a second key press debounce limit (236) if the first housing has moved relative to the second housing. In one implementation, the second debounce limit is at least twice the first debounce limit. By using different debounce limits based on whether housing movement has recently been detected, the electronic device reduces the effect of an inadvertent key press made while opening or closing the electronic device.
US07786896B2	Parking assistance system and parking assistance method A parking assistance system for outputting parking instructions to the driver of a vehicle has a sensor device which is designed for performing a parking space measurement on the basis of parking space limits and generating parking space information on the basis of the parking space measurement; a program-controlled device which calculates the driving trajectory to be traveled on the basis of the parking space information generated and calculates a time to collision and/or a distance to collision, within which the vehicle will presumably collide with one of the parking space limits, from the parking space information generated and the calculated driving trajectory; and a warning signal transducer which generates a warning signal if the calculated period of time is less than a first limit value and/or the calculated distance to collision is less than a second limit value.
US07786895B2	Multi-user motor vehicle telemetric system and method A multi-user vehicle telemetric system comprises vehicle interface units (VIUs), wireless gateways, and one or more central hosts. The VIU in a vehicle collects data over the OBD-II bus and stores the data in the form of DataPoint Records (DPRs) in an on-board non-volatile (e.g. flash) memory. When the VIU is within wireless range of a gateway, it establishes a WiFi (802.11b) connection with the gateway, and submits stored DPRs to the gateway, to be stored in permanent storage at the gateway. Although the DPRs are stored in permanent storage on the gateway, they are deleted from permanent storage on the gateway after they are successfully uploaded to the central hosts. The gateways are shared, and communicate with the central hosts over a wide area network (WAN). When a gateway has gathered new DPRs from a VIU, it submits these to selected central hosts. The central hosts collect vehicle data for a plurality of users, each user being assigned a central host exclusively, or sharing a central host with other users. Each of the VIUs may be exclusively accessed by a single user or a number of users, and the shared gateways forward DPRs from a VIU only to the central hosts of the users which are authorized to access the VIU.
US07786894B2	Methods, apparatus, and systems for monitoring transmission systems A sensing platform for monitoring a transmission system, and method therefor, may include a sensor that senses one or more conditions relating to a condition of the transmission system and/or the condition of an environment around the transmission system. A control system operatively associated with the sensor produces output data based on an output signal produced by the sensor. A transmitter operatively associated with the control system transmits the output data from the control system.
US07786892B2	Method for interpretation of a radio-electrical command A method for the interpretation of a radio-lectrical command for equipment in which the command is interpreted as a function of the emission zone is provided. This is achieved whereby the electromagnetic characteristics of the field generated by the radio-electrical command in the vicinity of a device for reception of radio-electrical commands are determined. The characteristics are compared to determine if the point of the radio-electrical command is located in a near-field or in a far-field zone. A command is then carried out as a function of the command received and as a function of the emission zone of the command. This permits the same command to have two meaning for the equipment.
US07786891B2	System and method for an interactive security system for a home A system and method for displaying video in a residence. An indication of an alert is received as communicated from a security system of a residence. The indication of the alert is communicated to a cellular telephone. A selection of a television communicated from the cellular telephone is received. The television is selected from multiple televisions located within the residence. A command is communicated to display one or more images on the selected televisions.
US07786888B2	False ceiling fire detector assembly A mounting apparatus usable with ambient condition detectors includes first and second mounting bases spaced apart axially along a common center line. Respective detectors can be coupled to the bases as required in a specific installation.
US07786882B2	Occupant-detecting apparatus An occupant-detecting apparatus includes a plurality of load sensors configured to detect a load imparted on a vehicle seat, and an occupant-sitting determination device configured to determine whether or not an occupant is seated on the vehicle seat, based on detected result of the load sensors. The load sensors are configured to detect loads at different positions on the vehicle seat, and the occupant-sitting determination device is configured not to perform occupant-sitting determination if an absolute value (ΔW) of a variable amount in a sum of detected result of the load sensors is lesser than a predetermined threshold value (TH/L).
US07786881B2	Content status provision related to volatile memories The present invention relates to a method, a content status information providing unit (100), a portable electronic device (114), a computer program product (50) and a computer program element for providing status information related to at least one data content file, within a portable electronic device (114), to a user, the method comprising the steps of obtaining a battery capacity value (step 206), obtaining content related information for at least one data content file (steps 214, 216), determining a content status of the' at least one data content file, in dependence of the obtained battery capacity related to the at least one data content file (steps 222, 226, 233, 234), and providing information on the determined content status to the user (step 224), such that the user of the portable electronic device (114) can be made aware of the status of the at least one data content file.
US07786878B2	Advanced transmitter isolation feature A signal representative of a pressure is received from an industrial transmitter. An isolation indicator signal may be obtained by control signals from an isolation valve assembly or by signals from a DCS to indicate that isolation has occurred.
US07786874B2	Methods for refining patient, staff and visitor profiles used in monitoring quality and performance at a healthcare facility Methods, systems and computer program products are used in monitoring patients, staff, assets and visitors at a facility, initiating a response to prevent or mitigate harm, and assess and ensure overall quality and performance, and refine individual patient, staff and visitor profiles. A plurality of sensors throughout the facility provide multiple data streams relating to the locations of patients relative to at least one of caregivers, assets, other patients, visitors or one or more fixed locations. A computer system analyses the data stream and determines the location and/or movements of the patients relative to the caregivers, assets, other patients, visitors and/or fixed locations. A profile containing individual data for the patient is used to accurately detect events, including actionable events, ensure completion of prescribed care, assess patient wellness, and, in some cases, provide tailored patient specific responses to detected events. Patient profiles are periodically refined by means of an information feedback loop in order to more accurately predict (actionable) events, provide adequate care and ensure a desired level of patient wellness. Staff and visitor profiles can be used to measure staff and visitor performance at a facility.
US07786867B2	Remotely powered and remotely interrogated wireless digital sensor telemetry system An electronic system includes a reader and a remotely powered and remotely interrogated sensor transponder. The sensor transponder includes a reader and a remotely powered and remotely interrogated sensor transponder. The sensor transponder includes a sensor and a radiation receiving device. Data from the sensor is conditioned to provide sensor data ratiometric with magnitude of excitation voltage provided by the radiation receiving device.
US07786865B2	RFID reader and range indicating method for the RFID reader An RFID reader and range indicating method for the RFID reader is provided. The RFID reader includes an RF antenna for communicating with one or more than one tag using RF signals, a module for operating on the tag, a module for analyzing a range of the RFID reader; and a module for indicating, based on the analysis, a potential area where the RFID reader is capable of implementing the operation on the tag.
US07786863B2	Information processing and wireless communication device wherein the resonant frequency of an antenna circuit is regularly corrected regardless of temperature An information processing device of the invention has an antenna circuit, and a reader/writer device provided with a received signal generating circuit, a microcomputer, a transmitted signal generating circuit, a level detecting circuit, and a D/A converter. The received signal generating circuit is connected to the microcomputer and the antenna circuit, the transmitted signal generating circuit is connected to the microcomputer and the antenna circuit, the D/A converter is connected to the microcomputer and the antenna circuit, the level detecting circuit is connected to the microcomputer and the antenna circuit, and the antenna circuit has an antenna, a resonant capacitor, and a variable capacitor.
US07786861B2	Detecting theft and disabling stolen equipment Some implementations of the present invention provide methods and devices for detecting the theft of, and disabling, electronic devices such as computers and network devices. The devices may be disabled when a signal is not detected, e.g., for a predetermined period of time. For example, a radio frequency (“RF”) signal (e.g., a beacon), an Internet Protocol (“IP”) signal or the like may define a space within which the devices may be operated with complete functionality. Outside this space, the devices will be disabled, at least to some degree. The degree of disablement may depend on the length of time since the signal was last detected. Alternatively, the devices may be disabled when a signal is detected: some such implementations define “portals,” “choke points” or the like past which a device may not be transported without some degree of disablement.
US07786860B1	Open and covert detection mechanisms for materials at locations of interest An optical receiving and data communications system for sensing materials of interest (e.g., drugs and/or explosives) in transportation systems such as buses, trucks, cars, trains, aircraft, and ships, and checkpoints such as building entrances, roadblocks, passenger boarding areas, and the like. The system can be included in the transportation system, and includes a fiber optic frontend that focuses and/or concentrates light reflected from a target into the fiber filament for communication to an optical sensor. When the target is illuminated at a predetermined wavelength, a vapor plume and/or particulate matter associated therewith is energized such that change information is caused to occur and be received into the fiber system. The change information is communicated over a fiber communications network to a remote processing and analysis system for processing and analysis to determine its chemical components.
US07786859B2	Locator apparatus and method using that apparatus An apparatus to locate an article is disclosed. The apparatus comprises a host device comprising a transmitter, and a client device attached to the article. The client device comprises a client controller, a receiver interconnected with the client controller, a battery interconnected with both the client controller and the receiver. The controller and the receiver alternate between an inactive mode and an active mode.
US07786858B2	Video-enabled rapid response system and method A video-enabled rapid response system and method that integrates identification technology and tracking technology in order to rapidly alert the most appropriate person to an incident. Such an approach includes a strong identification mechanism to get a positive identification on a person and a weak identification mechanism to maintain location information for the person moving in a facility. The system can rapidly determine the closest person with skills and or authority to respond when an incident occurs at a particular location and then pass an alert to them via a paging mechanism. The system combines strong and weak identification mechanism in order to provide accurate subject identification and tracking over the large facility.
US07786857B2	Path tracking system, terminal device, fixed communication device, and path management device A shopping path tracking system is disclosed that comprises a terminal device, a fixed communication device, and a path management device. The fixed communication device wirelessly communicates with the terminal device, calculates a response time of the terminal device, and reports the calculated response time to the path management device. The path management device detects a position of the terminal device based on the response time reported from the fixed communication device, stores the detected position, and detects a travel path of the terminal device by tracking the stored positions.
US07786856B2	Exercise monitor A device for measuring the aerobic capacity of a subject, has an input for receiving a measurement of distance travelled in a given time. The time is chosen to be sufficiently large to ensure that the user is working at the maximum of his or her aerobic capacity. A processor determines from the values of distance and time an aerobic capacity, and a measure of exercise level is output to the user based on the calculated aerobic capacity. The calculated aerobic capacity conforms to the relationship expressed as V02max=a+bx+c(x^2) wherein V02max is the maximal oxygen consumption of a user; a, b and c are non-zero constants, and x is a measure of distance per unit time.
US07786853B2	Method for transmitting data from at least one sensor to a control device A method for transmitting data from at least one sensor to a control unit is described, a value range, which is available for encoding the data to be transmitted, being divided into three portions. The first portion is used for the sensor values. The second portion is used for status signals and error signals, and the third portion is used for sensor identification data, the three portions being separated from one another and following in succession.
US07786852B2	Method and system for preventing leaving a child in an unattended vehicle A method is provided that includes determining whether a fastener of a child seat is fastened, determining whether a person is seated in a vehicle seat, and if it is determined that the fastener is fastened and the person is not seated in the vehicle seat: enabling a first notification signal of the alarm system, enabling a delay of the alarm system for a period of time, enabling a second notification signal of the alarm system if a door of the vehicle is locked within the period of time, and enabling the second notification signal after expiration of the period of time. If it is determined that the fastener is not fastened or the person is seated in the vehicle seat, the method includes resetting the alarm system.
US07786850B1	Method and apparatus for bridge collision alert monitoring and impact analysis This is a method and apparatus for bridge collision alert and monitoring impact analysis, which allows users of the method and apparatus to continuously monitor the integrity of a bridge as well as to detect insult or impact to the bridge structure or both as well as viewing purposes as for forensic purposes. The system is comprised of a series of monitors that gather different pieces of date and integrate that data into a system for view by the operator.
US07786849B2	Trailer detection system A proximity sensor system for a vehicle includes a first remote sensor that senses objects in a rearward area relative to the vehicle. A trailer detection module determines that one of the objects is a trailer that is attached to the vehicle based on a repeating pattern of signals from the first remote sensor. A response module selectively responds to the objects other than the trailer based on the objects outside of a predetermined distance threshold. An indicator responds to response module signals.
US07786848B2	Vehicle security systems A complementary security system for installation, at least in part in a vehicle, has an Original Equipment Manufacturer (OEM) security system installed therein. The complementary security system for communicating an alarm condition beyond the communication range of the OEM security system. The complementary security system comprising: a control module for receiving a trigger signal being indicative of the alarm condition detected by the OEM security system; a communication module for transmitting by Radio Frequency (RF) an alert signal upon receipt of the trigger signal by the control module; and a remote transmitter for alerting a user upon receipt of the alert signal. The remote transmitter being located beyond the communication range of the OEM security system. A corresponding method is also described.
US07786847B2	Radio frequency identification device An RFID device includes an analog block configured to receive a radio frequency signal so as to output an operation command signal, a digital block configured to output an address, a temperature address, an operation control signal, and a temperature sensor activation signal in response to the operation command signal received from the analog block and to provide a corresponding response signal into the analog block. The device further includes a memory block configured to receive the address, the temperature address, and the operation control signal so as to generate an internal control signal for controlling the internal operation, and to read/write data in a cell array including a non-volatile ferroelectric capacitor in response to the internal control signal, and a temperature sensor processing unit configured to detect a temperature change state of an RFID tag in response to the temperature sensor activation signal.
US07786846B2	Communication station for inventorizing transponders by means of selectable memory areas of the transponders A communication station (1) and a transponder (2) are designed in such a way that an inventorizing operation can be performed using various memory areas (36, 37, 38, 39, 40), which are provided in an addressable memory (35) of the transponder (2), and in which different identification data (UIDDATA, USERDATA) is stored.
US07786845B2	Method and apparatus for wireless communication of identification information between radio frequency devices Identification information is wirelessly communicated between radio frequency devices. In one embodiment, a first wireless device transmits a signal to request identification information. Other wireless devices are each affixed a respective item, and each of the other wireless devices determines if a reply signal is to be transmitted, and if so, communicates the reply signal to the first wireless device.
US07786841B2	Fuse cutout assembly A fuse cutout assembly having enhanced safety features to aid in both removal and replacement of fuse tubes. The inventive assembly can be produced by making modifications to standard fuse cutout assemblies. The modifications include lengthening the trunnions of the lower contact assembly and adding reflectors as a further visual aid for positioning the lower contact portion of the fuse tube within the trunnion sockets. Additionally, a molded plastic guide placed proximate the lower contact area of the fuseholder of the cutout promotes “self guiding” of the fuseholder during replacement. Also, the pull ring is modified by the addition of protruding arcuate sections extending from a standard pull ring, the sections allowing the technician to engage the pull down ring without aiming the hook stick through the ring. Additional reflectors are strategically placed to facilitate replacement of the fuseholder.
US07786840B2	Optimal packaging geometries of single and multi-layer windings The present invention is an optimized geometry for stacking multiple windings, where each winding multiple-turn coil having both a start lead and a finish lead on a perimeter of the coil. The start lead of each winding of the stack is indexed respective of adjacent windings of the stack.
US07786838B2	Wire wound electronic part A wire wound electronic part includes a ferrite core comprising ferrite having a columnar wire wound core and flanges formed at both ends thereof, a coil conductor wound around the wire wound core of the ferrite core, and at least a pair of terminal electrodes having a Cu conduction layer disposed to the outer surface of the flange, in which both ends of the coil conductor wound around the wire wound core are conductively connected to the terminal electrodes. The terminal electrode is formed by coating an electrode paste containing a Cu powder and a glass frit to the outer surface of the ferrite core, and then applying a heat treatment to the ferrite core. There is a reaction layer of a portion of the ferrite core and the glass frit at a boundary between the ferrite core and the Cu conduction layer. The terminal electrodes has the peel strength identical with that of an existent Ag terminal electrode, without forming a plate layer.
US07786837B2	Semiconductor power device having a stacked discrete inductor structure A power device includes a discrete inductor having contacts formed on a first surface of the discrete inductor and at least one semiconductor component mounted on the first surface of the discrete inductor and coupled to the contacts. The discrete inductor further includes contacts formed on a second surface opposite the first surface and routing connections connecting the first surface contacts to corresponding second surface contacts. The semiconductor components may be flip chip mounted onto the discrete inductor contacts or wire bonded thereto.
US07786830B2	Switch with movable portion A switch includes a movable portion, a first electrode and a second electrode. The movable portion is provided on a substrate and moves with respect to the substrate. The first electrode is provided on the movable portion. The second electrode is able to contact with the first electrode and is fixed to the substrate. f×Ro×C≦1.6×10−4 when an operation frequency is represented as “f” (Hz), a transmission impedance is represented as “Ro” (Ω), and a capacitance in “OFF” state between the first electrode and the second electrode is represented as “C” (F).
US07786826B2	Apparatus with acoustically coupled BAW resonators and a method for matching impedances An apparatus includes a first bulk acoustic wave (BAW) device including a first impedance and a second BAW device including a second impedance, wherein the first and second impedances are different and the first and second BAW devices are acoustically coupled.
US07786824B2	Multilayer filter A multilayer filter has a capacitor element body, at least two signal terminal electrodes, and at least one grounding terminal electrode. The capacitor element body has a plurality of laminated insulator layers, a first signal internal electrode and a grounding internal electrode arranged to be opposed to each other with at least one insulator layer out of the plurality of insulator layers in between, and a second signal internal electrode arranged to be opposed to either one internal electrode of the first signal internal electrode and the grounding internal electrode with at least one insulator layer out of the plurality of insulator layers in between. The second signal internal electrode is connected to the at least two signal terminal electrodes. The first signal internal electrode is connected through a through-hole conductor to only the second signal internal electrode. The grounding internal electrode is connected to the at least one grounding terminal electrode.
US07786822B2	Four-state digital attenuator having two-bit control interface A four-state digital attenuator for an RF signal includes a first external terminal adapted to receive a first control voltage; a second external terminal adapted to receive a second control voltage, and a third external terminal connected to a fixed supply voltage. The four-state digital attenuator receives no supply voltages other than the control voltages and the fixed supply voltage connected to the third external terminal. A plurality of series paths are provided from an RF input to an RF output, each of the series paths passing through a node. A plurality of shunt paths are provided from the node to the third external terminal. A driver selectively enables the series paths and shunt paths in response to the first and second control voltages to provide four attenuation levels for an RF signal from the RF input to the RF output.
US07786820B2	Tunable dielectric radio frequency microelectromechanical system capacitive switch The invention is a tunable RF MEMS switch developed with a BST dielectric at the contact interface. BST has a very high dielectric constant (>300) making it very appealing for RF MEMS capacitive switches. The tunable dielectric constant of BST provides a possibility of making linearly tunable MEMS capacitive switches. The capacitive tunable RF MEMS switch with a BST dielectric is disclosed showing its characterization and properties up to 40 GHz.
US07786816B2	Phase controlled oscillator circuit with input signal coupler An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input signal may be generated in a pulse generator to have an input pulse duration less than or equal to that of the oscillating signal. The oscillator circuit may be used as a filter to filter pulse width variations or to filter jitter from a reference clock. The oscillator circuit may also serve as a buffer by amplifying the input signal. Phase interpolation can be obtained by coupling at least one input signal with at least one oscillating signal.
US07786815B2	Apparatus and method for generation of noise signal An apparatus and method for generation of a noise signal are provided. The apparatus includes a noise synthesizing module and a noise signal transfer module. The noise synthesizing module includes a voltage controlled oscillator, a phase frequency detector, a phase locked loop filter, and a reference generator which form a phase locked loop. An output signal of the reference generator is provided to a first phase-frequency input of the phase-frequency detector, and an output signal of the voltage controlled oscillator is provided to a second input of the phase-frequency detector. An output signal of the phase-frequency detector is provided to an input of the phase locked loop filter, and an output of the phase locked loop filter is provided to a frequency control input of the voltage controlled oscillator. The noise signal transfer module includes a sinusoidal generator and a frequency mixer having a first input which is provided with an output signal of the phase frequency detector and a second input which is provided with an output signal of the sinusoidal.
US07786814B2	Method and apparatus for deriving an integrated circuit (IC) clock with a frequency offset from an IC system clock Generally, methods and apparatus are provided for deriving an integrated circuit (IC) clock signal with a frequency that is offset from the IC system clock. An offset clock having a frequency that is offset from a system clock is generated by configuring a ring oscillator in a first mode to generate the system clock having a desired frequency; and adjusting the configuration of the ring oscillator in a second mode to generate the offset clock having the frequency that is offset from the system clock. The configuration of the ring oscillator is adjusted in the second mode by adjusting (i) a power supply value applied to the ring oscillator in the second mode relative to a power supply value applied in the first mode; or (ii) a number of delay line elements that are active in the ring oscillator loop.
US07786813B2	Interleaved voltage controlled oscillator An interleaved voltage-controlled oscillator (VCO) is disclosed. The VCO includes a ring circuit comprising a series connection of main logic inverter gates, a plurality of delay elements connected in parallel with a selected sequence of the main logic inverter gates, at least one temperature compensation circuit comprising a logic inverter gate in series connection with one or more field effect transistors, the field effect transistor responsive to a compensating voltage input that is proportional to temperature, and an electronic circuit in signal communication with the at least one temperature compensation circuit and configured to provide a voltage signal responsive to temperature. Each delay element includes a feedforward section, comprising controls for regulating signal transmission through feedforward elements responsive to one or more control voltages, and a proportional section, comprising controls for regulating signal transmission through at least one logic inverter gate.
US07786812B2	Oscillators having reactance-adjustable frequency control In various embodiments, the invention provides a frequency controller to control and provide a stable resonant frequency of a clock generator and/or a timing and frequency reference. Such stability is provided over variations in a selected parameter such as temperature and fabrication process variations. The various apparatus embodiments include a sensor adapted to provide a signal in response to at least one parameter of a plurality of parameters; and a frequency controller adapted to modify the resonant frequency in response to the second signal. In exemplary embodiments, the sensor is implemented as a current source responsive to temperature fluctuations, and the frequency controller is implemented as a plurality of controlled reactance modules which are selectively couplable to the resonator or to one or more control voltages. The controlled reactance modules may include fixed or variable capacitances or inductances, and may be binary weighted. Arrays of resistive modules are also provided, to generate one or more control voltages.
US07786810B2	Phase locked loop with leakage current calibration A phase locked loop with a current leakage adjustment function is provided. The phase locked loop includes a phase locked loop unit having a compensation voltage node, a digitalized leakage-detection circuit generating a plurality of digital control signals based upon the phase error between a reference clock signal and a feedback signal, and a compensation circuit generating a compensation current based upon the plurality of digital control signals. When there exist current leakages of the MOS capacitors, the current leakage adjustment circuits provided by the present invention may prevent the conventional phase locked loop from un-locking due to jittering.
US07786809B1	Method of low power PLL for low jitter demanding applications A system that includes a phase locked loop and an activation circuit; wherein the phase locked loop includes an oscillator, a frequency divider, a phase detector, a control circuit, and a memory circuit. The activation circuit is adapted to activate the memory circuit and the oscillator; to deactivate the frequency divider, the phase detector and the control circuit during deactivation periods and to activate the frequency divider, the phase detector and the control circuit during activation periods. The timing relationship between a deactivation period and an activation period is responsive to an output signal jitter limitation and to a power consumption limitation.
US07786805B2	Power amplifier module and a time division multiple access radio A power amplifier module comprises a power amplifier circuit having an output power level controlled by a power supply voltage. A power supply transistor controls the power supply to the power amplifier circuit from a drive signal which is received from a drive circuit. The drive circuit generates the drive signal in response to a power level input signal, which specifically may correspond to a power ramping for a GSM cellular communication system. The power amplifier module furthermore comprises a detection circuit which determines an operating characteristic of the power supply transistor. The operating characteristic is preferably a saturation characteristic. A control circuit controls the drive signal in response to the operating characteristic. The control circuit preferably controls the drive signal such that the power supply transistor does not enter the linear region for a Field Effect Transistor and the saturated region for a bipolar transistor.
US07786803B2	Operational transconductance amplifier (OTA) Apparatus and methods provide an operational transconductance amplifier (OTA) with one or more self-biased cascode current mirrors. Applicable topologies include a current-mirror OTA and a folded-cascode OTA. In one embodiment, the self-biasing cascode current mirror is an optional aspect of the folded-cascode OTA. The self-biasing can advantageous reduce the number of biasing circuits used, which can save chip area and cost. One embodiment includes an input differential pair of a current-mirror OTA.
US07786799B2	Trimming technique for high voltage amplifiers using floating low voltage structures The system contains a first MOS transistor having a first source element, a first drain element, and a first gate element. A first low voltage current source has two ends. The ends of the low voltage current source are connected to at least two of the first MOS transistor elements. At least one first Zener clamp is in parallel with the low voltage current source.
US07786798B2	Amplifying pulses of different duty cycles An amplifier stage capable of delivering a peak limited voltage pulse with sharp transitions, at a desired width and duty cycle, and with high efficiency is disclosed. One disclosed embodiment relates to a circuit that includes a tuned class D amplifier that receives an input signal and generates a pulsed RF output signal in response to the input signal. The pulsed RF output signal has a greater power than that of the input signal.
US07786797B2	Amplifying apparatus The amplifying apparatus includes an amplifier having a circuit constant determined so as to satisfy a condition for E-class operation; power detecting unit which detects an output electricity from the amplifier; and controlling unit which controls the circuit constant in accordance with the output power detected by the power detecting unit.
US07786796B2	Audio amplifier An audio amplifier including a differential mode integrator, a first comparator, a second comparator, a logic circuit and a driving unit is provided. The differential mode integrator receives a differential input signal and a differential output signal and outputs a differential mode intermediate signal. The first comparator has a positive input terminal receiving a first terminal signal of the differential mode intermediate signal, a negative input terminal receiving a ramp signal, and generates a first signal. The second comparator has a positive input terminal receiving a ramp signal, a negative input terminal receiving a second terminal signal of the differential mode intermediate signal, and generates a second signal. The logic circuit performs a logic operation on the first and second signals to generate a third signal and a fourth signal. The driving unit generates a differential output signal to drive a load according to the third and fourth signals.
US07786794B2	Amplifier circuit An amplifier circuit is disclosed that includes a first input terminal; a second input terminal; a first differential amplifier circuit that samples signals input to the first and second input terminals and outputs signals obtained by applying a gain to the sampled input signals having different voltages; and a second differential amplifier circuit that supplies first and second reference voltages referred to when a sampling operation is performed in the first differential amplifier circuit to the first and second input terminals, respectively. A potential difference between the first and second reference voltages is equal to an offset voltage of the first differential amplifier circuit.
US07786788B2	Systems including level shifter having voltage distributor A level shifter includes a voltage distributor for receiving an input signal and respectively outputting a first signal and a second signal at a first node and a second node according to the input signal; and an output circuit coupled to the voltage distributor for generating an output signal according to the first signal and the second signal, wherein the voltage distributor includes: a first transistor having a first electrode, a second electrode coupled to the first node, and a first control electrode for receiving the input signal; a switch coupled between the first node and the second node for selectively establishing an electrical connection between the first and the second nodes; and a second transistor having a third electrode coupled to the second node, a fourth electrode, and a second control electrode coupled to the first node.
US07786785B2	Peaking control circuit There are provided a peaking detection part detecting a peaking amount in an output part of an inductor peaking circuit and a control signal generation part varying a circuit parameter of the inductor peaking circuit based on the peaking amount detected by the peaking detection part. Particularly, the inductor peaking circuit has inductors and resistors inserted in series between the output part and a power supply, and capacitances coupled in parallel between the output part and an earth (GND), and depending on respective values of these inductors, resistors and capacitances, it is possible to suppress a peaking generated in the output part.
US07786784B2	Variable delay circuit, variable delay device, and VCO circuit Herein disclosed is a variable delay circuit, including a first delay portion that delays an input signal; an output portion; and a variable impedance portion provided coupled between the first delay portion and an the output portion.
US07786782B2	Method and apparatus for counter-based clock signal adaptation A method and apparatus to implement clock signal adaptation is provided to characterize an input clock signal that is to be adapted and in response, generate adaptation updates at each subsequent clock cycle of the input clock signal. In a first embodiment, clock signal adaptation occurs through duty cycle correction (DCC) to substantially achieve a 50% duty cycle. In an alternate embodiment, clock signal adaptation occurs through a multiplication operation that is applied to the clock signal to be adapted, whereby the multiplication operation is parameterizable to allow odd/even multiplication. In an alternate embodiment, clock signal adaptation occurs through a phase-shift operation that is applied to the clock signal to be adapted, whereby the phase-shift operation is parameterizable to allow all possible fractions and percentages of phase shifts.
US07786780B2	Clock doubler circuit and method Apparatus for producing a signal, comprising a capacitor; a first current source for one of charging and discharging the capacitor over a first time period; a second current source for one of discharging and charging the capacitor over a first portion of a second time period; a detector for detecting when the voltage across the capacitor is substantially a first voltage and controlling the second current source for a second portion of the second time period to substantially maintain the voltage across the capacitor; and an apparatus output for indicating when the voltage across the capacitor is one of above and below the first voltage.
US07786779B2	Buffer for driving circuit and method thereof A buffer for a driving circuit includes a first transistor, a second transistor and a slew rate controlling circuit. The first transistor serves to provide a current to an output terminal. The second transistor serves to sink a current from the output terminal. The slew rate controlling circuit serves to control slew rate of at least one of the first transistor and the second transistor according to the input signal. The managing circuit serves to prevent the first transistor and the second transistor from turning on simultaneously.
US07786770B1	Reducing power consumption by disabling power-on reset circuits after power up Circuits and methods for reducing power consumption in an Integrated Circuit (IC) are provided. In one embodiment, a circuit includes a POR system control circuit, a POR latch and a control block circuit. The POR system control circuit generates a pulse during power up which is sent to the POR latch to set the state of the POR latch to a first logic state. The state of the POR latch is used to enable POR circuits during power up. The control block generates an output to disable POR circuits in the IC based on the state of the POR latch. After power-up, the state of the POR latch is set to a second logic state in order to disable the POR circuits resulting in power savings in the IC by eliminating static POR circuit current.
US07786767B2	Common-mode insensitive sampler An approach to rejecting input common-mode voltage variations in a sampler/converter that avoids the use of a differential amplifier in the signal path, and without introducing added distortion or noise. In one embodiment, the input common-mode variations are sensed on a pair of matched resistors that straddle the common mode analog inputs, on a node ‘Vcmi’. An alternative, switched-capacitor-based sensing scheme is also possible. Using this measured Vcmi, adjustments are then made to the rest of the sampler/converter to take out any variations observed at Vcmi.
US07786760B2	I/O buffer circuit An output buffer circuit is provided. The output buffer circuit receives a control signal (OE) and a data signal (Dout) from a first core circuit (10) and operates in a transmitting mode according to the control signal. The output buffer circuit converts the data signal into an output signal at a first voltage level or a ground voltage level according to the data signal logic level and a supply voltage (VDDIO). The supply voltage is adjusted to pull up or pull down the first voltage level of the output signal.
US07786757B2	Integrated circuits with hybrid planer hierarchical architecture and methods for interconnecting their resources Methods for interconnecting base, switching and interconnect resources for configurable integrated circuits are provided, where these methods include the following steps: interconnecting base and switching resources with interconnect resources to form a hierarchical interconnect structure; physically placing the hierarchical interconnect structure in a two dimensional format; and directly interconnecting selected neighboring base and switching resources. The integrated circuits generated include base resources, interconnect resources; and switching resources that are interconnected to form a hierarchical interconnect structure, and, additional interconnect resources that directly interconnect neighboring switching or base resources.
US07786755B2	Reducing errors in data by dynamically calibrating trigger point thresholds Methods, systems, computer readable media and means for reducing errors in data caused by noise are provided. In some embodiments of the present invention, circuitry of the device receives timing data from one or more other circuitries and identifies noiseless periods from the timing data. The circuitry then actively adjusts the trigger point threshold of data being transmitted to and/or from the circuitry only during the noiseless periods. The circuitry subsequently monitors the timing data to identify noise periods. In response to identifying a noise period, the device ceases to adjust the trigger point threshold until the noise period is over.
US07786753B2	Output driver circuit, semiconductor memory device including the output driver circuit, and method for operating the semiconductor memory device Output driver circuit, semiconductor memory device including the output driver circuit, and method for operating the semiconductor memory device, including a pre-driver to generate a pull-up control signal and a pull-down control signal according to a logic value of data to output, and to adjust and output a slew rate of the pull-up control signal and a slew rate of the pull-down control signal according to a termination resistance setting information, a pull-up driver to output logic high data in response to the pull-up control signal and a pull-down driver to output logic low data in response to the pull-down control signal.
US07786752B2	Memory systems, on-die termination (ODT) circuits, and method of ODT control According to one aspect, an on-die termination (ODT) circuit is controlled during transition from a first power mode to a second power mode of a memory device. The transition from an asynchronous ODT circuit path to a synchronous ODT circuit path is delayed to compensate for an operational latency of a delay locked loop (DLL) circuit.
US07786749B1	Programmable integrated circuit having built in test circuit A programmable integrated circuit has a plurality of logic elements with each logic element having a plurality of input leads and at least one output lead. The programmable integrated circuit further comprises a group of interconnect lines, and a first set of programmable circuits for electrically connecting the input and output leads of the plurality of logic elements to each other through the group of interconnect lines. The programmable integrated circuit further comprises a test circuit having at least one input and one output. Further the programmable integrated circuit comprises a second set of programmable circuits for electrically connecting the one output of the test circuit to the plurality of input leads of each of the plurality of logic elements and for electrically connecting the at least one output lead of each of the plurality of logic elements to the one input of the test circuit, through the group of interconnect lines.
US07786748B1	Method and apparatus for signal inversion in superconducting logic gates In one embodiment, the disclosure relates to a single-flux quantum logic gate capable of providing output from one of the two inputs, which is also known as the A and NOT B gate. The logic gate includes a first input gate and a second input gate for respectively receiving a first input pulse and a second input pulse. An output gate is wired in parallel with the first input gate. A first Josephson junction and a second Josephson junction are connected to the first input gate and the second input gate, respectively. A cross-coupled transformer is also provided. The cross-coupled transformer diverts the first pulse from the output gate if the second pulse is detected at the second input gate. In an optional embodiment, the first Josephson junction has a first critical current which is selected to be less than the critical current of the second Josephson junction.
US07786747B2	Microdisplay assemblies and methods of packaging microdisplays Microdisplay assemblies, methods of packaging microdisplays, and methods of testing microdisplays are disclosed. In accordance with one embodiment, a microdisplay assembly includes a support and a microdisplay disposed on the support. The microdisplay includes a semiconductor workpiece mounted to the support and an optical device region disposed over the semiconductor workpiece. A plurality of contacts is disposed over a portion of the semiconductor workpiece, wherein each of the plurality of contacts comprises a protruding feature.
US07786743B2	Probe tile for probing semiconductor wafer A tile used to hold one or more probes for testing a semiconductor wafer is disclosed. The tile has one or more sites for inserting one or more probes to test the semiconductor wafer. Each site has one or more holes. Each hole is coupled with a slot forming an angle. A probe is inserted into the tile from a top of the tile through the hole and seated on the slot. The probe has a probe tip. The probe top is in contact with the semiconductor wafer at one end of the slot at a bottom of the tile. The probe tip is aligned with an X and Y coordinate of a bond pad on the semiconductor wafer.
US07786738B2	Cancelling low frequency errors in MEMS systems Systems and methods are described below for cancelling low frequency errors in electronic systems including MEMS systems. The systems include a first circuit coupled to one or more switches. One or more bond wires are coupled to the switches and a second circuit. Control signals are coupled to the switches, and the control signals are configured to control coupling of the first circuit to the second circuit via the switch to cancel variable offsets introduced by the bond wire in an output of the first circuit.
US07786736B2	Method and system for detecting damage in aligned carbon nanotube fiber composites using networks Methods and structural defect detectors for detecting a structural defect in composites are presented. An exemplary method includes forming a nanocomposite including a plurality of nanotubes mechanically aligned in a principal direction within a polymer matrix. A voltage is applied to the nanocomposite and a resistance of the nanocomposite is measured using the applied voltage to detect the structural defect. An exemplary structural defect detector includes a nanocomposite including a plurality of mechanically aligned nanotubes within the polymer matrix, electrodes coupled to the nanocomposite, a voltage source for applying a voltage to the electrodes, and a resistance detector for measuring a resistance of the nanocomposite that allows identification of a structural defect. The plurality of nanotubes form a conducting percolating network of sensors.
US07786733B2	Apparatus and system for well placement and reservoir characterization A resistivity array having a modular design includes a transmitter module with at least one antenna, wherein the transmitter module has connectors on both ends adapted to connect with other downhole tools; and a receiver module with at least one antenna, wherein the transmitter module has connectors on both ends adapted to connect with other downhole tools; and wherein the transmitter module and the receiver module are spaced apart on a drill string and separated by at least one downhole tool. Each transmitter and receiver module may comprise at least one antenna coil with a magnetic moment orientation not limited to the tool longitudinal direction. A spacing between the transmitter and receiver module may be selected based on expected reservoir thickness.
US07786731B2	Dipole locator using multiple measurement points A receiver and tracking system for identifying a location of a magnetic field source. In a preferred embodiment a plurality of tri-axial antennas are positioned at three distinct points on a receiver frame. Each antenna detects a magnetic field from a source and a processor is used to determine a location of the source relative to the frame using the antenna signals. Each tri-axial antenna comprises three windings in each of three channels defined by a support structure. The windings each define an aperture area. The windings have substantially identical aperture areas and have a common center point. The receiver may to display to the operator the relative location of the field source or may direct the operator to a spot directly above the field source.
US07786718B2	Time measurement of periodic signals A system for measuring the time interval of a signal. The second signal has a frequency higher than a frequency of the first signal. According to one embodiment, the system includes an electronic circuit for determining an approximation of the time based on a period of the second signal and for determining an adjustment to the approximation based on the second signal and a third signal corresponding to the second signal and aligned with the first signal. The length of the adjustment is less than the period of the second signal.
US07786711B2	Auxiliary turn-on mechanisms for reducing conduction loss in body-diode of low side MOSFET of coupled-inductor DC-DC converter Conduction loss in the body-diode of a low side MOSFET of a power switching stage of one phase of a coupled-inductor, multi-phase DC-DC converter circuit, associated with current flow in the output inductor of that one phase that is induced by current flow in a mutually coupled output inductor of another phase, during normal switching of that other stage, is effectively prevented by applying auxiliary MOSFET turn-on signals, that coincide with the duration of the induced current, to that low side MOSFET, so that the induced current will flow through the turned-on low side MOSFET itself, thereby by-passing its body-diode.
US07786710B2	Electric power flow control An apparatus for reactive power compensation in an ac medium voltage power network. The apparatus includes a common connection; a first branch including a first switch, and a first capacitor; and a second branch including a second switch and a second capacitor.
US07786707B2	Oscillator circuit The invention provides an oscillator circuit that reduces the dependence of an oscillation frequency on a power supply voltage. When a first charging and discharging circuit completes its discharge, a terminal voltage of a first capacitor of the first charging and discharging circuit is initialized to a power supply voltage and simultaneously a second charging and discharging circuit starts its discharge. Then, when the second charging and discharging circuit completes its discharge, a terminal voltage of a second capacitor of the second charging and discharging circuit is initialized to the power supply voltage and simultaneously the first charging and discharging circuit starts its discharge. The first and second charging and discharging circuits alternately repeat the initialization and the discharge, and the discharge is always started from the power supply voltage.
US07786698B2	Charging a secondary battery A method of charging a battery includes applying a charging current from a semiconductor device to the battery during a first battery charging time period. The method also includes measuring a charging voltage level at the battery during the first battery charging time period. During a non-charging voltage measurement time interval, the method includes temporarily stopping application of the charging current from the semiconductor device to the battery and measuring a non-charging voltage level at the battery while the charging current is not being applied to the battery.
US07786695B2	Configurable battery management system with embedded SRAM in chip architecture A battery management system includes an external non-volatile memory and a battery management chip with embedded SRAM, CPU, ROM, and ROM_RAM encoder. The chip communicates with the non-volatile memory via standard protocols. While the battery management system is powered on or reset, a battery management program stored in the non-volatile memory is loaded to the embedded SRAM and the executed by CPU. As turning off this system, the program in the SRAM is then restored back the non-volatile memory. A battery protection IC is optionally embedded in the chip or externally connected with this chip to protect the battery from over-/under-voltage, over-current and short-circuit in both charge and discharge.
US07786689B2	Trapping prevention guard and method for controlling a motor-driven adjusting device In order to reliably detect a jamming situation, in particular in a seat adjusting means, provision is made for a total loading exerted by the drive during a start phase to be determined and for this to be fixed as the basic loading. The existence or non-existence of a jamming situation is finally determined during a monitoring phase by comparing the basic loading and the total loading that varies during operation of the adjusting apparatus.
US07786684B2	Electromechanical flight control system and method for rotorcraft Flight control systems and methods for rotorcraft are provided. The flight control system includes a user input device and a motor in operable communication with the user input device. The motor includes a plurality of winding sets and an armature coupled to the plurality of winding sets. The armature includes multiple magnets. The winding sets and the armature are configured such that when one or more of the plurality of winding sets are selectively energized, the armature moves relative to the one or more of the plurality of winding sets.
US07786677B2	Control circuit for turning on/off automobile lights A control circuit for turning on/off automobile lights is connected to first, second and third power output units and an input trigger circuit. When a car is started, the second power output unit supplies power to the control circuit. Thereafter, the third power output unit supplies power to the control circuit for each time when the input trigger circuit is conducted electrically. The control circuit is selectively disconnected from the first power output unit to allow the first power output unit to supply power to turn on the automobile lights. Since the control circuit cannot receive the power from the second power output unit immediately when the engine is turned off, the control circuit will prohibit the first power output unit to supply power to the automobile lights and turn off the automobile lights.
US07786674B2	Quartz metal halide lamp with improved lumen maintenance A quartz metal halide lamp includes an outer sealed envelope defining an interior space, and an arc tube disposed in the interior space. The arc tube has a fill space. A chemical fill is disposed in the fill space. The chemical fill includes sodium halide and lanthanide halide, with the lanthanide halide selected from the group consisting of europium iodide, europium bromide, praseodymium iodide, praseodymium bromide, ytterbium iodide, ytterbium bromide and combinations thereof. The lanthanide halide is between 2 and 6 weight percent of the chemical fill. Electrodes are partially disposed within the fill space.
US07786665B2	Organic electroluminescent device having a diffraction grating for enhancing light extraction efficiency An organic electroluminescent device is provided, which includes an emission portion comprising a first electrode and a second electrode and an organic layer sandwiched between the first and second electrodes, and a diffraction grating disposed neighboring on the emission portion, the diffraction grating having first regions and a second region, the first regions comprising a plurality of pair of recessed and projected portions, the plurality of pair of recessed and projected portions being periodically arranged and provided with a primitive translation vector of a direction, the second region comprising an aggregate of the first regions and located parallel with an emission surface of the organic electroluminescent device.
US07786662B2	Display using a movable electron field emitter and method of manufacture thereof A field emission device 100 comprises an anode 105 and a cathode 110 separated by a distance 115 from the anode. At least one of the anode or cathode is configured to move with respect to the other in response to an applied voltage 120 to at least one of the anode and cathode, the distance being adjustable by the movement.
US07786659B2	Plasma display with a novel green-silicate phosphor Using Eu2+ as the luminescence center for a green-emitting phosphor, a plasma display panel and a PDP device using it are configured by using an Eu2+-activated silicate green-emitting phosphate (Ca1-xM1x)2-e.M2.Si2O7:Eue with improved decay characteristics. In the formula, M1 is at least one element selected from the group containing Sr and Ba; M2 is at least one element selected from the group containing Mg and Zn; and x indicates the mole fraction of the component M1 and e indicates the mole fraction of Eu respectively satisfy the following conditions: 0
US07786654B2	Compact rake piezoelectric assembly and method of manufacturing same A compact rake piezoelectric assembly comprises a body (110), a plurality of blades (120) extending away from the body, and a piezoelectric patch (130) attached to the body. The piezoelectric patch has a fixed portion (138) and a free portion (139), with the fixed portion being constrained to be in physical contact with the body.
US07786653B2	MEMS piezoelectric switch The present invention provides a MEMS piezoelectric switch that has an articulated unimorph bridge attached to a substrate. The bridge includes a passive layer of zirconia and at least one silicon-based material, an active layer of a piezoelectric material that has a high piezoelectric coefficient, at least one pair of interdigitated electrodes, disposed on the top surface of the active layer and across which the bias voltage is applied, and a top contact electrode. A bottom contact electrode is provided on the substrate, and signals flow through the switch when the top and bottom contact electrodes contact one another.
US07786648B2	Semi-resonant driving systems and methods thereof A driving system in accordance with embodiments of the present invention includes a structure and a vibration system. The structure has at least one point to frictional couple to and drive a movable element in one of at least two directions. The structure also has at least two bending modes which each have a different resonant frequency. The vibration system applies two or more vibration signals which are at a vibration frequency to each of the bending modes of the structure. The vibration frequency is substantially the same as one of the resonant frequencies. At the vibration frequency one of the bending modes of the structure is vibrating substantially at resonance and the other of the bending modes of the structure is vibrating at partial resonance. The vibration system adjusts a phase shift between the two or more applied vibration signals to control which one of the at least two directions the moveable element is moved.
US07786647B2	Micromotion mechanism and microscope apparatus having micromotion mechanism A micromotion mechanism includes: a fixing base; a movable element supported by the fixing base and movable thereon; an ultrasonic actuator for relatively moving the movable element and the fixing base; and a control device for outputting a drive signal of the ultrasonic actuator. The drive signals of the ultrasonic actuator during the micromotion drive are two types of burst signals equal in frequency and different in phase, and amplitude of the start and end of each of the two burst signals changes, and the maximum amplitude of at least one of the two burst signals is lower than in the normal driving operation.
US07786645B2	Superconducting machine stator A stator for an electrical machine includes a back iron including a substantially cylindrical annular structure having an inner surface and an axis. A plurality of supports are fabricated of non-magnetic material, each support extending parallel to the axis of the annular structure along the inner surface of the annular structure, each support including a primary base and at least two primary support members. The primary bases substantially conform to the inner surface of the back iron with the primary support members extending radially inward from the primary base towards the axis of the annular structure. A stator winding is positioned between the at least two primary support members and between the primary base of the support and the axis of the annular structure.
US07786642B2	Rotating machinery In a rotating machinery having armature windings constituted by a lot of strands, when the armature winding is constituted by four layers, a step number of the strands becomes half with respect to two layers of armature windings so as to facilitate manufacturing an armature winding of 540 degree transposition in which a transposition pitch is elongated and a circulating current loss is reduced, but since an output voltage becomes twice, for securing a voltage limit value caused by an isolation resisting force, one layer of armature windings are constituted by sub windings separated into at least two layers in a vertical direction, a transposition is independently applied to each of the sub windings, the sub windings are connected to the armature windings of the other slot while keeping an isolation of the sub winding at an armature winding end region by at least two connecting methods, and the sub winding constructs a parallel circuit by the armature windings of a plurality of slots.
US07786622B2	Juvenile product inductive power transfer A juvenile product includes a power adapter comprising a first AC-to-DC converter to generate a DC transmission voltage from a line power source, and a power cable coupled to the power adapter and configured to carry the DC transmission voltage. A power transmitter coupled to the power cable includes a transmitter coil and a DC-to-AC converter coupled to the transmitter coil such that an AC current flows through the transmitter coil based on the DC transmission voltage. A power supply includes a receiver coil configured for generation of induced current in the receiver coil via inductive coupling with the transmitter coil, and further includes a second AC-to-DC converter coupled to the receiver coil to generate DC power based on the induced current. An electrical load coupled to the power supply is configured for operation via the DC power.
US07786620B2	Battery supplementing super capacitor energy storage charge and discharge converter A super capacitor energy storage supplementing a battery providing power to a direct current bus including charge and discharge converters is disclosed. A bank of super capacitors may be charged by a battery with a pulse-width modulation controller and an electromagnetic interference filter. The bank of super capacitors may be controllably connected to the direct current bus through an isolating transformer implemented as a isolated boost converter.
US07786611B1	System and method for generating wind power from a vertical structure A ducting structure for generating wind power from a vertical structure. The ducting structure includes a main housing sized and shaped to be coupled to a wind turbine and located on the vertical structure. The main housing includes a vertically oriented aperture having a first duct leading to the coupled wind turbine and a horizontally oriented aperture having a second duct leading to the coupled wind turbine. The vertically oriented aperture captures a prevailing wind and the horizontally oriented aperture captures an updraft flowing upwardly along the vertical structure. The captured updraft and the prevailing wind are guided through the first and second ducts past the coupled wind turbine.
US07786609B2	Ocean energy system and method A wave energy system and method are provided that have a main body that floats on the surface of the ocean and generates energy due to the motion of the crests and troughs of the ocean.
US07786607B2	Overlay correction by reducing wafer slipping after alignment A method and apparatus for correcting overlay errors in a lithography system. During lithographic exposure, features being exposed on the wafer need to overlay existing features on the wafer. Overlay is a critical performance parameter of lithography tools. The wafer is locally heated during exposure. Thermal expansion causes stress between the wafer and the wafer table, which will cause the wafer to slip if it exceeds the local frictional force. To increase the amount of expansion allowed before slipping occurs, the wafer chuck is uniformly expanded after the wafer has been loaded. This creates an initial stress between the wafer and the wafer table. As the wafer expands due to heating during exposure, the expansion first acts to relieve the initial stress before causing an opposite stress from thermal expansion. The wafer may be also be heated prior to attachment to the wafer chuck, creating the initial stress as the wafer cools.
US07786606B2	Resin-sealed electronic device and method of manufacturing the same A resin-sealed semiconductor device includes a metal frame, an electronic substrate, an adhesive agent, a molded resin, and a bonding agent. The electronic substrate includes a first surface having a circuit element wiring part, a second surface facing the metal frame, and a side surface arranged approximately perpendicularly to the first surface and the second surface. The adhesive agent is disposed between the metal frame and the second surface to cover the second surface and a portion of the side surface adjacent to the second surface. The molded resin covers the metal frame and the electronic substrate, and holds the other portion of the side surface adjacent to the first surface. The bonding agent is disposed between the circuit element wiring part and the molded resin so that the molded resin holds the circuit element wiring part through the bonding agent.
US07786605B2	Stacked semiconductor components with through wire interconnects (TWI) A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via bonded to the substrate contact, and a contact on the wire. A stacked semiconductor component includes the semiconductor substrate, and a second semiconductor substrate stacked on the substrate and bonded to a through wire interconnect on the substrate. A method for fabricating a semiconductor component with a through wire interconnect includes the steps of providing a semiconductor substrate with a substrate contact, forming a via through the substrate contact and part way through the substrate, placing the wire in the via, bonding the wire to the substrate contact, and then thinning the substrate from a second side to expose a contact on the wire. A system for fabricating the semiconductor component includes a bonding capillary configured to place the wire in the via, and to form a bonded connection between the wire and the substrate contact.
US07786601B2	Semiconductor chip and multi-chip package There is provided a semiconductor chip and a multi-chip package. Each semiconductor chip includes a plurality of pads formed on a first surface thereof and electrically connected to an integrated circuit, and interconnection patterns formed as stripes on a second surface of the semiconductor chip. The interconnection patterns are formed by transferring a part of the basic layout configured with a pattern of stripes extending from a center portion to an edge portion, wherein the pads are electrically connected to the interconnection patterns.
US07786600B2	Circuit substrate having circuit wire formed of conductive polarization particles, method of manufacturing the circuit substrate and semiconductor package having the circuit wire A circuit substrate includes a substrate body having a first terminal and a second terminal separated from the first terminal. A circuit wire includes a wiring unit for electrically connecting the first and second terminals by electrically connecting conductive polarization particles that include a first polarity and a second polarity that is opposite to the first polarity. The circuit wire also includes an insulation unit for insulating the wiring unit.
US07786595B2	Stacked chip package structure with leadframe having bus bar The present invention provides a chip-stacked package structure with leadframe having bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads and is vertically distant from the plurality of inner leads; a chip-stacked structure formed with a plurality of chips that stacked together and set on the die pad, the plurality of chips and the plurality of inner leads being electrically connected with each other; and an encapsulant covering over the chip-stacked package structure and the leadframe, in which the leadframe comprises at least a bus bar, which is provided between the plurality of inner leads arranged in rows facing each other and the die pad.
US07786594B2	Wafer level stack structure for system-in-package and method thereof A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, wherein the first wafer and the second wafer are stacked, and wherein the first wafer and the second wafer are coupled to each other. A system-in-package, including a wafer level stack structure including at least one first device chip with a first plurality of input/output (I/O) pads and at least one second device chip with a second plurality of I/O pads, and a common circuit board to which the wafer level stack structure is connected.
US07786582B2	System for providing a redistribution metal layer in an integrated circuit A system and method is disclosed for providing a redistribution metal layer in an integrated circuit. The redistribution metal layer is formed from the last metal layer in the integrated circuit during manufacture of the integrated circuit before final passivation is applied. The last metal layer provides sites for solder bump pads used in flip chip interconnection. The redistribution metal layer can be (1) a flat layer deposited over the next to last metal layer through an opening in a dielectric layer, or (2) deposited over an array of vias connected to the next to last metal layer. Space between the solder bump pads is deposited with narrower traces for connecting active circuit areas below. A final passivation layer is deposited to ensure product reliability.
US07786579B2	Apparatus for crack prevention in integrated circuit packages A microelectronic package having integrated circuits is provided. The microelectronic package includes multiple dielectric laminate layers, copper circuitry between the dielectric laminate layers where the copper circuitry includes circuit traces, and ball grid arrays/land grid arrays operatively connected to the copper circuitry such that conduction occurs. Further, proximate to the connection of the copper circuitry and the ball grid arrays/land grid arrays, a protective copper tongue is below an extension of the circuit traces, such that the protective copper tongue prevents the circuit traces from being affected by cracking propagated in the dielectric laminate layers or the ball grid arrays/land grid arrays.
US07786577B2	Component with chip through-contacts A panel for the production of electronic components is disclosed. The components have a substantially planar semiconductor chip with chip through-contacts which are provided with electrically conductive material. A rewiring region is subdivided into an insulating layer and also a first rewiring arranged therein, the rewiring projecting laterally beyond the side edge of the planar semiconductor chip. The rewiring has external contacts for electrical connections toward the outside. The panel provides a filling layer made of plastic, which encapsulates the semiconductor chip in a side region between the chip front side and the chip rear side and which is connected to the rewiring region.
US07786574B2	Microelectronic imaging units Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method includes providing a plurality of imaging dies on a microfeature workpiece. The individual imaging dies include an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality of external contacts operably coupled to the integrated circuit. The method further includes attaching a plurality of covers to corresponding imaging dies, cutting the microfeature workpiece to singulate the imaging dies, and coupling the singulated dies to a support member. The covers can be attached to the imaging dies before or after the workpiece is cut.
US07786572B2	System in package (SIP) structure A System In Package (SIP) arrangement and method of connecting a plurality of flip chips and wire bond chips with reduced wiring complexity and increase flexibility. The SIP arrangement includes at least one wire bond chip and at least one flip chip.
US07786569B2	Semiconductor device using wiring substrate having a wiring structure reducing wiring disconnection The semiconductor device concerning the present invention has a wiring substrate, a semiconductor chip, under-filling resin, a reinforcement ring, a heat spreader, a power supply pattern and a wiring layer under surface via land which are formed on the wiring substrate and spaced out by a clearance region, an insulating film, a wiring layer via land, a via, and a wiring which is formed on the insulating film, passes over the clearance region, and connects the wiring layer via land to the semiconductor chip. The wiring layer via land is formed between the semiconductor chip and the reinforcement ring, and within a region of a 1 mm width from the extension line of the diagonal line of the semiconductor chip. The angle of the lead-out direction of the wiring from a wiring layer via land to the extension line of the diagonal line of the semiconductor chip is 20° or more.
US07786568B2	Window BGA semiconductor package A WBGA semiconductor package primarily comprises a substrate, a chip, a chip-bonding adhesive, a plurality of bonding wires electrically connecting the chip and the substrate, an encapsulant to encapsulate the chip and the bonding wires, and a plurality of external terminals disposed under the substrate. The substrate has a depression for accommodating the chip-bonding adhesive and a slot for passing through bonding wires. The chip is partially embedded in the depression to dispose on the substrate. During the chip bonding step, the chip-bonding adhesive is confined in the depression in a manner to fill the gaps between the sides of the first chip and the inwalls around the depression to generate a non-planar adhering interface by partially covering the sides of the first chip. Therefore, the total package thickness is reduced, the delamination of the passivation layer and the fractures at the sides of the chip are avoided.
US07786564B2	Semiconductor device and method for manufacturing semiconductor device A semiconductor device according to the present invention is provided with a semiconductor chip in which a plurality of electrode pads is provided on a principal surface, a plurality of bump electrodes provided on the electrode pads of the semiconductor chip, a square-shaped wiring board which is disposed on a side of the principal surface of the semiconductor chip, and in which at least two sides of an outer circumference that face each other are positioned in an area on the principal surface of the semiconductor chip, a plurality of external terminals which is provided on the wiring board, and which are electrically connected to a plurality of the bump electrodes through a wiring of the wiring board, and sealing material which is provided between the semiconductor chip and the wiring board, and which covers a connection part between the bump electrode and the wiring.
US07786562B2	Stackable semiconductor chip layer comprising prefabricated trench interconnect vias A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.
US07786556B2	Semiconductor device and lead frame used to manufacture semiconductor device A semiconductor device has an element encapsulated in a resin mold. Metal leads protruding from the resin mold are solder plated except at the lead-tip end surfaces, and the exposed lead-tip end surfaces have an area less than half the cross-sectional area of the protruding metal leads. The semiconductor device is manufactured using a lead frame in which the metal leads are connected to a frame by plating bars having a thickness smaller than half the thickness of the metal leads. In another embodiment, the metal leads are connected to the frame by plating bars that extend sideways from the metal leads, and the end tips of the metal leads are entirely covered with plating to improve soldering wettability.
US07786554B2	Stress-free lead frame The present invention relates to a stress-free lead frame (1) for a semiconductor. The stress-free lead frame (1) is provided with a stress-relief means (15) and an interlocking means (16) at the outer periphery. The stress-relief means (15) is capable of accommodating expansion and compression while the interlocking means (16) take care of shock and vibration during handling to thereby eliminate delamination of the lead frame (10).
US07786549B2	Antifuse structure and system for closing thereof A structure and method for providing an antifuse which is closed by laser energy with an electrostatic assist. Two or more metal segments are formed over a semiconductor structure with an air gap or a porous dielectric between the metal segments. Pulsed laser energy is applied to one or more of the metal segments while a voltage potential is applied between the metal segments to create an electrostatic field. The pulsed laser energy softens the metal segment, and the electrostatic field causes the metal segments to move into contact with each other. The electrostatic field reduces the amount of laser energy which must be applied to the semiconductor structure to close the antifuse.
US07786548B2	Electric element, memory device, and semiconductor integrated circuit An electric element includes a first electrode (1), a second electrode (3), and a variable-resistance film (2) connected between the first electrode (1) and the second electrode (3). The variable-resistance film (2) contains Fe (iron) and O (oxygen) as constituent elements. The content of oxygen in the variable-resistance film (2) is modulated along the film thickness direction.
US07786546B2	System-on-chip with shield rings for shielding functional blocks therein from electromagnetic interference A system-on-chip (SoC) that is immune to electromagnetic interference has block shield rings fabricated therein. The SoC includes a microprocessor core; an on-chip bus interface; an embedded memory block; and an analog/mixed-signal integrated circuit shielded by an EMI shield ring encircling the analog/mixed-signal integrated circuit for protecting the analog/mixed-signal integrated circuit from electromagnetic interference. The EMI shield ring is grounded and includes a metal rampart consisting of multi-layer metals and vias. A pickup diffusion is connected to the metal rampart. In one embodiment, the memory block is also shielded.
US07786545B2	Image sensor and method for manufacturing the same Disclosed are an image sensor and a method for manufacturing the same. The image sensor includes a substrate provided with a transistor circuit, first and second interconnections separated from each other on the substrate, a first conductive-type conductive layer formed at side surfaces of the first interconnection, a second conductive-type conductive layer formed at side surfaces of the second interconnection, and an intrinsic layer formed between the first and second conductive-type conductive layers thereby forming a P-I-N structure.
US07786543B2	CDS capable sensor with photon sensing layer on active pixel circuit A MOS or CMOS based active pixel sensor with special sampling features to substantially eliminate clock noise. The sensor includes an array of pixels fabricated in or on a substrate, each pixel defining a charge collection node on which charges generated inside a photodiode region are collected, a charge integration node, at which charges generated in said pixel are integrated to produce pixel signals, a charge sensing node from which reset signals and the pixel signals are sensed. In preferred embodiments the sensor includes a continuous electromagnetic radiation detection structure located above the pixel circuits providing a photodiode region for each pixel. The sensor includes integrated circuit elements adapted to maintain voltage potentials of the charge integration nodes substantially constant during charge integration cycles. The sensor also includes integrated circuit elements having electrical capacitance adapted to store charges providing an electrical potential at the charge integration node. In preferred embodiments this is a pinned diode.
US07786540B2	Sensor platform using a non-horizontally oriented nanotube element Sensor platforms and methods of making them are described. A platform having a non-horizontally oriented sensor element comprising one or more nanostructures such as nanotubes is described. Under certain embodiments, a sensor element has or is made to have an affinity for an analyte. Under certain embodiments, such a sensor element comprises one or more pristine nanotubes. Under certain embodiments, the sensor element comprises derivatized or functionalized nanotubes. Under certain embodiments, a sensor is made by providing a support structure; providing one or more nanotubes on the structure to provide material for a sensor element; and providing circuitry to electrically sense the sensor element's electrical characterization. Under certain embodiments, the sensor element comprises pre-derivatized or pre-functionalized nanotubes. Under other embodiments, sensor material is derivatized or functionalized after provision on the structure or after patterning. Under certain embodiments, a large-scale array of sensor platforms includes a plurality of sensor elements.
US07786537B2	Semiconductor device and method for manufacturing same A semiconductor device includes a silicon substrate; a P channel type field effect transistor including a first gate insulating film on the substrate, a first gate electrode on the first gate insulating film and a first source/drain region; and an N channel type field effect transistor including a second gate insulating film on the substrate, a second gate electrode on the second gate insulating film and a second source/drain region. The entire first gate electrode is made of a metal silicide, and at least in an upper portion including the upper surface of the second gate electrode, a silicide region of the same kind as the metal (M) is provided. The metal concentration in the silicide region is lower than that in the silicide of the first gate electrode. In an upper portion including the upper surface of the second gate electrode, there is a barrier layer region containing a metal diffusion suppressing element at a concentration higher than that in the lower portion.
US07786535B2	Design structures for high-voltage integrated circuits Design structures for high-voltage integrated circuits. The design structure, which is formed using a semiconductor-on-insulator (SOI) substrate, may include device structure with a semiconductor body positioned between first and second gate electrodes. The first and second gate electrodes and the semiconductor body may be formed from the monocrystalline SOI layer of the SOI substrate. A dielectric layer separates each of the first and second gate electrodes from the semiconductor body. These dielectric layers are formed by defining trenches in the SOI layer and filling the trenches with a dielectric material, which may occur concurrently with a process forming other device isolation regions.
US07786534B2	Semiconductor device having SOI structure A plurality of conductive layers and a plurality of wiring layers connecting a supporting substrate having SOI structure and uppermost wire are formed along a peripheral part of a semiconductor chip together with the uppermost wire, to thereby surround a transistor forming region in which a transistor is to be formed.
US07786533B2	High-voltage vertical transistor with edge termination structure A high-voltage transistor includes a drain, a source, and one or more drift regions extending from the drain toward the source. A field plate member laterally surrounds the drift regions and is insulated from the drift regions by a dielectric layer. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).
US07786530B2	Vertical field-effect transistor A vertical field-effect transistor having a semiconductor layer, in which a doped channel region is arranged along a depression. A “buried” terminal region leads as far as a surface of the semiconductor layer. The field-effect transistor also has a doped terminal region near an opening of the depression as well as the doped terminal region remote from the opening, a control region arranged in the depression, and an electrical insulating region between the control region and the channel region. The terminal region remote from the opening leads as far as a surface containing the opening or is electrically conductively connected to an electrically conductive connection leading to the surface. The control region is arranged in only one depression. The field-effect transistor is a drive transistor at a word line or at a bit line of a memory cell array.
US07786529B2	Semiconductor device and method of fabricating the same A semiconductor device includes a transistor having a recessed gate, contact plugs formed in a region of a plurality of trenches, which are formed by recessing a semiconductor substrate. Further, a metal line and a source/drain region can be connected through the contact plug, so that on-current can be increased as much as an increased channel area.
US07786526B2	Nonvolatile semiconductor memory device It is an object of the present invention to provide a nonvolatile semiconductor memory device which has superior writing characteristics and electric charge retention characteristics. In addition, it is an object of the present invention to provide a nonvolatile semiconductor memory device in which a writing voltage can be reduced. The nonvolatile semiconductor memory device includes a semiconductor region with a channel formation region formed between a pair of impurity regions which are formed to be apart from each other; and a first insulating layer, a charge accumulation layer, a second insulating layer, and a control gate are formed in a location which is a top layer portion of the semiconductor region and which roughly overlaps with the channel formation region. The charge accumulation layer is insulative and is formed as a layer in which electric charge can be trapped.
US07786524B2	Semiconductor device and method of manufacturing the same A semiconductor device includes a semiconductor substrate including a first region and a second region being adjacent to the first region; a floating gate electrode layer formed above the semiconductor substrate in the first region, the floating gate electrode layer including a first width; a dummy gate electrode layer formed above the semiconductor substrate in the second region, the dummy gate electrode layer including a second width being greater than the first width of the floating gate electrode layer; a first gate insulating film formed on the floating gate electrode layer, the first gate insulating film including a first thickness; a second gate insulating film formed on the dummy gate electrode layer, the second gate insulating film including a second thickness being greater than the first thickness of the first gate insulating film; and a control gate electrode layer formed on the first and the second gate insulating films.
US07786519B2	Light emitting device and method for manufacturing the same This document discloses an organic light emitting device comprising a first electrode and a wire comprising a contact part formed on a substrate, an insulating layer formed on the first electrode and a portion of the wire, the insulating layer comprising an opening which exposes a portion of the first electrode and a contact hole which exposes an entire upper surface of the contact part, an emission layer formed in the opening, a second electrode formed on the emission layer and the upper surface of the contact part though the contact hole.
US07786516B2	Discrete trap non-volatile multi-functional memory device A multiple layer tunnel insulator is fabricated between a substrate and a discrete trap layer. The properties of the multiple layers determines the volatility of the memory device. The composition of each layer and/or the quantity of layers is adjusted to fabricate either a DRAM device, a non-volatile memory device, or both simultaneously.
US07786513B2	Semiconductor integrated circuit device and power source wiring method therefor In a semiconductor integrated circuit device, from a first power source strap supplying a potential to a first standard cell receiving a supply of the potential, the potential is supplied via a first cell power source line having a constant width. The width of the first cell power source line is determined in accordance with power consumed by the first standard cell and with the number of standard cells that can be placed between the first power source strap and a third power source strap.
US07786512B2	Dense non-volatile memory array and method of fabrication A non-volatile memory array includes a multiplicity of memory cells, each of whose area is less than 4 F2 per cell (where F is a minimum feature size), and periphery elements to control the memory cells. The present invention also includes a non-volatile memory array which includes word lines and bit lines generally perpendicular to the word lines, with a word line pitch of less than 2 F. In one embodiment, the word lines are made of polysilicon spacers.
US07786511B2	Semiconductor device with Schottky and ohmic electrodes in contact with a heterojunction To provide a semiconductor device that has a sufficiently low on-resistance and excellent low-capacitance and high-speed characteristics as compared with conventional GaN-based diodes. The semiconductor device includes: a substrate (101); a buffer layer (102); a stack structure (103 and 104) including at least one heterojunction unit (103 and 104) that is a stack of a layer (GaN layer 103) made of a nitride semiconductor and a layer (AlGaN layer 104) made of another nitride semiconductor having a larger band gap than the nitride semiconductor (GaN layer 103); a Schottky electrode (106) that is placed at a first end of the stack structure (103 and 104) and forms a Schottky barrier contact with the heterojunction unit (103 and 104); and an ohmic electrode (107) that is placed at a second end of the stack structure (103 and 104) and forms an ohmic contact with the heterojunction unit (103 and 104).
US07786510B2	Transistor structure and manufacturing method thereof An HBT structure and manufacturing method thereof, in which the HBT structure includes an emitter, an intrinsic base, a collector, an insulating sidewall, and a stress-inducing base formed by selective epitaxial growth to locally induce a stress to the HBT structure. Compressive or tensile stress is additionally induced from outside to modify physical and electric properties of a semiconductor layer, thereby improving the performance of the transistor.
US07786509B2	Field-effect transistor and method of making same A field-effect transistor is composed of a substrate, an electron transport layer and an electron supply layer formed sequentially on the substrate, wherein the electron transport layer and the electron supply layer are formed of a nitride semiconductor, a gate electrode, a source electrode and a drain electrode formed on the electron supply layer; and two high impurity concentration regions located in a depth direction directly below the source electrode and the drain electrode, respectively, the two high impurity concentration regions being formed to sandwich a two-dimensional electron gas layer formed between the electron transport layer and the electron supply layer. The two high impurity concentration regions each have a higher impurity concentration than the electron transport layer and the electron supply layer located directly below the gate electrode.
US07786506B2	Semiconductor devices with a field shaping region A semiconductor device includes a semiconductor region having a pn junction and a field shaping region located adjacent the pn junction to increase the reverse breakdown voltage of the device. The field shaping region is coupled via capacitive voltage coupling regions to substantially the same voltages as are applied to the pn junction. When a reverse voltage is applied across the pn junction and the device is non-conducting, a capacitive electric field is present in a part of the field shaping region which extends beyond a limit of the pn junction depletion region which would exist in the absence of the field shaping region. The electric field in the field shaping region inducing a stretched electric field limited to a correspondingly stretched pn junction depletion region in the semiconductor region.
US07786504B2	Bidirectional PNPN silicon-controlled rectifier The present invention discloses a bidirectional PNPN silicon-controlled rectifier comprising: a p-type substrate; a N-type epitaxial layer; a P-type well and two N-type wells all formed inside the N-type epitaxial layer with the two N-type wells respectively arranged at two sides of the P-type well; a first semiconductor area, a second semiconductor area and a third semiconductor area all formed inside the P-type well and all coupled to an anode, wherein the second semiconductor area and the third semiconductor area are respectively arranged at two sides of the first semiconductor area, and wherein the first semiconductor area is of first conduction type, and the second semiconductor area and the third semiconductor area are of second conduction type; and two P-type doped areas respectively formed inside the N-type wells, wherein each P-type doped area has a fourth semiconductor area neighboring the P-type well and a fifth semiconductor area, and wherein both the fourth semiconductor area and the fifth semiconductor area are coupled to a cathode, and wherein the fourth semiconductor area is of second conduction type, and the fifth semiconductor area is of first conduction type.
US07786503B2	Gallium nitride crystals and wafers and method of making A crystal comprising gallium nitride is disclosed. The crystal has at least one grain having at least one dimension greater than 2.75 mm, a dislocation density less than about 104 cm−2, and is substantially free of tilt boundaries.
US07786500B2	Light-emitting diodes lamp lens structure The present invention is an LED lamp lens, on which orderly arranged surface plural protuberances. And with the differences of light perviousness, a particular luminous pattern of the LED lamp is displayed when the LED lamp is turned on.
US07786499B2	Replaceable through-hole high flux LED lamp The present invention is a through-hole LED light source with capability of emitting a beam angle of less than 75 degrees. The light source presents a three-dimensional lead frame with a well, into which at least one LED is mounted, and an optical housing which serves as a directional lens. Through adjustment of the housing and lead well properties, beam angle is adjusted to any angle. The frame is three-dimensional, preferably cylindrical, with both inner and outer portions, electrically isolated. The inner portion serves as the mounting area for the LEDs (and contains the well) and the LED serves as the electrical conduit between the portions, completing a circuit an illuminating the LED.
US07786496B2	Semiconductor device and method of manufacturing same A FET is formed on a semiconductor substrate, a curved surface having a radius of curvature is formed on an upper end of an insulation, a portion of a first electrode is exposed corresponding to the curved surface to form an inclined surface, and a region defining a luminescent region is subjected to etching to expose the first electrode. Luminescence emitted from an organic chemical compound layer is reflected by the inclined surface of the first electrode to increase a total quantity of luminescence taken out in a certain direction.
US07786495B2	Light-emitting element array and image forming apparatus A light-emitting element array can be manufactured without the separation of a metal reflection layer. The light-emitting element array includes a plurality of light-emitting element portions provided on a substrate, at least one space of the spaces between adjacent light-emitting element portions being electrically separated from each other, wherein the metal reflection layer is provided on the substrate and under the plurality of light-emitting element portions, and a resistive layer for electrical separation between the light-emitting element portions is provided between the plurality of light-emitting element portions and the metal reflection layer. The plurality of light-emitting element portions are divided into a plurality of blocks. Each of the blocks includes a plurality of light-emitting portions. The electrical separation between the light-emitting portions can be made as electrical separation between adjacent light-emitting element portions in adjacent and different blocks.
US07786490B2	Multi-chip module single package structure for semiconductor The invention is to provide a semiconductor light-emitting device package structure. The semiconductor light-emitting device package structure includes a substrate, N sub-mounts and N semiconductor light-emitting die modules, where N is a positive integer lager than or equal to 2. Each of the sub-mounts is embedded on the substrate and exposed partially. Each of the semiconductor light-emitting die modules is mounted on the exposed surface of one of the sub-mounts.
US07786489B2	Nitride semiconductor light emitting device and production method thereof The present invention provides a nitride semiconductor light emitting device, which comprises positive and negative electrodes with high adhesion, can output high power, and does not generate heat; specifically, the present invention provides a nitride semiconductor light emitting device comprising at least an ohmic contact layer, a p-type nitride semiconductor layer, a nitride semiconductor light emitting layer, and an n-type nitride semiconductor layer, which are laminated on a plate layer, wherein a plate adhesion layer is formed between the ohmic contact layer and the plate layer, and the plate adhesion layer is made of an alloy comprising 50% by mass or greater of a same component as a main component of an alloy contained in the plate layer.
US07786488B2	Nitride semiconductor wafer and method of processing nitride semiconductor wafer Nitride semiconductor wafers which are produced by epitaxially grown nitride films on a foreign undersubstrate in vapor phase have strong inner stress due to misfit between the nitride and the undersubstrate material. A GaN wafer which has made by piling GaN films upon a GaAs undersubstrate in vapor phase and eliminating the GaAs undersubstrate bends upward due to the inner stress owing to the misfit of lattice constants between GaN and GaAs.
US07786480B2	System for displaying images including thin film transistor device and method for fabricating the same A system for displaying images. The system comprises a thin film transistor (TFT) device comprising a substrate having a pixel region. An active layer is disposed on the substrate of the pixel region, comprising a channel region, a pair of source/drain regions separated by the channel region. The channel region comprises dopants with a first conductivity type and a second conductivity type opposite to the first conductivity type. A gate structure is disposed on the active layer, comprising a stack of a gate dielectric layer and a gate layer. A method for fabricating a system for displaying images including the TFT device is also disclosed.
US07786478B2	Semiconductor integrated circuit having terminal for measuring bump connection resistance and semiconductor device provided with the same An integrated circuit is formed in a chip. Positioning marks are provided on at least two of four regions respectively near four corners of a first main surface of the chip. Terminals are provided on the first main surface to measure bump connection resistance. The terminals adjoin the positioning marks respectively. A connection wire is provided in the chip. The connection wire is connected to the terminals electrically.
US07786475B2	In-line test circuit and method for determining interconnect electrical properties and integrated circuit incorporating the same A test circuit for, and method of, determining electrical properties of an underlying interconnect layer and an overlying interconnect layer of an integrated circuit (IC) and an IC incorporating the test circuit or the method. In one embodiment, the test circuit includes a gate chain having a ring path and a stage. In one embodiment, the stage includes: (1) a underlying test segment in the underlying interconnect layer, (2) a overlying test segment in the overlying interconnect layer and (3) logic circuitry activatible after formation of the underlying interconnect layer and before formation of the overlying interconnect layer to place the underlying test segment in the ring path and further activatible after the formation of the overlying interconnect layer to substitute the overlying test segment for the underlying test segment in the ring path.
US07786474B2	Organic light-emitting device and method of fabricating the same An organic light-emitting device, comprising: a substrate; a first conductive layer formed over the substrate; at least one layer of a light-emissive organic material formed over the first conductive layer; a barrier layer formed over the at least one organic layer which acts to protect the at least one layer of organic material; and a second conductive layer, preferably a patterned sputtered layer, formed over the barrier layer.
US07786467B2	Three-dimensional nanoscale crossbars Various embodiments of the present invention include three-dimensional, at least partially nanoscale, electronic circuits and devices in which signals can be routed in three independent directions, and in which electronic components can be fabricated at junctions interconnected by internal signal lines. The three-dimensional, at least partially nanoscale, electronic circuits and devices include layers, the nanowire or microscale-or-submicroscale/nanowire junctions of each of which may be economically and efficiently fabricated as one type of electronic component. Various embodiments of the present invention include nanoscale memories, nanoscale programmable arrays, nanoscale multiplexers and demultiplexers, and an almost limitless number of specialized nanoscale circuits and nanoscale electronic components.
US07786463B2	Non-volatile multi-bit memory with programmable capacitance Non-volatile multi-bit memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region. A first insulating layer is over the substrate. A first solid electrolyte cell is over the insulating layer and has a capacitance that is controllable between at least two states and is proximate the source region. A second solid electrolyte cell is over the insulating layer and has a capacitance or resistance that is controllable between at least two states and is proximate the drain region. An insulating element isolates the first solid electrolyte cell from the second solid electrolyte cell. A first anode is electrically coupled to the first solid electrolyte cell. The first solid electrolyte cell is between the anode and the insulating layer. A second anode is electrically coupled to the second solid electrolyte cell. The second solid electrolyte cell is between the anode and the insulating layer. A gate contact layer is over the substrate and between the source region and drain region and in electrical connection with the first anode and the second anode. The gate contact layer is electrically coupled to a voltage source.
US07786462B2	Chalcogenide devices exhibiting stable operation from the as-fabricated state A chalcogenide material and chalcogenide memory device having less stringent requirements for formation, improved thermal stability and/or faster operation. The chalcogenide materials include materials comprising Ge, Sb and Te in which the Ge and/or Te content is lean relative to the commonly used Ge2Sb2Te5 chalcogenide composition. Electrical devices containing the instant chalcogenide materials show a rapid convergence of the set resistance during cycles of setting and resetting the device from its as-fabricated state, thus leading to a reduced or eliminated need to subject the device to post-fabrication electrical formation prior to end-use operation. Improved thermal stability is manifested in terms of prolonged stability of the resistance of the device at elevated temperatures, which leads to an inhibition of thermally induced setting of the reset state in the device. Significant improvements in the 10 year data retention temperature are demonstrated. Faster device operation is achieved through an increased speed of crystallization, which acts to shorten the time required to transform the chalcogenide material from its reset state to its set state in an electrical memory device.
US07786461B2	Memory structure with reduced-size memory element between memory material portions A memory cell device includes a memory cell access layer, a dielectric material over the memory cell access layer, a memory material structure within the dielectric material, and a top electrode in electrical contact with the memory material structure. The memory material structure has upper and lower memory material portions and a memory material element therebetween. The lower memory material layer is in electrical contact with a bottom electrode. The lower memory material layer has an average lateral dimension. The memory material element defines an electrical property state change region therein and has a minimum lateral dimension which is substantially less than the average lateral dimension. In some examples the memory material element is a tapered structure with the electrical property state change region at the junction of the memory material element and the lower memory material layer.
US07786460B2	Phase change memory device and manufacturing method A phase change memory device comprises a photolithographically formed phase change memory cell having first and second electrodes and a phase change element positioned between and electrically coupling the opposed contact elements of the electrodes to one another. The phase change element has a width, a length and a thickness. The length, the thickness and the width are less than a minimum photolithographic feature size of the process used to form the phase change memory cell. The size of the photoresist masks used in forming the memory cell may be reduced so that the length and the width of the phase change element are each less than the minimum photolithographic feature size.
US07786454B2	Optics for generation of high current density patterned charged particle beams A direct-write electron beam lithography system employing a patterned beam-defining aperture to enable the generation of high current-density shaped beams without the need for multiple beam-shaping apertures, lenses and deflectors is disclosed. Beam blanking is accomplished without the need for an intermediate crossover between the electron source and the wafer being patterned by means of a double-deflection blanker, which also facilitates proximity effect correction. A simple type of “moving lens” is utilized to eliminate off-axis aberrations in the shaped beam. A method for designing the patterned beam-defining aperture is also disclosed.
US07786452B2	Ion sources, systems and methods Ion sources, systems and methods are disclosed.
US07786450B2	Multipole coils Multipole coils (1, 2, 3, 4, 5, 6) for influencing particle beams have at least two coils (1, 2) which concentrically enclose an imaginary axis (10), wherein a winding (7) made from a flexible circuit board (8) is formed by means of conducting paths (9) disposed thereon for each coil (1, 2, 3, 4, 5, 6) and the circuit boards (8) are rolled into at least one circuit board layer (11, 12, 13, 14). Multipole coils of this kind (1, 2, 3, 4, 5, 6) are utilized for aberration correction in particle optics, wherein the windings (7) of the multipole coils (1, 2, 3, 4, 5, 6) form windows (16) whose width in the peripheral direction is chosen in such a fashion that no secondary interfering fields occur and whose length in the axial direction corresponds at least to its width.
US07786444B2	Multi-aperture single photon emission computed tomography (SPECT) imaging apparatus Methods and systems for improving image quality of single photon nuclear imaging systems, such as single photon emission computed tomography (SPECT) systems for imaging of an object under study, such as small objects including small animals of different sizes using synthetic apertures. The methods and systems include processes and instrumentations for high-resolution, high detection efficiency leading to lower image noise and artifact-free synthetic aperture single photon nuclear images, such as SPECT images. Also, the method and systems provide design parameters, hardware settings, and data acquisition processes for optimal imaging of objects having different sizes.
US07786442B2	Method and apparatus for ion source positioning and adjustment The invention is directed to a method and apparatus for ion source positioning and adjustment. According to one embodiment, the invention relates to an apparatus for ion source positioning and adjustment. The apparatus comprises a bottom plate, a middle plate and a top plate, wherein the top plate is coupled to the middle plate by at least one adjustment member for causing the top plate to move in a first direction, wherein the at least one adjustment member positions the top plate in a predetermined position with respect to the middle plate; and the middle plate is coupled to the bottom plate by a worm gear assembly for causing the middle plate to move in a second direction with respect to the bottom plate.
US07786436B1	FIB based open via analysis and repair An improved method, apparatus, and control/guiding software for localizing, characterizing, and correcting defects in integrated circuits, particularly open or resistive contact/via defects and metal bridging defects, using FIB technology. An apparatus for identifying an abnormal discontinuity in a contact/via in an integrated circuit comprising a focused ion beam system to scan the ion beam over the contact/via to do remove or deposit via material, a detector to collect a secondary particle signal from the contact/via material that gets removed, a sub-system for storing the secondary particle signal from the contact/via in time as well as x-y scan position, a sub-system for correlating secondary particle signals and identifying discontinuities in the correlated secondary particle signals, a sub-system for optimizing the display of the abnormal discontinuity; and a computer to implement software aspects of the system.
US07786428B2	Remote optical control of electrical circuits having a control module with a mechanical switch and a light magnifying lens An optical controlling circuit and an electrical controlled circuit such as a motor control circuit are interconnected by an electro-optic interface. A passive optical switch located in the optical circuit at a position remote from the electrical circuit is physically actuated to generate a change in optical transmission state of the optical circuit. At the electro-optic interface, the change in optical transmission state of the optical circuit is detected and triggers a change in the electrical transmission state of the electric circuit. Embodied as STOP and START pushbuttons, a pair of such passive optical switches at a position remote from the electric circuit reduces the risk that actuating motor control circuits and the like will cause arcing and, in hazardous environments, explosion.
US07786427B2	Proximity optical memory module having an electrical-to-optical and optical-to-electrical converter A memory module is formed of multiple memory chips and an optical interface chip fixed on a substrate. The chips are interconnected by proximity communication (PxC) in which each chip includes transmitting and receiving elements, such as electrical pads which form capacitively coupled links when the chips are placed together with their pads facing each other. The PxC links may be directly between the chips or through an intermediate passive bridge chip. The interface chip is coupled to an external optical channel and includes converters between optical and electrical signals, control circuitry, buffers, and PxC elements for communicating with the memory chips. The array of memories may be a linear or two-dimensional array around the interface chip forming a redundant PxC network, optionally with redundant PxC connections. Multiple rectangular memory chips may present their narrow sides to the interface chip to maximize bandwidth.
US07786424B2	Electronic day and night vision goggles having dual camera Electronic spectacles, especially night vision spectacles (10), include a camera (26), integrated into the spectacles, as the primary recording device for the user of the spectacles (10). The camera has a special camera lens and a CCD sensor or a CMOS sensor. An image processing unit (48) mounted downstream of the camera (26) processes the image taken by the camera (26) and provides an output for display means (28, 30) which are associated with each eye for displaying the image. A reproduction lens system (32, 34) is mounted downstream of each display means (28, 30). At least one transmission and/or reception interface (64,66) is connected to an additional camera (126), separate from the spectacles (10), by signals. The image signals of the additional camera (126) are available via the interface (64, 66) to the display means (28, 30) for displaying the image of the additional camera (126).
US07786421B2	Solid-state curved focal plane arrays The present invention relates to curved focal plane arrays. More specifically, the present invention relates to a system and method for making solid-state curved focal plane arrays from standard and high-purity devices that may be matched to a given optical system. There are two ways to make a curved focal plane arrays starting with the fully fabricated device. One way, is to thin the device and conform it to a curvature. A second way, is to back-illuminate a thick device without making a thinned membrane. The thick device is a special class of devices; for example devices fabricated with high purity silicon. One surface of the device (the non VLSI fabricated surface, also referred to as the back surface) can be polished to form a curved surface.
US07786419B2	Beam power with beam redirection A beam power source transmits a signal indicating power availability, receives a request for power in response, and beams power in response to the request.
US07786418B2	Multimode seeker system with RF transparent stray light baffles There is disclosed a multimode seeker including an imaging infrared seeker and a radio frequency seeker. The imaging infrared seeker and the radio frequency seeker may share an optical system adapted to form an infrared image of an outside scene on a focal plane array image detector and to collimate radio frequency radiation transmitted from a radio frequency transceiver and focus millimeter ware radiation received from the outside scene onto the radio frequency transceiver. The shared optical system may include a plurality of baffles to block sunlight from reaching the focal plane array image detector, each baffle comprising a material that is opaque to infrared radiation and transparent to radio frequency radiation.
US07786410B2	Method of controlling electric kettle for “dry” burn prevention A method of controlling an electric kettle for “dry” burn prevention during heating process, including the steps of: providing a temperature sensor, a microprocessor, and a control circuit; detecting the water temperature; determining the temperature rate change and comparing the temperature rate change with the rate change threshold; and when the temperature rate change is larger than the preset rate change threshold, sending a control signal to the control circuit. The microprocessor determines the temperature rate change and the acceleration rate change that when the temperature rate change and acceleration rate change are larger than the corresponding thresholds respectively, the microprocessor sends the control signal to the control circuit to stop the heating process. Therefore, the present invention accurately determines the increasing temperature of the water and simultaneously cuts off the heating power to prevent the electric kettle from being burnt.
US07786405B2	Connection between two components A method of connecting a fixture to a case component at an opening on the case component, the case component having a base and a wall disposed along at least a portion of the perimeter of the base, and the case component having an interior surface and an exterior surface, includes positioning a first end of the fixture within the opening in the case component such that the first end of the fixture is substantially flush with the interior surface of the wall of the case component. Then welding the fixture to the case component along the interior surface of the case component. Further disclosed is a welded apparatus that includes a first component, an opening, a fixture, and a weld between the first component and the fixture that is located along an inner surface of the first component.
US07786404B2	Method and device for laser welding A plurality of stretches of laser weld are executed on a structure to be welded by means of a device for focusing and orientation of the laser beam, which is associated to a component element of a manipulator robot. The focusing head is kept in the proximity of, but not closely adjacent to, the different areas to be welded and can consequently follow a simplified path, whilst the device for orientation of the laser beam aims the latter on the different areas of the structure to be welded, so that the speed of travel of the laser beam spot along the longitudinal direction of the weld stretch is independent from the speed of travel of the robot end element.
US07786399B2	Apparatus comprising a button formed with a panel and flat panel display An exemplary flat panel display (2) includes a front housing part (20), which has a frame (21) having a button through hole (222) defined in a lower side thereof; a button (221) corresponding to the button through hole, the button comprising a pressing end (2215), at least one claw (2213), and a contact portion (2219), the at least one claw extending inward from an inner side of the button, and the contact portion extending inward from an inner side of the button at the pressing end; and an elastic arm (225) fixed at an inner surface of the lower side of the frame. The at least one claw of the button is snappingly engaged adjacent an inner surface of the lower side of the frame such that the button is engaged in the button through hole and slidable in the button through hole.
US07786398B2	Command switch, in particular an emergency stop switch A command switch or and emergency stop switch is disclosed, which includes an actuator and a contact sensor which is separated therefrom. The actuator includes housing and a tappet, which is guided therein and which has a rest position and an actuation position. The contact sensor includes an open switch element which can be placed in the actuation position by way of the tappet in a tensed position. In at least one embodiment, the command switch also includes an additional switch element which is provided with a first switch piece and a second switch piece, which are applied to the actuator in a separated manner and in/on the contact sensor. The additional switch element only closes when the contact sensor is secured to the actuator. The switch pieces of the additional switch element are separated from each other in a compulsory and advantageous manner by the separated embodiment of the command switch enabling them to be secured to different components of the command switch. An axial or radial misalignment, tilting or rotation between the actuator and the contact sensor leads to the non-conductive connection of the contact piece.
US07786397B2	Safety trigger guard Method and device are provided where a barrier is formed at or around the trigger of a device with a rest area for the index finger so that the finger can remain (extended) off the trigger when the device is not in use. Position and/or size of the rest area is adjustable to, for example, accommodate index fingers of various sizes. Adjustment of the position of the rest area can be achieved by means of a screw which slides a resting piece to a selected correct location, or by means of inserts that may be indexed to a selected length. Device can be a nailer, and the barrier is configured to accommodate a depth gage of the nailer.
US07786396B2	Key-press structure and a method for making the same In one aspect, a key-press structure comprises a frame and a plurality of keys disposed in said frame. Said frame comprises a main portion and two reflecting portions. The main portion has two opposite sides and the two reflecting portions are disposed on the two opposite sides of the main portion, respectively. Said reflecting portion has a reflective surface facing toward the main portion. Said keys are made of a transparent material, and the keys comprise characters formed on the internal surface of said keys. In another aspect, a method of preparing a key-press structure comprises forming a frame that includes a main portion and two reflecting portions. The reflecting portions each have a reflective surface. The main portion has two opposite sides that is connected to the two reflecting portions. The method further comprises forming characters on the internal surface of a plurality of keys, and disposing said keys in the main portion of the frame.
US07786394B2	Backlight keyboard A backlight keyboard (100) includes a plurality of keys (120), a light guide plate (140), and an elastic element (160). Each key includes a key cover (124) and a keypad (122) integrally connected to each other. Further, keypad portions of adjacent keys are integrally connected, as well. The light guide plate is arranged below the keys. The light guide plate defines a plurality of through holes (142), each through hole corresponding to one key. An opaque film (144) is coated on a top surface of the light guide plate. The elastic element is positioned under the light guide plate and is configured for exerting a biasing force on at least one key so as to enable the key to return to its previous position when pressed and released.
US07786393B2	Coating of Mn+1AXn material for electrical contact elements An element for making an electric contact to a contact member for enabling an electric current to flow between the element and the contact member. The element includes a body having at least a contact surface thereof coated with a contact layer applied against the contact member. The contact layer includes a film including a multielement material with equal or similar composition as any of a layered carbide or nitride that can be described as Mn+1AXn, where M is a transition metal or a combination of a transition metals, n is 1, 2, 3 or higher, A is an group A element or a combination of a group A element, element and X is Carbon, Nitrogen or both.
US07786391B1	Ballast housing having rolled edge lead wire exit A ballast housing having a rolled edge lead wire exit for providing protection and strain relief to lead wires extending out from the housing. Grommets are not required in order to provide protection and strain relief to lead wires exiting the housing. The housing includes a lead wire opening having rolled upper and lower edges. The housing includes a lid including the rolled upper edge and a can including the rolled lower edge. The rolled upper edge is vertically aligned with the rolled lower edge but horizontally misaligned with the rolled lower edge. As a result, the rolled upper edge is positioned away from the rolled lower edge a distance that is horizontally shorter than the diameter of the lead wire. Additionally, the lead wire opening has a vertical diameter that is shorter than the diameter of the lead wire.
US07786388B2	Card insulator with provision for conformance to component height changes A card insulator is formed with slits that conform to height changes required by the components mounted to a card. The insulative sheet has simple linear slits that extend completely through the sheet and allow the insulator to deform with simple linear bends when contacted by the tall components mounted to the card. The linear bends allow the surface of the deformed insulator to be flexible without buckling the insulator and without bowing the card.
US07786386B2	High-voltage vehicle component connection method and apparatus A method and apparatus provide an electrical splice between different high-voltage components in a high-voltage propelled vehicle (HVPV), which enables a daisy-chain or series connection of the components. The method includes connecting a first end of a cable to a first component, a second end of the cable to a high-voltage bus bar within a second component to form a splice, and using the outer housings of the components to provide an environmental seal and electromagnetic capability (EMC) shield for the splice, rather than providing such a splice within a dedicated or shared power distribution box. A ring terminal connects to an end of a cable by a press-fitting process or a soldering process. The components can be an energy storage system (ESS), a power inverter module (PIM), an air conditioning control module (ACCM), an auxiliary power module (APM), a power steering controller, and an electrical motor/generator.
US07786385B2	Superconducting cable line A superconducting cable line includes a heat insulation pipe for a fluid for transporting a fluid having a temperature lower than an ordinary temperature and a superconducting cable housed in the heat insulation pipe for a fluid. The superconducting cable including a cable core in a heat insulation pipe for a cable is housed in the heat insulation pipe for a fluid to make a temperature difference between the inside and outside of the heat insulation pipe smaller than that in a situation of laying in an atmosphere. In addition, the superconducting cable has a double heat insulation structure formed with the heat insulation pipe for a cable and the heat insulation pipe for a fluid. Therefore, the superconducting cable line can effectively reduce heat intrusion from the outside into the cable.
US07786384B2	Efficient high-ampacity bowl-shaped tubular conductors A high ampacity busbar includes a pair of oppositely facing bowl-shaped conductors, each of whose cross sections resembles half of a hexagon or an open isosceles trapezoid, separated by an air gap in both horizontal and vertical configurations. The air gap increases cooling efficiency by natural convection by exposing more surface area of the conductors directly to the air flow within the electrical distribution equipment cabinet. As a result, the overall temperature of the bus system is reduced. The shaped conductors have smoother transitions presented to the electrical current between the bends of the conductors. These smooth transitions improve current distribution throughout the conductor, reducing skin effects. As a result of improved thermal dissipation and reduced skin effects, the amount of copper needed to maintain the same ampacity is significantly reduced. Magnetic shields can be placed between adjacent busbars, reducing proximity effects.
US07786382B2	High efficiency paired phases busway system A paired phase electrical power distribution bus way system wherein the three phase paired conductors are surrounded and encapsulated by the neutral conductor and packed all together with the housing as a company element to obtain equal separation between the neutral bus bar assembly and the paired phase conductors. The neutral conductor or bus bar assembly consists of two covers that sandwich the three pairs of phase conductors and the insulator layers to achieve minimum and equal distance between them and to reduce and balance the impedance between the neutral and the paired conductors. The housing compresses each pair through the neutral conductor and insulation layer to maintain contact between the conductors, the neutral, and the housing to get efficient heat conduction to the outside.
US07786381B2	Automatic pool cleaner power conduit including stiff sections An improved power conduit for use with automatic pool cleaners particularly configured to avoid the formation of persistent coils and/or knots. Embodiments in accordance with the invention are characterized by the use of at least one axially stiff elongate member together with axially flexible and axially swivelable means for coupling said stiff member between a stationary power source fitting and a cleaner. The axially flexible and axially swivelable means can be implemented in a variety of ways, e.g., a flexible elongate hose member and a swivel coupling.
US07786376B2	High efficiency solar cells and manufacturing methods A Schottky contact photovoltaic energy conversion cell. The Schottky contact photovoltaic energy conversion cell comprises a flexible substrate and a first array of a plurality of closely-spaced microscale pillars connected to a first electrical cell contact. The pillars and the contact are formed of (or having a top) layer of a first Schottky metal material with a work function selected for efficiently collecting photogenerated electrons. The Schottky contact photovoltaic energy conversion cell further comprises a second array of a plurality of closely-spaced microscale pillars connected to a second electrical cell contact. The pillars and the contact are formed of (or having a top) layer of a second Schottky metal material with a work function selected for efficiently collecting photogenerated holes. The Schottky contact photovoltaic energy conversion cell further comprises a semiconductor absorber thin-film layer covering the first and second contacts and filling spaces among all the pillars, for creating photogenerated electrons and holes.
US07786375B2	Preventing harmful polarization of solar cells In one embodiment, harmful solar cell polarization is prevented or minimized by providing a conductive path that bleeds charge from a front side of a solar cell to the bulk of a wafer. The conductive path may include patterned holes in a dielectric passivation layer, a conductive anti-reflective coating, or layers of conductive material formed on the top or bottom surface of an anti-reflective coating, for example. Harmful solar cell polarization may also be prevented by biasing a region of a solar cell module on the front side of the solar cell.
US07786374B2	Pianoforte instrument exhibiting an additional delivery of energy into the sound board, and method for influencing the sound of a pianoforte instrument Disclosed is a pianoforte instrument comprising a musical mechanism with keys. Also provided are strings which are struck via a mechanism when the keys are actuated and are made to vibrate. The vibrations of the strings are transmitted to a sound board. A device is provided for delivering additional oscillating energy into the sound board. Also provided are sensors which directly or indirectly detect actuation of the keys of the musical mechanism. The measured values of the sensors are fed to a sound-amplifying device. The sound-amplifying device is equipped with units which compile data corresponding to a desired characteristic sound in accordance with the measured values of the sensors. The sound amplifying device supplies the sound board with additional oscillation energy via the delivering device according to the determined data.
US07786372B2	Wind musical instrument with pitch changing mechanism and supporting system for pitch change Three valve assemblies are linked with finger buttons and inserted into a pipe structure of a trumpet for changing the length of air column, and a supporting system assists a player in fingering on the finger buttons; sensors are adhered to the finger buttons so as to supply a detecting signal representative of force exerted on the finger buttons by the player to a controlling unit; when the force exceeds over a threshold, the controlling unit energizes actuators connected to the valve assemblies so as to make the player feel the valve assemblies lightly changed.
US07786371B1	Modular system for MIDI data Rack mountable, user-programmable electronic modules are disclosed that may be used separately, or combined into an integrated system, to analyze, display, troubleshoot, or perform signal conversion on contents or a Musical Instrument Data Interface (MIDI) data stream. Signal conversion capabilities include conversion from a standard MIDI unbalanced current-driven signal format to other electronic forms, such as a balanced differential voltage format, or optical fiber or wireless media formats, that are more suitable for longer distance transmission, and include conversion from a format suitable for long distance back to a standard MIDI format. Custom, remotely controllable dimmer packs responsive to MIDI messages also provide verification and operating condition data, as may be useful in controlling and monitoring lights, pyrotechnics, lasers, fountains, music, and other elements of an animated display or entertainment show, back to a computer which may also be running custom software of the instant invention.
US07786368B2	Actuator unit for performance operator, keyboard musical instrument and actuator unit assembly An actuator unit includes: a performance operator drive device including a movable member that mechanically drives the performance operator member; an optical pattern having a pattern to cause an amount of light reflection or light transmission to gradually vary in accordance with movement of the movable member; and an optical sensor that irradiates light toward the optical pattern and receives light reflected from or transmitted through the optical pattern. One of the optical pattern and the optical sensor is provided to move in interlocked relation to the movable member, and the amount of the reflected light or transmitted light, based on the optical pattern, is detected by the optical sensor, so that a moving position of the movable member is detected on the basis of the detected amount of the reflected or transmitted light.
US07786366B2	Method and apparatus for universal adaptive music system The present invention is method and apparatus for assistive music performance. More specifically, the present invention is an interactive wireless music apparatus comprising actuating an event originating on a remote wireless device. The transmitted event received by a processing host computer implements the proper handling of the event.
US07786365B1	Sound shoe The present invention relates to the foot operated musical instruments like tambourine, cymbals, jingles and cowbells. These musical instruments can be operated by using one or both feet at the same time. The tambourine playing shoes can be converted to a percussion shoe very easily. The foot operated instruments of the present invention lets musicians to play multiple instruments at the same time, while giving a new found sound to a musician's tapping foot.
US07786364B2	Percussion musical instrument A percussion musical instrument comprises a beating surface (13) fastened to a shell (2), the shell (2) comprises at least two, preferably three or more, hollow shells (4) telescopically coupled to each other and movable along a common axis (X) of translation at least between a closed configuration in which a hollow body contains at least partially the next hollow body and an open configuration in which the hollow bodies are substantially superposed.
US07786363B1	Annular drum hoop for a drum An annular drum hoop for a drum having a cylindrical drum shell, two drumheads and multiple tension control devices and the annular drum hoop has an outer ring, a mounting segment, an inner ring, multiple holding mounts and a curved segment. The mounting segment is formed on the outer ring. The inner ring is formed annularly on the mounting side of the annular drum hoop and is formed with the mounting segment. The holding mounts are formed on the annular drum hoop between the mounting segment and the inner ring at intervals and each holding mount has a through hole formed through the holding mount to mount on one of the tension control devices. The curved segment is formed on and protrudes inwards from the free edge of the outer ring and has an inner surface, a curved outer surface and an engaging groove formed in the inner surface.
US07786362B1	Pick for stringed musical instruments A musician's pick having a pick body made up of both a pick portion and a gripping portion. The pick portion and gripping portion are angularly oriented with respect to each other in a predetermined manner. The predetermined angular orientation between the pick portion and the grip portion of the pick allows the pick portion to engage the strings of an instrument being played in a generally perpendicular relation despite the normal, parallel relation between the strings and the longitudinal axis of the musician's thumb.
US07786359B2	Plants and seeds of corn variety CV602114 According to the invention, there is provided seed and plants of the corn variety designated CV602114. The invention thus relates to the plants, seeds and tissue cultures of the variety CV602114, and to methods for producing a corn plant produced by crossing a corn plant of variety CV602114 with itself or with another corn plant, such as a plant of another variety. The invention further relates to corn seeds and plants produced by crossing plants of variety CV602114 with plants of another variety, such as another inbred line. The invention further relates to the inbred and hybrid genetic complements of plants of variety CV602114.
US07786358B2	Tomato plant line TZ367 The present invention relates to a new and distinct inbred tomato lines and hybrids. This invention also relates to plants and seeds of such inbred tomato lines and hybrids, and to parts thereof. The invention also relates to methods for producing a tomato plant produced by crossing such inbred tomato lines and hybrids with themselves or other tomato plants.
US07786357B2	Soybean cultivar 6819331 A soybean cultivar designated 6819331 is disclosed. The invention relates to the seeds of soybean cultivar 6819331, to the plants of soybean 6819331, to plant parts of soybean cultivar 6819331 and to methods for producing a soybean plant produced by crossing soybean cultivar 6819331 with itself or with another soybean variety. The invention also relates to methods for producing a soybean plant containing in its genetic material one or more transgenes and to the transgenic soybean plants and plant parts produced by those methods. This invention also relates to soybean cultivars or breeding cultivars and plant parts derived from soybean variety 6819331, to methods for producing other soybean cultivars, lines or plant parts derived from soybean cultivar 6819331 and to the soybean plants, varieties, and their parts derived from use of those methods. The invention further relates to hybrid soybean seeds, plants and plant parts produced by crossing the cultivar 6819331 with another soybean cultivar.
US07786354B2	Compositions and methods of increasing stress tolerance in plants The present invention provides novel isolated FT polynucleotides and polypeptides encoded by the FT polynucleotides. Also provided are the antibodies that immunospecifically bind to a FT polypeptide or any derivative, variant, mutant or fragment of the FT polypeptide, polynucleotide or antibody. The invention additionally provides methods of constructing transgenic plants that have altered levels of FT polynucleotides and polypeptides.
US07786351B2	Recombinant DNA constructs and methods for controlling gene expression The present invention provides molecular constructs and methods for use thereof, including constructs including heterologous miRNA recognition sites, constructs for gene suppression including a gene suppression element embedded within an intron flanked on one or on both sides by non-protein-coding sequence, constructs containing engineered miRNA or miRNA precursors, and constructs for suppression of production of mature microRNA in a cell. Also provided are transgenic plant cells, plants, and seeds containing such constructs, and methods for their use. The invention further provides transgenic plant cells, plants, and seeds containing recombinant DNA for the ligand-controlled expression of a target sequence, which may be endogenous or exogenous. Also disclosed are novel miRNAs and miRNA precursors from crop plants including maize and soy.
US07786345B2	Transgenic plants expressing cellulase for autohydrolysis of cellulose components and methods for production of soluble sugar The present invention relates to transgenic plants for producing cellulose by a mechanism of autohydrolysis and a method producing soluble sugars using them, more particularly to transgenic plants transformed with recombinant cDNA coding cellulase, cellulose binding domain and chloroplast targeting peptide and a method producing soluble sugars using them. Transgenic plants and a method producing soluble sugars using them would be a highly cost-effective system for the production of soluble sugars on a large scale.
US07786330B2	Process for producing 1,2-dialkoxy-3-fluorobenzene The present invention relates to a process for producing a 2-fluoro-6-halophenol as an intermediate; a process for producing a 2-alkoxy-3-fluorophenol and further a 1,2-dialkoxy-3-fluorobenzene from the 2-fluoro-6-halophenol; a second process for producing a 1,2-dialkoxy-3-fluorobenzene from the 2-fluoro-6-halophenol; and a 2-alkoxy-3-fluorophenol. The 2-fluoro-6-halophenol can be obtained using a 2-fluorophenol as a starting material and through a sulfonation reaction, a halogenation reaction, and a deprotection reaction. The 2-fluoro-6-halophenol is alkyl-etherified, and subsequently the halogen atom is converted into a hydroxyl group to obtain the 2-alkoxy-3-fluorophenol, which is further alkyl-etherified to thereby obtain the 1,2-dialkoxy-3-fluorobenzene. Alternatively, a 1,2-dialkoxy-3-fluorobenzene is also obtained by converting the halogen atom of the 2-fluoro-6-halophenol into a hydroxyl group to thereby form 3-fluorocatechol and subsequently alkyl-etherifying two hydroxyl groups thereof. The processes of the invention realize low production costs and high process yields, and thus are suitable for industrial production of a 1,2-dialkoxy-3-fluorobenzene.
US07786329B2	Process for preparing ester oxazolidine compounds and their conversion to Florfenicol A process for preparing ester oxazolidine compounds is disclosed. These compounds are useful intermediates in processes for making Florfenicol.
US07786327B2	Method for co-producing electric power and urea from carbonaceous material A method for co-producing electric power and urea from carbonaceous fuels such as coal, by pyrolizing the coal with oxygen to produce a raw rich gas and a hot char which is gasified with air to produce a raw lean gas. Subsequent to the cleaning of the two gases, the cleaned rich gas is made up of CO and 2H2, and the clean lean gas is made up of N2+CO. The CO in the rich gas is separated from the 2H2 and is added to the lean gas to enrich it with CO to become a lean fuel gas which fuels a gas turbine and is part of a combined cycle system which efficiently generates electric power while exhausting an off-gas (flue gas) made up of N2+CO2. The 2H2 separated from the CO, and the N2+CO2 of the exhausted flue gas are together synthesized to produce urea —CO(NH2)2. To augment the 2H2 in order to make the process more efficient, steam is extracted from the power generation system, mixed with the 2H2, and electrolyzed in a high-temperature electrolysis system prior to the synthesis step with the electrical energy required for the electrolysis being derived from the combined cycle power generation source. This approach will consume the CO2 in a beneficial manner by co-producing an added-value, useful by-product while at the same time obviating the necessity of collecting CO2 and sequestering it, which is an inefficient way of mitigating the effect of global warming caused by CO2.
US07786326B2	Polyacylurethanes based on diisocyanates and polyesterpolyols The present invention relates to a polyacylurethane having the following general formula (I) and a process for the preparation of such polyacylurethane. Preferred embodiments of the polyacylurethanes according to the invention have elastomeric properties. The polyacylurethanes can suitable be used in biodegradable, biocompatible and/or biomedical devices.
US07786325B2	Process for producing O-methyl-N-nitroisourea Disclosed is an industrially advantageous process for producing O-methyl-N-nitroisourea. Disclosed is a process for obtaining O-methyl-N-nitroisourea represented by the following chemical formula (1) or a salt thereof in a high yield by performing the nitration of O-methylisourea represented by the following chemical formula (2) or a salt thereof with nitrating agents in the presence of fuming sulfuric acid.
US07786324B2	Method for producing borazine compound In a synthesis of a borazine compound by a reaction of an alkali boron hydride represented by ABH4 (A represents lithium atom, sodium atom or potassium atom) and an amine salt represented by (RNH3)nX (R represents a hydrogen atom or an alkyl group, X represents a sulfate group or a halogen atom, and n is 1 or 2), or b) diborane (B2H6) and an amine represented by RNH2 (R represents a hydrogen atom or an alkyl group), a water content of raw material is controlled below a prescribed value; mixed solvents containing solvents each having a prescribed boiling point are used as a solvent for reaction; or a raw material is gradually fed to a reactor in a reaction. Or, a borazine compound is subjected to distillation purification treatment and filtration treatment. By such a method, a high purity of borazine compound can be produced safely and in a high yield.
US07786322B2	Salt suitable for an acid generator and a chemically amplified resist composition containing the same The present invention provides a salt of the formula (I): wherein ring X represents monocyclic or polycyclic hydrocarbon group having 3 to 30 carbon atoms, and one or more hydrogen atom in the monocyclic or polycyclic hydrocarbon group is optionally substituted with alkyl group having 1 to 10 carbon atom, alkoxy group having 1 to 10 carbon atom, perfluoroalkyl group having 1 to 4 carbon atoms, hydroxyalkyl group having 1 to 10 carbon atoms or cyano group; Q1 and Q2 each independently represent fluorine atom or perfluoroalkyl group having 1 to 6 carbon atoms; and A+ represents organic counter ion. The present invention also provides a chemically amplified resist composition comprising the salt of the formula (I).
US07786315B2	Process for selectively extracting procyanidins A process is described for selectively extracting cocoa procyanidins from an aqueous mixture of cocoa polyphenols by using a particular sequence of solvents to extract selected procyanidin monomers and/or oligomers. The solvents are n-butyl acetate, ethyl acetate, methyl acetate, diethyl ether, or mixtures of methyl acetate and diethyl ether. Preferably, the aqueous mixture of cocoa polyphenols is first extracted with n-butyl acetate. The mixtures of methyl acetate and diethyl ether are between 25:75 and 75:25 (v/v).
US07786310B2	Small molecule transcriptional activation domains The present invention relates to gene regulation. In particular, the present invention provides small molecule activation domain compositions and methods of making the same. The present invention further provides methods of regulating gene expression using the novel activation domains. The invention also provides methods of screening small molecule/compound libraries for identifying ligands of a protein or molecule of interest.
US07786306B2	Process for resolving chiral piperidine alcohol and process for synthesis of pyrazolo[1,5-a] pyrimidine derivatives using same The present invention provides a method of resolving piperdin-yl-alkylene-alcohols, in high yield at high enantiomeric purity, for example 2-piperidin-2-yl-ethanol.
US07786305B2	Tetrahydropyranyl cyclopentyl tetrahydropyridopyridine modulators of chemokine receptor activity The present invention is directed to compounds of the formula I: (wherein R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, X, n and the dashed line are defined herein) which are useful as modulators of chemokine receptor activity. In particular, these compounds are useful as modulators of the chemokine receptor CCR-2. The present invention is also directed to intermediates useful in the preparation of formula I compounds.
US07786303B2	Acidic bath for electrolytically depositing a copper deposit containing halogenated or pseudohalogenated monomeric phenazinium compounds For manufacturing particularly uniform and mirror bright copper coatings that are leveled and ductile as well using a relatively high current density, halogenated or pseudohalogenated monomeric pheanzinium compounds or a purity at least 85 mole-% and having the general chemical formula (I) are utilized in which R1, R2, R3, R4, R7′, R7″, R8, R9, X and A have the significations denoted in the claims. The compounds are prepared by diazotizing a suited starting compound prior to halogenating or pseudohalogenating it in the presence of mineral acid, diazotization means and halide or pseudohalide, with the reaction steps being run in one single vessel.
US07786294B2	Compositions and methods for amplification and cloning of near full-length viral genome samples A method of producing a polydeoxyribonucleotide molecule by reverse transcriptase polymerase chain reaction wherein the polydeoxyribonucleotide molecule has a length of greater than 5,000 base-pairs is disclosed. The method involves combining two reverse transcriptases followed by two protocols of polymerase chain reaction. This method enable the amplification of large DNAs, such as viruses, from a sample while preserving genetic diversity of the large DNA.
US07786293B2	Organic compounds The present invention provides a process for the sulfurization of phosphorus-containing compounds. More particularly, the process involves contacting the compound to be sulfurized with a sulfur transfer reagent as defined hereinbefore in a solvent or a mixture of solvents.
US07786287B2	Hepatitis C virus assay systems The present invention features assays employing a beta-lactamase reporter system, an HCV replicon enhanced cell, and/or a chimeric HCV replicon containing a 3′ UTR based on the HCV-1a 3′ UTR. These features can be employed alone or together, and are preferably combined together to measure HCV replicon activity and the affect of compounds on such activity.
US07786286B2	Proteinase K resistant surface protein of Neisseria meningitidis The identification of a highly conserved, immunologically accessible antigen at the surface of Neisseria facilitates treatment, prophylaxis, and diagnosis of Neisseria diseases. This antigen is highly resistant to Proteinase K and has an apparent molecular weight of 22 kDa on SDS-PAGE. Specific polynucleotides encoding proteins of this class have been isolated from three Neisseria meningitidis strains and from one Neisseria gonorrhoeae strain. These polynucleotides have been sequenced, and the corresponding full-length amino acid sequences of the encoded polypeptides have been deduced. Recombinant DNA methods for the production of the Neisseria surface protein, and antibodies that bind to this protein are also disclosed.
US07786285B2	Recombinant vaccine against botulinum neurotoxin This invention is directed to preparation and expression of synthetic genes encoding polypeptides containing protective epitopes of botulinum neurotoxin (BoNT). The invention is also directed to production of immunogenic peptides encoded by the synthetic genes, as well as recovery and purification of the immunogenic peptides from recombinant organisms. The invention is also directed to methods of vaccination against botulism using the expressed peptides.
US07786284B2	Polynucleotides encoding IL-17 receptor A antigen binding proteins The present invention relates to IL-17 receptor A (IL-17RA or IL-17R) antigen binding proteins, such as antibodies, and the polynucleotide sequences encoding them, as well as host cells, expression vectors, and methods of making IL-17 receptor A antigen binding proteins.
US07786283B2	BRI constructs and methods of using The invention provides constructs that feature a nucleic acid molecule encoding an amino terminal region of a BRI polypeptide. A construct of the invention can further include a multiple cloning site joined to the 3′ end of the BRI nucleic acid molecule or a nucleic acid molecule encoding a heterologous polypeptide operably linked to the BRI nucleic acid molecule. The invention further provides methods of directing a heterologous polypeptide through the secretory pathway in a cell. Such methods utilize a construct of the invention that additionally contains a promoter that directs expression of the BRI and heterologous nucleic acid molecules. The construct is introduced into a cell and, following expression, the fusion protein is directed through the secretory pathway of the cell. In addition, a construct of the invention can be introduced into an animal to make the animal transgenic for the heterologous polypeptide.
US07786277B2	Methods for introducing mannose 6-phosphate and other oligosacharides onto glycoproteins Methods to introduce highly phosphorylated mannopyranosyl oligosaccharide derivatives containing mannose 6-phosphate (M6P), or other oligosaccharides bearing other terminal hexoses, to carbonyl groups on oxidized glycans of glycoproteins while retaining their biological activity are described. The methods are useful for modifying glycoproteins, including those produced by recombinant protein expression systems, to increase uptake by cell surface receptor-mediated mechanisms, thus improving their therapeutic efficacy in a variety of applications.
US07786276B2	Sequestering of glycoprotein molecules and oligosaccharide moieties in lipo-glycoprotein membranes and micelles Spontaneous formation of a coherent membrane at the interface between a non-polar liquid and an aqueous solution of glycoprotein can be used to separate proteins and carbohydrates from tissue fluid and other complex mixtures. When volatile hydrocarbons are used to induce membrane formation, evaporation of organic and aqueous solvents leaves behind a delicate film or powder. The method for extracting glycoprotein from solution and sequestering it in floating membranes can be used to study environmental conditions or to remove carbohydrates from proteins in the tissues of living organisms. This technique can also be used for detecting proteins in solutions.
US07786270B2	Humanized FcγRIIB-specific antibodies and methods of use thereof The present invention relates to humanized FcγRIIB antibodies, fragments, and variants thereof that bind human FcγRIIB with a greater affinity than said antibody binds FcγRIIA. The invention encompasses the use of the humanized antibodies of the invention for the treatment of any disease related to loss of balance of Fc receptor mediated signaling, such as cancer, autoimmune and inflammatory disease. The invention provides methods of enhancing the therapeutic effect of therapeutic antibodies by administering the humanized antibodies of the invention to enhance the effector function of the therapeutic antibodies. The invention also provides methods of enhancing the efficacy of a vaccine composition by administering the humanized antibodies of the invention. The invention encompasses methods for treating an autoimmune disease and methods for elimination of cancer cells that express FcγRIIB.
US07786258B2	Methods for inhibiting immune complex formation in a subject Polypeptides and other compounds that can bind specifically to the CH2-CH3 cleft of an immunoglobulin molecule, and methods for using such polypeptides and compounds to inhibit Fc-mediated immune complex formation, are described.
US07786252B2	Preparation of transparent multilayered articles Disclosed is a process for the preparation of multilayered, shaped articles having high transparency and low haze having at least one layer contains one or more thermoplastic polymers selected from polyesters, polycarbonates, and homogeneous blends thereof, and a separate layer which contains a transamidized, homogeneous blend of a least two polyamides. The thermoplastic polymer components and the polyamide components have refractive indices which differ by about 0.006 to about −0.0006. The small difference in the refractive indices enable the incorporation of regrind into one or more of the layers of the article while maintaining high clarity. These articles can exhibit improved excellent barrier properties and good melt processability while retaining excellent mechanical properties. Metal catalysts can be incorporated into one or more layers to impart oxygen-scavenging properties.
US07786251B2	Process for producing polyester ether poly- or mono-ol To provide a process for producing a polyester ether poly- or mono-ol having a narrow molecular weight distribution, which is obtained by copolymerizing an initiator having hydroxyl groups with a cyclic ester compound and an alkylene oxide.It is possible to produce a polyester ether poly- or mono-ol having a molecular distribution (Mw/Mn) of from 1.02 to 1.4 by copolymerizing a cyclic ester compound which carbon number is from 3 to 9 and an alkylene oxide which carbon number is from 2 to 20 with an initiator having from 1 to 12 hydroxyl groups and having a number average molecular weight (Mn) of from 18 to 20,000 in the presence of a double-metal cyanide complex catalyst is having tert-butyl alcohol as at least a part of an organic ligand.
US07786250B2	Vector directional polymer systems and methods of nano-structural self assembly Vector-directional polymers and polymer systems are disclosed. In accordance with the embodiments of the invention, the polymer has aromatic moieties that are restrained or fixed through conformational linkage units bonding nearest neighbor aromatic moieties together to form the polymer backbone. The conformational linkage units preferably include conformational ring structures which exhibit hydrogen bonding or other Lewis acid-Lewis base type of interactions. The conformational ring structures can include hetero-atoms and cationic metal atoms. The chemical groups and bonding features of the polymer backbone constrain bond movement and bond rotation along the polymer backbone. Accordingly, the vector-directional polymers of the present invention can assemble into or form extended three dimensional structures or arrays.
US07786248B2	Underfill compositions and methods for use thereof The invention is based on the discovery that certain polyester-linked compounds are useful as components in underfill compositions for the microelectronic packaging industry.
US07786245B2	Process for preparing polyarylene ether ketone A process for preparing a polyarylene ether ketone, comprising: a) reacting an aromatic dihalogen compound with a bisphenol and/or a halophenol in the presence of alkali metal carbonate and/or alkaline earth metal carbonate in a high-boiling aprotic solvent to give a polyarylene ether ketone, b) wet-comminuting the solidified reaction mixture in the presence of water, c) washing with an organic solvent, d) washing with water and e) drying the washed product, wherein the wet-comminuted reaction mixture is fed to the two-stage washing with a residual moisture content of at least 1% by weight, which process leads to distinctly reduced residual contents of salts and reaction solvents.
US07786239B2	Modified vegetable oil-based polyols Methods of making unsaturated modified vegetable oil-based polyols are described. Also described are methods of making oligomeric modified vegetable oil-based polyols. An oligomeric composition having a modified fatty acid triglyceride structure is also described. Also, methods of making a polyol including hydroformylation and hydrogenation of oils in the presence of a catalyst and support are described.
US07786237B2	Polyethylene materials prepared using mixed ziegler-natta catalysts systems A polyethylene may be prepared using a mixture of a silica supported catalyst and a magnesium chloride supported catalyst. By changing the ratio of the two catalysts, the polyethylene produced may have a varying bulk density and shear response. The method allows for the tuning or targeting of properties to fit a specific application, such as a blow molding or vapor barrier film.
US07786236B2	Polymeric nano-particles of flower-like structure and applications A flower-like nano-particle composition including a poly(alkenylbenzene) core and a poly(conjugated diene) or a poly(alkylene) surface layer is provided. The nano-particles have a mean average diameter less than about 100 nm and are substantially free of chain ends. The nano-particles can be modified via, for example, hydrogenation. The nano-particles can advantageously be incorporated into rubbers, elastomers, and thermoplastics.
US07786230B2	Method for polymerizing cycloolefin polymer containing polar functional groups and electronics devices employing the polymerized cycloolefins Disclosed is a method for preparing a cycloolefin polymer containing polar functional groups, comprising the steps of: a) preparing a catalyst mixture including i) a precatalyst; ii) a first cocatalyst; and iii) a second cocatalyst; and b) subjecting a monomer solution comprising a norbornene-based compound containing a polar functional group to an addition polymerization reaction in the presence of an organic solvent and the catalyst mixture, wherein the product yield of the prepared polymer is 50% by weight or more based on the total weight of the monomer.
US07786227B2	Monomer concentration prediction and control in a polymerization process A method for the control of a polymerization process, which method employs the combination of a densitometer measurement of the polymerization reaction mixture and a quadratic computer model.
US07786225B2	Curable resin composition A curable resin composition, which is a solid resin at ordinary temperatures obtained by reacting an epoxy resin with a (meth)acrylic anhydride, contains an unsaturated resin having a (meth)acryloyl group (A) which has a double bond equivalent weight of 200 to 500, an ester number of 100 to 300, and a hydroxyl number of no more than 130, an ethylenically unsaturated monomer (B), and a radical polymerization initiator (C).
US07786223B2	Epoxy resin and curing agent of di- and/or mono-glycidyether/monoamine-polyamine reaction product A curable composition comprising a) an epoxy resin containing on average more than one epoxy group per molecule, and b) as curing agent a composition comprising b1) 40-100 wt % of a reaction product from the reaction of b1a) at least one diglycidyl- and/or at least one monoglycidylether with b1b) a composition comprising a volatile monoamine and a polyamine, said composition b1b) is used in an amount to provide an excess amino groups relative to epoxy groups from b1a), and whereby the excess of monoamine is removed off from the reaction product, b2) 0-60 wt % of a polyamine, and b3) 0-25 wt % of a polyphenol novolac, and whereby the sum of components b1), b2) and b3) is 100 wt %, providing long pot life combined with fast cure times at low temperatures, thus making said compositions especially useful for marine and offshore coatings, industrial maintenance, construction, tank and pipe linings, adhesive, automobile and electrical potting applications.
US07786222B2	Polyamide oligomers and their use The present invention relates to polyamide oligomers with linear or branched chain structure with a number average molar mass of 800 to 5000 g/mol, with basic end groups which are at least partially NH2 end groups and carboxyl end groups, produced by condensation of polyamide-forming monomers, the concentration of NH2 end groups being at most 300 mmol/kg and in that these end groups are present in excess in a ratio to the carboxyl end groups.
US07786215B2	Thermoplastic polymer, use thereof in polyamide compositions with improved hydrophily and anti-staticity The invention provides a novel thermoplastic polymer comprising at least one polyalkylene oxide block. It relates to a process for preparing the thermoplastic polymer and to an application of this polymer as a hydrophilicity and/or antistatic modifier, especially in polyamide compositions. These compositions are particularly suitable for the manufacture of yarns, fibres and filaments.
US07786209B2	Nanostructured particles, phase change inks including same and methods for making same A hydrophobically- or hydrophilically-functionalized polyhedral oligomeric silsesquioxane has the following formula: where each R, which can be the same or different, independently represents a linear, branched or cyclic organic group selected from the group consisting of hydrophobic alkyl groups, hydrophobic aryl groups, hydrophobic arylalkyl groups, hydrophobic cycloaliphatic groups, and hydrophilic organic moieties, provided that at least one of the R groups is a wax-like aliphatic group.
US07786206B2	Thermoplastic resin composition A thermoplastic resin composition comprising: (A) 30 to 80 parts by mass of a polyamide; (B) 20 to 70 parts by mass of a polyphenylene ether; (C) 0 to 40 parts by mass, based on 100 parts by mass of the total amount of the polyamide (A) and the polyphenylene ether (B), of a rubbery polymer; and (D) 10 to 50 parts by mass, based on 100 parts by mass of the total amount of the polyamide (A) and the polyphenylene ether (B), of a platy inorganic filler having an average particle size of 9 to 20 μm, and having a particle size ratio (d75%/d25%) of the particle size (d75%) at 75% counted from smaller particle size to the particle size (d25%) at 25% of 1.0 or more and 2.5 or less.
US07786205B2	Foamable adhesive composition A foamable copolymer based coupling is provided for securely affixing a light emitting glass lamp in a metal base to form a lamp assembly. The copolymer is preferably selected from ethylene vinyl acetate, ethylene methyl acrylate, and combinations thereof. The foamable coupling may be placed around one end of the glass lamp or in the lamp base before the lamp and base are matingly engaged. The assembled lamp is then heated to a temperature, which causes the foamable coupling to expand and securely affix the lamp in the base.
US07786201B2	Mixture of diisononyl esters of 1,2-cyclohexanedicarboxylic acid, method for the production thereof and use of these mixtures The present invention relates to a mixture of diisononyl esters of 1,2-cyclohexanedicarboxylic acid, wherein the isononyl radicals of the diisononyl esters present in the mixture have a degree of branching of from 1.2 to 2.0, to a process for its preparation and to the use of such mixtures.
US07786197B2	Flame retardant resin composition and molded articles thereof A flame retardant resin composition consisting essentially of: (A) 100 parts by weight of the total of resin components (components A) which include at least 60 wt % of an aromatic polyester resin; (B) an organic phosphorus compound (component B-1) represented by the following general formula (1) and having an acid value of 0.7 mgKOH/g or less or an organic phosphorus compound (component B-2) represented by the following general formula (2); (C) 0 to 50 parts by weight of a flame retardancy improving resin (component C); and (D) 0 to 200 parts by weight of a filler (component D), and a molded article thereof. Wherein, when the organic phosphorus compound is the component B-1, the amount of the component B-1 is 1 to 100 parts by weight and when the organic phosphorus compound is the component B-2, the component B-2 is used in combination with a biscumyl compound (component B-3), the amount of the component B-2 is 5 to 30 parts by weight, and the amount of the component B-3 is 0.01 to 5 parts by weight. According to the present invention, there can be obtained a flame retardant polyester resin composition which contains substantially no halogen and has UL-94 V-2 flame retardancy or V-0 flame retardancy under favorable conditions as well as a molded article thereof.
US07786194B2	Compositions and methods for protecting materials from damage Certain exemplary embodiments comprise a composition prepared from a Class 1 member, a Class 2 member, and a Class 3 member, said Class 1 member contributing approximately 0.1 percent to approximately 10 percent by dry weight of said composition, said Class 2 member contributing approximately 1 percent to approximately 10 percent by dry weight of said composition, and said Class 3 member contributing an amount up to a balance by dry weight of said composition.
US07786193B2	Thermoplastic stiffening material used for manufacturing shoes, and a method for the production thereof The invention relates to a novel thermoplastic stiffening material used for manufacturing shoes or shoe parts, and to an environmentally friendly method for the production thereof. The inventive material is proved in the form of a hot-melt adhesive/filling compound and is characterized in that it is comprised of one or more hot-melt adhesives and of one or more fillers, which are provided in quantities ranging from 50 to 15% by weight and which do not dissolve in the hot-melt adhesive. The hot-melt adhesive/filler compound simultaneously fulfills the following parameters: 1. MVR value between 2 and 6, preferably between 3 and 5 cm3/10 min; 2. Surface tack, when measured according to DIN EN 14610 at 65° C., ranging from at least 10 N/2 cm, preferably 15 N/2 cm, particularly 20 N/2 cm; 3. Bonding value/peel resistance with regard to upper materials and linings of at least 30 N/5 cm when measured according to DIN 53357; 4. Longitudinal extension of no greater than 25%, preferably less than 20%, when measured at a temperature of 90° C.
US07786186B2	Optically transparent polymer with antibiofouling properties Optically transparent, impact-resistant solid polymer bodies are provided that are resistant to fouling by organisms such as algae, bacteria and molds. The bodies may be sheets of polymer for use as covers for optical sensors, windows or other cover glasses. The materials may be formed by solvent casting, extrusion or other processing methods.
US07786185B2	Wettable hydrogels comprising acyclic polyamides The present invention relates to biomedical devices, and particularly contact lenses comprising a polymer having entangled therein at least one acyclic polyamide.
US07786180B2	Methanol synthesis A process for synthesising methanol comprises the steps of: (i) reforming a hydrocarbon feedstock and separating water to generate a make-up gas comprising hydrogen and carbon oxides, the make-up gas mixture having a stoichiometric number, R, R=([H2]−[CO2])/([CO2]+[CO]) of less than 2.0, (ii) combining the make up gas with an unreacted synthesis gas to form a synthesis gas mixture, (iii) passing the synthesis gas through a bed of methanol synthesis catalyst to generate a product stream, (iv) cooling the product stream to recover a crude methanol stream from the unreacted synthesis gas, (v) removing a portion of the unreacted synthesis gas as a purge gas, and (vi) feeding the remaining unreacted synthesis gas to step (ii), wherein hydrogen is recovered from a portion of the purge gas and the make up gas, and the recovered hydrogen is included in the synthesis gas mixture.
US07786177B2	Phenylalanine enamide derivatives Phenylalanine enamide derivatives of formula (1) are described: wherein R1 is a group Ar1 L2Ar2Alk- in which: Ar1 is an optionally substituted aromatic or heteroaromatic group; L2 is a covalent bond or a linker atom or group; Ar2 is an optionally substituted arylene or heteroarylene group; and Alk is a chain —CH2—CH(R)—, —CH═C(R)— or in which R is a carboxylic acid (—CO2H) or a derivative or biostere thereof; X is an —O— or —S— atom or —N(R2)— group in which: Rx, Ry and Rz which may be the same or different is each a hydrogen atom or an optional substituent; or Rz is an atom or group as previously defined and Rx and Ry are joined together to form an optionally substituted spiro linked cycloaliphatic or heterocycloaliphatic group; and the salts, solvates, hydrates and N-oxides thereof. The compounds are able to inhibit the binding of integrins to their ligands and are of use in the prophylaxis and treatment of immuno or inflammatory disorders or disorders involving the inappropriate growth or migration of cells.
US07786171B2	Amide derivatives as positive allosteric modulators and methods of use thereof The invention relates to novel amide derivatives that are positive allosteric modulators of neuronal nicotinic receptors, compositions comprising the same, processes for preparing such compounds, and methods for using such compounds and compositions.
US07786169B2	Phenoxyalkycarboxylic acid derivatives in the treatment of ulcerative colitis A method of treating ulcerative colitis in a patient suffering therefrom comprising: administering an effective amount of a compound selected from compound 1, its metabolite 2 and pharmaceutically acceptable salts or esters thereof:
US07786165B2	Aminophenylpropanoic acid derivative A compound represented by the formula (1): wherein each symbol is as defined in the specification, and a salt thereof and a prodrug thereof unexpectedly have superior GPR40 receptor agonist activity, superior in the properties as a pharmaceutical product such as stability and the like, and can be a safe and useful pharmaceutical agent as a drug for the prophylaxis or treatment of GPR40 receptor related pathology or diseases such as diabetes and the like.
US07786164B2	Lipophilic di(anticancer drug) compounds, compositions, and related methods Lipophilic di(anticancer drug) compounds, compositions that include the compounds, and methods for treating a cell proliferative disease using the compounds.
US07786162B2	Agents useful for reducing amyloid precursor protein and treating dementia and methods of use thereof The present invention provides compounds and methods of administering compounds to a subject that can reduce βAPP production and that is not toxic in a wide range of dosages. The present invention also provides non-carbamate compounds and methods of administering such compounds to a subject that can reduce βAPP production and that is not toxic in a wide range of dosages. It has been discovered that either the racemic or enantiomerically pure non-carbamate compounds can be used to decrease βAPP production.
US07786159B2	Thrombopoietin mimetics The invention relates to compounds and their use in the treatment of thrombocytopenia resulting from diseases or conditions such as immune thrombocytopenic purpura, cancer chemotherapy, surgery, bone marrow or stem cell transplantation, radiation injury or treatment, chronic viral infection, and pancytopenia. The invention further relates to pharmaceutical compositions containing the compounds and compositions of the invention as well as methods for treating such diseases or conditions in a mammal, including a human, by administering to such mammal an effective amount of a selected thrombopoietin receptor agonist.
US07786154B2	Substituted gamma lactams as therapeutic agents A compound having the formula or a pharmaceutically acceptable salt or a prodrug thereof is disclosed herein. Y, A, and B are as described herein. Methods, compositions, and medicaments related to these compounds are also disclosed.
US07786151B2	Therapeutic composition of treating abnormal splicing caused by the excessive kinase induction The present invention provides a composition of treating, preventing abnormal splicing caused by the excessive kinase induction, which comprises TG003 and a method using the same of treating, preventing abnormal splicing caused by the excessive kinase induction.
US07786149B2	Thiadiazoles as CXC- and CC- chemokine receptor ligands Disclosed are novel compounds of the formula: and the pharmaceutically acceptable salts and solvates thereof. Examples of groups comprising Substituent A include heteroaryl, aryl, heterocycloalkyl, cycloalkyl, aryl, alkynyl, alkenyl, aminoalkyl, alkyl or amino. Examples of groups comprising Substituent B include aryl and heteroaryl. Also disclosed is a method of treating a chemokine mediated diseases, such as, cancer, angiogenisis, angiogenic ocular diseases, pulmonary diseases, multiple sclerosis, rheumatoid arthritis, osteoarthritis, stroke and ischemia reperfusion injury, pain (e.g., acute pain, acute and chronic inflammatory pain, and neuropathic pain) using a compound of formula IA.
US07786148B2	Fungicidal composition comprising a pyridylethylbenzamide derivative and a compound capable of inhibiting the transport of electrons of the respiratory chain in phytopathogenic fungal organisms A composition comprising at least a pyridylethylbenzamide derivative of general formula (I) (a) and a compound capable of inhibiting the transport of electrons of the respiratory chain in phytopathogenic fungal organisms (b) in a (a)/(b) weight ratio of from 0.01 to 20. A composition further comprising an additional fungicidal compound. A method for preventively or curatively combating the phytopathogenic fungi of crops by using this composition.
US07786147B2	Analogs of choline for neuroprotection and cognitive enhancement in neurodegenerative disorders The present invention relates to novel analogs of choline and methods of use or treatment of neurodegenerative disorders and/or conditions such as Parkinson's disease, Huntington disease, Alzheimer's disease and related disorders such as amyotrophic lateral sclerosis, spinal muscular atrophy, Friedrich's ataxia, Pick's disease, Bassen-Kornzweig syndrome, Refsom's disease, retinal degeneration, Cruetzfelt-Jacob syndrome or prion disease (mad cow disease), dementia with Lewy bodies, schizophrenia, paraneoplastic cerebellar degeneration and neurodegenerative conditions caused by stroke. The present compounds are effective to treat any neurological condition where acetylcholine transmission neurons and their target cells are affected. Compounds according to the present invention are effective to alleviate and/or reverse the effects of a neurodegenerative condition, prevent further deterioration and/or enhance cognition and memory in patients suffering from neurodegenerative disorders, especially Alzheimer's disease.
US07786146B2	Derivatives of 5-amino-4,6-disubstituted indole and 5-amino-4,6-disubstituted indoline as potassium channel modulators This invention provides compounds of formula I where the dashed line represents an optional double bond; where R1 is phenyl, naphthyl, pyridyl, pyrimidyl, pyrrolyl, imidazolyl, pyrazyl, furyl, thienyl, oxazolyl, isoxazolyl, thiazolyl, or isothiazolyl, optionally substituted, and other substituents are defined herein. Such compounds are potassium channel modulators.
US07786142B2	Heterocyclic compounds as pSTAT3/IL-6 inhibitors The present invention relates to novel heterocyclic compounds of the general formula (I), as IL-6 inhibitors, their derivatives, their analogs, their tautomeric forms, their stereoisomers, their polymorphs, their hydrates, their solvates, their pharmaceutically acceptable salts and compositions, their metabolites and prodrugs thereof. The present invention more particularly provides novel heterocyclic compounds of the general formula (I). Also included is a method for treatment of cancer, cancer cachexia and inflammatory diseases including immunological diseases, particularly those mediated by cytokines such as IL-6, through pSTAT3 inhibition, in a mammal comprising administering an effective amount of a compound of formula (I) as described above
US07786140B2	Piperidine derivative having NMDA receptor antagonistic activity A piperidine derivative of the formula (I) is found to bind specifically with the NR1/NR2B receptor and usable as an analgesic (pain treatment drug). wherein X is OH or lower alkylsulfonyloxy; Ar is optionally substituted aryl or optionally substituted heteroaryl; n is an integer of 1 to 4; m is an integer of 0 to 1; R1 is hydrogen; R2 is OH or R1 and R2 taken together may form a single bond; excluding that 1) n is 2; m is 0; R1 and R2 taken together may form a single bond; and Ar is optionally substituted phenyl and 2) n is 3; m is 0; R1 and R2 taken together may form a single bond; and Ar is phenyl.
US07786138B2	Process for making montelukast and intermediates therefor A compound of the following formula wherein R′ is a straight or branched C1-C4 alkyl group is useful in processes associated with the synthesis of montelukast and its salts.
US07786135B2	Substituted pyrroline kinase inhibitors The present invention is directed to novel substituted pyrroline compounds useful as kinase inhibitors and methods for treating or ameliorating a kinase mediated disorder.
US07786134B2	Lipophilic anticancer drug compounds, compositions and related methods Lipophilic anticancer drug compounds, compositions that include the compounds, and methods for treating a cell proliferative disease using the compounds.
US07786122B2	α-(N-sulfonamido)acetamide derivatives as β-amyloid inhibitors There is provided a series of novel α-(N-sulfonamido)acetamide compounds of the Formula (I) wherein R, R1, R2 and R3 are defined herein, which are inhibitors of β-amyloid peptide (β-AP) production and are useful in the treatment of Alzheimer's Disease and other conditions affected by anti-amyloid activity.
US07786115B2	Amide derivatives The invention concerns a compound of the Formula I wherein m is 0-2 and each R1 is a group such as hydroxy, halogeno, trifluoromethyl heterocyclyl and heterocyclyloxy; R2 is halogeno, trifluoromethyl or (1-6C)alkyl; R3 is hydrogen, halogeno or (1-6C)alkyl; and R4 is (3-6C)cycloalkyl;or pharmaceutically-acceptable salts thereof; processes for their preparation, pharmaceutical compositions containing them and their use in the treatment of diseases or medical conditions mediated by cytokines.
US07786111B2	Medicaments for the treatment of chronic obstructive pulmonary disease A pharmaceutical composition comprising a compound of formula 1 wherein: n is 1 or 2; R1 is hydrogen, C1-C4-alkyl, halogen, OH, or —O—C1-C4-alkyl; R2 is hydrogen, C1-C4-alkyl, halogen, OH, or —O—C1-C4-alkyl; R3 is hydrogen, C1-C4-alkyl, OH, halogen, —O—C1-C4-alkyl, —O—C1-C4-alkylene-COOH, or —O—C1-C4-alkylene-CO—O—C1-C4-alkyl, or an acid addition salt thereof with a pharmacologically acceptable acid, or a solvate or hydrate thereof; and a pharmaceutically acceptable excipient or carrier, and methods for using the pharmaceutical formulation in the treatment of chronic obstructive pulmonary disease (COPD).
US07786106B2	Substituted benzene derivatives or salts thereof There are provided compounds having an anticoagulant action on the basis of inhibition of activated blood coagulation factor X and being useful as anticoagulants or preventive/therapeutic agents for diseases induced by thrombosis or embolism. Effective ingredients are the compounds such as 4′-bromo-2′-[(5-chloro-2-pyridyl) carbamoyl]-6′-β-D-galactopyranosyloxy-1-isopropylpiperidine-4-carboxanilide, 2′-(2-acetamido-2-deoxy-β-D-glucopyranosyloxy)-4′-bromo-6′-[(5-chloro-2-pyridyl)carbamoyl]-1-isopropylpiperidine-4-carboxanilide, etc. or salts thereof.
US07786104B2	N-(aminoheteroaryl)-1H-indole-2-carboxamide derivatives, and preparation and therapeutic application thereof The invention concerns compounds of general formula (I): Wherein n, X1, X2, X3, X4, Y, Z, Z1, Z2, Z3 and Z4 are as defined herein. The invention also concerns a process for the preparation of compounds of formula (I) and their therapeutic use.
US07786103B2	Method for isolating an intestinal cholesterol binding protein The invention describes a method for isolating an intestinal protein which is able to bind cholesterol and/or cholesterol uptake inhibitors.
US07786101B2	Cardiovascular protection using anti-aldosteronic progestins A composition comprises drospirenone as the sole therapeutically active agent.
US07786100B2	Composition and method of treating hearing loss A composition for treating hearing loss includes components that function through different biological mechanisms to provide an additive effect that is greater than the effect of the individual components alone. The composition includes a biologically effective amount of vitamin E for inhibiting propagation of lipid peroxidation that contributes to hearing loss. The composition also includes a biologically effective amount of a salicylate for reducing hydroxyl radicals that contribute to hearing loss. A method of treating hearing loss includes the step of internally administering the composition, as described above, to a mammal within three days of trauma to a middle or inner ear of the mammal. In other words, the composition is effective even when administered as late as three days after trauma to a middle or inner ear of a mammal.
US07786099B2	Aromatic a-ring derivatives of tetracycline compounds Aromatized A-ring derivatives of tetracycline compounds are described.
US07786097B2	Tricyclic compounds, compositions and methods The present invention is directed to compounds of Formula I: or salt thereof, which are modulators of the glucocorticoid receptor. The compounds and salts of the invention are useful in the treatment of conditions mediated by glucocorticoid receptor activity.
US07786095B2	Amphiphilic macrocyclic derivatives and their analogues Soluble amphiphilic macrocycle analogues having lipophilic groups attached to one side of the units making up the macrocycle and hydrophilic groups attached to the other side. These amphiphilic macrocyclic derivatives have the ability to self-assemble in aqueous solvent forming micelles or vesicles and can be used as hosts for the solubilization and/or stabilization of various compounds. Embodiments of the present invention utilize macrocyclic oligosaccharides and preferably cyclodextrin as the macrocyclic derivatives to be modified.
US07786092B2	Composition and method of RNAi therapeutics for treatment of cancer and other neovascularization diseases Compositions and methods are provided for treatment of diseases involving unwanted neovascularization (NV). The invention provides treatments that control NV through selective inhibition of pro-angiogenic biochemical pathways, including inhibition of the VEGF pathway gene expression and inhibition localized at pathological NV tissues. Tissue targeted nanoparticle compositions comprising polymer conjugates and nucleic acid molecules that induce RNA interference (RNAi) are provided. The nanoparticle compositions of the invention can be used alone or in combination with other therapeutic agents such as VEGF pathway antagonists. The compositions and methods can be used for the treatment of NV diseases such as cancer, ocular disease, arthritis, and inflammatory diseases.
US07786089B2	Immunostimulatory activity of immune modulatory oligonucleotides (IMO™) containing different lengths of palindromic segments The invention provides a palindromic immune modulatory nucleic acid. The invention also provides methods for generating, enhancing and modifying the immune response caused by palindromic immune modulatory compounds used for immunotherapy applications.
US07786082B2	Combinations of human proteins to enhance in vivo viability of stem cells and progenitor cells Embodiments of the present invention include the use of placental alkaline phosphatase and other members of the alkaline phosphatase family alone or in combination with human transferrin and, optionally, human α1-antitrypsin to enhance the proliferation and survival of adult or embryonic stem cells and stem cell-derived progenitor cells in vivo.
US07786079B2	Substituted nonadepsipeptides The invention relates to nonadepsipeptides and methods for their preparation and their use for the production of medicaments for the treatment and/or prophylaxis of diseases, in particular bacterial infectious diseases.
US07786077B2	Insulins combinations A pharmaceutical association or combination comprising a therapeutic effective amount of insulin or insulin analogue, and a therapeutic effective amount of a pharmaceutically acceptable betaine, in which the insulin and the betaine possibly form a chemical entity or complex, and in which the amount of betaine is adapted for controlling the degradation and/or for increasing the duration of action and/or for enhancing the therapeutically effect of the insulin or insulin analogue.
US07786074B2	Composition and methods for promoting wound healing and tissue regeneration Provided herein are compositions and methods for use in promoting wound healing and tissue regeneration following tissue injury in a subject.
US07786072B2	Stabilized compounds having secondary structure motifs The present invention provides novel stabilized crosslinked compounds having secondary structure motifs, libraries of these novel compounds, and methods for the synthesis of these compounds libraries thereof. The synthesis of these novel stabilized compounds involves (1) synthesizing a peptide from a selected number of natural or non-natural amino acids, wherein said peptide comprises at least two moieties capable of undergoing reaction to promote carbon-carbon bond formation; and (2) contacting said peptide with a reagent to generate at least one crosslinker and to effect stabilization of a secondary structure motif. The present invention, in a preferred embodiment, provides stabilized p53 donor helical peptides. Additionally, the present invention provides methods for disrupting the p53/MDM2 binding interaction comprising (1) providing a crosslinked stabilized α-helical structure; and (2) contacting said crosslinked stabilized α-helical structure with MDM2.
US07786066B2	Stability of detergents containing hypochlorite, phosphonate chelant, and optical brightener The stability of aqueous, liquid detergents containing hypochlorite and brighteners is achieved by the use of a specific complexing agent.
US07786065B2	Ionic liquids derived from peracid anions A novel class of ionic liquids and methods for their preparation are disclosed. Specifically, these novel ionic liquids can be derived from peracid anions. The present invention also relates to compositions containing these novel ionic liquids and method of using the same.
US07786064B1	Ionic liquids derived from functionalized anionic surfactants A novel class of ionic liquids and methods for their preparation are disclosed. Specifically, these novel ionic liquids can be derived from anionic surfactants, such as alkyl aryl sulfonates, and mid-chain branched derivatives of alkyl sulfates, alkyl alkoxy sulfates, and alkyl aryl sulfonates. In addition, novel ionic liquids can be derived from other anionic surfactants, such as methyl ester sulfonates (MES), alkyl glycerol ether sulfonates, and alpha olefin sulfonates. Anions may be paired with a variety of cations to achieve various advantageous properties. The present invention also relates to compositions containing these novel ionic liquids and method of using the same.
US07786056B2	Heat dissipating silicone grease compositions A silicone grease composition comprising 3-30 wt % of an organopolysiloxane and 60-96.9 wt % of a heat conductive filler is diluted with a least volatile isoparaffin having a boiling point of 260-360° C. Despite a heavy loading of heat conductive filler, the grease composition is easily applicable to heat sinks as a thin uniform coating. The composition is drastically increased in shelf stability at room temperature, easy to handle, and provides for good heat dissipation.
US07786052B2	Hydrophobically modified fluid loss additives and viscosifier products A wellbore fluid that includes an oleagninous continuous phase; a non-oleaginous phase; and a polymeric additive formed by reaction of at least one lipophilic epoxy modifier and at least one epoxide-reactive agent, wherein the at least one epoxide-reactive agent comprises at least one selected from lignins, tannins, biopolymers, starches, carboxy methyl cellulose, polyacrylates, polyacrylamides, and synthetic polymers is disclosed.
US07786051B2	Method of preventing or reducing fluid loss in subterranean formations A method of treating a formation penetrated by a wellbore to reduce fluid loss to the formation is carried out by providing a quantity of water-degradable particles formed from a solid polymeric acid precursor having a number average molecular weight (Mn) of greater than 4000. A slurry of the particles is formed with a carrier fluid, which may be an aqueous fluid. The slurry is introduced into the formation through the wellbore at a pressure below the fracture pressure of the treated formation. A treating fluid is subsequently introduced into the formation through the wellbore. The water-degradable particles degrade by contacting the particles with a free aqueous fluid introduced into the formation through the wellbore. The water-degradable particles may have a particle size of from about 0.25 mm or less. The slurry may contain from about 0.01 kg/L to about 0.15 kg/L of the water degradable particles.
US07786049B2	Drilling fluids with improved shale inhibition and methods of drilling in subterranean formations The present invention relates to subterranean drilling operations, and more particularly, to drilling fluids that may be used to drill a well bore in a subterranean formation that may demonstrate improved shale inhibition and methods of using such drilling fluids in subterranean formations. One embodiment of the methods of the present invention provides a method of drilling a well bore in a subterranean formation comprising providing a drilling fluid comprising an aqueous-based fluid and a shale inhibiting component comprising a nanoparticle source; and placing the drilling fluid in the well bore in the subterranean formation. Another embodiment of the present invention provides a method of flocculation comprising providing a fluid comprising suspended particles, and adding a shale inhibiting component comprising a nanoparticle source to the fluid comprising suspended particles to form flocculated particles.
US07786048B2	Condensed heterocyclic pyrazole derivatives as kinase inhibitors Bicyclo-pyrazole compound of formula (I) and pharmaceutically acceptable salts thereof, as defined in the specification, processes for their preparation, combinatorial libraries comprising a plurality of them and pharmaceutical compositions thereof, are herewith disclosed: the compounds of the invention are useful, in therapy, as protein kinase inhibitors, for instance in the treatment of cancer.
US07786047B2	Immunoglobulins devoid of light chains The invention relates to an immunoglobulin having determined antigen specificity, and having a variable fragment which is derived from a so-called heavy-chain immunoglobulin having two heavy polypeptide chains capable of recognizing and binding one or several antigens and which is further naturally devoid of light chains, wherein the immunoglobulin having determined antigen specificity is devoid of CH1 constant region between the variable region and the hinge region and has within its constant region at least part of a constant region of a human antibody.
US07786046B2	Benzoyl-substituted serineamides The present invention relates to benzoyl-substituted serinamides of the formula I in which the variables R1 to R11 are as defined in the description, and to their agriculturally useful salts, to processes and intermediates for their preparation, and to the use of these compounds or of compositions comprising these compounds for controlling unwanted plants.
US07786045B2	Aryl ether compounds and their preparation and use thereof The invention relates to aryl ether compounds and its preparation method and use thereof. The aryl ether compounds of the invention having general formula (I): The groups are as defined as specification. The aryl ether compounds of present invention have wide spectrum fungicidal activity, and may be used to control diseases in all sorts of plants caused by oomycete, basidiomycete, ascomycete pathogens and deuteromycete. The some of the compounds have very good insecticidal and acaricidal activity, and may be used to control insects and mites.
US07786041B2	Synergistic crop plant-compatible herbicidal compositions comprising herbicides from the group of the benzoylcyclohexanediones Synergistic crop plant-compatible herbicidal compositions comprising herbicides from the group of the benzoylcyclohexanedionesHerbicidal compositions comprising A) a compound from the group of the benzoylpyrazoles, B) at least one further herbicide and C) at least one safener are described as herbicides which are active against monocotyledonous and/or dicotyledonous harmful plants. Compared to the herbicides used on their own, these compositions have superior activity and at the same time high compatibility with crop plants.
US07786036B2	Dielectric porcelain composition, and method for manufacturing capacitor using the same A dielectric ceramic composition containing at least 0.15 to 2.5 mol of a Mg compound in terms of MgO, 0 to 1.6 mol of a Ba compound in terms of BaCO3, 0.1 to 3.0 mol of a Ln (Ln includes two or three kinds of elements selected from Er, Dy, and Ho with Er being essential) compound in terms of Ln2O3, 0.01 to 0.4 mol of a Mn compound in terms of MnO4/3, 0.01 to 0.26 mol of a V compound in terms of V2O5, 0.3 to 3.5 mol of a Si compound in terms of SiO2, and 0.01 to 2.5 mol of an Al compound in terms of Al2O3 to 100 mol of barium titanate adjusted for a Ba/Ti molar ratio of 0.997 to 1.007.
US07786034B2	Rotary process for forming uniform material A process is provided for issuing material from a nozzle in a rotor rotating at a given rotational speed wherein the material is issued by way of a fluid jet. The material can be collected on a collector concentric to the rotor. The collector can be a flexible belt moving in the axial direction of the rotor. The collected material can take the form of discrete particles, fibers, plexifilamentary web, discrete fibrils or a membrane.
US07786032B2	Hot-melt adhesive based on blend of amorphous and crystalline polymers for multilayer bonding The present invention is generally directed to adhesive compositions comprising selected ratios of crystalline and amorphous polymers. In some versions of the invention, polymers capable of existing in different configurations (e.g., a polymer such as polypropylene which can exist in an atactic, syndiotactic. or isotactic configuration) is used to prepare adhesives of the present invention. As an example, a selected amount of isotactic polypropylene is blended with a selected amount of atactic polypropylene to prepare an adhesive composition having one or more performance properties (e.g., bond strength) that are superior to the performance properties of a conventional hot-melt adhesive.
US07786029B2	Resin composition and application thereof A resin composition contains a solvent and a solid content dispersed in the solvent. The solid content does not contain phenolic resin. The solid content contains a benzoxazine resin and a phosphorus-containing epoxy resin. The weight ratio of the benzoxazine resin to phosphorus-containing epoxy resin is about 0.6:1 to about 3.0:1. A circuit board substrate and a copper clad laminate fabricated with the resin composition mentioned above are disclosed too.
US07786028B2	Nonwoven polymeric fiber mat composites and method A flexible nonwoven mat of polymeric fibers is liquid water transmission resistant and is particularly well suited for use as a prefabricated building construction underlayment. The polymeric fibers may be standard polymeric fibers or sheathed polymeric fibers that have fiber sheaths with a lower softening point temperature than the softening point temperature of the fiber cores. Preferably, the polymeric fibers are spunbond fibers and are bonded together through the application of heat and pressure. Where the fibers are sheathed fibers, interstices of the nonwoven mat are at least partially filled by a portion of the polymeric material of the sheaths that is dispersed into the interstices to reduce the porosity of the mat. In certain embodiments, the polymeric fibers on the top major surface of the mat are coated with a hydrophobic binder coating material, which is overlaid with a water repellant coating material, such as a filled asphalt, modified bitumen, or a non-asphaltic polymeric film, to increase the liquid water impermeability and enhance other physical properties of the mat.
US07786026B2	Enhanced thickness fabric and method of making same The present invention provides thickened fabrics and reinforcements for use as a spacer or reinforcement for a matrix system. The fabric includes in a first embodiment a woven fabric comprising weft and warp yarns containing glass fibers. A portion of the weft yarns are undulated, resulting in an increased thickness for the fabric. The fabric is coated with a polymeric resin or bonding agent, for substantially binding the weft yarns in the undulated condition. This invention also includes methods for making such fabric by increasing the thickness of a woven or non-woven material by such methods as applying tension during weaving operations, or using unbalanced yarns.
US07786024B2	Selective processing of semiconductor nanowires by polarized visible radiation Methods, systems, and apparatuses for annealing semiconductor nanowires and for fabricating electrical devices are provided. Nanowires are deposited on a substrate. A plurality of electrodes is formed. The nanowires are in electrical contact with the plurality of electrodes. The nanowires are doped. A polarized laser beam is applied to the nanowires to anneal at least a portion of the nanowires. The nanowires may be aligned substantially parallel to an axis. The laser beam may be polarized in various ways to modify absorption of radiation of the applied laser beam by the nanowires. For example, the laser beam may be polarized in a direction substantially parallel to the axis or substantially perpendicular to the axis to enable different nanowire absorption profiles.
US07786020B1	Method for fabricating nonvolatile memory device A method for fabricating a nonvolatile memory device includes repeatedly stacking a stacked structure over a substrate to form a multi-stacked structure, wherein the stacked structure includes a conductive layer and an insulation layer, forming a photoresist pattern over the multi-stacked structure, first-etching an uppermost stacked structure of the multi-stacked structure using the photoresist pattern as an etch barrier, second-etching a resultant structure formed by the first-etching through the use of a breakthrough etching, slimming the photoresist pattern to form a slimmed photoresist pattern, and third-etching the uppermost stacked structure using the slimmed photoresist pattern as an etch barrier and, at the same time, etching a stacked structure disposed under the uppermost stacked structure and exposed by the first-etching.
US07786019B2	Multi-step photomask etching with chlorine for uniformity control Methods for etching quartz are provided herein. In one embodiment, a method of etching quartz includes providing a film stack on a substrate support disposed in a processing chamber, the film stack having a quartz layer partially exposed through a patterned layer; and etching the quartz layer of the film stack in a multi-step process including a first step of etching the quartz layer utilizing a first process gas comprising at least one fluorocarbon process gas and a chlorine-containing process gas; and a second step of etching the quartz layer utilizing a second process gas comprising at least one fluorocarbon process gas.
US07786016B2	Methods of uniformly removing silicon oxide and a method of removing a sacrificial oxide A method of substantially uniformly removing silicon oxide is disclosed. The silicon oxide to be removed includes at least one cavity therein or more than one density or strain therein. The silicon oxide having at least one cavity or more than one density or strain is exposed to a gaseous mixture of NH3 and HF and heated, to substantially uniformly remove the silicon oxide. A method of removing an exposed sacrificial layer without substantially removing exposed isolation regions using the gaseous mixture of NH3 and HF and heat is also disclosed, as is an intermediate semiconductor device structure that includes a semiconductor substrate, a sacrificial layer overlying the semiconductor substrate, a diffusion barrier overlying the sacrificial layer, and exposed isolation regions.
US07786002B2	Method for producing a component comprising a conductor structure that is suitable for use at high frequencies The invention provides a process for producing a substrate having a conductor arrangement that is suitable for radio-frequency applications, with improved radio-frequency properties. For this purpose, the process includes the steps of: depositing a structured glass layer having at least one opening over a contact-connection region by evaporation coating on the substrate and applying at least one conductor structure to the structured glass layer so that the at least one conductor has electrical contact with the contact-connection region.
US07786000B2	Buried bit line anti-fuse one-time-programmable nonvolatile memory An anti-fuse one-time-programmable (OTP) nonvolatile memory cell has a P well substrate with two P.sup.− doped regions. Another N.sup.+ doped region, functioning as a bit line, is positioned adjacent and between the two P.sup.− doped regions on the substrate. An anti-fuse is defined over the N.sup.+ doped region. Two insulator regions are deposited over the two P.sup.− doped regions. An impurity doped polysilicon layer is defined over the two insulator regions and the anti-fuse. A polycide layer is defined over the impurity doped polysilicon layer. The polycide layer and the polysilicon layer function as a word line. A programmed region, i.e., a link, functioning as a diode, is formed on the anti-fuse after the anti-fuse OTP nonvolatile memory cell is programmed. The array structure of anti-fuse OTP nonvolatile memory cells and methods for programming, reading, and fabricating such a cell are also disclosed.
US07785995B2	Semiconductor buffer structures Pile ups of threading dislocations in thick graded buffer layer are reduced by enhancing dislocation gliding. During formation of a graded SiGe buffer layer, deposition of SiGe from a silicon precursor and a germanium precursor is interrupted one or more times with periods in which the flow of the silicon precursor to the substrate is stopped while the flow of the germanium precursor to the substrate is maintained.
US07785994B2	Ion implantation method and semiconductor device manufacturing method In the ion implantation method and semiconductor device manufacturing method relating to the present invention, a disc on which multiple semiconductor substrates are mounted is positioned in the manner that a first angle β1 is made between an X-Y plane perpendicular to an ion beam and a line perpendicular to the Y-axis in a disc rotation plane. In this state, an ion beam is emitted to implant a first conductivity type impurity in the semiconductor substrates while the disc is rotated about a disc rotation axis. Then, the disc is positioned in the manner that a second angle β2 is made between the X-Y plane and a line perpendicular to the Y-axis in the disc rotation plane. In this state, an ion beam is emitted to implant a second conductivity type impurity in the semiconductor substrates while the disc is rotated about the disc rotation axis.
US07785993B2	Method of growing a strained layer A method of forming a Si strained layer 16 on a Si substrate 10 includes forming a first SiGe buffer layer 12 on the Si substrate 10. Then, the first SiGe buffer layer is implanted with an amorphising implant to render the first SiGe buffer layer amorphous using ion implantation. A second SiGe buffer layer 14 is grown on the first SiGe buffer layer after annealing. This produces a relaxed SiGe layer 12, 14. Then, the strained layer of Si 16 is grown.
US07785991B2	Process for integrating a III-N type component on a (001) nominal silicium substrate A process is provided for integrating a III-N component, such as GaN, on a (001) or (100) nominal silicon substrate. There are arranged a texture of elementary areas each comprising an individual surface, with the texture comprising at least one hosting area intended to receive a III-N component. A mask layer is deposited on non-hosting areas which are not intended to receive a III-N type component. The hosting area is locally prepared so as to generate on the surface of the area one domain comprising one single type of terrace. There is grown by Molecular Beam Epitaxy or Metalorganic Vapor Phase Epitaxy on the hosting area one intermediary AlN buffer layer, followed by the growth of one III-N based material so as to realize a substantially monocrystalline structure. There is eliminated the mask layer located on non-hosting areas as well as surface polycrystalline layers deposited above the mask layers, and MOS/CMOS structures are subsequent integrated on at least some of the non-hosting areas.
US07785985B2	Methods of manufacturing semiconductor devices Methods of manufacturing a semiconductor device, which can reduce hot electron induced punchthrough (HEIP) and/or improve the operating characteristics of the device include selectively forming an oxynitride layer in a device isolation layer according to the characteristics of transistors isolated by the device isolation layer. The methods include forming first trenches and second trenches on a substrate, forming an oxide layer on the surfaces of the first trenches and the second trenches, selectively forming an oxynitride layer on the second trenches by using plasma ion immersion implantation (PIII), and forming a buried insulating layer in the first trenches and the second trenches. The buried insulating layer may be planarized to form a first device isolation layer in the first trenches and a second device isolation layer in the second trenches.
US07785984B2	Manufacturing method for semiconductor device A manufacturing method for a semiconductor device includes generating on a substrate liquid-phase silanol having fluidity by causing a source gas made of a material containing silicon to react with a source gas made of a material containing oxygen, introducing the silanol into a first recess having an aspect ratio of a predetermined value wholly, and introducing the silanol into a space from a bottom to an intermediate portion in a second recess having an aspect ratio lower than the predetermined value, the first and second recesses are provided in the substrate, burying a silicon oxide film in the first recess and providing the silicon oxide film in the second recess by converting the silanol into the silicon oxide film by dehydrating condensation, and providing a dielectric film having film density higher than that of the silicon oxide film on the silicon oxide film.
US07785983B2	Semiconductor device having tiles for dual-trench integration and method therefor A method for forming a semiconductor device includes providing a semiconductor substrate having a first region and a second region. The first region has one or more first elements and the second region has one or more second elements. The first elements are different from the second elements. A tile location and a first tile surface area for a tile feature on the semiconductor device is defined. An active semiconductor layer is formed over both the first region and the second region of the semiconductor substrate. A first trench is formed in the active semiconductor layer at the tile location using a negative tone mask. The first trench has a first depth and forms at least a portion of the tile feature. A second trench is formed in the active semiconductor layer using a positive tone mask. The second trench has a second depth different than the first depth.
US07785982B2	Structures containing electrodeposited germanium and methods for their fabrication Methods for electrodepositing germanium on various semiconductor substrates such as Si, Ge, SiGe, and GaAs are provided. The electrodeposited germanium can be formed as a blanket or patterned film, and may be crystallized by solid phase epitaxy to the orientation of the underlying semiconductor substrate by subsequent annealing. These plated germanium layers may be used as the channel regions of high-mobility channel field effect transistors (FETs) in complementary metal oxide semiconductor (CMOS) circuits.
US07785981B2	Solid-state imaging device and method of manufacturing solid-state imaging device A solid state imaging device having a back-illuminated type structure in which a lens is formed on the back side of a silicon layer with a light-receiving sensor portion being formed thereon. Insulating layers are buried into the silicon layer around an image pickup region, with the insulating layer being buried around a contact layer that connects an electrode layer of a pad portion and an interconnection layer of the surface side. A method of manufacturing such a solid-state imaging device is also provided.
US07785980B2	Method of manufacturing semiconductor device using alignment mark and mark hole An object of the present inventions is to overcome a problem that the presence of a metal film, which is opaque to a visible light, between a lower layer alignment mark and a photoresist prevents the detection of the lower layer alignment mark, to make the pattern formation difficult. In the present inventions, an insulating film is placed beneath the alignment mark in structure; an alignment mark consisting of said multi-layered film comprising an alignment mark layer and the insulating film, which constitutes a stepped part with an increased difference in level, is first formed, inside a mark hole, in a manner of self-alignment; and then the metal film which is the very cause of the above problem is formed thereon. Since the metal film itself has a stepped shape corresponding to the alignment mark, alignment can be made with great accuracy.
US07785978B2	Method of forming memory cell using gas cluster ion beams A variable resistance memory cell structure and a method of forming it. The method includes forming a first electrode, forming an insulating material over the first electrode, forming a via in the insulating material to expose a surface of the first electrode, forming a heater material within the via using gas cluster ion beams, forming a variable resistance material within the via, and forming a second electrode such that the heater material and variable resistance material are provided between the first and second electrodes.
US07785974B2	Methods of employing a thin oxide mask for high dose implants A method for forming a bipolar transistor device includes providing a semiconductor substrate. An oxide layer is formed on the semiconductor substrate. The oxide layer is patterned to form an opening that exposes a portion of the semiconductor substrate. A dopant, such as antimony, is implanted into the semiconductor substrate through the opening to form a buried layer. An upper portion of the mask layer is removed to define a thin mask layer. A buried layer diffusion process is performed to drive in the implanted dopants while mitigating recess formation.
US07785972B2	Method for fabricating semiconductor MOS device A method of making a transistor device having silicided source/drain is provided. A gate electrode is formed on a substrate with a gate dielectric layer therebetween. A spacer is formed on sidewalls of the gate electrode. A source/drain is implanted into the substrate. A pre-amorphization implant (PAI) is performed to form an amorphized layer on the source/drain. A post-PAI annealing process is performed to repair defects formed during the PAI process. A metal silicide layer is then formed from the amorphized layer.
US07785964B2	Non-volatile semiconductor memory device and method of manufacturing the same Example embodiments relate to a non-volatile semiconductor memory device and a method of manufacturing the same. A semiconductor device includes an isolation layer protruding from a substrate, a spacer, a tunnel insulation layer, a floating gate, a dielectric layer pattern and a control gate. The spacer may be formed on a sidewall of a protruding portion of the isolation layer. The tunnel insulation layer may be formed on the substrate between adjacent isolation layers. The floating gate may be formed on the tunnel insulation layer. The floating gate contacts the spacer and has a width that gradually increases from a lower portion toward an upper portion. The dielectric layer pattern and the control gate may be sequentially formed on the floating gate.
US07785957B2	Post metal gate VT adjust etch clean A method for fabricating a CMOS integrated circuit (IC) includes providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the semiconductor surface followed by forming at least a first metal including layer on the gate dielectric layer. A polysilicon or amorphous silicon layer is formed on the first metal including layer to form an intermediate gate electrode stack. A masking pattern is formed on the intermediate gate electrode stack. The polysilicon or amorphous silicon layer is dry etched using the masking pattern to define a patterned intermediate gate electrode stack over the NMOS or PMOS regions, wherein the dry etching stops on a portion of the first metal comprising layer. The masking pattern is removed using a first post etch clean for stripping the masking pattern. A multi-step solution cleaning sequence is used after the removing step and includes a first wet clean including sulfuric acid and a fluoride, and a second wet clean after the first wet clean including a fluoride. Fabrication of the IC is then completed.
US07785955B2	CMOS structure and method including multiple crystallographic planes A complementary metal oxide semiconductor (CMOS) structure includes a semiconductor substrate having first mesa having a first ratio of channel effective horizontal surface area to channel effective vertical surface area. The CMOS structure also includes a second mesa having a second ratio of the same surface areas that is greater than the first ratio. A first device having a first polarity uses the first mesa as a channel and benefits from the enhanced vertical crystallographic orientation. A second device having a second polarity different from the first polarity uses the second mesa as a channel and benefits from the enhanced horizontal crystallographic orientation.
US07785954B2	Semiconductor memory integrated circuit and its manufacturing method A method of manufacturing a semiconductor memory integrated circuit intended to improve properties and reliability of its peripheral circuit includes the step of forming a tunnel oxide film (21a) in the cell array region, gate oxide film (21b) for a high-voltage circuit and gate oxide film (21c) for a low-voltage circuit both in the peripheral circuit to respectively optimum values of thickness, and covering them with a first-layer polycrystalline silicon film (22). After that, device isolation grooves (13) are formed and buried with a device isolation insulating film (14). The first-layer polycrystalline silicon film (24) is a non-doped film, and after device isolation, a second-layer polycrystalline silicon film (24) is doped with phosphorus in the cell array region to form floating gates made of the first-layer polycrystalline silicon film (22) and the second-layer polycrystalline silicon film (24). In the peripheral circuit, gate electrodes are made of a multi-layered film including the first-layer polycrystalline silicon, film (22), second-layer polycrystalline silicon film (24) and third-layer polycrystalline silicon film 28, and impurities are ion implanted thereafter to respective transistor regions under respectively optimum conditions.
US07785953B2	Method for forming trenches on a surface of a semiconductor substrate A method for forming trenches on a surface of a semiconductor substrate is described. The method may include: etching a first plurality of trenches into the surface of the semiconductor substrate; filling the first plurality of trenches with at least one material; and etching a second plurality of trenches into every second trench of the first plurality of trenches. Furthermore, a method for forming floating-gate electrodes on a semiconductor substrate and an integrated circuit is described.
US07785951B2	Methods of forming integrated circuit devices having tensile and compressive stress layers therein and devices formed thereby Methods of forming integrated circuit devices include forming first, second and third gate electrodes on a semiconductor substrate. A first stress film is provided that covers the first gate electrode and at least a first portion of the third gate electrode. The first stress film has a sufficiently high internal stress characteristic to impart a net compressive stress in a first portion of the semiconductor substrate extending opposite the first gate electrode. A second stress film is also provided. The second stress film covers the second gate electrode and at least a second portion of the third gate electrode. The second stress film has a sufficiently high internal stress characteristic to impart a net tensile stress in a second portion of the semiconductor substrate extending opposite the second gate electrode. The second stress film has an upper surface that is coplanar with an upper surface of the first stress film at a location adjacent the third gate electrode.
US07785950B2	Dual stress memory technique method and related structure A method for providing a dual stress memory technique in a semiconductor device including an nFET and a PFET and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer over the nFET and a compressive stress layer over the pFET, annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200° C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET.
US07785946B2	Integrated circuits and methods of design and manufacture thereof Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.
US07785943B2	Method for forming a multi-gate device with high k dielectric for channel top surface Method for providing a transistor that includes the steps of providing a silicon on insulator layer, providing a silicon oxide insulation layer, providing a dielectric layer, removing at least a portion of the silicon oxide insulation layer and the dielectric layer to form a gate stack, and forming a gate electrode. The gate electrode covers a portion of the gate stack.
US07785942B2	Active matrix organic EL display device and manufacturing method thereof An active matrix organic EL display device includes pixels each having an organic EL element (7a) and a pixel circuit (3) including a polysilicon TFT for controlling the organic EL element (7a) arranged adjacently in each of the regions partitioned into a matrix shape by data line (12) and gate line (11) that intersect each other. The organic EL element (7a) has a cathode (7) arranged in at least a region that excludes a space above the polysilicon TFT. The cathode (7) is arranged continuously over two or more adjacent pixels in the direction of gate line (11).
US07785941B2	Method of fabricating thin film transistor A method for fabricating a thin film transistor (TFT) is provided. A substrate having a gate, a dielectric layer, a channel layer and an ohmic contact layer formed thereon is provided. Next, a metal layer is formed over the substrate covering the ohmic contact layer. Next, the metal layer and the ohmic contact layer are simultaneously etched by a wet etching process to form a source/drain and expose the channel layer. Because the wet etching process can be used to selectively etch the ohmic contact layer, damage to the underlying channel layer may be negligible. Thus, the reliability of the device may be promoted. Furthermore, the process may be simplified, the production yield and the throughput of TFT may be increased.
US07785940B2	TFT array substrate and method for fabricating the same A four-mask process thin film transistor (TFT) array substrate and a method for fabricating the same is disclosed, which prevents a semiconductor tail from being formed. An open area is thus obtained and wavy noise is prevented from occurring. The method of fabricating a TFT array substrate comprises: forming a gate line, a gate electrode and a pad electrode on a substrate; sequentially depositing a gate insulation layer, a silicon layer and a metal layer on an entire surface of the substrate including the gate line; forming an open area in the pad electrode; forming a semiconductor layer, data line and source/drain electrodes by patterning the silicon layer and the metal layer; and forming a pixel electrode connected with the drain electrode and a transparent conductive layer connected with the pad electrode by depositing and patterning a transparent conductive material on the entire surface of the substrate including the data line, and simultaneously defining a channel region by separating the source and drain electrodes from each other.
US07785938B2	Semiconductor integrated circuit, manufacturing method thereof, and semiconductor device using semiconductor integrated circuit A step of forming a through hole in a semiconductor substrate, or a step of polishing the semiconductor substrate from its back surface requires a very long time and causes decrease of productivity. In addition, when semiconductor substrates are stacked, a semiconductor integrated circuit which is formed of the stack is thick and has poor mechanical flexibility. A release layer is formed over each of a plurality of substrates, layers each having a semiconductor element and an opening for forming a through wiring are formed over each of the release layers. Then, layers each having the semiconductor element are peeled off from the substrates, and then overlapped and stacked, a conductive layer is formed in the opening, and the through wiring is formed; thus, a semiconductor integrated circuit is formed.
US07785937B2	Electrical fuse having sublithographic cavities thereupon An electrical fuse and a first dielectric layer thereupon are formed on a semiconductor substrate. Self-assembling block copolymers containing two or more different polymeric block components are applied into a recessed region surrounded by a dielectric template layer. The self-assembling block copolymers are then annealed to form a pattern of multiple circles having a sublithographic diameter. The pattern of multiple circles is transferred into the first dielectric layer by a reactive ion etch, wherein the portion of the first dielectric layer above the fuselink has a honeycomb pattern comprising multiple circular cylindrical holes. A second dielectric layer is formed over the circular cylindrical holes by a non-conformal chemical vapor deposition and sublithographic cavities are formed on the fuselink. The sublithographic cavities provide enhanced thermal insulation relative to dielectric materials to the fuselink so that the electrical fuse may be programmed with less programming current.
US07785935B2	Manufacturing method for forming an integrated circuit device and corresponding integrated circuit device The present invention provides a manufacturing method for forming an integrated circuit device and to a corresponding integrated circuit device. The manufacturing method for forming an integrated circuit device comprises the steps of: forming a first level on a substrate; forming a second level above the first level; forming a cap layer on the second level which covers a first region of the level and leaves a second region uncovered; and simultaneously etching a first contact hole in the first region and a second contact hole in the second region such that the etching is selective to the cap layer in the second region and proceeds to a greater depth in the first region.
US07785921B1	Barrier for doped molybdenum targets A sputtering target, including a sputtering layer and a support structure. The sputtering layer includes an alkali-containing transition metal. The support structure includes a second material that does not negatively impact the performance of a copper indium selenide (CIS) based semiconductor absorber layer of a solar cell. The sputtering layer directly contacts the second material.
US07785919B2	Image sensor and method for manufacturing the same An image sensor and a method for manufacturing the same are provided. The image sensor can comprise a substrate, a metal pad, and a sulfur layer. The substrate can include a pixel region and a pad region. The metal pad can be formed of a material containing sulfur and can be disposed in the pad region of the substrate. The sulfur layer can be formed from the sulfur of the metal pad and provided on a top surface of the metal pad.
US07785917B2	Image sensor and manufacturing method for the same An image sensor including a first region where a pad is to be formed, and a second region where a light-receiving element is to be formed. A pad is formed over a substrate of the first region. A passivation layer is formed over the substrate of the first and second regions to expose a portion of the pad. A color filter is formed over the passivation layer of the second region. A microlens is formed over the color filter. A bump is formed over the pad. A protective layer is formed between the bump and the pad to expose the portion of the pad.
US07785914B2	Image sensor and method for manufacturing the same An image sensor including a substrate and an interlayer dielectric layer divided into a pixel region and a logic pad region. An image sensor may include at least one of the following: a color filter, an over coating layer, and a micro lens sequentially formed over the interlayer dielectric layer in the pixel region; a top conductive layer formed over the interlayer dielectric layer of the logic pad region; an etch stop layer formed over the interlayer dielectric layer in the logic pad region and on the sides and a portion of an upper surface of a top conductive layer; and a first and second protective layers sequentially formed over the etch stop layer.
US07785913B2	System and method for forming moveable features on a composite substrate A method for forming moveable features suspended over a substrate is described, wherein a cavity beneath the moveable feature is first formed using a liquid etchant applied through one or more release holes. After formation of the cavity, the outline of the moveable feature is formed using a dry etch process. Since the moveable feature is free to move upon its formation using the dry etch process, no stiction issues arise using the systems and methods described here.
US07785912B2	Piezo-TFT cantilever MEMS fabrication A piezo-TFT cantilever microelectromechanical system (MEMS) and associated fabrication processes are provided. The method comprises: providing a substrate, such as glass for example; forming thin-films overlying the substrate; forming a thin-film cantilever beam; and simultaneously forming a TFT within the cantilever beam. The TFT is can be formed least partially overlying a cantilever beam top surface, at least partially overlying a cantilever beam bottom surface, or embedded within the cantilever beam. In one example, forming thin-films on the substrate includes: selectively forming a first layer with a first stress level; selectively forming a first active Si region overlying the first layer; and selectively forming a second layer overlying the first layer with a second stress level. The thin-film cantilever beam is formed from the first and second layers, while the TFT source/drain (S/D) and channel regions are formed from the first active Si region.
US07785911B2	Semiconductor laser diode with current restricting layer and fabrication method thereof Provided are a semiconductor laser diode having a current confining layer and a method of fabricating the same. The semiconductor laser diode includes a substrate, a first material layer deposited on the substrate, an active layer which is deposited on the first material layer and emits a laser beam, and a second material layer which is deposited on the active layer and includes a ridge portion protruding from the active layer and a current confining layer formed by injection of ions into peripheral portions of the ridge portion so as to confine a current injected into the active layer. Therefore, it is possible to fabricate an improved semiconductor laser diode having a low-resonance critical current value that can remove a loss in an optical profile and reduce the profile width of a current injected into the active layer while maintaining the width of the ridge portion.
US07785910B2	Light emitting device having protrusion and recess structure and method of manufacturing the same The semiconductor light emitting device having a protrusion and recess structure includes: a lower clad layer disposed on a substrate; an active layer formed on one portion of a top surface of the lower clad layer; an upper clad layer formed on the active layer; a first electrode formed on the upper clad layer; and a second electrode that is formed on a protrusion and recess structural pattern region formed on a portion of the top surface of the lower clad layer not occupied by the active layer.
US07785908B2	Method of making diode having reflective layer A method of forming a light emitting diode includes forming a transparent substrate and a GaN buffer layer on the transparent substrate. An n-GaN layer is formed on the buffer layer. An active layer is formed on the n-GaN layer. A p-GaN layer is formed on the active layer. A p-electrode is formed on the p-GaN layer and an n-electrode is formed on the n-GaN layer. A reflective layer is formed on a second side of the transparent substrate. A scribe line is formed on the substrate for separating the diodes on the substrate. Also, a cladding layer of AlGaN is between the p-GaN layer and the active layer.
US07785906B2	Method to detect poly residues in LOCOS process A test structure which can be used to detect residual conductive material such as polysilicon which can result from an under etch comprises a PMOS transistor and an OTP EPROM floating gate device. By testing the devices using different testing parameters, it can be determined whether residual conductive material remains subsequent to an etch, and where the residual conductive material is located on the device. A method for testing a semiconductor device using the test structure is also described.
US07785902B2	Method for analyzing a mixture of biological and/or chemical components using magnetic particles and device for the implementation of said method Disclosed is a method of analysis of a mixture of biological and/or chemical components that entails spatially arranging a chosen component attached to magnetic particles, exposing the particles to a magnetic field, and recording a magnetic induction signal, from which the content of the analyte in the mixture is judged; this includes grouping the chosen component in a probe volume, making the magnetic field alternating, pre-setting its spectrum, at least, at two frequencies, and recording the signal at a frequency, which is a linear combination of these frequencies, during the exposure of the magnetic particles to the field.
US07785900B1	Glutathione beads and GST fusion proteins The present invention relates generally to glutathione derivatized beads which are adapted for use in conjunction with glutathione-S-transferase fusion proteins (generally, GST fusion proteins, which contain a fluorescent label such as fluorescent green protein) for use in flow cytometry. The present invention also relates to methods for detecting and/or quantifying interactions between a GST fusion protein and their binding partners, in particular, labeled binding partners such as fluorescently labeled binding partners. By creating glutathione beads with an appropriate high or increased site density, disadvantages often associated with low affinity systems and quick off-rates in solution may be resolved to provide a workable system and method. Methods of identifying potential agonists, antagonists and regulator compounds of proteins fused to GST from libraries of compounds represents another aspect of the present invention.

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