| Document | Document Title |
|---|---|
| US07787322B2 |
Multi-port memory device having self-refresh mode
The multi-port memory device includes a mode input/output controller for receiving a flag signal and generating a self-refresh entry signal and a self-refresh escape signal, a refresh interval signal generator for providing a self-refresh interval signal notifying a self-refresh interval in response to the self-refresh entry signal and the self-refresh escape signal, a refresh cycle signal generator for periodically generating a cycle-pulse signal during an activation of the self-refresh interval signal, an internal refresh signal generator for producing an internal refresh signal in response to the self-refresh entry signal and the cycle-pulse signal, and an internal address counter for generating an internal address in response to the internal refresh signal. |
| US07787316B2 |
Semiconductor memory device and write control method thereof
A semiconductor memory device includes a plurality of word lines, a plurality of bit lines, a plurality of memory elements arranged at intersecting points between the word lines and the bit lines, respectively, a row selector selectively activating the word lines, a plurality of write drivers provided to correspond to the bit lines, and supplying a write current to the corresponding bit lines, respectively, a plurality of write control circuits controlling operations performed by the corresponding write drivers, respectively, and a column selector selecting the write control circuits. The column selector sequentially selects a predetermined write control circuit per one clock in a state of activating a predetermined word line, and the selected write control circuit activates one corresponding write driver over a period of one clock or more. |
| US07787309B2 |
Method of operating integrated circuit embedded with non-volatile one-time-programmable and multiple-time programmable memory
A programmable non-volatile device is operated using a floating gate that functions as a FET gate that overlaps a portion of a source/drain region. This allows a programming voltage for the device to be imparted to the floating gate through capacitive coupling, thus changing the state of the device. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications. |
| US07787308B2 |
Flash memory device and program method thereof
A method for programming a flash memory device comprising programming memory cells via repetition of program loops, a first of the program loops including a program execution interval and a verify read interval, a second of the program loops including the program execution interval, the verify read interval, and a judging interval. Also disclosed is a flash memory device comprising a memory cell array having memory cells arranged in rows and columns, a read/program circuit configured to perform program and read operations to the memory cell array, and a control logic circuit configured to control the read/program circuit so as to perform a judging operation according to a program loop number. |
| US07787307B2 |
Memory cell shift estimation method and apparatus
Memory devices and methods are disclosed, such as those facilitating interpolation methods for reference memory cells based on their reference state and/or location in an array of memory cells. For example, a group of reference cells programmed to a subset of possible data states are utilized to interpolate for data states other than those in the subset. Such embodiments might be used to reduce the quantity of reference cells required. |
| US07787306B2 |
Nonvolatile semiconductor memories for preventing read disturbance and reading methods thereof
A method of reading a flash memory device can include driving a selected word line by applying a selection voltage thereto and driving unselected word lines by applying a first voltage thereto, driving the unselected word lines and first and second selection lines by applying a second voltage that is higher than the first voltage thereto, and reading data from a memory cell that is coupled to the selected word line. |
| US07787304B2 |
Method of making integrated circuit embedded with non-volatile one-time-programmable and multiple-time programmable memory
A programmable non-volatile device is made which uses a floating gate that functions as a FET gate that overlaps a portion of a source/drain region. This allows a programming voltage for the device to be imparted to the floating gate through capacitive coupling, thus changing the state of the device. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications. |
| US07787303B2 |
Programmable CSONOS logic element
A complementary SONOS-type (CSONOS) logic device is programmed and erased with a common voltage. The programming method involves reading the logic state of a complementary pair without disturbing the logic state after setting the complementary pair of non-volatile trapped-charge memory devices, including a first memory device and a second memory device, to a first logic state or a second logic state with a common voltage to control the complementary pair. The CSONOS device retains data integrity over extended read endurance cycles. |
| US07787299B2 |
Semiconductor memory device and erase method in the same
A semiconductor memory device and an erase method in the same are disclosed. The semiconductor memory device includes a memory cell array configured to have a cell string in which memory cells are coupled, a block switch configured to switch a global word line and a word line of the memory cell array, a block decoder configured to control the block switch, and a recycle switch configured to use an erase voltage charged in a P-well of the memory cell array as a supply voltage of the block decoder. |
| US07787295B2 |
Integrated circuit embedded with non-volatile multiple-time programmable memory having variable coupling
A multi-programmable non-volatile device is operated with a floating gate that functions as a FET gate that overlaps a portion of a source/drain region and allows for variable coupling through geometry and/or biasing conditions. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications. |
| US07787294B2 |
Operating method of memory
An operating method of a memory is provided. The memory includes a memory cell array composed of a plurality of memory cells, a plurality of bit lines, and a plurality of word lines. During programming the memory, a column of memory cells is selected. A voltage difference is respectively occurred between a bit line corresponding to first source/drain regions of the memory cells in the selected column and adjacent two bit lines, and a bias is respectively applied to a word line corresponding to a control gate of each memory cell in the selected column so as to allow a data bit of the memory cell at a plurality of predetermined programmed states and an unusable bit of each memory cell in an adjacent column which shares the same bit line with the selected column at an unusable state. |
| US07787293B2 |
Semiconductor memory device
This disclosure concerns a semiconductor memory device including Fin semiconductors extending in a first direction; source layers provided in the Fin semiconductors; drain layers provided in the Fin semiconductors; floating bodies provided in the Fin semiconductors between the source layers and the drain layers, the floating bodies being in an electrically floating state and accumulating or discharging carries so as to store data; first gate electrodes provided in first grooves located between the Fin semiconductors adjacent to each other; second gate electrodes provided in second grooves adjacent to the first grooves and located between the Fin semiconductors adjacent to each other; bit lines connected to the drain layers, and extending in a first direction; word lines connected to the first gate electrodes, and extending in a second direction orthogonal to the first direction; and source lines connected to the source layers, and extending in the second direction. |
| US07787292B2 |
Carbon nanotube fuse element
In one embodiment of the invention, a fuse element for a one time programmable memory may include carbon nanotubes coupled to a first transistor node and to a second transistor node. The carbon nanotubes may have a first resistance which may be changed upon programming the memory cell with low current levels. |
| US07787285B2 |
Independent-gate controlled asymmetrical memory cell and memory using the cell
Techniques are provided for employing independent gate control in asymmetrical memory cells. A memory circuit, such as an SRAM circuit, can include a number of bit line structures, a number of word line structures that intersect the bit line structures to form a number of cell locations, and a number of asymmetrical memory cells located at the cell locations. Each of the asymmetrical cells can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each of the cells can include a number of field effect transistors (FETS), and at least one of the FETS can be configured with separately biased front and back gates. One gate can be biased separately from the other gate in a predetermined manner to enhance read stability of the asymmetrical cell. |
| US07787284B2 |
Integrated circuit chip with improved array stability
A multi-threshold integrated circuit (IC) that may be supplied by multiple supplies, with an array of latches such as an array static random access memory (SRAM) cells and a CMOS SRAM with improved stability and reduced subthreshold leakage. Selected devices (NFETs and/or PFETs) in array cells and support logic, e.g., in the data path and in non-critical logic, are tailored for lower gate and subthreshold leakage. Normal base FETs have a base threshold and tailored FETs have a threshold above. In a multi-supply chip, circuits with tailored FETs are powered by an increased supply voltage. |
| US07787283B2 |
Devices and methods for controlling active termination resistors in a memory system
A termination resistor is mounted on a memory circuit and provides a termination resistance for the memory circuit. The termination resistor includes a node, a plurality of first termination resistors responsive to a corresponding control signal and connected between a power voltage and the node, and a plurality of second termination resistors responsive to a corresponding control signal and connected between a ground voltage and the node. |
| US07787282B2 |
Sensing resistance variable memory
The present disclosure includes devices and methods for operating resistance variable memory. One device embodiment includes an array of memory cells wherein a number of the cells are commonly coupled to a select line, the number cells including a number of data cells programmable within a number of target threshold resistance (Rt) ranges which correspond to a number of data states, and a number of reference cells interleaved with the data cells and programmable within the number of target Rt ranges. The aforementioned device embodiment also includes control circuitry coupled to the array and configured to sense a level associated with at least one data cell and at least one reference cell, and compare the sensed level associated with the at least one data cell with the sensed level associated with the at least one reference cell to determine a data state of the at least one data cell. |
| US07787280B2 |
Electric element, memory device, and semiconductor integrated circuit
An electric element includes a first terminal (1), a second terminal (3), and a variable-resistance film (2). The variable-resistance film (2) is connected between the first terminal (1) and the second terminal (3). The variable-resistance film (2) includes Fe3O4 crystal phase and Fe2O3 crystal phase. |
| US07787279B2 |
Integrated circuit having a resistive memory
An integrated semiconductor memory includes a storage medium (6) arranged between two electrodes (10, 20), which storage medium may be a phase change medium, for example. The storage medium (6) can be put into a first state or a second state by means of an electric current, as a result of which an item of information can be stored. According to embodiments of the invention, a layer plane (L) is provided in which impurity particles made from a material (4) are embedded, as a result of which the current density in the storage medium is locally increased and the programming current required for reprogramming is reduced. As a result, the current consumption of memory elements containing a phase change medium is reduced, so that for the first time they can be embodied with minimal feature size, together with other components such as transistors, and integrated into a single semiconductor circuit and no longer have to be arranged in separate subcircuits. |
| US07787275B1 |
Content addressable memory having programmable combinational logic circuits
A content addressable memory (CAM) device includes a plurality of independently configurable CAM groups, each CAM group including a number of CAM rows and a programmable combinational logic circuit. Each CAM row includes a plurality of CAM cells coupled to a match line that generates a row match signal during a compare operation between a search key and data stored in the CAM row. The programmable combinational logic circuit logically combines the row match signals to generate a corresponding group match signal according to a respective one of a plurality of selectable logical operations selected by a corresponding function select signal. |
| US07787272B2 |
Inverter based storage in dynamic distribution systems including distributed energy resources
A microsource is provided, which includes an inverter, an energy storage device, and a controller. The controller calculates a maximum frequency change for the inverter based on a first comparison between a first power set point and a measured power from the inverter. The first power set point is defined based on a charge level of the energy storage device. A minimum frequency change for the inverter is calculated based on a second comparison between a second power set point and the measured power from the inverter. An operating frequency for the inverter is calculated based on a third comparison between a power set point and a measured power flow. A requested frequency for the inverter is calculated by combining the maximum frequency change, the minimum frequency change, and the operating frequency. The requested frequency is integrated to determine a phase angle of a voltage of the inverter to control a frequency of an output power of the inverter. |
| US07787271B2 |
Power supply start-up and brown-out inrush management circuit
A power supply device including a diode bridge, a converter module, and an inrush control module. The diode bridge is configured to rectify an input voltage. The converter module is coupled to the diode bridge and is configured to convert the input voltage into a direct current regulated output voltage. The inrush control module is connected to the diode bridge and is configured to gradually activate a transistor and to limit an inrush current peak value based upon a zero crossing being detected in the input voltage. A method for limiting the inrush current peak value is also disclosed. |
| US07787269B2 |
Switching power supply device
The present invention provides a switching power supply device including a switching element, a control circuit controlling the switching element, a transformer having an auxiliary winding, a potential clamp circuit connected to one of outputs of the transformer, a delay capacitor connected to an output of the potential clamp circuit, a potential detection circuit detecting a potential at the delay capacitor, and an overload protection actuation circuit realizing overload protection. During an overload, the delay capacitor is charged only by ringing of the auxiliary winding, generated immediately after the switching element is turned off, through the potential clamp circuit. Then, the potential detection circuit supplies an actuation signal to a latch stop circuit by detecting that the potential at the delay capacitor rises. The latch stop circuit latches and stops the switching operation of the switching element to realize the overload protection when the actuation signal is fed into the latch stop circuit. Thus, the overload protection can be realized with a sufficient delay time by the relatively small delay capacitor. |
| US07787255B2 |
Grounding apparatus of portable electronic devices
A grounding apparatus (200) includes at least one conductive member (20), a sliding mechanism (30) and a flexible printed circuit board (40). The sliding mechanism is conductive and electrically connected to the conductive member. The flexible printed circuit board includes a conductive layer (421) and a grounding end (4231), the conductive layer and the grounding end are electrically connected to the sliding mechanism. |
| US07787251B2 |
Printed circuit board employing heat sink retaining apparatus and method of use
A printed circuit board employing a heat sink retaining apparatus and method of use is disclosed. In one form of the disclosure, a heat sink apparatus can include a heat sink operable to be coupled to a first portion of a printed circuit board having an integrated circuit, and a retaining mechanism operably coupled along a first surface of the heat sink. The retaining mechanism can be coupled to a second portion of the printed circuit board to produce a tension between the first surface of the heat sink and the second portion of the printed circuit board. |
| US07787247B2 |
Circuit board apparatus with induced air flow for heat dissipation
A cooling mechanism to dissipate thermal energy generated by the heat generating components of a graphics card assembly. An apparatus includes a circuit board having at least one heat generating component affixed thereto. The apparatus also includes a fan and carrier therefor including a heat sink plate having a portion thermally coupled to the heat generating component. The heat sink plate includes a means for forming at least one slot proximate the portion. The fan is adapted to direct airflow cross the portion. The thermal energy generated by the heat generating component is transferred to the fan carrier and ultimately removed from the fan carrier by the airflow. The airflow inducts a secondary airflow drawn through the slot during operation thereby to enhance transfer of the thermal energy from the heat generating component. |
| US07787243B2 |
Retractable card adapter
Methods and apparatus for interfacing a memory device with a host device are disclosed. According to one aspect of the present invention, an apparatus which enables a non-volatile memory device to communicate with a host device includes a body and an element. The body has a boundary, and the element is arranged to move at least partially within the body. The element includes an interface which may be coupled to the host device when the element is in a first position with respect to the body. The element is also arranged to receive the non-volatile memory device and to move the non-volatile memory device and the interface with respect to the body. In one embodiment, when the element is in the first position with respect to the body, the interface at least partially extends past the boundary associated with the body. |
| US07787231B2 |
High voltage generating circuit, ion generating device and electrical apparatus
A high voltage generating circuit includes a boosting portion (e.g., a trigger coil (22)) for boosting DC voltage delivered from a DC power supply (26) so as to deliver high voltage at a secondary side, a switching element (e.g., a MOSFET (23)) for turning on and off current flowing in the primary side of the boosting portion, and a pulse signal generating portion (24B) for generating a pulse signal for controlling on and off of the switching element. |
| US07787225B2 |
Semiconductor apparatus using back-side high-withstand-voltage integrated circuit
A semiconductor apparatus includes an electroconductive member; a switching device electrically connected to the electroconductive member on the electroconductive member and having a withstand voltage between a front side and a back side as a first withstand voltage; a back-side high-withstand-voltage integrated circuit provided on the electroconductive member separately from the switching device, incorporating a control circuit for controlling turning-on/off of the switching device, and having a withstand voltage between a front side and a back side as a second withstand voltage higher than the first withstand voltage; an insulating substrate provided on the electroconductive member separately from the switching device and the back-side high-withstand-voltage integrated circuit; input/output wiring connected to the insulating substrate; first wiring connecting the insulating substrate and the switching device; and second wiring connecting the insulating substrate and back-side high-withstand-voltage integrated circuit. |
| US07787224B2 |
Protection circuit for an integrated circuit device
The integrated protection circuit according to the invention for ESD protecting an circuit device having at least one pad, e.g. a I/O pad, comprises a first transistor (MPI) whose control outputs are connected between the pad (2, 3) and the control input of a clamp transistor (MN4). The control outputs of the clamp transistor (MN4) are connected between the pad (2, 3) and a reference terminal (4). The protection circuit further comprises a second transistor (MN3) whose control outputs are connected between the control output of the first transistor (.MP 1) and the reference terminal (4). Finally the protection circuit also comprises time-delay elements (R, MN 1) connected between a supply voltage terminal (1) and the control inputs of the first transistor (MP I) and the second transistor (MN3). |
| US07787222B2 |
Over-voltage protection for voltage regulator modules of a parallel power system
A protection circuit for a parallel power system having at least two parallel coupled voltage regulators is disclosed. The protection circuit includes at least two isolation control circuits, each control circuit being coupled to a respective voltage regulator. Each isolation control circuit includes a current sense circuit for sensing current polarity at an output of the respective voltage regulator, and a controller for automatically isolating the respective voltage regulator when an over-voltage condition exists at an output of the parallel power system and a positive current polarity is sensed at the output of the respective voltage regulator. The at least two isolation control circuits isolate only a voltage regulator having positive current outflow during the over-voltage condition. In one embodiment, each isolation control circuit further includes an over-voltage detection circuit for detecting when the over-voltage condition exists at the output of the parallel power system. |
| US07787221B2 |
Tunneling magnetic sensing element including non-magnetic metal layer between magnetic layers
A first pinned magnetic sublayer 4a has a multilayered structure including a first insertion subsublayer disposed between a lower ferromagnetic subsublayer and an upper ferromagnetic subsublayer. The first insertion subsublayer has an average thickness exceeding 3 Å and 6 Å or less. This results in an interlayer coupling magnetic field Hin lower than a known art while RA and the rate of resistance change (ΔR/R) substantially identical to those of the known structure are maintained. |
| US07787220B2 |
Magnetoresistance element with improved magentoresistance change amount and with free layer having improved soft magnetic characteristics
A free layer of an MR element incorporates a first layer, a second layer, a third layer, a fourth layer, a fifth layer and a sixth layer that are stacked in this order on a nonmagnetic conductive layer. The absolute value of magnetostriction constant of the free layer is 1×10−6 or smaller. The coercivity of the free layer is 20×79.6 A/m or smaller. The first layer is made of an alloy containing ‘a’ atomic percent cobalt and (100−a) atomic percent iron wherein ‘a’ falls within a range of 20 to 50 inclusive. The second layer is made of an alloy containing ‘b’ atomic percent cobalt and (100−b) atomic percent iron wherein ‘b’ falls within a range of 70 to 90 inclusive. In addition, oxidation treatment is given to a surface of the second layer farther from the first layer. |
| US07787218B2 |
Data storage device
Embodiments in accordance with the present invention relate to suppressing deterioration in rigidity and dynamic characteristics of a tab even when an initial point of contact between a tab and a ramp during unloading is set closer to the outer periphery of a disk. A data storage device in one embodiment of the present invention includes a head, a ramp for unloading the head, a load beam having a head support portion for supporting the head and a tab adapted to slide on a sliding surface of the ramp on a front end side with respect to the head support portion, and an actuator having the load beam and adapted to actuate the head for loading and unloading. During unloading, a portion of the tab offset from the center in the transverse direction of the tab first comes into contact with the sliding surface of the ramp. The load beam has a flange formed to be bent and continuously from the front end portion of the tab up to both ends of the head support portion. |
| US07787213B1 |
Disk drive flow control plate with integrated air management features
A flow control plate (152) for a disk drive is disclosed. The flow control plate (152) includes both a diffuser section (156) and an air displacement section (168). The diffuser section (156) is contained within a pocket (160) having a plurality of spaced protuberances or ridges (164). The air displacement section (168) may be located upstream of the diffuser section (156) and includes a pair of flat primary surfaces (172) that are disposed in opposing and parallel relation. In one embodiment, the flow control plate (152) is an integral structure and is fabricated from a resinous material. |
| US07787210B1 |
Feed-forward method for repeatable runout cancellation
A magnetic hard disk drive includes a method for eliminating that portion of track following error by a read/write transducer that is caused by repeatable runout of the disk tracks. The repeatable runout is eliminated by application of an iterative algorithm that calculates feed-forward correction terms based on gain coefficients iteratively calculated from the amplitude and phase portions of a Bode plot characterizing the system. The corrective coefficients can be inserted into the hard disk drive at a summing junction that redefines the centerline of the track, or at a summing junction that causes the actuator to follow the repeatable runout and make non-repeatable runout corrections relative thereto. |
| US07787206B2 |
Systems and methods for accessing preamp registers using commands via read channel/hard disk controller interface
A system and method for providing an interface between a read channel and a disk controller. The interface includes a plurality of differential pair signal lines operable o communicate data and control signals between the read channel and the hard disk controller. The data and control signal lines communicate operations for transferring data between the disk controller and the read channel. The operations may be communicated as commands that may be communicated to a preamplifier circuit to access registers in the preamplifier that may be configured to control the preamplifier operation. |
| US07787205B2 |
Detecting and correcting insertion and deletion of bits for bit patterned media storage systems
A method of determining errors in a data storage device is disclosed. The disclosed method includes receiving a first code word from the data storage device. The method further includes determining whether a data error exists in the code word by analyzing a plurality of subsequent code words. Detecting a data error includes calculating first, second, and third checksums for each of a plurality of subsequent code words and determining whether there is an insertion or deletion error based on the calculated checksums. A further method includes receiving location information of errors on a data medium and adjusting a write clock frequency to reduce the probability of creating errors on the data medium during a write process. |
| US07787204B2 |
Error correction coding of longitudinal position information
A sequential data storage medium, comprising a sequence of plurality of servo patterns that provide lateral position information and longitudinal position information, wherein each of the plurality of servo patterns comprises a first burst comprising a first plurality of pulses, a second burst comprising a second plurality of pulses, a third burst comprising a third plurality of pulses, and a fourth burst comprising a fourth plurality of pulses. The spacings between the first plurality of pulses, in combination with the spacings between the second plurality of pulses, encode a first bit without affecting the recovery of lateral position information. The spacings between the third plurality of pulses, in combination with the spacings between the fourth plurality of pulses, encode a second bit without affecting the recovery of lateral position information. The sequence of plurality of servo patterns comprises a sequence of the first bits and a sequence of the second bits to form an error-correction codeword providing error-correction capability. |
| US07787203B2 |
Error correction mapping
A method according to one embodiment includes receiving signals from multiple readers; and performing more error control processing on a signal from an outer reader than on a signal from an inner reader. A method according to one embodiment includes receiving signals from multiple readers; and performing different amounts of error control processing on signals from at least two of the readers. A tape drive system according to one embodiment includes a tape head having an array of readers; and a processor coupled to the head for performing error control processing, wherein the processor performs more error control processing on a signal from the outer reader than on a signal from the inner reader. |
| US07787200B2 |
Disk-device correcting system, information managing device, master-disk producing device, and master-disk producing method
A master-disk producing device produces a master disk with master-disk identification information added. A disk producing device produces a first disk with the master-disk identification information added, using the master disk with the master-disk identification information added. A first disk device obtains, after the first disk with the master-disk identification information added is mounted, first correction information from a correction-information storing device based on the master-disk identification information of the first disk. |
| US07787199B2 |
Camera module and method for making the same
A camera module includes a lens barrel, a lens, a sensing element, and an electromagnetic shield. The lens barrel defines a receiving space. The lens is mounted in the receiving space. The sensing element is covered by the lens barrel, is disposed below the lens, and is spaced apart from the lens. The sensing element includes a top face, a bottom face, a side face extending between the top and bottom faces, a plurality of first conductors mounted on the bottom face, at least one second conductor mounted on one of the top, bottom, and side faces, and a grounding element having one end connected to one of the first conductors and the other end connected to the second conductor. The electromagnetic shield is coupled to the lens barrel and includes a grounding portion electrically connected to the second conductor. |
| US07787187B2 |
Laser irradiation apparatus, laser irradiation method, and method for manufacturing semiconductor device
Providing a method and apparatus for efficiently irradiating a uniform laser light on an irradiation surface even when a laser light of high coherence or a large size substrate is used. The laser irradiation apparatus of the invention comprises a laser; means for dividing a laser light emitted from the laser into plural laser beams; means for synthesizing the laser beams on the irradiation surface or place in the vicinity thereof thereby forming a laser light having a periodical energy distribution; and means for moving the substrate relative to the laser light. Such a laser irradiation apparatus may be used to anneal the overall surface of a semiconductor film. |
| US07787184B2 |
Member having antireflection structure
A reflection of unnecessary light, which should be prevented, can be suppressed, and occurrence of stray light can be reduced using a member having an antireflection structure, comprising a plate-like portion 2, and an aperture portion 3 formed in the plate-like portion 2, wherein the antireflection structure having an aspect ratio of 1 or more and comprising structural elements arranged in an array form at a period smaller than the shortest wavelength of light, the reflection of which should be prevented, is formed on an inner wall 4 of the aperture portion 3. |
| US07787180B2 |
Discontinuous or variable thickness gain modification coating for projection film and method for making same
The present invention relates to projection films and methods of making the same. In particular, the present invention relates to a projection film whereby the microspheres exhibit improved alignment on the light exit surface and have alignment on the light entrance surface that varies according to the individual microsphere diameter. In another embodiment, the present invention relates to a projection film that has the attributes of variable gain within the single projection film. In another embodiment, the present invention relates to an exposed microsphere projection film construction that provides modification of the head-on and angular pattern of light transmission (gain). |
| US07787178B2 |
Objective-lens guiding device and objective lens unit
Without setting an examination site, it is possible to easily position an end face of a narrow-diameter end portion at a suitable position with respect to an examination target, allowing an image of the examination site to be acquired quickly and easily. The invention provides an objective-lens guiding device comprising a support portion secured to an objective lens having a narrow-diameter end portion; and a cylindrical portion for accommodating the narrow-diameter end portion. The support portion supports the cylindrical portion such that a front end of the cylindrical portion is disposed at a location farther toward the front than an end face of the narrow-diameter end portion, and so as to be capable of moving in an optical axis direction. |
| US07787177B2 |
High-NA projection objective with aspheric lens surfaces
A projection objective for imaging a pattern provided in an object surface onto an image surface of the projection objective has an object-side imaging subsystem for creating a final intermediate image closest to the image surface from radiation coming from the object surface and an image-side imaging subsystem for directly imaging the final intermediate image onto the image surface. The image-side imaging subsystem includes at least one aspheric primary correcting lens having an aspheric primary correcting surface. The object-side imaging subsystem includes a secondary correcting group having at least one secondary correcting lens having an aspheric secondary correcting surface. Conditions involving maximum incidence angles and subaperture offsets at the correcting surfaces are given which should be observed to obtain sufficient aberration correction at very high image-side numerical apertures NA. |
| US07787172B2 |
Gamma correction for adjustable light source
The present invention provides a projection apparatus, that includes: a light source; a light source control unit for controlling the output of the light source; at least one spatial light modulator for modulating the illumination light from the light source by a plurality of pixel elements; and an optical system for projecting, onto a screen, the illumination light deflected by the spatial light modulator, wherein: the light source control unit performs a gamma (γ) correction on input image data by a modulation control of the light source. |
| US07787170B2 |
Micromirror array assembly with in-array pillars
The present invention provides a microstructure device comprising multiple substrates with the components of the device formed on the substrates. In order to maintain uniformity of the gap between the substrates, a plurality of pillars is provided and distributed in the gap so as to prevent decrease of the gap size. The increase of the gap size can be prevented by bonding the pillars to the components of the microstructure. Alternatively, the increase of the gap size can be prevented by maintaining the pressure inside the gap below the pressure under which the microstructure will be in operation. Electrical contact of the substrates on which the micromirrors and electrodes are formed can be made through many ways, such as electrical contact areas, electrical contact pads and electrical contact springs. |
| US07787169B2 |
Electro-optic displays, and methods for driving same
The invention relates to electro-optic displays and methods for driving such displays. The invention provides (i) electrochromic displays with solid charge transport layers; (ii) apparatus and methods for improving the contrast and reducing the cost of electrochromic displays; (iii) apparatus and methods for sealing electrochromic displays from the outside environment and preventing ingress of contaminants into such a display; and (iv) methods for adjusting the driving of electro-optic displays to allow for environmental and operating parameters. |
| US07787167B2 |
Display apparatus using micro mirror unit, and method for controlling micro mirror unit
In a method for driving a micro mirror such as MEMS mirror and a display apparatus using the method, there are provided a mirror driving unit for driving the micro mirror which operates in a resonant mode and a nonresonant mode, a driving-condition setting unit for setting a mirror driving condition, a switching unit for switching on/off a mirror driving signal in the nonresonant mode, and a look-up table for indicating the relationship of a mirror response with respect to the driving condition already known in advance. The switching unit controls the transmission of the nonresonant-mode mirror driving signal while grasping the mirror response state with respect to the mirror driving signal, thereby finely increasing and decreasing a driving torque for the micro mirror. This fine increase and decrease allows the micro mirror to be fluctuated stably, and a further enhancement in the fluctuation rate. |
| US07787166B2 |
Method for controlling image forming apparatus
An image forming apparatus that previously rotates a polygonal mirror drive motor before starting a job and forms a latent image by using an optical scanning unit including the polygonal mirror drive motor is provided. The image forming apparatus includes a control unit configured to perform control such that, in the determination of the presence or absence of each of color toners before a previous rotation is started, if it is determined that any one of the color toners is absent, only the polygonal mirror drive motor corresponding to a black toner is previously rotated. |
| US07787163B2 |
Method of sharpening an RGB image for sending to a printhead
The invention provides for a method of sharpening an image to be sent to a printhead. The method includes the steps of receiving an RGB (red, green, blue) data set indicative of the image, and deriving an initial luminance channel from the received data set. The method also includes the steps of sharpening the initial luminance channel to form a revised luminance channel, and incorporating the revised luminance channel into the data set. |
| US07787162B2 |
Smart start of scan (SOS) detector
A technique for achieving a smart start of scan (SOS) detector that is related with line scan timing on raster output scanners by expanding the available functions to include beam size and position. A start of scan detection system adapted to provide beam size and position control. The system includes a CPU, a data source and laser driver managed by the CPU, and a multiple element pre-patterned detector managed by the CPU and enabling a sensor pattern through which laser beams from the laser driver are passed and detected. According to a method for managing beam size and position in a image processing system, a multiple element pre-patterned detector adapted to enable a sensor pattern is provided wherein at least one laser beam is passed through said sensor pattern enabled by the multiple element pre-patterned detector, analyzed and used by the image processing system to adjust beam size and position. |
| US07787158B2 |
Data processing apparatus, image processing apparatus, data processing method, image processing method, and programs for implementing the methods
A data processing apparatus that is capable of improving the accuracy with which form types can be identified. An image file of a form and an additional file including a form type ID of the form are inputted. A character recognition process on the image file is carried out based on the form type ID. The image file and a result obtained in the character recognition process are stored in a storage device 103. |
| US07787157B2 |
Image reading apparatus, image reading method and image processing apparatus
An image reading apparatus is disclosed. The image reading apparatus provides plural sensors and a correction unit that corrects displacement of image data caused by intervals among the plural sensors and includes a first draft reading mode whose scanning direction by the sensors is the same as at the time of shading correction and a second draft reading mode whose scanning direction by the sensors is different from at the time of shading correction. The correction unit includes plural paths in which a different number of delay units are disposed in each path and changing over units that change over a connection between the sensors and the paths. The changing over units are changed over between at the time of reading image data and the shading correction in the first draft reading mode and at the time of reading image data in the second draft reading mode. |
| US07787155B2 |
Communications device and communications method
In a communications device, a terminal machine transmits/receives data over a network and makes a request for a response to a data transmission from a receiving-end machine. In the terminal machine, an e-mail message identifying unit determines whether data to be received over the network is response data to the response request, and a main control unit controls so as to preferentially receive data identified as the response data by the e-mail message identifying unit over other data. Thus, if an e-mail message is transmitted with a request for a disposition verification, a reply message to the disposition verification request can be quickly received from the receiving-end machine. |
| US07787154B2 |
Font printing system having embedded security information comprising variable data periodic line patterns
A method and system is provided for providing a variable data guilloché shaped pattern comprised of variable data differential line pattern fonts comprising decodable template symbols which are capable of being selectively assembled into a predetermined variable data code. The code representations are embedded in the guilloché pattern amongst a plurality of unvaried standard base patterns. The representation can be decoded with a digital scan capable of identifying the embedded patterns and communicated it to a user for verifying a document containing the code. |
| US07787153B2 |
Image forming apparatus and image forming method
An image forming apparatus capable of recording image information and additional information added separately from the image information to a photographic printing medium is disclosed. The image forming apparatus includes: image information acquisition means for acquiring the image information, additional information acquisition means for acquiring the additional information, and recording means for recording the image information acquired by the image information acquisition means and the additional information acquired by the additional information acquisition means to the photographic printing medium, wherein the recording means can record the additional information by laminating a first transparent material that absorbs light of a specific wavelength and a second transparent material that does not absorb the light on a recording surface of the photographic printing medium. |
| US07787151B2 |
Tone setting for monochrome image using ink color diagram
A color tone setting window 100 that includes an ink color circle 110 is displayed in order to set a color tone of a monochrome image. By specifying a point Pcc in the ink color circle 110, intensities of color components representing three chromatic primary color inks are specified. The color component intensities representing three chromatic primary color inks are determined as parameters defining the color tone of the monochrome image in accordance with the position of the specified point Pcc in the ink color circle 110. The ink color circle 110 is configured such that the color component intensities representing three chromatic primary color inks can be visually recognized from the position in the ink color circle 110. Alternatively, ink color sliders can be used in lieu of the ink color circle 110. |
| US07787144B2 |
Storage medium storing image processing program, image processing apparatus and image processing method
A storage medium readable by a computer, stores a program of instructions executable by the computer to perform a function for executing an image processing on an image defined by vector data containing a plurality of lines having different line widths, the function including calculating the line widths of the plurality of lines so as to maintain the number of types of line widths of the plurality of lines and a thinner-or-thicker relation among the line widths of the plurality of lines before executing the image processing, and setting the line widths calculated by the calculating step as line widths of the plurality of lines after the image processing. |
| US07787142B2 |
Method and system for designing the color of a coating composition on an article
A method of designing the appearance of an article having steps of creating a digital file of a design configuration for an article, representing the design configuration on a computer screen, selecting or creating a color for a coating composition to be applied to the article, generating color data for the created color, merging the color data with the digital file of the design configuration, and displaying on the computer screen an image of the article coated with the colored coating composition. Accurate calibration of the color of the article on a computer screen allows for production of coated articles based on the generated color data. The color data is further transmitted to a formulation computer that determines the formulation for a coating composition exhibiting the color data. Output from the formulation computer may be directly transmitted to a production facility for coating articles with the coating composition. |
| US07787140B2 |
Printing system and method of printing data on a designated paper
A printing system which includes a printer connected with at least one user terminal by a wire or wirelessly to print printing data transmitted from the user terminal, prevents printing of data before a special printing job and a printing method for the same. In the printing system, the user terminal connectable with the printer includes a printer driver to set a pause mode to temporarily prevent a printing operation in the printer, and a monitoring program unit to monitor an operation status of the printer and to display information supplied from the printer on the pause-set printing data. The printer includes a control unit to inform the user terminal the pause-set printing data is printed, upon receiving the pause-set printing data and to control second printing data supplied from a second user terminal to stand by. |
| US07787137B2 |
Image forming apparatus, user restriction method and use history generation method
An image forming apparatus is provided, in which the image forming apparatus includes: a user database in which user identification information for identifying an user of the image forming apparatus is registered; an operation panel for receiving a key operation input; a secure program used for determining whether a user service can be provided on the basis of the user identification information in the user database and another user identification information input by the user. |
| US07787135B2 |
System and method for developing a configuration for a combination of two of more printshops
A system is provided for forming a print shop configuration with a first set of equipment, the first set of equipment being derived from a second set of equipment from a first print shop and a third set of equipment from a second print shop. The system includes a print shop configuration manager for determining whether a selected relationship exists between (1), one or more sets of job requirements and at least one of a set of print processing related cells or (2) two sets of print processing related cells. A possible print shop configuration may be discarded or prioritized, based on the existence of the selected relationship. |
| US07787134B2 |
Multiple fanned laser beam metrology system
Systems and techniques for laser metrology. Two or more fanned probe beams are scanned relative to a surface including one or more targets. A position detection module receives return beam information from the fanned probe beams, and determines a position of at least a first target of the one or more targets based on the return beam information. |
| US07787133B2 |
Optical displacement-detecting mechanism and probe microscope using the same
The optical displacement-detecting mechanism has: a light source for irradiating a target for measurement with light; a light source-driving circuit for driving the light source; an optical detector made from a semiconductor for receiving light after the irradiation of the target for measurement by the light source and converting the light into an electric signal thereby to detect an intensity of light; and an amplifier including a current-voltage conversion circuit for performing current-to-voltage conversion on a detection signal of the optical detector with a predetermined amplification factor. In the optical displacement-detecting mechanism, a light source having a spectrum half width of 10 nm or larger is used, whereby the light source can be driven with an output power of 2 mW or larger without generating mode hop noise and optical feedback noise. |
| US07787127B2 |
System and method to determine chromatic dispersion in short lengths of waveguides using a common path interferometer
The present invention relates to a system and method to determine chromatic dispersion in short lengths of waveguides using a two wave interference pattern and a common path interferometer. Specifically the invention comprises a radiation source operable to emit radiation connected to a means for separating incident and reflected waves; the means for separating incident and reflected waves possessing an output arm adjacent to a first end of the waveguide; and the means for separating incident and reflected waves further connected to an optical detector operable to record an interference pattern generated by a reflected test emission from the radiation source. The interference pattern consists of two waves: one reflected from a first facet of a waveguide and the second reflected from a second facet of the same waveguide. |
| US07787126B2 |
Method and apparatus for conjugate quadrature interferometric detection of an immunoassay
A detection system for detecting target material is provided. The system comprises a photonic structure having a reflectance-band and associated side bands; an illumination source for illuminating at a wavelength in at least one of an edge of the reflectance-band and the side bands of the photonic structure and for generating a return beam; a detector system having an intensity-sensitive channel configured to detect an in-line signal from the return beam and a phase-sensitive channel configured to detect a differential phase contrast signal from the return beam; and a processing system for receiving and adding in quadrature the in-line signal and the differential phase contrast signal to generate a joint signal, and for determining one of the presence or the absence of the target material on the photonic structure using the joint signal. |
| US07787125B2 |
Apparatus for measuring a spectral distribution of a printed product produced with a printing device
An apparatus (10) measures a spectral distribution of a printed product (12) produced with a printing device. The apparatus (10) has an illuminating source (20) for illuminating the printed product (12), an optoelectronic measuring means (32) for measurer the reflectance value of a section of the spectrum of the light (26) reflected from the printed product (12), an optical disperser (28) for dispersing the wavelengths of the reflected light (26), and a light entry gap plane that is definitive for the disperser (28). The light entry gap plane that is definitive for the disperser (28) is created by the surface of the printed product (12) to be examined. |
| US07787123B2 |
Two line gas spectroscopy calibration
A method of calibrating an absorption spectroscopy measurement wherein the calibration method includes projecting laser light through a sample of a first quantity of a gas of interest and a second irrelevant quantity of a spectroscopically identical or similar gas (10). The first and second spectroscopic absorptions of the laser light are measured over specific first and second absorption lines. A functional relationship is determined between the first and second measured spectroscopic absorptions and two unknown variables. The function relationships may then be simultaneously solved to determine one or both unknown variables and thereby obtain a measurement relating to the first quantity of the gas of interest, calibrated for the second irrelevant quantity of gas. |
| US07787122B2 |
Optical waveform measurement device and measurement method thereof, complex refractive index measurement device and measurement method thereof, and computer program recording medium containing the program
A light-waveform measuring device and method include a complex-refractive-index measuring device and a computer-program recording medium An electric field of an electromagnetic wave, in a light region having wavelengths smaller than those of electromagnetic waves in a near-infrared region, is measured, and time-varying waveforms are outputted. Gate-pulse-light generating means, measurement-light generating means and light-detecting means for detecting measurement light, are included, The measurement light is coherent light having a wavelength smaller than those of a near-infrared region. The gate pulse light is coherent light with a pulse width smaller than a period of the measurement light. A physical quantity, based on carriers generated from the measurement light and the gate pulse light is measured. |
| US07787120B2 |
Spectrophotometer and liquid chromatography system
Detection sensitivity is improved by increasing the amount of light of beams that irradiate a sample cell without causing saturation of a detector with ultraviolet beams or visible beams. This spectrophotometer includes a sample cell, which stores a sample to be measured, a visible light source and an ultraviolet light source each for supplying an incident beam that enters the sample, a spectroscope, which disperses a beam that has passed through the sample, an optical detector, which detects beams dispersed from such beam (spectrum), and a dichroic element which reflects or transmits ultraviolet beams from the ultraviolet light source and which transmits or reflects visible beams from the visible light source. Optics are configured such that ultraviolet beams and visible beams that have passed through or have been reflected by the dichroic element enter the sample cell. |
| US07787119B2 |
Method for remote sensing of targets in a transparent medium using ultra-short intense lasers
There is described a method for identifying at least one target in a substantially transparent medium. High-power, ultra-short laser pulses are transmitted into the medium. A diameter of the laser pulses is enlarged and the laser pulses having an enlarged beam diameter are focused using a focusing element so as to generate filaments substantially near a geometrical focal zone of the focusing element, whereby a spontaneous fluorescence signal (amplified through amplified spontaneous emission or not) is detected and analyzed to identify the target. |
| US07787117B1 |
Method and apparatus for in situ measurement of material properties by surface enhanced raman spectroscopy
In apparatus for performing Surface Enhanced Raman Spectroscopy (SERS), rather than applying a sample to be analyzed to an SERS active substrate, the SERS active substrate is applied to the sample using an inkjet nozzle to apply a substance containing a colloidal metal, such as silver, to the sample. The prepared sample is then analyzed with a Raman spectrometer in a conventional fashion. |
| US07787115B2 |
Optical apparatus for defect inspection
An optical apparatus for defect inspection having an illuminating optical system for irradiating illumination light beams on the surface of a specimen to form a beam spot and a detection optical system for detecting a reflection light ray originating from the beam spot comprises a storage unit in which the position and size of a standard particle of known size on a specimen for correction are stored in advance, a correction processing section which, when the correction specimen is used as an inspection target, correlates a detected scattering light quantity from the standard particle with the known size of standard particle stored at a corresponding position in the storage unit to prepare a correlation between the scattering light quantity and a true value, and a signal processing section which, when an inspection wafer is used as an inspection target, converts a detected scattering light quantity into a defect dimension. |
| US07787113B2 |
Method for optically detecting an electrical arc in a power supply
A method for optically detecting an electrical arc in a power supply. The method includes capturing light with a light pipe, transmitting the captured light along at least a portion of a length of the light pipe, optically detecting the transmitted light with a photodetector which is optically coupled to the light pipe, generating a signal indicative of an intensity of the detected light, and determining whether the detected light is associated with an electrical arc. |
| US07787108B2 |
Inline stress evaluation in microstructure devices
By performing optical measurements and evaluating the optical response of an appropriately prepared measurement site, stress-related characteristics, such as intrinsic stress of dielectric layers, may be evaluated due to the dependency of the optical response on stress-induced modifications of the charge carrier mobility of a conductive layer provided below the dielectric layer probed by an optical signal. Consequently, inline measurement results may be obtained in a highly efficient manner, thereby providing the potential for monitoring complex stress engineering strategies during a manufacturing sequence for forming microstructure devices. |
| US07787107B2 |
Motion measurement and synchronization using a scanning interferometer with gratings
Indicating relative speed is disclosed. A first grating coupled to a first moving object is illuminated using a coherent light source to generate a first diffracted beam and a diffracted order beam. A second grating coupled to a second moving object is illuminated using the first diffracted beam and the second diffracted beam to generate a third diffracted beam and a fourth diffracted beam. The third diffracted beam and the fourth diffracted beam are measured. A relative speed of the first moving object with respect to the second moving object is indicated based at least in part on the measured third diffracted beam and the measured fourth diffracted beam. |
| US07787104B2 |
Illumination optics for a microlithographic projection exposure apparatus
Illumination optics for a microlithographic projection exposure apparatus is used for illumination of an object field in the object plane with illumination light of a radiation source. The illumination optics has an optical beam influencing element which is divided into at least two beam influencing regions in order to generate various illumination modes for the object field which are independent of a light attenuation. The optical beam influencing element is displaceable between a first beam influencing position where a first one of the beam influencing regions is exposed to a bundle of the illumination light, and at least another beam influencing position where another one of the beam influencing regions is exposed to the bundle of the illumination light. Each of the beam influencing regions has a surface which is exposable to illumination light and has a long and a short side length, with the optical beam influencing element being displaceable perpendicular to the long side length. The result is an illumination optics which allows rapid switching between various illumination settings, preferably within fractions of a second and substantially without light loss. |
| US07787103B2 |
Projection exposure apparatus, optical member, and device manufacturing method
A projection exposure apparatus 100 projects the pattern of an original 6 onto a substrate 7 via a projection optical system PL. The projection exposure apparatus 100 includes an original stage 5 which holds the original 6, a substrate stage 8 which holds the substrate 7, and a measurement unit. The measurement unit includes a Fizeau interferometer IF including an optical unit 17 and mirror 22. The optical unit 17 includes a Fizeau surface which splits a light beam into a reference light beam and a test light beam. The mirror 22 reflects the test light beam having passed through the projection optical system PL. The optical unit 17 is mounted on the original stage 5. The mirror 22 is mounted on the substrate stage 8. |
| US07787100B2 |
Liquid crystal display with wide viewing angle with overlapping coupling electrodes forming capacitor interconnecting sub-pixel electrodes
A method of manufacturing an active matrix substrate is presented. The method includes forming a transistor having a gate line, a semiconductor layer, an insulating layer between the gate line and the semiconductor layer, a source electrode, and a drain electrode; forming a pixel electrode comprising a first sub-pixel electrode and a second sub-pixel electrode; forming an auxiliary coupling electrode connected to the second sub-pixel electrode through a first contact hole; and forming the first sub-pixel electrode through a second contact hole connected to the drain electrode of the transistor. The auxiliary coupling electrode and the first sub-pixel electrode overlap each other such that the second sub-pixel electrode is capacitively coupled to the first sub-pixel electrode and the auxiliary coupling electrode and the electrode part form a capacitor. |
| US07787096B2 |
Liquid crystal display device and manufacturing method thereof
A liquid crystal display panel includes a first substrate, a second substrate, and a liquid crystal layer formed between the first substrate and the second substrate. A pixel area is formed on the first substrate, and a driver is formed on the substrate and electrically connected with the pixel area. A plurality of lines are electrically connected with the driver, and a plurality of pads are electrically connected with the plurality of lines. The plurality of pads are formed in a straight line and are not electrically connected with each other except for the electric connection with the plurality of lines. |
| US07787095B2 |
Thin film transistor array panel and method of manufacturing the same
A thin film transistor array panel including a substrate, a plurality of first signal lines formed on the substrate, a plurality of second signal lines, insulated from the first signal lines, which are formed on the substrate and which define an area of a display area by traversing the first signal lines, a driver disposed on a peripheral area, a plurality of connection lines, disposed on the peripheral area, which couple the driver to each of the first signal lines, and an insulating layer which insulate the first signal lines from the connection lines. The insulating layer includes a plurality of contact holes, portions of the first signal lines and the connection lines are connected through the contact holes, and sizes of exposed portions of the first signal lines exposed through the contact holes increase as respective distances from the contact holes to the driver increase. |
| US07787094B2 |
Liquid crystal panel with adjoining adhesive strips and liquid crystal panel assembly and liquid crystal display with same
An exemplary liquid crystal panel includes (1) a first substrate (11), a second substrate (12) opposite to the first substrate, a first adhesive strip (13) provided at a periphery of the liquid crystal panel between the first and second substrates, and at least one second adhesive strip (14) in direct contact with an outside of the first adhesive strip. The first and second substrates are bonded to each other by the first adhesive strip and the at least one second adhesive strip. |
| US07787087B2 |
Liquid crystal display having wide viewing angle
A tetragonal ring shape aperture is formed in the common electrode on one substrate and a cross shape aperture is formed at the position corresponding to the center of the tetragonal ring shape aperture in the pixel electrode on the other substrate. A liquid crystal layer between two electrodes are divided to four domains where the directors of the liquid crystal layer have different angles when a voltage is applied to the electrodes. The directors in adjacent domains make a right angle. The tetragonal ring shape aperture is broken at midpoint of each side of the tetragon, and the width of the aperture decreases as goes from the bent point to the edge. Wide viewing angle is obtained by four domains where the directors of the liquid crystal layer indicate different directions, disclination is removed and luminance increases. |
| US07787085B2 |
Optical alignment method and liquid crystal display element
An optical alignment method which develops a pretilt angle by batch plane exposure without tilting a substrate. This optical alignment method provides liquid crystal aligning capability to the surface of a polymer film by exposing the surface of the polymer film through a slit exposure mask while the surface of the polymer film and the slit exposure mask are moved relative to each other substantially at a fixed rate. Alternatively, liquid crystal aligning capability is provided to the surface of the polymer film by exposing the surface of the polymer film through an optical exposure pattern while the optical exposure pattern having a plurality of lines with a certain width at certain intervals is formed on the surface of the polymer film continuously. |
| US07787084B2 |
Optical compensation film, polarizing plate and liquid crystal display device
Provided are a liquid crystal display device, in particular, an optical compensation film and a polarizing plate having an excellent optical compensation function for OCB mode liquid crystal display device which has a rapid response speed and a suitability for moving images and capable of further contributing to thinning the liquid crystal display device, as well as the OCB mode liquid crystal display device having a high display grade, the rapid response speed, the suitability for moving images and a high transmittance. For this purpose, a roll-shaped lengthy optical compensation film wherein values of Re(0°), Re(40°) and Re(−40°) thereof are in the ranges of 37±6 nm, 50±6 nm and 124±12 nm, respectively is provided. |
| US07787081B2 |
Photo-sensitive element and liquid crystal display with the same
A photo-sensitive element, a readout pixel with the photo-sensitive element, and a liquid crystal display with the readout pixels are described. The photo-sensitive element includes a switch TFT and a photo detecting device. The hate electrode of the switch TFT is electrically connected to a switch line and the source electrode of the switch TFT is electrically connected to a readout line. The photo detecting device is connected between the switch line and the drain electrode of the switch TFT for detecting the brightness of a light incident thereon. The photo detecting device is preferably a photo TFT, a photo diode, or a light sensitive resistor. The photo TFT and the switch TFT are preferably amorphous silicon transistors. The switch line is preferably a gate line disposed on the TFT array substrate of the crystal display. |
| US07787077B2 |
Liquid crystal display apparatus
The liquid crystal display apparatus according to the present invention includes a first substrate, a second substrate, a reflective polarizer, mounted on the first substrate and having a first transmission axis and a first reflection axis at right angles to each other, for transmitting linearly polarized light vibrating in a plane parallel to the first transmission axis and for reflecting linearly polarized light vibrating in a plane parallel to the first reflection axis, a polarizer, mounted on the second substrate and having a second transmission axis, for transmitting linearly polarized light vibrating in a plane parallel to the second transmission axis, and a liquid crystal layer, provided between the first and second substrates, having a first mode which causes the direction of polarization of incident light to change by utilizing birefringence and a second mode which does not utilize birefringence and therefore does not cause the direction of polarization of incident light to change, wherein a display state is switched between a bright display state and a dark display state by applying a voltage to the liquid crystal layer, and the bright display state is produced by driving the liquid crystal layer in the second mode. |
| US07787071B2 |
Display device
A display device 1 of an embodiment of the invention has a first display panel (10A), a second display panel (10B) that is disposed behind the first display panel (10A), a front rim 20 that is disposed in front of the first display panel (10A), an intermediate cases (30, 35) that are disposed between the first display panel (10A) and the second display panel (10B), and support the first display panel (10A) and the second display panel (10B), and a backlight 40 that is provided behind the second display panel (10B). At least the front rim 20, intermediate cases (30, 35) and backlight 40 are provided with fixing holes 23a, 33a, 38a, 44a in their corners, and fixing is effected integrally at each corner. Thanks to such structure, a display device is provided in which the distance between the two display panels can be altered by an inexpensive method. |
| US07787070B2 |
Liquid crystal display device having a wire securing member
A liquid crystal display device capable of securing the lamp wire to the mold frame is disclosed. The liquid crystal display device includes a liquid crystal display panel for displaying an image, a back light assembly for providing a light to the liquid crystal display panel and a mold frame receiving the liquid crystal display panel and the backlight assembly. The back light assembly includes a light supplying part including a light source for generating a light and a lamp wire for supplying an electrical current to the light supplying part. A securing portion for securing the lamp wire is formed on a side surface or a rear surface of the mold frame, shaped as a groove or a depressed portion, and the lamp wire is secured to the securing portion in such a way that securing and separation of the lamp wire is performed with ease and simplicity. A pair of securing ribs are formed on the bottom of the securing depressed portions facing each other. The lamp wire is secured in the space between a pair of the securing ribs having a width less than a diameter of the lamp wire. Accordingly, a connection failure of the soldering portion of the lamp wire due to a sway of the lamp wire is reduced and the repeated process of securing the lamp wire in manufacturing the LCD device is no longer necessary. |
| US07787069B2 |
Display device and manufacturing method thereof
A display device includes: a light source; a light guide plate including a light emitting surface that emits light incident from the light source; a light source board including the light source arranged thereon, the light source board arranged in close proximity to a side surface of the light guide plate; a rear frame arranged to support the light guide plate and including a protruding portion formed on a side surface of the rear frame; a middle frame arranged to support the light guide plate and the rear frame and including a notch portion where the protruding portion of the rear frame penetrate; and a display panel whose horizontal position is regulated by the protruding portion of the rear frame penetrating the notch portion of the middle frame. |
| US07787068B2 |
Array substrate for liquid crystal display device and method of fabricating the same
Array substrates for liquid crystal display (LCD) devices are formed on a substrate with first and second gate lines crossing a data line to define first and second pixel regions. A thin film transistor includes a source electrode and a drain electrode. A metal pattern overlaps a common line and makes up a portion of the drain electrode. A passivation layer is disposed on the source and drain electrodes and on the metal pattern. A first pixel electrode is connected to the metal pattern and a common electrode is connected to the common line. Various repair patterns are formed to define one or more repairing portions that enable connection of the drain electrode or metal pattern to a second pixel electrode of the second pixel region if the cut line is cut in the event the first pixel electrode fails to display an image. |
| US07787066B2 |
Display panel, display apparatus having the same, and method of manufacturing the same
A display panel including a first capacitor and a second capacitor is disclosed. The first and second capacitors boost a second driving voltage from a driving chip and apply the boosted second driving voltage to the driving chip. The driving chip receives the boosted second driving voltage and outputs a first driving voltage to drive the display panel. Thus, the display panel does not require any additional capacitor for boosting the second driving voltage, thereby reducing a thickness and a manufacturing cost of the display panel. |
| US07787064B2 |
Automatic holographic display device having cholesteric liquid crystal panel with barrier and slit regions and first and second phase difference plates above and below the panel
Provided is an automatic holographic display device including: a first liquid crystal panel, a second liquid crystal panel disposed below the first liquid crystal panel, and a backlight that is disposed below the second liquid crystal panel and emits light, wherein the second liquid crystal panel comprises a cholesteric liquid crystal panel in which a barrier region and a slit region are alternately arranged according to an applied electric field, a first phase difference plate disposed above the cholesteric liquid crystal panel, and a second phase difference plate disposed below the cholesteric liquid crystal panel, wherein the backlight comprises a reflection plate that reflects light. The automatic holographic display device includes a modulated cholesteric liquid crystal panel and a phase difference plate, and thus mutual conversion between 2D flat images and 3D holographic images can be easy, the process of manufacturing the device can be simplified, and the manufacturing costs can be decreased. In addition, an automatic holographic display device in which optical transmittance can be improved by the modulated cholesteric liquid crystal panel and the phase difference plates, and luminance reduction that commonly occurs using a parallax barrier method can be prevented is provided. |
| US07787060B2 |
Video apparatus and method of controlling the same
A video apparatus having a display module and a method of controlling the same are provided, whereby an electric field strength or automatic gain control (AGC) signal is recognized from a received broadcast signal and a power supply mode of the display module is controlled according to a level of the recognized AGC signal, to prevent an overheating of the display module without using an additional device. The video apparatus includes a display module for displaying a broadcast signal received via a broadcast channel, the display module being selectively driven according to one of a plurality of power supply modes; and a controller for controllably setting the power supply mode of the display module according to the strength of an electric field of the received broadcast signal, the controller maintaining the set power supply mode if the electric field strength lies between lower and upper thresholds defining a threshold region. |
| US07787059B2 |
Digital television receiver
A ATSC compliant digital television (DTV) receiver including an image rejection filter, an interpolator, a numerically controlled oscillator (NCO), a matched filter unit, a frequency converter, and a DC remover. The image rejection filter removes (filters out) an unwanted image signal and an adjacent channel's interference signal from a first intermediate frequency (IF) signal sampled at a first sampling frequency. The interpolator resamples (at a second sampling frequency) a signal output from the image rejection filter and compensates for a predetermined symbol timing offset in response to a first control signal, thereby outputting a second IF signal. The NCO down converts the second IF signal and simultaneously compensates for a predetermined carrier offset in response to a second control signal, thereby outputting a first complex signal. The matched filter unit receives the first complex signal and filters the first complex signal, thereby outputting a second complex signal. The frequency converter generates a third complex signal having a double side band from the second complex signal output from the matched filter unit. The DC remover removes (filters out) a pilot signal from a DC signal included in the third complex signal output from the frequency converter. |
| US07787053B2 |
VSB reception system with enhanced signal detection for processing supplemental data
A VSB reception system includes a sequence generator for decoding a symbol corresponding to the supplemental data and generating a predefined sequence included in the supplemental data at VSB transmission system. The reception system also includes a modified legacy VSB receiver for processing the data received from the VSB transmission system in a reverse order of the VSB transmission system by using the sequence, and a demultiplexer for demultiplexing the data from the modified legacy VSB receiver into the MPEG data and the supplemental data. The VSB reception system also includes a supplemental data processor for processing the supplemental data segment from the demultiplexer in a reverse order of the transmission system, to obtain the supplemental data, thereby carrying out the slicer prediction, decoding, and symbol decision more accurately by using the predefined sequence, to improve a performance. |
| US07787050B2 |
Method and system for downloading and storing interactive device content using the horizontal overscan portion of a video signal
A method and system for decoding and storing encoded control data delivered via the horizontal overscan area of a video signal. An interactive device performs behavior defined by control data encoded into a video signal that can be broadcast or played-back from video tape. The interactive device is equipped with a non-volatile memory that permits the control data to be stored for performance subsequent to, or during, the transmission session. The control data is delivered as a series of control data words that include genus codes identifying the interactive device to which the data word is directed. During a transmission session, control data words will be repeated, so that an interactive device receives several control data words with the same sequence number. Based on the relative gradings, the interactive device will replace previously received control data words of lower quality than subsequently received data words having the same sequence number. |
| US07787048B1 |
Motion-adaptive video de-interlacer
One embodiment of a motion-adaptive video de-interlacing system includes a motion estimator and a pixel interpolator. The motion estimator determines the magnitude of motion associated with each pixel within a de-interlaced video frame. In some instances, as determined by the motion values, the pixel interpolator produces final pixel values by blending between pixel values produced through different de-interlacing methods optimized for different levels of pixel motion. The present invention advantageously produces de-interlaced video frames having relatively better picture quality than those produced using prior art techniques, especially for small pixel motions. |
| US07787044B2 |
Lens module with ramped lens and camera module with same
A lens module includes a lens barrel, a first lens, an adjusting disk and at least one first elastic member. The first lens has at least three first sloping portions thereon each having a lower end and a higher end gradually sloping from the lower end. The first sloping portions arranged end to end with the higher end of each first sloping portion being adjacent to the lower end of the corresponding adjacent first sloping portion, with the first sloping portions arranged on a common circular path. The adjusting disk has a first surface and an opposite second surface. The adjusting disk is rotatably mounted on the lens barrel. The adjusting disk has at least three first protrusions on the first surface thereof. The first protrusions respectively abut the first sloping portions of the first lens. The first elastic member biases the first lens toward the adjusting disk. |
| US07787043B2 |
Lens apparatus for controlling an initial value
Provided is a lens apparatus in which serial communication and parallel communication between a camera body and the lens apparatus are performed and resumption of the serial communication is accomplished after occurrence of a communication error, and controlling of a controlled object being controlled through the parallel communication is transferred to temporally controlling through the serial communication, in which, by setting a state of the controlled object when the controlling is transferred to controlling through the serial communication, to be coincident with a state during controlling through the parallel communication, the controlled object to be controlled through the parallel communication is not affected by an effect caused due to a communication error in the serial communication. |
| US07787040B2 |
Solid-state image-taking element and image-taking apparatus including the solid-state image-taking element
An image-taking apparatus according to the present invention is constituted to have a wiring structure of transfer electrodes matching with a color filter arrangement and exert vertical transfer control over signal charges so as to transfer the signal charges read from pixels in the same color to the same horizontal transfer route. According to another embodiment of the present invention, the pixel of an image-taking device includes an odd-numbered electrode readout gate and an even-numbered electrode readout gate so that it allows control to read the charges to either of vertical transfer routes adjacent to the right and left of the pixel. It can be constituted so that one of the right and left vertical transfer routes transfers the charges to the first horizontal transfer route and the other transfers them to the second horizontal transfer route. |
| US07787038B2 |
Solid-state image pickup device and driving method therefor
A CMOS image sensor is disclosed which can achieve reduction of the voltage used to read out signal charge and can achieve expansion of the dynamic range. A P-well region is formed on a semiconductor substrate, and an embedded photodiode, a transfer transistor, an amplification transistor, a selection transistor, a reset transistor, a floating diffusion and so forth are provided in the P-well region. Signal charge of the photodiode is transferred to the floating diffusion by operation of the transfer transistor. A substrate bias voltage in the form of a negative voltage is applied to the P-well region in synchronism with the charge transfer operation of the transfer transistor to control the potential balance between the photodiode and the transfer gate portion to reduce the voltage for charge transfer. Further, during charge storage of the photodiode, the substrate bias voltage is varied to modify the angle of the sensitivity curve to achieve expansion of the dynamic range. |
| US07787036B2 |
Imaging apparatus configured to correct noise
An imaging apparatus includes an imaging area having, in a vertical direction, a plurality of lines having a plurality of pixels in a horizontal direction, wherein each of the plurality of lines includes an light-shielded area and an effective pixel area that is not light-shielded, a first correction unit configured to correct a shading component in the vertical direction that is included in an image signal from the effective pixel area of the plurality of lines, according to a first correction signal from the light-shielded area of the plurality of lines, and a second correction unit configured to correct the image signal output from the first correction unit according to a second correction signal obtained by multiplying the first correction signal, which is in the same line as the image signal, by a coefficient for decreasing a signal level of the first correction signal. |
| US07787031B2 |
Image-pickup apparatus for dust prevention
An optical filter which can remove dust stuck to the incidence surface of incidence of light and reduce the mounting space. A filter body is adapted to have predetermined transmittivity as well as a piezoelectric characteristic. At least two electrodes are formed on the filter body. A drive voltage is applied between the at least two electrodes to vibrate the filter body. |
| US07787030B2 |
Method and apparatus for identifying an imaging device
A new technique for identifying from images a camera, or other imaging device such as a scanner, is based on the device's reference noise pattern, a unique stochastic characteristic of all common digital imaging sensors, including CCD, CMOS (Foveon™ X3), and JFET. First, one determines from images the sensor's reference pattern noise, which uniquely identifies each sensor. To identify the sensor from a given image, the presence or absence of the reference pattern noise in the image under examination is established using a correlation detector or other means. |
| US07787029B2 |
Imaging apparatus
An imaging apparatus comprises an optical magnification changing mechanism which optically changes a magnification of an image, and an electronic magnification changing mechanism which reduces or expands a magnification with respect to image data by signal processing, the imaging apparatus providing a magnification-changed image according to a predetermined magnification based on the optical magnification changing mechanism and the electronic magnification changing mechanism. The optical magnification changing mechanism has at least two magnifications W and T (W |
| US07787028B2 |
Composite image output apparatus and composite image delivery apparatus
A composite image output/delivery apparatus for (10) adding to a picked-up scene image a corresponding animation image and outputting/delivering a resulting composite image without adding a fixed animation image simply to the picked-up scene image. When an object image is extracted from the picked-up scene image received via an image input unit (17), any specified type of character image corresponding to the scene image is selected from an appropriate one of a character 1 “memory (12)e, a character 3 “cat” pose image memory (12f). The selected type of character image replaces the object image in the picked-up scene image or adds to the scene image to thereby provide and display a resulting composite image. That is, by replacing the object image with an animation image similar in pose to the object image or by adding the animation image to the scene image, a very delightful picked-up image with an animation is easily created without adding a fixed animation image simply to an image pickup framerabbit” pose image memory (12d), a character 2 “bear” pose image. |
| US07787024B2 |
Portable electronic apparatus, image processing method, photographing apparatus, and computer readable recording medium
Even when a remaining amount of an image memory built in a digital camera is decreased, the photographing can be further continued while reserving a photographed image. An image which is obtained from an image input unit including image pickup means is accumulated into an image memory. When a remaining amount calculating unit detects that the remaining amount of the image memory is small, an image record discriminating unit compares it with an image size in a photograph mode at that time which is obtained from an image size table, thereby discriminating whether the continuation of the photographing can be performed or not. When the photographing is impossible, an image selecting unit selects an old image, an image in which the number of colors is small, or the like on the basis of management data regarding the photographed images in a memory managing table. The selected image is transmitted by a PHS communication by a data transmitting apparatus. After it was transmitted, the image is erased from the image memory. |
| US07787016B2 |
Imaging device for the stabilized imaging of an object onto a detector
An imaging device (2) for the stabilized imaging of an object onto a detector (14) with a first optical unit (4) and a second optical unit (6) and an optical element that is arranged between the optical units (4, 6) and can be moved for the purpose of stabilizing the imaging on the detector (14). For image stabilization in order to compensate for an undesirable wobbling movement of the imaging over the detector (14), the optical element is constituted of a micro-optical lens array (10). |
| US07787012B2 |
System and method for video image registration in a heads up display
A system and method for aligning video images with an underlying visual field are provided. A video camera is coupled with a heads up display, and a computer positions images from the video camera on the heads up display based on the relative orientations of the camera and the display. As the video camera moves with respect to the display, the images are repositioned within the heads up display. The video image, which may, for example, come from a weapon sight, is aligned within the heads up display so that an observer can easily view the camera image without having to shift focus from the larger scene. |
| US07787011B2 |
System and method for analyzing and monitoring 3-D video streams from multiple cameras
Embodiments of the present invention introduce a novel technique to analyze and monitor video streams captured from multiple cameras. It highlights the foreground region of the video streams via local alpha blending and displays the videos in an immersive 3-D environment. The spatial arrangement of the displays can be generated by multi-dimensional scaling of the amount of simultaneous motion across different video streams. This description is not intended to be a complete description of, or limit the scope of, the invention. Other features, aspects, and objects of the invention can be obtained from a review of the specification, the figures, and the claims. |
| US07787010B2 |
Video to film flat panel digital recorder and method
A method for recording video images onto film media includes orienting a flat panel display relative to a film recording device, receiving a first frame of video data and a second frame of video data, displaying a first display image on the flat panel data, wherein the first display image is determined in response to the first frame of video data, and while displaying the fist display image on the flat panel display, exposing a portion of the film media with the film recording device. |
| US07787008B2 |
Three-dimensional image display device
It is possible to provide a three-dimensional image display device which can improved a final resolution balance and can prevent display blocking. A three-dimensional image display device includes: a two-dimensional image display device where pixels constituting a pixel group displaying an elemental image are arranged in a matrix shape; and an optical plate which has exit pupils corresponding to the pixel group and controls light rays from the pixels of the pixel group, wherein the exit pupils in the optical plate are constituted so as to be continued in an approximately vertical direction, and an angle formed between a direction in which the exist pupils are continued and a column direction of a pixel arrangement in the two-dimensional image display device is given by arctan (1/n) when n is a natural number which is different from multiples of 3. |
| US07787007B2 |
Method and system for preparing video communication image for wide screen display
A system and method is disclosed for composing a video layout having an aspect ratio of 16:9 from a plurality of video segments having an aspect ratio other than 16:9. For example, the plurality of video segments might have an aspect ratio of 4:3. To create a composite frame having an aspect ratio of about 16:9, the disclosed system scales each one of the segments and places each scaled segment in the layout in such a way that the composite layout has an aspect ratio of about 16:9. |
| US07787006B2 |
Image forming apparatus capable of forming excellent image
Differing ratios of the amount of light from light source LD2 to the amount of light from light source LD1 are provided. An image pattern for adjustment that includes, for each color, an area made up of isolated dots by light source LD1 and an area made up of isolated dots by light source LD2, is printed for each ratio. In a copier, a density of each area is detected, a ratio at which a difference between the density of an area of isolated dots by light source LD1 and the density of an area of isolated dots by light source LD2 is smallest is decided as an adjustment ratio, and control is performed such that light sources LD1 and LD2 emit light at the adjusted ratio. |
| US07786998B2 |
Methods and apparatus for controlling video playback
The present disclosure discusses methods and apparatus for controlling the video playback in a video playback system. In particular, a method for controlling video playback includes receiving a flip call to display video data from a flip queue buffer. Processing of the video data is then initiated. Flip acknowledgement information is issued in response to receiving the flip call information and prior to completion of the processing of video data to be displayed from the flip queue buffer. By issuing flip acknowledgement information regardless of whether the processing of the video data has been completed, video flip calls can continue to be issued at a constant rate and other processing can continue without waiting, thus resulting in better and smoother video playback and economizing processing resources. Additionally, a decision whether or not to drop a particular video frame is made based on whether a flip queue buffer from a predetermined number of flip queue buffers is available. The disclosed apparatus includes a flip manager, such as under the control of a driver, that controls the timing of video frame flips, rather than an application controlling the timing. |
| US07786995B2 |
Information processing apparatus and information processing method for determining character layout
Information that is required for laying out character string data is entered, as are character string data. The printing attributes for the data are then edited, and are employed to extract contour information. Thereafter, the extracted contour information is employed to determine the information that is to be used as a reference when laying out the character string data, and a layout position is specified. Then, the various data that are obtained are stored as printing data, and the character string data are laid out in a drawing area. Therefore, the printing data can be precisely and easily prepared, without the work efficiency of a user being deteriorated. |
| US07786989B2 |
Electronic circuit, method of driving electronic circuit, electro-optical device, method of driving electro-optical device, and electronic apparatus
The present invention provides an electronic circuit, a method of driving the electronic circuit, an electro-optical device, a method of driving the electro-optical device, and an electronic apparatus capable of improving yield or aperture ratio by reducing the number of transistors to be used. A pixel circuit can include a driving transistor, a transistor, a switching transistor, and a holding capacitor. Furthermore, a driving-voltage supplying transistor is connected between a first power source line, which supplies a driving voltage to drive the driving transistor, and a voltage supply line extending in a row in the direction of the pixel circuits provided at the right end side of an active matrix part. |
| US07786988B2 |
Window information preservation for spatially varying power conservation
Described herein are systems and methods that reduce power consumption for an electronics device that includes a display device. The systems and methods identify characteristic window video information for a window that allows a person to visually locate the window in a display area for the display device. Video information in the display area other than the characteristic window video information is altered to conserve power. Preserving the characteristic window video information for the window maintains a person's ability to see and locate the window at a later time, even though other portions of the display area have been altered and potentially visually degraded to conserver power. |
| US07786987B2 |
Methods and apparatus to detect an operating state of a display based on visible light
Methods and apparatus to detect operating states of a display based on visible light are disclosed. An example device to detect an operating state of a display includes at least one optical sensor and a logic circuit. The at least one optical sensor is disposed to detect visible light emanating from a screen of the display and to convert the visible light into an electrical signal. The logic circuit is coupled to the at least one optical sensor to generate an output signal indicative of the operating state of the display based on the electrical signal. |
| US07786984B2 |
Method and system for processing observation charts
The invention concerns a method and system for digitally processing information to be written on an observation form, said form being preprinted with at least one blank chart having at least one line and several columns, each column corresponding to a determined printed time, said form being also preprinted with a pattern adapted to cooperate with a digital pen and a computerized localization system for determining the position of the pen; using a pen having a writing tip and a digital tip; filling in data in one column at a time; reproducing said data in the computerized localization system and associating to said data its recording time; and comparing said recording time with the localized printed time of said data, so as to detect any inconsistency between the recording time and the printed time. |
| US07786980B2 |
Method and device for preventing staining of a display device
A method and apparatus for preventing staining of a display screen by a user's fingers, by encouraging a user not to touch the surface of a display screen while using a graphic user interface associated with the display screen includes determining a first threshold distance from the display screen within which a user's finger may be detected, determining a second threshold distance from the display screen within which a user's fingers may be detected, the second threshold distance being shorter than the first threshold distance, first detecting when a user's finger is within the first threshold distance, indicating to the user, upon a detection in the first detecting step, that the user's finger has entered a zone proximate to the screen where interaction with a graphical user interface (GUI) is enabled, the GUI enabling manipulating various display functions by movements of the user's finger, second detecting when a user's finger is within the second threshold distance, and indicating to the user, upon a detection in the second detecting step, that the user's finger has entered a forbidden zone. |
| US07786977B2 |
Position input device, remote control device, computer system and electronic equipment
A position input device is provided which includes a sensor portion having a detection face, an operation element movable along the detection face of the sensor portion, and a position detection unit which detects the position of the operation element on the detection face. According to additional embodiments, the position input device includes a lid covering the detection face. The lid is movable between opened and closed states, and integrally supports the operation element so as to move integrally with the lid when the lid is opened and closed. A remote control device including the position input device and a wireless transmission unit are also provided. Also provided are computer systems and electronic devices. |
| US07786975B2 |
Continuous scrolling list with acceleration
Movement of a point of contact by a user of a touch-sensitive display is determined. In response to the movement, a list of items on the touch-sensitive display is scrolled through. The scroll through is accelerated in response to an accelerated movement of the point of contact. The scroll through and acceleration of the scroll through may be in accordance with a simulation of a physical device having friction. |
| US07786966B2 |
Method for driving liquid crystal panel, and liquid crystal display device
A method for driving a liquid crystal panel that includes horizontal scan wires, data wires, pixel electrodes surrounded by the horizontal scan wires and the data wires; and switching elements connected to the pixel electrodes, wherein the switching elements are controlled by a gate selection signal and during a on-time period, the switching elements is turned on, and an image data signal output from the data wires is supplied to the pixel electrodes by the switching elements. The method includes: detecting a peripheral temperature of the liquid crystal panel; and controlling the gate selection signal so that when the detected temperature is within a normal temperature range, the on-time period is set to a first gate selection period, and that when the detected temperature is within a low temperature range, the on-time period is set to a second gate selection period longer than the first gate selection period. |
| US07786965B2 |
Liquid crystal display device
One picture element of a liquid crystal panel is divided into a region I where a cell gap is set to 4 μm and a region II where a transparent insulating film is formed and a cell gap is set to 2 μm. In the region I, there occurs a phenomenon (overshoot) that, when a voltage is applied, luminance becomes high immediately before an alignment of liquid crystal molecules becomes stable, and in the region II, no overshoot occurs. Response characteristics of an entire picture element are those obtained by synthesizing the response characteristics in these regions. Parameters such as an area ratio of the regions I and II, and cell gaps are set so that a maximum luminance value is not greater than 110% of the luminance at a stable time. |
| US07786962B2 |
Image display device, portable terminal device, display panel and image display method using the same
A three-dimensional image/two-dimensional image display device includes a plurality of display pixels, and a lenticular lens for three-dimensional display. Each display pixel is consisted of M×N number of sub-pixels to be viewed from N view points. A pitch a of sub-pixels arranged in the longitudinal direction of ridge projection of the lenticular lens and a pitch b of the sub-pixels arranged in a direction orthogonal to the longitudinal direction of the lenticular lens satisfy the following expression. The M×N number of sub-pixels included in each of said display pixels are formed within a square area. a:b=N:1 |
| US07786961B2 |
Liquid crystal display device and method for driving the same
A liquid crystal display device and method for driving the same are provided. A liquid crystal display device includes a driving circuit that includes a data driver that is inputted with a m-bit data signal. The data driver is operative to extract a n-bit data signal from the m-bit data signal and a (m-n)-bit data signal, and adjust a gray level of the (m-n)-bit data signal using the n-bit data signal. A liquid crystal panel includes a pixel that is supplied with the (m-n)-bit data signal during a plurality of frames. |
| US07786959B2 |
Display apparatus
When the transistor Q3 is OFF, a predetermined potential is supplied to a potential wire Ui such that a switching transistor Q2 becomes ON. This changes a gate potential of a driving transistor Q1 from an ON potential to a threshold potential. Thereafter, the transistor Q2 is turned OFF, with the result that the potential of the potential wire Ui is changed (in cases where the transistor Q1 is a p-type transistor, the potential is decreased). With this, the transistor Q1 allows a current to constantly flows therethrough, irrespective of the threshold potential. This shortens time for setting an output current of the driving TFT for driving a current driving type display element. |
| US07786956B2 |
Plasma display device
A plasma display device includes an AD converter; a video signal processing circuit producing subfield data; a subfield processing circuit producing control signals of each of drive circuits; a plasma display panel having scan electrodes and sustain electrodes which are alternately arranged in n rows, and data electrodes in (k+m) columns arranged in a direction of intersecting with the scan and sustain electrodes; a scan-electrode drive circuit for driving scan electrodes; a sustain-electrode drive circuit for driving sustain electrodes; and a data-electrode drive circuit which has a first drive circuit for driving data electrodes and a second drive circuit for driving data electrodes, and applies writing pulse voltage in order from a data electrode group nearest to the scan-electrode drive circuit. |
| US07786955B2 |
Plasma display apparatus
A plasma display apparatus includes an image data transmitter to convert an externally input image signal into image data and to transmit the converted image data, an image data receiver to receive the image data and to restore an image signal from the image data, and a data driver to supply the restored image signal to an address electrode of the plasma display panel through a switching operation. The image data may be transmitted as a differential signal. |
| US07786953B2 |
Apparatus displaying three-dimensional image
In a three-dimensional image display apparatus in which a lenticular plate and shutter device are arranged in front of a display module, one frame image is displayed using n field images. To display each field image, a shutter device is driven to substantially simultaneously open a group of shutter elements for every n lenses along a horizontal direction. Thus, light beams are transmitted from lenses through the shutter elements to an observing zone. The group of the opened shutter elements is sequentially changed in response to n switchings of the field. The switching of shutter elements is synchronized with the pixels on the display surface sequentially rewritten from top to bottom by linear sequential driving during the switching of the field. The elemental image is projected on the viewing zone via the lenses and the shutter elements. |
| US07786951B2 |
Apparatus with display
A (display) device (31,4,5) contains multiple panels (3,7) like e.g. displays. Every display can be used to display its own content and can be rolled out of a sub-housing (5) like e.g. a cartridge separately. In different configurations the same cartridge can be arranged in such a way that the panels are used for a separate functionality or multiple display panels form one big screen. |
| US07786948B2 |
Array antenna with embedded subapertures
An array antenna with an embedded subaperture includes an array of radiator elements. The array includes a subaperture of one or a group of the radiator elements. A main receive channel is coupled to at least some of the radiator elements by a feed network. An RF power dividing network is connected in a signal path between the subaperture and the special use receive channel, and is adapted to allow at least most of the RF energy from the subaperture to pass to the special use receiver channel while diverting a small amount of energy to the main receive channel. The array includes circuitry for introducing an amplitude taper to signals received from the array of radiator elements, so that some of the signals from the radiator elements are attenuated to achieve the amplitude taper. The circuitry in an exemplary embodiment includes the RF power dividing network, wherein the small amount of energy diverted to the main receive channel from the subaperture is substantially equal to an attenuated signal level for the subaperture to achieve an amplitude taper attenuation. |
| US07786945B2 |
Beam waveguide including Mizuguchi condition reflector sets
A beam waveguide may include a first set of dual offset reflectors and a second set of dual offset reflectors. The first set of dual offset reflectors and the second set of dual offset reflectors may each include reflector geometries to produce a radiation pattern that is symmetric about a first axis between the first and second set of dual offset reflectors and to produce an axi-symmetric beam from the second set of dual offset reflectors that is unaffected by any rotation of the first and second set of dual offset reflectors relative to one another about the first axis. |
| US07786942B2 |
Hybrid dual dipole single slot antenna for MIMO communication systems
An antenna arrangement implemented within a printed circuit board (PCB) having three metal co planar layers, for use in multiple input multiple output (MIMO) communication systems. The antenna arrangement comprises a first dipole antenna and second dipole antenna, substantially symmetrical to the first dipole antenna a slot antenna positioned substantially between the first and the second dipole antennas. The antenna arrangement is implemented in three coplanar metal layers. The antennas are used for MIMO communication systems, specifically complying with IEEE 802.11n and are shaped such that their combined radiation pattern exhibits a substantially omni directional radiation pattern. |
| US07786939B2 |
Mobile terminal equipment and antenna thereof
The present invention relates to a mobile terminal and an antenna thereof of which the radiation pattern is not distorted regardless of the length of the mobile terminal. The mobile terminal includes a terminal body; an antenna connected to a high frequency signal source within the terminal body; and a grounding means connected to a ground voltage source within the terminal body. |
| US07786935B2 |
Method and system for inferring a location of a mobile computing device
A computer-based method for inferring a location of a mobile computing device comprises the steps of using the mobile computing device to receive data about one or more devices present in a first location at a first time, including those devices available for connection; assigning an identification code to each device present in the first location; storing said data and identification code for each device present in the first location in a database; receiving new data about each device present in a location at a subsequent time, including those devices available for connection to the mobile computing device; and inferring that the mobile computing device is at the first location by comparing the new data to the stored data and identification codes. |
| US07786931B2 |
Determining mobile terminal positions using assistance data transmitted on request
A mobile terminal (UE) comprises means (CR) for acquiring pseudo-random codes modulating signals received from positioning satellites (SN) in view belonging to a constellation (CS) and related to a reference time, and computation means (MC1-MC3) for determining its position received from the acquired codes and from navigation data contained in the signals. The acquisition means (CR), on receiving assistance data representing an approximate reference time and the approximate position of the terminal (UE), determine estimated positions of the satellites, estimated distances between the terminal and each of the satellites in view and associated Doppler effects as a function of pairs of hypotheses relating to the approximate reference time and the approximate position, and then determine a signal replica for each pair of hypotheses corresponding to the estimated positions and distances and to the associated Doppler effects over a selected time interval, and select the pair of hypotheses corresponding to the signal replica having the maximum correlation with the signal received during the time interval in order to determine the pseudo-random codes modulating the received signals. |
| US07786928B2 |
Monostatic planar multi-beam radar sensor
A monostatic multi-beam radar sensor for motor vehicles, having a group antenna, a planar lens having multiple inputs, and a homodyne mixer system, wherein the mixer system comprises multiple transfer mixers that are connected in parallel to the inputs of the lens. |
| US07786922B2 |
Systems and methods employing active TCAS to enhance situational awareness
A method according to the present invention includes transmitting a Mode S interrogation and receiving a response from an aircraft that has received the Mode S interrogation. A range to the aircraft is determined based on a time period between transmitting the Mode S interrogation and receiving the response. The method further includes receiving information from one or more data sources and determining at least one of a bearing to the aircraft and a position of the aircraft using the determined range and the information from the one or more data sources. Information can be received from any number (or type) of data sources, such as ADS-B-equipped aircraft. |
| US07786916B2 |
Digital to analog converter circuits and methods of operation thereof
A multi-bit digital to analog converter is implemented by a switched-capacitor arrangement in which a reservoir capacitor (Cf) accumulates charge representing the desired analog output signal (Vout+/Vout−). An array of further capacitors (C0-CN) correspond in number at least to the number of data bits (D0-DN) to be converted. The capacitors (Cf, C0-CN) are selectively interconnected with one another and with reference voltage sources (Vmid, Vdd, Vss) in a repetitive sequence of phases including (i) a sampling phase (P2) in which the further capacitors are connected (S3, S4) to reference voltages selected in accordance with the values of the data bits, (ii) an equalization phase (P6a) in which the further capacitors are connected (S2) in parallel with one another without connecting them in parallel with the first capacitor, followed by (iii) a transfer phase (P6b) in which the parallel connected further capacitors are connected (S1, S5) in parallel with the first capacitor. The equalization phase masks nonlinearities arising in switches (S2) and thereby improves harmonic distortion. |
| US07786915B1 |
Adaptive digital audio pre-distortion in an audio digital to analog converter
An adaptive digital pre-distortion block is used to cancel device nonlinearities to improve the overall linearity of a Delta-Sigma DAC system. In particular, the pre-distortion block may be implemented all in digital components and utilize programmable registers that change the pre-distortion transfer function either statically or dynamically, or both. Static changes can be for variation in process corners during production, whereas, dynamic changes can be used to correct nonlinear changes that can occur from environmental reasons such as voltage, temperature, aging and device stress. |
| US07786914B2 |
Time-interleaved delta-sigma modulator
Embodiments of the present disclosure provide methods, systems, and apparatuses related to a time-interleaved delta-sigma modulator are described. Other embodiments may be described and claimed. |
| US07786912B2 |
Sigma delta converter system and method
A sigma delta converter system and method includes a multi bit quantizer circuit coupled to an output of the converter. A single bit analog-to-digital converter circuit is contained in a feedback path of the converter. The converter includes a feed forward path operable to multiply an input voltage by a feed forward coefficient having a value that is a function of a gain control input signal. The gain control input signal can have a value that is a function of the output of the multi bit quantizer. |
| US07786910B2 |
Correlation-based background calibration of pipelined converters with reduced power penalty
A device and method for correlation-based background calibration of pipelined converters with a reduced power penalty. A pipelined analog-to-digital converter (ADC) utilizes a random or pseudorandom signal to reduce the quantization error of subconverting stages. Stages within the ADC comprise an injection circuit having a plurality of capacitive branches in parallel. Less than all of the branches can function during a given clock cycle of the ADC. This allows a subconverting stage within the ADC to be accurately trimmed before operation using a large amplitude signal. At the same time, the capability to inject smaller amplitude random or pseudorandom signals into the subconverting stage during operation is maintained, saving valuable dynamic range and power. The various capacitive branches are cycled through either randomly or in sequence such that the quantizer manifests the same average gain error over time for which the quantizer was initially trimmed. |
| US07786909B2 |
Analog to digital converter with improved input overload recovery
With high speed analog to digital converters (ADCs), components within the ADC can enter a saturation region when an input exceeded the input range of the ADC, which can cause errors. Here, a sample of an input signal to an ADC is compared with the upper and lower full-scale levels of the ADC. If input overload is detected, inputs to amplifiers in an input stage of the ADC are forced to zero for the duration of the input overload, and are thus prevented from going into saturation. Input overload conditions are signaled directly to an output digital block of the ADC, which provides output digital codes equivalent to either the upper or the lower full scale level depending on whether the input overload is signaled as exceeding the upper level or the lower level. Input overload recovery time of the ADC may thus be minimized. |
| US07786907B2 |
Combinatorial coding/decoding with specified occurrences for electrical computers and digital data processing systems
Embodiments described herein may include example embodiments of a method, article and apparatus for compressing data utilizing combinatorial coding with specified occurrences which may be used for communicating between two or more components connected to an interconnection medium (e.g., a bus) within a single computer or digital data processing system, and/or for communication between computing platforms via a network or other interconnection medium. |
| US07786906B2 |
Modulation coding and decoding
Methods and apparatus are provided for modulation coding a stream of binary input data. A 4-ary enumerative encoding algorithm is applied to the input bit-stream to produce a succession of 4-ary output symbols. The 4-ary algorithm is operative to simultaneously encode respective generalized Fibonacci codes in the odd and even interleaves of the input bit-stream. The bits of each successive 4-ary output symbol are then interleaved, producing an output bit-stream which has global and interleaved run-length constraints. Inverting the bits of the 4-ary output symbols produces an output bit-stream with (G, I)-constraints as in the PRML (G, I) codes used in reverse-concatenation modulation systems. Corresponding decoding systems are also provided. |
| US07786898B2 |
Fusion of far infrared and visible images in enhanced obstacle detection in automotive applications
A method in computerized system mounted on a vehicle including a cabin and an engine. The system including a visible (VIS) camera sensitive to visible light, the VIS camera mounted inside the cabin, wherein the VIS camera acquires consecutively in real time multiple image frames including VIS images of an object within a field of view of the VIS camera and in the environment of the vehicle. The system also including a FIR camera mounted on the vehicle in front of the engine, wherein the FIR camera acquires consecutively in real time multiple FIR image frames including FIR images of the object within a field of view of the FIR camera and in the environment of the vehicle. The FIR images and VIS images are processed simultaneously, thereby producing a detected object when the object is present in the environment. |
| US07786897B2 |
High occupancy vehicle (HOV) lane enforcement
An HOV enforcement system comprises roadside imaging units connected over a network to a central processing center. The roadside imaging units include Ethernet cameras with integrated vehicle detectors, night-time lighting, and image servers. The central processing center includes a central server with license plate reading and vehicle matching software, storage and databases, and review staff to issue bills and citations. |
| US07786893B2 |
Battery saving two-way communication circuit and system and method for automatic meter reading
A battery-powered two-way long range automatic meter reading system and method that increases battery longevity. The system includes a meter side unit (MSU) transceiver that acquires utility data, a centralized data collector (Collector) that gathers data from the MSU, and a repeater to facilitate long-range transmission by shuttling radio signals around physical or geographic transmission barriers. The MSU includes a circuit to monitor the passage of time and apply power to a transmitter in response to a predetermined elapsed period of time. The MSU transceiver monitors a predetermined radio channel for traffic. In response to the predetermined radio channel being essentially clear of signal traffic, the MSU sends utility data to the collector. The MSU scans for a reply from the collector. In response to the collector having control data to transmit to the MSU, the collector transmits this control data in response to receiving a transmission from the MSU. The MSU is configured to enter a sleep mode. In response to receiving commands from the collector, the MSU is configured to perform the commands. |
| US07786890B2 |
Network status indicating circuit
A network status indicating circuit includes a logic circuit, a switch circuit, and an indicating unit. The logic circuit includes nine input ends, a NOT gate, and two OR gates. The switch circuit includes two input ends and two output ends. The indicating unit includes two LEDs. The logic circuit is connected to the indicating unit to indicate the status of a network IC. |
| US07786887B2 |
Electromagnetic energy converter
An autonomous-power radio device including an electromagnetic energy transducer having a permanent magnet (1), a soft-magnetic element (9), an electrical coil (6), and stop points (8a-8d). The electrical coil surrounds a part of the magnetic circuit, wherein the permanent magnet (1) and said soft-magnetic element (9) are arranged to form a magnetic circuit with a first flux direction. At least one of the soft-magnetic element (9) and the permanent magnet (1) is mounted for rotary movement about an axis (4) with respect to the other. End points of the rotary movement are formed by the stop points (8a-8d). |
| US07786884B1 |
Alarm equipped door safety device
An alarm equipped door safety device for engagement at the hinge-side of a door's interface with a door jamb. The device is formed of an elastic body which prevents closure of the door to provide protection against crushing of a finger or object between the door and jamb. To provide warning and protect the door, the door jamb, and the hinges from stress damage, a body-compression activated switch generates a sonic alarm when closure of the door is attempted with the device engaged. |
| US07786880B2 |
Smoke detector
A smoke detector having a closed internal optical path can detect airborne particulate matter, such as smoke from a fire, via a light scattering sensor and/or a light absorption sensor. The path can be implemented with a plurality of reflectors, such as piezoelectric minors. Input light can be coupled to the path, on a pulsed basis, for example via one of the minors, in a resonant condition. |
| US07786879B2 |
Self-powered rechargeable smoke/carbon monoxide detector
A rechargeable smoke and carbon monoxide detector is provided. The base of the detector has a battery formed therein that is charged when connected to a power source, such as a 110-volt light bulb socket. The detector is further configured to receive a 110-volt light bulb so as to not eliminate the use of the light socket as a light source. Additionally, the detector may include one or more warning devices such as an ionization or photoelectric sensor, speaker, or light source. A power indicator LED, a smoke indicator LED, and a carbon monoxide indicator LED all provide visual notification that the detector is functioning properly. |
| US07786876B2 |
Large area position/proximity correction device with alarms using (D)GPS technology
A collar to be worn on an object or a large or small animal has been designed incorporating (D)GPS technology. The operation of the device includes programming the three dimensional boundary into the memory of the device and simply installing the collar on the animal. As the animal approaches the preprogrammed boundary, a first alarm sounds when the subject is within an arbitrary user defined distance, and a second more drastic alarm such as a shock correction is applied when the subject approaches a second position closer to the boundary. Means to easily program the device are also included in the system. The device has the capability to call or transmit important information such as location, speed, identity, and medical parameters, etc. to a station automatically or when polled. All necessary analog and digital circuitry, microprocessor, programming, communications hardware are integrated into the collar. The device also has applications in land, air and sea navigation, farming, construction, tracking stolen vehicles, and keeping track of children. This device could also be embedded in a specialized lawnmower that would know where your yard ended and your neighbor's began, and traverse around all obstacles in the yard. Important Military applications would include warning and directing soldiers of front line boundaries, minefield mapping and 3-D direction around MOA's for aircraft. |
| US07786869B2 |
Radio communication system
There is provided a radio communication system including a first transceiver equipped with an antenna circuit and a transmitting-receiving unit and for transmitting a data signal by an electromagnetic wave, and a second transceiver equipped with an antenna circuit, a transmitting-receiving unit, a memory unit for storing the data signal, a display unit having display memory property, and a power source unit for obtaining an operation voltage for each unit from the electromagnetic wave. The first transceiver relatively varies the transmission output of the data signal to a high level or a low level, and the second transceiver receives the data signal and stores the data signal in the memory unit when the level of the transmission output of the data signal is low, and sends the data signal from the memory unit to the display unit when the level of the transmission output of the data signal is high. |
| US07786868B2 |
RFID device with multiple passive operation modes
A radio frequency identification (RFID) device is capable of operating in multiple passive modes, in either a fully passive mode or a boosted passive mode. The device includes an RFID chip that is suitable for operation of passive RFID devices. An antenna is coupled to the chip for receiving radio frequency signals, such as those sent by a reader/detector device. In addition, the RFID device has an energy booster which may be used to boost the energy of signals received by the device, in order to enable operation at a reduced level of RF signal. The energy boost may be selectively applied in order to transform the passive RFID device into operating in a boosted passive mode. The energy booster may include a one-port transistor and an energy source that is used to power the transistor. The energy source may be a rechargeable energy source. |
| US07786866B2 |
Radio frequency identification (RFID) system that meets data protection requirements through owner-controlled RFID tag functionality
An RFID tag can include a transmitting device and a receiving device for transmitting data to and receiving data from a tag reader, and the tag can include a memory for storing identification data unambiguously labeling the RFID tag and circuitry which automatically executes functions depending on the fact that: the reader demonstrates knowledge of an internal password in a memory of the tag; and information stored in the memory of the tag for an internal state permits the execution of the function. The tag also includes circuitry for changing the stored password and/or the internal state, in particular depending on a previous comparison of the internal password to one received from the reader. |
| US07786855B2 |
Mobile system and method for traffic detector simulations
Traffic induction loop simulator (LOOPSIM) software, and a system and method designed for traffic research and education. The system is able to generate output signals in response to previously recorded real traffic events or simulated traffic. If directly connected to a controller cabinet or a traffic event data collection system, LOOPSIM can be used to simulate output signals from loop detectors and to test algorithms executable in the controller, or to test the performance of a traffic data collection/monitoring system. LOOPSIM can simulate different predefined patterns of traffic distributions and replay loop event data recorded by a detector event data collection (DEDAC) system or an advanced loop event data analyzer (ALEDA) at a pace responsive to controller feedback. Using LOOPSIM, many traffic system tests can be conducted for multi-purpose traffic control applications, and traffic arrival patterns can be generated for researchers and educators to test theoretical models. |
| US07786844B2 |
Mobile portal for RFID applications
A mobile portal for RFID applications includes an RFID reader for reading identifications of proximately located RFID tagged items in the environment. A communicator is coupled to the RFID reader to receive the read identifications and then communicate the received read identifications over the wireless interface, through one of the gateways, to the central data processing system. Each mobile portal may be actuated for RFID read operations in response to information sensed concerning operation of the mobile asset/vehicle. Additionally, the central data processing system may issue instructions concerning mobile asset/vehicle operation, with those instructions communicated over the wireless interface to the mobile portal. Responsive to implementation of those instructions, the mobile portal actuates the RFID reader and compares the read identifications to identifications of certain RFID tagged items to be manipulated which were identified in the received instruction. |
| US07786843B2 |
System and method for training a trainable transmitter and a remote control system receiver
A method for training a receiver of a remote control system to a trainable transmitter includes receiving a control signal from an original transmitter associated with the remote control system. A first period of time is started in response to receipt of the control signal. During the first period of time, a learn message is received from a trainable transmitter. In response to the learn message, the receiver begins a receiver training mode. During the training mode, a rolling code control signal is received from the trainable transmitter and the trainable transmitter is enrolled by storing an identifier of the trainable transmitter. |
| US07786835B2 |
Magnetic element and method of manufacturing magnetic element
There are provided a magnetic element capable of enhancing magnetic permeability of a magnetic member, improving a direct current superposition characteristic, and improving production efficiency and a method of manufacturing the magnetic element. The magnetic element includes a coil (30) formed of a conductor having an insulating film, a first core member (20) constituted of insulative soft magnetic ferrite and covering the coil (30), and a second core member (50) having soft magnetic metal powder as material and surrounded by the first core member (20). Furthermore, the magnetic element includes a third core member (40) which has soft magnetic metal powder as material and a higher filling ratio of the soft magnetic metal powder than the second core member 50 and is surrounded by the first core member (20). |
| US07786834B2 |
Inductor and its manufacturing method
An inductor 10 has a magnetic body 11 of a rectangular solid shape and a coil 12 embedded in the magnetic body 11. The coil 12 integrally has a part constituted by a helically wound coil wire, two leader parts 12a provided at the two ends of the wound part, and terminal parts 13 connected to the ends of the leader parts and wider than the leader parts 12a, where the boundary between each leader part 12a and each terminal part 13 is positioned in the magnetic body 11, and the end of each terminal part 13 is exposed from the corresponding side face of the magnetic body 11 and folded in an L shape along the side face and bottom face. |
| US07786833B2 |
Edgewise coil
An edgewise coil which includes a non-circular cross-sectional shaped conductor having a cross-sectional shape defined by a pair of first and second long sides and a pair of first and second short sides, the shaped conductor wire being laminated while being bended with using the first short side as a bending fulcrum so as to form a plurality of laminated wire layers having a rectangular shape in a plan view, wherein the pair of long sides include, in a longitudinal cross section in a pre-bending-process state before the shaped conductor wire is bended, a pair of straight-line regions extending from both ends of the second sides so as to be parallel to each other and a pair of tapered regions extending between the straight-line regions and the first short side, and the pair of tapered regions, in a longitudinal cross section in the pre-bending-process state, come closer to each other as they approach the first short side. |
| US07786829B2 |
High frequency MEMS switch having a bent switching element and method for its production
A high-frequency MEMS switch comprises a signal conductor which is arranged on a substrate and an oblong switching element which has a bent elastic bending area and is fastened on the substrate in a cantilevered manner. An electrode arrangement generates an electrostatic force which bends the switching element toward the signal conductor. The switching element is arranged longitudinally parallel to the signal conductor, and has a contact area which extends transversely to the switch element over the signal conductor. Under the effect of the electrostatic force, the elastic bending area of the switching element progressively approaches the electrode arrangement in a direction parallel to the signal line. The switching element has, for example, two mutually parallel extending switching arms, which are mutually connected by a bridge as the contact area and are arranged on both sides of the signal line and parallel thereto. |
| US07786827B2 |
Surface acoustic wave device, transmitter, and transceiver
A surface acoustic wave device comprises a surface acoustic wave element, including: a piezoelectric substrate, a first interdigital transducer unit having a first interdigital transducer and a second interdigital transducer formed on the piezoelectric substrate, and a second interdigital transducer unit having a third interdigital transducer and a fourth interdigital transducer formed on the piezoelectric substrate; a first terminal electrically coupled to the first interdigital transducer; a second terminal electrically coupled to the second interdigital transducer; a first variable resistor electrically coupling the first terminal to the third interdigital transducer; a second variable resistor electrically coupling the first terminal to the fourth interdigital transducer; a third variable resistor electrically coupling the second terminal to the third interdigital transducer; and a fourth variable resistor electrically coupling the second terminal to the fourth interdigital transducer. |
| US07786825B2 |
Bulk acoustic wave device with coupled resonators
A bulk acoustic wave device includes first and second resonators, which are acoustically coupled and electrically connected in parallel. |
| US07786817B2 |
Crystal oscillator emulator
An integrated circuit comprises a microelectromechanical (MEMS) resonator circuit that generates a reference frequency. A temperature sensor senses a temperature of the integrated circuit. Memory stores calibration parameters and selects at least one of the calibration parameters as a function of the sensed temperature. A phase locked loop module receives the reference signal, comprises a feedback loop having a feedback loop parameter and selectively adjusts the feedback loop parameter based on the at least one of the calibration parameters. |
| US07786808B2 |
Micro-structured optic apparatus
A micro-structured optics apparatus includes a concave microlens to expand a beam of light, a reflector to provide a first reflection of at least a portion of the beam of light and a micro-Fresnel lens to collimate the at least a portion of the beam of light after the expansion. |
| US07786807B1 |
Cascode CMOS RF power amplifier with programmable feedback cascode bias under multiple supply voltages
A Radio Frequency (RF) cascode power amplifier operates with differing battery supply voltages. A transconductance stage has a transistor with an RF signal input at its gate. A cascode stage has at least one cascode transistor, the cascode stage coupled in series with the transconductance stage between a battery voltage node and ground, the cascode stage having an RF signal output at the battery voltage node and at least one bias input to the at least one cascode transistor. Cascode bias feedback circuitry applies fixed bias voltage(s) to the at least one two bias inputs for a low battery voltage and applies feedback bias voltage(s) to the at least two bias inputs for a high battery voltage, the feedback bias voltage(s) based upon a voltage of the battery voltage node. More than two differing battery supply voltages are supported. |
| US07786804B2 |
Driving amplifier circuit with digital control and DC offset equalization
A driving amplifier circuit includes: a first driver for sourcing a load current to a load; a second driver for sinking the load current from the load; a first operational amplifier (op-amp) for driving the first driver; a second operational amplifier for driving the second driver; a first bias circuit for biasing the first driver; a second bias circuit for biasing the second driver; an enabling circuit for enabling either the first bias circuit or the second bias circuit according to a control signal; a digital control circuit for monitoring currents of the first driver and the second driver to generate the control signal; and an offset equalization circuit, coupled between an internal node of the first operational amplifier and an internal node of the second operational amplifier, for adjusting DC offset of at least one of the first operational amplifier and the second operational amplifier. |
| US07786802B2 |
Output stage circuit and operational amplifier thereof
The present invention relates to an output stage circuit and an operational amplifier thereof. In the output stage circuit, one of a gate of a transistor is coupled to a gate of a bias transistor and a level shifter in response to a small signal outputted from an amplifying circuit in the operational amplifier. In addition, a gate voltage of the bias transistor is controlled by a voltage generating circuit to control a DC bias of the transistor of the output stage circuit. Therefore, there is no need extra frequency compensating component for compensating the transistor of the output stage circuit, and to save circuit layout area and cost can be achieved by the present invention. |
| US07786801B2 |
Operational amplifier having high slew rate and stability, and operating method thereof
An operational amplifier includes a differential amplifier, an output stage, and a control unit. The differential amplifier generates a first current through a first output node and a second current through a second output node in response to a voltage difference between a first input signal input through a first input terminal and a second input signal input through a second input terminal. The output stage generates an output signal through an output node. The control unit receives a voltage of the first output node and a voltage of the second output node, as bias voltages, and controls an output current of the output stage to determine the output signal of the output stage in response to the received voltages of the first and second output nodes. |
| US07786800B2 |
Class AB amplifier
A class AB amplifier includes: a voltage amplifier stage operating off a first source voltage, and amplifying a differential input voltage to produce a first amplified voltage; a level shift stage coupled to the voltage amplifier stage and adjusting a direct current level of the first amplified voltage to produce a first shift voltage; and a power amplifier stage coupled to the level shift stage, operating off a second source voltage, and converting the first shift voltage to produce a first output current. The second source voltage is larger than the first source voltage. |
| US07786795B2 |
Class-D amplifier circuit
A class-D amplifier circuit of one aspect includes a gain controller, a pulse-width modulator, an output driver, and a drive controller. The gain controller selectively amplifies an analog input signal according to a level control signal, and outputs a corresponding gain-adjusted analog input signal. The pulse-width modulator converts the gain-adjusted analog input signal into a pulse signal. The output driver includes a plurality of output driver circuits which generate an amplified pulse signal corresponding to the pulse signal output by the pulse-width modulator. The drive controller selectively disables a subset of the plurality of output driver circuits according to the level control signal. |
| US07786787B2 |
Series/shunt switch and method of control
A switch includes at least two signal ports in series with a series FET connected therebetween, and a shunt path having an FET, whereby an input bias is applied to a gate on the series FET and to a drain on the shunt FET. In one embodiment, the switch includes a control signal input, an FET connected in series across the first port and the second port, the series FET having a gate coupled to the control signal input, and a shunt path provided by an FET, the shunt FET having a drain coupled to the control signal input and to the gate of the series FET, whereby a single control signal is applied to both the series FET and the shunt FET, via the control signal input, in order to turn the series FET on and simultaneously turn the shunt FET off and, conversely, in order to turn the series FET off and simultaneously turn the shunt FET on. |
| US07786786B2 |
Multiphase clock for superconducting electronics
A multiphase clock circuit in which bit errors are propagated only for the duration of the clock cycle in which a bit error occurs. The circuit recovers automatically from bit errors and is capable of operating at high frequency with high clock precision. The multiphase clock circuit can generate a plurality of clock pulse streams, each pulse stream at the same clock frequency, with fixed phase relationships among the streams. The multiphase clock circuit includes a master clock signal of frequency fc which is applied to a divide by N frequency divider circuit for producing a base clock signal of fc/N. The base clock signal is sequentially applied to the data input of a series chain of N clocked data flip-flops (DFFs) each of which is simultaneously clocked by a clock signal of frequency fc to produce N clock signals of base frequency fc/N separated from each other by a constant time delay T=1/fc. |
| US07786781B1 |
Pseudo-random pulse width modulation for high resolution fan control
A pulse width modulation (PWM) device, system and method for high resolution fan control are disclosed. In one embodiment, the method comprises determining a target duty cycle of a PWM signal, determining the number of PWM cycles in the period of the PWM signal, pseudo-randomly selecting a duty cycle for each PWM cycle using one or more look-up tables and generating the PWM signal based on the duty cycle. |
| US07786776B2 |
Semiconductor integrated circuit
The semiconductor integrated circuit includes a clock generating section having a digital control signal generating part operable to generate a clock signal and a digital control part. The clock generating section further includes a phase-frequency comparator and a control register. The comparator is supplied with a reference signal CLKin and a feedback signal. The control register is supplied with an output signal of the comparator, and stores two or larger bits of digital control information. The clock generating section further includes a control data storing circuit for previously storing sets of initial set data for lock operations. In response to operation select information, initial set data are stored at upper bit of the control register from the control data storing circuit. Thus, it becomes possible to reduce the number of steps to store control information in a register for digitally controlling the clock signal generating part. |
| US07786775B2 |
Delay circuit
The object is to provide a delay circuit capable of improving the accuracy of delay time with a simple circuit configuration. A delay circuit includes a first delay unit including a plurality of delay elements connected in series for detecting delay time characteristics of the first delay unit, a detection unit detects the number of delay elements used in the first delay unit to delay an input signal by a reference time, a second delay unit including a plurality of delay elements connected in series so as to output a signal delayed in accordance with the delay time characteristics of the first delay unit, and a selection unit selects the number of delay elements in the second delay unit to delay the input signal in accordance with the number of delay elements detected by the detection unit. The ratio between each of the delay values of the plurality of delay elements in the first delay unit and each of the delay values of the corresponding the plurality of delay elements in the second delay unit are equivalent to the ratio between the reference time and a desired delay time in the second delay unit. |
| US07786773B2 |
Phase-locked loop circuit
A phase-locked loop circuit for generating an output signal includes a phase frequency detector (PFD), a processing module, and a clock generator. The PFD is implemented for generating a plurality of indicating signals according to a first reference signal and a feedback signal, where the feedback signal is generated according to the output signal. The processing module is coupled to the PFD, and is implemented for generating a control signal according to the indicating signals and a plurality of clock signals, where the clock signals have an identical frequency but different phases. The clock generator is coupled to the processing module, and is implemented for generating the clock signals according to the control signal. The output signal is generated according to a specific clock signal selected from the clock signals. |
| US07786771B2 |
Phase lock loop (PLL) with gain control
A Phase Lock Loop (PLL) with gain control is provided. The PLL has a dual-path configuration, where a first and a second VCO control voltage are generated in response to a phase or frequency difference between a PLL input signal and an output signal. The PLL comprises a dynamic voltage gain control (DVGC) unit and a voltage-to-current (V2I) unit, where the DVGC creates a baseline reference current in response to the first VCO control voltage and the V2I provides a substantially linear current in response to the second VCO control voltage. The currents from the DVGC and V2I are combined and fed into a current-controlled oscillator, which generates a PLL output frequency signal. Frequency gain of the VCO is substantially reduced, thus providing a PLL with improved tuning precision. |
| US07786769B2 |
On die signal detector without die power
In general, in one aspect, the disclosure describes an apparatus having on die circuitry coupled to at least one input port to receive a signal. A resistor is coupled to the on die circuitry and an off die power supply When a signal of sufficient amplitude is received by the on die circuitry the on die circuitry enables current to flow through the resister and reduces the voltage applied to the on die circuitry via the resister. |
| US07786768B2 |
Waveform generating circuit and spread spectrum clock generator
A spread spectrum clock generator is provided which improves the spread spectrum effect with little increasing the circuit cost by modifying the shape of a triangular wave used for frequency modulation by a simple method. The output signal of the modulation waveform generating circuit has such a modulation waveform as indicated by solid lines in FIG. 2A. The modulation waveform is input to a VCO (voltage-controlled oscillator). In response to the modulation waveform, the oscillation frequency of the VCO is modulated, and the output clock that varies its frequency as illustrated in FIG. 2B is obtained. The frequency transition of the output clock involves such temporal variations as indicated by solid lines in FIG. 2C. |
| US07786766B2 |
Appliance control system with a zero crossing detecting circuit
A control system includes a zero crossing detecting circuit for detecting a zero crossing of an AC signal. The circuit includes a transformer having a primary portion and a secondary portion. The primary portion receives the AC signal. The secondary portion comprises first and second terminals. The first terminal is biased at a first DC voltage level. An output switch is operatively connected to the second terminal and has an on state and an off state. The output switch selectively activates an output signal of the zero crossing detecting circuit according to an activation voltage level sensed by the output switch and corresponding to the zero crossing. While in the off state, the output switch is biased at a second DC voltage level. A voltage difference between the first and second DC voltage levels substantially equals the activation voltage level. A controller monitors the output signal and controls an operation based on the output signal. |
| US07786765B2 |
Low voltage shutdown circuit
A low voltage shutdown circuit comprises an input node for receiving a voltage Vin to be monitored, first and second voltage-to-current (V to I) converters arranged to receive Vin at respective inputs and to convert Vin to currents I1 and I2 at respective outputs, and a current comparison circuit arranged to produce an output which is in a first state when I1 |
| US07786764B2 |
Signal receiver and voltage compensation method thereof
A signal receiver includes a first-stage circuit, a second-stage circuit, a current compensation circuit, and a biasing circuit. A first input end of the first-stage circuit receives a reference voltage, and a second end of the first-stage circuit receives an input signal. A first input end and a second input end of the second-stage circuit are respectively coupled to a first output end and a second output end of the first-stage circuit. The current compensation circuit is coupled to the first input end of the second-stage circuit for dynamically providing a compensation current to the first input end of the second-stage circuit in response to a biasing voltage, so as to stabilize its voltage level. The biasing circuit biases the first-stage circuit and the current compensation circuit and sets the biasing voltage of the current compensation circuit in response to the reference voltage. |
| US07786763B1 |
Clock circuit with harmonic frequency detector
A clock circuit includes a phase-lock loop for generating an output clock signal based on a data signal and a harmonic frequency detector for detecting whether the frequency of the output clock signal is a harmonic frequency of a frequency of a reference clock signal. The harmonic frequency detector includes a counter for generating a first divided clock signal by dividing the frequency of the output clock signal by a first divisor. Additionally, the harmonic frequency detector includes a counter for generating a second divided clock signal by dividing the frequency of the reference clock signal by a second divisor. The harmonic frequency detector also includes a frequency comparator for generating an output indicating whether the frequency of the output clock signal is a harmonic frequency of the frequency of the reference clock signal based on the first divided clock signal and the second divided clock signal. |
| US07786761B2 |
Output buffer device
A controlling output buffer slew rate method and an output buffer circuit for a memory device is provided. The output buffer include an output stage formed by a PMOS transistor and a NMOS transistor electrically connected in series, a pre-driver for respectively controlling each gate terminal of the PMOS transistor and the NMOS transistor in order to bring these transistors to the turning-on threshold, a first wire, for transmitting a pull-up signal, coupled between the output stage and the pre-driver, and a second wire, for transmitting a pull-down signal, coupled between the output stage and the pre-driver. After a DATA signal transition (logic state is changed from “H” to “L” or “L” from to “H”), the PMOS or NMOS transistor is turned off first, and then the NMOS or PMOS transistor is turned on due to the time difference between the pull-up signal and the pull-down signal. |
| US07786758B2 |
Asynchronous clock gate with glitch protection
A tristate buffer circuit includes a tristate buffer switchable into a high impedance state in response to configuration signal, a delay stage delays the an input signal to the tristate buffer and a gating stage having inputs for the input signal, a delayed input signal and an asynchronous tristate control signal and an output supplying the configuration signal to the tristate buffer. The gating stage sets the configuration signal to the high impedance mode only when the tristate control signal is set and the input signal and the delayed input signal have logic levels indicating that no signal transition of the input signal propagates within the delay stage. Depending upon signal polarity, the input signal and the delayed input signal are required to have the same digital state or opposite digital states. |
| US07786756B1 |
Method and system for latchup suppression
Systems and methods of suppressing latchup. In accordance with a first embodiment of the present invention a latchup suppression system comprises a voltage comparator for comparing a voltage applied to a body terminal of a semiconductor device to a reference voltage. The voltage comparator is also for controlling a selective coupling mechanism. The selective coupling mechanism is for selectively coupling the body terminal to a respective power supply. The latchup suppressing system is preferably independent of a voltage supply for applying a voltage to the body terminal. |
| US07786754B2 |
High speed digital signaling apparatus and method using reflected signals to increase total delivered current
A signaling apparatus and method are described that use reflected signals to increase the total current delivered to a receiver. Dynamic source-side transmission line termination control is employed to generate reflected signals that constructively add to a nonreflected signal to enhance the signal at the receiver. Switching controls selectively connect and disconnect the transmission line source-side termination resistors to either provide signal termination or remove it. Driver designs using either voltage or current sources for use in signaling systems (including, for example, magnetic storage devices with inductive coil based write heads) are described. |
| US07786750B2 |
Methods and apparatus for compensating for skew in a differential signal using non-complementary inverters
Methods and apparatus are provided for compensating for skew in a differential signal using non-complementary inverters. A skew attenuator is provided for a differential signal having a P rail and an N rail. The skew attenuator comprises one or more non-complementary inverters for compensating for skew between the P rail and the N rail. The non-complementary inverters attenuate a time difference of arrival of transitions for the P rail and the N rail. An exemplary skew attenuator includes a first non-complementary inverter associated with each of the P rail and the N rail. The P rail and the N rail signals are each applied to a gate of one of the first non-complementary inverters, and drains of the first non-complementary inverters provide differential output signals OUTP and OUTN. The exemplary skew attenuator also includes an additional non-complementary inverter associated with each of the first non-complementary inverters. |
| US07786746B2 |
Semiconductor integrated circuit apparatus, measurement result management system, and management server
A semiconductor integrated circuit apparatus, and more particularly a technology for measuring and managing a physical amount of factors that exert an influence upon an operation of a semiconductor integrated circuit is provided; more particularly, a semiconductor integrated circuit that is an object of measurement, and a measurement circuit which measures a physical factor that exerts an influence upon the actual operation of the semiconductor integrated circuit, such as jitter or noise jitter, and noise of this semiconductor integrated circuit are provided on an identical chip; also, a measurement result of the measurement circuit of the present invention is analyzed, and is fed back to a circuit for adjusting the semiconductor integrated circuit that is the object of measurement. |
| US07786744B2 |
Probe card assembly and test probes therein
Discloses are a probe card assembly and test probes used therein. The probe card assembly includes a main body, a probe base disposed in a central portion of the main body and a plurality of test probes connected between the probe base and the main body. Each of the test probes has a tip extending from the probe base for contacting a wafer under test. The test probes include at least one power probe, at least one signal probe and a plurality of ground probes. Each of the test probes has a middle section interposed between the main body and the probe base. Each of the test probes except the ground probes has a naked middle section coated with an insulating film but not sheltered by an insulating sleeve. |
| US07786742B2 |
Prober for electronic device testing on large area substrates
An apparatus and method for testing large area substrates is described. The large area substrates include patterns of displays and contact points electrically coupled to the displays on the large area substrate. The apparatus includes a prober assembly that is movable relative to the large area substrate and/or the contact points, and may be configured to test various patterns of displays and contact points on various large area substrates. The prober assembly is also configured to test fractional sections of the large area substrate positioned on a testing table, and the prober assembly may be configured for different display and contact point patterns without removing the prober assembly from the testing table. |
| US07786741B2 |
Measuring tip for high-frequency measurement
The invention relates to a contact arrangement for a measuring probe or a measuring head for measuring high frequency, especially on a semiconductor wafer. The arrangement comprises a contact end for electrically contacting planar structures. A coplanar conductor structure having at lease two conductors carried by a dielectric is provided at the contact end. Between the dielectric and the contact end, the measuring tip is configured in such a manner that the conductors of the coplanar conductor structure are disposed in mid-air and in a resilient manner in relation to the dielectric retaining them. The invention is characterized in that the dielectric is provided with at least one arrangement for transmitting electrical signals, the arrangement being electrically connected to at least one conductor of the conductor structure in such a manner that the arrangement transmits signals from the at least one conductor that is electrically connected to the arrangement. |
| US07786740B2 |
Probe cards employing probes having retaining portions for potting in a potting region
Method and apparatus using a retention arrangement for probes used for electrical testing of a device under test (DUT). The apparatus has a number of probes each of which has a connect end for applying a test signal, a retaining portion, at least one arm portion and a contact tip for making an electrical contact with the DUT. A retention arrangement has a tip holder for holding each of the probes by its contacting tip and a plate with openings for holding each of the probes below the retaining portion. The retaining portion of each of the probes is potted in a potting region defined above the plate with the aid of a potting agent. The apparatus can be used with space transformers, a variety of probes of different geometries and scrub motion characteristics and is well-suited for use in probe card apparatus under tight pitch and small tolerance requirements. |
| US07786737B2 |
Modeling and calibrating a three-port time-domain reflectometry system
A three-port TDR front end comprises numerous components. An exemplary three-port TDR front end is a DSL modem. Information-bearing TDR signals are distorted as they pass through these components. With a perfect model of the response of its front-end, a TDR system usually can compensate for the effects of its front-end. In reality, however, the electrical characteristics of each component vary from design-to-design, board-to-board, and slowly over time The result is imperfect knowledge about the true response of the front-end, errors in the model of the front-end, and degraded TDR performance. At least for this reason it is important to precisely calibrate the response of the TDR front-end through the use of a TDR modeling system. |
| US07786735B2 |
Corrective device protection
A control system for an electrical power system includes an electrical corrective device, a voltage measuring device coupled to each phase of the electric power system, a current measuring device connected between each phase of the electric power system and the electrical corrective device, and a protective device connected to outputs of the voltage measuring device and the current measuring device. The protective device includes a controller configured to detect an imbalance using the measured voltages and currents output from the voltage measuring device and the current measuring device without using or independently of other recent voltage or current measurements for other points in the electrical corrective device and independently of a neutral-ground measurement at the electrical corrective device. |
| US07786729B2 |
Method for magnetic resonance imaging
A method of magnetic resonance imaging based on rapid acquisition by sequential excitation and refocusing is provided. The method comprises turning on a first time-encoding gradient and applying an excitation pulse in the presence of the first time-encoding gradient. The excitation pulse excites magnetization sequentially along one spatial axis. Thereafter, a first refocusing pulse is applied. A second time-encoding gradient is turned on followed by a second refocusing pulse. A third time-encoding gradient is turned on and a signal is acquired in the presence of the third time-encoding gradient. The third time-encoding gradient sums to zero with the first time-encoding gradient and the second time-encoding gradient for sequential points in space. |
| US07786726B2 |
Sensor
A magnetic sensor that is inexpensive and suppresses changes in offset voltage caused by wear. The magnetic sensor includes magnetoresistance elements having electrical resistances that change in accordance with magnetism changes. The magnetic sensor detects magnetism based on changes in the electrical resistances. The magnetoresistance elements are covered by a protective film. Part of the protective film is etched and eliminated to form a recess. |
| US07786725B2 |
Magnetic field detection apparatus for detecting an external magnetic field applied to a magnetoresistance effect element, and method of adjusting the same
A magnetic field detection apparatus capable of changing the detection range and detection sensitivity as desired for a specific application is disclosed. A magnetoresistance effect element is applied a bias magnetic field and an external magnetic field. The bias magnetic field and the external magnetic field are generated on the same straight line, and therefore the bias magnetic field functions to hamper the external magnetic field applied to the magnetoresistance effect element. Thus, the magnetization of the free layer of the magnetoresistance effect element is suppressed, and the rotational angle of the magnetized vector is reduced. As a result, the characteristic of the resistance value of the magnetoresistance effect element to the external magnetic field is shifted by an amount equivalent to the bias magnetic field. |
| US07786724B1 |
Methods and apparatus for collecting process characterization data after first failure in a group of tested devices
Collecting process characterization data local to a failed integrated circuit (IC), includes providing a wafer having ICs, each IC having contact terminals, the wafer having process characterization test sites distributed across it such that at least one process characterization test site is adjacent each IC; selecting two or more ICs for simultaneous testing; for each of those ICs, coupling two or more contact terminals of the selected IC, and a corresponding two or more contact terminals of an associated test site to corresponding input terminals of a multiplexer, each multiplexer having an output terminal and a select control input terminal, the multiplexer operable to selectively provide an electrical pathway between either an IC contact terminal or a test site contact terminal and the multiplexer output terminal; coupling the output terminal of each multiplexer to a tester channel; operating the multiplexer so that its output terminal is coupled to the IC contact terminal; simultaneously testing two or more ICs; detecting a failure of at least one of the selected ICs prior to completion of testing the remaining ICs simultaneously being tested; subsequent to detecting the failure, operating the multiplexer so that its output terminal is coupled to the test site contact terminal; and collecting process characterization data prior to completion of testing the remaining ICs. |
| US07786723B2 |
Test stage for a carrier having printhead integrated circuitry thereon
This invention provides for a test stage for a printhead integrated circuit tester for testing operation of printhead integrated circuits mounted on a carrier. The test stage includes a support structure. A fixture is arranged on the support structure and is configured to receive and locate the carrier. A clamping mechanism is arranged on the fixture. The clamping mechanism has at least one clamp assembly for clamping the carrier to the test stage. A controller controls operation of the clamping mechanism. |
| US07786721B2 |
Multilayer type test board assembly for high-precision inspection
There is provided a multilayer type test board assembly for high-precision inspection. The multilayer test board assembly comprises: a plurality of test boards separated from each other according to their functions, having input/output signal terminals, and including at least one test board each having a first section where first mounting devices sensitive to an influence of electrical signals are mounted and a second section where second mounting devices insensitive to an influence of electrical signals are mounted; spacers that arrange the test boards in parallel by spacing apart the test boards by predetermined intervals; connection cables connected to the input/output signal terminals of the test boards; and a signal shielding fence formed on each of the at least one test board so as to protect the first mounting devices from electrical signals generated by the second mounting devices. |
| US07786720B2 |
Passive mixer power detector method and apparatus
The power level of an RF signal is detected using a circuit having relatively low DC offset, high dynamic range, small frequency and temperature dependence and low flicker noise. According to one embodiment, the power detector circuit comprises a chain of amplifiers and a passive mixer. The chain of amplifiers converts the RF input signal to a supply-limited RF square wave signal. The passive mixer passively mixes the supply-limited RF square wave signal with the RF input signal and in response generates a rectified output signal that tracks the amplitude of the RF input signal. |
| US07786719B2 |
Optical sensor, optical current sensor and optical voltage sensor
A simple constitution together with an easy calibration of output by realizing a fast light intensity detection method is realized without using the carrier signal.An optical sensor, including: a sensor to which light from a light source is lead, and by which light intensity of the light is modulated based on a physical value; light receiving elements 61 and 62 receiving two elements of divided light PA and PB having polarized waves which are orthogonally crossing each other; a variable optical attenuator operating light which is received by the light receiving elements 61 and 62; and a variable amplifier operating output signals from the light receiving elements 61 and 62, wherein both a zero point of a sensor output and sensitivity are calibrated based on a light attenuation factor or an amplification factor which is adjusted when a physical value is detected by calculating a ratio between a sum and a difference of outputs of the light receiving elements 61 and 62. |
| US07786716B2 |
Nanosatellite solar cell regulator
A solar cell regulator in a nanosatellite includes a pulse width modulated DC-DC boost converter and a peak power tracking controller for converting solar cell power to bus power for charging of system batteries and powering loads while the controller controls the pulse width modulation operation of the converter for sensing solar cell currents and voltages along a power characteristic curve of the solar cell for peak power tracking, for determining any power data point, including a peak power point, an open circuit voltage point, and a short circuit current point along the power characteristic curve of the solar cell, and for communicating the power data to a satellite processor for monitoring the performance of the solar cell during operational use of the satellite. |
| US07786715B2 |
Dc/dc converter
The present invention is related to a dc/dc converter. A dc/dc converter according to the present invention comprises an inductor, a switch unit connected to both ends of the inductor and charging or retrieving an energy into the inductor, an output unit comprising an output switch unit outputting the energy charged in the inductor into an output end and a first comparison unit controlling an on-off of the output switch unit, a freewheeling switch unit connected to both ends of the inductor and returning a residual current remained in the inductor, a current sense unit sensing the residual current, an offset current generation unit generating an offset current, an error amplifier comparing the residual current inputted from the current sense unit to the offset current generated in the offset current unit and outputting the error signal, and a control unit controlling the switch unit with the error signal inputted from the error amplifier. |
| US07786712B2 |
High-efficiency DC/DC voltage converter including up inductive switching pre-regulator and capacitive switching post-converter
A DC/DC converter includes a pre-regulator stage, which may include a boost converter, and a post-converter stage, which may include a charge pump. The duty factor of the pre-regulator stage is controlled by a feedback path that extends from the output terminal of the pre-regulator stage or the post-converter stage. The pre-regulator steps the input DC voltage up by a variable amount depending on the duty factor, and the post-converter steps the voltage at the output of the pre-regulator up or down by an positive or negative integral or fractional value. The converter overcomes the problems of noise glitches, poor regulation, and instability, even near unity input-to-output voltage conversion ratios. |
| US07786709B2 |
Bi-polar bi-directional energy balancing power-conversion engine
The invention provides a power converter and method for controlling same, comprising a plurality of switch elements, an inductive reactor, and at least two ports for the movement of electrical energy. Any energy-moving port may be made unipolar, bidirectional, bipolar, or bidirectionally bipolar. Ports may be equipped with sensing circuitry to allow the converter output to be controlled responsively to an input signal. The invention may be configured to be used in many ways, for example, as a power-supply, as an amplifier, or as a frequency converter. The invention may comprise energy predictive calculating means to obtain excellent transient response to line and load variations. The invention may also include a switch to create a low impedance path around the inductor to allow current to recirculate through the inductor when it is not needed at any of the ports. |
| US07786708B2 |
Starter/generator system with control to address a voltage rise
A control circuit for a generator has a control function that monitors the voltage across a bus capacitor. The circuit delivers excess voltage back to associated stator windings if an unduly high voltage is detected across the bus capacitor. |
| US07786702B1 |
Battery conditioner and charger
An apparatus for charging either a normal or a sulfated type of a storage battery includes a first charging stage, a second charging stage, and a final third charging stage. The first charging stage applies a pulsed voltage with a high peak and average voltage to the battery until an average current of about 12 amperes is attained, at which time transition into the second charging stage occurs. A pulse width modulator reduces the average voltage and average current to a safe level and continue to charge the battery for about 20 minutes. At that time transition into the third charging stage occurs wherein a low ripple 14.8 VDC steady state current-limited voltage is applied to the battery for a second duration of about four hours, after which charging is complete and the apparatus shuts itself off. |
| US07786700B2 |
Battery-powered apparatus, method of controlling the apparatus, program for implementing the method, and storage medium storing the program
A battery-powered apparatus which makes it possible to perform battery check with accuracy irrespective of whether a battery is used as an internal battery or an external battery and make the end voltages of the internal battery and the external battery coincide with each other. It is determined whether the battery or an accessory having the battery incorporated therein has been attached to the apparatus, and a predetermined voltage threshold level is set based on the determination result. The voltage value of the battery or the accessory having the battery incorporated therein is detected, and the detected voltage value and the voltage threshold level are compared with each other to decide whether or not it is possible to drive the apparatus. |
| US07786699B2 |
Power supply charger and method of charging
A power supply charger for charging battery cells divided into at least two battery cell groups, each battery cell group having an associated protector circuit module. The power supply charger comprises, for each battery cell group, a power converter, a constant-current and constant-voltage device connected to the power converter for selectively applying a voltage from the power converter across the battery cell group and a current sensing circuit. The power supply charger further comprises, for each battery cell of a battery cell group, a voltage sensing circuit and a balancer circuit. Finally, the power supply charger comprises a micro-controller operatively connected to the various components and is so configured as to, for each battery cell group, selectively apply a voltage across the battery cell group or decrease the voltage of individual battery cells in the battery cell group in response to sensed battery cell voltage and battery cell group current. |
| US07786696B2 |
Battery pack charged by external power generator and supplying discharge power to external load in parallel to external power generator
A battery pack that is charged with power generated in an external power generator and supplies battery power to an external load in parallel with the external power generator, and a power receiving device of a portable electronic device that receives and supplies battery power to an external load in parallel with the external power generator, the battery pack including: a battery cell to discharge power based on a charged amount of electric charge; an external power input terminal to receive power from an external power generator; a power output terminal to supply power to an external load; and a voltage transforming circuit to transform voltage of the power received through the external power input terminal to transfer the transformed voltage to the power output terminal. |
| US07786693B2 |
Method for braking a running metal strip and unit for carrying out the method
The method and unit for braking a metal strip (1), running off a wind-out coiler (2.1) in the form of a coil (1.1) and running onto a wind-on coiler (2.2) again, are to guarantee that a surface of the metal strip remains undamaged and a full effective braking force is exerted on the metal strip (1) by means of an eddy current brake (3.1) with a rotating magnet system (3.2). The above is achieved, whereby the braking force is exerted on the metal strip (1) by means of an induced counter-torque against a support bearing (4) to one side in a non-contact manner, whereby the support bearing (4) may be embodied as a counter roller (4.1). |
| US07786692B2 |
Signal transmission apparatus of a DC brushless motor for a ceiling fan
A signal transmission apparatus of a DC brushless motor for a ceiling fan is provided. The signal transmission apparatus comprises a transmitting line. The transmitting line is configured to transmit processed output signals of a plurality of electromagnetic sensors, in which usage of transmission lines is reduced. The output signals of the electromagnetic sensors represent the operation of the magnetic poles of the DC brushless motor. |
| US07786691B2 |
Bus disturbance regulator
Presented is a harmonic regulator that regulates a plurality of individual harmonics in a system having periodic torque disturbances to commanded values, including zero. For each harmonic being regulated, a feedback signal having at least one harmonic component due to the harmonic being regulated is transformed from a source reference frame to a harmonic reference frame of the harmonic being regulated to form a qd feedback signal. The qd feedback signal is subtracted from the commanded value to form a qd signal and regulated. The regulated qd signal is transformed to a destination reference frame to form a compensation signal and the compensation signal is added to a control signal to form a qd control signal that drives each harmonic being regulated towards the commanded value. |
| US07786688B2 |
Motor drive circuit
A drive signal generation circuit generates drive signals that control ON and OFF states of transistors of a H-bridge circuit, in accordance with a target value of torque. A driver circuit alternatively turns ON and OFF high side transistors, and low side transistors of the H-bridge circuit, based on the drive signals outputted from the drive signal generation circuit. The driver circuit immediately turns OFF the high side transistors, when an instruction is issued to stop a motor, and after a predetermined delay time τd has elapsed, turns OFF the low side transistors. |
| US07786686B2 |
Method and device for estimating the angular position of the rotor of a brushless motor
A method is for estimating an angular position of a rotor of a motor having position sensors along the circumference of a stator and generating digital signals that switch each time the rotor crosses certain angular positions. The method includes storing rotor angular positions at every digital signal switching, and determining for each rotor revolution a time interval elapsed between a current and a precedent switching edge of the signal generated. The method also includes estimating the angular position during a current rotor revolution by identifying which position sensor generated the last detected switching edge. The corresponding angular position and the time interval elapsed between two consecutive rotor crossings, through a same angular position, correspond to a sum between the angular position and a product between a fraction of the time interval elapsed from the corresponding precedent switching edge multiplied by 360° and a number of polar pairs. |
| US07786676B2 |
LED driver structure
The present invention discloses an LED driver structure, which obtains input power coming from a power source to generate a constant-current power to drive a plurality of LEDs, and which comprises: a plurality of diode groups connected in parallel, a first piezoelectric conversion unit and a second piezoelectric conversion unit respectively arranged at both sides of the diode groups. The first and second piezoelectric conversion units receive the input power and opposite-phase convert the input power into driving powers to drive the diode groups. Among the plurality of diode groups, at least one diode group is formed of a plurality of LEDs. Each of the first and second piezoelectric conversion units has a piezoelectric inverter, which can easily achieve an impedance matching and a constant-current power to drive LEDs via a piezoelectric effect. Besides, the present invention also has the advantage of cost efficiency. |
| US07786675B2 |
Fast ferroelectric phase shift controller for accelerator cavities
The present invention relates to methods and systems for fast ferroelectric tuning of RF power used in a particle accelerating system. By adjusting the voltages fed to the ferroelectric phase shift controller, the amplitude and phase of the RF power wave are altered, thus changing the coupling of the power generating circuit and the superconducting cavity. By altering this coupling rapidly, maximum power transfer efficiency can be achieved, which is important given the large amounts of power shunted through the particle accelerating system. In one embodiment, the ferroelectric tuner is optimally made of a magic-T waveguide circuit element and two phase shifters, although other implementations of the system may be utilized. Alternative phase shifters are shown. |
| US07786673B2 |
Gas-filled shroud to provide cooler arctube
A lamp is provided having an arctube having a light-transmitting envelope. The arctube is surrounded by a gaseous medium confined by a containment envelope such as a hermetic shroud. The gaseous medium is preferably He or H2 or Ne or another gas whose thermal conductivity is greater than that of N2 at 800° C., or a mixture thereof, to help cool the arctube. The inside and/or outside of the shroud may be coated with a diffusion barrier. To help cool the hot spot of the arctube the gap between the shroud and the envelope can be made small, the portion of the shroud wall near the arc can be thickened, the arctube can be offset above the longitudinal axis of the shroud, and the return lead of the arctube can be located between the shroud and the arctube. |
| US07786671B2 |
Photomultiplier tube with least transit time variations
A single-channel photomultiplier tube having a sealed envelope, of which one wall includes an internal face having a concavity with a central axis, turned toward the inside of the tube, having a plane of symmetry and containing a photocathode, inlet optics including electrodes, an electron multiplier including a plurality of dynodes, an anode, and a mechanism connecting the dynodes, the photocathode, electrodes of the optics, and the anode, at their respective operating voltages. The electron multiplier is composed of parts physically distinct from one another, and having between them a symmetry of revolution with respect to the central axis of the concavity. |
| US07786670B2 |
Organic light emitting diodes
This invention relates to organic light emitting diodes (OLEDs) and to methods for their manufacture. The invention provides an OLED element or display which enables contrast to be produced in an image. In accordance with the invention a layer of ink is patterned as a blocking layer between two OLED layers. The ink reduces or prevents conduction, i.e. movement of charge, between the two OLED layers in that area of the device. The ink may be dark in color, e.g. black, to increase the contrast ratio of the OLED. The blocking layer is provided between any two layers in the OLED and blocks the charge movement in these areas. The blocking layer may comprise a multiplicity of ink dots, the density of which determines the extent to which conduction is hindered. The blocking layer may be produced as a “grey-scale” pattern wherein the density of dots is varied across the pattern. |
| US07786669B2 |
Organic electro-luminescence display device and method for fabricating the same
An organic electro-luminance display device includes a first substrate including a plurality of sub-pixels, a first electrode on the first substrate, a buffer layer on the first electrode of a region that partitions each of the sub-pixels, a spacer on the buffer layer, the buffer layer and the spacer being integrally formed, an organic light-emitting layer on the first electrode that corresponds to each of the sub-pixels and the spacer, and a second electrode on the organic light-emitting layer. |
| US07786668B2 |
Organic EL device
An organic EL device includes an element region having a plurality of light-emitting elements, each including a first electrode disposed on a substrate body, a functional layer disposed above the first electrode, and a second electrode disposed above the functional layer; an enclosing member which surrounds the element region, covers the peripheral sides of the functional layers contained at least in the light-emitting elements located closest to the outer periphery of the substrate body among the plurality of light-emitting elements, and is disposed on the substrate body; a conductive member placed outside the enclosing member; and a connecting conductive member which is connected to the conductive member, extends from outside of the enclosing member over the enclosing member, and is connected to the second electrode. The connecting conductive member has a thickness larger than the thickness of the second electrode. |
| US07786664B2 |
Plane display device
An embodiment of the invention provides a plane display device in which a cathode panel having a plurality of electron emitting areas provided therein, and an anode panel having phosphor layers and an anode electrode provided therein are joined to each other in their peripheral portions, and a space defined between the cathode panel and the anode panel is kept at a vacuum, the plane display device, including: an exhaust tube made of a conductive material, the exhaust tube having one end portion communicating with the space, and the other end portion located outside the plane display device; and an elastic member made of a conductive material; in which the exhaust tube and the anode electrode are electrically connected to each other through the elastic member disposed in the space; and a predetermined voltage is applied to the anode electrode through the exhaust tube and the elastic member. |
| US07786663B2 |
Flat panel display having a control frame pedestal and method of making same
A method for providing a flat panel display includes the steps of: providing an anode assembly containing a plurality of pixels; applying a photoresist to a surface of the anode assembly; applying a mask that defines a control frame top surface; exposing the mask to UV radiation and causing the photoresist to cross link at the exposed areas of the photoresist such that the exposed photoresist is inert and does not outgas in a vacuum; removing the unexposed areas of the photoresist to define a pedestal; forming a planarizing layer over the exposed photoresist pedestal; applying a metal layer over the planarizing layer; applying a second photoresist over the metal layer; exposing portions of the second photoresist and removing excess of the metal layer and the planarizing layer to form the metal layer only on top of the exposed photoresist pedestal; and applying nanotube emitters on the metal layer. |
| US07786661B2 |
Emissive electrode materials for electric lamps and methods of making
Electron emissive compositions comprising a barium neodymium oxide are described. These compositions may be applied to electrodes such that electron emission is facilitated. Methods of manufacturing emissive electrodes comprising a barium neodymium oxide are also described. Various discharge lamps employing such electrodes are described as well. |
| US07786658B1 |
Electron-emitting device and image display apparatus using the same
An electron-emitting device has an insulating layer having a side surface, a recess portion formed on the side surface of the insulating layer, a gate electrode which is arranged above the recess portion, and a wedge-shaped emitter which is arranged on an edge of a lower side of the recess portion and has a first slope on a side of the recess portion and a second slope on a side opposite to the recess portion. A lower end of the first slope of the emitter enters the recess portion, and both the first slope and the second slope of the emitter tilt to an outside of the recess portion. |
| US07786657B2 |
Spark plug for internal combustion engine
A spark plug including a ground electrode and a noble metal tip joined to a distal end portion of the noble metal tip. The noble metal tip is joined to the ground electrode via a molten bond in which the noble metal tip and the ground electrode are fused. A protruding length of the noble metal tip is 0.3 mm or more. Regarding the molten bond, relationships 50≦S1+S2≦120 and θ1>θ2 are satisfied for a first molten angle S1°, a second molten angle S2°, a first contact angle θ1° and a second contact angle θ2° as defined herein. |
| US07786651B2 |
Micromotion mechanism having ultrasonic motor and oscillation element holding mechanism
A micromotion mechanism having an ultrasonic motor includes: a fixing base; a moving element supported to be movable in the moving axis direction with respect to the fixing base; an oscillation element having a rectangular geometry including a first plane parallel to the moving axis direction and provided with a plurality of projections and a second plane parallel to the first plane for exciting a plurality of oscillation modes by applying a high frequency voltage signal, and a holding mechanism for holding the oscillation element with respect to the fixing base. The holding mechanism is fixed to a part of the second plane of the oscillation element, and is incorporated with a high rigidity material not including high nonlinearity elements including at least one of a friction sliding unit and a rubber member. |
| US07786646B2 |
Magnetic force rotation device
A magnetic force rotation device includes a rotor and a stator. The rotor is provided with a plurality of magnetic assemblies containing permanent magnet. The plurality of magnetic assemblies are arranged along the circumferential direction of the rotating shaft to form a wheel-shaped ring, and each magnetic assembly is provided with two magnetic poles. The stator is provided with a plurality of magnetically isolated electromagnets coaxially arranged. The electromagnets form a wheel-shaped ring around the rotating shaft, and each electromagnet is provided with paired poles. The wheel-shaped ring of the stator is at least party surrounded by the wheel-shaped ring of the rotor, so that each pole of the paired poles of the electromagnets of the stator corresponds to one magnetic pole of the two magnetic poles of the magnetic assemblies of the rotor respectively. Two axial component air gaps are provided between the rotor and the stator. One of the above two axial component air gaps and two radial component air gaps are provided between one of the paired poles of the electromagnets of the stator and one corresponding magnetic pole of the two magnetic poles of the magnetic assemblies of the rotor. |
| US07786641B2 |
Magnetic member, rotor and motor
In the present invention, since gaps respectively provided at one ends of a field magnet through-hole respectively extend toward the other ends passing on the side of a periphery with respect to the field magnet through-hole, the radial dimension of the magnetic member in this portion can be made smaller than the center of magnetic poles, so that the difference in thickness of the magnetic member in the radial direction between the border of magnetic poles and the magnetic poles can be reduced. Accordingly, the asymmetry of the configuration of a rotor is not absolutely necessary, and the outer surface does not need to be depressed for reducing the torque ripple. |
| US07786640B2 |
Drive device
A drive device includes an input shaft connected to an engine; a first rotating electrical machine and a second rotating electrical machine; a differential gear unit including a first rotating element, a second rotating element, and a third rotating element; and a control device. The first rotating electrical machine and the differential gear unit are positioned coaxially with the input shaft. The first rotating electrical machine and the second rotating electrical machine are positioned on different axes from each other so as to axially overlap each other. A first component of the control device is positioned lower than the first rotating electrical machine and positioned so that at least a part of the first component overlaps the first rotating electrical machine when viewed in a vertical top plan view. |
| US07786639B2 |
Motor
A motor includes a bearing having first and second end faces spaced along a longitudinal axis thereof. A longitudinal hole extends from the first end face through the second end face and includes a recessed portion having first and second peripheral edges respectively contiguous to the first end face and an inner periphery of the longitudinal hole. A retaining member is mounted to the first end face. A radial spacing between an inner periphery of a through-hole of the retaining member and the inner periphery of the longitudinal hole of the bearing in a radial direction is not greater than an axial spacing from the first end face to the second peripheral edge. The retaining member further includes a plurality retaining plates. The recessed portion provides a space sufficient to allow deformation of the retaining plates when inserting a shaft through the through-hole into the longitudinal hole of the bearing. |
| US07786638B2 |
Electric machine having a hybrid bearing
An electric machine having a hybrid bearing for the purpose of supporting a rotor with respect to a stator, the hybrid bearing consisting of a radial bearing, taking the form of a fluid dynamic bearing, and an axial bearing that is made up of magnetic elements, wherein the magnetic elements comprise at least one permanent magnet and one flux guide element that are disposed so as to be located opposite each other in a radial direction. |
| US07786637B2 |
Touchdown bearing
A calcium zinc phosphate-type coating is formed on at least one of those surfaces of an inner ring, an outer ring and rolling elements (balls) and further a cage (if the cage is used) (which form a touchdown bearing) contacting other members, and further a molybdenum disulfide coating is formed thereon. By doing so, the adhesion of the molybdenum disulfide coating is enhanced by microscopic pits and projections due to crystal grains on the surface of the calcium zinc phosphate-type coating, and also even when the molybdenum disulfide coating is worn out, the wearing-out of a substrate can be suppressed by the lubricating ability of the calcium zinc phosphate-type coating underlying it. |
| US07786635B2 |
Motor for high moisture applications
A motor that includes a motor frame, an end-bell assembly, a stator assembly, and filling material is described. The stator assembly is placed within the frame such that at least one open area is defined between an inner diameter of the stator assembly and an inner diameter of the motor frame. The at least one end-bell assembly is attached to the motor frame, forming an inside area adjacent the motor frame and the stator assembly. The motor also includes a material configured to fill the at least one open area and the inside area of the at least one end-bell assembly for the purpose of sealing the stator assembly and the inside area associated with the at least one end-bell assembly. The material assists in a bonding and attachment between any two or more of the stator assembly, the motor frame, and the at least one end-bell assembly. |
| US07786634B2 |
Motor- or a generator-related arrangement
The disclosure relates to a motor- or generator-related arrangement or structure (20) with two parts (5, 15) rotatably disposed in relation to one another, where a first part (5), serving as rotor unit, is rotatably disposed about a shaft (7) in a first selected direction of rotation, and a second part (15), serving as stator unit, is rotatably disposed about said shaft (7) in a second selected direction of rotation counter directed to said first selected direction of rotation. Means (2, 3, 4, 14 and 13) are arranged for transforming the speed of the first direction of rotation to the second direction of rotation. Said means includes a first gear rim or ring (14), associated with the stator unit (15), at least two gear rotary wheels (4, 4′), coordinated with a housing (1, 11), and a second gear rim or ring (3) associated with the rotor (5). |
| US07786632B2 |
Terminal device for vehicle AC generator
A terminal device for a vehicle AC generator including a common base terminal group 100A1 having a plurality of terminals and an external connector terminal 200A1 formed by integrating a plurality of individual connector terminals having connecting terminals with respect to the external device at one ends thereof and having connecting terminal portions to be connected to a regulator circuit at the other ends thereof by premolding with respect to each other, in which the external connector terminal is arranged at predetermined positions of the common base terminal group, and the common base terminal group and the external connector terminal are integrally mold-formed with resin. |
| US07786630B2 |
Spray cooled V-wedge for aerospace generator
A high speed generator cooling system directs a cooling oil spray through a chamber inside a coil support wedge assembly, which may be disposed adjacent to the generator coils. Heat from the generator coils may be conducted through the walls of the coil support wedge assembly and into the chamber where it is removed by the cooling oil spray passing through the chamber. The cooling oil passes through a generator rotor shaft and into a cooling passage in least one of the rotor laminations. |
| US07786627B2 |
Electrical hand-held power tool with cooling of electronics
An electrical hand-held power tool includes a drive motor, a ventilation device (10) for generating an air flow (L) along a main flow path (26) for cooling the drive motor (8), and an electronic device (22) for controlling operation of the drive motor (8) all of which are located in the housing (4), and a plurality of air conducting elements (30) that project from an inner wall (32) of the housing for limiting an auxiliary flow path (36) through which at least a portion of the air flow (L) is forwarded to the electronic device (22), with the air conducting elements (30) forming an auxiliary path inlet (40) of the auxiliary flow path (36) and which projects between a main path inlet (24) of the housing (4) and the ventilation device (10) into the main flow path (26), so that the auxiliary path inlet (40) is walled off from the ventilation device (10). |
| US07786624B2 |
Power control device
A power control device prevents unauthorized and unwanted use of electrical devices by locking the plug of the electrical device in the power control device, when the current flowing through the power control device is stopped. The device includes a switch, moveable between on and off conditions by moving a slide lock or bolt, typically by rotating a key in a locking structure. When the slide lock has moved into contact with the switch, such that it is in an off-condition and current is not flowing through the power control device, the slide lock has also locked the plug in the power control device. The electrical device is temporarily inoperable and can not resume normal operation until the power control device is unlocked. |
| US07786623B2 |
Power management for electronic devices
A cordless electronic device with power management system and method is provided that includes an outer surface, a power consumption circuit operable to consume power and for use in a cordless electronic device, a power supply circuit operable to regulate the power from a power source used to power the power consumption circuit of the cordless electronic device, a power control circuit operable to receive an input signal and to place the power consumption circuit in a lower or higher power state upon receipt of the input signal, a presence sensor operable to detect the presence of a user and to provide a presence sensor input signal to the power control circuit to place the power consumption circuit in the higher power state. |
| US07786621B2 |
Circuit arrangement and method for reducing electromagnetic interference
Circuit arrangement and method for reducing electromagnetic interference. The circuit arrangement includes a supply potential connection, a reference-ground potential connection, a controllable impedance element, a signal generator, and a circuit unit. The controllable impedance element is connected between the supply potential connection and the reference-ground potential connection, and has a control connection for receiving a control signal for controlling the impedance of the impedance element. The signal generator is coupled to the control connection of the impedance element. The circuit unit is connected between the supply potential connection and the reference-ground potential connection, and originates the electromagnetic interference during operation. The signal generator is designed to produce the control signal, which varies over time, in such a manner that the electromagnetic interference which originates from the circuit unit during operation is changed. |
| US07786619B2 |
DC power backup
A barrier movement operator with a backup source of DC power is disclosed. The power supply of the barrier movement operator sends current limited DC to the backup which uses the DC to charge a battery. The battery is in circuit at all times with the barrier movement operator power supply by means of a power diode and, when an AC mains power failure occurs, DC power is sent from the battery to power the barrier movement operator. |
| US07786618B2 |
Apparatus, system and method for a UPS
According to one aspect of the invention, a UPS includes an input configured to be coupled to an AC power source, a DC power source, an output configured to receive power from at least one of the AC power source and the DC power source, a first switched receptacle outlet coupled to the output and configured to be coupled to a first electrical load and a second receptacle outlet coupled to the output and configured to be coupled to a second electrical load. According to some embodiments, the UPS also includes a control unit configurable to provide a first configuration associated with the first switched receptacle outlet, where the first configuration is employed by the control unit to control a connection of the first switched receptacle outlet to the output independent of the second receptacle outlet. |
| US07786616B2 |
Generator with DC boost and split bus bidirectional DC-to-DC converter for uninterruptible power supply system or for enhanced load pickup
A local power generation system generates DC voltage at an inverter input, modulated to generate an AC power signal to a load. The inverter input voltage may be obtained from an engine generator, providing a rectified AC power signal. An energy storage device helps maintain DC voltage at the inverter input when load power draw increases or during engine startup or acceleration, for example, until the engine accommodates increased power demand. The system may also be used in an uninterruptible power supply (UPS), in which the load draws power from a utility-provided AC power source until a fault condition appears. When the fault condition appears, the load switches its power draw from the utility-provided AC power source to the inverter output. The energy storage device is charged through a bidirectional DC-to-DC converter and through an inverter operating in rectifier mode to rectify a utility-provided AC power signal. |
| US07786615B2 |
Power distribution architecture for actuating moving elements of an aircraft in sequence
The invention relates to an electrical power distribution architecture specially adapted for actuating in sequence aircraft moving elements such as doors, undercarriages, or high-lift elements, said moving elements being actuated by electromechanical actuators powered in sequence from electrical power delivered by at least one electrical power bus of the aircraft. |
| US07786612B2 |
Wind turbine power module mounted on the tower foundation
The invention relates to a method of constructing a wind energy plant and to a wind energy plant as such. In one aspect, the invention provides a method for constructing wind energy plants at lower expenses and more rapidly. According to one embodiment, a method for constructing a wind energy plant that comprises a tower that is based on a foundation and an electrical power module, the power module is mounted on the tower foundation before the tower itself is constructed. The power module includes a transformer and may optionally an inverter and/or other electrical installations, such as for example switch cabinets, that are provided for controlling the wind energy plant and/or for guiding the electrical power that is provided by the generator of the wind energy plant and that is fed to a network. |
| US07786610B2 |
Funneled wind turbine aircraft
An aircraft adapted to house a wind funnel and a wind turbine configured to convert the airflow through the wind funnel into electricity. An electrical cable between the aircraft and a ground station transfers the generated electricity from the aircraft to the receiving ground station for distribution. A plurality of aircraft according to certain embodiments may form a system for generating electricity from airflow. |
| US07786608B2 |
Protection system for wind turbine
A braking system for a wind turbine is provided, and the wind turbine includes a rotor having at least one blade. A generator includes a plurality of stator windings having a plurality of phases. The braking system includes a plurality of resistors, and at least one switch connected between the stator windings and the resistors. The switch can be configured to connect the stator windings to each other via the resistors, for the effect of slowing down or stopping the rotor of the wind turbine. |
| US07786593B2 |
Integrated circuit die with pedestal
An integrated circuit die is provided having a body portion having a singulation side and a pedestal portion extending from the body portion and having a singulation side coplanar with the singulation side of the body portion. |
| US07786592B2 |
Chip capacitive coupling
A method of creating a semiconductor chip having a substrate, a doped semiconductor material abutting the substrate and a device pad at an outer side of the doped semiconductor material involves creating a via through at least a portion of the substrate, the via having a periphery and a bottom at a location and depth sufficient to bring the via into proximity with the device pad but be physically spaced apart from the device pad, introducing an electrically conductive material into the via, and connecting the electrically conductive material to a signal source so the signal will deliberately be propagated from the electrically conductive material to the device pad without any direct electrical connection existing between the electrically conductive material and the device pad. |
| US07786591B2 |
Die down ball grid array package
A cavity or die down ball grid array package includes an interposer substrate structure attached to the die. In an example, the interposer substrate reduces the interconnect length from a board to which the package mounts to power and ground pads on a top layer of the semiconductor or integrated circuit (IC) die. In this example, the interposer substrate also removes the requirement that power and ground pads be located on a periphery of the die. Power and ground pads can be located in an interior region on a top metal layer where they can be interconnected to the interposer substrate using electrically conductive bumps or wire bond(s). |
| US07786588B2 |
Composite interconnect structure using injection molded solder technique
Composite interconnect structure forming methods using injection molded solder are disclosed. The methods provide a mold having at least one opening formed therein with each opening including a member of a material dissimilar to a solder to be used to fill the opening, and then fill the remainder of each opening with solder to form the composite interconnect structure. The resulting composite interconnect structure can be leveraged to achieve a much larger variety of composite structures than exhibited by the prior art. For example, the material may be chosen to be more electrically conductive than the solder portion, more electromigration-resistant than the solder portion and/or more fatigue-resistant than the solder portion. In one embodiment, the composite interconnect structure can include an optical structure, or plastic or ceramic material. The optical structure provides radiation propagation and/or amplification between waveguides in the substrate and device, and the plastic material provides fatigue-resistance. |
| US07786585B2 |
Semiconductor integrated circuit device
In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 μm and is smaller than about 1.44 μm, and the width of a second Cu wiring and the diameter of a plug are about 0.18 μm, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other. |
| US07786573B2 |
Packaging chip having interconnection electrodes directly connected to plural wafers
A packaging chip formed with plural wafers. The packaging chip includes plural wafers stacked in order and plural interconnection electrodes directly connecting the plural wafers from an upper surface of an uppermost wafer of the plural wafers to the other wafers. At least one or more of the plural wafers mounts a predetermined circuit device thereon. Further, at least one or more wafers of the plural wafers have a cavity of a predetermined size. Meanwhile, the packaging chip further includes plural pads independently arranged on the upper surface of the uppermost wafer one another and electrically connected to the plural interconnection electrodes respectively. Accordingly, the present invention can enhance the performance and reliability of a packaging chip and improve fabrication yield. |
| US07786571B2 |
Heat-conductive package structure
A heat-conductive package structure includes a carrier board having a first surface and an opposing second surface and formed with a through opening passing the carrier board; a first heat-conductive structure including a heat-conductive hole in the through opening, a first heat-conductive sheet on the carrier board, and a second heat-conductive sheet on the carrier board, wherein the first and second heat-conductive sheets are conductively connected by the heat-conductive hole; a first dielectric layer formed on the first surface of the carrier board and formed with a first opening for exposing the first heat-conductive sheet; a second dielectric layer formed on the second surface of the carrier board and formed with at least a second opening for exposing a portion of the second heat-conductive sheet; and a second heat-conductive structure formed in the second opening and mounted on the second heat-conductive sheet. |
| US07786567B2 |
Substrate for electrical device and methods for making the same
Substrate for electrical devices and methods of manufacturing such substrate are disclosed. An embodiment for the substrate comprised of an insulator and a plurality of conductive elements, wherein the conductive elements embedded in the insulator, and two surfaces of the conductive element exposed to two surfaces of the insulator for electrical connection respectively, meanwhile a portion of conductive element may protrude the insulator, in this manner, solder balls are not needed, moreover the conductive element of substrate may further include either an extending portion or a protruding portion, and the present invention may be capable of affording a thinner electrical device thickness, enhanced reliability, and a decreased cost in production. |
| US07786558B2 |
Semiconductor component and methods to produce a semiconductor component
A semiconductor component and production method is disclosed. In one embodiment, the semiconductor component includes at least one vertical semiconductor power device having an upper side which includes at least one output electrode and a lower side which includes at least one input electrode and at least one control electrode. A contact clip with at least one peripheral rim portion is disposed on and electrically connected to the output electrode. The peripheral rim portion extends over and spaced from an edge of said semiconductor power device and terminating in a clip rim surface with is substantially coplanar with the source electrode and gate electrode. A thermally conductive, electrically insulating isolation layer is disposed on the upper surface of the contact clip and an electrically conductive layer is disposed on at least regions of isolation layer. The electrically conductive layer lies at a free potential and provides a connection surface for heat dissipating means. |
| US07786555B2 |
Semiconductor devices with multiple heat sinks
A semiconductor device that includes multiple heat sinks is provided along with methods for forming a semiconductor device having multiple heat sinks. The semiconductor device includes a first heat sink that is configured as a conductive lead frame. The conductive lead frame is electrically coupled to a conducting area of a semiconductor die. The semiconductor device also includes a second heat sink that is configured as a conductive clip. The conductive clip is electrically coupled to another conducting area of the die. Alternative embodiments of the device may include more than two heat sinks. |
| US07786551B2 |
Integrated circuit system with wafer trimming
An integrated circuit system includes an integrated circuit wafer, forming a trimmed edge on the integrated circuit wafer, and applying a thinning process on the integrated circuit wafer with the trimmed edge. |
| US07786547B2 |
Formation of active area using semiconductor growth process without STI integration
A semiconductor device can be formed without use of an STI process. An insulating layer is formed over a semiconductor body. Portions of the insulating layer are removed to expose the semiconductor body, e.g., to expose bare silicon. A semiconductor material, e.g., silicon, is grown over the exposed semiconductor body. A device, such as a transistor, can then be formed in the grown semiconductor material. |
| US07786542B2 |
Dual image sensor and manufacturing method thereof
Embodiments relate to a dual image sensor which includes a first device including a first wafer having a first inclined step, a first reflective face on an inclined plane on the first inclined step, at least one first microlens over a lower end surface adjacent the first inclined step, and a first via-hole filled with metal on an upper end face adjacent the first inclined step. A second device in the dual image sensor includes a second wafer having a second inclined step, a second reflective face on an inclined plane on the second inclined step, and at least one second microlens over a first portion of an upper end face adjacent the second inclined step. A dual image sensor is formed by connecting the metal in the first via-hole and the metal in the second via-hole together. The dual image sensor is capable of imaging light incident from one or both sides as well as light incident in front or rear of the image sensor. |
| US07786538B2 |
Semiconductor device having a nickel silicide layer on a single crystal silicon layer
A semiconductor device includes: a first MOSFET including: first source and drain regions formed at a distance from each other in a first semiconductor region; a first insulating film formed on the first semiconductor region between the first source region and the first drain region; a first gate electrode formed on the first insulating film; a first sidewall insulating film formed at side portions of the first gate electrode; a first single-crystal silicon layer formed on each of the first source and drain regions, and having at least an upper-face made of a {111} plane; a first NiSi layer formed at least on the first single-crystal silicon layer, and having a portion whose interface with the first single-crystal silicon is on the {111} plane of the first single-crystal silicon layer and a part of the portion of the first NiSi layer being in contact with the first sidewall insulating film; and a first TiN film being in contact with the portion of the first NiSi layer on the {111} plane of the first single-crystal silicon. |
| US07786536B2 |
Semiconductor device and method for fabricating the same
In a semiconductor device, a first p-type MIS transistor includes: a first gate insulating film formed on a first active region; a first gate electrode formed on the first gate insulating film; a first side-wall insulating film; a first p-type source/drain region; a first contact liner film formed over the first active region; a first interlayer insulating film formed on the first contact liner film; and a first contact plug formed to reach the top surface of the first source/drain region. The first contact liner film has a slit extending, around a corner at which the side surface of the first side-wall insulating film intersects the top surface of the first active region, from the top surface of the first contact liner film toward the corner. |
| US07786532B2 |
Structure of a high breakdown voltage element for use in high power application
The relationship between a distance Ls between a base layer and an n type buffer layer formed on the surface of a drift layer and the thickness t of a semiconductor substrate in contact with the drift layer is set to Ls≦t≦2×Ls. A loss upon turn-off of a high breakdown voltage semiconductor device can be reduced without deteriorating breakdown voltage characteristics. |
| US07786525B2 |
Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device includes an element isolation insulating film buried in first trenches, a floating gate electrode formed on an element forming region with a first gate insulating film being interposed between them, and a second gate insulating film formed on upper portions of the floating gate electrode and an element isolation insulating film. The floating gate electrode is formed so as to have a side that extends from a bottom thereof to its upper portion and is substantially an extension of a sidewall of each first trench. The element isolation insulating film includes a portion located between its sidewall and the sidewall of a second trench, and the portion of the element isolation insulating film having a film thickness in a direction along the upper surface of the semiconductor substrate. The film thickness is equal to a film thickness of the second gate insulating film. |
| US07786522B2 |
Method for forming memory cell and device
A memory cell, device, and system include a memory cell having a shared digitline, a storage capacitor, and a plurality of access transistors configured to selectively electrically couple the storage capacitor with the shared digitline. The digitline couples with adjacent memory cells and the plurality of access transistor selects which adjacent memory cell is coupled to the shared digitline. A method of forming the memory cell includes forming a buried digitline in the substrate and a vertical pillar in the substrate immediately adjacent to the buried digitline. A dual gate transistor is formed on the vertical pillar with a first end electrically coupled to the buried digitline and a second end coupled to a storage capacitor formed thereto. |
| US07786521B2 |
Semiconductor device with dielectric structure and method for fabricating the same
A semiconductor device with a dielectric structure and a method for fabricating the same are provided. A capacitor in the semiconductor device includes: a bottom electrode formed on a substrate; a first dielectric layer made of titanium dioxide (TiO2) in rutile phase and formed on the bottom electrode; and an upper electrode formed on the first dielectric layer. |
| US07786520B2 |
Embedded semiconductor device including planarization resistance patterns and method of manufacturing the same
An embedded semiconductor device which a logic region and the memory region are planarized with planarization resistance patterns and a method of manufacturing the same are disclosed. The embedded semiconductor device includes a substrate, gates formed on the substrate, source/drain regions formed on both sides of the gates in the substrate, a first interlayer dielectric (ILD) layer which covers the gates and the source/drain regions, first via plugs which vertically penetrate the first ILD layer and are selectively connected to the source/drain regions, capacitors and second via plugs selectively connected to the first via plugs, a second ILD layer that fills the space between the capacitors and the second via plugs, planarization resistance patterns formed on the second ILD layer, a third ILD layer formed on the second ILD layer and the planarization resistant patterns, and third via plugs which vertically penetrate the third ILD layer, and are selectively connected to a top electrode of the capacitors and the second via plugs. |
| US07786518B2 |
Growth of unfaceted SiGe in MOS transistor fabrication
Semiconductor devices and fabrication methods are provided in which disposable gates are formed over isolation regions. Sidewall structures, including disposable sidewall structures, are formed on sidewalls of the disposable gates. An epitaxially grown silicon germanium is formed in recesses defined by the sidewalls. The process provides a compressive strained channel in the device without faceting of the epitaxially grown silicon germanium. |
| US07786505B1 |
Reduction of charge leakage from a thyristor-based memory cell
Formation of a thyristor-based memory cell is described. A first gate dielectric of the storage element is formed over a base region thereof located in a silicon layer. A transistor is coupled to the storage element via a cathode region located in the silicon layer. The transistor has a gate electrode formed over a second gate dielectric. A spacer is formed at least in part along a sidewall of the gate electrode facing a gate electrode of the storage element. A shallow implant region is formed in the silicon layer responsive at least in part to the spacer. The spacer offsets the shallow implant region from the sidewall. A portion of the shallow implant region is for an extension region. The first gate dielectric and the second gate dielectric are formed at least in part by deposition of a dielectric material. |
| US07786502B2 |
Nitride semiconductor light-emitting device and method of manufacturing the same
A nitride semiconductor light-emitting device includes, a support substrate 170; a nitride semiconductor layer 100 which includes a p-type nitride semiconductor layer 140 formed on the support substrate 170, an MQW active layer 130 formed on the p-type nitride semiconductor layer 140, and an n-type nitride semiconductor layer 120 formed on the MQW active layer 130; a contact electrode 161 formed on the n-type nitride semiconductor layer 120; a second transparent electrode 165 having an optical transparency and formed on the contact electrode 161; and a second pad electrode 166 formed on the support substrate 170 and electrically connected to the second transparent electrode 165, wherein, on a projection plane S parallel to a main surface of the MQW active layer 130, a region on which the MQW active layer 130 is projected and a region on which the second pad electrode 166 is projected are not overlapped. |
| US07786501B2 |
Fabricating process and structure of thermal enhanced substrate
A fabricating process of a thermal enhanced substrate is provided for fabricating thermal conduction blocks to increase the heat dissipation area. First, a metallic substrate having a first surface and a second surface opposite to the first surface is provided. A first shallow trench with a first depth is then formed on the first surface. A second shallow trench with a second depth is formed on the second surface, and a deep trench penetrating the first shallow trench and the second shallow trench is formed, where the metallic substrate is separated into many thermal conduction blocks by the deep trench. At least one metallic layer and at least one insulating material are laminated on the thermal conduction blocks, and the insulating material is filled into the deep trench and covers the thermal conduction blocks. |
| US07786498B2 |
Light emitting device and package having the same
There is provided a light emitting device that can minimize reflection or absorption of emitted light, maximize luminous efficiency with the maximum light emitting area, enable uniform current spreading with a small area electrode, and enable mass production at low cost with high reliability and high quality. A light emitting device according to an aspect of the invention includes a light emitting lamination including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer, and a conductive substrate at one surface thereof. Here, the light emitting device includes a barrier unit separating the light emitting lamination into a plurality of light emitting regions, a first electrode structure, and a second electrode structure. The first electrode structure includes a bonding unit, contact holes, and a wiring unit connecting the bonding unit to the contact holes. |
| US07786497B2 |
Pixel structure of LCD and fabrication method thereof
In this pixel structure, a metal layer/a dielectric layer/a heavily doped silicon layer constitutes a bottom electrode/a capacitor dielectric layer/a top electrode of a storage capacitor. At the same time, a metal shielding layer is formed under the thin film transistor to decrease photo-leakage-current. |
| US07786493B2 |
Light emitting diode, method for manufacturing light emitting diode, integrated light emitting diode, method for manufacturing integrated light emitting diode, light emitting diode backlight, light emitting diode illumination device, light emitting diode display, electronic apparatus, electronic device, and method for manufacturing electronic device
Disclosed herein is a light emitting diode includes: a first semiconductor layer of a first conductivity type; an active layer on the first semiconductor layer; a second semiconductor layer of a second conductivity type on the active layer; a first electrode configured to be electrically coupled to the first semiconductor layer; and a second electrode configured to be provided on the second semiconductor layer and be electrically coupled to the second semiconductor layer, the second electrode including a first metal film that has a predetermined shape and is composed mainly of silver and a second metal film that covers the first metal film and is composed mainly of palladium and/or platinum. |
| US07786491B2 |
Semiconductor light-emitting device comprising a plurality of semiconductor layers
A semiconductor light-emitting device includes: a substrate; a plurality of semiconductor layers grown on the substrate and including an active layer; and an electrode formed on the semiconductor layers. An opening in which at least a portion of the semiconductor layers is exposed is formed in the substrate. The electrode faces the opening in the substrate and a portion of the substrate surrounding the opening. |
| US07786487B2 |
Semiconductor device and manufacturing method thereof
Disclosed is a semiconductor device including a SiC substrate and a heat conductor formed in a hole in the SiC substrate and made of a linear structure of carbon elements. |
| US07786486B2 |
Double-sided package for power module
An electronic semiconductor package is described. The package has a wide band gap electronic semiconductor device requiring heat removal. On one side of the electronic semiconductor device is a first, thermally-conductive, electrically-insulative substrate having a predetermined electrically-conductive wire pattern affixed thereto. On the other side of the electronic semiconductor device is a second, thermally-conductive, electrically-insulative substrate. A heat removal device is mechanically-coupled to the second substrate. The heat removal device is made of a graphite-metal or metal-matrix composite material and a fin array structure of the same material. The coefficients of thermal expansion of the heat removal device and the first and second substrates are matched to minimize internal and external stresses. |
| US07786485B2 |
Thin-film transistor and display device
A thin-film transistor includes a pair of impurity semiconductor layers in which an impurity element imparting one conductivity type is added to form a source and drain regions so as to be overlapped at least partly with a gate electrode with a gate insulating layer interposed between the gate electrode and the impurity semiconductor layers; a pair of conductive layers which is overlapped over the gate insulating layers at least partly with the gate electrode and the impurity semiconductor layers, and is disposed with a space therebetween in a channel length direction; and an amorphous semiconductor layer which is in contact with the gate insulating layer and the pair of conductive layers and is extended between the pair of conductive layers. |
| US07786476B2 |
Semiconductor device system and method for modifying a semiconductor device
A semiconductor device system and a method for modifying a semiconductor device is disclosed. In one embodiment, a function provided by a circuit positioned on the semiconductor device is replaced, modified, and/or supplemented by a function provided by a circuit positioned on a further semiconductor device. |
| US07786471B2 |
Organic electroluminescence device
The present invention relates to an organic electroluminescence device comprising a substrate, an anode, a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, an electron injection layer, and a cathode, wherein the electron injection layer contains alkali metal nitride and has a thickness of 0.2-10 nm. The organic electroluminescence device of the present invention has improved electron injection from the cathode to the organic layer, high device luminance and efficiency, long device lifetime, low material poisonousness, wide choice of film-forming thickness and low film-forming temperature. |
| US07786470B2 |
Switching element
The present invention provides a switching element that has a stable bistable characteristic and a high transition voltage and demonstrates excellent cyclic performance. The switching element has two stable resistance values with respect to the voltage applied between electrodes, wherein a first electrode layer, an organic bistable material layer, and a second electrode layer are successively formed as thin films on a substrate and the organic bistable material constituting the organic bistable material layer is a quinomethane-based compound or a monoquinomethane-based compound. A metal constituting the second electrode layer is diffused into the organic bistable material layer. It is preferred that the second electrode layer be formed by vapor deposition and the temperature of the substrate during the vapor deposition be 30-150° C. |
| US07786458B2 |
Image reading method and apparatus
An image reading method and apparatus for reading an image signal by exposure to reading light L2 from a radiation solid-state detector, where radiation image information is recorded by exposure to recording light L1, suppresses degradation of image quality such as the S/N ratio of a reproduced image, the degradation being caused by an effect of charges which are produced by exposure to excessive radiation or the like and remains in the radiation solid-state detector. In the image reading method and apparatus, a past image signal read regarding past image information recorded in the radiation solid-state detector in the past, and an elapsed time from a time of recording the past image information in the radiation solid-state detector to a time of recording the current radiation image information are stored. The current image signal is then corrected based on the recorded past image information and the elapsed time. |
| US07786457B2 |
Systems and methods of non-invasive level sensing for a surgical cassette
Embodiments of the present invention provide a system and method for detecting the level of a fluid in a surgical cassette by projecting light from a linear light source into a wall of a cassette. Depending on the amount a light reflected or refracted in the cassette (i.e., due to the cassette material/fluid interface or cassette material/air interface (or other interface)) various portions of a linear sensor array will be more or less illuminated. By examining the illumination of the linear sensor array, the level of fluid in the chamber can be determined. |
| US07786456B2 |
Apparatus for providing additional radiation shielding to a container holding radioactive materials, and method of using the same to handle and/or process radioactive materials
A system, method and apparatus for providing additional radiation shielding to a container holding radioactive materials. The invention utilizes a sleeve-like structure that is slid over a container holding high level radioactive materials to add radiation shielding protection. Because the sleeve-like structure and container are non-unitary and slidably separable from one another, crane lifting capacity is not affected. In one aspect, the invention is an apparatus comprising: a tubular shell constructed of a gamma radiation absorbing material and having an inner surface that forms a cavity having an axis, the cavity having an open top end and an open bottom end; a plurality of spacers extending from the inner surface of the shell toward the axis of the cavity, the spacers extending a first height from the inner surface of the tubular shell; and one or more flange members located at or near the open top end of the cavity extending from the tubular shell toward the axis of the cavity, the flange member extending a second height from the inner surface of the shell, the second height being greater than the first height. |
| US07786455B2 |
Laser-driven light source
An apparatus for producing light includes a chamber and an ignition source that ionizes a gas within the chamber. The apparatus also includes at least one laser that provides energy to the ionized gas within the chamber to produce a high brightness light. The laser can provide a substantially continuous amount of energy to the ionized gas to generate a substantially continuous high brightness light. |
| US07786451B2 |
Ion sources, systems and methods
Ion sources, systems and methods are disclosed. |
| US07786447B2 |
Scintillator panel, method of manufacturing the same and radiation imaging apparatus
A scintillator panel comprising: a radiation-transparent substrate; and a phosphor layer provided on the substrate, the phosphor layer emitting light when irradiated with a radiation, wherein at least one edge of the substrate and at least one edge of the phosphor layer are arranged on a same plane. |
| US07786446B2 |
Radiation detector
An extended electrode is electrically connected to a conductor in a portion outside of an inner wall of a protection member disposed on a photoconductive layer side, the pressure applied to the photoconductive layer is reduced and the deterioration of the photoconductive layer may be suppressed. Further, since the extended electrode is electrically connected to a high-voltage wire in a portion outside of the inner wall of the protection member, the extended electrode may be connected to the high-voltage wire in the state that the photoconductive layer is surrounded by the protection member. As a result, deterioration of the photoconductive layer may be suppressed even while a connection work is performed. |
| US07786440B2 |
Nanowire multispectral imaging array
A multispectral imaging array system and method of forming the same. A substrate and a group of antennas can be located with respect to one another on the substrate, such that respective gaps are formed between each antenna group and wherein different antenna sizes may be used for different spectral ranges. Additionally, one or more nanowires can be located within one or more gaps among the respective gaps, such that the nanowires in communication with the antennas and the substrate comprise a multispectral imaging system in which the use of the nanowire(s) decreases the thermal time constant and therefore the read out rate from the antennas while decreasing the ambient gas cooling speed relative to the read out rate to increase the manufacturability of the multispectral imaging array system. |
| US07786439B2 |
Detector apparatus
A detector apparatus is disclosed. In one embodiment, the detector apparatus includes i) a radiation detector configured to generate an analog signal representative of radiation incident upon the radiation detector and ii) an analog-to-digital converter configured to convert the analog signal to a corresponding digital signal, wherein the radiation detector and the analog-to-digital converter are both housed in a common temperature-controlled housing. |
| US07786438B1 |
Sensor assemblies using redundant two-dimensional detector arrays
A sensor assembly that replaces a single focal plane array detector with two focal plane array detectors orientated with respect to each other such that a power splitter divides an incoming light source equally between each detector. The two detectors are selected such that the locations of poorly-operating pixels in each detector do not overlay. The output signals of each detector are then electronically or analytically combined to yield 100 percent operability. Separate switchable wavelength filter wheels having one or more different wavelength filters may be positioned between the power splitter and each of the detectors. The power splitter may be replaced by a polarization splitter. One detector can be translated perpendicular to the incoming light source relative to the second detector to compensate for new poorly-operating pixels and/or to improve the spatial resolution. |
| US07786437B2 |
Pattern inspection method and pattern inspection system
A pattern data examination method and system capable of accurately and speedily examining a circuit pattern without failing to extract pattern contour data are provided. While pattern comparison is ordinarily made by using a secondary electron image, a contour of a pattern element is extracted by using a backscattered electron image said to be suitable for observation and examination of a three dimensional configuration of a pattern element, and pattern inspection is executed by using the extracted contour of the pattern element. More specifically, pattern inspection is executed by comparing a contour of a pattern element with design data such as CAD data to measure a difference between the contour and the data, and by computing, for example, the size of the circuit pattern element from the contour of a pattern. From two or more backscattered electron images formed by detecting backscattered electrons at two or more different spatial positions, pattern contour data contained in the backscattered electron images may be obtained. |
| US07786435B2 |
RF surfaces and RF ion guides
Apparatus and methods are provided for trapping, manipulation and transferring ions along RF and DC potential surfaces and through RF ion guides potential wells are formed near RF-field generating surfaces due to the overlap of the radio-frequency (RF) fields and electrostatic fields created by static potentials applied to surrounding electrodes. Ions can be constrained and accumulated over time in such wells During confinement, ions may be subjected to various processes, such as accumulation, fragmentation, collisional cooling, focusing, mass-to-charge filtering, spatial separation ion mobility and chemical interactions, leading to improved performance in subsequent processing and analysis steps, such as mass analysis. Alternatively, the motion of ions may be better manipulated during confinement to improve the efficiency of their transport to specific locations, such as an entrance aperture into vacuum from atmospheric pressure or into a subsequent vacuum stage. |
| US07786434B2 |
Microengineered vacuum interface for an ionization system
The invention provides a planar component for interfacing an atmospheric pressure ionizer to a vacuum system. The component combines electrostatic optics and skimmers with an internal chamber that can be filled with a gas at a prescribed pressure and is fabricated by lithography, etching and bonding of silicon. |
| US07786432B2 |
Apparatus and method for changing optical tweezers
An apparatus and a method for changing optical tweezers are provided. The apparatus includes a diffractive optical element (DOE), a mask unit and an objective lens. The DOE includes a plurality of phase delay patterns. The mask unit includes a plurality of mask patterns that correspond to the phase delay patterns, respectively, wherein at least a portion of the mask patterns are complementary. A laser beam passing through each phase diffractive pattern correspondingly passes through each mask pattern to generate a compound diffractive pattern. The objective lens receives the compound diffractive pattern and focuses it on an examining object to form an optical tweezers. |
| US07786425B2 |
Optical sensor
An optical sensor for a touch-sensitive push button of a control mechanism for an electronic household appliance has a transmitter, which emits electromagnetic radiation, and a receiver, which receives reflected electromagnetic radiation. A cover is at least partly transparent to the electromagnetic radiation and the transmitter and the receiver are arranged behind the cover. A radiation guide mechanism, for example a diaphragm frame, is provided between the transmitter and the receiver, on the one hand, and the cover, on the other hand, for guiding the radiation emitted from the transmitter towards the cover and to guide the reflected radiation penetrating the cover to the receiver. The diaphragm frame broadens the emission characteristic of the transmitter outward from the cover and/or the reception characteristic of the receiver inward into the cover. Additionally or alternatively, the emission characteristic outward from the cover is inclined in the direction of the reception characteristic of the receiver into the cover and/or the reception characteristic of the receiver into the cover is inclined in the direction of the emission characteristic of the transmitter out from the cover. This moves the range of intersection between emission and reception characteristic closer to the cover, so that the signal-to-noise ratio of the optical sensor is reduced. |
| US07786423B2 |
Image sensor and method for manufacturing the same
An image sensor is disclosed that can provide a microlens aligned directly above an active area of a substrate. The image sensor can include a substrate having a pixel area. An active region can be formed on the pixel area and can include photodiodes. Metal lines and an interlayer dielectric can be provided on the pixel area of the substrate. A microlens can be formed above the metal lines and interlayer dielectric to be directly aligned with the active area of the pixel area. To achieve such an alignment, an alignment key of the microlens can be aligned with an alignment key of the active region. In one embodiment, the microlens can avoid being formed right above the metal lines. |
| US07786417B2 |
RAM neutralization system and method
An article for neutralizing an enemy weapon comprising an interceptor and a deployable net attached to the interceptor, said deployable net remaining attached to the interceptor upon deployment, is disclosed. A method of neutralizing an airborne enemy weapon comprising launching an interceptor, with a capture sock, towards the enemy weapon and deploying the capture sock just prior to the interceptor encountering the enemy weapon is also disclosed. The capture sock remains attached to the interceptor upon deployment. |
| US07786415B2 |
Induction heating system having multiple temperature input control
A system and method for inductively heating a work piece. The induction heating system is coupleable to a plurality of temperature feedback devices operable to provide a signal representative of work piece temperature. The induction heating system is operable to control the output of the induction heating system based on the plurality of signals representative of work piece temperature received from the plurality of temperature feedback devices. |
| US07786414B2 |
Induction heating device and hob having such an induction heating device
An induction heating device for a glass ceramic hob or cooktop is embodied as an autonomous component. Said induction heating device comprises a bearing device which, in addition to the induction coil, supports a component support comprising power electronics and control electronics. Only the control connections for the control signals in relation to the power of a line and a direct connection to the household power are provided on said induction heating device. The control electronics ensure the power of a line to the power electronics. Advantageously, said induction heating devices have external dimensions which are the same as traditional radiant heating bodies and thus can easily be used in lieu of said traditional radiant heating bodies when constructing said hob. |
| US07786411B2 |
Heated computer mouse
A heated mouse includes a shell having a heat-conductive part, a heating device installed in the shell, and an insulating layer. The heating device comprises a heat source. The insulating layer forms a closed space together with the heat-conductive part for accommodating the heat source therein. The heat-conductive part absorbs heat from the heat source. The heat-preserving mouse can not only heat the mouse, but also avoid reducing the lifespan of the mouse caused by overheat. |
| US07786409B2 |
Igniter shields
New igniter systems are provided that comprise a ceramic igniter element and an affixed encasing shield element. The shield element may be engaged or affixed to the igniter element in a variety of configurations, including by direct attachment to the igniter element or through another structure interposed between the igniter and shield elements. In preferred systems, a proximal end of an igniter element may be engaged in a mounting structure and a shield element that encases the igniter element is affixed to the mounting structure. |
| US07786408B2 |
Bus bar interfaces for flexible heating elements
A flexible heating subassembly, which may be incorporated in an electric warming blanket or any other type of flexible heater, includes a single heater, which is preferably formed from an electrically conductive polymeric fabric. The subassembly further includes first and second conductive bus bars, each extending alongside a respective first and second edge of the heater, each being coupled to the heater by at least one row of stitching that extends along the respective bus bar. The edges of the heater may be folded over respective bus bars for coupling and each of the bus bars may terminate just beyond opposing ends of the heater. A ribbon of conductive material may be interposed between each of the bus bars and the heater. |
| US07786407B2 |
Process for capillary electric welding of low and high alloy steels, hardened or not, and bimetals, for the obtainment of a determined texture, without thermal treatment
Patent of Invention for PROCESS CAPILLARY ELECTRIC WELDING OF LOW AND HIGH ALLOY STEELS, HARDENED OR NOT, AND BI-METALS, FOR THE OBTAINMENT OF A DETERMINED TEXTURE, WITHOUT THERMAL TREATMENT, in which the first layer (1) is used to line the bevel and its root with electrodes of crystallization of the deposited welding material, said weld being adequate for the obtainment of the austenitic plus ferretic texture. With the second layer (2), proceed with the filling of the bevel with the crystallization of the deposited weld, obtaining a perlitic or pearlitic plus troostitic texture, while in the third and fifth layers (3, 5), the electrode for the obtainment of an austenitic plus ferritic texture. In the fourth layer (4), the electrode of deposited weld crystallization for the obtainment of a sorbitic plus bainitic texture is used, and in the sixth layer (6), an electrode for deposited weld crystallization for the obtainment of a bainitic texture is used. |
| US07786406B2 |
Laser stent cutting
A stent may be manufactured by providing a tube having a longitudinal axis therethrough, providing a stationary source of laser radiation, generating a beam of laser radiation using the source of laser radiation, and cutting a desired pattern into the tube by scanning the beam over a desired region of the tube. |
| US07786402B2 |
Nanospot welder and method
A method and apparatus for assembly of small structures is disclosed. The present invention discloses electron beams created from one or more nanotips in an array operated in a field emission mode that can be controlled to apply heat to very well defined spots. The multiple electron beams may be generated and deflected and applied to electron beam heating and welding applications. |
| US07786390B2 |
Printed wiring board and a method of production thereof
A printed wiring board has an insulating resin substrate having a first surface and a second surface, the insulating resin substrate having one or more penetrating-holes passing through the insulating resin substrate from the first surface to the second surface, a first conductor formed on the first surface of the insulating resin substrate, a second conductor formed on the second surface of the insulating resin substrate, and a through-hole conductor structure formed in the penetrating-hole of the insulating resin substrate and electrically connecting the first conductor and the second conductor. The penetrating-hole has a first portion having an opening on the first surface and a second portion having an opening on the second surface. The first portion and the second portion are connected such that the first portion and the second portion are set off from each other. |
| US07786389B2 |
Flexible printed wiring board
A flexible printed wiring board includes a first conductor layer in the element mounting part adjacent to the top surface of the wiring board; a second conductor layer in the element mounting part adjacent to the bottom surface of the wiring board; and a third conductor layer between the first conductor layer and the second conductor layer, wherein the first and third conductor layers extend through and beyond the bending part, and the second conductor layer is absent in the bending part. |
| US07786387B2 |
Composite electrical conductor and method for producing it
An electrical composite conductor includes a CuAg alloy base having an Ag content of 0.08 to 0.12% and a CuMg alloy having a Mg content of 0.1 to 0.7%. The composite conductor further includes a conductor edge and a conductor core, wherein at least one of the edge and the core include the CuMg alloy. |
| US07786380B2 |
Wall plate with a multiple flexible member covered opening
The present disclosure is a wall plate with a multiple flexible member covered opening. A wall plate with a multiple flexible member covered opening may allow for multiple types of wires to run through the same wall box and wall plate. Wall plate may be designed to directly attach to a standard single gang wall box for an easy installation. Wall plate may include multiple flexible members that may allow cables to enter and exit through the flexible members while covering an opening defined by a frame of the wall plate to provide a finished appearance. |
| US07786379B1 |
Method for attaching an electrical fixture to a junction box
A mounting assembly for connecting a housing of an electrical fixture to an electrical junction box, in which a plate attached to the housing includes a locking member having an engager at a first end moveable relative to the plate between a first position and a second position. A locking post adapted for connecting to an electrical junction box includes a receiver for engaging the engager. The locking post secures the housing to the electrical junction box upon moving the locking member to the second position to engage the engager with the receiver of the locking post. A method of attaching a housing for an electrical fixture to an electrical junction box is disclosed. |
| US07786378B2 |
Electric wire for automobile
A conductor for an automobile is provided. The conductor is configured by compressing a plurality of surrounding wires that surround a central wire. Individual wires of single materials are combined in various combinations. Materials from which individual wires are formed in one embodiment are one of stainless steel, copper or copper alloy. Materials from which individual wires are formed in another embodiment are one of stainless steel, aluminum or aluminum alloy. |
| US07786373B2 |
Device and method for automatically tuning a stringed instrument, particularly a guitar
A device for automatically tuning a stringed instrument, particularly a guitar, comprising: a detecting device for detecting a note produced by strumming a string and for outputting a digital signal corresponding to the detected note; a memory device for storing default digital signals corresponding to a desired note; a comparator for comparing the digital signal output by the detecting device with a digital signal, which is stored in the memory device and which corresponds to the desired note; an adjusting device for altering the tension of the strings; at least one drive for driving the adjusting device, and; a controller, which is connected to the comparator and which controls the at least one drive via a bus line based on a difference between the signals representing the produced note and the desired note, this difference being determined in the comparator. The inventive device is improved compared to that of the prior art by virtue of the fact that it can be integrated in an instrument, particularly a guitar, while having a minimal influence upon the sound characteristics and with as few as possible elements that are also small. To this end, the controller and the at least one drive are placed inside the stringed instrument while being situated, when viewing in a longitudinal of the strings, on opposite sides of the strings, and the bus line is led between the controller and the at least one drive while spanning the length of the strings. The invention also relates to a method for automatically tuning a stringed instrument. |
| US07786367B2 |
Music player connection system for enhanced playlist selection
A system compiles a music playlist to accommodate the tastes of various participants in a group setting. A music profile is created for each participant, the profile containing representations of songs that are characteristic of the participant's tastes. A master device may then compile a “super profile” that constitutes a compilation of the various participant profiles. Each participant device may then access the super profile and search among its specific song collection to find music that is similar to one or more songs represented in the super profile. From such songs, the master device may compile a playlist of songs that are similar among the participant devices, thereby representing the songs that correspond to the collective musical tastes of the participants. The playlist may be updated as participants enter and leave the group to track the changing collective tastes of the participants. |
| US07786361B1 |
Wood on graphite layup instruments
A wood on graphite layup instrument includes a soundboard, reinforced bridge, and neck made of reinforced plies of graphite fibers. The outer surface of the instrument is adorned with a wood veneer for a finished look that resembles a traditional instrument, such as a guitar. |
| US07786360B2 |
Rice cultivar designated ‘CL131’
A novel rice cultivar, designated ‘CL131,’ is disclosed. The invention relates to the seeds of rice cultivar ‘CL131,’ to the plants of rice ‘CL131,’ and to methods for producing a rice plant produced by crossing the cultivar ‘CL131’ with itself or another rice variety, and to single gene conversions of such plants. The invention further relates to hybrid rice seeds and plants produced by crossing the cultivar ‘CL131’ with another rice cultivar. The invention further relates to other derivatives of the cultivar ‘CL131.’ |
| US07786349B2 |
Methods and means for increasing the tolerance of plants to stress conditions
Methods and means are provided to increase the tolerance of plants to abiotic stress or adverse growing conditions, including drought, high light intensities, high temperatures, nutrient limitations and the like by reducing the activity of endogenous PARG proteins in plants. |
| US07786348B2 |
Methods for producing pathogen-resistant plants with allene oxide synthase and divinyl ether synthase, and the amino acid and nucleotide sequences thereof
The present invention relates to enzymes from the cytochrome P450 family and to the nucleotide sequences encoding them, and to their use in a method for the generation of pathogen-resistant plants. |
| US07786347B2 |
Inhibitor of apoptosis proteins and nucleic acids and methods for making and using them
The invention provides polypeptides comprising inhibitor of apoptosis protein (IAP) family members, such as BmIAP initially derived from Bombyx mori BmN cells, and nucleic acids encoding them, and methods for making and using these compositions, including their use for inhibiting apoptosis. |
| US07786346B2 |
Generation of plants with improved drought tolerance
The present invention is directed to plants that display a pathogen resistance and increased drought tolerance phenotype due to altered expression of a PRDT1 nucleic acid. The invention is further directed to methods of generating plants with a pathogen resistance and increased drought tolerance phenotype. |
| US07786343B2 |
Transgenic plants expressing recombinant barley alanine aminotransferase
Transgenic plants containing recombinant barley alanine aminotransferase are described. Also provided are methods for generating transgenic plants containing recombinant barley alanine aminotransferase. |
| US07786342B2 |
Double flower Calibrachoa breeding methods and plants produced therefrom
A method for breeding double flower Calibrachoa sp. plants using controlled crosses of selected parent plants is disclosed. The invention additionally relates to methods for breeding double flower Calibrachoa plants using anther culture and induced mutation techniques. Finally, the invention relates to new Calibrachoa plants produced by the described methods and characterized by their unique double flowers. |
| US07786340B2 |
Dark colored absorbent articles with loading indicator
An absorbent article for absorbing liquid, typically body liquid, with a loading indicator, said article includes a dark topsheet having an L Hunter value of less than 60, preferably being black, an underlying layer comprising a light layer having an L Hunter value of 60 or more and a backsheet, all layers being coextensive to have a common peripheral edge. By this execution the light layer is noticeable along the peripheral edge of the article, thereby providing said loading indicator by changing color to the color of the absorbed liquid. |
| US07786338B2 |
Selective oligomerization of isobutene
A process for oligomerizing isobutene includes contacting a feedstock including isobutene with a catalyst comprising an EMM-10 molecular sieve under conditions effective to oligomerize said isobutene and produce an effluent containing less isobutene than the feedstock. |
| US07786335B2 |
Method for preparing 1,1,1,3,3-pentafluoropropane
A process for the production of C2-C4 hydrofluorocarbon, such as 1,1,1,3,3-pentafluoropropane, by contacting a non-fluorinated hydrochlorocarbon with a fluorinating agent, such as hydrogen fluoride, in a liquid catalyst system preferably comprising fluorinated superacid catalyst prepared from SbF5, NbF5, TaF5 or TaF5/SnF4 and HF. |
| US07786323B2 |
Method for collecting (meth)acrolein or (meth)acrylic acid and collecting device for the same
(Meth)acrolein or (meth)acrylic acid is collected by bringing a reaction gas (1) containing (meth)acrolein or (meth)acrylic acid obtained through a vapor-phase catalytic oxidation reaction into contact with an aqueous solution as a collecting solvent in a collecting tower main body (2). The reaction gas (1) is supplied to the collecting tower main body (2) from two nozzles (2c) facing each other, and is caused to collide in the collecting tower main body (2). According to the present invention, (meth)acrolein or (meth)acrylic acid can be efficiently collected from a gas containing (meth)acrolein or (meth)acrylic acid while preventing polymerization. |
| US07786321B2 |
Compounds of the N-acylamino amide family compositions comprising them and uses thereof
The invention concerns novel compounds of the N-acylamino-amide family, compositions, in particular cosmetic or pharmaceutical, containing them, and their use for treating body or face skin ageing, whether chronobiologic or light-induced, and in particular skin ageing caused by decrease of skin elasticity and/or by collagen degradation in the structure for tissues. |
| US07786320B2 |
Composition and method for low temperature deposition of silicon-containing films such as films including silicon, silicon nitride, silicon dioxide and/or silicon-oxynitride
Silicon precursors for forming silicon-containing films in the manufacture of semiconductor devices, such as low dielectric constant (k) thin films, high k gate silicates, low temperature silicon epitaxial films, and films containing silicon nitride (Si3N4), siliconoxynitride (SiOxNy) and/or silicon dioxide (SiO2). The precursors of the invention are amenable to use in low temperature (e.g., <500° C.) chemical vapor deposition processes, for fabrication of ULSI devices and device structures. |
| US07786319B2 |
Asymmetric cationic surfactants
A process for preparing esterquats with asymmetric side chains, including the steps of: (a) reacting one or more alkanolamines with a mixture, including: (i) 30:70% b.w. of one or more C6-C10 monocarboxylic acids, and (ii) 70:30% b.w. of one or more C12-C22 monocarboxylic acids, and (b) quaternizing the resulting esters with one or more alkylation agents is provided.A process for preparing esterquats with asymmetric side chains, including the steps of: esterifying a mixture of carboxylic acids with one or more alkanolamines to form a mixture of mono-, di- and trialkanolamine esters, where the mixture of carboxylic acids comprises (i) 30:70% b.w. of one or more C6-C10 monocarboxylic acids, and (ii) 70:30% b.w. of one or more C12-C22 monocarboxylic acids; and quaternizing the esters with one or more alkylation agents is also provided. |
| US07786318B2 |
Catalyst preparation
Titanium silicallite crystals useful as catalyst for the production of propylene oxide are prepared by forming a solution of a silicon component, a titanium component and a template, the mol ratio of template to silicon component being 0.25 or less and heating the solution to reaction temperature at a rate not to exceed 0.3° C./min. |
| US07786316B2 |
Metalloprotein inhibitors
The present invention relates to metalloprotein inhibitors comprising: a. an organic substituent and at least one zinc binding group (ZBG) covalently attached thereto; or b. a ZBG substituted by a side chain wherein the ZBG is of formula (I): wherein X is O or S and each R1, R2, R3, and R4 is individually hydrogen or an organic radical. The metalloprotein inhibitors are useful for preventing or treating a pathological disease, condition, or symptom that is associated with pathological metalloprotein activity and/or that is alleviated by inhibition of said activity. |
| US07786314B2 |
Processes for preparing bicyclo [3.1.0] hexane derivatives, and intermediates thereto
Processes for the preparation of certain [3.1.0]hexane derivatives which are useful as mGluR agonists, and intermediates prepared during such processes. |
| US07786312B2 |
Methods of preparing heterocyclic boronic acids and derivatives thereof
In the context of synthesizing heterocyclic boronic acid compounds, a convergent synthetic methodology is particularly efficient for preparing boropyrrolidines and derivatives of boropyrrolidines. |
| US07786308B2 |
Muscarinic modulators
The present invention relates to modulators of muscarinic receptors. The present invention also provides compositions comprising such modulators, and methods therewith for treating muscarinic receptor mediated diseases. |
| US07786304B2 |
Process for the preparation of eszopiclone
The invention relates to a process for making 6-(5-chloro-2-pyridinyl)-6,7-dihydro-7-oxo-5H-pyrrolo-[3,4-b]pyrazin-5-yl-4-methyl piperazine-1-carboxylate, also known as zopiclone. The invention further describes an effective method for resolving zopiclone into its enantiomers (eszopiclone and (R)-zopiclone) and also provides a method of recycling of (R)-zopiclone. The process for making (S)-6(S)-6-(5-chloro-2-pyridinyl)-6,7-dihydro-7-oxo-5H-pyrrolo-[3,4-b]pyrazin-5-yl-4-methyl piperazine-1-carboxylate (eszopiclone), comprises reacting 2-amino 5-chloropyridine with pyrazine 2,3,dicarboxylic acid anhydride at room temperature to obtain 3-(5-chloropyrid-2-yl)carbamoyl-2-pyrazine-2-carboxylic acid; cyclizing the 3-(5-chloropyrid-2-yl)carbamoyl-2-pyrazine-2-carboxylic acid in a second inert organic solvent to obtain 6-(5-chloropyrid-2-yl)5,7-dioxo-5,6-dihydropyrrolo[3,4-b]-pyrazine; reducing the 6-(5-chloropyrid-2-yl)5,7-dioxo-5,6-dihydropyrrolo[3,4-b]-pyrazine to obtain 6-(5-chloropyrid-2-yl)-5-hydroxy-7-oxo-5,6-dihydropyrrolo-[3,4-b]pyrazine; pyrazine with 1-chlorocarbonyl-4-methylpiperazine hydrochloride in a third organic solvent in presence of triethyl amine along with a catalytic amount of an acylation catalyst to obtain racemic zopiclone; e) recrystallizing the zopiclone from an alkyl ester solvent followed by purifying in suitable alcohols or mixtures thereof; and resolving the racemic zopiclone by treating with (+)-O—O′ dibenzoyl tartaric acid to obtain eszopiclone. |
| US07786301B2 |
Process for preparing xanthine phosphodiesterase V inhibitors and precursors thereof
A process for preparing xanthine phosphodiesterase V inhibitors, and compounds utilized in said process. The process includes a five-step methodology for efficient synthesis of Compound 5 without intermediate purifications or separations, a dihalogenation step to synthesize Compound 7, and a coupling reaction to produce Compound 9. |
| US07786299B2 |
Methods for treating diseases or conditions using dihydropteridinone compounds
Disclosed are new dihydropteridinones of general formula (I) wherein the groups L and R1-R5 have the meanings given in the claims and specification, the isomers thereof, intermediates and processes for preparing these dihydropteridinones and the use thereof as pharmaceutical compositions. |
| US07786297B2 |
Purified form of tanaproget
Micronized tanaproget, purified tanaproget Form I, and micronized, purified tanaproget Form I are provided. Also provided are compositions containing one or more of the prepared tanaproget forms, methods of using one or more of the prepared tanaproget forms, and kits containing one or more of the prepared tanaproget forms. |
| US07786295B2 |
Method to isolate DNA
An improved method for isolating DNA from biological samples is provided. |
| US07786291B2 |
Compositions and methods for short interfering nucleic acid inhibition of Nav1.8
The invention provides short interfering nucleic acids, either single-stranded or double-stranded, that cause RNAi-induced degradation of mRNA from the Nav1.8 sodium channel gene; to pharmaceutical compositions comprising such short interfering nucleic acids; recombinant vectors comprising such short interfering nucleic acids; a method for inhibiting translation of an mRNA; a method for inhibiting expression of a polypeptide; a method for blocking the membrane potential in a cell; a method for blocking the sodium current in a cell; and a method for inhibiting chronic pain. |
| US07786288B2 |
Immunizing compositions encoding an epitope obtained from the HIV-1 capsid protein cyclophilin A binding site
The present invention relates to an immunogenic composition. More particularly, the present invention is a composition directed to eliciting an immune response to at least one binding site of Cyclophilin A on the HIV capsid protein. (SEQ ID NOS: 2, 4, and 6) The present invention contemplates three categories of embodiments: protein or protein fragments (SEQ ID NOS: 2, 4, and 6), messenger RNA, or DNA/RNA. DNA/RNA compositions (SEQ ID NOS 1, 3, 5, 7, 9, and 11) may be either naked or recombinant. The present invention further contemplates use with a variety of immune stimulants. |
| US07786281B2 |
Protein-deamidating enzyme, microorganism producing the same, gene encoding the same, production process therefor, and use thereof
A method for the production of an enzyme, which comprises culturing in a medium a strain that belongs to a bacterium classified into Cytophagales or Actinomycetes, or a new bacterium Chryseobacterium sp. No. 9670 belonging to the genus Chryseobacterium, and has the ability to produce an enzyme having a property to deamidate amido groups in protein, thereby effecting production of the enzyme, and subsequently collecting the enzyme from the culture mixture and a method for the modification of protein making use of a novel enzyme which directly acts upon amido groups in protein, as well as a gene which encodes the enzyme, a recombinant vector which contains the gene, a transformant transformed with the vector and a method in which the transformant is cultured in a medium to effect production of the protein-deamidating enzyme and then the protein-deamidating enzyme is collected from the culture mixture. It is possible to provide a novel protein-deamidating enzyme which has an activity to release side chain carboxyl groups and ammonia from a protein by acting upon side chain amido groups in the protein, a microorganism capable of producing the same, a gene encoding the same, a production process therefor and use thereof. |
| US07786280B1 |
Isolated genomic polynucleotide fragments from chromosome 10q25.3 that encode human soluble aminopeptidase P
The invention is directed to an isolated genomic polynucleotide fragment that encodes human soluble (cytosolic) aminopeptidase P, vectors and hosts containing the fragment and fragments hybridizing to noncoding regions as well as antisense oligonucleotides to these fragments. The invention is further directed to methods of using these fragments to obtain human soluble aminopeptidase P and to diagnose, treat, prevent and/or ameliorate a pathological disorder. |
| US07786279B2 |
Nucleic acid molecules, polypeptides, antibodies and compositions for treating and detecting influenza virus infection
Polynucleotides and polypeptides which participate in influenza virus infection of cells and nucleic acid molecules, which include a polynucleotide sequence capable of specifically binding the polypeptides of the present invention. Also provided are methods of using such nucleic acid molecules, polynucleotides and antibodies directed thereagainst for diagnosing, treating and preventing influenza virus infection. |
| US07786274B2 |
Anti-IL-20 antibody and its use in treating IL-20 associated inflammatory diseases
This invention features an antibody specifically binding to human IL-20 (e.g., mAb 7E and a equivalent thereof) and its use in treating an IL-20 associated inflammatory disease, such as atherosclerosis, RA, psoriasis, psoriatic arthritis, bacteria-induced gastric ulcer, and acute renal failure. |
| US07786268B2 |
Anti-IP-10 antibodies and methods of use thereof
The invention relates to fully human antibodies, and fragments thereof, that bind to interferon-inducible-protein-10 (IP-10, CXCL10), thereby modulating the interaction between IP-10 and its receptor, CXCR3, and/or modulating the biological activities of IP-10. The invention also relates to the use of such anti-IP-10 antibodies in the prevention or treatment of immune-related disorders and in the amelioration of one or more symptoms associated with an immune-related disorder. |
| US07786267B2 |
Multivariable antigens complexed with targeting humanized monoclonal antibody
The present invention includes compositions and methods for designing, making and using modular recombinant antibodies or fragments thereof with one half of a cohesin-dockerin pair that permits the rapid assembly of multivariant antigen conjugates. |
| US07786266B2 |
Methods for damaging cells using effector function of anti-DSC2 antibody
The present invention is based on the discovery that the cytoxicity of anti-desmocollin 2 (DSC2) antibodies can be used for treating various cancers including lung, colon, pancreatic, prostate, breast, gastric or liver cancers. Specifically, the present invention provides antibodies against DSC2 that have effector function. Furthermore, the present invention provides methods and pharmaceutical compositions that comprise anti-DSC2 antibody as an active ingredient for damaging DSC2-expressing cells via the effector function of the antibody. |
| US07786264B2 |
Monoclonal antibody against hepatitis E virus or its fragment with binding activity and use thereof
The present invention relates to monoclonal antibody specifically binding to polypeptide(s) comprising the amino acid sequence as set forth in SEQ ID No. 1 of hepatitis E virus ORF 2 or its conserved variants or its active fragments, or other monoclonal antibodies against ORF2 which can cross react with said monoclonal antibody of present invention, and its nucleotide sequence or its degenerate sequence; to the antigenic determinant in hepatitis E virus ORF2; to a method for screening isolated or recombined polypeptide or polypeptide analog, which has the same property of specifically binding said monoclonal antibody 8C11 and/or 8H3 as said antigenic determinant 1) or 3) of hepatitis E virus ORF2; to polypeptide or polypeptide analog screened by the method above and its nucleotide sequence or degenerate sequence; to a use of said polypeptide or polypeptide analog in preparation of a medicament for the diagnosis and/or precaution of hepatitis E virus infection; to a diagnostic kit for hepatitis E virus infection and a vaccine composition for prophylaxis of hepatitis E virus infection; to use of said monoclonal antibodies or their active fragments or conserved variants in preparation of a medicament for diagnosis, prophylaxis and/or treatment of hepatitis E virus infection; to pharmaceutical composition for prophylaxis and/or treatment of hepatitis E virus infection and a method for prophylaxis and/or treatment of hepatitis E virus infection; to a recombinant expression vector comprising said nucleotide molecule in present invention and a host cell transformed with said recombinant expression vector that is able to express monoclonal antibody and its conserved variants or active fragments or polypeptide or polypeptide analogs. |
| US07786260B1 |
Polypeptide fragments comprising c terminal portion of helicobacter catalase
An isolated polypeptide and immunogenic fragments thereof are described together with their variants and derivatives as novel immunogenic agents for treating or preventing Helicobacter infection in a mammalian host. The polypeptide comprises a C-terminal portion of a Helicobacter catalase, which portion lacks significant amino acid sequence identity with human catalase, wherein the polypeptide is other than full-length Helicobacter catalase. |
| US07786257B2 |
Signal-1/signal-2 bifunctional peptide inhibitors
A novel peptide sequence having the general formula AB wherein each of A and B represent a chain of amino acid residues and wherein said A chain is capable of binding with a major histocompatibility complex on an antigen presenting cell, and wherein said B chain is capable of binding with a Signal-2 receptor on an antigen presenting cell. Preferred forms of the peptide sequence further include an X chain positioned intermediate the A chain and the B chain. Moreover, preferred forms include an A chain which has at least about 10% sequence homology with a Signal-1 moiety, or is a peptidomimetic of a Signal-1 moiety, said B chain has at least 10% sequence homology with a Signal-2 receptor moiety, or is a peptidomimetic of a Signal-2 receptor moiety, and wherein the X chain has at least one amino acid residue, or is a peptidomimetic of that amino acid residue. Advantageously, the novel peptide sequence is capable of shifting a type-1 immune response to a type-2 immune response or from a type-2 immune response to a type-1 immune response. |
| US07786247B2 |
High IV melt phase polyester polymer catalyzed with antimony containing compounds
A melt phase process for making a polyester polymer melt phase product by adding an antimony containing catalyst to the melt phase, polycondensing the melt containing said catalyst in the melt phase until the It.V. of the melt reaches at least 0.75 dL/g. Polyester polymer melt phase pellets containing antimony residues and having an It.V. of at least 0.75 dL/g are obtained without solid state polymerization. The polyester polymer pellets containing antimony residues and having an It.V. of at least 0.70 dL/g obtained without increasing the molecular weight of the melt phase product by solid state polymerization are fed to an extruder, melted to produce a molten polyester polymer, and extruded through a die to form shaped articles. The melt phase products and articles made thereby have low b* color and/or high L* brightness, and the reaction time to make the melt phase products is short. |
| US07786246B2 |
Isosorbide-based polycarbonates, method of making, and articles formed therefrom
Disclosed herein is an isosorbide-based polycarbonate polymer comprising: an isosorbide unit, an aliphatic unit derived from a C14-44 aliphatic diacid, C14-44 aliphatic diol, or combination of these; and a polysiloxane block. |
| US07786244B2 |
Development and characterization of novel proton conducting aromatic polyether type copolymers bearing main and side chain pyridine groups
Featured are novel heterocycle substituted hydroquinones, aromatic copolymers and homopolymers bearing main and side chain polar pyridine units. These polymers exhibit good mechanical properties, high thermal and oxidative stability, high doping ability and high conductivity values. These novel polymers can be used in the preparation and application of MEA on PEMFC type single cells. The combination of the above mentioned properties indicate the potential of the newly prepared materials to be used as electrolytes in high temperature PEM fuel cells. |
| US07786243B2 |
Polyurea and polyurethane compositions for golf equipment
Golf equipment having improved cut and shear resistance that includes a polyurea composition, preferably saturated and/or water resistant, formed of a polyurea prepolymer and a curing agent, wherein the polyurea prepolymer includes an isocyanate and an amine-terminated compound, and wherein the curing agent includes a hydroxy-terminated curing agent, amine-terminated curing agent, or a mixture thereof. |
| US07786242B2 |
Ring-containing modified resins and dispersants including it
The ring-containing modified resin is represented by the following chemical formula (1) R1[—(—O—CO—NH—R2—NH—CO—O—R3—)p—O—R4]q (1) (in the chemical formula (1), R1 is a dehydroxyl residue of a resin having a benzene ring and/or a condensed ring and hydroxyl group: —R2— is deisocyanate group derived from an organic diisocyanate: —R3— is a dehydroxyl residue of polyol having number-average molecular weight of 200 to 30000: p is 1 to 3: —R4 is a hydrogen atom, alkyl group having 1 to 18 carbons, phenyl group: q is the same number as the number of the dehydroxyl residue of R1). |
| US07786240B2 |
Production and use of highly functional, highly branched or hyperbranched polylysines
The present invention relates to new high-functionality, highly branched or hyperbranched polylysines, to processes for preparing them, and to their use. |
| US07786235B2 |
Block polymer and device
The invention provides a block polymer capable of being used as a molecular wire facilitating injection of carriers between itself and an electrode, and a device in which electrodes are bridged by one molecule. The block polymer has a main chain composed of polyacetylene having a spiral structure, and includes a coating insulating block and a conductive block. The coating insulating block has a polyacetylene unit structure having alkyl chains at its side chains through functional groups, the alkyl chains being arranged in a direction parallel to the major axis of the main chain. The conductive block has a polyacetylene unit structure having hydrogen atoms at its side chains through functional groups, the hydrogen atoms being arranged in a direction parallel to the major axis of the main chain. The device has the above-mentioned block polymer, and two or more electrodes. |
| US07786233B2 |
Polyvinylpyrrolidone powder compositions
A polyvinylpyrrolidone powder composition including polyvinylpyrrolidone with a K value of not lower than 50 and not higher than 120, wherein a content of insoluble substances remaining on a membrane filter having a pore size of 1.2 μm when a 2 wt % aqueous solution of the composition is filtered with the filter is not higher than 70 ppm; a polyvinylpyrrolidone powder composition including polyvinylpyrrolidone with a K value of not lower than 50 and not higher than 120, wherein a K value lowering ratio to be observed when the composition is heated at 80° C. in air for 14 days is not higher than 12%; and a polyvinylpyrrolidone powder composition including polyvinylpyrrolidone with a K value of not lower than 50 and not higher than 120, wherein a content of insoluble substances remaining on a membrane filter having a pore size of 1.2 μm when a 2 wt % aqueous solution of the composition is filtered with the filter is not higher than 70 ppm, and a K value lowering ratio to be observed when the composition is heated at 80° C. in air for 14 days is not higher than 12%. |
| US07786228B2 |
Method for optimization of process by adjustment of initiator in polymerization system
Disclosed herein is an optimization method in a polymerization system in which heat is generated during the polymerization with an initiator. The optimization method includes the steps of measuring the heat generation amount based on the composition of the initiator in the polymerization system to previously set the relationship between the initiator composition and the heat generation amount, measuring the heat removal amount based on the temperature of a coolant in a cooling system of the polymerization system to previously set the relationship between the coolant temperature and the heat removal amount, calculating the initiator composition allowable at a predetermined coolant temperature to previously set the relationship between the coolant temperature and the initiator composition, and measuring the temperature of the coolant before and/or during the polymerization to adjust the composition of the initiator added at the measured temperature to the optimum condition, thereby decreasing the reaction time, and therefore, improving the productivity. |
| US07786220B2 |
pH and temperature sensitive hydrogels
The present invention relates to a block copolymer formed by coupling the following components with each other, as well as a hydrogel composition comprising the block copolymer and a hydrogel formed from the composition: (a) a copolymer of a polyethylene glycol (PEG)-based compound with a biodegradable polymer; and (b) a sulfonamide-based oligomer. The inventive block copolymer shows the sol-gel transition behavior sensitive to changes in not only temperature but also pH. Thus, the inventive block copolymer overcomes the shortcomings of temperature-sensitive copolymers, form a more strong and stable hydrogel, and is stable in vivo. Accordingly, the inventive block copolymer can be used in various applications in the medical and drug delivery fields. |
| US07786217B2 |
Organometallic-polyisomonoolefin block copolymers
The present invention provides copolymers which include a plurality of constitutional units that correspond to at least one cationically polymerizable isomonoolefin species and a plurality of constitutional units that correspond to at least one anionically polymerizable monomer species selected from the group consisting of monomers of formula (I): wherein R1, R2, R3, R4, n, p, M, X, and L are defined herein. The present invention also provides methods for making and using (e.g., in articles of manufacture such as medical devices) the copolymers of the present invention. |
| US07786212B2 |
Polyurethane and polyurea compositions for golf balls
Polyurethane and polyurea compositions for golf balls with improved stability of the curative blend, wherein the curative blend includes a pigment, a curing agent, and a compatible freezing point depressing agent so that the curative blend has a lower freezing point than the curing agent by itself and the blend does not lose pigment dispersion upon solidification and subsequent thawing. |
| US07786210B2 |
Plasticized poly(hydroxyalkanoic acid) composition
Disclosed is a composition comprising poly(hydroxyalkanoic acid), plasticizer, and optionally a nucleator, an impact modifier, or both. Also disclosed is a process for producing a thermoformed two-dimensional article having a surface area to thickness ratio greater than about 200:1 inch. |
| US07786208B2 |
Modified natural rubber masterbatch and method for producing the same as well as rubber composition and tire
This invention provides a method for producing a modified natural rubber masterbatch, which comprises the step of mixing a modified natural rubber latex, which is formed by adding a polar group-containing monomer to a natural rubber latex to graft-polymerize the polar group-containing monomer onto a natural rubber molecule in the natural rubber latex, with a slurry solution formed by previously dispersing a filler into water, and a modified natural rubber masterbatch produced by the method and capable of highly improving a low loss factor, a wear resistance and fracture characteristics of a rubber composition. |
| US07786202B2 |
Process for preparing organically modified layered double hydroxide
The invention relates to a process for preparing a layered double hydroxide comprising a charge-balancing anion, the process comprising the steps of: (a) preparing a precursor suspension or solution comprising a divalent metal ion source, a trivalent metal ion source, water, and a solvent which is miscible with water and in which at least 5 g/l of a charge-balancing anion precursor can be dissolved; (b) treating the precursor suspension or solution to obtain the layered double hydroxide, wherein the charge-balancing anion precursor is added to the suspension or solution before, during or after step (b), and wherein, if the charge-balancing anion is an organic anion, less than 50 wt % of the charge-balancing anion precursors, based on the total weight of charge-balancing anion precursors, is a salt, with the proviso that the charge-balancing anion is not carbonate. The invention further pertains to a layered double hydroxide obtainable by this process. |
| US07786199B2 |
Flame-retardants
Organic polymer compositions can be made flame-retardant by addition of selected organic phosphate and other components, such as known flame-retardants or conventional additives for further improvements, e.g. in flame retardancy or light stability. |
| US07786198B2 |
Crosslinkable substances based on organosilicon compounds
The present invention relates to substances, crosslinkable by attachment of an Si-bonded hydrogen atom to an aliphatic multiple bond, which comprise at least one compound of the formula R3P(O) (OH)2 (III) and/or the derivatives thereof, R3 being an optionally substituted hydrocarbon radical which can be interrupted by heteroatoms. |
| US07786191B2 |
Process for melt-shaping a polymer composition
The invention relates to a process for melt-shaping a polymer composition wherein the constituent components for the polymer composition are supplied directly to the shaping device in the form of a mixture of granules on or in which the constituent components are present. The granule mixture contains at least 3 granule-fractions containing the matrix polymer that differ in composition.The invention also relates to the granule mixture suitable for the melt-shaping process, the installation for the preparation and the process for preparing the granule mixture. The process results in a greater reproducibility and in articles with improved properties. |
| US07786189B2 |
Oligomer-modified layered inorganic compounds and their use in nanocomposites
Intercalates, exfoliates thereof, and nanocomposite compositions are formed by intercalating a layered silicate material, e.g., a phyllosilicate, with an oligomer or polymer intercalant that is a reaction product of at least one diamine with at least one dicarboxylic acid, to form a polyamide oligomer containing a xylylenediamine component. The oligomer or polymer may be formed in-situ by contacting the layered phyllosilicate with polymerizable monomer reactants using conditions to cause reaction and polymerization in the intercalating composition and intercalation of the resulting oligomer and/or polymer, between platelet layers of the phyllosilicate. An amine functionality of the oligomer or polymer is protonated for ion-exchange with interlayer cations of the phyllosilicate to bond the intercalant to the phyllosilicate platelet, at the protonated amine, at a negative charge site previously occupied by the interlayer cations. |
| US07786188B2 |
Nanocomposites of dendritic polymers
In the present invention, an inorganic reactant is, or reactants are, localized with respect to a dendritic polymer by physical constraint within or by a non-covalent conjugation to the dendritic polymer. The localized inorganic reactant or reactants is/are subsequently transformed to form a reaction product which is immobilized with respect to the dendritic polymer. This immobilization occurs on a nanoscopic scale as a consequence of the combined effects of structural, chemical and physical changes without having covalent bonds between the product(s) and the dendritic container and results in new compositions of matter called dendritic nanocomposites. The resulting nanocomposite material can be used to produce revolutionary products such as water soluble elemental metals, with specific applications including magnetic resonance imaging, catalytic, magnetic, optical, photolytic and electroactive applications. |
| US07786182B2 |
Method for production of water absorbing agent
The present invention provides a method for producing a water absorbing agent which excels in water absorption properties. In detail, the present invention provides a method for the production of a water absorbing agent, comprising a) a step of mixing a water absorbing resin, water, and a mixing aid without adding a water-soluble radical polymerization initiator and an ethylenically unsaturated monomer and b) a step of irradiating the resultant mixture with ultraviolet rays while keeping the mixture with flowed state. |
| US07786181B2 |
Chemical composition and process
The invention relates to a solid powdery composition comprising unexpanded thermally expandable microspheres including a thermoplastic polymer shell encapsulating a propellant and from about 0.1 to about 50 wt % of at least one inhibitor selected from the group consisting of acids having a melting point below about 200° C. and precursors therefore. The invention further relates to preparation and use thereof, a composition comprising a polymeric resin, preparation thereof, a process for working a polymeric resin and a material obtainable thereby. |
| US07786179B2 |
Demulsifiers in solvent base for separating emulsions and methods of use
Demulsifiers containing an anionic surfactant selected from alkylsulfosuccinates, alkylphosphonic acids, and their salts; a nonionic surfactant selected from ethylene oxide/propylene oxide copolymers, ethoxylated fatty acids of polyethylene glycol, terpene alkoxylates, and modified alkanolamides; and solvent bases comprising blends of dibasic esters. Methods for breaking emulsions using such demulsifiers and solvent bases are also disclosed. |
| US07786176B2 |
Vaginal treatment composition containing xylitol
A vaginal treatment composition that rapidly forms a gel when placed into contact with monovalent or polyvalent cations, such as sodium (Na+) and calcium (Ca2+) cations naturally found in vaginal mucosa, is provided. The gel may form in less than about 1 hour, in some embodiments less than about 1 minute, and in some embodiments, less than about 30 seconds. Among other things, such rapid gelation reduces the likelihood of leakage during use. In addition, because the gel may form intravaginally, it is more likely to retain its structure and shape over an extended period of time. In this manner, the gel may provide the prolonged release of a therapeutic agent that inhibits and/or treats vaginal infection. For instance, the gel may remain within the vagina for about 2 to about 48 hours to provide the desired effect. |
| US07786175B2 |
Anti-atherosclerosis composition containing carotenoids and method for inhibiting LDL oxidation
An anti-atherosclerosis composition comprising a LDL-oxidation inhibiting effective amount of phytoene, phytofluene or mixtures thereof and a method for inhibiting the progression of atherosclerosis. |
| US07786173B2 |
Tetralin analogs having sphingosine 1-phosphate agonist activity
Tetralin analogs that have agonist activity at one or more of the S1P receptors are provided. The compounds are sphingosine analogs, which, after phosphorylation, can behave as agonists at S1P receptors. |
| US07786167B2 |
Compositions containing prodrugs of florfenicol and methods of use
The present invention provides compositions and methods for administering florfenicol to mammals. The compositions contain a prodrug of florfenicol in a pharmaceutically acceptable carrier. In one embodiment the prodrug is an esterized form of florfenicol. Examples of suitable prodrugs include one or a combination of one or a combination of the following: florfenicol acetate, florfenicol propionate, florfenicol butyrate, florfenicol pentanoate, florfenicol hexanoate, florfenicol heptanoate, florfenicol octanoate, florfenicol nanoate, florfenicol decanoate, florfenicol undecanoate, florfenicol dodecanoate, and florfenicol phthalate. In another embodiment the prodrug is converted into the florfenicol in vivo by the action of one or more endogenous esterases. The invention also provides new compounds, pharmaceutical compositions containing the compounds, and methods for their administration. |
| US07786166B2 |
Methods and compositions for protecting and treating muscarinic receptors through administration of at least one protective agent
Methods and compositions for protecting muscarinic receptor(s) in a subject by administering at least one protective agent alone, in combination with other protective agents, or in combination with at least one neurologic agent. |
| US07786163B2 |
Constrained cyano compounds
Certain constrained cyano compounds are useful as inhibitors of post-proline/alanine cleaving amino-dipeptidases. Accordingly, these compounds can be employed, alone or with another therapeutic agent, to treat diabetes (especially, Type II diabetes), hyperglycemia, Syndrome X, diabetic complications, hyperinsulinemia, obesity, atherosclerosis and related diseases, as well as various immunomodulatory diseases and chronic inflammatory bowel disease. |
| US07786161B2 |
Carboxylic acid derivatives and pharmaceutical agent comprising the same as active ingredient
A carboxylic acid derivative of formula (I): wherein R1 is —COOH, —COOR6, etc.; A is a single bond, alkylene, etc.; R2 is alkyl, alkoxy, etc.; B is a carbocyclic ring or a heterocyclic ring; Q is alkylnene-Cyc2, etc.; D is a linking chain; and R3 is alkyl, a carbocyclic ring or a heterocyclic ring, or a non-toxic salt thereof. The compound of formula (I) binds to PGE2 receptor, especially subtypes EP3 and/or EP4 and show the antagonizing activity, are useful for the prevention and/or treatment of diseases induced pain, itch, urticaria, allergy, urinary frequency, urinary disturbance, Alzheimer's disease, cancer, dysmenorrhea, endometriosis, etc. |
| US07786158B2 |
Compounds as opioid receptor modulators
The present invention is directed to novel opioid receptor modulators of Formula (I). The invention further relates to methods for preparing such compounds, pharmaceutical compositions containing them, and their use in the treatment of disorders that may be ameliorated or treated by the modulation of opioid receptors. |
| US07786157B2 |
OXO-imidazolidines as modulators of chemokine receptors
The present invention provides compounds having formula (I): or pharmaceutically acceptable salts and N-oxides thereof, wherein the subscript m is an integer from 0-4; Ar is an optionally substituted aryl; B is an optionally substituted aryl; L1 is an optionally substituted linking group selected from the group consisting of C1-4 alkylene, C1-4 heteroalkylene, C2-4 alkenylene and —CH2N(Ru)X5—; and L2 is a bond or C1-3 alkylene. The compounds act as potent antagonists of the CCR1 receptor, and have in vivo anti-inflammatory activity. |
| US07786153B2 |
Compounds that are useful for improving pharmacokinetics
Novel compounds of formula 1 or a pharmaceutically acceptable salt thereof inhibit cytochrome P450 monooxygenase. |
| US07786152B2 |
Compound
A compound having Formula I wherein one of R1 and R2 is a group of the formula wherein R4 is selected from H and hydrocarbyl, R5 is a hydrocarbyl group and L is an optional linker group, or R1 and R2 together form a ring substituted with the group wherein R3 is H or a substituent, and wherein X is selected from S, O, NR6 and C(R7)(R8), wherein R6 is selected from H and hydrocarbyl groups, wherein each of R7 and R8 are independently selected from H and hydrocarbyl groups. |
| US07786144B2 |
Sulphur containing pyrazole derivatives as selective cannabinoid CB1 receptor antagonists
The present invention relates to sulphur containing pyrazole derivatives, and their S-oxidized active metabolites, as selective cannabinoid CB1 receptor antagonists having a high CB1/CB2 receptor subtype selectivity, to methods for the preparation of these compounds, to novel intermediates useful for the synthesis of these pyrazole derivatives, to pharmaceutical compositions comprising one or more of these pyrazole derivatives as active ingredients, as well as to the use of these pharmaceutical compositions for the treatment of psychiatric and neurological disorders. The compounds have the general formula (I) wherein the symbols have the meanings given in the specification. |
| US07786141B2 |
Dihydrospiroindene modulators of muscarinic receptors
The present invention relates to dihydrospiroindene modulators of muscarinic receptors. The present invention also provides compositions comprising such dihydrospiroindene modulators, and methods therewith for treating muscarinic receptor mediated diseases. |
| US07786139B2 |
PDE10 inhibitors and related compositions and methods
Compounds that inhibit PDE10 are disclosed that have utility in the treatment of a variety of conditions, including (but not limited to) psychotic, anxiety, movement disorders and/or neurological disorders such as Parkinson's disease, Huntington's disease, Alzheimer's disease, encephalitis, phobias, epilepsy, aphasia, Bell's palsy, cerebral palsy, sleep disorders, pain, Tourette syndrome, schizophrenia, delusional disorders, drug-induced psychosis and panic and obsessive-compulsive disorders. The compounds have the general structure: wherein m, n, p, x, R, R1, R2, R3, R4, R5, A and B, are defined herein, including pharmaceutically acceptable salts, stereoisomers, solvates or prodrugs thereof. Also disclosed are compositions containing a compound of this invention in combination with a pharmaceutically acceptable carrier, as well as methods relating to the use thereof for inhibiting PDE10 in a warm-blooded animal in need of the same. |
| US07786136B2 |
Indazole-carboxamide compounds
The invention provides novel indazole-carboxamide 5-HT4 receptor agonist compounds. The invention also provides pharmaceutical compositions comprising such compounds, methods of using such compounds to treat diseases associated with 5-HT4 receptor activity, and processes and intermediates useful for preparing such compounds. |
| US07786133B2 |
Chemically modified small molecules
The invention provides small molecule drugs that are chemically modified by covalent attachment of a water-soluble oligomer obtained from a monodisperse or bimodal water-soluble oligomer composition. A conjugate of the invention, when administered by any of a number of administration routes, exhibits a reduced biological membrane crossing rate as compared to the biological membrane crossing rate of the small molecule drug not attached to the water-soluble oligomer. |
| US07786131B2 |
Pyrimido[5,4-d]pyrimidines derivatives as irreversible inhibitors of tyrosine kinases
The present invention relates to pyrimido [5,4-d] pyrimidine compounds of Formula II or a pharmaceutically acceptable salt thereof, wherein Q is and X, E1, E2, E3, R6 and p are as defined herein. The compounds of this invention are irreversible inhibitors of tyrosine kinases and are useful in the treatment of cancer, atherosclerosis, restenosis, endometriosis and psoriasis. |
| US07786129B2 |
Piperazine derivatives of dialkyl oxindoles
The present invention is concerned with new 3,3-disubstituted indol-2-one derivatives of the general Formula (I), wherein R1 stands for hydrogen, halogen, alkyl having 1-7 carbon atom(s) or sulfonamido; R2 represents hydrogen or halogen; R3 denotes hydrogen, alkyl having 1-7 carbon atom(s) optionally carrying an aryl substituent or aryl optionally carrying one or two halogen substituent(s); R4 stands for alkyl having 1-7 carbon atom(s); R5 represents a group of the general Formula (II a) or (II b), wherein Q and W each represents nitrogen or CH; R6, R7 and R8 each stands for hydrogen, halogen, trifluoromethyl, alkyl or alkoxy having 1-7 carbon atom(s), or R6 and R7 together represent ethylenedioxy; m is 0, 1, or 2; a is a single, double or triple bond; n is 0, 1 or 2; and pharmaceutically acceptable acid addition salts thereof which are useful in the treatment or prophylaxis of diseases of the central nervous system, the gastrointestinal system and the cardiovascular system. |
| US07786128B2 |
Indole or benzimidazole derivatives as CB1 inverse agonists
Provided are compounds of the formula I: and pharmaceutically acceptable salts thereof, processes for making said compounds and pharmaceutically acceptable salts thereof, pharmaceutical compositions comprising said compound and pharmaceutically acceptable salts thereof, and methods of using said compounds. The compounds are useful for the treatment and/or prophylaxis of diseases which are associated with the modulation of CB1 receptors. |
| US07786125B2 |
Neuroprotective small organic molecules, compositions and uses of related thereto
The present application is directed to therapeutic compounds, compositions, and methods for culturing neuronal cells and for preventing and the treatment of neurodegenerative diseases, such as Parkinson's disease and amyotrophic lateral sclerosis (ALS). |
| US07786121B2 |
Derivatives of hydroxamic acid as metalloproteinase inhibitors
A compound of formula (I), or an enantiomer or diastereoisomer thereof, or a salt, hydrate or solvate thereof: for the treatment or prophylaxis of arthritis in mammals. |
| US07786118B2 |
Pharmaceutical formulations of antineoplastic agents
In its several embodiments, this invention discloses a pharmaceutical formulation comprising at least one antineoplastic agent or a pharmaceutically acceptable salt thereof, and at least one dissolution enhancing agent sufficient to substantially dissolve said at least one antineoplastic agent in at least one aqueous diluent, wherein said dissolution enhancing agent is urea, L-histidine, L-threonine, L-asparagine, L-serine, L-glutamine or mixtures thereof; a lyophilized powder comprising said pharmaceutical formulation, and articles of manufacture thereof. |
| US07786117B2 |
Therapeutic substituted thiazolidinones, oxazolidinones, and related compounds
Compounds comprising or a pharmaceutically acceptable salt or a prodrug thereof, are disclosed, wherein J, B, Y, G and A are as described. Methods, compositions, and medicaments related thereto are also disclosed. |
| US07786116B2 |
2-amino-quinoline derivatives useful as inhibitors of β-secretase (BACE)
The present invention is directed to novel 2-amino-quinoline derivatives, pharmaceutical compositions containing them and their use in the treatment of Alzheimer's disease (AD), mild cognitive impairment, senility and/or dementia. The compounds of the present invention are inhibitors of β-secretase, also known as β-site amyloid cleaving enzyme, BACE, BACE1, Asp2, or memapsin2. |
| US07786113B2 |
Heterocyclic carbamate derivatives, their manufacture and use as pharmaceutical agents
Objects of the present invention are the compounds of formula I their pharmaceutically acceptable salts, enantiomeric forms, diastereoisomers and racemates, the preparation of the above-mentioned compounds, medicaments containing them and their manufacture, as well as the use of the above-mentioned compounds in the control or prevention of illnesses such as cancer. |
| US07786109B2 |
Tricyclic amide derivatives as modulators of H3 receptors
The present invention relates to compounds of formula I wherein A, G, r and R1 to R5 are as defined in the description and claims, and pharmaceutically acceptable salts thereof. The compounds are useful for the treatment and/or prevention of diseases which are associated with the modulation of H3 receptors such as, for example, diabetes mellitus. |
| US07786108B2 |
Compounds and method for treating dyslipidemia
Compounds of formula I wherein n, m, p, q, Y, R1 R2, R3a, R3b, R4, R5, and R6 are as defined herein and their pharmaceutical compositions and methods of use are disclosed. |
| US07786102B2 |
Steroids as agonists for FXR
The invention relates to compounds of formula (I): wherein R is ethyl, and pharmaceutically acceptable salts, solvates or amino acid conjugates thereof. The compounds of formula (I) are useful as FXR agonists. |
| US07786098B2 |
Fluoroalkoxycombretastatin derivatives, method for producing the same and use thereof
Combretastatin derivatives of formula (I), preparation and use thereof are disclosed, wherein: Rf is alkyl with 1-8 carbon atoms and 1-17 fluorine atoms, R is amino, substituted amino, hydroxyl, nitro, halo, alkyloxy, phosphate or amino acid side chain. Said derivatives have a capability to inhibit the polymerization of microtubules and are useful in treatment against tumor and neovascularization. |
| US07786091B2 |
Compositions and methods for ameliorating myosin VIIa defects
The invention provides compositions and methods for ameliorating defects in myosin VIIa (MYO7A) expression and/or function, including providing vectors for myosin VIIa expression and formulations comprising them, and methods of using them, for treating human retinitis pigmentosa (or retinal degeneration), and blindness and deafness such as that found in Usher syndrome. The invention provides in vivo gene therapy for ameliorating defects in myosin VIIa (MYO7A) expression and/or function, including compositions and methods for gene transfer of the human myosin VIIa (MYO7A) gene (the MYO7A gene. |
| US07786084B2 |
Treatment of burns
The invention relates to the treatment of burn injuries. Described are methods for modulating a burn injury in a subject, the method comprising providing the subject with a gene-regulatory peptide or functional analogue thereof, e.g., LQG, AQG, LQGV (SEQ ID NO:1), AQGV (SEQ ID NO:2), LQGA (SEQ ID NO:3), VLPALP (SEQ ID NO:4), ALPALP (SEQ ID NO:5), VAPALP (SEQ ID NO:6), ALPALPQ (SEQ ID NO:7), VLPAAPQ (SEQ ID NO:8), VLPALAQ (SEQ ID NO:9), LAGV (SEQ ID NO:10), VLAALP (SEQ ID NO:11), VLPALA (SEQ ID NO:12), VLPALPQ (SEQ ID NO:13), VLAALPQ (SEQ ID NO:14), VLPALPA (SEQ ID NO:15), GVLPALP (SEQ ID NO:16), LPGC (SEQ ID NO:19), MTRV (SEQ ID NO:20), MTR, and VVC. Also described is the use of an NF-kappaB down-regulating peptide or functional analogue thereof for the production of a pharmaceutical composition for the treatment of burn injury of a subject. |
| US07786080B2 |
Mutein of a bone morphogenetic protein and use thereof
The present invention is related to a mutein of a bone morphogenetic protein, whereby the mutein comprises an amino acid substitution compared to the wildtype of the bone morphogenetic protein at the amino acid position corresponding to amino acid position 51 of human BMP-2. |
| US07786078B2 |
Template-fixed δ-hairpin peptidomimetics with CXCR4 antagonizing activity
Template-fixed β-hairpin peptidomimetics of the general formula (I) wherein Z is a template-fixed chain of 12, 14 or 18 α-amino acid residues which, depending on their positions in the chain (counted starting from the N-terminal amino acid), are Gly, NMeGly, Pro or Pip, or of certain types which, as the remaining symbols in the above formula, are defined in the description and the claims, and salts thereof, have CXCR4 antagonizing properties. These β-hairpin peptidomimetics can be manufactured by a process which is based on a mixed solid—and solution phase synthetic strategy. |
| US07786076B2 |
Immunogenic compositions and methods of use
Disclosed herein are immunogenic compositions comprising a multilayer film comprising two or more layers of polyelectrolytes, wherein adjacent layers comprise oppositely charged polyelectrolytes. A first layer polyelectrolyte comprises an antigenic polypeptide comprising one or more surface adsorption regions covalently linked to one or more antigenic determinant regions, wherein the antigenic polypeptide and the one or more surface adsorption regions have the same polarity. The immunogenic compositions may be employed in methods of eliciting an immune response in a vertebrate organism. |
| US07786075B2 |
Use of IL-28 and IL-29 to treat cancer and autoimmune disorders
Methods for treating patients with cancer and autoimmune disorders using IL-28 and IL-29 molecules. The IL-28 and IL-29 molecules include polypeptides that have homology to the human IL-28 or IL-29 polypeptide sequence and proteins fused to a polypeptide with IL-28 and IL-29 functional activity. The molecules can be used as a monotherapy or in combination with other known cancer and/or autoimmune therapeutics. |
| US07786071B2 |
Pon polypeptides polynucleotides encoding same and compositions and methods utilizing same
Isolated polynucleotides and polypeptides encoded therefrom are provided. These include mutated PON enzymes with increased, modified or substantially the same substrate specificity as compared to respective wild-type PON. Also provided are kits and methods using these enzymes. |
| US07786068B2 |
Cleaning composition comprising a ternary surfactant system in combination with dipropyl or diisopropyl adipate solvent
Cleaning compositions are described comprising an aqueous component: an organic solvent; an anionic surfactant; an amine co-surfactant containing either (a) an N-oxide group or (b) a zwitterionic group; and a nonionic surfactant; in a form of a microemulsion or microemulsion preconcentrate. Methods of cleaning a hard surface using such compositions are also described. |
| US07786063B2 |
Detergent composition for CIP comprising a C10-C14 aliphatic hydrocarbon and nonionic surfactant
The invention relates to a detergent composition for CIP, which comprises (A) a solvent having an SP value of 6 to 9 at 25° C. and (B) a surfactant such as a nonionic surfactant. |
| US07786061B2 |
Azeotropic compositions comprising fluorinated compounds for cleaning applications
The present invention relates to compositions comprising fluorinated olefins or fluorinated ketones, and at least one alcohol, halocarbon, hydrofluorocarbon, or fluoroether and combinations thereof. In one embodiment, these compositions are azeotropic or azeotrope-like. In another embodiment, these compositions are useful in cleaning applications as a degreasing agent or defluxing agent for removing oils and/or other residues from a surface. |
| US07786058B2 |
Rolling device employing lubricating grease composition and electric power steering apparatus employing the rolling device
A rolling device employing a lubricating grease composition containing a thickener which is a mixture of (a) one or more diurea compounds made from one or more primary amines and a diisocyanate; (b) at least one fatty acid metal salt; (c) at least one amide compound selected from the group consisting of aliphatic amides and bisamides, where the proportions of (a), (b) and (c) satisfy the relationship: a/(b+c)=0.2−10 provided that (1) the proportion of ingredient (a) is 1-10, (2) the proportion of ingredient (b) is 0.5-2.5, and (3) the proportion of ingredient (c) is 0.5-2.5, and the amount of the thickener is 2 to 30% by weight, based on the lubricating grease composition; (d) a base oil which is a lube base oil having a pour point of −36 to −67.7° C. that includes a synthetic hydrocarbon oil as the main component; and (e) 1-7% by weight of an additive mixture containing an organomolybdenum complex, an organozinc compound of a dithiocarbamic acid, and an organozinc compound of dithiophosphoric acid. |
| US07786057B2 |
Soot dispersants and lubricating oil compositions containing same
Linked aromatic compounds found to act as potent soot dispersants in lubricating oil compositions; lubricating, oil compositions containing such soot dispersants and precursor compounds from which the soot dispersants are derived. |
| US07786055B2 |
Antioxidant compositions for reducing odor in warming lubricant compositions
This invention relates to the clear, substantially anhydrous, warming compositions containing one or more polyhydric alcohols. The invention also relates to the compositions that include at least one or more antioxidant or antioxidants in combination selected from the group consisting of tocopherol, ascorbic acid and butylated hydroxytoluene (BHT), to prevent oxidation of polyhydric alcohol combination that results in the development of odor. |
| US07786050B2 |
Well treatment with ionic polymer gels
Methods comprising preparing an aqueous mixture of an anionic polymer, a charge screening surfactant, and a borate crosslinker, wherein the mixture has a conductivity less than 10 mS/cm, injecting the mixture down a wellbore, and gelling the mixture. An embodiment of the aqueous mixture can also include tetramethylammonium chloride as a clay stabilizer and a metal crosslinker such as a complex of zirconium and an amino acid ligand system. An embodiment can effectively provide borate crosslinking of an anionic polymer in a low-ionic-strength fluid system, without sacrificing ultimate gel strength or thermal persistence of the metal crosslinked polymer. |
| US07786044B2 |
2-substituted-6-amino-5-alkyl, alkenyl or alkynyl-4-pyrimidinecarboxylic acids and 6-substituted-4-amino-3- alkyl, alkenyl or alkynyl picolinic acids and their use as herbicides
6-Amino-4-pyrimidinecarboxylic acids having alkyl, alkenyl or alkynyl substituents in the 5-position and 4-aminopicolinic acids having alkyl, alkenyl or alkynyl substituents in the 3-position, and their amine and acid derivatives, are potent herbicides demonstrating a broad spectrum of weed control. |
| US07786043B2 |
2-(pyridin-2-yl)-pyrimidines and their use for controlling harmful fungi
The invention relates to 2-(pyridin-2-yl)-pyrimidine compounds of general formula (I) and their use for controlling pathogenic fungi and as plant protection products that, as an active constituent, contain compounds of this type: In general formula (I), k represents 0, 1, 2, 3; m represents 0, 1, 2, 3, 4 or 5; n represents 1, 2, 3, 4 or 5; R1, independent of one another, represents halogen, OH, CN, NO2, C1-C4 alkyl, C1-C4 alkyl halide, C1-C4 alkoxy, C1-C4 alkoxy halide, C2-C4 alkenyl, C2-C4 alkynyl, C3-C8 cycloalkyl, C1-C4 alkoxy-C1-C4 alkyl, amino, phenoxy, which is optionally substituted by halogen or C1-C4 alkyl, NHR, NR2, C(Ra)═N—ORb, S(═O)pA1 or C(═O)A2, or two radicals R1 bound to adjacent carbon atoms can, together, also represent a group —O-Alk-O—, wherein Alk represents a linear or branched C1-C4 alkylene, and 1, 2, 3 or 4 hydrogen atoms can also be replaced by halogen; R2 represents C1-C4 alkyl halide, C1-C4 alkoxy, C1-C4 alkoxy halide, hydroxy, halogen, CN or NO2; whereby R2 can also represent hydrogen or C1-C4 alkyl when at least one of the three following conditions is fulfilled: n represents 3, 4 or 5; k represents 1, 2 or 3; if m is not equal to 0, at least one of the radicals R1 represents a radical that differs from halogen, C1-C4 alkyl, C1-C4 alkoxy and C1-C4 alkyl halide, and; R3 represents C1-C4 alkyl. |
| US07786042B2 |
Fluridone as an anti-inflammatory agent
The invention relates to a novel use of fluridone—compound known per se and used as an aquatic erbicide—in the medical field, in particular as an active compound for preparing a medicament having anti-inflammatory activity. Pharmaceutical compositions comprising fluridone as an active compound and pharmaceutically acceptable carriers and/or diluents are also disclosed. Finally, there is disclosed the pro-inflammatory activity of abscisic acid (ABA), a plant hormone which is also found in mammal serum and against which fluridone acts an inhibitor. |
| US07786040B2 |
4-cyclopropyl-1,2,3,-thiadiazole compound, agrohorticultural plant disease controlling agent and method of using the same
The present invention relates to 1,2,3 -thiadiazole compounds represented by formula (I): wherein R1, R2, R3, R4 and R5 each represents H, halogen, CN, alkyl, alkoxyalkyl, aryl, arylalkyl, alkylcarbonyl or the like; R6 represents —C═(W1)YR7 in which R7 represents H, alkyl, alkenyl, phenylcarbonyl, heterocyclic ring-carbonyl, arylsulfonyl or the like; Y represents O, S, —N(R11), —N(R11)O— in which R11 represents H, alkyl, cycloalkyl, substituted phenyl, or the like; W1 represents O or S; and symbols in the formula are defined in detail in the specification or salts thereof, and to a plant disease control agent for agricultural and horticultural use which contains the compound as an active ingredient. |
| US07786038B2 |
Composite metal oxide adsorbent for fluoride removal
The invention provides a composite metal oxide adsorbent for fluoride removal and the preparation method thereof. Said composite metal oxide adsorbent for fluoride removal comprises: 0.05-0.15 molar parts of transition metal, 0.2-0.6 molar parts of Al and/or Mg, and 0.05-0.15 molar parts of rare earth metal. The composite metal oxide adsorbent for fluoride removal has a saturation adsorption capacity on fluorine in water of up to 229 mg/g, under a neutral condition. |
| US07786033B2 |
Substrate with a photocatalytic coating
A substrate includes a fibrous material in the form of mineral wool of insulation type and/or glass fibers of reinforcement type, and a coating provided over at least a portion of a surface of the fibrous material, the coating having photocatalytic properties and including at least partially crystallized semiconductor material which has photocatalytic properties and which is of the oxide or sulphide type, and a bonding agent configured to adhere fibers of the fibrous material to each other, the bonding agent including an adhesion promoting agent configured to promote the adhesion of the coating to the fibrous material. The bonding agent is selected from one of an adhesive agent for mineral wool, a sizing agent for reinforcing threads, a bonding agent for a mat or web obtained from reinforcement threads, and an adhesive agent for a web obtained from glass wool. |
| US07786030B2 |
Cleaning tool
The present invention provides an indoor cleaning tool having a dry fibrous base material. An antigenicity-reducing composition that includes an antigenicity-reducing component, a lubricant, and a surfactant is applied to the fibrous base material. It would be preferable for the antigenicity-reducing component to be tannic acid. |
| US07786027B2 |
Functionalized substrates comprising perfume microcapsules
A functionalized substrate comprising: from about 1% to about 20% of a water-dispersible and/or a water-disintegrating material comprising a cellulose by weight; from about 0.001% to about 50% of a binder material by weight; and a plurality of microcapsules encapsulating at least one functional material, wherein said plurality of microcapsules is incorporated with said functionalized substrate. |
| US07786025B1 |
Activating dopants using multiple consecutive millisecond-range anneals
A method of fabricating an integrated circuit includes providing a gate conductor spaced above a semiconductor substrate by a gate dielectric, a pair of dielectric spacers disposed on sidewall surfaces of the gate conductor, and source and drain regions disposed in the substrate on opposite sides of the dielectric spacers, wherein the gate conductor and the source and drain regions comprise dopants; and subjecting at least a portion of the dopants to at least 3 consecutive anneal exposures to activate the dopants, wherein a duration of each exposure is about 200 microseconds to about 5 milliseconds. |
| US07786021B2 |
High-density plasma multilayer gate oxide
A thin-film transistor (TFT) with a multilayer gate insulator is provided, along with a method for forming the same. The method comprises: forming a channel, first source/drain (S/D) region, and a second S/D region in a Silicon (Si) active layer; using a high-density plasma (HDP) source, growing a first layer of Silicon oxide (SiOx) from the Si active layer, to a first thickness, where x is less than, or equal to 2; depositing a second layer of SiOx having a second thickness, greater than the first thickness, overlying the first layer of SiOx; using the HDP source, additionally oxidizing the second layer of SiOx, wherein the first and second SiOx layers form a gate insulator; and, forming a gate electrode adjacent the gate insulator. In one aspect, the second Si oxide layer is deposited using a plasma-enhanced chemical vapor deposition (PECVD) process with tetraethylorthosilicate (TEOS) precursors. |
| US07786017B1 |
Utilizing inverse reactive ion etching lag in double patterning contact formation
Solutions for solutions for utilizing Inverse Reactive Ion Etching lag in double patterning contact formation are disclosed. In one embodiment, a method includes providing a CMOS device including: an NMOS device having an NMOS gate and a PMOS device having a PMOS gate; a shallow trench isolation located between the NMOS device and the PMOS device; and an inter-level dielectric located over the NMOS device, the PMOS device and the shallow trench isolation; performing a double-patterning etch process on the CMOS device under conditions causing inverse reactive ion etching lag, the performing including forming a first opening, a second opening and a third opening, the second opening being wider than the first opening, and the third opening being contiguous with the second opening; and forming a first contact in the first opening and forming a second contact in both of the second opening and the third opening. |
| US07786012B2 |
Tapered edge exposure for removal of material from a semiconductor wafer
A semiconductor wafer edge exposure process as described herein employs a photoresist exposure step that exposes photoresist material to radiation having a gradient intensity profile near the outer edge of the wafer. The gradient intensity profile creates a tapered outer edge in the developed photoresist material, which in turn creates a tapered outer edge in the underlying target material after etching. Different gradient intensity profiles can also be used for subsequent layers of material. The resulting tapered edge profile of the wafer is resistant to edge peeling and flaking. |
| US07786009B2 |
Universal connector assembly and method of manufacturing
An advanced modular plug connector assembly incorporating an insert assembly disposed in the rear portion of the connector housing. In one embodiment, the connector has a plurality of ports in multi-row configuration, and the insert assembly includes a substrate adapted to receive one or more electronic components such as choke coils, transformers, or other signal conditioning elements or magnetics. The substrate also interfaces with the conductors of two modular ports of the connector, and is removable from the housing such that an insert assembly of a different electronics or terminal configuration can be substituted therefor. In this fashion, the connector can be configured to a plurality of different standards (e.g., Gigabit Ethernet and 10/100). In yet another embodiment, the connector assembly comprises a plurality of light sources (e.g., LEDs) received within the housing. Methods for manufacturing the aforementioned embodiments are also disclosed. |
| US07786007B2 |
Method and apparatus of stress relief in semiconductor structures
A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer. |
| US07786006B2 |
Interconnect structures with a metal nitride diffusion barrier containing ruthenium and method of forming
A method for forming an interconnect structure for copper metallization and an interconnect structure containing a metal nitride diffusion barrier are described. The method includes providing a substrate having a micro-feature opening formed within a dielectric material and forming a metal nitride diffusion barrier containing ruthenium, nitrogen, and a nitride-forming metal over the surfaces of the micro-feature. The nitride-forming metal is selected from Groups IVB, VB, VIB, and VIIB of the Periodic Table, and the metal nitride diffusion barrier is formed by exposing the substrate to a precursor of the nitride-forming metal, a nitrogen precursor, and a ruthenium precursor. |
| US07786004B2 |
Method of treating an exposed conductive film prior to forming a silicide
A method of manufacturing a semiconductor device includes forming a first conductive film on a semiconductor substrate via a first insulating film; forming a second conductive film on the first conductive film via a second insulating film; patterning the first and the second conductive films and the second insulating film to form a plurality of gate electrodes; filling a third insulating film between the plurality of gate electrodes; exposing an upper portion of the second conductive film by removing the third insulating film; covering surfaces of the exposed upper portion of the second conductive film with fluoride (F) or carbon (C) or oxygen (O); and forming a metal film on an upper surface of the second conductive film; and forming silicide layers on the upper portion of the second conductive films by thermally treating the metal film. |
| US07785997B2 |
Method for fabricating semiconductor device
A method for fabricating a semiconductor device includes forming at least two gate insulating layers having different thickness on a substrate having low, medium and high voltage regions; and then depositing a gate layer material on the gate insulating layers; and then forming a first etch mask on the gate layer material; and then forming gate electrodes in the low, medium and high voltage regions by etching the gate layer material using the first etch mask; and then forming a second etch mask to expose a thickest one of the gate insulating layers, the gate electrode and the first etch mask each formed in the high voltage region while covering the remaining gate insulating layers, the gate electrodes and the first etch masks formed in the low and medium voltage regions; and then etching the thickest gate insulating layer using the second etch mask; and then removing the first and second etch masks. Thereby, the first etch mask used for forming the gates remains without being removed even after the gate is formed to perform a role of a barrier during etching the gate insulating layer. |
| US07785996B2 |
Nonvolatile memory device and method of manufacturing the same
A nonvolatile memory device and a method of manufacturing the same are provided. The nonvolatile memory device includes a semiconductor substrate on which a source region, a drain region, and a channel region are formed, a silicon oxide layer formed on the channel region, a transition metal oxide layer having trap particles that trap electrons, formed on the silicon oxide layer, and a gate electrode formed on the transition metal oxide layer. |
| US07785990B2 |
Semiconductor device and method of fabricating the same
A method of forming a semiconductor device includes forming a first chip region, a second chip region, and a scribe lane region between the first and second chip regions in a wafer, the wafer having a first surface and a second surface facing the first surface, and forming a penetrating extension hole and a scribe connector in the scribe lane region, the penetrating extension hole penetrating the wafer from the first surface to the second surface and extending along the scribe lane region, wherein the scribe connector connects the first and second chip regions spaced apart from each other by the penetrating extension hole. |
| US07785987B2 |
Isolating chip-to-chip contact
An apparatus has two slabs of substrate material joined to each other, the two slabs including a pair of contacts joined to each other having a shape separating a first area from a second area. |
| US07785986B2 |
Method of manufacturing semiconductor device
To prevent semiconductor chips from adhering to the trays during transport, a method is employed which transports semiconductor chips in the following state. When trays provided with a plurality of accommodating portions having a recessed cross section for accommodating semiconductor chips on a main surface thereof are stacked in a plurality of stages, the semiconductor chips are accommodated in spaces defined by the accommodating portions formed over the main surface of the lower-stage tray and corresponding accommodating portions formed over the back surface of the upper-stage tray. Here, on bottom surfaces of the accommodating portions formed over the back surface of the upper-stage tray, isolated projections having a height which prevents the projections from coming into contact with the semiconductor chips are arranged in a scattered manner. In this way, it is possible to prevent the semiconductor chips from adhering to the back surface of the upper-stage tray. |
| US07785977B2 |
Thin film capacitor and manufacturing method therefor
A thin film capacitor including a substrate, a capacitor portion having an upper conductor, a lower conductor, and a dielectric thin film, and a resin protective layer for protecting the capacitor portion. A barrier layer is interposed between the capacitor portion and the resin protective layer. The barrier layer includes a crystalline dielectric barrier layer formed in contact with the capacitor portion and having the same composition system as the dielectric thin film, and an amorphous inorganic barrier layer formed on the surface of the crystalline dielectric barrier layer and composed of silicon nitride having non-conductivity. The inorganic barrier layer prevents deterioration in the properties of the dielectric thin film by blocking diffusion of the constituent elements of the inorganic barrier layer toward the capacitor portion. |
| US07785976B2 |
Method of forming a memory device incorporating a resistance-variable chalcogenide element
A method of forming a memory device, such as a PCRAM, including selecting a chalcogenide glass backbone material for a resistance variable memory function and devices formed using such a method. |
| US07785975B2 |
SOI device with improved storage capacity and method for manufacturing the same
An SOI device includes an SOI substrate composed of a stack structure of a silicon substrate, a buried oxide layer, and a silicon layer. Grooves are defined in the silicon layer each exposing the buried oxide layer. A barrier layer is formed on the lower portion of the sidewall of each of the grooves. An epi-silicon layer is formed to fill the grooves and cover the barrier layer. Gates are formed on the epi-silicon layer, and junction areas are formed in the silicon layer on both sides of the gates. |
| US07785973B2 |
Electronic device including a gate electrode having portions with different conductivity types and a process of forming the same
An electronic device can include a gate electrode having different portions with different conductivity types. In an embodiment, a process of forming the electronic device can include forming a semiconductor layer over a substrate, wherein the semiconductor layer has a particular conductivity type. The process can also include selectively doping a region of the semiconductor layer to form a first doped region having an opposite conductivity type. The process can further include patterning the semiconductor layer to form a gate electrode that includes a first portion and a second portion, wherein the first portion includes a portion of the first doped region, and the second region includes a portion of the semiconductor layer outside of the first doped region. In a particular embodiment, the electronic device can have a gate electrode having edge portions of one conductivity type and a central portion having an opposite conductivity type. |
| US07785970B2 |
Method of forming source and drain regions utilizing dual capping layers and split thermal processes
Source and drain regions are formed in a first-type semiconductor device. Then, a high tensile stress capping layer is formed over the source and drain regions. A thermal process is then performed to re-crystallize the source and drain regions and to introduce tensile strain into the source and drain regions of the first-type semiconductor device. Afterwards, source and drain regions are formed in a second-type semiconductor device. Then, a high compressive stress capping layer is formed over the source and drain regions of the second-type semiconductor device. A thermal process is performed to re-crystallize the source and drain regions and to introduce compressive strain into the source and drain regions of the second-type semiconductor device. |
| US07785969B2 |
Method for forming semiconductor device
A method for forming a semiconductor device of the present invention solves problems in a process for forming a fin type gate including a recess region, such as, a complicated process, low production margin, and difficulty in forming an accurate fin shape. In a process for forming an isolation dielectric film defining an active region, a nitride film pattern is formed in such a manner that the size of the nitride film is adjusted according to line width of a fin portion in a fin type active region formed in a subsequent process step, and an isolation dielectric film is formed in every region except for the nitride film pattern of a semiconductor substrate. Then, a recess is etched, and the isolation dielectric film is removed from a region where the line width of the nitride film pattern was reduced to a certain degree. Consequently, a process margin for forming a fin type active region is increased, and the shape of a fin shaped portion can be adjusted accurately, which together contribute to improved electrical properties in the semiconductor devices. |
| US07785965B2 |
Dual storage node memory devices and methods for fabricating the same
Dual storage node memory devices and methods for fabricating dual storage node memory devices have been provided. In accordance with an exemplary embodiment, a method includes the steps of etching a plurality of trenches in a semiconductor substrate and forming a layered structure within the trenches. The layered structure includes a tunnel dielectric layer and a charge storage layer. Bit lines are formed within the semiconductor substrate and a layer of conductive material is deposited overlying the layered structure. |
| US07785963B2 |
Method for fabricating inverted T-shaped floating gate memory
A memory device having a floating gate with a non-rectangular cross-section is disclosed. The non-rectangular cross-section may be an inverted T shape, a trapezoid shape, or a double inverted T shape. Methods are disclosed for producing a floating gate memory device having an improved coupling ratio due to an increased surface area of the floating gate. The memory device has a floating gate having a cross-sectional shape, such as an inverted T shape, such that a top contour is not a flat line segment. |
| US07785961B2 |
Trench DRAM cell with vertical device and buried word lines
A DRAM array having trench capacitor cells of potentially 4F2 surface area (F being the photolithographic minimum feature width), and a process for fabricating such an array. The array has a cross-point cell layout in which a memory cell is located at the intersection of each bit line and each word line. Each cell in the array has a vertical device such as a transistor, with the source, drain, and channel regions of the transistor being formed from epitaxially grown single crystal silicon. The vertical transistor is formed above the trench capacitor. |
| US07785960B2 |
Vertical channel transistor in semiconductor device and method of fabricating the same
A method of fabricating a vertical channel transistor for a semiconductor device includes forming, on a substrate, a plurality of active pillars each having a gate electrode formed on and surrounding a lower portion thereof; forming a first insulation layer over the active pillars to fill a gap region between the active pillars; partially removing the first insulation layer to exposes a circumferential surface of the gate electrode in all directions, without exposing the substrate in the gap region between the active pillars; forming a conductive layer on the remaining first insulation layer to fill the gap region between the active pillars; and patterning the conductive layer to form a word line that surrounds and contacts the circumferential surface of the gate electrode in all directions. |
| US07785959B2 |
Method of multi-port memory fabrication with parallel connected trench capacitors in a cell
A method is provided for fabricating a multi-port memory in which a plurality of parallel connected capacitors are in a cell. A plurality of trench capacitors are formed which have capacitor dielectric layers extending along walls of the plurality of trenches, the plurality of trench capacitors having first capacitor plates and second capacitor plates opposite the capacitor dielectric layers from the first capacitor plates. The first capacitor plates are conductively tied together and the second capacitor plates are conductively tied together. In this way, the first capacitor plates are adapted to receive a same variable voltage and the second capacitor plates are adapted to receive a same fixed voltage. |
| US07785958B2 |
Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, a trench within the first dielectric layer, and a second dielectric layer on the substrate. The second dielectric layer has a first part that is formed in the trench and a second part. After a first metal layer with a first workfunction is formed on the first and second parts of the second dielectric layer, part of the first metal layer is converted into a second metal layer with a second workfunction. |
| US07785956B2 |
Technique for compensating for a difference in deposition behavior in an interlayer dielectric material
By selectively providing a buffer layer having an appropriate thickness, height differences occurring during the deposition of an SACVD silicon dioxide may be reduced during the formation of an interlayer dielectric stack of advanced semiconductor devices. The buffer material may be selectively provided after the deposition of contact etch stop layers of both types of internal stress or may be provided after the deposition of one type of dielectric material and may be used during the subsequent patterning of the other type of dielectric stop material as an efficient etch stop layer. |
| US07785952B2 |
Partially and fully silicided gate stacks
Metal-oxide semiconductor (MOS) devices and techniques for the fabrication thereof are provided. In one aspect, a metal-oxide semiconductor device is provided comprising a substrate; and at least one n-channel field effect transistor (NFET) having a gate stack over the substrate. The NFET gate stack comprises an NFET gate stack metal gate layer; a first NFET gate stack silicon layer over the NFET gate stack metal gate layer; a second NFET gate stack silicon layer over a side of the first NFET gate stack silicon layer opposite the NFET gate stack metal gate layer, wherein an interface is defined between the first NFET gate stack silicon layer and the second NFET gate stack silicon layer; and an NFET gate stack silicide region that extends through the interface between the first NFET gate stack silicon layer and the second NFET gate stack silicon layer. |
| US07785949B2 |
Method for forming semiconductor device using multi-functional sacrificial dielectric layer
A composite dielectric layer including a nitride layer over an oxide layer serves the dual function of acting as an SMT (stress memorization technique) film while an annealing operation is carried out and then remains partially intact as it is patterned to further serve as an RPO film during a subsequent silicidation process. The need to form and remove two separate dielectric material layers is obviated. The nitride layer protects the oxide layer to alleviate oxide damage during a pre-silicidation PAI (pre-amorphization implant) process thereby preventing oxide attack during a subsequent HF dip operation and preventing nickel silicide spiking through the attacked oxide layer during silicidation. |
| US07785948B2 |
Semiconductor element and process for producing the same
The present invention provides a thin film transistor having excellent formability and processability, and particularly a thin film transistor using plastics as a substrate; an organic semiconductor as an active layer; and SiO2 thin films formed by coating as a sealing layer and a gate insulating layer, and a process for producing the same. The present invention provides a field-effect type thin film transistor having an active layer of an organic semiconductor, comprising on a plastic substrate, a sealing layer of a SiO2 thin film formed by coating; a gate electrode; a gate insulating layer of a SiO2 thin film formed by coating; gate and drain electrodes; and a semiconductor active layer. The high-quality SiO2 thin film is obtained by using a silicon compound as a starting material and irradiating a coated thin film of the solution of the starting material with light in an oxygen atmosphere. |
| US07785947B2 |
Method for manufacturing semiconductor device comprising the step of forming nitride/oxide by high-density plasma
In order to manufacture a highly reliable and compact TFT, it is an object of the present invention to provide a method for manufacturing a semiconductor device for forming a gate electrode, a source wiring and a drain wiring with high reliability, and a semiconductor device. In the method for manufacturing a semiconductor device, a semiconductor film is formed over a substrate having an insulated surface, a gate insulating film is formed over the semiconductor film, a gate electrode is formed over the gate insulating film, and a nitride film is formed over the surface of the gate electrode by nitriding the surface of the gate electrode by using high-density plasma. |
| US07785945B2 |
Method for fabricating PMOS transistor
A method for fabricating a PMOS transistor is disclosed herein. In one embodiment, the method can include forming a gate insulation layer and a polysilicon layer over a semiconductor substrate; asymmetrically etching the polysilicon layer; doping the asymmetrically etched polysilicon layer with a P-type dopant; diffusing the dopant in the asymmetrically etched polysilicon layer towards the semiconductor substrate; planarizing the asymmetrically etched polysilicon layer; forming a gate metal layer over the planarized polysilicon layer; forming a hard mask, which delimits a region to be formed with a gate of the PMOS transistor, over the gate metal layer; forming a gate stack by patterning the gate metal layer, the planarized polysilicon layer, and the gate insulation layer; and forming a source/drain in the semiconductor substrate at both sides of the gate stack. |
| US07785932B2 |
Placement method of an electronic module on a substrate and device produced by said method
The aim the disclosed process is to ensure maximum precision both at the level of the manufacturing of an electronic assembly from a chip with small dimensions as well as the level of the placement of such an assembly on an insulating substrate. This aim is achieved by a placement process on a support, called substrate, of at least one electronic assembly consisting of a chip including at least one electric contact on one of its faces, said contact being connected to a segment of conductive track, and said placement being carried out by means of a placement device holding and positioning said assembly on the substrate, comprising the following steps: formation of a segment of conductive track having a predetermined outline, transfer of the track segment onto the placement device, seizing of the chip with the placement device carrying the track segment in such a way that said track segment is placed on at least one contact of the chip. placement of the electronic assembly consisting of the chip and the track segment at a predetermined position on the substrate, embedding of the chip and of the track segment into the substrate. A placement device used in the process and a portable object including an electronic assembly placed according to the process are also objects of the present invention. |
| US07785931B2 |
Chip-based thermo-stack
A chip unit has a stack of at least two electronic chips stacked one on top of the other, a through-chip connection within the stack, the through-chip connection including a bounding material having an inner and outer perimeter, the inner perimeter defining an interior volume longitudinally extending through at least one of the at least two chips and at least partially into another of the at least two chips so as to form a tube extending between the one and the other of the chips, and an amount of working fluid hermetically sealed within the tube, the working fluid having a volume and being at a pressure such that the working fluid and tube will operate as a heat pipe and transfer heat from the stack of chips to the working fluid. |
| US07785930B2 |
Securing a transistor outline can within an optical component
The present invention relates to affixing components of optical packages. The optical packages can include an optical component, such as a TO-Can. The TO-Can can house an optical transmitter and/or an optical receiver. Another optical component of the optical package can be a barrel for aligning the TO-Can with an optical fiber. The TO-Can can be affixed within an open end of the optical barrel using a bonding substance, such as an epoxy, that has wicking properties. The wicking properties cause the bonding substance to enter a gap between the optical barrel and the TO-Can by capillary action. Use of the bonding substance with wicking properties creates a more robust optical package in a cost effective manner. |
| US07785929B2 |
Mountable integrated circuit package system with exposed external interconnects
The present invention provides a mountable integrated circuit package system comprising: providing an inner integrated circuit package including a first external interconnect having a shoulder; connecting an intraconnect between a second external interconnect and the shoulder; and forming an outer encapsulation over the inner integrated circuit package, the intraconnect, and partially exposing the first external interconnect on a top encapsulation side of the outer encapsulation and the second external interconnect on a bottom encapsulation side of the outer encapsulation. |
| US07785927B2 |
Multi-die wafer level packaging
A semiconductor die package is provided. The semiconductor die package includes a plurality of dies arranged in a stacked configuration. Through-silicon vias are formed in the lower or intermediate dies to allow electrical connections to dies stacked above. The lower die is positioned face up and has redistribution lines electrically coupling underlying semiconductor components to the through-silicon vias. The dies stacked above the lower die may be oriented face up such that the contact pads are facing away from the lower die or flipped such that the contact pads are facing the lower die. The stacked dies may be electrically coupled to the redistribution lines via wire bonding or solder balls. Additionally, the lower die may have another set of redistribution lines on an opposing side from the stacked dies to reroute the vias to a different pin-out configuration. |
| US07785925B2 |
Integrated circuit packaging system with package stacking and method of manufacture thereof
A method of manufacture of an integrated circuit packaging system includes: providing a stack board with a side having a connect contact next to a connect edge and a top contact next to a top edge perpendicular to the connect edge, and a bottom contact on an opposite side; mounting a circuit assembly having an assembly end next to the connect contact and an edge pad over the stack board; connecting the edge pad with the stack board; and applying an edge encapsulant over the connect contact and over the assembly end with the edge encapsulant extending no more than half the width of the stack board. |
| US07785923B2 |
Phase change memory device preventing contact loss and method for manufacturing the same
A phase change memory device includes a silicon substrate having a phase change cell region. A plurality of phase change cell are formed in the phase change region of the silicon substrate. A contact comprising a first contact and a second contact is formed on each of the phase change cells. A plurality of bit lines are electrically connected to the contacts. A contact plug is formed on the silicon substrate in a region outside of the phase change cell region, and a word line is formed over the silicon substrate and is connected to the contact plug. |
| US07785918B2 |
Image device and method of manufacturing the same
An image device which includes reflowed color filters. Reflowed color filters may be formed by heat treating preliminary color filters. When preliminary color filters are reflowed, color filters of different colors may be formed continuous with each other. Contiguous color filters in an image device may reduce manufacturing costs, maximize optical efficiency, minimize noise, and/or minimize crosstalk. |
| US07785916B2 |
Image sensor and method for manufacturing the same
Embodiments relate to an image sensor and a method for manufacturing the same. According to embodiments, a semiconductor substrate may include a pixel part and a peripheral part. A photo diode pattern may be formed over the pixel part having a height that is greater than a height of a surface of an interlayer dielectric film over the peripheral part. A device isolation film and a metal layer may be provided over the photodiode and over interlayer dielectric film over the peripheral part. A planarization layer may be provided and may compensate for a height difference so that a first metal film pattern connected to the photo diode pattern and a second metal film pattern connected to the metal wire in peripheral part may be simultaneously formed by patterning the planarization layer and metal film. |
| US07785915B2 |
Wafer level method of locating focal plane of imager devices
A method is disclosed which includes providing an imager substrate comprised of at least one imager device, providing a transparent substrate, forming a plurality of standoff structures on one of the imager substrate and the transparent substrate, the standoff structures having a width, forming an adhesive material having an initial thickness on a surface on at least one of the standoff structures, the adhesive material having an initial width that is less than the width of the standoff structures, and urging one of the imager substrate and the transparent substrate toward the other until such time as the imager substrate and the transparent substrate are in proper focal position relative to one another, the urging causing the initial thickness of the adhesive material to be reduced to a final thickness that is less than the initial thickness. |
| US07785904B2 |
High quantum yield acridinium compounds and their uses in improving assay sensitivity
The present invention relates to hydrophilic, high quantum yield acridinium compounds. It has been discovered that the placement of electron-donating groups in the acridinium ring system increases the amount of light that is emitted by the corresponding acridinium compound when its chemiluminescence is triggered by alkaline peroxide. More specifically, it has been found that the placement of one or two hydrophilic, alkoxy groups at the C-2 and/or C-7 position of the acridinium ring system of acridinium compounds increases their quantum yield and enhances the aqueous solubility of these compounds. The present hydrophilic, high quantum yield, acridinium compounds are useful chemiluminescent labels for improving the sensitivity of immunoassays. |
| US07785903B2 |
Variable domain library and uses
The invention provides polypeptides comprising a variant heavy chain variable framework domain (VFR). In some embodiments, the amino acids defining the VFR form a loop of an antigen binding pocket. In an embodiment, the polypeptide is a variable domain of a monobody and has a variant VFR. The polypeptide may optionally comprise one or more complementary determining regions (CDRs) of antibody variable domains. In an embodiment, the polypeptide is a variable domain of a monobody and has a variant VFR and one or more variant CDRs. Libraries of polypeptides that include a plurality of different antibody variable domains generated by creating diversity in a VFR, and optionally, one or more CDRs are provided and may be used as a source for identifying novel antigen binding polypeptides that can be used therapeutically or as reagents. The invention also provides fusion polypeptides, compositions, and methods for generating and using the polypeptides and libraries. |
| US07785901B2 |
Method of attaching hydrophilic species to hydrophilic macromolecules and immobilizing the hydrophilic macromolecules on a hydrophobic surface
The present invention is related to a method of attaching hydrophilic species to hydrophilic macromolecules and immobilizing the hydrophilic macromolecules on a hydrophobic surface, to a nano-assembly and to uses of the nano-assembly. |
| US07785898B2 |
Maternal antibodies as fetal cell markers to identify and enrich fetal cells from maternal blood
The present invention provides methods for identifying and/or enriching fetal cells from maternal blood, using as fetal cell markers the antibodies that the mother produces against paternally inherited fetal antigens. The fetal cell-maternal antibody complexes are identified and isolated using labelled agents that bind to the maternal antibodies. The present invention also provides fetal cells, isolated by use of said maternal antibodies, as a source of fetal DNA for prenatal genetic diagnosis of the fetus. |
| US07785897B2 |
Method and apparatus for producing a discrete droplet for subsequent analysis or manipulation
A method and apparatus for producing a discrete particle for subsequent analysis (such as mass spectrometry) or manipulation is disclosed. A discrete particle is generated by a particle generator. A net charge is induced onto the particle by an induction electrode. The particle is delivered to a levitation device where it is then electrodynamically levitated. If the particle is a droplet, desolvation will occur, leading to Coloumbic fissioning of the droplet into smaller droplets. The movement of the levitated droplet(s) can be manipulated by an electrode assembly. The droplet(s), and the charge thereon, can be delivered to a mass spectrometer in one aspect of the invention, providing an ion source for mass spectrometry without the detrimental space charge effects of electrospray ionization techniques. In another aspect of the invention, the levitated particle(s) may be controllably and precisely deposited onto a plate for subsequent analysis by matrix assisted laser desorption and ionization mass spectrometry. |
| US07785896B2 |
Methods for determining organic biocide concentration in a composite wood product
A composite wood product and methods for manufacturing the same and determining the concentration and distribution of an organic biocide within a composite wood product are provided. The organic biocide may be added to wood elements (i.e., fibers, flakes, strands, veneers) prior to consolidation and/or heating of the wood particles to form the composite wood product. A tracer additive may be mixed with the biocide, or applied separately to the furnish which is used to produce the composite wood product. The tracer additive may be detected via, for example, x-ray fluorescence. An amount of tracer additive detected may correlate to an amount of organic biocide within the wood elements and/or the composite wood product. |
| US07785892B2 |
Method of determining iron concentration
The present invention discloses a method of measuring iron concentration in a sample. The method includes bringing iron contained in the sample into contact with a metallochromic indicator for iron in the presence of lithium ion and determining the iron concentration based on the degree of resultant coloring. The present disclosure further includes a reagent and a kit using therefor. |
| US07785891B2 |
Device and methods for identifying and treating aspirin non-responsive patients
The present invention relates to methods and compositions for identifying and treating subjects in need of antithrombotic therapies but who are not responsive to aspirin. |
| US07785890B2 |
Method and device for the analysis of living reaction media
A method and device for analysis of reaction media containing one or more cells. This method and device can be used to perform an automated high-throughput analysis. |
| US07785884B2 |
Low density spreading methods for conifer somatic embryogenesis
In one aspect, the present invention provides methods of producing conifer cotyledonary somatic embryos from pre-cotyledonary embryos. The methods of this aspect of the invention include the step of (a) dispensing a plurality of pre-cotyledonary embryos onto a porous material horizontally disposed over a non-porous surface in a volume of sterile dilution medium sufficient to submerge at least the surface of the porous material, thereby uniformly dispersing the pre-cotyledonary embryos; (b) removing the sterile dilution medium from the non-absorbent porous material, thereby trapping the uniformly dispersed pre-cotyledonary embryos on the porous material; and (c) contacting the pre-cotyledonary embryos trapped on the porous material with development medium for a period of time sufficient to produce conifer cotyledonary somatic embryos. |
| US07785880B2 |
Mammalian cell lines for increasing longevity and protein yield from cell culture
Disclosed are compositions and methods for increasing the longevity of a cell culture and permitting the increased production of proteins, preferably recombinant proteins, such as antibodies, peptides, enzymes, growth factors, interleukins, interferons, hormones, and vaccines. Cells transfected with an apoptosis-inhibiting gene or vector, such as a triple mutant Bcl-2 gene, can survive longer in culture, resulting in extension of the state and yield of protein biosynthesis. Such transfected cells exhibit maximal cell densities that equal or exceed the maximal density achieved by the parent cell lines. Transfected cells can also be pre-adapted for growth in serum-free medium, greatly decreasing the time required to obtain protein production in serum-free medium. In certain methods, the pre-adapted cells can be used for protein production following transformation under serum-free conditions. The method preferably involves eukaryotic cells, more preferably mammalian cells. |
| US07785879B1 |
Pregnane X receptor compositions, crystals and uses thereof
The present invention relates, inter alia, to PXR polypeptides and crystals that are useful, for example, for crystallization and in assays for identification of modulators of PXR. |
| US07785876B2 |
Cultivation of hair inductive cells
The present invention relates to culturing cells which may be used in hair induction. In one aspect of the invention there is provided a method for cultivation of hair inductive cells, comprising the step of culturing the hair inductive cells in a culture medium comprising a medium conditioned by conditioning cells, in which the conditioning cells are derived from non-epidermal tissue. |
| US07785873B2 |
Antigen arrays for treatment of bone disease
The present invention is related to the fields of molecular biology, virology, immunology and medicine. The invention provides a composition comprising an ordered and repetitive antigen or antigenic determinant array, and in particular a RANKL protein, RANKL fragment or RANKL peptide-VLP-array. More specifically, the invention provides a composition comprising a virus-like particle and at least one RANKL protein, RANKL fragment or RANKL peptide bound thereto. The invention also provides a process for producing the conjugates and the ordered and repetitive arrays, respectively. The compositions of the invention are useful in the production of vaccines for the treatment of bone diseases and as a pharmaccine to prevent or cure bone diseases and to efficiently induce immune responses, in particular antibody responses. Furthermore, the compositions of the invention are particularly useful to efficiently induce self-specific immune responses within the indicated context. |
| US07785870B2 |
Cell-specific expression/replication vector
The present invention provides a cell-specific expression/replication vector, and a method of treatment comprising introducing a cell-specific expression/replication vector into specific cells such as malignant tumors in order to selectively disrupt the specific cells. A vector according to the invention is constructed by: obtaining a transcriptional initiation regulatory region of human calponin gene that is specifically expressed in smooth muscle cell; linking the above region upstream to a replication-related gene of a virus such as ICP4 and the like; linking DNA that encodes a protein such as suppressive factor for tumor angiogenesis or apoptosis-related factors and the like via IRES to the replication-related gene of the virus; and integrating a thymidine kinase gene in an intact state into the viral DNA. |
| US07785866B2 |
Compost tea apparatus
An apparatus and method of producing compost tea comprising a hopper, a separator having an intake and a discharge, the hopper communicating compost to the intake, a u-shaped screen, an auger rotably mounted thereon for conveying compost through the separator, and a plurality of spray nozzles directing spray onto the auger and compost, whereby water flows from the nozzles onto the compost separating nutrients and microorganisms from the compost producing compost tea, the compost tea passes through the screen into a catch basin, and the auger conveys the compost through the separator toward the discharge. |
| US07785860B2 |
Method for producing L-histidine using Enterobacteriaceae bacteria which has an enhanced purH gene produced
A method is provided for producing L-histidine using bacterium of the Enterobacteriaceae family wherein the L-amino acid productivity of said bacterium is enhanced by enhancing an activity of the AICAR transformylase-IMP cyclohydrolase encoded by the purH gene. |
| US07785858B2 |
Use of phosphoketolase for producing useful metabolites
The present invention provides a bacterium which has an ability to produce a useful metabolite derived from acetyl-coenzyme A, such as L-glutamic acid, L-glutamine, L-proline, L-arginine, L-leucine, L-cysteine, succinate, and polyhydroxybutyrate, wherein said bacterium is modified so that activities of D-xylulose-5-phosphate phosphoketolase and/or fructose-6-phosphate phosphoketolase are enhanced. The present invention also provides a method for producing the useful metabolite using the bacterium. |
| US07785852B2 |
Cleavage of nucleic acids
The present invention relates to means for cleaving a nucleic acid cleavage structure in a site-specific manner. Enzymes, including 5′ nucleases and 3′ exonucleases, are used to detect and identify nucleic acids derived from microorganisms. Methods are provided which allow for the detection and identification of bacterial and viral pathogens in a sample. |