最新美国发明专利
Document Document Title
US07719995B2 Application driven fast unicast flow replication
A technique to replicate unicast flows is described. A plurality of unicast control flows are received at a network element from a plurality of clients. One of the unicast control flows is forwarded to a server. A unicast content flow is received from the server at the network element in response to forwarding the one of the unicast control flows. The unicast content flow is replicated at the network element as a plurality of replicated unicast content flows for transmission to the plurality of clients.
US07719989B2 Routing protocol for ad hoc networks
A routing method for an ad hoc network is disclosed, the network comprising two or more nodes (A, B, C, D, E, F), and the method comprising: sending a message from a start node (A) to a finish node (F) via one or more intermediate nodes (B, C, D, E); each of the start node (A) and intermediate nodes (B, C, D, E) receiving an acknowledgement signal (AckB, AckC, AckD, AckE, AckF) from a one-hop neighboring node when the one-hop neighboring node receives the message from the start node (A;F) or intermediate nodes (B, C, D, E) and, in the case of the one-hop neighboring node not being the finish node (F), the start node and intermediate nodes receiving an acknowledgement signal (AckC, AckD, AckE, AckF) from a two-hop neighboring node when the two-hop neighboring node receives the message from the one-hop neighboring node.
US07719979B1 Bandwidth detection in a heterogeneous network with parallel and proxy modes
Effective bandwidth of a communication link is determined in a heterogeneous, packet switched network between a source and a destination, where effective bandwidth is defined as actual available bandwidth between the server and the client, minus the overhead of the various network protocols used to transmit the data. The method includes measuring transmission times between the source and a destination for a plurality data segments having different characteristics, such as different sized files or subfiles of data; processing the transmission times to cancel effects of transmission latencies other than the different characteristics of the data segments; and indicating a bandwidth based on said processing. The processing is done in parallel with the return of user resources to the destination, and using a bandwidth detection engine associated with a proxy server.
US07719978B2 Method for transmitting data over lossy packet-based communication networks
The invention is concerned with the transmission of streaming scalable data, particularly video data, through lossy communication channels, for applications in which limited retransmission is possible, and the associated reception and decoding of transmitted data. The PET (Priority Encoding Transmission) framework is used and the invention exploits both unequal error protection and limited retransmission. Each element in the scalable representation of each frame can be transmitted in one or both of two transmission slots, depending on the availability of the data received from the first of the two transmission slots. An optimization algorithm determines the level of protection which should be assigned to each element in each slot, subject to transmission bandwidth constraints. To balance the protection assigned to elements which are being transmitted for the first time with those which are being retransmitted, the proposed algorithm in preferred embodiments formulates a collection of hypotheses concerning its own behavior in future transmission slots.
US07719976B2 Variable dynamic throttling of network traffic for intrusion prevention
Methods, apparatus, and computer program products for variable dynamic throttling of network traffic for intrusion prevention are disclosed that include initializing, as throttling parameters, a predefined time interval, a packet count, a packet count threshold, a throttle rate, a keepers count, and a discards count; starting a timer, the timer remaining on no longer than the predefined time interval; maintaining, while the timer is on, statistics including the packet count, the keepers count, and the discards count; for each data communications packet received by the network host, determining, in dependence upon the statistics and the throttle rate, whether to discard the packet and determining whether the packet count exceeds the packet count threshold; and if the packet count exceeds the packet count threshold: resetting the statistics, incrementing the throttle rate, and restarting the timer.
US07719974B2 System and method for loadbalancing in a network environment using feedback information
A method for loadbalancing in a network environment is provided that includes receiving a request from an end user for a communication session at a central node. The method further includes identifying a selected one of a plurality of network nodes to facilitate the communication session for the end user based on feedback information provided by the selected network node. The feedback information is communicated from the selected network node and processed before making a decision to establish the communication session between the selected network node and the end user.
US07719972B2 Methods and apparatus for providing an admission control system in a wireless mesh network
Embodiments of methods and apparatus for providing an admission control system in a wireless mesh network are generally described herein. Other embodiments may be described and claimed.
US07719967B2 Cumulative TCP congestion control
Methods and apparatus, including computer program products, providing cumulative TCP (Transmission Control Protocol) congestion control. One method includes establishing multiple TCP connections between a transmitting host and a receiving host for sending data from the transmitting host to the receiving host; and using one congestion window on the transmitting host to perform congestion control for the multiple TCP connections as a whole.
US07719965B2 Methods and systems for coordinated monitoring of network transmission events
Methods and systems for coordinated monitoring of network transmission events. Predetermined information for the network transmission event is obtained at a first network location and the network transmission event predetermined information is provided to a predetermined monitoring location (or server). From the predetermined monitoring location, the predetermined information is provided to other network monitoring devices at one or more other network locations. At the one or more other network locations, the network transmission event, corresponding to the predetermined information obtained at the first location, is monitored. Network transmission event information, corresponding to the predetermined information obtained at the first location, is provided to the predetermined monitoring location from the first location and the other network locations. The monitoring of network transmission can be thereby coordinated.
US07719963B2 System for fabric packet control
A method for managing data traffic in nodes in a fabric network, each node having internally-coupled ports, follows the steps of establishing a managed queuing system comprising one or more queues associated with each port, for managing incoming data traffic; and accepting or discarding data directed to a queue according to the quantity of data in the queue relative to queue capacity. In one preferred embodiment the managed system accepts all data directed to a queue less than full, and discards all data directed to a queue that is full. In some alternative embodiments the queue manager monitors quantity of data in a queue relative to queue capacity, and begins to discard data at a predetermined rate when the quantity of queued data reaches the threshold. In other cases the queue manager increases the rate of discarding as the quantity of queued data increases above the preset threshold, discarding all data traffic when the queue is full.
US07719957B2 Resiliency in minimum cost tree-based VPLS architecture
A system for providing resilient multimedia broadcasting services over a VPLS network is described. A Network Management System (NMS) calculates disjoint minimum cost trees using the Steiner algorithm, executed with extra steps to result in disjoint trees. Destination PE routers in the VPLS network are connected to the disjoint trees so that they can be serviced by either tree in case of a fault. Each of the disjoint trees is provisioned with enough bandwidth to carry all of the services provided by the VPLS network. Under normal operation, however, the services are distributed evenly over the trees. In the event of a fault, the services on a faulty tree are switched to another tree using split horizon bridging. Each Steiner tree can also be realized using point-to-multipoint LSPs which is fully protected by a precomputed point-to-multipoint LSP.
US07719955B2 Transmission of signaling information in an OFDM communication system
An Orthogonal Frequency Division Multiplexing, OFDM, transmitter comprises a signalling data generator (113) which generates a set of data symbols indicative of physical layer characteristics of data transmissions from the OFDM transmitter (100). A first symbol generator (115) and second symbol generator (117) generates a first and second OFDM signalling symbol by allocating the set of data symbols to subcarriers. The allocation of the physical layer data symbols to subcarriers is different for the first OFDM signalling symbol and the second OFDM signalling symbol. A data packet generator (105) and transmitter (101) generate a data packet and transmit this to an OFDM receiver (300). The OFDM receiver (300) determines the physical layer data symbols by combining the data symbols of corresponding subcarriers of the first and second OFDM signalling symbols and uses the resulting information to decode the user data of the data packet.
US07719953B2 Optical recording medium, optical recording method, optical reproducing method, optical recording apparatus, and optical reproducing apparatus
A substrate in which a minute ruggedness structure including columnar projections is formed in a track shape is prepared. The pitch of the columnar projections of the ruggedness structure is set such that a plurality of the columnar projections is within a beam spot. A flat portion is disposed between adjacent tracks. A reflecting layer is formed on the substrate. The flat portion becomes a mirror surface because of the formation of the reflecting layer. The reflectance of the ruggedness structure becomes significantly lower than the reflectance of the flat portion. When the ruggedness structure is irradiated with high-power laser light, a portion of the ruggedness structure is raised to a reflecting layer side and flattened. At this time, reflectance of the raised portion becomes higher than reflectance of a non-raised portion. When a track including the ruggedness structure is irradiated with high-power pulse laser light, signal recording based on a change in reflectance is possible.
US07719950B2 Disk drive apparatus and method for adjusting focus bias and spherical aberration correction value
A disk drive apparatus includes: head means for performing laser irradiation to and detection of reflected light from an optical disk recording medium and having a focus bias mechanism and a spherical aberration correction mechanism; focus bias means for driving the focus bias mechanism to add a focus bias to a focus servo loop; spherical aberration correction means for driving the spherical aberration correction mechanism based on a spherical aberration correction value; evaluation value creating means for creating an evaluation value based on reflected light information obtained by the head means; adjustment means for adjusting the focus bias and the spherical aberration correction value; and control means for determining whether data is written on at least one track of the tracks adjacent to an adjustment use range on the recording medium and controlling an adjustment operation on the focus bias and the spherical aberration correction value by the adjustment means based on the determination result.
US07719948B2 Lens unit for optical pick-up apparatus and optical pick-up apparatus
The lens unit for the optical pick-up apparatus has: the objective lens by which the projecting light from the light source is condensed on the information recording surface of the optical information recording medium; the phase control element which is arranged on the light source side to the objective lens, and which controls the phase of the projecting light from the light source; and the supporting member holding the objective lens and the phase control element; and the phase control element is held under the condition that its optical axis is inclined by a predetermined angle to the optical axis of the objective lens, and the intersection at which the optical axis of the phase control element crosses the optical surface having the phase structure is arranged on the optical path passing through the central point which passes the optical axis of the objective lens.
US07719944B2 Method and apparatus for recording information on optical recording medium with compensation for thermal effects in ultra-high-density optical recording and reproducing system
A method for recording information on an optical recording medium in which a laser beam modulated into one or a plurality of write pulses with one or a plurality of write powers in accordance with target data to be written is projected onto a recording layer of the optical recording medium to form a record mark. During recording the information on the optical recording medium, a data level and a weight index are assigned to each channel bit in reference data trains before and after the target data. Recording compensation of the target data is carried out in accordance with the sum totals of the products of the data level and the weight index in the reference data trains, so that it is possible to easily carry out high a real recording by writing fine mark/space trains.
US07719943B2 Information recording device and information recording method
An information recording device and method capable of forming a recording mark by suppressing thermal interference. The device applies a laser beam to a recording medium and forms a recording mark in accordance with a recording signal. The device includes a light source for emitting the laser beam, signal generation elements for generating a recording pulse signal according to the recording signal, and drive elements for driving the light source according to the recording pulse signal. The recording pulse signal has a mark period for forming the recording mark and a space period. The recording pulse signal makes the level in the entire space period equal to or shorter than a predetermined length and a part of the space period longer than the predetermined length to be off level. While the recording pulse signal is off level, the recording medium is cooled down, thereby suppressing the affect of thermal interference.
US07719938B2 Optical disk recording/reproducing apparatus and optical disk recording method
An optical disk recording/reproducing apparatus for accurately determining optimum recording power of a laser beam even if medium deviations occurs, stabilizing recording quality, and realizing recording which hardly causes read inability error. In test recording, a laser drive (5) irradiates a laser beam to an optical disk (1) to record information while varying the recording power stepwise and reproduce the information stepwise recorded on the optical disk. A recorded state index value calculating unit (9) determines the value representing the index of the recorded state from the signal level of the reproduced information at each step. A smoothing calculating unit (11) performs smoothing calculation of the recorded state index value at each step. An optimum recording power determining unit (12) determines the optimum power by acquiring the optimum value from the recorded state index values at the steps after smoothing calculation to record information on the optical disk with the optimum power determined in recording.
US07719937B2 Method of optimizing the write power for recording marks in an information layer of a record carrier and recording device using such an optimizing method
A method of optimizing the write power for recording marks in an information layer of a record carrier by irradiating the information layer with a (pulsed) radiation beam. The method includes recording a pattern of test marks including short marks having a predetermined short nominal runlength onto the record carrier by applying at least three different write powers; measuring the runlengths of the recorded short marks obtained by applying the at least three different write powers; and determining an optimum write power based of the deviations of the measured runlengths from the nominal runlength of said short marks.
US07719935B2 Information storage medium having multiple information storage layers with optimal power control area, and recording apparatus to record data with respect to the information storage medium
An information storage medium is provided with a plurality of information storage layers, each of which includes an optimal power control (OPC) area for obtaining an optimal recording condition. Optimal power control areas in odd-numbered and even-numbered information storage layers viewed from a direction in which light is incident upon the information storage medium are disposed one on another to not directly face each other. An actually usable area of an optimal power control area in each of the information storage layers varies depending on use circumstances of each of the information storage layers. Therefore, when an OPC area of one information storage layer performs OPC, this OPC does not affect another information storage layer. Also, an area of each of the information storage layers can be efficiently used.
US07719933B2 Apparatus for manufacturing information record medium, information record medium, information recording apparatus and information recording method
On an information record medium (10, 11), record information can be recorded one time or a plurality of times by a predetermined record format. An apparatus for manufacturing the information record medium by using a stamper (27, 28) is provided with an embossed pit array forming device (20 to 26, 50) for forming on the stamper as an embossed pit array, pre-record data (SFi) which is a predetermined data row to disable overwriting on the record information in a pre-record area, which is set in advance in a range including an area (13c) assigned to information required to control a reproduction of the record information, which is recorded by the predetermined record format.
US07719926B2 Slotted cylinder acoustic transducer
A slotted cylinder acoustic transducer has a crescent-shaped insert disposed between a ceramic stack assembly and s cylindrical housing shell. In some embodiments, all of the ceramic elements in the ceramic stack assembly can have the same shape.
US07719921B2 Duty detection circuit, DLL circuit using the same, semiconductor memory circuit, and data processing system
A duty detection circuit includes discharge transistors, charge transistors, detection lines, and a comparator circuit that detects a potential difference of these detection lines, and also includes a gate circuit that controls the discharge transistors and the charge transistors in response to the internal clock signal of an even cycle. As a result, the detection lines are charged and discharged in response to the internal clock signal of the even cycle. Consequently, the duty detection circuit can be applied to a multi-phase DLL circuit, and a potential difference appearing in the detection line can be sufficiently secured.
US07719916B2 Semiconductor memory device
A semiconductor memory device includes a command decoder, a refresh address counter, an address delivery unit, and an address output selector. The command decoder decodes a command signal to generate a refresh signal. The refresh address counter generates a refresh address in response to the refresh signal. The address delivery unit delivers one of the refresh address and an address from outside of the semiconductor memory device to a memory core area. The address output selector outputs the refresh address to the outside of the semiconductor memory device.
US07719913B2 Sensing circuit for PCRAM applications
A sensing method for a memory cell as described herein includes selecting a memory cell. A first bias applied to the memory cell induces a first response in the memory cell. A second bias applied to the memory cell induces a second response in the memory cell, the second bias different from the first bias. The method includes determining a data value stored in the memory cell based on a difference between the first and second responses and a predetermined reference.
US07719910B2 Sense amplifier circuit and method for a dram
A sense amplifier of a DRAM includes, in series between two terminals of application of a supply voltage, at least one first transistor of a first channel type, and an amplification stage formed of two parallel branches each including a second transistor of the first channel type in series with a transistor of a second channel type. The gates of the transistors of a same branch are connected to the junction point of the transistors of the other branch. Each branch including at least one first additional transistor of the first channel type in parallel with at least each second transistor of the first channel type.
US07719909B2 DRAM writing ahead of sensing scheme
This invention discloses a write-sensing circuit for a semiconductor memory having at least one memory block with a continuous word-line being coupled to all the memory cells in a column of the memory block and a continuous bit-line being coupled to all the memory cells in a row of the memory block, the write-sensing circuit comprising a first and a second sense amplifier belonging to the same memory block, a first switching device coupled between the first sense amplifier and a first power supply, the first switching device being controlled by a first signal, and a second switching device coupled between the second sense amplifier and the first power supply, the second switching device being controlled by a second signal different from the first signal, wherein when the first sense amplifier is activated, the second sense amplifier can remain de-activated.
US07719908B1 Memory having read disturb test mode
Embodiments of the invention relate to the testing and reduction of read disturb failures in a memory, e.g., an array of SRAM cells. A read disturb test mode may be added during wafer sort to identify any marginal memory cells that may fail read disturb, thus minimizing yield loss. The read disturb test mode may include first writing data to the memory. After a predetermined time period, the read disturb test mode reads data from the same memory, and compares the read data with the data previously written to the memory. A repair signal may be generated, when the read data is different from the data previously written to the memory. Additionally, a system may be implemented to reduce read disturb failures in the memory. The system may include a match logic circuit and a data selecting circuit. When a match condition is satisfied, data is read from a register that stores the previous written data, instead of from the memory. The match logic circuit may be selectively enabled or disabled.
US07719906B2 Semiconductor device
Disclosed is a semiconductor storage device in which a cell array including a plurality of cells in need of refresh for data retention includes the redundancy area, which has a plurality of redundant cells for replacing faulty cells of a normal area within the cell array. When the redundancy area is tested, a refresh counter circuit for generating and outputting refresh addresses rearranges the address in such a manner that a row address of the redundancy area is substantially reduced and placed on a lower-order bit side inclusive of the LSB of the counter.
US07719897B2 Program verification for non-volatile memory
A non-volatile memory device includes page buffers arranged in groups, each group being coupled to a corresponding data output line so that data from more than one of the page buffers in each group may be simultaneously represented on the corresponding data output line during a program verification operation. Page buffers may be arranged in repair units with data from more than one page buffer simultaneously coupled to a data output line during a column scan operation.
US07719896B1 Configurable single bit/dual bits memory
A configurable memory device includes an array of configurable memory units arranged into rows and columns. The configurable memory unit includes a memory cell comprising a first storage element configured to store a first value and a second storage element configured to store a second value. The memory unit can be either a single-ended or a differential configuration. In the single-ended configuration, the stored value of each storage element is interpreted as one bit. In the differential configuration, the stored first and second values of the storage elements are interpreted as a differential single bit. An external control signal determines in which configuration the unit is in.
US07719889B2 Methods of programming multilevel cell nonvolatile memory
A memory system includes a first block in which data is stored with a low density and a second block in which data is stored with a high density. When data is received it is written to the first block, and in parallel some of the data is written to the second block, so that the second block is partially programmed. The second block is later fully programmed by copying additional data from the first block.
US07719888B2 Memory device having a negatively ramping dynamic pass voltage for reducing read-disturb effect
The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying sensing voltages to selected access lines for sensing selected memory cells. The method also includes applying a dynamic pass voltage to unselected access lines while the sensing voltages are applied.
US07719885B2 Thin film magnetic memory device having a highly integrated memory array
Read word lines and write word lines are provided corresponding to the respective MTJ (Magnetic Tunnel Junction) memory cell rows, and bit lines and reference voltage lines are provided corresponding to the respective MTJ memory cell columns. Adjacent MTJ memory cells share at least one of these signal lines. As a result, the pitches of signal lines provided in the entire memory array can be widened. Thus, the MTJ memory cells can be efficiently arranged, achieving improved integration of the memory array.
US07719884B2 Integrated circuit, cell arrangement, method of manufacturing an integrated circuit, method of operating an integrated circuit, and memory module
According to one embodiment of the present invention, and integrated circuit having a cell arrangement is provided. The cell arrangement includes: at least one reference memory cell set to a reference memory cell state; and a bias supplier to supply a bias condition to the reference memory cell when accessing the memory cell, such that the bias condition increases the stability of the set reference memory cell state.
US07719880B2 Method and system for semiconductor memory
Methods and systems for embodiments of a 9T memory cell, memory devices which utilize such 9T memory cells and the creation of embodiments of such memory devices are disclosed. More specifically, an embodiment of a 9T memory cell may comprise a 6T memory cell portion and a 3T read port. Additionally, in one embodiment, a memory which utilizes 9T memory cells may be made by from a grid comprising columns and rows of transistors formed according to a layout for 6T memory cells.
US07719876B2 Preservation circuit and methods to maintain values representing data in one or more layers of memory
Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer.
US07719875B2 Resistance change memory device
A resistance change memory device including: a substrate; cell arrays stacked thereabove, each including a matrix layout of memory cells; a write circuit configured to write a pair cell constituted by two neighboring memory cells; and a read circuit configured to read complementary resistance value states of the pair cell as one bit of data, wherein the memory cell includes a variable resistance element for storing as information a resistance value, and wherein the variable resistance element has a recording layer formed of a first composite compound expressed by AxMyOz (where “A” and “M” are cation elements different from each other; “O” oxygen; and 0.5≦x≦1.5, 0.5≦y≦2.5 and 1.5≦z≦4.5) and a second composite compound containing at least one transition element and a cavity site for housing a cation ion.
US07719870B2 Storage device
The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected wordline conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.
US07719869B2 Memory cell array comprising floating body memory cells
A memory cell array includes a plurality of floating body memory cells, which are arranged in cell rows, and world lines, wherein each word line is configured to control memory cells associated with a pair of cell rows. The memory cell array also includes bitlines, wherein each bitline is electrically connected to an individual memory cell of each pair of the cell rows.
US07719867B2 Voltage transformer with sequentially switchable voltage selection circuit
A voltage transformer with a sequentially switchable voltage selection circuit is provided for converting input electrical energy through the sequentially switchable voltage selection circuit, which is arranged within the transformer body with its two ends electrically connected to an input port and an output port respectively, into one of a plurality of output voltage values and outputting the electrical energy. When it is desired to regulate an output voltage, a connection device must be plugged in a socket portion on the transformer body to initialize a micro control unit through feedback to change a voltage value sent to a voltage transformation unit, and in turn change the voltage of output electrical energy until a display device displays an ideal output voltage value. Then, the user removes the connection device, and the voltage value of the input electrical energy is converted into corresponding to the selected predetermined voltage value to output the electrical energy.
US07719864B2 Pulse amplitude modulated current converter
A direct current to pulse amplitude modulated (“PAM”) current converter, denominated a “PAMCC”, is connected to an individual source of direct current. The PAMCC receives direct current and provides pulse amplitude modulated current at its output. The pulses are produced at a high frequency relative to the signal modulated on a sequence of pulses. The signal modulated onto a sequence of pulses may represent portions of a lower frequency sine wave or other lower frequency waveform, including DC.
US07719863B2 Active start judgment circuit
An active start judgment circuit is electrically connected to an AC/DC transforming power supply which has at least one standby power unit to transform AC to DC in regular conditions and a main power unit to transform the AC to the DC in an ON condition for operation of an electronic equipment. The start judgment circuit bridges the standby power unit and the main power unit, and generates a reference potential based on a voltage output from the standby power unit, and gets a power signal from the standby power unit to be compared with the reference potential to output a start signal to the main power unit to transform the AC to the DC. Thus the standby power unit can actively drive the main power unit to supply DC power to activate the electronic equipment.
US07719861B2 Signal differentiation with differential conversion circuit
A circuit for transmitting signals includes a transformer having an input side and an output side, the input side having a first end and a second end. A first transistor is coupled to the first end of the transformer, the first transistor being configured to provide a first signal to the first end in response to an input signal transitioning to a first state. A second transistor is coupled to the second end of the transformer; the second transistor being configured to provide a second signal to the second end in response to the input signal transitioning to a second state. The output side is configured to output differential signals according to the first and second signals applied to the transformer.
US07719860B2 Power supply and its controlling method
When an AC power supply (9) is powered up, a constant current supply section (14) supplies a constant current to a capacitor (C3) to charge the capacitor (C3). When a voltage across the capacitor (C3) becomes equal to or greater than a predetermined voltage, a switch control section (17) sets a switch (13) off. When an output current drops to lead to a light load, a load detecting circuit (15) stops the operation of a PWM control circuit (12) and activates a timer (16). The timer (16) supplies a switch-ON signal to the switch control section (17) when it is activated and a predetermined time measured elapses. When supplied with the switch-ON signal, the switch control section (17) sets the switch (13) on. When the switch (13) is set on, the capacitor (C3) is charged again, applying a voltage to the PWM control circuit (12).
US07719857B2 Structure of mounting shield cover and display device
A structure of mounting a shield cover according to the present invention includes a shield cover having an insertion part which is inserted into a gap formed between a circuit substrate and a shield cover fastening part along the circuit substrate. The insertion part of the shield cover includes a convex part that is elastic and deformable, and the end of the insertion part and the shield cover fastening part come in contact with each other by the elasticity with the convex part being in contact with the circuit substrate as the fulcrum.
US07719853B2 Electrically connecting terminal structure of circuit board and manufacturing method thereof
An electrically connecting terminal structure of a circuit board and a manufacturing method thereof are disclosed. The method includes: providing a circuit board defined with first and second predetermined areas; forming the first electrically connecting pad in the first predetermined area and the second electrically connecting pad in a portion of the second predetermined area; forming an insulated protecting layer on the circuit board, forming openings on the insulated protecting layer for exposing the first and second electrically connecting pads and a pad-uncovered portion of the second predetermined area; forming a conductive layer on the insulated protecting layer and forming openings of the insulated protecting layer; forming a resist on the conductive layer, forming openings on the resist above the openings of the insulated protecting layer; and forming first and second metals in the openings above the first and second electrically connecting pads and the pad-uncovered portion of the second predetermined area.
US07719852B2 Electronic component, mounting structure of electronic component
A high-reliability electronic component without reduction in insulation resistance under high-temperature and high-humidity conditions has satisfactory solderability of external electrodes. The electronic component includes a main body and external electrodes disposed on surfaces of the main body, the external electrodes include underlying electrode layers each containing a metal, alloy layers each disposed on the corresponding underlying electrode layer, Ni plating layers each disposed on the corresponding alloy layer, Ni oxide layers each disposed on the corresponding Ni plating layers, and upper plating layers each disposed on the corresponding Ni oxide layer, each Ni oxide layer having a thickness of about 150 nm or less, and each Ni plating layer having an average particle size of Ni particles of about 2 μm or more. To form the Ni plating layers having reduced grain boundaries, heat treatment is performed at about 500° C. to about 900° C. inclusive in a reducing atmosphere having an oxygen concentration of about 100 ppm or less.
US07719850B2 Arrangement with an integrated circuit mounted on a bearing means and a power supply module arrangement
A power supply module arrangement with an integrated circuit mounted on a bearing unit and a power supply includes an integrated circuit mounted on a bearing unit and a power supply module arrangement that is placed on the combination of bearing unit and integrated circuit. The power supply module arrangement includes a base extending at least partially over the base of the integrated circuit and/or all around the base of the integrated circuit. The power supply module arrangement allows for greater permissible load jumps, greater permissible current change rates and ever tighter tolerances regarding the constancy of the supply voltage.
US07719837B2 Method and apparatus for cooling a blade server
A method and apparatus adapted to cool a circuit board in a rack-mountable housing includes transferring heat from a heat source on the board to a primary heat storage medium positioned at an edge of the board or within a rack-mountable housing using at least one heat pipe, transferring heat from the primary heat storage medium to a secondary heat storage medium positioned in the rack-mountable housing through contacting surfaces of the primary and secondary heat storage mediums, transferring heat from the secondary heat storage medium to a heat exchanger, which may be positioned within the rack-mountable housing, using at least one heat pipe, and cooling the heat exchanger. A method and apparatus adapted to cool a printed circuit board includes transferring heat from a heat source on the board to a heat exchanger positioned in the rack-mountable housing using at least one heat pipe, and cooling the heat exchanger.
US07719836B2 Cooling fan module
A cooling fan module is disclosed. The cooling fan module includes a module housing, a fan assembly, a fan control circuit board, and an electrical connector. The fan assembly is disposed within the module housing and includes a fan housing, a motor disposed within the fan housing, and a blade assembly coupled to the motor. The fan control circuit board is disposed between the module housing and the fan housing, and is coupled to the motor. The electrical connector is coupled to the fan control circuit board and projects outside of the module housing.
US07719834B2 Storage device
Two or more media drives that cannot be detached by the user are pre-installed in an enclosure. An expansion slot member having the smaller number of expansion drive slots than the number of media drives that can be pre-installed are provided. The media drives that are installed via the expansion drive slots are installed so as to be detached by the user.
US07719833B2 Electronic control device
An upper lid forming an upper portion of a casing is formed by a metal (an aluminum alloy or the like) having a high heat radiation performance. The upper lid serves as a heat sink (a heat radiation member) radiating heat generated from electronic components within the casing to an external portion. A plurality of flat plate-shaped heat radiation fins are provided in an upper surface of the heat sink. A groove forming each of the heat radiation fins is open in a side surface of the heat sink without forming a step.
US07719831B2 Electronic apparatus
According to one embodiment, an electronic apparatus is provided with a circuit board contained in a case and including a first surface and a second surface formed on the reverse side of the first surface, a first heat generating component mounted on the first surface, a second heat generating component mounted on the second surface, a radiator section located off the circuit board, a first heat transfer member extending along the first surface and provided between the first heat generating component and the radiator section, and a second heat transfer member extending along the second surface and provided between the second heat generating component and the radiator section.
US07719830B2 Universal docking station for hand held electronic devices
A docking station is disclosed. The docking station has an adjustable opening that accommodates portable electronic devices with differing sizes and shapes. The opening is capable of expanding to accommodate larger devices and retracting to accommodate smaller devices while still supporting the portable electronic device in its proper position within the docking station.
US07719826B1 Integrated access cover
Integrated access cover arrangements for use in a portable computing devices, where the portable computing devices include a processor and are configured to house a user accessible component are presented including: a base configured to be coupled to the portable computing device; an integrated access cover housing a keyboard, the integrated access cover being slidingly connected with the base and configured to be disposed in at least a closed position and an open position with respect to the base, the user accessible component being hidden from a user when the integrated access cover is disposed in the closed position, the user accessible component being accessible by the user when the integrated access cover is disposed in the open position. In some embodiments, arrangements further include: a drive mechanism for translating the integrated access cover. Advantages include the ability to utilize lower profile configurations while maintaining functionality.
US07719825B1 Faceplate including wireless LAN communications
A faceplate for a housing of a computing device including a processor includes a bezel with interior and exterior surfaces. The bezel removeably covers at least a portion of an opening defined by the housing. A wireless local area network (LAN) unit is mechanically coupled to the interior surface of the bezel and comprises a data interface that enables data transfer between the wireless LAN unit and the processor.
US07719824B2 Electronic apparatus and unit
An electronic apparatus includes a housing having a hole, an electronic component disposed adjacent to the hole, and a support fitting that supports the electronic component. The support member has a partition that supports the electronic component and defines a space around the hole in cooperation with an inner wall of the housing.
US07719821B2 Electric double layer capacitor
The present invention provides an electric double layer capacitor. An electric double layer capacitor element sandwiches a separator between a cathode and an anode, arranged inside a container comprising a concave shaped containing portion and lid. A first conductive layer on the inner bottom face of a containing portion is covered by an insulating layer, and opening portions formed on the insulating layer penetrate to the first conductive layer. A second conductive layer is formed on the insulating layer and inside the opening portions, and is connected to a cathode through a conductive adhesive. The first conductive layer penetrates through the side wall of the containing portion, and is connected to a connecting terminal. An anode is connected to a third conductive layer through a conductive adhesive, and a collector is connected to a connecting terminal by extending between the containing portion and the lid.
US07719807B2 Field replaceable module for protection circuitry
Methods and apparatus for enabling internal circuitry associated with a device to be efficiently replaced in an operating environment for the device are disclosed. According to one aspect of the present invention, a device includes an enclosure that defines an interior of the device, and a circuit arrangement that is located in the interior. A data port interface is located in the interior, and the device also includes a receptacle and a protection circuitry arrangement. The receptacle is coupled to the circuit arrangement, and the protection circuitry arrangement provides protection to the circuit arrangement. The protection circuitry arrangement has an interface that is removably coupled to the receptacle such that at least a portion of the protection circuitry arrangement is contained in the interior of the device.
US07719804B1 Protective device with improved surge protection
The present invention is directed to an electrical wiring protection device that includes a housing assembly having a plurality of line terminals and a plurality of load terminals. A fault detection circuit is coupled to at least one of the plurality of line terminals and configured to generate a fault detection signal in response to detecting at least one fault condition in the electrical distribution system. A circuit interrupter is coupled to the fault detection circuit, The circuit interrupter is configured to couple the plurality of line terminals to the plurality of load terminals to form a conductive electrical path in a reset state, and decouple the plurality of line terminals from the plurality of load terminals in response to a fault detection signal in a tripped state. A voltage transient suppression circuit is coupled to at least one of the plurality of line terminals. The voltage transient suppression circuit is configured to generate a signal simulating the at least one fault condition in the event of failure.
US07719800B2 Magnetoresistive effect element and manufacturing method thereof, and magnetic head, magnetic reproducing apparatus, and magnetic memory using the same
An example magnetoresistive effect element includes a magnetoresistive effect film including a magnetization pinned layer, a magnetization free layer, and an intermediate layer interposed therebetween and having a magnetic region and a nonmagnetic region whose electrical resistance is higher than the magnetic region. A sense current is passed to the magnetoresistive effect film in a direction substantially perpendicular to the film plane thereof. The magnetic region of the intermediate layer penetrates the nonmagnetic region locally and extends in the direction substantially perpendicular to the film plane. The nonmagnetic region contains a nonmagnetic metallic element having a larger surface energy than a magnetic metallic element contained in the magnetic region.
US07719791B2 Reducing a probability of an organic ring forming on an air bearing surface of a slider while manufacturing the head stack assembly
Embodiments of the present invention pertain to reducing a probability of an organic ring forming on an air bearing surface of a slider while manufacturing the head stack assembly. According to one embodiment, clean dry air is received. The clean dry air is blown at a location on a suspension for the slider to vaporize at least a portion of a solution that potentially causes the organic ring to form on the air bearing surface of the slider.
US07719788B2 Servo information correcting method
A operation of storing a post code, which is read from each servo frame on a target track of a disk recording medium, in a memory if an on-track condition for determining that a head is controlled to be positioned on the target track is satisfied is executed. Next, a operation of using the post code, which is stored in the memory, for a correction of a demodulation position if the post code corresponding to each servo frame is stored in the memory and the on-track condition is satisfied in the correction of the demodulation position in each servo frame is executed.
US07719785B2 Disk drive device, manufacturing method thereof, and method for setting heater power value for a heater for adjusting a clearance
Embodiments of the present invention help to accomplish accurate and reliable clearance control. In one embodiment of the present invention, a disk drive device adjusts the clearance between a head element portion and a disk with a heater on a slider. The clearance control according to the present embodiment incorporates the variation in heater power efficiency in the clearance variation depending on the radial position. The clearance variation in a unit of heater power varies depending on the radial position. Taking account of the variation in the heater power efficiency in the thermal fly-height control (TFC) depending on the radial position in addition to the clearance variation between the head element portion and the disk caused by variation in fly-height or attitude, accomplishes more accurate TFC.
US07719778B2 Optical axis tilting device of laser optical system
An optical axis tilting device of a laser optical system, includes a lens barrel inside of which provided with a laser optical system; a tilt frame supported at the lens barrel; a tilt sensor which is provided at the tilt frame and is configured to detect a preset reference position of the tilt frame; a fixed frame fixed to the lens barrel and provided with a tilting mechanism which tilts the tilt frame relative to a horizontal plane; a leveling mechanism which supports the lens barrel tiltably, and tilts the lens barrel so as to detect the reference position by the tilt sensor and then levels the tilt frame; a feed screw which is rotatably driven by a driving motor; a feed piece which is reciprocated by the feed screw and engages with the tilt frame and tilts the tilt frame relative to the reference position; a piece position detection device configured to detect a position of the feed piece; and a computing device configured to calculate a tilting angle based on the position of the feed piece detected by the piece position detection device.
US07719777B2 Uniform diffuse omni-directional reflecting lens
A transparent multi-layer lens construction to be worn as a sunglass lens, or a fashion lens, that reflects light in a diffuse manner. The multi-layer lens construction is, in part, a combination of surface form and surface texture combined with a reflective medium and an anti-reflective coating. The present invention offers vast improvements over previously disclosed lens constructions in that it provides for both improved reflectivity and improved optical quality.
US07719773B2 Zoom lens unit and imaging apparatus
A zoom lens unit includes, in order from an object side to an image side: a first lens group having a positive refracting power; a second lens group having a negative refracting power; a third lens group having a positive refracting power; a fourth lens group having a negative refracting power; a fifth lens group having a positive refracting power; and a sixth lens group having a negative refracting power, an aperture stop is disposed between the second lens group and the third lens group, and when changing magnification from a wide-angle end to a telephoto end, at least the second lens group, the third lens group and the fifth lens group are moved, and the first lens group includes a reflecting optical element which bends a light path in the first lens group to obtain a predetermined light path length.
US07719772B2 Catoptric objectives and systems using catoptric objectives
In general, in a first aspect, the invention features a system that includes a microlithography projection optical system. The microlithography projection optical system includes a plurality of elements arranged so that during operation the plurality of elements image radiation at a wavelength λ from an object plane to an image plane. At least one of the elements is a reflective element that has a rotationally-asymmetric surface positioned in a path of the radiation. The rotationally-asymmetric surface deviates from a rotationally-symmetric reference surface by a distance of about λ or more at one or more locations of the rotationally-asymmetric surface.
US07719770B2 Three-dimensional display device with background image display
The present invention relates to a 3-dimensional video display device using a single image source for background image and object image display, which uses a double Fresnel lens structure, multi-reflector, and half mirror part. In particular, the present invention relates to a 3-dimensional image device with which the problem in prior art of spatial size in obtaining a background image is resolved, and with which a background image of a large display and a 3-dimensional image having an enhanced sense of depth and a large image are displayed simultaneously using only a single image source.
US07719766B2 Illumination source and method therefor
An illumination source and a method therefor. A light source includes a light circuit configured to process light and direct light, and a lighting element optically coupled to the light circuit to provide multiple colors of light. The light circuit propagates light using light guides. The use of light guides eliminates the use of free space optical elements, enabling the creation of more compact light sources. Furthermore, the use of light guides may enable the creation of light sources with fewer mechanical restrictions, thereby making the light sources potentially more reliable and less expensive.
US07719764B1 Method and device for stereo projection of pictures
A device for stereo projection of pictures represented by a picture signal which alternates periodically between pictures intended for right eye and pictures intended for left eye. A page selector which is adapted to transmit picture signals for first and, thereupon, each odd number picture to one projector and second and, thereupon, each even number picture to another projector.
US07719763B2 Light-diffusing member, transmission type screen, rear-projection-type display, and light-absorbing-part-forming resin composition
The present invention provides a light-diffusing member having no non-uniformity in stripes. The light-diffusing member according to the present invention is for diffusing at least a part of transmitted light by totally reflecting the same. The light-diffusing member comprises a light-diffusing part that has a diffusing-part base having a plurality of grooves tapered down toward the incident side, formed on the light-outgoing side in juxtaposition with one another, and light-absorbing parts formed, in the grooves in the diffusing-part base, by a radiation-curing resin composition. The radiation-curing resin composition includes colored particles. The colored particles have a mean particle diameter of 3.5 μm or more and 20 μm or less.
US07719759B2 Imaging optical system
Provided is a compact and bright imaging optical system having a high resolution. The imaging optical system includes three reflectors composed of a first reflector (1), a second reflector (2), and a third reflector (3) that are arranged in this order on an optical path of incident ray so as not to block the incident light. In the imaging optical system, in which light beams reflected by the three reflectors form an image plane (4), a convex mirror is used for any one of the first reflector (1) and the third reflector (3) and a concave mirror is used for the other thereof, and vertexes of a triangular dipyramid (6) are defined in terms of a central chief ray (5) by an appropriate point on the central chief ray (5) that is incident to the first reflection surface, a reflection point of each central chief ray on the first to third reflection surfaces, and an image forming point of the central chief ray. A plane containing three reflection points of the central chief ray on the first to third reflection surfaces coincides with a bonding plane between two triangular pyramids forming the triangular dipyramid (6).
US07719757B2 Microcapsule, electrophoretic display sheet, electrophoretic display device, and electronic apparatus
A microcapsule includes an electrophoretic dispersion liquid including at least one kind of electrophoretic particle having a polarity, and a capsule body encapsulating the electrophoretic dispersion liquid and made of a polymeric material including one of a nonpolar resin without having a polarity and a resin material having a nonpolar group without having a polarity as a side chain.
US07719755B2 Dispersion, microcapsule, electrophoretic device, electro-optical device, and method of forming a dispersion
A method for making an electrophoretic solution includes: including two kinds of particles having different charging polarities into the electrophoretic solution; calculating a mixing ratio so that charge amounts of the two kinds of particles become approximately equal to each other on a basis of a unit volume of a dispersion medium; and mixing the two kinds of particles in each mixed quantity that satisfies the calculated mixing ratio.
US07719750B2 Vehicular rearview mirror elements and assemblies incorporating these elements
The present invention relates to improved electro-optic rearview mirror elements and assemblies incorporating the same.
US07719749B1 Multi-purpose periscope with display and overlay capabilities
A periscope that is switchable between the normal optical view of the outside, a display view, and an overlay view in which the outside view and display view are combined. The switching element is an electronically switchable mirror with primarily reflective, primarily transparent, and intermediate states, depending on the application of electrical potentials.
US07719748B2 Method and apparatus for switching optical filters
The disclosure relates to a method and apparatus for providing switching optical filter. The switching optical filter provides several functionalities at the same time. For example, the filter can be used to remove photons of undesirable wavelength, such as ultraviolet or infrared, while simultaneously switching from and between one mode to another in order to accommodate changing ambient light conditions. In one embodiment, the disclosure relates to a method for forming an optical filter, the method comprising: forming a first electrode layer on a substrate; forming an ion conductor layer to at least partially cover the first electrode layer; forming an optically transparent layer over the ion conductor layer, the optically transparent layer preventing transmission of photons having a first wavelength while transmitting photons of a second wavelength; and forming a second electrode layer to at least partially cover the optically transparent layer.
US07719740B2 Hinge memory mitigation system and method
Provided are a system and method for reducing failures due to hinge memory. The method, in one embodiment, includes providing a torsional element having an amount of hinge memory, wherein the hinge memory is at least partially created using an average operational temperature. The method, in this embodiment, further includes subjecting the torsional element having the hinge memory to a temperature equal to or greater than the average operational temperature while the torsional element is in a parked state for an amount of time to reduce the amount of the hinge memory.
US07719735B2 Hologram recorder
A hologram recorder (A) records holograms in a selected unit recording area (B1) of a hologram recording medium (B) by interference between a recording beam (Lr) which is applied vertically to the unit recording area (B1) and a reference beam (Lr) which is applied obliquely to the unit recording area (B1). The hologram recorder (A) includes a reference beam oblique applier (23A, 23B) for application of the reference beam (Lr) obliquely to the unit recording area (B1) by reflection, and a reference beam swing mechanism (30) for supporting the reference beam oblique applier (23A, 23B) and for swinging the reference beam oblique applier (23A, 23B) about a predetermined rotation axis which is perpendicular to an entering direction of the recording beam (Lw) that makes an entry into the unit recording area.
US07719730B2 Image reader for use in an image forming apparatus, and contamination check method of guide film for the same
An image reading apparatus for use in an image forming apparatus includes a document glass installed on an upper side of the image reading body on which a document is placed; an image reading sensor installed under the document glass for stopping after being transferred to a predetermined position or for reciprocating in a straight direction parallel to the document glass; a cover for opening and closing the upper surface of the document glass; an automatic document feeder (ADF) for feeding the document to the position to which the image reading sensor is fixed; a document discharging plate for discharging the document fed through the automatic document feeding unit; first and second guide members for guiding to allow the document fed through the automatic document feeding unit to be discharged to the document discharging plate, the first and second guide members being installed at a predetermined interval to expose the document toward the image reading sensor; and a guide film installed to cover the interval between the first and second guide members for guiding to allow the document to be discharged to the document discharging plate. By this structure, a size of the image forming apparatus can be reduced.
US07719727B2 Image reproducing apparatus for preventing white balance offset and solid-state imaging apparatus
A digital camera supplies raw pixel data in a raw data mode to a digital processor. In the digital processor, a white balance decision circuit determines a white balance gain as color temperature information. The digital processor outputs the image data and the white balance gain thus determined over data bus to an interface unit. The linear matrix coefficients, supplied from a system controller, are sent over the data bus to the interface unit, which interfaces the data in accordance with a recording format, according to which the three sorts of data are recorded in a storage unit responsive to a control signal.
US07719708B2 Secured release method and system for transmitting and imaging a print job in which a security attribute in the print job header will prevent acceptance of subsequent data packets until a user performs authentication on the imaging device
An effective method for securing the release of the transmission, rendering, and outputting of an imaging/print job at an imaging device, for imaging/print jobs that originate in traditional print/spooling subsystems include the following steps. A print job header is associated with an imaging/print job to form a headed imaging/print job. A secured release input (that may be input at a secured release input apparatus of the client host device) is associated with the print job header by including a secured release indicative command/code in the print job header. The headed imaging/print job is divided into data packets. Initial data packet(s) are transmitted to the imaging device. It is determined whether the secured release indicative command/code is present in the initial data packet(s). Acceptance of subsequent data packets of the headed imaging/print job are prevented if the secured release indicative command/code is present in the initial data packet(s). When a secured release input is received on a secured release input apparatus of the imaging device, subsequent data packets of the headed imaging/print job are accepted.
US07719706B2 Direct printing authorization in a digital camera
This invention completes an authentication procedure early when it is ready to directly communicate with a printer, and serves as a user interface device of a direct print system. To this end, when a digital camera DSC is ready to directly communicate with a printer, and receives from the printer an inquiry about objects stored and held by the camera, it assigns an object which contains a word serving as authentication information of those stored and held in the DSC to a first handler (S52), assigns other objects (image data and the like) to subsequent handlers (S53), and sends that assignment result to the printer (S54).
US07719703B2 Print control program and medium and information processing apparatus
A print control program executed by an information processing apparatus, which spools print data created and spooled via a print data creation module such as a printer driver again and concurrently performs the re-spooling and output of the print data to a resending destination or an alternate device. It is thereby possible to speed up a throughput of the output on alternation of printing or resending.
US07719698B2 Displaying device and image forming apparatus
Such a displaying device that can be easily operated by aged persons and handicapped persons, and an image forming apparatus using the same will be provided. Upon continuously operating an upper button for the predetermined period of time, a set value of a magnification is changed at intervals of numeric change that are different from each other between a voice guide mode activated by a voice guide button and a normal mode. At this time, it is configured in such a manner that the interval of numeric change for the normal mode is smaller than the interval of numeric change for the voice guide mode, i.e., the changing rate of the set value of the magnification for the normal mode is larger than that for the voice guide mode.
US07719697B2 Probe for measuring the thickness of frost accretion on a surface
A probe for measuring the thickness of frost accretion on a surface includes a plurality of measuring stages that are stacked substantially orthogonally to the base of the probe. Each measuring stage has an emitter that emits a light beam that is substantially parallel to the base and a receiver that receives the light beam after reflection on the frost.
US07719694B1 System and method of surface wave imaging to detect ice on a surface or damage to a surface
A system and a method are provided for detecting a surface characteristic of a surface. A plurality of transponders are located on the surface for transmitting electromagnetic surface waves and for receiving the electromagnetic surface waves upon being reflected, diffracted, refracted, scattered, or otherwise altered by ice on the surface. A controller is coupled to the plurality of transponders. The controller is adapted to coordinate the plurality of transponders for imaging the surface characteristic of the surface.
US07719686B2 System for measuring a color property of a liquid
A system utilizing the flow cell of the present invention includes a reflectance mode spectrophotometer positioned with respect to the flow cell or a probe. Either the flow cell or the probe has a thin partition mounted in spaced relationship with respect to a transparent window. The partition has a predetermined index of refraction and has a thickness dimension that is less than that of the window. The spacing between the partition and the window is such that evanescent coupling of radiation reflected from the liquid into the material of the window is prevented.The spectrophotometer directs interrogating radiation toward a liquid flowing through the sample chamber and responds to interrogating radiation reflected from the liquid to produce an electrical signal representative of a color property thereof.
US07719660B2 Exposure apparatus
An exposure apparatus includes a projection optical system for projecting a pattern of a mask onto an object using a light with wavelength of 20 nm or less from a light source, and first and second accommodating parts for accommodating the projection optical system and the mask or the object, said first and second accommodating part has different pressures, wherein said a Ps/Po≧100 and Ps≦10−3 Pa are met, where Po is the pressure of the first accommodating part, and Ps is the pressure of the second accommodating part.
US07719659B2 Exposure apparatus and device manufacturing method
An exposure apparatus includes a projection optical system for projecting a pattern of a mask onto a substrate, a holder for holding the substrate and having a first channel for the fluid to flow, and a fluid supply unit for supplying the fluid from the first channel of the holder to at least part of a space between the projection optical system and the substrate, the exposure apparatus exposing the substrate via the projection optical system and the fluid.
US07719658B2 Imaging system for a microlithographical projection light system
Imaging system of a microlithographic projection exposure apparatus, with a projection objective (200, 300, 500, 600) that serves to project an image of a mask which can be set into position in an object plane onto a light-sensitive coating layer which can be set into position in an image plane, and with a liquid-delivery device (205) serving to fill immersion liquid (202, 310, 507) into an interstitial space between the image plane and a last optical element (201, 309, 506) on the image-plane side of the projection objective; wherein the last optical element on the image-plane side of the projection objective is arranged so that, seen in the direction of gravity, it follows the image plane; and wherein the projection objective is configured in such a way that when the system is operating with immersion, the immersion liquid has at least in some areas a convex-curved surface facing in the direction away from the image plane. It is also proposed for the last optical element (201, 309, 506) on the image-plane side of the projection objective to be arranged below the image plane in such a way that the immersion liquid (202, 310, 507, 601) is held at least in part in a substantially tub-shaped area on the last optical element on the image-plane side. Also, a rotator can be provided which serves to rotate a substrate carrying the light-sensitive coating (401) between a transport orientation in which the light-sensitive coating lies on a substrate surface that faces against the direction of gravity and an exposure orientation in which the light-sensitive coating (401) lies on a substrate surface that faces in the direction of gravity.
US07719653B2 Substrate for a liquid crystal display device and liquid crystal display device
The present invention relates to a substrate for a liquid crystal display device and a liquid crystal display device which are used as, for example, a display unit of an electronic apparatus, and an object of the present invention is therefore to provide a substrate for a liquid crystal display device and a liquid crystal display device capable of providing high transmittance, high luminance, and good display characteristics as well as a high production yield. A substrate for a liquid crystal display device is provided with a storage capacitor bus line formed approximately parallel with a gate bus line, a first pixel electrode connected electrically to the source electrode of a transistor, a second pixel electrode formed so as to be opposed to part of the source electrode of the transistor via an insulating film and to be separate from the first pixel electrode, and a slit formed between the adjoining end portions of the first pixel electrode and the second pixel electrode and having a slit width which is greater than a shortest width in a region over the storage capacitor bus line.
US07719651B2 In-plane switching liquid crystal display device
An in-plane switching liquid crystal display device including: first and second substrates; a gate line and data line arranged vertically and horizontally, respectively, on the first substrate and defining a pixel region; a thin film transistor (TFT) formed at a crossing of the gate line and the data line; common electrodes and pixel electrodes alternately disposed in the pixel region in a curvature form and generating an in-plane electric field; a common electrode connection line electrically connecting the common electrodes; a pixel electrode connection line electrically connecting pixel electrodes; a compensation electrode formed along at least one of the common electrode connection line and the pixel electrode connection line and compensating electric field; and a liquid crystal layer formed between the first and second substrates.
US07719650B2 Display panel and display device
The proceeding of peeling of a conductive layer in the vicinity of terminals is prevented. A display panel includes a conductive layer extending to the outside of terminals, and the conductive layer has slits extending in directions from one end face to the other end face alternately at two end faces along the extending direction of the conductive layer.
US07719649B2 Liquid crystal display panel
A liquid crystal display (LCD) panel including an active device array substrate, an opposite substrate and a liquid crystal layer is provided. The active device array substrate includes a substrate, a plurality of scan lines, a plurality of data lines, and a plurality of pixel units. The scan lines, the data lines and the pixel units are disposed on the substrate. Each of the pixel units is electrically connected to one of the scan lines and one of the data lines correspondingly and crosses over two sides of the corresponding scan line. The opposite substrate includes a plurality of alignment protrusions. The alignment protrusions are located over the scan lines. Besides, the liquid crystal layer is disposed between the opposite substrate and the active device array substrate. The above-mentioned liquid crystal display panel has higher aperture ratio.
US07719648B2 Manufacturing apparatus for liquid crystal device, manufacturing method for liquid crystal device, liquid crystal device and electronic device
A manufacturing apparatus for a liquid crystal device having a pair of substrates facing each other, an oriented film formed on an facing surface of at least one substrate in the pair of the substrates, and a liquid crystal held between the pair of substrates, includes: a film formation chamber; an evaporating section having an evaporation source, evaporating an inorganic material on the substrate in the film formation chamber by a physical vapor deposition, and forming an oriented film and a base film arranged under the oriented film; a base film formation area forming the base film and located substantially above the evaporation source in the film formation chamber; and an oriented film formation area located obliquely above the evaporation source in the film formation chamber, forming the oriented film and having a shielding plate having an elongated opening for selectively evaporating an inorganic material.
US07719647B2 Liquid crystal display apparatus
An IPS-mode liquid-crystal display apparatus for controlling transmission and cutoff of light by applying a cross-directional electric field to liquid-crystal molecules horizontally oriented reduces diagonal luminance rise and coloring at the time of black display by a simple configuration. A configuration is used in which an optical phase compensation member for canceling the double refraction property of a polarization-plate support base material is provided between the liquid-crystal-layer-side support base material of a lower polarizer and a liquid-crystal layer. Or, a configuration is used in which the optical phase compensation for canceling double refraction property of the polarization-plate support base material is provided between the liquid-crystal-layer-side support base material and the liquid-crystal layer.
US07719646B2 Liquid crystal display device
A liquid crystal display device of the present invention is composed of a λ/4 plate 1, a λ/2 plate 2, and a polarizing plate 3 which are provided in this order from the side of a liquid crystal layer 10. Here, an angle formed between an absorption axis of the polarizing plate 3 and an absorption axis of the λ/2 plate 2 is about 45°, an in-plane retardation of the λ/2 plate 2 is set to a value obtained by adding λ/4 to an in-plane retardation of a retardation plate 1, desirably, the λ/4 plate 1, and an optical axis of the λ/4 plate 1 and an optical axis of the λ/2 plate 2 are orthogonal to each other. In this configuration, the optical axis of the λ/4 plate 1 is placed at 150°, the optical axis of the λ/2 plate 2 is placed at 60°, and the absorption axis of the polarizing plate 3 is placed at 15°. This configuration improves display characteristics, that is, performs bright display at a higher contrast ratio and in a wider viewing angle with less dependence on visual field, thereby realizing an excellent reflection-type liquid crystal display device that is very easy to view even in a relatively dim place such as an indoor environment.
US07719643B2 Retardation layer and liquid crystal display apparatus using the same
A retardation layer capable of effectively restraining the display quality deterioration without generating a bright and dark pattern in the display image even when a retardation layer is disposed in between a liquid crystal cell and a polarizing plate. The retardation layer includes a plurality of minute units (domains) having molecular structure of cholesteric structure. Moreover, in the retardation layer, the helical pitch of the molecular structure is adjusted such that the selective reflected wavelength of the selected reflected light deriving from the molecular structure is shorter than the wavelength of the incident light on the retardation layer.
US07719639B2 Transflective-type liquid crystal display device and method of fabricating the same
A transflective-type liquid crystal display device includes a plurality of gate and data lines crossing each other on a substrate to define a plurality of pixel regions, a thin film transistor at each crossing of the gate and data lines, the thin film transistor including a semiconductor layer, and source and drain electrodes contacting source and drain regions, respectively, a projection seed pattern within the pixel region along a same layer as the semiconductor layer of the thin film transistor, and a reflective electrode contacting the drain electrode of the thin film transistor and having a reflective projection corresponding to the projection seed pattern.
US07719638B2 Semi-transmissive liquid crystal display device with signal lines that are broader in the transmissive portion than in the reflective portion
A semi-transmissive liquid crystal display device 10 having a first substrate which is partitioned by signal lines 13 and scanning lines 12 provided in a matrix pattern in which a reflective part 15 and a transmissive part 16 are formed on respective positions, a second substrate which is formed with a color filter and a common electrode, and a liquid crystal layer which is provided in between said two substrates, whereina pixel electrode 19 which is provided on said reflective part 15 and said transmissive part 16 is formed so as to overlap with said signal lines 13 and said scanning lines 12 via an insulating layer when viewed from the upper side,a width L1 of the signal line 13 corresponding to said transmissive part 16 is greater than a width L3 of said signal line 13 corresponding to said reflective part 15, andan overlapping width L2 of said pixel electrode 19 and said signal line 13 corresponding to said transmissive part 16 is greater than an overlapping width L4 of the pixel electrode 19 and said signal line 13 corresponding to said reflective part 15. As a result, it will be possible to provide a semi-transmissive liquid crystal display device having good contrast without any negative effects on display quality such as cross-talk or the like can be provided.
US07719635B2 Optical sheet and manufacturing method thereof, backlight, liquid crystal display
The present invention provides an optical sheet having one generally planar surface and composed of transmissive material, wherein on the other surface of the optical sheet, a concavo-convex pattern formed of a convex portion having a triangular top portion and a concave portion of a surface parallel to the one surface of the optical sheet is formed alternately in a generally parallel array.
US07719633B2 Light source apparatus
A light source apparatus capable of being reduced in size and thickness and superior in light combining performance includes a prism sheet unit having two mutually parallel prism surfaces each having a plurality of mutually parallel fine prism rows. The prism rows on the two prism surfaces intersect each other at a predetermined angle in plan view. A plurality of light sources are disposed at the light entrance surface side of the prism sheet unit to emit light so that the light is incident on the light entrance surface of the prism sheet unit at a predetermined angle thereto. The lights from the light sources are combined or color-mixed together by passing through the two prism surfaces, and the resulting combined or color-mixed light is emitted as exiting light.
US07719632B2 Liquid crystal display device
The present invention provides a liquid crystal display device which can largely enhance a property of focusing light from a backlight. The backlight arranged on a back surface of a liquid crystal panel includes a light guide plate, a light source, a first asymmetrical prism sheet, and a second asymmetrical prism sheet. A reflection surface having an inclination of 2° or less for guiding light from the light source toward the liquid crystal display panel is formed on a back surface of the light guide plate. The first asymmetrical prism sheet and the second asymmetrical prism sheet respectively include projecting portions which extend in the arrangement direction of the light source and are arranged in parallel to each other in the direction which intersects the arrangement direction of the light source.
US07719631B2 Optical sheet, backlight and liquid crystal display apparatus
An optical sheet has a large number of cylindrical lens elements provided successively on one of principal faces thereof. The cylindrical lens elements have a hyperboloidal face or a paraboloidal face and have a finite focal distance on the emission side of illumination light. Where a Z axis is taken in parallel to a normal line direction to the optical sheet and an X axis is taken in a direction of the row of the cylindrical lens elements, a cross sectional shape of the cylindrical lens elements satisfies Z=X2/(R+√{square root over ( )}(R2−(1+K)X2)) (where R is the radius of curvature of a distal end vertex, and K is a conic constant).
US07719629B2 Liquid crystal display device, liquid crystal module and front panel of liquid crystal display device
A liquid crystal display device is disclosed. The liquid crystal display device may include a cabinet having a front panel facing the front and in which an opening is formed; a liquid crystal panel having a display surface; and a chassis configured to clamp the outer region of the liquid crystal panel from the front side and the back side, to face the display surface to the opening, and to arrange the liquid crystal panel inside the cabinet. A hook may be provided that is projected rearward from a position close to the opening on the back surface of the front panel and engaged with the chassis that clamps the outer region of the liquid crystal panel, and prevents a displacement of the chassis toward the rear side.
US07719628B2 Backlight assembly and display apparatus having the same
A backlight assembly includes a light providing unit, an optical sheet, and a mold frame. The light providing unit generates light. The optical sheet has a main body disposed on the light providing unit and a sheet-guiding portion protruding outward from the main body. The mold frame has a frame shape to receive the light providing unit and the optical sheet and includes a sheet-guiding recess and a securing protrusion adjacent to at least one side of the sheet-guiding recess and protruding with respect to an upper surface of the optical sheet to prevent misalignment of the optical sheet. The sheet-guiding recess receives the sheet-guiding portion.
US07719627B2 Display, mobile device, and method of manufacturing display
A display includes: a display panel; a flexible printed circuit board that is attached to the display panel at a first height; and a frame that has the display panel disposed therein. The frame includes a guide portion that pulls the flexible printed circuit board to the outside of the frame, with the height of the flexible printed circuit board being varied from the first height to a second height by bending the flexible printed circuit board.
US07719621B2 Image display device and method having image control unit preventing light source unit from outputting an image when observer is outside of predefined normal viewing area
It is an object of the present invention to display unnaturalness-free images without showing an observer repetitive images in accordance with the observer's viewpoint.A light beam control element 101b limits a viewing area of images composed of light emitted from a light source array 101a. Here, a terminal position detection sensor 102 or an observer position detection sensor 103 detects a relative positional relationship between the observer's eye observing the image formed by the light emitted from the light source array 101a, and the light source array 101a and the light beam control element 101b. Based on the positional relationship detected by these sensors, a display image control device 104 controls the light source array 101a so as to change display contents of the light forming the image with the viewing area limited by the light beam control element 101b.
US07719618B2 Method and apparatus for masking of video artifacts and/or insertion of film grain in a video decoder
A video decoder comprising a first comfort noise addition block and a second comfort noise addition block. The first comfort noise addition block may be configured to (i) add comfort noise to luminance data and (ii) adjust a distribution of the comfort noise added to the luminance data. The second comfort noise addition block may be configured to (i) add comfort noise to chrominance data and (ii) adjust a distribution of the comfort noise added to the chrominance data. The first and the second comfort noise addition blocks may be integrated into a video output path of the video decoder. The distribution of the comfort noise added to the luminance data and the distribution of the comfort noise added to the chrominance data may be adjusted independently.
US07719617B2 Television having a java engine and a removable device port
Method and apparatus for use with televisions having an internal Java engine are included among the embodiments. In exemplary systems, a PCMCIA port allows the Java engine to load and execute Java applets selected by the viewer. Provision is made for system-aware applets to run concurrently with platform-independent applets on different Java display planes that are merged for display. Other embodiments are described and claimed.
US07719616B2 Direct digital encoding and radio frequency modulation for broadcast television application
A digital audio encoder, digital video conditioner, and a digital modulator are described for producing a television broadcast signal at a desired channel frequency range. Left and right audio channel signals are digitized and encoded according to a stereo standard and then combined to form a stereo audio signal. A second audio programming channel signal may be included. A video input can be digitized and conditioned to form a digital video channel. The stereo audio signal can be placed directly at a desired channel frequency by frequency modulation without the need for using an intermediate frequency. The digital video channel can be placed at a desired frequency by amplitude modulation. The digital and audio channels can be digitally combined to create a television transmission signal at a desired frequency and according to a desired standard.
US07719615B2 Digital broadcast receiver and method for processing caption thereof
A digital cable broadcast receiver and a method for automatically processing caption data of various standards and types, is disclosed. The digital broadcast receiver includes: a demultiplexer for dividing a received broadcast stream into video data, audio data, supplementary information; a controller for determining whether caption data included in the video data is digital caption data or analog caption data on the basis of caption information included in the supplementary information, and outputting a control signal according to a result of the determining; a digital caption decoder for extracting and decoding digital caption data from the video data according to the control signal; and an analog caption decoder for extracting and decoding analog caption data from the video data according to the control signal.
US07719613B2 Cradle for digital camera
Free setting of the angle or direction of a camera is available while the camera is being inserted into a cradle. A cradle for a digital camera is provided, which is capable of confirming a display screen of the camera, changing the recording medium or battery, or mounting or demounting a communication cable or the like while the camera is being mounted on the cradle without deteriorating the camera holding. The cradle has a structure such that a tripod screw hole is formed on the bottom surface of the cradle, thereby capable of fixing the cradle to a tripod while the digital camera is being inserted into the cradle. By making the height of rubber pads equal or higher than that of a tripod base, the cradle can be stably placed on a desk or the like. The cradle also has a structure that, among the walls holding the camera, a part of the walls that cover a liquid-crystal monitor of the camera, a media slot for a memory card, a terminal part including a power supply terminal or USB terminal is constituted by movable walls. The movable walls can be used as a simple tripod by employing a free stop structure or click stop structure.
US07719607B2 Electronic device system and electronic camera system
The invention provides an electronic camera system which operates an electronic camera in a minimum power mode when a not-genuine secondary battery is attached to the electronic camera. Namely, for the electronic camera which uses a detachable secondary battery as a power source, it determines from identification information whether the secondary battery is a genuine battery of the electronic camera. When determining that the secondary battery is a genuine battery, the electronic camera system allows the electronic camera to normally operate. When determining that the secondary battery is not a genuine battery, it places the electronic camera into the minimum power mode.
US07719605B2 Video camera apparatus including automatic focusing
A video camera includes a gate circuit for extracting a sharpness signal relative to an area which is set in a portion of a picture, a focus adjusting device for performing focus adjustment on the basis of the sharpness signal relative to the area, and an area selecting circuit for controlling the gate circuit to vary the area in size and determining a size of the area during a driving of a variator lens in accordance with a size of the area and a focal length used before the driving of the variator lens.
US07719599B2 Adapter for video camera for providing decreased depth of focus
The invention relates to a method and apparatus for capturing a low depth of focus image with a video camera (10) by forming a first image of a scene, with a first image format size, onto a projection area (16), housed inside an adaptor, and forming another image of the scene, with a second smaller image format size onto a semiconductor sensor field (28), housed inside the video camera (10). The invention further relates to configuring the projection area (16) to prevent non-image characteristics of the projection area from being imaged in a disturbing manner onto the semiconductor sensor field (28). The projection area is either movable with respect to the first image or encapsulated by clear filter glass, or both to prevent the non-image characteristics from being imaged in a disturbing manner. The adaptor includes an adaptor housing (30′) for attaching to the video camera (10) and the adaptor housing houses the projection area (16) and a first objective lens (12).
US07719595B1 Preview mode low resolution output system and method
A processing system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA) having amplifiers of selectable current level to enable reduced data resolution in a preview display, a low power mode analog-to-digital converter (ADC) having a selectable narrow bit-width output and coupled to said VGA circuit, and a gain circuit coupled to said ADC. The single chip low-power analog front end produces digitized CCD data in either 13-bit, 12-bit or 10-bit formats at a first current level and 9-bit, 8-bit, or 6-bit formats at a second current level. The VGA amplifier includes symmetrical subcircuits which are independently actuable to enable full or reduced data resolution levels respectively for still image capture operation and video previewing on a separate preview screen.
US07719592B2 Multi junction APS with dual simultaneous integration
A new kind of pixel is formed of two floating diffusions of different sizes and different conductivity type. The two floating diffusions have different image characteristics, and hence form a knee-shaped slope.
US07719588B2 Solid-state imaging device and camera
Provided is a solid-state imaging device which is able to achieve reductions in size and in thickness of the device, while being also able to have an auxiliary function of imaging lenses, an infrared cut filter, an antireflection function, a dust preventing function for downsizing of packaging, and an infrared light imaging function for capturing images at night. The solid-state imaging device includes: a light-collecting element which collects incident light; and a transparent thin film formed above the light-collecting element, and an air gap is formed between the light-collecting element and the transparent thin film. On the transparent thin film, the auxiliary function of imaging lenses, the infrared cut filter, the antireflection function, the dust preventing function for downsizing of packaging, and the infrared light imaging function for capturing images at night are integrated.
US07719586B2 Solid-state imaging device, pixel-signal processing method, analog-signal transferring device, and analog-signal transferring method
From a pixel array where imaging pixels are arranged, pixel signals of respective columns on a selected row are read in parallel in a horizontal blanking period of a horizontal period. The pixel signals of the respective columns are output to horizontal signal lines in an effective period of the horizontal period via charge integrating amps provided respectively for the columns, i.e., provided respectively for vertical signal lines, and are thereby transferred horizontally. In the charge integrating amps, it is possible to enter a standby state while holding the pixel signals by a holding voltage. Furthermore, in the charge integrating amps, a reference potential for precharging feedback capacitors for amps at the time of a reading operation is automatically controlled based on a black level. Furthermore, pixel signals from the respective charge integrating amps are horizontally transferred in parallel using a plurality of horizontal signal lines.
US07719576B2 Method and apparatus for tagging digital photographs with geographic location data
A method and apparatus for tagging digital photographs with geographic location data is described. In one example, a digital camera includes an imaging unit, a radio frequency/intermediate frequency (RF/IF) front end, and a memory. The imaging unit is configured to generate digital photographs. The RF/IF front end is configured to receive satellite positioning system signals and generate digital samples therefrom. The memory is configured to store a set of digital samples generated by the RF/IF front end with each digital photograph generated by the imaging unit. The digital samples produced by the RF/IF front end may be intermediate frequency samples and may include both in-phase samples and quandrature samples. Notably, the memory stores digital samples of GPS signals, rather than location data. The digital GPS samples may be processed by an off-line processing unit, such as a computer, to produce location data.
US07719568B2 Image processing system for integrating multi-resolution images
The image processing system for integrating multi-resolution images mainly applies several different multi-resolution image capture devices to extract the images from the observed scene and using the multi-resolution imaging devices to present the scene images relative to the observed scenes, respectively. In order to present a seamless image according to two different-resolution image sources, the coordinate conversions among the image capture devices, and among the imaging devices are mainly applied to extract and present the entire image to be able to resemble having a single image capturing source and a single imaging source.
US07719564B2 Plug-in kiln video camera and image processing system
The present invention provides a video camera plugged into kiln to monitor and an image processing system using the camera. The video camera is composed of a camera body, a video recorder, a monitor, and a digital thermometer; the image processing system is composed of the camera body mentioned above, a computer and a color monitor. Especially, the present invention is used to monitor material surface during the smelting in a blast furnace; process the image by a computer, describing quantificationally the airflow and temperature distribution of the material surface; monitor the operation state of charging chute or bell, the material stream, and the abnormality in the furnace such as pipeline and material collapse. The advantages of the present invention: Micro camera used to obtain IR image in the furnace, pint-sized, low cost, easy installation, simple maintenance, long service life, and the maintenance performed without stopping production.
US07719560B2 Line head and imaging apparatus incorporating the same
An optical write line head includes multiple rows of light emitter devices lined up corresponding to respective positive lenses located in array form, wherein even with a fluctuation of its write plane in an optical axis direction, there is none of variations resulting from displacements of light emitting dots. A plurality of light emitter blocks, each including at least one row of light emitter devices lined up in a main scan direction, are located at a spacing in the main scan direction to define a light emitter array. On the exit side of the light emitter array, a lens array including one positive lens system in alignment with each light emitter block is located parallel with the light emitter array, and a write plane is located parallel on the imaging side of the lens array. A stop plate forming an aperture stop is located near a light-gathering position at which parallel light incident from the write plane side on each positive lens system comes together.
US07719557B2 Apparatus for providing delay signals to perform print scan line synchronization within a laser printer
An apparatus for providing delay signals to perform print scan line synchronizations within a laser printer is disclosed. The apparatus includes a voltage-control oscillator, a frequency divider and multiple output control modules. The voltage-control oscillator converts a clock signal to a higher frequency signal. The frequency divider then reduces the frequency of the higher frequency signal. Then, each of the output control modules generates a delay signal, and each of the delay signals is delayed by no more than one tenth of a clock cycle from an adjacent one of the delay signals.
US07719553B2 Exposure apparatus and image forming apparatus
An exposure apparatus comprises: a plurality of light sources; a first condensing unit, arranged to contact a light emitting surface of each of the light sources, that condenses the lights emitted from the plurality of light sources; and a second condensing unit that condenses the lights from each of the light sources, which are emitted from the first condensing unit, wherein the first condensing unit is configured so that a center of curvature of an output surface, to emit the light from the light source, of the first condensing unit is positioned near the side of the second condensing unit rather than an arrangement position of the light source.
US07719551B2 Image displaying method, image displaying device, and contrast-adjusting circuit for use therewith
A system provides an image displaying technique that provides stable high contrast even in an area having high brightness. Based on information about an average brightness level of a digital luminance signal, black-correction processing which decreases a brightness level by offsetting the brightness level to the minus side, and increase processing which increases a contrast gain within a dynamic range, are performed for an analog luminance signal or a digital luminance signal, enabling improvement in contrast even where brightness is intense.
US07719549B2 Color changing image with backlighting
The present invention provides a method of making an imaged media and a method of displaying an image, comprising the steps of providing a color image, creating a modified image by transforming a first color portion of the color image into a gray-scale portion, wherein a second color portion of said color image remains in color in said modified image, and reproducing said modified image on a fully or partially light transmitting media which can be used to display the modified image in color.
US07719543B2 Methods and apparatus for method to optimize visual consistency of images using human observer feedback
Systems and methods are provided for optimizing visual consistency for a dataset of images by using observed and formulated display attributes. The formulated display attributes are derived from an analysis of a first set of images from the image repository. The formulated display attributes from the first set are combined with observer's display attributes to determine scaling factors. The optimized display attributes are then derived from the calculated scaling factors for a second set of images. In another aspect, a system and method is described where a digital image is processed in order to enhance viewing of the image on a display device in accordance to the optimized attributes associated with the observer.
US07719536B2 Glyph adjustment in high resolution raster while rendering
Methods and apparatus, including computer program products, that implement a method for glyph adjustment in high resolution raster while rendering. In one aspect, a method includes the actions of receiving a glyph for display at a size on a raster output device; receiving a grid ratio specifying an integer number of fine pixels of a high resolution grid that correspond to a device pixel of the output device; rendering the glyph at the size on the high resolution grid; determining for each line of pixels of the high resolution grid, a line-specific, per-transition adjustment number; and in each line of pixels, marking or erasing the line-specific, per-transition adjustment number of fine pixels in the high resolution grid at each transition from a marked fine pixel to an unmarked fine pixel in a particular direction of the line of pixels.
US07719535B2 Method for displaying character strings
A system and method for translating character strings into another national language and displaying the translated character strings without updating any source code. The character strings are displayed on GUI environment upon the execution of the object computer program. The method for displaying character strings on GUI environment provided by a computer program comprises the steps of; (a) providing an executable program; (b) providing a text file including the character strings and being openable with the executable program; (c) executing the executable program (301); (d) retrieving the text file from the executable program (307); and (e) displaying the character strings included in the opened text file (315).
US07719534B2 Object association in a computer generated drawing environment
Methods and systems for associating two objects in a drawing application with one another are provided. Embodiments of the invention are directed toward a method in a computing environment that includes receiving a command to designate a target and designating the target. The method can further include identifying a subject and providing a suggested association of the subject with the target. The method can still further include receiving a command to accept the suggested association and associating the subject with the target as suggested.
US07719532B2 Efficient and flexible data organization for acceleration data structure nodes
Embodiments of the invention provide an efficient and flexible organization of data for an acceleration data structure (e.g., spatial index). In contrast to storing primitive information within a spatial index, embodiments of the invention may store pointers in the spatial index which point to or link to primitive-defining information in buffers. Storing pointers to primitive-defining information may reduce the size of the spatial index. Additionally, embodiments of the invention enable vertex and triangle sharing. Vertex and triangle sharing may reduce the amount of storage space required to define the primitives within the three-dimensional scene. Furthermore, the data organization provided by the embodiments of the invention allows for easy manipulation of the spatial index and primitive data.
US07719530B2 Image display control apparatus and image display control method
An image is moved and displayed through an image movement orbit composed of one or more annular orbits. The annular orbit is set such that a central point of the image to be displayed on a display screen is defined as a reference position, and the reference position is used as a start point, and this reference position is returned to when a movement corresponding to one round is completed. Thus, the image movement orbit is established so as to always pass through a reference point, for each cycle of an annular orbit. As a result of such image movement, the image movement as a pixel shift is unrecognizable so as to reduce ghost effects.
US07719527B2 LED control circuit for automatically generating latch signal
A control circuit for controlling an LED device according to an input data signal and a clock signal is disclosed. The control circuit includes at least one first control module. The first control module includes a shift register unit, a latch register unit, an LED driving circuit, and a latch signal generator. The shift register unit includes at least one shift register and is triggered by the clock signal for buffering data transmitted in the input data signal. The latch register unit includes at least one latch register and is triggered by a latch signal for latching data buffered by the shift register. The LED driving circuit is utilized for driving the LED device according to data latched by the latch register. The latch signal generator is used to generate the latch signal according to the input data signal and the clock signal.
US07719525B2 Electronic device
To reduce EMI and current consumption in internal wiring after display data have been input to a data driver. Display data DN/DP constituted by RSDS signals input to a data driver in a first stage are converted to display data DA constituted by CMOS signals, subjected to primary inversion control according to a data inversion signal INV generated inside, and transferred into internal wiring 31 in a data capturing circuit 30. Then, the display data are subjected to secondary inversion control by a secondary data inversion circuit 33 disposed immediately before data registers 34 according to the data inversion signal INV, and then captured by the data registers 34. Further, chip-to-chip transfer of the display data DA and the data inversion signal INV to the data drivers in second and subsequent stages is performed through the internal wiring 31 and internal wiring 32. Then, as in the data driver in the first stage, the display data DA are captured by the data registers 34.
US07719518B2 Computer peripheral device
A computer peripheral device includes a first housing, a second housing, a connecting member and a judging circuit. The connecting member is made of a conducting material and includes a rotating shaft. The second housing is rotatable relative to the first housing with rotation of the rotating shaft, so that the computer peripheral device is switched between a first configuration and a second configuration. The judging circuit includes a first conducting contact and a second conducting contact. The judging circuit activates a first function when the computer peripheral device is adjusted to the first configuration such that the first conducting contact is electrically connected to the second conducting contact through the connecting member. The judging circuit activates a second function when the computer peripheral device is adjusted to the second configuration such that the electrical connection between the first conducting contact and the second conducting contact is interrupted.
US07719516B2 Actuator having an inputting function
An actuator includes: a magnetic field generator that has different magnetic poles alternately arranged in a plane, with a predetermined position being the center of the magnetic poles; a coil holder that holds a plurality of coils that are radially arranged and face the magnetic field generator, relative motion being caused between the magnetic field generator and the coil holder; and an electromagnetic conversion unit that detects the relative motion and is mounted on either the magnetic field generator or the coil holder.
US07719515B2 Input device and I/O-integrated display
The invention concerns an input device including an input receiving panel and a stylus enabling an input, the input device sensing an input by means of capacitive coupling between a panel electrode on the input receiving panel and a stylus electrode on the stylus, and includes: a signal supply section supplying an input sensing signal to the panel electrode; a signal detecting circuit detecting a signal generated in the stylus electrode; and an input sensing section comparing the input sensing signal with the detection signal detected by the signal detecting circuit and sensing an input based on a result of the comparison. An input-sensing digital code is superimposed on the input sensing signal. This allows for further reduction in the possibility of false sensing caused by noise than conventional techniques.
US07719514B2 Apparatus and method for converting a digital video signal to conform with a display panel format
The present invention is directed to a drive apparatus adapted for driving display panel of the active matrix type, which comprises first signal processing means (3), (5), (7) for converting a digital video signal of m (m is natural number) bits which has been converted into data arrangement in conformity with the display format by data arrangement converting means (2) into parallel analog video signals of p (p is natural number)-phase, second signal processing means (4), (6), (8) for developing the analog video signals of p-phase into analog video signals of x/k (k is natural number)-phase to deliver the analog video signals thus developed to the video signal supply lines, and signal line selecting means (14) for sequentially selecting, one by one, at the same timing, desired signal lines from respective groups of the x/k number of signal lines obtained by dividing x number of signal lines to perform sampling of analog video signals delivered via the x/k number of video signal supply lines with respect to the selected signal lines.
US07719511B2 Display apparatus with dynamic blinking backlight and control method and device thereof
A display apparatus with dynamic blinking backlights, a control method and a device thereof are provided. The dynamic blinking backlight control method for dynamically controlling the lighting status of the backlights of the display panel includes the following steps. First, the motion condition of a frame to be displayed on the display panel is detected for obtaining a motion detection result. The scanning frequency is determined in accordance with the motion detection result. Also, the lighting status of the backlights is controlled sequentially and respectively in accordance with the determined scanning frequency.
US07719506B2 Display device and driver
A display device includes a display panel including a bus line section; and at least one driver for driving the bus line section included in the display panel. Each of the at least one driver includes an amplifier for generating a non-driving signal based on an input signal, the non-driving signal not contributing to driving of the bus line section.
US07719504B2 Liquid crystal display and driving method thereof
A liquid crystal display and a driving method thereof. A gate driver drives a first pixel of the display via a first scanning line within a frame period including first and second data writing intervals. A first data voltage and a second data voltage are transmitted to the first pixel in the first and second data writing intervals, respectively. After the first data writing interval, a first color light source illuminates the first pixel. After the second data writing interval, a second color light source illuminates the first pixel. In a reset interval between the first and second data writing intervals, a voltage of a common line coupled to a storage capacitor of the first pixel is changed from a first common voltage to a second common voltage so that a voltage of a first liquid crystal capacitor of the first pixel is changed.
US07719499B2 Organic electronic device with microcavity structure
A multi-color pixel array and method includes an organic active layer of a material emitting a first spectral distribution of visible light having a first color; a transparent conducting layer, each of which include portions that correspond to individual pixels and sub-pixels of the array; one or more pairs of electrodes for selectively energizing sub-pixel areas of the organic active layer to generate an emission of visible light of a first spectral distribution; wherein different sub-pixels within individual pixels of the array have different optical thicknesses based at least on corresponding sub-pixel portions of the transparent conducting layer having different optical thicknesses; and wherein at least one sub-pixel of has a selected color different from the first color due to at least one narrowed spectral band being selected out of the first spectral distribution as emitted light is coupled out of the display through the transparent conducting layer.
US07719497B2 Current feedback-type AMOLED where sense feedback is sent over the adjacent data line
A current feedback-type AMOLED driving circuit. The current feedback-type AMOLED driving circuit includes a plurality of pixel circuits each having a data terminal for receiving a pixel current command, and a sense terminal for transmitting pixel current to a driver Integrated Circuit (IC), and a plurality of data lines provided such that a single data line is provided for a single column formed by a plurality of pixel circuits, thus data terminals of the pixel circuits, forming the column, are connected to the data line. In the AMOLED driving circuit, two columns are paired, sense terminals of pixel circuits, forming a first column of the two columns, are connected to a data line for a second column, and sense terminals of pixel circuits, forming the second column, are connected to the data line for the first column. The AMOLED driving circuit is operated such that, when the first column is driven, the data line for the second column is used as a current feedback line for the first column, and when the second column is driven, the data line for the first column is used as a current feedback line for the second column. Accordingly, the number of pads of the driver IC is limited to one per column, and price competitiveness of the driver IC is improved.
US07719495B2 Organic light emitting diode display device and driving method thereof
An organic light emitting diode display device capable of reducing power consumption by limiting a current to lower the total luminance if an area exhibiting a high luminance is larger than a threshold, and a driving method thereof are disclosed. The device includes a luminance controller for controlling an emission time of the pixel unit by determining a luminance limit of the pixel unit corresponding to a sum of the values of the video data input into one frame; and a power source controller for controlling driving of the luminance controller to correspond to the luminance limit of the pixel unit.
US07719494B2 Brightness adjustment circuit and electroluminescent display using the same
A brightness adjustment circuit for an electroluminescent display is provided. The brightness adjustment circuit is electrically connected to an electroluminescent panel and a power supply. The brightness adjustment circuit provides a feedback voltage to the power supply. The power supply provides a working voltage to the electroluminescent panel in response to the feedback voltage. The brightness adjustment circuit includes a circuit module and a switch or a circuit module and a voltage supply unit. The feedback voltage is modulated by operating the switch in accordance with a control signal or by a control voltage provided by a voltage supply unit.
US07719489B2 Driving waveform and circuit for plasma display panel
A driving circuit, which can realize the driving waveforms for a PDP without staying at ground potential includes having one side, the X side, of an panel equivalent capacitor Cp of the PDP coupled directly to ground with the Y side of the equivalent capacitor having a Scan IC 99 connected to a plurality of switches, each switch coupled to a different voltage source. One of the switches is bi-directional and coupled to ground.
US07719488B2 Set-up voltage generating circuit and plasma display panel driving circuit using same
A set-up voltage generating circuit for a plasma display panel (PDP) is disclosed. The circuit is capable of generating a set-up voltage by way of a method of charging a predetermined capacitor using a sustain voltage Vs without recourse to a DC/DC converter in forming a set-up voltage necessary for a set-up period of the PDP. As a result, the circuit is simple in its structure and a manufacturing cost thereof can be reduced because there is no need for a DC/DC converter for supplying a set-up voltage.
US07719487B2 Method for driving a gas electric discharge device
A method of driving a gas discharge device for displaying a frame with gradation. A charge producing voltage and a charge adjusting voltage are successively applied in an address preparation period to respective subfields.
US07719485B2 Plasma display apparatus and driving method thereof
The present invention relates to a plasma display apparatus and driving method thereof, and more particularly, to a plasma display apparatus implementing gray levels and driving method thereof. The plasma display apparatus according to the present invention comprises a plasma display panel in which a plurality of scan electrodes and a plurality of sustain electrodes are formed on a substrate, drivers for driving the plurality of the scan electrodes and the sustain electrodes, and a sustain pulse controller for controlling the drivers to set a total number of sustain pulses applied to the scan electrodes and the sustain electrodes to be at least one or more of a plurality of sub-fields in which a sub-field having an odd number constitutes one frame. The present invention can implement a finer gray level. Accordingly, half-tone noise when implementing a low gray level can be reduced and the picture quality can be improved.
US07719481B2 Resolution reduction technique for displaying documents on a monitor
A method of generating an output image having a lower resolution than that of a source image is provided. A thinned image is generated by discarding outer pixels of the source image. In parallel with generation of the thinned image, an averaged image is generated, such that each pixel of the averaged image represents an average of a subset of pixels in the source image. A first output image is then generated by subsampling the pixels of the thinned image. A final output image is generated as a function of both the first output image and the averaged image.
US07719479B2 Antenna array
An antenna array includes five grounding plates, a signal transmission part, two radiation conductors, and a signal feed cable. The first and fifth grounding plates located at the same plane are substantially perpendicular with the second and fourth grounding plates respectively. The second and fourth grounding plates respectively connected to the first and fifth grounding plates extend with the same direction and have two holes or grooves. The third grounding plate connected between the second and fourth grounding plates is substantially perpendicular with the second and fourth grounding plates. The signal transmission part passing through the two holes or grooves is substantially perpendicular with the second and fourth grounding plates. The signal transmission part is connected between the two radiation conductors. The signal feed cable includes a central conductor connected to the signal transmission part and an outer conductor connected to the third grounding plate.
US07719476B2 Complex antenna with protection member
A complex antenna adapted for used in a electronic device, comprises a rod antenna, a helical antenna, a dipole antenna comprising a radiating element and a grounding element, and a feeding line. The feeding line comprises an inner conductor electrically connecting to the radiating element at a first joint position and an outer conductor electrically connecting to the grounding element at a second joint position. The first joint position is tightly covered by a insulating tubular element for avoiding to be destroyed and oxidized.
US07719474B2 Antenna Structure with fixing unit
An antenna structure includes a substrate, a signal transmission unit and at least one fixing unit. The substrate is made of a dielectric material and has at least a through hole. The signal transmission unit has a transmission path and goes through the through hole. The fixing unit is made of a flexible or deformable material, and is in contact with the signal transmission unit and the inner surface of the through hole to fix the signal transmission unit on the substrate.
US07719472B2 Antenna unit, wireless communication structure, and antenna structure
There is provided an antenna unit including a non-conductive base film, an endless conductive flat plate member attached onto one surface of the base film and having an opening in a center thereof, and an antenna attached to the one surface of the base film so as to be positioned in the opening of the conductive flat plate member with a gap formed between the antenna and an inner circumferential edge of the conductive flat plate member.
US07719470B2 Multi-band antenna, and associated methodology, for a radio communication device
An antenna, and an associated methodology, for a portable radio device, such as a mobile station capable of operation at a plurality of frequency bands spread across a wide range of frequencies. The antenna includes a first antenna patch and a second antenna patch. The first antenna patch comprises an L-shaped patch disposed upon a substrate. A second antenna patch forms a folded patch formed of three contiguous portions, folded about fold lines in a manner to cause the second antenna patch to include a first contiguous portion that extends upwardly beyond the first antenna patch at an angle perpendicular thereto. Second and third contiguous portions are formed by folding additional portions of the second antenna patch about additional fold lines.
US07719469B2 Device and method for position measurement by means of linear doppler shifts generated
A position determination method including a step of transmitting a periodic signal having a carrier frequency, a step of sequentially receiving the periodic signal having the carrier frequency at various locations using at least one antenna, and a step of determining a first coordinate of the object location on the basis of a zero crossing of a Doppler frequency response which may be associated with the first coordinate of the object location, the first coordinate of the object location corresponding to a coordinate of that location of the at least one antenna which it has when receiving the periodic signal at the zero crossing in relation to the object location.
US07719468B2 Terminal device, method of controlling terminal device, and recording medium
A terminal device searches for a satellite signal by performing a correlation process over a predetermined first accumulation time within a predetermined frequency range in units of search frequencies at specific intervals. When the terminal device has failed in searching for the satellite signal, the terminal device searches for the satellite signal by performing the correlation process over a predetermined second accumulation time longer than the first accumulation time at the search frequency and frequencies differing from the search frequency by a specific frequency which is less than the interval of the search frequencies and specified based on a drift of a reference oscillator of the terminal device within the second accumulation time. The terminal device determines a search result of the satellite signal based on a search result at the search frequency and search results at the frequencies differing from the search frequency by the specific frequency.
US07719466B2 Communications systems that reduces auto-correlation or cross-correlation in weak signals
The present invention discloses methods, apparatuses, and systems for eliminating auto- and cross-correlation in weak signal CDMA systems, such as GPS systems. The invention uses parallel data paths that allow standard correlation of signals in parallel with verification of the lock signal to determine whether the system has locked onto the proper signal within the scanned signal window. The invention can be made with multiple CPUs, a single CPU with dual input modes, on multiple IC chips, or as a single IC chip solution for small, low cost reception, downconversion, correlation, and verification systems.
US07719465B2 Method of acquiring initial GPS signal in broadcasting system and system using the method
A system and method for acquiring an initial Global Positioning System (GPS) signal in a communication system including a terminal. The system includes an Assisted GPS (AGPS) server for generating Acquisition Assistance (AA) data distinguished according to an area based on a pre-set position of each service area, a transmitting station for broadcasting the generated AA data to terminals, and the terminals for acquiring an initial GPS signal by receiving the broadcasted AA data. In addition, the method includes the steps of generating AA data distinguished according to an area based on a pre-set position of each service area, broadcasting the generated AA data to terminals, and acquiring, by each of the terminals, a GPS signal by receiving the broadcasted AA data.
US07719464B2 System and method for providing aided GPS positioning via satellite digital radio system
A system and method for providing aiding information to a satellite positioning system (“SPS”) receiver. A digital satellite radio system satellite receives aiding information communicated from a positioning system. The digital satellite radio system broadcasts the aiding information in the data signals it broadcasts to its subscribers. The subscribers receive the aiding information at satellite radio receivers and communicate the aiding information to the SPS receiver. The data signals may also be communicated to terrestrial repeaters for re-broadcast at a higher power. The terrestrial repeaters may input a transmitter identifier to permit the satellite radio receiver to determine a geographical location of the terrestrial repeater as its own.
US07719461B1 Track fusion by optimal reduced state estimation in multi-sensor environment with limited-bandwidth communication path
The invention, called “ORSE Track Fusion”, combines sensor tracks from dispersed sites, when limited communication bandwidth does not permit sharing of individual measurements. Since estimation errors due to maneuver biases are not independent for each sensor, optimal fusion of tracks produced by Kalman filters requires transmission of all the filter gain matrices used to update each sensor track prior to the fusion time. For this reason, prior art has resorted to suboptimal designs. ORSE Track Fusion according to aspects of the invention overcomes this disadvantage by propagating, transmitting, and fusing separately calculated covariance matrices for random and bias estimation errors. Furthermore, with ORSE, each sensor can have its own criteria in forming its track, and track fusion can be performed with different criteria at each processing site. Thus, ORSE Track Fusion has the unique flexibility to optimize track fusion simultaneously for multiple criteria to serve multiple users.
US07719460B1 Radar device
In a radar device including a transmitting unit for transmitting a transmission signal having plural modulation sections, a receiving unit for receiving a reflection signal obtained through reflection of the transmission signal from a target by an array antenna having plural channels, a mixing unit for mixing the transmission signal with reception signals of the plural channels to obtain beat signals of the plural channels, a frequency analyzing unit for frequency-analyzing the beat signals of the plural channels, and a direction calculating unit for calculating the direction to the target on the basis of frequency analysis results of the plural channels, the direction calculating unit adds correlation matrixes generated from peak frequency spectra of the plural modulation sections to obtain an summed correlation matrix, and calculating the direction to the target on the basis of the summed correlation matrix.
US07719457B1 Digitally tuned digital radio frequency memory
A digitally tuned digital radio frequency memory that captures a portion of a first radio frequency signal and retransmits the portion as a coherent radio frequency signal. The digitally tuned radio frequency memory may include a track and hold configured to track and hold the first radio frequency signal and to output a shaped signal; a digitizer configured to convert the shaped signal to a digital word; a memory configured to store the digital word; and a direct digital frequency synthesizer configured to provide a sampling clock signal, wherein the sampling clock signal is provided to the track and hold.
US07719454B2 Logical current division multiplexing for encoding multiple digital signals
A method and a system are disclosed for transmitting an N-bit digital signal at a source. The N-bit digital signal representing a binary value is used to modulate an electrical current by using N discrete voltages representing each bit. The N discrete voltages are coupled to N corresponding switches to control the switches. The switches conduct a corresponding electrical current if the value of the corresponding discrete voltage is the binary value of 1. The currents from each of the closed switches are summed to form a current-encoded data signal in a single physical conductor representing the original N-bit digital signal. The current-encoded data signal is transmitted through the single physical conductor to a current decoder for decoding the current-encoded data signal and extracting the original N-bit digital signal at a destination.
US07719450B2 Device for the parallel-serial conversion of several signal parameters each detected by a detector
A device for parallel-serial conversion of several evaluation parameters determined respectively by a detector from detected signal values. The device includes a primary buffer memory for the synchronized buffering of each determined evaluation parameter, a synchronization unit for the generation of a synchronization signal for the synchronized buffering and a unit for the serial readout of the evaluation parameters stored in a synchronized manner in the primary buffer memory. A synchronization signal generated by the synchronization unit is derived from a release signal which provides the highest data rate of all the release signals associated respectively with the determined evaluation parameters.
US07719442B2 Multi-mode multi-parallelism data exchange method and device thereof
A multi-mode multi-parallelism data exchange method and the device thereof are proposed to apply to a check node operator or a bit node operator. The proposed method comprises the steps of: duplicating part or all of an original shift data as a duplicated shift data; combining the original shift data and the duplicated shift data to form a data block; and using a data block as the unit to shift this data block so as to conveniently retrieve shift data from the shifted data block. With a maximum z factor circuit and duplication of part of data, specifications of different shift sizes can be supported. The functions of shifters of several sizes can therefore be accomplished with the minimum complexity.
US07719434B2 Method for identifying critical features as a function of process
The method for identifying critical features as a function of process provides a way to identify critical features associated with a particular part, and to relate the effect of performing repair processes on the identified critical features. The method includes identifying critical features associated with the part, and determining the effect repair processes will have on the identified critical features. This information is included in a an output that is made available to repair centers. Based on the identification of critical features and the associated effect of repair processes on the identified critical features, repair centers are able to focus process and quality control resources on the identified critical features affected by a particular repair process.
US07719432B1 Long range, battery powered, wireless environmental sensor interface devices
Long range, battery powered, wireless environmental sensor interface devices that can be connected to a plurality of sensors and wirelessly communicate the sensor readings back to a central collection device or Internet terminal. Instead or additionally, sensors can be integrated with the device for added efficiency. The devices incorporate a rugged enclosure and an internal power supply that allows them to be placed in harsh environmental conditions and operate for multiple years without maintenance due to unique power-saving design features. The RF circuitry is specially optimized for long-range outdoor communications of small quantities of data. Line-of-sight communication range of several miles is possible with this device. Various embodiments are disclosed.
US07719425B2 Radio frequency shielding
Shielding is associated with RFID tags to achieve new systems and methods having various advantages. These systems include containers configured to store RFID enabled identity documents, the use of RFID tags to monitor the state of a container, and the inclusion of shielding in identity devices. Disclosed are shielded passports, driver's licenses, and the like. Some embodiments further including reading systems for reading identity devices comprising shielding and RFID tags.
US07719424B2 Table monitoring identification system, wager tagging and felt coordinate mapping
A table monitoring system and method for monitoring a table games. In one embodiment, the system comprises an RFID system and a processing engine. The system may include a camera, and image controller, or both. The system creates RFID data and image data in response to table events and its processing engine cross-references this data with time stamps to monitor table events such as wagers, payouts, or other occurrences. The data is associated with a tag which represents a table event. Table events are tracked during play. In one embodiment, the RFID data and image data is mapped to a coordinate grid. With the coordinate mapping and by cross-referencing this data, the system can distinguish individual table events occurring within the detection zone of a single RFID antenna such as distinguishing wagers placed on multiple bet locations within the detection zone of a single antenna.
US07719418B2 System and method for locating objects
A system and method for locating objects in an approximate immediate proximity to a user is disclosed. A two-way radio transponder system is employed with a Coordinator as a parent device and multiple Identification Tags as child devices. The system is low-cost and consumes relatively low power using advancement in microcircuit technology and additionally the system employs predetermined timing cycles to further optimize power consumption. The Coordinator has a microprocessor programmed to compare signal strength in successive communication cycles to help determine the proximity of the Coordinator to the multiple Identification Tags. Additionally, in a preferred embodiment, motion sensors are used to assist in determining relative motion between Coordinator and Identification Tags. A USB port is further included for the system to interface with a PC. A method for associating the various Identification Tags, each having a unique electronic address to all others manufactured, with the particular Coordinator is also disclosed.
US07719417B2 Portable terminal and information provision system utilizing the portable terminal
A portable terminal comprising a transmission part that transmits to information provision equipment or a server, a signal indicating presence at a prescribed location, presence of a communications counterparty at a prescribed location, a reception part that receives from the information provision equipment or the server, a signal indicating the position of a moving body, a moving body is approaching or is present at the prescribed location, an alarm part that issues an alarm using the moving body in position signal received at the reception part, indicating the moving body is approaching or is present at the prescribed location, a light detection part detecting the degree of brightness, a part deciding whether or not to transmit a present in prescribed location signal that decides, using the brightness as detected by the light detection part, whether or not to send a present in prescribed location signal from the transmission part.
US07719413B2 Occupant detection system and occupant protection system
An occupant detection system includes occupant sensors on each of plural seats, first resistors in connection to each of the occupant sensors with different resistance values, a power supply line that supplies electric power to the sensors and resistors from a power source by connecting those parts and the power source, and a control unit that detects occupancy of each of the plural seats based on an electric current value of the power supply line. The occupant detection system having the above configuration detects the occupancy of each of the plural seats without increasing the number of input terminals on the control unit.
US07719405B2 Crosspoint switch with low reconfiguration latency
A method of operating a circuit for processing a digital signal is disclosed. The circuit includes various circuit stages having respective enabled states. A present signal path is established which includes circuit stages in their respective enabled states. Power is disabled to selected circuit stages not used in the present signal path so as to minimize power consumption in the disabled circuit stages. A data signal is then processed through the circuit stages in the present signal path. Before a next signal path is needed, power is re-enabled to selected disabled circuit stages in the next signal path to allow the enabled circuit stages to approach their respective enabled states. Then the next signal path can be established including the enabled circuit stages in their respective enabled states. The data signal can then be processed through the circuit stages in the next signal path.
US07719404B2 Temperature detector/indicator
The invention relates to an electrical and/or optical temperature detector/indicator based on conductive polymers, said detector/indicator being suitably used in such packages for products, the temperature changes of which need to be monitored.
US07719399B2 Laminated coil component
A laminated coil component includes high-magnetic-permeability ferrite layers that are disposed on both main surfaces of a low-magnetic-permeability ferrite layer. Pores or pores filled with a resin are formed in the low-magnetic-permeability ferrite layer. Nickel in the high-magnetic-permeability ferrite layers does not significantly diffuse into the pores or the pores filled with the resin during firing, and thus, Ni does not readily diffuse into the low-magnetic-permeability ferrite layer.
US07719398B2 Laminated coil
A laminated coil includes a laminated body having magnetic body sections that are provided on both main surfaces of a non-magnetic body section and include a plurality of stacked magnetic layers, the non-magnetic body section including at least one non-magnetic layer, and a coil including helically connected coil conductors provided in the laminated body. The conductor width of at least one of the coil conductors provided inside the non-magnetic body sections and the coil conductors provided on both main surfaces of the non-magnetic body sections is greater than the conductor width of the other coil conductors in the laminated body.
US07719392B2 Ferroelectric varactors suitable for capacitive shunt switching
A ferroelectric varactor suitable for capacitive shunt switching is disclosed. High resistivity silicon with a SiO2 layer and a patterned metallic layer deposited on top is used as the substrate. A ferroelectric thin-film layer deposited on the substrate is used for the implementation of the varactor. A top metal electrode is deposited on the ferroelectric thin-film layer forming a CPW transmission line. By using the capacitance formed by the large area ground conductors in the top metal electrode and bottom metallic layer, a series connection of the ferroelectric varactor with the large capacitor defined by the ground conductors is created. The large capacitor acts as a short to ground, eliminating the need for vias. The varactor shunt switches can be used to create a bandpass filter and a tunable notch filter. The bandpass filter is implemented by cascading the switches, and the bandpass filter implemented through the use of a resonance circuit.
US07719383B2 High isolation electronic multiple pole multiple throw switch
A high isolation electronic multiple pole multiple throw (MPNT) switching device is formed as a ring circuit that includes plural poles, plural throws, plural series switches and plural means for shunting. Each series switch receives a control signal, and each means for shunting receives shunt control signals. In one aspect, the shunt control signals include control signals received by distant series switches. In another aspect, the shunt control signals include control signals received by adjacent series switches. In another aspect, the shunt control signals include signals complementary to signals received by adjacent series switches. In another aspect, the shunt control signals include pole DC potentials or throw DC potentials. In another aspect, a switching device may operate in multiple transmission mode or multiple input multiple output (MIMO) mode. The MPNT switching device provides low insertion loss and high isolation at a wide range of frequencies.
US07719382B2 Low-loss tunable radio frequency filter
A tunable radio frequency (RF) filter is provided. The RF filter comprises a signal transmission path having an input and an output, a plurality of resonant elements disposed along the signal transmission path between the input and the output, and a plurality of non-resonant elements coupling the resonant elements together. The resonant elements are coupled together to form a stop band having a plurality of transmission zeroes corresponding to respective frequencies of the resonant elements, and at least one sub-band between the transmission zeroes. The non-resonant elements comprise at least one variable non-resonant element for selectively introducing at least one reflection zero within the stop band to create a pass band in one of the sub-bands(s). The variable non-resonant element(s) may be configured for displacing the reflection zero(es) along the stop band to selectively move the pass band within the one sub-band or within selected ones of the sub-bands.
US07719379B2 High speed electronics interconnect having a dielectric system with air holes of varying diameters and spans
Fundamental interconnect systems for connecting high-speed electronics elements are provided. The interconnect systems consists of signal line, dielectric system with open trench or slot filled up with air or lower dielectric loss material, and the ground plane. The signal line could be for example, microstripline, strip line, coplanar line, single line or differential pairs. The interconnect system can be used for on-chip interconnects or can also be used for off-chip interconnects. The fundamental techniques provided in this invention can also be used for high-speed connectors and high-speed cables.
US07719373B2 Device and method for generating a signal with predefined transcient at start-up
A device and a method are presented for generating an intermitted oscillating signal comprising a plurality of oscillating portions separated from each other in time. The device and method are suited for communication systems, in particular for Ultra-Wide Bandwidth (UWB) applications. The device comprises a variable oscillator for generating the oscillating portions; switching circuitry for switching on/switching off the variable oscillator at the beginning/end of each oscillating portion; and circuitry for setting initial conditions in the variable oscillator to impose a predefined transient and a characterizing frequency upon each start-up.
US07719372B2 Voltage controlled piezoelectric oscillator that can be linear frequency controlled
A variable capacitance unit that configures a voltage controlled piezoelectric oscillator including a first variable capacitance diode, a first condenser connected in parallel with the first variable capacitance diode, the second variable capacitance diode, a second condenser inserted and connected between a cathode of the first variable capacitance diode and an anode of the second variable capacitance diode, a third condenser inserted and connected between an anode of the first variable capacitance diode and a cathode of the second variable capacitance diode. The external control voltage is applied to the first variable capacitance diode and the second variable capacitance diode so that respective polarities thereof are reversed.
US07719367B2 Automatic frequency calibration
Disclosed is a system and method for providing an oscillating signal of relatively precise frequency without using a signal provided by a crystal as a reference. Disclosed is a feedback oscillator circuit configured to output an oscillating signal having a frequency defined by a reference signal. The oscillating signal can be sent to one or more circuits including at least one frequency sensitive element. The frequency sensitive element produces an output signal which depends on the frequency of the oscillating signal. A controller controls the reference signal in order to cause an attribute of the output signal to have a value within a desired range.
US07719366B2 PLL circuit
Disclosed herein is a phase lock loop (PLL) circuit capable of executing digital control of an oscillation circuit thereof by using a dividing ratio represented by a digital value obtained by dividing an oscillation frequency by a reference frequency. The PLL circuit includes a phase comparator for comparing the digital value obtained by converting the dividing ratio with a digital value representing each cumulative addition value of a clock count expressed in a decimal-point format representing the oscillation signal in each period of a reference signal, a loop-gain control section configured to control the loop gain of the PLL circuit, and an output converging section configured to converge an output by the phase comparator.
US07719365B2 Method and apparatus for reducing silicon area of a phase lock loop (PLL) filter without a noise penalty
In a method and system for filtering an input signal with a filter included in a phase locked loop (PLL), a unidirectional feedback path is configured from an output of the filter to an input of the filter. The unidirectional feedback path includes a feedback resistor that is configured to adjust a bandwidth of the PLL. A zero path is configured from the output to a voltage reference, such as ground. The zero path includes a capacitor coupled in series with a bias resistor. The bias resistor, which along with the capacitor determines a zero frequency of the filter, is configured to reduce a value of the capacitor without a substantial increase in a phase noise of the PLL due to the unidirectional nature of the feedback. A reduction in the value of the capacitor enables a corresponding reduction in a silicon area to form the capacitor.
US07719363B2 Method and apparatus for output amplifier protection
An amplifier circuit includes a first circuit and a second circuit connected in series. The first circuit has a first terminal coupled to a first power supply terminal, a second terminal coupled to an output node, and a control terminal for receiving a first signal for controlling a current flow. The second circuit has a first terminal coupled to the output node, a second terminal couple to a second power supply terminal, and a control terminal for receiving a second signal controlling a current flow in the first circuit. A bias circuit is coupled to the third terminal of the first circuit and is configured to limit a current flow in the first circuit when a voltage at the output node is outside a predetermined voltage range. In an embodiment, the bias circuit includes a plurality of diode devices connected in series and a switch device coupled to the diode devices.
US07719361B2 Differential amplifier with current source controlled through differential feedback
A differential amplifier includes a first electrical path formed between a first transistor and a first load impedance; a second electrical path formed between a second transistor and a second load impedance; a tail-current transistor coupled to the first and second transistors; an input end of a feedback amplifier coupled directly to the first and second electrical paths for receiving a differential voltage output signal; and an output end of the feedback amplifier coupled directly to the tail-current transistor for adjusting the current provided through each of the first and second electrical paths. The feedback amplifier includes a non-inverting input node and an inverting input node, each node coupled directly to one or the other of the first and second electrical paths.
US07719360B2 Variable gain circuit
Disclosed is a variable gain circuit, which operates in a region where the gain varies substantially exponentially with respect to a control voltage, having an operation region in which the gain varies substantially with an exponential function {(√{square root over (1−x)}−√{square root over (2)})2+K}/{(√{square root over (1+x)}−√{square root over (2)})2+K} where 0≦K≦1 and x is a variable corresponding to the control voltage. The denominator and the numerator of the above function are given by a first sum current and a second sum current, respectively. The first sum current is a sum of the drain current of a first transistor and a constant current, and the second sum current is a sum of the drain current of a second transistor and the constant current. The first and second transistors have sources grounded, having gates connected common and supplied with a bias voltage, and having back-gates supplied with control voltages differentially.
US07719358B2 Low frequency analog circuit and design method thereof
A low frequency analog circuit and a method for designing the same are provided. In a low frequency analog circuit according to the present invention, a part of MOS transistors employed in the circuit are operated at a weak inversion region.
US07719357B2 Differential amplifier with a plurality of input pairs
The present invention provides a differential amplifier with a plurality of input pairs. The differential amplifier not only includes a differential amplifier with a single input pair but also includes a pair of transistors and a current source to provide the input signals of an extra input pair. The pair of transistors and the differential amplifier with a single input pair share a same load unit. In addition, by using control signals to control the on/off state of each current source, the input signals of the plurality of input pairs are switched, and thereby improve the signal quality. Thus, the need of an additional electrostatic discharge device (ESD device) may be avoided, and thereby reduce cost.
US07719345B2 Reference buffer circuits
A reference buffer circuit is disclosed, providing a reference voltage at an output node and comprising a closed-loop branch comprising an amplifier and first and second MOS transistors and an open-loop branch comprising third and fourth MOS transistors and a tracking circuit. The first MOS transistor has a gate coupled to an output terminal of the amplifier and a source coupled to a negative input terminal of the amplifier. The second MOS transistor is coupled to the source of the first MOS transistor. The third MOS transistor has a gate coupled to the output terminal and a source coupled to the output node. The fourth MOS transistor has a drain coupled to the source of the third MOS transistor. A gate voltage of the fourth MOS transistor tracks a drain voltage of the third MOS transistor through the tracking circuit.
US07719340B2 Internal voltage trimming circuit for use in a semiconductor memory device and method thereof
An internal power voltage trimming circuit and its method individually or simultaneously perform level trimming for a plurality of power voltages in a semiconductor memory device. The internal power voltage trimming circuit includes a trimming control signal generator for generating a trimming selection signal and a trimming enable signal by using an inputted address signal, and an internal power voltage level controller for controlling the levels of the internal power voltages by using the trimming selection signal that is outputted under control of the trimming enable signal.
US07719339B2 Circuit arrangement and method for limiting a signal voltage
The invention relates to the field of signal processing. It is an object of the invention to provide for limitation of a signal voltage to a predetermined maximum voltage (Vmax). To this end, an input signal (Vin) is applied to a voltage divider which includes a variable-resistance component (T1) whose resistance is controlled by a control signal. An output signal (Vin′) is picked-up at the variable-resistance component (T1). The control signal is generated as an amplified difference between the output signal (Vin′) and a fixed reference voltage (Vmax/2), so that for an “overvoltage case” in which the value of the input signal (Vin) exceeds that of a predetermined maximum voltage (Vmax) the output signal (Vin′) is kept substantially constant.
US07719336B2 Pulse width modulation sequence maintaining maximally flat voltage during current transients
A digital circuit implementing pulse width modulation controls power delivered in what one can model as a second order or higher order system. An exemplary control plant could embody a step-down switch mode power supply providing a precise sequence of voltages or currents to any of a variety of loads such as the core voltage of a semiconductor unique compared to its input/output ring voltage. One of several algorithms produce a specific predetermined sequence of pulses of varying width such that the voltage maintains maximally flat characteristics while the current delivered to the load from the system plant varies within a range bounded only by inductive element continuous conduction at the low power extreme and non-saturation of the inductor core at the high power extreme. The specific pulse width modulation sequence controls a plant such that the voltage maintains maximally flat characteristics in one embodiment without a feed-forward or feedback loop physically embodied in the control system thereby reducing the parts cost or control semiconductor production yield cost while enhancing noise immunity and long term reliability of the control system. Several specific algorithms maintain maximally flat voltage despite extreme load variations therewith control plant element parameters otherwise exacerbating excessive voltage fluctuation during the given current transients.
US07719334B2 Apparatus and method for multi-phase clock generation
An apparatus and method for multi-phase clock generation are disclosed. One embodiment of the apparatus includes a clock divider generating first and second intermediate signals having edges delayed from first edges of a clock signal having a first frequency. Each of the first and second intermediate signals has a second frequency that is half of the first frequency. The first and second intermediate signals have a phase difference of 180° from each other. The apparatus also includes a first delay element delaying the first intermediate signal by a first delay amount; a second delay element delaying the first intermediate signal by a second delay amount; a third delay element delaying the second intermediate signal by a third delay amount; and a fourth delay element delaying the second intermediate signal by a fourth delay amount. The third delay amount is equal to the first delay amount. The fourth delay amount is equal to the second delay amount. The apparatus also includes a delay detection loop to adjust the second and fourth delays.
US07719333B2 Power control circuit, method of controlling power control circuit, and DLL circuit including power control circuit
A power control circuit includes a check unit that receives a reference clock and generates a check signal for cyclically activating a feedback loop of a DLL circuit, a phase detecting unit that detects a phase difference between the reference clock and a feedback clock, and generates a phase difference detection signal, and a signal combining unit that generates a power cutoff signal in response to a locking completion signal, the check signal, and the phase difference detection signal.
US07719331B2 PLL circuit
Disclosed is a PLL circuit including a phase frequency detector (PFD) for comparing phase and frequency between an input signal and an output signal, a charge pump circuit for charging a capacitor when an up-signal from the PFD is activated, discharging the capacitor when a down-signal is activated, and for outputting the terminal voltage of the capacitor as a control voltage, and a VCO for outputting an output signal of a frequency in accordance with the control voltage. An output of the VCO is fed back as an output signal to the PFD as input. The PFD includes a delay adjustment circuit for exercising control for resetting the up-signal and the down-signal with a preset delay as from a time point both up-signal and the down-signal have been activated. There is also provided a comparator amplifier circuit for comparing a reference voltage, corresponding to a control voltage when both up-signal and down-signal are activated, to supply first and second control signals to the delay adjustment circuit. The pulse widths of up and down-signals are adjusted depending on current offset characteristics of the charge pump circuit.
US07719330B2 Phase locked loop device and control method thereof
A phase locked loop device is provided. The phase locked loop device includes a phase/frequency detector, a charge pump, a low pass filter, a voltage-controlled oscillator, and a control unit. The phase/frequency detector generates a compared signal corresponding to a phase difference between a reference clock signal and a feedback clock signal. The charge pump coupled to the phase/frequency detector generates a pump current according to the compared signal. The low pass filter coupled to the charge pump generates an operating voltage corresponding to the pump current. The voltage-controlled oscillator coupled to the low pass filter generates an output clock signal in response to the operating voltage. The control unit coupled to the low pass filter and the voltage-controlled oscillator constrains the operating voltage to a predetermined voltage level when the frequency of the output clock signal is out of a predetermined frequency range.
US07719319B2 Semiconductor integrated circuit
In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value is selected using a selection signal, a first node N1 is L, a second node N2 of a second dynamic circuit is H, so that an output signal has an H level. In this case, when none of a plurality of pieces of data is selected using a selection signal, the first node N1 is H, so that the electric charge of the second node N2 is discharged and the output signal erroneously has an L level. However, in this case, an output node N3 is H and a fourth node N4 is L, so that an n-type transistor of the second dynamic circuit is turned OFF, thereby preventing the second node N2 from being discharged. Therefore, a normal operation is performed while securing a satisfactorily high-speed operation even when none of the pieces of data is selected.
US07719317B2 Clock distribution network architecture with resonant clock gating
Disclosed herein is a digital system that includes a distribution network to carry a reference clock, and a circuit domain coupled to the distribution network to receive the reference clock for synchronous operation in accordance with the reference clock. The circuit domain includes a clock generator driven by the reference clock to generate a resonant clock signal, an input port to receive a control signal, and a gate coupled to the input port to discontinue application of the resonant clock signal within the circuit domain based on the control signal.
US07719310B2 Semiconductor integrated circuit device and method for manufacturing the same
A circuit for attaining reduction in AC noise on power supply line caused by IR drop upon use of a decoupling capacitor represented by a cross-coupled decoupling capacitor with enhanced resistance to electrostatic breakdown, required in the case of a process of a high technology. There is also provided a circuit for suppressing the AC noise on power supply line due to resonance. MOS transistors composing the cross-coupled decoupling capacitor with enhanced resistance to electrostatic breakdown are caused to have lower threshold voltages Vth, thereby reducing a resistance between a source and a drain of each of the MOS transistors, resulting in reduction in IR drop. Further, a damping resistance is effective for suppressing the AC noise on power supply line, and the source-to-drain resistance of each of the MOS transistors is utilized as the damping resistance. At this point in time, a resistance value as desired is attained through combination of decoupling capacitors having threshold voltages Vth differing from each other.
US07719308B2 Semiconductor apparatus, on-die termination circuit, and control method of the same
An on-die termination circuit of a semiconductor apparatus can include: a code converting unit configured to change a code value of a termination code in response to a termination control signal; and a plurality of on-die termination blocks configured to commonly receive the termination code, and perform a termination operation.
US07719307B2 Data output driving circuit of semiconductor apparatus
A data output driving circuit for a semiconductor apparatus can include a code multiplier configured to multiply a received first code by a multiplication factor determined in response to a control signal and generating a second code; a signal line configured to transmit the second code; and a plurality of data output drivers commonly connected to the signal line and changed in an impedance thereof in response to the second code.
US07719306B2 Output buffer for an electronic device
In order to reduce production cost, an output buffer for an electronic device includes a first logic unit, a second logic unit, a first transistor, a second transistor and a control unit. The first logic unit and the second unit are both coupled to an input terminal and conductions of the first logic unit and the second unit are controlled by an input signal from the input terminal. The control unit is coupled to the first logic unit, the second logic unit, the first transistor and the second transistor, for controlling the first transistor and the second transistor to conduct at different times for implementing the non-overlapping function.
US07719305B2 Signal isolator using micro-transformers
A logic signal isolator including a micro-transformer with a primary winding and a secondary winding. A transmitter circuit drives the primary winding in response to a received input logic signal such that, in response to a first type of edge in the logic signal, at least a first amplitude signal is supplied to the primary winding and, in response to a second type of edge in the logic signal, a second different amplitude signal is supplied to the primary winding. A receiver circuit receives corresponding first amplitude and second amplitude signals from the secondary winding and reconstructs the received logic input signal from the received signals.
US07719304B1 Radiation hardened master-slave flip-flop
The present invention provides a radiation hardened flip-flop formed from a modified temporal latch and a modified dual interlocked storage cell (DICE) latch. The temporal latch is configured as the master latch and provides four output storage nodes, which represent outputs of the temporal latch. The DICE latch is configured as the slave latch and is made of two cross-coupled inverter latches, which together provide four DICE storage nodes. The four outputs of the temporal latch are used to write the four DICE storage nodes of the DICE latch. The temporal latch includes at least one feedback path that includes a delay element, which provides a delay.
US07719302B2 On-chip electromigration monitoring
A method is provided for monitoring interconnect resistance within a semiconductor chip assembly, A semiconductor chip assembly can include a semiconductor chip having contacts exposed at a surface of the semiconductor chip and a substrate having exposed terminals in conductive communication with the contacts. A plurality of monitored elements of the semiconductor chip can include conductive interconnects, each interconnecting a respective pair of nodes of the semiconductor chip through wiring within the semiconductor chip. In an example of such method, a voltage drop across each monitored element is compared with a reference voltage drop across a respective reference element on the semiconductor chip at a plurality of different times during a lifetime of the semiconductor chip assembly. In that way, it can be detected when a resistance of such monitored element is over threshold. Based on a result of such comparison, a decision can be made whether to indicate an action condition.
US07719301B2 Testing method of semiconductor integrated circuit and information recording medium
A testing method of semiconductor integrated circuit wherein the quality of diffusion for semiconductor chips can be tested before the semiconductor chips become packaged semiconductor integrated circuits is provided. Input data is set, and circuit current values I(L) and I(H) obtained for each of a plurality of circuit areas are compared with first test pass ranges I1(L) and I1(H) to extract articles within the first test pass (S2), and the current values of the circuit areas determined to be articles within the first test pass and second test pass ranges I2(L), and I2(H) determined based on these current values are compared, thereby conducting a retest to extract circuit areas within the second test pass. The current values may be replaced by the voltage values.
US07719299B2 Process and temperature insensitive flicker noise monitor circuit
In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defects are within an allowable range.
US07719296B2 Inspection contact structure and probe card
In the present invention, an inspection contact structure is attached to the lower surface side of a circuit board in a probe card. In the inspection contact structure, elastic sheets with protruding conductive portions are respectively attached to both surfaces of a silicone substrate. The silicone substrate is formed with current-carrying paths passing therethrough in the vertical direction, and the sheet conductive portions are in contact with the current-carrying paths from above and below. The conductive portions on the upper side are in contact with connecting terminals of the circuit board. At the time of inspection of electric properties of a wafer, electrode pads on the wafer are pressed against the conductive portions on the lower side and thereby brought into contact with them.
US07719293B2 System and method for current measurement
Load current of a circuit is determined across a component of the circuit by calibrating the resistance of the component with a reference current having a distinguishable characteristic. For example, a reference current with swept frequency modulation is applied to the component so that the resistance of the component is determined from voltage drop associated with the reference current across the component. The component resistance is applied to a voltage drop associated with the load current to determine the load current. For example, a filter matched to the reference current frequency modulation isolates the reference current voltage drop so that a ratio of the reference current voltage drop and the load current voltage drop provides a ratio of the reference current and load current.
US07719292B2 Method and apparatus for electrochemical corrosion monitoring
A method and apparatus for simultaneously and continuously monitoring both the general and localized corrosion of a working metallic electrode is provided, wherein a low frequency, low amplitude periodic potential excitation is used to perturb the electrode around its free corrosion potential. The potential is controlled with respect to a reference electrode by means of a potentiostat, and an auxiliary electrode used to stimulate current flow. The current response of the working electrode is monitored and analyzed continuously for general and localized corrosion activity. Means are provided for validation of the integrity of the current response to the applied potential excitation. Simultaneous and continuous outputs for both general and localized corrosion activity are also provided.
US07719280B2 Detection of resonant tags by ultra-wideband (UWB) radar
A detection system having a receiver for detecting a material having a magnetic resonance response to illumination by pulses of ultra-wideband (UWB) electromagnetic radiation is disclosed. The receiver comprises a detector for detecting the pulses after they have interacted with the material, and a discriminator arranged to identify in the detected pulses the magnetic resonance response of the material. By scanning an item tagged with a tag having a material having a magnetic resonant response, by illuminating the item with UWB pulses and identifying in detected pulses the magnetic resonance response of the material, items can be located, imaged, or activated. The magnetic resonance response of the tag can cause activation of the tag. The tag can have a magnetic resonance response arranged to provide an identifiable magnetic resonance signature such that different tags can be identified and distinguished by their signatures.
US07719270B2 Method and apparatus for accelerated spiral-coded imaging in magnetic resonance tomography
In a method and apparatus for accelerated spiral-coded imaging in magnetic resonance tomography using spiral-shaped k-space sampling, the underlying k-matrix is under-sampled such that an additional spiral is obtained by point mirroring of the measured values at the center of the k-matrix. This additional spiral forms a complete data set of the k-matrix together with the first spiral for imaging the output information.
US07719267B2 Apparatus and method for real time and real flow-rates measurements of oil and water cuts from oil production
A inventive flow-meter uses a measuring method which is based on the passage time of fluid molecules in a single sensor, without using any magnetic field gradient for the measurement of said fluid mean velocity. This method consists of the ultrafast irradiation of hydrogen nuclei from fluid molecules through pulses which are repeated every short time intervals, following a Carr-Purcell-Meiboom-Gill (CPMG) type sequence.
US07719262B2 Inductive proximity sensor and related methods
An inductive proximity sensor or switch and a method of using same. The sensor or switch includes an Application Specific Integrated Circuit (“ASIC”) and a plurality of external components. The ASIC is implemented in CMOS technology and has an oscillator. A switch point of the sensor or switch is predetermined by selection of a bias voltage to a potential node of the oscillator.
US07719261B2 Methods and systems for calibrating a sensor using a vector field
Systems and methods according to exemplary embodiments address, among other features, the area of calibrating a sensor using a constant vector field. In one exemplary embodiment, a method for calibrating a sensor includes the steps of placing the sensor in a cube, rotating the cube between a plurality of different orientations, collecting at least one reading from the sensor from each of the plurality of different orientations and calibrating the sensor using the collected readings.
US07719260B2 Method for pre-treating epitaxial layer, method for evaluating epitaxial layer, and apparatus for evaluating epitaxial layer
An apparatus for evaluating an epitaxial layer, including pre-treating the epitaxial layer before evaluation of the epitaxial layer by making the epitaxial layer contact with a metal electrode by a capacitance-voltage measurement, the method comprising; applying carbon-bearing compound to a surface of the epitaxial layer; subsequently irradiating ultraviolet light to the surface of the epitaxial layer; and thereby forming an oxide film on the surface of the epitaxial layer.An apparatus for evaluating an epitaxial layer of an epitaxial wafer, the apparatus including a pretreatment unit for pre-treating an epitaxial wafer having a semiconductor wafer and an epitaxial layer formed on the semiconductor wafer, a metal-electrode which can be made contact with or vapor-deposited on the surface of the epitaxial layer of the epitaxial wafer which has been pre-treated in the pretreatment unit, a measuring electrode which can be made contact with or vapor-deposited on the semiconductor wafer, and a measuring unit which is connected to each of the electrodes and is used to measure physical properties of the epitaxial layer. The pretreatment unit includes an applying device for applying a carbon-bearing compound to a surface of the epitaxial layer, and an irradiation device for irradiating ultraviolet light to the surface of the epitaxial layer in an oxygen-bearing atmosphere.
US07719259B2 Temperature stable current sensor system
A current sensor system that uses a sensor resistor to sense current flow and in which the level of voltage drop across that resistor is used to control the current flow through another resistor, the input resistor, into a current integrator. The ratio of input resistor to sensor resistor resistance values determines the ratio of sense current to integrator input current level. By matching the temperature coefficients of the resistors the effects of temperature are reduced. The integrator output provides either directly or indirectly a voltage level, frequency, or duty cycle output signal to indicate the sensor resistor current level.
US07719258B2 Method and apparatus for current measurement using hall sensors without iron cores
A method and apparatus for current measurement using Hall sensors without iron cores, used to estimate a flowing current in an electric conducting cable are provided by the exemplary examples of the present invention. The method for current measurement using Hall sensors without iron cores includes the following step: (a) providing Hall sensors to be attached to or located near the electric conducting cable; (b) using each of the Hall sensors to measure the flux density of the magnetic field generated by the flowing current, so as to generate an output voltage according to the flux density of the magnetic field; (c) performing a statistical operation on the output voltages of the Hall sensors, so as to generate a statistical voltage; (d) estimating the flowing current in the electric conducting cable according to the statistical voltage.
US07719257B2 Current sensing module and assembly method thereof
A current sensing module for disposal proximate a conductor is disclosed. The current sensing module includes a housing having a first section and a second section that together define an opening for receiving the conductor therethrough. The second section is in operable connection with the first section. The current sensing module further includes a micro-electromechanical system (MEMS) based current sensor disposed within the first section proximate the opening for receiving the conductor.
US07719256B1 Method for determining a separation time
A method for determining a time interval between leading edges of two adjacent cyclic input pulses of a series of cyclic input pulses. A sample of the cyclic input pulses is taken at each of a series of sampling times to produce sampling hits, each sampling hit being an indication of a presence of a cyclic input pulse, recording a count number at each of the sampling hits, determining initial sampling hits from the detected sampling hits, determining a minimum sampling interval between initial sampling hits, and determining a count number located at a back end of the minimum sampling interval, count numbers of the minimum sampling interval being used to determine a time interval between lead edges of two adjacent cyclic input pulses.
US07719254B2 Method for setting a reference potential of a current sensor and arrangement for determining the reference potential of a power semiconductor device
A method for setting a reference potential of a current sensor in a power semiconductor device is disclosed. On the basis of a specific geometry and a typical two-dimensional potential distribution of the power semiconductor device, a plurality of tapping points is predetermined on an area of the power semiconductor device. On the basis of the specific geometry of the power semiconductor device, a line course between the tapping points and a measuring point for measuring a potential average value is determined and realized. Respective potential values are detected at the tapping points and fed to the measuring point. The potential average value is determined at the measuring point. The potential of the current sensor is set to the potential average value thus determined.
US07719252B2 Power supply
A power supply is provided, which is capable of stabilizing a generated output of the fuel cell using neither a voltage nor a current outputted from the fuel cell as a negative feedback signal. The power supply includes a fuel cell 110, a DC-DC converter 120 that adjusts a voltage outputted from the fuel cell 110 according to a PWM signal and then outputs the voltage to a load device 200, a switching controller 130 that generates the PWM signal and outputs this signal to the DC-DC converter 120, a voltmeter 140 that measures a voltage Vout outputted from the DC-DC converter 120, and a rechargeable battery 150 connected to the load device 200 in parallel. The DC-DC converter 120 calculates a duty ratio of the PWM signal by performing a specific computation using the voltage Vout and a target fuel cell voltage Vt.
US07719251B2 Enhancement of power conversion efficiency using dynamic load detecting and tracking
A switching mode power converter may include a modulation circuit to dynamically control a variable switching frequency of the power converter based on an error voltage of the power converter. The power converter may also include a control circuit connected to the modulation circuit and arranged to dynamically limit an inductor current in the power converter while the switching frequency of the power converter changes. A variable limit on the inductor current may be based on the error voltage of the power converter, a load current of the power converter, or information from a power manager of a system in which the power converter resides. In some implementations, the power converter may also include a disabling circuit to control the modulation circuit to disable the variable switching frequency when a sufficiently large load transient is detected.
US07719249B2 Soft-start circuit and method therefor
In one embodiment, a soft-start circuit is configured to form drive pulses that increase in width independently of the current through the power switch during a first portion of the soft-start operation period.
US07719246B2 Power control system using a nonlinear delta-sigma modulator with nonlinear power conversion process modeling
A power control system includes a switching power converter and a power factor correction (PFC) and output voltage controller. The switching power converter utilizes a nonlinear energy transfer process to provide power to a load. The PFC and output voltage controller generates a control signal to control power factor correction and voltage regulation of the switching power converter. The PFC and output voltage controller includes a nonlinear delta-sigma modulator that models the nonlinear energy transfer process of the switching power converter. The nonlinear delta-sigma modulator generates an output signal used to determine the control signal. By using the nonlinear delta-sigma modulator in a control signal generation process, the PFC and output voltage controller generates a spectrally noise shaped control signal. In at least one embodiment, noise shaping of the control signal improves power factor correction and output voltage regulation relative to conventional systems.
US07719244B2 Method and apparatus for enabling a voltage regulator
A voltage regulator circuit is operated by enabling a bias network operable to set a bias current in an amplifier. A startup circuit is connected to the bias network, the startup circuit operable to assist the bias network in setting the amplifier bias current during a startup period. The startup circuit is disconnected from the bias network responsive to the startup period lapsing while the voltage regulator circuit is enabled for resetting the startup circuit to an initial state. The bias network may be disabled to reduce the amplifier bias current. Subsequent re-enablement of the bias network is prevented until the amplifier is reliably disabled.
US07719243B1 Soft-start system and method for power converter
In one embodiment, a method for soft-start in a power converter includes the following: providing a feedback signal indicative of the output voltage of the power system at a first input terminal of an error amplifier in a negative feedback loop of the power converter; providing a reference voltage at a second input terminal of the error amplifier; comparing the feedback signal against the reference voltage to generate a control signal for regulating an output voltage of the power converter; charging a soft-start capacitor coupled to the second input terminal of the error amplifier with a current for establishing the reference voltage; and adjusting the current in response to the control signal so that the error amplifier is prevented from saturation.
US07719240B2 AC-DC converter
An AC-DC converter includes a rectifier DB for rectifying an alternating current supplied from an alternating power source AC, a power factor controller 11 connected to an output side of the rectifier DB to improve a power factor, a DC-DC converter 12 that converts a voltage outputted from the power factor controller 11 to another voltage and also outputs either a power or a current limited to a predetermined value, a capacitor for storing an energy and a two-way converter 13 having one input/output terminals connected to output terminals of the DC-DC converter 12 and the other input/output terminals connected to the capacitor to carry out a two-way power conversion.
US07719234B2 Methods of discharge control for a battery pack of a cordless power tool system, a cordless power tool system and battery pack adapted to provide over-discharge protection and discharge control
In a cordless power tool system, a battery pack which may removably attachable to a cordless power tool and to a charger may include at least one battery cell and a power limiting device. The power limiting device may be arranged in series with the at least one battery cell for limiting power output of the battery pack based on the component that is connected to the pack. Current and hence power out of the battery pack may be controlled as a function of total internal impedance in the battery pack, which may be adjusted depending on the component that is connected to the pack.
US07719232B2 Method for battery charging based on cost and life
One embodiment of the present subject matter includes a system that includes a battery, an electric vehicle, the battery coupled to the electric vehicle to propel the electric vehicle, and a charging circuit to charge the battery. The embodiment includes a charging cost circuit to estimate a charging cost rate and to turn on the charging circuit. The embodiment also includes a timer circuit to provide a time signal to the charging cost circuit. The embodiment is configured such that the charging cost circuit is to turn on the charging circuit during a first time period in which the charging cost rate is below a first threshold until the battery reaches a first energy stored level, and to turn on the charging circuit during a second time period in which the charging cost rate is above the first threshold.
US07719228B2 Portable battery recharge station for secondary batteries
A system and method for recharging secondary batteries. One embodiment of the present invention comprises a supervisory circuit, a voltage converter, a portable power source, and one or more of a holder and a socket. The holder is adapted to receive a specific type of secondary battery of a portable device. The socket is adapted to mate with a plug of a device-specific charging cord connected to the portable device. Each of the holder and the plug can be associated with a programming resistor that provides a voltage requirement of the secondary battery. When the secondary battery is either placed in the holder or is connected to the socket, the supervisory circuit communicates with the voltage converter to supply the appropriate voltage required to recharge the secondary battery. The voltage converter receives power from the portable power source. The voltage converter can convert the voltage of the portable power source up (i.e., increasing the voltage) or down (i.e., decreasing the voltage) as appropriate to recharge the secondary battery as instructed by the supervisory circuit. The portable power source of the portable battery recharge station can be one of several types of power sources. For example, the portable power source can be replaceable, rechargeable, or renewable.
US07719227B2 Electrical energy supply methods and electrical energy power supplies
Electrical energy supply methods and electrical energy power supplies are described. According to one aspect, an electrical energy supply method includes providing first and second battery assemblies individually configured to store electrical energy, coupling the first and second battery assemblies to form a unitary device configured to supply electrical energy to a load, charging one of the first and the second battery assemblies using electrical energy from a supply at a first moment in time, discharging electrical energy from the first and second battery assemblies to the load at a second moment in time, and disabling discharging of electrical energy from the other of the first and second battery assemblies during the charging.
US07719226B2 Highly responsive permanent magnet motor controller
Current command values are used instead of detected current values to estimate axis error by calculation. An axis error command value is generated according to a speed command value, and a difference between the generated axis error command value and the estimated axis error value is used to control an estimated frequency value.
US07719224B2 Simulated encoder pulse output system and method
The invention includes a system and method for generating simulated encoder outputs in a control system. An output pulse width between reference position inputs is computed, the output pulse width being based upon a difference between an updated reference position input and a previous reference position input, and upon a time interval between the reference position inputs. Next, a plurality of simulated encoder pulses is output between updates of the reference position input based upon the computed output pulse width. The output pulse is thereafter adjusted in a closed loop manner between updates of the reference position input.
US07719223B2 Switching node based sensorless motor control for PM motor
A circuit for indirectly measuring a sign of a current flowing in an inverter stage coupled to a phase of a motor or indirectly measuring the sign of the voltage induced by a counter Electromotive Force (EMF) in a coil of the phase of the motor, the inverter stage being connected between a power supply and the ground. The circuit includes a gate driver circuit coupled to the inverter stage for alternatively connecting the phase of the motor to the power supply and to ground, the gate driver circuit having a current sign detection circuit, wherein the current sign detection circuit senses the sign of the current flowing in the inverter stage, or the sign of the counter EMF for controlling the commutation of switches in the inverter stage.
US07719221B2 Servo control apparatus
A servo control apparatus includes a motor including a motor shaft, the motor for driving a drive subject; a detecting section that detects a rotation position of the motor shaft; and a control system configured to generate a motor torque command for the motor using the rotation position. The control system includes an observer configured to estimate friction torque occurring in the vicinity of the motor shaft on the basis of the rotation position and an application voltage to the motor. The observer is configured to generate a compensation voltage to be added to the application voltage on the basis of the friction torque.
US07719220B2 Safety enhanced control system for servo actuators
An electrical control system comprising a controllably conductive device, an input receiving circuit and a timer circuit. The controllably conductive device selectively applies power to an electrically operated servo. The input receiving circuit receives an input signal from an input switch for selection of the motion of the control surface operated by the electrically operated servo. The input signal receiving circuit is coupled to the controllably conductive device to cause it to be conductive in response to the input signal. The timer circuit is responsive to a signal from the input receiving circuit for causing the controllably conductive device to be non-conductive if the input signal is present for greater than a selectable time period.
US07719219B2 Wizard for configuring a motor drive system
An electronic line shaft comprising a motor drive comprising a velocity noise filter coupled to receive a feedback position signal and operable to filter the feedback position signal to generate a feedback velocity signal where the noise filter has at least one controllable filter parameter that affects filter operating characteristics and a processing unit operable to execute a wizard for configuring the motor drive, the wizard being operable to receive mechanical characteristic data associated with the motor drive that is provided as input by a wizard user via a user interface and to determine a noise parameter based on the mechanical characteristic data, wherein the at least one controllable filter parameter is adjusted as a function of the noise parameter.
US07719216B2 Motor drive control device and motor drive control system
A motor drive control device for controlling the driving of a brushless motor includes position detecting units (e.g. sensors or Hall elements), a drive signal determining unit and a drive signal outputting unit (an output circuit). The position detecting units are disposed in positions apart from each other by an electric angle of 120 degrees and output position detection signals representing the position of the rotor with respect to the stator. The drive signal determining unit determines drive signals for driving the 3-phase drive coils on the basis of the position detection signals. The drive signal outputting unit generates and outputs, to the 3-phase drive coils, the drive signals that have been determined by the drive signal determining unit.
US07719213B2 Door actuator and opener
An actuating mechanism for a door includes a first antenna block having a first integrated microcontroller electrically connected to a first transceiver device and a first antenna. A second antenna block having a second integrated microcontroller is electrically connected to a second transceiver device and a second antenna. A processor device is electrically connected between the first and second microcontrollers and a first switch. The first and second antennas receive a first radio frequency signal from a third, mobile transceiver device. The processor device measures a time difference of arrival (TDOA) of the first radio frequency signal. The processor device computes a direction of arrival (DOA). The DOA measurement is compared against a predefined range of DOAs. The processor device sends a control signal to the first switch to actuate the door in the event of a match.
US07719208B2 Color control method for LED lighting systems
When temperature variation occurs to the LED dice of an LED lighting system, a feedback control mechanism is applied to compensate temperature-related wavelength shift for precisely controlling the light generated by the LED dice based on the voltage drop variation or current variation of the LED dice. The color control method for the LED lighting system includes a preliminary detection phase and a feedback control phase. In the preliminary detection phase, voltage drop signals or current signals together with corresponding color and hue signals of each LED module of the LED lighting system are detected. In the feedback control phase, signal compensating processes are performed to precisely control the light generated by the LED lighting system based on the voltage drop variation or the current variation in conjunction with the corresponding color and hue signals generated in the preliminary detection phase.
US07719206B2 Method and system for open lamp protection
A detector circuit monitors the phase relationship between the lamp voltage and the excitation voltage, and if one or more conditions are met, triggers the open lamp protection process in a discharge lamp system. The detection circuit can be incorporated into a lamp voltage feedback circuit and implemented on the integrated circuit level with less cost and circuit complexity.
US07719193B2 Discharge lamp cathode having tip, middle, and body portions
A discharge lamp includes a cathode and an anode which face each other in an arc tube, wherein the cathode is made of tungsten in which thorium oxide is doped. The cathode has a cylindrical body portion, a tip portion having a cone shape, and a middle portion formed between the body portion and the tip portion, wherein an angle θ1 of the tip portion is set to a range of 55 degrees≦θ1≦65 degrees, and an angle θ2 formed by side faces of the middle portion is smaller than that of the tip portion.
US07719192B2 Metal halide lamp with intermetal interface gradient
The invention relates to a metal halide lamp comprising a ceramic discharge vessel (21), characterized in that a molybdenum leadthrough (11) is connected to a cermet stopper (15) via an intermetal interface gradient (20).
US07719188B2 Plasma display apparatus
A plasma display apparatus is disclosed. The plasma display apparatus includes a plasma display panel, on which an image is displayed, and a filter positioned in front of the plasma display panel. A discharge gas filled in the plasma display panel contains xenon (Xe) equal to or more than 10% based on total weight of the discharge gas. The filter includes a base portion, and a pattern portion formed on the base portion, having a color darker than a color of the base portion.
US07719185B2 Flat panel display and driving method using the same
An organic light emitting display (OLED), which includes a display unit and a controlling unit, is provided. The display unit includes an organic light emission layer and a transparent thin film transistor (TFT) to drive the organic light emission layer, and the display unit emits light into two opposite surfaces (upper and lower surfaces). The controlling unit includes an electro-optical layer that is capable of being switched from one state to another state by applying voltage to the layer. The controlling unit controls transmission of light emitted from the display unit. Therefore the flat panel display of the present invention is capable of displaying an image in one surface or in two surfaces. The selection of surface of image display can be manually or automatically controlled by a user. The controlling unit can includes a liquid crystal device, an electrophoretic device, or an electrochromic device.
US07719184B2 Organic EL element having a protective layer
Provided is an organic EL element including: a first electrode 13; a protection layer 15 that is formed on the first electrode 13 and has an opening portion through which the first electrode 13 is exposed; an insulation layer 17 that is formed on the protection layer 15; an organic layer 19 that is formed over the insulation layer 17 and the first electrode 13 exposed through the opening portion, and includes an emission layer; and a second electrode 21 formed on the organic layer 19, wherein a film thickness of the protection layer 15 is less than that of the organic layer 19.
US07719182B2 OLED device having improved light output
An organic light-emitting diode (OLED) device, comprising: first and second non-metallic transparent electrodes, and one or more layers of organic material formed between the first and second non-metallic transparent electrodes, the layers of organic material including one or more light-emitting layers; and one or more non-metallic reflective layers located on a side of either of the first or second non-metallic transparent electrodes opposite to the organic material layers; wherein the device further comprises a light transmissive scattering layer in optical contact with the organic material layers and the electrodes or wherein at least one of the one or more non-metallic reflective layers comprises a reflective scattering layer in optical contact with the organic material layers and the electrodes. Additionally, a low-index layer is preferably employed in various embodiments to improve device sharpness.
US07719176B2 Spacer configured to prevent electric charges from being accumulated on the surface thereof and electron emission display including the spacer
A spacer, disposed between first and second substrates of an electron emission display, includes a main body, a resistive layer arranged on a side surface of the main body, a secondary electron emission preventing layer arranged on the resistive layer, and a diffusion preventing layer arranged between the resistive layer and the secondary electron emission layer. The diffusion preventing layer prevents interdiffusion between the resistive layer and the secondary electron emission preventing layer.
US07719175B2 External electrode fluorescent lamp and display device including the same
A liquid crystal display contains one or more external electrode fluorescent lamps (EEFL). Each EEFL has a tube filled with a discharge gas. Opposing first and second electrodes are disposed on an outer surface of the tube. Each of the first and second electrodes includes a cap electrode at one end of the tube and a first line electrode along a length direction of the tube; and a second electrode on the outer surface, the second electrode including a second cap electrode at the other end of the tube and a second line electrode along the length direction of the tube.
US07719172B2 Platinum-based alloy for spark plug electrodes incorporating palladium and iridium
A spark plug comprising: an insulator shell; a center electrode inside the insulator shell such that one end of the center electrode protrudes from the insulator shell; a metal shell exterior to the insulator shell; a side ground electrode having one end coupled to the metal shell and the other end facing the protruding end of the center electrode to form a spark discharge gap between the center electrode and the side ground electrode; and a metal tip on at least one of the side ground electrode or the center electrode, located at the spark discharge gap, that is a platinum-based alloy including 23-35 weight percent palladium, greater than 0 to 10 weight percent iridium and the balance being platinum.
US07719169B2 Micro-electromechanical device
A micro-electromechanical device includes a first piezoelectric actuator and a second piezoelectric actuator. The first piezoelectric actuator includes a first beam fixed on a substrate and a second beam extended in parallel to the first beam from a first connecting end to a first working end. A second piezoelectric actuator includes a third beam, spaced from the first beam, fixed on the substrate and a fourth beam extended in parallel to the third beam from a second connecting end to a second working end. The second working end faces the first working end in a perpendicular direction to a surface of the substrate.
US07719165B2 Method and circuit arrangement for the precise dynamic digital control of especially piezoelectric actuators for micropositioning systems
The invention relates to a method and a circuit arrangement for the precise, dynamic, digital control of especially piezoelectric actuators for micropositioning systems, comprising a regulator, whereby in order to minimise position order deviations the future system behaviour is estimated and current correction signals for the purpose of a feedforward correction are obtained. According to the invention, the signal of the command variable is passed via a switchable bypass to a digital/analog converter with highest resolution for the purpose of reducing the latency times in the feedforward loop of the sampling system, with said converter being operated at the sampling rate of the sampling system. The feedforward loop leads to a fast digital/analog converter which is controlled independent of the sampling system. The output signals of the converters, which represent control voltages are supplied in an added-up form to the device to be controlled, in particular, to a piezoelectric actuator which together with a position sensor forms the controlled system.
US07719160B2 Coreless and brushless direct-current motor, Gifford McMahon (GM) cryogenic cooler, pulse tube cryogenic cooler, cryopump, Magnetic Resonance Imaging (MRI) apparatus, Superconducting Magnet (SCM) apparatus, Nuclear Magnetic Resonance (NMR) apparatus, and cryogenic cooler for cooling semiconductor
A coreless and brushless direct-current motor includes an armature coil wound without core and formed in the shape of a saddle; an outside rotor magnet formed by a permanent magnet, the outside rotor magnet being provided at an outside of the armature coil in the shape of a cylinder so as to face the armature coil, the outside rotor magnet being rotated by the magnetic field; an inside rotor magnet formed by a permanent magnet, the inside rotor magnet being provided in the shape of a cylinder at an inside of the armature coil so that the inside rotor magnet has a pole opposite to the outside rotor magnet and a rotational shaft is independently provided; an output shaft connected to the inside rotor magnet; and a sealing part of a barrier structure which sealing part partitions the armature coil and the outside rotor magnet to an outside of the inside rotor magnet and seals the armature coil and the outside rotor magnet.
US07719158B2 Slip-ring brush and slip-ring unit equipped with such a slip-ring brush
A slip-ring brush includes a holder and a brush element that has three regions. The brush element is joined in the first region to the holder, and exhibits a cross-sectional geometry having a cross-sectional area in the second region, which is predetermined for the contacting with a slip ring. The brush element has the same cross-sectional area in the third region as in the second region. The brush element is additionally arranged such that its third region is disposed between the first region and the second region. The cross-sectional geometry of the brush element in the third region is shaped so that it deviates from the cross-sectional geometry of the second region, to reduce the effective spring stiffness of the brush element.
US07719155B2 Two-phase synchronous electric motor with permanent magnets for mechanical priming washing pumps of dishwashers and similar washing machines
A two-phase synchronous electric motor, comprising a permanent-magnet rotor rotating around a rotation axis, and a core lamination pack stator. First and second pairs of pole pieces define: a housing/rotation seat for the rotor. Each pole piece comprises a core, having an end associated to the core lamination pack, a free end portion facing the rotor housing/rotation seat, and a coil. The free end portion of the core of each pole piece comprises a core lamination pack extending in parallel planes to the rotation axis of the rotor. The core laminations have a variable length to form a surface of the free end portion of the core of each pole piece that is concave in the axial direction and partially wraps the rotor. A coupling between the rotor and a load is through a motion transmission joint having driving and driven elements associated in a kinematic series.
US07719152B2 Magnetic levitation actuator
A rotating shaft is accommodated in a case. A ferromagnetic portion is formed on the rotating shaft, and electromagnets are provided to the case. Many projecting portions are formed so as to be arranged in a direction along which the movement of the rotating shaft is required to be regulated. Furthermore, Many projecting portions are likewise formed on the ferromagnetic portion. According to this construction, magnetic flux occurring in the electromagnets concentrates, so that restoring force occurs in the axial direction with suppressing reduction of the attractive force in a radial direction to the ferromagnetic portion. Therefore, the movement in the axial direction of the rotating shaft can be regulated.
US07719146B2 Power tool with yoke rotation prevention means
A power tool 1 includes a cylindrical-shaped yoke 31, magnets 32 provided in the interior of the yoke 31, an armature 41 disposed rotatably in the interior of the yoke 31, a cooling fan 7 rotatably secured to the armature 41, a fan guide 8 disposed on the periphery of the cooling fan 7, and a cylindrical-shaped housing 2 for storing the yoke 31 therein. The fan guide 8 is contacted with the axial-direction one end face of the yoke 31, and the fan guide 8 is engaged with the yoke 31 in the rotation direction thereof.
US07719143B2 Apparatus for providing an auxiliary electrical outlet
An apparatus is provided for mounting between a light fixture and an electrical box supplying a source of electrical power to the fixture where the apparatus includes an auxiliary electrical outlet that is electrically connected to the source of electrical power.
US07719141B2 Electronic switch network
Systems and methods for switching electronic signals are disclosed. The switching may be performed with a low loss and low peak voltages. The switching scheme is suitable for switching RF signals, for example, and may be used in devices such as wireless systems, terminals, and handsets. One exemplary embodiment is directed to a CMOS-implemented transmit/receive switching system. The system comprises one or more transmit ports, each coupled via a respective transmit path to an input/output port and one or more receive ports, each coupled via a respective receive path to the input/output port. Each receive path comprises a switching circuit comprising a transistor and an inductor in parallel with the transistor. The switching circuit is adapted to at least substantially isolate the respective receive port from the input/output port when the transistor is in an on state and operatively couple the respective receive port to the input/output port when the transistor is an off state.
US07719140B2 Systems for boundary controlled solar power conversion
A high efficiency photovoltaic DC-DC converter achieves solar power conversion from high voltage, highly varying photovoltaic power sources to harvest maximum power from a solar source or strings of panels for DC or AC use, perhaps for transfer to a power grid at high power levels with coordinated control possible for various elements. Photovoltaic DC-DC converters can achieve efficiencies in conversion that are extraordinarily high compared to traditional through substantially power isomorphic photovoltaic DC-DC power conversion capability that can achieve 97%, 98%, 99.2% efficiency, or even only wire transmission losses. Switchmode impedance or voltage conversion circuit embodiments may have pairs of photovoltaic power interrupt switch elements and pairs of photovoltaic power shunt switch elements to first increase voltage and then decrease voltage as part of the desired photovoltaic DC-DC power conversion.
US07719139B2 Power supply unit
A power supply unit includes a main power-supply circuit and a secondary power-supply circuit which are connected to an alternating current power supply AC. The main power-supply circuit includes a full-wave rectifier and an input current control circuit corresponding to a harmonic current suppression circuit. The input current control circuit includes a resistor as circuit current detection element and a control circuit for controlling a switch element by detecting a current flowing in the resistor. A connection is provided such that a current flowing in a diode as a second rectifying circuit of the secondary power-supply circuit may return to the alternating current power supply through the resistor.
US07719138B2 Two-source series inverter
Systems and methods are disclosed for a two-source series inverter. The systems and methods combine operation of a first voltage source and a second voltage source in series powering a novel voltage combining arrangement and a conventional inverter via a switch configuration to power a load. The switch configuration is controlled by a plurality of control signals generated by a controller based on a variety of control modes, and feedback signals.
US07719132B2 Ruggedized mobile computing device
A ruggedized mobile computing system for a motor vehicle includes a ruggedized mobile computing device, which can be mounted in the trunk or other convenient location, and a suitable user interface system, such as a display screen, keyboard, etc., mounted in the vehicle cabin. The computing device can accommodate user-removable, plug-in electronic modules that perform specialized processing, communications, control or other specialized tasks relating in some way to the vehicle mission or purpose. The device has a ruggedized enclosure made of a durable material such as sheet metal or high-impact plastic. The enclosure can include a guard that protects cables extending from the front panel from being damaged or inadvertently removed. Cooling and warming systems can be included that maintain the enclosure environment within suitable operating temperatures in hot or cold weather. Some or all of the electronic or electromechanical elements, such as a disk drive, can be mounted with isolation mounts that protect them against harmful effects of mechanical shock and vibration.
US07719129B2 Electric generator for wind and water turbines
A generator housed in a wind turbine nacelle includes a generator rotor that is mounted to gearbox output pinions, thereby eliminating the need for couplings. The generator frame is located directly on the gearbox and is located to control the air gap. To facilitate removal of the generator, tapers are used that have steep angles that exceed the friction coefficient of the materials used. To provide adequate support over its length, the shaft employs dual tapers, each short and precisely located conical surface of which provides exact location on the near and far sides of the shaft. The length of straight shaft between the dual locating tapers serves to support the generator during mounting and de-mounting. During installation, the tapers center the rotor and bullet pins center the frame (stator). When the system aligns the rotor and stator, retainer elements act as labyrinth seals designed to protect the generator interior from contamination.
US07719123B2 Method of manufacturing semiconductor device
There is provided a method of manufacturing a semiconductor device. The method includes the successive steps of: (a) providing a semiconductor substrate; (b) forming a plurality of semiconductor chips having electrode pads on the semiconductor substrate; (c) forming internal connection terminals on the electrode pads; (d) forming an insulating layer on the plurality of semiconductor chips to cover the internal connection terminals; (e) forming a metal layer on the insulating layer; (f) pushing a whole area of the metal layer to bring the metal layer into contact with upper end portions of the internal connection terminals; (g) pushing portions of the metal layer which contact the upper end portions of the internal connection terminals, thereby forming first recesses in the internal connection terminals, and thereby forming second recesses in the metal layer; and (h) forming wiring patterns by etching the metal layer.
US07719118B2 Semiconductor chip scale package incorporating through-vias electrically connected to a substrate and other vias that are isolated from the substrate, and method of forming the package
A semiconductor chip scale package formed with through-vias, which can be either isolated or electrically connected to a substrate, and a method of producing the semiconductor chip scale package with through-vias, which can be isolated or electrically connected to the substrate.
US07719115B2 Semiconductor integrated circuit including a multi-level interconnect with a diagonal wire
A computer automated design system includes a subject routing module configured to set a first grid area and a first diagonal grid area and route a first wire in the first grid area and a first diagonal wire extending diagonally to a longitudinal direction of the first wire and a next routing module configured to set a second grid area and a second diagonal grid area and route a second wire in the second grid area and a second diagonal wire extending diagonally to a longitudinal direction of the second wire.
US07719113B2 Semiconductor device including dummy patterns
A semiconductor device in which surge breakdown of interlayer-insulating film does not occur even when effectively suppressing variations in etching and proximity effects. The semiconductor comprises dummy patterns 7b that are made from a gate layer and shaped to be disposed within the surface shape of the insulating material of element-isolation areas 3a and are located on the insulating material of the element-isolation areas 3a; wherein dummy patterns 7b are located on an underlayer that includes area directly under wiring layers 10a that are located on layers above the gate layer.
US07719112B2 On-chip magnetic components
An integrated circuit chip comprising a bond wire and a mass of magnetic material provided on the bond wire, wherein the mass of magnetic material increases the inductance of the bond wire.
US07719109B2 Embedded capacitors for reducing package cracking
A linear coefficient of thermal expansion (CTE) mismatch between two materials, such as between a microelectronic die and a mounting substrate, may induce stress at the interface of the materials. The temperature changes present during the process of attaching a die to a mounting substrate can cause cracking and failure in the electrical connections used to connect the die and mounting substrate. A material with a CTE approximately matching the die CTE is introduced in the mounting substrate to reduce the stress and cracking at the electrical connections between the die and mounting substrate. Additionally, this material may comprise thin film capacitors useful for decoupling power supplies.
US07719108B2 Enhanced reliability semiconductor package
A method of packaging a semiconductor component with a printed wiring board is disclosed. The method includes determining a first distance, applying a thin film onto a surface of the semiconductor component such that the thin film is spaced apart from a support of the semiconductor, applying a solder pad onto the printed wiring board, placing the semiconductor component with the thin film onto the printed wiring board, and positioning the thin film adjacent the solder pad.
US07719104B2 Circuit board structure with embedded semiconductor chip and method for fabricating the same
The present invention provides a circuit board structure with an embedded semiconductor chip and a method for fabricating the same. The circuit board structure includes a carrier board having a first surface, a second surface, and a through hole penetrating the carrier board from the first surface to the second surface; a semiconductor chip having an active surface whereon a plurality of electrode pads are formed and a non-active surface, embedded in the through hole; a photosensitive first dielectric layer formed on the first surface of the carrier board and an opening formed thereon to expose the non-active surface of the semiconductor chip; a photosensitive second dielectric layer formed on the second surface of the carrier board and the active surface of the semiconductor chip.
US07719102B2 Semiconductor device
A manufacturing method of a semiconductor device of this invention includes forming metal pads on a Si substrate through a first oxide film, bonding the Si substrate and a holding substrate which bolsters the Si substrate through a bonding film, forming an opening by etching the Si substrate followed by forming a second oxide film on a back surface of the Si substrate and in the opening, forming a wiring connected to the metal pads after etching the second oxide film, forming a conductive terminal on the wiring, dicing from the back surface of the Si substrate to the bonding film and separating the Si substrate and the holding substrate.
US07719101B2 Semiconductor device with surface-mountable external contacts and method for manufacturing the same
A semiconductor device includes surface-mountable external contacts on an underside of the semiconductor device, wherein the external contacts are arranged on external contact pads and surrounded by a solder-resist layer. The external contacts of the outer edge regions include external contact pads that merge into inspection tags, wherein the inspection tags can be wetted by solder and are not covered by the solder-resist layer.
US07719100B2 Power semiconductor module with MOS chip
To prevent any uneven solder wetting in a main surface of electrodes of a semiconductor connected with a main surface of a planar lead and any displacement of the lead vis-a-vis the electrodes due to the reflow of the solder in a semiconductor module having the semiconductor element mounted on a substrate and the planar lead electrically connected therewith, the present invention provides an improved semiconductor module characterized in that the width of at least a part of the region of the main surface of the lead facing the semiconductor element is expanded wider than or equal to the width of the electrodes formed on the semiconductor element, and preferably the other part of the main surface of the lead soldered to an electrode formed on the substrate is split in the extending direction thereof.
US07719099B2 Package structure for solid-state lighting devices and method of fabricating the same
Silicon substrates are applied to the package structure of solid-state lighting devices. Wet etching is performed to both top and bottom surfaces of the silicon substrate to form reflecting cavity and electrode access holes. Materials of the reflecting layer and electrode can be different from each other whose preferred materials can be chosen in accordance with a correspondent function. Formation of the electrode can be patterned by an etching method or a lift-off method.
US07719095B2 Lead frame and semiconductor device provided with lead frame
A lead frame and a semiconductor device having a lead frame are disclosed. The lead frame is provided with a mount bed to mount a semiconductor chip, first and second lead terminals and first and second extension portions of band-shapes. The first and the second extension portions extend from sides of the first and second lead terminals and are bent. An electronic component is attached to Tip portions of the first and the second extension portions with connection conductors interposed in between.
US07719094B2 Semiconductor package and manufacturing method thereof
A semiconductor package includes a lead frame, at least one chip, and an encapsulation. The lead frame has a plurality of leads, and each of the leads includes at least one first conductive part, at least one second conductive part, and at least one third conductive part. The first conductive part is not electrically connected to the second conductive part, and the second conductive part is electrically connected to the third conductive part. The chip is electrically connected to the first conductive part. The encapsulation encapsulates the chip and at least a portion of the lead frame, and forms a first surface and a second surface opposite to the first surface. The first conductive part and the third conductive part are exposed from the first surface, and the second conductive part is exposed from the second surface.
US07719093B2 Circuit board with decoupling capacitors
A printed circuit board includes a source interconnect and a ground interconnect, and the circuit board has a two-dimensional geometry having a corner. Protruding portions are provided in circumferences of the source interconnect and the ground interconnect in regions except the corner in plan view, and the source interconnect and the ground interconnect are connected to a common first decoupling capacitor in each of the protruding portions.
US07719092B2 Power semiconductor module
The power semiconductor module includes a module package housing power semiconductor devices therein and a magnetic core set around the module package, such that magnetic core surrounds the power semiconductor devices such as IGBTs. Alternatively, the magnetic core is built in the module package such that the outer circumference faces of magnetic core and the side faces of module package form side faces of the power semiconductor module. The power semiconductor module according to the invention facilitates replacing the magnetic core, setting the magnetic core around the module package thereof, reducing the size thereof, simplifying the structure thereof, and easy manufacture thereof.
US07719090B2 Semiconductor device with strain
A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed above the semiconductor substrate, traversing the p-MOS active region and defining a p-MOS channel region under the p-MOS gate electrode structure; a compressive stress film selectively formed above the p-MOS active region and covering the p-MOS gate electrode structure; and a stress released region selectively formed above the element isolation region in the p-MOS region and releasing stress in the compressive stress film, wherein a compressive stress along the gate length direction and a tensile stress along the gate width direction are exerted on the p-MOS channel region. The performance of the semiconductor device can be improved by controlling the stress separately for the active region and element isolation region.
US07719088B2 High-frequency bipolar transistor
A high-frequency bipolar transistor includes an emitter contact adjoining an emitter connection region, a base contact adjoining a base connection region, and a collector contact adjoining a collector connection region. A first insulation layer is disposed on the base connection region. The collector connection region contains a buried layer, which connects the collector contact to a collector zone. A silicide or salicide region is provided on the buried layer and connects the collector contact to the collector zone in a low-impedance manner. A second insulation layer is disposed on the collector connection region but not on the silicide region.
US07719086B2 Lateral insulated gate bipolar transistor having a retrograde doping profile in base region and method of manufacture thereof
In a semiconductor device of the present invention, a first base region 16 is extended to a part under a gate electrode 7 while having a vertical concentration profile of an impurity that increases from the surface of a semiconductor layer 3 and becomes maximum under an emitter region 5, and the length in the lateral direction from a point where the impurity concentration becomes maximum located under an end of the gate electrode 7 to the boundary with a second base region 15 is not smaller than the length in the vertical direction from the point where the impurity concentration becomes maximum to the boundary with the second base region 15.
US07719082B2 Memory device and storage apparatus
A memory device 10 has an arrangement in which a memory thin film 4 is sandwiched between first and second electrodes 2 and 6, the memory thin film 6 contains at least rare earth elements, the memory thin film 4 or a layer 3 in contact with the memory thin film 4 contains any one of elements selected from Cu, Ag, Zn and the memory thin film 4 or the layer 3 in contact with the memory thin film 4 contains any one of elements selected from Te, S, Se. The memory device can record and read information with ease stably, and this memory device can be manufactured easily by a relatively simple manufacturing method.
US07719079B2 Chip carrier substrate capacitor and method for fabrication thereof
A chip carrier substrate includes a capacitor aperture and a laterally separated via aperture, each located within a substrate. The capacitor aperture is formed with a narrower linewidth and shallower depth than the via aperture incident to a microloading effect within a plasma etch method that is used for simultaneously etching the capacitor aperture and the via aperture within the substrate. Subsequently a capacitor is formed and located within the capacitor aperture and a via is formed and located within the via apertures. Various combinations of a first capacitor plate layer, a capacitor dielectric layer and a second capacitor plate layer may be contiguous with respect to the capacitor aperture and the via aperture.
US07719076B2 High-voltage MOS transistor device
A HV MOS transistor device having a substrate, a gate, a source, a drain, a first ion well of a first conductive type disposed in the substrate, and a plurality of field plates disposed on the substrate is disclosed. The HV MOS transistor device further has a first doped region of a second conductive type positioned in the first ion well. Therefore, a first interface and a second interface between the first ion well and the first doped region are formed, and the first interface and the second interface are respectively positioned near the drain and the source. In addition, the first interface is positioned under a respective field plate to produce a smooth field distribution and to increase the breakdown voltage of the HV transistor device.
US07719072B2 Image sensor and method for fabricating the same
The image sensor includes a semiconductor substrate, a first color filter pattern formed over the substrate, the first color filter pattern having an edge portion with a first slope, and a second color filter pattern formed next to the first color filter pattern, the second color filter pattern having an edge portion with a second slope.
US07719071B1 Bipolar spin transistors and the applications of the same
A bipolar spin transistor is provided. In one embodiment of the present invention, the bipolar spin transistor includes a first semiconductor region having a first conductivity type, a second semiconductor region having a second conductivity type that is different from the first conductivity type and also having a spin polarization, and a third semiconductor region having a conductivity type that is the same conductivity type of the first semiconductor region. The first semiconductor region and the second semiconductor region are adjacent to each other so as to form a first charge depletion layer therebetween, the first charge depletion layer having a first side facing the first semiconductor region and an opposing second side facing the second semiconductor region. Additionally, the second semiconductor region and the third semiconductor region are adjacent to each other so as to form a second charge depletion layer therebetween, the second charge depletion layer having a first side facing the second semiconductor region and an opposing second side facing the third semiconductor region.
US07719069B2 Three terminal magnetic sensor having a collector region electrically isolated from a carrier substrate body
In one illustrative example, a three terminal magnetic sensor includes a collector region made of a semiconductor material, a base region, and an emitter region. An insulator layer is formed between the collector region and a carrier substrate body which carries the three terminal magnetic sensor. The insulator layer serves to reduce a capacitance otherwise present between the collector region and magnetic media at a magnetic field sensing plane of the three terminal magnetic sensor. Thus, the insulator layer electrically isolates the collector region from the carrier substrate body. The structure may be formed through use of a separation by implanting oxygen (SIMOX) technique or a wafer-bonding technique, as examples.
US07719068B2 Multi-bit electro-mechanical memory device and method of manufacturing the same
There are provided a multi-bit electro-mechanical memory device capable of enhancing or maximizing a degree of integration of the memory device and a method of manufacturing the multi-bit electro-mechanical memory device which includes a substrate, a bit line on the substrate, and extending in a first direction; a word line on the bit line, insulated from the bit line, and extending in a second direction transverse to the first direction, and a cantilever electrode including a shape memory alloy. The cantilever electrode has a first portion electrically connected to the bit line and a second portion extending in the first direction, and spaced apart from the word line by an air gap, wherein the cantilever electrode, in a first state, is in electrical contact with the word line, and, in a second state, is spaced apart from the word line.
US07719062B2 Tuned tensile stress low resistivity slot contact structure for n-type transistor performance enhancement
A method for forming a slot contact structure for n-type transistor performance enhancement. A slot contact opening is formed to expose a contact region, and a barrier plug is disposed within a portion of the slot contact opening in order to induce a tensile stress on an adjacent channel region. The remainder of the slot contact opening is filled with a lower resistivity contact metal. Barrier plug deposition temperature can be varied in order to tune the tensile stress on the adjacent channel region.
US07719060B2 Tensile strain source using silicon/germanium in globally strained silicon
By embedding a silicon/germanium mixture in a silicon layer of high tensile strain, a moderately high degree of tensile strain may be maintained in the silicon/germanium mixture, thereby enabling increased performance of N-channel transistors on the basis of silicon/germanium material. In other regions, the germanium concentration may be varied to provide different levels of tensile or compressive strain.
US07719059B2 Fin field effect transistor arrangement and method for producing a fin field effect transistor arrangement
A fin field effect transistor arrangement comprises a substrate and a first fin field effect transistor on and/or in the substrate. The first fin field effect transistor includes a fin in which a channel region is formed between a first source/drain region and a second source/drain region and above which a gate region is formed. A second fin field effect transistor is provided on and/or in the substrate including a fin in which a channel region is formed between a first source/drain region and a second source/drain region and above which a gate region is formed. The second fin field effect transistor is arranged laterally alongside the first fin field effect transistor, wherein a height of the fin of the first fin field effect transistor is greater than a height of the fin of the second fin field effect transistor.
US07719055B1 Cascode power switch topologies
A normally-off cascode power switch circuit is disclosed fabricated in wide bandgap semiconductor material such as silicon carbide or gallium nitride and which is capable of conducting current in the forward and reverse direction under the influence of a positive gate bias. The switch includes cascoded junction field effect transistors (JFETs) that enable increased gain, and hence blocking voltage, while minimizing specific on-resistance.
US07719054B2 High-voltage lateral DMOS device
All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and P-N diode clamps and rectifiers and junction terminations. Since the processes eliminate the need for high temperature processing and employ “as-implanted” dopant profiles, they constitute a modular architecture which allows devices to be added or omitted to the IC without the necessity of altering the processes used to produce the remaining devices.
US07719050B1 Low power electrically alterable nonvolatile memory cells and arrays
A memory cell comprises a body of a semiconductor material having a first conductivity type. A conductor-filter system includes a first conductor having thermal charge carriers, and a filter contacting the first conductor and including dielectrics for providing a filtering function on the charge carriers of one polarity. The filter includes a first set of electrically alterable potential barriers. A conductor-insulator system includes a second conductor and a first insulator contacting the second conductor at an interface and having a second set of electrically alterable potential barriers. A first region is spaced-apart from the second conductor. A channel of the body is defined therebetween. A second insulator is adjacent to the first region. A charge storage region is disposed in between the first and the second insulators. A word-line has a first portion and a second portion comprising the first conductor disposed over and insulated from the body.
US07719049B2 Flash memory device and fabrication method thereof
The present invention relates to a flash memory device and a fabrication method thereof. A trench may be formed within a junction region between word lines by etching a semiconductor substrate between not only a word line and a select line, but also between adjacent word lines. Accordingly, the occurrence of a program disturbance phenomenon can be prevented as the injection of hot carriers into a program-inhibited cell is minimized in a program operation.
US07719048B1 Heating element for enhanced E2PROM
A heating element is utilized to improve the bias conditions of an E2PROM cell during program and erase operations. The heating element can also be used to anneal or condition the cell for improved charge storage. During a program or an erase operation, the cell's control gate and read transistor are set to ground. The heating element then has a voltage potential applied across its terminals, causing current to flow in this resistor. As the current density increases, the resistor begins to generate heat. This heat is thermally coupled into the cell's floating gate, causing its temperature to rise.
US07719047B2 Non-volatile memory device and fabrication method thereof and memory apparatus including thereof
A non-volatile memory device is capable of reducing an excessive leakage current due to a rough surface of a polysilicon and of realizing improved blocking function by forming the first oxide film including a silicon oxy-nitride (SiOxNy) layer using nitrous oxide (N2O) plasma, and by forming silicon-rich silicon nitride film, and a fabricating method thereof and a memory apparatus including the non-volatile memory device. Further, the non-volatile memory device can be fabricated on the glass substrate without using a high temperature process.
US07719044B2 Platinum-containing integrated circuits and capacitor constructions
In one aspect, the invention includes a method of forming a roughened layer of platinum, comprising: a) providing a substrate within a reaction chamber; b) flowing an oxidizing gas into the reaction chamber; c) flowing a platinum precursor into the reaction chamber and depositing platinum from the platinum precursor over the substrate in the presence of the oxidizing gas; and d) maintaining a temperature a within the reaction chamber at from about 0° C. to less than 300° C. during the depositing. In another aspect, the invention includes a platinum-containing material, comprising: a) a substrate; and b) a roughened platinum layer over the substrate, the roughened platinum layer having a continuous surface characterized by columnar pedestals having heights greater than or equal to about one-third of a total thickness of the platinum layer.
US07719040B2 Solid-state imaging device
Realized is a solid-state imaging device capable of achieving both a finer pixel size and high light receiving efficiency with an excellent image characteristic. A high concentration p-well layer (5) is partially formed in the interior of a semiconductor substrate (1) centering on a region under a STI (6), and a photoelectric conversion layer (9a, 9b) is formed so as to extend to a region under a gate electrode (10a, 10b). Furthermore, a salicide region (12a, 12b) covers only a portion of a surface of the gate electrode (10a, 10b) and is formed at a position closer to a side at which a drain region (13) is provided. Thus, an incident light is allowed to pass through a portion, included in the surface of the gate electrode (10a, 10b), on which the salicide region (12a, 12b) is not formed, and then to be further incident on the photoelectric conversion layer (9a, 9b) extending to the region under the gate electrode (10a, 10b).
US07719035B2 Low contact resistance CMOS circuits and methods for their fabrication
A low contact resistance CMOS integrated circuit and method for its fabrication are provided. The CMOS integrated circuit comprises a first transition metal electrically coupled to the N-type circuit regions and a second transition metal different than the first transition metal electrically coupled to the P-type circuit regions. A conductive barrier layer overlies each of the first transition metal and the second transition metal and a plug metal overlies the conductive barrier layer.
US07719031B2 Heterojunction biploar transistor and method for manufacturing same
A bipolar transistor 120 comprises a substrate 1, a intrinsic base region 11 and an extrinsic base region 12. The intrinsic base region 11 comprises a silicon buffer layer 109 comprised of silicon which is formed on the substrate 1, and a composition-ratio graded base layer 111 which is formed on the silicon buffer layer and comprises silicon and at least germanium and where a composition ratio of the germanium to the silicon varies in a thickness direction of the composition-ratio graded base layer 111. The extrinsic base region 12 comprises an extrinsic base formation layer 113 comprised of silicon which is formed on the substrate and adjacent to the silicon buffer layer. And the thickness of the extrinsic base formation layer 113 is not less than 40 nm.
US07719028B2 Semiconductor light-receiving device and manufacturing method thereof
A semiconductor light-receiving device and its manufacturing method are provided which are capable of suppressing dark current and deterioration. Semiconductor crystals were sequentially grown over an n-type InP substrate, including an n-type InP buffer layer, an undoped GaInAs light absorption layer, an undoped InP diffusion buffer layer, and a p-type InP window layer. Next, a first mesa was formed by removing a part from the p-type InP window layer to the n-type InP buffer layer with a Br-based etchant having low etching selectivity, so as to form a sloped “normal” mesa structure. Next, a second mesa having a smaller diameter than the first mesa was formed by dry etching, by precisely removing a part from the p-type InP window layer to a certain mid position of the undoped InP diffusion buffer layer.
US07719027B2 Intergrated circuit utilizing down bond to define the function of the die and the implementing method thereof
The present invention provides an integrated circuit and the method of implementing the same. The integrated circuit includes a die, a base, a covering material and a plurality of pins. The die has at least a first function and a second function and includes a plurality of signal pads and at least a switching pad. The die receives and outputs signals through the signal pads, and the switching pad is utilized to switch the functions of the die. The base is utilized to support the die, and the covering material is utilized to cover the die and the base. One terminal of each pin is inside the covering material and coupled to the corresponding signal pad, and the other terminal of each pin is outside the covering material. The signal pads are connected to the circuits outside the integrate circuit through the pins.
US07719026B2 Un-assisted, low-trigger and high-holding voltage SCR
A protective SCR integrated circuit device is disclosed built on adjacent N and P wells and defining an anode and a cathode. In addition to the anode and cathode contact structures, the device has an n-type stack (N+/ESD) structure bridging the N-Well and the P-Well, and a p-type stack (P+/PLDD) structure in the P-Well. The separation of the n-type stack structure and the p-type stack structure provides a low triggering voltage without involving any external circuitry or terminal, that together with other physical dimensions and processing parameters also provide a relatively high holding voltage without sacrificing the ESD protection robustness. In an embodiment, the triggering voltage may be about 8V while exhibiting a holding voltage, that may be controlled by the lateral dimension of the n-type stack of about 5-7 V.
US07719024B2 Semiconductor light emitting device and a method for producing the same
Both ends of the lead arrangement project outward from side surfaces of a package to form outer lead regions. Each of the outer lead regions includes a pair of outer lead projections and lead terminal smaller projections that are located between the outer lead projections. The outer lead projections and lead terminal smaller projections project outward. Adjustment is made to the projection amount of end surfaces of the lead smaller projections lying in a plane perpendicular to a longitudinal direction of the lead arrangement, whereby the end surfaces projecting less than end surfaces of the outer lead projections. Thus, cut surfaces of lead connection portions with edged corners are not exposed. This arrangement prevents that the cut surfaces damage other devices.
US07719022B2 Phosphor illumination optics for LED light sources
Devices and methods for collecting and distributing light from a light emitting diode (LED) emitter onto a phosphor layer to produce substantially white light are provided. The devices may include a reflective cavity with a reflective material, surrounding the reflective cavity, with a reflective side of the reflective material facing towards the inside of the reflective cavity. Further, the devices may incorporate an LED on one end of the reflective cavity and a phosphor layer on another end. Additionally, the devices may use a gradient index (GRIN) rod lens to refract light produced from the LED onto a phosphor surface with an LED on one end of the GRIN rod lens and the phosphor layer on the other end.
US07719018B2 Light emitting devices with compact active regions
A light emitting device includes a region of first conductivity type, a region of second conductivity type, an active region, and an electrode. The active region is disposed between the region of first conductivity type and the region of second conductivity type and the region of second conductivity type is disposed between the active region and the electrode. The active region has a total thickness less than or equal to about 0.25λn and has a portion located between about 0.6λn and 0.75λn from the electrode, where λn is the wavelength of light emitted by the active region in the region of second conductivity type. In some embodiments, the active region includes a plurality of clusters, with a portion of a first cluster located between about 0.6λn and 0.75λn from the electrode and a portion of a second cluster located between about 1.2λn and 1.35λn from the electrode.
US07719016B2 Light-emitting diode device and backlight apparatus and liquid-crystal display apparatus using light-emitting diode device
A light-emitting diode device and backlight apparatus and liquid-crystal display apparatus using light-emitting diode device are provided. A light-emitting diode device has a lens covered around a light-emitting diode chip and a processed portion for adjusting light going from the light-emitting diode chip along the central axis of the lens is provided at the light-emitting diode chip or the lens or being provided right above the lens. The light-emitting diode chip is processed near the central axis by a suitable method such as etching. Alternatively, a diffusion material containing low refractive index material portion or an angle selective film is provided on the lens. A light-emitting diode device is able to adjust a quantity of light emitted from the LED chip along the central axis of the lens so that light can be radiated with a desired angle distribution. A backlight apparatus and a liquid-crystal display apparatus are able to suppress ununiformity of brightness and ununiformity of color by using the above-mentioned light-emitting diode device.
US07719015B2 Type II broadband or polychromatic LED's
An LED is provided comprising two or more light-emitting Type II interfaces wherein at least two of the Type II interfaces differ in transition energy by at least 5%, or more typically by at least 10%, and wherein at least one of the Type II interfaces is within a pn junction. Alternately, an LED is provided comprising two or more light-emitting Type II interfaces wherein at least two of the Type II interfaces differ in transition energy by at least 5%, or more typically by at least 10%. The Type II interfaces may include interfaces from a layer which is an electron quantum well and not a hole quantum well, interfaces to a layer which is a hole quantum well and not an electron quantum well; and interfaces that satisfy both conditions simultaneously. The Type II interfaces may be within a pn or pin junction or not within a pn or pin junction. In the later case, emission from the Type II interfaces may be photopumped by a nearby light source. The LED may be a white or near-white light LED. In addition, graphic display devices and illumination devices comprising the semiconductor device according to the present invention are provided.
US07719013B2 Semiconductor light emitting device and method of manufacturing the same
A semiconductor light emitting device and a method of manufacturing the semiconductor light emitting device are provided. The semiconductor light emitting device includes a substrate, at least two light emitting cells located on the substrate and formed by stacking semiconductor material layers, a reflection layer and a transparent insulating layer sequentially stacked between the light emitting cells, and a transparent electrode covering the upper surface of the light emitting cells.
US07719009B2 Thin film transistor array panel and method of manufacture
A thin film transistor array panel includes a gate line formed on a substrate, an interlayer insulating film formed on the gate line and having an opening, a gate insulator formed in the opening, a data line formed on the interlayer insulating film and including a first conductive layer made of a transparent conductive oxide and a second conductive layer made of a metal, a source electrode connected to the data line and made of a transparent conductive oxide, a drain electrode facing the source electrode and made of a transparent conductive oxide, a pixel electrode connected to the drain electrode, and an organic semiconductor contacting the source electrode and the drain electrode.
US07719005B2 Structure and method for monitoring and characterizing pattern density dependence on thermal absorption in a semiconductor manufacturing process
According to the present invention, there is disclosed a thermal detection device and method of using the device for characterizing and monitoring the dependence of pattern density on thermal absorption of a semiconductor. One or more of the devices can be disposed on a die of a test wafer. The thermal detection device comprises a silicon substrate having a test structure located substantially in the center of the silicon substrate. Frame shaped structures of polysilicon, silicon and oxide, in various configurations, form a collocated arrangement on the silicon substrate. The test wafer is subjected to a rapid thermal process and the resistance of the at least one testing structure is measured and the measured resistance of the at least one test structure is tabulated to a thermal absorption value of the at least one die.
US07718999B2 Polythiophene electronic devices
An electronic device with a semiconductor layer of (I) wherein X is O or NR′; m represents the number of methylenes; M is a conjugated moiety; R and R′ are selected from the group consisting of at least one of hydrogen, a suitable hydrocarbon, and a suitable hetero-containing group; a represents the number of 3-substituted thiophene units; b represents the number of conjugated moieties, and n represents the number of polymer repeating units.
US07718995B2 Nanowire, method for fabricating the same, and device having nanowires
A nanowire according to the present invention includes: a nanowire body made of a crystalline semiconductor as a first material; and a plurality of fine particles, which are made of a second material, including a constituent element of the semiconductor, and which are located on at least portions of the surface of the nanowire body. The surface of the nanowire body is smooth.
US07718993B2 Pattern enhancement by crystallographic etching
A method for producing predetermined shapes in a crystalline Si-containing material that have substantially uniform straight sides or edges and well-defined inside and outside corners is provided together with the structure that is formed utilizing the method of the present invention. The inventive method utilizes conventional photolithography and etching to transfer a pattern, i.e., shape, to a crystalline Si-containing material. Since conventional processing is used, the patterns have the inherent limitations of rounded corners. A selective etching process utilizing a solution of diluted ammonium hydroxide is used to eliminate the rounded corners providing a final shape that has substantially straight sides or edges and substantially rounded corners.
US07718992B2 Nitride semiconductor device
A nitride semiconductor device is provided. In the device, first and second conductivity type nitride layers are formed. An active layer is formed between the first and second conductivity type nitride layers. The active layer includes at least one quantum barrier layer and at least one quantum well layer. Also, a current spreading layer is interposed between the first conductivity type nitride layer and the active layer. The current spreading layer has an In content greater than the quantum well layer of the active layer.
US07718991B2 Lighting device and method of making
A lighting device comprises a solid state light emitter, first and second electrodes connected to the emitter, an encapsulant region comprising a silicone compound and a supporting region. The encapsulant region extends to an external surface of the lighting device. At least a portion of the first electrode is surrounded by the supporting region. The encapsulant region and the supporting region together define an outer surface which substantially encompasses the emitter. A method of making a lighting device, comprises electrically connecting first and second electrodes to an emitter; inserting the emitter into mold cavity; inserting an encapsulant composition comprising a one silicone compound; and then inserting a second composition to substantially surround at least a portion of the first electrode.
US07718990B2 Active material devices with containment layer
An active material electronic device with a containment layer. The device includes an active chalcogenide, pnictide, or phase-change material in electrical communication with an upper and lower electrode. The device includes a containment layer formed over the active material that prevents escape of volatilized matter from the active material when the device is exposed to high temperatures during fabrication or operation. The containment layer further prevents chemical contamination of the active material by protecting it from reactive species in the processing or ambient environment. Once the containment layer is formed, the device may be subjected to high temperature or chemically aggressive environments without impairing the compositional or structural integrity of the active material.
US07718986B2 Radiation image conversion panel, production method of the same, and X-ray image capturing system
A radiation image conversion panel containing a substrate having thereon a phosphor layer, wherein the phosphor layer is formed with a vapor deposition method, and an adhesion force of the phosphor layer with the substrate is greater than a breaking strength of the phosphor layer.
US07718982B2 Programmable particle scatterer for radiation therapy beam formation
Interposing a programmable path length of one or more materials into a particle beam modulates scattering angle and beam range in a predetermined manner to create a predetermined spread out Bragg peak at a predetermined range. Materials can be “low Z” and “high Z” materials that include fluids. A charged particle beam scatterer/range modulator can comprise a fluid reservoir having opposing walls in a particle beam path and a drive to adjust the distance between the walls of the fluid reservoir under control by a programmable controller. A “high Z” and, independently, a “low Z” reservoir, arranged in series, can be used. When used for radiation treatment, the beam can be monitored by measuring beam intensity, and the programmable controller can adjust the distance between the opposing walls of the “high Z” reservoir and, independently, the distance between the opposing walls of the “low Z” reservoir according to a predetermined relationship to integral beam intensity. Beam scattering and modulation can be done continuously and dynamically during a treatment in order to deposit dose in a target volume in a predetermined three dimensional distribution.
US07718981B2 Composite charged-particle beam system
There is provided a method of arranging, as a composite charged-particle beam system, a gas ion beam apparatus, an FIB and an SEM in order to efficiently prepare a TEM sample. The composite charged-particle beam system includes an FIB lens-barrel 1, an SEM lens-barrel 2, a gas ion beam lens-barrel 3, and a rotary sample stage 9 having an eucentric tilt mechanism and a rotating shaft 10 orthogonal to an eucentric tilt axis 8. In the composite charged-particle beam system, an arrangement is made such that a focused ion beam 4, an electron beam 5 and a gas ion beam 6 intersect at a single point, an axis of the FIB lens-barrel 1 and an axis of the SEM lens barrel 2 are orthogonal to the eucentric tilt axis 8, respectively, and the axis of the FIB lens-barrel 1, an axis of the gas ion beam lens-barrel 3 and the eucentric tilt axis 8 are in one plane.
US07718980B2 Beam processing system and beam processing method
A beam processing system is for causing a particle beam extracted from a beam generating source to pass through a mass analysis magnet device, a mass analysis slit, and a deflection scanner in the order named, thereby irradiating the particle beam onto a processing object. The mass analysis slit is installed between the mass analysis magnet device and the deflection scanner at a position where the particle beam having passed through the mass analysis magnet device converges most in a lateral direction. A first DC quadrupole electromagnet and a second DC quadrupole electromagnet are installed on an upstream side and a downstream side of the mass analysis slit, respectively.
US07718978B2 Ion source and method for operating same
An ion source is provided that can generate an ion beam in which the width is wide, the beam current is large, and the uniformity of the beam current distribution in the width direction is high, and that can prolong the lifetime of a cathode. The ion source 2a has: a plasma generating chamber 6 having an ion extraction port 8 extending in the X direction; a magnet 14 which generates a magnetic field 16 extending along the X direction, in the plasma generating chamber 6; indirectly-heated cathodes 20 which are placed respectively on the both sides of the plasma generating chamber 6 in the X direction, and which are used for generating a plasma i0 in the chamber 6, and increasing or decreasing the density of the whole of the plasma 10; and plural filament cathodes 32 which are juxtaposed in the X direction in the plasma generating chamber 6, and which are used for generating the plasma i0 in the chamber 6, and controlling the density distribution of the plasma 10.
US07718977B2 Stray charged particle removal device
In order to reduce the exposure of a detector surface 180 of a photo-multiplier 160 to stray charged particles, an off-axis structure is interposed between the resonant structure and the detector surface of the photo-multiplier. By providing the off-axis structure with at least one reflective surface, photons are reflected toward the detector surface of the photo-multiplier while at the same time absorbing stray charged particles. Stray particles may be absorbed by the reflective surface or by any other part of the off-axis structure. The off-axis structure may additionally be provided with an electrical bias and/or an absorbing coating for absorbing stray charged particles.
US07718974B2 X-ray converter element
An x-ray converter element has an x-ray-permeable and moisture-impermeable substrate, an x-ray-permeable carrier that is connected to the substrate, and a scintillator that is applied on the substrate, and an optically-transparent and moisture-impermeable protective layer that covers the scintillator.
US07718971B2 Nuclear medicine imaging apparatus and a method for generating image data
The present invention provides a nuclear medicine imaging apparatus and image data generation method that achieves restarting of the generation of projection data and at an early stage while monitoring a variation of count values for detecting an occurrence of non-permissible body movement of a patient. The image processing apparatus consistent with the present invention detects a pair of gamma-rays successively emitted from an object with a radioactive isotope through a pair of detector modules in a data detecting unit. A data processing unit and an incident direction calculating unit in the image processing apparatus respectively calculate a gamma-ray detection position and a gamma-ray incident direction based on the acquired detection signals. A projection data generating unit in the apparatus generates monitoring projection data based on each count value of the detection signals in correspondence to the gamma-ray detection position and the gamma-ray incident direction. A projection data monitoring unit calculates a body movement index of the object by comparing count values of the monitoring projection data that are generated in each of two preferably adjoining monitoring periods. A system control unit generates an alarm signal for performing repetition of the monitoring projection data when the body movement index exceeds a threshold value and displays the alarm signal on a display unit.
US07718967B2 Die temperature sensors
The invention provides a sensor array having a plurality of sensor elements formed in a first substrate and having a plurality of die temperature sensors located thereabout. Each of the die temperature sensors are configured to provide an output related to the temperature of the die on which they are located, the sensor elements providing an output indicative of the intensity of radiation incident thereon.
US07718966B2 Thermal infrared solid state imaging device and infrared camera
An infrared solid state imaging device includes a pixel area with arranged infrared detection pixels and a integration circuit for modulating output current based on the output of the pixel. The integration circuit contains an integrating transistor that modulates a current based on the difference in potential between first and second constant current devices, a integration capacitor for storing the modulated current and being reset periodically, a bias current supply transistor, a switch for connecting the drain with the gate of the bias current supply transistor, a capacitor providing AC coupling between the output of the integrating transistor and the integrating capacitor, a gate bias switch for providing the integrating transistor with a bias voltage, a switch for selecting, as input to the integrating transistor, either one of outputs from the first and second constant current devices, and a capacitor for providing AC coupling between the switch and the gate of the integrating transistor.
US07718965B1 Microbolometer infrared detector elements and methods for forming same
Microbolometer infrared detector elements that may be formed and implemented by varying type/s of precursors used to form amorphous silicon-based microbolometer membrane material/s and/or by varying composition of the final amorphous silicon-based microbolometer membrane material/s (e.g., by adjusting alloy composition) to vary the material properties such as activation energy and carrier mobility. The amorphous silicon-based microbolometer membrane material/s materials may include varying amounts of one or more additional and optional materials, including hydrogen, fluorine, germanium, n-type dopants and p-type dopants.
US07718963B2 Passive solid state ionizing radiation sensor
A radiation sensor and a method for making the radiation sensor are described. An ionizing radiation sensitive area is formed in a radiation insensitive or hardened die. When the sensitive area is impacted by ionizing radiation, properties of the sensitive area change. For example, the changed property may be charge density, threshold voltage, leakage current, and/or resistance. Circuitry for measuring these property changes is located in a radiation hardened area of the die. As a result, a radiation sensor may be fabricated on a single die.
US07718960B2 Ion mobility spectrometer and ion-mobility-spectrometry/mass-spectrometry hybrid spectrometer
A low-cost and high-ion-transmission-ratio ion-mobility spectrometry filter, including an ion source, a first drift region in which a gas flow direction and a DC electric-field direction are opposite to each other, a second drift region in which a gas flow direction is provided, the gas flow direction being different from the gas flow direction in the first drift region, and being opposite to a DC electric-field application direction in the second drift region, an intermediate region having an electric field for causing ions to travel between the first drift region and the second drift region, and a detector for detecting ions which have passed through the first drift region and the second drift region.
US07718958B2 Mass spectroscopic reaction-monitoring method
A mass spectroscopic reaction-monitoring method including: forcing charge-laden liquid drops to move along a traveling path; exposing to a laser beam a region to be formed of a liquid sample surface, the laser beam having an irradiation energy sufficient to cause analytes present behind the liquid sample surface to be desorbed to fly along a flying path; introducing to the region at successive points of time a liquid sample containing one reactant that undergoes an ongoing chemical reaction as a first analyte to form one product as a second analyte; and positioning the liquid sample surface relative to the laser beam at each point of time such that the flying path intersects the traveling path for enabling occlusion of at least one of the first and second analytes in at least one charge-laden liquid drop to thereby form at least a corresponding one of first and second ionized analytes.
US07718952B2 Information carrier
The invention relates to an information carrier (10), having a metal layer (40) with at least one track (14) in which marks (20) are disposed, which can be detected by means of light of a central wavelength (λ) which is emitted by a light source (30) and which is incident upon the information carrier (10) at an angle (θi), and from which the position of the information carrier (10) can be derived, wherein the marks (20) are formed by areas (25) which are structured at least by first structures (22) of a lattice period (Λ) which are disposed on the back side (40b) of the metal layer (40) and/or on the front side (40a) of the metal layer (40), and wherein the lattice period (Λ) of the first structures (22) satisfies the equation Λ=λ/(np*−sin(⊖i)) or Λ=λ/(np*+sin(⊖i)), wherein λ is the central wavelength of the used light, ⊖i is the angle at which the light of the light source (30) is incident upon the information carrier (10) and np* is the effective index of a plasmon mode along the metal layer (40).
US07718949B2 Solid-state imaging element and solid-state imaging device
A solid-state imaging element or the like capable of limiting an abrupt refractive index distribution and collecting incident light at high efficiency is provided. The solid-state imaging element (size: 5.6 μm square) has a distributed index lens, a G color filter, Al wiring, a signal transmitting unit, a planarizing layer, a light receiving element (Si photodiode) and a Si substrate. A concentric structure of the distributed index lens is formed of SiO2 (n=1.43). This structure is a two-stage structure having film thicknesses of 1.2 and 0.8 μm. The distributed index lens is constructed by cutting concentric circular recesses into SiO2 and has a planar region about the center. A medium surrounding the lens is air (n=1).
US07718948B2 Monitoring light pulses
To monitor light pulses from a light source, such as a laser, sense signals are provided to a photosensing component or array, causing photosensing during a series of one or more sense periods for the light pulse. Each light pulse can be provided through a transmission structure, such as a layered structure, that provides output light with an energy-dependent position on the photosensing component. A pulse's sensing results can be used to obtain a set of one or more differential quantities; for example, with a photosensing array, two cells of the array can be read out and compared. For a narrow band light pulse, a transmission structure can provide a spot on the photosensing component, and the light spot position can be sensed.
US07718946B2 Image generating method and apparatus
An image generating method and apparatus are provided. The image generating method irradiates a light with a predetermined wavelength to a target object at a predetermined interval, passes a light having a wavelength required to generate a color image from among lights reflected from the target object, detects color values according to the passed light, generates a depth image of the target object using color values detected during a period in which the light with the predetermined wavelength is irradiated, and generates the color image of the target object using color values detected during a period other than the period in which the light with the predetermined wavelength is irradiated. Accordingly, the image generating method can generate a depth image having high resolution while maintaining the resolution of the color image.
US07718944B2 Solid-state image sensing device and method of operating the same
A charge coupled device is provided with: an output gate; a main CCD region operated in response to a set of clock signals; and an output region positioned between the output gate and the main CCD region and designed to transfer electric charges received from the main CCD region to the output gate. The main CCD region includes first and second transfer electrodes. The output region includes third and fourth transfer electrodes receiving clock signals which are phase-reversed from each other. The set of clock signals received by the main CCD region and the clock signals received by the output region are outputted from different driver circuits.
US07718942B2 Illumination and color management system
Systems and methods for illumination and color management in a system having a plurality of color sources and a plurality of color sensors, wherein there are more color sources than color sensors are described herein. An embodiment of the method includes emitting a plurality of different colors of light from at least two of the color sources, wherein the plurality of colors consist of different intensities of light emitted by the plurality of color sources. Colors of light emitted by the at least two color sources are detected using at least one of the color sensors. The color rendering index for each of the plurality of colors emitted is determined. A color of light to be emitted by the light sources is selected. The intensities of light to be emitted by the color sources is selected, based at least in part on the color rendering index, to achieve the selected color of light.
US07718933B2 Methods and systems for direct manufacturing temperature control
Methods and systems for direct manufacturing are provided. The system includes a part bed, a deck disposed within the part bed, and a heater configured to heat a workpiece area adjacent the deck. The heater includes a plurality of individually movable heating elements wherein the heating elements are movable in a plane parallel with the deck, rotatable about an element mounting point such that an amount of heat directed towards the workpiece area is controllable using the rotation, and the heater is movable in a direction substantially normal to the deck.
US07718921B2 Active beam delivery system with variable optical path segment through air
A laser energy delivery system includes a relay imaging system. Input optics arranged to receive the laser energy, a transmitting mirror having adjustable angle of incidence relative to the input optics, and a robot mounted optical assembly are configured to direct laser energy toward the movable target image plane. The laser energy follows an optical path including an essentially straight segment from the transmitting mirror to the receiving mirror, having a variable length and a variable angle relative to the input optics through air. Diagnostics on the processing head facilitate operation.
US07718920B2 Method and device for holding sheet-like workpiece
There is provided a method and a device capable of holding a sheet-like workpiece without wrinkles. The sheet-like workpiece holding method includes mounting the sheet-like workpiece such that almost no tensile force is applied thereon on a machining table, and pressing out wrinkles of the sheet-like workpiece by lowering a pressing member whose surface facing to the workpiece protrudes in the shape of a convex lens toward the workpiece so that the workpiece is pressed against the machining table. The method also includes retaining the sheet-like workpiece on the machining table using suction while continuously pressing the sheet-like workpiece with the pressing member and releasing the pressing force of the pressing member while retaining the sheet-like workpiece.
US07718919B2 Industrial plasma reactor for plasma assisted thermal debinding of powder injection-molded parts
Industrial plasma reactor for plasma assisted thermal debinding of power injection-molded parts is a reactor used for the plasma assisted debinding and sintering of metallic or ceramic parts produced by the powder injection molding process, comprising a vacuum chamber (1) containing a cathode-anode (7,8) system for plasma generation and a resistive heating system (6) in the same vacuum chamber (1) ambient.
US07718916B2 Low impact spot welding cylinder using dual pistons
A weld cylinder having a dual piston arrangement is provided. The cylinder has a movable retract piston assembly with the piston arranged within the retract piston assembly. The piston supports a rod that is movable between home, intermediate, work, and advanced work positions. The rod moves rapidly from the home position to the intermediate position however, the rod moves more slowly from the intermediate position to the work position to reduce the impact force. A cushion chamber slowly exhausts through a hole in the cushion valve while an isolator is in an open position. Once the cushion valve opens in response to a weld-forward pressure on the cushion valve, the cushion chamber exhausts rapidly so that weld force increases rapidly to minimize increases in cycle time.
US07718913B2 Actuation by cylindrical CAM of a circuit-breaker for an alternator
An alternator disconnector circuit-breaker of the invention includes a cylindrical cam (40) for optimizing the sequence for opening/closing the switch-over first switch (10), the circuit-breaker second switch (20), and the disconnector third switch (30). The cam (40) has a cylindrical wall in which three slots (42), and preferably three pairs of slots, of different shapes, are defined; an end element of an element driving a respective one of the switch contacts is mounted to slide in each slot.
US07718912B2 Outer surface-inspecting method and outer surface-inspecting apparatus
A outer surface-inspecting method for judging whether a defect of a defective portion (27) extracted from an inspection area in an image (21A) of an object to be inspected through comparison with a template is acceptable or not, including: dividing the inspection area into a plurality of sections (22, 23, 24a, 24b, 25a, 25b, 28a, 28b, 28c) respectively having different acceptable levels (CONDITION 1-6); judging, when at least one extracted defective portion (27) spreads out over some of the sections (28a, 28b, 28c) respectively having different acceptable levels, whether the defect of the defective portion (27) is acceptable or not based on a strictest acceptable level (CONDITION 3) of all the acceptable levels (CONDITION 3-5) respectively set on the plurality of sections (28a, 28b, 28c) on which the defective portion (27) is located.
US07718906B2 Hand-held devices with touch sensing on/off operation
A hand-held battery powered device senses when it is picked up, and then automatically turns on. When the device is released or set back down, it automatically turns off. Touch or contact sensors sense the touch of a human hand, causing a circuit in the device to switch on a light source, such as an LED, or a motor, or other load. The device is advantageously designed so that when grasped or picked up, the fingers of the user's hand lay over touch sensors. Various types of touch sensors may be used. The touch sensors operate electrically, and without any movement, or moving parts.
US07718904B2 Enhancing shock resistance in semiconductor packages
A shock load applied to a solder ball may be cushioned by providing a viscoelastic material in association with the solder ball. The viscoelastic material dampens shock loads applied to the solder ball and reduces the rate of failure between the solder ball and the rest of the package.
US07718903B2 Component placement substrate and production method thereof
The component placement substrate of the present invention can be produced easily with suppressed cracks in a thin film formed on a pattern film of the substrate. The present invention provides a component placement substrate provided with one or more pattern films on a substrate, wherein at least one of the pattern film(s) has a cross-sectional shape composed of a semi-elliptical circular upper part, and one of a forward taper shaped lower part and a approximately vertical taper shaped lower part and the average thickness of the lower part is 50 Å or larger and 3,000 Å or smaller.
US07718901B2 Electronic parts substrate and method for manufacturing the same
An electronic parts substrate includes a base substrate, a plurality of insulating resin layers provided on the base substrate, at least one conductive circuit, and at least one filled via provided in the plurality of insulating resin layers. The at least one conductive circuit is sandwiched between the plurality of insulating resin layers and/or between the base substrate and the plurality of insulating resin layers. At least one opening is formed in at least one of the plurality of insulating resin layers.
US07718900B2 Electronic parts packaging structure and method of manufacturing the same
An electronic parts packaging structure including an insulating layer acting as a flexible substrate, an electronic parts buried in the insulating layer in a state that a whole electronic parts is covered with the insulating layer, and a wiring layer buried in the insulating layer and connected electrically to a connection pad of the electronic parts. A structure body in which a plurality of electronic parts are buried in the insulating layer may be folded and electronic parts may be connected electrically.
US07718899B2 High pressure, high voltage penetrator assembly for subsea use
The invention relates to a high pressure, high voltage penetrator assembly for subsea use, wherein the assembly is upright attachable to a wet gas, subsea gas compressor, and wherein the assembly includes a penetrator unit for feed-through of electric power to a compressor motor; a funnel shaped housing with a housing chamber, the penetrator unit being located at an upper end of the chamber; a grid located inside the chamber transversely of a longitudinal axis of the chamber, the penetrator unit being located above the grid, a filter located in the chamber below the grid and above an inlet to a housing of the compressor motor, and a sensor unit extending into the chamber from the penetrator unit and towards, but spaced from the grid.
US07718897B2 Low AC loss superconductor for a superconducting magnet and method of making same
A low AC loss electrical conductor includes an electrically conductive core surrounded by a first layer of superconductor filaments. A resistive shell surrounds the first layer and an insulation coating radially encloses the resistive shell.
US07718892B2 Control module housing
A housing unit for securing electronics of a control module to a vehicle may include a housing and at least two connection members. The connection members connected to the housing may be adapted to engage an adaptor member (e.g., bracket) configured to be secured to a vehicle. The connection members may include at least one connection member configured to hook into the adaptor member and at least one connection member configured to snap into the adaptor member. Protrusion(s) may be included on the connection member(s) and be configured to contact the adaptor member to substantially eliminate transverse movement of the housing. The protrusion(s) may be crush-rib(s). The housing may include features to position, support, and minimize vibration of the electronics, where the electronics maybe disposed on a printed circuit board (PCB).
US07718890B1 Method and apparatus for electrical box repair cover
A method and apparatus for an electrical box repair cover have been described. The repair cover has two or more attachment points which extend beyond the electrical box which it covers. The repair cover may be secured to the electrical box by various techniques including straps, clamps, etc.
US07718889B2 Adjustable scalable rack power system and method
Systems and method for installing computer equipment and power distribution equipment in facilities is provided. In one aspect, the present invention provides an uninterruptible power supply system for use with a plurality of devices, each of the plurality of devices having a power input to receive power. The uninterruptible power supply system includes an equipment rack, an input to receive input power, a DC power source mounted in the equipment rack that provides DC power, an output that provides output power derived from at least one of the input power and the DC power, power distribution circuitry, mounted within the equipment rack, having a plurality of distribution devices each having an input coupled to the output to receive the output power, and a plurality of output power cables each having a first end coupled to one of the plurality of distribution devices to receive output power and a second end that mates with the power input of one of the plurality of devices.
US07718888B2 Solar cell having polymer heterojunction contacts
A solar cell having backside contacts is economically fabricated through use of acceptor and donor polymers which are inkjet printed in interleaved patterns on the back surface as the carrier accepting electrodes of the solar cell. The polymers can be placed on a tunnel oxide on the surface of a semiconductor substrate, or the polymers can be in direct contact with the semiconductor substrate. Electrical patterns interconnecting the acceptor and donor polymer patterns can also be formed by inkjet printing a seed layer and then electroplating the seed layer. Advantageously, high temperature processing is not required in the process as is required in conventional solar cell fabrication using dopant implants into the semiconductor substrate. In alternative embodiments, doped contacts are diffused in the top surface and a polymer contact is formed over the back surface.
US07718885B2 Expressive music synthesizer with control sequence look ahead capability
The present synthesizer includes functionality for changing over from a current note to the following notes that results in natural and expressive combinations and transitions. The method of the present invention incorporates an delay (actual, functional, or look ahead) between receiving control data inputs and generating an output sound. This period of delay is used to modify how notes will be played according to control data inputs for later notes. The input to the synthesizer is typically a time-varying MIDI stream, which may be provided by a musician or a MIDI sequencer from stored data. An actual delay occurs when the synthesizer receives a MIDI stream and buffers it while looking ahead for changeovers between notes. A functional delay occurs in a system in which the synthesizer has knowledge of note changeovers ahead of time. A look ahead delay occurs when the synthesizer queries the sequencer for information about the stored sequence ahead of when the synthesizer needs to generate the output for the sequence.
US07718881B2 Method and electronic device for determining a characteristic of a content item
The method of determining a characteristic of a content item comprises the steps of selecting (1) data representative of a plurality of sounds from the content item, determining (3) a characteristic of each of the plurality of sounds by analyzing said data, each characteristic representing a temporal aspect of an amplitude of one of the plurality of sounds, and determining (5) the characteristic of the content item based on the plurality of determined characteristics. The characteristic of the content item and/or a genre and/or mood based on the characteristic of the content item may be associated with the content item as an attribute value. If the content item is part of a collection of content items, the attribute value can be used in a method of searching for a content item in the collection of content items. The electronic device of the invention comprises electronic circuitry. The electronic circuitry is operative to perform one or both methods of the invention.
US07718879B2 Hammer shank of piano and method of manufacturing the same
There is provided a hammer shank for a piano which is capable of suppressing a change in the dimension between two arms due to dryness and wetness to thereby ensure smooth and stable operation of a hammer. A hammer shank is supported by a flange and pivotally moves in accordance with key depression. A shank body formed of wood has two bifurcated arms formed on one end thereof. These arms extend in facing and parallel relation to each other along respective opposite sides of the flange, and are pivotally supported by the flange. Phenol backers are attached on outer side surfaces of the respective two arms so as to prevent the two arms from being displaced in a direction in which they face each other.
US07718877B2 Device and musical instrument
The invention relates to a device for setting skin tension, in particular for use in a musical instrument such as a kettledrum. The device comprises a tensioning star provided with an engaging element for engaging an operating mechanism for adjusting the tensioning star in an axial adjusting direction, substantially parallel to a central axis of the tensioning star. The tensioning star is also provided with a plurality of arms extending substantially in radial directions of which at least a part is provided with a coupling element for coupling to a tensioning rod construction attachable to the skin. In addition, the device comprises an adjusting device for adjusting the distance between a coupling element and the central axis of the tensioning star.
US07718876B1 Angled grain drum shell ply configuration
In a drum shell, the combination comprising the shell having multiple wooden curved plys, each ply having a grain extending in a characteristic direction, the grain direction of at least one ply extending crosswise relation to the grain direction of the next adjacent ply.
US07718875B2 Guitar cord securing apparatus
In an embodiment, an apparatus includes a first section including a protrusion-engaging portion and a second section including a first coupling member adapted to mate to a second coupling member attachable to a guitar cord.
US07718872B2 Repetition action mechanism for an upright piano
An improved device for providing the magic touch effect during a double repetition in an upright piano wherein the device comprises a plurality of keys swingably mounted on a keyboard frame and supporting a suitably inclined slanted drive element, which can be screw adjusted and is intercoupled to a slanted swinging arm that operates as a control lever that is pivoted to an abruptly clockwise downstream slanted main bridge having an escapement lever coupled to a butt roller of a hammer, pivoted to a first pillar element, that supports adjusting buttons for adjusting a first and second escapements. The main bridge assembly is coupled to a second pillar element, that is pivoted to the lever of the second escapement.
US07718870B1 Plants and seeds of hybrid corn variety CH771816
According to the invention, there is provided seed and plants of the hybrid corn variety designated CH771816. The invention thus relates to the plants, seeds and tissue cultures of the variety CH771816, and to methods for producing a corn plant produced by crossing a corn plant of variety CH771816 with itself or with another corn plant, such as a plant of another variety. The invention further relates to genetic complements of plants of variety CH771816.
US07718868B1 Plants and seeds of corn variety CV319521
According to the invention, there is provided seed and plants of the corn variety designated CV319521. The invention thus relates to the plants, seeds and tissue cultures of the variety CV319521, and to methods for producing a corn plant produced by crossing a corn plant of variety CV319521 with itself or with another corn plant, such as a plant of another variety. The invention further relates to corn seeds and plants produced by crossing plants of variety CV319521 with plants of another variety, such as another inbred line. The invention further relates to the inbred and hybrid genetic complements of plants of variety CV319521.
US07718865B2 Plants and seeds of hybrid corn variety CH490055
According to the invention, there is provided seed and plants of the hybrid corn variety designated CH490055. The invention thus relates to the plants, seeds and tissue cultures of the variety CH490055, and to methods for producing a corn plant produced by crossing a corn plant of variety CH490055 with itself or with another corn plant, such as a plant of another variety. The invention further relates to genetic complements of plants of variety CH490055.
US07718863B2 Plants and seeds of hybrid corn variety CH465107
According to the invention, there is provided seed and plants of the hybrid corn variety designated CH465107. The invention thus relates to the plants, seeds and tissue cultures of the variety CH465107, and to methods for producing a corn plant produced by crossing a corn plant of variety CH465107 with itself or with another corn plant, such as a plant of another variety. The invention further relates to genetic complements of plants of variety CH465107.
US07718860B2 Plants and seeds of corn variety CV911339
According to the invention, there is provided seed and plants of the corn variety designated CV911339. The invention thus relates to the plants, seeds and tissue cultures of the variety CV911339, and to methods for producing a corn plant produced by crossing a corn plant of variety CV911339 with itself or with another corn plant, such as a plant of another variety. The invention further relates to corn seeds and plants produced by crossing plants of variety CV911339 with plants of another variety, such as another inbred line. The invention further relates to the inbred and hybrid genetic complements of plants of variety CV911339.
US07718855B1 Inbred corn line SY0705W
An inbred corn line, designated SY0705W, the plants and seeds of the inbred corn line SY0705W, methods for producing a corn plant, either inbred or hybrid, produced by crossing the inbred corn line SY0705W with itself or with another corn plant, and hybrid corn seeds and plants produced by crossing the inbred line SY0705W with another corn line or plant and to methods for producing a corn plant containing in its genetic material one or more transgenes and to the transgenic corn plants produced by that method. This invention also relates to inbred corn lines derived from inbred corn line SY0705W, to methods for producing other inbred corn lines derived from inbred corn line SY0705W and to the inbred corn lines derived by the use of those methods.
US07718853B1 Soybean cultivar S07-03JR103829
The present invention is in the field of soybean cultivar S07-03JR103829 breeding and development. The present invention particularly relates to the soybean cultivar S07-03JR103829 and its progeny, and methods of making S07-03JR103829.
US07718850B2 Methods and means for delaying seed shattering in plants
The invention relates to methods and compositions for modulating properties of fruit dehiscence in plants such Brassicaceae plants, specifically to improved methods and means for reducing seed shattering in Brassicaceae plants, particularly the Brassicaceae plants grown for oil production, to a degree which is agronomically important.
US07718849B2 Use of a tospoviral nucleid acid molecule for broad-spectrum transgenic resistance against different tospoviruses
A method of using a tospoviral nucleic acid molecule of the sequence of nt (nucleotide) 3975-4928 in accordance with GenBank Accession No. AF133128 or a full complement thereof comprising the steps of: (a) obtaining at least one fragment made from the tospoviral nucleic acid molecule; (b) obtaining a transgene from the at least one fragment; (c) introducing the transgene into a plant to generate a transgenic plant; (d) culturing the transgenic plant; (e) selecting a transgenic plant with broad-spectrum resistance; and (f) obtaining the transgenic plant with broad-spectrum resistance.
US07718848B2 Safe production of a product of interest in hybrid seeds
A process of the production of a product of interest in an F1 seed obtained by a hybridization of a first and a second transgenic parental plant, said hybridization generating a genetic endowment in said F1 seed for said production by combining in said F1 seed first and second partial genetic endowments of said first and second transgenic parental plants, followed by isolating said product of interest from said F1 seed or a seedling thereof.
US07718844B2 Absorbent article having an interior graphic
An absorbent article has an outer cover at least in part defining the outer surface of the article and a liner in opposed relationship with the outer cover and at least in part defining the inner surface of the article. An absorbent structure is disposed between the liner and the outer cover. At least one graphic is visible from the inner surface of the article. The at least one graphic disposed intermediate the inner surface and the outer surface of the article and being free from direct contact with the liner. The article being configured such that the graphic is visible from the inner surface of the article. A process for manufacturing an absorbent article having a graphic visible from the inner surface of the article is provided.
US07718829B2 Production method of acrolein
The present invention has an object to provide a production method of acrolein capable of producing acrolein with suppressing the yield change with time. The production method of the invention is that glycerin is dehydrated under coexistence with a catalyst having crystalline metallosilicates containing at least one kind of T atoms and 15% by mass or less of a binder, and the Si atoms to T atoms ratio (Si/T) of the catalyst is 800 or less.
US07718825B2 Arylamine process
A process for converting an arylamine into an arylamine derivative, includes (i) providing a first arylamine compound; (ii) formylating the first arylamine compound to form a formyl substituted arylamine compound, where the first arylamine compound is not a formyl substituted arylamine compound; and (iii) acidifying the formyl substituted arylamine compound, in the presence of a solvent and a solid organic catalyst, to convert formyl functional groups into acid functional groups to form an acidified compound.
US07718820B2 Process for the preparation of an alkanediol and a dialkyl carbonate
An alkanediol and a dialkyl carbonate are prepared in a process comprising: (a) reacting an alkylene carbonate and an alkanol feedstock in a first reaction zone under transesterification conditions to obtain a product mixture of dialkyl carbonate, unconverted alkanol, the alkanediol, unconverted alkylene carbonate and dimers of the alkanediol; (b) separating dialkyl carbonate and alkanol from the product mixture to obtain a bottom product stream containing alkanediol, unconverted alkylene carbonate and dimers of the alkanediol; (c) recovering the dialkyl carbonate; and (d) separating alkanediol from the bottom product stream to leave a recycle stream comprising unconverted alkylene carbonate and dimers of the alkanediol, which process further comprises (e) passing at least part of the recycle stream to a second reaction zone in which the dimers of the alkanediol are converted to higher-boiling oligomers of alkanediol, yielding an oligomers-containing effluent; (f) separating the higher-boiling oligomers from the oligomers-containing effluent yielding an alkylene carbonate-containing remaining stream; and (g) recycling the alkylene carbonate-containing remaining stream to the first reaction zone.
US07718819B2 Process for making organofunctional silanes and mixtures thereof
A process is provided for preparing organofunctional silanes, inclusive of dimers and oligomers, in which individual silanes possess both free and blocked mercaptan functionality or particular mixtures of the organofunctional silanes possess both free and blocked mercaptan functionality. The organofunctional silanes and silane mixtures are useful, inter alia, as coupling agents for elastomeric compositions, e.g., rubber formulations employed in the manufacture of tires, where they exhibit a desirable balance of low scorch and good performance properties.
US07718816B2 Carboxamide derivative, processes for producing the same, and detergent composition
To provide: a carboxamide derivative having reduced content of amide ester; a method for producing thereof; and a detergent composition containing the carboxamide derivative and having excellent low-temperature stability. One method for producing a carboxamide derivative is to react carboxamide, produced with a manufacturing method of carboxamide including 0.02% by weight to 0.18% by weight of amide ester, with hydrogen peroxide, wherein the method includes a carboxamide synthesis process to synthesize carboxamide by reacting diamine with fatty acid ester at a molar rate of 1.20 to 1.60. Another method for producing a carboxamide derivative is to react the carboxamide with monohaloalkylcarboxylic acid or a salt thereof. A carboxamide derivative is produced by the method for producing a carboxamide derivative. A detergent composition includes the carboxamide derivative. The carboxamide derivative is preferably amidoamine oxide or amide betaine.
US07718809B2 Chromane substituted benzimidazole derivatives as acid pump antagonists
This invention relates to compounds of the formula (I): or a pharmaceutically acceptable salt thereof, wherein: A, B, X, R1, R2, R3, R4, R5 and R6, R7, R8 and R9 are each as described herein or a pharmaceutically acceptable salt, and compositions containing such compounds and the use of such compounds in the treatment of a condition mediated by acid pump antagonistic activity such as, but not limited to, as gastrointestinal disease, gastroesophageal disease, gastroesophageal reflux disease (GERD), peptic ulcer, gastric ulcer, duodenal ulcer, NSAID-induced ulcers, gastritis, infection of Helicobacter pylori, dyspepsia, functional dyspepsia, Zollinger-Ellison syndrome, non-erosive reflux disease (NERD), visceral pain, heartburn, nausea, esophagitis, dysphagia, hypersalivation, airway disorders or asthma.
US07718807B2 Salt of 1,2-dihydropyridine compound
An acid addition salt of 3-(2-cyanophenyl)-5-(2-pyridyl)-1-phenyl-1,2-dihydropyridin-2-one or a hydrate thereof, wherein the acid is selected from the group consisting of benzenesulfonic acid, p-toluenesulfonic acid, hydrochloric acid, hydrobromic acid, sulfuric acid, methanesulfonic acid, fumaric acid, tartaric acid, succinic acid and benzoic acid.
US07718806B2 Process for production of carbostyril compound
The invention provides an improved process for preparing a carbostyril compound (1) or a salt thereof that is useful as a medicament, which makes it possible to prepare it more safely and efficiently.In more detail, the invention provides an improved process for preparing the carbostyril compound (1) by heating the compound (4) with a high boiling solvent in hydrochloric acid under reflux to give the compound (5) safely; and then acylating the compound (5).
US07718795B2 Succinoylamino benzodiazepines as inhibitors of aβ protein production
This invention relates to novel lactams having the formula (I): to their pharmaceutical compositions and to their methods of use. These novel compounds inhibit the processing of amyloid precursor protein and, more specifically, inhibit the production of Aβ-peptide, thereby acting to prevent the formation of neurological deposits of amyloid protein. More particularly, the present invention relates to the treatment of neurological disorders related to β-amyloid production such as Alzheimer's disease and Down's Syndrome.
US07718793B2 Method for the preparation of 6-α fluoro corticosteroids
A method for producing a 6α-fluorinated corticosteroid or derivative thereof by reacting a 17-hydroxy-21-ester epoxide of Formula II with a stereoselective fluorinating agent to stereoselectively form a 21-ester-17-hydroxy 6α-fluorinated compound of Formula VII R1 can be OC(O)—Rd; R4 can be C(O)—Rd; R3 can be H or Rd. Each Rd may be the same or different and is independently selected from (C1-4)alkyl, aryl and heteroaryl. The dashed line can be a single or a double bond. R4 may be, for example, acetyl; R3 may be, for example, alpha or beta methyl; R1 may be, for example, acetate or propionate, The stereoselective fluorinating agent used in the reaction may be, for example, a fluoropyridinium or fluoroquinuclidium compound, for example, Selectfluor®.
US07718792B2 Stereospecific reduction of sapogen-3-ones
A method to stereospecifically prepare a steroidal sapogenin or a derivative thereof by reducing a 3-keto,5β-H steroidal sapogenin with a hindered organoborane or an organo-aluminium hydride. A 3β-hydroxy,5β-H steroidal sapogenin or derivative thereof may be prepared by reducing the 3-keto,5β-H steroidal sapogenin using as reducing agent a relatively highly hindered organoborane reagent or by SN 2 inversion of a 3α-hydroxy,5β-H steroidal sapogenin or derivative thereof. The organo-aluminium hydride may be used to prepare a 3α,5β-H steroidal sapogenin or derivative thereof. The invention provides a convenient route to useful steroidal sapogenins such as sarsasapogenin, episarsasapogenin, smilagenin, epismilagenin and esters thereof, from readily available or easily preparable starting materials (e.g. diosgenone, preparable from diosgenin).
US07718779B2 Prophylactic and therapeutic monoclonal antibodies
In this application are described monoclonal antibodies which specifically recognize V antigen of Y. pestis and epitopes recognized by these monoclonal antibodies. Also provided are mixtures of antibodies of the present invention, as well as methods of using individual antibodies or mixtures thereof for the detection, prevention, and/or therapeutical treatment of plague infections in vitro and in vivo.
US07718777B2 MHC-peptide complex binding ligands
Disclosed are protein ligands comprising an immunoglobulin heavy chain variable (VH) domain and an immunoglobulin light chain variable (VL) domain, wherein the proteins bind a complex comprising an MHC and a peptide, do not substantially bind the MHC in the absence of the bound peptide, and do not substantially bind the peptide in the absence of the MHC, and the peptide is a peptide fragment of gp100, MUC1, TAX, or hTERT. Also disclosed are methods of using and identifying such ligands.
US07718776B2 Human anti-OPGL neutralizing antibodies as selective OPGL pathway inhibitors
Monoclonal antibodies and hybridomas producing them that interact with osteoprotegerin ligand (OPGL) are provided. Methods of treating osteopenic disorders by administering a pharmaceutically effective amount of antibodies to OPGL are also provided. Methods of detecting the amount of OPGL in a sample using antibodies to OPGL are further provided.
US07718772B2 Canine thymic stromal lymphopoietin protein and uses thereof
The present invention discloses a canine TSLP protein and a nucleic acid that encodes that protein. Peptide fragments of the protein that comprise specific epitopes of the canine TSLP protein are also disclosed. The canine TSLP protein and related peptide fragments may be used as an antigen for immunological assays, as well as for vaccines that induce anti-TSLP antibodies. The present invention further discloses methods of making and using the canine TSLP gene, the canine TSLP protein, and the related peptide fragments.
US07718769B2 Tri-peptide hepatitis C serine protease inhibitors
The present invention relates to compounds of Formula I, or a pharmaceutically acceptable salt, ester, or prodrug, thereof: which inhibit serine protease activity, particularly the activity of hepatitis c virus (HCV) NS3-NS4A protease. Consequently, the compounds of the present invention interfere with the life cycle of the hepatitis c virus and are also useful as antiviral agents. The present invention further relates to pharmaceutical compositions comprising the aforementioned compounds for administration to a subject suffering from HCV infection. The invention also relates to methods of treating an HCV infection in a subject by administering a pharmaceutical composition comprising the compounds of the present invention.
US07718768B2 Biologically active peptide PTTKTYFPHF
Thirty substantially pure and biologically active peptides are disclosed. Nucleic acids that have sequences coding for the biologically active peptides and pharmaceutical formulations produced therefrom are also disclosed.
US07718767B2 3-ether and 3-thioether substituted cyclosporin derivatives for the treatment and prevention of hepatitis C infection
This invention relates to cyclosporin derivatives of general formula (I): wherein A, B, R1, R2 and X are as defined in the specification, and pharmaceutical compositions prepared from the same, for use in treatment of hepatitis C virus.
US07718766B2 Fret protease assays for botulinum serotype A/E toxins
The present invention provides clostridial toxin substrates useful in assaying for the protease activity of any clostridial toxin, including botulinum toxins of all serotypes as well as tetanus toxins. A clostridial toxin substrate of the invention contains a donor fluorophore; an acceptor having an absorbance spectrum overlapping the emission spectrum of the donor fluorophore; and a clostridial toxin recognition sequence that includes a cleavage site, where the cleavage site intervenes between the donor fluorophore and the acceptor and where, under the appropriate conditions, resonance energy transfer is exhibited between the donor fluorophore and the acceptor.
US07718759B2 Polyester process using a pipe reactor
The invention is directed to polyester processes that utilizes a pipe reactor in the esterification, polycondensation, or both esterification and polycondensation processes. Pipe reactor processes of the present invention have a multitude of advantages over prior art processes including improved heat transfer, volume control, agitation and disengagement functions.
US07718752B2 Process for producing resorcinol-formalin resin
A process for producing a resorcinol-formalin resin containing no salts, having a moderate flowability when transformed into an aqueous solution, and having a reduced content of resorcinol monomer and a reduced content of resorcinol-formalin resin of resorcinol pentanuclear or higher nuclear bodies, the whole steps including an one-stage reaction and liquid-liquid distribution being conducted in the same reactor, which comprises adding resorcinol, an inorganic salt, and an organic solvent having a solubility parameter of 7.0 to 12.5 to a water solvent, stirring the mixture to give a two-phase system containing no remaining solid matter, adding an acid catalyst, adding formalin dropwise into the reaction system to cause a liquid-liquid heterogeneous reaction to proceed, removing the aqueous layer, adding an organic solvent and water to the reaction product layer, the amount of the water being half of the amount of the organic solvent, stirring the resulting mixture, allowing it to stand, and then removing the aqueous layer to obtain the resorcinol-formalin resin.
US07718751B2 Syntactic phenolic foam composition
The present invention concerns a pre-mix for a syntactic phenolic foam composition; a syntactic phenolic foam composition; and a process for preparing the syntactic phenolic foam composition.The pre-mix comprises thermally expandable and/or expanded thermoplastic microspheres, the microspheres comprising a thermoplastic polymer shell made of a homopolymer or copolymer of 100 to 25, for example 93 to 40, parts by weight of a nitrile-containing, ethylenically unsaturated monomer, or a mixture thereof; and 0 to 75, for example 7 to 60, parts by weight of a non-nitrile-containing, ethylenically unsaturated monomer, or a mixture thereof; and a propellant, or a mixture thereof, trapped within the thermoplastic polymer shell; and one of either a highly reactive phenolic resole resin capable of fully crosslinking at temperatures between 15° C. and 60° C., optionally in the presence of up to ten times its own weight in water, and having, typically, a free phenol content of 12-15% (w/w); or an acidic catalyst for curing the phenolic resole resin.The process comprises either curing the above-mentioned pre-mix in the presence of the other of the acidic catalyst; and the highly reactive phenolic resole resin, as defined above or, alternatively, curing all three components, together with any other components.
US07718750B2 Multi alkoxylated silicone surfactants
The present invention is directed to organo-silicone compound that have alkoxylated allyl alcohol groups of different degree of ethylene oxide and or propylene oxide present on two or more different groups. It is also directed to the use of that compound in personal care and other applications. These compounds by virtue of their unique structure provide outstanding emulsions including microemulsions.
US07718748B2 Antimicrobial polymerizable ear piece material
A two-component addition-crosslinking silicone comprises(a) 0.1-70% by weight polyorganosiloxanes containing at least two unsaturated groups in the molecule;(b) 0.1-15% by weight polyorganohydrogensiloxanes containing at least two SiH groups in the molecule;(c) 0.01-2.0% by weight noble metal catalyst; and(d) 0.1-5% by weight of a non-toxic antimicrobial additive or a combination of at least two non-toxic antimicrobial additives.
US07718746B2 Anion-binding polymers and uses thereof
Anion-binding polymers are described. The anion-binding polymers in some cases are low swelling anion-binding polymers. In some cases, the anion-binding polymers have a pore volume distribution such that a fraction of the polymer is not available for non-interacting solutes above a certain percentage of the MW of the target ion for the polymer. In some cases, the anion-binding polymers are characterized by low ion-binding interference, where the interference is measured in, for example, a gastrointestinal simulant, relative to non-interfering buffer. Pharmaceutical composition, methods of use, and kits are also described.
US07718741B2 Epoxy resin composition and cured article thereof, novel epoxy resin and production method thereof, and novel phenol resin
The present invention relates to a composition containing as a main component, an epoxy resin which has a structure comprising a polyaryleneoxy structure such as polynaphthylene oxide as a main skeleton, (methyl)glycidyloxy group and aralkyl group being introduced on an aromatic ring of the polyaryleneoxy structure, and which has low viscosity, according to the present invention, there can be provided an epoxy resin composition which can impart remarkably excellent flame retardancy and dielectric characteristics to a cured article and a cured article thereof, an epoxy resin, a phenol resin as an intermediate of the epoxy resin, and a method for producing the epoxy resin.
US07718739B2 Polyalkenoate cement compositions and methods of use in cementing applications
Methods and compositions for cementing applications. In one embodiment, the present invention provides a method of cementing comprising the steps of: providing a cement composition that comprises: a polyelectrolyte and/or an alkenoic acid first monomer; a filler; and a crosslinking agent; placing the cement composition in a desired location; and allowing the cement composition to set therein.
US07718738B2 Self assembly of molecules to form nano-particles
A polymer nano-particle composition is provided, wherein the nano-particle includes a poly(alkenylbenzene) core and a surface layer including poly(conjugated diene). A method for self-assembly of the nano-particles is also provided. The polymer nano-particles are preferably less than about 100 nm in diameter.
US07718733B2 Optically clear polycarbonate polyester compositions
An optically clear thermoplastic resin composition consisting essentially of: structural units derived at least one substituted or unsubstituted polycarbonate, at least greater than 30 weight percent of a substituted or unsubstituted polyester, a modified polycarbonate, an impact modifier having a refractive index in the range between about 1.51 and about 1.56 and an additive is disclosed. The composition possess good optical properties, flow, stability and mechanical property. Also disclosed is a process to prepare these compositions and articles therefrom.
US07718730B2 Two-component silylated polyurethane adhesive, sealant, and coating compositions
A two-component adhesive, sealant, or coating composition containing (i) a first component containing a portion of an alkoxysilane-functional urethane and water; and (ii) a second component containing the remaining portion of the alkoxysilane-functional urethane and a catalyst. The alkoxysilane-functional urethane includes the reaction product of (a) the reaction product of a hydroxy functional compound and a polyisocyanate, that contains isocyanate groups; with (b) an amine functional aspartate. The composition is used in a method of bonding a first substrate to a second substrate. The method includes (a) combining component i) and component ii) to form a mixture, applying a coating of the mixture to at least one surface of the first substrate or the second substrate, and contacting a surface of the first substrate with a surface of the second substrate. The method is used make an assembly.
US07718729B2 Aqueous intermediate coating composition and method for forming multilayer coating film
The present invention provides an aqueous intermediate coating composition comprising (A) an acrylic emulsion resin having a hydroxy value of 5 to 80 mgKOH/g and an acid value of 1 to 15 mgKOH/g, obtainable by emulsion polymerization of monomer mixture (a) comprising ethyl acrylate, a hydroxy-containing radically polymerizable unsaturated monomer and a carboxy-containing radically polymerizable unsaturated monomer, the ethyl acrylate content of the monomer mixture being 60 wt. % or more; (B) a carboxy-containing resin having a hydroxy value of more than 80 mgKOH/g but not more than 200 mgKOH/g; (C) a curing agent; and (D) a coloring pigment, and having a solids content of 60 wt. % or more. The invention also provides a method for forming a multilayer coating film using said aqueous intermediate coating composition.
US07718727B2 Fluoroplastic silicone vulcanizates
Fluoroplastics containing fluorocarbon resins and silicones are prepared by first mixing a fluorocarbon resin with a compatibilizer, then adding a curable organopolysiloxane with a radical initiator, and vulcanizing the organopolysiloxane in the mixture. The fluoroplastics can be processed by various techniques, such as extrusion, vacuum forming, injection molding, blow molding or compression molding, to fabricate plastic parts. The resulting fabricated parts can be re-processed (recycled) with little or no degradation of mechanical properties.
US07718725B2 Smoke and fire inhibitors for PVC
We describe novel compositions and methods for reducing fire and smoke hazards associated with rigid and flexible PVC. Cone calorimetry studies have identified several copper additives that are highly effective as combustion inhibitors for PVC. Mixed-metal oxides of copper(II) are especially attractive in this regard, some of which are strongly synergistic for smoke suppression when they are combined, in particular CuTi3O7 and Cu3(MoO4)2(OH)2. These novel combinations are useful for PVC applications wherein color is not of primary importance.
US07718715B2 pH-modified latex comprising a synergistic combination of biocides
A stabilized latex with improved antimicrobial features is disclosed. In preferred embodiments, this latex comprises a mixture of 2-bromo-2-nitro-1,3-propanediol and 4,4-dimethyl-oxazolidine or 2-bromo-2-nitro-1,3-propanediol and 1-(3-chloroallyl)-3,5,7-triaza-1-azoniaadamantane chloride.
US07718714B2 Resin curable with actinic energy ray, photocurable and thermosetting resin composition containing the same, and cured product obtained therefrom
An actinic energy ray-curable resin is obtained by reacting an unsaturated monocarboxylic acid (c) with a terminal epoxy group of an epoxy resin having an unsaturated group and a hydroxyl group in its side chains and an epoxy group in its terminal and further reacting a polybasic acid anhydride (d) with the hydroxyl group of the above-mentioned epoxy resin, wherein the above-mentioned epoxy resin is a product of the polyaddition reaction of a reaction product (I) of a polybasic acid anhydride (a) and a compound (b) having at least one unsaturated double bond and one alcoholic hydroxyl group in its molecule, a compound (II) having at least two carboxyl groups in its molecule, and a bifunctional epoxy compound (III), wherein at least either one of the carboxyl group-containing compound (II) and the bifunctional epoxy compound (III) is a compound containing no aromatic ring. A photocurable and thermosetting resin composition comprising this actinic energy ray-curable resin, a photopolymerization initiator, a diluent, and a cyclic ether compound is useful as a solder resist for a printed circuit board, interlaminar insulating materials for a multi-layer printed circuit board, and the like.
US07718710B2 Stable concentrated metal colloids and methods of making same
A method for manufacturing stable concentrated colloids containing metal nanoparticles in which the colloid is stabilized by adding a base. This allows the metal particles to be formed in higher concentration without forming larger agglomerates and/or precipitating. The method of manufacturing the stable colloidal metal nanoparticles of the present invention generally includes (i) providing a solution comprising a plurality of metal atoms, (ii) providing a solution comprising a plurality of organic agent molecules, each organic agent molecule comprising at least one functional group capable of bonding to the metal atoms, (iii) reacting the metal atoms in solution with the organic agent molecules in solution to form a mixture comprising a plurality of complexed metal atoms, (iv) reducing the complexed metal atoms in the mixture using a reducing agent to form a plurality of nanoparticles, and (v) adding an amount of a base to the mixture, thereby improving the stability of the nanoparticles in the mixture. The base may be added before or after forming the nanoparticles.
US07718707B2 Method for preparing nanoparticle thin films
A set of nanoparticles is disclosed. Each nanoparticle of the set of nanoparticles is comprised of a set of Group IV atoms arranged in a substantially spherical configuration. Each nanoparticle of the set of nanoparticles further having a sphericity of between about 1.0 and about 2.0; a diameter of between about 4 nm and about 100 nm; and a sintering temperature less than a melting temperature of the set of Group IV atoms.
US07718706B2 Arylphenyl-substituted cyclic keto-enols
The present invention relates to novel arylphenyl-substituted cyclic ketoenols of the formula (I) in which X represents halogen, alkyl, alkoxy, alkenyloxy, alkylthio, alkylsulphinyl, alkylsulphonyl, halogenoalkyl, halogenoalkoxy, halogenoalkenyloxy, nitro, cyano or in each case optionally substituted phenyl, phenoxy, phenylthio, phenylalkoxy or phenylalkylthio, Y represents in each case optionally substituted cycloalkyl, aryl or hetaryl, Z represents hydrogen, halogen, alkyl, alkoxy, alkenyloxy, halogenoalkyl, halogenoalkoxy, halogenoalkenyloxy, nitro or cyano, CKE represents one of the groups in which A, B, D, G and Q1 to Q6 are each as defined in the description, to a plurality of processes for their preparation and to their use as pesticides and herbicides.
US07718703B2 Norvaline derivative and method for preparation thereof
Norvaline derivative of the formula [I] or pharmaceutically acceptable salt thereof, method for preparing the same, pharmaceutical composition containing the same, and use of the compound for inhibiting transporting activity of glycine transporter type 2 (GlyT2) wherein X is —CH2—, —O—, —S— or single bond; Ar is optionally substituted aryl or lower cycloalkyl; n is 0 to 2; R1 and R2 are (i) each is hydrogen or lower alkyl; (ii) R1 and R2 are combined to form lower alkylene; or (iii) R1 is hydrogen or lower alkyl and R2 is combined with R4 or R6 to form lower alkylene; R3 and R4 are (i) each is hydrogen or lower alkyl; (ii) R3 and R4 are combined to form lower alkylene; or (iii) R3 is hydrogen or lower alkyl and R4 is combined with R2 or R6 to form lower alkylene; R is  or —OR7; R5 and R6 are (i) each is optionally substituted lower alkyl, or hydrogen; (ii) R5 and R6 are combined to form aliphatic 5- to 6-membered heterocyclic group; or (iii) R5 is optionally substituted lower alkyl or hydrogen and R6 is combined with R2 or R4 to form lower alkylene; R7 is lower alkyl.
US07718699B1 Abscissic acid and derivatives thereof for the treatment of diseases
The present invention relates generally to the fields of molecular biology and pharmacology. More particularly, it concerns the use of abscissic acid to treat various diseases, including neurodegenerative diseases and neuromuscular diseases.
US07718697B2 Method for treating glaucoma comprising administering α-lipoic acid
The present invention provides compositions and methods for treating glaucoma, ocular hypertension, and age-related macular degeneration. More specifically, the present invention describes the use of agents that down-regulate expression of tanis and/or p21Waf1/Cip1/Sd1 genes to treat such disorders of the eye.
US07718687B2 Prodrugs of mitotic kinesin inhibitors
The present invention relates to prodrugs of dihydropyrazole compounds that are useful for treating cellular proliferative diseases, for treating disorders associated with KSP kinesin activity, and for inhibiting KSP kinesin. The invention also related to compositions which comprise these compounds, and methods of using them to treat cancer in mammals.
US07718684B2 Methods and materials for assessing prostate cancer therapies and compounds
A modest (2-5 fold) increase in androgen receptor (AR) mRNA is the only expression change consistently associated with developing resistance to antiandrogen therapy. Increased levels of AR confer resistance to anti-androgens by amplifying signal output from low levels of residual ligand and altering the normal response to antagonists. This invention provides cell based assays for use in the examination of new therapeutic modalities and provides for the design of novel antiandrogen compounds.
US07718682B2 Heterocyclic analogs of diphenylethylene compounds
Novel diphenylethylene compounds and derivatives thereof containing thiazolidinedione or oxazolidinedione moieties are provided which are effective in lowering blood glucose level, serum insulin, triglyceride and free fatty acid levels in animal models of Type II diabetes. The compounds are disclosed as useful for a variety of treatments including the treatment of inflammation, inflammatory and immunological diseases, insulin resistance, hyperlipidemia, coronary artery disease, cancer and multiple sclerosis.
US07718680B2 Inhibition of lethal factor protease activity from anthrax toxin
The present invention provides compounds that efficiently and specifically inhibit lethal factor (LF) protease activity of anthrax toxin.
US07718679B2 Heteroaryl carboxamides
The invention is concerned with novel heteroaryl carboxamides of formula (I) wherein A, R1, R2, X, Y, Z and m are as defined in the description and in the claims, as well as physiologically acceptable salts thereof. These compounds inhibit the coagulation factor Xa and can be used for the treatment or prevention of thrombotic disorders.
US07718677B2 Methods and compositions for reduction of side effects of therapeutic treatments
The invention provides compositions and methods utilizing a nicotinic receptor modulator, e.g., to reduce or eliminate a side effect associated with dopaminergic agent treatment. In some embodiments, the invention provides compositions and methods utilizing a combination of a dopaminergic agent and a nicotinic receptor modulator that reduces or eliminates a side effect associated with dopaminergic agent treatment.
US07718676B2 2-aminoaryloxazole compounds as tyrosine kinase inhibitors
The present invention relates to novel compounds selected from 2-aminoaryloxazoles of formula I that selectively modulate, regulate, and/or inhibit signal transduction mediated by certain native and/or mutant tyrosine kinases implicated in a variety of human and animal diseases such as cell proliferative, metabolic, allergic, and degenerative disorders. More particularly, these compounds are potent and selective c-kit, bcr-abl, FGFR3 and/or Flt-3 inhibitors.
US07718673B2 Isonipecotamides for the treatment of integrin-mediated disorders
The invention is directed to novel isonipecotamide derivatives of Formula (I): which are useful in treating integrin-mediated disorders.
US07718669B2 Triazolopyridine derivatives as inhibitors of lipases and phospholipases
The invention relates to triazolopyridine derivatives of general formula (I), which are defined as cited in the description, to their pharmaceutically applicable salts and to their use as medicaments.
US07718666B2 Pyrido [2,1-a] isoquinoline derivatives
The present invention relates to compounds of formula (I) wherein R1 is as defined in the description, and pharmaceutically acceptable salts thereof. The compounds are useful for the treatment and/or prophylaxis of diseases which are associated with DPP-IV, such as diabetes, particularly non-insulin dependent diabetes mellitus, and impaired glucose tolerance.
US07718657B2 Certain indanyl urea modulators of the cardiac sarcomere
Certain substituted urea derivatives selectively modulate the cardiac sarcomere, for example by potentiating cardiac myosin, and are useful in the treatment of systolic heart failure including congestive heart failure.
US07718656B2 Prostaglandin derivatives
Nitroderivatives of prostaglandin amides having improved pharmacological activity and enhanced tolerability are described. They can be employed for the treatment of glaucoma and ocular hypertension.
US07718655B2 Trisubstituted triazine compounds, and methods for making and using the compounds, which have antitubulin activity
Trisubstituted triazines can be synthesized from cyanuric chloride. These compounds are useful anti-tubulin agents for treating cancer and proliferative diseases.
US07718652B2 Substituted benzothiadiazinedioxide derivatives and methods of their use
The present invention is directed to substituted benzothiadiazinedioxide derivatives of formula I: or a pharmaceutically acceptable salt, stereoisomer or tautomer thereof, which are monoamine reuptake inhibitors, compositions containing these derivatives, and methods of their use for the prevention and treatment of conditions, including, inter alia, vasomotor symptoms, sexual dysfunction, gastrointestinal disorders and genitourinary disorder, depression disorders, endogenous behavioral disorders, cognitive disorders, diabetic neuropathy, pain, and other diseases or disorders.
US07718648B2 Pyridobenzazepine compounds and methods for inhibiting mitotic progression
This invention relates to compounds and methods for the treatment of cancer. In particular, the invention provides compounds that inhibit Aurora kinase, pharmaceutical compositions comprising the compounds, and methods of using the compounds for the treatment of cancer.
US07718647B2 Substituted azepine derivatives as serotonin receptor modulators
The present invention generally relates to a series of compounds, to pharmaceutical compositions containing the compounds, and to use of the compounds and compositions as therapeutic agents. More specifically, compounds of the present invention are hexahydroazepinoindole and octahydroazepinoindole compounds. These compounds are serotonin receptor (5-HT) ligands and are useful for treating diseases, disorders, and conditions wherein modulation of the activity of serotonin receptors (5-HT) is desired (e.g. anxiety, depression and obesity).
US07718645B2 Substituted bicyclolactam compounds
The invention provides compounds of formula (1), and the pharmaceutically acceptable salt thereof, wherein R1, R2, R3, R4, R5a, R5b, R5c, R5d, Q, A, Z, and R7 are as described herein; compositions thereof; and uses thereof.
US07718639B2 7-hydroxyepiandrosterone having neuroprotective activity
7-Hydroxyepiandrosterone may be used for protection against acute or chronic neuronal damage.
US07718637B2 (20S)-23,23-difluoro-methylene-19-nor-bishomopregnacalciferol-vitamin D analogs
This invention discloses (20S)-23,23-difluoro-2-methylene-19-nor-bishomopregnacalciferol-vitamin D analogs, and specifically (20S)-23,23-difluoro-1α-hydroxy-2-methylene-19-nor-bishomopregnacalciferol, and pharmaceutical uses therefor. This compound exhibits pronounced activity in arresting the proliferation of undifferentiated cells and inducing their differentiation to the monocyte thus evidencing use as an anti-cancer agent and for the treatment of skin diseases such as psoriasis as well as skin conditions such as wrinkles, slack skin, dry skin and insufficient sebum secretion. This compound also has little, if any, calcemic activity and therefore may be used to treat autoimmune disorders or inflammatory diseases in humans as well as renal osteodystrophy. This compound may also be used for the treatment or prevention of obesity.
US07718634B2 Method of treatment using bisphosphonic acid
The present invention refers to a pharmaceutical composition of a bisphosphonic acid or salt thereof, and an excipient thereof, and a method of treating disorder characterized by pathologically increased bone resorption comprising orally administering at least 150% of the expected efficious daily dose of a bisphosphonic acid or a pharmaceutically acceptable salt thereof and one or more pharmaceutically acceptable excipients thereof and administering the dose at a period of one two or three consecutive days per month.
US07718630B2 MicroRNA1 therapies
Delta protein expression in a cell is reduced by introducing miR-1 into the cell, and detecting a resultant reduction of Delta protein expression in the cell.
US07718629B2 Compositions and methods for inhibiting expression of Eg5 gene
The invention relates to a double-stranded ribonucleic acid (dsRNA) for inhibiting the expression of the Eg5 gene (Eg5 gene), comprising an antisense strand having a nucleotide sequence which is less that 30 nucleotides in length, generally 19-25 nucleotides in length, and which is substantially complementary to at least a part of the Eg5 gene. The invention also relates to a pharmaceutical composition comprising the dsRNA together with a pharmaceutically acceptable carrier; methods for treating diseases caused by Eg5 expression and the expression of the Eg5 gene using the pharmaceutical composition; and methods for inhibiting the expression of the Eg5 gene in a cell.
US07718625B2 Polynucleotides targeted against the extended 5′-UTR region of argininosuccinate synthase and uses thereof
The present invention is based in part on the discovery that the upstream open reading frame (uORF) in the extended 5′-untranslated region (5′-UTR) argininosuccinate synthase (AS) mRNA species is functional, and when functional, limits overall AS expression as well as nitric oxide (NO) production. Thus, the extended 5′-UTR AS mRNA species is a mechanism for regulating AS expression and NO production, and provides a target for the treatment of pathophysiological conditions associated with vascular endothelial dysfunction and characterized by impairment of NO production, such as heart failure, hypertension, hypercholesterolemia, atherosclerosis, and diabetes.
US07718620B2 Methods for preventing or treating ischemia-reperfusion injury of the kidney
The invention provides a method of treating or preventing ischemia-reperfusion injury of the kidney in a mammal. The method comprises administering an effective amount of an aromatic-cationic peptide having at least one net positive charge; a minimum of four amino acids; a maximum of about twenty amino acids; a relationship between the minimum number of net positive charges (pm) and the total number of amino acid residues (r) wherein 3pm is the largest number that is less than or equal to r+1; and a relationship between the minimum number of aromatic groups (a) and the total number of net positive charges (pt) wherein 2 a is the largest number that is less than or equal to pt+1, except that when a is 1, pt may also be 1.
US07718614B2 Combination therapy of peptide vaccination and estramustine treatment
A method for treating a prostate cancer, which comprises administering a therapeutically effective amount of a cancer antigen peptide-associated agent and a lower dose of an estramustine or a salt thereof to a patient in need thereof, and a pharmaceutical composition thereof are provided.
US07718613B2 Armed peptides
This invention relates to peptides useful for releasing active agent in the fields of diagnostics and drug delivery.
US07718610B2 Retrocyclins: antiviral and antimicrobial peptides
Retrocyclin peptides are small antimicrobial agents with potent activity against bacteria and viruses. The peptides are nonhemolytic, and exhibit minimal in vitro cytotoxicity. A pharmaceutical composition comprising retrocyclin as an active agent is administered therapeutically to a patient suffering from a bacterial and/or viral infection, or to an individual facing exposure to a bacterial and/or viral infection, especially one caused by the HIV-1 retrovirus or other sexually-transmitted pathogens.
US07718606B2 Methods for treating muscle diseases and disorders
The invention relates to methods of treating diseases and disorders of the muscle tissues in a vertebrate by the administration of compounds which bind the p185erbB2 receptor. These compounds are found to cause increased differentiation and survival of cardiac, skeletal and smooth muscle.
US07718603B1 Selective targeting agents for mitochondria
The present invention provides a composition and related methods for delivering cargo to a mitochondria which includes (a) a membrane active peptidyl fragment having a high affinity with the mitochondria and (b) cargo. The cargo may be selected from a wide variety of desired cargos which are to be delivered to the mitochondria for a specific purpose. Compositions and methods are disclosed for treating an illness that is caused or associated with cellular damage or dysfunction which is caused by excessive mitochondrial production of reaction oxygen species (ROS). Compositions which act as mitochondria-selective targeting agents using the structural signaling of the β-turn recognizable by cells as mitochondria) targeting sequences are discussed. Mitochondria and cell death by way of apoptosis is inhibited as a result of the ROS-scavenging activity, thereby increasing the survival rate of the patient. In a preferred embodiment, the compositions and methods may be administered therapeutically in the field to patients with profound hemorrhagic shock so that survival could be prolonged until it is feasible to obtain surgical control of the bleeding vessels. In further preferred embodiments, the composition for scavenging radicals in a mitochondria membrane includes a radical scavenging agent and a membrane active compound having a high affinity with said mitochondrial membrane and associated methods. In another embodiment, the cargo transported by mitochondrial-selective targeting agents may include an inhibitor of nitric oxide synthase (NOS) enzyme activity.
US07718600B2 IAP binding compounds
Compounds that bind cellular IAPs (inhibitor of apoptosis proteins) are disclosed. The compounds are mimetics of the N-terminal tetrapeptide of IAP-binding proteins, such as Smac/DIABOLO, IIid, Grim and Reaper, which interact with a specific surface groove of IAP. Also disclosed are methods of using these compounds for therapeutic, diagnostic and assay purposes.
US07718598B1 Auxiliary for amide bond formation
This invention relates to methods for preparing cyclic peptides and peptidomimetic compounds in solution and bound to solid supports, and to cyclic peptide or peptidomimetic libraries for use in drug screening programmes. In particular, the invention relates to a generic strategy for synthesis of cyclic peptides or peptidomimetics that enables the efficient synthesis under mild conditions of a wide variety of desired compounds. Two approaches were evaluated for their improvements in solution and solid phase synthesis of small cyclic peptides: positioning reversible N-amide substituents in the sequence; and applying native ligation chemistry in an intramolecular sense. Systematic investigation of the effects of preorganizing peptides prior to cyclisation by using peptide cyclisation auxiliaries, and developing new linkers and peptide cyclisation auxiliaries to aid cyclic peptide synthesis gives surprising improvements in both yields and purity of products compared to the prior art methods. The combination of these technologies provides a powerful generic approach for the solution and solid phase synthesis of small cyclic peptides. The ring contraction and N-amide substitution technology of the invention provide improved methods for the synthesis of cyclic peptides and peptidomimetics. When used in conjunction with linker strategies, this combination provides solid-phase avenues to cyclic peptides and peptidomimetics.
US07718597B2 Fabric softening composition
Aqueous fabric softening composition having good high temperature stability comprising a cationic fabric softening compound and water soluble polysaccharide polymers comprising hydrophobic groups selected from aryl, alkyl, alkenyl, aralkyl each having at least 14 carbon atoms and cationic quaternary ammonium salt groups such that the cationic degree of substitution is from 0.01 to 0.2, the polymers having a molecular weight in the range from 100,000 to 700,000.
US07718596B2 Unit dose laundry products containing fatty acid esters
A unit dose fabric treatment system comprises a water soluble container in which a liquid fabric treatment composition is disposed, the composition comprising one or more fatty acid esters wherein, in at least one of the fatty acid esters, the average proportion of C18 chains is less than 60%, preferably less than 50%, more preferably less than 40%, e.g. less than 30% by weight of the total weight of fatty acid chains in the fatty acid ester.
US07718594B1 Aqueous based chemical and biological warfare decontaminating system for extreme temperature applications
The current invention encompasses a microemulsion having environmentally safe components, the microemulsion exhibiting optical clarity and stability over a wide range of temperatures. The microemulsion also forms a part of a decontaminant solution for treating chemical and biological contaminant agents, the solution preferably containing peroxycarboxylic acids generated from solids as the primary decontamination agent. The solution is a single phase emulsion that is both stable and effective over a broad range of temperatures, the range extending well below 0° C. There is also disclosed a microemulsion decontaminate solution having components that stabilize the included solid and peroxycarboxylic acids.
US07718592B2 Sodium percarbonate particles having a shell layer comprising thiosulfate
Coated sodium percarbonate particles, having an inner shell layer which comprises at least one inorganic, hydrate-forming salt as the main constituent, and an outer shell layer which comprises an alkali metal thiosulfate, an alkaline earth metal thiosulfate and/or an ammonium thiosulfate, are stable to storage and have an improved storage stability in detergents and cleaning agents. Detergents and cleaning agents which comprise such sodium percarbonate particles show a reduced oxidative attack on oxidation-sensitive constituents of the composition during storage. Machine dishwashing agents in the form of tablets which comprise such sodium percarbonate particles and a corrosion protection agent for silver show a reduced yellowing of the tablets during storage.
US07718590B2 Method to remove resist, etch residue, and copper oxide from substrates having copper and low-k dielectric material
A variety of compositions that are particularly applicable for removing one or more of resist, etching residue, planarization residue, and copper oxide from a substrate comprising copper and a low-k dielectric material are described. The resist, residues, and copper oxide are removed by contacting the substrate surface with the composition, typically for a period of 30 seconds to 30 minutes, and at a temperature between 25° and 45° C. The composition includes a fluoride-providing component; at least 1% by weight of a water miscible organic solvent; an organic acid; and at least 81% by weight water. Typically the composition further includes up to about 0.4% of one or more chelators.
US07718589B2 Method for washing the face skin and a composition for carrying out said method
The inventions relate to hygiene and cosmetology, in particular to skin care. The inventive method for washing the skin by applying washing or cleaning agents and water is characterized in that it uses water with pH level ranging from 3.0 to 6.0, wherein the water flow rate ranges from 0.1 to 5 ml per 1 cm3 of the skin surface. The inventive composition comprises water, mineral salts and oxygen dissolved in said water, and also one or several types of essential proteinogenic amino acids with isoelectric point ranging from 3.0 to 6.0 pH, and its hardness is equal to or less than 0.5 mg-equivalent unit/dm3. The inventive method and composition make it possible to correct complex unfavourable changes of the skin surface layers by providing it with the required pH values during and after the washing and also by maintaining the normal chemical and bacteriological condition of the face skin.
US07718588B2 Lubricating oil additive containing acrylic polymer and lubricating oil compositions
A lubricating oil additive containing at least one acrylic block copolymer having a weight-average molecular weight of 10,000 to 1,000,000 and a molecular weight distribution [ratio of weight-average molecular weight (Mw) to number-average molecular weight (Mn), i.e., Mw/Mn ratio] of 1.5 or below; and lubricating oil compositions containing the additive. The lubricating oil additive exhibits a thickening effect higher than those of conventional acrylic lubricating oil additives and can improve the viscosity index of lubricating oil even when added in a small amount. Further, the additive can also improve the low-temperature characteristics, flow characteristics, and shear stability. The lubricating oil compositions enable energy saving and can lengthen the lifetime of lubricating oil and reduce the load on the global environment.
US07718584B2 Dual-function additives for enhancing fluid loss control and stabilizing viscoelastic surfactant fluids
Among many things, in some embodiments, dual-function additives that enhance fluid loss control and the stability of viscoelastic surfactant fluids, and their associated methods of use in subterranean formations, are provided. In one embodiment, the methods comprise: providing a viscoelastic surfactant fluid that comprises an aqueous base fluid, a viscoelastic surfactant, and a dual-function additive that comprises a soap component; and introducing the viscoelastic surfactant fluid into at least a portion of a subterranean formation.
US07718582B2 Method for treating subterranean formation with enhanced viscosity foam
A method for treating a subterranean formation by introducing into a gas or oil well a stable foam well treatment fluid which exhibits high viscosity. The well treatment fluid is prepared by first forming a mixture of crosslinking agent and foaming agent and then introducing the mixture to an aqueous fluid containing a crosslinkable polymer followed by the addition of a gas or gaseous liquid.
US07718578B2 Method of synthesis and testing of combinatorial libraries using microcapsules
The invention describes a method for the synthesis of compounds comprising the steps of: (a) compartmentalizing two or more sets of primary compounds into microcapsules; such that a proportion of the microcapsules contains two or more compounds; and (b) forming secondary compounds in the microcapsules by chemical reactions between primary compounds from different sets. The invention further allows for the identification of compounds which bind to a target component of a biochemical system or modulate the activity of the target, and which is co-compartmentalized into the microcapsules.
US07718573B2 Method for producing oxide superconductor, oxide superconductor and substrate material for supporting precursor of the same
A method for producing an oxide superconductor by partially melting and solidifying the precursor of the oxide superconductor is a method wherein the precursor is placed on a substrate material containing pure metal or a compound which is meltable in the precursor when the precursor is in a partially molten state, and partially melting and solidifying the precursor in said state.
US07718571B2 Method of cultivating fruit vegetables in an increased yield
The invention provides a method wherein a treating solution containing a compound (A) of specific structure having a C10 to C22 hydrocarbon group at a concentration of 1 to 1000 ppm is applied at least once in a period of from germination of a fruit vegetable to planting in a field and applied at least once after planting in the field.
US07718564B2 Partially decomposed catalyst and hydrocarbon oxidation processes using the same
The present invention is related to a hydrocarbon oxidation process. The process comprises bringing one or more hydrocarbons into contact with a source of oxygen in the presence of a radical initiator and a catalyst. The catalyst comprises an organic metal complex located on a catalyst support, and is obtained by partial decomposition of the organic metal complex. For example, the process can be used to produce dimethyl carbonate from dimethoxy methane. The invention is also related to a partially decomposed catalyst that comprises a silica support and an organic metal complex, wherein at least 5% of the organic compound remains in the catalyst. The organic metal complex comprises an organic compound and a metal-based compound wherein the metal is selected from copper, nickel, and combinations thereof. The invention is also related to a process for manufacturing of a catalyst comprising mixing L-arginine, a Cu-based compound, water, and optionally another metal-based compound to form a solution; impregnating the solution onto a silica support to form a catalyst precursor; and partially decomposing the L-arginine to form the catalyst so that at least 5% of L-arginine remains in the catalyst.
US07718561B2 Multi-layer catalyst for producing phthalic anhydride
The present invention relates to a catalyst for preparing phthalic anhydride by gas phase oxidation of o-xylene and/or naphthalene, comprising at least three catalyst zones which have different compositions and, from the gas inlet side toward the gas outlet side, are referred to as first, second and third catalyst zone, the catalyst zones having in each case an active composition comprising TiO2, and the active composition content decreasing from the first catalyst zone disposed toward the gas inlet side to the third catalyst zone disposed toward the gas outlet side, with the proviso that (a) the first catalyst zone has an active composition content between about 7 and 12% by weight, (b) the second catalyst zone has an active composition content in the range between 6 and 11% by weight, the active composition content of the second catalyst zone being less than or equal to the active composition content of the first catalyst zone, and (c) the third catalyst zone has an active composition content in the range between 5 and 10% by weight, the active composition content of the third catalyst zone being less than or equal to the active composition content of the second catalyst zone. Also described is a preferred process for preparing such a catalyst and the preferred use of the titanium dioxide used in accordance with the invention.
US07718559B2 Erosion resistance enhanced quartz used in plasma etch chamber
A method of fabricating doped quartz component is provided herein. In one embodiment, the doped quartz component is a yttrium doped quartz ring configured to support a substrate. In another embodiment, the doped quartz component is a yttrium and aluminum doped cover ring. In yet another embodiment, the doped quartz component is a yttrium, aluminum and nitrogen containing cover ring.
US07718558B2 Composite fabric with high water repellency
A composite fabric for use as a roof lining material made of a multilayer base sheet of a meltblown web of bicomponent fibers sandwiched between two spunbond sheet layers of bicomponent sheath-core fibers and a spunbond top sheet of bicomponent sheath-core fibers wherein the base sheet and top sheet are joined in a manner such that the moisture vapor permeability of the composite fabric is not substantially reduced from the moisture vapor permeability of the base sheet alone.
US07718557B2 Composite upholstery fabric panels with enlarged graphite intumescent particles
Fabric layers and composite articles that incorporate graphite-containing coatings that do not stain are provided. A fabric layer for use as a flame and heat blocking component of an upholstered article includes intumescent graphite particles that are configured to swell and char in the presence of flame so as to form a barrier to flame, hot gases and heat for a predetermined period of time. The graphite particles have a size greater than about 150 microns which prevents the particles from being drawn to a surface of an upholstered article during sewing and quilting operations.
US07718552B2 Nanostructured titania
A method and device of nanostructured titania that is crack free. A method in accordance with the present invention comprises depositing a Ti film on a surface, depositing a masking layer on the Ti film, etching said masking layer to expose a limited region of the Ti film, the limited region being of an area less than a threshold area, oxidizing the exposed limited region of the Th.ucsbi film, and annealing the exposed limited region of the Ti film.
US07718549B2 Method of making a polymer device
A method of making a transistor having first and second electrodes, a semiconductive layer, and a dielectric layer; said semiconductive layer comprising a semiconductive polymer and said dielectric layer comprising an insulating polymer; characterised in that said method comprises the steps of: (i) depositing on the first electrode a layer of a solution containing material for forming the semiconductive layer and material for forming the dielectric layer; and (ii) optionally curing the layer deposited in step (i); wherein, in step (i), the solvent drying time, the temperature of the first electrode and the weight ratio, of (material for forming the dielectric layer): (material for forming the semiconductive layer) in the solution are selected so that the material for forming the semiconductive layer and the material for forming the dielectric layer phase separate by self-organisation to form an interface between the material for forming the semiconductive layer and the material for forming the dielectric layer.
US07718543B2 Two step etching of a bottom anti-reflective coating layer in dual damascene application
Methods for removing a BARC layer from a feature are provided in the present invention. In one embodiment, the method includes providing a substrate having a feature filled with a BARC layer in an etching chamber, supplying a first gas mixture comprising NH3 gas into the chamber to etch a first portion of the BARC layer filling in the feature, and supplying a second gas mixture comprising O2 gas into the etching chamber to etch the remaining portion of the BARC layer disposed in the feature.
US07718540B2 Pitch reduced patterns relative to photolithography features
Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC. The combined pattern made out by the first pattern and the second pattern is transferred to an underlying amorphous silicon layer and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, having features of difference sizes, is then etched into the underlying substrate through the amorphous carbon hard mask layer.
US07718530B2 Method for manufacturing semiconductor device
A method for manufacturing a semiconductor device includes forming a gate conductive layer, a first mask layer, a second mask layer, and a third mask layer over a semiconductor substrate that includes a cell region and a peripheral region. The method also includes forming a second mask pattern and a third mask pattern using a gate mask. The method further includes trimming the second mask pattern in the peripheral region to form a fourth mask pattern having a size smaller than that of the second mask pattern. Still further, the method includes removing the third mask pattern, and patterning the first mask layer and the gate conductive layer using the fourth mask pattern as a mask.
US07718528B2 Photoactive adhesion promoter in a SLAM
A semiconductor process technique to help reduce semiconductor process effects, such as undesired line edge roughness, insufficient lithographical resolution, and limited depth of focus problems associated with the removal of a photoresist layer. More particularly, embodiments of the invention use a photoacid generator (PAG) material in conjunction with a sacrificial light absorbing material (SLAM) to help reduce these and other undesired effects associated with the removal of photoresist in a semiconductor manufacturing process. Furthermore, embodiments of the invention allow a PAG to be applied in a semiconductor manufacturing process in an efficient manner, requiring fewer processing operations than typical prior art techniques.
US07718526B2 Fabrication method of semiconductor integrated circuit device
A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edge of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.
US07718525B2 Metal interconnect forming methods and IC chip including metal interconnect
Methods of forming a metal interconnect and an IC chip including the metal interconnect are disclosed. One embodiment of the method may include providing an integrated circuit (IC) chip up to and including a middle of line (MOL) layer, the MOL layer including a contact positioned within a first dielectric; recessing the first dielectric such that the contact extends beyond an upper surface of the first dielectric; forming a second dielectric over the first dielectric such that the second dielectric surrounds at least a portion of the contact, the second dielectric having a lower dielectric constant than the first dielectric; forming a planarizing layer over the second dielectric; forming an opening through the planarizing layer and into the second dielectric to the contact; and forming a metal in the opening to form the metal interconnect.
US07718522B2 Method and apparatus for plating a semiconductor package
A method of plating a plurality of semiconductor devices includes: applying an electrical power source to an anode terminal and a cathode terminal; placing the plurality of semiconductor devices on a non-conductive platform in a plating solution; moving conductive parts across surfaces of the semiconductor devices to be plated, wherein the conductive parts electrically connect the surfaces of the semiconductor devices to the cathode; and wherein plating particles connected to the anode terminal move to and plate the surfaces of the semiconductor devices.
US07718518B2 Low temperature doped silicon layer formation
A doped silicon layer is formed in a batch process chamber at low temperatures. The silicon precursor for the silicon layer formation is a polysilane, such as trisilane, and the dopant precursor is an n-type dopant, such as phosphine. The silicon precursor can be flowed into the process chamber with the flow of the dopant precursor or separately from the flow of the dopant precursor. Surprisingly, deposition rate is independent of dopant precursor flow, while dopant incorporation linearly increases with the dopant precursor flow.
US07718516B2 Method for epitaxial growth of (110)-oriented SrTiO3 thin films on silicon without template
A process and structure utilizes pulsed laser deposition technique to grow SrTiO3 (STO) films with single (110) out-of-plane orientation upon a surface of all (100), (110) and (111)-oriented silicon (Si) substrates. No designed buffer layer is needed beneath the STO thin films. The in-plane alignments for the epitaxial STO films grown directly on Si (100) are as STO [001]//Si [001] and STO [1 10]/Si [010]. The SrTiO3/Si interface is epitaxially crystallized without any amorphous oxide layer. The formation of a coincident site lattice at the interface between Si and a Sr-silicate and/or STO helps to stabilize STO in the epitaxial orientation. The invention can be applied to epitaxial template and barrier for the integration of many other functional oxide materials on silicon. In particular, the (110)-oriented STO structure is useful for practical applications such as the preparation of ferroelectric-insulator-semiconductor devices as well as providing a broad solution to the generic problem of polarity discontinuities at perovskite heterointerfaces.
US07718512B2 Integrated circuit wafer with inter-die metal interconnect lines traversing scribe-line boundaries
A metal interconnect structure formed over a substrate in an integrated circuit that traverses a scribe-line boundary between a first die and a second die includes at least one metal interconnect line that traverses the scribe-line boundary. A switch is coupled between the at least one metal interconnect line and the substrate, the switch having a control element coupled to a scribe-cut control line. The control line turns the switch on if the two dice are separated into individual dice and turns the switch off if the two dice are to remain physically connected so that the interconnect line may be used to make connections between circuits on the two dice.
US07718511B2 Processing method for wafer
A processing method for a wafer includes: preparing a wafer which has a device region having plural devices formed on a surface of the wafer; and a peripheral reinforcing portion which is integrally formed around the device region and has a projection projecting outwardly on a rear surface of the wafer. The processing method further includes: holding the wafer on a holding surface of a rotatable holding table such that the rear surface of the wafer is exposed and the surface of the wafer closely contacts the holding table. The processing method further includes: thinning the peripheral reinforcing portion by cutting and removing at least the projection of the peripheral reinforcing portion of the wafer by using a cutting tool having a rotational shaft parallel to the holding surface, while rotating the wafer by rotating the holding table after the holding of the wafer. The peripheral reinforcing portion is thinned so as to have a thickness equal to or thinner than that of the device region by the thinning.
US07718510B2 Laser processing method and semiconductor chip
A laser processing method is provided, which, even when a substrate formed with a laminate part including a plurality of functional devices is thick, can cut the substrate and laminate part with a high precision.This laser processing method irradiates a substrate 4 with laser light L while using a rear face 21 as a laser light entrance surface and locating a light-converging point P within the substrate 4, so as to form modified regions 71, 72, 73 within the substrate 4. Here, the quality modified region 71 is formed at a position where the distance between the front face 3 of the substrate 4 and the end part of the quality modified region 71 on the front face side is 5 μm to 15 μm. When the quality modified region 71 is formed at such a position, a laminate part 16 (constituted by interlayer insulating films 17a, 17b here) formed on the front face 3 of the substrate 4 is also cut along a line to cut with a high precision together with the substrate 4.
US07718509B2 Method for producing bonded wafer
A bonded wafer is produced by comprising a step of implanting oxygen ions from a surface of a wafer for active layer to form an oxygen ion implanted layer at a given position inside the wafer for active layer; a step of bonding the wafer of active layer to a wafer for support substrate directly or through an insulating film; a step of subjecting the resulting bonded wafer to a heat treatment for increasing a bonding strength; a step of removing a portion of the wafer for active layer in the bonded wafer to a given position not exposing the oxygen ion implanted layer by a given method; a step of exposing the entire surface of the oxygen ion implanted layer; and a step of removing the exposed oxygen ion implanted layer to obtain an active layer of a given thickness, wherein the step of exposing the entire surface of the oxygen ion implanted layer is carried out by a dry etching under given conditions.
US07718508B2 Semiconductor bonding and layer transfer method
The present invention provides a method of coupling substrates together. The method includes providing first and second substrates and then coupling the first and second substrates together. One of the first and second substrates includes devices with an interconnect region positioned thereon and the other substrate carries a device structure.
US07718504B2 Semiconductor device having align key and method of fabricating the same
Disclosed is a semiconductor device having an align key and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having a cell area and an align key area. An isolation layer that defines a cell active area is disposed in the cell area of the semiconductor substrate. A cell charge storage layer pattern is disposed across the cell active area. An align charge storage layer pattern is disposed in the align key area of the semiconductor substrate. An align trench self-aligned with the align charge storage layer pattern is formed in the align key area of the semiconductor substrate.
US07718503B2 SOI device and method for its fabrication
A silicon on insulator (SOI) device and methods for fabricating such a device are provided. The device includes an MOS capacitor coupled between voltage busses and formed in a monocrystalline semiconductor layer overlying an insulator layer and a semiconductor substrate. The device includes at least one electrical discharge path for discharging potentially harmful charge build up on the MOS capacitor. The MOS capacitor has a conductive electrode material forming a first plate of the MOS capacitor and an impurity doped region in the monocrystalline silicon layer beneath the conductive electrode material forming a second plate. A first voltage bus is coupled to the first plate of the capacitor and to an electrical discharge path through a diode formed in the semiconductor substrate and a second voltage bus is coupled to the second plate of the capacitor.
US07718500B2 Formation of raised source/drain structures in NFET with embedded SiGe in PFET
A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source/drain stressor in the recesses. We form a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor. The epitaxial Si layer over PFET embedded source/drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source/drain stressor. We perform a NFET S/D implant by implanting N-type ions into NFET region adjacent to the NFET gate structure and into the NFET S/D stressor Si layer to form the raised NFET source/drains.
US07718497B2 Method for manufacturing semiconductor device
A semiconductor device manufacturing method includes: forming a sidewall spacer on a sidewall surface of a gate electrode; forming a pair of second conductive type source and drain regions in an active region; covering top surfaces of a semiconductor layer, a device isolation region, the sidewall spacer and the gate electrode with a metal film; reducing resistance of the source and drain regions and the gate electrode partially by making the metal film react with the semiconductor layer and the gate electrode; and removing an unreacted portion of the metal film and the sidewall spacer simultaneously by using an etchant which readily etches the unreacted portion of the metal film and the sidewall spacer while hardly etching the device isolation region, resistance-reduced portions of the gate electrode and resistance-reduced portions of the source and drain regions.
US07718496B2 Techniques for enabling multiple Vt devices using high-K metal gate stacks
Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.
US07718495B2 Methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors
The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one implementation, conductive metal silicide is formed on some areas of a substrate and not on others. In one implementation, conductive metal silicide is formed on a transistor source/drain region and which is spaced from an anisotropically etched sidewall spacer proximate a gate of the transistor.
US07718494B2 Method for forming high-drain-voltage tolerance MOSFET transistor in a CMOS process flow with double well dose approach
A method for forming a high-voltage drain metal-oxide-semiconductor (HVD-MOS) device includes providing a semiconductor substrate; forming a well region of a first conductivity type; and forming an embedded well region in the semiconductor substrate and only on a drain side of the HVD-MOS device, wherein the embedded region is of a second conductivity type opposite the first conductivity type. The step of forming the embedded well region includes simultaneously doping the embedded well region and a well region of a core regular MOS device, and simultaneously doping the embedded well region and a well region of an I/O regular MOS device, wherein the core and I/O regular MOS devices are of the first conductivity type. The method further includes forming a gate stack extending from over the embedded well region to over the well region.
US07718492B2 Non-volatile memory cell circuit with programming through band-to-band tunneling and impact ionization gate current
Electronic circuitry is described having a first transistor having a first gate dielectric located between an electrically floating gate and a semiconductor substrate. The first injection current flows through the first gate dielectric to establish a first amount of electrical charge on the gate electrode. The electronic circuitry also includes a second transistor having a second gate dielectric located between the gate electrode and the semiconductor substrate. A band-to-band tunneling current flows between valence and conduction bands of the second transistor to create a second injection current that flows through the second gate dielectric to establish the first amount of electrical charge on the gate electrode. Non-volatile memory cell circuits having the above described circuitry are also described.
US07718488B2 Process of fabricating flash memory with enhanced program and erase coupling
Self-aligned split-gate flash memory cell array and process of fabrication in which erase and select gates are positioned on opposite sides of stacked floating and control gates, with source regions in the substrate beneath the erase gates, bit line diffusions which are partially overlapped by select gates at the ends of the rows of the cells. The floating and control gates are self-aligned with each other, and the erase and select gates are split from but self-aligned with the stacked gates. With the floating gates surrounded by the other gates and the source regions, high voltage coupling for both programming and erase operations is significantly enhanced. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.
US07718485B2 Interlayer dielectric under stress for an integrated circuit
An integrated circuit that has logic and a static random access memory (SRAM) array has improved performance by treating the interlayer dielectric (ILD) differently for the SRAM array than for the logic. The N channel logic and SRAM transistors have ILDs with non-compressive stress, the P channel logic transistor ILD has compressive stress, and the P channel SRAM transistor at least has less compressive stress than the P channel logic transistor, i.e., the P channel SRAM transistors may be compressive but less so than the P channel logic transistors, may be relaxed, or may be tensile. It is beneficial for the integrated circuit for the P channel SRAM transistors to have a lower mobility than the P channel logic transistors. The P channel SRAM transistors having lower mobility results in better write performance; either better write time or write margin at lower power supply voltage.
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