Semiconductor capacitor structure and memory cell, and method of making专利检索-激子扩散电子零件及设备专利检索查询-专利查询网

Semiconductor capacitor structure and memory cell, and method of making

阅读：599发布：2023-06-20

专利汇可以提供Semiconductor capacitor structure and memory cell, and method of making专利检索，专利查询，专利分析的服务。并且In one example, a random access memory cell includes an MOS gating transistor to activate the cell for reading, writing, or refreshing data stored on a cell capacitor structure. A typical cell transistor includes P1 (input/output) and P2 (cell storage) diffusions in an N-type substrate, P2 serving as one terminal or plate of the cell capacitor structure. According to this application, a preferred cell capacitor is formed by diffusing an N+ region over a major portion of the P2 region and extending beyond the P2 region in electrical contact with the grounded N substrate. The primary cell capacitor is defined between the P2 diffusion, a depletion region induced at the P2-N+ junction when P2 is charged, and the grounded N substrate. The N+ diffusion also reduces an unwanted parasitic capacitance between the P2 region and a transistor gate conductor for the cell, reduces leakage currents and permits greater packing density of cells. More generally, the application relates to an improved semiconductor capacitor storage structure and method, including a substrate of one conductivity type, a first diffusion of the opposite type on the substrate and constituting one capacitor terminal, and a second diffusion of the substrate conductivity type covering most of the first diffusion and in electrical contact with the substrate, the second diffusion and substrate forming the second capacitor terminal. The dielectric of the capacitor storage structure is formed by a depletion region between the first diffusion and both the substrate and second diffusion.，下面是Semiconductor capacitor structure and memory cell, and method of making专利的具体信息内容。

权利要求

1. An improved cell capacitor structure for an MOS integrated circuit memory chip of the Type having a cell-gating field-effect transistor including a grounded substrate of type I semiconductor material and first and second controlled terminals consisting of first and second diffusions of type II semiconductor material formed in the upper surface of the substrate, the first controlled terminal being selectively connectable (1) to a source of charging potential for the cell to store charge on the second controlled terminal when the transistor is turned ON, or (2) to ground to discharge any stored charge on the second controlled terminal when the transistor is turned ON, the second diffusion being an isolated island of substantial area unconnected to external circuits so as to form a first electrode of the cell capacitor, the grounded substrate forming the second electrode of the cell capacitor, and the induced depletion region formed at the second diffusion to substrate junction when the second diffusion is charged constituting the capacitor dielectric, the improved cell capacitor structure being characterized in that: a third diffusion, of type I+ semiconductor material, is formed in the upper surface of the chip overlying the second diffusion area except for the second controlled terminal area of the transistor, the third diffusion being covered by an insulating layer of oxide and being isolated from external circuits, the third diffusion extending beyond the periphery of the second diffusion into electrical contact with the grounded substrate, the interconnected substrate and third diffusion together forming the second electrode on the cell capacitor and the induced depletion region formed at the junction between the second and third diffusions when the second diffusion is charged constituting the major portion of the cell capacitance.

2. A cell capacitor structure as recited in claim 1, wherein the substrate comprises an N-type silicon substrate, the first and second diffusions are P diffusions, the third diffusion is an N+ diffusion, and the insulating layer comprises a thick layer of SiO2.

3. A cell capacitor structure as recited in claim 1, wherein a gate conductor for the MOS field-effect transistor overlies a portion of the second diffusion, being separated therefrom by the third diffusion and by the insulating layer formed on the third diffusion, the third diffusion serving to reduce the intrinsic parasitic capacitance between the gate conductor and the second diffusion.

4. An MOS cell capacitor structure as recited in claim 1, wherein the cell capacitance consists entirely of the P-N junction capacitance recited in claim 1, the third diffusion overlapping the entire perimeter of the second diffusion area except for the second controlled terminal area of the transistor.

5. An improved random access memory comprising an array of MOS memory cells as recited in claim 4, arranged in an X-Y matrix of columns (X) and rows (Y) as viewed from the top of the chip and further characterized in that: there are a plurality of parallel first diffusions (P1), each consisting of an elongated diffusion of P-type silicon formed in the upper surface of a common substrate of N-type silicon, each P1 diffusion serving as an I/O column conductor (X) for a plurality of individual cells arranged in parallel columns on both sides of each P1 diffusion, to charge, discharge and refresh the associated cell capacitances at periodic intervals; there are a plurality of second diffusions (P2), each consisting of an isolated rectangular island of P+ type silicon formed in the upper surface of the substrate, the P2 islands being arranged in parallel rows spaced from each other and spaced from a corresponding P1 diffusion so as to define a cell gating transistor between one edge of each P2 island and the corresponding P1 diffusion; and the third diffusion (50) comprises an elongated slab of N+ type silicon extendiNg in the area between each pair of P1 diffusions and spaced therefrom, each N+ diffusion covering all P2 islands in the space between the P1 diffusions except for a rectangular cut out region (52) defining the second controlled terminal region of each cell transistor, the third diffusion burying all of each P2 island beneath the surface oxide layer except for the controlled terminal area of each cell transistor, so as to minimize leakage current from the P2 regions and so as to permit closer spacing between P2 islands.

6. An improved random access memory as recited in claim 5, further characterized in that: a plurality of row conductors (Y), consisting of parallel aluminum strips are deposited on the oxide layer and run across the chip in the Y direction, each Y conductor serving as a gating input to a plurality of transistors in a row and being separated from the silicon by thick oxide except for the gate region of each transistor where it is separated by thin oxide, the third diffusion serving to reduce the intrinsic parasitic capacitance (C2) between each gate conductor and the underlying P2 diffusions.

7. In a process of fabricating an MOS integrated circuit memory chip, of the type wherein first and second diffusions of type II semiconductor material are formed in portions of the upper surface of a substrate of type I semiconductor material to define first and second controlled terminals of a field-effect transistor, a thin gate oxide region is formed in the upper surface of the substrate between the first and second controlled terminal regions, thick oxide insulating regions are ultimately formed over the other areas of the upper surface of the chips, and a gate conductor is deposited over the thin oxide gate region and extending across the chip over portions of the thick oxide and overlying portions of the second diffusion area, the second diffusion being an isolated island of substantial area unconnected to external circuits so as to define a cell capacitance to the grounded substrate when charged from the first diffusion through the transistor when the transistor is turned ON, a method of reducing parasitic capacitance between the access conductor and the second diffusion, which comprises: prior to formation of the oxide layers, forming a third diffusion, of type I+ semiconductor material, in the upper surface of the chip overlying the second diffusion area except for the second controlled terminal area of the transistor, the third diffusion extending beyond the periphery of the second diffusion into electrical contact with the grounded substrate, the third diffusion forming a ground shield for the second diffusion to reduce the parasitic capacitance between the access conductor and the second diffusion.

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Semiconductor capacitor structure and memory cell, and method of making

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