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The present invention relates to computer systems, and more particularly to a technique for assuring a correlation of ordered changes and the accomplishment of those changes in computer components.

A computer system is made up of a plurality of component units, many of which are in the form of separate printed circuit boards. From time to time, after the system is in the field, changes or improvements are originated at the design level. Instructions for effecting such changes are sent to field service personnel who then follow the instructions and make the necessary changes in the apparatus. It also often happens that after a system has been in the field in service for some time, a problem develops requiring correction. When the problem has been analyzed at the .design level, certain revisions are made to the circuitry which overcome the particular problem. In recognition that the particular problem would be common to all of the systems in the field of that particular type, field change orders are sent to the field service personnel at each location having such a computer. Following such instructions, it is assumed that the field service personnel will have effected the necessary changes. Very often, the complement of the change in the circuit structure of the computer system is a corresponding change in the applied software. The software changes are then sent to the users for implementation into their system. The part of the instruction for the field service personnel is that the particular circuit board on which changes have been made is to be annotated in handwriting indicating that the changes have been completed. It happens on occasions that the field service personnel, in the press of an abundance of work, will make the hand written annotations on the board without actually making the changes. Then, later, when a problem develops in the system, much time and effort is wasted in trying to resolve the problem, sometime occasioned by the fact that the program material now supplied to the system does not match the hardware because the change had not been made. On other occasions, time and effort are wasted in looking for a solution to a presumed different problem, based on the assumption that the change had been made to the particular system when in fact the change had not been made.

Accordingly, the present invention provides a computer system having a computer and a plurality of components making up said system, annotation means for annotating technical changes in any of said components, characterized in that the annotation means comprise:

• a coding section included in each component for establishing a code word,.identifying the revision status of the component, which is changeable in accordance with a predetermined instruction to correspond to revisions to said component, said code word being changeable with a difficulty commensurate with the corresponding revision to said component; and
• addressing means addressable by the computer to enable the computer to interrogate the component for its revision status.

Two embodiments of the present invention will now be described with reference to the accompanying drawings, in which:

• Figure 1 shows a computer system;
• Figure 2 is a block diagram of a portion of the system shown in Figure 1 in greater detail;
• Figure 3 is a block diagram showing circuit elements of one form of the present invention; and
• Figure 4 is a block diagram of circuit elements of a different form of the present invention.

• Figure 1 shows a computer system including a chassis 2, which may be one of several such chassis, in which a number of printed circuit boards 4, 6, 8,... are inserted in appropriate slots. Board 4 may be, for example, a buffer board to provide a buffering interface between this computer system and other systems in a multicomputer combination or a buffer from one chassis to another. Board 6 may be the computer, or central processor, board. Board 8 may comprise memory boards. The chassis 2 also includes interface boards 10 for interfacing with peripheral equipment and process I/O controller board 12, and a power supply unit on one or more boards 14. The several boards are interconnected by a bus made up of one or more ribbon type cables 16 connected to the boards by suitable edge connectors 18, or by a printed circuit back plane.
• Figure 2 shows, in greater detail, a portion of the structure shown in Figure 1. Board 6, the central processor unit, includes a data processor 20 connected by an on-board bus 22 to a bus interface unit 24. The bus interface unit 24 provides an interface between the date processor and the computer bus 16. The on-board bus 22 also is connected to other board components 26. The board 6 also includes two coded identification sections each also connected to the data processor 20 by way of the on-board bus 22. These two sections are a board type code section 28, and a revision status section 30. The board type section 28 includes a unique code to identify the type of board on which this section appears. That section may be addressed by the data processor 20 to ascertain the board type. This code is a fixed code pattern which may be a permanent part of the artwork on the board itself. The revision status code section 30 is a variable code to identify the revision status of the components on the board itself. This code is changeable by a field service engineer at the same time that technical changes are made in the component structure of the board itself, in order to annotate those changes.

The memory board 8 also includes a bus interface unit 32 to interface the computer bus 16 and the other board components 34 on the board 8 by way of the on-board bus 36. Also on the board 8 is a board type code section 38 and a revision status code section 40 both of which are in communication with the on-board bus 36. Here, too, the board type section features a unique fixed code which will identify the board type. Again, the revision status code is a variable code which may be changed by the field service engineer at the same time that technical changes are being made to the other components on the board. Since the board type section 38 and the revision status section 40 are connected to the on-board bus 36 and thereby through the bus interface 32 to the bus 16, the board 8 may be addressed by the computer on the board 6 to enable the board type section 38 and the revision status section 40. This enables the computer board 6 to interrogate the board 8 to identify itself electronically as to board type and to identify electronically its current revision status. The I/O controller board 12 also includes a bus interface unit 42 which interfaces the computer bus 16 with the operative board component 44 by way of the on-board bus 46. Here again, the board includes a board type section 48 and a board revision status section 50. The board type section 48 and the revision status section 50 are, again, connected to the on-board bus 46 and hence through the bus interface unit 42 to the computer bus 16. Thus, the data processor . on the board 6 may address the board 12 and request identification of the board and its present revision status.

Similarly, all of the other boards in the computer system will have a section reserved for the board type iden- tificatioi code and the revision status code. Each of these sections will be addressable by the data processor whereby each board may then identify itself and also its current revision status, these being accomplished electronically.

Figure 3 is a more detailed diagram of certain parts of the printed circuit board 8 of Figure 2. The board type code unit 38 includes a first component 52 which comprises the code unit, per se, and a second component 54 which comprises a plurality of addressable gates. The outputs of the addressable gates 54 are connected to the on-board bus 36 for connection to the bus interface unit 32. Similarly the revision status code section 40 includes a first component which comprises the variable status code unit 56 and a second component 58 which, again, comprises a plurality of addressable gates. The addressable gates are also connected by the on-board bus 36 to the bus interface unit 32 for communication with the central processor. The addressable gate units 54 and 58 are addressable from the central processor to enable the transmission of the coded signals to the central processor.

A somewhat different embodiment is.shown in Figure 4. Whereas in Figure 3.the output of the board type code and the revision status code are transmitted to the bus interface unit 32 via an on-board bus 36, and thence to the central processor in parallel data form, in Figure 4 there are means provided for transmitting that data to the bus interface unit 42 via an on-board multiplexor 46, and thence to the central processor in serial data form. In Figure 4 the board type code unit is connected directly to a multiplexor 60. Similarly, the revision status code unit 40 is connected directly to the multiplexor 60. The multiplexor 60 is connected to the bus interface unit 52 for communication with the central processor. In the structure shown in Figure 4, the board type code unit and the revision status code unit are addressed from the central processor by enabling and select signals applied from the bus interface unit through a select unit 62 to enable the multiplexor 60 and select among its inputs. The select unit 62 may be in a form of a conventional decoder.

In the Figure 3 arrangement, the board type 'code unit 52 may conveniently be an 8-bit unit, in which 8 output lines are individually connected to either earth or a positive voltage supply to generate an 8-bit board type code. The connections will be part of the permanently wired artwork of the board. The 8 output lines will be connected to a set of 8 gates 54 having a common addressing (enabling) line. When the particular board has been addressed and the gates 54 enabled by the central processor, the code signlas representing the board identification are transmitted by way of the bus interface unit 32 and the bus 16 to the data processor 20. There the signals are recognized as properly or improperly identifying the selected board.

The revision status code unit 56 may also conveniently be an 8-bit unit, the structure of which is slightly more complicated than that of the unit 52. For unit 56, each of the 8 lines is connected to a positive voltage supply through a respective pull-up resistor, and to a respective one of a set of 8 terminals to which jumpers to earth can be soldered. Thus by soldering jumpers into place, a desired revision status code can be encoded into the unit 56. When a technical change is made on the board, the change instructions include an instruction to add a jumper or to remove a jumper from one.of the jumper terminals. While it is desired to keep the annotation code changes as simple as possible, it is also desired to arrange the sequence of the code in such a manner as to render it not readily decipherable by a field service engineer. To this end, it is preferred that the order of progression of the change order numbers be in accordance with a modified gray scale code. The purpose of this arrangement is in an effort to avoid the probability that the field service engineer will merely make the annotation change without actually making the technical change on the board. It is recognized that the electrical annotation could be accomplished with mini- switches or the like. This, however, would make the annotation much easier to implement than the technical change t itself and would tend to defeat the purpose of maintaining the technical changes current with the annotation. : The solder connected jumpers are of the same order of magnitude of difficulty to change as is the technical change on the board itself. Accordingly, while the field service engin-. eer has his soldering iron out and operating he will then make both changes at the same time.

Unit 58 is substantially identical to unit 54. Again these gates are enabled by a signal derived from the central processor and applied to the gates on a common lead connected to the bus interface 32. Thus when the board has been addressed and the enable signal transmitted from the central processor to enable the gates 58, the revision status code for that particular board will be transmitted through the gates 58 and the bus interface 32 to the central processor. There, the proper revision status will be acknowledged or the error recognized, since a revision status code will have been included within the software applicable to the operation of that particular computer.