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序号	专利名	申请号	申请日	公开（公告）号	公开（公告）日	发明人
1	具有由沟槽隔离限定的JFET宽度的半导体器件	CN201380042822.X	2013-08-29	CN104584218A	2015-04-29	B·胡; P·郝; S·彭迪哈卡
本发明涉及一种具有结型场效应晶体管(JFET)(100)的半导体器件，其包括具有包括顶侧表面(106a)的第一类型半导体表面(106)的衬底(105)，以及在该半导体表面形成的第二类型顶部栅极(110)。第一类型漏极(120)和第一类型源极(115)在顶部栅极的相对侧上形成。第一深沟槽隔离区(125)具有围绕顶部栅极、漏极和源极的第一内沟槽壁(125a)和第一外沟槽壁(125b)，并且从顶侧表面垂直地延伸到深沟槽深度(139)。在半导体表面上形成的第二类型下沉区(135)在第一外沟槽壁之外横向地延伸。下沉区从顶侧表面垂直地延伸到第二类型深部，其既低于深沟槽深度也在横向上处于第一内沟槽壁之内，以提供底部栅极。
2	具有由沟槽隔离限定的JFET宽度的半导体器件	CN201380042822.X	2013-08-29	CN104584218B	2017-09-05	B·胡; P·郝; S·彭迪哈卡
本发明涉及一种具有结型场效应晶体管(JFET)(100)的半导体器件，其包括具有包括顶侧表面(106a)的第一类型半导体表面(106)的衬底(105)，以及在该半导体表面形成的第二类型顶部栅极(110)。第一类型漏极(120)和第一类型源极(115)在顶部栅极的相对侧上形成。第一深沟槽隔离区(125)具有围绕顶部栅极、漏极和源极的第一内沟槽壁(125a)和第一外沟槽壁(125b)，并且从顶侧表面垂直地延伸到深沟槽深度(139)。在半导体表面上形成的第二类型下沉区(135)在第一外沟槽壁之外横向地延伸。下沉区从顶侧表面垂直地延伸到第二类型深部，其既低于深沟槽深度也在横向上处于第一内沟槽壁之内，以提供底部栅极。
3	位置测量仪和用于其运行的方法	CN201310433843.6	2013-09-23	CN103673943A	2014-03-26	J.奥伯豪泽; B.施米德; J.J.罗森勒纳-埃姆德; W.施瓦格; T.施维策尔; H.迈耶; M.O.蒂曼
本发明涉及一种位置测量仪和用于其运行的方法，该位置测量仪带有编码载体，该位置测量仪带有：至少一个第一分度轨道和第二分度轨道，其中，第二分度轨道是增量分度轨道，用于通过在测量方向上探测第一分度轨道和第二分度轨道产生第一位置信号的第一探测器组件，用于通过在测量方向上探测第二分度轨道产生第二位置信号的第二探测器组件，用于将第一位置信号处理成第一绝对位置值的第一位置处理单元以及用于将第二位置信号处理成第二绝对位置值的第二位置处理单元，其中，第二位置处理单元可利用绝对辅助位置值初始化，绝对辅助位置值由第一位置处理单元输送给第二位置处理单元。
4	Method to optimize random IOS of a storage device for multiple versions of backups using incremental metadata	US14788598	2015-06-30	US10055420B1	2018-08-21	Prashant Pogde; Yamini Allu; Mahesh Kamat
Methods, systems, and apparatus for optimizing a cache memory device of a storage system are described. In one embodiment, a first base segment tree representing a first full backup including data and metadata describing the data is cached in a cache memory device. Subsequently, a plurality of incremental segment trees representing incremental backups to the first full backup are cached in the cache memory device. Each of incremental segment trees corresponding to the changes to the first full backup, without modifying the first base segment tree in response to the changes. At least two of the incremental segment trees are merged into an updated incremental segment tree to reduce a storage space of the cache memory device to store the incremental segment trees. The updated incremental segment tree comprises data and metadata represented by two or more incremental segment trees.
5	Batch processed data structures in a log repository referencing a template repository and an attribute repository	US14482400	2014-09-10	US10049171B2	2018-08-14	Sreenivas Gukal; Kiran Jyotsna Achyutuni
A method by a computer includes, for each of a plurality of log records received as part of a log stream from a host machine node, identifying a template identifier within a template repository for a template string matching an invariant string of the log record, and identifying an attribute identifier in an attribute repository for an attribute string matching a variant string of the log record. The log records are partitioned into batches. Each of the batches are defined by a data structure that includes the template identifier and the attribute identifier for each of the log records within the batch. The data structures for each of the batches are stored into a log repository.
6	Tamper resistant electronic system utilizing acceptable tamper threshold count	US13354657	2012-01-20	US09299451B2	2016-03-29	Travis R. Hebig; Joseph Kuczynski; Robert E. Meyer, III; Steven R. Nickel
A tamper resistant electronic device includes multiple eFuses that are individually blown in each instance the electronic device is tampered with. For example an eFuse is blown when the electronic device is subjected to a temperature that causes solder reflow. Since it is anticipated that the electronic device may be tampered with in an acceptable way and/or an acceptable number of instances, functionality of the electronic device is altered or disabled only after a threshold number of eFuses are blown. In certain implementations, the threshold number is the number of anticipated acceptable tamper events. Upon a tamper event an individual eFuse is blown. If the total number of blown eFuses is less than the threshold, a next eFuse is enabled so that it may be blown upon a next tamper event.
7	Redirecting guest-generated events to an event aggregator in a networked virtualization environment	US13667094	2012-11-02	US09135051B2	2015-09-15	Gilad Chaplik; Haim Ateya
A method for integrating responses to asynchronous events is provided. A hypervisor of a host receives a request from a network manager to re-direct asynchronous events from a guest to an address of an event aggregation manager distinct from an address of the network manager. The hypervisor receives an asynchronous event having a destination address of the network manager from the guest. The hypervisor maps the destination address of the network manager to the address of the event aggregation manager. The hypervisor transmits the asynchronous event to the event aggregation manager.
8	TAMPER RESISTANT ELECTRONIC SYSTEM UTILIZING ACCEPTABLE TAMPER THRESHOLD COUNT	US13354657	2012-01-20	US20130187706A1	2013-07-25	Travis R. Hebig; Joseph Kuczynski; Robert E. Meyer, III; Steven R. Nickel
A tamper resistant electronic device includes multiple eFuses that are individually blown in each instance the electronic device is tampered with. For example an eFuse is blown when the electronic device is subjected to a temperature that causes solder reflow. Since it is anticipated that the electronic device may be tampered with in an acceptable way and/or an acceptable number of instances, functionality of the electronic device is altered or disabled only after a threshold number of eFuses are blown. In certain implementations, the threshold number is the number of anticipated acceptable tamper events. Upon a tamper event an individual eFuse is blown. If the total number of blown eFuses is less than the threshold, a next eFuse is enabled so that it may be blown upon a next tamper event.
9	METHOD AND APPARATUS OF SECURELY PROCESSING DATA FOR FILE BACKUP, DE-DUPLICATION, AND RESTORATION	US13074231	2011-03-29	US20120254125A1	2012-10-04	Charles Bosson
Disclosed are an apparatus and method of restoring at least one data file. The method may include retrieving the at least one data file to be restored from a data storage location, determining that the at least one data file is a link file, and regenerating a previously exchanged shared secret. The method may also include decrypting a key from the link file using the shared secret, and retrieving data from a data repository location to be restored.
10	Integrated circuit and method of operation	US292481	1994-08-18	US5642487A	1997-06-24	David Walter Flynn; Philip Brian Endecott
An integrated circuit includes a plurality of data handling devices and a data buffer for enabling transfer of data between the internal data handling devices and one or more external data handling devices external to the integrated circuit. A controller responds to an original clock signal for supplying a clock signal to control data transfer between the data handling devices. The controller includes a delay circuit operable to delay the original clock signal to generate a delayed clock signal, and includes a selector for inhibiting operation of the delay circuit and for selecting the original clock signal for controlling data transfer from an internal data handling device to another data handling device. The selector also enables operation of the delay circuit and selects the delayed clock signal for controlling data transfer from an external data handling device to an internal data handling device.
11	エンコーダ及びこのエンコーダを稼働させるための方法	JP2013188221	2013-09-11	JP6373564B2	2018-08-15	ヨーハン・オーバーハウザー; ベルンハルト・シュミート; ヤニク・イェンス・ローゼンレーナー−エムデ; ヴェルナー・シュヴァイガー; トーマス・シュヴァイツァー; フーベルト・マイヤー; マルク・オーリヴァー・ティーマン

12	Integrated circuit and method for controlling operation	JP23397694	1994-08-23	JPH07219895A	1995-08-18	DEBITSUDO UORUTAA FURIN; FUIRITSUPU BURAIAN ENDEKOTSUTO
PURPOSE: To control data transfer from an external data processor to a certain internal data processor by making a delay circuit operable and selecting a delay clock signal. CONSTITUTION: When it is detected that a clock selector 140 has not at present received any data from the external data processor, according to a bus clock signal 130, an initial clock signal is supplied to the internal data processor. When it is detected that the clock selector 140 is accessed from the external data processor, the clock selector 140 controls a switch 150, moves it to the inverse position and supplies an initial clock signal 80 to an output buffer 180. The output buffer 180 is operated as a 1st delay device, and this delays the clock signal 80 precisely for delay time equal to the delay added by outside the data buffer. The delayed signal 80 is supplied to the output terminal of an integrated circuit, namely, to a pad 190.
13	Encoder and method for operating encoder	JP2013188221	2013-09-11	JP2014062903A	2014-04-10	OBERHAUSER JOHANN; SCHMIED BERNHARD; ROSENLEHNER-EMDE JANNIK JENS; WERNER SCHWAIGER; THOMAS SCHWEIZER; MAYER HUBERT; TIEMANN MARC OLIVER
PROBLEM TO BE SOLVED: To provide a simply constituted reliable encoder and a method for operating the encoder.SOLUTION: First detector arrangements 2.221, 2.222 generate first position signals Z1_1, Z16_1 by scanning a first scale track 1.21 and a second scale track 1.22 in a measurement direction. A second detector arrangement 2.232 generates a second position signal Z16_2 by scanning the second scale track 1.22 in the measurement direction. A first position processor 3.1 converts the first position signals Z1_1, Z16_1 into a first absolute position value POS1, and a second position processor 3.2 processes a second position signal Z16_2 into a second absolute position value POS2. The second position processor 3.2 can be initialized by an auxiliary absolute position value HPOS supplied from the first position processor 3.1 to the second position processor 3.2.
14	Integrated circuit and method for controlling the operation thereof	JP23397694	1994-08-23	JP3577347B2	2004-10-13	ウォルターフリンデビッド; ブライアンエンデコットフィリップ
An integrated circuit includes a plurality of data handling devices and a data buffer for enabling transfer of data between the internal data handling devices and one or more external data handling devices external to the integrated circuit. A controller responds to an original clock signal for supplying a clock signal to control data transfer between the data handling devices. The controller includes a delay circuit operable to delay the original clock signal to generate a delayed clock signal, and includes a selector for inhibiting operation of the delay circuit and for selecting the original clock signal for controlling data transfer from an internal data handling device to another data handling device. The selector also enables operation of the delay circuit and selects the delayed clock signal for controlling data transfer from an external data handling device to an internal data handling device.
15	BATCH PROCESSED DATA STRUCTURES IN A LOG REPOSITORY REFERENCING A TEMPLATE REPOSITORY AND AN ATTRIBUTE REPOSITORY	US14482400	2014-09-10	US20160070739A1	2016-03-10	Sreenivas Gukal; Kiran Jyotsna Achyutuni
A method by a computer includes, for each of a plurality of log records received as part of a log stream from a host machine node, identifying a template identifier within a template repository for a template string matching an invariant string of the log record, and identifying an attribute identifier in an attribute repository for an attribute string matching a variant string of the log record. The log records are partitioned into batches. Each of the batches are defined by a data structure that includes the template identifier and the attribute identifier for each of the log records within the batch. The data structures for each of the batches are stored into a log repository.
16	JFET having width defined by trench isolation	US13597439	2012-08-29	US09076760B2	2015-07-07	Binghua Hu; Pinghai Hao; Sameer Pendharkar
A junction field-effect transistor (JFET) includes a substrate having a first-type semiconductor surface including a topside surface, and a top gate of a second-type formed in the semiconductor surface. A first-type drain and a first-type source are formed on opposing sides of the top gate. A first deep trench isolation region has an inner first trench wall and an outer first trench wall surrounding the top gate, the drain and the source, and extends vertically to a deep trench depth from the topside surface. A second-type sinker formed in semiconductor surface extends laterally outside the outer first trench wall. The sinker extends vertically from the topside surface to a second-type deep portion which is both below the deep trench depth and laterally inside the inner first trench wall to provide a bottom gate.
17	INFORMATION PROCESSING APPARATUS AND METHOD FOR SHUTTING DOWN VIRTUAL MACHINES	US14461545	2014-08-18	US20140359356A1	2014-12-04	Shigeto AOKI
A storage unit stores information indicating the priority level of each of a plurality of virtual machines. When causing the plurality of virtual machines to perform their shutdown processes in parallel, a control unit selects a first virtual machine from the plurality of virtual machines with reference to the storage unit. In addition, the control unit selects a second virtual machine from virtual machines with lower priority level than the first virtual machine with reference to the storage unit. The control unit then reduces the amount of resources allocated to the selected second virtual machine and increases the amount of resources allocated to the first virtual machine using resources equivalent to the reduced amount of resources.
18	SNMP/WMI INTEGRATION INTO A VIRTUALIZATION ENVIRONMENT FOR HANDLING GUEST-ORIENTED EVENTS WITH VIRTUALIZATION-ENVIRONMENT-RELATED ACTIONS	US13667094	2012-11-02	US20140130039A1	2014-05-08	Gilad Chaplik; Haim Ateya
A method for integrating responses to asynchronous events is provided. A hypervisor of a host receives a request from a network manager to re-direct asynchronous events from a guest to an address of an event aggregation manager distinct from an address of the network manager. The hypervisor receives an asynchronous event having a destination address of the network manager from the guest. The hypervisor maps the destination address of the network manager to the address of the event aggregation manager. The hypervisor transmits the asynchronous event to the event aggregation manager.
19	FREQUENCY PHASE DETECTION THREE PHASE SYSTEM	US13447849	2012-04-16	US20130271114A1	2013-10-17	Evropej Alimi
A system, method, and apparatus are described for monitoring the operation of a three phase system. In some embodiments, one or more vectors may be generated. The vectors may be indicative of an output of the three phase system. In some embodiments, one or more of the vectors may correspond to a difference of two of the three phases of the three phase system. A gain associated with a third of the vectors may be different from a gain associated with each of the first and the second vectors. The gain associated with the third vector may be maximized. The three vectors may be combined with hardware or software. In some embodiments, frequency content associated with the three phase system may be filtered with hardware or software. For example, filtering may be used to remove frequencies outside of a specified frequency range of interest.
20	Sparse segment trees for high metadata churn workloads	US14788184	2015-06-30	US09996426B1	2018-06-12	Prashant Pogde; Yamini Allu; Mahesh Kamat
Methods, systems, and apparatus for providing data storage services of a storage system are described. In one embodiment, a first file representing a first full backup including data and metadata describing the data is cached as a first segment tree having a plurality of layers of nodes in a tree hierarchy. A second file representing an incremental backup of the first full backup is cached as a second segment tree in the cache memory device. The second segment tree describes changes of the data and the metadata of the incremental backup in view of the data and the metadata of the first full backup without caching any of nodes of the first segment tree again. The first and second segment trees are collectively used to represent a second full backup based on the incremental backup and the first full backup.

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