最新美国发明专利第2023-10-03期 - 专利汇|PatentHub专利检索|专利查询网|发明专利查询分析

Document	Document Title
US11777715B2	Method and apparatus for generating shared secrets A method for generating a shared secret is disclosed. In an example embodiment, a sequence of data packets is transmitted from a first node to a second node. A packet error bitmap corresponding to packets in the sequence of packets that are received correctly in a first transmission attempt is generated at the second node. Further, the packet error bitmap is transmitted from the second node to the first node. Then, the first node and the second node separately mixes the packets received correctly in the first transmission attempt to generate the shared secret.
US11777711B1	Encryption and decryption engines with selective key expansion skipping A system on a chip (SoC) includes a security processor configured to determine that a first channel ID describing a {source, destination} tuple for a crypto packet matches a second channel ID describing a corresponding {source, destination} tuple for a preceding crypto packet received immediately prior to the crypto packet. The SoC also includes a decryption engine configured to, responsive to the determination that the first channel ID matches the second channel ID: obtain a set of round keys applied to perform an add round key computational stage of a previous decryption datapath used to decrypt a preceding cipher text block obtained from the preceding crypto packet, and to reuse the set of round keys to perform a corresponding add round key computational stage of a current decryption datapath used to decrypt a cipher text block obtained from the crypto packet.
US11777705B2	Techniques for preventing memory timing attacks Techniques and apparatuses for detecting and preventing memory attacks are described. In one embodiment, for example, an apparatus may include at least one memory comprising a shared memory and a system memory, logic, at least a portion of the logic comprised in hardware coupled to the at least one shared memory, the logic to implement a memory monitor to determine a memory attack by an attacker application against a victim application using the shared memory, and prevent the memory attack, the memory monitor to determine that victim data is being reloaded into the shared memory from the system memory, store the victim data in a monitor memory, flush shared memory data stored in the shared memory, and write the victim data to the shared memory. Other embodiments are described and claimed.
US11777704B1	Concurrent multistandard detection receiver with prepacket transmission detection A concurrent multistandard detection receiver with prepacket transmission detection capabilities is disclosed. In one aspect, a receiver is configured to switch between two different wireless protocols, alternately listening for incoming messages on one then the other protocol. For at least one listening period, the receiver uses two pretransmission detectors that are configured to detect predictable pretransmission emissions. A third detector may detect traditional transmissions. On detection of a signal that matches a predictable pretransmission emission or a traditional transmission, the receiver confirms that an incoming signal according to that standard is being received and acts in accordance with that signal. If no such emission or transmission was received, or if after trying to confirm the presence of an incoming signal fails, the receiver switches back to listening according to the other protocol.
US11777701B2	Phase synchronization circuit, transmission and reception circuit, and integrated circuit A phase synchronization circuit which includes a first delay circuit for adjusting a first delay amount, delaying a first reference clock signal by the first delay amount, and outputting a first delayed reference clock signal. The phase synchronization circuit further includes a first clock control circuit that compares phases of the first delayed reference clock signal and a first output clock signal and generates a first clock control signal based on a result of the comparison; a first clock signal generation circuit that generates the first output clock signal based on the first clock control signal; and a first monitoring circuit that monitors jitter in the first output clock signal and adjusts the first delay amount based on a result of monitoring the jitter in the first output clock signal.
US11777700B2	Dynamic time division duplex (DTDD) access for satellite RAN A ground station communicates with a satellite having a field of view (FOV), the satellite directly communicating with user equipment (UE) over uplink signals and downlink signals. The ground station has a Dynamic Time Division Duplex (DTDD) controller configured to establish UE uplink time slots during which the UE sends UE uplink signals, the UE uplink time slots based on a unique delay for the UE, whereby UE uplink signals are received at the satellite during a same satellite uplink time slot. The controller avoids overlapping uplink and downlink signals being received at the satellite, as well as at the UE.
US11777699B2	Implicit full duplex communication in 802.11ax wireless networks A wireless access point device is full-duplex capable and serves wireless communication for at least first and second wireless client devices. The wireless access point device sends to the first wireless client device a trigger frame that causes the first wireless client device to send an uplink transmission to the wireless access point after a first time interval. The wireless access point device waits a second time interval after the first wireless client is expected to begin sending the uplink transmission. The wireless access point device receives the uplink transmission from the first wireless client device. After the second time interval, and while receiving the uplink transmission from the first wireless client device, the wireless access point device sends to the second wireless client device a downlink transmission that overlaps at least partially in frequency and time with the uplink transmission from the first wireless client device.
US11777697B2	Method and apparatus for processing activation/deactivation of inter-eNodeB carrier aggregation The present invention relates to the technical field of radio communications, and particularly to a method and apparatus for processing activation/deactivation of inter-eNodeB carrier aggregation. Embodiments of the present invention provide a method for processing activation/deactivation of inter-eNodeB carrier aggregation, comprising the steps of: receiving, by UE, an MAC CE for activation/deactivation of an SCell sent by a master eNodeB or a secondary eNodeB; determining, by the UE, the corresponding SCell; and performing, by the UE, activation/deactivation to the corresponding SCell according to the indication information in the MAC CE for activation/deactivation.
US11777691B2	System and method for reporting signal quality information A wireless user equipment (UE) may employ any of various mechanisms for reporting signal quality measurements to a wireless network. The UE may impose a time delay between measurement and reporting, based on a delay parameter K. The UE may average measurements obtained at different measurement instances. The UE may employ any of various schemes for prioritizing transmission of one type of report over another, when temporal collisions occur between different types of report. The UE may employ a differential report that includes a state for indicating that a beam is not workable. The UE may employ a beam index that includes a state for indicating an invalid beam. A base station may receive a signal quality report and determine workability of a beam, e.g., by triggering a report of channel state information.
US11777685B2	Method and apparatus for wireless communication using modulation, coding schemes, and transport block sizes A method of processing a signal received over a wireless link may utilize sharing of Modulation and Coding Scheme (MCS) and Transport Block Size (TBS) data. At least one parameter is obtained including a sub-carrier spacing of a transport format. A modulation order and a transport block size may be detected, based on the at least one parameter. The signal received over the wireless link is then processed, based on the detected modulation order and the transport block size. An apparatus may perform the embodiments of the method to process the received signal.
US11777682B2	Techniques and apparatuses for wakeup signal design and resource allocation A method, an apparatus, a base station, a user equipment, and a computer program product for wireless communication are provided. The base station may configure resource allocation for wakeup signaling based at least in part on one or more resource patterns corresponding to different user equipment groups and/or antenna port configurations. The user equipment may receive a wakeup signal based at least in part on the resource allocation, detect the wakeup signal based at least in part on a preamble of the wakeup signal, and receive a subsequent communication based at least in part on the wakeup signal. Numerous other aspects are provided.
US11777679B2	Techniques for unified synchronization channel design in new radio Various aspects described herein relate to techniques for synchronization channel design and signaling in wireless communications systems (e.g., a 5th Generation (5G) New Radio (NR) system). In an aspect, a method includes identifying a frequency band supported by a user equipment (UE), identifying one or more frequency locations based on the identified frequency band, and the one or more frequency locations are a subset of synchronization raster points used for synchronization signal transmission. The method further includes searching for at least one synchronization signal based on the one or more identified frequency locations.
US11777677B2	Techniques for aligning clustered reference signal tones in wireless communications Aspects described herein relate to transmitting or receiving a demodulation reference signal (DMRS) for an antenna port over a set of multiple DMRS frequency tones in a symbol of a slot based on a DMRS configuration, and transmitting or receiving a phase tracking reference signal (PTRS) for the antenna port over a cluster of multiple PTRS frequency tones in the symbol or a different symbol of the slot, wherein the cluster of multiple PTRS frequency tones are adjacent to one another in frequency, and wherein at least one PTRS frequency tone in the cluster of multiple PTRS frequency tones is a non-zero power (NZP) PTRS frequency tone that overlaps, in frequency, at least one DMRS frequency tone in the set of DMRS frequency tones.
US11777674B2	Spectrum-efficient utilization of an uplink control channel A communication system for statically allocating physical uplink control channel (PUCCH) resources on a PUCCH. The communication system includes a base station configured to exchange radio frequency (RF) signals with a plurality of user equipment terminals (UEs). The base station is also configured to identify two PUCCH resources, each sharing the same orthogonal code sequence and located in different resource block of adjacent slots of a subframe. The base station is also configured to statically allocate the two PUCCH resources to two of the UEs, where both UEs are legacy UEs or Category-M1 (Cat-M1) UEs.
US11777673B2	Multiplexing of uplink control information for operation with multiple transmission-reception points A user equipment (UE) communicates with transmission-reception points (TRPs). When the UE generates uplink control information (UCI), it determines a higher layer index (HLI) value to target the UCI to the appropriate TRP. (Possible values of the HLI are associated with the TRPs.) For UCI on Physical Uplink Control Channel (PUCCH), the HLI value may be determined: based on an HLI value configured for a control resource set (CORESET), or for particular Physical Uplink Control Channel (PUCCH) resources; based on UCI type or spatial relation data or an index related to PUCCH resources. For UCI on a configured-grant Physical Uplink Shared Channel (PUSCH), the HLI value may be based on higher layer signals or an indicator relating to channel sounding on spatial relation data. For UCI on MsgA PUSCH in a two-step random access procedure, the HLI value may be based on PUSCH resource unit or PUSCH opportunity.
US11777672B2	Fiber back channel modem management system A method for equalizing a wireless communication channel includes transmitting a data signal over a primary channel. During transmission of the data signal, a corresponding data signal is sent over a secondary channel. The information received from the secondary channel is compared to the information received from the primary channel and differences between the information received from each of the channels are observed. These differences are used as inputs to an equalizer algorithm that may be used to reduce distortion of the data signal sent over the primary channel.
US11777668B2	Method and apparatus for device-to-device communication based on a threshold The subject application is related to a method and apparatus for Device-to-Device communication. A method for Device-to-Device communication includes transmitting a signal toward a group of user equipments (UEs); detecting a HARQ feedback signal accumulated by signal (s) from one or more UEs within the group of UEs; and transmitting a signal toward the group of UEs, wherein the UE and the group of UEs are configured to perform groupcast transmission.
US11777665B2	Information processing method, communication device and storage medium Provided are an information processing method, a communication device and a storage medium. The information processing method which is applied to a first communication device includes: sending X sets of parameter values jointly encoding M types of transmission parameters, where the M types of transmission parameters include a beam indication and/or a quasi-co-location indication parameter, where the beam indication is used for indicating a beam, the quasi-co-location indication parameter is used for indicating a parameter of the beam, and M>1; selecting Y sets of parameter values from the X sets of parameter values, where X>=Y>=1; and sending a selection indication based on the Y sets of parameter values, where the selection indication is used for selecting the Y sets of parameter values from the X sets of parameter values for a data transmission.
US11777661B2	URLLC HARQ processes A base station transmits configuration parameters indicating: a plurality of hybrid automatic repeat request (HARQ) processes of a cell; a subset of the plurality of HARQ processes; and a HARQ process identifier offset. The base station may further transmit a downlink control information (DCI) comprising a first HARQ process identifier and a resource assignment. The first HARQ process identifier indicates a HARQ process in the subset of the plurality of HARQ processes. A second HARQ process identifier is determined based on the first HARQ process identifier and the HARQ process identifier offset. The second HARQ process identifier indicates a second HARQ process of the plurality of HARQ processes. The base station may further receive a transport block of a HARQ buffer associated with the second HARQ process is transmitted, based on the resource assignment.
US11777653B2	Sequence design for noncoherent transmission with frequency and timing errors Methods, systems, and devices for wireless communications are described. A first network device (e.g., a base station) may determine, based on one or more transmissions received over a channel and a channel condition of the channel, a configuration for repeating a sequence from multiple sequences over a resource allocation. A second network device (e.g., a UE) may transmit one or more transmissions over a channel to the first network device. The first network device may transmit, to the second network device, an indication of the configuration for repeating the sequence over the resource allocation. The second network device may transmit a first instance of the sequence and a second instance of the sequence based on the configuration. The first network device may perform error correction on the data based on the received first instance of the sequence and the received second instance of the sequence.
US11777647B2	Method and apparatus for traffic transmission in communication system An operation method of a terminal may include: receiving, from a base station, an addition value KN, information on linear combination coefficient matrices for respective numbers of transport blocks, and configuration information on each linear combination coefficient matrix; dividing a source block into M transport blocks; selecting one linear combination coefficient matrix among the linear combination coefficient matrices based on M; generating (M+KN) network coding blocks by performing network coding on the M transport blocks with the selected one linear combination coefficient matrix; and transmitting, to the base station, messages each including one network coding block among the network coding blocks, a control index of the one linear combination coefficient matrix, and a preamble.
US11777645B2	Retransmission of physical uplink control channel (PUCCH) for ultra reliable low latency communications (URLLC) Techniques are provided for retransmission of Physical Uplink Shared Channel (PUCCH) for Ultra Reliable Low Latency Communications (URLLC). A User Equipment (UE) transmits at least one code block of a control channel, the at least one code block including Channel State Information (CSI), wherein each code block is polar encoded by assigning bit indices of the code block to bit channels in a particular order of reliabilities of the bit channels. The UE detects a trigger, and in response, retransmits at least a portion of each code block including retransmitted CSI, wherein the portion is polar encoded by assigning bit indices of the retransmitted CSI to the bit channels in the reverse order of reliabilities of the bit channels as compared to the polar encoding of the CSI.
US11777639B2	How to maximize phase-noise margins in 5G and 6G Enhanced phase-noise mitigation is possible at low-to-no cost. Communication at the high frequencies envisioned for late 5G and 6G will require much better phase-noise control than current frequency bands, because the tight margins will result in excessive phase faults and greatly reduced throughput. The disclosed examples show how to use two modulation schemes to provide the best phase margins at the final step. For example, the message can be initially modulated in classical amplitude-phase modulation as transmitted, but is received and processed using convenient QAM orthogonal components. Then the receiver can convert the results back to the amplitude-phase modulation scheme analytically, and can finally demodulate using calibrated amplitude and phase levels derived from a proximate demodulation reference. Since the amplitude-phase modulation scheme provides substantially larger phase margins than QAM with the same information content, substantially higher frequencies can be accessed while retaining high reliability.
US11777638B2	Reliable link quality estimation in multi-rate networks Techniques are directed to using communication metric data associated with multiple modulation schemes to achieve a link quality metric that is representative of the link as a whole, across the multiple modulation schemes that may be employed on the link. A calculation of a link quality metric may be triggered by a network layer transmission attempt, with communication metrics accumulated at the link layer of the link. A filter used to calculate the link quality metric may be updated based on network layer transmission attempts, based on successful and/or unsuccessful transmissions at a Media Access Control (MAC) layer of the link. More generally, a calculation of link quality may be triggered by a higher layer transmission attempt while being calculated based on transmission attempts at a lower layer of the link.
US11777637B2	System and method for phase manipulation attack protection and detection in AoA and AoD Systems and methods for detecting and protecting against phase manipulation during AoA or AoD operations are disclosed. For AoA operations, the network device receiving the constant tone extension (CTE) generates an antenna switching pattern, which may be randomly generated. The network device then receives the CTE using a plurality of antenna elements. In one embodiment, the network device compares the phase of portions of the CTE signal received that utilize the same antenna element. If the phase of these portions differs by more than a threshold, the network device detects a malicious attack and acts accordingly. In another embodiment, if the AoA algorithm cannot determine the angle of arrival, the network device detects a malicious attack and acts accordingly. For angle of departure operations, the network device that transmits the CTE signal generates the antenna switching pattern and transmits it to the position engine, which performs the comparisons described above.
US11777635B2	Diffraction compensated compact wavelength division multiplexing devices A wavelength division multiplexing device includes a common port and a plurality of filters that define an optical path. The common port includes a collimator that transmits an optical beam including a plurality of optical signals. Each optical signal is associated with a different wavelength range, and each filter includes an interface having a radius of curvature. One filter is configured to receive the optical beam from the collimator, transmit an optical signal through its interface, and reflect the remaining portion of the optical beam toward another filter. The common collimator and filter are configured so that the reflected portion of the optical beam has a beam waist located in the optical path midway between the filters, and a wavefront radius of curvature at the other filter that matches the filter radius of curvature of that filter. A method of processing light in such a device is also disclosed.
US11777634B2	Bundling capacity changes in channel holder based optical links Systems and methods include, responsive to a request for capacity change of X channels, X is an integer >1, on an optical section (14) and at an Optical Add/Drop Multiplexer (OADM) node (12) in an optical network (10), dividing optical spectrum on the optical section into M slots, M is an integer >1, such that the capacity change of X channels takes a maximum of N steps, N is an integer >1; and performing the capacity change of X channels in up to the N steps in an interleaved manner that changes a subset of the X channels in each of the N steps. For each step, the performing can include a maximum of M/N slots of the M slots with spacing between each of the M/N slots not used for the capacity change in a corresponding step. The spacing can be f, (N+f), (2N+f), . . . , M over the optical spectrum, where f is each step, f=1, 2, . . . , N.
US11777633B2	Optical multiplexer/demultiplexer module and associated methods A TORminator module is disposed with a switch linecard of a rack. The TORminator module receives downlink electrical data signals from a rack switch. The TORminator module translates the downlink electrical data signals into downlink optical data signals. The TORminator module transmits multiple subsets of the downlink optical data signals through optical fibers to respective SmartDistributor modules disposed in respective racks. Each SmartDistributor module receives multiple downlink optical data signals through a single optical fiber from the TORminator module. The SmartDistributor module demultiplexes the multiple downlink optical data signals and distributes them to respective servers. The SmartDistributor module receives multiple uplink optical data signals from multiple servers and multiplexes them onto a single optical fiber for transmission to the TORminator module. The TORminator module coverts the multiple uplink optical data signals to multiple uplink electrical data signals, and transmits the multiple uplink electrical data signals to the rack switch.
US11777629B2	Reference time determining method and apparatus A reference time determining method and apparatus are provided, to prevent aberrations in a control instruction execution time caused by inconsistency between a reference time of a terminal and a reference time of a control device in the conventional technology. In this application, the terminal may receive a plurality of pieces of time reference information sent by the network device. When the terminal receives indication information from the network device, the terminal may select, based on the indication information, one piece of time reference information from the plurality of pieces of time reference information as first time reference information. The indication information indicates the first time reference information. After determining the first time reference information, the terminal may determine the reference time of the terminal based on the first time reference information.
US11777623B2	Systems and methods for identifying a source of radio frequency interference in a wireless network An interference detection system in a network identifies a first wireless station that has experienced radio frequency (RF) interference from an unknown source on at least one physical resource block (PRB) by determining that a key performance indicator (KPI) for the at least one PRB on the first wireless station has a value indicative of interference. The interference detection system identifies one or more second wireless stations that have experienced similar interference on the at least one PRB. A plurality of estimated interference source locations are determined based at least on geographic locations of the first wireless station and the one or more second wireless stations. Determining the plurality of estimated interference source locations further comprises generating a boundary based on the geographic locations of the first wireless station and the one or more second wireless stations and selecting a plurality of estimated interference source locations within the boundary.
US11777621B2	User equipment including spectrum analyzer, and network device User equipment (UE) can include a spectrum analyzer to monitor characteristics of transmission channels. The user equipment can monitor a 600 MHz spectrum and associated channels, for example, to determine if the spectrum is free of interference or is currently occupied. The UE can analyze a received signal strength indication (RSSI), a reference signal received power (RSRP), a reference signal received quality (RSRQ), and signal-to-interference-plus-noise ratio (SINR), for example, to distinguish between types of interference if a channel is occupied. User equipment (UE) can aggregate data and report such data to a network device further aggregate the data and to generate reports. Network components can be deployed or optimized based at least in part on network metrics provided by individual UEs or aggregated data provided by a plurality of UEs. In some instances, the UE can be a mobile phone of a customer to gather metrics in a distributed manner.
US11777613B2	Polarization change tracking apparatus, processing apparatus for received signal and methods thereof A polarization change tracking apparatus, a processing apparatus for a received signal and methods thereof. The polarization change tracking method includes: estimating a polarization change speed in a link according to a received signal; setting a response coefficient of polarization tracking according to a relationship between an estimated polarization change speed and a predetermined value, to make a response of polarization tracking and a response of adaptive equalization be consecutive; and performing compensation for polarization change on the received signal according to a set response coefficient of polarization tracking.
US11777612B2	Method for nonlinear compensation of coherent high-capacity high-order qam system The invention provides a method for nonlinear compensation of coherent high-capacity high-order QAM system, including: deploying an OPC on an intermediate link of communication between a transmitter and receiver, and performing phase conjugation on a transmitted signal based on the OPC to generate idler; performing phase recovery on a compensated signal at the receiver to obtain a constellation diagram, simulating a nonlinear function relationship between a transmitted signal and a received signal by using a trained and learned CVDNN, and performing nonlinear compensation on the constellation diagram to obtain the compensated constellation diagram; and calculating a Q-factor based on the compensated constellation diagram, and evaluating communication performance by the Q-factor. Nonlinear compensation is performed on a transmitted signal by using an OPC+CVDNN method to equalize nonlinear degradation of an optical fiber in a WDM coherent optical communication system.
US11777611B2	Coherent optical receiving apparatus and optical system that uses coherent optical receiving apparatus A coherent optical receiving apparatus including a polarization optical splitter, a polarization controller, an optical hybrid unit, and a combiner. The polarization optical splitter is connected to an input terminal of the optical hybrid unit, and an output terminal of the optical hybrid unit is connected to the combine. The polarization optical splitter receives signal light and local oscillator light in any polarization mode, decomposes the signal light into a plurality of beams of sub signal light, and decomposes the local oscillator light into a plurality of beams of sub local oscillator light. The optical hybrid unit obtains a plurality of beams of hybrid light by performing optical hybridization on the sub signal and sub local oscillator lights, the combiner performs conversion on the plurality of beams of hybrid light to obtain and output coherent electrical signals, and the polarization controller controls polarization of the local oscillator light.
US11777610B2	Method and apparatus for ultra-short pulsed laser communication through a lossy medium Free-space optical (FSO) wireless transmission, including optical communications, remote-sensing, power beaming, etc., can be enhanced by replacing conventional laser sources that operate in the infrared portion of the optical spectrum with ultra-short pulsed laser (USPL) sources having peak pulse powers of one kWatt or greater and pulse lengths of less than one picosecond. Specifically, it has been observed that under these conditions the attenuation of an USPL beam having the same average optical power as a conventional laser in a lossy medium, such as the atmosphere, is substantially less than the attenuation of a conventional laser beam having a lower peak pulse power and/or a longer pulse width. The superior system performance when using an USPL can be translated into an increased distance between a laser source in a transmitter and a photodetector in receiver and/or a higher reliability of system operation in inclement weather conditions.
US11777604B2	Gate-based optical data transmission A system and method for updating and maintaining an onboard entertainment server on an aircraft includes a gate LiFi access point positioned in a gate area of an airport, the gate LiFi access point having a removable server. An aircraft LiFi receiver is positioned in the aircraft, the aircraft LiFi receiver and the removable server capable of line-of-sight transmission of updated data and a content loader receives the updated data in the onboard entertainment server.
US11777592B2	Intelligent measurement and control communication network system The intelligent measurement and control communication network at least includes at least one management node and at least one common node. The whole intelligent measurement and control communication network is logically divided into a control plane and a service plane. The control plane selects a routing strategy with the shortest path to cause each management node on the control plane to communicate with all common nodes. The service plane is divided into multiple task subnets according to tasks performed by each node, and each task subnet may select different routing strategies according to task requirements of this task subnet. According to the application and scenario needs of the tasks, the control plane combines externally changed parameters and utilizes machine learning to generate a new mathematical model in real time and sends a new task instruction to the service plane.
US11777575B2	CSI reporting method and apparatus The present disclosure relates to channel state information (CSI) reporting methods and apparatus. When receiving first indication information used to trigger reporting of CSI, a terminal device determines a first time interval from a plurality of candidate first time intervals. The first time interval is used to determine whether the first indication information is valid. The terminal device reports the CSI based on the first time interval.
US11777572B2	Method for generating at least one backscattering zone of an ambient signal and/or for receiving a backscattered ambient signal A process for generating at least one backscattering zone, by at least one transmitter device and to at least one receiver device, of an ambient radio signal emitted by at least one source; and a process for generating at least one reception zone, by the receiver device, of the backscattered ambient signal. The process for includes: determining an emission constraint, when it is respected by the source, for generating at least one backscattering zone in which the received electromagnetic power is greater than a determined threshold, called “backscattering threshold”, and/or generating at least one reception zone in which the received electromagnetic power is less than a determined threshold, called “reception threshold”; and transmitting, by the source, with respect to the emission constraint.
US11777570B2	Simultaneous beamforming and nullforming for secure wireless communications Systems and methods for wireless communications comprising a plurality of agents, which together as the group, are configured to: (i) wirelessly broadcast an interference signal by forming a radiation pattern having null vectored substantially toward a client; (ii) wirelessly transmit a communication signal to the client by forming a radiation beam carrying the communication signal vectored substantially toward the client; and (iii) wirelessly broadcast a combined communication signal and interference signal to the client using phases of processes (i) and (ii). In some embodiments, the agents together as a group may be further configured to: allocate and adjust power for performing processes (i) and (ii) at substantially the same time.
US11777565B2	Downlink multiple input multiple output enhancements for single-cell with remote radio heads A base station selects a subset of at least one geographically separated antennas for each of the plurality of user equipments. The base station forms at least layer of data stream including modulated symbols, precodes the data stream via multiplication with the NT-by-N precoding matrix where N is the number of said layers and NT is the number of transmit antenna elements and transmits the precoded layers of data stream to the user equipment via the selected geographically separated antennas. The base station signals the subset of the plurality of geographically separated antennas via higher layer Radio Resource Control or via a down link grant mechanism. The base station optionally does not signal the subset of the plurality of geographically separated antennas to the corresponding mobile user equipment.
US11777563B2	Broadcast signal transmission method, broadcast signal transmission apparatus, broadcast signal reception method, and broadcast signal reception apparatus Disclosed is a transmission scheme for transmitting a first modulated signal and a second modulated signal in the same frequency at the same time. According to the transmission scheme, a precoding weight multiplying unit multiplies a precoding weight by a baseband signal after a first mapping and a baseband signal after a second mapping and outputs the first modulated signal and the second modulated signal. In the precoding weight multiplying unit, precoding weights are regularly hopped.
US11777557B2	Personal mobile signal egress logging and augmented reality leak locator A system, method and computer application to log signal egress (leakage signal) readings from a test instrument during a “walkout” mode where the technician and test instrument have left a vehicle and troubleshooting is being performed on foot. A unique troubleshooting and discovery dataset is created and capable of revealing problems not previously discoverable using vehicle mounted test instruments. In addition, the dataset may be used for quality control and other purposes such as e.g., providing a report or mapping of the path the technician used during the troubleshooting process. Augmented reality features may also be displayed on the technician's mobile device to facilitate finding the source of one or more leaks.
US11777554B2	In-device coexistence for new radio A network control device, e.g., a gNB, receives a message from a communications device, e.g. a UE, indicating that the communications device is experiencing an in-device coexistence (IDC) problem, e.g. in the 52.6 GHz-71 GHz frequency range with respect to NR-U and WiGig. The message is one of: i) an IDC assistance message indicating that the victim system is Wi-Gig or ii) an antenna panel switch message requesting that the network control device instruct the communications device to change the antenna panel that it uses for uplink NR signaling. The network control device generates and sends a response message to the communications device including: a selected new frequency to be used by the communications device for uplink NR signaling or a selected different antenna panel to be used by the communications device for uplink NR signaling. The communications device implements the change reducing or avoiding the IDC problem.
US11777553B2	High-frequency module A high-frequency module includes a transmission signal amplifier that outputs a transmission signal to an antenna terminal side; a reception signal amplifier that amplifies a reception signal supplied from an antenna terminal; a switch that selectively connects the antenna terminal to either an output of the transmission signal amplifier or an input of the reception signal amplifier; and a directional coupler that is provided on a transmission signal path and detects a signal level of the transmission signal. The transmission signal amplifier is controlled by a first control signal supplied from a first control circuit. The reception signal amplifier is controlled by a second control signal supplied from a second control circuit. The switch is controlled by a switch control signal supplied from the first control circuit. The directional coupler is controlled by a coupler control signal supplied from the first control circuit.
US11777550B2	Device cradle Provided is a device cradle. The device cradle includes a fixer for fixing a device, a body portion including a main body and a penetrating groove which is formed to penetrate the main body from a top surface of the main body and accommodates at least a portion of the fixer, and a first driving portion for rotating the fixer by a specified angle around a horizontal axis with respect to the body portion, wherein the penetrating groove has a spherical shape, and wherein at least part of the fixer may be formed in a spherical shape.
US11777549B2	Radio frequency front end modules implementing coexisting time division duplexing and frequency division duplexing Radio frequency front end modules implementing coexisting time division duplexing and frequency division duplexing are provided. In one aspect, a front end system includes a time-division duplexing transmit terminal, a time-division duplexing receive terminal, a frequency division duplexing terminal, and an antenna terminal. The front end system further includes first, second, and third switches configured to selectively connect the terminals to either a node or the antenna. The front end system also includes a controller configured to provide delays between disconnecting the terminals from the antenna and connecting the terminals to the node.
US11777546B2	Receiver with improved noise immunity A binary receiver combines a fast amplifier with a relatively slow amplifier for noise rejection. Both the fast and slow amplifiers employ hysteresis. The fast amplifier has relatively lower hysteresis, meaning that its sensitivity is a less effected by prior data values but more susceptible to glitch-induced errors. Conversely, the slow amplifier has relatively higher hysteresis and rejects glitches but introduces undesirable signal-propagation delays. A state machine taking input from both amplifiers allows the receiver to filter glitches without incurring a significant data-propagation delay.
US11777545B2	Interference cancellation device, control circuit, storage medium, and interference center frequency estimation method An interference cancellation device includes a data symbol extraction unit that extracts a data symbol portion from a received signal, a null symbol extraction unit that extracts a null symbol portion from the received signal, a data symbol power calculation unit that calculates a data symbol power estimated value, a null symbol power calculation unit that calculates a null symbol power estimated value, a null symbol spectrum calculation unit that calculates a null symbol spectrum from a null symbol signal, and an interference center frequency estimation unit that eliminates the effect of an image for an interference in calculation of an interference bandwidth when is calculating an interference center frequency estimated value, using a data symbol signal, the data symbol power estimated value, the null symbol power estimated value, and the null symbol spectrum.
US11777538B2	Differential output circuits with configurable harmonic reduction circuits and methods of operation thereof An electronic circuit includes a differential output circuit that produces a differential output signal at a differential output. A primary winding of a balun has a first balun terminal coupled to a first differential output terminal, and a second balun terminal coupled to a second differential output terminal. A configurable harmonic reduction circuit includes first and second configurable shunt capacitance circuits coupled between the first differential output terminal or the second differential output terminal, respectively, and a ground reference node. A control circuit receives tuning data associated with a calibrated tuning state. The tuning data indicates a first and second calibrated capacitance values, which are unequal, for the first and second configurable shunt capacitance circuits, respectively. The control circuit controls the first configurable shunt capacitance circuit to have the first calibrated capacitance value, and controls the second configurable shunt capacitance circuit to have the second calibrated capacitance value.
US11777536B2	Devices and methods for radio frequency front end systems A wireless device comprising a first antenna and second antenna, a transceiver and a radio frequency front end system electrically coupled between the transceiver and the antennas. The RF front end system includes a first module operable to provide a high band transmit signal to the first antenna, receive a first high band receive signal and a first mid band receive signal from the first antenna. The first high band receive signal has a frequency range greater than that of the first mid band receive signal. The RF front end system further includes a second module operable to provide a mid band transmit signal to the second antenna, receive a second mid band receive signal and a second high band receive signal from the second antenna. The second high band receive signal has a frequency range greater than that of the second mid band receive signal.
US11777533B2	Method for polar decoding with dynamic successive cancellation list size and polar decoder It provides a method (300) for polar decoding a received signal into a number, N, of bits with Successive Cancellation List, SCL. The method (300) includes: at the i-th level of a binary tree for decoding the i-th bit of the N bits, where 1≤i≤N: when the i-th bit is an information bit, calculating (310) a path metric for each of 2Li-1 candidate paths at the i-th level, where Li-1 is an SCL size at the (i−1)-th level and L0=1; setting (320) an SCL size at the i-th level, Li, based on Li-1 and a statistical distribution of the path metrics calculated for the 2Li-1 candidate paths; and selecting (330) Li surviving paths from the 2*Li-1 candidate paths based on their respective path metrics.
US11777529B2	Binned feedback from receiving device to network encoder This disclosure provides systems, methods and apparatus, including computer storage media, for retransmission of sidelink transmissions using network coding with binned feedback. A transmitting device transmits a transport block and a request for a network coding (NC) encoding device to retransmit the transport block to a plurality of user equipment (UEs). The UEs decode the transport block and report an acknowledgment (ACK) or negative acknowledgment (NACK) on a physical sidelink feedback channel (PSFCH) resource associated with a bin for the UEs. The NC encoding device decodes the PSFCH resource for each bin to determine an ACK or NACK status for each bin, and determines whether to encode the transport block in a NC combination packet. The UEs receive the NC combination packet including an encoding of a subset of transport blocks. The receiving devices transmit an ACK or NACK on a PSFCH resource for a bin for each transport block.
US11777526B2	Efficient control channel design using polar codes Aspects of the disclosure relate to wireless communication systems configured to provide techniques for multiplexing dedicated control information for a plurality of users in a single information block and polar coding the information block to produce a polar code block of dedicated control information for transmission over a wireless air interface. The information block may further include group cyclic redundancy check (CRC) information for the information block and individual CRC information for each dedicated control information.
US11777525B2	Method for transmitting LDPC code using row-orthogonal and apparatus therefor A method for encoding a quasi-cyclic low-density parity-check (LDPC) code according to an embodiment of the present invention may comprise the steps of: generating a multi-edge LDPC code matrix including a high rate code matrix and a single parity check code matrix; and encoding a signal by using the multi-edge LDPC code matrix, wherein the single parity check code matrix includes a first matrix having a non-row-orthogonal structure matrix and a second matrix having a pure row-orthogonal structure, which are concatenated.
US11777522B1	Bit flipping decoder with dynamic bit flipping criteria Methods, systems, and apparatuses include receiving a codeword stored in a memory device. Syndrome information and energy function values are determined for bits of the codeword. A bit flipping criterion is selected using the syndrome information from a plurality of values. A bit of the codeword is flipped when the energy function values for a bit of the codeword satisfies the bit flipping criterion. A corrected codeword that results from the flipping of the bits is returned.
US11777511B2	Linearization of digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) and associated methods Systems and methods for processing and storing digital information are described. One embodiment includes a method for linearizing digital-to-analog conversion including: receiving an input digital signal; segmenting the input digital signal into several segments, each segment being thermometer-coded; generating a redundant representation of each of the several segments, defining several redundant segments; performing a redundancy mapping for the several segments, defining redundantly mapped segments; assigning a probabilistic assignment for redundantly mapped segments; converting each redundantly mapped segment into an analog signal by a sub-digital-to-analog converter (DAC); and combining the analog signals to define an output analog signal.
US11777509B2	Radar system and related method of scanning remote objects A radar system includes: a plurality of first receiving devices for generating a plurality of first digital signals according to a plurality of first incoming signals, respectively; and a plurality of second receiving devices for generating a plurality of second digital signals according to a plurality of second incoming signals, respectively. A processing device is arranged to perform a first beamforming operation to generate a plurality of first beamforming signals according to the plurality of first digital signals and a first gain matrix, and to perform a second beamforming operation to generate a plurality of second beamforming signals according to the plurality of second digital signals and a second gain matrix; and to determine an altitude angle of a first object and a second object, and to determine a first azimuth angle of the first object and a second azimuth angle of the second object.
US11777498B2	High power RF switch with controlled well voltage for improved linearity RF transistors manufactured using a bulk CMOS process exhibit non-linear drain-body and source-body capacitances which degrade the linearity performance of the RF circuits implementing such transistors. The disclosed methods and devices address this issue and provide solutions based on implementing two or more bias voltages in accordance with the states of the transistors. Various exemplary RF circuits benefiting from the described methods and devices are also presented.
US11777495B2	Driver circuitry and operation This application relates to methods and apparatus for driving a transducer with switching drivers where the switching driver has an output bridge stage for switching an output node between switching voltages and a modulator for controlling the duty cycle of the output bridge stage based on an input signal. The switching driver also includes a voltage controller for providing the switching voltages which is operable to provide different switching voltages in different driver modes. A controller is provided to control the driver mode of operation and the duty cycle of the switching driver based on the input signal, and the controller is configured to transition from a present driver mode to a new driver mode by controlling the voltage controller to provide the switching voltages for the new mode and controlling the modulator to vary the duty cycle of the output bridge stage. The change in duty cycle is controlled such that there is no substantial discontinuity in switching ripple due to the mode transition.
US11777494B2	Level shift circuit A level shift transistor of a first conductivity type configured to level shift a signal from a primary side circuit to a secondary side circuit between the primary side circuit having a primary side reference potential as reference and the secondary side circuit having a secondary side reference potential independent from the primary side reference potential as reference, a diode connected in a forward direction between a first main electrode of the level shift transistor and the secondary side circuit, a capacitor connected in parallel to the diode, and an inverter configured to invert the signal are provided. A control electrode of the level shift transistor is connected to a primary side power supply of the primary side circuit, and a second main electrode thereof is connected to an output of the inverter. The inverter operates between the primary side reference potential and the primary side power supply.
US11777487B1	Gate driver coreless transformers for magnetic resonance imaging power electronics A gate driver circuit includes an isolated gate driver power supply circuit. The isolated gate driver power supply circuit includes a coreless transformer including a primary winding and a secondary winding. The secondary winding is wound about a toroid-shaped, non-magnetic body and the primary winding is a single turn primary winding to reduce capacitance coupling between the primary winding and the secondary winding. The isolated gate driver power supply circuit also includes a resonance converter coupled to the coreless transformer, wherein the resonance converter is configured to enable the isolated gate driver power supply circuit to generate an output voltage independent of load.
US11777482B2	Gain-boosted comparator The present invention provides a dynamic comparator including a dynamic amplifier and a latch circuit. The dynamic amplifier includes a first input pair, a current source and a gain boosting circuit. The first input pair is configured to receive an input signal to generate an amplified signal at an output terminal. The current source is coupled between the first input pair and a first reference voltage. The gain-boosting circuit is coupled between the first input pair and a second reference voltage, and is configured to receive the input signal to selectively inject current to the output terminal or sink current from the output terminal. The latch circuit is coupled to the dynamic amplifier, and is configured to receive the amplified signal to generate an output signal.
US11777481B2	Noise-tolerant delay circuit In a delay circuit, first and second sets of transistors are connected in series between a supply voltage and a ground. The first and second sets of transistors both include a current source transistor, a cascode transistor, and a control transistor. The first set of transistors generates a current that charges a capacitor to generate a ramp signal with a positive slope. A first bias transistor may cause the ramp signal to be biased to ground upon activating the first set of transistors. The second set of transistors generates a current that discharges the capacitor to generate the ramp signal with a negative slope. A second bias transistor may cause the ramp signal to be biased to the supply voltage upon activating the second set of transistors. The delay circuit transitions the state of the output signal based on a voltage level of the ramp signal.
US11777476B2	Level shifter circuit with integrated feedback circuit, dc-dc converter, and method There is described a pulse-triggered level shifter circuit comprising: i) a command circuit configured to shift a command input signal of a first voltage domain to a command output signal of a second voltage domain, the command circuit comprising: a) a command input stage for receiving the command input signal, and b) a command output stage for providing the command output signal; and ii) a feedback circuit coupled to the command circuit and configured to shift a feedback input signal of a third voltage domain to a feedback output signal of a forth voltage domain, the feedback circuit comprising: c) a feedback input stage for receiving the command output signal as the feedback input signal, and d) a feedback output stage for providing the feedback output signal. The command circuit and the feedback circuit are hereby integrated into one single level shifter circuit.
US11777474B2	Signal generation circuit having minimum delay, semiconductor apparatus using the same, and signal generation method A signal generation circuit includes a first delay circuit, a second delay circuit, and a duty control circuit. The first delay circuit delays a first input signal to generate a first output signal. The second delay circuit delays a second input signal to generate a second output signal. The duty control circuit compares phases of the first and second output signals and changes the value of the second delay control signal, and then decreases the times, by which the first and second input signals are delayed, by the same value.
US11777469B2	Bonded substrate, surface acoustic wave element, surface acoustic wave element device, and bonded substrate manufacturing method A bonded substrate includes a quartz substrate and a piezoelectric substrate which is bonded on the quartz substrate and on which a surface acoustic wave propagates, wherein the quartz substrate and the piezoelectric substrate are bonded by covalently coupling at a bonding interface, and an orientation of the quartz substrate and an orientation of the piezoelectric substrate intersect with each other on an orthogonal direction side or in the range of 65 degrees to 115 degrees in a bonding surface direction.
US11777468B2	Acoustically decoupled MEMS devices Embodiments of the present disclosure relate generally to acoustically decoupled microelectromechanical system devices and, more particularly, to acoustically decoupled microelectromechanical system devices anchored upon phononic crystals. In some embodiments described herein, a device may comprise a resonator, a handle layer, and a pedestal disposed between the resonator and the handle layer, the pedestal connecting the resonator to the handle layer. In the devices described herein, the resonator and the handle layer may be non-coplanar. In some embodiments, the handle layer comprises a phononic crystal to acoustically decouple the resonator from the substrate of the handle layer.
US11777467B2	Air-gap type film bulk acoustic resonator An air-gap type film bulk acoustic resonator (FBAR) is provided. The air-gap type FBAR includes a substrate which comprises an air gap portion having a substrate cavity formed in a top surface, a lower electrode formed on the substrate, a piezoelectric layer which is formed on the lower electrode and has one side forming an edge portion in the vicinity of a virtual edge according to vertical projection of the air gap portion, an upper electrode formed on the piezoelectric layer, a first electrode frame which comprises an open ring structure in plane, the open ring structure surrounding a part of a periphery of the piezoelectric layer on the lower electrode, and a second electrode frame positioned on the upper electrode and adjacent to an open portion of the open ring structure.
US11777465B2	Packaged surface acoustic wave devices Packaged surface acoustic wave devices are provided. The packaged surface acoustic wave devices are relatively thin and can have a height of less than 220 micrometers. The packaged surface acoustic wave device includes a photosensitive resin over a conductive structure which may be formed by a plating process. The conductive structure may overlie a cavity-defining structure encapsulating a surface acoustic wave device, the cavity-defining structure including walls and a roof. The photosensitive resin can include a phenol resin. The photosensitive resin can be relatively thin. Edge portions of a piezoelectric substrate can be free from the photosensitive resin.
US11777463B2	Multipath programmable gain instrumentation amplifier frontend A system includes an instrumentation amplifier (INA) including a first transistor coupled to a first input node, and a second transistor coupled to a second input node. The INA also includes a resistor coupled between the first transistor and the second transistor. The INA includes a gain resistor network coupled to the resistor and to the first and second transistors, where the gain resistor network includes two or more gain resistors. The system also includes a voltage to current converter, where the voltage to current converter is coupled to the resistor and the gain resistor network.
US11777457B2	Circuit and a method for generating a radio frequency signal A circuit for generating a radio frequency signal is provided. The circuit includes an amplifier configured to generate a radio frequency signal based on a baseband signal. Further, the circuit includes a power supply configured to generate a variable supply voltage based on a control signal indicating a desired supply voltage, and to supply the variable supply voltage to the amplifier. The circuit further includes an envelope tracking circuit configured to generate the control signal based on a bandwidth of the baseband signal, and to supply the control signal to the power supply.
US11777453B1	Public voltage compensation method and display panel Disclosed are a public voltage compensation method and a display panel. The public voltage compensation method includes: installing the first multi-channel operational amplifier; connecting the first public voltage feedback output terminal with the first feedback input terminal, connecting the second public voltage feedback output terminal with the second feedback input terminal, connecting the first compensation input terminal with the first compensation output terminal, connecting the third compensation input terminal with the third compensation output terminal, connecting one of the n second compensation input terminals with the second compensation output terminal, and connecting one of the n fourth compensation input terminals with the fourth compensation output terminal; interconnecting each of the n second compensation input terminals and interconnecting each of the n fourth compensation input terminals.
US11777452B1	High-speed transimpedance amplifier with bandwidth extension feature over full temperature range and bandwidth extension method A high-speed transimpedance amplifier with bandwidth extension feature over full temperature range and bandwidth extension method belong to the field of integrated circuit. The present invention solves the problem existed in boosting core amplifier bandwidth technology over full temperature range. The present invention includes a preamplifier TIA, a phase splitting stage PS, a pre-driver stage Pre-Drive, an output buffer BUFF and an offset cancelation circuit OC. The preamplifier TIA adopts the gate-drain voltage cancelation technology to expand the bandwidth, so that its −3 dB bandwidth is greater than twice the closed-loop bandwidth of the first-order TIA. The pre-driver stage Pre-Drive is used to drive the output buffer BUFF. By adjusting the source-level negative feedback capacitance value of the pre-driver stage Pre-Drive circuit to generate a high-frequency gain that varies with temperature, the preamplifier TIA bandwidth differences under different temperature conditions are compensated.
US11777451B2	Cascode gain boosting and linear gain control using gate resistor Methods and apparatuses for controlling gain of a single stage cascode FET amplifier are presented. According to one aspect, a series-connected resistor and capacitor is coupled to a gate of a cascode FET transistor of the amplifier, the capacitor providing a short at frequencies of operation of the amplifier. According to another aspect, values of the resistor can be used to control gain of the amplifier. According to yet another aspect, the resistor is a variable resistor whose value can be controlled/adjusted to provide different gains of the amplifier according to a linear function of the resistor value. An input matching network coupled to an input of the amplifier can be used to compensate for different noise figure degradations from different values of the resistor.
US11777449B1	Frequency mixing An apparatus is disclosed for mixing signals. In example aspects, the apparatus includes a mixer circuit having multiple local oscillator nodes, a first node corresponding to a first frequency, and multiple second nodes corresponding to a second frequency. The mixer circuit includes multiple capacitors coupled between the multiple local oscillator nodes and the multiple second nodes. The mixer circuit has multiple switches including a first switch, a second switch, a third switch, and a fourth switch. The multiple switches are coupled between the multiple capacitors and the multiple second nodes. The first switch and the second switch are coupled between the multiple capacitors and the first node. The first switch and the second switch are disposed between the fourth switch and the third switch.
US11777448B2	Efficient high power microwave generation using recirculating pulses A high frequency electromagnetic radiation generation device is disclosed that includes a high voltage input, a nonlinear transmission line, an antenna, and a pulse recirculating circuit. In some embodiments, the high voltage input may be configured to receive electrical pulses having a first peak voltage that is greater than 5 kV, and/or may be electrically coupled with the nonlinear transmission line. The antenna may be electrically coupled with the nonlinear transmission line and/or may radiate electromagnetic radiation at a frequency greater than 100 MHz about a voltage greater than 5 kV. The pulse recirculating may be electrically coupled with the high voltage input and the antenna. The pulse recirculating circuit may include a diode; a low pass filter; and a delay line. In some embodiments, unradiated energy from the antenna is directed through the pulse recirculating circuit to the nonlinear transmission line with a delay of less than 100 ns.
US11777439B2	Compact, lightweight, portable trailer with solar tower and autonomous hybrid power solutions Embodiments related to a power platform having a mobile trailer, a tower pivotally attached to the mobile trailer, and a plurality of power sources. The plurality of power sources including at least a solar panel disposed on the tower and a fuel cell generator. The power platform also includes a housing having a transfer switching assembly and a power cord panel, wherein the transfer switching assembly is configured to receive electrical power generated from the plurality of power sources and convert the electrical power for transfer to ancillary devices via the power cord panel.
US11777437B2	Fault tolerant operations of a six-phase machine A method of operating a multi-phase electric machine includes operating a six-phase machine with six phases that are configured into a first group having a first neutral connection and a second group having a second neutral connection. The method also includes determining whether at least one of the six phases is experiencing a fault. In response to the determining, the method includes combining the first and second neutral connections to form a common neutral connection to continue operating the six-phase machine by using the remaining phase not experiencing the fault.
US11777436B2	Method and system for a safety concept for an AC battery A method for a safety concept for an AC battery, in which the AC battery includes a central controller, a plurality of battery modules which respectively have a power board with a plurality of switching states, a plurality of contactors, a plurality of current sensors, a fault loop and a high-speed bus and is connected to a traction machine. The central controller has a hardware-programmable processor unit with at least one microprocessor core on which a control program is configured to control the battery modules, the plurality of contactors and the fault loop. A state machine is implemented by the control program. The battery modules are connected, starting from the central controller, via the high-speed bus and the fault loop. If an abort fault occurs, the AC battery is changed to a safe operating state. The safe state is achieved at least by emergency disconnection of the central controller.
US11777434B2	Method for operating a drive system, and drive system In a method for operating a drive system, and drive system, having a rectifier and at least one inverter including an electric motor, the electric motor is connected at the AC-voltage-side connection of the inverter, the DC-voltage-side connection of the inverter is connected via inductance(s) in addition to the line inductance, to the DC-voltage-side connection of the rectifier, a capacitance is connected at the DC-voltage-side connection of the inverter and/or at the DC-voltage-side connection of the rectifier, a series circuit, including a resistor and a controllable semiconductor switch is connected at the DC-voltage-side connection of the inverter and/or at the DC-voltage-side connection of the rectifier, the braking chopper being operated using a single frequency during the particular time span in which the braking chopper is in operation, the frequency, e.g., being set apart from the resonant frequency of the resonant circuit including the inductance or the capacitances.
US11777433B2	Driver and method for low inductance motor A brushless DC motor system, includes a single coil brushless DC motor and a driver for driving the single coil brushless DC motor. The brushless DC motor system has a maximum time constant τmax. The driver comprises a control unit which is adapted for driving the brushless DC motor at a constant speed and at a variable speed by applying a PWM driving signal to the coil of the brushless DC motor with a PWM frequency larger than a ratio defined by a constant/τmax wherein the ratio is such that a current through the coil is always bigger than a pre-defined undercurrent limit.
US11777432B2	Process for disaggregating charges using an electrical signature A process for identifying the usage of electrical equipment connected to a power supply grid has an asynchronous motor coupled to a charge including identifying the usage of the electrical equipment by using an electrical signature of this equipment. The electrical signature is determined in a previous step and consists of a limited and predetermined set of characteristic frequencies and their harmonics obtained from the only information featuring on the identification plate of the asynchronous motor, and from visual inspection of the charge and its method for coupling to the asynchronous motor.
US11777430B2	Motor drive control device, motor unit, and motor drive control method A motor drive control device includes: a feedback control unit calculating an operation amount (Sad) of a motor such that a rotation speed S3 of the motor matches a target rotation speed S1; a drive control signal generation unit generating a drive control signal Sd based on the operation amount Sad; a current fluctuation detection unit detecting a fluctuation of a current flowing through the motor; a correction instruction unit instructing correction of the operation amount Sad when the fluctuation of the current flowing through the motor is detected by the current fluctuation detection unit; and a correction unit correcting the operation amount Sad and providing the corrected operation amount S2 to the drive control signal generation unit when the correction of the operation amount Sad is instructed from the correction instruction unit.
US11777429B2	Control device and failure determination method A failure phase of an AC current sensor is determined without providing a DC current sensor. A control device that controls a motor via an inverter circuit that supplies power converted from direct current to three-phase alternating current to the motor, in which a current sensor that detects alternating current of each phase of three-phase alternating current is provided at an output of the inverter circuit, and the control device calculates estimated DC current values by using a duty value of a PWM signal for controlling switching of the inverter circuit and an AC current value of two phases among three phases detected by the current sensor, and determines a failure of the current sensor on the basis of a change in the estimated DC current values that have been calculated.
US11777427B2	Motor control device and automatic adjustment method for same An estimated value of frequency of a vibration component for automatically adjusting a control unit that suppresses resonance characteristics of a machine is stably and reliably estimated without depending on the magnitude of amplitude of the vibration component and without risk of arithmetic overflow. A motor control device including an automatic adjustment device that adaptively adjusts a controller included in a motor control system based on a frequency of a vibration component superimposed on a response of the motor control system, the automatic adjustment device including a vibration extraction unit that receives the response of the motor control system and extracts the vibration component from the response of the motor control system; a notch filter unit that receives the vibration component from the vibration extraction unit; an encoding unit; a limiter unit that receives an output of the notch filter unit; an adaptive updating unit; and a unit conversion unit.
US11777424B2	Method for determining initial rotor position of permanent magnet synchronous motor according to phase current differences and line current differences and associated motor device A method for determining an initial rotor position of a permanent magnet synchronous motor (PMSM) includes: generating a plurality of transient currents by applying a plurality of voltages to each phase stator winding of a three phase stator winding of the PMSM; generating three phase current differences according to the plurality of transient currents; determining a first zone in which the initial rotor position of the PMSM is located according to the three phase current differences, wherein angles between 0-360 degrees are divided into a plurality of zones, and the first zone is selected from the plurality of zones; calculating three line current differences according to the three phase current differences; and determining the initial rotor position of the PMSM according to the first zone and the three line current differences.
US11777422B2	Multilayered microhydraulic actuators An actuator with a stack of thin layers operates by electrowetting droplets between the layers. The actuator includes a first layer structure and a second layer structure positioned adjacent to the first layer structure. One or more liquid droplets are pinned to one of the layers and are positioned between the layers. The other layer includes electrodes. When the electrodes are energized, they electrostatically attract the liquid droplets to create relative motion between the two layers.
US11777420B2	Submodule as a parallel serial full bridge for a modular multilevel converter A submodule for a modular multilevel converter has nine semiconductor switches that can be switched off, four capacitors, six network nodes, and two terminals. The components are mounted such that different voltages are generated between the terminals of the submodule by controlling the semiconductor switches. This arrangement of components substantially improves the behavior of the converter and of the submodule in the event of a fault.
US11777419B2	Semiconductor device, semiconductor device manufacturing method, and power converter A semiconductor device includes: a semiconductor substrate in which a cell region, an isolation region being a region which is located outward of the cell region, and a termination region including a guard ring region being located outward of the isolation region and an excess region being a region which is located outward of the guard ring region are defined; an insulating layer covering a top surface of the semiconductor substrate in the isolation region and the termination region; a surface electrode located on a portion of the top surface of the semiconductor substrate and a portion of a top surface of the insulating layer in the cell region and the isolation region; and a waterproof layer covering a portion of the insulating layer exposed from the surface electrode. The waterproof layer is spaced apart from the surface electrode.
US11777416B2	Flyback converter and output voltage acquisition method therefor and apparatus thereof A flyback converter and an output voltage acquisition method therefor and apparatus thereof, wherein the output voltage acquisition method comprises the following steps: acquiring the reference output voltage of a flyback converter; sampling the current output voltage of the flyback converter within a reset time of each switching period among M continuous switching periods of the flyback converter, wherein M is a positive integer; and according to the reference output voltage and the current output voltage, sampling a dichotomy to successively approximate the current output voltage until the M switching periods are finished, and acquiring the output voltage of the flyback converter.
US11777415B2	Synchronous rectification to mitigate rail pumping in a single-ended Class D amplifier An amplifier system may include at least one input source, a converter configured to provide voltage rails to an amplifier, the voltage rails including a first voltage rail and a second voltage rail, a MOSFET arranged at a secondary side of the system at the first voltage rail, a second MOSFET arranged at the first voltage rail, a third MOSFET arranged at the second voltage rail, a fourth MOSFET arranged at the second voltage rail; and, a first capacitor arranged at the first voltage rail and a second capacitor arranged at the second voltage rail, the first and forth MOSFETS are configured to operate simultaneously with one another and the second and third MOSFETs are configured to operate simultaneously with one another and opposite of the first and fourth MOSFETs so as to allow synchronous rectification so that the first and second capacitors reciprocally and mutually exclusively charge and discharge.
US11777412B2	Switching power supply apparatus for reducing common mode noise due to line-to-ground capacitances A switching power supply apparatus is provided with a switching circuit and an even number of transformers. The transformer are provided with: cores each having an identical shape; primary windings each having an identical arrangement around the cores, and each having first and second terminals; and secondary windings each having an identical arrangement around the cores, and each having third and fourth terminals. The primary windings of the transformers are connected so that when a current flows from the first terminal to the second terminal of a first transformer, a current flows from the second terminal to the first terminal of a second transformer. The secondary windings of the transformers are connected so that when a current flows from the third terminal to the fourth terminal of the first transformer, a current flows from the fourth terminal to the third terminal of the second transformer.
US11777408B2	Converter adaptable to wide range output voltage and control method thereof The invention discloses a converter adaptable to a wide range output voltage and a control method thereof. The converter comprises a PWM half-bridge circuit. The control method comprises the steps of: controlling the PWM half-bridge circuit to enter into a discontinuous conduction mode by regulating a switching frequency; when the PWM half-bridge circuit is operated in the discontinuous conduction mode, oscillation occurs among the output inductor, a magnetizing inductor of the transformer and a parasitic capacitor of the PWM half-bridge circuit, and when a center point voltage of the primary switching bridge arm reaches a valley or a peak, turning on the corresponding power switch. The invention reduces switching loss by controlling the corresponding power switch in the PWM half-bridge circuit to turn on when a voltage across the power switch is oscillated to valley.
US11777406B2	Multiphase switched mode power supply clocking circuits and related methods Multiphase switched mode power supply clock apparatus, systems, articles of manufacture, and related methods are disclosed. An example apparatus includes a first clock recovery circuit to in response to obtaining a first clock pulse, transmit the first clock pulse to a power converter to cause the power converter to switch based on the first clock pulse, in response to obtaining a second clock pulse after the first clock pulse re-transmit the second clock pulse to a second clock recovery circuit, and increment a count value, and in response to the count value meeting a phase selection value, reset the count value.
US11777402B2	Precharge system and method A precharge system and method are provided. The precharge system comprises a load circuit, a precharge circuit and a control circuit. The load circuit comprises an input terminal, an input switch and a bus capacitor. The precharge circuit comprises a precharge resistor and a precharge switch. The precharge method comprises: during the load circuit being in a precharge mode, controlling the input switch to be in an off state, and controlling the precharge switch to switch between the on and off state for multiple times; and during the load circuit being in a work mode, controlling the input switch to be in an on state. During the load circuit being in the precharge mode, when the precharge switch is in the on state, a consuming power of the precharge resistor is larger than a threshold power and is smaller than or equal to a limit power of the precharge resistor.
US11777400B2	Switching control in electrical load controllers Operating an electrical load controller includes, in one aspect, detecting zero-crossings of an AC waveform, determining periods each corresponding to a full cycle of the AC waveform, determining a frequency of the AC waveform based on the determined periods, and controlling a supply of AC power to a load based thereon using the determined frequency to fire a switching circuit of the electrical load controller. In another aspect, a method includes maintaining a minimum on-time for which a control signal to the switching circuit is to remain in an ON state to fire the switching circuit; based on a desired load level setting of the electrical load controller, setting a corresponding control signal turn-on time to turn the control signal to the ON state to conduct the supply of AC power to the load, the control signal turn-on time corresponding to a firing angle of half cycles of the AC power; selecting a control signal turn-off time to turn the control signal to the OFF state, where the selecting is made between (i) a first turn-off time equal to the set turn-on time plus the minimum on-time, and (ii) a second turn-off time equal to a default turn-off time for turning the control signal to the OFF state, the control signal turn-off time corresponding to a second angle of half cycles of the AC power; and controlling the supply of AC power to the load by selectively controlling the switching circuit to conduct the supply of AC power to the load, the controlling the supply of AC power to the load including: based on turning the control signal to the ON state during a half cycle of the AC power at the set control signal turn-on time, holding the control signal in the ON state until the selected control signal turn-off time during the half cycle.
US11777398B2	Pre-charging bootstrapped FET gate Circuitry for bootstrapping and precharging a gate of a field-effect transistor (FET) is disclosed. In one embodiment, an apparatus includes a first transistor coupled to a switching node and further coupled to receive a supply voltage from a supply voltage node, and a second transistor coupled between the switching node and a ground node, wherein the first and second transistors are of a same type. A precharge circuit is configured to precharge a gate terminal of the first transistor to a voltage that is less than a supply voltage on the voltage supply node. The apparatus also includes a bootstrap circuit. Subsequent to precharging the gate terminal of the first transistor, the bootstrap circuit is configured to cause activation of the first transistor by charging the gate terminal to a voltage greater than the supply voltage.
US11777394B1	Modular power supply architecture optimized for flat efficiency across loadings A control method improves the efficiency profile of a power supply across a wide range of output loading. The method includes obtaining a measure of output power for a power supply, which includes one or more output modules and an auxiliary power supply. The method determines whether a maximum power rating of the auxiliary power supply is sufficient to provide the measure of output power. Responsive to a determination that the maximum power rating of the auxiliary power supply is sufficient to provide the measure of output power, the controller of the power supply directs the auxiliary power supply to provide the output power.
US11777388B2	Transport system, mover, control apparatus, and control method A transport system includes: a mover having a first magnet group arranged in parallel to a first direction and a second magnet group arranged in parallel to a second direction crossing the first direction; and a plurality of coils arranged in parallel to the first direction so as to be able to face the first magnet group and the second magnet group, and the mover is able to move in the first direction along the plurality of coils by electromagnetic force received by the first magnetic group from the plurality of coils while an attitude of the mover is controlled by electromagnetic force received by the first magnetic group or the second magnetic group from the plurality of coils.
US11777386B2	System and method for an electric motor/generator with a multi-layer stator/rotor assembly Disclosed are various embodiments for a new and improved electric motor/generator including a toroidal magnetic cylinder centered on the longitudinal axis, and a coil assembly including a first coil assembly support positioned within the toroidal magnetic cylinder, and a second coil assembly support positioned within the toroidal magnetic cylinder.
US11777384B2	Electromagnetic machine using magnetic field binding of multiple multi-phase winding wires The present invention relates to an electromagnetic machine comprising: rotation shaft; a stator comprising a multi-phase winding wire; a mover (rotor 1) comprising the multi-phase winding wire and spaced apart from the stator at a preset interval; and a controller for independently controlling a first magnetic field of the stator and a second magnetic field of the mover (rotor 1). The electromagnetic machine according to the present invention can resolve, by means of the mover (rotor 1) and the wound-type stator that can be independently and actively controlled, a torque issue at start-up or when needed and, thereby, has the effects of producing a maximum driving torque while having a minimum size, and of maximizing efficiency.
US11777374B2	Integrated motor drive architecture A motor drive architecture is provided. The motor drive architecture includes a three-dimensional (3D) stack of cold plates on which power electronic components for an electric machine are mountable and supporting structures. Each cold plate has an annular shape with internal fluid pathways. The supporting structures hold the cold plates in the 3D stack. At least one supporting structure defines an internal cavity bifurcated into an internal inlet fluid pathway configured to direct fluid into the internal fluid pathways of each cold plate and an internal outlet fluid pathway receptive of the fluid from the internal fluid pathways of each cold plate.
US11777373B2	Method of efficient thermal management of rotor in a high power generator Disclosed is a rotor for a generator, having: a rotor body; rotor poles extending radially outward from the rotor body, wherein each rotor pole includes a pole body and opposing pole circumferential side surfaces that are spaced apart from each other in a circumferential direction about the rotor body; coil windings wound about the rotor poles to form a wire bundle against one of the pole circumferential side surfaces; and a wire separator, disposed within the wire bundle, that divides the coil windings within the wire bundle into subsets of wire bundles.
US11777355B2	Stator and electric rotating machine A stator to be provided in an electric rotating machine includes a stator core and a distributed winding coil. The stator core has a plurality of slots. The distributed winding coil includes a plurality of segment coils coupled to each other. Each of the segment coils is accommodated across a pair of slots out of the plurality of slots. The distributed winding coil has a coil structure including a plurality of parallel coils coupled to each other in series. Each of the parallel coils includes two or more of the segment coils. The two or more segment coils are coupled to each other in parallel and are accommodated across the same pair of slots out of the plurality of slots. The two or more segment coils included in each of the parallel coils are disposed adjacent to each other in a radial direction in the same pair of slots.
US11777352B2	Electrical machine An electrical machine for a vehicle may include a rotor, a stator, a coolant distributor chamber and a coolant collector chamber. The rotor may be configured to be rotated about an axis of rotation defining an axial direction of the electrical machine. The stator may include a plurality of stator windings. The coolant collector chamber may be axially arranged at a distance from the coolant distributor chamber. The coolant distributor chamber may be configured to communicate fluidically with the coolant collector chamber by at least one cooling channel through which a coolant can flow. At least one of the stator windings may be embedded in at least one plastic mass consisting of an electrically insulating plastic for thermal coupling to the coolant. At least one of the coolant distributor chamber and the coolant collector chamber may be arranged at least partially in the at least one plastic mass.
US11777348B2	Rotor core with load bearing polymer and insert A rotor core for an electric machine of an automobile includes a core stack including a plurality of lamination plates. Each lamination plate includes a plurality of apertures formed therein. The plurality of apertures of each of the lamination plates are axially aligned and define and a slot extending through the core stack and shaped to receive a corresponding insert. The rotor core also includes at least one insert received by the slot that provides radial structural stability to the plurality of lamination plates to prevent portions of the plurality of lamination plates adjacent the plurality of magnet slots from flexing due to radial forces exerted on the plurality of lamination plates during operation of the rotor core. The rotor core includes a load bearing polymer disposed within the aperture of the rotor core that provides contact between and the insert and the lamination plates.
US11777340B2	Charging case for electronic contact lens A contact lens charging case comprises a container sized and shaped to receive an electronic contact lens (“eCL”) and charging coil to couple to a coil of the eCL. In some embodiments, the charging coil comprises a diameter larger than a diameter of the coil of the eCL, so as to decrease sensitivity of the location and orientation of the eCL in the container and improve coupling between the coils. In some embodiments, the charging coil is dimensioned so as to extend at least partially around the container that receives the eCL.
US11777336B2	PV inverter apparatus with energy storage capability Systems and methods for providing AC power to a power grid using renewable energy sources as well as energy storage devices. A control system controls multiple DC/DC converters that are coupled to renewable energy sources as well as to one or more energy storage devices. The control system also controls the charge/discharge of the energy storage devices. Each DC/DC converter control block in the control system automatically detects whether to perform MPPT on the renewable energy source or to control the discharge of the energy storage devices. Each DC/DC converter control block ensures that power from the renewable energy source or from the energy storage device is converted and provided to the power grid.
US11777335B2	Systems and methods to harvest energy and determine water holdup using the magnetohydrodynamic principle Embodiments provide systems and methods for creating and storing energy using the magnetohydrodynamic principle and the flow of a conductive fluid through a magnetic field downhole in a pipeline system. The system can also be configured to determine water holdup using the magnetohydrodynamic principle. The energy the system generates can be used to control electric valves and other electronic devices along the pipeline. The power storing and generating system can be configured to include permanent magnets, electrode pairs, isolation material, and a conductive flowing multiphase media. The multiphase media, i.e., oil, gas, water, or a mixture, flows through a pipeline that has electrodes in direct contact with the media and magnets also configured adjacent the media. The electrode pairs can be arranged inside of the pipeline opposite each other, with a permanent magnet placed between the electrodes and flush to the inside of the pipe, with flux lines perpendicular to the flow direction. Power output from the system is a function of the conductive fluid volume, flow velocity, magnet strength, and electrode size. Various embodiments include different arrangements of permanent magnets and electrode pairs.
US11777332B2	Low-cost task specific device scheduling system A low-cost task specific device system for scheduling tasks that are performed by one or more devices is described. After a preceding task is performed, the performance of a successive task is delayed for a task-specific recharge interval associated with the preceding task. The successive task is performed after the task-specific recharge interval has expired.
US11777329B2	Method for controlling a charging or discharging current of a removable battery pack and/or an electrical device and system for carrying out the method A method controls a charging or discharging current of a removable battery pack and/or an electrical device, in particular a charging device, a diagnostic device or an electrical consumer, using a first monitoring unit integrated in the removable battery pack and a further monitoring unit integrated in the electrical device. The method includes monitoring a defined control potential of a signal or data contact between the removable battery pack and the electrical device using the further monitoring unit.
US11777326B2	Device for preventing overvoltage-induced damage caused by fault propagation in safety-relevant systems A device controls a safety-relevant electronic system and has a power supply. The power supply is supplied with a battery voltage at a first input terminal and supplies a first supply voltage at a first output terminal which is lower than the battery voltage. A microcontroller for generating a first control signal, provided at a first control output of the microcontroller for processing by way of a control unit, is supplied with the first supply voltage at a second input terminal. A monitoring unit for generating a second control signal, provided at a second control output of the monitoring unit for processing by the control unit, is supplied with the first supply voltage at a third supply potential input terminal. The third supply potential input terminal, the second control output and the second data port of the monitoring unit are configured to be voltage-proof with respect to the battery voltage.
US11777325B2	In-vehicle system and junction box An in-vehicle system is provided with a front J/B and a first voltage detection unit. The front J/B has a main relay unit, a second voltage detection unit, and a second MCU. Based on detection results detected by the first voltage detection unit and a second voltage detection unit when the main relay unit is subjected to on/off operations, the second MCU monitors whether each of the main relay unit, the first voltage detection unit, and the second voltage detection unit has abnormality or not.
US11777323B2	Sequential power discharge for batteries in a power system The battery pack of an EV is partitioned into multiple removeable and replaceable batteries to mitigate challenges associated with the power charging of battery in an EV. A set of control switches are linked in a control chain to control an orderly discharge of energy from the batteries disposed in the battery pack.
US11777321B1	Online estimation of POI-level aggregated inertia considering frequency spatial correlation An exemplary two-step method for power system inertia online estimation is described. The first step is to accurately estimate the POI-level aggregated inertia. The second step is to calculate the system-level inertia constant by weighting all the POI-level aggregated inertia and to monitor the inertia spatial distribution. In one example embodiment, the PMU is installed at POI, the frequency spatial difference is considered, and the mechanical power is carefully treated.
US11777312B2	Power distribution arrangement A power distribution arrangement for distributing AC power to loads requiring AC power is disclosed. The power distribution arrangement comprises a power distribution substation comprising transformers, switches, buses, and feeders, a DC transmission line, and at least one control unit. The control unit may control operation of the switches to selectively connect or disconnect one or more feeders to or from at least one transformer via one or more buses and to selectively connect or disconnect the DC transmission line to or from one or more feeders via at least one bus, whereby AC power is distributed to the loads via the feeders. The control unit may control operation of the switches based on: loading in and a power transfer rating of respective feeders and transformers, and any power transfer via the DC transmission line from the other power distribution substation to the at least one bus.
US11777308B2	Surge protection circuit, lightning protector and electronic device The present application provides a surge protection circuit, a lightning protector and an electronic device. The surge protection circuit includes a first protection module, the first protection module comprises a first protection sub-module and a second protection sub-module electrically connected to the first protection sub-module. The first protection sub-module is used for surge protection during a first surge input, the second protection sub-module is used for surge protection during a second surge input protection, and the second surge strength is higher than the strength of the first surge. The surge protection circuit, lightning protection and electronic equipment could provide different levels of surge protection for different levels of surge and could greatly enhance the sensitivity of lightning protection.
US11777307B2	Electronic valve apparatus An electronic valve apparatus for a high voltage direct current, HVDC, power transmission system. The electronic valve apparatus includes a first device chain including a number of first devices connected in series between an input node and an output node. Each of the first devices has an asymmetric transfer function configured substantially to block current flow through the device in a first direction, and the first devices are connected such that they all block current flow in the same direction. The electronic valve apparatus also includes a second device chain including a number of second devices connected in series between the input node and the output node. Each of the second devices has an asymmetric transfer function configured substantially to block current flow through the device in a first direction, and the second devices are connected such that they all block current flow in the same direction.
US11777306B2	Load control device for controlling energization of a load using a semiconductor switch A load control device includes an energization circuit unit connected between a power source and a load and configured to switch ON and OFF of energization of the load, a failure detection unit connected to a downstream side of the energization circuit unit, a current interruption unit connected to an upstream side of the energization circuit unit and configured to interrupt supply of current of the power source to the energization circuit unit based on an input from the failure detection unit, and a control unit configured to supply an ON-OFF control signal to the energization circuit unit. The energization circuit unit includes a first semiconductor switch and a second semiconductor switch which are connected in parallel to each other. The control unit supplies a common ON-OFF control signal to the first semiconductor switch and the second semiconductor switch.
US11777304B2	High voltage protection system A high voltage protection system for saddle type vehicle detects the short circuiting of any wire. The high voltage protection system provides three different modules: a high voltage protection circuit, a fault collection circuit, and a fault detection circuit, working together to detect the short circuiting or voltage spike and disconnect the vehicle loads from the power supply to prevent an accident.
US11777303B2	Leakage current based remote monitoring device and method for disconnector devices Disclosed is a leakage current measuring device for a grid protection system protecting a power distribution or transmission grid from damage in case of a power surge, the grid protection system including a disconnector device and a surge arrester connected in series along a grounding path, the grounding path connecting a phase of a power distribution or transmission grid through the surge arrester and the disconnector device to ground, the disconnector device being configured for being activated in case of an overload condition, thereby disconnecting the surge arrester. The leakage current measuring device includes a leakage current sensor for measuring a leakage current IL flowing along the grounding path, the leakage current IL being indicative of the electrical connection status of the disconnector device. The electrical connection status is one of an activated and an inactivated status of the disconnector device.
US11777302B2	Leakage current blocking circuit and leakage current blocking method for decoupling capacitor A leakage current blocking circuit and a leakage current blocking method for a decoupling capacitor are provided. A first end of the decoupling capacitor is coupled to a power voltage. The leakage current blocking circuit is coupled between a second end of the decoupling capacitor and a ground voltage, and the leakage current blocking circuit includes at least one switch. The at least one switch is used to provide a channel for the decoupling capacitor to be coupled to the ground voltage when the decoupling capacitor is not damaged, and when the decoupling capacitor is damaged, the at least one switch is turned off to block a leakage current of the decoupling capacitor.
US11777297B2	Cord reel including a polymeric sheath with a conductive EMI drain A cord reel cable including a polymeric sheath with a conductive EMI drain and a method of manufacture therefor. The cord reel includes a cable comprising power and data conductors, as wells as a single drain wire which is grounded to a cord reel housing or spool or the like. The drain wire contacts an outer ETFE layer surrounding the cable in order to provide EMI shielding to the cable.
US11777294B2	Multi-gang adjustable mud ring assemblies A mud ring assembly includes base member, raised member, telescoping member and plurality of drive members. The base member has a flange and an opening through the flange. The raised member extends from the base member and follows the opening in the flange to form a raised wall. The raised member has a plurality of mounting tabs extending from the raised wall toward the opening in the raised member. The telescoping member is positioned within the raised member opening and is movable relative to the raised member between a retracted position and an extended position. The telescoping member has a wall, an opening and a plurality of mounting tabs extending from the wall toward the opening in the telescoping member. Rotation of the drive members causes the telescoping member to move between the retracted position and the extended position.
US11777290B1	Plastic gang box with metal threaded nut attachment The plastic gang box with metal threaded nut attachment is a containment structure. The plastic gang box with metal threaded nut attachment forms a protection space. The protection space contains one or more electrical connections. The plastic gang box with metal threaded nut attachment comprises a gang box, and an insert structure. The gang box is formed from plastic. The insert structure inserts into the gang box. The insert structure is a metal device that is formed with an interior screw thread. The insert structure provides a more durable threaded connection than is available with a traditional plastic gang box.
US11777289B2	Delivery device for rooftop equipment and systems and method of installation Rooftop device for delivering electrical power, plumbing, lines and other systems from the inside of a building to the outside of the building to equipment and systems installed on the rooftop. The device comprises a powder coated white NEMA 4 enclosure to reduce corrosion and minimize the effects of heat buildup in the enclosures during high temperature exposure. A GFCI circuit breaker in the enclosures allows electricians to move electrical power from the closes source, which reduces installation costs. The device comprises MCB or MCP disconnect switches which will provide faster and more precise protection to equipment and the circuits that supply them, and ethernet cable, coaxial cable, conductor thermostat wire. A mounting assembly, comprising a flashing and a cleat, and a vice assembly cooperate to apply pressure from the outside of the rooftop and from the inside of the roof, providing a more secure, dryer fit for roof penetrations.
US11777288B1	Snap in zip connector A snap-in zip connector with a clamp for gripping a wire between a first bracket and a second bracket. The first bracket includes a clamp seat and a first fastener opening formed by an elongated slot and hole joined together and extending through the clamp seat. The second bracket includes a fastener opening that aligns with the hole. An insert positioned in the elongated slot includes a spring arm extending into the circular hole extend into the circular hole that engages a threaded shaft of the fastener to restrict removal except through rotation of the at least one fastener.
US11777287B1	Cable tray having cover panels A cable tray cover for a substantially U-shaped cable tray having a base portion and two opposing sidewalls extending upward generally perpendicular to base portion. The cover includes a plurality of interlocking cover panels for covering cable carried by the cable tray, with each cover panel having a top side, with a first end and a second end, with each cover panel configured to extend transverse across the tray. The first end of each cover panel includes a hinge point to allow the second end of the cover panel to rotate and overlap the second end of an adjacent cover panel for use in a radius section of the cable tray. The cover panels may include a hinge slot and a hinge tab, wherein the hinge tab of a cover panel may be placed through the hinge slot of an adjacent cover panel to form the hinge point.
US11777283B2	System and method for an inland pipeline control station A system and method for a modular inland pipeline valve control station includes a control valve, a control enclosure, a flow instrument, and a piping spool connected to a pipeline. The modular inland pipeline valve station is transportable and controlled from a central control location. The modular inland pipeline valve station is constructed, assembled, tested, and commissioned with the center control center at a module yard prior to being transported and installed at the pipeline. The modules can be installed slightly offset to the pipeline with drop-out or curved rotatable spools to allow possible access to the pipeline for testing and inspection and for connecting a pig receiver, pig launcher or a bypass.
US11777279B2	Laser architectures using quantum well intermixing techniques A laser chip including a plurality of stripes is disclosed, where a laser stripe can be grown with an initial optical gain profile, and its optical gain profile can be shifted by using an intermixing process. In this manner, multiple laser stripes can be formed on the same laser chip from the same epitaxial wafer, where at least one laser stripe can have an optical gain profile shifted relative to another laser stripe. For example, each laser stripe can have a shifted optical gain profile relative to its neighboring laser stripe, thereby each laser stripe can emit light with a different range of wavelengths. The laser chip can emit light across a wide range of wavelengths. Examples of the disclosure further includes different regions of a given laser stripe having different intermixing amounts.
US11777276B2	Semiconductor light emitting array with phase modulation regions for generating beam projection patterns The present embodiment relates to a single semiconductor light-emitting element including a plurality of light-emitting portions each of which is capable of generating light of a desired beam projection pattern and a method for manufacturing the semiconductor light-emitting element. In the semiconductor light-emitting element, an active layer and a phase modulation layer are formed on a common substrate layer, and the phase modulation layer includes at least a plurality of phase modulation regions arranged along the common substrate layer. The plurality of phase modulation regions are obtained by separating the phase modulation layer into a plurality of places after manufacturing the phase modulation layer, and as a result, the semiconductor light-emitting element provided with a plurality of light-emitting portions that have been accurately aligned can be obtained through a simple manufacturing process as compared with the related art.
US11777274B2	Semiconductor optical device and method for manufacturing the same A semiconductor optical device includes a substrate including a waveguide made of silicon and a semiconductor layer joined to the substrate so as to overlap the waveguide and including a diffraction grating formed of a first semiconductor layer and a second semiconductor layer having different refractive indices. The waveguide includes a bent portion and a plurality of straight portions that are connected to each other by the bent portion and that extend straight. The first semiconductor layer and the second semiconductor layer are each made of a compound semiconductor. The second semiconductor layer is embedded in the first semiconductor layer and includes a plurality of portions arranged in a direction in which the plurality of straight portions extend. The diffraction grating is positioned above the plurality of straight portions.
US11777273B2	Femtosecond pulse stretching fiber oscillator A pulse stretching fiber oscillator (or laser cavity) may comprise a chirped fiber Bragg grating (CFBG) and an optical circulator arranged such that a first portion of a beam that is transmitted through the CFBG continues to propagate through the laser cavity while a second portion of the beam that is reflected from the CFBG is stretched and chirped by the CFBG and directed out of the laser cavity by the optical circulator. Accordingly, a configuration of the CFBG and the optical circulator in the laser cavity may enable pulse stretching contemporaneous with outcoupling, which may prevent deleterious nonlinear phase from accumulating prior to stretching.
US11777270B2	Dieless utility crimper Embodiments of the invention provide a crimper for use in a tool. The crimper can include a clevis, a nest, and an indenter. The clevis can include a first leg having a first slot and a second leg having a second slot. The first leg and the second leg can extend from a cylindrical body that has a base surface. The indenter can be configured to be moved from a retracted position to an extended position. The indenter can include a body with a work surface and a base on opposing sides of the body. The base of the indenter can be configured to engage the base surface of the cylindrical body when the indenter is in the retracted position.
US11777269B2	Connection body of high-temperature superconducting wire materials and connecting method Provided is a connection body of high-temperature superconducting wire materials including a first oxide high-temperature superconducting wire material and a second oxide high-temperature superconducting wire material, characterized in that a first superconducting layer of the first oxide high-temperature superconducting wire material and a second superconducting layer of the second oxide high-temperature superconducting wire material are bonded together via a junction including M-Cu—O (wherein M is a single metal element or a plurality of metal elements included in the first superconducting layer or the second superconducting layer). The connection body may be, for example, a connection body of Bi2223 wire materials, and the junction may include CaCuO2.
US11777265B2	Shielded Y-shaped splice connector and his method of assembly The disclosure relates to a shielded Y-shaped splice connector having a housing that includes a lower body, an upper cover, and three openings arranged to receive three cable fixing devices on the housing. The periphery of the lower body and the periphery of the upper cover are each formed of a flat surface arranged to form the contact surface of the lower body and the upper cover when the housing is assembled.
US11777260B2	Charging socket and lead frame assembly and charging socket The present invention discloses a charging socket lead frame assembly and a charging socket. The charging socket lead frame assembly has a lead frame which has a frame body and an electrical connection structure arranged in the frame body. The lead frame is adapted to be installed in a cavity of a charging socket, and a plurality of terminals of the charging socket are adapted to pass through the frame body. One end of the electrical connection structure is exposed from the frame body to electrically connect with a lead of a temperature sensor. The lead frame is arranged in non-electrical contact with at least one signal terminal of the charging socket. Therefore, the structure of the lead frame can be simplified and the manufacturing difficulty and cost can be reduced.
US11777255B1	Power distribution unit, power outlet modules with secure socket-and-plug connection A power distribution unit includes a housing; a plurality of power outlet modules accommodated in the housing, at least one of the power outlet modules including a socket having at least three electrical terminals which are configured to connect with one power cord plug of various types of power cord plugs, including a C14 plug and a C20 plug, and a sliding cover having a central opening, the sliding cover being slidable on an outer casing of the socket and engageable with the power cord plug when the power cord plug is completely inserted into the socket, thereby providing a secure connection between the socket and the power cord plug; and at least one power input module providing power to the power outlet modules.
US11777246B2	Electrical pop out device An electrical pop out device has an shroud and a pop out housing configured to be inside the shroud in a retracted position and to extend outside the shroud in an extended position. A guidance mechanism connects the pop out housing with the shroud and allows movement of the pop out housing with respect to the shroud between a retracted position and an extended position. The electrical pop out device includes an electrical connection for powering an electrical/electronic device in the pop out housing and/or charging a battery of the electrical/electronic device in the pop out housing. The electrical pop out device may also include audio, video and/or data connections for the electrical/electronic device in the pop out housing. In some embodiments, the electrical/electronic device is portable and the pop out housing is detachable from the shroud.
US11777243B2	Connector receptacle with improved mating retention and release A connector receptacle for connecting with a corresponding connector plug coupled with electrodes being used for performing EMG procedure on a patient is provided. The receptacle includes a first ball bearing pressing against a first end of a housing of the plug and, preferably, a second ball bearing pressing against a first end of the housing of the plug when the plug is connected to the receptacle for exerting a retention force against the plug. The first and the second ball bearings are pressed against the first and the second ends respectively by using a spring force generated, for example, by a retention band.
US11777238B2	Receptacle assembly, interface card, and electronic device having the same A receptacle assembly is configured to be disposed on a circuit board and to receive a pluggable module and includes a cage member and a connector. The cage member includes a housing portion and at least one fin portion. The housing portion defines an accommodation space and an insertion hole in fluid communication with the accommodation space. The insertion hole is located at one end of the accommodation space. The fin portion is integrally formed with the housing portion and extends outwardly from an outer surface of the housing portion. The connector is located at another end of the accommodation space. The insertion hole is configured for an insertion of the pluggable module into the accommodation space and the connector is configured to be electrically connected to the pluggable module.
US11777236B2	Distribution block A distribution block for attaching to a support rail extending in a support direction comprises an insulating housing, and a conductive member arranged in the insulating housing. A mounting assembly of the distribution block is connected to the insulating housing for attaching to the support rail. The distribution block is mountable on the support rail in a longitudinal configuration wherein the extension direction of the insulating housing is substantially parallel to the support direction, and in a transverse configuration wherein the extension direction of the insulating housing is transverse to the support direction.
US11777233B2	Conductor connection terminal A conductor connection terminal having an insulating material housing that includes a conductor insertion opening having a conductor insertion channel attached to the conductor insertion opening and a contact pin insertion opening having a contact pin insertion channel attached to the contact pin insertion opening. The conductor connection terminal also has a busbar and a clamping spring. The busbar includes a first contact portion and a second contact portion and the clamping spring has a first clamping limb having a first clamping edge oriented towards the first contact portion of the busbar, a first spring bow, a bearing limb, a second spring bow and a second clamping limb.
US11777230B2	Antenna device, system, and transmission/reception method According to one embodiment, an antenna device comprises an antenna panel including a first transmission antenna, a first reception antenna, and a second reception antenna, and a rotation device configured to rotate the antenna panel. A first radio wave is irradiated from the first transmission antenna when a rotation angle of the antenna panel is a first angle and a reflected radio wave of the first radio wave is received by the first reception antenna and the second reception antenna. A second radio wave is irradiated from the first transmission antenna when the rotation angle is a second angle and a reflected radio wave of the second radio wave is received by the first reception antenna and the second reception antenna.
US11777229B2	Antennas including multi-resonance cross-dipole radiating elements and related radiating elements Radiating elements include a first dipole radiator that extends along a first axis, the first dipole radiator including a first pair of dipole arms that are configured to resonate at a first frequency and a second pair of dipole arms that are configured to resonate at a second frequency that is different than the first frequency. Each dipole arm in the first pair of dipole arms comprises a plurality of widened sections that are connected by intervening narrowed sections.
US11777225B2	Electromagnetic wave reflecting structure and manufacturing method thereof A method of manufacturing an electromagnetic wave reflecting structure includes the steps of presetting an operating frequency, a reflected wave pointing angle, an incident wave pointing angle, and an incident distance of an electromagnetic wave; obtaining an electromagnetic wave reflecting structure phase distribution of an electromagnetic wave reflecting structure according to the operating frequency, the reflected wave pointing angle, the incident wave pointing angle, and the incident distance; and arranging a plurality of reflecting elements on a substrate according to the electromagnetic wave reflecting structure phase distribution and a reflecting element phase curve of any one of the reflecting elements at the operating frequency.
US11777223B2	Meandered slotted waveguide for a leaky wave antenna, and a leaky wave antenna A waveguide 200 for a leaky wave antenna 20 is described. The waveguide 200 comprises a male member 210 (210A-210T) and a corresponding female member 220 (220A-220T) arranged to receive the male member 210 (210A-210T) therein. The waveguide is arrangeable in a first configuration and a second configuration. The male member 210 (210A-210T) is received in the female member 220 (220A-220T) spaced apart therefrom in the first configuration and the second configuration. The first configuration defines a first effective delay line. The second configuration defines a second effective delay line. The first effective delay line is different from the second effective delay line. The leaky wave antenna 20 is also described.
US11777221B2	Antenna module A plurality of multi-band antenna elements operable at a plurality of frequencies constitutes an array antenna. An antenna drive unit selects at least some of the multi-band antenna elements from the plurality of multi-band antenna elements in accordance with one operation frequency selected from the plurality of operation frequencies, and causes the selected multi-band antenna elements to operate.
US11777220B2	Light path defining apparatus and methods An apparatus includes a horn having a horn body including at least one horn sidewall defining a first opening that tapers down to a second opening in a direction of elongation and a port that is tubular and dimensionally uniform transverse to the direction of elongation and extends in the direction of elongation from a first port end that is in communication with the second opening to a second port end that defines an external opening. A dielectric rod includes a rod length extending between a first rod end and a second rod end with the first rod end extending through the external opening of the second port end and into the port cavity such that the first rod end is in a spaced apart relationship from the port sidewall along the light path.
US11777213B2	Radio frequency (RF) amplifier circuit for antenna systems having a modal antenna An antenna system is provided. The antenna system includes a modal antenna disposed on a circuit board. The modal antenna includes a driven element and a parasitic element. The modal antenna is operable in a plurality of different modes. Each of the plurality of modes has a distinct radiation pattern. The antenna system further includes a radio frequency amplifier circuit disposed on the circuit board. The radio frequency amplifier circuit is coupled between the drive element of the modal antenna and a transmission line.
US11777208B2	E-fuse switched-delay path phased array A phase shifter element includes: a first signal path and a second signal path extending in parallel between an input node of the phase shifter element and an output node of the phase shifter element; at least one first signal path e-fuse in the first signal path; and at least one second signal path e-fuse in the second signal path. The phase shifter element is programmable to select one of the first signal path and the second signal path. The phase shifter element has a first phase shift when the first signal path is selected and a second phase shift, different than the first phase shift, when the second signal path is selected.
US11777207B2	Virtual phased-array for coherent, distributed, and dynamic applications A virtual phased-array and associated methods are disclosed for coherent transmission and/or reception of radio signals among antenna elements of the array, where the antenna elements are wirelessly interconnected and one or more of the elements may be moving. In one embodiment, clocks of the antenna elements are synchronized based on a first set of measurements of wireless signal(s) transmitted by one or more of the antenna elements. Relative positions and orientations of the antenna elements are determined based on a second set of measurements of wireless signal(s) transmitted after the synchronizing of the clocks. Weight(s) of a manifold vector are determined based on the relative positions and orientations, to calibrate the manifold vector. A plurality of coherent wireless signals are transmitted via two or more of the antenna elements based on the calibrated manifold vector.
US11777203B2	Asymmetrically constructed radome An asymmetrically constructed radome for an aircraft and an aircraft having an antenna and a corresponding radome are described. The radome has a first layer with a first dielectric constant and a first layer thickness, and a second layer with a second dielectric constant and a second layer thickness. The first layer thickness and the second layer thickness are different from each other. The first layer includes a thermosetting material and the second layer includes a thermoplastic material. Such an asymmetrical radome structure improves the mechanical stability and electromagnetic transparency of the radome.
US11777194B2	Coil-driven near field communications antenna A communication device includes a conductive chassis, an electrical feed positioned within the conductive chassis and configured to supply a communication signal, an edge antenna at least partially formed in the conductive chassis at an edge of the communication device, and a conductive coil positioned within the conductive chassis in proximity to the edge antenna. The conductive coil is configured to receive the communication signal from the electrical feed and to generate a magnetic field corresponding to the communication signal that inductively drives the edge antenna to radiate a radio frequency signal corresponding to the communication signal.
US11777187B2	Reconfigurable quadrature coupler A method of operating a reconfigurable quadrature coupler is disclosed. The method includes determining a first switchable impedance to provide a second port reflection coefficient by operating a coupled port transformer, which coupled port transformer is coupled to a second port having a coupled port transmission line connected to a first transistor; determining a second switchable impedance to provide a third port reflection coefficient by operating an isolation port transformer, which isolation port transformer is coupled to a third port having an isolation port transmission line connected to a second transistor; and determining a fourth switchable impedance to provide a fourth port reflection coefficient by operating a through port transformer, which through port transformer is coupled to a fourth port having a through port transmission line connected to a third transistor, and switching on or off selected ones of the first, second, and third transistors by operating a controller.
US11777179B2	Electrode assembly, secondary battery including same, and method for manufacturing same The present invention provides an electrode assembly, which can reduce resistance and improve a process property, a secondary battery including same, and a method for manufacturing same. For example, disclosed is an electrode assembly comprising: a first electrode plate having a first electrode tab attached thereto: a plurality of second electrode plates having second electrode tabs attached thereto, respectively, and a separator interposed between the first electrode plate and the plurality of second electrode plates, wherein the first electrode plate, the separator, and the plurality of second electrode plates are wound in a state of being stacked on one another, and the second electrode tabs are formed to be symmetrical to each other on the basis of a winding center thereof.
US11777178B2	Battery module, vehicle provided with same, and bus bar A battery module includes a plurality of battery cells each including an electrode terminal, and a bus bar that connects respective electrode terminals of adjacent battery cells in a state where the plurality of battery cells are stacked, wherein the bus bar includes a first bus bar having a first thickness, and a second bus bar having a second thickness larger than the first thickness, the first bus bar is connected to the respective electrode terminals of the adjacent battery cells, and the second bus bar is in non-contact with electrode terminals of the battery cells.
US11777171B2	Buckling structure for a battery of a handheld power tool A buckling structure for a battery of a handheld power tool includes a horizontal opening end formed at a handheld seat of the power tool, a buckling structure arranged on top of a battery base and configured to mutually guide, insert and buckle into the opening end to be integrally attached thereto, the buckling structure comprising: a guiding slot formed at a front side surface of the battery base, two receiving slots formed at two sides of the guiding slot respectively, a pressing member arranged inside the guiding slot and two buckling members arranged inside the receiving slot respectively, and an elastic element connected to the pressing member and each of the buckling members respectively, thereby achieving an assembly and buckling structure having single direction movement and stable, durable structure that is convenient to use and operation.
US11777166B2	Multi-gear brightness adjustment circuit board, multi-gear battery holder structure, and multi-gear brightness adjustment assembly A multi-gear brightness adjustment circuit board, and a multi-gear battery holder structure, which through adding the automatic control gear AUTO conductive contact piece and a light spot dot-circle pattern composite conductive contact piece on the circuit board, the gear can be automatically adjusted when the solar cell is used for power supply. Ensuring that the output light power meets the needs of ambient light, rationally use electric energy, which is conducive to energy saving; at the same time, the mode switching of the shooting target is integrated, which reduces the parts of the sight and makes the sight more compact.
US11777165B2	Battery A battery includes a metal battery can that has a tubular portion having an opening edge portion and a bottom portion; an electrode body that is in the battery can; an electrolytic solution that fills the battery can; and a sealing member that has an outer peripheral surface facing an inner peripheral surface of the opening edge portion of the tubular portion and is configured to seal the opening edge portion. A part of the inner peripheral surface of the opening edge portion and a part of the outer peripheral surface of the sealing member are joined by a melting portion, and a preventing portion is on the outer peripheral surface of the sealing member, the preventing portion being configured to prevent the electrolytic solution from rising toward a position, in which the melting portion is formed.
US11777163B2	Battery cell To reduce influence of external force on a current collection tab lead and a current collection tab in a laminated cell type battery. A single film of an exterior body contacts and covers a top surface, a bottom surface, and two side surfaces of a battery perpendicular to an end surface of the battery from which a current collection tab and a current collection tab lead are provided to extend, covers the end surface of the battery from which the current collection tab and the current collection tab lead protrude, and is folded in from both short sides of the end surface such that triangular pyramid-shaped spaces are formed on both sides. A reinforcement member is arranged in and joined to each triangular pyramid-shaped space.
US11777161B2	Pouch exterior material for lithium secondary battery and lithium secondary battery including same The present invention relates to a pouch exterior material which is for a lithium secondary battery and includes an inner layer, an outer resin layer, and a metal layer located between the inner layer and the outer resin layer, wherein the inner layer contains an ethylenically unsaturated group, and a lithium secondary battery including the pouch exterior material.
US11777160B2	Electric vehicle battery coolant heater assembly with electrical connection through gasket A battery coolant heater assembly including a coolant manifold having liquid coolant pathways and a heat transfer surface for transferring heat to liquid coolant flowable within the coolant manifold, an electric heater element thermally contacted to the heat transfer surface of the manifold, and a cover sealably enclosing the heating element between the heat transfer surface and the cover via a gasket. The electric heater element is electrically connected via an electrical connector extending through and formed integrally with the gasket.
US11777157B2	Battery module Disclosed is a battery module including a module housing capable of effectively increasing an energy density while improving the heat dissipation efficiency. The battery module includes a cell assembly having a plurality of secondary batteries; and a module housing having at least one sidewall to accommodate the cell assembly in an inner space defined by the sidewall and having a cooling channel embedded in the sidewall.
US11777156B2	Method for recovering and recycling electrolyte salts from lithium batteries A method for recovering a lithium electrolyte salt from spent batteries comprises first extracting electrolyte from shredded batteries (e.g., spent batteries at the end of their useful lifetime) with an organic carbonate solvent; concentrating the extracted electrolyte in vacuo to form a solid lithium electrolyte salt that is solvated with the organic carbonate; and then extracting solvent from the solvated, solid lithium electrolyte salt with supercritical CO2 to purify the lithium electrolyte salt sufficiently for reuse in lithium batteries. In the first extraction, the organic carbonate solvent is selected based on the solubility of the lithium electrolyte salt in the solvent, as well as the volatility of the solvent to facilitate the concentration process. The supercritical CO2 is preferably held at a pressure in the range of about 1,500 to about 30,000 psi and is passed through a bed or column of the solvated salt.
US11777155B2	Battery pack Embodiments of the invention provide a battery pack including a pack body and a plurality of terminals. The pack body has first and second main surfaces that are opposed to each other in a first axis direction, first and second end surfaces that are opposed to each other in a second axis direction orthogonal to the first axis direction, and first and second side surfaces that are opposed to each other in a third axis direction orthogonal to the first axis direction and the second axis direction. The plurality of terminals includes a positive terminal, a negative terminal, a temperature detection terminal, and a control terminal that are arranged on the first end surface along the third axis direction. The negative terminal is arranged between the temperature detection terminal and the control terminal and closer to the control terminal than the temperature detection terminal.
US11777154B2	Battery management systems and methods, and open cell detection systems An open cell detection system includes a battery management system. The battery management system includes a control unit that transmits an open cell detection signal, to enable a balance unit for a first time period and to disable it for a second time period, and to enable an under-voltage comparison unit and an over-voltage comparison unit for a third time period. The under-voltage comparison unit compares a voltage with a first open cell threshold and outputs a first comparison result in the third time period. The over-voltage comparison unit compares a voltage with a second open cell threshold and outputs a second comparison result in the third time period. A judging unit determines whether a connection between a first battery unit and the battery management system is inoperative based on the first and second comparison results.
US11777153B2	Thermal and electrical management of battery packs Provided are battery packs and interface modules for electrically interconnecting electrochemical cells in the packs and for providing heat distribution with the packs. An interface module interfaces one side of all electrochemical cells in a battery pack. The interface module may have a substantially planar shape such that the space occupied by the module in the battery pack is minimal. Most, if not all, conductive components of the interface module may be formed from the same sheet of metal. In some embodiments, the interface module includes multiple bus bars such that each bus bar interconnects two or more terminals of different electrochemical cells in the battery pack. Each bus bar may have a separate voltage sense lead extending from the bus bar to a connecting portion. The bus bars may be flexibly supported within the module. The interface module may also include multiple thermistors disposed on different bus bars.
US11777151B2	Arrangements for inhibiting intrusion into battery pack electrical components A battery pack and a method of assembling a battery pack. The battery pack may include an outer housing; a cell module supportable by the outer housing, the cell module including a module housing, a plurality of battery cells supported by the module housing, the battery cells having an energy of at least about 60. Watt-hours, a controller operable to control an operation of the battery pack, a conductive strap electrically connected to at least one of the battery cells, a weld strap connected between the controller and the conductive strap, and a terminal electrically connected to the battery cells and operable to connect the battery cells to an electrical device for power transfer; and a vapor-deposited, hydrophobic nano coating applied to at least a portion of the cell module.
US11777150B2	Battery module A battery module includes a set of power contacts, a set of signal contacts and a battery pack operable to deliver electrical power to the set of power contacts. An electronic isolation system is operable to electrically disconnect and connect the battery pack and the set of power contacts. An electronic control system is electrically connected to the electronic isolation system and to one of the set of signal contacts or the set of power contacts. The electronic control system is operable to measure a parameter associated with one of the battery module and an electrical device and to compare the parameter to a predefined value. The electronic isolation system connects the battery pack to the set of power contacts based on a positive result of the comparison, and disconnects the battery pack and the set of power contacts based on a negative result of the comparison.
US11777149B2	Stackable battery bussing system A stackable electrical-energy bussing system, for energy storage battery cells constructed according to the present invention includes a battery cell case having electrically conductive terminals that fit together with the terminals of a similar battery cell in order to enable multiple battery cells to be interconnected physically and electrically by stacking them atop each other. A Stackbatt bussing system housing contains the electricity-producing elements for each cell, connected from each opposing side. Preferably, the battery cell includes at least two such male terminals in spaced-apart relationship on the top side of the cell case, and at least two such female bus tubes that mate and receive with a spaced-apart relationship on both sides of the Stackbatt bussing system. Preferably, a multi-cell battery bussing system constructed to the invention includes multiple battery cells as described above, stacked when desired to achieve desired battery voltage for series and or parallel configurations.
US11777145B2	Gel composite cathode for solid-state batteries and methods of manufacturing thereof A battery includes a substrate; a composite cathode disposed on the substrate; a solid-state electrolyte disposed on the composite cathode; and a lithium anode disposed on the solid-state electrolyte, such that the composite cathode comprises a gel polymer electrolyte layer and a porous cathode active material layer. A method of forming a cathode for a solid-state battery includes mixing an active cathode material, at least one of a conductive carbon component and an electronic conductive component, and a polymer binder to form a slurry; immersing the slurry in an alcohol reagent to form a porous disc structure by phase conversion; and immersing the porous disc structure in a liquid electrolyte to form the cathode.
US11777144B2	Secondary battery A secondary battery includes: a first electrode configured to function as a p-type semiconductor; a second electrode configured to function as an n-type semiconductor; and a solid electrolyte provided between the first electrode and the second electrode, the solid electrolyte contains a compound and polyethylene oxide, the compound has a perovskite structure.
US11777143B2	Solid electrolyte, electrode, power storage device, and method for producing solid electrolytes A solid electrolyte of the present disclosure includes: a porous dielectric having a plurality of pores interconnected mutually; and an electrolyte including a metal salt and at least one selected from the group consisting of an ionic compound and a bipolar compound and at least partially filling an interior of the plurality of pores. Inner surfaces of the plurality of pores of the porous dielectric are at least partially modified by a functional group containing a halogen atom.
US11777137B2	Member for electrochemical devices, and electrochemical device Disclosed is a member for electrochemical devices comprising a current collector, an electrode mixture layer provided on the current collector, and an electrolyte layer provided on the electrode mixture layer in this order, wherein the electrode mixture layer comprises an electrode active material, a polymer having a structural unit represented by the following formula (1), at least one electrolyte salt selected from the group consisting of lithium salts, sodium salts, calcium salts, and magnesium salts, and a molten salt having a melting point of 250° C. or less, and the electrolyte layer comprises an inorganic solid electrolyte: wherein X− represents a counter anion.
US11777135B2	3D magnesium battery and method of making the same 3-D magnesium voltaic cells have a magnesium anode coated on multiple opposing surfaces with a continuous protective/electrolyte layer that is ionically conductive and electronically insulating. The resulting protected 3-D magnesium anode is coated on multiple opposing surfaces with a continuous cathode layer that is electronically and ionically conductive, and includes a magnesium storage medium. Suitable magnesium anodes, in particular, magnesium foam anodes, can be made by pulsed galvanostatic deposition of magnesium on a copper substrate. The protective layer can be formed by electropolymerization of a suitable methylacrylate ester. The continuous cathode layer can be a slurry cathode having powders of an electronic conductor and a reversible magnesium storage component suspended in a magnesium electrolyte solution.
US11777134B2	Secondary battery and device including the same The application provides a secondary battery and a device including the same. The second battery includes: a negative electrode plate, the negative electrode plate including a negative active material; a separation film, the separation film including a base material and a coating arranged on at least one surface of the base material; and an electrolyte, the electrolyte including an organic solvent, where the negative active material includes a silicon-based material and a carbon material; thickness of the base material of the separation film is 7 μm˜12 μm; and the organic solvent includes ethylene carbonate, and a weight ratio of the ethylene carbonate in the organic solvent is ≤20%. The secondary battery and the device including the same, which are provided by the application, in the premise of having high energy density, can also have good high-temperature cycle performance, good high-temperature storage performance, and low low-temperature direct current resistance.
US11777132B2	Solid electrolyte material and battery A solid electrolyte material includes a first crystal phase. The first crystal phase has a composition that is deficient in Li as compared with a composition represented by the following composition formula (1). Li3Y1Br6 formula (1)
US11777126B2	Methods of making and using an oxide ion conducting membrane Herein discussed is a method of using an oxide ion conducting membrane comprising exposing the oxide ion conducting membrane to a reducing environment on both sides of the membrane. In an embodiment, the oxide ion conducting membrane also conducts electrons. In various embodiments, the membrane is impermeable to fluid flow (e.g., having a permeability of less than 1 micro darcy). In an embodiment, the oxide ion conducting membrane comprises lanthanum chromite and a material selected from the group consisting of doped ceria, yttria-stabilized zirconia (YSZ), lanthanum strontium gallate magnesite (LSGM), scandia-stabilized zirconia (SSZ), Sc and Ce doped zirconia, and combinations thereof. In an embodiment, the lanthanum chromite comprises undoped lanthanum chromite, strontium doped lanthanum chromite, iron doped lanthanum chromite, strontium and iron doped lanthanum chromite, lanthanum calcium chromite, or combinations thereof. In an embodiment, the membrane is mixed conducting.
US11777125B2	Solid oxide fuel cell system with hydrogen pumping cell with carbon monoxide tolerant anodes and integrated shift reactor A fuel cell system includes at least one of plural electrochemical pump separators to separate carbon dioxide from a fuel exhaust stream or a combination of a gas separator and a fuel exhaust cooler located outside a hotbox.
US11777124B2	Proton-conducting PBI membrane processing with enhanced performance and durability The current disclosure teaches one to achieve PBI membranes with high ionic conductivity and low mechanical creep for the first time. This is in contrast to previous teachings of PBI membrane fabrication methods, which yield PBIs with either high ionic conductivity and high mechanical creep or low ionic conductivity and low mechanical creep. The membranes produced according to the disclosed process provide doped membranes for applications in fuel cells and electrolysis devices such as electrochemical separation devices.
US11777123B2	Direct alcohol fuel cell A direct alcohol fuel cell having a proton exchange membrane (PEM) separating an anode section from a cathode section, which cathode section contains a cathode collection element electrically connected to a cathode catalyst, the cathode catalyst being in diffusive communication with a gaseous oxidant, and which anode section comprises an anode collection element electrically connected to an anode catalyst. The anode catalyst is in diffusive communication with a fuel supply. The PEM is structured to have a bottom and walls extending from the bottom to a containment distance into the cathode section, and the cathode catalyst is located within the containment distance from the bottom. The fuel cell is suited for a microelectronic device.
US11777122B2	Hydrogen generator with carbon capture for use with a hydrogen fuel cell A hydrogen generator includes a gasifier, upon receiving steam and methane, configured to convert the methane and steam into hydrogen and carbon monoxide; and a carbon trap, operatively connected to the gasifier, configured to capture carbon from the carbon monoxide and allow the hydrogen to pass therethrough. The carbon trap includes iron and a heat source.
US11777121B2	Power system, vehicle, vehicular power control method, and control method for power system A power system comprises a fuel cell system having a fuel cell stack and a fuel cell water pump, a heat source having a heat source water pump and configured to be actuated to generate heat, a heat radiator for exchanging heat with the atmosphere, a cooling passage thermally connecting the fuel cell system, the heat source, and the heat radiator, and a controller for controlling the fuel cell system, the heat source, and the heat radiator, and the cooling passage.
US11777118B2	Method of controlling start/stop of parallel fuel cell system Disclosed herein is a method of controlling start/stop of a parallel fuel cell system, which, when controlling stop of a parallel fuel cell system in which two or more fuel cell systems are connected in parallel, considers operating state information of each fuel cell system, such as a current speed value of an air compressor and an opening degree of an air-exhaust-side air pressure valve of a fuel cell stack. Accordingly, the method can calculate a delay time for performing fuel cell system stop control for the two or more fuel cell systems, and sequentially perform the fuel cell system stop control for the two or more fuel cell systems based on the calculated delay time. Therefore, it is possible to minimize output delay of each fuel cell system and to achieve deterioration prevention and efficiency improvement of the fuel cell stack by fuel cell system start/stop control.
US11777109B2	Hydrophilic porous carbon electrode and manufacturing method of same A hydrophilic porous carbon electrode which has excellent hydrophilicity, which has high reaction activity when used for a battery, and with which excellent battery characteristics is able to be obtained is provided. A hydrophilic porous carbon electrode is a sheet-form hydrophilic porous carbon electrode in which a carbon fiber is bonded using a resin carbide and has a contact angles θA of water on both surfaces in a thickness direction being 0 to 15° and a contact angle θB of water in a middle portion in the thickness direction being 0 to 15°. The hydrophilic porous carbon electrode is obtained by forming the carbon fiber and a binder fiber into a sheet, impregnating the sheet into a thermosetting resin, subjecting it to heat press processing, and then subjecting it to carbonization at 400 to 3000° C. in an inert atmosphere. The hydrophilic porous carbon electrode is transported and is subjected to a heat treatment while an oxidizing gas flows at 400 to 800° C. in a direction perpendicular to a direction in which the hydrophilic porous carbon electrode is transported to be subjected to hydrophilization.
US11777108B2	Power storage device and method for charging the same A decrease in the capacity of a power storage device is inhibited by adjusting or reducing imbalance in the amount of inserted and extracted carrier ions between positive and negative electrodes, which is caused by decomposition of an electrolyte solution of the negative electrode. Further, the capacity of the power storage device can be restored. Furthermore, impurities in the electrolyte solution can be decomposed with the use of the third electrode. A power storage device including positive and negative electrodes, an electrolyte, and a third electrode is provided. The third electrode has an adequate electrostatic capacitance. The third electrode can include a material with a large surface area. In addition, a method for charging the power storage device including the steps of performing charging by applying a current between the positive and negative electrodes, and performing additional applying a current between the third electrode and the negative electrode is provided.
US11777106B2	Oxygen catalyst, electrode using the same, and electrochemical measurement method In a case where an alkali aqueous solution is used as an electrolyte, provided are an oxygen catalyst excellent in catalytic activity and composition stability, an electrode having high activity and stability using this oxygen catalyst, and an electrochemical measurement method that can evaluate the catalytic activity of the oxygen catalyst alone. The oxygen catalyst is an oxide having peaks at positions of 2θ=30.07°±1.00°, 34.88°±1.00°, 50.20°±1.00°, and 59.65°±1.00° in an X-ray diffraction measurement using a CuKα ray, and having constituent elements of bismuth, ruthenium, sodium, and oxygen. An atom ratio O/Bi of oxygen to bismuth and an atom ratio O/Ru of oxygen to ruthenium are both more than 3.5.
US11777105B2	Proton-conducting ceramic fuel cell architecture A method of manufacturing a proton-conducting fuel cell includes assembling a green anode-electrolyte half-cell by forming an anode substrate layer having an upper surface and a lower surface, forming an anode functional layer on the upper surface of the anode substrate layer, forming an electrolyte layer on an upper surface of the anode functional layer, and forming a stress balancing layer on the lower surface of the anode substrate layer. The method further includes positioning the green anode-electrolyte half-cell on kiln furniture inside a sintering kiln and sintering the green anode-electrolyte half-cell using SSRS to an anode-electrolyte half-cell.
US11777098B2	Method and system for functional conductive polymer initiated cathode electrolyte interface for silicon anode-based lithium ion batteries Systems and methods for conductive polymer monomers as cathode additives for silicon-based lithium ion batteries may include a silicon-based anode, an electrolyte, and a cathode. The cathode may include an active material and small amounts of dispersed conductive polymer monomer additive. The cathode active material may include one or more of nickel cobalt aluminum oxide (NCA), nickel cobalt manganese oxide (NCM), lithium iron phosphate (LFP), lithium cobalt oxide (LCO), and lithium manganese oxide (LMO). The conductive polymer monomer additive may any known monomer based on thiophene, aniline, and/or pyrrole core structures alone or in combination. The conductive polymer monomer additive may comprise 5% or less by weight of the active material, or 1% or less by weight of the active material, or 0.5% or less by weight of the active material.
US11777097B2	Binder composition, mixture for producing electrode for non-aqueous electrolyte secondary battery, electrode for non-aqueous electrolyte secondary battery, and non-aqueous electrolyte secondary battery The present invention is to provide a binder composition of a non-aqueous electrolyte secondary battery, which contains a vinylidene fluoride polymer and is capable of further enhancing adhesive strength of the electrode mixture layer to a surface of a current collector. The above objective can be achieved by a binder composition of a non-aqueous electrolyte secondary battery, the binder composition comprising a vinylidene fluoride copolymer for a binder of a non-aqueous electrolyte secondary battery, the vinylidene fluoride copolymer containing: a first constituent unit derived from vinylidene fluoride, and a second constituent unit containing an isocyanate group or having a structure that produces an isocyanate group when heated at 200° C. for 1 hour. This binder composition can be used in a mixture for producing an electrode for a non-aqueous electrolyte secondary battery, an electrode for a non-aqueous electrolyte secondary battery, and a non-aqueous electrolyte secondary battery.
US11777095B2	Secondary battery comprising electrode tab provided with insulation coating layer Provided is a secondary battery which includes an electrode assembly having an electrode tab extended from an electrode current collector, wherein the electrode tab is provided with an insulation coating layer containing an inorganic filler and a binder, the binder has an electrolyte uptake more than 0% and less than 50%, and the electrolyte uptake is determined by a predetermined method. In the secondary battery according to the present disclosure, the insulation coating layer provided in the electrode tab includes a binder having a low electrolyte uptake, and thus the insulation coating layer has improved adhesion and is prevented from detachment from the electrode tab. As a result, it is possible to maintain an excellent insulation state and to minimize an internal short-circuit in a secondary battery, thereby ensuring safety.
US11777094B2	Composite binder composition for all-solid-state battery, electrode slurry comprising same, and method of manufacturing electrode for all-solid-state battery using electrode slurry A composite binder composition for an all-solid-state battery includes: a first polymer comprising a repeating structure represented by Chemical Formula 1a or Chemical Formula 1b below, and a second polymer comprising at least one selected from a group consisting of diene-based rubber, polysiloxane, and combinations thereof:
US11777085B2	Lithium-supplement layer and its negative electrode sheet, lithium ion battery and device The application relates to the field of lithium ion battery technology and, more particularly, relates to a lithium-supplement layer and its negative electrode sheet, a lithium ion battery and a device. The lithium-supplement layer is formed by connecting a transition layer, an oxide layer and a surface layer in sequence, the surface layer contains an appropriate amount of an organic material and a filling substance, which can reduce a winding temperature of the negative electrode sheet, the oxide layer substance in the lithium-supplement layer is used to provide an additional lithium source, after injection, the lithium source can be continuously supplemented during the cycle process to improve the activity of a lithium layer, at the same time, the filling substance contained in the surface layer can effectively play a role of restraining the expansion of an active substance, and improve the battery cycle performance.
US11777082B2	Negative electrode material for lithium ion secondary batteries, method for manufacturing the same, paste for negative electrode, negative electrode sheet, and lithium ion secondary A negative electrode material for lithium ion secondary batteries, including composite material particles containing nanosilicon particles having a 50% particle diameter (Dn50) of 5 to 100 nm in a number-based cumulative particle size distribution of primary particles, graphite particles and an amorphous carbon material; the composite material particles containing the nanosilicon particles at a content of 30 to 60 mass % or less, and the amorphous carbon material at a content of 30 to 60 mass % or less; the composite material particles having a 90% particle diameter (DV90) in the volume-based cumulative particle size distribution of 10.0 to 40.0 μm, a BET specific surface area of 1.0 to 5.0 m2/g, and an exothermic peak temperature in DTA measurement of 830° C. to 950° C. Also disclosed is a paste for negative electrodes, a negative electrode sheet, a lithium ion secondary battery and a method for manufacturing the negative electrode material.
US11777080B2	Negative electrode for secondary battery Provided herein are a negative electrode and a secondary battery including the same. In particular, the negative electrode includes: a current collector; a first active material layer including first active material particles and disposed on the current collector; and a second active material layer including second active material particles and disposed on the first active material layer, in which a lithium ion diffusion rate of the second active material particles is two to three times that of the first active material particles.
US11777077B2	Silicon particles for battery electrodes Silicon particles for use in an electrode in an electrochemical cell are provided. The silicon particles may have outer regions extending about 20 nm deep from the surfaces, the outer regions comprising an amount of aluminum such that a bulk measurement of the aluminum comprises at least about 0.01% by weight of the silicon particles. The bulk measurement of the aluminum may provide the amount of aluminum present at least in the outer regions.
US11777076B2	All-solid secondary battery, and method of manufacturing all-solid secondary battery An all-solid secondary battery including: a cathode layer including a cathode active material layer; an anode layer; and a solid electrolyte layer including a solid electrolyte, wherein the solid electrolyte layer is disposed between the cathode layer and the anode layer, wherein the anode layer includes an anode current collector, a first anode active material layer in contact with the solid electrolyte layer, and a second anode active material layer disposed between the anode current collector and the first anode active material layer, wherein the first anode active material layer includes a first carbonaceous anode active material, and the second anode active material layer.
US11777075B2	Positive active material for rechargeable lithium battery, preparing method thereof and rechargeable lithium battery comprising positive electrode including positive active material A positive active material for a rechargeable lithium battery, a preparing method thereof, and a rechargeable lithium battery including the same are provided. The positive active material includes: a first positive active material in a form of secondary particles in which a plurality of primary particles are aggregated, wherein at least a portion of the primary particles have a radially arranged structure, and a second positive active material having a monolithic structure, wherein both the first positive active material and the second positive active material are nickel-based positive active materials, each of the first positive active material and the second positive active material is coated with cobalt, and a maximum roughness of the surface of the second positive active material is greater than or equal to about 15 nm.
US11777069B2	Light-emitting module A light emitting module includes a board, light sources, first and second wirings, and an insulating member. Each of the light sources includes first and second electrodes exposed from an upper side. The first wiring includes first extending portions and first connecting portions. The second wiring includes second extending portions and second connecting portions. The insulating member covers the first wiring and the second extending portions of the second wiring while a portion of each of the second extending portions of the second wiring is exposed from the insulating member through a corresponding one of the openings. The second connecting portions of the second wiring are arranged on or above a part of the insulating member positioned on or above the first connecting portions of the first wiring. The second connecting portions of the second wiring are respectively connected to the second extending portions at the openings.
US11777062B2	Method of manufacturing nitride semiconductor light emitting element A method of manufacturing a nitride semiconductor light-emitting element configured to emit deep ultraviolet light includes: providing a semiconductor structure comprising: an n-side semiconductor layer comprising an n-side contact layer comprising aluminum, gallium, and nitrogen, a p-side semiconductor layer, and an active layer between the n-side semiconductor layer and the p-side semiconductor layer; forming an n-side electrode, which comprises forming, successively from an n-side contact layer side: a first layer located above the n-side contact layer and comprising a titanium layer, a second layer located above the first layer and comprising a silicon-containing aluminum alloy layer, and a third layer located above the second layer and comprising a tantalum layer and/or a tungsten layer; and heating the n-side electrode.
US11777061B2	Light emitting diode device with tunable emission Described at light emitting diode (LED) devices emitting different colors on the same wafer, which facilitates their integration with close packing density (not requiring transfer of devices from two different wafers to a third substrate module). The LED devices and driving methods allow light of different colors and similar luminance levels to be emitted for given input current.
US11777055B2	Light emitting device A light emitting device includes a substrate, a plurality of light sources, a partitioning member, a light transmissive member, a plurality of reflecting portions. The light sources are arranged on the substrate. Each of the light sources has a light emitting diode. The partitioning member includes a plurality of wall portions defining a plurality of sections respectively surrounding at least one of the light sources, the wall portions including top portions. The light transmissive member is arranged above the light sources. The plurality of reflecting portions are arranged on a lower surface of the light transmissive member. Lower surfaces of the reflecting portions are positioned lower than apexes of the top portions of the wall portions of the partitioning member.
US11777053B2	Light-emitting diode A light-emitting diode is provided. The light-emitting diode includes a P-type semiconductor layer, a N-type semiconductor layer, and a light-emitting stack located therebetween. The light-emitting stack includes a plurality of well layers and a plurality of barrier layers that are alternately stacked, the well layers includes at least one first well layer, at least one second well layer, and third well layers that have different indium concentrations. The first well layer has the largest indium concentration, and the third well layers have the smallest indium concentration. Three of well layers that are closest to the P-type semiconductor layer are the third well layers, and the first well layer is closer to the N-type semiconductor layer than the P-type semiconductor layer.
US11777052B2	Method of repairing the light emitting device A method of repairing a light emitting device, comprises: providing a light emitting device comprising a carrier board and a first light emitting unit; destroying the first light emitting unit and forming a removal surface on the light emitting device; planarizing the removal surface; providing a bonding structure on the removal surface; and fixing a second light emitting unit on the planarized removal surface through the bonding material.
US11777050B2	Optical sensor An optical sensor includes: a photosensitive layer that absorbs incident light to generate a first carrier with a first polarity and a second carrier with a second polarity different from the first polarity; a channel layer that is electrically connected to the photosensitive layer and that conducts the first carrier that has moved from the photosensitive layer; a counter electrode facing the channel layer through the photosensitive layer; an insulating layer positioned between the photosensitive layer and the counter electrode; and a source electrode and a drain electrode each electrically connected to the channel layer.
US11777047B2	Two-junction photovoltaic devices The present disclosure relates to a photovoltaic (PV) device that includes a first junction constructed with a first alloy and having a bandgap between about 1.0 eV and about 1.5 eV, and a second junction constructed with a second alloy and having a bandgap between about 0.9 eV and about 1.3 eV, where the first alloy includes III-V elements, the second alloy includes III-V elements, and the PV device is configured to operate in a thermophotovoltaic system having an operating temperature between about 1500° C. and about 3000° C.
US11777043B1	Photodetectors with substrate extensions adjacent photodiodes A substrate is formed to include a substrate base and a substrate extension. A photodiode contacts the substrate base. The substrate extension is adjacent the photodiode. An additional device contacts the substrate extension. A sidewall spacer contacts the photodiode and the substrate extension. The additional device includes conductive elements within the substrate extension adjacent the sidewall spacer.
US11777040B2	Semiconductor device with nanostructures A semiconductor device includes a substrate, a photo sensing region, and a plurality of semiconductor plugs. The photo sensing region is in the substrate. The photo sensing region forms a p-n junction with the substrate. The semiconductor plugs extend from above the photo sensing region into the photo sensing region.
US11777035B2	Multi-layer film device and method A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
US11777033B2	Transistors having vertical nanostructures A semiconductor device according to the present disclosure includes a first isolation feature and a second isolation feature, a fin structure extending lengthwise along a first direction and sandwiched between the first isolation feature and the second isolation feature along a second direction perpendicular to the first direction, a first channel member disposed over the first isolation feature, a second channel member disposed over the second isolation feature, and a gate structure disposed over and wrapping around the first channel member and the second channel member.
US11777031B2	Semiconductor structure and manufacturing method for the semiconductor structure The present disclosure provides a semiconductor device and a method for fabricating a semiconductor device. The semiconductor device includes a substrate, a metal gate layer over the substrate, a channel between a source region and a drain region in the substrate, and a ferroelectric layer, at least a portion of the ferroelectric layer is between the metal gate layer and the substrate, wherein the ferroelectric layer includes hafnium oxide-based material, the hafnium oxide-based material includes a first portion of hafnium oxide with orthorhombic phase, a second portion of hafnium oxide with monoclinic phase, and a third portion of the hafnium oxide with tetragonal phase, wherein a first volume of the first portion is greater than a second volume of the second portion, and the second volume of the second portion is greater than a third volume the third portion.
US11777030B2	Semiconductor device A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.
US11777028B2	Semiconductor device According to one embodiment, a semiconductor device includes first to third electrodes, a first conductive member, a semiconductor member, and a first insulating member. The third electrode includes a third electrode end portion and a third electrode other-end portion. The first conductive member includes a first conductive member end portion and a first conductive member other-end portion. The first conductive member is electrically connected with one of the second electrode or the third electrode. The semiconductor member includes first to fourth semiconductor regions. The first semiconductor region includes first and second partial regions. The third semiconductor region is electrically connected with the second electrode. The fourth semiconductor region is electrically connected with the first electrode. At least a portion of the first insulating member is between the semiconductor member and the third electrode and between the semiconductor member and the first conductive member.
US11777027B2	Semiconductor device A first semiconductor region, a second semiconductor region, and a third semiconductor region are arranged in layers. Trenches penetrate through the second semiconductor region and reach the first semiconductor region. Each of the trenches may include a gate electrode, and an insulating film insulating the gate electrode from the first semiconductor region and the second semiconductor region. An upper electrode is electrically connected to the second semiconductor region and the third semiconductor region. A fourth semiconductor region of the second conductivity type is arranged on an outer side of the trench of which the gate electrode is an outermost gate electrode in a plan view. An edge trench is arranged on an outer side of the fourth semiconductor region. The fourth semiconductor region is electrically connected to the upper electrode and a bottom of the fourth semiconductor may be arranged deeper than a bottom of the second semiconductor region.
US11777023B2	Semiconductor device and method for manufacturing the same A semiconductor device includes a substrate, a first GaN-based high-electron-mobility transistor (HEMT), a second GaN-based HEMT, a first interconnection, and a second interconnection is provided. The substrate has a plurality of first-type doped semiconductor regions and second-type doped semiconductor regions. The first GaN-based HEMT is disposed over the substrate to cover a first region on the first-type doped semiconductor regions and the second-type doped semiconductor regions in the substrate. The second GaN-based HEMT is disposed over the substrate to cover a second region. The first region is different from the second region. The first interconnection is disposed over and electrically connected to the substrate, forming a first interface. The second interconnection is disposed over and electrically connected to the substrate, forming a second interface. The first interface is separated from the second interface by at least two heterojunctions formed in the substrate.
US11777019B2	Lateral heterojunction bipolar transistor with improved breakdown voltage and method Disclosed is a semiconductor structure including a device, such as a lateral heterojunction bipolar transistor (HBT), made up of a combination of at least three different semiconductor materials with different bandgap sizes for improved performance. In the device, a base layer of the base region can be positioned laterally between a collector layer of a collector region and an emitter layer of an emitter region and can be physically separated therefrom by buffer layers. The base layer can be made of a narrow bandgap semiconductor material, the collector layer and, optionally, the emitter layer can be made of a wide bandgap semiconductor material, and the buffer layers can be made of a semiconductor material with a bandgap between that of the narrow bandgap semiconductor material and the wide bandgap semiconductor material. Also disclosed herein is a method of forming the structure.
US11777013B2	Channel formation for three dimensional transistors Embodiments herein describe techniques for a three dimensional transistor above a substrate. A three dimensional transistor includes a channel structure, where the channel structure includes a channel material and has a source area, a drain area, and a channel area between the source area and the drain area. A source electrode is coupled to the source area, a drain electrode is coupled to the drain area, and a gate electrode is around the channel area. An electrode selected from the source electrode, the drain electrode, or the gate electrode is in contact with the channel material on a sidewall of an opening in an inter-level dielectric layer or a surface of the electrode. The electrode is further in contact with the channel structure including the source area, the drain area, or the channel area. Other embodiments may be described and/or claimed.
US11777010B2	Semiconductor structure and method for forming the same A semiconductor structure includes a gate stack over a substrate and a blocking layer disposed between the gate stack and the substrate. The gate stack includes an upper electrode, a lower electrode, a ferroelectric layer disposed between the upper electrode and the lower electrode, and a first seed layer disposed between the ferroelectric layer and the lower electrode. The blocking layer includes doped hafnium oxide.
US11777009B2	Contacts for highly scaled transistors A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.
US11777007B2	Method for fabricating memory device A method for fabricating memory device is provided. The method comprises forming a cell structure on a substrate, wherein the cell structure comprises a first gate structure and a second gate structure disposed on a substrate and an insulating layer in contact between the first gate structure and the second gate structure, wherein the first gate structure and the second gate structure are planarized and the first gate structure is for storing charges. Further, the first gate structure and the second gate structure are patterned to have a shallow indent above the insulating layer. An isolation structure is formed in the shallow indent to have a shallow indent isolation.
US11777006B2	Nonvolatile memory device In a gate electrode of a nonvolatile memory device of an embodiment, a tunnel insulating film covers a channel region. A first current collector file is disposed on the side opposite to the channel region with respect to the tunnel insulating film. An ion conductor film is disposed between the tunnel insulating film and the first current collector film. A first electrode film is disposed between the tunnel insulating film and the ion conductor film. The first electrode film is in contact with the ion conductor film. A second electrode film is disposed between the ion conductor film and the first current collector film. The second electrode film is in contact with the ion conductor film. A second current collector film is disposed between the tunnel insulating film and the second electrode film.
US11777002B2	Laterally-diffused metal-oxide semiconductor transistor and method therefor A transistor includes a trench formed in a semiconductor substrate with the trench having a first sidewall and a second sidewall. A gate region includes a conductive material filled in the trench. A drift region having a first conductivity type is formed in the semiconductor substrate adjacent to the second sidewall. A drain region is formed in the drift region and separated from the second sidewall by a first distance. A dielectric layer is formed at the top surface of the semiconductor substrate covering the gate region and the drift region between the second sidewall and the drain region. A field plate is formed over the dielectric layer and isolated from the conductive material and the drift region by way of the dielectric layer.
US11776995B2	Device comprising a transistor A transistor is produced by forming a first part of a first region of the transistor in a semiconductor substrate by implanting dopants through an opening in an isolating trench formed at an upper surface of the semiconductor substrate. A second region of the transistor in the opening by epitaxy.
US11776993B2	Capacitor array and method for forming the same A method for forming a capacitor array includes depositing a first nitride layer, a first oxide layer, and a second nitride layer in sequence over first and second contacts on a substrate; etching the first nitride layer, the first oxide layer, and the second nitride layer to form first and second openings exposing the first and second contacts; conformally depositing a bottom electrode layer over the first and second nitride layers and the first oxide layer and on the first and second contacts; etching the second nitride layer and the first oxide layer to form a third opening having a bottom position higher than a top surface of the first nitride layer; removing the first oxide layer through the third opening; forming a capacitor dielectric layer over the bottom electrode layer; forming a top electrode layer over the capacitor dielectric layer.
US11776992B2	Trench capacitor having improved capacitance and fabrication method thereof A semiconductor memory device includes a substrate; a film stack on the substrate; a silicon device layer on the film stack; and a trench with corrugated sidewall surface extending into the silicon device layer, the film stack, and the substrate. A trench capacitor is located in the trench. The trench capacitor includes an inner electrode and an outer electrode with a node dielectric layer therebetween. The node dielectric layer is in direct with the film stack and the bulk semiconductor substrate. A transistor is disposed on the substrate. The transistor includes a source region and a drain region, a channel region between the source region and the drain region, and a gate over the channel region. The source region is electrically connected to the inner electrode of the trench capacitor.
US11776990B2	Micro light-emitting diode display panel A micro light-emitting diode display panel including first and second substrates, micro light-emitting diodes, a wavelength conversion layer, a light-shielding pattern layer, a light filter layer, and an air gap is provided. The micro light-emitting diodes are disposed on the first substrate and respectively located in a plurality of sub-pixel areas. The micro light-emitting diodes are adapted to emit a light beam. The wavelength conversion layer is overlapped with at least a portion of the micro light-emitting diodes. The light beam is used to excite the wavelength conversion layer to emit a converted light beam. The light filter layer is disposed between the wavelength conversion layer and the second substrate and overlapped with the micro light-emitting diodes. The air gap is disposed between any two adjacent ones of any one of the micro light-emitting diodes, the second substrate, the wavelength conversion layer, and the light filter layer.
US11776989B2	Methods of parallel transfer of micro-devices using treatment A method of transferring micro-devices includes selectively treating a first adhesive layer to form a treated portion and an untreated portion while micro-devices are attached the first adhesive layer. A second adhesive layer on a second surface is placed to abut the micro-devices. The first adhesive layer is exposed to illumination in a region that overlaps at least some of the treated portion and at least some of the untreated portion. Exposing the first adhesive layer to illumination neutralizes the at least some of the untreated portion to create a neutralized portion that is less adhesive than an exposed area of the treated portion. The first surface is separated from the second surface such that micro-devices in the treated portion remain attached to the first surface and micro-devices in the neutralized portion are attached to the second surface and separate from the first surface.
US11776988B2	Micro light-emitting display apparatus and method of manufacturing the same A micro light-emitting display apparatus and a method of manufacturing the same are disclosed The micro light-emitting display apparatus includes a first semiconductor layer, an isolation structure provided on the first semiconductor layer and configured to define a plurality of sub-pixels each configured to emit light, a first light-emitting unit including a first active layer provided in a first sub-pixel among the plurality of sub-pixels, and a second semiconductor layer provided on the first active layer, and a second light-emitting unit including a rod semiconductor layer provided in a second sub-pixel among the plurality of sub-pixels, a second active layer provided on the rod semiconductor layer, and a third semiconductor layer provided on the second active layer. The first active layer is configured to emit blue light and the second active layer is configured to emit green light.
US11776986B2	Packaging methods of semiconductor X-ray detectors Disclosed herein are various methods of packaging a semiconductor X-ray detector. The methods may include bonding chips including an X-ray absorption layer or including both an X-ray absorption layer and an electronic layer onto another support such as an interposer substrate or a printed circuit board.
US11776985B2	Method of forming self aligned grids in BSI image sensor A method of fabricating self-aligned grids in a BSI image sensor is provided. The method includes depositing a first dielectric layer over a back surface of a substrate that has a plurality of photodiodes formed therein, forming a grid of trenches, and filling in the trenches with dielectric material to create a trench isolation grid. Here, a trench passes through the first dielectric layer and extends into the substrate. The method further includes etching back dielectric material in the trenches to a level that is below an upper surface of the first dielectric layer to form recesses overlaying the trench isolation grid, and filling in the recesses with metallic material to create a metallic grid that is aligned with the trench isolation grid.
US11776984B2	Image sensor comprising an angular filter An image sensor includes organic photodetectors and an angular filter less than 20 μm away from the photodetectors. Further, a method of manufacturing an image sensor includes the forming of organic photodetectors and of an angular filter less than 20 μm away from the photodetectors.
US11776978B2	Solid-state image pickup device and electronic apparatus having a separation wall between the first photodiode and the second photodiode The present disclosure relates to a solid-state image pickup device and an electronic apparatus that are capable of preventing leakage of charges between adjacent pixels. A plurality of pixels perform photoelectric conversion on light incident from a back surface via different on-chip lenses for each pixel. A pixel separation wall is formed between pixels adjacent to each other, and includes a front-side trench formed from a front surface and a backside trench formed from the back surface. A wiring layer is provided on the front surface. The present disclosure is applicable to, for example, a backside illuminated CMOS image sensor.
US11776977B2	Laminate and solid-state imaging element A laminate includes a colored layer and a light attenuating layer, in which the colored layer and the light attenuating layer are laminated, and a difference ΔT1 between a maximum value and a minimum value of light transmittance of the light attenuating layer in a wavelength range of 400 to 700 nm is 10% or less.
US11776976B2	Electromagnetic wave processing device The present technology relates to an electromagnetic wave processing device that enables suppression of a ripple. Provided are a photoelectric conversion element, a narrow band filter stacked on a light incident surface side of the photoelectric conversion element and configured to transmit an electromagnetic wave having a desired wavelength, and interlayer films respectively formed above and below the narrow band filter, and the narrow band filter is formed in a shape with a level difference. The level difference is formed for each photoelectric conversion element. Alternatively, the level difference is formed between the photoelectric conversion elements and in the interlayer film. The present technology can be applied to an imaging element or a sensor using a plasmon filter or a Fabry-Perot interferometer.
US11776974B2	Photoelectric conversion apparatus, photoelectric conversion system, and moving body A photoelectric conversion apparatus includes a photoelectric conversion portion, an amplification transistor having an input node, a first transfer transistor, a second transfer transistor arranged between the first transfer transistor and the input node, and a reset transistor connected to the input node. When electric charges are transferred from the photoelectric conversion portion to the input node, the photoelectric conversion apparatus switches a capacity value of the input node by controlling the second transfer transistor to be on or off.
US11776973B2	Method of manufacturing display device A method of manufacturing a display device, the method including providing a substrate, forming a first electrode, a second electrode spaced from the first electrode and in a same plane as the first electrode, a first alignment line connected to the first electrode, and a second alignment line connected to the second electrode on the substrate, self-aligning the plurality of light emitting elements by providing a solution containing a plurality of light emitting elements on the substrate, removing the first alignment line and the second alignment line from the substrate on which the plurality of light emitting elements are self-aligned, forming a first contact electrode electrically connecting one end of each light emitting element to the first electrode, and forming a second contact electrode electrically connecting an other end of each light emitting element to the second electrode.
US11776969B2	Semiconductor device and electronic device To provide a novel shift register. Transistors 101 to 104 are provided. A first terminal of the transistor 101 is connected to a wiring 111 and a second terminal of the transistor 101 is connected to a wiring 112. A first terminal of the transistor 102 is connected to a wiring 113 and a second terminal of the transistor 102 is connected to the wiring 112. A first terminal of the transistor 103 is connected to the wiring 113 and a gate of the transistor 103 is connected to the wiring 111 or a wiring 119. A first terminal of the transistor 104 is connected to a second terminal of the transistor 103, a second terminal of the transistor 104 is connected to a gate of the transistor 101, and a gate of the transistor 104 is connected to a gate of the transistor 102.
US11776968B2	Semiconductor device comprising oxide semiconductor layer An object of an embodiment of the present invention is to manufacture a semiconductor device with high display quality and high reliability, which includes a pixel portion and a driver circuit portion capable of high-speed operation over one substrate, using transistors having favorable electric characteristics and high reliability as switching elements. Two kinds of transistors, in each of which an oxide semiconductor layer including a crystalline region on one surface side is used as an active layer, are formed in a driver circuit portion and a pixel portion. Electric characteristics of the transistors can be selected by choosing the position of the gate electrode layer which determines the position of the channel. Thus, a semiconductor device including a driver circuit portion capable of high-speed operation and a pixel portion over one substrate can be manufactured.
US11776966B2	Semiconductor device and method for manufacturing the semiconductor device First to third insulators are successively formed in this order over a first conductor over a semiconductor substrate; a hard mask with a first opening is formed thereover; a resist mask with a second opening is formed thereover; a third opening is formed in the third insulator; a fourth opening is formed in the second insulator; the resist mask is removed; a fifth opening is formed in the first to third insulators; a second conductor is formed to cover an inner wall and a bottom surface of the fifth opening; a third conductor is formed thereover; polishing treatment is performed so that the hard mask is removed, and that levels of top surfaces of the second and third conductors and the third insulator are substantially equal to each other; and an oxide semiconductor is formed thereover. The second insulator is less permeable to hydrogen than the first and third insulators, the second conductor is less permeable to hydrogen than the third conductor.
US11776965B2	Light emitting display device comprising anode having at least one opening A light emitting display device includes a substrate including first subpixels, second subpixels and third subpixels; a first anode, having at least one opening, in each of the first subpixels; a second anode in each of the second subpixels, and a third anode in each of the third subpixels; a reflective insulating film at the opening of the first anode to contact the first anode under the first anode; an organic stack on each of the first anode, the second anode and the third anode; and a cathode on the organic stack.
US11776961B2	Semiconductor device and manufacturing method thereof for selectively etching dummy fins A semiconductor device includes a first device fin and a second device fin that are each located in a first region of the semiconductor device. The first region has a first pattern density. A first dummy fin is located in the first region. The first dummy fin is disposed between the first device fin and the second device fin. The first dummy fin has a first height. A third device fin and a fourth device fin are each located in a second region of the semiconductor device. The second region has a second pattern density that is greater the first pattern density. A second dummy fin is located in the second region. The second dummy fin is disposed between the third device fin and the fourth device fin. The second dummy fin has a second height that is greater than the first height.
US11776956B2	III-V fins by aspect ratio trapping and self-aligned etch to remove rough epitaxy surface A semiconductor device that includes a fin structure of a type III-V semiconductor material that is substantially free of defects, and has sidewalls that are substantially free of roughness caused by epitaxially growing the type III-V semiconductor material abutting a dielectric material. The semiconductor device further includes a gate structure present on a channel portion of the fin structure; and a source region and a drain region present on opposing sides of the gate structure.
US11776950B2	Integrated circuit including cells with different heights and method of designing the same An IC includes: a plurality of first cells placed in a series of first rows extending in a first horizontal direction and each having a first height; and a plurality of second cells placed in a series of second rows extending in the first horizontal direction and each having a second height different from the first height, wherein a total height of the series of first rows corresponds to a multiple of a height of a first multi-height cell with a maximum height among the plurality of first cells, and a total height of the series of second rows corresponds to a multiple of a height of a second multi-height cell with a maximum height among the plurality of second cells.
US11776946B2	Method of manufacturing package-on-package device and bonding apparatus used therein A method of manufacturing a package-on-package device includes a bonding step carried out by a bonding apparatus including a pressing member and a light source that produces a laser beam. A bottom package including a lower substrate, lower solder balls alongside an edge of the lower substrate, and a lower chip on a center of the lower substrate is provided, the bottom package is bonded to an interposer substrate having upper solder balls aligned with the lower solder balls, and a top package having an upper substrate and an upper chip on the upper substrate is bonded to the interposer substrate. While the interposer substrate is disposed on the bottom package, the pressing member presses the interposer substrate against the bottom package, and the laser beam adheres the lower solder balls to the upper solder balls.
US11776945B2	Package-on-package structure including a thermal isolation material A semiconductor device includes a first package component and a second package component. The first package component has a first die formed on a first substrate. A second package component has a second die formed on a second substrate. A thermal isolation material is attached on the first die, wherein the thermal isolation material thermally insulates the second die from the first die, and the thermal isolation material has a thermal conductivity of from about 0.024 W/mK to about 0.2 W/mK. A first set of conductive elements couples the first package component to the second package component.
US11776944B2	Discrete three-dimensional processor A discrete three-dimensional (3-D) processor comprises communicatively coupled first and second dice. The first die comprises 3-D memory (3D-M) arrays, whereas the second die comprises at least a non-memory circuit and at least an off-die peripheral-circuit component of the 3D-M arrays. The first die does not comprise said off-die peripheral-circuit component. The non-memory circuit on the second die is not part of a memory.
US11776941B2	Semiconductor package A semiconductor package includes a package substrate, a connection substrate on the package substrate, a first image sensor chip on the connection substrate, a second image sensor chip on the connection substrate, the second image sensor chip being horizontally spaced apart from the first image sensor chip, and a memory chip disposed on the package substrate and electrically connected to the first image sensor chip through the connection substrate. A distance between the first image sensor chip and the second image sensor chip is less than a thickness of the first image sensor chip.
US11776939B2	Stacked light emitting diode (LED) display Embodiments of the present disclosure include apparatuses and method for a stacked light emitting diode (LED) display. A stacked LED display can include a first array of LEDs that are configured to emit red light, a second array of LEDs that are configured to emit green light, and a third array of LEDs that are configured to emit blue light. The stacked LED hologram display can include a number of actuators configured to adjust a position of a first array of LEDs in a first direction and a second direction orthogonal to the first direction, adjust a position of a second array of LEDs in the first direction and the second direction, and adjust a position of a third array of LEDs in the first direction and the second direction to control the packing scheme of the LEDs.
US11776937B2	Electronic module An electronic module has a first substrate 11; a first electronic element 13 provided on one side of the first substrate 11; a first connection body 60 provided on the one side of the first electronic element 13; a second electronic element 23 provided on the one side of the first connection body 60; and a second connection body 70 provided on the one side of the second electronic element 23. The first electronic element 13 and the second electronic element 23 do not overlap in a plane direction.
US11776936B2	Semiconductor device The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, amounting layer, switching elements, a moisture-resistant layer and a sealing resin. The substrate has a front surface facing in a thickness direction. The mounting layer is electrically conductive and disposed on the front surface. Each switching element includes an element front surface facing in the same direction in which the front surface faces along the thickness direction, a back surface facing in the opposite direction of the element front surface, and a side surface connected to the element front surface and the back surface. The switching elements are electrically bonded to the mounting layer with their back surfaces facing the front surface. The moisture-resistant layer covers at least one side surface. The sealing resin covers the switching elements and the moisture-resistant layer. The moisture-resistant layer is held in contact with the mounting layer and the side surface so as to be spanned between the mounting layer and the side surface in the thickness direction.
US11776935B2	Semiconductor device and method of manufacture An integrated fan out package on package architecture is utilized along with a reference via in order to provide a reference voltage that extends through the InFO-POP architecture. If desired, the reference via may be exposed and then connected to a shield coating that can be used to shield the InFO-POP architecture. The reference via may be exposed by exposing either a top surface or a sidewall of the reference via using one or more singulation processes.
US11776933B2	Methods of bonding semiconductor elements to a substrate, including use of a reducing gas, and related bonding machines A method of bonding a semiconductor element to a substrate includes: carrying a semiconductor element including a plurality of first electrically conductive structures with a bonding tool; supporting a substrate including a plurality of second electrically conductive structures with a support structure; providing a reducing gas in contact with each of the plurality of first conductive structures and the plurality of second conductive structures; establishing contact between corresponding ones of the plurality of first conductive structures and the plurality of second conductive structures; moving at least one of the semiconductor element and the substrate such that the corresponding ones of the plurality of first conductive structures and the plurality of second conductive structures are separated; re-establishing contact between the plurality of first conductive structures and the plurality of second conductive structures; and bonding the plurality of first conductive structures to the respective ones of the plurality of second conductive structures.
US11776930B2	Die bond head apparatus with die holder motion table A die bond head apparatus has a die bond head body coupled to a die bond head motion table, a die holder motion table mounted on the die bond head body and a die holder which is operative in use to secure a semiconductor die to a substrate. The die holder is positionable by the die holder motion table independently of the die bond head motion table.
US11776925B2	Methods of forming microelectronic devices, and related microelectronic devices and electronic systems A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a first semiconductor structure, control logic circuitry at least partially overlying the first semiconductive structure, first back-end-of-line (BEOL) structures over and in electrical communication with the control logic circuitry, and first isolation material covering the control logic circuitry and the first BEOL structures. A second microelectronic device structure is bonded over the first BEOL structures to form a first assembly. The first assembly is vertically inverted. A third microelectronic device structure comprising a second semiconductor structure is bonded over the vertically inverted first assembly to form a second assembly. Memory cells comprising portions of the second semiconductor structure are formed after forming the second assembly. Second BEOL structures are formed over the memory cells. Microelectronic devices, electronic systems, and additional methods are also described.
US11776924B2	Method of manufacturing semiconductor device The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming an interconnect layer on a semiconductor component, wherein the interconnect layer contains at least one metal pad electrically coupled to the semiconductor component; depositing an insulating layer on the interconnect layer; depositing a bonding dielectric on the insulating layer; and forming a re-routing layer penetrating through the bonding dielectric and the insulating layer and contacting the interconnect layer.
US11776922B2	Semiconductor structure containing pre-polymerized protective layer and method of making thereof A method of forming a semiconductor structure includes providing a semiconductor wafer including a plurality of semiconductor dies, providing a polymerized material layer, attaching the polymerized material layer to the semiconductor wafer such that the polymerized material layer is polymerized prior to the step of attaching the polymerized material layer to the semiconductor wafer, applying and patterning an etch mask layer over the polymerized material layer, such that openings are formed through the etch mask layer, etching portions of the polymerized material layer that are proximal to the openings through the etch mask layer by applying an etchant into the openings through the etch mask layer in an etch process, and removing the etch mask layer selective to the polymerized material layer. Alternatively, a patterned polymerized material layer may be transferred from a transfer substrate to the semiconductor wafer.
US11776920B2	Capacitor and filter and redistribution layer structure including the same Provided a filter and a redistribution layer structure including the same. The capacitor includes a first electrode, a second electrode, a third electrode, a dielectric layer, and a conductive through via. The second electrode is disposed above the first electrode. The third electrode is disposed between the first electrode and the second electrode. The dielectric layer is disposed between the first electrode and the third electrode and between the second electrode and the third electrode. The conductive through via penetrates the dielectric layer and the third electrode to be connected to the first electrode and the second electrode, and is electrically separated from the third electrode. The first electrode and the second electrode are signal electrodes, and the third electrode is a ground electrode.
US11776918B2	Semiconductor package having stiffening structure A semiconductor package having a stiffening structure is disclosed. The semiconductor package includes a substrate, an interposer on the substrate, and a first logic chip, a second logic chip, memory stacks and stiffening chips, all of which are on the interposer. The first logic chip and the second logic chip are adjacent to each other. Each memory stack is adjacent to a corresponding one of the first logic chip and the second logic chip. Each memory stack includes a plurality of stacked memory chips. Each stiffening chip is disposed between corresponding ones of the memory stacks, to be aligned and overlap with a boundary area between the first logic chip and the second logic chip.
US11776914B2	Package device A package device is provided and includes a redistribution layer. The redistribution layer includes a first dielectric layer, a second dielectric layer, and a conductive layer. The second dielectric layer is disposed on the first dielectric layer, and the second dielectric layer includes a dielectric pattern. The conductive layer is disposed between the first dielectric layer and the second dielectric layer, and the conductive layer includes a first conductive pattern. The dielectric pattern has a through hole, and in a top view of the package device, the first conductive pattern and the through hole are overlapped with each other.
US11776913B2	Semiconductor package and a package-on-package including the same A semiconductor package including: a first wiring structure; a semiconductor chip disposed on the first wiring structure; a second wiring structure disposed on the semiconductor chip and including a cavity; and a filling member between the first wiring structure and the second wiring structure and in the cavity, wherein an uppermost end of the filling member and an uppermost end of the second wiring structure are located at the same level.
US11776911B2	Semiconductor device and manufacturing method thereof A method includes forming a gate structure on a substrate; forming a gate spacer on a sidewall of the gate structure; forming a carbon-containing layer on the gate spacer; diffusing carbon from the carbon-containing layer into a portion of the substrate below the gate spacer; forming a recess in the substrate on one side of the gate spacer opposite to the gate structure; and forming an epitaxy feature in the recess of the substrate.
US11776908B2	Semiconductor die edge protection for semiconductor device assemblies and associated systems and methods Semiconductor dies with edges protected and methods for generating the semiconductor dies are disclosed. Further, the disclosed methods provide for separating the semiconductor dies without using a dicing technique. In one embodiment, trenches are formed on a front side of a substrate including semiconductor dies. Individual trenches correspond to scribe lines of the substrate where each trench has a depth greater than a final thickness of the semiconductor dies. A composite layer may be formed on sidewalls of the trenches to protect the edges of the semiconductor dies. The composite layer includes a metallic layer that shields the semiconductor dies from electromagnetic interference. Subsequently, the substrate may be thinned from a back side to singulate individual semiconductor dies from the substrate.
US11776902B2	Semiconductor device, an image unit and an endoscope system A semiconductor device includes a semiconductor substrate, a trench capacitor arranged on the semiconductor substrate, a first wiring layer, a second wiring layer, a first TSV penetrating the semiconductor substrate outside the trench capacitor, a second TSV penetrating the semiconductor substrate outside the trench capacitor, a first connecting terminal connected to the first TSV, a second connecting terminal connected to the first TSV, a third connecting terminal connected to the second TSV, and a fourth connecting terminal connected to the second TSV. A plurality of connecting terminals including the first through fourth connecting terminals are arranged dispersively over an entire area of the first wiring layer and the second wiring layer of the semiconductor device, thereby stabilizing voltage supplied to an image unit and achieving a stable image signal.
US11776898B2	Sidewall interconnect metallization structures for integrated circuit devices Interconnect metallization of an integrated circuit device includes a sidewall contact between conductive features. In a stacked device, a terminal interconnect of one device layer may intersect a sidewall of a conductive feature in another device layer or between two devices layers. In some examples, a terminal interconnect coupled to a gate, source, or drain terminal of a finFET in a vertically-stacked device may extend to a depth below a plane of the fin and intersect a sidewall of another interconnect, or another device terminal, that is in another plane of the stacked device. A stop layer below a top surface of the conductive feature may allow for sidewall contact while avoiding interconnect shorts.
US11776897B2	Electronic module, manufacturing method thereof and electronic package having the same An electronic module is provided, in which a first metal layer, an insulating layer and a second metal layer are sequentially formed on side faces and a non-active face of an electronic component to serve as a capacitor structure, where the capacitor structure is exposed from an active face of the electronic component so that by directly forming the capacitor structure on the electronic component, a distance between the capacitor structure and the electronic component is minimized, such that the effect of suppressing impedance can be optimized.
US11776889B2	Semiconductor package device and method of manufacturing the same A semiconductor device package includes a carrier provided with a first conductive element, a second conductive element arranged on a semiconductor disposed on the carrier, and a second semiconductor device disposed on and across the first conductive element and the first semiconductor device, wherein the first conductive element having a surface that is substantially coplanar with a surface of the second conductive element.
US11776888B2	Package with a substrate comprising protruding pad interconnects A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a plurality of protruding pad interconnects, and a solder resist layer located over the at least one dielectric layer, the solder resist layer comprising a thickness that is greater than a thickness of the plurality of protruding pad interconnects. A protruding pad interconnect may include a first pad portion and a second pad portion.
US11776885B2	Substrate, semiconductor device package and method of manufacturing the same A substrate includes a first dielectric layer having a first surface and a second dielectric layer having a first surface disposed adjacent to the first surface of the first dielectric layer. The substrate further includes a first conductive via disposed in the first dielectric layer and having a first end adjacent to the first surface of the first dielectric layer and a second end opposite the first end. The substrate further includes a second conductive via disposed in the second dielectric layer and having a first end adjacent to the first surface of the second dielectric layer. A width of the first end of the first conductive via is smaller than a width of the second end of the first conductive via, and a width of the first end of the second conductive via is smaller than the width of the first end of the first conductive via.
US11776883B2	Embedded die packaging for power semiconductor devices Embedded die packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a power semiconductor die is embedded in laminated body comprising a layer stack of a plurality of dielectric layers and electrically conductive layers. For example, the dielectric layers comprise dielectric build-up layers of filled or fiber reinforced dielectric and conductive interconnect comprises copper layers and copper filled vias. A dielectric build-up layer, e.g. filled or glass fiber reinforced epoxy, forms an external surface of the package covering underlying copper interconnect, particularly in regions which experience high electric field during operation, such as between closely spaced source and drain interconnect metal. For example, the power semiconductor device comprises a GaN HEMT rated for operation at ≥100V wherein the package body has a laminated structure configured for high voltage, high temperature operation with improved reliability.
US11776876B2	Distributing heatsink load across a processor module with separable input/output (I/O) connectors A heatsink for distributing heatsink load across a processor module with separable input/output (I/O) connectors, comprising: a thermal conductor; and one or more pistons aligned with one or more separable interconnects of the processor module.
US11776874B2	Apparatus and method for holding a heat generating device Systems, apparatuses, and methods are described for clamping a heat generating device such as a thyristor in place. The use of spring washers in various configurations is described. A spring washing washer may be used to apply force to a pad which in turn applies the force to a plate above a heat generating device. The plate above the heat generating device may apply downward pressure, which may force the heat generating device against a lower surface. Related systems, apparatuses, and methods are also described.
US11776873B2	Semiconductor structure and manufacturing method for the same A semiconductor structure and a manufacturing method for the same. The semiconductor structure includes a plug element and a via element. The plug element includes a tungsten plug. The plug element has a plug size in a lateral direction. The via element is electrically connected on the plug element. The via element is non-symmetrical with respect a center line of the plug element extending along a longitudinal direction. The via element has a via size in the lateral direction. The plug size is bigger than the via size.
US11776866B2	Semiconductor module heatspreading lid having integrated separators for multiple chips A semiconductor module includes a substrate having a central region, an outer region that surrounds the central region, and a middle region disposed between the central and the outer region, a first semiconductor package mounted on the central region of the substrate, a plurality of second semiconductor packages mounted on the middle region of the substrate, and a heat radiation structure disposed on the first semiconductor package and second semiconductor packages. The heat radiation structure includes a first part that is disposed on top surfaces of the first and second semiconductor packages, a second part that surrounds the middle region, a third part that is spaced apart from the second part and surrounds the first semiconductor package, and a fourth part that connects the second part to the third part.
US11776862B2	Lid structure and semiconductor device package including the same The present disclosure relates to a semiconductor device package, which includes a carrier, a lid, a first adhesive layer and a constraint structure. The carrier includes a surface and a first conductive pad on the surface of the carrier. The lid includes a first portion and a second portion separated from the first portion on the surface of the carrier. The first conductive pad is disposed between the first portion of the lid and the surface of the carrier. The first adhesive layer includes a first portion between the first portion of the lid and the first conductive pad. The constraint structure surrounds the first adhesive layer.
US11776861B2	Compartment shielding with metal frame and cap A semiconductor device has a substrate and a first semiconductor die disposed over the substrate. A first metal frame is disposed over the substrate around the first semiconductor die. A first metal lid is disposed over the first metal frame. A flap of the first metal lid includes an elastic characteristic to latch onto the first metal frame. An edge of the flap can have a castellated edge. A recess in the first metal frame and a protrusion on the first metal lid can be used to latch the first metal lid onto the first metal frame. A second metal frame and second metal lid can be disposed over an opposite surface of the substrate from the first metal frame.
US11776854B2	Semiconductor structure with hybrid nanostructures Semiconductor structures and methods for forming the same are provided. The semiconductor device includes a fin protruding from a substrate and an isolation structure surrounding the fin. The semiconductor device also includes a first channel layer and a second channel layer formed over the fin and at least partially overlapping the isolation structure. The semiconductor device further includes a gate structure formed in a space between the first channel layer and the second channel layer and wrapping around the first channel layer and the second channel layer.
US11776851B2	Semiconductor device with multi-layered source/drain regions having different dopant concentrations and manufacturing method thereof A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer.
US11776850B2	Semiconductor device with reduced loading effect The present disclosure relates to a method for forming a semiconductor structure includes depositing a dielectric layer on a substrate and depositing a patterning layer on the dielectric layer. The method also includes performing a first etching process on the patterning layer to form a first region including a first plurality of blocks at a first pattern density and a second region including a second plurality of blocks at a second pattern density that is lower than the first pattern density. The method also includes performing a second etching process on the second plurality of blocks to decrease a width of each block of the second plurality of blocks and etching the dielectric layer and the substrate using the first and second pluralities of blocks to form a plurality of fin structures.
US11776846B2	Methods for depositing gap filling fluids and related systems and devices Methods and systems for manufacturing a structure comprising a substrate. The substrate comprises plurality of recesses and a plurality of lateral spaces. The recesses and lateral spaces are at least partially filled with a gap filling fluid.
US11776843B2	Method for transferring blocks from a donor substrate onto a receiver substrate by implanting ions in the donor substrate through a mask, bonding the donor substrate to the receiver substrate, and detaching the donor substrate along an embrittlement plane A process for transferring blocks from a donor to a receiver substrate, comprises: arranging a mask facing a free surface of the donor substrate, the mask having one or more openings that expose the free surface of the donor substrate, the openings distributed according to a given pattern; forming, by ion implantation through the mask, an embrittlement plane in the donor substrate vertically in line with at least one region exposed through the mask, the embrittlement plane delimiting a respective surface region; forming a block that is raised relative to the free surface of the donor substrate localized vertically in line with each respective embrittlement plane, the block comprising the respective surface region; bonding the donor substrate to the receiver substrate via each block located at the bonding interface, after removing the mask; and detaching the donor substrate along the localized embrittlement planes to transfer blocks onto the receiver substrate.
US11776842B2	Method and device for surface treatment of substrates A method for surface treatment of an at least primarily crystalline substrate surface of a substrate such that by amorphization of the substrate surface, an amorphous layer is formed at the substrate surface with a thickness d>0 nm of the amorphous layer. This invention also relates to a corresponding device for surface treatment of substrates.
US11776840B2	Superstrate chuck, method of use, and method of manufacturing an article A chuck for retaining a superstrate or a template. The chuck comprises a geometric structure formed on a surface of the chuck. The geometric structure includes at least one of a rounded edge portion and a roughened surface portion, such that an intensity variation of light transmitting through the geometric structure and an area of the chuck adjacent to the geometric structure is reduced.
US11776838B2	Semiconductor package and manufacturing method thereof A semiconductor package includes a semiconductor device, an encapsulating material encapsulating the semiconductor device, and a redistribution structure disposed over the encapsulating material and the semiconductor device. The semiconductor device includes an active surface having conductive bumps and a dielectric film encapsulating the conductive bumps, where a material of the dielectric film comprises an epoxy resin and a filler. The conductive bumps are isolated from the encapsulating material by the dielectric film, and the redistribution structure is electrically connected to the conductive bumps. A manufacturing method of a semiconductor package is also provided.
US11776833B2	Method for improving accuracy of imprint force application in imprint lithography An imprint method is provided. The method includes exercising an imprint head along a preconditioning trajectory before contacting the imprint head with a formable material on a substrate, followed by performing imprinting on the formable material after exercising the imprint head. The exercise of the imprint head along the preconditioning trajectory may be performed after the imprint head has been idled for a predetermined period of time. The exercise of the imprint head along the preconditioning trajectory may also be performed for a duration decided based on expected throughput requirements and tools used for the imprinting process.
US11776832B2	Transfer system, transfer device, and transfer method A transfer system has a storage device including a plurality of shelves, each of the shelves including a placement portion in which an opening region is formed and on which the article is placed and an attaching portion provided according to a position of the placement portion; and a transfer device used for transferring the article, from the one side with respect to the transfer target shelf. The transfer device has a main unit portion attached to the attaching portion of the transfer target shelf from the one side, a moving portion including a grip portion and being capable of supporting the article and configured to move along the one direction, and an elevating portion configured to elevate the moving portion through the opening region of the transfer target shelf.
US11776831B2	Substrate transport system and substrate transport method A substrate transport system for transporting a substrate in a vacuum atmosphere includes a vacuum chamber, inside of which is configured to be capable of being set to a vacuum atmosphere, a transport arm provided inside the vacuum chamber and configured to hold and transport the substrate, a horizontal movement mechanism configured to move the transport arm in a horizontal direction inside the vacuum chamber, a horizontal duct arm mechanism including therein an accommodation portion having a normal pressure atmosphere, the horizontal duct arm mechanism being configured to be extendable/contractible as the transport arm moves horizontally, a vertical movement mechanism configured to move the transport arm in a vertical direction inside the vacuum chamber, and a vertical duct arm mechanism including therein an accommodation portion having a normal pressure atmosphere, the vertical duct arm mechanism being configured to be extendable/contractible as the transport arm moves vertically.
US11776826B2	Apparatus and method for treating substrate An apparatus for treating a substrate includes a process chamber having a process space therein, a support unit that supports the substrate in the process space, a heating member that heats the substrate supported on the support unit, and an exhaust unit that evacuates the process space. The exhaust unit includes an exhaust duct and a heat retention unit having a retention space that retains heat released from the process space. The retention space surrounds an adjacent area located adjacent to the process chamber in the exhaust duct.
US11776823B2	Substrate processing method and substrate processing apparatus A substrate processing method includes a process of cooling a substrate to below a freezing point of a processing liquid using a cooling fluid brought into contact with the substrate opposite. While the substrate is cooled to below the freezing point of the processing liquid, a droplet of processing liquid is dispensed onto a surface of the substrate at a specified location of a foreign substance. The droplet then forms a frozen droplet portion at the specified location. The frozen droplet portion is then thawed.
US11776822B2	Wet cleaning of electrostatic chuck Embodiments described herein relate a cleaning fixture and method to prevent chemical solutions from contacting the various substrate supporting member features and penetrating into the holes and the metal plate of the substrate supporting surface. The cleaning fixture includes a mounting plate having a plurality of thru-holes arranged on a bolt circle and configured to align with a plurality of thread holes disposed in an electrostatic chuck, a recess formed in the mounting plate, and a gas port formed through the mounting plate. A sealed plenum is formed between the recess of the mounting plate and a lower surface of the electrostatic chuck when the electrostatic chuck is coupled to the mounting plate. The gas port is fluidly coupled to the sealed plenum.
US11776821B2	Micro-electronic package with substrate protrusion to facilitate dispense of underfill between a narrow die-to-die gap A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die. An encapsulant is over the protrusion of the substrate, the encapsulant extending beneath the first die, and the encapsulant extending beneath the second die.
US11776817B2	Pattern forming method There is provided a pattern forming method for forming a pattern on a substrate. The method comprises preparing on a base a substrate in which a plurality of core materials arranged in a convex shape and in a line shape, and first and second line materials arranged in a convex shape and in a line shape on one side and the other side of each of the core materials, respectively, are formed, selectively forming a mask material on any one of the first and the second line materials by a process including anisotropic film formation, by a process including etching using a line mask having a line-shaped hole at a portion corresponding to a region where line cutting is performed, etching and removing the one on which the mask material is not formed among the first and the second line materials in the region, and removing the core material.
US11776814B2	Method of forming semiconductor device by driving hydrogen into a dielectric layer from another dielectric layer Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.
US11776813B2	Method for preparing semiconductor device structure with fine patterns at different levels The present disclosure provides a method for preparing a semiconductor device structure with fine patterns at different levels. The method includes forming a hard mask material over a substrate; etching the hardmask material to form hard mask pillars; forming spacers over sidewall surfaces of the hard mask pillars; etching the hard mask pillars and the target material by using the spacers as a mask to integrally forming a plurality of target structures, a high-level recesses in one of the plurality of target structures and a low-level recess between two target structures; and integrally forming a high-level conductive pattern in the high-level conductive pattern and a low-level conductive pattern in the low-level recess.
US11776812B2	Method for pattern reduction using a staircase spacer Devices are made by self-aligned quad pitch patterning (SAQP), staircase patterning and double staircase patterning. Methods for making devices by self-aligned quad pitch patterning (SAQP) use a single spacer in the process. Methods for making devices by staircase patterning and double staircase patterning do not use a spacer. An intermediate process step called self-aligned double patterning (SADP) is used to double the pitch following the spacer deposition. A pattern is formed on a substrate, the pattern having ultra-fine resolutions by repeating the SADP step twice for pitch quadrupling and introducing a reversal layer to form a fine trench pattern and hole pattern. The pattern designs or pattern layouts have improved LER/LWR (line edge roughness and line width roughness respectively) for below 12 nm lines and trenches in order to create self-aligned cross pitch quad trenches.
US11776811B2	Selective deposition of carbon on photoresist layer for lithography applications A method for etching a hardmask layer includes forming a photoresist layer comprising an organometallic material on a hardmask layer comprising a metal-containing material, exposing the photoresist layer to ultraviolet radiation through a mask having a selected pattern, removing un-irradiated areas of the photoresist layer to pattern the photoresist layer, forming a passivation layer comprising a carbon-containing material selectively on a top surface of the patterned photoresist layer, and etching the hardmask layer exposed by the patterned photoresist layer having the passivation layer formed thereon.
US11776810B2	Method of forming a semiconductor device A method for forming a semiconductor device is provided. In some embodiments, the method includes forming a target layer over a semiconductor substrate, forming a carbon-rich hard masking layer over the target layer, patterning features in the carbon-rich hard masking layer using an etching process, performing a directional ion beam trimming process on the features patterned in the carbon-rich hard masking layer, and patterning the target layer using the carbon-rich hard masking layer as a mask.
US11776806B2	Multi-step pre-clean for selective metal gap fill Methods for pre-cleaning substrates having metal and dielectric surfaces are described. The substrate is exposed to a strong reductant to remove contaminants from the metal surface and damage the dielectric surface. The substrate is then exposed to an oxidation process to repair the damage to the dielectric surface and oxidize the metal surface. The substrate is then exposed to a weak reductant to reduce the metal oxide to a pure metal surface without substantially affecting the dielectric surface. Processing tools and computer readable media for practicing the method are also described.
US11776805B2	Selective oxidation and simplified pre-clean Method for selectively oxidizing the dielectric surface of a substrate surface comprising a dielectric surface and a metal surface are discussed. Method for cleaning a substrate surface comprising a dielectric surface and a metal surface are also discussed. The disclosed methods oxidize the dielectric surface and/or clean the substrate surface using a plasma generated from hydrogen gas and oxygen gas. The disclosed method may be performed in a single step without the use of separate competing oxidation and reduction reactions. The disclosed methods may be performed at a constant temperature and/or within a single processing chamber.
US11776801B2	Inductively coupled plasma based atomic analysis systems and methods Inductively coupled plasma (ICP) analyzers use an ICP torch to generate a plasma in which a sample is atomized an ionized. Analysis of the atomic ions can be performed by atomic analysis, such as mass spectrometry (MS) or atomic emission spectrometry (AES). Particle based ICP analysis includes analysis of particles such as cells, beads, or laser ablation plumes, by atomizing and ionizing particles in an ICP torch followed by atomic analysis. In mass cytometry, mass tags of particles are analyzed by mass spectrometry, such as by ICP-MS. Systems and methods of the subject application include one or more of: a demountable ICP torch holder assembly, an external ignition device; an ICP load coil comprising an annular fin, particle suspension sample introduction fluidics, and ICP analyzers thereof.
US11776799B2	Data processing device An analysis operator checks an optical microscopic image obtained with an imaging mass microscope and indicates a color characteristic of an area which the analysis operator is focusing on. An optical microscopic image feature extractor calculates luminance distribution data in the indicated color. An image position adjustment processor performs a position adjustment process on a luminance distribution image derived from the optical microscopic image and an MS imaging graphic, while a resolution adjuster equalizes their spatial resolutions. A statistical analysis processor calculates a coefficient of spatial correlation between the luminance distribution image and the MS imaging graphic for each mass-to-charge ratio. Based on the calculated correlation coefficients, an analysis result display processor extracts a mass-to-charge ratio which shows an ion intensity distribution similar to the luminance distribution image. and displays it on a display unit.
US11776794B2	Electrostatic chuck assembly for cryogenic applications Embodiments of the present disclosure generally relate to an electrostatic chuck assembly suitable for use in cryogenic applications. In one or more embodiments, an electrostatic chuck assembly is provided and includes an electrostatic chuck having a substrate supporting surface opposite a bottom surface, a cooling plate having a top surface, where the cooling plate contains an aluminum alloy having a coefficient of thermal expansion (CTE) of less than 22 ppm/° C., and a bonding layer securing the bottom surface of the electrostatic chuck and the top surface of the cooling plate, where the bonding layer contains a silicone material.
US11776793B2	Plasma source with ceramic electrode plate A plasma source assembly for use with a substrate processing chamber is described. The assembly includes a ceramic lower plate with a plurality of apertures formed therein. A method of processing a substrate in a substrate processing chamber including the plasma source assembly is also described.
US11776792B2	Plasma processing apparatus and plasma processing method A plasma processing apparatus or a plasma processing method having an improved yield, the plasma processing apparatus includes: a processing chamber arranged inside a vacuum container; a processing gas supply line connecting to the vacuum container, communicating with the processing chamber, and configured to supply processing gas having adhesiveness to the processing chamber; and a gas exhaust line for the processing gas connecting and communicating the processing gas supply line with a processing chamber exhaust line that is connected to an exhaust pump and communicates with the processing chamber, in which the plasma processing apparatus exhausts the processing gas in the processing gas supply line through the gas exhaust line and the processing chamber exhaust line in a state where supplying of the processing gas to the processing chamber is stopped between one processing step of etching the wafer and a subsequent processing step.
US11776790B2	Apparatus and method for coating and in particular plasma coating of containers Provided is an apparatus and a method for coating objects and in particular containers with at least one first and one second coating station, wherein these coating stations each have at least one first coating electrode and one second coating electrode, and with a supply device for electrical supply of in each case at least one of the coating electrodes. The supply device has a high-frequency generator device for generating an a.c. voltage and/or voltage pulses as well as an a.c. voltage distribution device which distributes this a.c. voltage and/or the voltage pulses respectively to in each case at least one electrode of the first coating station and at least one electrode of the second coating station, wherein the a.c. voltage distribution device is suitable and intended for distributing the a.c. voltages and/or the voltage pulses with a time delay to the electrodes.
US11776783B2	Kit and method for the assembly of at least two variants of a relay and contact spring for a relay A stationary contact spring for a relay includes a base section fixed in a housing of the relay, a contact area opposite the base section adapted to perform an electric switching with a contact force, a spring section extending between the base section and the contact area, and an abutting latch abutting the housing with a biasing force directed against the contact force.
US11776779B2	Medium voltage switching apparatus A switching apparatus is provided herein. The switching apparatus includes: (i) a first pole terminal, a second pole terminal and a ground terminal, (ii) a first contact arrangement including a first fixed contact member and a first movable contact member, (iii) a second contact arrangement including a second fixed contact member and a second movable contact member, (iv) a vacuum chamber wherein the second fixed contact and the second movable contact are enclosed and can be coupled or decoupled, and (v) an electrically conductive coupling lever pivoted on the second movable contact member and reversibly movable about a second rotation axis.
US11776777B2	Charging protection and regulation device for electron storage A charging protection and regulation device includes a matrix of Positive Temperature Coefficient (PTC) devices having multiple legs each including one or more PTC devices, a matrix of diodes having multiple legs and multiple types of diodes having different voltage drops, and a matrix of resistors having multiple legs each including a current limiting resistor. Each PTC device is thermally coupled to an ambient environment using a different amount of thermal coupling. Respective legs of the matrix of PTC devices, matrix of diodes, and matrix of resistors are electrically coupled together, and coupled to one or more electron storage devices. During conditions of overload or circuit fault, the PTC devices act as high resistance circuit interrupters. During conditions of light loading between input and output terminals, the different voltage drops across the diodes provide voltage regulation/current regulation such that a specified charge voltage is provided to electron storage devices.
US11776776B2	High power battery disrupter A power circuit breaker has a housing defining a first passage and a cross passage through the housing. A bus bar extends through the cross passage and is configured to transmit electric power and/or break transmission of the electric power through the housing. The bus bar includes at least an input section, a coin or center section, and an output section that are separable from each other. The housing aligns a solenoid piston within the first passage of the housing. The solenoid has a piston with two opposite ends, and one of the ends operates as a plunger to separate the sections of the bus bar when the solenoid is actuated. The plunger moves the coin or center section of the bus bar out of contact with the input section and the output section of the bus bar to break electrical transmission across the bus bar.
US11776771B2	Protection structure of fuse link switch A protection structure is disclosed and is applied in a fuse link switch. The fuse link switch comprises: an insulator, a fuse tube including an upper connection portion and a lower connection portion, an upper-end fixing unit, a lower-end fixing unit, and a toggle mechanism, wherein the upper connection portion is connected with a pull hook. The protection structure comprises at least one electrically insulating shielding layer covering at least one of the upper-end fixing unit, the pull hook, the upper connection portion, the lower connection portion, the lower-end fixing unit, and the toggle mechanism through overmolding technique.
US11776755B2	Multilayer ceramic electronic component A multilayer ceramic electronic component includes a ceramic body having a dielectric layer, and a capacitance forming portion disposed in such a manner that first and second internal electrodes are stacked with the dielectric layer interposed therebetween, and first and second external electrodes disposed on the ceramic body, respectively, the first and second external electrodes including first and second base electrodes connected to the first and second internal electrodes, respectively, and first and second conductive layers disposed to cover the first and second base electrodes, respectively. The first and second conductive layers have a thickness in a range of 0.1 μm to 10 μm.
US11776753B2	Multilayer electronic component and board having the same mounted thereon A multilayer electronic component includes a multilayer capacitor including a capacitor body and a plurality of external electrodes spaced apart from each other on a mounting surface of the capacitor body, and a connection terminal including a plurality of land portions disposed on the plurality of external electrodes, respectively. When a thickness of the multilayer capacitor is defined as T1 and a distance from an uppermost end of the plurality of external electrodes to a bottom of the connection terminal is defined as T2, T1/T2 is 0.6 to 0.9.
US11776751B2	Multilayer ceramic capacitor A multilayer ceramic capacitor includes first dielectric ceramic layers each with a thickness of about 0.48 μm or more and about 0.50 μm or less in the lamination direction, and additional dielectric ceramic layers each with a thickness of about 10 μm or more and about 15 μm or less in the width direction. A number of dielectric particles in each first dielectric ceramic layer in a thickness direction is three or more and six or less. A number of dielectric particles in each additional dielectric ceramic layer in a thickness direction is 100 or more and 150 or less. When the number of dielectric particles in each of first dielectric ceramic layer is NT, and the number of dielectric particles in each additional dielectric ceramic layer is NW, a ratio of NT to NW is about 1:23.08 or more and about 1:46.15 or less.
US11776750B2	Ceramic electronic component A ceramic electronic component includes a body, including a dielectric layer and an internal electrode, and an external electrode disposed on the body and connected to the internal electrode. At least a region of the dielectric layer includes tin (Sn) and a lanthanide rare earth element (RE) including dysprosium (Dy). In the at least a region of the dielectric layer, a molar ratio of tin (Sn) to dysprosium (Dy) is from 0.15 to 0.30.
US11776748B2	Dielectric ceramic composition and multilayer ceramic capacitor comprising the same A dielectric ceramic composition and a multilayer ceramic capacitor including the same are provided. The dielectric ceramic composition includes a BaTiO3-based base material main ingredient and an accessory ingredient, where the accessory ingredient includes dysprosium (Dy) and niobium (Nb) as first accessory ingredients. A total content of the Dy and Nb is greater than 0.2 mol and less than or equal to 1.5 mol based on 100 mol of titanium (Ti) of the base material main ingredient.
US11776743B2	Multilayer capacitor and board having the same mounted thereon A multilayer capacitor includes a capacitor body including a dielectric layer and first and second internal electrodes and having first and second surfaces opposing each other, third and fourth surfaces connected to the first and second surfaces and opposing each other, and fifth and sixth surfaces connected to the first and second surfaces, connected to the third and fourth surfaces, and opposing each other, first and second side portions disposed on the fifth and sixth surfaces of the capacitor body, respectively, and first and second external electrodes disposed on the third and fourth surfaces of the capacitor body, respectively, and connected to the first and second internal electrodes, respectively. The first and second internal electrodes have protrusions at one-side edge in a direction perpendicular to the fifth and sixth surfaces of the capacitor body.
US11776739B2	Ignition coil for internal combustion engine An ignition coil includes a primary coil, a secondary coil, a center core, an outer core, an igniter, a coil case and an electrically-insulative fixation resin. On an interior surface of the coil case on a bottom part side in a mounting direction, there is formed a case-side rib to protrude from the interior surface of the coil case to a high-voltage side in an axial direction. The case-side rib has a taper shape such that the protruding amount of the case-side rib to the high-voltage side in the axial direction increases in the mounting direction toward the bottom part side. The case-side rib is arranged to abut a corner portion of the igniter on the bottom part side in the mounting direction and on a low-voltage side in the axial direction and thereby press the igniter against the outer core.
US11776737B2	Inductor element An inductor element includes a core including a first core portion and a second core portion that are disposed to face each other in a first direction; and a conductor including a first mounting portion and a second mounting portion that are exposed from the core at a predetermined interval therebetween on one side of a second direction orthogonal to the first direction, and a connecting portion which connects the first mounting portion and the second mounting portion and of which at least a part is interposed between the first core portion and the second core portion. The first mounting portion and the second mounting portion are disposed to overlap both of the first core portion and the second core portion as seen from the second direction.
US11776736B2	Electronic package for an electrically small device with integrated magnetic field bias An electronic package includes a mounting platform for mounting an electrically small device, at least one coil, and an insulator. The coil regulates a magnetic field through the electrically small device at the mounting platform. The coil is adapted to conduct a current for nullifying the magnetic field through the electrically small device at the mounting platform. The insulator is between the mounting platform and the coil for isolating the electrically small device from the coil. An electronic circuit includes this electronic package and the electrically small device mounted at the mounting platform of the electronic package. The electrically small device can be a quantum device and/or a topological device when cooled to a cryogenic temperature. The magnetic field is nullified to prevent the magnetic field from adversely affecting the electrically small device.
US11776734B2	Magnetic coupling coil element A coil element according to one embodiment includes: an insulator body including first insulating layers and second insulating layers laminated in a stacking direction; first conductive patterns formed on the first insulating layers; and second conductive patterns formed on the second insulating layers. The insulator body includes a first end region situated at a top in the stacking direction, a second end region situated at a bottom in the stacking direction, and an intermediate region situated between the first end region and the second end region. The insulator body includes a first portion and a second portion that is an area other than the first portion. The first portion covers upper and lower surfaces of one or more intermediate first conductive patterns in the intermediate region among the plurality of first conductive patterns. The electrical resistivity of the first portion is higher than that of the second portion.
US11776732B2	Coil component and switching power supply device mounted with coil component A coil component includes: first and second magnetic cores having first and second flat plate portions; a winding having a hollow core portion; first and second heat dissipation metal plates having first and second heat dissipation plane and first and second heat conduction portions, at least either one of the first and second flat plate portions has a middle leg, the middle leg is inserted into the hollow core portion of a winding, and the first magnetic core and the second magnetic core are combined in such a way that the first flat plate portion and the second flat plate portion face each other, the first heat dissipation plane portion is closely attached to the first flat plate portion and the second heat dissipation plane portion is closely attached to the second flat plate portion, the first heat conduction portion is connected to the second heat conduction portion.
US11776731B2	Reactor Downsized and weight reduced reactor is provided. An annular core 3 includes a first leg 31 and a second leg 32 to which a coil 2 is mounted and which generates magnetic flux, and a pair of yokes 33 which form a closed magnetic path together with the legs. Recess portions 35a is formed at four corners of the annular core 3, and a part of the end surfaces 31a and 32a of the legs which is a magnetic flux generating part or an end surface of the magnetic flux generating part is exposed from the recess portion 35a.
US11776725B2	Magnetic elements of amorphous based dual free layer structures and recording devices using such elements A magnetic element includes a first free layer, a barrier layer over the first free layer, and a second free layer over the barrier layer. The first free layer includes a first ferromagnetic bilayer and a first amorphous insertion layer (e.g., CoHf) between the first ferromagnetic bilayer. The first ferromagnetic bilayer is selected from CoB, CoFeB, FeB, and combinations thereof. The second free layer includes a second ferromagnetic bilayer and a second amorphous insertion layer (e.g., CoHf) between the second ferromagnetic bilayer. The second ferromagnetic bilayer is selected from CoB, CoFeB, FeB, and combinations thereof. Each of the first and the second amorphous insertion layer independently can be ferromagnetic or non-ferromagnetic and can have a recrystallization temperature of about 300° C. and above. The magnetic element can further include a non-ferromagnetic amorphous buffer layer and/or a non-ferromagnetic amorphous capping layer. The magnetic element can further include a ferromagnetic amorphous seed layer.
US11776718B2	Increased resonant frequency potassium-doped hexagonal ferrite Disclosed herein are embodiments of an enhanced resonant frequency hexagonal ferrite material and methods of manufacturing. The hexagonal ferrite material can be Y-phase strontium hexagonal ferrite material. In some embodiments, strontium can be substituted out for a trivalent or tetravalent ion composition including potassium, thereby providing for advantageous properties.
US11776714B2	Device for coating a wire with polymer fibers and method thereof A device for coating a wire with polymer fibers and method thereof are provided. The device includes a wire holder unit fixing both ends of a wire, a fiber forming unit including a first fiber forming module and a second fiber forming module that receive a polymer solution, face each other, and form fibers while approaching each other and retreating from each other, and a control unit adjusting a tension of the wire by controlling the wire holder unit and crossing the wire and the fibers by controlling the fiber forming unit. The fiber forming unit rotates the wire along an axis which extends in a longitudinal direction of the wire. The fibers are attached and coated on the wire when the wire and the fibers cross each other. The wire coating method can improve an adsorption state of coated fibers by including a post-processing step.
US11776709B2	Flexible conductive paste and flexible electronic device A flexible conductive paste and a flexible electronic device are provided, which relate to the technical field of new materials. The flexible conductive paste includes: 3% to 7% by weight of a film former; 20% to 50% by weight of a conductive powder; 25% to 45% by weight of a liquid metal microcapsule; 10% to 30% by weight of a solvent; 0.1% to 5% by weight of a curing agent; and 0.5% to 5% by weight of a functional additive. The wall of the liquid metal microcapsule is a coating resin, the core of the liquid metal microcapsule is a liquid metal. The melting point Tm of the liquid metal satisfies Tm≤T1. The film former has a molecular weight within a range of 15000 to 30000, and has a glass transition temperature Tg smaller than or equal to T1. T1 is a temperature at which the flexible conductive circuit manufactured by the flexible conductive paste is deformed. The flexible conductive circuit of the present disclosure can have better conductivity and better flexibility simultaneously.
US11776705B1	High temperature and high beam current compatible targets and methods thereof for generating noble gas/radiohalogen generators for medical isotopes A method of providing alpha particle emitters and materials suitable for use in generating the alpha particles for medical treatment is disclosed. Metal oxide targets, preferentially Bi2O3 pellets and Bi2O3 coatings on metallic or metal oxide substrates are formed. The targets placed in a heated vacuum chamber subjecting to irradiation using a 6Li beam at an elevated temperature below the melting point of the target generate a radioactive gas, such as 211Rn, the radioactive gas is carried by an inert gas which is delivered a carrier for, such as a carbon column or oil for delivery to a treatment facility. The radioactive gas such as 211Rn generates 211At, which has a useable half-life of at least about 14 hours, in turn releases alpha particles which are effective for use in medical procedures.
US11776701B2	Fission product getter formed by additive manufacturing A getter element includes a getter material reactive with a fission product contained within a stream of liquid and/or gas exiting a fuel assembly of a nuclear reactor. At least one transmission pathway passes through the getter element that is sufficiently sized to maintain a flow of the input stream through the getter element at above a selected flow level. At least one transmission pathway includes a reaction surface area sufficient to uptake a pre-identified quantity of the fission product.
US11776698B2	Virtual telemedicine mechanism Systems and methods related to virtual telemedicine systems, virtual examinations, medical marketplaces, and/or assistance for patient/physicians are provided. The systems can be configured to identify relevant medical service providers based on user-specific information, whether the user has experienced a medical event that may require emergency, urgent, or non-urgent medical services, and/or provide examinations, such as virtual examinations, in person examinations, or hybrid examinations (e.g., both a virtual examination with a first physician and a physical examination with another physician).
US11776695B2	Indicator for probable inheritance of genetic disease Systems, methods and computer-readable media are provided for identification of patients or family member having genetic disease or probable genetic disease. During or after registration of a patient, parents, grandparents, or siblings of the patient are identified. If it is determined that one of the patient or the parents, grandparents, or siblings of the patient has been assigned with a diagnosis indicating a genetic disease, an alert for genetic disease or probable genetic disease for the patient or family member of the patient is provided. A clinician is then prompted to confirm or rule out the patient or family member inheriting the disease.
US11776694B2	Method and system for identifying potential contaminants in test plates Systems and methods are provided for quality control for biological testing. One embodiment is a system that includes a liquid handler that applies samples of genetic material to a test plate comprising an array of wells, a Polymerase Chain Reaction (PCR) device that amplifies the genetic material, and an analysis device that determines, based on a change in visual appearance of each well, a numerical value indicating whether a corresponding sample is representative of a disease state. The system also includes a quality assurance server that identifies a pattern of the numerical values, and determines a likelihood of the pattern. In an event that the likelihood is less than a threshold value, the quality assurance server flags the test plate as potentially contaminated, and in an event that the likelihood exceeds the threshold value, the quality assurance server refrains from flagging the test plate as potentially contaminated.
US11776693B2	Conversational services for artificial intelligence health support A system provides artificial intelligence health support for people. The system renders specific, targeted treatments for people by using a flow engine and a conversational service to call one or more conversational modules. The treatments for the people may be tracked. The flow engine and/or one or more of the modules may include different instructions to perform for different programs and/or goals that have been configured. The flow engine and/or one or more of the conversational modules may also include instructions to perform when certain features are active (which may be activated when certain programs and/or goals are configured), when data regarding activity for people are received, and so on. Other modules may be dedicated to particular programs and/or goals. Some modules may determine whether or not to perform various instructions repetitiously, and/or may determine to do so when a priority of a previous instruction is below a threshold.
US11776691B2	Machine learning based depolarization identification and arrhythmia localization visualization Techniques that include applying machine learning models to episode data, including a cardiac electrogram, stored by a medical device are disclosed. In some examples, based on the application of one or more machine learning models to the episode data, processing circuitry derives, for each of a plurality of arrhythmia type classifications, class activation data indicating varying likelihoods of the classification over a period of time associated with the episode. The processing circuitry may display a graph of the varying likelihoods of the arrhythmia type classifications over the period of time. In some examples, processing circuitry may use arrhythmia type likelihoods and depolarization likelihoods to identify depolarizations, e.g., QRS complexes, during the episode.
US11776689B2	Field update of an ambulatory infusion pump system Portable or ambulatory infusion devices and systems capable of remotely updating an ambulatory fluid delivery device include safety protocols that verify the status of the ambulatory fluid delivery device before and after a field update of software. Methods of accomplishing the same field update of software are also described.
US11776688B2	Capturing user constructed map of bodily region of interest for remote telemedicine navigation A computer-implemented method for capturing a user constructed map of bodily region of interest for remote telemedicine navigation includes receiving, by a user-device, a request for capturing data for constructing a model of the bodily region using a designated capture-device. The method further includes generating, by the user-device, a visual feedback for capturing the data. Generating the visual feedback includes displaying a representation of the bodily region, and modulating, in response to the capture-device scanning the bodily region, the representation with a first indicator that indicates a duration to maintain a position of the capture-device. Generating the visual feedback includes further modulating, in response to completion of scanning the bodily region, the representation with a second indicator that indicates completion of the scan. The method further includes constructing, by the user-device, the model of the bodily region using data that is acquired by the capture-device by scanning the bodily region.
US11776687B2	Medical examination of human body using haptics An electronic apparatus and method for medical examination of human body using haptics is provided. The electronic apparatus controls a first head-mounted display to render a 3D model of an anatomical portion of the body of a human subject. The rendered 3D model includes a region corresponding to defect portion in the anatomical portion. The electronic apparatus transmits a touch input to wearable sensor in contact with the anatomical portion. Such an input corresponds to a human touch on the region of the rendered 3D model. The electronic apparatus receives, based on the touch input, bio-signals associated with the defect portion via the wearable sensor. The bio-signals include physiological signals and somatic sensation information associated with the defect portion. As a response to the human touch, the electronic apparatus controls a wearable haptic device to generate a haptic feedback based on the received set of bio-signals.
US11776684B2	Method and device for managing energy usage by a medical device A medical device and method are provided. The medical device includes a battery, a charge bank configured to store supplemental energy, memory to store program instructions, and device operational circuitry. The device operational circuitry identifies an energy demand (ED) action to be performed by the device operational circuitry in connection with at least one of monitoring a medical characteristic of interest (COI), treating the medical COI, or wirelessly communicating with a separate device. The device operational circuitry obtains an energy consumption estimate for an amount of energy to be consumed by the device operational circuitry in connection with performing the ED action and dispatches a charge instruction to charge the charge bank from the battery with supplemental energy. The device operational circuitry supplies the supplemental energy to the device operational circuitry for performing the ED action in connection with the at least one of monitoring, treating or communicating operations.
US11776680B2	Method and system for real-time and offline de-identification of facial regions from regular and occluded color video streams obtained during diagnostic medical procedures Systems and techniques that facilitate real-time and/or offline de-identification of facial regions from regular and/or occluded color video streams obtained during diagnostic medical procedures are provided. A detection component can generate a bounding box substantially around a person in a frame of a video stream, can generate a heatmap showing key points or anatomical masks of the person based on the bounding box, and can localize a face or facial region of the person based on the key points or anatomical masks. An anonymization component can anonymize pixels in the frame that correspond to the face or facial region. A tracking component can track the face or facial region in a subsequent frame based on a structural similarity index between the frame and the subsequent frame being above a threshold. If the structural similarity index between the frame and the subsequent frame is above the threshold, the tracking component can track the face or facial region in the subsequent frame without having the detection component generate a bounding box or a heatmap in the subsequent frame, and the anonymization component can anonymize pixels in the subsequent frame corresponding to the tracked face or facial region.
US11776676B2	Apparatus and associated methods for determining exercise settings An apparatus comprising means configured to: determine, based on data representative of a current health state of a first user of a first exercise apparatus, settings for one or more exercise variables of the first exercise apparatus, wherein the settings are tailored to the first user's current health state; and provide the determined settings for configuration of the first exercise apparatus.
US11776673B2	System and method for augmented reality detection of loose pharmacy items A method includes capturing, by an image-capturing device, a one or more images of at least a portion of a pharmacy workstation. The method also includes identifying, by a processor in communication with the image capturing device, objects of interest in a first image of the one or more images and classifying, by the processor, the detected objects of interest using a convolutional neural network associated with the processor. The method also includes identifying, by the processor, a boundary defining an opening of a container in a second image of the one or more images. The method also includes updating, by the processor, an objects in container list based on a determination that at least one of the classified objects passed the boundary.
US11776671B2	Electronic patient monitoring system An electronic patient monitoring system comprising a monitoring client and a remote communicator are provided. The monitoring client is configured to store patient information. The patient information may be patient-specific information. The monitoring client may receive the information from a database, e.g., through a monitoring server.
US11776668B2	Capturing person-specific self-reported subjective experiences as behavioral predictors Disclosed methodologies provide improved predictors of patient treatment adherence by using person-specific subjective experience and social-environmental factors. Methodologies combine emotion and data sciences. Advanced tools capture, measure, store, and analyze self-report of subjective experiences using digital applications and platforms. Patient-specific data is obtained regarding emotional or affective determinants and social determinants for generating a calculated composite score of the patient's probability of adherence or achievement relative to target outcomes, e.g. adherence to treatment plans, wellness activities, etc. for a subject individual. Internal/subjective factors are judged by self-report measures designed to validly judge tested factors based on a patient adjusting continuously-variable graphical interfaces to capture and measure subjective experiences. Emotional characteristics may include perception and intensity in each category of sickness versus wellness, stress, depression, anxiety, pain, and feelings about most recent health provider/staff interaction (with determined intensity for choices of Delighted, Satisfied, Meh, Disappointed, Frustrated). Emotional characteristics may be considered among health, and social characteristics in measuring potential obstacles to adherence.
US11776666B2	Simulating electronic structure with quantum annealing devices and artificial neural networks Approaches, techniques, and mechanisms are disclosed for predicting molecular electronic structural information. According to one embodiment, quantum simulation results are generated for a molecule based on a quantum simulation of an electronic structure of the molecule. The quantum simulation of the electronic structure of the molecule is performed with quantum processing units. An input vector comprising data field values derived from the quantum simulation results for the molecule is created. An electronic structural information prediction model is applied to generate, based at least in part on the input vector, predicted electronic structural information for the molecule.
US11776665B2	Method for determining the average deuterium substitution rate The present disclosure relates to a method for analysis of an average deuterium substitution rate of a deuterium-substituted sample using information of a 1H-NMR spectrum of the deuterium-substituted sample.
US11776662B2	Finding relatives in a database Determining relative relationships of people who share a common ancestor within at least a threshold number of generations includes: receiving recombinable deoxyribonucleic acid (DNA) sequence information of a first user and recombinable DNA sequence information of a plurality of users; processing, using one or more computer processors, the recombinable DNA sequence information of the plurality of users in parallel; determining, based at least in part on a result of processing the recombinable DNA information of the plurality of users in parallel, a predicted degree of relationship between the first user and a user among the plurality of users, the predicted degree of relative relationship corresponding to a number of generations within which the first user and the second user share a common ancestor.
US11776660B2	Information processing apparatus, suspect information generation method and program An information processing apparatus includes an input, a blood-relative list generator, a similar image searcher, and a suspect information generator. The input receives DNA information of a suspect and facial image relating to a plurality of facial images. The blood relative list generator generates a list of blood relatives who are presumed to be blood relatives of the suspect from a plurality of pieces of DNA information. The similar image searcher calculates degree of similarity between facial images of persons on the blood-relative list and each of the plurality of facial images, and searches for and retrieves a facial image resembling the image of the person on the blood-relative list based on the calculated degree of similarity. The suspect information generation part generates suspect information by associating information relating to the retrieved facial image with information relating to the person on the blood-relative list who resembles the retrieved facial image.
US11776658B2	Computational analysis of biological data using manifold and a hyperplane A method of analyzing biological data containing expression values of a plurality of polypeptides in the blood of a subject. The method comprises: calculating a distance between a segment of a curved line and an axis defined by a direction, the distance being calculated at a point over the curved line defined by a coordinate along the direction. The method further comprises correlating the distance to the presence of, absence of, or likelihood that the subject has, a bacterial infection. The coordinate is defined by a combination of the expression values, wherein at least 90% of the segment is between a lower bound line and an upper bound line.
US11776655B2	Memory device virtual blocks using half good blocks Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).
US11776651B2	Controlling memory including managing a correction value table A memory system according to an embodiment includes a memory device, and a memory controller. The memory device includes first and second memory cells, a first word line, and first and second bit lines. The first and second memory cells are provided in first and second layers, respectively. The first word line is coupled to the first memory cell and the second memory cell. The first bit line is coupled to the first memory cell. The second bit line is coupled to the second memory cell. The memory controller includes a storage circuit capable of storing a correction value table. The correction value table is configured to store a first correction value of a read voltage associated with the first layer and a second correction voltage of a read voltage associated with the second layer.
US11776650B2	Memory calibration device, system and method A memory calibration system includes a memory array having a plurality of memory cells, a sensing circuit coupled to the memory array, and calibration circuitry. A pattern of test data is applied to the memory array in order to generate calibration information based on output provided by the first sensing circuit in response to the application of the pattern of test data to the memory array. The generated calibration information is stored in a distributed manner within memory cells of the memory array. Some of the generated calibration information may be combined with data values stored in the plurality of memory cells as part of one or more operations on the stored data values. The stored data values may be stored in an in-memory compute cluster of the memory array, such that operations on the stored data values include combining the multiple data values of the in-memory compute cluster with at least a portion of the generated calibration information as at least part of an in-memory compute operation for the in-memory compute cluster.
US11776649B2	Method for generating an memory built-in self-test algorithm circuit A method for generating a memory built-in self-test circuit includes steps of providing an editable file, wherein the editable file configured to be edited by a user to customize a memory test algorithm; performing a syntax parsing on the editable file to obtain the memory test data, wherein the memory test data being corresponding to the memory test algorithm; and generating the memory built-in self-test circuit based on the memory test data.
US11776648B2	Circuit for testing memory A test circuit for testing a memory is provided. The input of the memory is coupled to a register, and the register is coupled to a logic circuit. The test circuit includes a first test register group, a second test register group, a first multiplexer, and multiple second multiplexers. The first test register group includes at least one test register. The second test register group includes at least one test register. The first multiplexer is coupled between the first test register group and the register. The second multiplexers are coupled between the second test register group and the register.
US11776645B2	Stacked electronic device capable of retaining an analog potential An electronic device applicable to an artificial neuron network. The electronic device includes a first circuit, a second circuit, and first to sixth wirings. The first circuit includes a first transistor, a second transistor, and a capacitor. The second circuit includes a third transistor. A gate of the third transistor is electrically connected to the third wiring. The capacitor capacitively couples the third wiring and the gate of the second transistor. The first circuit is capable of storing a weight as an analog value. The first transistor is typically an oxide semiconductor transistor.
US11776642B2	Memory device including massbit counter and method of operating the same A method of operating a memory device that includes a plurality of stages each having a plurality of page buffers. The method including performing a verify operation of a first program loop from among a plurality of program loops, the verify operation of the first program loop including, performing a first off-cell counting operation on a first stage of the plurality of stages based on a first sampling rate to generate a first off-cell counting result; selectively changing the first sampling rate based on the first off-cell counting result to generate a changed first sampling rate; and performing a second off-cell counting operation on a second stage of the plurality of stages based on one of the first sampling rate and the changed first sampling rate to generate a second off-cell counting result.
US11776636B2	Memory array and operation method thereof A memory array and its operation method are provided. The array includes plural sets of word lines; plural bit lines; and plural memory cell each arranged at intersection of the plural sets of word lines and the plural bit lines. Each memory cell has first and second conductive filament component and a switch circuit, and one ends of the first and the second conductive filament components are coupled to corresponding bit lines and the other ends thereof are coupled to the switch circuit. In the differential mode, read is performed based on the reading currents of the first and the second conductive filament components. In the single-ended mode, read is performed based on a reference current and a reading current of the first or the second conductive filament component that is formed successfully.
US11776630B2	Memory device performing incremental step pulse program operation and operating method thereof A memory device comprises a memory cell array and a control circuit. The control circuit applies a pass voltage to each of a selected and unselected word line from a first to second time point whenever a program loop is performed once. Then, the control circuit applies a program voltage to the selected word line and the pass voltage to the unselected word line from the second to third time point, performs a bit line precharge operation from a fourth time point ahead of the first time point to the second time point when a first program loop is performed, and performs the bit line precharge operation from the fourth time point to a fifth time point, which is the same as or ahead of the first time point, when the other program loops are performed.
US11776628B2	Systems and methods for adjusting threshold voltage distribution due to semi-circle SGD The following disclosure is directed to mitigating issues related to semi-circle drain side select gate (SC-SGD) memory holes in memory structures. When a memory hole is cut, the channel and the charge trap layer of the memory hole cut. Further, the outer dielectric layer (used to shield the channel and the charge trap layer) is cut and partially removed. When the selected SC-SGD is selected for an operation (e.g., programming), the channel and the charge trap layer are exposed to neighboring electrical field from bias voltage applied to an unselected SC-SGD. To prevent or mitigate the effects of this electrical field, a negative bias voltage is applied to the unselected SC-SGD. Additionally, this disclosure is directed to self-compensating techniques for SC-SGD. For example, the memory structure can utilize the neighboring electric field during verify, program, and read operations, whether the neighboring electric field is relatively strong or weak.
US11776626B2	Selector device for two-terminal memory Disclosed is a solid state memory having a non-linear current-voltage (I-V) response. By way of example, the solid state memory can be used as a selector device. The selector device can be formed in series with a nonvolatile memory device via a monolithic fabrication process. Further, the selector device can provide a substantially non-linear I-V response suitable to mitigate leakage current for the nonvolatile memory device. In various disclosed embodiments, the series combination of the selector device and the non-volatile memory device can serve as one of a set of memory cells in a 1-transistor, many-resistor resistive memory cell array.
US11776625B2	Boost-assisted memory cell selection in a memory array Systems, methods, and apparatus related to selecting memory cells in a memory array of a memory device. In one approach, bias circuitry generates a voltage on an access line used to select a memory cell for programming. During programming, a controller connects a boost capacitor to the access line by controlling a switch. Connecting the boost capacitor causes an increase in the rate of discharge of the access line (e.g., discharge of a word line to a negative voltage). After programming, the controller disconnects the boost capacitor from the access line, and the boost capacitor is pre-charged in preparation for a next programming operation (e.g., on the same or a different memory cell).
US11776623B2	Bitline precharge system for a semiconductor memory device A bitline precharge system is provided for a semiconductor memory device. The bitline precharge system comprises a voltage comparator circuit to output a reference voltage signal based on an input wordline voltage supply level (VDDWL), and a periphery power supply voltage (VDDP) level. A voltage control circuit is electrically coupled to a periphery power supply and the voltage comparator circuit to output a precharge voltage (VDDM) level based on the reference voltage signal and the periphery power supply voltage (VDDP) level. A bitline precharge circuit is electrically coupled to the voltage control circuit and a plurality of bitlines of the memory device to precharge the plurality of bitlines based on the precharge voltage (VDDM) level in response to a precharge enable signal during one of a read operation to read data from the memory device and a write operation to write data from the memory device. Further, the at least one bitline is discharged from the precharge voltage (VDDM) level during at least one of the read operation or the write operation.
US11776621B2	Memory device for increasing write margin during write operation and reducing current leakage during standby operation and operation method thereof A memory device and an operation method thereof is disclosed. The memory device includes a SRAM cell and a power supply assist circuit connected to the SRAM cell. The power supply assist circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor receives a power supply voltage. The control terminals of the first transistor and the second transistor are connected to each other. The third transistor switches, in response to a first control signal, to connect the control terminal and the connect terminal of the second transistor. The fourth transistor switches, in response to a second control signal, to drive the control terminal of the second transistor to a system ground voltage. The fifth transistor switches, in response to a third control signal, to drive the control terminal of the first transistor to the power supply voltage.
US11776619B2	Techniques to couple high bandwidth memory device on silicon substrate and package substrate Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.
US11776618B2	Memory device with in-memory searching array and operation method thereof for implementing finite state machine The present invention discloses a memory device and operation method thereof. The operation method comprises: programming a plurality of first strings of a plurality of string pairs representing a finite state machine (FSM) to an in-memory-searching (IMS) array of a memory device; programming a plurality of second strings of the string pairs to a working memory of the memory device; and programming a string representing a starting state of the FSM to a buffer of the memory device.
US11776617B2	Application processors and electronic devices including the same An application processor includes a memory interface and a memory controller. The memory interface is connected to a semiconductor memory device through first data input/output (I/O) pads and second data I/O pads. The memory controller exchanges data with the semiconductor memory device by controlling the memory interface. The memory interface includes a training circuit to perform duty training of first data signals and second data signals by adjusting a duty of each of the first data signals with respect to a first reference voltage and adjusting a duty of each of the second data signals with respect to a second reference voltage.
US11776616B2	DRAM memory device with oxide semiconductor access transistor and method of controlling plate line potential A semiconductor memory device includes a memory cell that includes a capacitor including a first and second end and a first transistor. The first transistor includes a third and fourth end, is coupled to the first end at the fourth end, and contains an oxide semiconductor. A bit line is coupled to the third end. A sense amplifier is coupled to the bit line and coupled between a first node of a first potential and a second node of a second potential lower than the first potential. A potential generator is configured to supply the second end with a fourth potential that is different from a third potential intermediate between the first potential and the second potential.
US11776614B2	Memory system, data processing system and method of operating the same A data processing system may include a plurality of memory modules, a controller, a power supply and a plurality of switches. Each of the memory modules may include a plurality of pages. The controller may control operations of the memory modules. The power supply may provide the memory modules with a power. The switches may be arranged corresponding to each of the memory modules. The switches may be selectively driven in response to a switch drive signal from the controller.
US11776604B2	Magnetic recording array and magnetoresistance effect unit A magnetic recording array includes a plurality of units. Each unit has a first magnetoresistance effect element, second magnetoresistance effect element, and writing transistor. Each of the first magnetoresistance effect element and the second magnetoresistance effect element has a wiring and a laminate which is laminated on the wiring. The writing transistor is connected to each of the wiring of the first magnetoresistance effect element and the wiring of the second magnetoresistance effect element. The wiring of the first magnetoresistance effect element and the wiring of the second magnetoresistance effect element are electrically connected in series at the time of writing, and a writing current flows through each of the wirings. A direction of a writing current flowing in the wiring of the first magnetoresistance effect element and a direction of a writing current flowing in the wiring of the second magnetoresistance effect element are opposite to each other.
US11776597B2	Memory subsystem calibration using substitute results A memory subsystem and method for performing calibrations therein is disclosed. A memory subsystem includes a memory controller coupled to a memory by a plurality of signal paths. The memory controller is configured to perform an initial calibration to determine respective eye patterns corresponding to the ones of the plurality of signal paths. For a subsequent calibrations, updated eye patterns are determined for a subset of the plurality of signal paths. Remaining ones of the plurality of signal paths (not included in the subset), are not active during the subsequent calibrations. Updated eye patterns for the remaining ones of the plurality of signal paths are determined based on information obtained during the initial calibration and information from signal paths in the subset designated proxies for the remaining ones of the plurality of signal paths.
US11776594B2	Scalable in situ DRAM-based accelerators and methods of operating the same Apparatus includes a plurality of memory cells (e.g., a dynamic random access memory (DRAM)) addressable as rows and columns and a plurality of matching circuits configured to be coupled to respective bit lines associated with the columns A control circuit is configured to store respective reference sequences (e.g., binary-encoded k-mer patterns) in respective ones of the columns, to sequentially provide rows of bits stored in the memory cells and bits of a query to the matching circuits, and to identify one of the reference sequences as corresponding to the query responsive to comparisons by the matching circuits.
US11776591B2	Concurrent access techniques utilizing wordlines with the same row address in single port memory Various implementations described herein refer to a method for providing single port memory with multiple different banks having a first bank and a second bank that is different than the first bank. The method may include coupling multiple wordlines to the single port memory including coupling a first wordline to the first bank and coupling a second wordline to the second bank. The method may include performing multiple memory access operations concurrently in the single port memory.
US11776590B2	On-the-fly programming and verifying method for memory cells based on counters and ECC feedback The present invention relates to a method of operating memory cells, comprising reading a previous user data from the memory cells; writing a new user data and merging the new user data with the previous user data into write registers; generating mask register information, and wherein the mask register information indicates bits of the previous user data stored in the memory cells to be switched or not to be switched in their logic values; counting numbers of a first logic value and a second logic value to be written using the mask register information, respectively; storing the numbers of the first logic value and the second logic value into a first counter and a second counter, respectively; and applying a programming pulse to the memory cells according to the mask register information.
US11776588B2	Sense amplifier and semiconductor memory device including the sense amplifier A sense amplifier includes a bit line sense amplifier including a first transistor and a second transistor spaced apart from each other in a first direction, a second conductive line configured to electrically connect the first transistor to the second transistor and extending in the first direction and a local sense amplifier configured to at least partially overlap the second conductive line and disposed between the first transistor and the second transistor. The local sense amplifier includes an active region, a plurality of gate patterns at least partially extending in the first direction and disposed on the active region, a first contact disposed between the plurality of gate patterns and including a long side extending in the first direction and a short side extending in a second direction crossing the first direction and a first conductive line electrically connected to the first contact while overlapping the first contact in a plan view and including a first conductive region extending in the first direction.
US11776585B2	Memory device including a pass transistor circuit and a discharge transistor circuit A memory device includes a pass transistor circuit included in a first wafer, and configured to transfer an operating voltage to row lines of a memory cell array; and a discharge transistor circuit included in a second wafer that overlaps with the first wafer in a vertical direction, and configured to transfer a discharge voltage to at least one of the row lines.
US11776583B2	Semiconductor memory devices A semiconductor memory device includes a plurality of bit line structures including bit lines extending in parallel in a first lateral direction on a substrate, and a plurality of buried contacts and a plurality of landing pads. The plurality of buried contacts fill lower portions of spaces between the plurality of bit line structures on the substrate, and the plurality of landing pads fill upper portions of the spaces between the plurality of bit line structures and extend on the plurality of bit line structures. The plurality of landing pads have a hexagonal array structure, and central points of respective top surfaces of a first landing pad, a second landing pad, and a third landing pad, which are adjacent to each other from among the plurality of landing pads, are connected by a scalene triangle.
US11776580B2	Systems and methods for protocol for animated read along text A system and method for displaying emphasized text are described. A line of text having multiple words is displayed successively emphasized at the pace of human speech. Each of the words is displayed in a first state. The emphasized word is then displayed in a second state as having an outline. Next, the emphasized word is displayed in a third state as heavier-weighted text. Finally, the emphasized word is displayed in a fourth state as regular text. The words are visually emphasized one at a time such that a first word is displayed in the third state when a second word is displayed in the second state and the first word is displayed from the third state to the fourth state when the second word is displayed from the second state to the third state and a third word is displayed in the second state.
US11776579B2	Scene and activity identification in video summary generation Video and corresponding metadata is accessed. Events of interest within the video are identified based on the corresponding metadata, and best scenes are identified based on the identified events of interest. A video summary can be generated including one or more of the identified best scenes. The video summary can be generated using a video summary template with slots corresponding to video clips selected from among sets of candidate video clips. Best scenes can also be identified by receiving an indication of an event of interest within video from a user during the capture of the video. Metadata patterns representing activities identified within video clips can be identified within other videos, which can subsequently be associated with the identified activities.
US11776577B2	Camera tracking system for live compositing A 3D camera tracking and live compositing system includes software and hardware integration and allows users to create, in conjunction with existing programs, live composite video. A video camera, a tracking sensor, encoder, a composite monitor, and a software engine and plugin receive video and data from and integrate it with existing programs to generate real time composite video. The composite feed can be viewed and manipulated by users while filming. Features include 3D masking, depth layering, teleporting, axis locking, motion scaling, and freeze tracking. A storyboarding archive can be used to quickly load scenes with the location, lighting setups, lens profiles and other settings associated with a saved a photo. The video camera's movements can be recorded with video to be later applied to other 3D digital assets in post-production. The system also allows users to load scenes based on a 3D data set created with LIDAR.
US11776574B2	Authenticating digital recordings Techniques for authentication of digital recordings are provided. An element of encrypted data is output in a recording environment. The element of encrypted data, embedded in a digital recording comprising at least one of audio data and image data captured in the recording environment, is extracted. A decrypted value is generated based on a private key and the first element of encrypted data, and the first decrypted value and a stored value associated with a first element of the digital recording are compared. The digital recording is authenticated based on the first decrypted value substantially matching the stored value.
US11776573B2	Magnetic disk device and method for measuring counter electromotive voltage of spindle motor According to an embodiment, a magnetic disk device includes a magnetic disk, a spindle motor that rotates the magnetic disk, a motor driver, and a controller. The motor driver supplies a motor current to the spindle motor and measures a counter electromotive voltage of the spindle motor every time the spindle motor makes one rotation. After the rotation of the magnetic disk starts, the controller adjusts a motor position where the counter electromotive voltage is measured to a set first position.
US11776572B2	Magnetic tape having alternating sections for use in ultra-high areal density tape storage systems The present disclosure generally relates to a tape utilized with a tape drive including a tape head. The tape comprises a plurality of writeable portions configured to store data and a plurality of non-writeable portions that are unable to store data. The writeable portions comprise one or more materials selected from the group consisting of: Ru, Pt, Ta, and Co, and the non-writeable portions comprise a different material than the writeable portions. Each writeable portion is defined between two non-writeable portions, and each writeable portion has a greater area on the tape than each non-writeable portion. The non-writeable portions are utilized during stop-start and turn-around operations of the tape head, are configured to lubricate the tape head, clean the tape head, and remove debris from the tape head. The non-writeable portions enable improved performance of the tape drive while reducing a cost of the tape.
US11776567B2	SOT film stack for differential reader The present disclosure generally relates to spin-orbital torque (SOT) differential reader designs. The SOT differential reader is a multi-terminal device comprising a first seed layer, a first spin hall effect (SHE) layer, a first interlayer, a first free layer, a gap layer, a second seed layer, a second SHE layer, a second free layer, and a second interlayer. The gap layer is disposed between the first SHE layer and the second SHE layer. The materials and dimensions used for the first and second seed layers, the first and second interlayers, and the first and second SHE layers affect the resulting spin hall voltage converted from spin current injected from the first free layer and the second free layer, as well as the ability to tune the first and second SHE layers. Moreover, the SOT differential reader improves reader resolution without decreasing the shield-to-shield spacing (i.e., read-gap).
US11776565B2	Tape head with side-shielded writers and process for making same The present disclosure generally relates to a tape head of a tape drive, and methods of forming thereof. In one embodiment, a tape head for magnetic storage devices comprises a trailing shield, a leading shield, a first write pole coupled to the trailing shield, a second write pole coupled to the leading shield, and side shields spaced from the first write pole and the second write pole by a thin insulation layer. The side shields are further disposed between the trailing shield and the leading shield. In another embodiment, a tape head for magnetic storage devices comprises a main pole disposed between a trailing shield and a leading shield and a side shield disposed adjacent to the main pole. The side shield is further disposed between the trailing shield and the leading shield and spaced from the main pole by a thin insulation layer.
US11776564B2	Memory device A memory device including at least one channel and a fluid including particles is provided. In one aspect, the channel includes a least some of the fluid. The memory device may further include an actuator configured to induce a movement of the particles in the channel; and a writing element configured to arrange the particles in a sequence, thereby yielding a sequence of particles in the channel. The particles may include first particles and second particles. The particles may be in a first state or a second state in the channel. In certain aspects, the channel is configured to preserve the sequence of the particles. The memory device may further include a reading element for detecting the sequence of the particles in the channel.
US11776561B2	Diagnostic techniques based on speech models A method includes obtaining one or more speech models, each model including one or more acoustic states and, provided that the model includes multiple acoustic states, allowed transitions therebetween. The method further includes receiving a speech sample produced by a subject while a physiological state of the subject was unknown. The method further includes mapping at least one sample portion of the speech sample to a respective one of the speech models, by computing a plurality of feature vectors quantifying acoustic features of different respective portions of the sample portion, and mapping the feature vectors to respective acoustic states included in the speech model such that a total distance between the feature vectors and the respective acoustic states is minimized. The method further includes, in response to mapping the sample portion to the speech model, communicating an output indicating the physiological state of the subject. Other embodiments are also described.
US11776559B2	Determining subtitle synchronization when compared to audio track According to at least one embodiment, a method for determining a level of synchronicity between subtitle text in audiovisual content and speech that would be heard during display of the audiovisual content includes: accessing a first binary sequence, each bit of the first binary sequence indicating whether the speech is provided at a respective sampling time of a plurality of sampling times; and accessing a second binary sequence, each bit of the second binary sequence indicating whether the subtitle text is provided at a respective sampling time of a plurality of sampling times. The method further includes comparing the first binary sequence and the second binary sequence to determine the level of synchronicity between the subtitle text and the speech.
US11776558B1	Systems and methods for generating and/or implementing a modified audiogram An exemplary system includes a processor communicatively coupled to a memory and configured to execute instructions to generate a modified audiogram for a user of a hearing device. The modified audiogram may be based on a frequency lowering scheme that maps at least some audio frequencies included in a first set of audio frequencies to relatively lower audio frequencies to form a second set of audio frequencies. The modified audiogram may indicate a set of modified hearing thresholds of the user at the first set of audio frequencies. The generating of the modified audiogram may include applying an inverse of the frequency lowering scheme to the set of modified hearing thresholds at the second set of audio frequencies to obtain the set of modified hearing thresholds of the modified audiogram at the first set of audio frequencies.
US11776556B2	Unified deep neural network model for acoustic echo cancellation and residual echo suppression A method, computer program, and computer system is provided for an all-deep-learning based AEC system by recurrent neural networks. The model consists of two stages, echo estimation stage and echo suppression stage, respectively. Two different schemes for echo estimation are presented herein: linear echo estimation by multi-tap filtering on far-end reference signal and non-linear echo estimation by single-tap masking on microphone signal. A microphone signal waveform and a far-end reference signal waveform are received. An echo signal waveform is estimated based on the microphone signal waveform and a far-end reference signal waveform. A near-end speech signal waveform is output based on subtracting the estimated echo signal waveform from the microphone signal waveform, and echoes are suppressed within the near-end speech signal waveform.
US11776554B2	Audio processor and method for generating a frequency enhanced audio signal using pulse processing An audio processor for generating a frequency enhanced audio signal from a source audio signal has: an envelope determiner for determining a temporal envelope of at least a portion of the source audio signal; an analyzer for analyzing the temporal envelope to determine temporal values of certain features of the temporal envelope; a signal synthesizer for generating a synthesis signal, the generating having placing pulses in relation to the determined temporal values, wherein the pulses are weighted using weights derived from amplitudes of the temporal envelope related to the temporal values, where the pulses are placed; and a combiner for combining at least a band of the synthesis signal that is not included in the source audio signal and the source audio signal to obtain the frequency enhanced audio signal.
US11776552B2	Methods and apparatus for decoding encoded audio signal(s) There are provided decoding and encoding methods for encoding and decoding of multichannel audio content for playback on a speaker configuration with N channels. The decoding method comprises decoding, in a first decoding module, M input audio signals into M mid signals which are suitable for playback on a speaker configuration with M channels; and for each of the N channels in excess of M channels, receiving an additional input audio signal corresponding to one of the M mid signals and decoding the input audio signal and its corresponding mid signal so as to generate a stereo signal including a first and a second audio signal which are suitable for playback on two of the N channels of the speaker configuration.
US11776549B2	Multi-factor audio watermarking Techniques are described herein for multi-factor audio watermarking. A method includes: receiving audio data; processing the audio data to generate predicted output that indicates a probability of one or more hotwords being present in the audio data; determining that the predicted output satisfies a threshold that is indicative of the one or more hotwords being present in the audio data; in response to determining that the predicted output satisfies the threshold, processing the audio data using automatic speech recognition to generate a speech transcription feature; detecting a watermark that is embedded in the audio data; and in response to detecting the watermark: determining that the speech transcription feature corresponds to one of a plurality of stored speech transcription features; and in response to determining that the speech transcription feature corresponds to one of the plurality of stored speech transcription features, suppressing processing of a query included in the audio data.
US11776547B2	System and method of video capture and search optimization for creating an acoustic voiceprint Systems and method of diarization of audio files use an acoustic voiceprint model. A plurality of audio files are analyzed to arrive at an acoustic voiceprint model associated to an identified speaker. Metadata associate with an audio file is used to select an acoustic voiceprint model. The selected acoustic voiceprint model is applied in a diarization to identify audio data of the identified speaker.
US11776543B2	Authentication system, authentication method, and, non-transitory computer-readable information recording medium for recording program An authentication system prevents leakage of a key-reading speech during user authentication based on the key-reading speech of a user reading an authentication key. For each user ID, a storage stores a voiceprint of a user in association with a recorded sound including speech spoken previously by the user. A specifier specifies the user ID of a user attempting to receive authorization. An outputter outputs a masking sound that includes the recorded sound recorded in association with the specified user ID. An acquirer acquires a key-reading speech of the user reading the authentication key and the output masking sound. A remover acquires a second sound by removing the masking sound from the acquired first sound. A determiner determines whether the user has authority pertaining to the specified user ID based on the acquired second sound.
US11776541B2	Communicating announcements Techniques for synchronizing communication across devices are described. A system receives an input command corresponding to an announcement and sends data representing the announcement to devices of the system. The system receives responses from the devices and causes the device that originated the announcement to output content corresponding to the responses.
US11776540B2	Voice control of remote device A system configured to enable remote control to allow a first user to provide assistance to a second user. The system may receive a command from the second user granting remote control to the first user, enabling the first user to initiate a voice command on behalf of the second user. In some examples, the system may enable the remote control by treating a voice command originating from the first user as though it originated from the second user instead. For example, the system may receive the voice command from a first device associated with the first user but may route the voice command as though it was received by a second device associated with the second user.
US11776537B1	Natural language processing system for context-specific applier interface A computer-implemented method is provided to optimize natural language processing of voice interaction data in product/service categorization and product/service application. The computer-implemented method receives, from a voice interaction device through a context discovery interface, user voice data corresponding to a user. Furthermore, the computer-implemented method performs, with an NLP engine, natural language processing of the user voice data to determine a context category. Additionally, the computer-implemented method selects, with an AI engine, one of a plurality of context-specific applier interfaces based on the context category. The computer-implemented method automatically transitions, with the AI engine, to said one of the plurality of context-specific applier interfaces. Finally, the computer-implemented method interacts, via the AI engine, with the user via a voice interaction to initiate the product/service application.
US11776533B2	Building a natural language understanding application using a received electronic record containing programming code including an interpret-block, an interpret-statement, a pattern expression and an action statement A method of building a natural language understanding application is provided. The method includes receiving at least one electronic record containing programming code and creating executable code from the programming code. Further, the executable code, when executed by a processor, causes the processor to create a parse and an interpretation of a sequence of input tokens, the programming code includes an interpret-block and the interpret-block includes an interpret-statement. Additionally, the interpret-statement includes a pattern expression and the interpret-statement includes an action statement.
US11776529B2	Method and apparatus with speech processing A method, the method includes determining a target segment partially overlapping a preceding segment from a speech signal, determining a target character sequence corresponding to the target segment by decoding the target segment, identifying a first overlapping portion between the target character sequence and a preceding character sequence based on an edit distance, and merging the target character sequence and the preceding character sequence based on the first overlapping portion. A cost applied to the edit distance is determined based on any one or any combination of any two or more of a type of operation performed at the edit distance, whether characters to be operated are located in the first overlapping portion, and whether the characters to be operated match. A portion overlapping the preceding segment in the target segment is greater than or equal to 8.3% of the target segment.
US11776525B1	Systems and methods for machine learning based active metasurfaces for flexural and/or longitudinal wave control and harmonics generation A wave control system includes a substrate with a plurality of beams spaced apart from each other, a plurality of sensors disposed on the plurality of beams, a plurality of actuators disposed on the plurality of beams, a processor, and a memory communicably coupled to the processor. The memory stores machine-readable instructions that, when executed by the processor, cause the processor to determine a frequency of a fundamental incident wave propagating within and/or incident on the plurality of beams based on a plurality of signals from the plurality of sensors, and control the plurality of actuators to generate at least one of a cancellation wave, a subharmonic wave, and a superharmonic wave, based on the frequency of the fundamental incident wave. In addition, a reflected fundamental wave, the sub harmonic wave, and/or the superharmonic wave can be steered to a desired direction or path along the substrate.
US11776524B2	Electromyography signal detection device An embodiment electromyography signal detection device includes a noise signal obtaining device configured to obtain a noise signal of an unknown reference frequency at a periphery of a user, an electromyography signal acquisition device configured to measure an electromyography signal from the user, and a controller configured to remove a noise signal included in the electromyography signal of the user based on the obtained noise signal of the unknown reference frequency.
US11776523B2	Sound insulation apparatus In the sound insulation apparatus, a sound wave transmitter configured to transmit sound waves with frequencies including the frequencies of propagation sound waves from a sound source and a sound wave receiver configured to receive the sound waves transmitted from the sound wave transmitter are coupled such that the orientation of a sound wave transmission surface of the sound wave transmitter and the orientation of a sound wave receiving surface of the sound wave receiver intersect each other and one pair set is formed. The one pair set is disposed in plurality such that the sound wave transmission surface of one set is spaced from and opposed to the sound wave receiving surface of another set and a space surrounding the sound source is formed. The sound waves transmitted from each of the sound wave transmitters are mixed with the propagation sound waves.
US11776521B2	Sound absorbing structure having one or more acoustic scatterers attached to or forming a vehicle structure A sound absorbing structure includes a vehicle structure having a surface and at least one acoustic scatterer coupled to the surface. The at least one acoustic scatterer has a resonant frequency. The at least one acoustic scatterer has an opening and at least one channel. The at least one channel has a channel open end and a channel terminal end, the channel open end being in fluid communication with the opening. The sound absorbing structure may be configured to absorb sound waves at a certain frequency generated by a noise source. The certain frequency may be substantially similar to the resonant frequency of the at least one acoustic scatterer.
US11776519B2	Vibration generating device and display apparatus including the same A display apparatus includes a display panel displaying an image and a vibration generating device disposed on a rear surface of the display panel to vibrate the display panel. The vibration generating device includes a piezoelectric structure including a first region and a second region, the first region has a vibration characteristic of a first frequency, and the second region has a vibration characteristic of a second frequency which differs from the first frequency.
US11776518B2	Automated music composition and generation system employing virtual musical instrument libraries for producing notes contained in the digital pieces of automatically composed music An automated music composition and generation system including a system user interface for enabling system users to review and select one or more musical experience descriptors, as well as time and/or space parameters; and an automated music composition and generation engine, operably connected to the system user interface, for receiving, storing and processing musical experience descriptors and time and/or space parameters selected by the system user, so as to automatically compose and generate one or more digital pieces of music in response to the musical experience descriptors and time and/or space parameters selected by the system user. Each digital piece of composed and generated music contains a set of musical notes arranged and performed in the digital piece of music. The engine includes: a digital piece creation subsystem and a digital audio sample producing subsystem supported by virtual musical instrument libraries.
US11776515B1	Reinforced solid wood block idiophone A solid wood block idiophone having slit reinforcement plates mounted against the sides of the idiophone's wood block is described. Advantageously, the reinforcement plates act to increase the durability of the wood having one or more open faced resonant chambers with chamber sidewall slits by preventing the wood from fracturing to and from the open woodgrain ends terminated at the sidewall slits.
US11776512B2	Keyboard device Provided is a keyboard device for which the number of parts can be reduced. The present invention is provided with: hammers rotatably linked to a chassis; keys rotatably linked to the hammer thereof; guiding pins provided to the keys and extending in the widthwise direction of the keys; and a guiding groove provided to the chassis side and into which the guiding pins are inserted. The downward displacement of the front-end sides of the keys is guided by the rotation of the hammers with respect to the chassis, and the downward displacement of rear-end parts of the keys is guided by the sliding of the guiding pins with respect to the guiding groove. This eliminates the need for links to guide the displacement of the rear-end parts of the keys, thus allowing the number of parts to be reduced.
US11776510B2	Image update method for a display device and driving device thereof A screen update method for a display device and a driving device thereof, the frame update method includes: following a write-in command, controlling a driving circuit to drive a display panel to update a screen; the write-in command represents writing a display data to a storage element. The driving device includes: the driving circuit, which is coupled to the display panel and drives the display panel to update the screen; and a control circuit, which receives the write-in command and the display data, is coupled to the driving circuit; the control circuit follows the write-in command writing the display data to the storage element, and follows the write-in command to control the driving circuit to drive the display panel to update the screen.
US11776508B2	Pre-display adaptive codeword mapping for display monitor with non-ideal electro-optical transfer function A system includes a display monitor compatible with a video specification having a reference EOTF while exhibiting an actual EOTF that deviates from the reference EOFT. The system further includes a video source subsystem operable to determine an approximated EOTF representative of the actual EOTF based on user input received from a display of at least one test pattern to the user via the display monitor. The at least one test pattern is intended to elicit input from the user based on a visual inspection of the at least one test pattern by the user. The video source subsystem further is to convert color values of each video image of a stream of images to corresponding non-linear codewords based on the approximated EOTF, and transmit the codewords to the display monitor for display as display images representative of the video images.
US11776506B2	Systems and techniques for aggregation, display, and sharing of data Systems and techniques for aggregation, display, and sharing of data. Graphic items representing data objects identified by a data package may be displayed on timelines. Each timeline may be associated with a respective class of data, and each graphic item displayed on a respective timeline may represent one or more of the data objects in the class associated with the respective timeline.
US11776503B2	Generating display data based on modified ambient light luminance values A method includes sensing a plurality of luminance values associated with ambient light from a physical environment. The plurality of luminance values quantifies the ambient light arriving at a see-through display. The method includes identifying respective portions of the plurality of luminance values, across the see-through display, based on corresponding portions of rendered image data. The method includes modifying one or more of the respective portions of the plurality of luminance values based on a function of predetermined display characteristics associated with the rendered image data, in order to generate one or more modified portions of the plurality of luminance values. The method includes modifying the corresponding portions of the rendered image data in order to generate display data, based on the one or more modified portions of the plurality of luminance values. The method includes displaying, on the see-through display, the display data.
US11776502B1	Using variable refresh rate to seamlessly adapt to arbitrary and variable video frame rates Techniques for using variable refresh rate to seamlessly adapt to arbitrary and variable video frame rates are described. According to some embodiments, a computer-implemented method includes receiving, by a media player, a video entirely encoded at a fixed frame rate, decoding the encoded video into a rendered video at the fixed frame rate with a video decoder of the media player, setting a display and a display interface that is to output the rendered video to the display to a variable refresh rate mode that synchronizes a refresh rate of the display to a varying frame rate of rendered frames, sending the rendered video at the fixed frame rate from the media player to the display interface, sending the rendered video from the display interface to the display at the fixed frame rate when the display interface is in the variable refresh rate mode, and displaying the rendered video on the display at the fixed frame rate when the display is in the variable refresh rate mode.
US11776500B2	Liquid-crystal display apparatus and driving method Multiple adjustment capacitors corresponding to multiple source bus lines on a one-to-one correspondence basis are arranged. Each adjustment capacitor includes a first electrode supplied with an adjustment signal and a second electrode connected to the source bus line. The adjustment capacitors are divided into multiple groups. An adjustment signal having a amplitude different from group to group is supplied to the adjustment capacitor. A potential of the adjustment signal is raised after a liquid-crystal capacitor is charged in a pixel formation region including a thin-film transistor (TFT) that is turned on with a gate driver causing a scanning signal to rise and before the gate driver causes the scanning signal to fall.
US11776497B2	Global and local contrast control with brightness and shading adjustment of smart glass display A smart glass display includes a first glass layer, a second glass layer, a display layer, an auto-shading layer and a control module. The display layer is disposed between the first glass layer and the second glass layer and includes an array of light emitting diodes and at least one ambient light sensor. The at least one ambient light sensor is configured to detect a level of ambient light at the display layer. The auto-shading layer includes suspended particle devices each of which configured to selectively provide different levels of transparency. The control module is configured to, based on an output of the at least one ambient light sensor, adjust a transparency level of at least a portion of the auto-shading layer.
US11776496B2	Driving voltages for advanced color electrophoretic displays and displays with improved driving voltages Improved methods for driving a four particle electrophoretic medium including a scattering particle and at least two subtractive particles. Such methods allow displays such as a color electrophoretic display including a backplane having an array of thin film transistors, wherein each thin film transistor includes a layer of metal oxide semiconductor. The metal oxide transistors allow faster, higher voltage switching, and thus allow direct color switching of a four-particle electrophoretic medium without a need for top plane switching. As a result, the color electrophoretic display can be updated faster and the colors are reproduced more reliably.
US11776494B2	Backlight driving method and device for driving a scan-type display A backlight driving method includes steps of: (A) receiving a piece of image data that includes a number (K) of segments, where K≥2; (B) generating a piece of adjustment data that includes a number (K) of segments; each segment of the adjustment data being generated based on a respective segment of the image data and upon receipt of the respective segment of the image data; (C) generating, based on a piece of delay data and on an original synchronization control (SC) signal that has a pulse, an internal SC signal that has a number (K) of pulses; and (D) generating a backlight driving output based on the adjustment data and the internal SC signal, so as to drive a backlight source of a scan-type display to emit light.
US11776493B2	Backlight module and display device including the same A backlight module and a display device are provided. The backlight module includes a backlight and a driving circuit for driving the backlight. In the driving circuit corresponding to at least one backlight unit in the backlight, a data signal input module is configured for inputting a first data signal to a first point during a detection stage, and inputting a compensated second data signal to the first point according to a threshold voltage detected by a detection module during a display stage. The present invention improves uniformity of light emission of the backlight module.
US11776492B1	Dynamic backlight color shift compensation systems and methods A device may include an electronic display having a backlight that generates light and multiple display pixels that modulate the amount of generated light emitted from the electronic display based on compensated image data. The backlight may include multiple illuminators that generate the light, and a first color component illuminator may have a slower response rate than a second color component illuminator. The device may also include image processing circuitry that generates the compensated image data by compensating input image data for a color shift associated with a change in brightness of the backlight and the slower response rate of the first color component illuminator. The input image data may be compensated by increasing first color component pixel values of the input image data relative to second color component pixel values of the input image data, and the compensated image data may be output to the electronic display.
US11776491B2	Display control device, image display device, display control method, and recording medium to control a light emission amount of a region based on a light source control value for the region In an image display device including a backlight (6) divided into multiple regions, color shift information (CSR, CSB) is generated from a light source control value (BL(i,j)) for each region, the region to which a pixel of interest belongs and regions therearound are taken as reference regions, luminance conversion information is generated from the light source control value for each reference region, color conversion information is generated from the color shift information for each reference region, and an image signal is converted based on the color conversion information and luminance conversion information, so that an output image signal is generated. Even when there is light leakage from a peripheral region, it is possible to perform color correction so that the color difference is not noticeable at a region boundary portion.
US11776489B2	Liquid crystal display device having a control device for tone mapping A control device that controls a liquid crystal display device, the control device includes: an obtainer that obtains a first video signal; a determiner that determines a first backlight value as a reference luminance of a backlight of the liquid crystal display device, using a first luminance characteristic of the first video signal; a tone map processor that performs tone mapping on the first video signal based on the first backlight value and a peak luminance displayable by the liquid crystal display device, and outputs a second video signal obtained through the tone mapping; and a generator that generates a control signal for local dimming control on the liquid crystal display device based on the first backlight value and the second video signal, and outputs the control signal to the liquid crystal display device.
US11776487B2	DA conversion circuit, electro-optical device and electronic apparatus A first capacitance element provided corresponding to a bit D0, a second capacitance element provided corresponding to a bit D1, and a third capacitance element and a fourth capacitance element provided corresponding to a bit D2, and electrically coupled in parallel are included. An area S1 where electrodes of the first capacitance element overlap in plan view is smaller than half an area S2 where electrodes of the second capacitance element overlap in plan view, an area in which electrodes of the third capacitance element overlap in plan view is substantially the same as the area S2, and an area where electrodes of the fourth capacitance element overlap in plan view is substantially the same as the area S2.
US11776484B2	Display device A display device of the invention includes a pixel unit including first pixels which display a first color; and a data driver which supplies first data voltages to the first pixels. The data driver includes: a first master gamma block including first master amplifiers which generate first reference gamma voltages; a first slave gamma block which generates first gamma voltages by dividing the first reference gamma voltages; and a first decoder which provides some of the first gamma voltages as the first data voltages, and each of the first master amplifiers is enabled or disabled based on a maximum luminance of the pixel unit.
US11776482B2	Scan driver for a display device with reduced degradation of transistors A scan driver for a display device includes a plurality of scan stage groups, each of the scan stage groups including a first scan stage and a second scan stage. The first scan stage includes: a first transistor including a gate electrode coupled to a first Q node, one electrode coupled to a first scan clock line, and another electrode coupled to a first scan line; a second transistor including a gate electrode and one electrode, which are coupled to a first scan carry line, and another electrode coupled to the first Q node; a third transistor including a gate electrode coupled to a first control line and one electrode coupled to a first sensing carry line; a fourth transistor including a gate electrode coupled to the other electrode of the third transistor, one electrode coupled to a second control line, and another electrode coupled to a first node; a first capacitor including one electrode coupled to the one electrode of the fourth transistor and another electrode coupled to the gate electrode of the fourth transistor; a fifth transistor including a gate electrode coupled to a third control line, one electrode coupled to the first node, and another electrode coupled to the first Q node; and a sixth transistor including a gate electrode coupled to the first Q node, one electrode coupled to the second control line, and another electrode coupled to the first node.
US11776480B2	Pixel and display device including the same A pixel includes a light emitting element, a first transistor connected between first and second nodes and that generates a driving current flowing from a first power line to a second power line through the light emitting element, a second transistor connected between a data line and the first node and turned on in response to a fourth scan signal, a third transistor connected between the second node and a third node corresponding to a gate electrode of the first transistor and turned on in response to a second scan signal, a fourth transistor connected between the third node and a third power line providing a third power voltage and turned on in response to a first scan signal, and a fifth transistor connected between the first and fourth nodes and turned on in response to a fifth scan signal.
US11776476B2	Pixel circuit and display device including the same A pixel circuit and a display device including the same are disclosed. The pixel circuit includes a driving element including a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a third electrode connected to a third node; a light emitting element including an anode electrode connected to the third node, and a cathode electrode to which a pixel ground voltage supply voltage is applied; a first switch element configured to supply a data voltage to the second node in response to a scan pulse; and a second switch element configured to supply a first initialization voltage set to a negative voltage that is less than the pixel ground voltage supply voltage to the third node in response to a first initialization pulse.
US11776475B2	Display device Display devices are disclosed. In one example, a display device includes light emitting element groups each including light emitting element units, each of the light emitting element units including first, second and third light emitting elements. Each of the light emitting element groups includes first drive circuits that drive the first light emitting elements, second drive circuits that drive the second light emitting elements, and third drive circuits that drive the third light emitting elements, and in each of the light emitting element groups, the number of first drive circuits is equal to the number of first light emitting elements, the number of second drive circuits is less than the number of second light emitting elements, and the number of third drive circuits is less than the number of third light emitting elements.
US11776474B2	Display device A pixel includes a driving transistor, a switching transistor, and first and second capacitors. The gate of the driving transistor is disposed below a first insulating layer, and a first conductive pattern defining a first electrode of the first capacitor is disposed below the first insulating layer. A second conductive pattern defining a second electrode of the first capacitor and a first electrode of the second capacitor is disposed on the first insulating layer, a third conductive pattern defining a second electrode of the second capacitor is disposed on a second insulating layer covering the second conductive pattern, and the data line is disposed above the second insulating layer.
US11776462B2	Pulse width modulation (PWM) control apparatus and method for improving dynamic false contour of display device A display apparatus is capable of improving a dynamic false contour. The display apparatus may control to change an order of a plurality of pulses of which widths are modulated for an emission time set within one frame, or divide pulses corresponding to the most significant bit (MSB) and the second significant bit (MSB-1) of image data among the pulses into two or more sub-pulses, and output the sub-pulses.
US11776461B2	Method of generating a PWM signal and circuit for generating a PWM signal A circuit for generating a PWM signal includes a shift register having a plurality of clock-controlled register units. Each clock-controlled register unit has an input and an output. The circuit also includes a write unit configured to set the outputs of the register units each to a designated logical value. The circuit further includes a clock generator configured to drive the register units with a common clock signal. The register units are connected in series. The shift register is configured to output the PWM signal at an output contact. The PWM signal is a chronological sequence of the logical values set in the register units, the PWM signal assumes each of the logical values with the duration of one clock of the clock signal, the clock signal is cyclic, during one cycle the duration of successive clocks changes, and the clock signal is identical per cycle.
US11776460B2	Active control of light emitting diodes and light emitting diode displays Active control of light emitting diodes (LEDs) and LED packages within LED displays is disclosed. LED packages are disclosed that include a plurality of LED chips that form at least one LED pixel for an LED display or an LED panel. Each LED package may include an active electrical element that is configured to receive a control signal and actively maintain an operating state, such as brightness or grey level while other LED packages are being addressed. Active electrical elements are disclosed that are configured to provide both forward and reverse bias states to LEDs to detect adverse operating conditions including reverse leakage and deviations to forward voltage levels. LED packages are also disclosed that may self-configure based on the manner in which various input or output lines are connected.
US11776458B2	Display device and method of operation the same A display device includes a display panel and a driving circuit that receives an input image signal and provides an output image signal corresponding to the input image signal to the display panel. The driving circuit includes an edge and slope detector that detects an edge of the input image signal, and determines an angle between the edge and a virtual line parallel to a first direction, a weight calculator that determines a weight, based on the edge and the angle, and a rendering module that compensates for the input image signal, based on the weight, and outputs the output image signal. The weight is determined through an arithmetic operation between the edge and the angle.
US11776457B2	Electrostatic protection circuit and display panel The present disclosure provides an electrostatic protection circuit and a display panel, wherein the electrostatic protection circuit includes a first voltage reference unit configured to divide a voltage between an array substrate row driving signal line and a common electrode line once; a second voltage reference unit configured to divide the voltage between the array substrate row driving signal line and the common electrode line twice; and a charge releasing unit that adjusts charge distribution between the array substrate row driving signal line and the common electrode line based on reference voltages provided by the first voltage reference unit and the second voltage reference unit.
US11776452B2	Display substrate and display device A display substrate, a method for driving the same, a display device, and a high-precision metal mask are provided. The display area includes a first display sub-area in which pixels are distributed at a high density (e.g., a high resolution), and a second display sub-area in which pixels are distributed at a low density (e.g., a low resolution), and a transition display sub-area, with a distribution density of pixels (a resolution) between the distribution density of pixels in the first display sub-area and a distribution density of pixels in the second display sub-area, is arranged between the first display sub-area and the second display sub-area.
US11776449B2	Pixel circuit, display panel and display apparatus The present disclosure provides a pixel circuit, a display panel and a display apparatus. A gate of a data writing transistor is electrically connected with a first scan line, a first electrode of the data writing transistor is electrically connected with a data line, and a second electrode of the data writing transistor is electrically connected with a first electrode of a drive transistor; a gate of a threshold compensation transistor is electrically connected with a second scan line, a first electrode of the threshold compensation transistor is electrically connected with a gate of the drive transistor, and a second electrode of the threshold compensation transistor is electrically connected with a second electrode of the drive transistor; and a compensation circuit is electrically connected with the gate of the drive transistor.
US11776447B2	Display device, data driving circuit and display panel A display device includes a display panel in which a plurality of pixels including first, second, and third subpixels disposed in a region where a plurality of gate lines extending in a first direction and a plurality of data lines extending in a second direction intersect. The display device further includes a gate driving circuit configured to drive the plurality of gate lines, a data driving circuit configured to drive the plurality of data lines, and a timing controller configured to control the gate driving circuit and the data driving circuit. In the display panel, a first data voltage is applied to the first subpixel, and a second data voltage is applied to the second subpixels or the third subpixels.
US11776444B2	Pixel array substrate A pixel array substrate, including scanning line pads, data line pads, scanning lines, data lines, gate transmission lines, pixels, a data line signal chip, and a scanning line signal chip, is provided. The scanning lines extend along a first direction. The data lines and the gate transmission lines extend along a second direction. The data lines are electrically connected to the data line pads. The scanning lines are electrically connected to the scanning line pads through the gate transmission lines. A ratio of a number of rows of pixels arranged in the first direction to a number of rows of pixels arranged in the second direction is X:Y. Each pixel includes m sub-pixels.
US11776443B2	Gate driving circuit and driving method thereof, display panel and display device There is provided a gate driving circuit including cascaded Gate Driver On Array (GOA) units, each GOA unit drives a row of pixels and includes a starting sub-unit, an output sub-unit and an output terminal, in the GOA unit at a first stage, the starting sub-unit is coupled with a starting signal, a first control signal, a second control signal and a constant voltage potential, and the output sub-unit is coupled with a first clock signal and a first power supply signal; in the GOA unit at an nth stage, the starting sub-unit is coupled with the starting signal, the first control signal, the second control signal and the output terminal of the GOA unit at an (n−1)th stage, the output sub-unit is coupled with the first power supply signal and the output terminal of the GOA unit at an (n+1)th stage, n is an integer greater than 1.
US11776441B2	Rollable display device and driving method thereof for controlling refresh rate of display Display device and driving method thereof are provided. The display device includes a housing, a display screen, and a drive circuit. The housing includes a first side and a second side opposite to the first side in a first direction. The display screen includes a first end and a second end. At least one of the first end and the second end is accommodated in the housing. A first display area in a display area of the display screen is located between the first side and the second side. A second display area in the display area of the display screen is accommodated in the housing. The drive circuit is configured, when the display screen displays an image, to provide drive signals to the first display area, and control a display of the first display area without providing the drive signals to the second display area.
US11776439B2	Display driver including crack resistance measurement circuit and method of measuring crack of display panel A display driver including a crack resistance measurement circuit according to one embodiment of the present disclosure includes a crack resistance measurement circuit connected to a crack resistance circuit of a display panel to measure a crack resistance of the crack resistance circuit, wherein the crack resistance measurement circuit includes a reference resistance generation circuit configured to generate a reference resistance using at least two resistors connected in series and at least two switches connected to correspond to the at least two resistors, a comparator configured to compare a magnitude of the crack resistance with a magnitude of the reference resistance and output a resistance comparison result, and a circuit controller configured to output a reference resistance control signal for controlling the at least two switches according to the resistance comparison result.
US11776436B2	Foldable display device A foldable display device includes a display area having a plurality of unit pixels and a non-display area surrounding the display area, and a folding area defined in the display area and the non-display area, and non-folding areas on both sides of the folding area. The foldable display device can further include a first substrate, a second substrate corresponding to the first substrate and including the plurality of unit pixels, a thin film transistor disposed on the second substrate, an organic light emitting diode disposed on the thin film transistor, and a mesh pattern disposed between the first substrate and the second substrate and having a plurality of openings. Openings of the mesh pattern in the folding area are smaller in size than openings of the mesh pattern in the non-folding areas.
US11776431B2	Multilayer label A label for a package that includes a base layer and a top layer attached to the base layer is disclosed. The base layer includes a central surface adapted to receive written markings. The top layer covers at least part of the base layer and includes perforations such that a detachable part of the top layer has a perimeter at least partially defined by the perforations. The detachable part includes a front surface and a back surface that faces the base layer while the perforations remain intact. The front and back surfaces of the top layer are adapted to receive written markings. And, the top layer is opaque such that while the perforations remain intact, any written markings on the back surface of the detachable part or on the central surface of the base layer are not visible from a vantage point outside of the label.
US11776430B1	Assembled structure container and plateform of seismic fault simulation test The present invention relates to the technical field of researching and developing a seismic fault motion simulation experimental instrument, and particularly relates to a matching box body structure for simulating fault motion and a seismic fault simulation experimental platform, including a left box body and a right box body arranged in a left and right matching manner, wherein the inner cavities of the left box body and the right box body communicate with each other and form an accommodating cavity for accommodating a soil layer, both the left box body and the right box body include a main box body, two sides along the left direction and right direction have openings, and the top side has an opening; and an end cover.
US11776428B1	Systems, models, and methods for simulating surgery on anatomical organs The invention provides systems and methods for improved simulation of surgical procedures, using models of anatomical organs. The models comprise models of internal components present in the anatomical organ. The models of the internal components are registered to the position which the internal component occupies in the anatomical organ, and in some embodiments the models of the anatomical organ can lose simulated physiological fluids during simulated surgery.
US11776426B1	Dentistry training apparatus A dentistry training apparatus includes a suction assembly that includes a collection portion having a bottom wall and a sidewall extending upwardly from the bottom wall, the bottom wall defining a central aperture in fluid communication with a liquid suction device. A support tray is positioned atop the collection portion and includes a plurality of legs configured to displace the support tray above the bottom wall, the support tray including a lower wall and a support tray sidewall extending upwardly from a peripheral edge of the lower wall. The lower wall of the support tray defines a hole having a circular configuration for selectively receiving an endodontic cup. An apex locator lead is electrically connected to a power source and positioned atop the bottom wall of the suction assembly, the apex locator lead being registered with the hole so as to engage the endodontic cup when received in the aperture.
US11776421B2	Systems and methods for monitoring and evaluating body movement The present disclosure relates to systems and methods for analyzing and evaluating movement of a subjects and providing feedback. In some embodiments, a method comprises receiving one or more images of a body of the subject captured during performance of a physical movement by the subject; computing a model descriptive of positions and orientations of body parts of the subject based on the one or more images; generating a comparison of the positions and orientations to target positions and target orientations, respectively, for the physical movement; and generating a recommendation based on the comparison.
US11776414B1	System and method for providing guidance to a user of a website or application A system and method assists a user in achieving one or more goals of the user or the operator of a web site, application or other media by comparing a series of two or more actions of a user to those of other users, and identifying whether a primary action has been requested or performed by the user, or determining if a first piece of information has been specified by the user as being in a first set, and a second piece of information has not been specified or has been specified in a non-committal manner, and then provides relevant information to the user to instruct the user how to perform the primary action or to notify the user of the consequences of not specifying the second piece of information or specifying it in a non-committal manner.
US11776407B2	Cargo detection system and method for detecting overhanging cargo on a motor vehicle A cargo detection system for detecting overhanging cargo on a motor vehicle comprises a sensor system configured to provide cargo measurement data for cargo loaded onto the motor vehicle by measuring at least one of exterior dimensions of cargo protruding over an outer edge of the motor vehicle and an opening condition of a tailgate of the motor vehicle. The system further comprises a control device configured to assess, based on the cargo measurement data of the sensor system, whether cargo is overhanging from the motor vehicle and to calculate an updated vehicle length and/or vehicle width for the motor vehicle accounting for the overhanging cargo.
US11776405B2	Apparatus and method for V2X communication A method of transmitting a CPM message by a V2X communication device of a vehicle is disclosed. The method includes detecting at least one surrounding object; based on whether a state of the detected object satisfies a preset trigger condition of a collective perception (CP) message, generating the CP message including information on the detected object; and transmitting the CP message, wherein the CP message is generated when the state of the detected object satisfies the trigger condition, or is generated when the state of the detected object does not satisfy the trigger condition and a specific time has passed after the previously transmitted CP message is generated.
US11776400B2	Junction queueing Junction queueing for vehicles is described, in which vehicles may be queued based on arrival time at a junction, position relative to a stopping location at the junction, and/or an amount of time waiting for other vehicles to proceed through the junction (timeout). In some examples, the queue may be first generated based on the arrival times of any other vehicle relative to a particular vehicle generating the queue. The queue may be updated based on arrival times of other vehicles (e.g., after the particular vehicle), whether another vehicle has proceeded out-of-turn (e.g., based on a position at the junction), and/or a timeout for vehicles that wait for others to yield at the junction. In some examples, hysteresis and alterations of the score for safety reasons may alter queue order. The queue may be used to control the particular vehicle to traverse the junction.
US11776396B2	Intersection infrastructure warning system A warning system for warning vulnerable road users (VRUs) includes an edge computing device having a graphics processing unit (GPU), one or more sensors that acquire spatial-temporal data of road users, and one or more warning devices that output a warning to warn targeted VRUs of danger. The GPU uses one or more artificial intelligence (AI) algorithms to process the spatial-temporal data of the road users to predict a path, trajectory, behavior, and intent for the road users. The GPU then analyzes the predictions of the road users to determine convergences between the predictions to determine threat interactions and identify targeted VRUs. In response to determining threat interactions and identifying the targeted VRUs, the edge computing device outputs targeting instructions and warning response instructions to the one or more warning devices to deploy the one or more warning devices to warn the targeted VRUs.
US11776394B2	Systems and methods for shared parking permit violation detection Provided is a technology that allows, inter alia, two different patrol-vehicles to be used to enforce parking regulations. Unique systems and methods, inter alia, allow a patrol vehicle or the like to collect parking data pertaining to parked vehicles, and to wirelessly transmit such parking data to a server. A later patrol vehicle or the like can wirelessly receive parking data related to parking events related to its parking enforcement situation and determine whether parking violations, such as overtime or permit sharing violations, are occurring using a combination of parking data generated locally and extraneous parking data collected by the previous patrol vehicle.
US11776393B2	Method and system for reversing the direction of a road segment A method at a computing device in an intelligent transportation system for reconfiguring a road segment, the method including receiving a request from a second computing device associated with a vehicle to change a configuration for the road segment; determining a road segment configuration; and reconfiguring the road segment based on the determined road segment configuration.
US11776391B2	Generating and transmitting parking instructions for autonomous and non-autonomous vehicles Systems and apparatuses for receiving data from a plurality of sensors and using the data, as well as other data, to generate a parking recommendation for an autonomous vehicle and instruct the autonomous vehicle to travel to the recommended parking location are provided. Data may be received from a plurality of sensors within a first autonomous vehicle, as well as from other vehicles and/or structures. Historical parking data associated with the first autonomous vehicle may also be extracted. In some examples, an expected future trip of the first autonomous vehicle may be determined. The system may then evaluate the data to generate a parking recommendation for the first autonomous vehicle. The system may generate and transmit instructions for traveling from a current location to the recommended parking location and may cause the first autonomous vehicle to travel to the recommended parking location.
US11776384B2	Methods and apparatus for providing notifications in a media system A system to convey user alert messages is disclosed. The system may have a alert service coupled between alert providers and a number of households. After receiving in the alert service an alert message from an alert provider, the alert service may altar the alert message to identify the household designated to receive the alert message. The alert service sends a notification to a home media system within the household designated to receive the alert message.
US11776382B1	Premises security system using ultra-wideband (UWB) functionality to initiate at least one action A management device for a premises security system that is configured to monitor a premises is provided. The management device includes an ultra-wideband (UWB) transceiver configured to provide a coverage area, and processing circuitry. The processing circuitry is in communication with the UWB transceiver and configured to detect a UWB device within the coverage area, determine a distance of the UWB device from the management device based on signaling received from the UWB transceiver, determine a movement vector of the UWB device based on the signaling received from the UWB transceiver, and initiate a premises security system action based on the distance and the movement vector.
US11776379B2	Notification system for detecting tool usage A tool notification system for determining tool usage information that would be otherwise unavailable or not easily discoverable by comparing information output by a tool and information obtained from a source. The tool notification system includes a tool operatively coupled to a sensor which may communicate information about the use, location, or other status of the tool to a processing system of the tool notification system. The processing system also receives the information from the source, which may include information about the parts supplied to the tool, the designated location of the tool, or other threshold parameters associated with supplying or using the tool. The processing system is configured to compare the information output from the tool and the information from the source and determine whether a condition is met for thereby sending a notification about tool usage.
US11776376B2	Flood monitoring unit and system An integrated flood monitoring unit comprises a sensor capable of at least detecting one or more floodwater levels or measuring water levels and assembly of a data acquisition module, and a wireless transmitter that is specially adapted to be mounted one top and at least partially inside of a hollow pole secured in a vertical orientation at a fixed geographical location to monitor water levels, with the sensor being located nearer the bottom of the pole.
US11776373B2	System and method for detecting child distress and generating suggestion for relieving child distress The present invention provides a system and method for child monitoring. The child monitoring system comprises an audio sensor, a video sensor, an input module, a processing module, and a display module. The audio sensor is configured to capture speech data, the video sensor is configured to capture activity data. The input module is configured to receive one or more child parameters. The processing module is configured to generate a suggestion in response to the computation of the speech data, the activity data, and the one or more child parameters with a suggestion database or a predefined suggestion database. The display module is configured to display the suggestion and prompt a parent to provide an input. Further, the suggestion database is updated in response to the input provided by the parent. The processing module uses one or more machine learning modules to generate the suggestion.
US11776370B2	Systems and methods for monitoring, tracking and tracing logistics Methods for tracking a container with a tracking device are provided.
US11776366B2	Systems and methods for projecting action indicators In some embodiments, apparatuses and methods are provided herein useful to projecting action indicators on items in a retail facility. In some embodiments, a system comprises an image capture device configured to capture an image of a shelving unit, a control circuit configured to identify items located in the shelving unit, determine an action item for an item located in the shelving unit, identify boundaries of the item, and generate an action image including an action indicator based on the action item for the item, wherein the action indicator is located within the boundaries of the item, and a display device configured to present the action image on the shelving unit, wherein the action indicator is presented on the item.
US11776364B2	Gaming device having poker lock and improve feature Embodiments of the present invention set forth systems, apparatuses and methods for providing a lock and improve feature in gaming devices. Accordingly, a gaming device can be configured to include a video poker game where items associated with cards in poker hand, or card positions where the cards in the poker hand are displayed, can be locked, held, stuck, or otherwise maintained and a secondary game event is played where additional items can be received. The items may provide credits, bonus opportunities, progressives, multipliers, or other types of awards, modifiers, or beneficial game enhancements.
US11776363B2	Gaming devices and methods for enriching game play with migrating award enhancements Systems, apparatuses and methods for providing opportunities to enhance gaming results over a plurality of gaming events. In one embodiment, award enhancements such as wild cards and/or payout modifiers migrate through a multi-hand poker array over multiple poker games, thereby changing the award enhancement opportunities as the award enhancements migrate.
US11776362B2	Gaming systems and methods for tracking and limiting sports wagers for identified and un-identified players A gaming system configured to create electronic player sports wagering profiles for un-identified players, track each sports related wager made by each un-identified player, determine if any un-identified player has reached a sports related wager limit for a designated time period, and responsive to determining that an un-identified player has reached the sports related wager limit for the designated time period, initiate a sports wager limit resolution process.
US11776356B2	Gaming machine and a method of gaming thereon Described herein is a gaming machine and, a method of gaming thereon, comprising: a symbol selector for selecting a plurality of symbols from a set of symbols during play of a game, the set of symbols including a plurality of function symbols; a display having at least a game area, the selected symbols being displayed in said game area; an outcome evaluator for determining that at least one predefined triggering criterion is satisfied; and a game area expander for expanding said game area in response to said at least one predefined triggering criterion being satisfied, such that at least one additional symbol of the set of symbols is displayed in an expanded game area.
US11776352B2	Graphical user interface for a gaming system A graphical user interface for a gaming console is configured to render a first graphical element in a first region that includes multiple user selectable resource objects, detect a first touching operation at a first location in the first region to select and highlight a resource, detect a first touching operation and a second touching operation in the second region, render an instance of the resource at a first and second location in the second region, determine if a time period of the first and second touching operation exceeds a predetermined time period, and if so, render multiple instances of the resource at the first and second location in the second region, wherein a number of rendered the multiple instances of the resource is determined by a duration that the time period of the second touching exceeds the predetermined time period.
US11776351B2	Autonomous food station A novel food station comprises a plurality of cubbies, each cubby sized to enclose a food portion container, and an externally accessible collection hatch large enough for the food portion container to pass therethrough. A heating system can controllably heat the food portion container within a selected one of the cubbies, independently of an operation of the heating system the other cubbies. A cooling system can perform cooling within a subset of cubbies that includes at least the selected cubby. An internal transport system includes an end effector that temporarily couples to the portion container carrier of the selected cubby and controllably moves the food portion container carrier within the food station to the collection hatch. A control system includes a memory that controls the heating and controls the movement of the internal transport system.
US11776344B1	Ballot drop box A ballot drop box adapted to collect voting ballots. The drop box is a shell having an interior and an exterior. A chute is used by the voter to deposit their ballot. Within the drop box is a scale which collects the deposited ballot from the chute. The scale determines if a single ballot has been deposited or multiple ballots. Based on this determination, the ballot(s) are sent to an “acceptable” bin within the box or to a “further investigation needed” bin. An alternative embodiment marks the she submitted ballot(s) allowing a later determination if the ballots have been “stuffed”.
US11776339B2	Control system, control method, and computer readable medium for opening and closing a security gate A control system that controls opening-closing of a security gate which is provided in a facility in which a plurality of mobile robots travels autonomously is provided. The control system performs: receiving a passing-through reservation signal for passing through the security gate; and allowing a plurality of mobile robots to consecutively pass through the security gate while the security gate opens its gate once when passing-through reservation signals are received from the plurality of mobile robots.
US11776337B1	Multi-locking mechanisms for premises security systems A primary lock device is provided which is configured to wirelessly communicate with a premises security system hub device and at least one secondary lock device in a premises security system. The primary lock device receives a lock configuration, receives a user input, authenticates the user input, and engages or disengages a locking mechanism based at least in part on the lock configuration and a result of authenticating the user input. The primary lock device determines a lock indication based at least in part on the lock configuration and a result of authenticating the user input, and transmits the lock indication to at least one secondary lock device for engaging or disengaging at least one respective lock mechanism of the at least one secondary lock device.
US11776336B2	Automobile with a lock for providing contactless secure access to the automobile Systems and methods related to a lock for providing contactless secure access to an automobile are described. A current state of the lock can be changed based on an exchange of information, via a wireless interface, between a mobile device and the lock. The exchange of information includes a use of a sharable digital key associated with at least one of a set of persons authorized to change a state of the lock. The exchange of information is configurable to operate in a first mode or a second mode. In the first mode, no identity-related information from at least one set of persons attempting to change the state of the lock to is required. In the second mode, identity-related information from at least one of a set of persons attempting to change the state of the lock is required.
US11776330B2	Closed-loop diagnostic model maturation for complex systems A method is provided for maintaining an onboard reasoner for diagnosing failures on an aircraft that includes aircraft systems configured to report faults to the onboard reasoner. The method includes accessing diagnostic data received from an onboard computer of the aircraft that includes the onboard reasoner. An off-board reasoner builds an off-board diagnostic causal model that describes causal relationships between the failed tests and the diagnosed failure modes. The off-board diagnostic causal model is compared to the diagnostic data. Based thereon, a discrepancy is identified between the graph of the off-board diagnostic causal model, and the other graph of the onboard diagnostic causal model, to determine a new causal relationship relative to the known causal relationships. The onboard diagnostic causal model is updated to further describe the new causal relationship, including producing an updated model, and uploading the updated model to the onboard computer.
US11776329B2	Sound analysis to identify a damaged component in a work machine An agricultural work machine, an agricultural work machine control system, and method for an agricultural work machine having a sound sensor configured to transmit sound signals generated by the work machine during operation. The transmitted sound signals are received by a controller and used to determine if the work machine is operating properly. The controller compares an operating frequency profile, based on the transmitted sound signals, to a baseline frequency profile, to determine whether a likelihood of a malfunctioning or damaged part or system of the work machine is present. If so, the controller transmits a signal to either turn off the agricultural work machine or transmits an alert to a display indicating that a malfunctioning or damaged part or system has been identified.
US11776328B2	Variable multiplexer for vehicle communication bus compatibility Disclosed are systems, methods, and non-transitory computer-readable media for a variable multiplexer for vehicle communication bus compatibility. A device includes a variable multiplexer that can be electronically configured to a desired pinout configuration to provide compatibility with multiple vehicles. For example, the variable multiplexer may be electronically configured based on a pinout configuration used by the vehicle to connect pins in the device to the corresponding pins on the data link connector that provide the same specified function. The device may therefore use a single standardized cable with vehicles using a variety of pinout configurations.
US11776325B2	Information management device of work machine, information management method, and information management system An information management device of a work machine includes an information collection unit that collects vehicle information of the work machine, an information analysis unit that analyzes the vehicle information to generate analysis information, a selection definition storage unit that stores a selection definition that defines transmission propriety information indicating whether it is allowed to transmit the vehicle information and the analysis information to a general-purpose processing function unit, and an information selection unit that selects, based on the selection definition, information to be transmitted to the general-purpose processing function unit.
US11776324B2	Operation management method, server, and system An operation management method for managing a plurality of circulating buses, each circulating bus being introduced into a circulation route from a base and returning to the base to be switched with another circulating bus after traveling a specified number of laps, includes storing, by a server, an operation schedule of the plurality of circulating buses, judging, by the server, whether a predetermined condition is satisfied when a predetermined event not planned in the operation schedule occurs, and revising, by the server, the operation schedule to introduce an additional circulating bus into the circulation route from the base when it is judged that the predetermined condition is satisfied.
US11776318B2	Information processing system, information processing method, and storage medium Provided is an information processing system including: a comparison information acquisition unit that acquires comparison information regarding iris comparison generated based on an iris image including an iris of a recognition subject; and a display image generation unit that generates a display image including an image indicating a content of the comparison information in association with positions in the iris.
US11776315B2	Appearance based dominant eye selector systems and methods for gaze estimation from passive imagery The disclosure relates to systems, methods, and programs for implicitly determining the relation of the eyes associated with gaze inference, including salient features (e.g., ocular dominance) that are not visible within a digital frame, allowing for real-time determination of the user's dominant eye for the purpose of gaze estimation, and point-of-regard mapping onto a 2D plane, achieved through an end-to-end training of an eye selector agent with domain-expertise knowledge embedded in an unsupervised manner via a convolutional deep neural network training process.
US11776314B2	Iris capture apparatus, iris capture method, and storage medium The present invention provides a technology that acquires a high resolution iris image more quickly than before. An iris capture apparatus according to one example embodiment of the present invention includes a rotatable movable mirror; a control unit that controls rotation of the movable mirror; a capture unit that captures different regions of a face of a user via the movable mirror and outputs a group of images every time the control unit rotates the movable mirror by a predetermined angle; and an iris image acquisition unit that acquires an image of an iris of the user from the group of images.
US11776313B2	Scanning apparatus for reducing field of view search space The disclosure provides for a scanning apparatus. The scanning apparatus may be configured to capture identifying information of a user and may comprise one or more infrared emitters, at least one image sensor configured to capture image data in a field of view, and a controller in communication with the scanning apparatus. The controller may be configured to activate the one or more infrared emitters, control the at least one image sensor to capture a first image in the field of view, deactivate the one or more infrared emitters, and control the at least one image sensor to capture a second image in the field of view.
US11776308B2	Frictionless access control system embodying satellite cameras for facial recognition A frictionless access control system and method embodying satellite cameras for facial recognition are disclosed. The cameras capture image data of individuals at an access point such as a door. Preferably, two or more cameras are placed on opposite sides of the access point to increase the likelihood that the individuals are captured in the image data. A facial cropper module extracts facial patches from the image data, and a facial signature module computes facial signatures from the facial patches. A facial recognition module receives the computed facial signatures from the facial signature module, matches the computed facial signatures to stored facial signatures, and sends user identity information of individuals corresponding to the stored facial signatures to the facial signature module when the computed facial signatures match the stored facial signatures.
US11776306B2	Method and chip for biometric characteristic acquisition, and computer readable storage medium Some embodiments of the present disclosure relate to biometric characteristic detection technology, which provide a method and chip for biometric characteristic acquisition, and a computer readable storage medium. The method for biometric characteristic acquisition includes: acquiring a plurality of configuration parameters, where the plurality of configuration parameters include a first exposure duration, parameters defining a first region and a target photosensitive value, where the first region is a local region in a photosensitive region of the chip for biometric characteristic acquisition; exposing the first region according to the first exposure duration, and acquiring a photosensitive value of the first region; determining a second exposure duration required to acquire the target photosensitive value in the photosensitive region according to the photosensitive value of the first region and the first exposure duration; and acquiring a biometric image according to the second exposure duration.
US11776302B2	Biometric recognition apparatus and biometric recognition method A biometric recognition apparatus and fingerprint feature extraction method can automatically optimize parameters used for extracting a feature template from a biometric image. The biometric recognition apparatus includes: a teacher data generation unit that generates a genuine pair and an imposter pair of first and second biometric images; a learning data generation unit that uses a plurality of different temporary parameters to extract feature templates from the first biometric image and the second biometric image; and an optimum solution determination unit that calculates a score separation degree on the temporary parameter basis based on a first score representing a similarity degree of a pair of the feature templates extracted from the genuine pair and a second score representing a similarity degree of a pair of the feature templates extracted from the imposter pair and determines the temporary parameter based on a level of the score separation degree.
US11776300B2	Electronic device and method for obtaining biometric information thereof According to an embodiment, an electronic device may include: a display including a polarization layer, a biometric sensor positioned to at least partially overlap the display, and an optical member including a light condenser positioned between the display and the biometric sensor. The biometric sensor may include a light receiving unit comprising light receiving circuitry configured to receive light emitted from the display and reflected by an external object. A length of the light receiving unit in a first direction, which is a polarization axis direction of the polarization layer, is greater than a length of the light receiving unit in a second direction crossing the first direction.
US11776296B2	Ultrasonic fingerprint recognition circuit, method for driving same, and display device Disclosed is an ultrasonic fingerprint recognition circuit. In the ultrasonic fingerprint recognition circuit, an ultrasonic sensor generates an AC echo signal based on an echo signal upon the fingerprint detection, and a signal converting unit converts the AC echo signal to a DC signal and transmit the DC signal to the signal output unit to generate a fingerprint recognition signal by a signal output unit.
US11776293B2	System and method for increasing safety during law enforcement stops An improvement is provided for routine law enforcement stops by making it safer for police officers and pedestrians. Implementation of smart technology into the industry wide standard use of physical interactions between police officers and pedestrians, a streamed lined method and process will yield optimal results as a safer method and system in executing such a tactic. Utilizing technology i.e. algorithms and databases, servers, and cloud-based infrastructures with application processing interfaces (api's) communicating in this ecosystem, creating a synergy while transferring specific data; will replace the current process of a routine traffic stop.
US11776292B2	Object identification device and object identification method An object identification method includes: generating a tracking sample and an adversarial sample; training a teacher model according to the tracking sample; and initializing a student model according to the teacher model. The student model adjusts a plurality of parameters according to the teacher model and the adversarial sample, in response to the vector difference between the output result of the student model and the output result of the teacher model being lower than the learning threshold, the student model is deemed to have completed training, and the student model is extracted as an object identification model.
US11776291B1	Document analysis architecture Systems and methods for generation and use of document analysis architectures are disclosed. A model builder component may be utilized to receiving user input data for labeling a set of documents as in class or out of class. That user input data may be utilized to train one or more classification models, which may then be utilized to predict classification of other documents. Trained models may be incorporated into a model taxonomy for searching and use by other users for document analysis purposes.
US11776290B2	Document classification using signal processing Aspects of the present disclosure provide techniques for document classification through signal processing. Embodiments include receiving a document for classification. Embodiments include generating an image of the document. Embodiments include producing a signal representation of the document based on numbers of non-white pixels in each horizontal scan line or vertical scan line of the image of the document. Embodiments include comparing the signal representation of the document to signal representations of previously-classified documents. Embodiments include determining, based on the comparing, a classification for the document. Embodiments include performing additional processing with respect to the document based on the classification for the document.
US11776289B2	Method and electronic device for predicting plurality of multi-modal drawings Embodiments herein disclose a method and electronic device for predicting multi-modal drawings. The method includes: receiving, by the electronic device, at least one of a text input and strokes of a drawing and determining, by the electronic device, features associated with the text input and features associated with the strokes of the drawing. The method includes classifying, by the electronic device, the features associated with the text input and the features associated with the strokes of the drawing into one of a dominant feature and a non-dominant feature and performing, by the electronic device, early concatenation or late concatenation of the features based on the classification; classifying, by the electronic device, the strokes of the drawing based on the concatenation into a category using a deep neural network (DNN) model; and predicting, by the electronic device, primary drawings corresponding to the category.
US11776284B2	Process and device for colony counting A device and a process to count a number of colonies present in a set of samples. The colony counting device has a storage device with plural storage locations. A handling system is operative to convey samples to analyze from storage locations to an analysis area and from the analysis area to storage locations. An imaging device is operative to acquire a plurality of images of a sample to analyze, the plurality of images including all or a part of the analysis area. A processing unit is operative to implement, for each sample to analyze, a detection step to detect the presence of colonies by analyzing an image of the plurality of images of the sample and a determination step to determine the number of colonies present in the sample by counting the colonies whose presence have been detected during the detection step.
US11776282B2	Method, apparatus, and system for removing outliers from road lane marking data An approach is provided for removing outliers from road lane marking data (e.g., using two-phase filtering). The approach involves processing spatial data points representing a road lane into clusters, and filtering cluster(s) away from a main cluster from the clusters to generate an initial filtered data point set. The approach also involves calculating a degree of relationship among the data points of the initial filtered set based on a distance metric to generate group node(s) of the initial filtered set. The approach further involves for each group node, determining a probability that a spatial data point belongs in said each group node by comparing the spatial data point to a center of said each group node, and filtering the spatial data point from said each group node based on determining that the probability is less than a threshold to generate a final filtered data point set.
US11776279B2	Method and apparatus for providing unknown moving object detection An approach is provided for an unknown moving object detection system. The approach, for instance, involves capturing a plurality of unknown object events indicating an unknown object detected by one or more computer vision systems. The approach also involves clustering the plurality of unknown object events into a plurality of clusters based on one or more clustering parameters. The approach further involves selecting at least one cluster of the plurality of clusters based on a selection criterion. The approach further involves determining at least one operating scenario for the one or more computer vision systems based on a combination of the one or more clustering parameters associated with the selected at least one cluster.
US11776273B1	Ensemble of machine learning models for automatic scene change detection Techniques for automatic scene change detection are described. As one example, a computer-implemented method includes receiving a request to train an ensemble of machine learning models on a training dataset of videos having labels that indicate scene changes to detect a scene change in a video, partitioning each video file of the training dataset of videos into a plurality of shots, training the ensemble of machine learning models into a trained ensemble of machine learning models based at least in part on the plurality of shots of the training dataset of videos and the labels that indicate scene changes, receiving an inference request for an input video, partitioning the input video into a plurality of shots, generating, by the trained ensemble of machine learning models, an inference of one or more scene changes in the input video based at least in part on the plurality of shots of the input video, and transmitting the inference to a client application or to a storage location.
US11776269B2	Action classification in video clips using attention-based neural networks Methods, systems, and apparatus, including computer programs encoded on computer storage media, for classifying actions in a video. One of the methods obtaining a feature representation of a video clip; obtaining data specifying a plurality of candidate agent bounding boxes in the key video frame; and for each candidate agent bounding box: processing the feature representation through an action transformer neural network.
US11776263B2	Bidirectional pairing architecture for object detection in video Techniques related to training and implementing a bidirectional pairing architecture for object detection are discussed. Such techniques include generating a first enhanced feature map for each frame of a video sequence by processing the frames in a first direction, generating a second enhanced feature map for frame by processing the frames in a second direction opposite the first, and determining object detection information for each frame using the first and second enhanced feature map for the frame.
US11776260B2	Facility occupancy detection with thermal grid sensor Systems, methods and apparatus for providing an availability status associated with a facility. One system includes an illumination indicator, a thermal grid array sensor, and an electronic controller. The thermal grid array sensor is configured to sense an outside region, an entryway region, and an inside region associated with a facility subsystem. The electronic controller is configured to determine the current availability status as unavailable responsive to the thermal grid array sensor detecting a heat signature in the outside region, subsequently in the entryway region, and subsequently in the inside region. The electronic controller is also configured to determine the current availability status as available responsive to the thermal grid array sensor detecting the heat signature in the inside region, subsequently in the entryway region, and subsequently in the outside region. The electronic controller is further configured to control the illumination indicator to indicate the current availability status.
US11776259B2	Control system of traffic lights and method thereof A control method for traffic lights includes: acquiring an image at a preset time point before a red light is turned off, wherein the image includes at least one vehicle waiting for the red light; determining a time length according to the image, wherein the time length is generated by an artificial intelligence algorithm; and controlling a green light according to the time length.
US11776257B2	Systems and methods for enhancing real-time image recognition Disclosed embodiments provide systems and user devices for enhancing vehicle identification with preprocessing. The systems or user devices may comprise at least one memory device, an augmentation tool, and at least one processor. The at least one processor may be configured to execute instructions to receive an image depicting a vehicle, analyze the image, and determine a first predicted identity of the vehicle and a first confidence value distribution. The at least one processor may further select a processing technique for modifying the image and analyze the modified image to determine a second predicted identity of the vehicle and a second confidence value distribution. The system may further compare the second confidence value distribution to a predetermined threshold or to the first confidence value distribution to select the first or second predicted identity for transmission to a user.
US11776256B2	Shared augmented reality system An augmented reality system to perform operations that include: accessing image data at a client device; determining a position of a user of the client device based on the image data; causing display of a projection that extends from the position of the user upon a presentation of the image data at the client device; detecting an intersection of the projection and a surface of an object; generating a request that includes an identification of the portion of the surface of the object at the client device; and presenting the portion of the surface of the object based on the graphical property of the projection at the client device in response to the request that includes the identification of the portion of the surface of the object.
US11776253B2	Displaying object names in association with augmented reality content Aspects of the present disclosure involve a system comprising a computer-readable storage medium storing a program and method for displaying object names in association with augmented reality content. The program and method provide for receiving, by a messaging application running on a device, a first request to identify plural objects based on an image captured by a camera of the device; identifying, in response to receiving the first request, the plural objects based on the image; for each of the plural objects, determining at least one attribute of the object, and calculating a number of augmented reality content items, from plural augmented reality content items, corresponding to the at least one attribute of the object; selecting, from the plural objects, an object with a largest calculated number of corresponding augmented reality content items; and displaying a name for each of the plural objects based on the selecting.
US11776249B2	Method for identifying non-inspectable objects in packaging, and apparatus and storage medium applying method A method for identifying individual objects and their number and respective locations in a sealed case creates a detection model by using standard data as a training set. Image of the sealed case is captured and divided into a specified number of detection regions. Images of first detection regions in the detection image as taken as local images and input into the detection model. The numbers and locations of target objects in the sealed case is obtained based on a statistic result outputted by the detection model. The standard data includes sample images of the sealed case with different numbers and respective locations of the target objects in the case. A capacity of the sealed case is M, and a number of the sample image is less than 2M. A target identification apparatus and a storage medium applying the method are also disclosed.

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