| Document | Document Title |
|---|---|
| US10785091B2 |
Cognitive thermal cable holder
According to some embodiments of the present disclosure, a computer-implemented method for managing a data center that is temperature controlled using a thermal management system is disclosed. The method includes collecting ambient temperature data in the data center, collecting server temperature data in servers located in the data center, collecting rack temperature data at server racks located in a data center using rack temperature sensors, wherein each rack temperature sensor is associated with one of the server racks, wherein at least one of the server racks includes at least two of the servers. The method further includes analyzing the ambient temperature data, the server temperature data, and the rack temperature data to discover a cause of a fault in the data center, wherein the cause is selected from the thermal management system, the servers, or the rack temperature sensors, and generating a notification regarding the cause of the fault. |
| US10785090B2 |
Using machine learning based on cross-signal correlation for root cause analysis in a network assurance service
In one embodiment, a network assurance service associates a target key performance indicator (tKPI) measured from a network with a plurality of causation key performance indicators (cKPIs) measured from the network that may indicate a root cause of a tKPI anomaly. The network assurance service applies a machine learning-based anomaly detector to the tKPI over time, to generate tKPI anomaly scores. The network assurance service calculates, for each of cKPIs, a mean and standard deviation of that cKPI using a plurality of different time windows associated with the tKPI anomaly scores. The network assurance service uses the calculated means and standard deviations of the cKPIs in the different time windows to calculate cross-correlation scores between the tKPI anomaly scores and the cKPIs. The network assurance service selects one or more of the cKPIs as the root cause of the tKPI anomaly based on their calculated cross-correlation scores. |
| US10785089B2 |
Service-level resiliency in virtualization environments
A set of service-level reliability metrics and a method to allocate these metrics to the layers of the service delivery platform. These initial targets can be tuned during service design and delivery, and feed the vendor requirements process, forming the basis for measuring, tracking, and responding based on the service-level reliability metrics. |
| US10785087B2 |
Modifying computer configuration to improve performance
Embodiments of the present disclosure relate to improving computer performance. An action may be issued to a first client and a second client. A first optimization factor list (OFL) may be generated for the first client and a second OFL may be generated for the second client. After each OFL is generated, the first OFL may be compared to the second OFL. A correlation factor (CF) may be generated between the first client and the second client based on the OFL comparison, wherein the CF indicates a level of similarity between the first client and the second client. A bottleneck causing performance issues in the first client may be determined and computer configuration of the first client may be adjusted based on the bottleneck. |
| US10785084B2 |
Coding and modulation apparatus using non-uniform constellation and different PHY modes
A coding and modulation apparatus and method are presented, particularly for use in a system according to IEEE 802.11. The apparatus comprises an encoder configured to encode input data into cell words according to a low density parity check code, LDPC, and a modulator configured to modulate said cell words into constellation values of a non-uniform constellation and to assign bit combinations to constellation values of the used non-uniform constellation, wherein said modulator is configured to use, based on the PHY mode, the total number M of constellation points of the constellation and the code rate, a particular non-uniform constellation. |
| US10785080B2 |
Determining a number of RACH preamble messages for transmission
Methods, systems, and devices for wireless communications are described. In some systems, base stations and user equipment (UEs) may use beamforming for transmitting random access channel (RACH) messages. A UE may transmit multiple RACH preamble messages (e.g., within a random access response (RAR) window) to initiate a RACH procedure. The UE may transmit the RACH preamble messages in transmission opportunities corresponding to reference signals received from the base station. In some cases, the UE may determine the number of RACH preamble messages to transmit within the RAR window based on an ability of the UE to simultaneously monitor for a RAR message in response to each of the transmitted messages. In other cases, the UE may transmit an indication of UE capabilities to the base station. The base station may determine a RACH resource configuration for the UE based on the capabilities and may indicate the configuration to the UE. |
| US10785078B2 |
Method for signal modulation in filter bank multi-carrier system
A method for signal modulation in a filter bank multi-carrier system is provided. A modulation method according to one embodiment of the present disclosure includes generating a plurality of different candidate transmission signals by modulating a complex symbol vector including a plurality of complex symbols in a discrete Fourier transform (DFT) spread filter bank multi-carrier (FBMC)/offset quadrature amplitude modulation (OQAM) scheme and selecting a candidate transmission signal having a lowest peak power or peak-to-average power ratio (PAPR) as a transmission signal, wherein the generating of the plurality of candidate transmission signals comprises applying a different phase offset to the complex symbol vector according to a candidate transmission signal to be generated. |
| US10785077B1 |
Reconstruction of a skywave symbol
A method for symbol reconstruction, the method comprises: receiving, by a skywave propagation receiver, a partial skywave symbol that comprises a first number (N1) of of legal subcarriers out of a set of a second number (N2) of legal subcarriers that represent a given skywave symbol; wherein the given skywave symbol belongs to a group of skywave symbols; wherein each pair of skywave symbols of the group share up to a third number (N3) of legal subcarriers; and selecting the given skywave symbol from the group when N1 exceeds N3. |
| US10785075B2 |
Radio frequency (RF) to digital polar data converter and time-to-digital converter based time domain signal processing receiver
The present disclosure includes a time-to-digital converter (TDC) based RF-to-digital (RDC) data converter for time domain signal processing polar receivers. Polar data conversion achieves better SNR tolerance owing to its phase convergence near the origin in a polar coordinate. The proposed RDC consists of a TDC for phase detection and an analog-to-digital converter (ADC) for amplitude conversion. Unlike the conversional data converter, the proposed ADC's sampling position is guided by the detected phase result from the TDC's output. This TDC assisted data-converter architecture reduces the number of bits required for the ADC. In addition, oversampling is no longer needed. With precisely controlled tunable delay cells and gain compensator, this hybrid data convertor is capable to directly convert Quadrature Amplitude Modulation (QAM) waveforms and Amplitude Phase Shift Keying (APSK) waveforms directly from the RF signal without down-conversion. Thus, the proposed RDC architecture achieves lower power consumption and better performance comparing with conventional I/Q receivers. |
| US10785072B2 |
Clock data recovery with decision feedback equalization
Methods and systems are described for generating two comparator outputs by comparing a received signal to a first threshold and a second threshold according to a sampling clock, the first and second thresholds determined by an estimated amount of inter-symbol interference on a multi-wire bus, selecting one of the two comparator outputs as a data decision, the selection based on at least one prior data decision, and selecting one of the two comparator outputs as a phase-error decision, the phase error decision selected in response to identification of a predetermined data decision pattern. |
| US10785071B2 |
Communication apparatus and received signal processing method
A wireless communication apparatus includes components below. An equalization unit performs equalization processing on a part of a received signal corresponding to a first range and a part of the received signal corresponding to a second range. The first range includes detection target data. The second range is outside the first range. A replica generation unit decomposes the second range, on which equalization processing has been performed, into a plurality of signal components, and reproduces the part of the received signal corresponding to the second range for each of the signal components to generate a replica of an interference component. An interference cancellation unit cancels the interference component from the part of the received signal corresponding to the first range by using the replica. A data extraction unit extracts the detection target data from the received signal. |
| US10785069B2 |
Early detection and indication of link loss
This disclosure describes techniques for detecting link loss in a physical layer receiver of a communication system. The system includes a slicer coupled to receive, at a slicer input, a signal from a channel equalizer and map the signal to a physical coding sublayer (PCS) level at a slicer output and processor coupled to at least one of the slicer input or the slicer output. The processor is configured to analyze a window of consecutive samples at the at least one of the slicer input or the slicer output over a time window; increment a counter as a function of the window of consecutive samples at the at least one of the slicer input or the slicer output; compare the counter to a threshold; and generate a signal indicating link loss in response to determining that the counter corresponds to the threshold independently of a timer. |
| US10785066B1 |
Can communication with broken cable
A circuit for generating a bias voltage for a terminating end capacitor in a controller area network (CAN) bus having a CANH and a CANL terminals is disclosed. The circuit includes a configurable voltage source, a controller to generate a control signal to operate the configurable voltage source, a CANH error detector and a CANL error detector. The CANH error detector and the CANL error detector are configured to provide inputs to the controller. The controller is configured to generate the control signal based on the outputs of the CANH error detector and the CANL error detector. The configurable voltage source is configured to output a bias voltage based on the control signal. |
| US10785064B1 |
Semiconductor device and method therefor
In one embodiment, a transmitter circuit may be configured to transmit a signal to a receiver. The transmitter circuit may also be configured to detect receiving energy from a transient event, for example detect a transient current, and to direct at least a portion of the energy away from the transmitted signal while the transmitter circuit is transmitting the signal. |
| US10785062B2 |
Method and apparatus for state feedback decoder based channel estimation
The present disclosure relates to a state feedback decoder based channel estimating method including: calculating a first output bit when an input bit is 0 and a second output bit when an input bit is 1 using convolution encoder state information received from a determining unit; configuring a first virtual pilot and a second virtual pilot through modulation by receiving the first output bit and the second output bit; deinterleaving an i-th (here, i refers to a natural number corresponding to the number of OFDM symbols from 1) OFDM symbol; estimating a first channel and a second channel based on the first virtual pilot and the second virtual pilot using an output value in accordance with the deinterleaving result and calculating a first mean square error (MSE) and a second MSE; and comparing the calculated first MSE and second MSE to determine an input bit having a lower MSE as a reception bit by the determining unit and updating and feedbacking the convolution encoder state information using the determined reception bit. |
| US10785061B2 |
Propagation channel estimation method
A propagation channel estimation method is provided. In-phase and quadrature components of a propagation channel estimation value in each pilot subcarrier are separated into amplitude and phase components. A propagation channel of a data subcarrier portion existing between pilot subcarriers is estimated by phase/amplitude separation linear interpolating in each separated amplitude and phase component. A reference parameter is produced by linear interpolating a portion between pilot subcarriers on a complex plane. When quadrants on the complex plane of the interpolated phase component estimation value and the reference parameter are different, a phase connecting process to cancel a discontinuity of the phases is executed to the phase component estimation value interpolated by the phase/amplitude separation linear interpolation. When the quadrants are not different or after the phase connecting process, a complex propagation channel estimation value of the data subcarrier portion is calculated from the phase and amplitude components of the propagation channel estimation value. |
| US10785060B2 |
Efficient channel estimation and symbol detection for massive MIMO-OFDM
A communication system that minimizes the transmission of pilot symbols while ensuring real-time channel tracking and symbol detection. The system employs a multiple-input multiple-output (MIMO) transmitter-receiver pair where there are many more receive antennas than transmit antennas. Communication occurs over a wide band RF channel via orthogonal frequency division multiplexing (OFDM) that employs a large number of sub-carriers. |
| US10785059B2 |
Processing of wireless signals for access points using a central controller
Techniques are disclosed to reduce latency of processing for access points using a central controller. For example, an example method of wireless communication includes receiving, at an access point, a signal wirelessly. The method further includes filtering the signal using a first passband filter having a first bandwidth to generate a first filtered signal. The method further includes filtering the signal using a second passband filter having a second bandwidth to generate a second filtered signal, wherein the first bandwidth is less than the second bandwidth. The method further includes determining whether the signal includes a packet based on the first filtered signal and generating a control signal indicative of the determination. The method further includes transmitting the control signal and the second filtered signal to a central controller. |
| US10785057B2 |
Programmable and reconfigurable frame processor
A programmable and reconfigurable frame processor comprises: a first data processing unit; a first state machine connected to the first data processing unit; a second data processing unit; a second state machine connected to the second data processing unit; and a master state machine respectively connected to the first and second state machines. The first and second data processing units each comprises a frame structure description table for storing a frame header address pointer, a frame tail address pointer and values of respective sections specified in a communication protocol. The first state machine, the second state machine and the master state machine each comprises a protocol state structure description table for storing a header address pointer, a tail address pointer and state transition values. |
| US10785054B2 |
Slave module
A slave module receives a first wake-up signal from an adjacent previous module to perform a wake-up operation and to transmit a second wake-up signal to an adjacent subsequent module. The slave module includes: an analog front end (AFE) including a first terminal and a second terminal, the AFE may be woken up by receiving the first wake-up signal through the first terminal and may output a first voltage through the second terminal in a woken up state; a processor including a third terminal electrically connected to the first terminal, a fourth terminal electrically connected to the second terminal, and a fifth terminal electrically connected to a second slave terminal. The processor may boot up when the first voltage is applied to the fourth terminal, may output a second voltage to the third terminal after being booted up, and may output the second wake-up signal to the fifth terminal. |
| US10785053B2 |
Systems, methods, and apparatuses for implementing persistent management agent (PMA) functions for the control and coordination of DPU and DSLAM components
In accordance with embodiments disclosed herein, an exemplary system or computer implemented method for implementing Persistent Management Agent (PMA) functions for the control and coordination of DPU and DSLAM components may include, for example: a memory to store instructions for execution; one or more processors to execute the instructions; a virtualized module operating on virtualized computing infrastructure, in which the virtualized module is to provide a virtualized implementation of a plurality of functions associated with one or more remotely located Distribution Point Units (DPUs) and/or Digital Subscriber Line Access Multiplexers (DSLAMs), each of the one or more remotely located DPUs and/or DSLAMs having a plurality of broadband lines coupled thereto; in which the virtualized module is to further control Persistent Management Agent (PMA) functions and control coordination of the one or more remotely located DPUs and/or DSLAMs and the plurality of broadband lines coupled with the one or more remotely located DPUs and/or DSLAMs by virtualizing one or more functions of the one or more remotely located DPUs and/or DSLAMs to operate on the virtualized computing infrastructure; and a network interface to receive data and send control instructions for operation of the plurality of broadband lines to and from the one or more remotely located DPUs and/or DSLAMs. Other related embodiments are disclosed. |
| US10785052B2 |
Remote control with muscle sensor and alerting sensor
A remote control system detects a directional signal at an alerting sensor package; activates an appliance to accept a control signal in response to the directional signal; accepts the control signal at the appliance from a muscle sensor package; and adjusts operation of the appliance in response to the control signal. |
| US10785050B2 |
Multi-services gateway device at user premises
An application gateway including application service programming positioned at a user premises can provide voice controlled and managed services to a user and one or more endpoint devices associated with the application gateway. The application gateway can be controlled remotely by the application service provider through a service management center and configured to execute an application service provided from the application service provider. The application gateway can execute the application service at the user premises upon voice command by a user and independent of application services executing on the application service provider's network. An application service logic manager can communicate with an application service enforcement manager to verify that the request conforms with the policy and usage rules associated with the application service in order to authorize execution of the application service on the application gateway, either directly or through endpoint devices. |
| US10785049B2 |
Configuring a common automation system controller
A common automation system controller configured using a graphical approach for use in a building automation system is provided. There is an increasing demand for flexible and adaptable room or building automation applications with an easy and intuitive way for application configuration. In pre-engineering as well as during installation and commissioning, the application configuration for preloaded or loadable device needs to be easily changeable and can be used for operating and/or monitoring. |
| US10785046B1 |
Systems and methods for providing a collaboration work management platform that facilitates differentiation between users in an overarching group and one or more subsets of individual users
Systems and methods for providing a collaboration work management platform that facilitates differentiation between users in an overarching group and one or more subsets of individual users within the overarching group to enable the users within the individual subsets to use the collaboration work management platform differently users within the other subsets, the method being implemented by a computer system including one or more physical processors configured by machine-readable instructions are disclosed. Exemplary implementations may: manage environment state information for maintaining a collaboration environment. |
| US10785043B2 |
Load shedding system, communication method and access apparatus thereof
Provided are an accurate load shedding system, and a communication method and an access apparatus thereof. The access apparatus includes: two E1 interfaces, eight optical fiber interfaces, a CPU and an FPGA. The two E1 interfaces are respectively connected to a control apparatus A and a control apparatus B of a control substation. The eight optical fiber interfaces are respectively connected to eight control terminals. The FPGA includes eight optical fiber transceivers respectively connected to the eight optical fiber interfaces through serial interfaces, and two E1 transceivers respectively connected to the two E1 interfaces through serial interfaces. Each optical fiber transceiver includes a reset submodule. Each E1 transceiver also includes a reset submodule. The CPU is connected to the FPGA through a parallel bus. |
| US10785041B2 |
Method for providing a space puzzle
A method for providing a space puzzle includes computing, by a puzzle generating entity (PGE), a master secret key (MSK), a public key (PK), a random predicate (RP), and a secret key (SK) using the computed MSK and the computed RP; providing, by the PGE, a challenge comprising the PK and the SK to a proving computing entity; computing, by the proving computing entity, a response to the challenge using a size of the RP by computing a higher dimensional virtual structure; encrypting each row of the higher dimensional structure with the PK; decrypting the encrypted rows using the SK to obtain a decrypted predicate; recomputing the RP using the decrypted predicate and the higher dimensional virtual structure to provide a recomputed random predicate; and verifying the provided challenge by comparing the recomputed random predicate with the RP. |
| US10785035B1 |
Anti-replay attack authentication protocol
Disclosed herein are methods, systems, and apparatus, including computer programs encoded on computer storage media, for enhancing blockchain network security. Embodiments of this specification include receiving a transaction request from a client, wherein the transaction request includes a transaction requested to be recorded on a blockchain and a transaction hash calculated based on hashing the transaction; determining the transaction hash is not previously stored in a cache resource or the blockchain; storing the transaction hash in the cache resource; and executing the transaction request. |
| US10785031B2 |
Data encryption of a storage area
A method for encrypting data stored in a memory area is proposed, wherein the data are encrypted on the basis of a key identification for the data and on the basis of a one-time key. |
| US10785028B2 |
Protection of keys and sensitive data from attack within microprocessor architecture
A processor core that includes a token generator circuit is to execute a first instruction in response to initialization of a software program that requests access to protected data output by a cryptographic operation. To execute the first instruction, the processor core is to: retrieve a key that is to be used by the cryptographic operation; trigger the token generator circuit to generate an authorization token; cryptographically encode the key and the authorization token within a key handle; store the key handle in memory; and embed the authorization token within a cryptographic instruction that is to perform the cryptographic operation. The cryptographic instruction may be associated with a first logical compartment of the software program that is authorized access to the protected data. |
| US10785027B2 |
Systems and methods for accessing and controlling media stored remotely
In some embodiments, an apparatus includes a server that stores a set of media files. The server is configured to send an authentication code to a first communication device in response to a request from the first communication device to access the set of media files such that the first communication device can present the authentication code to a user. The server is configured to associate an identifier of a second communication device with the first communication device such that a user of the second communication device can authorize access to the set of media files from the first communication device by sending the authentication code to the server using the second communication device. |
| US10785021B1 |
User account authentication
Methods for authenticating a user account are generally described. In various examples, the methods may comprise performing a first handshake comprising sending authentication data to a first computing device. The authentication data may include a handshake identifier, a user token, and an encryption key. In some examples, the methods may further comprise storing the handshake identifier, the user token, and the encryption key in a database. The methods may further comprise receiving a request for verification of a transaction. The request may comprise the handshake identifier and an encrypted user token. The user token and the encryption key may be retrieved from the database based at least in part on the handshake identifier of the request. The encryption key may be used to decrypt the encrypted user token. A determination may be made that the decrypted user token matches the user token retrieved from the database. |
| US10785017B2 |
Mitigating timing attacks via dynamically scaled time dilation
Techniques for mitigating timing attacks via dynamically scaled time dilation are provided. According to one set of embodiments, a computer system can enable time dilation with respect to a program, where the time dilation causes the program to observe a dilated view of time relative to real time. Then, while the time dilation is enabled, the computer system can track a count of application programming interface (API) calls or callbacks made by a program within each of a series of time buckets and, based on counts tracked for a range of recent time buckets, scale up or scale down a degree of the time dilation. |
| US10785010B2 |
Wireless communications method and apparatus
A wireless communication method is provided. The method includes: determining, by a terminal device, a first coefficient, where the first coefficient belongs to a first coefficient set corresponding to a first transmission time interval TTI, the first coefficient set includes N coefficients, N≥2, and the N coefficients include at least two coefficients used for uplink transmission in the first TTI, or at least two coefficients used for downlink transmission in the first TTI; determining, by the terminal device, a first transport block size TBS based on the first coefficient; and performing, by the terminal device, wireless communication based on the first TBS in the first TTI. Reliability and accuracy of wireless communication can be improved. |
| US10785009B2 |
Reference signal transmission method and related device and system
A reference signal transmission method and a related device and system are disclosed. The method includes: determining, by a first base station, at least one target subframe on a target frequency band, where the target frequency band is a frequency band whose uplink and downlink transmission directions are configurable, and uplink-downlink timeslot configurations and/or transmission directions of the first base station and a neighboring second base station in the at least one target subframe are different; and sending, by the first base station, a first reference signal to first user equipment UE in the at least one target subframe, where the first UE is UE served by the first base station. When embodiments of the present invention are implemented, a reference signal can be transmitted on a flexible frequency band, thereby effectively reducing interference between reference signals between neighboring cells in a flexible duplex system. |
| US10785008B2 |
Determining one or more data modulation profiles for one or more devices
Described herein is a system and method for determining one or more data modulation profiles for one or more devices. The system and method described herein may measure signal quality, such as a modulation error ratio (MER), signal-to-noise ratio (SNR), receive power, transmit power, etc. Based on the signal quality, the system may determine one or more data modulation profile(s) (e.g., quadrature amplitude modulation (QAM) profiles) for a subcarrier, a plurality of subcarriers, a device, and/or a grouping of devices. |
| US10785007B2 |
Dynamic precoding of shared reference signals
A receiver apparatus receives a terminal-specific demodulation reference signal having a rank k and estimates an effective multi-layer channel response, using the received terminal-specific demodulation reference signal. The receiver demodulates first data symbols from first time-frequency resource elements, using the estimate of the effective multi-layer channel response and using a first symbols-to-virtual-antenna mapping matrix M to obtain nc modulation symbols from each of the first time-frequency resource elements, wherein nc>1 and wherein the first symbol-to-transmit-layer mapping matrix M has dimensions k by nc. The first data symbols are decoded to obtain downlink control information assigning second time-frequency resource elements to the receiver. The receiver demodulates second data symbols from the second time-frequency resource elements, using the estimate of the effective multi-layer channel response, to obtain nd modulation symbols from each of the second time-frequency resource elements, wherein 1 |
| US10785006B2 |
Method for transmitting or receiving signal in wireless communication system and apparatus therefor
A method for receiving downlink control information by a terminal in a wireless communication system according to an embodiment of the present invention may comprise the steps of: performing blind detection of a group-common physical downlink control channel (PDCCH) in a common search space (CSS) having a plurality of PDCCH candidates; and acquiring downlink control information (DCI) indicating a slot format from the group-common PDCCH acquired through the blind detection, wherein, in the blind detection of the group-common PDCCH, the terminal attempts to selectively detect the group-common PDCCH for only a PDCCH candidate at a predetermined position in the CSS having the plurality of PDCCH candidates. |
| US10785003B2 |
Systems and methods for adaptation in a wireless network
An embodiment method of network node operation includes indicating, by a first network node, to a first UE, a first number of REs in a first set of RBs for a first reference signal, transmitting, by the first network node, to the first UE, the first reference signal in accordance with the first number of REs and a first precoding in a first subframe, receiving, by the first network node, from the first UE, a report indicating a first MCS in accordance with a level of signal and interference measured by the first UE, wherein the measurement is restricted to the first reference signal, and transmitting, by the first network node, a first data with the indicated first MCS and the first precoding in a second subframe, the first data being transmitted on a second number of REs in the first set of RBs in the second subframe. |
| US10785001B2 |
Systems and methods for UE-specific beam management for high frequency wireless communication
A physical downlink shared channel (PDSCH) region of a subframe may include a reference signal (RS) section that includes one or more of a beam-scanning subsection, a transmit (TX) beam-tracking subsection, a receive (RX) beam-tracking subsection, and a channel state information (CSI) subsection. Reference signals in the TX beam-tracking subsection may be used to update TX analog beams. Reference signals in the RX beam-tracking subsection may be used to update RX analog beams. Reference signals in the beam-scanning subsection may be used to evaluate different combinations of TX and RX analog beams for use in a future directional data transmission. Reference signals in the CSI subsection may be transmitted over quasi-co-located (QCL) antenna ports, and may be used for purposes of channel estimation. |
| US10784999B2 |
Narrowband physical broadcast channel design on multiple anchor channels
Techniques and apparatuses described herein facilitate narrowband communication within the unlicensed frequency spectrum by simultaneously transmitting (e.g., in adjacent channels) a plurality of anchor channels. For example, a base station may simultaneously transmit at least three anchor channels of 180 kHz each so that the 500 kHz minimum bandwidth requirement is satisfied. Furthermore, the techniques and apparatuses described herein provide discovery reference signal (DRS) structures to cause the different types of DRS to be repeated and/or transmitted on different anchor channels, which improves frequency diversity. Also, a synchronization signal of the anchor channels may be used to indicate a configuration of the anchor channels. Thus, synchronization in the NB-IoT-unlicensed (NB-IoT-u) spectrum is enabled, and efficiency is improved over synchronization using a single anchor channel. |
| US10784998B2 |
Wireless communication in multi-rat system
A buffer status reporting scheme for a terminal (10) wishing to transmit data simultaneously in multiple RATs of a wireless communication network, which enables the co-ordination of multiple base stations (12, 14) of different RATs (e.g. LTE eNB, UMTS base station, WiFi access point, etc.) with the assistance of the terminal (10) in order to achieve efficient radio resource scheduling for multi-RAT multi-flow aggregation in uplink. A radio bearer is configured for multi-RAT multi-flow aggregation by the network, and multiple logical channel IDs are assigned to this RB that may be associated with different RATs. Logical channels associated with a certain RAT (or a given set of RATs) may be grouped into one logical channel group for radio resource scheduling reason. The terminal (10) performs buffer status reporting, according to the configuration, on all involved RATs and sends reports/indications to one or more involved base stations (12.14). |
| US10784994B2 |
Method for transmitting information for LTE-WLAN aggregation system and a device therefor
The present invention relates to a wireless communication system. More specifically, the present invention relates to a method and a device for transmitting information for LTE-WLAN aggregation system, the method comprising: checking, by a Packet Data Convergence Protocol (PDCP) entity, whether a FCI transmission condition is met or not; and transmitting Flow Control Information (FCI) when the FCI transmission condition is met. |
| US10784991B2 |
Polar code construction for low-latency decoding and reduced false alarm rate with multiple formats
A transmitter may select a control message format of a set of possible control message formats, each of the possible control message formats corresponding to a different number of information bits. The transmitter may polar encode a payload in the selected control message format to generate and transmit a polar-encoded codeword, the payload having a same number of bits for any of the set of possible control message formats. A receiver may determine the set of possible control message formats for the polar-encoded codeword, and may decode the polar-encoded codeword to identify a candidate control message. The receiver may identify a control message format in the set of possible control message formats for the candidate control message based on multiple hypotheses corresponding to the different number of information bits, and may obtain control information from the candidate control message based on the identified control message format. |
| US10784989B2 |
Bit error correction for wireless retransmission communications systems
A system includes a transmitter configured to transmit an original packet. The system also includes a receiver comprising a processing device. The processing device is configured to receive a corrupted Bluetooth® packet of the original packet and at least one retransmitted packet of the original packet. The processing device is also configured to generate an accumulated packet based on the corrupted packet and the at least one retransmitted packet, and generate a decision packet for the original packet based on the accumulated packet. The processing device is further configured to verify the decision packet to determine whether the decision packet is correct. |
| US10784983B2 |
Assembly comprising a noise emitting element
An assembly of a standard RFID/NFC element and a scrambling element for outputting wireless noise in response to a wireless request signal from a terminal, such as NFC, RFID or the like. The scrambling element has a noise generating circuit and an antenna for receiving the request signal and outputting a voltage. The scrambling element further comprises a voltage increasing element receiving the voltage from the antenna and feeding a higher voltage to the circuit to have the circuit start operation faster than the circuit of the standard RFID/NFC element. |
| US10784982B2 |
Method and system for allocating wavelength channels in passive optical network, and optical line terminal
Provided are a method and system for allocating wavelength channels in a Passive Optical Network (PON), and an Optical Line Terminal (OLT). In the method, an OLT may acquire pre-set wavelength channel priority information and Optical Network Unit (ONU) priority information; and the wavelength channel priority information and the ONU priority information may be sent to each ONU to enable each ONU to selectively access a corresponding wavelength channel according to the wavelength channel priority information and the ONU priority information based on a pre-set rule. |
| US10784981B2 |
System for loading fiber optic transport systems for channel additions and deletions
A system for loading a fiber optic transport system includes a wavelength selective switch (WSS) having inputs and an output connected to an optical fiber, wherein the inputs are connected to one or more lines having data-bearing channels thereon; and an amplified spontaneous emission (ASE) generator connected to one of the inputs of the WSS, wherein the WSS is configured to perform a channel addition through substitution of an ASE channel from the ASE generator for a data-bearing channel, and a channel deletion through substitution of a data-bearing channel for an ASE channel from the ASE generator, and wherein, to limit perturbations on the optical fiber due to channel additions and deletions, the WSS is configured to limit a number of channels that are switched at a same time for a set of channel additions or deletions. |
| US10784975B1 |
Systems and methods for automatically tuning a radio system to a preferred channel
Computing devices are disclosed. For example, a computing device includes one or more processors and one or more databases. The computing device includes one or more non-transitory memory modules storing machine-readable instructions that, when executed, cause the one or more processors to: receive a plurality of event flags, wherein each event flag of the plurality of event flags is associated with a respective broadcasted audio signal of a plurality of broadcasted audio signals; compare the plurality of event flags to a user profile stored within the one or more databases, wherein the user profile comprises preference characteristics associated with a user; determine whether one or more event flags matches a set of preference characteristics of the user profile; and transmit a notification signal to a vehicle in response to the one or more event flags matching the set of preference characteristics of the user profile. |
| US10784973B2 |
Remotely testing operational components of a mobile device
Implementations of the disclosure provide for to remotely testing operational components of a mobile device. In one implementation, a method is provided. The method includes providing, by a server processing device, instructions to a mobile device for a user to interact with a component of the mobile device. Data associated with an operation of the component in view of the instructions is received. The received data is compared to a model input characterizing a functional level associated with the operation of the component. Thereupon, it is determined whether there is a depleted operation of the component in view of the comparison. |
| US10784967B2 |
Photonic radio-frequency receiver with mirror frequency suppression function
A photonic radio-frequency receiver with mirror frequency suppression function, in which a single modulator is utilized to form a photoelectric oscillator so as to generate high-quality and low-phase-noise optically generated local oscillators, without the need for an external local oscillator source, and at the same time, another radio-frequency port is used as a radio-frequency signal input port, thereby allowing a compact structure. By properly setting a bias point for the two-electrode modulator and orthogonally synthesizing two branches of intermediate frequency signals respectively generated by the upper and lower sideband beat frequencies of the modulated optical signal, the photonic radio-frequency receiver realizes the functions of receiving radio-frequency signals and suppressing mirror frequency signals. The present disclosure can realize a photonic mirror-frequency suppression receiver. |
| US10784960B2 |
Fiber delivered laser based white light source configured for communication
A packaged integrated white light source configured for illumination and communication or sensing comprises one or more laser diode devices. An output facet configured on the laser diode device outputs a laser beam of first electromagnetic radiation with a first peak wavelength. The first wavelength from the laser diode provides at least a first carrier channel for a data or sensing signal. |
| US10784958B2 |
Method and device of determining a time-of-flight of an optical signal between a starting point of an optical path and a reflection point within the optical path
The invention relates to a method of determining a time-of-flight of an optical signal between a starting point and a reflection point of an optical path, comprising: supplying to the path at least one optical probing signal; detecting an electrical return signal according to an optical return signal returning from the path in response to a corresponding one of the probing signals using direct detection; deriving at least one receive code sequence by sampling and slicing the return signal using a sampling rate corresponding to a bit rate of a sequence of pulses of the probing signal; determining a correlation function by correlating the transmit code sequence and the at least one receive code sequence; and identifying a main peak of the correlation function that corresponds to the reflection point and a time position of the peak, and determining the time-of-flight as the time position of the peak. |
| US10784956B2 |
Sparing configurations and protocols for parallel fiber optics
A transmitter can include: at least one primary laser emitter configured to emit primary laser light; at least one primary monitor photodiode optically coupled with the at least one primary laser emitter; and at least one spare laser emitter configured to emit spare laser light. Each spare laser emitter can be adjacent with a corresponding primary laser emitter such that a first primary laser emitter and a first spare laser emitter pair are directed through an optical system and out a common optical fiber. |
| US10784954B2 |
Dynamic satellite beam assignment
Embodiments provide techniques for dynamic spot beam assignment in a geostationary satellite communications network. For example, a ground processing node in the geostationary satellite network can monitor spot beam coverage area location and can detect a beam drift trigger indicating present drifting of one or more coverage areas. Ground terminals can be identified as serviced by spot beams associated with the drifting coverage area(s) and as experiencing a signal quality impact from the drifting. The ground terminal node can compute an update to a beam assignment map having a reassignment of the identified user terminals from their presently servicing spot beams to another of the spot beams in a manner that seeks to address at least some of the signal quality impact identified as associated with the drifting. Some embodiments further account for load balancing, and/or other factors, and/or can maintain stateful communications between the reassigned user terminals and the geostationary satellite. |
| US10784950B2 |
Method for performing beam failure recovery in wireless communication system and apparatus therefor
This specification provides a beam failure recovery method in a wireless communication system. In this specification, a beam failure recovery method performed by a UE includes: receiving, from a base station, control information related to a candidate beam configuration for the beam failure recovery; selecting an RS having a quality of the threshold or more among the RSs related to the candidate beam identification; and; transmitting, to the base station, a beam failure recovery request based on an uplink (UL) resource related to the selected RS. |
| US10784948B2 |
Apparatus and method for beam failure recovery
The disclosure relates to technology for identifying a user equipment beam index in a base station. The base station indicates one or more resources assigned to the user equipment within a beam failure random access channel (BRACH) resource, and transmits one or more synchronization signal block resources and one or more new beam identification reference signal resources to the user equipment. The base station then receives one of the resources from a group of the one or more resources within the BRACH resource assigned to the user equipment corresponding to the BRACH resource, and identifies a preferred beam index of the user equipment based on information in the BRACH resource and the received one of the resources. |
| US10784942B2 |
System and method for beamed reference signal with hybrid beam
Described is an apparatus of an Evolved Node-B (eNB). The apparatus may comprise a first circuitry, a second circuitry, and a third circuitry. The first circuitry may be operable to associate a first Beam Reference Signal (BRS) for a first Transmit (Tx) beam having a first beamwidth with one or more second BRSes for one or more respectively corresponding second Tx beams having a second beamwidth. The second circuitry may be operable to generate a first BRS transmission carrying the first BRS, and to generate one or more second BRS transmissions carrying the one or more respectively corresponding second BRSes. The third circuitry may be operable to provide information regarding the first BRS and the second BRSes to the second circuitry. |
| US10784941B2 |
Minimizing network planning using reference signal grouping
According to some embodiments, a method for use in a network node of transmitting reference signals in a wireless network using a plurality of beams comprises obtaining a node identifier for the network node. The node identifier is unique for neighboring network nodes within a particular coverage area of the wireless network. The method further comprises obtaining a group of reference signal sequences. The group comprises a subset of a pool of possible reference signal sequences for use in the wireless network. Each reference signal sequence is associated with a beam reference identifier. The method further comprises selecting a reference signal sequence from the obtained group: scrambling a reference signal transmission pattern using the obtained node identifier and the selected reference signal sequence with associated beam reference identifier; and transmitting the scrambled reference signal transmission pattern to a user equipment on one of the beams among the plurality of beams. |
| US10784940B2 |
5G platform-oriented node discovery method and system, and electronic device
A 5G platform-oriented node discovery method and system, and an electronic apparatus are provided. A macro eNB sends a measurement configuration parameter to a user equipment, determines a cooperation set and a main transmission point base on a measurement report, schedules resource in real-time through the cooperation set and the main transmission point; when the user equipment moves, transmits a modified measurement configuration parameter, and determines a new cooperation set and a target transmission point of the new cooperation set base on the measurement report, schedules resources in real-time through the new cooperation set and the target transmission point. |
| US10784939B2 |
Method and apparatus for calculating CQI in a wireless communication system
Disclosed in the present invention is a method for a user equipment reporting channel state information to a base station in a wireless communication system. The method for reporting CSI comprises the steps of: receiving, from the base station, a channel state information-reference signal (CSI-RS) defined by at least two antenna ports; estimating the rank of a downlink channel based on the CSI-RS; configuring a plurality of precoders corresponding to the estimated rank with at least two precoder groups; calculating a channel quality indicator under the assumption that the at least two precoder groups are rotationally applied to at least one resource block unit, wherein precoders included in the precoder groups rotationally applied to the at least one resource block unit is rotationally applied to at least one resource element unit; and reporting the CSI including the calculated CQI to the base station. |
| US10784933B2 |
Transmission device and transmission method
A transmission device comprising: a weighting circuitry which, in operation, generates transmission signals of n streams (n is an integer of 3 or more) by weighting modulated signals of the n streams using a predetermined fixed precoding matrix; a phase changing circuitry which, in operation, regularly changes each phase of a symbol series included in each of the transmission signals of the n streams; and a transmitter which, in operation, transmits the transmission signals of the n streams from different antennas, the phases of each of the transmission signals of the n streams being changed in each symbol, wherein the transmission signal of an i-th stream has an mi kind of phase change value yi(t) (i is an integer between 1 and n (inclusive), 0≤yi<2π, and mi is set in each stream, t is an integer of 0 or more, and indicates a symbol slot), and the phase changing circuitry changes the phase in one or more u (u=m1×m2× . . . ×mn) symbol periods using all patterns of a set of phase change values yi(t) different from each other in each symbol. |
| US10784930B2 |
Systems and methods for dynamic inter-sector MIMO transmission
A system includes a first antenna array, and a sector scheduler. The sector scheduler determines if a number of transmit antennas of the first antenna array, that serves a location of a user equipment (UE), is less than a maximum multiple-input, multiple-output (MIMO) capability of the UE. The sector scheduler causes data to be transmitted to the UE via one or more transmit antennas of the first antenna array and at least one transmit antenna associated with a second antenna array of a selected adjacent sector based on the number of transmit antennas of the first antenna array being less than the maximum MIMO capability of the UE. |
| US10784928B2 |
Rotary data coupler
Various examples are directed to a rotary coupler and methods of use thereof. The rotary data coupler may comprise a transmitter and receiver. The transmitter may comprise a first band and a second transmitter band. The receiver may comprise a receiver housing positioned to rotate relative to the first transmitter band and the second transmitter band. A first receiver band may be positioned opposite the first transmitter band to form a first capacitor and a second receiver band may be positioned opposite the second transmitter band to form a second capacitor. The receiver may also comprise a resistance electrically coupled between the first receiver band and the second receiver band and a differential amplifier. The differential amplifier may comprise an inverting input and a non-inverting input, with the non-inverting input electrically coupled to the first receiver band and the inverting input electrically coupled to the second receiver band. |
| US10784919B2 |
Adaptation circuit for a transceiver
Examples provide an adaptation circuit and apparatus, method and computer programs for adapting, fabricating and operating, a radio transceiver, a mobile transceiver, a base station transceiver and storage for computer programs or instructions. The adaptation circuit (10) is configured to adapt a local oscillator signal in a radio transceiver (30). The radio transceiver (30) comprises a transmission branch (14) and a reception branch (16), which are subject to cross-talk. The reception branch (16) comprises a local oscillator (18) configured to generate the local oscillator signal. The adaptation circuit (10) comprises a control module (12) configured to determine crosstalk level information between the transmission branch (14) and the reception branch (16), and to adapt the local oscillator signal based on the crosstalk level information. |
| US10784917B2 |
PSI5 base current sampling in synchronous mode
Multiple sensors are coupled to a first pin of a PSI5 transceiver to receive a sensor bus signal. A Manchester decoder is coupled to a second pin and a battery is coupled to a third pin. A comparator receives a first voltage that is proportional to a current on the sensor bus signal and a second voltage that is proportional to a base current on the sensor bus signal and sends a data output signal to the second pin. A sample-and-hold circuit captures a third voltage used to effect the second voltage responsive to a high value on a base current sampling signal. A base-current-renewal circuit detects edge transitions on the data output signal and when the data output signal has no edge transitions for a period of time greater than a gap time defined in a PSI5 standard, sets the base current sampling signal high. |
| US10784916B2 |
Mobile device cover for use with a host mobile device
A mobile device cover for use with a host mobile device includes a front frame, a middle frame, and a back frame. The back frame includes a plate or portion that can be removed and interchanged with a second plate or portion. The second plate or portion can be designed to look different and to provide different functionality. For example, the plate or portion of the back frame can be replaced with the second interchangeable plate or portion to provide a screen that can be used by one or both of the mobile device cover and the host mobile device. |
| US10784915B2 |
Compression sleeve carrying system for mobile electronic devices
A compression sleeve carrying system for mobile electronic devices such as cell phones that are between 3.5 inches wide and 6.5 inches long, with or without an additionally attached phone case. The carrying sleeve has a pocket for key, credit card, and money storage. The sleeve employs an elastic system that connects four corner brackets in which each corner of the phone sits in. Elastic weaves through the corner brackets and through the a patch system. The patch system is attached to a stretchable fabric under the brackets and the patch system is sewn into the arm sleeve to prevent sweat from getting to the phone. The phone retention space stretches based off of the size of the phone and the brackets have a 0.5 inch space that fits both cell phones or other cell phone size and devices. |
| US10784913B2 |
Antenna for wearable electronic devices
A wearable electronic device includes a first member and a second member. The second member includes a first, RF-attenuating, portion and a second, electrically conductive portion. A gap exists between the first member and at least the second portion of the second member. One or more transmitter/receivers, such as one or more BLUETOOTH®, BLUETOOTH® low energy, and/or IEEE 802.11 transceivers may be mounted in the first member. The one or more transmitter/receivers are conductively coupled to the second portion of the second member. RF signals generated by the one or more transceivers are emitted from the second portion of the second member. |
| US10784912B2 |
Wireless communication device
The invention relates to a wireless communication device 1 having an upper part 10 and a bottom part 11, the upper part 10 comprising one or more transmission antenna device(s) 12a, 12b; 15. The upper part 10 and the bottom part 11 are arranged movably in relation to each other, so that the bottom part 11, in use mode, is closer to the user than the upper part 10. The bottom part 11 comprises one or more reception antenna device(s) 14a, 14b, 14c, 14d. |
| US10784909B2 |
Receiver and non-transitory computer readable medium storing program
A receiver and a program capable of, when they have received a pulse noise together with a reception signal, improving quality of the reception signal are provided. A receiver according to the present disclosure includes a received-signal amplification circuit configured to amplify a monitoring received signal branched from a received signal, a gain control circuit configured to set a gain setting value for an AGC operation in the received-signal amplification circuit, the AGC operation being an operation for making an amplitude of an amplified monitoring received signal fall within a predetermined range, a pulse detection circuit configured to monitor a change in the gain setting value and detect whether or not a pulse noise is contained in the received signal based on whether or not the change in the gain setting value meets a predetermined condition. |
| US10784908B2 |
Spur reduction circuit and apparatus, radio transceiver, mobile terminal, method and computer program for spur reduction
Examples provide a spur reduction circuit and a spur reduction apparatus, a radio transceiver, a mobile terminal, a method and a computer program for spur reduction. The spur reduction circuit (10) is configured to reduce spur interference in a baseband radio signal, d(n), n indexing samples and comprises at least one input (12) for the baseband radio signal, d(n), and information on at least one spur frequency, ω(n). The spur reduction circuit further comprises an adaptive filter (14) configured to filter the baseband radio signal, d(n), to obtain a baseband radio signal with reduced spur interference, e(n). The adaptive filter (14) is further configured to filter the baseband radio signal, d(n), based on at least one filter coefficient, w(n), and based on the information on the at least one spur frequency, ω(n). The spur reduction circuit (10) further comprises an update module (16) configured to adapt the at least one filter coefficient, w(n), based on the baseband radio signal with reduced spur interference e(n). The spur reduction circuit (10) further comprises at least one output (18) for the baseband signal with reduced spur interference e(n). |
| US10784907B2 |
Apparatus to detect interference in wireless signals
An apparatus to detect interference in wireless signals, comprising an antenna for receiving a wireless signal; and wherein the apparatus is operable to identify a dominant waveform in the received signal; subtract the dominant waveform from the received signal to create a modified received signal; and repeat the above steps, recursively substituting the modified received signal for the received signal, until all adjusted reference waveforms have been subtracted. |
| US10784906B2 |
Transmitting device, transmitting method, and communication system
A transmitting device of the present disclosure include: a first driver that includes a first sub-driver unit which operates on a basis of a first control signal and a second sub-driver unit which operates on a basis of, of the first control signal and a second control signal, a signal selected through a first selecting operation, and is configured to be able to set a voltage at a first output terminal; and a controller that controls the first selecting operation. |
| US10784904B2 |
Transceiver configuration for millimeter wave wireless communications
Methods, systems, and devices are described for transceiver architecture for millimeter wave wireless communications. A device may include two transceiver chip modules configured to communicate in different frequency ranges. The first transceiver chip module may include a baseband sub-module, a first radio frequency front end (RFFE) component and associated antenna array. The second transceiver chip module may include a second RFFE component and associated antenna array. The second transceiver chip module may be separate from the first transceiver chip module. The second transceiver chip module may be electrically coupled to the baseband sub-module of the first transceiver chip module. |
| US10784897B2 |
Deinterleaver
A method, apparatus, and system for a deinterleaver. |
| US10784893B2 |
Method and apparatus for low density parity check channel coding in wireless communication system
A low density parity check (LDPC) channel encoding method for use in a wireless communications system includes a communication device encoding an input bit sequence by using a LDPC matrix to obtain an encoded bit sequence for transmission. The LDPC matrix is obtained based on a lifting factor Z and a base matrix. The encoding method can be used in various communications systems including the fifth generation (5G) telecommunication systems, and can support various encoding requirements for information bit sequences with different code lengths. |
| US10784892B1 |
High throughput hardware unit providing efficient lossless data compression in convolution neural networks
An apparatus includes a first memory interface circuit and a decompression circuit coupled to the first memory interface circuit. The decompression circuit may be configured to (i) receive a reduced size representation of a coding block of data comprising a first bit map, a second bit map, and zero or more non-zero values from an external memory via the first memory interface circuit, (ii) losslessly restore the coding block of data from the reduced size representation of the coding block using the first bit map, the second bit map, and the zero or more non-zero values, and (iii) transfer the restored coding block of data to a processing circuit. |
| US10784888B2 |
Use of differently delayed feedback to suppress metastability in noise shaping control loops
Described herein is a ΣΔ modulator with improved metastability in which the control loop remains stable. In one embodiment, the ΣΔ modulator utilizes differently delayed feedback to successive integrators of the control loop to suppress metastability errors without compromising the stability of the control loop. This is accomplished by including one or more quantizers in the control loop. This technique may be applied to control loops of at least second order, i.e., having two or more integrator stages, where at least one feedback term after the first is non-zero. |
| US10784885B2 |
Semiconductor device and electronic device
A semiconductor device in which an increase of circuit area is prevented is provided. A semiconductor device including a control circuit with a plurality of scan chain circuits, a DA converter electrically connected to the control circuit, and a plurality of potential holding units electrically connected to the DA converter is provided. The plurality of potential holding units each include a transistor including an oxide semiconductor in a channel formation region and a capacitor electrically connected to the transistor. In accordance with digital data held in any one of the plurality of scan chain circuits, an output potential output from the DA converter is held in any one of the plurality of potential holding units. |
| US10784883B1 |
Noise shaping analog-to-digital converter
In certain aspects, an analog-to-digital converter includes a first capacitive digital-to-analog converter (DAC), a second capacitive DAC, and a comparator including a first input, a second input, and an output. The analog-to-digital converter also includes a switch circuit including a first input coupled to the first capacitive DAC, a second input coupled to the second capacitive DAC, a first output coupled to the first input of the comparator, and a second output coupled to the second input of the comparator. The analog-to-digital converter further includes a first switch coupled between the output of the comparator and the first input of the comparator, and a successive approximation register (SAR) coupled to the output of the comparator, the first capacitive DAC, and the second capacitive DAC. |
| US10784877B2 |
Extended period timer circuits for ophthalmic devices
Programmable timer circuits are disclosed. One timer circuit may include a reference circuit configured to generate a bias current, a current controlled oscillator configured to receive the bias current c, and a frequency divider network configured to divide an output of the oscillator. The timer circuit may be capable of timing for 24 hour period, while using less than 5nA of quiescent current. |
| US10784873B1 |
Square wave-to-sine wave converter
A circuit includes a bandpass filter and a self-tracking circuit. The bandpass filter has a first input node configured to receive an input square wave signal and an output node configured to provide an output sine wave signal. The bandpass filter includes a first binary-weighted programmable resistor array. The self-tracking circuit includes a second input node coupled to the output node. The self-tracking circuit includes a counter, and the counter includes an output node coupled to the first binary weighted programmable resistor array. |
| US10784872B1 |
Fractional realignment techniques for PLLs
Systems, methods, and devices for fractional realignment are disclosed herein. A feedback divider generates a feedback dividing clock signal based on a controlling oscillator frequency. A delta-sigma modulator is coupled to the feedback divider and generates a dividing ratio to the feedback divider. An accumulating phase adjustor is coupled to the delta-sigma modulator and (i) determines a difference between a frequency tuning word (FCW) and the dividing ratio and (ii) generates a coarse tuning word and a fine tuning word. A digital-to-time converter (DTC) is coupled to the accumulating phase adjustor and generates a first clock frequency based on a reference clock frequency, the coarse tuning word and the fine tuning word. A realignment pulse generator is coupled to the DTC and generates a realignment clock based on the first clock frequency having a period that is the same as a period of the controlling oscillator frequency. |
| US10784871B1 |
Clocking architecture for DVFS with low-frequency DLL locking
A circuit and corresponding method for dynamic voltage frequency scaling (DVFS) on a chip employ a delay-locked loop (DLL)-based clocking architecture. The circuit comprises a DLL including a fixed delay line path, with a first insertion delay, and variable delay line path, with a second insertion delay, and a clock generator. The clock generator is configured to source a DLL input clock to the fixed and variable delay line paths at a start-up frequency prior to a run-time frequency. The start-up frequency is lower relative to a target frequency for the chip. The run-time frequency is configured based on DVFS, following release of the chip from reset. The chip is configured to be released from reset with the DLL locked at the start-up frequency, enabling the second insertion delay to match the first insertion delay with the DLL locked at the start-up frequency. |
| US10784868B1 |
Low power logic circuitry
A combinational logic circuit includes input circuitry to receive a first input signal that transitions between upper and lower voltages of a first voltage domain, and to generate, in response to the transitions of the first input signal, a first localized signal that transitions between upper and lower voltages of a second voltage domain. The combinational logic circuit additionally includes output circuitry to generate a first output signal that transitions between the upper and lower supply voltages of the first voltage domain based at least in part on the transitions of the first localized signal. |
| US10784867B1 |
Supply difference controlled cross-coupled level shifting circuit
A level shifting circuit for a voltage level translator includes first and second cross-coupled level shifters, each coupled between an output supply voltage and a lower rail and further coupled to receive first and second input control signals and to provide an output control signal. The second cross-coupled level shifter includes a first PMOS transistor coupled in series with a first NMOS transistor and a second PMOS transistor coupled in series with a second NMOS transistor. When an input supply voltage is less than a VCCI trigger associated with the output supply voltage, only the first and second NMOS transistors are coupled to contribute to the output control signal and when the input supply voltage is equal to or greater than the VCCI trigger, only the first and second PMOS transistors are coupled to contribute to the output control signal. |
| US10784864B1 |
Low power integrated clock gating system and method
According to one general aspect, an apparatus may include a latch circuit configured to, depending in part upon a state or at least one enable signal, pass a clock signal to an output signal. The latch circuit may include an input stage controlled by the clock signal and the enable signal(s). The latch may include an output stage configured to produce the output signal. The input and output stages may share a common transistor controlled by the clock signal. |
| US10784858B2 |
Driver circuit, corresponding system and method
A driver circuit includes a supply node, a control node configured to receive a control signal, and an output node. An output transistor is coupled to the output node to provide the CAN bus drive signal via the current path through the output transistor. A current mirror is in a current line from the supply node to the output node through the output transistor. The current line includes an intermediate portion between the current mirror and the output transistor. The current mirror is configured to be switched, as a function of the control signal between a first, dominant mode, with the CAN bus drive signal applied to the output node via the output transistor, and a second, recessive mode, with the output transistor providing a high output impedance at the output node. |
| US10784856B2 |
Semiconductor device
A semiconductor device includes a first drive circuit and a bootstrap control circuit. When a voltage VB is equal to or smaller than a power supply voltage VCC, the boost control circuit turns on a MOSFET by controlling a gate signal input to a gate terminal, and a back gate control circuit makes a voltage applied to a back gate terminal smaller than the voltage VB. |
| US10784853B2 |
Semiconductor device having a bidirectional switch and a passive electrical network
A device includes a semiconductor body having an active region and a substrate region that is beneath the active region. A bidirectional switch is formed in the semiconductor body having first and second gate structures that are configured to block voltage across two polarities as between first and second input-output terminals that are in ohmic contact with the electrically conductive channel. First and second switching devices are configured to electrically connect the substrate region to the first and second input-output terminals, respectively. A passive electrical network includes a first capacitance connected between a control terminal of the first switching device and the second input-output terminal and a second capacitance connected between a control terminal of the second switching device and the first input-output terminal. The passive electrical network is configured temporarily electrically connect the substrate region to the first and second input-output terminal at different voltage conditions. |
| US10784847B1 |
Duty cycle correction circuit
A duty cycle correction circuit includes a duty cycle adjuster that is configured to receive first and second differential input signals having first and second duty cycles, respectively, that are distorted with respect to a reference duty cycle. The duty cycle adjuster is further configured to iteratively adjust the first and second duty cycles to generate first and second differential output signals having third and fourth duty cycles that are within a predefined range of the reference duty cycle, respectively. During each iteration, the duty cycle adjuster adjusts the first and second duty cycles based on correction bits that are generated based on a duty cycle detection signal that indicates whether the third duty cycle is greater than or less than the fourth duty cycle, and a lock signal that is activated when the duty cycle detection signal toggles from one logic state to another. |
| US10784833B2 |
Lamb acoustic wave resonator and filter with self-aligned cavity via
A method for forming a lamb acoustic wave resonator and filter and the resulting device are provided. Embodiments include forming a sacrificial layer over a substrate; forming a first electrode over the sacrificial layer; forming a piezoelectric thin film over the first electrode; forming a second electrode over the piezoelectric thin film; forming a hardmask over the second electrode; etching through the hardmask and the second electrode down to the piezoelectric thin film forming self-aligned vias; forming and patterning a photoresist layer over the self-aligned vias; etching through the photoresist layer forming cavities extending through the vias and to the sacrificial layer; and removing the sacrificial layer forming a cavity gap under the cavities and first metal electrode. |
| US10784832B2 |
Film bulk acoustic resonator and method of fabrication same
A film bulk acoustic resonator (FBAR) and a method of fabricating the FBAR are disclosed. In the method, formation of several mutually overlapped and hence connected sacrificial material layers above and under a resonator sheet facilitates the removal of the sacrificial material layers. Cavities left after the removal overlap at a polygonal area with non-parallel sides. This reduces the likelihood of boundary reflections of transverse parasitic waves causing standing wave resonance in the FBAR, thereby enhancing its performance in parasitic wave crosstalk. Further, according to the invention, the FBAR is enabled to be integrated with CMOS circuitry and hence exhibits higher reliability. |
| US10784828B2 |
Methods and apparatus for an operational amplifier with a variable gain-bandwidth product
Various embodiments of the present technology comprise a method and apparatus for an operational amplifier with a variable gain-bandwidth product. According to various embodiments, an amplifier circuit comprising the operational amplifier operates in multiple stages and provides a low gain-bandwidth and a high gain-bandwidth. |
| US10784826B2 |
Bias sequencing and switching circuit
The present disclosure provide a device, system, and method for generating, in an electrical device, a 1 bit or a 0 bit that is received in a switching circuit powered by a battery. The device, system, and method generates, in the switching circuit, a negative bias voltage and a positive bias voltage. The device, system, and method transmits the negative bias voltage and the positive bias voltage to a power amplifier. The device, system, and method turns the power amplifier from an off-state to an on-state in response to receiving the negative bias voltage. The device, system, and method amplifies, with the power amplifier, a power signal moving through power amplifier when the amplifier is in the on-state. |
| US10784825B2 |
RF power amplifier with frequency selective impedance matching network
An amplifier circuit includes an input port, an output port, and a reference potential port, an RF amplifier device having an input terminal electrically coupled to the input port, an output terminal electrically coupled to the output port, and a reference potential terminal electrically coupled to the reference potential port. An impedance matching network is electrically connected to the output terminal, the reference potential port, and the output port. The impedance matching network includes a reactive efficiency optimization circuit that forms a parallel resonant circuit with a characteristic output impedance of the peaking amplifier at a center frequency of the fundamental frequency range. The impedance matching network includes a reactive frequency selective circuit that negates a phase shift of the RF signal in phase at the center frequency and exhibits a linear transfer characteristic in a baseband frequency range. |
| US10784819B2 |
Apparatus and methods for power amplifiers with positive envelope feedback
Apparatus and methods for power amplifiers with positive envelope feedback are provided herein. In certain implementations, a power amplifier system includes a power amplification stage that amplifies a radio frequency signal, at least one envelope detector that generates one or more detection signals indicating an output signal envelope of the power amplification stage, and a wideband feedback circuit that provides positive envelope feedback to a bias of the power amplification stage based on the one or more detection signals. The power amplifier system further includes a supply modulator that controls a voltage level of a supply voltage of the power amplification stage based on the one or more detection signals such that the supply voltage is modulated with the output signal envelope through positive envelope feedback. |
| US10784817B2 |
Oscillator, electronic apparatus and vehicle
Provided is an oscillator including a resonator which includes a resonator element and a resonator element container accommodating the resonator element, an integrated circuit element which includes an inductor, and a nonconductive spacer member, in which the resonator and the integrated circuit element are stacked above each other, the resonator has a metal member, and the spacer member is provided between the resonator and the integrated circuit element. |
| US10784816B2 |
Electrical and mechanical roof underlayment
The invention is an electrical and mechanical roof underlayment which provides electrical and mechanical connection of solar shingles to a roof. The underlayment simplifies the installation of solar shingles allowing the shingles to be installed and connected together in the same step. The underlayment includes a membrane which has embedded electrical conductors and electrical connectors that provides an electrical connecting system extending to an electrical circuit. The membrane further has embedded mechanical members with mechanical connectors that secure the shingles to the membrane. The membrane is structurally attached to a roof surface. The structural attachment may be an adhesive attachment. Solar shingles are connected to the membrane by an integral clasping mechanism that mechanically and electrically connects the shingles to the membrane. No external wiring, connectors or devices are required to make the electrical connection between the shingles and the membrane. Contacts are integral and embedded into each individual shingle. |
| US10784814B2 |
Support apparatus for photovoltaic module and photovoltaic system
A support apparatus for a photovoltaic module and a photovoltaic system are provided. The support apparatus for a photovoltaic module is to be arranged on a water surface, and includes: a support body for mounting the photovoltaic module; and a floating body connected to the support body and configured to provide buoyancy for the support apparatus. A connection function for providing connection with the photovoltaic module and a buoyancy function for providing the buoyancy are separated. The support body having the connection function may be used for providing only connection with the photovoltaic module and not for providing buoyancy. In manufacturing and installation processes, it is unnecessary for the support body to be watertight, thus the manufacturing process of the support body may be greatly simplified, and the manufacturing cost can be reduced. |
| US10784812B2 |
Power grid photo-voltaic integration using distributed energy storage and management
Distributed energy storage within the distribution network of an electric power network at least partially supplied by time varying and unpredictable generation sources provides smoothing of energy flow within the distribution network. The distributed energy storage may include a plurality of distributed energy storage units operating under the control of a single controller or regional controllers. The distributed energy storage units may operate as groups of units or as separate units. |
| US10784810B1 |
Motor controller with accurate current measurement
A motor control system for reducing or eliminating current ripple error during current sampling comprises a motor having a plurality of phase coils, a motor driver circuit having a plurality of switches coupled to the plurality of phase coils to drive current through the phase coils, and a motor controller circuit configured to provide a plurality of output control signals coupled to the plurality of switches. A phase circuit modifies a first output control signal to produce a modified control signal that is out of phase with a second output control signal. A current measuring circuit is included to measure a current through the motor by measuring the current during a first time period when the first output control signal is active and measuring the current during a second time period when the modified control signal is active. |
| US10784809B2 |
Linear motor system and compressor
Controllability of a linear motor or a compressor is improved. There is provided a linear motor system that includes: an armature having magnetic poles and winding wires; a mover having a permanent magnet; and a power conversion unit that outputs AC power to the winding wires, in which the mover and the armature are relatively movable, and the mover or the armature is connected to an elastic body. The linear motor system further includes: a position detection unit that detects and outputs the position of the mover with respect to the armature, a position estimation, or a current detection unit that outputs the value of current flowing through the winding wires; and a control unit that controls the output of the power conversion unit on the basis of the output of the position detection unit, the output of the position estimation unit, or the output of the current detection unit. In the case where a signal having a frequency substantially the same as the frequency of the AC power is applied to the output of the position detection unit, to the output of the position estimation unit, or to the output of the current detection unit, the control unit changes the frequency of the AC power, and in the case where a signal having a frequency substantially larger than the frequency of the AC power is applied, the control unit keeps the frequency of the AC power substantially the same. |
| US10784807B2 |
Methods and systems for controlling an electrical machine
A method and a parameter estimation system are provided for controlling an electrical machine, (e.g., an induction motor), powered by a drive unit. The method and the parameter estimation system disclosed herein detect a travelling wave generated on a linking element disposed between a first connection point, which is at least one terminal of the electrical machine, and a second connection point, which is at least one terminal of the drive unit. Further, the method and the parameter estimation system disclosed herein obtain at least one of a plurality of wave characteristics associated with the travelling wave, (e.g., an amplitude, a width, a frequency, a travel time of the travelling wave). Further, the method and the parameter estimation system disclosed herein determine one or more control parameters, (e.g., an operational torque and speed), of the electrical machine based on at least one of the wave characteristics. |
| US10784804B2 |
Magnetization state control method and magnetization state control device
A magnetization state control method for a variable magnetization machine, the method includes generating a flux linkage vector while changing a magnetization state of the variable magnetization machine such that a trajectory of the flux linkage vector has a curved clockwise trajectory on a dq-axis plane and a magnitude of the flux linkage vector temporally changes, with the dq-axis plane being a synchronous reference frame with a d-axis pointing in a direction of a permanent magnet flux and a q-axis being 90 degrees ahead of the d-axis in a rotational direction of a rotor. |
| US10784803B2 |
Position control device
A position control device includes a subtracter for subtracting a q-axis current detection value iq from a q-axis current command value iq* to output a q-axis current error Δiq, an adder for adding a q-axis current compensation amount iqc* for compensating for response timing of q-axis current to the q-axis current error Δiq, a q-axis current controller for amplifying an output of the adder by I-P control to calculate a q-axis voltage error Δvq and calculating a q-axis voltage command value vq* on the basis of the q-axis voltage error Δvq, and a second adder for adding a q-axis voltage feedforward amount vqf corresponding to a time derivative value s·iq of the q-axis current to the q-axis voltage command value vq* to calculate a final q-axis voltage command value. |
| US10784802B2 |
Generator starter of a turbomachine with asynchronous multi-winding electric machine
A generator starter of a turbomachine, including an asynchronous electric machine configured so as to operate in motor mode during a starting phase of the turbomachine while being supplied by an electrical source, and so as to operate in generator mode after the starting phase of the turbomachine in order to supply an electrical load. An inverter is arranged between the electrical source and the asynchronous machine with at least two alternating current terminals coupled to the asynchronous machine, and a control unit for the inverter configured to supply the asynchronous machine with a starting current in motor mode and a magnetisation current in generator mode. The asynchronous machine includes at least one first stator winding connected to the alternating current terminals to be supplied with the starting current in motor mode and with the magnetisation current in generator mode, and at least one second stator winding connected to the electrical load in generator mode. |
| US10784795B1 |
Conversion circuit
A conversion circuit includes a main device, a voltage control circuit and a trigger circuit. An output terminal of the voltage control circuit is electrically connected to a control terminal of the main device. The voltage control circuit is configured to output a driving signal having a first voltage level to the main device. The trigger circuit comprises an output terminal and a sense terminal. The output terminal of the trigger circuit is electrically connected to the control terminal of the voltage control circuit, and the sense terminal of the trigger circuit is electrically connected to the control terminal of the main device. |
| US10784794B2 |
GaN FET gate driver for self-oscillating converters
A power converter in which two power FETs are provided in a full bridge arrangement with two diodes for supplying a rectified voltage to a load. The gates of the power FETs receive alternating and opposite voltage waveforms such that the power FETs conduct oppositely to each other. A turn-off FET is connected to the gate of each power FET to prevent spurious turn on of the power FET during periods in which the opposite power FET is turned on. A voltage sense FET is also connected to the gate of each power FET to limit the gate voltage of the power FET. The voltage sense FETs are each synchronously modulated with the corresponding power FET to limit the gate to source voltage of the voltage sense FET when the corresponding turn-off FET is on and the corresponding power FET is off. |
| US10784790B1 |
Resonant conversion apparatus with extended hold-up time and method of operating the same
A resonant conversion apparatus with extended hold-up time includes a resonant conversion unit, a time-extended unit, and a control unit. The resonant conversion unit includes a primary side, a transformer unit, and a secondary side. The time-extended unit includes a coil and a bridge arm assembly. When a switching frequency of the primary side is less than a critical frequency, the control unit controls the bridge arm assembly being switched on or switched off so that an output voltage of the resonant conversion apparatus is higher than a predetermined voltage within a hold-up time. |
| US10784789B1 |
Switched mode power supply with multi-mode operation and method therefor
In one form, a method for generating a drive signal for a switch in a switched mode power supply includes receiving a feedback signal, generating a feedback voltage in response to the feedback signal, modulating a pulse width of the drive signal in response to the feedback voltage and a mode signal, generating a modulate signal in response to a magnitude of the feedback voltage crossing a first level in a first direction, generating the mode signal in response to the magnitude of the feedback voltage crossing a second level different from the first level in a second direction, and varying a gain between the feedback signal and the feedback voltage in response to the mode signal. |
| US10784788B2 |
Reactor and DC-DC converter using same
An object of the present invention is to provide a small-sized and highly heat-dissipative reactor and a DC-DC converter using the reactor. A reactor according to the present invention includes a plate bus bar, a core, and a heat sink. The core includes a middle leg portion. The heat sink cools the plate bus bar. The plate bus bar is formed such that a winding axis of a winding including the plate bus bar passes through the middle leg portion. A main surface of the plate bus bar is disposed in parallel with a direction of the winding axis and thermally connected to the heat sink via an insulating layer. |
| US10784787B2 |
Control circuit for half-bridge diodes
A circuit includes a first field-effect transistor and a second field-effect transistor. The first field-effect transistor includes a first diode with drain, source, gate and first additional electrodes. The second field-effect transistor includes a second diode with drain, source, gate and second additional electrodes. A first switch selectively connects the gate and drain electrodes of the first field-effect transistor. A second switch selectively connects the gate and drain electrodes of the second field-effect transistor. A control circuit controls the first and second switches. The first additional electrode is coupled to the gate electrode of the second field-effect transistor, and the second additional electrode is coupled to the gate electrode of the first field-effect transistor. |
| US10784786B2 |
PSFB converter and methods for controlling a PSFB converter
A method for controlling a PSFB converter, an apparatus, and a storage medium are disclosed, and relate to the field of power supply technologies. The method includes: controlling, by a control circuit after controlling a first clock and a second clock to operate in a first state for a time period, the first clock and the second clock to switch to a second state, where when the first clock and the second clock operate in the first state, the first bridge arm is a leading bridge arm, and the second bridge arm is a lagging bridge arm, and when the first clock and the second clock operate in the second state, the first bridge arm is a lagging bridge arm, and the second bridge arm is a leading bridge arm. |
| US10784785B2 |
Monitoring SMPS power switch voltage via switch drain source capacitance
A switch-mode power supply includes a power transistor, a transformer, and detection circuitry. The transformer includes a primary winding that is coupled to a drain terminal of the power transistor. The detection circuitry is coupled to a source terminal of the power transistor. The detection circuitry is operable to monitor signal present on the drain terminal via parasitic drain-source capacitance of the power transistor while the power transistor is switched off, and to detect demagnetization of a secondary winding of the transformer via the monitored signal. |
| US10784784B2 |
DC-DC converter with dynamic feedback loop
A power supply includes a controller integrated circuit that controls a switching operation of a primary switch based on a feedback voltage indicative of an output voltage of the power supply. The controller integrated circuit starts the switching of the primary switch when the feedback voltage reaches a first threshold voltage and stops the switching of the primary switch when the feedback voltage reaches a second threshold voltage. The controller integrated circuit adjusts the feedback voltage relative to the first threshold voltage to reduce the delay time to start switching the primary switch to increase the output voltage in response to changing load conditions. |
| US10784781B2 |
Transistor having asymmetric threshold voltage, buck converter and method of forming semiconductor device
A transistor includes a gate structure over a substrate, wherein the substrate includes a channel region under the gate structure. The transistor further includes a source in the substrate adjacent a first side of the gate structure. The transistor further includes a drain in the substrate adjacent a second side of the gate structure, wherein the second side of the gate structure is opposite the first side of the gate structure. The transistor further includes a first lightly doped drain (LDD) region adjacent the source. The transistor further includes a second LDD region adjacent the drain. The transistor further includes a doping extension region adjacent the first LDD region. |
| US10784777B2 |
Output current boosting of capacitor-drop power supplies
A capacitor-drop power supply includes a rectifier and a switched capacitor converter coupled to the rectifier. The rectifier is configured to receive an alternating current (AC) signal at an AC voltage and convert the AC signal into a rectified direct current (DC) signal at a rectified voltage. The switched capacitor converter is configured to receive the rectified DC signal and generate a converter output signal at a converter voltage that is proportional to the rectified voltage and that is less than the AC voltage. |
| US10784772B2 |
Switching power supply
A switching power supply that has a reduced conduction loss, when a direct current power supply is connected as an input power supply, by changing a part of a circuit for alternating current-to-direct current conversion, is provided. The switching power supply includes power input terminals to which the direct current power supply or an alternating current power supply is connected; power output terminals configured to output electric power; a smoothing capacitor connected between the power output terminals; a first non-insulated chopper circuit connected between the power output terminals; a second non-insulated chopper circuit connected between the power output terminals; and a switching circuit configured to switch a connection circuit provided between the first non-insulated chopper circuit and the second non-insulated chopper circuit, and the power input terminals. |
| US10784771B2 |
Multiphase power supply and distributed phase control
A power converter circuit includes multiple phases and controller circuitry. The multiple phases collectively operate to produce an output voltage to power a load. The controller circuitry monitors an output voltage and produces control information to control the multiple phases. Controller circuitry in each respective phase of the multiple phases processes the control information independently with respect to other phases to determine whether to output a quantum of energy to maintain regulation of the output voltage. In one arrangement, the control information provides general information indicating, such as for each control cycle, how much current is needed to supply to a load to maintain the output voltage. In a specific arrangement, identities of the phases are randomized over each of multiple cycles so that randomly chosen, but an appropriate number of phases is activated to supply current to the load. |
| US10784770B2 |
Conversion circuit
A conversion circuit includes a main device, a voltage control switching circuit and a trigger circuit. The trigger circuit includes an output terminal and a sense terminal. The sense terminal is electrically connected to the control terminal of the main device. The voltage control switching circuit includes a first terminal, a second terminal and a control terminal. A first terminal is configured to receive an original signal. A second terminal is connected to a control terminal of the main device, and is configured to transmit a driving signal to drive the main device. A control terminal is connected to the main device and the output terminal. The driving signal has a first voltage level generated by the voltage control switching circuit in response to a voltage level at the control terminal of the voltage control switching circuit. |
| US10784768B2 |
Conversion circuit and conversion circuitry
A conversion circuit includes a main device including a first terminal, a second terminal and a control terminal, and a voltage control switching circuit including a first terminal configured to receive an first driving signal, a second terminal coupled to the control terminal of the main device and configured to transmit a second driving signal to drive the main device, and a reference terminal coupled to the second terminal of the main device. A current passing through the voltage control switching device is controlled in response to a voltage level of the reference terminal. |
| US10784766B2 |
Adaptive slope compensation for current mode control
Adaptive slope compensation for current mode control in a switch mode power supply converter is computed for every switching cycle based upon the input voltage and duty-cycle whereby the quality factor is maintained at a constant value. A digital signal processing (DSP) capable microcontroller comprises a voltage loop compensator and generates a desired current reference for every switching cycle. Slope calculations are adapted for switching frequency, inductance value, current circuit gain, etc. The slope calculation result is applied to a pulse-digital-modulation (PDM) digital-to-analog converter (DAC) capable of changing its output levels at a very fast rate compared to the power supply switching frequency whereby the required current slope is provided within the switching period. Actual inductor current may be used to compare against the slope reference, thereby taking care of changes in the inductance values under load. The slope levels are automatically changed when the switching frequency is changed. |
| US10784762B1 |
Torque transfer using electro-permanent magnets
An example apparatus includes a first disk that is rotatable and has a plurality of electro-permanent magnets disposed in a radial array on a surface of the first disk; and a second disk rotatably mounted adjacent to the first disk such that a gap separates the second disk from the first disk, where the second disk has a plurality of ferromagnetic elements disposed in respective radial array on a respective surface of the second disk. Applying an electric pulse to at least one electro-permanent magnet of the plurality of electro-permanent magnets changes a magnetic state of the electro-permanent magnet, thereby (i) generating an external magnetic field that traverses the gap between the first disk and the second disk and interacts with a corresponding ferromagnetic element of the plurality of ferromagnetic elements, and (ii) causing the second disk to rotate as the first disk rotates. |
| US10784761B2 |
Coil actuator
An actuator is introduced that utilizes the forces that result from placing a current carrying coil in a magnetic field to rotate a connected object about at least one axis. In some embodiments, the introduced coil actuator includes a coil of conductor coupled to an arm or other type of structural element that extends radially from an axis of rotation. The introduced coil actuator can be utilized to provide motion control in a variety of different applications such as gimbal mechanisms. In some embodiments, the introduced coil actuator can be implemented in a gimbal mechanism for adjusting an orientation of a device such as a camera relative to a connected platform such as the body of an aerial vehicle. |
| US10784758B2 |
Linear vibration motor
Disclosed is a linear vibration motor, comprising a vibrator and a stator, the vibrator comprises a counterweight block and a vibration block, the vibration block includes at least two magnets adjacently arranged and a magnetic conductive yoke disposed between any two adjacent magnets, and polarities of adjacent ends of two adjacent magnets are the same. The magnets are any combination of a permanent magnet and/or an electromagnet. The stator includes a stator coil disposed at one side, or upper and lower sides of the vibrator, and a magnetic conductive core disposed in the stator coil, and the axis direction of the stator coil is perpendicular to the magnetization direction of the magnets. The linear vibration motor adopts free combinations of permanent magnets and electromagnets to constitute the vibration block, and thus expands the implementation manners of the linear vibration motor so as to improve the flexibility in the production process. |
| US10784755B2 |
Stator bar mold insert
A stator bar mold insert includes an upper portion and a lower portion. A central cavity is disposed between, and defined by, the upper portion and the lower portion. The central cavity is configured for use with a stator bar. A low friction material lines the central cavity, and the low friction material substantially surrounds the stator bar located inside the stator bar mold insert. |
| US10784751B2 |
Stator, motor, blower, vacuum cleaner, and method for attaching hall effect sensor
A stator includes a first split core having a first yoke part extending in a circumferential direction about an axis line and a first tooth extending from the first yoke part toward the axis line, a second split core having a second yoke part extending in the circumferential direction and a second tooth extending from the second yoke part toward the axis line, a first insulator arranged to surround the first tooth and having a first holding part located between a tip end part of the first tooth and a tip end part of the second tooth, a second insulator arranged to surround the second tooth and having a second holding part located between the tip end part of the first tooth and the tip end part of the second tooth, and a Hall effect sensor held by the first holding part and the second holding part. |
| US10784747B2 |
Electric motor with improved cooling having v-shaped fins on a rotor facing radially extending fins on a stator
The invention relates to an electric motor, particularly an “external rotor motor”, comprised of a stator housing and a rotor housing which is rotatable with respect to the stator housing, wherein the rotor housing has a cooling ring disposed on its side which axially faces the stator housing, wherein the stator housing and the cooling ring are each provided with a plurality of first and second cooling fins (the second cooling fins also being referred to as “cooling ribs”) which face each other axially and are disposed so as to be distributed in the respective circumferential directions, which fins/ribs collaborate in flow technology when the rotor housing is in rotating operation; wherein, in an axial plan view, the first cooling fins extend radially outwardly, and the second cooling fins (the cooling ribs) are V-shaped and point in the circumferential direction, wherein a rotary relative movement of the first and second cooling fins (the cooling fins and the cooling ribs) generates a cooling air stream, at least between the stator housing and the rotor housing. |
| US10784745B2 |
Stators for electrical machines
A stator for an electrical machine (e.g., a motor or generator) is described. The stator includes a stator core consisting of a plurality of axially adjacent generally annular laminations. The stator has axially extending stator teeth between adjacent pairs of which are formed axially extending stator slots for receiving conductors of a stator winding. At least one of the stator teeth includes an axially extending cooling passageway through which a cooling fluid flows in use. The electrical machine can include means for circulating cooling fluid through the cooling passageway(s) to cool the stacked laminations and means for circulating air around the stator along an air cooling circuit where the circulated air is cooled by the stator laminations and there is no need for a separate heat exchanger. |
| US10784742B2 |
Mechanical brake for an electric motor
The present disclosure relates to mechanical braking mechanisms used in electric motor applications. The present braking mechanisms may be configured as non-back-drivable mechanical brakes and provide immediate braking of the motors. According to one embodiment, a mechanical brake assembly for an electric motor may include a female disk having a curved groove and an abutment. The mechanical brake assembly further includes a male disk having a projection, the male disk being attached to a rotor of the electric motor. When the electric motor is energized, the projection of the male disk is allowed to rotate uninterrupted with the rotation of the rotor. However, when the electric motor is de-energized, the projection of the male disk travels within the curved groove of the female disk and abuts the abutment of the female disk, thereby stopping the rotation of the rotor of the electric motor. |
| US10784740B2 |
Drive with a commutator motor
A drive including a commutator motor having a motor housing, an end shield secured to the housing, feedthroughs defined in the end shield, brushes mounted in the feedthroughs; and at least one stranded conductor forming a direct electrical and mechanical connection between a brush and the terminal contact arranged outside the motor housing. |
| US10784739B2 |
Radial clearance in a hybrid module
A hybrid module includes a housing, a bearing, and an electric motor. The electric motor has a rotor with a rotor carrier radially positioned by the bearing in the housing. The rotor carrier has an annular ring comprising an annular ring outer surface with a first outer diameter. The rotor has a plurality of rotor segments installed on the rotor carrier. The plurality of rotor segments include an outer circumferential surface with a second outer diameter, less than the first outer diameter. In some example embodiments, the electric motor has a stator with a bobbin core and a bobbin shield installed on the bobbin core. In some example embodiments, the bobbin core is at least partially radially aligned with the plurality of rotor segments, and the bobbin shield is at least partially radially aligned with the annular ring. |
| US10784737B2 |
Rotating electrical machine and method for manufacturing same
A rotating electrical machine with a fractional slot structure includes concentrically wound stator coils, and a method of manufacturing the same. In a rotating electrical machine, a plurality of unit coils included in the stator coil are allocated into a first pole coil and a second pole coil in units of slots that oppose a pair of movable element magnetic poles. Further, each pole pair coil forming a plurality of phase coils is provided with two types of the unit coils, namely a full-coil and a half-coil. In addition, in each pole pair coil, the coil pitches between pairs of coil sides of the plurality of unit coils forming said pole pair coil are different from one another, and each pole pair coil is provided with one half-coil. |
| US10784728B2 |
Rotor for an electrical machine with push-on windings
A rotor for an electrical machine has a rotor core with a center line, which forms an axis of rotation. The rotor core can be subdivided by a plurality of imaginary radial planes, which extend radially from the axis of rotation at regular angular intervals. For each radial plane, at least one pair of winding grooves is formed, which extend through the rotor core to either side of the radial plane with the radial plane serving as the plane of symmetry. A winding is arranged in each pair of winding grooves, in winding receiving areas of the winding grooves, which winding extends through the two winding grooves of the pair. Each winding groove is bounded in its winding receiving area on its side facing the assigned radial plane by a side face, which continues in a manner free from projections, in the sense of projections in a direction away from the radial plane, from the winding receiving area to the radially outer end of the winding groove. |
| US10784725B2 |
Vehicle misalignment measurement and compensation in dynamic wireless charging applications
For misalignment measurement, a method receives a plurality of position detection signals from a corresponding plurality of detection coils. The plurality of position detection signals are generated from mutual inductance between the plurality of detection coils and an energized field-generating detection coil. The method further generates detection information from the position detection signals. In addition the method calculates a lateral misalignment along a lateral Y axis from the detection information. The lateral misalignment includes a lateral misalignment distance and a lateral misalignment direction. The method calculates a vehicle speed along a longitudinal X axis from the detection information. In addition, the method energizes a transmitter power coil and controls the power transfer based on the vehicle speed and lateral misalignment. |
| US10784723B2 |
Nonlinear resonance circuit for wireless power transmission and wireless power harvesting
A nonlinear resonator is presented that enhances the bandwidth while providing high resonance amplitude. The nonlinear resonance circuit is comprised of an inductor electrically coupled to a capacitor, where either the inductor or capacitor is nonlinear. Response of the nonlinear resonance circuit to an excitation signal is described by a family of second-order differential equations with cubic-order nonlinearity, known as Duffing equations. In one aspect, the nonlinear resonator is implemented by a nonlinear dielectric resonator. |
| US10784720B2 |
Transmission coil module for wireless power transmitter
A wireless power transmission coil module includes a first coil and a second coil; a third coil on the first coil and the second coil; and a coil frame receiving the first coil, the second coil and the third coil. In addition, a first surface of the coil frame comprises a first receptacle for receiving the first coil and a second receptacle for receiving the second coil, a second surface of the coil frame opposite to the first surface of the coil frame comprises a third receptacle for receiving the third coil, and the first receptacle does not overlap the second receptacle in a first direction perpendicular to the first surface of the coil frame. |
| US10784718B2 |
Monitoring system, monitoring apparatus, server, and monitoring method
Provided is a monitoring apparatus that obtains, on an as-needed basis, audio data containing a notification sound emitted by an electrical appliance. A monitoring system (1) for monitoring the state of an electrical apparatus (400) which is to be monitored includes a monitoring apparatus (100) configured to (i) measure electric current consumed by the electrical appliance and obtain a notification sound that the electrical appliance emits during a predetermined sound recording period from when a predetermined change in the electric current is detected. The monitoring system (1) is configured to carry out a determination of the state of the electrical appliance from the notification sound and send report information, which is indicative of a result of the determination, to a communication terminal (300). |
| US10784717B2 |
Method, device, and system for controlling power supply
A method for controlling a power supply includes: acquiring working state information of the power supply in a current operation; determining whether a state value of the power supply in the current operation satisfies a preset condition according to the working state information; setting a first control strategy for controlling the current operation of the power supply as a second control strategy when the preset condition is satisfied; storing the state value in the current operation and the first control strategy of the power supply in the current operation when the preset condition is not satisfied, and modifying the first control strategy to obtain the second control strategy according to an adjustment strategy; and loading the second control strategy from the machine-learning control circuitry in next operation, and controlling the next operation of the power supply according to the second control strategy. |
| US10784712B2 |
Power supply recovery current history-based limitation
A power supply unit (PSU) dynamically limits total recovery current. The PSU includes at least a power input, a power output, a historic maximum power draw memory, an update logic, and a recovery current limiting logic. Some implementations include a latest power measurement register, an hourly max power register, and a rolling max register, and controlling firmware. The update logic monitors a power level. The update logic updates the historic maximum power draw memory to match the monitored level. After a power interruption, the recovery current permitted to flow into the PSU is limited based on the historic usage. The recovery current may be limited in a constant, stepped, or ramped manner. The PSU may also provide power distribution. Multiple PSUs may be treated as a group, allowing an individual PSU to exceed its historic usage while the group's recovery currents are limited to the sum of historic usage levels. |
| US10784709B2 |
Charging system for a barcode reader that uses different types of rechargeable power sources
A system includes a barcode reader that is configured to use different types of rechargeable power sources and charging circuitry that is configured to provide a charging current and a charging voltage for a rechargeable power source that is being used by the barcode reader. The charging circuitry is configured to adjust the charging current and the charging voltage for the different types of rechargeable power sources that are used by the barcode reader. |
| US10784706B2 |
Wireless power transmitter and method for controlling the same
A wireless power transmitter configured to wirelessly transmit power to an electronic device is provided. The wireless power transmitter includes a power transmission antenna including a plurality of patch antennas for wirelessly transmitting power, a sensor, and a processor, wherein the processor may be configured to create a first clutter map representing a reflection characteristic of an object positioned around the wireless power transmitter based on, at least, first data obtained by the sensor during a first period, store the first clutter map, compare a difference between the first clutter map and second data obtained by the sensor during a second period with data contained in the first clutter map, create a second clutter map corresponding to the second period based on a result of the comparison, determine a position of an organism using the second data and the second clutter map, and control the power transmission antenna such that a magnitude of the RF wave is less than a predetermined value based on the position of the organism. |
| US10784703B2 |
System and method for maintaining battery life
A system and method is disclosed for monitoring current consumption of various subsystems and applications and adjusting functional parameters to ensure a constant current drain from the battery. The constant current drain can be dynamically adjusted based on a predetermined amount of battery life. A user can determine the amount of battery life to be required and the system adjusts current consumption of various subsystem components and applications to provide consistent and predictable battery life. |
| US10784702B2 |
Battery control device, battery control system, battery control method,and recording medium
A battery control device controlling an operation of a battery connected to a power system includes detection means that detects battery-related information showing a state of the battery, or a state of an interconnection point of the power system and the battery, first communication means that transmits a detection result of the detection means to an external device, and executes reception processing to receive operation control information to control the operation of the battery from the external device at a predetermined time interval, and control means that executes battery operation control processing to control the operation of the battery based on a state of the power system and based on the operation control information received by the first communication means, at a time interval shorter than the predetermined time interval. |
| US10784701B2 |
Power system architecture for aircraft with electrical actuation
An electrical power system for regenerative loads may include a DC bus and an electrical actuator load, where back-driving the electrical actuator load generates regenerative electrical energy, and where the electrical actuator load is configured to transmit the regenerative electrical energy to the DC bus. The system may also include at least one additional load, where at least a portion of the regenerative electrical energy is transmitted to the at least one additional load. |
| US10784700B2 |
Arrangement for and method of dynamically managing electrical power between an electrical power source and an electrical load
Electrical power is dynamically managed a power source a load. A control switching system has a plurality of monitor nodes, a control switch having two switching states, and an electrical power storage cell connected to the power source in one of the switching states for storing voltage, and operative for discharging the stored voltage to the electrical load in the other of the switching states. A programmed controller dynamically monitors operating conditions at the monitor nodes during operation of the electrical load and the power source, and switches the control switch between the switching states in response to the monitored operating conditions for supplying a voltage of a desired waveform shape to the load. |
| US10784699B2 |
Systems and methods of powering circuits with near end-of-life batteries
The present application discloses systems and methods of powering a solenoid circuit and other circuits with batteries that are at (or near) the end of their functional life. |
| US10784694B1 |
Standing handbag rack with charging station
A standing handbag rack with charging station, having a vertical extending support structure having an upper portion and a lower portion, a base secured to the lower portion of the vertical extending support structure, one or more hooks for receiving a handbag or the like, the hooks are secured to the standing handbag rack, a tray secured to the vertical extending support structure, the tray including one or more cable openings, the tray adapted for receiving a portable electronic device, one or more power connectors provided at the tray, the power connector adaptable for coupling to a portable electronic device, a battery housing secured to the standing handbag rack, at least one cable, the cable having a first end and a second end, the first end connected to a power connector adaptable for extending through the cable opening for coupling to a portable electronic device, and the second end extending to the battery housing for coupling to a removable and rechargeable battery, for charging the portable electronic device. |
| US10784692B2 |
Method and device for checking charging parameter, and charger
The present disclosure relates to a method for checking a charging parameter. The method includes: after a communication channel between a terminal and a charger is successfully established, reading, by the terminal, charging capability information of the charger in a preset manner; comparing a maximum capability value of the charger for each preset charging parameter with a target value that is corresponding to a corresponding preset charging parameter and that is stored in the terminal, and determining a minimum value as a first configuration value for the corresponding preset charging parameter; writing, into the charger, the first configuration value that is obtained by means of comparison and that is for each preset charging parameter; reading a second configuration value of the charger for each preset charging parameter; and sending, by the terminal, a charging acknowledgment instruction to the charger after determining that all preset charging parameters are successfully configured. |
| US10784690B2 |
Method for controlling an electrical distribution network
A method for controlling an electrical distribution network, wherein a network control station is provided to control the electrical distribution network and the electrical distribution network comprises a plurality of balancing areas, wherein each balancing area outputs or receives an exchange power to or from the electrical distribution network, and wherein at least one of the balancing areas has at least one generator, in particular a wind farm, for generating a generator power and additionally at least one consumer for receiving a consumer power, wherein at least one balancing area controller is provided to control the at least one generator or wind farm, and the method comprises the following steps: reception by the balancing area controller from the network control station of a value of an exchange power to be set, wherein the exchange power is defined as a difference between the consumer power and the generator power, drawing up by the balancing area controller of a deployment plan for adherence to or attainment of the exchange power to be set, wherein the deployment plan is provided to control the generators and consumers and is drawn up in such a way that a difference between the attained exchange power and the exchange power to be set is minimal, and generation of electrical power by means of the at least one generator or wind farm depending on the deployment plan. |
| US10784685B2 |
Electrical power systems and subsystems
An electrical power subsystem includes a generator comprising a generator stator and a generator rotor, and a power converter electrically coupled to the generator. The power converter includes a plurality of rotor-side converters electrically coupled in parallel, a line-side converter, and a regulated DC link electrically coupling the plurality of rotor-side converters and the line-side converter. The electrical power subsystem further includes a stator power path for providing power from the generator stator to the power grid, and a converter power path for providing power from the generator rotor through the power converter to the power grid. |
| US10784683B2 |
Method of controlling electrical power system and apparatus using the same
The present application provides a method of controlling an electrical power system and an apparatus using the same. The electrical power system includes a DC bus and a DC bus capacitor connected to the DC bus. The method includes: receiving a virtual DC bus capacitance value of the DC bus capacitor; detecting a DC bus voltage; calculating an expected value of a DC bus current based on the virtual DC bus capacitance value and the DC bus voltage; and adjusting the DC bus current, so that the DC bus current reaches the expected value and thus the DC bus capacitor is equivalent to the virtual DC bus capacitance value. |
| US10784682B2 |
Network-cognizant voltage droop control
The present disclosure provides techniques for network-cognizant droop control in power systems, such as a power distribution system. An example device includes a processor configured to determine, based on (i) a model representing a structure of a power system that includes a plurality of energy resources and (ii) an indication of predicted uncontrollable power injections in the power system, for each controllable energy resource in the plurality of energy resources, a respective value of a first droop coefficient and a respective value of a second droop coefficient. The processor may be further configured to cause at least one controllable energy resource in the plurality of energy resources to modify an output power of the at least one energy resource based on the respective value of the first droop coefficient and the respective value of the second droop coefficient. |
| US10784679B2 |
Electrostatic discharge protection apparatus and integrated circuit with multiple power domains
This application discloses an electrostatic discharge protection apparatus and an integrated circuit with multiple power domains. The electrostatic discharge protection apparatus includes a diode and an NMOS transistor. A positive electrode of the diode is coupled to a first interface, a negative electrode of the diode is coupled to a first electrode of the NMOS transistor, both a second electrode of the NMOS transistor and a gate electrode of the NMOS transistor are coupled to a second interface, and a substrate of the NMOS transistor is used for grounding. At least one electrostatic discharge protection apparatus may be disposed in the integrated circuit with multiple power domains. |
| US10784677B2 |
Enhanced utility disturbance monitor
A method for detecting a voltage disturbance on an electrical line coupled to a utility that includes calculating a sliding window actual root mean squared (RMS) voltage for each three-phase power signal, calculating a sliding window filtered RMS average voltage for each actual RMS voltage to identify normal changes in the voltage of the power signals from a nominal voltage, and obtaining a difference between the actual RMS voltage and the RMS average voltage for each of the power signals. The method determines whether the difference between the actual RMS voltage and the RMS average voltage for any of the three-phase signals is greater than a first predetermined percentage, or whether the difference between the actual RMS voltage and the RMS average voltage for any of the three-phase signals is less than a second predetermined percentage, and if so, disconnects a load from the utility. |
| US10784675B2 |
Vehicle accessory power switch
An electrical switch for providing power from a power source to a component may include a voltage supervisor having an input and an output, a voltage divider, electrically coupled between the input of the voltage supervisor and ground, an RC filter electrically coupled to the output of the voltage supervisor, and a field-effect transistor having a first terminal coupled to the RC filter and a second terminal coupled to an output of the switch, the output configured to be electrically coupled to the component. A switch may additionally or alternatively include a light source electrically that emits light when power is provided from the input of the switch to the component, the light source arranged proximate a fuse so as to illuminate the fuse. |
| US10784672B2 |
Circuit interrupter with self-test circuit and method of operating a circuit interrupter
A circuit interrupter including a line conductor, a neutral conductor, separable contacts, an operating mechanism structured to trip open the separable contacts, a magnetic trip actuator structured to cause the operating mechanism to trip open the separable contacts in response to a short-circuit between the line and neutral conductors, a protection circuit including a self-test circuit structured to perform a self-test and to output a signal in response to failing the self-test, and an electrical component electrically connected between the line and neutral conductors and having an open state and a closed state. The electrical component is structured to switch from the open state to the closed state and cause a short-circuit between the line and neutral conductors in response to receiving the signal from the self-test circuit. |
| US10784666B2 |
Bracket for electrical devices
A bracket for supporting at least one electrical device includes a first portion including a flange oriented in a first plane and at least one second portion including a leg oriented in a second plane substantially parallel to and offset from the first plane. Each second portion is configured to be coupled to the at least one electrical device. |
| US10784664B2 |
Three-piece electronics enclosure
A three-piece electronics enclosure may be provided. The electronics enclosure may comprise a back housing, a lid, and a center frame. The back housing may comprise back housing heat sinks on an exterior of the back housing and back housing circuitry disposed in an interior of the back housing. The lid may comprise lid heat sinks on an exterior of the lid and lid circuitry disposed in an interior of the lid. The center frame may be disposed between the back housing and the lid. The center frame may comprise a plurality of input/output (I/O) ports comprising a first I/O port and a second I/O port. At least one of the plurality of I/O ports may provide power to the back housing circuitry and the lid circuitry. The center frame may further comprise a power bypass that passes power between the first I/O port and the second I/O port. |
| US10784662B2 |
Weak link latch
A weak-link latch for releasably pulling a cable (13) arranged in a conduit (14). The weak link latch is releasably connected to the conduit, and securely connected to the cable. A plurality of arms (4,5) extend laterally from a central member (1) arranged to engage the conduit, with at least one of which arms being a rotatable arm (5,19), rotatable about an axle (6) from an extended position in locked engagement with the conduit to a collapsed position disengaged from the conduit. A shear pin (7) is arranged between the rotatable arm (5,19) and the central member (1), the shear pin arranged to prevent rotation of the rotatable arm from the extended position to the collapsed position, said shear pin having a predetermined breaking force, said breaking force being a shear force due to rotational force from the rotatable arm. |
| US10784657B2 |
Electrical substation safety barrier device and method
A safety device is configured to be attached to components in an electrical substation to provide a physical and visual barrier between de-energized components and energized components in the electrical substation. The safety may include a safety barrier board formed from an electrically insulating material and configured to be attached to fastening devices that attach the safety barrier board to components in the substation. Each fastening device may be an inverted-J-hook configured to be attached to a surface of the safety barrier board or a coupling link attached to a variable length fastening component and an attachment hook. |
| US10784654B2 |
Spark plug
Spark plug has first and second electrodes. First electrode has tip principally made of noble metal and base material principally made of Ni. The tip is joined to the base material through fusion portion. Second electrode faces discharge surface of the tip. The fusion portion has overlap portion where first interface between the tip and the fusion portion and second interface between the base material and the fusion portion overlap in first direction perpendicular to the discharge surface. When viewing cross section which passes through a center of gravity of the overlap portion projected onto virtual surface parallel to the discharge surface and is perpendicular to the discharge surface, noble metal content is greater than 50 mass % at one end portion of the overlap portion in second direction extending along the discharge surface, and Ni content is greater than 50 mass % at the other end portion of the overlap portion. |
| US10784649B2 |
Optical semiconductor device
A semiconductor laser (2) includes an n-type semiconductor substrate (1), a stack of an n-type cladding layer (4), an active layer (5), and a p-type cladding layer (6) successively stacked on the n-type semiconductor substrate (1). An optical waveguide (3) includes a non-impurity-doped core layer (9) provided on a light output side of the semiconductor laser (2) on the n-type semiconductor substrate (1) and having a larger forbidden band width than the active layer (5), and a cladding layer (10) provided on the core layer (9) and having a lower carrier concentration than the p-type cladding layer (6). The semiconductor laser (2) includes a carrier injection region (X1), and a non-carrier-injection region (X2) provided between the carrier injection region (X1) and the optical waveguide (3). |
| US10784646B2 |
Laser system having a multi-stage amplifier and methods of use
A laser system having a multi-pass amplifier system which includes at least one seed source configured to output at least one seed signal having a seed signal wavelength, at least one pump source configured to output at least one pump signal, at least one multi-pass amplifier system in communication with the seed source and having at least one gain media, a first mirror, and at least a second mirror therein, the gain media device positioned between the first mirror and second mirror and configured to output at least one amplifier output signal having an output wavelength range, the first mirror and second mirror may be configured to reflect the amplifier output signal within the output wavelength range, and at least one optical system may be in communication with the amplifier system and configured to receive the amplifier output signal and output an output signal within the output wavelength range. |
| US10784645B2 |
Fiber laser having variably wound optical fiber
Some embodiments may include a fiber laser, comprising: a variably wound optical fiber, wherein the variably wound optical fiber includes: a first length arranged in a plurality of first loops with a first separation distance between successive ones of the first loops; and a second length arranged in a plurality of second loops with a second separation distance between successive ones of the second loops; wherein the first separation distance between successive ones of the first loops is greater than the second separation distance between successive ones of the second loops; and packaging to remove heat generated by the optical fiber of the fiber laser during operation of the fiber laser, wherein the variably wound optical fiber is fixably mounted to a surface of a heat conductor of the packaging. |
| US10784643B2 |
Reducing the pulse repetition frequency of a pulsed laser system
A method for generating a laser pulse train is provided, including at least the following method steps: generating a laser pulse train at a pulse repetition frequency; coupling the laser pulse train into an acousto-optical modulator, and selecting individual laser pulses of the laser pulse train. A system for generating a laser pulse train is also provided, including at least a pulsed laser and an acousto-optical modulator, and an associated control device. |
| US10784640B2 |
Connector with separable lacing fixture
A connector assembly (10) is disclosed in which a connector part (12) and a cable manager part (20) are provided. The cable manager part (20) can be provided with a separable lacing fixture (24) that functions to retain the severed portions (6a) of the wires (6) that result from the termination process, rather than allowing the severed wire portions (6a) to fall to the floor in an uncollected state. In one aspect, the cable manager part (20) has a main body (22) to which the separable lacing fixture (24) is attached via a plurality of breakaway portions (34). During installation, the connector part (12) is inserted onto the cable manager part (20) and is placed in a wire termination tool (7) which fully inserts the connector part (12) onto the cable manager part (20). This action causes the connector part (12) to cut the wires (6) and to sever or break the breakaway portions (34) such that the separable lacing fixture (24) is separated from the fully formed connector (10). |
| US10784639B2 |
Loop bridge
The present disclosure relates to a loop bridge for looping-through an electric signal, comprising: a first electric module comprising a first electrical connection terminal, wherein the electric signal loops through the first electric module to a second electric module comprising a second electrical connection terminal, wherein the first electrical connection terminal and the second electrical connection terminal each have a pressure piece: and a printed circuit board with a comb-like line structure. The comb-like line structure comprises: a first comb tine, wherein the first comb tine is configured to be inserted into the first electrical connection terminal, and wherein the first comb tine comprises a first metal support part configured to support the pressure piece of the first electrical connection terminal: and a second comb tine electrically connected to the first comb tine, wherein the second comb tine is configured to be inserted into the second electrical connection terminal. |
| US10784638B2 |
Adaptor plug assembly
An adaptor plug assembly includes an adaptor plug and a mobile device which has a receiving unit. The adaptor plug includes a housing having a first connection end from which two terminals extends, and a second connection end in which three receptacle holes are defined. The two terminals are connected to the second connection end. A coil is mounted to one of the two terminals and electrically connected to a micro controller which includes a calculating unit, a transforming unit and a wire-less transmitting unit. The transforming unit receives current inducted by the coil and transforms the current into a first signal which is sent to and calculated by the calculating unit to be a second signal which is transmitted by the wire-less transmitting unit to the receiving unit of the mobile device. A power unit is installed in the housing provides power to the micro controller. |
| US10784637B2 |
Comfortably operated travel plug adapter
The present invention relates to a travel plug adapter, which will also be referred to herein as a travel adapter, for short. Using such an adapter it is possible to insert power plugs of a certain (domestic) standard into the outlets present at the travel destination. The present invention relates in particular to a travel plug adapter (10), which has a housing, a plug receptacle (16), and at least a first plug (38, 84) of a first standard and a second plug (28, 86) of a second standard, wherein each plug is assigned an actuation slider (22, 24), which is guided outwardly through a slide slot (42) of the housing and is designed to displace the plug between a standby position, in which the plug is disposed substantially inside the housing, and a usage position, in which the plug is usably disposed outside the housing, and wherein the first plug (38, 84) is assigned a first blocking element (106A), such that displacement of the first plug (38, 84) between the standby position and the usage position is blocked when the movement of the first blocking element (106A) is blocked, and wherein the second plug (28, 86) is assigned a second blocking element (106B), such that the displacement of the second plug (28, 86) between the standby position and the usage position is blocked when the movement of the second blocking element (106B) is blocked, characterised in that at least one blocking slide (100A) is also provided, which in a first position releases the path of the first blocking element (106A) and in a second position blocks the path of the first blocking element (106A), wherein the second blocking element (106B) acts on the position of the blocking slide (100A). |
| US10784628B2 |
Electrical plug connector
An electrical plug connector. The electrical plug connector has: a connector housing for accommodating at least one electrical cable that extends along an axial direction; a shielding plate that completely encloses the connector housing in a circumferential direction around the axial direction. The connector housing has, on an external surface, a play-limiting element for limiting a degree of play in the state plugged together with the mating plug connector. The shielding plate has an opening, the play-limiting element protruding from the connector housing and extending through the opening of the shielding plate and/or the play-limiting element being fashioned as a connector housing opening in the connector housing and being adjacent to the opening. |
| US10784626B2 |
Electrical connector
An electrical connector includes a plug and a sliding lock element. The plug includes an inserting portion, a cover portion, and a first sidewall portion. The cover portion covers one end of the inserting portion. The first sidewall portion is perpendicularly connected to the cover portion. A gap is formed between the first sidewall portion and the inserting portion. The sliding lock element is assembled on the plug. The sliding lock element includes a lid portion, a vertical extension portion, and a fitting portion. The lid portion slidably covers the cover portion of the plug. The vertical extension portion is perpendicularly connected to the lid portion. The fitting portion is connected to the vertical extension portion and extends toward the lid portion. |
| US10784621B1 |
Connector housing latch
An electrical connector includes a connector housing having a first end and an opposed second end, a pair of release stops extending generally radially outward and adjacent to the first end, and a pair of deflection buttons extending longitudinally cantilevered from a pivot base having a lateral axis and having free ends extending toward the first end and located adjacent to and radially outward from respective ones of the release stops when in an unflexed state. The electrical connector also includes a latch arm extending longitudinally cantilevered from the pivot base toward the second end, with a free end of the latch arm including a latch lock configured to selectively engage a barb on a mating connector. |
| US10784620B2 |
Method of operating a connector latch for a housing
Method of operating a connector latch used to securely hold together a connector apparatus, wherein the connector apparatus has at least a first housing and a second housing which can be mated together. Initially, after the connector latch is manufactured, the connector latch is in an undeflected position. After manufacture, the connector latch is subjected to a pre-mating deflection process, in order to deflect the connector latch into a preloaded position. After the pre-mating deflection process has been completed, the connector latch is locked in the preloaded position. The preloaded connector latch provides a number of desirable characteristics, including at least an extra loud “click” sound when the connecting latch is operated to mate the first housing with the second housing. |
| US10784617B2 |
Plug connector with a contacting portion for diverting an electric arc
A plug connector part for electrically contacting a mating plug connector part includes: a contact element, which is engageable in a plug-in manner with a mating contact element of an associated mating plug connector part in an insertion direction for electrical contacting; and a lance element that includes an at least partially resilient shaft and a contacting portion, the shaft being connected to the contact element at a first end and the contacting portion being arranged at a second end of the shaft such that the contacting portion remains in electrical contact with the mating contact element of the mating plug connector part when the connector part is released from the mating plug connector part after the electrical contact between the contact element and the mating contact element has already been broken. |
| US10784607B2 |
Golden finger design methodology for high speed differential signal interconnections
A connector assembly is disclosed to reduce discontinuity impedance between golden finger connectors and components on a circuit board. The assembly includes a circuit board including a connector edge. A plurality of connectors is formed on the connector edge on a first surface of the circuit board. A ground plane is formed on part of the circuit board on a second opposite surface of the first surface. The ground plane leaves the second opposite surface under the connector edge exposed. A ground loop is formed on the second opposite surface under at least two of the plurality of connectors. |
| US10784606B2 |
Electrical connector and connector assembly
An electrical connector is mounted downward on a circuit board to mate with a mating member. The electrical connector includes an insulating body having a front end surface, where the front end surface is backward concavely provided with a mating slot for the mating member to be inserted therein, and at least one ground terminal. Each ground terminal has a main body provided on the insulating body. A first elastic arm and a second elastic arm extend forward from the main body. The first elastic arm has a first contact portion in downward contact with an upper shielding member. The second elastic arm has a second contact portion in downward contact with the mating member. The first contact portion is located in front of the second contact portion. An acting force by the first elastic arm counteracts a supporting force by the circuit board, preventing the insulating body from deformation. |
| US10784605B2 |
Connector with a contact retained in a housing
A connector comprises a housing and a plurality of contacts retained in the housing. Each of the contacts extends in a longitudinal direction and has a retained portion, a contacting portion disposed in front of the retained portion in the longitudinal direction, and a connecting portion disposed behind the retained portion in the longitudinal direction. Each of the contacting portion and the connecting portion are shifted with respect to the retained portion in a vertical direction perpendicular to the longitudinal direction. The housing is in contact with the retained portion of each of the contacts from both above and below in the vertical direction and from both right and left in a lateral direction perpendicular to the vertical direction and the longitudinal direction. |
| US10784603B2 |
Wire to board connectors suitable for use in bypass routing assemblies
A wire to board connector is provided for connecting cables of cable bypass assemblies to circuitry mounted on a circuit board. The connector has a structure that maintains the geometry of the cable through the connector. The connector includes a pair of edge coupled conductive signal terminals and a ground shield to which the signal terminals are broadside coupled. The connector includes a pair of ground terminals aligned with the signal terminals and both sets of terminals have J-shaped contact portions that flex linearly when the connector is inserted into a receptacle. In another embodiment, the signal terminal contact portions are supported by a compliant member that may deflect when the connectors engage contact pads on a substrate. |
| US10784600B1 |
Split, locknut grounding bushing
A split, locknut grounding bushing has a first metal bushing portion with first and second ends, a top, a bottom with teeth, an exterior surface with a boss for receipt of a lug, and an interior surface with threads; a second metal bushing portion similar to the first bushing portion, first and second insulators respectively connected to the top of the first and second metal bushing portions. The first and second metal bushing portions pivot with respect to each other at one end and can be fastened to each other at the second end. The threads of the first and second bushing portions can thread onto the threads of a conduit or connector passing through a hole in an electrical enclosure so as to engage the teeth on the bottom of the first and second bushing portions with an interior surface of the enclosure. |
| US10784590B2 |
Ultra-wide bandwidth frequency-independent circularly polarized array antenna
An array antenna has a plurality of antenna unit cells arranged in rows and columns, or in another configuration. Each unit cell from the plurality of unit cells includes a circularly polarized radiator and a balun. The array antenna further includes a reactive element or a circuit element (such as a capacitor or resistor or even an inductor) on the circularly polarized radiator that is coupled an adjacent unit cell in one of the row and the column. A spacing distance between adjacent unit cells coupled via the circuit element that is at most half of a wavelength at a frequency maximum of the array antenna, wherein the spacing distance reduces likelihood of grating lobes. |
| US10784589B2 |
Wireless communication device
A wireless communication device includes: a reflector plate that comprises a reflective surface, the reflective surface reflecting an electromagnetic wave; an array antenna that comprises a plurality of antenna elements, the antenna elements being arranged on the reflective surface; one or more fins that stand on the reflective surface; and a transmission and reception circuit that is connected to the reflector plate, and transmits and receives a wireless signal via the array antenna. |
| US10784586B2 |
Radio frequency antenna incorporating transmitter and receiver feeder with reduced occlusion
An antenna system (201) comprising a set of transmitting elements (320A-K) and a set of receiving elements (310A-N) formed on a same or different planar surface (210), an electromagnetic lens (220) to focus electromagnetic rays transmitted from the set of transmitting elements (320A-K), a convex secondary antenna (240) operative to reflect the electromagnetic rays and a concave parabolic primary antenna (230) operative to transmit the electromagnetic rays in a first direction such that, the lens, the convex secondary antenna and the concave parabolic primary antenna together provide a transmitting gain in the first direction. The set of transmitting elements are disposed at central area of the planar surface and the set of receiving elements are disposed on the periphery of the central area such that the set of receiving elements occupy larger area on the planar surface compared to the set of transmitting elements. |
| US10784577B2 |
Dual-band antenna module
A dual-band antenna module includes a substrate, a dual-band omnidirectional antenna, a low-frequency reflection module and a high-frequency reflection module. The dual-band omnidirectional antenna is disposed perpendicular to the substrate and is used for resonating to generate a first radio-frequency signal with a first frequency and a second radio-frequency signal with a second frequency. The low-frequency reflection module includes three low-frequency reflection units used for reflecting the first radio-frequency signal with the first frequency according to different low-frequency directional control signals. The high-frequency reflection module includes three high-frequency reflection units used for reflecting the second radio-frequency signal with the second frequency according to different high-frequency directional control signals. The low-frequency reflection units of the low-frequency reflection module and the high-frequency reflection units of the high-frequency reflection module are disposed on the substrate and are disposed around the dual-band omnidirectional antenna. |
| US10784575B2 |
Phased antenna array and method of thinning thereof
A method of thinning a phased antenna array including defining a performance characteristic for the phased antenna array, partitioning the phased antenna array to define a plurality of sectors that each include an equal number of radiating element locations, wherein each radiating element location is either an active radiating element location or an inactive radiating element location. The method also includes determining a number of active radiating element locations to be included in a first sector of the plurality of sectors, and determining, based on the number of active radiating element locations, at least one arrangement of active and inactive radiating element locations in the first sector configured to achieve the performance characteristic. The method further includes applying the at least one arrangement to each remaining sector of the plurality of sectors such that the phased antenna array has rotational symmetry. |
| US10784570B2 |
Liquid-crystal antenna device
A liquid-crystal antenna device includes a signal source, a driving module, a correction module, and a plurality of radiation units. The signal source provides an input electromagnetic wave. The driving module outputs a plurality of initial voltage signals according to a radiation address. The correction module receives the initial voltage signals and outputs a plurality of corrected voltage signals according to a lookup table. The radiation units respectively receive the corrected voltage signals and are coupled to the input electromagnetic wave to generate an output electromagnetic wave. |
| US10784567B2 |
Methods and systems for mitigating interference with a nearby satellite
In one embodiment, an antenna system is described. The antenna system includes a primary antenna on an aircraft. The primary antenna is mechanically steerable and has an asymmetric antenna beam pattern with a narrow beamwidth axis and a wide beamwidth axis at boresight. The antenna system also includes a secondary antenna on the aircraft, the secondary antenna including an array of antenna elements. The antenna system also includes an antenna selection system to control communication of a signal between the aircraft and a target satellite via the primary antenna and the secondary antenna. The antenna selection system switches communication of the signal from the primary antenna to the secondary antenna when an amount of interference with an adjacent satellite reaches a threshold due to the wide beamwidth axis of the asymmetric antenna beam pattern. |
| US10784562B2 |
Wireless communication chip having internal antenna, internal antenna for wireless communication chip, and method of fabricating wireless communication chip having internal antenna
A wireless communication chip having an internal antenna includes a substrate having first and second mounting regions; a wireless communication module molded on the first mounting region; and an antenna block mounted on the second mounting region to be electrically connected to the wireless communication module, wherein the antenna block includes a first antenna on the substrate; a connection element connected to the first antenna; an insulating layer on the first antenna and the connection element to cover the first antenna and the connection element; and a second antenna on the insulating layer such that a first surface of the second antenna is in contact with the insulating layer, and a second surface, which is a reverse surface of the first surface, is exposed to the outside of the wireless communication chip, wherein the second antenna is electrically connected to the first antenna through the connection element. |
| US10784560B1 |
Vehicle antenna with anti-theft feature
An after-market antenna for a vehicle includes an elongated body having a top end, a bottom end, and at least one peripheral side. The bottom end terminates with an axial bore extending partially through the body and adapted to receive an antenna wire within. The axial bore includes threads at the bottom end of the body that extend upward at least partially through the axial bore for receiving a conductive threaded shaft that projects out of the axial bore and that is adapted for screwing into a threaded antenna aperture of the vehicle. A first groove is formed around the body and has a back wall that is substantially circular in cross-section except for two opposing parallel sides adapted for contacting two opposing sides of a wrench that has a thickness that is smaller than a width of the first groove. |
| US10784556B2 |
Apparatus and a method for coupling an electromagnetic wave to a transmission medium, where portions of the electromagnetic wave are inside the coupler and outside the coupler
A dielectric waveguide coupling system for launching and extracting guided wave communication transmissions from a wire. At millimeter-wave frequencies, wherein the wavelength is small compared to the macroscopic size of the equipment, transmissions can propagate as guided waves guided by a strip of dielectric material. Unlike conventional waveguides, the electromagnetic field associated with the dielectric waveguide is primarily outside of the waveguide. When this dielectric waveguide strip is brought into close proximity to a wire, the guided waves decouple from the dielectric waveguide and couple to the wire, and continue to propagate as guided waves about the surface of the wire. |
| US10784553B2 |
Well thermalized stripline formation for high-density connections in quantum applications
A stripline that is usable in a quantum application (q-stripline) includes a first polyimide film and a second polyimide film. The q-stripline further includes a first center conductor and a second center conductor formed between the first polyimide film and the second polyimide film. The q-stripline has a first pin configured through a first recess in the second polyimide film to make electrical and thermal contact with the first center conductor. |
| US10784551B2 |
Band-pass filter
A band-pass filter includes a main body, five resonators, a shield, and a partition. The main body is formed of a dielectric. The partition is formed of a conductor. The five resonators are configured so that capacitive coupling is established between every two of the resonators adjacent to each other in circuit configuration. Each of the five resonators includes a resonator conductor portion. A first stage resonator and a fifth stage resonator are magnetically coupled to each other although not adjacent to each other in circuit configuration. The partition extends to pass between the respective resonator conductor portions of the first stage resonator and the fifth stage resonator, and is electrically connected to the shield. |
| US10784550B2 |
Low-loss, low-profile digital-analog phase shifter
A phase shifter having both digital and analog shifting components is disclosed. The digital-analog phase shifter includes an input/output port configured, in part, for receiving an input radio frequency (RF) signal from an external source and outputting a phase shifted RF signal. A digital shifter performs coarse phase shifts of the input RF signal, while an analog shifter variably shift the phase of the input RF signal relative to the coarse phase shift. This produces a phase shifted RF signal having a total phase range that is output is continuously variable from 0° to 360°. |
| US10784545B2 |
Submerged cell modular battery system
An apparatus includes a plurality of battery cells and a case. The case may be configured to hold the plurality of battery cells. The case generally has at least a first port and a second port configured to allow a cooling liquid to flow through the case with the battery cells submerged in the cooling liquid. The case is generally configured to interlock with one or more other cases to electrically and physically connect the one or more cases into a battery block or battery pack. |
| US10784543B2 |
Cell block and cell module
A battery block includes a holding unit that holds a plurality of cells. The holding unit is made of a material having a heat conductivity. The holding unit includes openings that are open over the entire length of the side surfaces of the cells in the longitudinal direction. Each opening is formed so that, on the side surface of each cell, the area of a first region exposed to the outside through the opening is smaller than that of a second region other than the first region. |
| US10784542B2 |
System and method with battery management
A processor-implemented battery management method includes iteratively determining fractions of components in an electrode of a battery; calculating a composite state of charge (SoC) of the battery by applying the iteratively determined fractions of the components to a composite cathode model used to predict a state of the battery; and predicting the state of the battery based on the calculated composite SoC. |
| US10784541B2 |
Storage battery device, and charging-discharging monitoring method, device and system thereof
A storage battery device, a charging and discharging monitoring method and device thereof and a corresponding system are described. The storage battery device includes multiple storage batteries connected in parallel. A storage battery switching unit connected in series with each storage battery is arranged on a parallel branch circuit where the storage battery is located, and includes a charging control unit configured to switch on or switch off a charging loop of the storage battery and a discharging control unit connected in parallel with the charging control unit and configured to switch on or switch off a discharging loop of the storage battery. |
| US10784539B2 |
Electrode assembly having high flexibility and battery cell including the same
The present invention provides an electrode assembly, including two or more positive electrode plates and two or more negative electrode plates laminated with each of separators interposed therebetween, wherein both side end portions of the electrode assembly are bent together in the same direction by a curvature radius (R) satisfying the following Equation 1: S[{1/ln(x/y)}*t]=R 1 wherein t is an average thickness (mm) of the laminated electrode assembly, x is a horizontal length of the electrode assembly, and y is a vertical length of the electrode assembly, and S is a constant of 10 or more, and ln(x/y)≥1. |
| US10784538B2 |
Multifunctional energy storage composites
Described here is a multifunctional energy storage (MES) composite comprising (a) a stack of energy storage materials and (b) one or more structural facesheets sandwiching the stack of energy storage materials, wherein the stack of battery materials is perforated by (c) one or more reinforcements, and wherein the reinforcements are bonded to the structural facesheets. Also described here is a MES composite comprising (a) a stack of energy storage materials, (b) one or more structural facesheets sandwiching the stack of energy storage materials, and (c) one or more reinforcements perforated by the stack of energy storage materials, wherein the reinforcements are bonded to the structural facesheets. |
| US10784535B2 |
Slurry, method for producing solid electrolyte layer, and method for producing all-solid-state battery
Provided are a slurry for a solid electrolyte, which can reduce the usage of a polymer binder, a method for producing a solid electrolyte layer, and a method for producing an all-solid-state battery. Disclosed is a slurry for a solid electrolyte, the slurry comprising a solvent, a lithium compound, and crystal particles of a garnet-type ion-conducting oxide represented by a general formula (Lix−3y−z,Ey,Hz)LαMβOγ (where E is at least one kind of element selected from the group consisting of Al, Ga, Fe and Si; L is at least one kind of element selected from an alkaline-earth metal and a lanthanoid element; M is at least one kind of element selected from a transition element that can be six-coordinated with oxygen and typical elements in groups 12 to 15 of the periodic table; 3≤x−3y−z≤7; 0≤y≤0.25; 0 |
| US10784533B2 |
Li—Sn—O—S compound, manufacturing method therefor and use thereof as electrolyte material of Li-ion batteries, and Li—Sn—O—S hybrid electrolyte
A Li—Sn—O—S compound, a manufacturing method therefor and use thereof as an electrolyte material of Li-ion batteries, and a Li—Sn—O—S hybrid electrolyte are provided. The Li—Sn—O—S compound of the present invention is laminated Sn—O—S embedded with lithium ions. The Li—Sn—O—S compound is represented by the formula Li3x[LixSn1−x(O,S)2], where x>0. The manufacturing method for a Li—Sn—O—S compound includes the following steps of: (S1000) providing a Sn—O—S compound; (S2000) adding a lithium source into the Sn—O—S compound to form a Li—Sn—O—S precursor; and (S3000) performing calcination on the Li—Sn—O—S precursor in a vulcanization condition. |
| US10784532B2 |
Chemical formulations for electrochemical device
Chemical additives are disclosed to increase solubility of salts in liquefied gas electrolytes. |
| US10784530B2 |
Dioxazolones and nitrile sulfites as electrolyte additives for lithium-ion batteries
Improved battery systems have been developed for lithium-ion based batteries. The improved systems include a nonaqueous electrolyte including one or more lithium salts, one or more nonaqueous solvents, and an additive or additive mixture comprising one or more operative additives selected from a group of disclosed compounds, including 3-aryl substituted 1,4,2-dioxazol-5-ones and 3-phenyl-1,3,2,4-dioxathiazole 2-oxide. |
| US10784529B2 |
Frame for fuel cell and fuel cell stack structure having the frame
There is provided a frame for a fuel cell. The frame include a frame body having a channel opening defined therein and a feed opening and a discharge opening defined therein, wherein the feed opening and discharge opening are spaced apart from each other with the channel opening being disposed therebetween; and a plurality of anti-deformation support structures protruding from a top face of the frame body, in a first region between the channel opening and the feed opening and in a second region between the channel opening and the discharge opening, wherein each of the plurality of anti-deformation support structures has an elliptical cross-sectional shape having a major axis and a minor axis. |
| US10784526B2 |
Fuel cell vehicle and control method of fuel cell vehicle
A fuel cell vehicle is configured such that at least a part of an underfloor of a vehicle body is formed to have a shape causing a downforce to the vehicle body by wind passing below the underfloor, and an exhaust port via which exhaust gas from a cathode-side passage of a fuel cell is discharged is disposed in a negative pressure region where a negative pressure is caused by the shape causing the downforce. A magnitude of the negative pressure to be caused by the shape is detected or estimated, so that a driving amount of an air supply configured to supply air to the fuel cell is controlled according to the magnitude of the negative pressure thus detected or estimated. |
| US10784525B2 |
Method of inspecting output of fuel cell
In a method of inspecting output of a fuel cell, a reduction step is performed, and thereafter, a measurement step is performed. In the reduction step, reduction treatment is applied to electrode catalyst contained in an anode and a cathode. After the reduction treatment is applied to the electrode catalyst of the anode and the cathode, in the measurement step, measurement current which is smaller than rated current of the fuel cell, is applied to the anode and the cathode to inspect the output of the fuel cell. |
| US10784523B2 |
Fuel cell stack presenting reinforced structure
A bipolar plate (20) for making a proton-exchange membrane fuel cell stack, said bipolar plate (20) being made up of metal sheets that are shaped and assembled together in such a manner as to define primary fluid-flow channels (24) and secondary fluid-flow channels (25) that are arranged in alternation, said primary channels (24) being formed between said assembled-together sheets; the bipolar plate (20) being characterized in that it includes mechanical reinforcement (35) made out of metal material arranged in a reinforcing duct (30) of the bipolar plate (20), said metal reinforcement (35) being configured in such a manner as to oppose a compression force applied to the bipolar plate (20), said bipolar plate (20) further including a source of electricity adapted to feed electric current to the mechanical reinforcement (35) and thereby give off heat by the Joule effect. |
| US10784519B2 |
Electrochemical cell with electrode filled protrusion
An electrochemical cell comprises a can comprising a cylindrical side wall extending from a closed end wall. The closed end wall comprises a protrusion. The protrusion has a protrusion cavity therein. The electrochemical cell further comprises a separator defining an inner cavity and separating the inner cavity from an outer cavity. The outer cavity is defined by the can and the separator. The electrochemical cell further comprises a first electrode material disposed in the outer cavity and the protrusion cavity; and a second electrode material disposed in the inner cavity. |
| US10784514B2 |
Conductive carbon, electrode material including said conductive carbon, and electrode using said electrode material
Provided is conductive carbon that gives an electrical storage device having a high energy density. This conductive carbon includes a hydrophilic part, and the contained amount of the hydrophilic part is 10 mass % or more of the entire conductive carbon. When performing a rolling treatment on an active material layer including an active material particle and this conductive carbon formed on a current collector during manufacture of an electrode of an electric storage device, the pressure resulting from the rolling treatment causes this conductive carbon to spread in a paste-like form and increase in density. The active material particles approach each other, and the conductive carbon is pressed into gaps formed between adjacent active material particles, filling the gaps. As a result, the amount of active material per unit volume in the electrode obtained after the rolling treatment increases, and the electrode density increases. |
| US10784509B2 |
Lithium metal secondary battery containing two anode-protecting layers
Provided is a lithium secondary battery, comprising a cathode, an anode, and a porous separator or electrolyte, wherein the anode comprises: (a) an anode active layer containing a layer of lithium or lithium alloy, in a form of a foil, coating, or multiple particles aggregated together, as an anode active material; (b) a first anode-protecting layer having a thickness from 1 nm to 100 μm, a specific surface area greater than 50 m2/g and comprising a thin layer of electron-conducting material selected from graphene sheets, carbon nanotubes, carbon nanofibers, carbon or graphite fibers, expanded graphite flakes, metal nanowires, conductive polymer fibers, or a combination thereof, and (c) a second anode-protecting layer having a thickness from 1 nm to 100 μm and comprising an elastomer having a fully recoverable tensile elastic strain from 2% to 1,000% and a lithium ion conductivity from 10−8 S/cm to 5×10−2 S/cm. |
| US10784508B2 |
Preparation method of modified positive electrode active material
The present disclosure provides a preparation method of a modified positive electrode active material preparation method, which comprising steps of: dispersing a positive electrode active material matrix into an alcohol solvent to form a positive electrode active material matrix suspension; dissolving an alcohol-soluble aluminum salt in an alcohol solvent to form an alcohol-soluble aluminum salt solution; dissolving an alcohol-soluble phosphorous compound in an alcohol solvent to form an alcohol-soluble phosphorous compound solution; mixing the alcohol-soluble aluminum salt solution and the alcohol-soluble phosphorous compound solution and heating to react, obtaining a liquid-phase coating solution which contains aluminum phosphate after the reaction is finished; mixing and stirring the positive electrode active material matrix suspension and the liquid-phase coating solution which contains aluminum phosphate, extraction filtrating and obtaining a filter cake after the stirring is finished, then drying and baking the filter cake, finally obtaining a modified positive electrode active material. |
| US10784501B2 |
Positive electrode plate and method of forming slurry for positive electrode plate
A method of forming slurry for a positive electrode plate is provided, which includes reacting maleimide compound and barbituric acid to form a hyper branched polymer. 0.1 to 1 part by weight of the hyper branched polymer is mixed with 0.01 to 1 part by weight of coupling agent and 0.1 to 6 parts by weight of carbon nanotube to form a mixture. 80 to 97.79 parts by weight of active material is added to the mixture, wherein the hyper branched polymer, the carbon nanotube, and the active material are bonded by the coupling agent. |
| US10784498B2 |
Positive electrode, battery, battery pack, electronic device, electric vehicle, electricity storage device, and electric power system
A positive electrode contains a first active material and a second active material. The first active material and the second active material each contain a lithium composite oxide containing at least manganese (Mn), nickel (Ni), and cobalt (Co) as transition metals. The first active material has a particulate shape. An average porosity V1 in a particle of the first active material satisfies 10[%]≤V1≤30[%]. An average particle diameter D1 of the first active material satisfies 6 [μm]≤D1≤20 [μm]. The second active material has a particulate shape. An average porosity V2 in a particle of the second active material satisfies 0[%]≤V2≤10[%]. An average particle diameter D2 of the second active material satisfies 1 [μm]≤D2≤6 [μm]. |
| US10784493B2 |
Charger, electronic device, charging system and charging method
The present disclosure relates to the technical field for charging an electrical appliance and provides a charger. The charger includes a base plate; and a first charge terminal and a control circuit disposed on the base plate. When the first charge terminal is connected with a charge plug, the first charge terminal switches from an extension position to a retraction position. The control circuit is configured to control the first charge terminal to be on-state when the first charge terminal is in the retraction position. |
| US10784492B2 |
Low profile pressure disconnect device for lithium ion batteries
Casings for lithium ion batteries are provided that include a container or assembly that defines a base, side walls and a top or lid, and a vent structure associated with the container or assembly. A flame arrestor may be positioned in proximity to the vent structure. The lithium ion battery may also include a pressure disconnect device associated with the casing. The pressure disconnect device may include a deflectable dome-based activation mechanism, and the deflectable dome-based activation mechanism may be configured and dimensioned to prevent burn through, e.g., by increasing the mass of the dome-based activation mechanism, adding material (e.g., foil) to the dome-based activation mechanism, and combinations thereof. Burn through may also be avoided, at least in part, based on the speed at which the dome-based activation mechanism responds at a target trigger pressure. |
| US10784490B2 |
Pouch type of battery cell having unit electrode where a plurality of electrode tabs are formed
The present invention provides a battery cell including: an electrode assembly having a structure in which a positive electrode, a negative electrode, and a separator are laminated, each of the positive electrode and the negative electrode having 2×n (n≥2), wherein a positive tab is provided in each of odd-numbered sides, and a negative electrode tab is provided in each of even-numbered sides, and the positive electrodes and the negative electrode tabs are alternately formed along the sides; electrode terminals respectively disposed on a first side and a second side of the electrode assembly, in which outermost electrodes are disposed, or third sides which are side surfaces of the electrode assembly, being perpendicular to the first side and the second side, and a battery case having a structure of surrounding an external surface of the electrode assembly. |
| US10784485B2 |
Cell contact-making system for an electrochemical device
A cell contact-making system for an electrochemical device that includes a plurality of electrochemical cells is provided. The cell contact-making system includes a signal conductor system having one or more signal conductors for electrically conductively connecting a signal source to a signal conductor terminal connector or to a monitoring arrangement of the electrochemical device, wherein the signal conductor system includes at least one flexible printed circuit, wherein the flexible printed circuit includes at least one flexible insulating film and at least one conductor track that is arranged on the insulating film. |
| US10784477B2 |
Rechargeable battery with elastically compliant housing
A rechargeable battery with elastically compliant housing includes a housing and at least one battery cell. The housing includes a pair of substantially rigid end plates and an elastically compliant structure joining the end plates so that the end plates are oriented in respective planes that are substantially parallel to each other and define a gap there between. Each battery cell is contained in the housing in the gap between the end plates and includes an anode, a cathode, and a separator between the anode and the cathode. The elastically compliant structure joins the end plates and includes an elastic component that exhibits elastic expansion greater than 3% along an axis orthogonal to the planes in which the end plates are oriented. |
| US10784476B2 |
Sealing apparatus for battery case with increased application area of pressure and heat
The present invention provides a sealing apparatus having a structure in which an application area of pressure and heat is increased by a pair of sealing blocks and a pressurization part extending from the sealing block. In the sealing apparatus according to the present invention based on the structure, when the sealing-planned part is pressurized, heat and pressure may be applied to the sealing-planned part or an insulating film to be extended, and thus an electrode lead and the sealing-planned part adjacent thereto may be firmly bonded. |
| US10784475B2 |
Cap assembly for a second battery and second battery
The present disclosure provides a cap assembly for a secondary battery and a secondary battery. The cap assembly includes a cap plate, a fixing member, a connecting member and an electrode terminal, wherein the cap plate has an electrode lead-out hole; the fixing member is fixed to the cap plate through the connecting member and provided with a weakened portion that is close to a center line of the cap plate in a width direction of the cap plate; and the electrode terminal includes a terminal board, wherein the terminal board has an outer peripheral surface at least partially surrounded by the fixing member so that the electrode terminal is fixed to the fixing member, and the terminal board is provided on a side of the cap plate and covers the electrode lead-out hole. |
| US10784472B2 |
Nozzle-droplet combination techniques to deposit fluids in substrate locations within precise tolerances
An ink printing process employs per-nozzle droplet volume measurement and processing software that plans droplet combinations to reach specific aggregate ink fills per target region, guaranteeing compliance with minimum and maximum ink fills set by specification. In various embodiments, different droplet combinations are produced through different print head/substrate scan offsets, offsets between print heads, the use of different nozzle drive waveforms, and/or other techniques. Optionally, patterns of fill variation can be introduced so as to mitigate observable line effects in a finished display device. The disclosed techniques have many other possible applications. |
| US10784467B2 |
Thin film packaging structures and display devices
The present disclosure relates to a thin film packaging structure, which includes at least one first composite film layer. The first composite film layer includes at least one first organic film layer and at least one mesh cushioning layer. A surface of at least part of the first organic film layers is provided with the mesh cushioning layer, and/or at least part of the first organic film layers is embedded with the mesh cushioning layer. According to applying the thin film packaging structure of the present disclosure, the mesh cushioning layer has better flexibility. During cutting process or under the influence of external forces, the mesh cushioning layer can effectively cushion stress acting on a display screen, and reduce stress propagation along a direction perpendicular to a thickness direction of the display screen, thereby avoiding cracking of the display screen effectively. The present disclosure further relates to a display device. |
| US10784465B2 |
Light-emitting device having white light emission
There has been a problem that difference in refractive index between an opposite substrate or a moisture barrier layer provided thereover, and air is maintained large, and light extraction efficiency is low. Further, there has been a problem that peeling or cracking due to the moisture barrier layer is easily generated, which leads to deteriorate the reliability and lifetime of a light-emitting element. A light-emitting element includes a pixel electrode, an electroluminescent layer, a transparent electrode, a passivation film, a stress relieving layer, and a low refractive index layer, all of which are stacked sequentially. The stress relieving layer serves to prevent peeling of the passivation film. The low refractive index layer serves to reduce reflectivity of light generated in the electroluminescent layer in emitting to air. Therefore, a light-emitting element with high reliability and long lifetime and a display device using the light-emitting element can be provided. |
| US10784464B2 |
Inorganic film and encapsulating film
The disclosure discloses an inorganic film applied for thin film encapsulation of an OLED device. The inorganic film includes inorganic layer units including a first inorganic layer, a second inorganic layer, and a third inorganic layer located between the first inorganic layer and the second inorganic layer, and the third inorganic layer is formed by reacting the first inorganic layer with the second inorganic layer. The inorganic film is used in the thin film encapsulation of the OLED device, which can improve the ability of the device to block the water and oxygen and improve the product quality. |
| US10784462B2 |
Display device
A display device includes: a substrate including a first pixel area (PA) and a second PA, the first PA being spaced apart from the second PA by a non-PA; a first pixel electrode (PE) overlapping the first PA; a second PE overlapping the second PA; a pixel-defining layer including a first opening overlapping the first PE and a second opening overlapping the second PE; a first intermediate layer (IL) on the first PE, the first IL including a first emission layer (EL); a second IL on the second PE, the second IL including a second EL spaced apart from the first EL; a first opposite electrode (OE) on the first IL; a second OE on the second IL, the second OE being spaced apart from the first OE; and a wiring layer (WL) overlapping the non-PA, the WL contacting respective portions of the first OE and the second OE. |
| US10784448B2 |
Electroluminescent imidazo-quinoxaline carbene metal complexes
Metal carbene complexes comprising at least one imidazo-quinoxaline ligand, organic electronic devices, especially OLEDs (Organic Light-Emitting Diodes) which comprise such complexes, a light-emitting layer comprising at least one inventive metal carbene complex, an apparatus selected from the group consisting of illuminating elements, stationary visual display units and mobile visual display units comprising such an OLED, the use of such a metal carbene complex for electrophotographic photoreceptors, photoelectric converters, organic solar cells (organic photovoltaics), switching elements, organic light emitting field effect transistors (OLEFETs), image sensors, dye lasers and electroluminescent devices and a process for preparing such metal carbene complexes. |
| US10784446B2 |
Compound, organic electroluminescence element material, organic electroluminescence element and electronic device
A compound is represented by a formula (100) below, where X1, X2 and X3 are each independently a nitrogen atom or a carbon atom bonded with R2, Y is an oxygen atom, a sulfur atom and the like, R1, R2, R11, R21 and R22 are each a hydrogen atom or a substituent, L1 is a single bond or a linking group, and L2 is a linking group. |
| US10784445B2 |
Test substrate and manufacturing method thereof, detection method, display substrate and display device
A test substrate includes a base and a first electrode layer, a pixel defining layer, a light-emitting functional layer and a second electrode layer disposed on the base in sequence. The test substrate has at least two test regions, and each test region is a region where one first electrode of the plurality of first electrodes is located. Each test region includes a first region. Orthographic projections of portions of the pixel defining layer and the light-emitting functional layer located in a same first region on the base overlap with each other, and areas of orthographic projections of portions of the first electrode layer located in first regions of the at least two test regions are different. |
| US10784444B2 |
Light detector
A light detection element including: a carbon nanotube structure; a first electrode and a second electrode, electrically connected to the carbon nanotube structure; wherein the carbon nanotube structure includes at least one carbon nanotube, the carbon nanotube includes two metallic carbon nanotube segments and one semiconducting carbon nanotube segment between the two metallic carbon nanotube segments, one of the two metallic carbon nanotube segments is electrically connected to the first electrode, the other one of the two metallic carbon nanotube segments is electrically connected to the second electrode. |
| US10784438B2 |
Magnetoresistive effect element
A magnetoresistive effect element according to one aspect of the present disclosure includes a first ferromagnetic layer, a second ferromagnetic layer, and a spacer layer. The spacer layer is provided between the first ferromagnetic layer and the second ferromagnetic layer. The spacer layer includes an Mn alloy represented by General Formula (1). MnγX1-γ (1) (in the Formula, X is at least one metal selected from the group consisting of Al, V, Cr, Cu, Zn, Ag, Au, an NiAl alloy, an AgMg alloy, and an AgZn alloy, and γ is 0<γ<0.5.) |
| US10784435B2 |
Method for producing ceramic multi-layer components
Methods for producing ceramic multi-layer components and multi-layer components made by such methods. A method includes the following steps: providing green layers for the ceramic multi-layer components, stacking the green layers into a stack and subsequently pressing the stack into a block, singulating the block into partial blocks each having a longitudinal direction, thermally treating the partial blocks and subsequently machining surfaces of the partial blocks. Recesses are produced on the surfaces of the partial blocks during the machining, and the partial blocks are singulated. |
| US10784433B2 |
Graphene-based superconducting transistor
A transistor. In some embodiments, the transistor includes a first superconducting source-drain, a second superconducting source-drain, a graphene channel including at least a portion of a graphene sheet, and a conductive gate. The first superconducting source-drain, the second superconducting source-drain, and the graphene channel together form a Josephson junction having a critical current. The graphene channel forms a current path between the first superconducting source-drain and the second superconducting source-drain. The conductive gate is configured, upon application of a electric field across the conductive gate and the graphene channel by applying a voltage, to modify the critical current. |
| US10784432B2 |
Vertical josephson junction superconducting device
Techniques for a vertical Josephson junction superconducting device are provided. In one embodiment, a chip surface base device structure is provided that comprises a substrate comprising crystalline silicon that is coupled with a first superconducting layer, wherein the first superconducting layer is coupled with a second substrate comprising crystalline silicon. In one implementation, the chip surface base device structure also comprises a vertical Josephson junction located in an etched region of the substrate, the vertical Josephson junction comprising a first superconducting layer, a tunnel barrier layer, and a top superconducting layer. |
| US10784426B2 |
Device substrate
A device substrate includes a receiving substrate, a micro light emitting element, a first wire, and a second wire is provided. The micro light emitting element is disposed on the receiving substrate. The micro light emitting element includes a first type semiconductor layer and a second type semiconductor layer. The first type semiconductor layer is disposed on the receiving substrate and has a first wire connecting surface away from the receiving substrate. The second type semiconductor layer is disposed on a part of the first type semiconductor layer and has a second wire connection surface away from the receiving substrate. The first wire is disposed on the first wire connection surface. The second wire is disposed on the second wire connection surface. A projection range of the first wire perpendicularly projected on the micro light emitting element and a projection range of the second wire perpendicularly projected on the micro light emitting element are at least partially overlap. |
| US10784425B2 |
Light illuminating module and wire board for LED device
The light illumination module includes a substrate, a plurality of wiring patterns formed in parallel on the substrate, and a plurality of LED devices disposed on the wiring patterns. Each wiring pattern has a stripe-shaped portion extending in a first direction, a first protrusion portion protruding in a second direction, and a second protrusion portion protruding in an opposite direction. The first and second protrusion portions are formed in an alternating manner along the first direction, and the LED devices are disposed on the first protrusion portion and the stripe-shaped portion at a location corresponding to the second protrusion portion. A first electrode of each LED device is electrically connected to the first protrusion portion or the stripe-shaped portion immediately below, and a second electrode of each LED device is electrically connected to the stripe-shaped portion or the second protrusion portion of an adjacent wiring pattern with a wire. |
| US10784418B2 |
Vertical type light emitting element having color conversion electrode part
A vertical type light emitting element is disclosed. The vertical type light emitting element includes: a color conversion electrode part including a first electrode pad and a color conversion layer; a reflective electrode part including a second electrode pad and a reflective layer; and a light emitting semiconductor part interposed between the color conversion electrode part and the reflective electrode part. The color conversion electrode part further includes an electrically conductive light transmissive plate. The first electrode pad and the color conversion layer are interposed between the light transmissive plate and the upper surface of the light emitting semiconductor part. Roughnesses are formed on the upper surface of the light emitting semiconductor part bordering the color conversion electrode part to increase the amount of light entering the color conversion electrode part through the light emitting semiconductor part. |
| US10784417B2 |
Wavelength conversion film
Provided is a wavelength conversion film that suppresses a deterioration of quantum dots by oxygen and is capable of suppressing a decrease in brightness. The wavelength conversion film includes a wavelength conversion layer and auxiliary layers sandwiching the wavelength conversion layer, in which the wavelength conversion layer has polyvinyl alcohol and cured substance particles of a (meth)acrylate compound including wavelength conversion particles, and an oxygen permeability of the auxiliary layer is 1.0×100 to 1.0×10−2 cc/(m2·day·atm). |
| US10784416B2 |
Light source device and light emitting device
Provided is a light source device including: at least one light emitting element of at least one type; at least one far-red phosphor that, when excited by output light from the light emitting element, emits light having a peak in a wavelength range of 680 nm or more to less than 780 nm; and at least one phosphor that, when excited by the output light from the light emitting element, emits light having a peak in a wavelength range different from the wavelength range of the light emitted from the far-red phosphor. The spectrum of light emitted from the light source device has characteristic A below. This light source device has sufficient emission intensity over the entire visible range, i.e., over a wavelength range of from 400 nm to 750 nm inclusive.Characteristic A: The ratio of a minimum emission intensity to a maximum emission intensity in a wavelength range of from 400 nm to 750 nm inclusive is 20% or more. |
| US10784415B2 |
Light-emitting device package, manufacturing method thereof, and vehicle lamp and backlight unit including same
Disclosed are a light-emitting device package, a manufacturing method therefor, and a vehicle lamp and a backlight unit including the same. The light-emitting device package includes: a light-emitting chip having electrode pads positioned at a lower part thereof; a wavelength conversion unit for covering at least an upper surface and lateral surfaces of the light-emitting chip; and a reflective part which covers the lateral surfaces of the light-emitting chip. Accordingly, the light-emitting device package can be miniaturized and a separate substrate for forming a lens is not required. |
| US10784410B2 |
Molecular coatings of nitride semiconductors for optoelectronics, electronics, and solar energy harvesting
Gallium nitride based semiconductors are provided having one or more passivated surfaces. The surfaces can have a plurality of thiol compounds attached thereto for enhancement of optoelectronic properties and/or solar water splitting properties. The surfaces can also include wherein the surface has been treated with chemical solution for native oxide removal and/or wherein the surface has attached thereto a plurality of nitrides, oxides, insulating compounds, thiol compounds, or a combination thereof to create a treated surface for enhancement of optoelectronic properties and/or solar water splitting properties. Methods of making the gallium nitride based semiconductors are also provided. Methods can include cleaning a native surface of a gallium nitride semiconductor to produce a cleaned surface, etching the cleaned surface to remove oxide layers on the surface, and applying single or multiple coatings of nitrides, oxides, insulating compounds, thiol compounds, or a combination thereof attached to the surface. |
| US10784409B2 |
Semiconductor element
An embodiment provides a semiconductor element, which comprises: a plurality of semiconductor structures, each of which comprises a first conductive semiconductor layer, a second conductive semiconductor layer, an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer, and a first recess extending through the second conductive semiconductor layer and the active layer to a partial area of the first conductive semiconductor layer; a second recess disposed between the plurality of semiconductor structures; a first electrode disposed at the first recess and electrically connected to the first conductive semiconductor layer; a reflective layer disposed under the second conductive semiconductor layer; and a protrusion part disposed on the second recess and protruding higher than the upper surfaces of the semiconductor structures, wherein a surface, on which the first electrode contacts the first conductive semiconductor layer in the first recess, is 300 to 500 nm distant from the upper surfaces of the semiconductor structures. |
| US10784408B2 |
Optoelectronic semiconductor chip and method of producing an optoelectronic semiconductor chip
An optoelectronic semiconductor chip includes a semiconductor body including a first semiconductor region, a second semiconductor region and an active zone disposed between the first and second semiconductor regions, an electrically conductive contact layer arranged on a side of the first semiconductor region facing away from the second semiconductor region, and an electrically conductive mirror layer arranged between the first semiconductor region and the electrically conductive contact layer, and laterally protruding at the edge by the first semiconductor region and the electrically conductive contact layer so that between the first semiconductor region and the electrically conductive contact layer there is an interspace in which a protective layer is arranged for protecting the mirror layer, wherein the electrically conductive contact layer extends laterally to an edge of the first semiconductor region, and the electrically conductive contact layer consists of Ni. |
| US10784404B2 |
Light-emitting device
A light-emitting device, includes a substrate structure, including a base portion having a surface and a plurality of protrusions formed on the base portion; a buffer layer covering the plurality of protrusions and the surface; and III-V compound semiconductor layers formed on the buffer layer; wherein one of the plurality of protrusions has a height not greater than 1.5 μm; wherein the light-emitting device has a full width at half maximum (FWHM) of smaller than 250 arcsec in accordance with a (102) XRD rocking curve. |
| US10784403B2 |
Glass wiring substrate, method of producing the same, part-mounted glass wiring substrate, method of producing the same, and display apparatus substrate
A glass wiring substrate includes a glass substrate, a first wiring portion being formed on a first surface of the glass substrate, a second wiring portion being formed on a second surface opposite to the first surface; a through-hole formed in a region of the glass substrate in which the first wiring portion and the second wiring portion are not formed, the through-hole having a diameter on a second surface side larger than a diameter on a first surface side; and a through-hole portion formed in the through-hole, one end portion of the through-hole portion extending to the first wiring portion, the other end portion of the through-hole portion extending to the second wiring portion, in which a wiring pitch P1 of the first wiring portion in the vicinity of the through-hole portion is narrower than a wiring pitch P2 of the second wiring portion in the vicinity of the through-hole portion. |
| US10784399B2 |
Method for fabricating graphene light emitting transistor
A method is provided for fabricating a graphene light emitting transistor. The method includes: forming a gate electrode on a substrate; forming a gate insulating layer on the substrate and the gate electrode; forming a graphene oxide layer on the gate insulating layer; reducing two ends of the graphene oxide layer to respectively form a source electrode and a drain electrode made of graphene; forming a graphene quantum dot layer on an unreduced part of the graphene oxide layer, the source electrode, and the drain electrode; and forming a water and oxygen resistant layer on the graphene quantum dot layer. |
| US10784398B2 |
Vertical solid state devices
A vertical current mode solid state device comprising a connection pad and side walls comprising a metal-insulator-semiconductor (MIS) structure, wherein leakage current effect of the vertical device is limited through the side walls by biasing the MIS structure. |
| US10784396B2 |
Solar cell, solar cell module, and production method for solar cell
An n-type low-doped region and a first main-surface side highly doped region, which has an n-type dopant concentration higher than that in the n-type low-doped region, are provided in an n-type crystalline silicon substrate. The first main-surface side highly doped region is arranged between the n-type low-doped region and a p-type amorphous silicon layer. |
| US10784392B2 |
Solar cell module and method for manufacturing the same
A solar cell module includes: a solar cell having a front surface and a back surface; a front surface side encapsulant disposed on a front surface side of the solar cell, the front surface side encapsulant including a transparent resin sheet; a light reflector protruding from an end portion of the solar cell, the light reflector including a light reflection layer that reflects incident light, and a substrate layer that is disposed on the light reflection layer on a light incident side; and an ultraviolet absorber disposed closer to the light incident side than the light reflection layer, the light incident side being a back surface side of the front surface side encapsulant. |
| US10784388B2 |
Photovoltaic devices with depleted heterojunctions and shell-passivated nanoparticles
Photovoltaic cells are fabricated in which the compositions of the light-absorbing layer and the electron-accepting layer are selected such that at least one side of the junction between these two layers is substantially depleted of charge carriers, i.e., both free electrons and free holes, in the absence of solar illumination. In further aspects of the invention, the light-absorbing layer is comprised of dual-shell passivated quantum dots, each having a quantum dot core with surface anions, an inner shell containing cations to passivate the core surface anions, and an outer shell to passivate the inner shell anions and anions on the core surface. |
| US10784385B2 |
Solar cell and solar cell module
A solar cell is disclosed. The solar cell includes a substrate of a first conductive type; a plurality of emitter layers having a second conductive type opposite the first conductive type, the plurality of emitter layers positioned in a first surface of the substrate and extended in a first direction in the first surface of the substrate; a plurality of surface field layers having the first conductive type more heavily doped than the substrate, the plurality of surface field layers positioned in the first surface of the substrate and extended in the first direction in the first surface of the substrate; a passivation layer positioned on the first surface of the substrate and including a plurality of first openings exposing portions of each of the plurality of surface field layers and a plurality of second openings exposing portions of each of the plurality of emitter layers; a plurality of first electrodes positioned in the plurality of first openings and contacting the plurality of surface field layers; a plurality of second electrodes positioned in the plurality of second openings and contacting the plurality of emitter layers; a plurality of first conductive members positioned on the plurality of first electrodes; and a plurality of second conductive members positioned on the plurality of second electrodes. |
| US10784378B2 |
Ultra-scaled fin pitch having dual gate dielectrics
Ultra-scaled fin pitch processes having dual gate dielectrics are described. For example, a semiconductor structure includes first and second semiconductor fins above a substrate. A first gate structure includes a first gate electrode over a top surface and laterally adjacent to sidewalls of the first semiconductor fin, a first gate dielectric layer between the first gate electrode and the first semiconductor fin and along sidewalls of the first gate structure, and a second gate dielectric layer between the first gate electrode and the first gate dielectric layer and along the first gate dielectric layer along the sidewalls of the first gate electrode. A second gate structure includes a second gate electrode over a top surface and laterally adjacent to sidewalls of the second semiconductor fin, and the second gate dielectric layer between the second gate electrode and the second semiconductor fin and along sidewalls of the second gate electrode. |
| US10784377B2 |
FinFET device and method of forming same
A method includes forming a fin over a substrate, forming a dummy gate structure over the fin, forming a first spacer over the dummy gate structure, implanting a first dopant in the fin to form a doped region of the fin adjacent the first spacer, removing the doped region of the fin to form a first recess, wherein the first recess is self-aligned to the doped region, and epitaxially growing a source/drain region in the first recess. |
| US10784374B2 |
Recessed transistors containing ferroelectric material
Some embodiments include transistor constructions having a first insulative structure lining a recess within a base. A first conductive structure lines an interior of the first insulative structure, and a ferroelectric structure lines an interior of the first conductive structure. A second conductive structure is within a lower region of the ferroelectric structure, and the second conductive structure has an uppermost surface beneath an uppermost surface of the first conductive structure. A second insulative structure is over the second conductive structure and within the ferroelectric structure. A pair of source/drain regions are adjacent an upper region of the first insulative structure and are on opposing sides of the first insulative structure from one another. |
| US10784372B2 |
Semiconductor device with high voltage field effect transistor and junction field effect transistor
Described is a semiconductor device including a first N-type well region disposed in a substrate and a second N-type well region in contact with the first N-type well region, a source region disposed in the first N-type well region, a drain region disposed in the second N-type well region, and a first gate electrode and a second gate electrode disposed spaced apart from the drain region. A maximum vertical length of the source region in a direction vertical to the first or second gate electrode is greater than a maximum vertical length of the drain region in the direction in a plan view. |
| US10784371B2 |
Self aligned top extension formation for vertical transistors
A method of forming a semiconductor device that includes providing a vertically orientated channel region; and converting a portion of an exposed source/drain contact surface of the vertically orientated channel region into an amorphous crystalline structure. The amorphous crystalline structure is from the vertically orientated channel region. An in-situ doped extension region is epitaxially formed on an exposed surface of the vertically orientated channel region. A source/drain region is epitaxially formed on the in-situ doped extension region. |
| US10784366B2 |
Integrated enhancement/depletion mode HEMT and method for manufacturing the same
The present invention provides an integrated enhancement/depletion mode HEMT and a method for manufacturing the same, by which method an enhancement mode transistor and a depletion mode transistor can be integrated together, which is beneficial for increasing the application of gallium nitride HEMT devices and improving the characteristics of circuits, and lay a foundation for realizing monolithic integration of high-speed digital/analog mixed signal radio frequency circuits. At the same time, by using a regrowth technology of a barrier layer, electrons generated by impurities are made part of a conductive channel, thus the concentration of the two-dimensional electron gas is increased, and the conductive performance is improved while preventing excessive electrons from interfering with the devices. |
| US10784365B2 |
Fin field effect transistor fabrication and devices having inverted T-shaped gate
A method of forming a fin field effect transistor (finFET), including forming a temporary gate structure having a sacrificial gate layer and a dummy gate layer on the sacrificial gate layer, forming a gate spacer layer on each sidewall of the temporary gate structure, forming a source/drain spacer layer on the outward-facing sidewall of each gate spacer layer, removing the dummy gate layer to expose the sacrificial gate layer, removing the sacrificial gate layer to form a plurality of recessed cavities, and forming a gate structure, where the gate structure occupies at least a portion of the plurality of recessed cavities. |
| US10784364B2 |
Nanosheet with changing SiGe pecentage for SiGe lateral recess
A method for manufacturing a semiconductor device includes forming a stacked configuration of a plurality of silicon germanium layers and a plurality of silicon layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a silicon layer stacked on a silicon germanium layer, patterning the stacked configuration into a plurality of patterned stacks spaced apart from each other, and etching exposed sides of the plurality of silicon germanium layers to remove portions of the silicon germanium layers from lateral sides of each of the plurality of silicon germanium layers, wherein a concentration of germanium is varied between each of the plurality of silicon germanium layers to compensate for variations in etching rates between the plurality of silicon germanium layers to result in remaining portions of each of the plurality of silicon germanium layers having the same or substantially the same width as each other. |
| US10784362B2 |
Semiconductor device and manufacturing method thereof
In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. The first metallic film includes a oriented crystalline layer. |
| US10784359B2 |
Non-conformal oxide liner and manufacturing methods thereof
A method includes forming a fin protruding over a substrate; forming a conformal oxide layer over an upper surface and along sidewalls of the fin; performing an anisotropic oxide deposition or an anisotropic plasma treatment to form a non-conformal oxide layer over the upper surface and along the sidewalls of the fin; and forming a gate electrode over the fin, the conformal oxide layer and the non-conformal oxide layer being between the fin and the gate electrode. |
| US10784358B2 |
Backside contact structures and fabrication for metal on both sides of devices
An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device. |
| US10784355B2 |
Gate hole defect relieving method
A method for relieving a hole defect of a gate is disclosed, which includes: providing a substrate; forming a polysilicon layer over the substrate; forming a sacrificial oxide layer over a surface, that faces away from the substrate, of the polysilicon layer; forming a patterned photoresist layer over the sacrificial oxide layer; performing ion implantation by using the patterned photoresist layer as a mask; removing the patterned photoresist layer and the sacrificial oxide layer. In the method, before ion implantation, an oxide layer is formed over the surface of the gate, and is used to reduce affinity of the polysilicon and the photoresist layer. Afterwards, the floating gate is cleaned for many times, and hydrofluoric acid of an appropriate amount is added, so as to completely remove the photoresist layer and other residues while cleaning off the sacrificial oxide layer. |
| US10784354B2 |
Trenches for increasing a quantity of reliable chips produced from a wafer
A light-emitting device may comprise a set of layers comprising a substrate layer, and a set of epitaxial layers deposited on the substrate layer. The set of epitaxial layers may include a strained layer. The strained layer may include a set of active zones to be used to generate optical gain. The light-emitting device may comprise a set of trenches etched into a subset of the set of layers of the light-emitting device. The set of trenches may prevent a set of defects or dislocations in a wafer from which the light-emitting device was formed from propagating into the set of active zones. |
| US10784352B2 |
Method to achieve a uniform Group IV material layer in an aspect ratio trapping trench
Related fields of the present disclosure are in the field of transistor devices, and in particular, FinFET device structures formed using aspect ratio trapping trench (ART) process techniques. For example, a FinFET device consistent with the present disclosure comprises a first fin structure including a first upper fin portion atop a first lower fin portion and a second fin structure including a second upper fin portion atop a second lower fin portion. The first and second upper fin structures include a Group IV material and the first and second lower fin structures include a Group III-V material. |
| US10784348B2 |
Porous semiconductor handle substrate
An integrated circuit (IC) may include an active device layer on a front-side surface of a semiconductor device substrate. The IC may also include a front-side dielectric layer having a first surface opposite a second surface, the first surface contacting the active device layer. The IC may further include a porous semiconductor handle substrate contacting the second surface of the front-side dielectric layer. The porous semiconductor handle substrate may be uniformly doped. |
| US10784344B2 |
Semiconductor devices and methods of manufacturing the same
Semiconductor devices are provided. A semiconductor device includes a substrate and a gate structure on the substrate. The semiconductor device includes a channel on the substrate. The semiconductor device includes a source/drain layer on the channel. Moreover, the semiconductor device includes a spacer on a sidewall of the gate structure. The spacer includes a central portion overlapping the channel in a vertical direction, and a protrusion portion protruding from the central portion. Related methods of manufacturing semiconductor devices are also provided. |
| US10784343B2 |
Nanowire field effect transistor detection device and the detection method thereof
The present invention discloses a Nanowire Field Effect Transistor Detection Device and the Detection Method thereof. The Nanowire Field Effect Transistor Detection Device of the present invention comprises: gate oxide, SiNW chip, surface oxide, and surface molecule layer. The circuit structure of the Nanowire Field Effect Transistor Detection Device comprises a first resistor, a second resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, an AC voltage source, and an ammeter. In addition, the present invention provides a method for attaching the probe Ni-NTA to the Nanowire Field Effect Transistor Detection Device. Furthermore, the present invention provides a method for attaching the isooctyl trimethoxysilane molecule to the Nanowire Field Effect Transistor Detection Device. |
| US10784341B2 |
Castellated superjunction transistors
A transistor is provided that comprises a source region overlying a base structure, a drain region overlying the base structure, and a block of semiconducting material overlying the base structure and being disposed between the source region and the drain region. The block of semiconducting material comprises a gate controlled region adjacent the source region, and a drain access region disposed between the gate controlled region and the drain region. The drain access region is formed of a plurality of semiconducting material ridges spaced apart from one another by non-channel trench openings, wherein at least a portion of the non-channel trench openings being filled with a doped material to provide a depletion region to improve breakdown voltage of the transistor. |
| US10784338B2 |
Field effect transistor devices with buried well protection regions
A method of forming a transistor device includes providing a drift layer having a first conductivity type, forming a first region in the drift layer, the first region having a second conductivity type that is opposite the first conductivity type, forming a body layer on the drift layer including the first region, forming a source layer on the body layer, forming a trench in the source layer and the body layer above the first region and extending into the first region, forming a gate insulator on the inner sidewall of the trench, and forming a gate contact on the gate insulator. |
| US10784334B2 |
Method of manufacturing a capacitor
The present invention discloses a method of manufacturing a capacitor, which includes the steps of forming a capacitor recess in a sacrificial layer, wherein the sidewall of capacitor recess has a wave profile, forming a bottom electrode layer on the sidewall of capacitor recess, filling up the capacitor recess with a supporting layer, removing the sacrificial layer to forma capacitor pillar made up by the bottom electrode layer and the supporting layer, forming a capacitor dielectric layer on the capacitor pillar, and forming a top electrode layer on the capacitor dielectric layer. |
| US10784332B2 |
Methods for producing integrated circuits with magnets and a wet etchant for the same
Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a lower conductor element overlying a substrate, and forming a magnetic stack layer overlying the lower conductor element. A waste portion of the magnetic stack layer is removed with a wet etchant to produce a magnetic core. The wet etchant includes hydrofluoric acid, a second acid different than the hydrofluoric acid, an oxidizer, and a solvent. |
| US10784329B2 |
Display apparatus
A display apparatus includes: a thin-film transistor including a source electrode, a drain electrode, and a gate electrode; a data line in a layer different from the source electrode, the drain electrode, and the gate electrode, wherein the data line is configured to transmit a data signal; and a shield layer between the data line and a component of the thin-film transistor. |
| US10784319B2 |
Flexible display panel, flexible display device, and method for producing flexible display panel
An organic EL element including light emitting layers is formed above a first region of a main surface of a back film. A plurality of terminal portions are formed above a second region of the main surface of the back film. A cover film including an opening is provided as an uppermost layer above the main surface of the back film. |
| US10784314B2 |
Image sensor including color filters
The present invention relates to image sensors and method of manufacturing the same. The image sensor may include a substrate having pixel regions in which photoelectric-conversion devices and storage node regions spaced apart from each other; a lower contact via between the photoelectric conversion-devices in the pixel regions; a first insulating layer on the lower contact via and having an opening; an upper contact via electrically connected to the lower contact via through the first insulating layer and protruding from the first insulating layer; a second insulating layer surrounding the first insulating layer and the upper contact via, an upper surface of the second insulating layer in the opening defining a trench; a color filter filling the trench; a protective film exposing the upper contact via; a first transparent electrode on the protective film that contacts the upper contact via; and an organic photoelectric layer on the first transparent electrode. |
| US10784311B2 |
Three-dimensional semiconductor memory devices
A three-dimensional semiconductor memory device includes first to third cell array layers sequentially stacked on a substrate. Each of the first to third cell array layers includes memory cells arranged along first and second directions crossing each other and parallel to a top surface of the substrate. Each of the memory cells includes a variable resistance element and a tunnel field effect transistor connected in series. The device further includes bit lines extending along the first direction between the first and second cell array layers and at least one source line extending along either the first direction or the second direction between the second and third cell array layers. The memory cells of the first and second cell array layers share the bit lines, and the memory cells of the second and third cell array layers share the source line. |
| US10784308B2 |
Display device including light emitting diode and method of manufacturing the same
A display device including pixels respectively containing a plurality of subpixels, the display device comprises: a light emitting diode (LED) array including a plurality of LED cells, the plurality of LED cells provided in the plurality of subpixels, the plurality of LED cells configured to emit light having substantially the same wavelength, each of the plurality of LED cells having a first surface and a second surface; thin-film transistor (TFT) circuitry including a plurality of TFT cells, each of the plurality of TFT cells disposed on the first surface of an LED cell of the plurality of LED cells and including source and drain regions and a gate electrode disposed between the source and drain regions; a wavelength conversion pattern disposed on the second surface of an LED cell of the plurality of LED cells, the wavelength conversion pattern including a composite of a quantum dot and/or a polymer, the quantum dot configured to emit different colors of light from colors of light emitted from other quantum dots of other wavelength conversion patterns; and a light blocking wall disposed between two of the plurality of subpixels including the plurality of LED cells and between wavelength conversion patterns to separate the plurality of subpixels. |
| US10784307B2 |
Light-emitting device and method for manufacturing the same
A light-emitting device includes a substrate and a first light-emitting unit. The first light-emitting unit is disposed on the substrate, and includes a first semiconductor layer, a first light-emitting layer, and a second semiconductor layer. The first semiconductor layer is disposed on the substrate. The first light-emitting layer is disposed between the first semiconductor layer and the second semiconductor layer. The second semiconductor layer is disposed on the first light-emitting layer. The first semiconductor layer has a first sidewall and a second sidewall. A first angle is between the substrate and the first sidewall. A second angle is between the substrate and the second sidewall. The first angle is smaller than the second angle. |
| US10784305B2 |
X-ray detector substrate based on photodiodes with a radial pin junction structure
The present application discloses a photodiode structure including multiple light trapping elements. Each light trapping element includes an N-type silicon layer with a recessed structure therein, an intrinsic silicon layer disposed overlying the N-type silicon layer including a side region and a bottom region inside the recessed structure, and a P-type silicon layer disposed as an inner layer overlying the intrinsic silicon layer inside the recessed structure. A radial PIN junction is formed around a nominal axis of the recessed structure. |
| US10784304B2 |
Solid-state imaging apparatus, and electronic apparatus
Provided is a solid-state imaging apparatus that is formed so that, in a pixel array unit in which combinations of a first pixel corresponding to a color component of a plurality of color components and a second pixel having higher sensitivity to incident light as compared with the first pixel are two-dimensionally arrayed, a first electrical barrier formed between a first photoelectric conversion unit and a first unnecessary electric charge drain unit in the first pixel, and a second electrical barrier formed between a second photoelectric conversion unit and a second unnecessary electric charge drain unit in the second pixel have different heights, respectively. |
| US10784303B2 |
Method of manufacturing a CMOS image sensor
A CMOS image sensor includes a semiconductor substrate, a plurality of pixel regions in the semiconductor substrate, a deep trench disposed between two adjacent pixel regions and filled with a polysilicon layer doped a first conductivity type, a plurality of well regions having a second conductivity type in each of the pixel regions, a through hole connected to the polysilicon material, and an metal interconnect layer connected to the through hole. The deep trench filled with the doped polysilicon layer completely isolates adjacent pixel regions. A voltage applied to the metal interconnect layer extracts excess photoelectrons generated by intensive incident light to improve the performance of the CMOS image sensor. |
| US10784299B2 |
Photoelectric conversion apparatus and equipment
Provided is a photoelectric conversion apparatus including: an interlayer insulating film that covers a semiconductor layer and has a contact hole positioned above a gate electrode; a contact plug that is disposed in the contact hole and connected to the gate electrode; a light-shielding film that is positioned between the interlayer insulating film and the semiconductor layer and includes a first part covering a charge holding portion and a second part covering an upper surface of the gate electrode; and a dielectric layer that is positioned between the second part and the gate electrode, in which a relative dielectric constant of the dielectric layer is lower than a relative dielectric constant of the interlayer insulating film. |
| US10784297B2 |
Chip scale package structures
A chip scale package structure is provided. The chip scale package structure includes an image sensor chip and a chip. The image sensor chip includes a first redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the first redistribution layer. The chip includes a second redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the second redistribution layer. The area of the chip is smaller than that of the image sensor chip. The second redistribution layer of the chip bonds to the first redistribution layer of the image sensor chip. |
| US10784295B2 |
Image capturing apparatus and method for controlling temperature of a light transmitting element through controlling the optical element's exposure to and transmittance of light
An image capturing apparatus comprising: an optical element that changes a transmittance of light; an image sensor; an acquisition unit that acquires information regarding a temperature of the optical element; a first control unit that controls a transmittance of the optical element; and a second control unit that controls exposure when a subject is captured using the image sensor and an image signal is output. The first control unit performs control so as to increase a target transmittance of the optical element in a first condition under which a temperature of the optical element exceeds a predetermined temperature, based on the information regarding the temperature, and the second control unit controls exposure excluding the transmittance according to a change in the transmittance of the optical element in the first condition. |
| US10784294B2 |
Image sensor including multi-tap pixel
An image sensor includes unit pixels, and from among the unit pixels, a first unit pixel and a second unit pixel that are adjacent to each other each include a first tap having a first photo gate, to which a first signal having a first phase difference with respect to an optical signal is applied, and a second tap having a second photo gate, to which a second signal having a second phase difference with respect to the optical signal is applied. A location of the first tap in the first unit pixel and a location of the first tap in the second unit pixel, and a location of the second tap in the first unit pixel and a location of the second tap in the second unit pixel are symmetrical with each other based on one point between the first unit pixel and the second unit pixel. |
| US10784290B1 |
Method of manufacturing array substrate and array substrate
A method of manufacturing an array substrate and an array substrate are provided. The method of manufacturing the array substrate includes forming a first metal layer on a substrate, wherein the first metal layer includes a plurality of first metal lines and a plurality of intermittent second metal lines, forming an interlayer dielectric insulating layer on the substrate and the first metal layer, and forming an intermittent data line on the interlayer dielectric insulating layer and the first metal layer, wherein the intermittent data line contacts the two ends of each of the intermittent second metal lines through the via holes. |
| US10784285B2 |
Display device, display module, and electronic device
A novel display device or the like in which a transistor connected to a scan line has small gate capacitance is provided. A novel display device or the like in which a scan line has low resistance is provided. A novel display device or the like in which pixels can be arranged with high density is provided. A novel display device or the like that can be manufactured without an increase in cost is provided. In a transistor including a first gate electrode and a second gate electrode, the first gate electrode is formed using a metal material with low resistance and the second gate electrode is formed using a metal oxide material that can reduce oxygen vacancies in an oxide semiconductor layer. The first gate electrode is connected to the scan line, and the second gate electrode is connected to a wiring to which a constant potential is supplied. |
| US10784284B2 |
Semiconductor device and method for manufacturing the same
To provide a highly reliable semiconductor device that is suitable for miniaturization and an increase in density. The semiconductor device includes a first insulator over a substrate, a transistor including an oxide semiconductor over the first insulator, a second insulator over the transistor, and a third insulator over the second insulator. The first insulator and the third insulator have a barrier property with respect to oxygen and hydrogen. The second insulator includes an excess-oxygen region. The transistor is enclosed with the first insulator and the third insulator that are in contact with each other in an edge of a region where the transistor is positioned. |
| US10784283B2 |
Semiconductor memory device
A semiconductor memory device includes a stacked body, a semiconductor member, a charge storage member, a first member, and second members. The stacked body includes electrode films arranged to be separated from each other along a first direction. A terrace is formed for each electrode film in an end portion of the stacked body in a second direction. The first member spreads along the first direction and the second direction. The first member is provided inside the cell portion. The second members are provided inside the end portion. The electrode film includes two portions separated from each other in a third direction. The two portions are separated in the third direction by the first member and the plurality of second members. An insulator between the electrode films is formed continuously between two sides of the plurality of second members in the third direction. |
| US10784280B2 |
Semiconductor memory device
According to one embodiment, a semiconductor memory device includes the following structure. First conductive layers are stacked in first direction and extends in second and third directions. The first conductive layers each includes a pair of first portions, and second and third portions. The first portions extend in second direction, is provided separately from each other in third direction and includes a metal. The second portion is provided between the first portions and includes silicon. The third portion is provided on at least one side of the second portion in second direction, extends in third direction, electrically connects the first portions and includes a metal. Memory pillars extend through the second portions in first direction. Contact plugs are respectively provided on the third portion of one of the first conductive layers. |
| US10784277B2 |
Integration of a memory transistor into High-k, metal gate CMOS process flow
A memory device that includes a non-volatile memory (NVM) transistor disposed in a first region of a substrate. The NVM transistor includes a first gate including a first type of conductor material. The memory device further includes a first type of low voltage field-effect transistor (LV FET) and an input/out field-effect transistor (I/O FET) disposed in a second region of the substrate. The LV FET includes a second gate comprising a second type of conductor material, the I/O FET includes a third gate comprising a second type of conductor material, and the first and second conductor materials are different. Other embodiments are also described. |
| US10784273B2 |
Memory arrays and methods used in forming a memory array
A method used in forming a memory array comprises forming a substrate comprising a conductive tier, a first insulator tier above the conductive tier, a sacrificial material tier above the first insulator tier, and a second insulator tier above the sacrificial material tier. A stack comprising vertically-alternating insulative tiers and wordline tiers is formed above the second insulator tier. Channel material is formed through the insulative tiers and the wordline tier. Horizontally-elongated trenches are formed through the stack to the sacrificial material tier. Sacrificial material is etched through the horizontally-elongated trenches selectively relative to material of the first insulator tier and selectively relative to material of the second insulator tier. A laterally-outer sidewall of the channel material is exposed in the sacrificial material tier. A conductive structure is formed directly against the laterally-outer sidewall of the channel material in the sacrificial material tier. The conductive structure extends through the first insulator tier and directly electrically couples the channel material to the conductive tier. Structure embodiments are disclosed. |
| US10784269B2 |
Memory device including pass transistors in memory tiers
Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes a semiconductor material, a pillar extending through the semiconductor material, a select gate located along a first portion of the pillar, memory cells located along a second portion of the pillar, and transistors coupled to the select gate through a portion of the semiconductor material. The transistors include sources and drains formed from portions of the semiconductor material. The transistors include gates that are electrically uncoupled to each other. |
| US10784268B1 |
OTP elements with high aspect ratio MTJ
A magnetic tunnel junction (MTJ) containing device and methods of constructing the MTJ containing device are described. In an example, the MTJ containing device may be a memory element including a bottom electrode structure, a MTJ pillar, and a top electrode structure located on the MTJ pillar. The MTJ pillar has a non-circular lateral cross section, where the MTJ pillar has a bottommost portion forming an interface with an uppermost portion of the bottom electrode structure. The MTJ pillar has a lateral perimeter-to-area ratio that defines a breakdown voltage of the MTJ pillar. |
| US10784259B2 |
Semiconductor device and method of manufacturing the same
Provided is a semiconductor device including a substrate, an isolation structure, a barrier structure, a first conductive layer, a second conductive layer, a first gate dielectric layer, and a second gate dielectric layer. The substrate has a first region and a second region. The barrier structure is located on the isolation structure. The first conductive layer is located on the first region. The second conductive layer is located on the second region. The first gate dielectric layer is located between the first conductive layer and the substrate in the first region. The second gate dielectric layer is located between the second conductive layer and the substrate in the second region. The first gate dielectric layer and the second gate dielectric layer are separated by the isolation structure. A method of manufacturing the semiconductor device is also provided. |
| US10784258B2 |
Selective contact etch for unmerged epitaxial source/drain regions
A semiconductor structure includes a plurality of semiconductor material fins located on a surface of a substrate. At least one gate structure straddles over a portion of each semiconductor material fin. Unmerged source-side epitaxial semiconductor material portions are located on an exposed surfaces of each semiconductor material fin and on one side of each gate structure and unmerged drain-side epitaxial semiconductor portions are located on other exposed surfaces of each semiconductor material fin and on another side of each gate structure. An etch stop structure is located between each unmerged source-side and drain-side epitaxial semiconductor material portions. Each etch stop structure includes a bottom material portion that has a higher etch resistance in a specific etchant as compared to an upper material portion of the etch stop structure. |
| US10784256B2 |
Semiconductor device and method of manufacturing semiconductor device
A semiconductor device includes a plurality of semiconductor switching elements disposed on a single semiconductor substrate comprising a semiconductor having a bandgap that is wider than that of silicon; and a plurality of electrode pads that are disposed in a predetermined planar layout on a front surface of the semiconductor substrate, the plurality of electrode pads each being electrically connected to the plurality of semiconductor switching elements. A plurality of terminal pins to externally carry out voltage of the electrode pads is bonded through a plated film to all of the plurality of electrode pads by solder. |
| US10784255B2 |
Diode having a plate-shaped semiconductor element
A diode is provided having a plate-shaped semiconductor element that includes a first side and a second side, the first side being connected by a first connecting layer to a first metallic contact and the second side being connected by a second connecting layer to a second metallic contact, the first side having a diode element in a middle area and having a further diode element in an edge area of the first side, which has crystal defects as a result of a separating process of the plate-shaped semiconductor element, the first connecting layer only establishing an electrical contact to the diode element and not to the further diode element and, on the first side, the further diode element having an exposed contact, which may be electrically contacted by the first connecting layer. |
| US10784252B2 |
Electrostatic discharge protection circuit
An ESD protection circuit, which protects a subject NMOS transistor coupled between an I/O pad and a ground, includes a first discharge device arranged between the I/O pad and the ground, having a trigger-on voltage that is lower than a breakdown voltage of the subject NMOS transistor; and a gate voltage control device, including a discharge NMOS transistor coupled to the ground and a gate of the subject NMOS transistor; a first PMOS transistor connected to the gate of the subject NMOS transistor and a connection node; and a first NMOS transistor connected to the connection node and the ground. The connection node is connected to the gate of the discharge NMOS transistor, and the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to each other. |
| US10784251B2 |
Internally stacked NPN with segmented collector
An integrated circuit includes a plurality of first n-type regions and a plurality of second n-type regions that each intersect a surface of a substrate. The first n-type regions are arranged in a first linear array within a first n-well and a second linear array within a second n-well. The first and second n-wells are each located within and separated by a first p-type region. The second n-type regions are located within and separated by a second p-type region. An n-type trench region is located between the first and second p-type regions. The n-type trench region extends into the substrate toward an n-type buried layer that extends under the first p-type region and the second p-type region. |
| US10784249B2 |
Integrated circuit and layout design method
According to one embodiment, there is provided an integrated circuit including a circuit provided with terminals, a plurality of circuit blocks provided with terminals, and a plurality of wirings that run in parallel from the terminals of the circuit toward the circuit blocks and each turns in mid-course toward a position at which a terminal of a corresponding circuit block exists to connect to the terminal of the corresponding circuit block, any adjacent wirings at the terminals of the circuit being connected to different circuit blocks. |
| US10784245B2 |
Highly integrated RF power and power conversion based on Ga2O3 technology
An integrated circuit is provided including a first substrate with a first thermal conductivity. An active layer is deposited on the first substrate. At least one native device is fabricated on the active layer. A window is formed in the active layer, which exposes a portion of the first substrate. A non-native device is fabricated on a second substrate with a second thermal conductivity lower than the first thermal conductivity. The non-native device is flip-chip mounted in the widow on the first substrate and electrically connected to the at least one native device. The non-native device is also thermally connected to the first substrate such that heat generated by the non-native device is removed through the first substrate. |
| US10784243B2 |
Uniplanar (single layer) passive circuitry
The present disclosure relates to semiconductor structures and, more particularly, to uniplanar (e.g., single layer) passive circuitry and methods of manufacture. The structure includes: passive circuitry comprising plural components each of which are formed on a same wiring level; and interconnects on the same wiring level connecting the plural components of the passive circuitry. |
| US10784241B2 |
Method of manufacturing micro-LED array display devices with CMOS cells
Micro-LED array display devices are disclosed. One of the micro-LED display devices includes: a micro-LED panel including a plurality of micro-LED pixels; a CMOS backplane including a plurality of CMOS cells corresponding to the micro-LED pixels to individually drive the micro-LED pixels; and bumps electrically connecting the micro-LED pixels to the corresponding CMOS cells in a state in which the micro-LED pixels are arranged to face the CMOS cells. The micro-LED pixels are flip-chip bonded to the corresponding CMOS cells formed on the CMOS backplane through the bumps so that the micro-LED pixels are individually controlled. |
| US10784240B2 |
Light emitting device with LED stack for display and display apparatus having the same
A light emitting diode pixel for a display includes a first subpixel, a second subpixel, and a third subpixel, each of the first, second, and third subpixels including a first LED sub-unit including a first type of semiconductor layer and a second type of semiconductor layer, a second LED sub-unit disposed on the first LED sub-unit and including a first type of semiconductor layer and a second type of semiconductor layer, and a third LED sub-unit disposed on the second LED sub-unit and including a first type of semiconductor layer and a second type of semiconductor layer, in which the second and third LED sub-units of the first subpixel are electrically floated, the first and third LED sub-units of the second subpixel are electrically floated, and the first and second LED sub-units of the third subpixel are electrically floated. |
| US10784239B2 |
Light emitting diode package and light emitting diode module
A light emitting diode package including a housing, first and second light emitting diode chips disposed in the housing, and a wavelength conversion part including a phosphor to absorb light emitted from the first light emitting diode chip and emit light having a different wavelength than that emitted from the first light emitting diode chip, in which light emitted from the first light emitting diode chip has a shorter wavelength than light emitted from the second light emitting diode chip, the wavelength conversion part is configured to emit red light having a peak wavelength of 580 nm to 700 nm and exhibiting at least three peaks at a wavelength of 600 nm to 660 nm, and the light emitting diode package is configured to emit white light by mixing light emitted from the first light emitting diode chip, the second light emitting diode chip, and the wavelength conversion part. |
| US10784238B2 |
Display device including sub-pixel units of the same color type and different luminous areas
Disclosed are an epitaxial wafer and a display device that includes a display substrate, a first sub pixel unit and a second sub pixel unit. The first sub pixel unit has a first luminous area, and the second sub pixel unit has a second luminous area different from the first luminous area. The first sub pixel unit and the second sub pixel unit belong to the same color type and are located in different pixel units. The first sub pixel unit is a sub epitaxial structure emitting light within a first photoluminescent wavelength, the second sub pixel unit is a sub epitaxial structure emitting light within a second photoluminescent wavelength, and the first photoluminescent wavelength is different from the second photoluminescent wavelength. The difference between electroluminescent wavelengths of the first sub pixel unit and the second sub pixel unit is less than or equal to 2 nm. |
| US10784237B1 |
Method for fabricating an emissive display
In a method for fabricating an emissive display, a package substrate with a top thereof having a plurality of wells is firstly provided. The well has a first electrode region and a second electrode region at different heights. The package substrate sinks in a suspension. Then, a plurality of light-emitting diodes sinks in the suspension. The light-emitting diode has a plane and a curved surface. Finally, the suspension horizontally jets such that the suspension flows across the plane and the curved surface of the light-emitting diode at different velocities. According to the different velocities, the suspension respectively embeds all the light-emitting diodes into all the wells. Each of the plurality of light-emitting diodes are respectively electrically connected to the first electrode region and the second electrode region of a corresponding one of the plurality of wells, thereby forming an emissive display. |
| US10784226B2 |
Semiconductor device
A semiconductor device includes an insulative substrate, a wiring pattern, a bonding portion, and a semiconductor element. The wiring pattern is formed on an upper surface of the insulative substrate. The bonding portion is formed on an upper surface of the wiring pattern. The semiconductor element includes an electrode pad connected to an upper surface of the bonding portion. The bonding portion includes first sintered layers distributed in the bonding portion and a second sintered layer having a density differing from each of the first sintered layers and surrounding the first sintered layer. |
| US10784220B2 |
Plurality of semiconductor devices encapsulated by a molding material attached to a redistribution layer
A package structure includes a first dielectric layer, a first semiconductor device, a first redistribution line, a second dielectric layer, a second semiconductor device, a second redistribution line, a first conductive feature, and a first molding material. The first semiconductor device is over the first dielectric layer. The first redistribution line is in the first dielectric layer and is electrically connected to the first semiconductor device. The second dielectric layer is over the first semiconductor device. The second semiconductor device is over the second dielectric layer. The second redistribution line is in the second dielectric layer and is electrically connected to the second semiconductor device. The first conductive feature electrically connects the first redistribution line and the second redistribution line. The first molding material molds the first semiconductor device and the first conductive feature. |
| US10784214B2 |
Semiconductor module, electric automobile and power control unit
A semiconductor module includes: a first lead frame connected to a plurality of semiconductor chips in a first arm circuit; a second lead frame connected to a plurality of semiconductor chips in a second arm circuit; a first main terminal connected to the first lead frame; and a second main terminal connected to the second lead frame, wherein each of the first lead frame and second lead frame has a facing part, a first terminal connection portion connected to the first main terminal is provided at a first end portion of the first lead frame, a second terminal connection portion connected to the second main terminal is provided at a second end portion of the second lead frame, and the first terminal connection portion and second terminal connection portion are arranged on opposite sides when viewed from the facing parts of the first lead frame and second lead frame. |
| US10784213B2 |
Power device package
A power device package includes a substrate, a high side power device, a low side power device and a driver device. The substrate includes a top surface, a bottom surface and a plurality of vias that extend through the substrate. The high side and low side power devices are disposed on the top surface of the substrate and connected with each other. The driver device is disposed on the bottom surface of the substrate and electrically connected with the high side and low side power devices through the vias to drive the high side and low side power devices in response to a control signal. The distance between the driver device and the high side and low side power devices is determined by the thickness of the substrate such that that a parasitic inductance between the driver device and the high side power device or the low side power device is reduced. |
| US10784211B2 |
Semiconductor package structure
A semiconductor package structure is provided. The semiconductor package structure includes a substrate having a first surface and a second surface opposite thereto. The substrate includes a wiring structure. The semiconductor package structure also includes a first semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure. The semiconductor package structure further includes a second semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure. The first semiconductor die and the second semiconductor die are separated by a molding material. In addition, the semiconductor package structure includes a first hole and a second hole formed on the second surface of the substrate. |
| US10784206B2 |
Semiconductor package
A semiconductor package includes a first substrate, a first layer structure, a second layer structure and a first antenna layer. The first antenna layer is formed on at least one of the first layer structure and the second layer structure. The first layer structure is formed between the first substrate and the second layer structure. |
| US10784201B2 |
Method of forming stacked trench contacts and structures formed thereby
Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate. |
| US10784200B2 |
Ionizing radiation blocking in IC chip to reduce soft errors
Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip. |
| US10784197B2 |
Method and structure to construct cylindrical interconnects to reduce resistance
A method for manufacturing a semiconductor device includes forming a plurality of trenches in a dielectric layer, wherein the plurality of trenches each comprise a rounded surface, depositing a liner layer on the rounded surface of each of plurality of trenches, and depositing a conductive layer on the liner layer in each of the plurality of trenches, wherein the conductive layer and the liner layer form a plurality of interconnects, and each of the plurality of interconnects has a cylindrical shape. |
| US10784192B2 |
Semiconductor devices having 3-dimensional inductive structures
Semiconductor devices having inductive structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a substrate and at least one circuit component coupled to the substrate. The semiconductor device can further include an inductive structure carried by the substrate and having a stack of alternating first and second layers. In some embodiments, the first layers comprise an oxide material and the second layers each include a coil of conductive material. The coils of conductive material can be electrically coupled (a) together to form an inductor and (b) to the at least one circuit component. |
| US10784187B2 |
Array substrate, chip on film, display panel and display device
Provided are an array substrate, a chip on film, a display panel and a display device. The array substrate has a display area and a bonding area located in a periphery of the display area. The array substrate includes a plurality of first bonding pads located in the bonding area, and length directions of the first bonding pads face the display area. |
| US10784186B2 |
Semiconductor module
A semiconductor module includes a die pad frame; a semiconductor chip disposed in a chip region on an upper surface of the die pad frame, the semiconductor chip having an upper surface on which a first electrode is disposed and a lower surface on which a second electrode is disposed; a conductive connection member for die pad disposed between the second electrode of the semiconductor chip and the upper surface of the die pad frame, the conductive connection member for die pad electrically connecting the second electrode of the semiconductor chip and the upper surface of the die pad frame; a first clip frame disposed on the upper surface of the semiconductor chip; a first clip conductive connection member disposed between the first electrode on the semiconductor chip and a lower surface of the first clip frame, the first clip conductive connection member electrically connecting the first electrode of the semiconductor chip and the lower surface of the first clip frame; and a sealing resin for sealing the semiconductor chip, the die pad frame, the first clip frame, the first clip conductive connection member, and the conductive connection member for die pad. |
| US10784185B2 |
Method for manufacturing semiconductor device with through silicon via structure
A semiconductor device includes at least one wafer and at least one TSV (through silicon via) structure. The at least one wafer each includes a substrate, an isolation structure, and a conductive pad. The isolation structure is formed in the substrate and extends from a first side of the substrate toward a second side opposite to the first side of the substrate. The conductive pad is formed at a dielectric layer disposed on the first side of the substrate, wherein the conductive pad is electrically connected to an active area in the substrate. The at least one TSV structure penetrates the at least one wafer. The conductive pad contacts a sidewall of the at least one TSV structure, and electrically connects the at least one TSV structure and the active area in the substrate. The isolation structure separates from and surrounds the at least one TSV structure. |
| US10784183B2 |
Semiconductor module with package extension frames
A semiconductor package includes a semiconductor module, a first package extension frame, a second package extension frame, and a plurality of fasteners. The semiconductor module includes a first side surface, a second side surface, a first major surface, and a second major surface on an opposite side of the semiconductor module from the first major surface. The first package extension frame is configured to attach to the first side surface. The second package extension frame is configured to attach to the second side surface. The plurality of fasteners are configured to mechanically couple the first package extension frame and the second package extension frame to one or more of a circuit board arranged on the first major surface and/or a heat sink arranged on the second major surface. |
| US10784182B2 |
Bonded substrate and method for manufacturing bonded substrate
Provided is a bonded substrate mainly for mounting a power semiconductor in which the reliability to a thermal cycle has been enhanced as compared with a conventional one. In a bonded substrate in which a copper plate is bonded to one or both main surface(s) of a nitride ceramic substrate, a bonding layer consisting of TiN intervenes between the nitride ceramic substrate and the copper plate and is adjacent at least to the copper plate, and an Ag distribution region in which Ag atoms are distributed is set to be present in the copper plate. Preferably, an Ag-rich phase is set to be present discretely at an interface between the bonding layer and the copper plate. |
| US10784178B2 |
Wafer-level stack chip package and method of manufacturing the same
A semiconductor product in the form of a stack chip package and a method of manufacturing the same, where a plurality of semiconductor chips are stacked one on another so as to enable the exchange of electrical signals between the semiconductor chips, and where a conductive layer is included for inputting and outputting signals to and from individual chips. A stack chip package having a compact size may, for example, be manufactured by stacking, on a first semiconductor chip, a second semiconductor chip having a smaller surface area by means of interconnection structures so as to enable the exchange of electrical signals between the first and second semiconductor chips, and by using a conductive layer for inputting and outputting signals to and from individual semiconductor chips, in lieu of a thick substrate. Furthermore, heat dissipation effects can be enhanced by the addition of a heat dissipation unit. |
| US10784177B2 |
Semiconductor device with encapsulating resin
A semiconductor device includes an interconnect substrate having a plurality of pads formed on a first surface thereof, a semiconductor chip having a plurality of electrodes formed on a circuit surface thereof, the semiconductor chip being mounted on the interconnect substrate such that the circuit surface faces the first surface, a plurality of bonding members that are made of a same material and that electrically couple the pads and the electrodes, and a resin disposed on the first surface to encapsulate the semiconductor chip and to fill a gap between the circuit surface and the first surface, wherein the semiconductor chip is mounted on the interconnect substrate such that the gap between the circuit surface and the first surface progressively increases from a first side to a second side. |
| US10784172B2 |
Testing solid state devices before completing manufacture
In some examples, a method for manufacturing a solid state device comprises forming a first layer of the solid state device; forming a conductive layer of the solid state device above the first layer, the conductive layer having an access pad formed on an end of the conductive layer; applying a voltage to the conductive layer using the access pad, the voltage forming an electric field in an area of the first layer beneath the conductive layer; and completing manufacture of the solid state device after applying the voltage. |
| US10784169B2 |
Self-aligned hard mask for epitaxy protection
A method includes isolating a first and at least a second region on a semiconductor substrate, and forming one or more devices on each of the first and at least second regions. Forming the one or more devices includes forming at least one gate structures in each of the first and at least second regions on a first surface of the substrate, depositing a spacer over the gate structures in each of the first and the at least second regions and over the first surface of the substrate, etching horizontal portions of the spacer in the first region, growing epitaxial portions in the first region in alignment with said at least one gate structure in the first region, oxidizing exposed surfaces of the epitaxial portions in the first region, and repeating the etching, growing and oxidizing steps for the at least second region. |
| US10784166B2 |
Wafer processing method
A wafer processing method includes the following steps: forming, on a back side of a wafer including a device layer, a mask to be used in forming grooves in a substrate along streets from the back side of the wafer; applying plasma etching from the back side of the wafer through the mask to form the grooves in the substrate along the streets; ejecting high-pressure fluid against the back side of the wafer with the wafer mounted at its front side on a mounting surface to press the wafer at regions surrounded by the etched grooves; and bonding a tape to the front side of the wafer before performance of at least the pressing step. |
| US10784165B2 |
Semiconductor device and dicing method
According to an embodiment, a semiconductor device includes a silicon substrate, a device layer, and a lower layer. The device layer is formed on an upper surface of the silicon substrate. The lower layer is formed on a lower surface of the silicon substrate and has a side surface connecting to a side surface of the silicon substrate. At least a pair of side surfaces of the semiconductor device has a curved shape widening from an upper side toward a lower side. |
| US10784161B2 |
Semiconductor chip including self-aligned, back-side conductive layer and method for making the same
A method for manufacturing a semiconductor device includes: partially dicing a substrate wafer arrangement having a plurality of semiconductor chips, wherein the partial dicing forms trenches around the semiconductor chips on a front-side of the substrate wafer arrangement, the depth being greater than a target thickness of a semiconductor chip; filling the trenches with a polymer material to form a polymer structure; first thinning of the back-side to expose portions of the polymer structure; forming a conductive layer on the back-side of the substrate wafer arrangement so that the exposed portions of the polymer structure are covered; second thinning of the back-side to form insular islands of conductive material, the insular islands separated from each other by the polymer structure, each insular island corresponding to a respective one of the semiconductor chips; and dicing the substrate wafer arrangement along the polymer structure. |
| US10784159B2 |
Semiconductor device and method of forming the semiconductor device
A semiconductor device includes a first dielectric layer including a first contact hole, a second dielectric layer formed on the first dielectric layer, and including a second contact hole aligned with the first contact hole, and a reflowed copper layer formed in the first and second contact holes. |
| US10784154B2 |
Double spacer immersion lithography triple patterning flow and method
A system and method for fabricating metal patterns are described. Multiple mandrels are formed on a first polysilicon layer which is on top of a first oxide layer. Each mandrel uses a second polysilicon on top of a first nitride. A spacer oxide and a spacer nitride are formed on the sidewalls of the mandrels to create double spacers. A second oxide layer is deposited followed by removing layers until the first nitride in the mandrels is reached. Areas are etched based on a selected method of multiple available methods until the first oxide layer is etched providing trenches for the metal patterns. Remaining materials on the first oxide layer are removed followed by metal being deposited in the trenches in the first oxide layer. |
| US10784150B2 |
Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a semiconductive substrate including a first surface and a second surface opposite to the first surface, a shallow trench isolation (STI) including a first portion at least partially disposed within the semiconductive substrate and tapered from the first surface towards the second surface, and a second portion disposed inside the semiconductive substrate, coupled with the first portion and extended from the first portion towards the second surface, and a void enclosed by the STI, wherein the void is at least partially disposed within the second portion of the STI. |
| US10784149B2 |
Air-cavity module with enhanced device isolation
The present disclosure relates to an air-cavity module having a thinned semiconductor die and a mold compound. The thinned semiconductor die includes a back-end-of-line (BEOL) layer, an epitaxial layer over the BEOL layer, and a buried oxide (BOX) layer with discrete holes over the epitaxial layer. The epitaxial layer includes an air-cavity, a first device section, and a second device section. Herein, the air-cavity is in between the first device section and the second device section and directly in connection with each discrete hole in the BOX layer. The mold compound resides directly over at least a portion of the BOX layer, within which the discrete holes are located. The mold compound does not enter into the air-cavity through the discrete holes. |
| US10784146B2 |
Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress
A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, a textured oxide, nitride, or oxynitride layer, a polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer. The multilayer structure is prepared in a manner that reduces wafer bow. |
| US10784140B2 |
Electronic device comprising a die comprising a high electron mobility transistor
An electronic device can include a semiconductor material and a semiconductor layer overlying the semiconductor material, wherein the semiconductor layer has a greater bandgap energy as compared to the semiconductor material. The electronic device can include a component having a high electrical field region and a low electrical field region. Within the high electrical field region, the semiconductor material is not present. In another embodiment, the component may not be present. In another aspect, a process can include providing a substrate and a semiconductor layer overlying the substrate; removing a first portion of the substrate to define a first trench; forming a first insulating layer within the first trench; removing a second portion of the substrate adjacent to first insulating layer to define second trench; and forming a second insulating layer within the second trench. |
| US10784138B2 |
Substrate processing system and substrate transfer method
There is provided a substrate processing system, including: a carrier transfer region in which a carrier that accommodates a substrate is transferred to a substrate processing apparatus, and a substrate transfer region in which the substrate accommodated in the carrier is transferred to a processing furnace, the substrate transfer region being partitioned from the carrier transfer region by a partition wall; a transfer port formed in the partition wall and through which the substrate is transferred between the carrier transfer region and the substrate transfer region; an opening/closing door configured to open and close the transfer port; and a pressure equalizing part configured to substantially equalize a pressure of the substrate transfer region and a pressure of a space surrounded by the carrier and the opening/closing door. |
| US10784135B2 |
Substrate container with improved substrate retainer and door latch assist mechanism
A substrate container with a substrate retainer mounted to a biased actuation linkage, and a door assembly with latch assist. Various configurations for biasing the substrate retainer in a substrate non-engagement position are disclosed. The biasing helps prevent the substrate retainer from hanging up due to friction that might otherwise counter the gravitational force that is otherwise relied upon for disengagement. The assembly may also include retention clips that positively secure the substrate retainer to the actuation linkage. The latch assist provides springs that deliver stored energy to assist in latching and unlatching the door assembly from the substrate carrier. The latch assist further provides off-center forces that bias the latching mechanism in either an unlatched or a fully latched configuration. |
| US10784133B2 |
Wafer clamp and a method of clamping a wafer
A wafer clamp includes a platform with a top surface, a stopper disposed at a front end of the platform, a push rod disposed at a rear end of the platform, at least one actuator pivotally connected to the push rod, and a sensor disposed at the front end of the platform, the sensor measuring a distance between the sensor and a wafer over the sensor. |
| US10784132B2 |
Method and apparatus for de-chucking a workpiece using a swing voltage sequence
A method and apparatus for de-chucking a workpiece is described that uses a swing voltage sequence. One example pertains to a method that includes applying a mechanical force from an electrostatic chuck against the back side of a workpiece that is electrostatically clamped to the chuck, applying a sequence of voltage pulses with a same polarity to the electrodes, each pulse of the sequence having a lower voltage than the preceding pulse, each pulse of the sequence having a lower voltage than the preceding pulse, and determining whether the workpiece is released from the chuck after the sequence of additional voltage pulses and if the workpiece is not released then repeating applying the sequence of voltage pulses. |
| US10784131B2 |
EFEM, equipment front end module
Disclosed is an equipment front end module (EFEM) in which wafer transfer is conducted between a wafer storage device where a wafer is stored and a process chamber. In addition, the EFEM generates gas flow in a wafer transfer chamber. |
| US10784130B2 |
Bonding apparatus
A bonding apparatus includes a stage supporting a substrate, a first bonding head at a first side of the stage, the first bonding head to pick up a first chip and to bond the picked-up first chip onto the substrate, a second bonding head at a second side of the stage, the second bonding head to pick up a second chip and to bond the picked-up second chip onto the substrate, and a first image acquisition unit over a movement path of the stage to acquire an image of the stage. |
| US10784129B2 |
Mounting device and mounting method
A mounting device in which a loading distance separating adjacent characteristic components are lined up side by side is shorter than separation distance between suction nozzle and mark camera, processing to image characteristic component by mark camera and recognize the position of characteristic component is performed consecutively or in one batch. With the mounting device, because mounting head is moved a loading distance that is shorter than the separation distance between suction nozzle and mark camera and image processing is performed consecutively or in one batch, the movement distance of mounting head is shorter. |
| US10784122B2 |
Method of producing electroconductive substrate, electronic device and display device
A method of producing an electroconductive substrate including a base material, and an electroconductive pattern disposed on one main surface side of the base material includes: a step of forming a trench including a bottom surface to which a foundation layer is exposed, and a lateral surface which includes a surface of a trench formation layer, according to an imprint method; and a step of forming an electroconductive pattern layer by growing metal plating from the foundation layer which is exposed to the bottom surface of the trench. |
| US10784120B2 |
Laminate, etching mask, method of producing laminate, method of producing etching mask, and method of producing thin film transistor
A laminate by using a paste or solution containing aliphatic polycarbonates having an etching mask function is provided. A method of producing a laminate of the present invention includes a pattern forming step of forming a pattern 80 of a first oxide precursor layer in which a compound of metal to be oxidized into a metal oxide is dispersed in a solution containing a binder (possibly including inevitable impurities) made of aliphatic polycarbonates on an oxide layer 44 or on the second oxide precursor layer to be oxidized into the oxide layer 44; an etching step of, after the pattern forming step, etching the oxide layer 44 or the second oxide precursor layer that is not protected by the pattern 80; and a heating step of, after the etching step, heating the oxide layer 44 or the second oxide precursor layer, and the first oxide precursor layer to a temperature at which the binder is decomposed or higher. |
| US10784118B2 |
Atomic layer etching using a combination of plasma and vapor treatments
A method for performing atomic layer etching (ALE) on a substrate, including the following method operations: performing a surface modification operation on a surface of the substrate, the surface modification operation configured to convert at least one monolayer of the substrate surface to a modified layer; performing a removal operation on the substrate surface, to remove the modified layer from the substrate surface, wherein removing the modified layer includes exposing the substrate surface to a metal complex, such that a ligand exchange reaction occurs between the metal complex and converted species of the modified layer; performing, following the removal operation, a plasma treatment on the substrate surface, the plasma treatment configured to remove residues formed from the exposure of the substrate surface to the metal complex, wherein the residues are volatilized by the plasma treatment; repeating the foregoing operations until a predefined thickness has been etched from the substrate surface. |
| US10784116B2 |
Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
There is provided a technique that includes: (a) providing a substrate having a film containing a predetermined element, oxygen and carbon formed on a surface of the substrate; and (b) modifying at least a surface of the film by supplying a carbon-free fluorine-based gas to the substrate under a condition in which etching of the film does not occur. |
| US10784115B2 |
Method of etching microelectronic mechanical system features in a silicon wafer
A method of etching features in a silicon wafer includes coating a top surface and a bottom surface of the silicon wafer with a mask layer having a lower etch rate than an etch rate of the silicon wafer, removing one or more portions of the mask layer to form a mask pattern in the mask layer on the top surface and the bottom surface of the silicon wafer, etching one or more top surface features into the top surface of the silicon wafer through the mask pattern to a depth plane located between the top surface and the bottom surface of the silicon wafer at a depth from the top surface, coating the top surface and the one or more top surface features with a metallic coating, and etching one or more bottom surface features into the bottom surface of the silicon wafer through the mask pattern to the target depth plane. |
| US10784113B2 |
Chemical mechanical polishing apparatus
Provided are a chemical mechanical polishing apparatus and a control method thereof. The chemical mechanical polishing apparatus includes a plurality of polishing platens provided with a polishing pad on an upper surface thereof, and a polishing platen transferring unit for transferring the plurality of polishing platens to different process positions according to a predetermined process sequence. Here, different processes are performed at different process positions. |
| US10784110B2 |
Tungsten film forming method, film forming system and film forming apparatus
A tungsten film forming method in which a substrate having a TiN film formed thereon is disposed in a processing container and a tungsten film is formed above a surface of the substrate while heating the substrate in a reduced pressure atmosphere, includes forming a first film of an aluminum-containing material on the substrate and forming the tungsten film on the first film. |
| US10784109B2 |
Semiconductor device
A semiconductor device includes a semiconductor layer and a metal electrode. The metal electrode is provided on the semiconductor layer. The metal electrode includes first to third metal regions. The first metal region contacts the semiconductor layer and includes a first metal element as a main component. The second metal region is provided on the first metal region and includes a second metal element as a main component. The third metal region is provided on the second metal region. The third metal region has a thickness in a first direction directed from the semiconductor layer toward the second metal region. The thickness of the third metal region is larger than a total thickness in the first direction of the first metal region and the second metal region. The second metal element has a standard free energy of oxide generation larger than that of the first metal element. |
| US10784108B2 |
Method for forming a functionalised assembly guide
A method for forming a functionalised assembly guide intended for the self-assembly of a block copolymer by graphoepitaxy, includes forming on the surface of a substrate a neutralisation layer made of a first material having a first neutral chemical affinity with regard to the block copolymer; forming on the neutralisation layer a first mask including at least one recess; depositing on the neutralisation layer a second material having a second preferential chemical affinity for one of the copolymer blocks, in such a way as to fill the at least one recess of the first mask; and selectively etching the first mask relative to the first and second materials, thereby forming at least one guide pattern made of the second material arranged on the neutralisation layer. |
| US10784107B2 |
Methods of forming tungsten pillars
Methods of forming self-aligned patterns are described. A film material is deposited on a patterned film to fill and cover features formed by the patterned film. The film material is recessed to a level below the top of the patterned film. The recessed film is converted to a metal film by exposure to a metal precursor followed by volumetric expansion of the metal film. |
| US10784106B2 |
Selective film growth for bottom-up gap filling
A method includes etching a portion of a semiconductor material between isolation regions to form a trench, forming a semiconductor seed layer extending on a bottom surface and sidewalls of the trench, etching-back the first semiconductor seed layer until a top surface of the semiconductor seed layer is lower than top surfaces of the isolation regions, performing a selective epitaxy to grow a semiconductor region from the semiconductor seed layer, and forming an additional semiconductor region over the semiconductor region to fill the trench. |
| US10784105B2 |
Methods for forming doped silicon oxide thin films
The present disclosure relates to the deposition of dopant films, such as doped silicon oxide films, by atomic layer deposition processes. In some embodiments, a substrate in a reaction space is contacted with pulses of a silicon precursor and a dopant precursor, such that the silicon precursor and dopant precursor adsorb on the substrate surface. Oxygen plasma is used to convert the adsorbed silicon precursor and dopant precursor to doped silicon oxide. |
| US10784104B2 |
Interfacial control of oxygen vacancy doping and electrical conduction in thin film oxide heterostructures
Systems and methods of reversibly controlling the oxygen vacancy concentration and distribution in oxide heterostructures consisting of electronically conducting In2O3 films grown on ionically conducting Y2O3-stabilized ZrO2 substrates. Oxygen ion redistribution across the heterointerface is induced using an applied electric field oriented in the plane of the interface, resulting in controlled oxygen vacancy (and hence electron) doping of the film and possible orders-of-magnitude enhancement of the film's electrical conduction. The reversible modified behavior is dependent on interface properties and is attained without cation doping or changes in the gas environment in contact with the sample. |
| US10784103B2 |
Water level sequencing flow cell fabrication
A method for forming sequencing flow cells can include providing a semiconductor wafer covered with a dielectric layer, and forming a patterned layer on the dielectric layer. The patterned layer has a differential surface that includes alternating first surface regions and second surface regions. The method can also include attaching a cover wafer to the semiconductor wafer to form a composite wafer structure including a plurality of flow cells. The composite wafer structure can then be singulated to form a plurality of dies. Each die forms a sequencing flow cell. The sequencing flow cell can include a flow channel between a portion of the patterned layer and a portion of the cover wafer, an inlet, and an outlet. Further, the method can include functionalizing the sequencing flow cell to create differential surfaces. |
| US10784099B2 |
Incandescent light bulb
To aim at a prevention of an occurrence of failure in and an extension of the life span of an incandescent light bulb by reducing the impact of an external force, which is applied to an outer lead wire positioned outside a bulb, on the connections between the lead wire and another element when manufacturing the incandescent light bulb, especially in a socket mounting process. In an incandescent light bulb wherein a filament assembly having filaments and lead wires which support the filaments is sealed in a bulb, a shape which, being easy to bend, enables a reduction in the impact of an applied external force on another element is imparted to a region of a predetermined length which includes the boundary of the lead wires between inside and outside the bulb. For example, a region in which the cross-sectional shape of the lead wires is changed by crushing is provided. |
| US10784097B2 |
Atmospheric-pressure ionization and fragmentation of molecules for structural elucidation
A solution-cathode glow discharge (SCGD) spectrometry apparatus may comprise an SCGD source and a mass or ion mobility spectrometer. A method for ionizing a molecular analyte may comprise contacting the molecular analyte with a plasma discharge to form ions and separating the ions in a mass spectrometer or ion mobility spectrometer. The contacting step may occur under atmospheric pressure and/or ambient conditions. The molecular analyte may be fragmented by the plasma discharge. |
| US10784094B2 |
Harmonic line noise correction for electron energy loss spectrometer
Electron Energy Loss Spectrometer including a correction circuit for fundamental and third harmonic line noise is described. Various circuits for creating the correction signals are also described. A method of correcting for fundamental and third harmonic line noise is also described. |
| US10784086B2 |
Cobalt etch back
Methods of etching cobalt on substrates are provided. Some methods involve exposing the substrate to a boron-containing halide gas and an additive, and exposing the substrate to an activation gas and a plasma. Additives improve selectively depositing a thicker layer of a boron-containing halide material on a surface of a mask than on a surface of a metal. Additives include H2, CH4, CF4, NF3, and Cl2. Boron-containing halide gases include BCl3, BBr3, BF3, and BI3. Exposures may be performed in two or more cycles, with variations in durations and/or bias power for each exposure in the two or more cycles. |
| US10784084B2 |
Energy-efficient plasma processes of generating free charges, ozone, and light
Embodiments of the present invention describe the formation of a current source, a light source, and an ozone generator by using a coated double dielectric barrier discharge system (CDDBD). A system for generating charge may include a CDDBD having at least two electrodes that are separated by a gap filled with a gas medium, wherein each of the at least two electrodes are covered with an insulator that prevents charges in the at least two electrodes from passing through the gas medium, and wherein surfaces of each of the at least two insulators are coated with a material having a secondary electron emission coefficient higher than a material of the insulator. Furthermore, the system for generating the charge may also include a power supply coupled with the CDDBD device that supplies energy to the CDDBD device to form an initial electric field. |
| US10784083B2 |
RF voltage sensor incorporating multiple voltage dividers for detecting RF voltages at a pickup device of a substrate support
A voltage sensor for a substrate processing system is provided. The voltage sensor includes a terminal, a first channel, and a second channel. The terminal connects to a pickup device of a substrate support in the substrate processing system. The first channel is configured to detect, at the pickup device, first radio frequency voltages in a first voltage range. The first channel includes a first voltage divider. The first voltage divider is connected to the terminal and is configured to output a first reduced voltage representative of a detected one of the first radio frequency voltages. The second channel is configured to detect, at the pickup device, second radio frequency voltages in a second voltage range. The second channel includes a second voltage divider. The second voltage divider is connected to the terminal and is configured to output a second reduced voltage representative of a detected one of the second radio frequency voltages. The second voltage range is different than the first voltage range. |
| US10784082B2 |
Apparatus for generating plasma and apparatus for treating substrate having the same
Disclosed is an inductively-coupled plasma-generating device including: a first power supply for supplying high frequency power; a second power supply for supplying low frequency power; a single coil-based plasma source including at least two antennas which comprise a first antenna having one end as a grounded end and the other end, wherein the first power supply is connected to the first antenna at a point thereof adjacent to the grounded end to receive the high frequency power; and a second antenna surrounded by the first antenna, wherein the second antenna has one end connected to the first antenna and the other end as a low frequency power receiving end connected to the second power supply; and a gas supply for supplying a gas, wherein the gas is excited into plasma by the single coil-based plasma source. |
| US10784074B2 |
Charged particle beam apparatus and control method thereof
The invention is directed to a charged particle beam apparatus that enables temperature maintenance in a cooling unit provided inside a vacuum application apparatus using a refrigerant. The charged particle beam apparatus includes a cooling tank that contains a refrigerant for cooling a cooling unit, a cooling pipe that supplies the refrigerant from the cooling tank to the cooling unit, and a unit that leads the refrigerant to liquefy when the refrigerant is biased to a solid. |
| US10784072B2 |
Aberration-corrected multibeam source, charged particle beam device and method of imaging or illuminating a specimen with an array of primary charged particle beamlets
A charged particle beam device for inspection of a specimen with an array of primary charged particle beamlets is described. The charged particle beam device includes a charged particle beam source to generate a primary charged particle beam; a multi-aperture plate having at least two openings to generate an array of charged particle beamlets having at least a first beamlet having a first resolution on the specimen and a second beamlet having a second resolution on the specimen; an aberration correction element to correct at least one of spherical aberrations and chromatic aberrations of rotational symmetric charged particle lenses; and an objective lens assembly for focusing each primary charged particle beamlet of the array of primary charged particle beamlets onto a separate location on the specimen. |
| US10784071B2 |
Electron emitter and method of fabricating same
Electron emitters and methods of fabricating the electron emitters are disclosed. According to certain embodiments, an electron emitter includes a tip with a planar region having a diameter in a range of approximately (0.05-10) micrometers. The electron emitter tip is configured to release field emission electrons. The electron emitter further includes a work-function-lowering material coated on the tip. |
| US10784067B2 |
Electronic assembly with thermal fuse, an electric motor and a drive of a motor vehicle
An electronic assembly contains a circuit board having a current-conducting current path with two mutually spaced-apart current path ends that form an interruption point and a contact clip bridging the interruption point. The contact clip is manufactured without a preload, as a thermal fuse. The contact clip has a multiple bent, open clip loop and a contact limb making contact with both mutually spaced-apart current path ends using solder. The contact clip further has a fixing limb with a limb end seated in a circuit board opening. The limb end of the fixing limb is oversized relative to a circuit board opening, and a deformation being imparted to the contact clip, with an internal preload being generated. |
| US10784058B2 |
Sealed electrical contact system
A sealed electrical contact system includes at least one male electrical contact with at least one annular flange and a male conductive contact. At least one female electrical contact includes a receptacle and a female conductive contact disposed in the receptacle. The at least one annular flange is configured to contact an inner surface of the receptacle when the male conductive contact contacts the female conductive contact and closes a circuit. |
| US10784056B2 |
Switch assembly and power supply system
A switch assembly and a power supply system are provided. The switch assembly includes a switch body having a two-pin plug, a first circuit board, and a second circuit board. The first circuit board is provided with a power supply terminal block and a group of female terminals. The group of female terminals includes a first female terminal, a second female terminal and a third female terminal. The first female terminal and the second female terminal are respectively plugged with two pins of the two-pin plug. The first female terminal is electrically connected to the power supply terminal block, and the second female terminal is electrically connected to the third female terminal. The second circuit board is provided with a load connection terminal and a male terminal electrically connected to the load connection terminal. The male terminal is plugged with the third female terminal. |
| US10784054B2 |
Nanoelectromechanical devices with metal-to-metal contacts
Nanoelectromechanical systems (NEMS) devices/switches and methods for implementing and fabricating the same with conducting contacts are provided. A nanoelectromechanical system (NEMS) switch can include a substrate; a source cantilever formed over the substrate and configured to move relative to the substrate; a drain electrode and at least one gate electrode formed over the substrate; wherein the source cantilever, drain and gate electrodes comprises a metal layer affixed to a support layer, at least a portion of the metal layer at the contact area extending past the support layer; and an interlayer sandwiched between the support layer and substrate. |
| US10784052B2 |
Electric storage module
An electric storage module includes an electric storage cell and an enclosure, wherein the electric storage cell includes an electric storage element and an exterior body in which the electric storage element is sealed; the enclosure has a housing space in which the electric storage cell is housed; the enclosure has a through hole that connects the housing space and the exterior space; and the through hole is formed at a position corresponding to the part of the electric storage cell where the electric storage element does not exist. |
| US10784051B2 |
Dye-sensitized photoelectric conversion element
The dye-sensitized photoelectric conversion element of the present invention has an electrolyte layer in which an ammonium ion, an inorganic salt and an iodide ion are dissolved in an organic solvent and in which the ratio of the molar amount of triiodide ions to the molar amount of iodide ions is less than 1%. High photoelectric conversion efficiency is obtained regardless of the kind of the sensitizing dye, and the design is also excellent. |
| US10784048B2 |
Capacitor component including amorphous second phase
A capacitor component includes a body including a dielectric layer and first and second internal electrodes, alternately disposed in a first direction, and first and second external electrodes, respectively disposed on opposite end surfaces of the body in a second direction, perpendicular to the first direction in the body. An amorphous second phase is disposed at an interface between the first and second internal electrodes and the dielectric layer, and ls/le is between 0.02 and 0.07, where ls is a total length of the amorphous second phase disposed in a boundary line between the first or second internal electrode and the dielectric layer in the second direction and le is a length of the first or second internal electrode in the second direction. |
| US10784044B2 |
Optimization of transmit and transmit/receive (TRX) coils for wireless transfer of power
In accordance with embodiments of the present invention, a coil design for the transmission of wireless power. In some embodiments, the coil can include a winding with one or more turns of conductive traces mounted on a substrate, wherein the one or more turns include characteristics that enhance operation of the coil. In some embodiments, the winding includes a transmit coil and a receive coil, each coupled to terminals that provide for a transmit functionality and a receive functionality. In some embodiments, the traces are varied in width and/or thickness in order to optimize the inductance and the coil resistance. In some embodiments, parameters of a control circuit coupled to the coil to affect a transmit functionality or a receive functionality can be optimized. |
| US10784041B2 |
Electromagnetic power converter
Magnetic flux valves can be used in electromagnetic (EM) power converters to electronically control output signals of the EM power converters. An input signal is provided to an EM power converter that includes two or more core sections in which at least one core section includes a magnetic flux valve having an adjustable reluctance. The EM power converter has one or more primary windings and one or more secondary windings wound around one or more core sections. One or more control signals are provided to the one or more magnetic flux valves to control a reluctance or reluctances of the one or more magnetic flux valves, affecting magnetic coupling between the primary and secondary windings. An output signal is generated, in which the output signal is a function of the input signal and the one or more control signals. |
| US10784036B2 |
Magnetic coupling coil component
One object of the present invention is to provide a magnetic coupling coil component having a coupling coefficient that can be readily adjusted. A coil component according to one embodiment of the present invention includes: a drum core including a winding core, a first flange, and a second flange, the first flange being provided on one axial end of the winding core, the second flange being provided on another axial end of the winding core; a spacer provided on a surface of the winding core between the first flange and the second flange, the spacer being separate from the winding core; a first winding wire wound around the winding core between the first flange and the spacer; and a second winding wire wound around the winding core between the second flange and the spacer. |
| US10784033B2 |
Vertical inductor for WLCSP
Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace. |
| US10784030B2 |
Magnetic sheet, module comprising same, and portable device comprising same
Provided herein is a magnetic sheet. The magnetic sheet according to one embodiment of the present invention includes a magnetic layer formed of crushed pieces of a magnetic body to improve flexibility of the magnetic sheet, and a thin film coating layer formed on at least one surface of the magnetic layer to maintain the magnetic layer in a sheet shape and buffer an external force applied to the crushed pieces of the magnetic body. According to the present invention, since the magnetic sheet is improved in mechanical strength properties, such as a tensile property, a bending property, and the like, to have significantly superior flexibility, degradation of physical properties, such as magnetic permeability and the like, caused by physical damage such as unintended cracks in the magnetic body provided in the magnetic sheet can be prevented even in the process of storing, transferring, and attaching the magnetic sheet to a target object and during usage of an electronic device provided with the target object to which the magnetic sheet is attached, and the magnetic sheet can be attached to a target surface of the target object with a superior adhering force even when a stepped portion is present at the surface, and at the same time, the magnetic sheet can block the influence of a magnetic field on parts of a portable terminal device or a human body of a user using the portable terminal device, significantly increase transmission and reception efficiencies and distances of a data and/or wireless power signal, and maintain the above-described performance for a long period of time, such that the magnetic sheet can be widely used in various portable devices such as mobile devices, smart appliances, devices for the Internet of Things, and the like. |
| US10784027B2 |
Voltage dependent resistor
A voltage dependent resistor includes a ceramic body and an electrically conductive structure for external connection. The ceramic body has two opposite surfaces and a side surface connecting the two opposite surfaces, and at least one of the two opposite surfaces is formed with at least one protrusion at a position adjacent to the side surface. As the protrusion makes the opposite surfaces of the ceramic body non-planar, the voltage dependent resistor is capable of suppressing the occurrence of flashover firelight during surge impact, so that its capability of withstanding surge impact is enhanced and its lifespan is prolonged. In addition, such structural arrangement is capable of preventing ceramic plates from adhering with each other when they are stacked with each other during the sintering stage of a green compact, thereby simplifying the post-processing procedures and minimizing the defect rate. |
| US10784022B1 |
Cable structure
A cable structure includes at least one stuffing element, a first transmission module surrounding outside the at least one stuffing element, a first shielding layer surrounding outside the first transmission module, a second transmission module surrounding outside the first shielding layer, a second shielding layer surrounding outside the second transmission module, a woven layer surrounding outside the second shielding layer, an insulating skin surrounding outside the woven layer, a plurality of first core wire assemblies disposed in the first transmission module and the second transmission module, respectively, and at least one second core wire assembly disposed in the first transmission module or the second transmission module. A diameter of each first core wire assembly is different from a diameter of each second core wire assembly. |
| US10784021B2 |
Shielded electrical cable
A shielded electrical cable includes conductor sets extending along a length of the cable and spaced apart from each other along a width of the cable. First and second shielding films are disposed on opposite sides of the cable and include cover portions and pinched portions arranged such that, in transverse cross section, the cover portions of the films in combination substantially surround each conductor set. An adhesive layer bonds the shielding films together in the pinched portions of the cable. A transverse bending of the cable at a cable location of no more than 180 degrees over an inner radius of at most 2 mm causes a cable impedance of the selected insulated conductor proximate the cable location to vary by no more than 2 percent from an initial cable impedance measured at the cable location in an unbent configuration. |
| US10784018B2 |
Insulated wire
An insulated wire having an electrical wire structure capable of reducing an outer diameter while an insulating property and a flame-retardant property are highly kept is provided. In the insulated wire including: a conductor; and a coating layer arranged on an outer periphery of the conductor, the insulated wire has a flame-retardant property that allows the insulated wire to pass a vertical tray flame test (VTFT) on the basis of EN 50266-2-4, has a direct-current stability that allows the insulated wire to pass a direct-current stability test in conformity to EN 50305.6.7, has a diameter of the conductor that is equal to or smaller than 1.25 mm, and has a thickness of the coating layer that is smaller than 0.6 mm. |
| US10784016B2 |
Intrinsically safe explosion-proof compound cable, signal processor provided with the intrinsically safe explosion-proof compound cable, teach pendant provided with the intrinsically safe explosion-proof compound cable, and robot provided with the intrinsically safe explosion-proof compound cable
An intrinsically safe explosion-proof compound cable includes a plurality of unit cables. Each of the unit cables is configured to transmit a signal or power. The plurality of unit cables include one or more shielded cables each having a shield layer and one or more unshielded cables without the shield layer. At least a highest-frequency unit cable that is the unit cable configured to transmit the signal or power at the highest frequency among the plurality of unit cables is the unshielded cable. |
| US10784011B1 |
Residue free electrically conductive material
A deformable yet mechanically resilient microcapsule having electrical properties, a method of making the microcapsules, and a circuit component including the microcapsules. The microcapsule containing a gallium liquid metal alloy core having from about 60 to about 100 wt. % gallium and at least one alloying metal, and a polymeric shell encapsulating the liquid core, said polymeric shell having conductive properties. |
| US10784005B2 |
Device for removing foreign objects from nuclear reactor vessel
A device for removing foreign objects from nuclear reactor vessel includes a suction pipe; a suction opening structure disposed at a lower end of the suction pipe, an electric valve disposed at a connection of the suction pipe and the suction opening structure, a filter mesh and a suction pump sequentially located in the suction pipe and above the electric valve. The suction opening structure has a suction opening thereon, a water inlet of the suction pump is communicated with the suction opening, and a water outlet of the suction pump is communicated with the outside space of the suction pipe though a drainage pipe. The device further includes a touch switch disposed on the filter mesh which is in operative connection with the electric valve. A foreign object impact force to the filter mesh triggers the touch switch to close which causes the electric valve to close. |
| US10784003B2 |
Containment cooling apparatus
A containment cooling apparatus includes a cooling water tank disposed above a containment; a spray header connected to the cooling water tank via a first communicating pipe, wherein the spray header is disposed on an outside of the containment for spraying cooling water to an outer wall of the containment; a bell shaped shield covering the containment, wherein the cooling water tank is disposed on a top portion of the shield; a space formed between an inner wall of the shield and the outer wall of the containment, wherein the spray header is disposed in the space; an exhaust hole disposed on the top portion of the shield; and a water separator disposed in the exhaust hole and/or the space. The containment cooling apparatus has higher utilization of coolant. |
| US10784000B2 |
Medical system interface apparatus and methods to classify and provide medical data using artificial intelligence
Apparatus, systems, devices, other articles of manufacture and associated methods are disclosed and described herein to process medical data to generate a classification of the medical data using artificial intelligence. An example apparatus includes a processor to execute instructions to implement a history of past illness (HPI) receiver to receive an HPI formatted as a string, the string including one or more words, the words organized in sentences, a natural language processor to tokenize the one or more words into tokens based on a context associated with at least one of the one or more words and a tensor generator to convert the tokens into hashes, each of the hashes forming a dimension of a tensor based on the context. The apparatus further includes a neural network to embed each of the hashes into vectors, process the vectors to classify the HPI as extended or brief based on a similarity to a set of classified HPIs and output a classification for the HPI. The apparatus further includes an electronic medical record modifier to modify an electronic medical record with the HPI and the classification and to trigger an action with respect to the electronic medical record based on the classification. |
| US10783998B1 |
Signal processing for making predictive determinations
In some examples, unstructured data is evaluated using a natural language processing model to output a set of subjective indicators. These subjective indicators are scored using a predictive model to determine whether a dependent user has or is likely to develop a particular condition such as a cellular abnormality. |
| US10783997B2 |
Personalized tolerance prediction of adverse drug events
Embodiments include method, systems and computer program products for predicting adverse drug events on a computational system. Aspects include receiving a personalized data set including a plurality of real-time drug doses for a first drug or drug combination and a plurality of corresponding real-time adverse drug reaction tolerance data for the first drug or drug combination for a patient. Aspects also include receiving known drug data for a candidate drug or drug pair. Aspects also include calculating, based upon the known drug data and the personalized data set, a predicted adverse drug reaction tolerance for the candidate drug or drug pair at a candidate dosage, wherein the predicted adverse drug reaction tolerance is personalized to the patient. |
| US10783994B2 |
Atomization system and device having single authentication mechanism
The present invention provides an atomizing system and device having a single authentication mechanism. The system includes at least one atomizing drug container and an atomizing device. The at least one atomized medicine container associates with an authentication code carrier and contains the atomized medicine. The atomizing device includes an atomizing module, a first power module, a control unit, an antenna module and an authentication module. The authentication module is configured to perform an authentication operation associated with the authentication code carrier to determine the authenticity of the at least one atomized medicine container or the atomized medicine and to generate an authentication result signal correspondingly. |
| US10783993B2 |
Systems for determining, and devices for indicating, viable life of replaceable components thereof and methods therefor
A system capable of monitoring a replaceable component is provided. The system includes a controller for controlling operation of the system; programming instructions according to which the system is configured to: accept input of a viable life for the component, calculate an accumulated amount of distress experienced by the component based on each set of previously collected use data associated with each previous use of the component, and determine, based in part on the accumulated amount of distress, a used portion of the viable life that the component has experienced as a result of the previous use(s) thereof and an unused portion of the viable life; and a feedback device configured to provide to an operator of the system an indication of at least one of the unused and used portions of the viable life of the component. Methods of monitoring a replaceable component of a system are also provided. |
| US10783992B1 |
Interactive cross-provider health care presentation and modification system
A cross-provider health care system is provided to analyze provider health care determinations with respect to a baseline and present interactive controls for modification of the determinations. Interactive maps are provided for presenting and interacting with health care provider characteristics. |
| US10783985B2 |
Physics-based computational methods for predicting compound solubility
Methods of calculating a free energy of solubility for a compound in a solvent by computer operations include the following steps: (i) establishing, using a computer model, an initial state for a system including an aggregate of multiple molecules of the compound in a solvent; (ii) establishing, using the computer model, a final state of the system including a single molecule from the aggregate fully solvated in the solvent and separate from a transformed aggregate; (iii) transforming, using the computer model, the system from the initial state to the final state, via removing a first molecule of the compound from the aggregate to form the transformed aggregate and replacing the first molecule with solvent at the site of the first molecule; and (iv) calculating the free energy of the transformation between the initial and the final states, which determines the free energy of solubility for the compound. |
| US10783984B2 |
De novo diploid genome assembly and haplotype sequence reconstruction
Exemplary embodiments provide methods and systems for diploid genome assembly and haplotype sequence reconstruction. Aspects of the exemplary embodiment include generating a fused assembly graph from reads of both haplotypes, the fused assembly graph including identified primary contigs and associated contigs; generating haplotype-specific assembly graphs using phased reads and haplotype aware overlapping of the phased reads; merging the fused assembly graph and haplotype-specific assembly graphs to generate a merged assembly haplotype graph; removing cross-phasing edges from the merged assembly haplotype graph to generate a final haplotype-resolved assembly graph; and reconstructing haplotype-specific contigs from the final haplotype-resolved assembly graph resulting in haplotype-specific contigs. |
| US10783981B1 |
Semiconductor memory capable of reducing an initial turn-on voltage of a memory cell using a stress pulse in a test mode, and method for driving the same
An electronic device includes a semiconductor memory. The semiconductor memory includes a plurality of first lines; a plurality of second lines; a plurality of memory cells disposed in respective intersection regions between the first lines and the second lines and coupled between the first lines and the second lines, the plurality of memory cells having a first turn-on voltage; and a test circuit block suitable for applying a stress pulse having a voltage level equal to or higher than the first turn-on voltage to one or more first lines selected from the first lines in a test mode. |
| US10783975B2 |
Semiconductor memory device
A semiconductor memory device includes first and second memory transistors and first and second word lines connected to gate electrodes of the memory transistors. The semiconductor memory device is configured such that a first write operation to the first memory transistor, a second write operation to the second memory transistor, a third write operation to the first memory transistor, and a fourth write operation to the second memory transistor are executed in this order. In the first and second write operations, data write is performed using only a program operation. In the third and fourth write operations, data write is performed using the program operation and the verify operation. |
| US10783973B1 |
Memory device having parameter adjusting mechanism and method of adjusting parameter by memory device
The disclosure provides a memory device including: a connection interface; a memory array associated with a parameter; and a memory control circuit configured at least to: receive operations, each of the operations being a read operation or a write operation, through the connection interface to perform the operations on the memory array; detect, based on performing the operations on the memory array, a read error which is either a binary 0 read error or a binary 1 read error; update the error counter by incrementing an counter value of the error counter in response to the read error being the binary 1 read error and decreasing the counter value in response to the read error being the binary 0 read error; and adjust the parameter in response to the counter value having reached a positive predetermined threshold or a negative predetermined threshold. |
| US10783966B2 |
Multistage set procedure for phase change memory
Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches. |
| US10783963B1 |
In-memory computation device with inter-page and intra-page data circuits
An in-memory computation device is described that comprises a memory with a plurality of blocks B(n) of cells, where n ranges from 0 to N−1. A page output circuit PO(n) and page input circuit PI(n) are operatively coupled to block B(n) in the plurality of sets. A data bus system for providing an external source of input data and a destination for output data is provided. Data circuits are configurable connect page input circuit PI(n) to one or more of page output circuit PO(n), page output circuit PO(n−1), and the data bus system to source the page input data in a sensing cycle. This configuration can be done between each sensing cycle, or in longer intervals, in order to support a variety of neural network configurations and operations. |
| US10783960B2 |
Non-volatile memory cell and non-volatile cell array
A non-volatile memory cell includes a first select transistor, a first floating gate transistor, a second select transistor and a second floating gate transistor. The first select transistor is connected with a source line and a first program word line. The first floating gate transistor has a first floating gate. The first floating gate transistor is connected with the first select transistor and a first program bit line. The second select transistor is connected with the source line and a first read word line. The second floating gate transistor has a second floating gate. The second floating gate transistor is connected with the second select transistor and a first read bit line. The first floating gate and the second floating gate are connected with each other. |
| US10783959B2 |
Method of compensating charge loss and source line bias in programing of non-volatile memory device
A method of compensating charge loss and source line bias in programing of non-volatile memory device including the steps of reading a previous program page with a low reference voltage to make an original previous program pattern, merging the original previous program pattern and a current program pattern to make a merged program pattern, reading the previous program page with a high reference voltage to make a verified previous program pattern, and merging the verified previous program pattern and the merged program pattern to make a compensated current program pattern. |
| US10783958B2 |
Tunable negative bitline write assist and boost attenuation circuit
An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle. |
| US10783957B1 |
Read and logic operation methods for voltage-divider bit-cell memory devices
In a particular implementation, a method to perform a read operation on a voltage divider bit-cell having first and second transistors and first and second storage elements is disclosed. The method includes: providing a first voltage to a bit-line coupled to the second transistor of the voltage-divider bit-cell; providing a second voltage to a first word-line and providing an electrical grounding to a second word-line; where the first and second word-lines are coupled to the respective first and second resistive memory devices; and determining at least one of first and second data resistances in the respective first and second storage elements based on an output voltage on the bit-line. |
| US10783955B2 |
Memory circuit having shared word line
A circuit includes a column of memory cells, a first read data line coupled exclusively with a first subset of memory cells of the column of memory cells, a second read data line coupled exclusively with a second subset of memory cells of the column of memory cells, and a plurality of read word lines. Each read word line of the plurality of read word lines is coupled with a memory cell of the first subset of memory cells and with a memory cell of the second subset of memory cells. |
| US10783952B2 |
Systems and methods for reducing standby power in floating body memory devices
Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set. |
| US10783948B2 |
Ferroelectric memory cells
Apparatuses and methods are disclosed that include ferroelectric memory cells. An example ferroelectric memory cell includes two transistors and two capacitors. Another example ferroelectric memory cell includes three transistors and two capacitors. Another example ferroelectric memory cell includes four transistors and two capacitors. |
| US10783947B2 |
Magnetic memory device
According to one embodiment, a magnetic memory device includes a first member, a first memory cell, and a controller. The first member includes first, second, and third regions. The first memory cell includes first and second magnetic layers, and a first nonmagnetic layer. The second magnetic layer is provided between the third region and the first magnetic layer. The first nonmagnetic layer is provided between the first and second magnetic layers. The controller is electrically connected to the first and second regions, and the first magnetic layer. The controller programs first information to the first memory cell by setting the first magnetic layer to a first electric potential. The controller programs second information to the first memory cell by setting the first magnetic layer to a second electric potential. The second electric potential is different from the first electric potential. The second information is different from the first information. |
| US10783946B2 |
Semiconductor memory device including memory cell arrays
According to an embodiment, a semiconductor memory device includes: memory cell arrays; word lines respectively connected to rows of each of the memory cell arrays; bit lines respectively connected to columns of each of the memory cell arrays; row selection circuits provided so as to respectively correspond to the memory cell arrays and connected to the word lines; and column selection circuits provided so as to respectively correspond to the memory cell arrays and connected to the bit lines. When an identical row address is received, the row selection circuits perform selection operations of word lines so that word line lengths from selected memory cells to the row selection circuits vary. |
| US10783943B2 |
MRAM having novel self-referenced read method
A STT-MRAM comprises apparatus, a method of operating and a method of manufacturing a self-referenced magnetoresistive memory and a plurality of magnetoresistive memory element including a self-referenced read scheme through a write/read circuitry coupled to the bit line positioned adjacent to selected ones of the plurality of magnetoresistive memory elements to supply bi-directional spin-transfer recording and reading currents across the MTJ stack. Thus magnetization of a recording layer can be readily switched or reversed to the direction in accordance with a direction of a current across the MTJ stack by applying a spin transfer current, and the magnetization of a reference layer can be readily rotated to two reading directions subsequently in accordance with directions of currents across the MTJ stack by applying low spin transfer currents. |
| US10783942B2 |
Modified decode for corner turn
Examples of the present disclosure provide apparatuses and methods for performing a corner turn using a modified decode. An example apparatus can comprise an array of memory cell and decode circuitry coupled to the array and including logic configured to modify an address corresponding to at least one data element in association with performing a corner turn operation on the at least one data element. The logic can be configured to modify the address corresponding to the at least one data element on a per column select basis. |
| US10783941B1 |
Floating block select based programming time (tPROG)
A memory device includes a conductive line coupled to access addressable storage locations of the memory device. The memory device includes a circuit with a line driver with an access device for the conductive line. A control circuit sets a gate of the access device to an initial overdrive bias voltage to drive a drain of the access device to an initial voltage while the access device control circuit is not connected to the conductive line via another conductive line. The control circuit floats the gate voltage of the access device and connects the control circuit to the conductive line via the other conductive line. The floating initial overdrive voltage does not drop when the initial voltage of the control circuit drops to a final voltage under load conditions. The overdrive can result in a steeper program slope, and a controllable program pulse width or programming time (tPROG). |
| US10783940B2 |
Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle
Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset. |
| US10783939B1 |
Training of communication interfaces on printed circuit board
A printed circuit board (PCB) includes first and second integrated circuits (ICs) connected by way of write and read interfaces. The first IC includes a training circuitry for training the write and read interfaces. The first IC further includes read and write delay elements. The training circuitry trains the read and write interfaces (i.e., configures the read and write delay elements) for correcting signal skews that may be introduced by the read and write interfaces, respectively. The training circuitry configures the write delay element with a first write delay value for which there are no errors while writing data to a buffer memory of the second IC. The training circuitry configures the read delay element with a first read delay value for which there are no errors while reading the data from the buffer memory. |
| US10783937B2 |
Voltage reference computations for memory decision feedback equalizers
A device includes a signal input to receive a data input as part of a bit stream. The device also includes a reference input to receive a reference signal. The device further includes push circuitry to receive a first weight value, receive a first correction value, and generate a push signal based on the first weight value and the first correction value to selectively modify the data input as well as pull circuitry to receive a second weight value, receive a second correction value, and generate a pull signal based on the second weight value and the second correction value to selectively modify the data input. |
| US10783933B2 |
Semiconductor memory device
A semiconductor memory device includes a power source pad, a first bank including a plurality of memory cells, a second bank including a plurality of memory cells, the first bank being sandwiched between the power source pad and the second bank, first power supply lines connected to the power source pad and supplying power to the first bank and not to the second bank, and second power supply lines connected to the power source pad, passing over the first bank, and supplying power to the second bank and not to the first bank. |
| US10783929B2 |
Managing playback groups
In some implementations, a system can be configured to manage groups of playback devices. For example, playback devices can be dynamically grouped in a variety of ways. Each playback device can store attributes that define the group to which the playback device belongs. Each playback device can send its group attributes to remote control devices and the remote control devices can determine groups of playback devices based on the group attributes. The remote control devices can then configure and present graphical user interfaces that represent the various groups of playback devices. In some implementations, a group of playback devices can be configured as a persistent group. For example, a pair of playback devices (e.g., wireless speakers) can store and send attribute data indicating that the pair of playback devices is a persistent group so that remote control devices can present and control the persistent group as a single device. |
| US10783928B2 |
Automated video generation from financial market analysis
Production of a financial market trading data video streams in a plurality of languages by receiving a financial market analysis result having an analysis type. Producing a sentence text-string corresponding to each of several languages by inserting characteristic information values from the financial market analysis result into a sentence template and translations of the sentence-template. The each said text string is converted into an audio segment and an image segment such that the audio segment and corresponding image segment have equal duration. A video segment is created by combining said audio segment and image segment. For each language of said plurality of languages, the video segments are stitched together thereby producing a financial market trading data video stream for said financial market analysis result. |
| US10783926B1 |
Editing and tracking changes in visual effects
A method for determining edits of a subject video reel, comprising steps of opening an original EDL, reading every line of the original EDL, identifying event names representing each shot and identifying a source file. Each event includes at least a camera time code for the shot length, and a location time code indicating location of the shot in the source file. Locating events and picking up the in and out camera time codes from the shot names, noting shot names and camera times for shots found to have common in and out times, identifying every VFX shot and storing VFX names. Next, the software compares camera times for the shots in the first temporary file with camera times for the same shots in the second temporary file; preparing a result EDL file listing exclusively all VFX shots in which changes were found, and detailing the changes. |
| US10783918B2 |
Heat-assisted magnetic recording device incorporating laser heater for improved laser stability
An apparatus comprises a slider configured to facilitate heat assisted magnetic recording and a submount affixed to the slider. A laser unit is affixed to the submount and comprises a laser operable in a non-lasing state and a lasing state. A heater is embedded in the laser unit or the submount. The heater is configured to generate preheat for heating the laser during the non-lasing state and to generate steering heat for heating the laser during the lasing state. |
| US10783916B1 |
Passivated nitrogenated diamond-like carbon layer and method for passivating it
A nitrogenated diamond-like carbon (DLC) layer, like a nitrogenated DLC overcoat on a magnetic recording disk, includes cyanoacrylates that are attached to nitrogenated sites on the surface of the carbon layer. Cyanoacrylates are reactive with surface amine groups, which are among the nitrogenated surface sites that act as adsorption sites for volatile contaminants in the disk drive. The covalent bonding of the cyanoacrylate with the amine groups and other reactive sites on the disk overcoat blocks the adsorption of contaminants when they impinge on the overcoat surface. The cyanoacrylate may be applied to the overcoat by dipping the disk into a solution containing the cyanoacrylate or by exposing the overcoat to a cyanoacrylate vapor. |
| US10783914B2 |
Ferrimagnetic particle powder and method of manufacturing ferrimagnetic particle powder, as well as magnetic recording medium and method of manufacturing magnetic recording medium
A magnetic recording medium includes: a substrate; and a magnetic layer including a ferrimagnetic particle powder. A product (V×SFD) of a particle volume V and a holding force distribution SFD of the ferrimagnetic particle is equal to or less than 2500 nm3. |
| US10783911B1 |
Data storage device bank writing servo sectors for interleaved servo control processing
A data storage device is disclosed comprising a first head actuated over a first disk surface, and a second head actuated over a second disk surface. During a first revolution of the disk surfaces, a first set of servo sectors are written to the first disk surface and a second set of servo sectors are written to the second disk surface, wherein the first set of servo sectors are circumferentially offset from the second set of servo sectors. During a second revolution of the disk surfaces, at least one of the servo sectors in the first set is read from the first disk surface and at least one of the servo sectors in the second set is read from the second disk surface to control a position of the first head over the first disk surface. |
| US10783909B1 |
In-plane gimbal tongue microactuator system
A data storage device can employ a microactuator system that efficiently translates longitudinal microactuator strain into movement in-plane with a mid-plane of a gimbal tongue. A gimbal tongue may be suspended from a load beam with a transducing head mounted to the gimbal tongue and the transducing head separated from a magnetic recording medium by an air bearing. A microactuator attached to the gimbal tongue can be positioned so that a mid-plane of the microactuator is congruent with a mid-plane of the gimbal tongue. |
| US10783907B1 |
Reader with bi-layered side shields
A reader includes a free layer and a side shield that biases the free layer. The side shield includes a main bias layer having a first magnetic moment value and a first magnetization direction. The side shield also includes a compensation bias layer having a second magnetic moment value that is less than the first magnetic moment value and a second magnetization direction that is opposite to the first magnetization direction. |
| US10783905B2 |
Stress-free tape head module
According to one embodiment, a method includes attaching a die to a beam, wherein the die comprises an array of transducers positioned in a transducer region of the die, a first region extending from the transducer region to a first end of the die and a second region extending from the transducer region to a second end of the die. The first region of the die is attached to the beam. The transducer region and the second region are not attached to the beam. |
| US10783904B2 |
Device and method for improving the quality of in-ear microphone signals in noisy environments
A method, and device, for enhancing speech generated from bone and tissue conduction of a user of an In-ear device in a noisy environment, the Intra-aural device having an in-ear microphone adapted to be in fluid communication with the ear canal of the user and an outer-ear microphone adapted to be in fluid communication with the environment outside the ear. The method comprises applying an adaptive filter on the in-ear microphone signal, using the outer-ear microphone signal as a reference for the ambient noise and interrupting the application of the adaptive filter to the In-ear microphone signal upon detecting speech by the user. |
| US10783900B2 |
Convolutional, long short-term memory, fully connected deep neural networks
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for identifying the language of a spoken utterance. One of the methods includes receiving input features of an utterance; and processing the input features using an acoustic model that comprises one or more convolutional neural network (CNN) layers, one or more long short-term memory network (LSTM) layers, and one or more fully connected neural network layers to generate a transcription for the utterance. |
| US10783899B2 |
Babble noise suppression
Systems and methods are introduced to perform noise suppression of an audio signal. The audio signal includes foreground speech components and background noise. The foreground speech components correspond to speech from a user's speaking into an audio receiving device. The background noise includes babble noise that includes speech from one or more interfering speakers. A soft speech detector determines, dynamically, a speech detection result indicating a likelihood of a presence of the foreground speech components in the audio signal. The speech detection result is employed to control, dynamically, an amount of attenuation of the noise suppression to reduce the babble noise in the audio signal. Further processing achieves a more stationary background and reduction of musical tones in the audio signal. |
| US10783892B2 |
Audio encoding apparatus and method, and audio decoding apparatus and method
An audio encoding apparatus to encode an audio signal using lossless coding or lossy coding and an audio decoding apparatus to decode an encoded audio signal are disclosed. An audio encoding apparatus according to an exemplary embodiment may include an input signal type determination unit to determine a type of an input signal based on characteristics of the input signal, a residual signal generation unit to generate a residual signal based on an output signal from the input signal type determination unit, and a coding unit to perform lossless coding or lossy coding using the residual signal. |
| US10783880B2 |
Speech processing system and method
A speech processing system includes an input for receiving an input utterance spoken by a user and a word alignment unit configured to align different sequences of acoustic speech models with the input utterance spoken by the user. Each different sequence of acoustic speech models corresponds to a different possible utterance that a user might make. The system identifies any parts of a read prompt text that the user skipped; any parts of the read prompt text that the user repeated; and any speech sounds that the user inserted between words of the read prompt text. The information from the word alignment unit can be used to assess the proficiency and/or fluency of the user's speech. |
| US10783878B2 |
Analysis of a topic in a communication relative to a characteristic of the communication
A device monitors a communication between a user associated with a user device and a service representative associated with a service representative device, and causes a natural language processing model to perform a natural language processing analysis of a user input of the communication to identify a topic associated with the communication. The device determines a first score associated with the topic, and determines a second score associated with enabling the communication, where the first score and second score indicate a service performance score of an entity. The device causes a sentiment analysis model to perform a sentiment analysis of the communication to determine a sentiment score indicating a level of satisfaction the user has relative to the topic. The device updates a transaction protocol associated with the topic based on the service performance score, and/or updates a communication processing protocol associated with the communication based on the sentiment score. |
| US10783877B2 |
Word clustering and categorization
A system for categorizing words into clusters includes a receiver to receive a set of sentences formed by a plurality of words. The set of sentences is indicative of interaction of a user with a virtual assistant. A categorizer categorizes the plurality of words into a first set of clusters by using a first clustering technique, and categorizes the plurality of words into a second set of clusters by using a second clustering technique. A detector detects words that appear in similar clusters after categorization by the first clustering technique and the second clustering technique. Similarity of clusters is based on a nature of words forming the clusters. A generator generates a confidence score for each of the plurality of words based on the detection. The confidence score of a word is indicative of accuracy of the categorization of the word. |
| US10783874B2 |
Method and apparatus for providing voice feedback information to user in call
A method for providing a voice feedback information to a user in a call is provided, including: acquiring a text information obtained by conducting a voice recognition on a voice information of the user; identifying a menu item to be jumped to according to the text information and multiple menu items of other party in the call, where the menu item to be jumped to is away from a present menu item by at least two levels; jumping to the identified menu item; where identifying the menu item to be jumped to includes: selecting a portion of menu items having a higher matching degree with the text information from the multiple menu items according to a predetermined information; identifying a menu item to be jumped to from the selected portion of menu items or a remaining portion of menu items. |
| US10783872B2 |
Integration of third party virtual assistants
A speech-enabled dialog system responds to a plurality of wake-up phrases. Based on which wake-up phrase is detected, the system's configuration is modified accordingly. Various configurable aspects of the system include selection and morphine of a text-to-speech voice; configuration of acoustic model, language model, vocabulary, and grammar; configuration of a graphic animation; configuration of virtual assistant personality parameters; invocation of a particular user profile; invocation of an authentication function; and configuration of an open sound. Configuration depends on a target market segment. Configuration also depends on the state of the dialog system, such as whether a previous utterance was an information query. |
| US10783869B2 |
Cell structure for use in an acoustic panel, and methods of producing the same
An improved cell structure that enables design improvements to acoustic panels is provided. The provided cell structure for an acoustic panel is (i) capable of damping a wider range of audible frequencies, (ii) able to be easily combined and integrated into a variety of panel dimensions, and (iii) manufacturable using additive manufacturing techniques such as direct metal laser sintering (DMLS). |
| US10783867B2 |
Acoustic filler including acoustically active beads and expandable filler
Aspects are disclosed of a filler for occupying a volume. The filler includes an expandable filler positioned in the volume so that it occupies a percentage of the volume. The expandable filler can permanently expand from a first dimension to a second dimension upon the application of an expansion trigger. The filler also includes an acoustic filler made up of a plurality of acoustically active beads positioned with the expandable filler in the volume so that the acoustic filler can adsorb gas flowing into the volume. Other embodiments are disclosed and claimed. |
| US10783865B2 |
Ergonomic electronic musical instrument with pseudo-strings
An ergonomic, portable, electronic, string-like instrument that utilizes a string-like interface. The string-like interface is tactile for sightless playability and capable of advanced input such as force and pressure sensitivity. The string-like interface functions to select a note, trigger a selected note, select and play a note on the instrument or an external peripheral. The instrument is played using the techniques of multiple stringed instruments and the ergonomics allow the user to hold and handle the device consistent with playing techniques familiar to musicians of multiple instruments. It is internally or externally powered and connects directly to industry-standard musical hardware such as MIDI devices, amplifiers and multi-track recorders. |
| US10783863B2 |
Machine-control of a device based on machine-detected transitions
Apparatus, methods, and systems that operate to provide interactive streaming content identification and processing are disclosed. An example apparatus includes a classifier to determine an audio characteristic value representative of an characteristic; a transition detector to detect a transition between a music category and a talk category by comparing the audio characteristic value to a threshold value among a set of threshold values, the set of threshold values corresponding to the music category and the talk category; and a context manager to control a device to initiate extraction of fingerprints, responsive to the detected transition between the music category and the talk category. |
| US10783861B2 |
System and method for compact bass chamber with internal beater and hi-hat apparatus
A versatile cajón having a compact footprint that incorporates actuators for an internal bass-beater and an external hi-hat. The cajón may further serve as a base for supporting additional percussive instruments, such as snare drums, tom drums, cymbals, and Latin percussion. In an embodiment, a bass drum pedal may be secured inside the cajón and having a rotating shaft protruding through a side wall of the cajón. The shaft protrusion may be coupled to a foot pedal in an actuating manner. As such, when a percussionist presses down on the foot pedal (e.g., with a foot action), the shaft rotates the beater head to strike an internal wall of the cajón, thereby producing a bass-like percussive sound. Similarly, the system may include a hi-hat pedal and shaft combination that is also attached directly to one or more external side walls of the cajón. |
| US10783860B2 |
Drum Wah
A drum and pitch adjustment device for a drum includes a drum with a sound producing membrane, a device for applying pressure to the sound producing membrane, and a cable configured to the device for applying and releasing pressure to the sound producing membrane, changing the pitch of the drum, but goes back to the drum's original pitch when absent this force. A hand operated lever, located on the side of the drum, operates the cable which makes the pressure device push up against the sound producing membrane and changing it's pitch. Absent this force, the drum goes back to its original pitch, which creates different tonal variety when played in real-time. |
| US10783857B2 |
Apparatus and method for fast memory validation in a baseboard management controller
An information handling system includes a host processing complex with a memory, and a baseboard management controller (BMC) with a processor and a video capture and difference engine (VCDE). The processor receives a memory compare command. The memory compare command includes a first pointer to a first block of the memory, a second pointer to a second block of the memory, and a memory block size. The processor further determines whether the memory block size is greater than a threshold, and forwards the memory compare command to the VCDE when the memory block size is greater than the threshold. The VCDE compares contents of the first block to contents of the second block in response to receiving the memory compare command. |
| US10783855B2 |
Display device and method for displaying an image thereon
In an embodiment of the present invention, a method for displaying an image of a display device includes moving the image displayed on an image display region along a movement path including a first position and a second position during a period of time, wherein, during the period of time, a total time for which the image is located at the first position is greater than a total time for which the image is located at the second position. |
| US10783854B2 |
Sporting event display device system
A method optimizes the visible area of a display device during a sporting event having a plurality of activities, where each activity ultimately has an outcome. To that end, the method receives a stream of electronic, machine readable real-time event information relating to the sporting event. When receiving the stream (i.e., at least part of the time when receiving the stream), the method displays, in real time on the display device, an event user interface having selection indicia configured to enable a user to predict the outcome of at least one of the plurality of activities of the event in real time. In response to user input via the event user interface, the method displays message indicia over at least a portion of the interface. |
| US10783844B2 |
Display device and method for controlling display device
This display device comprises a display panel whereon a plurality of pixels are disposed, and a drive unit for driving the display panel. The display device includes: a conversion unit that convers an original signal representing the luminance of the pixel into a brightened signal and/or a darkened signal; a calculation unit that calculates the difference in luminance of the original signal between one pixel unit and another pixel unit located next to the one pixel unit; a determination unit that determines whether or not the difference in luminance exceeds a threshold; a selection unit that selects the original signal when determined that the difference in luminance exceeds the threshold, and selects the brightened signal or the darkened signal when determined that the difference in luminance does not exceed the threshold; and an input unit that inputs an input signal based on the signal selected by the selection unit into the drive unit. |
| US10783836B2 |
Method and apparatus for controlling liquid crystal display brightness, and liquid crystal display device
This disclosure provides a method, and a liquid crystal display device, where the method includes: determining grayscale values of pixels in a zone image data block under a predetermined rule according to a received image signal; pre-obtaining a zone backlight value corresponding to the zone image data block according to the grayscale values; calculating an adjusted backlight value of a backlight zone corresponding to the zone image data block, based on the zone backlight value, a backlight value gain variable, and an ambient luminance revision variable; outputting the adjusted backlight value to a driver circuit of a backlight source in the backlight zone; and driving the backlight source according to the adjusted backlight value to control brightness of the backlight source in the backlight zone. |
| US10783831B2 |
Pixel circuit, display panel, display device, and method of driving pixel circuit
A pixel circuit comprising an organic light emitting diode; a driving transistor including a gate, a source connected to a first node, a drain connected to a second power supply terminal; and a photosensitive circuit connected between a second node and a third node, the second node configured to receive a reference voltage. The driving transistor is configured to, responsive to a gate voltage and a source voltage, control a magnitude of a driving current flowing through the organic light emitting diode. The photosensitive circuit is configured to sense an intensity of light emission of the organic light emitting diode and to set a potential at the third node according to the reference voltage and the intensity that was sensed, the potential that was set being detectable by an external circuit via a sense line. |
| US10783830B1 |
TFT pixel threshold voltage compensation circuit with short programming time
A pixel circuit has enhanced performance by minimizing noise effects from the data and reference voltage lines. To prevent data line noise from interfering with the drive transistor gate voltage during emission, a triple gate isolation is used between the data voltage line and the gate of the drive transistor by which three transistors are connected between the data voltage line and the gate of the drive transistor. To further improve the isolation, one of the middle nodes of the triple gate farthest from the data voltage line is connected to one floating node that is connectable to a reference voltage during the threshold compensation phase. A first capacitor is used for the threshold compensation, and a second capacitor is used to scale the data voltage during programming. The threshold compensation and data programming operations are thereby independent of each other to minimize programming time. |
| US10783825B2 |
Driving substrates and display panels
Disclosed are a driving substrate and a display panel. The driving substrate includes a substrate defining an irregular-shape non-display area, an anode layer, located on the irregular-shape non-display area and provided with a first curved groove for encapsulating, and an organic unit array formed on a surface of the anode layer away from the substrate. The organic unit array includes a number of organic units forming a number of unit rows and unit columns. The distances between every two adjacent organic units in each unit row or in each unit column are identical. The first curved groove is located between two organic units. |
| US10783821B2 |
Display panel, and method for driving the display panel
The disclosure provides a display panel and a method for driving the display panel. The display panel includes a display area and a peripheral area surrounding the display area, and the display area includes one first display area and at least one second display area. The design according to embodiments of the disclosure release enough space occupied by the peripheral area at one side of the at least one second display area far away from the first display area, thus increasing display area in desired direction and a screen-to-total face ratio. |
| US10783820B2 |
Gate driver and flat panel display device including the same
Disclosed herein are a gate driver capable of implementing a narrow bezel by deleting dummy gate-in-panels (GIPs) and a flat panel display device including the same. The gate driver includes gate-in-panels (GIPs) equal in number to a plurality of gate lines in order to sequentially supply scan pulses to the plurality of gate lines. A k-th GIP is enabled by a carry pulse from a GIP of a (k−a)-th stage and is disabled by a carry pulse output from a GIP of a (k+b)-th stage (a and b are natural numbers), first a GIPs are enabled by a gate start signal output from a timing controller, and last b GIPs are disabled by a reset signal output from the timing controller. |
| US10783817B2 |
Driving circuit, level shifter chip, and display device
Disclosed are a driving circuit, a level shifter IC and a display device. The driving circuit includes a level enhancing module, a switch module, a current detecting module and a control module, the control module correspondingly switches on the switch module or switches off the switch module according to current signal output by the current detecting module. |
| US10783810B1 |
Illumination display platforms and related methods
An illumination display platform is provided. The platform includes an illumination source, like an LED strip, that provides lighting effects in connection with an art element and a panel system when the art element and panel system are in electrical and magnetic communication with one another. The illumination display platform permits tool-free assembly and disassembly. |
| US10783809B2 |
Rollable display device
A rollable display device includes a first roller part, a second roller part, a first assembly, and a second assembly. The first assembly is configured to be wound around the first roller part or unwound from the first roller part. The second assembly is configured to be wound around the second roller part. The first assembly includes a first flexible display panel and a first support structure body. The first support structure body has a plurality of divided structures, and the first support structure body is coupled to the back surface of the first flexible display panel to support the first flexible display panel. The second assembly includes a second support structure body. The second support structure body has a plurality of divided structures, and the second support structure body is coupled to the first support structure body by a magnetic force to support the first flexible display panel. |
| US10783806B2 |
Display article
According to one aspect, a display article having a first article end and a second article end includes a first portion having a first portion end proximal the first article end and first and second spaced tabs disposed at a second portion end opposite the first portion end. A second portion is adjacent the first portion wherein the second portion includes a third portion end adjacent the second portion end and disposed between the first and second spaced tabs and a fourth portion end proximal the second article end. The first portion is adapted to be secured to a support apparatus and the second portion is adapted to be deflected to a display position transverse to the first portion. |
| US10783804B1 |
Greeting card holder
The new greeting card holder preferably comprises at least one rigid longitudinal component combined with at least one flexible longitudinal band and at least one laterally oriented flexible ring. Each flexible longitudinal band extends the entire longitudinal length of a single corresponding rigid longitudinal component. Each laterally oriented flexible ring preferably encompasses one rigid longitudinal component approximately perpendicular or exactly perpendicular to at least one longitudinal flexible band along the rigid longitudinal component. In the preferred embodiment the greeting card holder also comprises at least one mechanical device that attaches a rigid longitudinal component in parallel alignment to another structure or structures. In other embodiments the greeting card holder comprises at least one rigid longitudinal component attaching perpendicular to a rigid polyhedron or rigid longitudinal polyhedron. |
| US10783801B1 |
Simulation based training system for measurement of team cognitive load to automatically customize simulation content
In one example embodiment of the invention, a simulation based training system is provided having a sensor that unobtrusively collects objective data for individuals and teams experiencing training content to determine the cognitive states of individuals and teams; time-synchronizes the various data streams; automatically determines granular and objective measures for individual cognitive load (CL) of individuals and teams; and automatically determines a cognitive load balance (CLB) and a relative cognitive load (RCL) measure in real or near-real time. Data is unobtrusively gathered through physiological or other activity sensors such as electroencephalogram (EEG) and electrocardiogram (ECG) sensors. Some embodiments are further configured to also include sociometric data in the determining cognitive load. Sociometric data may be obtained through the use of sociometric badges. Some embodiments further automatically customize the simulation content by automatically selecting content based on the CL of the individuals and teams. |
| US10783798B2 |
Coaching system for guiding interactions
Embodiments include method, systems and computer program products for coaching an individual during an interaction with a client to produce a desired outcome. Aspects include receiving a user profile for the client, one or more needs of the client, and a goal of the interaction and receiving a modeling profile for the client and relevant environmental information for the client. Aspects also include monitoring the interaction between the individual and the client and analyzing a feedback of the client to actions of the individual and providing guidance to the individual to assist the individual in producing the desired outcome, wherein the guidance is based on the feedback. |
| US10783789B2 |
Lane change estimation device, lane change estimation method, and storage medium
A lane change estimation device includes a detection unit that detects a surrounding situation of an own-vehicle, a first index value deriving unit that derives a first index value according to a traveling-direction-related relationship between each of a plurality of pairs of vehicles, each pair including two vehicles among the own-vehicle, a first vehicle traveling in front of the own-vehicle in a first lane in which the own-vehicle travels, a second vehicle traveling in front of the own-vehicle in a second lane adjacent to the first lane, and a third vehicle traveling behind the second vehicle in the second lane on the basis of the surrounding situation of the own-vehicle, and an estimation unit that estimates a probability of lane change of the third vehicle on the basis of the first index value derived and a lateral position of the third vehicle. |
| US10783788B2 |
Information processing apparatus, information processing method, and information processing system
An advice target location at which a user had a predetermined emotion, for example, is determined based on location information, user biological information, and user transportation means information, which have been acquired by a terminal device (20) being used by the user. Advice information containing information indicating an advice presentation region set by a server device (50) is generated based on the advice target location. This advice information is supplied from the server device (50) to the terminal device (20), so that the terminal device (20) presents advice. With this, advice as to locations pedestrians find dangerous can be presented to drivers, and advice as to locations drivers find dangerous can be presented to pedestrians. Accordingly, accidents and the like can be prevented. |
| US10783787B2 |
Freeway queue warning system
A method includes using sensors to collect information about vehicles on a road and determining a plurality of crash probabilities based on the collected information. Each crash probability indicates a probability of a vehicular crash on the road at a respective point in time. The plurality of crash probabilities is averaged to form an average crash probability and the average crash probability is used to determine when to provide a message to a controller of a vehicle. |
| US10783775B2 |
Method and system for using intersecting electronic horizons
A method and system for using data associated with a first vehicle and a given road segment defined for a road network and using data associated with a second vehicle and the given road segment to determine a multi-vehicle probability value that indicates a probability that the first vehicle and the second vehicle will arrive at a common position of the given road segment simultaneously. The multi-vehicle probability value can be compared to a threshold probability value to determine whether the first vehicle and/or the second vehicle should take a responsive measure to avoid those vehicles arriving at the common position of the given road segment simultaneously. The data associated the first vehicle and the data associated with the second vehicle can each include a respective electronic horizon for that vehicle, and time parameters and probability values associated with those vehicles being on the given road segment. |
| US10783774B2 |
Method for estimating road travel time based on built environment and low-frequency floating car data
A method for estimating road travel time based on the built environment and low-frequency floating car data belongs to the technical field of urban traffic management and traffic system evaluation. The method takes built environment as an explanatory variable of the road travel time. The interpretability of this variable is proved by a numerical example. In addition, the method determines distribution parameters of road travel time using the number distribution of vehicles instead of distance. The benefits of the method are that: (1) it explains the positive effect of built environment on road travel time; and (2) it reflects the speed difference among different road sections, which can improve the precision of estimating road travel time. |
| US10783767B2 |
Device and method for controlling bluetooth enabled occupancy sensors
Device and method for controlling Bluetooth™ enabled occupancy sensors. One example system includes a transceiver, a display, and an electronic processor. The electronic processor is configured to receive from an occupancy sensor, a plurality of occupancy data points and an occupancy threshold, and to generate a graphical representation based on the data points and the threshold. The graphical representation includes a first line providing an indication of the values of the plurality of the occupancy data points relative to the occupancy threshold over time. The electronic processor is configured to present the graphical representation on the display. The electronic processor is configured to receive a user input indicating an updated occupancy sensing value, generate, based on the graphical representation and the updated occupancy sensing value, an updated graphical representation, present, on the display, the updated graphical representation, and transmit, to the occupancy sensor, the updated occupancy sensing value. |
| US10783765B2 |
Falling detection method and electronic system using the same
A falling detection method and an electronic system using the same are provided. The falling detection method includes: obtaining a video stream, and performing recognition on a person in an image of the video stream to obtain at least one human body feature; calculating based on the human body feature to obtain at least one falling related feature; calculating at least one movement trend in a plurality of directions of the person in the video stream by using an optical flow algorithm; inputting the falling related feature and the movement trend to a falling classifier, such that the falling classifier generates an output result indicating whether a falling event happens to the person; and sending an alarm according to the output result. |
| US10783763B2 |
Biological sensing perimeter and usage method therefor
A biosensitive perimeter includes a support, an excitation wire, an induction wire, a lead wire, a pulse signal generator, a triode, a step-up transformer, a processor, and an alarm; wherein, said excitation wire and said induction wire pass through a plurality of supports in parallel, and said excitation wire is used to form an induced electric field, and said induction wire is located in said induced electric field to sense the change information of said induced electric field caused by the biological magnetic field of a human body, and to transmit the sensed information of the induced electric field to the processor that is used to receive the information of the induced electric field sensed by the induction wire, and to determine whether the alarm is required to be activated; and said excitation wire and said induction wire are arranged in parallel. |
| US10783759B2 |
Intruder detection method and apparatus
An intruder detection method is provided, comprising a security server sending a verification prompt to a device in a controlled-access area, based on an entry indication of an entrant into the controlled-access area, with the verification prompt indicating the entrant should perform a predefined verification action, the security server receiving entrant behavior information, the security server comparing the entrant behavior information to a behavior model of a set of authorized persons associated with the controlled-access area, with the behavior model including the verification prompt, and the security server generating an intruder indication if the entrant behavior information does not match a behavior sequence included in the behavior model. |
| US10783755B2 |
Devices and methods for generating video overlay of transaction data on automated teller machine video
Systems and methods for associating automated teller machine (ATM) transaction information with photos and/or videos captured by cameras are provided. In some embodiments, an ATM communicates with a financial institution system via a first network. A video annotation device is communicatively coupled to the first network to receive copies of communications transmitted by the financial institution system to the ATM. The video annotation device extracts annotation information from the communications, and causes the annotation information to be associated with photos and/or videos captured by cameras. In some embodiments, the video annotation device is also communicatively coupled to a second network, and transmits the annotation information to an IP camera for use as on-screen display text. In some embodiments, the video annotation device receives a video signal from a camera, adds an annotation to the video signal, and provides the annotated video signal to a recording device. |
| US10783752B2 |
Crediting and debiting an electronic gaming machine in a casino environment
Devices, systems and methods are provided to enable casino operators to provide printed tangible items for patron uses, such as lottery tickets. Such embodiments accept tangible indicators of financial consideration from patrons, such as currency or tickets associated with certain verifiable values, such as valid and winning lottery tickets and other forms of consideration which a patron can provide to a casino in exchange for one or more points. |
| US10783747B2 |
Gaming systems and methods utilizing multi-mode game elements
Systems, apparatuses and methods for utilizing multi-mode symbols that interact with random game triggers to selectively activate gaming features. At least one multi-mode symbol is provided that includes at least first and second modes. When the multi-mode symbol is in the first mode, a first functionality is associated with the multi-mode symbol, such as its default symbol mode. In response to a trigger event involving the multi-mode symbol, the symbol is changed to exhibit the second mode, and a second symbol functionality is applied to the multi-mode symbol. Payouts are determined based on the first functionality of the multi-mode symbol when in the first mode, and based on the second functionality of the multi-mode symbol when in the second mode. |
| US10783746B2 |
Fraud detection system in a casino
A fraud detection system which detects fraud in a game of performing collection and redemption of chips in accordance with a win or lose result includes a camera which captures an image of chips contained in a chip tray of a dealer, an image analyzing apparatus which analyses the image captured by the camera to detect an amount of the chips contained in the chip tray, a card distribution device which determines a win or lose result of a game, and a control device which compares the win or lose result of the game and the amount of the chips contained in the chip tray before and after collection and redemption of the chips to detect fraud. |
| US10783744B2 |
System and method for wireless lottery
A lottery system is provided. Lottery tickets may be purchased using a communication device, such as a mobile device. Sales commissions, or other credit, for the purchased tickets may be determined for one or more retailers based at least partially on the location of the communication device, for example, when the purchase is made. |
| US10783741B2 |
Gaming systems, devices and methods for dynamic symbol substitution
Systems, apparatuses and methods for enhancing or otherwise modifying gaming indicia sources, such as slot game reels sourcing slot games, poker decks sourcing poker hands, etc. Slot game embodiments involve replacing or modifying symbols with new or transformed symbols on a slot game event basis, such as on a spin-by-spin basis. Multiple sets of different symbol replacement instructions may be provided, such that selection of one of the sets will cause different modifications to the slot reels than had another set been selected. Embodiments enable such selection and reel variation on a spin-by-spin basis in slot games. |
| US10783740B2 |
Gaming system and method having player selection of devices
A gaming system including an electronic gaming machine that enables a player to select one or more devices for operation of the electronic gaming machine and then provides operation of the electronic gaming machine based on the operation of such devices. |
| US10783738B2 |
Digital downloading jukebox with enhanced communication features
Systems and/or methods for use in connection with digital downloading jukeboxes are provided. Such systems and/or methods may be used to provide enhanced communications capabilities, e.g., to registered users of jukeboxes. In certain exemplary embodiments, users may become registered users directly at a jukebox. Registered users also may, in certain exemplary embodiments, receive coupons for free plays, import playlists from hardware devices and/or software applications, receive special pricing when playing certain instances of media, play playlists in whole or in part, create and/or manage playlists directly at a jukebox, establish and manage connections with other registered users, etc. Still further, in certain exemplary embodiments, one or more channels may be predefined and/or set up for a jukebox. |
| US10783733B2 |
Electronic voting system and control method
An authentication server authenticates a voter using authentication data including a first identifier (ID) associated with the voter and authentication information regarding the voter. The authentication server further synchronizes a first blockchain. The first blockchain includes first transaction data indicating that the voter has been authenticated with one or more of other authentication servers. A voting server receives, from a terminal, voting data including a second ID associated with a vote cast by the voter and voting information indicating the vote. The voting server synchronizes a second blockchain including, as second transaction data, the voting information included in the voting data with one or more of other voting servers. The terminal transmits the authentication data to the authentication server and, after the authentication is successfully completed, transmits the voting data to the voting server. |
| US10783730B2 |
Method and apparatus for an automated fuel authorization program for fuel terminals using a camera as part of the authorization process
A fuel authorization system enables data to be exchanged between vehicles and a fuel vendor, to verify that the vehicle is authorized to receive fuel. Each fuel island is equipped with a camera and a short range radio (RF) component. Participating vehicles are equipped with fuel authorization component including an IR transmitter and a RF component that can establish a data link with the fuel island's RF unit. When the camera senses a vehicle in the fuel lane, an RF query is sent to the vehicle. Participating vehicles respond with an IR transmission. An RF data link is then established between the enrolled vehicle and the fuel vendor to verify that the vehicle is authorized to receive fuel. Once the verification is complete, the fuel dispenser is enabled. In some embodiments, the IR data link is not required, as the camera can distinguish between multiple fuel lanes. |
| US10783726B1 |
Smart compartment for vehicles
The present invention is a secure document compartment that can hold important vehicle documents, and is conveniently placed proximate to a user, so that the user may retrieve the documents in a fast and secure fashion. According to the present invention, the user may actuate opening of the secure document compartment manually with the help of an access panel or by voice activation. Further, the present invention may be visible and attached to an upper dashboard of the vehicle, right behind the steering wheel for easy retrieval of documents, or, may be installed inside, as an invisible compartment inside the dashboard. Furthermore, the present invention may comprise a camera, a microphone, and necessary circuitry that enables the secure document compartment to have multiple smart functionalities, such as audio/video recording and play back, remote wireless operations etc. |
| US10783725B1 |
Evaluating operator reliance on vehicle alerts
A system and computer-implemented method detect and act upon operator reliance to vehicle alerts. The system and method include receiving user profile data of an operator that includes a baseline of at least one driving activity aided by activation of an alert from a feature of an Advanced Driver Assistance System (ADAS). The system and method may include receiving historical ADAS alert frequency data including a history of at least one driving activity aided by activation of the alert from the ADAS feature. The system and method may compare the user profile data with the historical ADAS alert frequency data, determine a reliance level based upon the comparing, and set at least a portion of an operator profile associated with the operator with the reliance level. As a result, a risk averse driver, and/or proper responsiveness to vehicle alerts may be rewarded with insurance-cost savings, such as increased discounts. |
| US10783724B2 |
Vehicle data collection system and method
A method of data collection for a vehicle includes defining a vehicle build configuration based on individual build configurations of one or more vehicle systems, and defining a data acquisition definition file at a data collection and reporting hub based on the vehicle build configuration. The data acquisition definition file includes parameters and measurements to be performed by a data acquisition system located at the vehicle. The data acquisition definition file is requested by the data acquisition system and the data acquisition definition file is communicated to the data acquisition system via a two way electronic communication link between the data collection and reporting hub following the request from the data acquisition system. Vehicle data is collected at the data acquisition system based on the data acquisition definition file. |
| US10783722B2 |
Short range communications for specific device identification during multi-device proximity
There is provided systems and methods for short range communications for specific device identification during multi-device proximity. A user may utilize a device to request a service at a specific location, such as a transportation service or ride sharing service. When arriving at the location, short range wireless communications between the user's device and the service provider's device may be used to detect the proximity of the devices to each other and exchange tokens that are used for identification of the other party. The communications may further be used to determine when the device are within communication range, and when the communication range ends indicating that the parties have moved outside the proximity range for the communications and the service has ended. At the end of the connection, a transaction for the service may automatically be generated and processed without requiring additional user input. |
| US10783721B2 |
Monitoring and diagnostics system for a machine with rotating components
A monitoring and diagnostics system for a machine having a plurality of rotating components includes a powertrain with a plurality of rotating components and a vibration sensor. The vibration sensor include a vibration sensor element and a sensor controller. The vibration sensor is disposed adjacent one of the plurality of rotating components. The vibration sensor element is configured to generate raw vibration data indicative of vibrations of the vibration sensor element. The sensor controller is configured to access a vibration threshold, access a time threshold, receive the raw vibration data from the vibration sensor element, generate condition indicators based upon the raw vibration data; compare the condition indicators to the vibration threshold, and if the condition indicators exceed the vibration threshold for a time exceeding the time threshold, transmit a predetermined amount of raw vibration data to a remote system remote from the machine. |
| US10783715B2 |
Augmented reality display reflective of visibility affecting features in real-world environment
Method and system for displaying augmented reality reflective of environmental features affecting visibility. Characteristics of a virtual object to be displayed on view of scene is determined. Environmental features affecting visibility along a line-of-sight from scene origin to virtual object are detected. When detected feature is at least one non-obstructing feature, its effect on visibility is determined, and virtual object is displayed superimposed onto view of scene such that appearance of virtual object is consistent with determined effect on visibility. When detected feature includes an amorphous obstructing feature, its range and contour is determined, and obstructed portions of virtual object is determined based on difference between range of virtual object and range of amorphous obstructing feature, and virtual object is displayed superimposed onto view of scene such that determined obstructed portions of virtual object appear obstructed in displayed view. |
| US10783714B2 |
Methods and systems for automatically tailoring a form of an extended reality overlay object
An exemplary extended reality presentation system presents, to a user, a field of view into an extended reality world, and identifies an augmentable object from a set of objects presented in the field of view. The system determines that the augmentable object is located at a first apparent proximity to the user, and presents, within the field of view, a first form of an overlay object graphically associated with the augmentable object. The first form is tailored to the first apparent proximity. Subsequent to determining that the augmentable object is located at the first apparent proximity, the system determines that the augmentable object has come to be located at a second apparent proximity to the user and replaces, within the field of view, the first form of the overlay object with a second form of the overlay object distinct from the first form and tailored to the second apparent proximity. |
| US10783711B2 |
Switching realities for better task efficiency
An intelligent recommendation system and method for suggesting users perform various tasks in different reality systems to help user to maximize their productivity and achieve better satisfaction. By recognizing that a user is not efficient or unable to perform tasks well in real reality, the system suggests that the user try doing the similar task in a virtual reality (VR) or augmented reality (AR) environment and effects a physical switching to that environment for the user to practice and improve user's skill on the tasks. Further, by recognizing that user's emotions (e.g., sad or bad mood), the system further suggests the user to do certain things in the VR or AR environment to improve user's mood. The system and method continuously suggests performing tasks in VR or AR as needed, based on user's task efficiency score in real reality and any improvement occurred in RR when doing the task in VR. |
| US10783710B2 |
Configuration of navigational controls in geometric environment
According to embodiments of the invention, methods, and a computer system for configuring navigational controls in a geometric environment are disclosed. The method may include obtaining a data set for geometric representation on a display, forming one or more reference surfaces, calculating a fit score and a confidence score using one or more of the reference surfaces, and configuring the navigational system to a control scheme when a computational operation on the fit score and the confidence score is outside of a threshold value. The control scheme may be a geometric control scheme, a planar control scheme, and a roaming control scheme. |
| US10783706B2 |
Stereoscopic rendering of virtual 3D objects
In one implementation, a method involves tessellating a surface of a 3D object by identifying vertices having 3D positions. The method transforms the 3D positions into positions for a first sphere-based projection for a left eye viewpoint and positions for a second sphere-based projection for a right eye viewpoint. Transforming the 3D positions of the vertices involves transforming the vertices based on a user orientation (i.e., camera position) and differences left and right eye viewpoints (e.g., based on interaxial distance and convergence angle). The method further renders a stereoscopic 360° rendering of the 3D object based on the first sphere-based projection for the left eye viewpoint and the second sphere-based projection for the right eye viewpoint. For example, an equirectangular representation of the first sphere-based projection can be combined with an equirectangular representation of the second sphere-based projection to provide a file defining a stereoscopic 360° image. |
| US10783703B2 |
Representing traffic along a route
Some embodiments provide a mapping application that has a novel way of displaying traffic congestion along roads in the map. The mapping application in some embodiments defines a traffic congestion representation to run parallel to its corresponding road portion when the map is viewed at a particular zoom level, and defines a traffic congestion representation to be placed over its corresponding road portion when the map is viewed at another zoom level. The mapping application in some embodiments differentiates the appearance of the traffic congestion representation that signifies heavy traffic congestion from the appearance of the traffic congestion representation that signifies moderate traffic congestion. In some of these embodiments, the mapping application does not generate a traffic congestion representation for areas along a road that are not congested. |
| US10783700B2 |
Progressive lens simulator with an axial power-distance simulator
A Progressive Lens Simulator comprises an Eye Tracker, for tracking an eye axis direction to determine a gaze distance, an Off-Axis Progressive Lens Simulator, for generating an Off-Axis progressive lens simulation; and an Axial Power-Distance Simulator, for simulating a progressive lens power in the eye axis direction. The Progressive Lens Simulator can alternatively include an Integrated Progressive Lens Simulator, for creating a Comprehensive Progressive Lens Simulation. The Progressive Lens Simulator can be Head-mounted. A Guided Lens Design Exploration System for the Progressive Lens Simulator can include a Progressive Lens Simulator, a Feedback-Control Interface, and a Progressive Lens Design processor, to generate a modified progressive lens simulation for the patient after a guided modification of the progressive lens design. A Deep Learning Method for an Artificial Intelligence Engine can be used for a Progressive Lens Design Processor. Embodiments include a multi-station system of Progressive Lens Simulators and a Central Supervision Station. |
| US10783699B2 |
Sub-voxel refinement of anatomical models
The current document is directed to methods and systems that refine anatomical models to sub-voxel resolution. In certain implementations, sophisticated, composite, digital anatomical atlases provide detailed three-dimensional models of the contents of three-dimensional medical images. However, three-dimensional medical images have limited resolutions characterized by a smallest volume, referred to as a voxel, to which an intensity is assigned by the imaging process. The currently disclosed methods employ computed percentages of different types of tissue within voxel volumes to adjust a three-dimensional model of the contents of the voxel volumes to more accurately model the contents of the voxel volumes. |
| US10783693B2 |
Seismic image orientation using 3D integration operations
A separate three-dimensional (3D) integration filter mask if precomputed for each of x, y, and z dimensions with a given operator length. A portion of a 3D post-stack seismic data set is received for processing and loaded into a generated 3D-sub-cube. The separate 3D integration filter masks are applied to the loaded 3D-sub-cube to generate filtered 3D-sub-cube data. The square mean of the 3D-sub-cube is calculated to generate smoothed 3D-sub-cube data. |
| US10783692B2 |
Animation authoring system and method for authoring animation
This invention relates to as animation authoring system and an animation authoring method, to enable beginners to produce a three-dimensional animation easily and to solve input ambiguity problem in the three-dimensional environment. The animation authoring method according to the invention comprises the steps of: (a) receiving a plane route of an object on a predetermined reference plane from a user; (b) creating a motion window formed along the plane route and having a predetermined angle to the reference plane to receive motion information of the object on the motion window from the user; and (c) implementing an animation according to the received motion information. |
| US10783691B2 |
Generating a stylized image or stylized animation by matching semantic features via an appearance guide, a segmentation guide, and/or a temporal guide
Certain embodiments involve generating one or more of appearance guide and a positional guide and using one or more of the guides to synthesize a stylized image or animation. For example, a system obtains data indicating a target image and a style exemplar image. The system generates an appearance guide, a positional guide, or both from the target image and the style exemplar image. The system uses one or more of the guides to transfer a texture or style from the style exemplar image to the target image. |
| US10783687B2 |
Efficient duplicate label handling
Techniques are described for efficient duplicate label handling. A vector tile is added to a render tree of an electronic map, the vector tile comprising a first set of labels. A vector tile family of the vector tile is identified, each vector tile of the family comprising a second set of labels. For each label of the first set, for each vector tile in the vector tile family, second labels from the second set are identified, and for each identified label, coordinates of the label of the first set are compared to coordinates of the identified label to determine whether the coordinates are within a threshold similarity of each other. Responsive to the determination, the label of the first set of labels is associated with an identifier with which the identified label is associated. |
| US10783681B2 |
Artificially tiltable image display
A computer-implemented method of creating an artificially tiltable image display from an image containing Z distance values, the method comprising: separating the image into a plurality of layers using the Z distance values; expanding the plurality of layers by a factor dependent on the Z distance values, a layer closer to a viewer being enlarged by a larger factor than a layer further from a viewer, to create information in the layer further from a viewer that is occluded by the layer closer to a viewer; and responsive to a request to tilt the image display, moving the plurality of layers relative to each other so as to display the occluded information. |
| US10783679B2 |
Circular visual representation of media content
According to one implementation, a system for visualizing media content includes a computing platform including a hardware processor and a system memory, storing a content visualization software code. The hardware processor is configured to execute the content visualization software code to receive a media file, parse the media file to identify a primary content and metadata describing the primary content, and analyze the metadata to determine representative features of the primary content. The hardware processor further executes the content visualization software code to generate a circular visual representation of the primary content based on the metadata and the representative features, the circular visual representation having a non-linear correspondence to at least one of the representative features. The circular visual representation includes a central circle having a central radius, and multiple, at least semicircular segments, each having a respective radius greater than the central radius. |
| US10783675B2 |
Weapon targeting system
A wearable electronic device displays an impact location that shows where a projectile fired from a weapon will hit a target and displays a bullseye location that shows a desired location where to hit the target. The wearable electronic device indicates firing the weapon when the impact location overlaps with the bullseye location. |
| US10783672B2 |
Makeup part generating apparatus, makeup part utilizing apparatus, makeup part generating method, makeup part utilizing method, non-transitory computer-readable recording medium storing makeup part generating program, and non-transitory computer-readable recording medium storing makeup part utilizing program
A makeup part generating apparatus includes a drawing receiver that receives a drawing operation of a makeup part image that is to be overlaid on a facial image, an information acquiring unit that acquires, at each time point in a process of the drawing operation, a progress image that is an image drawn by the time point, and a drawing technique used at the time point, and an information processor that records and outputs makeup part information including, in a time-series manner, image information indicating the progress image, and technique information indicating at least one of the drawing technique and a makeup technique that is an application technique of a cosmetic corresponding to the drawing technique. |
| US10783664B2 |
Method for setting a camera
A method for setting a camera, in particular of a monitoring device, comprising a recording of an image of a region to be monitored, an analysis of the recorded image to associate at least one image region of the image with an object, identification of the object on the basis of the acquired image region and ascertainment of a size of the object by access to stored size information of the identified object and a scaling of the image region associated with the object in the recorded image to scale the remaining acquired image and/or to determine a distance of the camera to the acquired object. |