| Document | Document Title |
|---|---|
| US09331713B2 |
Encoding apparatus, control method of encoding apparatus, and memory device
According to an embodiment, an encoding apparatus includes a parameter holding unit configured to hold a parameter; an error-detecting code holding unit configured to hold an error-detecting code that is generated from the parameter; an error detecting unit configured to detect an error in the parameter, which is held in the parameter holding unit, with the use of the error-detecting code held in the error-detecting code holding unit; an error correcting unit configured to correct the error detected by the error detecting unit; a selecting unit configured to select the parameter that has been subjected to error correction by the error correcting unit; and an encoding unit configured to encode data with the use of the parameter selected by the selecting unit. |
| US09331711B2 |
Method for processing a measured-value signal determined in an analog manner, a resolver system for implementing the method and a method for determining an output current of a converter
In method for processing a measured-value signal determined in an analog manner and a resolver system for implementing the method, the measured-value signal being supplied to a delta-sigma modulator, which makes a bit stream, particularly a one-bit data stream, available on the output side, in particular, whose moving average corresponds to the measured-value signal, the bit stream being supplied to a first digital filter, which converts the bit stream into a stream of digital intermediate words, that is a multibit data stream, the first digital filter having three serially arranged differentiators, the bit stream being clocked at a clock frequency fS, that is, at a clock-pulse period TS=1/fS, and therefore the stream of digital intermediate words being clocked, and thus updated, at a clock-pulse frequency fD, that is, at a clock-pulse period TD=1/fD, the output signal of the first digital filter being supplied to a second digital filter, the second digital filter having as its output data-word stream the difference between a first and a second result data-word stream, the first and second result data-word stream being determined around a first and second time interval from the intermediate data-word stream, the first and second time interval being situated at a distance in time T1, the first result data-word stream being determined as a time-discrete second derivation with time scale TD and the second result data-word stream being determined as a time-discrete second derivation with time scale TD. |
| US09331709B2 |
Analog-to-digital converter
An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented. |
| US09331705B2 |
Timing adjustment circuit, clock generation circuit, and method for timing adjustment
A timing adjustment circuit includes a detection unit to generate a detection signal in response to a first clock having a duty cycle of 50% and a first frequency, a second clock having a duty cycle of 50% and a second frequency that is half the first frequency, and a third clock having a duty cycle of 50%, the second frequency, and a phase displacement of 90 degrees relative to the second clock, the detection signal indicating timing relationship between the first clock and the second and third clocks, a low-pass filter to receive the detection signal, and a variable-delay circuit to adjust relative timing relationship between the first clock and the second clock in response to an output of the low-pass filter such that a center point of a pulse of the first clock is aligned with a center point of a pulse of the second clock. |
| US09331703B1 |
Sample rate converter
Techniques and mechanisms implement a sample rate converter for resampling data, such as audio data. The resampling may be based on a resampling clock. As the frequency of the resampling clock varies (e.g., due to jitter, rate adjustment, etc.), a control loop feedback mechanism can detect the variations and gradually correct the sampling rate of the resampled data. |
| US09331702B2 |
Apparatuses and methods for compensating for power supply sensitivities of a circuit in a clock path
Apparatuses and methods for compensating for differing power supply sensitivities of a circuit in a clock path. One such method includes altering signal timing of at least one of reference and feedback clock signals differently according to variations in power supply voltage to compensate for differences in delay power supply sensitivities of delays of a forward clock path and of a feedback clock path. Another example method includes providing an output clock signal in phase with an input clock signal and compensating for delay error between delays used in providing at least some of the delay of the output clock signal relative to the input clock signal by providing delays having power supply sensitivities resulting in a combined power supply sensitivity that is inverse to the delay error. |
| US09331699B2 |
Level shifters, memory systems, and level shifting methods
Level shifters, memory systems, and level shifting methods are described. According to one arrangement, a level shifter includes an input configured to receive an input signal in a first voltage domain, an output configured to output an output signal from the level shifter in a second voltage domain different than the first voltage domain, a plurality of pull-down devices, and wherein one of the pull-down devices is coupled with the input and the output, a plurality of cross-coupled devices coupled with the pull-down devices and configured to provide transitions in the output signal as a result of transitions in the input signal, a plurality of current limiting devices coupled with the cross-coupled devices and configured to limit a flow of current from a source to the cross-coupled devices, and a plurality of dynamic devices configured to selectively provide charging current from the source to the cross-coupled devices. |
| US09331697B2 |
Output apparatus and output system including the same
An output apparatus includes an output driving unit configured to drive a final output signal; an output compensating signal generation unit configured to generate a delayed output signal by delaying the output signal by a predetermined time, and generate an output compensating signal based on the delayed output signal and the output signal; and an output driving compensation unit configured to compensate for the final output signal to a level opposite to a level to which the final output signal is driven. |
| US09331694B2 |
Capacitive coupling based proximity sensor
A capacitive coupling based proximity sensor is disclosed. In some embodiments, a sensor embedded in a mobile device comprises a transmitter configured to transmit a transmit signal and a receiver configured to receive a receive signal via capacitive coupling between the receiver and the transmitter as well as a circuit configured to detect human proximity to the mobile device in the event that the receive signal does not sufficiently match the transmit signal and configured to generate an output signal indicating human proximity to the mobile device that is employed to facilitate an appropriate response. |
| US09331693B2 |
Touch display device
A touch display device including a substrate, a display medium layer disposed above the substrate, first side electrodes and a sensing electrode disposed above the substrate is provided. The display medium layer includes charged particles and micro-structures connected to each other. Each of the micro-structures holds a portion of the charged particles, and has a first side wall which is not parallel to the substrate. Each of the first side electrodes is disposed above the first side wall of each of the micro-structures. The micro-structures are disposed between the substrate and the first side electrodes. A touch sensing unit is composed by the sensing electrode and the first side electrodes. |
| US09331692B2 |
Luminous keyboard
A luminous keyboard includes a lateral-emitting type illumination element, a light guide panel, a sensing circuit pattern, a light-transmissible substrate, a supporting plate, and plural keys. When one of the keys is moved toward the sensing circuit pattern, the sensing circuit pattern generates a corresponding non-contact key signal. The lateral-emitting type illumination element is used for providing a light beam to the light guide panel. Consequently, the light beam can be diffused to the whole light guide panel. The light guide panel has plural light-guiding dots for collecting and scattering the light beam. The light-transmissible substrate is arranged between the light guide panel and the plural keys, and has plural light diffusion structures corresponding to the plural keys. The light beam scattered upwardly by each light-guiding dot is sequentially transmitted through the corresponding light diffusion structure and the supporting plate and directed to the corresponding key. |
| US09331687B2 |
Power-up circuit of semiconductor apparatus
A power-up circuit of a semiconductor apparatus using a plurality of external power voltages is configured to determine a stableness of the plurality of external power voltages through relative comparison of the plurality of external power voltages, and to activate a power-up signal. |
| US09331685B2 |
Comparator system
A comparator system includes: a clock node configured to supply a clock signal; a comparator configured to compare a signal of a first input node with a signal of a second input node in synchronization with the clock signal; and a first variable capacitance coupled between the first input node and the clock node. |
| US09331682B2 |
Method and apparatus for monitoring a signal
A method of monitoring an analog signal output from a sensor comprising comparing the amplitude of the analog signal to a first high and low threshold, setting a primary monitoring signal to a first value when the amplitude of the analog signal exceeds the first high threshold, setting the primary monitoring signal to a second value when the amplitude of the analog signal decreases below the first low threshold, comparing the amplitude of the analog signal to a second high and low threshold, setting a secondary monitoring signal to a first value when the amplitude of the analog signal exceeds the second high threshold, setting the secondary monitoring signal to a second value when the amplitude of the analog signal decreases below the second low threshold, comparing the primary and secondary monitoring signals and determining from the comparison whether an error exists with the monitoring of the analog signal. |
| US09331673B2 |
Integrated circuit operating active circuitry and chip pads in different operating modes and at different voltage levels
An integrated circuit having an external connection pad and an active circuit for generating signals to be output from the integrated circuit by means of the pad, the integrated circuit including an interface circuit associated with the pad, the interface circuit including a latch coupled between the pad and an output of the active circuit, the latch being capable of operating in a first mode in which the state of the pad follows the state of the output of the active circuit and a second mode in which the state of the pad is held by the latch. |
| US09331671B2 |
Automatic power switching and power harvesting in thin oxide open drain transmitter circuits, systems, and methods
A power harvesting circuit includes a new transmitter topology that ensures that no junction of thin oxide transistors forming the power harvesting circuit will experience a voltage across junctions of the transistors that is more than a maximum tolerable junction voltage. A supplemental power feed circuit operates to provide a supplemental feed current to components in a transmitter circuit when power harvested from a receiver circuit is insufficient to adequately power these components of the transmitter circuit, which may occur during high frequency operation of communications channels coupling the transmitter and receiver circuits. The supplemental power feed circuit also operates to sink a shunt current when power harvested from the receiver circuit is more than is needed to power the components in the transmitter circuit. |
| US09331669B2 |
High rejection surface acoustic wave duplexer
Filter devices and duplexer devices are disclosed. A filter device includes two or more surface acoustic wave resonators, including at least a first shunt resonator, formed on a surface of a substrate. A ground conductor formed on the surface of the substrate connects the first shunt resonator to a ground pad. At least a portion of an edge of the ground conductor is shaped as a plurality of serrations. |
| US09331667B2 |
Methods, systems, and apparatuses for temperature compensated surface acoustic wave device
Embodiments described herein may provide a temperature-compensated surface acoustic wave (TCSAW) device, a method of fabricating a TCSAW device, and a system incorporating a TCSAW device. The TCSAW device may include a pyroelectric substrate, a plurality of electrodes formed on a first surface of the pyroelectric substrate, an amorphous silicon layer formed over the plurality of electrodes, and a temperature compensating layer formed over the amorphous silicon layer. |
| US09331666B2 |
Composite dilation mode resonators
This disclosure provides systems, methods and apparatus related to acoustic resonators that include composite transduction layers for enabling selective tuning of one or more acoustic or electromechanical properties. In one aspect, a resonator structure includes one or more first electrodes, one or more second electrodes, and a transduction layer arranged between the first and second electrodes. The transduction layer includes a plurality of constituent layers. In some implementations, the constituent layers include one or more first piezoelectric layers and one or more second piezoelectric layers. The transduction layer is configured to, responsive to signals provided to the first and second electrodes, provide at least a first mode of vibration of the transduction layer with a displacement component along the z axis and at least a second mode of vibration of the transduction layer with a displacement component along the plane of the x axis and they axis. |
| US09331664B2 |
Marchand balun and power amplifier using the same
A Marchand balun has a primary transmission line with a width smaller than the two secondary transmission lines. The two secondary transmission lines also have different widths and lengths. This arrangement provides an imbalance between the widths and lengths of the transmission lines. It has been found that this imbalance can enable improved amplitude unbalance and phase unbalance. |
| US09331659B2 |
Integrated circuit architecture with strongly coupled LC tanks
An integrated circuit for a radio frequency (RF) circuit such as a voltage controlled oscillator or an injection locked frequency divider is provided. The integrated circuit architecture includes a primary LC tank circuit comprising a first inductor and a first capacitive device connected in parallel and one or more secondary LC tank circuits, each comprising an inductor and a capacitive device connected in parallel. Each of the one or more secondary LC tank circuits is strongly coupled to the primary LC tank circuit and to each other either electrically, magnetically or a combination of electrically and magnetically. |
| US09331653B2 |
Apparatus and methods for envelope shaping in power amplifier systems
Apparatus and methods for envelope shaping in power amplifier systems are provided. In certain implementations, a power amplifier system includes a modulator for generating a RF signal, a power amplifier for amplifying the RF signal, a gain control circuit for controlling the gain of the power amplifier, and an envelope tracking system for controlling a voltage level of the power amplifier's supply voltage based on an envelope signal corresponding to the RF signal's envelope. The gain control circuit includes a gain adjustment table, and the envelope tracking system includes an envelope shaping circuit including an isodistortion table. The isodistortion table can be used to map the envelope signal to a shaped envelope signal so as to maintain a substantially constant distortion in the system's transmit and/or receive bands across the envelope signal's range. |
| US09331650B2 |
Audio system
An audio system includes a channel (10) for processing signals. The channel (10) includes a processing module (50) that follows a chain of modules (40) wherein the chain (40) includes a preceding processing module (45). The following processing module (50) is coupled to the preceding processing module (45) in the chain of modules (40) for receiving the output signal (25). The channel (10) further includes a combiner (60). The combiner (60) has two inputs, a first input (65) receives the signal (30) to be processed in the channel (10), and a second input (70) receives a reference signal (75). The combiner (60) further includes an output (80) coupled to an input of the preceding processing module (45) in the chain (40). By coupling a combination of the signal (30) to be processed and the reference signal (75) to the input (55) of the preceding processing module (45) in the chain (40) and by having a correction signal (90) from the processing unit (85) generated in response to a modification of the reference signal (75) in the output signal (25) of the preceding processing module (45) in the chain (40), the amount and type of processing in the preceding processing module (45) in the chain (40) can be estimated in the processing unit (85) and be corrected for in the following processing module (50). |
| US09331645B2 |
Method for compensating a power amplification unit of a wireless RF module
The present invention relates to a method for compensating a power amplification unit of a wireless RF module that includes a baseband unit, a RF transceiver unit, a power amplification unit and a control unit. The baseband unit is connected to the power amplification unit through the control unit and the RF transceiver unit. Based on the characteristic of the power amplification unit, the baseband unit provides a control signal to regulate the output signal characteristic of the power amplification unit, or provides a RF transceiver unit control signal to regulate the characteristics of the RF signal being transmitted by the RF transceiver unit to the power amplification unit, or to regulate the characteristics of the baseband signal being transmitted to the RF transceiver unit, enabling the characteristics of the output signal of the power amplification unit to meet the specifications of the related system. |
| US09331643B2 |
Methods and devices for thermal control in power amplifier circuits
Methods of turning on and/or turning off amplifier segments in a scalable periphery amplifier architecture are described in the present disclosure. The turning on and/or turning off the amplifier segments according to the various embodiments of the present can reduce spectral splatter in adjacent channels. In some embodiments, amplifier performance and efficiency can be improved by dissipating heat more uniformly. |
| US09331636B2 |
Time and amplitude alignment in envelope tracking amplification stage
The invention relates to a method of calibrating an envelope path and an input path of an amplification stage including an envelope tracking power supply, the method comprising: generating input signals having a known relationship for each of the input and envelope paths; and varying an amplitude and a delay of the signal in one of the envelope and input paths in order to reduce the variation in the power detected in a signal at the output of the amplification stage. |
| US09331635B2 |
Quadrature modulator
A quadrature modulator includes a first switched capacitor power amplifier that amplifies a first high-frequency signal, a second switched capacitor power amplifier that amplifies a second high-frequency signal, a first combiner which includes at least one pair of winding wires, one winding wire in one pair being disposed on a primary side to which the amplified first high-frequency signal and the amplified second high-frequency signal are separately input and the other winding wire in the one pair being disposed on a secondary side, the first combiner combining the input amplified first high-frequency signal and the input amplified second high-frequency signal to generate a quadrature modulation signal from the secondary side, a first inductor disposed between the first switched capacitor power amplifier and the primary side of the first combiner, and a second inductor disposed between the second switched capacitor power amplifier and the primary side of the first combiner. |
| US09331631B2 |
Direct connection of lead bar to conductive ribbon in a thin film photovoltaic device
Thin film photovoltaic devices that include at least one lead bar extending through a connection aperture defined in the encapsulation substrate are provided. The photovoltaic device can include: a transparent substrate; a plurality of photovoltaic cells on the transparent substrate; a first conductive ribbon electrically connected to a first photovoltaic cell; an encapsulation substrate laminated to the transparent substrate such that the plurality of photovoltaic cells and the conductive ribbon are positioned between the transparent substrate and the encapsulation substrate; and, a first lead bar extending through a first connection aperture defined in the encapsulation substrate. The first lead bar is electrically connected to the first conductive ribbon. For example, a meltable conductive material can be connected to the first lead bar and to the first conductive ribbon to establish an electrical connection therebetween. Methods are also provided for electrically connecting a lead to a thin film photovoltaic device. |
| US09331629B2 |
Photovoltaic frame fastener
A photovoltaic frame fastener is provided. In one aspect, a photovoltaic frame attachment apparatus includes a strut or rail defining a generally U-shaped channel and a snap-in clip or fastener. In another aspect, a single-piece fastener includes a strut-engaging surface, at least one flexible wing matable with an opening in a strut, a flexible tongue internally projecting in a central manner from a top wall of a body, and a slot adapted to receive a portion of a photovoltaic panel frame. Yet another aspect of a photovoltaic frame fastener includes laterally projecting tabs abutting against a top of a strut. |
| US09331627B2 |
Control apparatus for AC motor
According to a control apparatus for an AC motor, a switching section selects a two-phase control current value as a current fixing value, when a first current detection value of a first phase of the AC motor and a second current detection value of a second phase of the AC motor are normal. The switching section selects an one-phase control current value, which is calculated based on a normal phase current detection value, which is a value of a normal phase and is one of the first and second current detection values, as the current fixing value, when an abnormality is detected in part of the first and second current detection values, and a predetermined period has elapsed from the detection of the abnormality. |
| US09331624B2 |
Thrust ripple mapping system in a precision stage and method thereof
The present invention proposes a thrust ripple mapping system in a precision stage with the thrust ripple mapping system comprising a moving stage, a load cell, a plurality of motors and a processing component. The load cell is coupled to the moving stage. The motors are employed in moving the load cell and the moving stage. The processing component takes a thrust force measurement at each of a plurality of moving increments of the load cell. |
| US09331618B2 |
Magnetic pole position detector for synchronous motor
A magnetic pole position detector includes, a voltage command unit that generates high-frequency voltage command in a dq coordinate system, a three-phase transformation unit that transforms the high-frequency voltage command in the dq coordinate system to high-frequency voltage command in a three-phase coordinate system by using an estimated magnetic pole position, a current detection unit that detects three-phase current fed from a power converter for generating drive power, a dq transformation unit that transforms the detected three-phase current to current in the dq coordinate system by using the estimated magnetic pole position, an estimated magnetic pole position calculation unit that calculates a new estimated magnetic pole position to be used in three-phase dq transformations, and a magnetic pole position confirmation unit that confirms that, when converging on a certain position, the estimated magnetic pole position is the magnetic pole position at the time when the synchronous motor is started. |
| US09331610B2 |
Electromotive furniture drive
An electromotive furniture drive includes an electric motor, the rotational direction of which can be reversed, a motor controller, a manual control, a battery unit, and a mains power supply device. A speed-reducing transmission is connected downstream of the electric motor and a further transmission is connected downstream of each speed-reducing transmission and the battery unit has at least one battery. To enable simple, economical and easy installation, in particular in tight installation spaces, the furniture drive has a coupling device which includes a charging device for charging the at least one battery of the battery unit. The coupling device also has a reference device, which is connected to a charging device The furniture drive is especially suited for slatted bed frames and armchairs. |
| US09331609B1 |
Electrical motors and methods thereof having reduced electromagnetic emissions
Motors and method of operation thereof operable in a running mode wherein the motor operates at a constant speed, and operable in a park mode wherein the motor is dynamically parked. The motor is housed within a housing and includes a rotating park disk configured to cause the motor to dynamically park. A park wire electrically couples the park disk to a switch configured to selectively switch the motor between the running mode and the park mode, and a power wire electrically couples the park disk to a power source. The park disk is electrically isolated from the power source during operation of the motor in the running mode and the park wire is electrically connected to the power source through the park disk and the power wire during operation of the motor in the park mode. |
| US09331606B2 |
Device with suspended beam and piezoresistive means of detecting displacement of the beam and method of manufacturing the device
A device with a suspended beam and piezoresistive means of detecting displacement of the beam and a method of manufacturing the device are disclosed. The device comprises a support, a suspended beam, moving parallel to the plane of the support, and means of detecting displacement, comprising at least two piezoresistive strain gauges that are not in line with each other. The beam is suspended through detection means. The two gauges are located on two opposite lateral faces of the beam respectively. |
| US09331602B2 |
Vibrator, oscillator, electronic device, and moving object
A MEMS vibrator includes: a substrate; a base portion which is disposed on the substrate; and a plurality of vibration portions which extends in a direction that intersects with a normal line of the substrate from the base portion. In a planar view, when a length of the vibration portion in a direction in which the vibration portion extends from the base portion is L, and a length of the vibration portion in a direction that intersects with a direction in which the vibration portion extends from the base portion is W, a dimension ratio (L/W) of the vibration portion satisfies a relationship in which 0.2≦(L/W)≦7.0. |
| US09331601B2 |
Inverter with power cell of dual structure
The present disclosure relates to an inverter with power cell of dual structure for use in high input voltage by changing a conventional 6-level cascaded H-bridge multilevel inverter to thereby reduce product development cost, manufacturing cost and volume of the product, the inverter including a first SMPS (Switching Mode Power Supply) connected to a first power cell region, a second SMPS connected to a second power cell region and a controller connecting the first and second SMPSs, where each phase is formed by serially connecting a plurality of power cells formed with a plurality of stages operated by receiving a power supplied from a phase shift transformer, and each of the plurality of power cells is mutually connected, and includes the first power cell region and the second power cell region independently operating. |
| US09331599B2 |
Multilevel electric power converter
There is described a multilevel electric power converter circuit comprising: Ns switching elements connected in series in a closed loop; NAE additional elements, the additional elements being one of a direct current source and at least one passive element, connected within the closed loop such that each additional element is connected to four of the switching elements, the ratio of a number of additional elements NAE to a number of switching elements NS corresponding to NS=2NAE+2; and one of a load and an alternating current source connected across the closed loop at nodes between adjacent switching elements that are separate from nodes to which the additional elements are connected. |
| US09331598B2 |
Power factor correction device, power supply, and motor driver
There is provided a power factor correction device including, a first switch switching input power to adjust a phase difference between a current and a voltage of the input power, a second switch switched on before the first switch is switched on to form a transfer path for residual power in the first switch, a first inductor charging and discharging energy according to switching of the first switch, and a second inductor adjusting an amount of current flowing through the second switch according to switching of the second switch, wherein the first inductor and the second inductor are inductively coupled. |
| US09331597B2 |
Latching comparator
A latching comparator includes a switching logic circuit coupled to receive a first signal from a first signal circuit, and a second signal from a second signal circuit. The switching logic circuit is further coupled to receive a latching signal that is a rectangular pulse waveform in either a first or a second state. An output circuit having an input terminal is coupled to the switching logic circuit. The input terminal of the output circuit is coupled to receive both the first and second signals to compare the first signal and second signal when the latching signal is in the first state. The input terminal of the output circuit is coupled to receive only one of the first and second signals when the latching signal is in the second state. |
| US09331595B2 |
Multi-level inverter
A multi-level inverter includes: a rectifying unit to rectify received a three-phase voltage; a smoothing unit to receive the rectified voltage and provide the rectified voltage as voltages having different levels to first to third different nodes; and an inverter unit including a plurality of switch units to transfer the voltages having three levels provided from the smoothing unit, wherein the inverter unit includes a first switch unit provided between the first node and a first output terminal, a second switch unit provided between the second node and the first output terminal, a third switch unit provided between the third node and the first output terminal, a fourth switch unit provided between the first node and a second output terminal, a fifth switch unit provided between the second node and the second output terminal, and a sixth switch unit provided between the third node and the second output terminal. |
| US09331593B2 |
Switching power supply device
In a switching power supply device having low loss in synchronous rectifying switches, exhibiting high power efficiency, and not causing troubles by reverse current in the switches. A secondary control circuit includes a reference voltage circuit to generate a reference voltage having a predetermined potential, and an ON-timing detector circuit to detect an ON timing of a synchronous rectifying switch through monitoring of a terminal voltage of the switch, an OFF-timing detector circuit to detect an OFF timing of the switch, and a timer circuit to be turned on at the ON timing and measure a predetermined period. The threshold voltage consisting of the reference voltage generated by the reference voltage circuit and an offset voltage is applied to the OFF-timing detector circuit during the measurement of the timer circuit, and the threshold voltage consisting of the reference voltage is applied to the OFF-timing detector circuit during the non-measurement. |
| US09331589B2 |
Primary feedback switching power converter controller with intelligent determination of and response to output voltage drops due to dynamic load conditions
The embodiments herein include a primary-side controller for a switching power converter that is capable of receiving a detection signal from a secondary-side detection circuit indicating that an output voltage has reached a condition. The controller determines the appropriate action once a detection signal has been received by distinguishing whether a dynamic load condition has been placed on the power supply versus other operating conditions. |
| US09331584B2 |
Switching power-supply device
A switching power-supply device which includes a control unit configured to perform a switching control; and a resonance current detection unit configured to detect the resonance current flowing through the series resonance circuit.When an absolute value level of the resonance current exceeds a second threshold greater than a first threshold, the control unit inverts the turn on-and-off state of the first switching element or the second switching element at the time when the absolute value level reaches a third threshold between the first threshold and the second threshold. When the absolute value level of the resonance current exceeds the first threshold and does not exceed the second threshold, the control unit inverts the turn on-and-off state of the first switching element or the second switching element at the time when the absolute value level reaches the first threshold. |
| US09331582B2 |
Volt-second integration cable compensation circuit
A power converter (such as a battery charger) includes a cable configured to deliver a source voltage and current to a load, where the cable is anticipated to drop some voltage as the load current increases. The power converter also includes a regulator having a feedback-adjusting transistor configured to gradually compensate for the dropped cable voltage as the load current increases. The transistor has a gate capacitance and a resistance forming an integrator configured to filter a volt-second product of an output waveshape of the converter to derive an average voltage correlated to the load current as the load current increases. The regulator is configured to increase a gate voltage of the transistor through a threshold region of the transistor and gradually turn the transistor on. The transistor is configured to apply an adjusting resistance coupled to a feedback sensing node of the regulator to increase the source voltage to compensate for the cable voltage drop and improve the load voltage regulation. |
| US09331581B2 |
AC-DC voltage converter with low standby power consumption and control method thereof
Disclosed are AC-DC voltage converter circuits and methods for low standby power consumption. In one embodiment, a method can include: (i) detecting operating states of an input power supply, where the input power supply is received by a safety capacitor and provided to a switching power supply circuit after being rectified and filtered; (ii) removing a phantom load when the input power supply operates in a normal operating state; (iii) loading the phantom load when the input power supply operates in an under voltage lock out state; and (iv) when the input power supply operates in the under voltage lock out state, using energy stored in the safety capacitor to supply power to a load of the switching power supply circuit and the phantom load, and disabling a power stage circuit until a voltage of the safety capacitor is reduced to less than a safety threshold value. |
| US09331579B2 |
Power balancing method for multiple module power supply using averaged feedback
A power supply includes power modules. Each of the power modules includes an input stage configured to convert an input voltage into an intermediate voltage, and an output stage configured to output a DC supply voltage according to the intermediate voltage. Input terminals of the input stages in the plurality of power modules are electrically connected in series, and the input stages are configured to be controlled with at least one first common control signal having a common duty cycle. Output terminals of the output stages in the plurality of power modules are electrically connected in parallel, and the output stages are configured to be controlled with at least one second common control signal having a common duty cycle. A method of supplying power is also disclosed herein. |
| US09331576B2 |
Multiple output dual-polarity boost converter
A dual-polarity multiple-output boost converter that includes an inductor coupled in series between a high-side switch and a low-side switch. A first terminal of the inductor is coupled to an output of the high-side switch and the second terminal of the inductor is coupled to an input of the low side switch, with an output of low-side switch being coupled to a reference terminal. A plurality of outputs provide a plurality of output voltages, including a first plurality of outputs to provide a first plurality of different output voltages having a first polarity and at least one second output to provide at least one second output voltage having a second polarity opposite the first polarity. A control circuit is coupled to the high-side switch and the low-side switch to control an on-time of the high-side switch and the low-side switch. |
| US09331572B2 |
Semiconductor device and power conversion device
A switching device includes a power semiconductor chip, and a drive circuit which drives the power semiconductor chip. In the power semiconductor chip, a path through which a main current flows is connected to a first source terminal, and a ground terminal of the drive circuit is connected to a second source terminal of the power semiconductor chip. As a result, a gate drive path is separated from the path through which the main current flows, and therefore, the influence of induced electromotive force which is generated due to source parasitic inductance, on a gate-source voltage, is reduced. |
| US09331571B2 |
Power converter with automatic on-time extension function and operating method thereof
A power converter is disclosed. The power converter includes a comparator and a timing generator. The comparator compares a first input signal with a second input signal to provide a control signal. The timing generator is coupled to the comparator. The timing generator includes a plurality of timing generating units, a logic unit, and a calculation unit. The timing generator generates a plurality of timing signals through the timing generating units and the logic unit according to the control signal, and the calculation unit forms a pulse width modulation (PWM) signal according to the timing signals. At least a part of the timing signals are overlapped. |
| US09331569B1 |
Current generating circuit, current generating method, charge pumping circuit and charge pumping method
A current generating circuit, which comprises: a first capacitor, comprising a first terminal and a second terminal; a second capacitor, comprising a first terminal and a second terminal; a first charge adjusting path, arranged for adjusting charges of the first capacitor according to a first charge adjusting voltage; a second charge adjusting path, arranged for adjusting charges of the second capacitor according to the first charge adjusting voltage; and a current generating path, coupled to the first capacitor and the second capacitor, arranged for generating a target current based on a difference between a first voltage provided by the first capacitor and a second voltage provided by the second capacitor. |
| US09331567B2 |
Systems and methods for reducing electromagnetic interference using switching frequency jittering
System and method are provided for regulating a power converter. The system includes a signal processing component configured to receive a first input signal and a second input signal, process information associated with the first input signal and the second input signal, and output a drive signal to a switch based on at least information associated with the first input signal and the second input signal. The first input signal is associated with at least a feedback signal related to an output voltage of the power converter. The second input signal is associated with at least a primary current flowing through a primary winding of the power converter. The signal processing component is further configured to change a peak value of the primary current within a first predetermined range, and change the switching frequency of the power converter within a second predetermined range. |
| US09331564B2 |
Connecting a photovoltaic array at a high open circuit voltage
For connecting a PV array via an inverter to an AC power grid, at first a DC link at the input side of the inverter is pre-charged from the AC power grid. A link voltage of the DC link is adjusted to a pre-set value with the inverter connected to the AC power grid, the pre-set value being lower than an open circuit voltage of the PV array, and then the PV array at its open circuit voltage is directly connected to the DC link, while the link voltage is continuously adjusted to the pre-set value. |
| US09331561B2 |
Method to minimize input current harmonics of power systems such as ESP power systems
Disclosed is a method for the improvement of the line quality in a system, in which a common feeding (1), via at least one distribution transformer (3), feeds at least two non-linear loads (11) drawing non-sinusoidal currents from the common feeding (1), wherein between the common feeding (1) and the distribution transformer (3) there is at least one primary side transformer line (2) and between the at least one distribution transformer (3) and the loads (11) there is at least one lower voltage secondary side transformer line (22), wherein at least one active filter (24) attached to at least one lower voltage secondary side transformer line (22) is used for the attenuation or elimination of higher order harmonics experienced by the common feeding (1). Furthermore a high power distribution system for use of such a method is disclosed, in particular for the operation of an electrostatic precipitator. |
| US09331560B2 |
Heat engine for converting low temperature energy to electricity
The disclosure relates to heat engines that operate using low temperature differentials. A Stirling engine is modified to provide a new heat engine that has no contained working fluid. The new heat engine flexible cylinders and the pistons are moved vertically upward by cables and vertically downward by gravity. |
| US09331559B2 |
Kinetic energy harvesting methods and apparatus
A system, method, and apparatus for kinetic energy harvesting are disclosed. An example kinetic energy harvesting apparatus includes a tubular-shaped magnet housing, a first end-cap magnet configured to connect to a first end of the magnet housing and a second end-cap magnet configured to connect to a second end of the magnet housing. The apparatus also includes a first wire coil configured to be connected to the magnet housing between the first end and a center of the magnet housing and a second wire coil configured to be connected to the magnet housing between the second end and the center of the magnet housing. The apparatus further includes a central magnet configured to be located within the magnet housing between the first end and the second end such that the central magnet is suspended within the magnet housing. |
| US09331556B2 |
Brush motor and cooling fan incorporating the motor
A brush motor includes a stator and a rotor. The stator includes multiple magnets attached to an inner surface of a stator housing and a brush assembly fixed relative to the housing. The rotor includes a rotor core and a commutator located in a receiving space defined by a mounting portion and an annular sidewall of the rotor core. The commutator includes multiple conductive segments, each of which has a leg penetrating the rotor core and connected with windings on the rotor core. |
| US09331555B2 |
Apparatus, brush holder and system for monitoring brush wear
An apparatus, brush holder and system are provided. The apparatus includes a main body configured for attachment to a brush holder, and a proximity sensor on the main body. The proximity sensor is configured for detecting the presence of a brush located at least partially inside the brush holder. The apparatus is configured to transmit a wireless signal to a remote location, and the wireless signal is transformable into an indication of a remaining life of the brush. |
| US09331554B2 |
System and method for controlling motor
Provided are a system for controlling a motor and a method thereof. The system includes: a data storage unit in which data relating to a thermal equivalent circuit of the motor is stored; a temperature measuring unit which measures a temperature of a cooling medium which enters a cooling flow path portion; a rotation speed measuring unit which measures a rotation speed of a rotor; a driving electric current measuring unit which measures a driving electric current of the motor; a permanent magnet temperature estimating unit which estimates a temperature of the permanent magnet portion of the rotor; and a driving controller controls driving of the motor. |
| US09331550B2 |
Air cooling of a motor using radially mounted fan
A motor cooling system is provided comprising an electric motor including a rotor having first and second axial ends, and a stator having first and second axial ends, a motor housing surrounding the motor including an air chamber extending around the motor and axially along the motor length, a motor enclosure enveloping the motor housing, and a cooling fan radially mounted to the motor enclosure and adapted to operatively cool said electric motor. |
| US09331548B1 |
Devices and systems for generating sustainable energy from traffic
A device that is installed underneath a predetermined surface to harness gravity from the weight of overpassing traffic to produce and amplify mechanical energy. The weight received forces or pushes the device downward thereby translating the weight into mechanical energy. The amplification of mechanical energy is achieved through the decrease in the cross section area from the upper portion to the lower portion of the device. Also provided herein is a system wherein the device is connected to a piston, a crankshaft and an electricity generator so that the mechanical energy can be further converted into rotational motion and ultimately, electricity. |
| US09331546B2 |
In-wheel motor and in-wheel driving device
An in-wheel motor includes: a motor rotor installed inside a wheel of a vehicle; and a plurality of motor stators installed on the circumference of the motor rotor so as to be separated from each other, and forming magnetic fields to rotate the motor rotor. |
| US09331538B2 |
Winding for a rotating electric machine and method for manufacturing same
A winding for a rotating electric machine includes conductive bars having straight parts and end windings and terminal portions of the end windings that are connected together. A protective cap is disposed on at least a portion of each respective connected end winding terminal portion. An electrical insulating material is disposed between each end winding terminal portion and respective protective cap and a seal is inside each protective cap. |
| US09331530B2 |
Laminated core of motor having structure suitable for insulation coating
Disclosed herein is a laminated core of a motor including: a first core sheet including a first rounded core base, a plurality of first teeth which are radially formed on the first core base, and first tooth ears formed at the end of each of the first teeth; and a second core sheet including a second rounded core base, a plurality of second teeth which are radially formed on the second core base, and second tooth ears formed at the end of each of the second teeth, the second core sheet having the same shape as the first core sheet but being smaller than the first core sheet, wherein the second core sheet is located at the lowermost part, one or more the first core sheets are laminated on the second core sheet, and another second core sheet is located at the uppermost part. |
| US09331528B2 |
Stator tooth assembly for axial flux stator and methods of assembling the same
In one aspect, a three-phase axial flux stator is provided. The stator includes a plurality of stator modules oriented in an axial direction, and each of the stator modules includes a pair of teeth connected by a yoke section. The stator also includes a plurality of windings, each of the windings wound around one of the stator modules. The stator modules and the windings produce a three-phase flux in an axial direction. |
| US09331525B2 |
Energy access control
A method of controlling access to an electrical power network, comprising: receiving a power network access rule from a power network, the power network access rule defining an access condition which permits a device to access the power network; receiving a device usage rule, the device usage rule being a condition when the device is permitted use of the power network; comparing the device usage rule with the received power network access rule; and permitting the transfer of energy between the power network and the device upon a positive comparison between the device usage rule and the power network access rule. |
| US09331523B2 |
Power control device and power control method
A power control device is provided, the power control device comprising a first conversion part configured to convert DC voltage power into AC voltage power, the DC voltage power being output from a power generation part configured to generate power using natural energy; a second conversion part configured to convert the AC voltage power output from the first conversion part into DC voltage power; and a controller configured to control output power of the second conversion part based on a voltage value of the power output from the power generation part when supply of power from an external power system is stopped. |
| US09331522B2 |
Backup power supplying device having programmable current-balancing control
A backup power supplying device having programmable current-balancing control includes at least two power modules connected in parallel. The power module includes a power converter, a current sensing component, a potential tuner, a microprocessor, a current-balancing control circuit and an output voltage controller. The current sensing component senses an output current of the power converter to generate a current sensing signal. The microprocessor controls the potential tuner to generate a tuning signal, and receives a mode signal to control the power module to operate in a power supply or sleep mode. The current-balancing control circuit receives the current sensing signal, the tuning signal and the mode signal. When the power module operates in the sleep mode, an output voltage of the power converter is a sleep voltage; a voltage level of the sleep voltage is lower than a voltage level of a supply voltage by a predetermined voltage value. |
| US09331520B2 |
Inductively coupled charger
A device includes a charge controller to regulate a battery output voltage based on an input voltage and an input current received from a charging circuit. A loop controller monitors the input voltage and the input current to generate a feedback signal to adjust the input voltage to the charge controller. |
| US09331518B2 |
Adaptive multi-pathway wireless power transfer
Adaptive multi-pathway wireless charging is described. In one aspect, embodiments enable one or more wireless charging pathways to be established concurrently in a wireless charging environment. The wireless charging pathways use same or different frequencies, powers, wireless power transfer (WPT) standards, and WPT configurations. Embodiments for adaptively configuring wireless charging based on detected events or changes in WPT characteristics are also provided. |
| US09331517B2 |
Electronic device, method, and storage medium
An electronic device includes a first unit that wirelessly receives power from a power supply apparatus, and a control unit that executes control, if an external apparatus, including a second unit that wirelessly receives power from the power supply apparatus, and the electronic device are connected, to select at least one of the first unit and the second unit. |
| US09331516B2 |
Single power supply level shifter
A single power supply level shifter has first and second inverters in tandem that invert an input signal from a first voltage domain and provide a first inverted signal and an output signal in a second voltage domain. A charging control circuit charges a capacitor towards the second voltage when the input signal is high, and conducts a discharge current from the capacitor during a transition of the input signal from high to low to accelerate a corresponding transition of the first inverted signal from low to high. A third inverter controls a current reduction transistor in series with the first inverter, and a third control transistor connected between the input and the charging control circuit to accelerate the flow of discharge current during the transition of the input signal from high to low. |
| US09331515B2 |
System for charging an energy store, and method for operating the charging system
The invention relates to a system for charging at least one energy storing cell (5) in a controllable energy store (2) that is used to control and supply electric energy to an n-phase electric machine (1), wherein n ≧1. The controllable energy store (2) has n parallel energy supply branches (3-1, 3-2, 3-3), each of which has at least two serially connected energy storing modules (4), each said energy storing module comprising at least one electric energy storing cell (5) with a corresponding controllable coupling unit (6). The energy supply branches (3-1, 3-2, 3-3) can be connected to a reference bus (T-), and each energy supply branch can be connected to a phase (U, V, W) of the electric machine (1). The coupling units (6) bridge the respective corresponding energy storing cells (5) or connect same into the respective energy supply branch (3-1, 3-2; 3-3) dependent on control signals. The aim of the invention is to allow at least one energy storing cell (5) to be charged. This is achieved in that a neutral point (S) of the electric machine (1) and the reference bus (T-) can be connected to a secondary side (9) of a charging transformer (10). |
| US09331507B2 |
Control apparatus and method for conducting fast battery charge
A battery charging system includes a charging source, at least one battery cell, a battery internal temperature sensor configured to measure an internal temperature of the at least one battery cell responsive to charging of the at least one battery cell by the charging source, and a charge controller. The charge controller is configured to receive indications of the internal temperature of the at least one battery cell over time, to identify an indication that the at least one battery cell is at a point of full charge based on rate of change of the internal temperature, and to interrupt power delivery from the charging source to the at least one battery cell responsive to the indication that the at least one battery cell is at the point of full charge. |
| US09331504B2 |
Method for charging a battery
The disclosure relates to a method for charging a battery having at least one battery cell. A first connection of a charging device is connected to a first pole of the at least one battery cell by a rectifying device. The rectifying device is set up such that charging current can flow. The disclosure further relates to a charging device, a battery, and a motor vehicle, which are configured to carried out the method. |
| US09331498B2 |
Power generation system that provides efficient battery charger selection
Some embodiments relate to a power generation system. The power generation system includes a first generator and a first battery charger. The first battery charger is adapted to charge a first battery and a second battery. The first battery and the second battery are each adapted to provide power to start the first generator. The power generation system further includes a controller that determines a state of charge for each of the first battery and the second battery. Based on the state of charge for each of the first battery and the second battery, the controller determines which of the first battery and the second battery receives charging current from the first battery charger. |
| US09331497B2 |
Electrical energy storage unit and control system and applications thereof
An electrical energy storage unit and control system, and applications thereof. In an embodiment, the electrical energy storage unit includes a battery system controller and battery packs. Each battery pack has battery cells, a battery pack controller that monitors the cells, a battery pack cell balancer that adjusts the amount of energy stored in the cells, and a battery pack charger. The battery pack controller operates the battery pack cell balancer and the battery pack charger to control the state-of-charge of the cells. In an embodiment, the cells are lithium ion battery cells. |
| US09331496B2 |
Contactless power-feed equipment
Contactless power-feed equipment includes: a power-supply device that outputs an AC constant current having a predetermined oscillation frequency to a main induction line; a primary coil provided on the main induction line connected to the power-supply device; a secondary coil that forms an insulating transformer with the primary coil and is connected in parallel with the sub induction line, a resonance capacitor that is connected in parallel with the secondary coil and constitutes a parallel resonant circuit with the sub induction line, and a switch provided between the secondary coil and the parallel resonant circuit. In the parallel resonant circuit, the sub induction line and the resonance capacitor have constants such that the parallel resonant circuit has a resonance frequency equal to the oscillation frequency of the power-supply device. |
| US09331495B2 |
Soldier system wireless power and data transmission
An inductively coupled power and data transmission system include a main power source, apparel having an electrical conductor in electrical communication with the main power source, the apparel having a first inductively couplable power and data transmission sub-system to regulate power to the primary coil or coils and transmission of power and data by the primary coil or coils and reception of data by the primary coil or coils, and an independent device having a second inductively couplable power and data transmission sub-system so as to regulate reception of power and data by the secondary coil or coils and transmission of data from a secondary processor by the secondary coil or coils. The first and second primary coils transfer said power and data during inductive coupling, at electromagnetic radiation frequencies, between the first primary coil or coils and the secondary coil or coils. |
| US09331493B2 |
Electric load control apparatus
An electric load control apparatus includes an inverter connected to input terminals of an electric storage device, and having output terminals connected via output electric power lines to an electric motor. The inverter includes switching elements, which are controlled to energize the electric motor with electric power stored in the electric storage device. A noise removal filter disposed on at least a portion of the output electric power lines includes a bendable sheet made of a magnetic material wound around the output electric power lines, with air gaps disposed between coiled sheet layers of the wound sheet. |
| US09331490B2 |
Voltage-application drive systems and voltage-application method thereof
The present invention provides a voltage-application drive system, including a power module, a switching module and a voltage-application module, wherein the switching module including a plurality of switches and the voltage-application module including a plurality of voltage-application units; switching module receiving selection of voltage driver manner from user and controlling the plurality of switches and selectively supplying drive voltage according to the selection of voltage-application drive manner; the voltage-application unit receiving the drive voltage and converting the drive voltage into voltage required by the selection of voltage-application drive manner. As such, the present invention can reduce manufacturing cost, improve production efficiency and improve the flexibility of manufacturing process. |
| US09331483B2 |
Thermal energy storage apparatus, controllers and thermal energy storage control methods
Thermal energy storage apparatus, controllers and thermal energy storage control methods are described. According to one aspect, a thermal energy storage apparatus controller includes processing circuitry configured to access first information which is indicative of surpluses and deficiencies of electrical energy upon an electrical power system at a plurality of moments in time, access second information which is indicative of temperature of a thermal energy storage medium at a plurality of moments in time, and use the first and second information to control an amount of electrical energy which is utilized by a heating element to heat the thermal energy storage medium at a plurality of moments in time. |
| US09331479B2 |
Sensor device
A sensor device has a sensor unit, a control unit; and multiple power supply paths from a power supply to the sensor unit and the control unit. The multiple power supply paths are configured to be switched in accordance with an operation status of the sensor unit. The sensor device further has a wireless communication device for transmitting a measurement result of the sensor unit. The multiple power supply paths are provided to supply power from the power supply to the wireless communication device. The multiple power supply paths are configured to be switched in accordance with an operation status of the wireless communication device. |
| US09331475B2 |
Core
A magnetic fault current limiter core (10a) comprising at least one first magnetic element (12) and at least one second magnetic element (14), the magnetic elements (12,14) being arranged to define a substantially parallel array of magnetic elements (12,14), the or each first magnetic element (12) including a soft magnetic material and the or each second magnetic element (14) including a hard magnetic material, wherein the or each soft magnetic material in a non-saturated state has a higher magnetic permeability than the or each hard magnetic material. |
| US09331473B2 |
Fault detecting device for an electricity supply
A fault detecting device having a plurality of supply conductors, including a first current transformer having a primary winding comprising at least two supply conductors and a secondary winding into which a current is induced in response to a fault current in the primary winding. A fault detection circuit connects the secondary winding to an electromechanical actuator having mechanical contacts in the supply conductors, the fault detection circuit generating an output signal to the actuator when an induced current is detected in the secondary winding, the output signal causing the actuator to open the mechanical contacts. The device further includes a second current transformer having a primary winding connected to an oscillator and a secondary winding comprising at least one supply conductor, the second current transformer arranged to induce an oscillating current into the at least one supply conductor in the event of a fault condition. |
| US09331466B2 |
Protective devices for electric power adapters/chargers
A protective device for an electric power adapter/charger includes a trumpet-shaped support member having an inner passage along a longitudinal axis for receiving and supporting a cable of the adapter/charger to prevent bending the cable at sharp angles and an enclosure for enclosing at least a portion of the support member and at least a portion of a body of the adapter/charger to secure to the support member to the adapter/charger. The support member includes first and second portions connectable about a parting plane containing the longitudinal axis so that the support member can be laterally connected about the cable. The enclosure includes first and second portions connectable about a parting plane containing the longitudinal axis so that the enclosure can be secured about the body of the adapter/charger and clamping the first and second portions of the support member together. |
| US09331462B2 |
Junction box
A junction box includes a box body that has a component mounting portion, an upper cover that covers an upper part of the box body, and a side cover that is attached to a side face of the box body. The box body has a side wall portion which surrounds a component mounting portion and an electric distribution portion which is electrically connected to the component mounting portion. The upper cover has a top panel and a down wall portion which are downwardly provided from the peripheral end of the top panel. The side cover has a terminal and a case portion which covers the terminal. A recess or a hole which is located outside the down wall portion of the upper cover is formed on an upper face of the case portion. |
| US09331461B2 |
Electric-wire protecting pipe and wire harness
It is an object of the exemplary embodiments to obtain a long electric-wire protection pipe having a flat outer shape, using a simple press working process, while reducing or even preventing warping problems. An electric-wire protection pipe is a metal pipe that surrounds an electric wire, and has a reinforced section (11) and a flat pipe section. The reinforced section is a section that is located at a part in the circumferential direction of the electric-wire protection pipe while extending along the entire length in the longitudinal direction of the electric-wire protection pipe, and that is thicker than other sections. The flat pipe section is a section that constitutes at least a part in the longitudinal direction of the electric-wire protection pipe, and is flattened by press working. |
| US09331458B2 |
Ignition system
An ignition system for an internal combustion engine includes a discharge portion of the center electrode in which a part thereof is surrounded by a bottom portion and a tubular tip portion of the center dielectric, the part of the discharge portion and the tubular tip portion are projected into a combustion chamber of the internal combustion engine from a substantially annular tip portion of the ground electrode that opens to the combustion chamber at a distal end of the ground electrode, a diameter-changing portion formed by reducing a diameter of a part of the tubular tip portion in a radial direction gradually as approaching toward a tip thereof, and a thin-walled portion formed by reducing a thickness of the tip of the tubular tip portion. |
| US09331457B2 |
Semiconductor laser apparatus
A semiconductor laser apparatus, including: a beam divergence angle correction optical system for correcting a divergence angle of beams generated from light emitting points of a semiconductor laser bar; a beam rotation optical system for rotating the beams each having the corrected divergence angle; a wavelength dispersion optical element having a wavelength dispersion function; and a partial reflection mirror. A relative position of the beam divergence angle correction optical system with respect to the light emitting point in a divergence angle correction direction is changed for each light emitting point. |
| US09331456B2 |
Method of manufacturing semiconductor laser
A method of manufacturing a semiconductor laser according to an aspect of the present invention includes (a) sequentially epitaxially growing a first cladding layer, an active layer and a second cladding layer on a semiconductor substrate composed of InP or GaAs and having a plane index of (100), (b) forming a plurality of growth start surfaces having a plane index greater than (100) in an upper surface of the second cladding layer, and (c) epitaxially growing a third cladding layer containing zinc in the plurality of growth start surfaces of the second cladding layer. |
| US09331449B2 |
Gas laser oscillator capable of controlling gas pressure and gas consumption amount
A gas laser oscillator includes a first control valve for controlling an amount of laser gas supplied into a gas container, a second control valve for controlling an amount of laser gas exhausted from the gas container, and a controller for controlling openings of the first and second control valves. The controller includes a storage unit for storing data indicating a relationship between the laser gas pressure in the gas container, the opening of the second control valve, and the exhaust amount of laser gas, a gas pressure control unit for controlling the openings of the first and second control valves, respectively, such that the laser gas pressure becomes closer to a reference gas pressure, and a gas consumption amount control unit for controlling the openings of the first and second control valves, respectively, such that the exhaust amount of laser gas becomes closer to a target consumption amount. |
| US09331440B2 |
Connector
A connector (10) includes a first housing (12) made of synthetic resin and including a fitting (11), and a second housing (14) made of synthetic resin and including a tubular receptacle (13) into which the fitting (11) is to be fit. At least one first projection (37) projects forward on a front end part (40) of the fitting (11) in the connecting direction and at least one second projection (43) projecting toward the first projection (37) is formed on a part of a back wall (27) of the receptacle (13) corresponding to the first projection (37). A fitting depth of the first and second housings (12, 14) is specified by the contact of a tip (38) of the first projection (37) and a tip (44) of the second projection (43) when the first and second housings (12, 14) are connected properly. |
| US09331438B2 |
Split jack assemblies and methods for making the same
Split jack assemblies are constructed with a tubeless pin block. Elimination (or split) of the tube, or more particularly, a tube that is an integrally formed part of the pin block form the pin block allows for the use of a tubeless pin block design that results in a jack assembly having smaller overall dimensions than a conventional jack assembly constructed to accommodate a plug of the same dimensions. The tubeless pin block can be used in conjunction with a tube sleeve or with a curved surface of a housing for an electronic device, or both to provide a plug receptacle of the split jack assembly. |
| US09331436B2 |
Multi-outlet capable of conveniently organizing cables connected to electric appliances
Provided is a multi-outlet capable of conveniently organizing cables connected to electric appliances. The provided multi-outlet capable of conveniently organizing cables connected to electric appliances comprises: a plug housing comprising an upwardly opened housing space formed inside for accommodating cables and plugs of electric appliances, downwardly opened cable entry roads formed at a lower portion, inducing holes formed on the bottom for connecting the housing space and the entry roads, and curved arc-shaped apertures formed at the upper ends; a finishing cover insertedly connected to the upper end of the plug housing for finishing the housing space, and having a cable winding drum projected at a lower portion; and a power connection portion embedded in the finishing cover so as to supply electric power to the electric appliances, and comprising a plurality of plug terminals for power supply at all times which is opened toward the housing space to be electrically connected to the plugs accommodated in the housing space, and a plug terminal for power supply at any time which is opened outwardly, individual switches formed at the plug terminals for power supply at all times for controlling the power supplied thereto, a power input cable formed at the outside of the cable winding drum so as to be electrically connected to the terminals for supplying external power, and a main switch formed at the upper portion of the finishing cover to be connected to the power input cable for controlling the power supplied therethrough. It is possible to make the surroundings of a multi-output be neat and improve user convenience. |
| US09331433B2 |
Connector
A connector includes at least one contact, a ground plate formed of a metal plate of a predetermined thickness, an insulator that holds the at least one contact and the ground plate, and a metal shell that covers an outer periphery portion of the insulator, the metal shell having a window section formed facing the ground plate and having a thickness greater than the thickness of the metal plate which forms the ground plate, the ground plate having a shell fixing section formed by folding and overlapping the metal plate and located to contact the window section from inside the metal shell, a periphery of the window section of the metal shell and the shell fixing section of the ground plate being welded to each other inside the window section of the metal shell. |
| US09331432B1 |
Electrical connector having bussed ground contacts
A contact assembly for an electrical connector includes a holder and multiple ground contacts and signal contacts. The ground contacts and signal contacts are held by the holder along an outer side of the holder. The ground contacts and the signal contacts each have a mating segment proximate to a front end of the holder and a terminating segment proximate to a rear end of the holder. Ground contacts nearest to each other define a contact spacing therebetween. The nearest ground contacts are mechanically connected by a bridge member that connects the mating segments of the nearest ground contacts to electrically common the ground contacts. At least one signal contact is disposed in the contact spacing between the nearest ground contacts. The ground contacts provide electrical shielding between the signal contacts that are in different contact spacings. |
| US09331430B2 |
Enclosed power outlet
Power outlets adapted for installation within an enclosure are provided. Power outlets are provided having a safety interlock adapted to prevent the creation of a hazardous condition within the enclosure as a result of the continued operation of an electrical device within the enclosed space. The safety interlock may include current limiting circuitry and hardware, hazard sensing devices interconnected with such current limiting circuitry and hardware or other circuit breaker switches, and combinations of such safety interlocks. The power outlets may also be adapted for installation within a movable enclosure, such as, for example, a drawer. |
| US09331426B2 |
Socket panel for receiving connector plugs with latch guards comprising a security cover plate
A modular connector is provided having a connector plug, which may be inserted into an associated socket in a first longitudinal direction, a resilient leg, depending at a first end thereof from the connector plug, and having a depressible part, distal therefrom, depressible towards the connector plug, and a guard cover, configured to prevent access to the depressible part of the resilient leg in its direction of depression, but to permit access to the resilient leg in the longitudinal direction through an access aperture, the access aperture being aligned with the depressible part of the resilient leg on an axis parallel with the longitudinal direction, to allow depression of the resilient leg through the access aperture directly. Corresponding extraction tool and methods, loopback connector, blanking plug, keyed protrusions and notches, security gasket, and blanking plate and patch panel also are disclosed. |
| US09331423B2 |
Methods for making dual material strain-relief members for cables
Aesthetically pleasing strain-relief members for cables and methods for making the same are disclosed. The strain-relief member include a tapered, inner strain-relief portion and an aesthetically pleasing outer strain-relief portion. |
| US09331415B2 |
Electrical connector
An electrical connector allowing a housing and a contact portion to be displaced relative to a mounting circuit board, parallel to a board surface, without a reinforcing plate separate from a contact member. A basal portion of a contact member is present along an upper surface of a base portion of a housing. A mounting-side elastic portion of the contact member is present along a lower surface of the base portion of the housing. A folding-back portion of the contact member is located at a rear of the base portion of the housing to connect the basal portion to the mounting-side elastic portion. First and second connecting leg portions extend downward from the mounting-side elastic portion. Each tip side of the leg portions acts as a mounting portion for a circuit board at positions different from each other in a front-back direction. |
| US09331414B2 |
Electrical connector
An electrical connector is to be connected to a mating side connector. The electrical connector includes a fixed housing to be fixed to a board; a movable housing arranged to be movable relative to the fixed housing; and a plurality of terminals disposed between the fixed housing and the movable housing. The terminal includes a connecting portion held with the fixed housing; a first elastic portion connected to the connecting portion; a terminal portion held with the movable housing; a second elastic portion connected to the terminal portion; and a wide width portion connected between the first elastic portion and the second elastic portion so that the first elastic portion is curved in a direction opposite to a direction that the second elastic portion is curved. The wide width portion has a width greater than that of the first elastic portion and the second elastic portion. |
| US09331413B2 |
Dual thickness double-ended male blade terminal
A printed circuit board (PCB) assembly having a double-ended male blade electrical terminal is presented. The double-ended terminal has a first blade with a substantially uniform first thickness and a second blade opposite the first blade that has an embossed mesial region providing a substantially uniform second thickness, wherein the effective thickness of the second blade is greater than the thickness of the first blade. The terminal may be used in an electrical center of a motor vehicle to interconnect a female socket in a vehicle wiring harness to an electronic device, such as a fuse or relay, having a socket terminal that is mounted on the PCB. A method of manufacturing such as double ended-terminal is also presented. |
| US09331412B2 |
Press-in pin for an electrical press-in connection between an electronic component and a substrate plate
The invention relates to a press-in pin (1, 2) for an electrical press-in connection between an electronic component (3) and a substrate plate (4) with an electrical contact hole (5). The press-in pin (1, 2) has a press-in pin head (6) which has a press-in head length (IK) which is matched to a thickness (d) of the substrate plate (4). A press-in pin leg (7) extends between the electronic component (3) and the press-in pin head (6). A press-in pin collar (13) forms a transition between the press-in pin leg (7) and the press-in pin head (6) and has a locking projection (14). The press-in pin head (6) is coated with a layer (20) of a lead-free tin alloy (15). At least the press-in pin collar (13) with the locking projection (14) has an electrically insulating coating (16). |
| US09331409B2 |
Electrical connection device
An electrical connection device is to be attached to a wiring board for holding a plate conductive member so that the wiring board is electrically connected to the plate conductive member. The electrical connection device includes a contact piece including an arm portion, a leg portion, and a base portion disposed between the arm portion and the leg portion; and a base member to be attached to the wiring board for supporting the contact piece at the base portion thereof. The base member is to be attached to the wiring board so that the base member is movable in parallel to the wiring board. The contact piece is arranged so that the plate conductive member pushes the arm portion to urge the leg portion against the wiring board with the base portion as a pivot when the plate conductive member contacts with the arm portion. |
| US09331408B2 |
Electrical connector assembled component
An electrical connector assembled component includes a first connector to be disposed on a circuit board and including a receiving portion; and a second connected to be accommodated in the receiving portion. The receiving portion includes a cylindrical receiving portion and an open receiving portion. The open receiving portion includes a locking piece connected to the side plate portion. The locking piece includes a locking portion at a front edge thereof. The cylindrical receiving portion includes an elastic contact piece. The second connector includes an elastic locking arm extending from the flat plate portion. The elastic locking arm is situated inside the cylindrical receiving portion at a position different from that of the elastic contact piece in the width direction, and at a position overlapped with that of the elastic contact piece in a vertical direction. |
| US09331406B2 |
Receptacle connector and method of producing receptacle connector
A receptacle connector includes a receptacle insulator having an annular outer peripheral wall which defines a fitting recess; receptacle contacts; and a receptacle-side metal fixing member. When a projecting fitting portion of a plug insulator of a plug connector is fitted into the fitting recess, plug contacts of the plug connector come into contact with the receptacle contacts, and the plug connector comes into contact with the receptacle-side metal fixing member. The receptacle-side metal fixing member and the receptacle insulator are integrally formed by insert molding, and the receptacle-side metal fixing member includes a resilient contact portion which is spaced from a surface of the outer peripheral wall on the circumferentially inner side thereof when the resilient contact portion is in a free state. |
| US09331401B2 |
Multi-tap piercing connector
A piercing connector includes a connector body, a piercing insert, and a piercing cover. The connector body has a plurality of conductor apertures and a piercing aperture. The piercing insert has a plurality of piercing teeth and is inserted into the piercing aperture. The piercing cover is inserted into the piercing aperture and removably attached to the connector body. The piercing cover removably secures the piercing insert in the connector body. The piercing connector receives and electrically connects two or more conductors. |
| US09331399B2 |
Terminal-fitted wire manufacturing method
It is aimed to enable a heat shrinkable tube to be mounted on a connected part of a core exposed portion of a wire and a terminal with high positioning accuracy. A terminal-fitted wire manufacturing method is for mounting a heat shrinkable tube on a connected part of a core exposed portion of a wire and a terminal. After the wire is inserted into the heat shrinkable tube, the terminal is connected to the core exposed portion. Thereafter, the heat shrinkable tube is moved to a position for covering the connected part of the core exposed portion and the terminal, and a part of the heat shrinkable tube is temporarily fixed to at least parts of the wire and the terminal. Thereafter, the heat shrinkable tube is mounted by being heated and thermally shrunk. |
| US09331398B2 |
Dual-mode terminal antenna and signal processing method
The disclosure discloses a dual-mode terminal antenna, comprising a main antenna comprising a main antenna of a first mode and a main antenna of a second mode, an auxiliary antenna comprising an auxiliary antenna of the first mode and an auxiliary antenna of the second mode, and an antenna bracket. The main and auxiliary antennas are fixed on a same antenna bracket, each of which is configured with a spring lea. When the antenna bracket is clasped on a main board, four spring leaves of the main and auxiliary antennas contact with four antenna feeding points on the main board respectively, An LC resonant circuit is disposed ahead of each antenna feeding point, and four LC resonant circuits resonate at a working frequency band of the antenna corresponding to the antenna feeding point with which each said LC resonant circuits connects, respectively. The disclosure also discloses a signal processing method, which solves signal interference and loss problems existed in an antenna of the prior art in a reception mode, through high impedance of the LC resonant circuit to the signal at different frequency bands. Furthermore, the dual-mode terminal antenna of the disclosure simplifies the layout of the Printed Circuit Board (PCB). |
| US09331397B2 |
Tunable antenna with slot-based parasitic element
Electronic devices may be provided that contain wireless communications circuitry. The wireless communications circuitry may include radio-frequency transceiver circuitry and antenna structures. The antenna structures may form a dual arm inverted-F antenna. The antenna may have a resonating element formed from portions of a peripheral conductive electronic device housing member and may have an antenna ground that is separated from the antenna resonating element by a gap. A short circuit path may bridge the gap. An antenna feed may be coupled across the gap in parallel with the short circuit path. Low band tuning may be provided using an adjustable inductor that bridges the gap. The antenna may have a slot-based parasitic antenna resonating element with a slot formed between portions of the peripheral conductive electronic device housing member and the antenna ground. An adjustable capacitor may bridge the slot to provide high band tuning. |
| US09331392B1 |
Tapered slot antenna with a curved ground plane
An apparatus includes an antenna element and a curved ground plane positioned beneath the antenna element. The antenna element has a height h and a first end with a tapered width, where h is approximately equal to the distance of a width-wise cross-sectional curve of the curved ground plane. The width of the curved ground plane is less than or equal to ½ h. A load may be positioned on top of a second end of the antenna element. The second end of the antenna element has a thickness greater than the first end and less than a thickness of the load. The curved ground plane may be substantially hemispherical in shape or may have a tapered height and increase in width from a first end to a second end. |
| US09331387B2 |
Wideband antenna
A wideband antenna includes a first substrate, a second substrate, a ground plane, an exciting element, a connection element, a first branch, a second branch, and a coupling branch. The ground plane is disposed on the first substrate. The exciting element is disposed on the second substrate and has a feed point coupled to a signal source. The connection element is disposed on the second substrate and coupled to the ground plane. The first branch is disposed on the second substrate and coupled to the connection element. The second branch is disposed on the second substrate and coupled to the connection element. The coupling element is disposed on the second substrate and coupled to the connection element. The distance between the coupling element and the second branch is smaller than 5 mm. |
| US09331383B2 |
Antenna structure and the manufacturing method therefor
An antenna structure is provided. The antenna structure includes a radiating portion having an approximately quadrangular body, wherein the quadrangular body has a first side, a second side opposite to the first side, a third side, and a fourth side opposite to the third side; and a ground portion surrounding an entire length of the first side, an entire length of the fourth side, and at most a half of a length of the second side. |
| US09331382B2 |
Space-filling miniature antennas
A novel geometry, the geometry of Space-Filling Curves (SFC) is defined in the present invention and it is used to shape a part of an antenna. By means of this novel technique, the size of the antenna can be reduced with respect to prior art, or alternatively, given a fixed size the antenna can operate at a lower frequency with respect to a conventional antenna of the same size. |
| US09331378B2 |
Active load modulation antenna
Active load modulation antennas for contactless systems typically require the presence of a battery power source in the transponder device. The transponder typically cannot be powered by the reader device alone and also transmit an active load modulation signal. Embodiments in accordance with the invention are disclosed that allow transponder devices to transmit an active load modulation signal when powered only by the reader in the contactless system. |
| US09331375B2 |
Pivoting underwater RFID antenna assembly
An underwater antenna assembly (or array thereof) suitable for subsurface RFID tag interrogation in flowing water such as a river. In preferred embodiments, the antenna interrogates RFID tags implanted in aquatic species. The antenna resides in an elongate antenna housing whose cross-sectional shape is preferably a hydrodynamic teardrop shape. A first end of the housing is linked to a pivoting mechanism such that when the pivoting mechanism is held substantially stationary with respect to the water flow, the second end of the housing is free to rotate generally about the first end in a substantially vertical plane parallel to the water flow direction. The length of the antenna housing is advantageously selected to enable the antenna to monitor for signals across substantially the entire water depth. |
| US09331374B2 |
MIMO coverage over bi-directional leaky cables
The invention relates to a wireless communications system for communicating with user equipment located inside a physical structure. The system comprise a node having at least two antenna ports and being adapted for wireless communication with the user equipment, and at least one leaky cable having two ends wherein each end of the at least one leaky cable is connected to one of the antenna ports of the node. The at least one leaky cable is provided at least partially inside the physical structure and being adapted for wireless communication over a radio channel with the user equipment. |
| US09331365B2 |
Shared control of thermistor and dual purpose thermistor line
A battery pack can include a temperature sensor that can provide an output that is indicative of a temperature associated with the battery pack. A battery management unit can directly measure the temperature sensor when the battery pack is by itself or engaged with a tool. A charger can directly read the temperature sensor when the battery pack is engaged with the charger. Thus, the temperature sensor can be shared by the battery pack and the charger. The battery pack can utilize a same terminal that provides access to the temperature sensor to indicate a stop-charge signal. The charger can read the stop-charge signal on the same terminal used to directly access the temperature sensor. |
| US09331363B2 |
Structural electric device having improved safety
Provided is a novel structural electric device having improved safety. More particularly, provided is a novel structural electric device devised to resolve several issues regarding heat generation, ignition, and explosion, which may be caused by a sharp needle-shaped object penetrating an electric device. |
| US09331361B2 |
Nonaqueous electrolyte secondary battery and production method thereof
According to the embodiment, there is provided a nonaqueous electrolyte secondary battery comprising a positive electrode; a negative electrode including a negative electrode active material layer; and a nonaqueous electrolyte. The negative electrode active material layer contains carbon dioxide and releases the carbon dioxide in the range of 0.01 ml to 3 ml per 1 g when heated at 400° C. for 1 minute. The nonaqueous electrolyte contains carbon dioxide of 50 ml/L to 1000 ml/L. |
| US09331360B2 |
Fluoride ion battery electrolyte compositions
A fluoride ion battery includes a substantially lithium-free anode and cathode. At least one of the anode or cathode contains fluorine, and a substantially lithium-free liquid electrolyte is used for charge transport. The electrolyte is liquid at temperatures below about 200 degrees Celsius, and can be formed from an organic-soluble fluoride salt dissolved in selected classes of solvents. |
| US09331358B2 |
Battery with multiple jelly rolls in a single pouch
The disclosed embodiments provide a battery cell which includes a set of jelly rolls enclosed in a pouch. Each jelly roll includes layers which are wound together, including a cathode with an active coating, a separator, and an anode with an active coating. The battery cell also includes a first set of conductive tabs and a second set of conductive tabs. Each of the first set of conductive tabs is coupled to the cathode of one of the jelly rolls, and each of the second set of conductive tabs is coupled to the anode of one of the jelly rolls. At least one of the first set and one of the second set of conductive tabs extend through seals in the pouch to provide terminals for the battery cell. |
| US09331357B2 |
Electrochemically self assembled batteries
The present invention relates to in situ formation of a single-layered electrochemical cell comprising a full tri-layer battery structure containing a discrete positive electrode, solid state electrolyte, and negative electrode from self-assembled nanocomposites. The single layered cell makes it possible to fabricate cells in three dimensions resulting in a very high energy density power source within very small and/or complex dimensions. |
| US09331349B2 |
Waste heat recovery system
A waste heat recovery system includes a fuel cell, a coolant circulation flow passage, a first heat exchanger, a waste heat recovery flow passage, a second heat exchanger, an upstream end of the waste heat recovery flow passage, and a downstream end of the waste heat recovery flow passage. The coolant circulation flow passage includes a first coolant supply flow passage, a first coolant exhaust flow passage, and a first bypass flow passage. The upstream end is connected to at least one of an inlet coolant reservoir and the first coolant exhaust flow passage at a position downstream of a connection point between the first coolant exhaust flow passage and the first bypass flow passage. The downstream end is connected to at least one of the inlet coolant reservoir, an outlet coolant reservoir, and the first coolant supply flow passage. |
| US09331347B2 |
Fuel cell system and control method thereof
A fuel cell system that can quickly transition to idling stop and can suppress degradation of the electrolyte membrane and decline in cell voltage during idling stop, without requiring a discharge resistor to be provided, and a control method thereof are provided. A fuel cell system (1) includes a fuel cell (10) configured by layering a plurality of fuel cell cells that generate power by reactant gas being supplied thereto, and a supply device 20 that supplies reactant gas to the fuel cell (10), in which idling stop control is initiated to supply air of a lower flow rate than during idling power generation to the fuel cell (10), while producing lower current than during idling power generation from the fuel cell (10), in a case of a predetermined condition being established during idling power generation. |
| US09331346B2 |
Fuel cell resin frame equipped membrane electrode assembly
A resin frame equipped membrane electrode assembly includes a membrane electrode assembly and a resin frame member. The membrane electrode assembly includes an anode, a cathode, and a solid polymer electrolyte membrane interposed between the anode and the cathode. The resin frame member is provided around the solid polymer electrolyte membrane. The resin frame member includes an inner extension protruding toward the outer periphery of the cathode to contact the outer end of the solid polymer electrolyte membrane. The inner extension of the resin frame member includes a plurality of columnar projections formed integrally with an adhesive surface where an adhesive layer is provided. |
| US09331345B2 |
Bonded sheet and sheet-member bonding method
A bonded sheet to be applied to a membrane electrode assembly includes gaskets serving as a first sheet member and an electrolyte membrane serving as a second sheet member stacked on the gaskets. The gaskets each include a first bonded portion where grooves provided in a sheet surface direction at least partly face sheet end portions, and a second bonded portion having no groove. The electrolyte membrane is stacked on the gaskets in the first bonded portion and the second bonded portion. |
| US09331341B2 |
Durable platinum/multi-walled carbon nanotube catalysts
Platinum nanocatalysts on multi-walled carbon nanotubes (MWCNTs) functionalized with citric acid (CA) are disclosed, along with methods for the synthesis thereof. |
| US09331337B2 |
Non-aqueous electrolyte secondary battery and method for producing the same
A positive electrode active material with least part of a surface coated with a surface treatment layer composed of a phosphate compound. The phosphate compound contains at least one element selected from the group consisting of neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium. |
| US09331336B2 |
Lithium-ion secondary battery
Provided is a lithium-ion secondary battery that uses a non-carbonaceous negative electrode active material capable of exhibiting capacitance properties. The lithium-ion secondary battery includes a positive electrode, a negative electrode, and a non-aqueous electrolyte solution. The negative electrode includes a mica group mineral having at least one transition metal in its composition as a negative electrode active material. |
| US09331335B2 |
Solid solution lithium-containing transition metal oxide and lithium ion secondary battery
A solid solution lithium-containing transition metal oxide includes a compound represented by chemical formula (1): Li1.5[NiaCobMnc[Li]d]O3, where a, b, c and d satisfy relationships: 0 |
| US09331331B1 |
Water-based binder for high voltage cathode material for Li-ion battery
The present invention generally relates to using water-based binders for high voltage cathode materials, such as LMNO (spinel LiNi0.5Mn1.5O4), in Li-ion batteries. An example of a water compatible polymer binder according to some embodiments of the present invention is a combination of CMC (carboxymethylcellulose) and a second water compatible polymer that produce coatings of adequate thickness and loading (mAh/cm2). A method of forming a cathode for a Li-ion battery may include: preparing an aqueous solution of CMC; mixing together LMNO and carbon black; combining the LMNO and carbon black mixture with the CMC solution, an aqueous polyacrylic solution and distilled water, and mixing to form a slurry; coating a conductive substrate with the slurry; and drying the coated substrate, forming a cathode layer on the substrate. Furthermore, this invention describes a cathode for Li-ion batteries and tools for carrying out the above method. |
| US09331325B2 |
Battery pack
A battery pack including: a plurality of battery modules, each including a plurality of battery cells arranged in a direction; at least one first fuse between battery modules of the plurality of battery modules; a battery control unit connected to the at least one first fuse; and at least one sensing unit connected to the battery control unit, the battery control unit being configured to transfer a signal received from the at least one sensing unit to the at least one first fuse, and the at least one first fuse including a power cutoff unit at a region of a connection member connecting the battery modules to each other, and a case surrounding the power cutoff unit. |
| US09331318B2 |
Battery module
A battery module that includes a plurality of electrochemical cells. Each of the electrochemical cells has a first end including at least one terminal and a second end having a vent. The plurality of electrochemical cells are arranged such that the second ends of a first set of the plurality of electrochemical cells face the second ends of a second set of the plurality of electrochemical cells. A central chamber is located between the second ends of the first set of the plurality of electrochemical cells and the second ends of the second set of the plurality of electrochemical cells. The central chamber is configured to receive gases released from the vents of the plurality of electrochemical cells. |
| US09331314B2 |
Battery module having electrochemical cells with integrally formed terminals
An electrochemical cell includes a housing and a lid coupled to the housing. The electrochemical cell also includes a first member conductively coupled to the housing and configured to act as a first terminal for the electrochemical cell. The electrochemical cell further includes a second member electrically insulated from the lid and configured to act as a second terminal for the electrochemical cell. A first portion of the second member extends through the lid and a second portion of the second member extends in a direction generally perpendicular to the first portion. |
| US09331311B2 |
Fluorine-containing plasma polymerized HMDSO for OLED thin film encapsulation
Methods for forming an OLED device are described. An encapsulation structure having organic buffer layer sandwiched between barrier layers is deposited over an OLED structure. The buffer layer is formed with a fluorine-containing plasma. The second barrier layer is then deposited over the buffer layer. Additionally, to ensure good adhesion, a buffer adhesion layer is formed between the buffer layer and the first barrier layer. Finally, to ensure good transmittance, a stress reduction layer is deposited between the buffer layer and the second barrier layer. |
| US09331309B2 |
Display apparatus, method for manufacturing display apparatus, and method for designing display apparatus
A display apparatus includes (A) a first substrate where a plurality of light emitting elements, which are formed by laminating a first electrode, a light emitting section which is configured by an organic layer provided with a light emitting layer, and a second electrode, are formed, and (B) a second substrate which is arranged to oppose the first substrate, in which the first substrate is further provided with a light reflecting layer formed of first members which propagate and output light from each light emitting element to an outside and second members placed between two first members, the first members have a truncated cone shape where a cutting head section opposes the light emitting element, a part of light propagated by the first members is completely reflected on opposing surfaces of the second members which oppose the first members. |
| US09331307B2 |
Method for manufacturing organic EL device and organic EL device
Provided is a method for manufacturing an organic EL device which suppresses a deterioration in the light emission properties. In this method, while first and second electrode layers are prevented from being in contact with each other, an organic layer is allowed to protrude from the first electrode layer toward at least both outer sides in the longitudinal direction of a substrate. Further, the second electrode layer is allowed to protrude from the organic layer toward at least both outer sides in the longitudinal direction. Thereby, the first electrode layer, the organic layer, and the second electrode layer are formed so that both end edges of the organic layer in a longitudinal direction of the substrate are covered by both end sides of the second electrode layer in the longitudinal direction, on at least both outer sides of the light emitting part in the longitudinal direction. |
| US09331306B2 |
Organic optical device and protective component of organic optical device
An organic optical device which can suppress deterioration due to moisture or an impurity is provided. An organic optical device includes a supporting body, a functional layer provided over the supporting body, and a light-emitting body containing an organic compound provided over the functional layer. The functional layer includes an insulating film containing gallium or aluminum, zinc, and oxygen. The supporting body and the functional layer each have a property of transmitting light with a wavelength of greater than or equal to 400 nm and less than or equal to 700 nm. By using the insulating film containing gallium or aluminum, zinc, and oxygen as a protective film, entry of moisture or an impurity into an organic compound or a metal material can be suppressed. |
| US09331303B2 |
Organic light-emitting diode lighting apparatus
Disclosed herein is an organic light-emitting diode lighting apparatus. The organic light-emitting diode lighting apparatus may include a transparent substrate main body with a plurality of groove lines formed therein, auxiliary electrodes formed in at least of the plurality of groove lines, a first electrode formed on the substrate main body, positive temperature coefficients configured to connect the auxiliary electrodes and the first electrode, an organic emission layer formed on the first electrode, and/or a second electrode formed on the organic emission layer. |
| US09331296B2 |
Organic light-emitting device
Aspects of the present invention provide a blue organic light-emitting device having a continuous operation lifetime.An organic light-emitting device includes a light-emitting layer containing a dopant having the ability to trap electrons or holes, and a hole-blocking layer or electron-blocking layer, in which the difference between the LUMO of the dopant and the LUMO of a host material, the size relationship between the HOMO of the host material and the HOMO of the dopant, and the difference between the T1 of the host material and the T1 of the hole-blocking layer or between the T1 of the host material and the T1 of the electron-blocking layer, are specified. |
| US09331290B2 |
Metal complexes
The present invention relates to metal complexes and to electronic devices, in particular organic electro-luminescent devices, comprising these metal complexes. M(L)n(L′)m formula (1), where the compound contains a moiety M(L)n of the formula (2). |
| US09331289B2 |
Organic electroluminescent material, organic electroluminescent element, display device and lighting device
Disclosed are: an organic EL material which emits light having a short wavelength and has high luminous efficiency and long light emission life; an organic EL element which contains the organic EL material; and a lighting device and a display device, each of which comprises the organic EL element. The organic EL material is a compound represented by Formula (1): |
| US09331285B2 |
Aromatic amine derivative and organic electroluminescent element using same
An aromatic amine derivative represented by the following formula (1): wherein at least one of R1 to R8 is a group other than a hydrogen atom, Ar1 to Ar4 are a substituted or unsubstituted aryl group having 6 to 30 ring carbon atoms. |
| US09331284B2 |
Polymer compound and light-emitting device using same
It is an object of the invention to provide a polymer compound that, when used in a light-emitting device, results in excellent luminance life for the obtained light-emitting device. The invention provides a polymer compound comprising a constitutional unit represented by formula (1). [In formula (1), R1A, R1B, R2A, R2B represent an unsubstituted alkyl group, R3 and R4 represented an unsubstituted or substituted alkyl group, an unsubstituted or substituted alkoxy group, an unsubstituted or substituted aryl group, an unsubstituted or substituted aryloxy group, an unsubstituted or substituted heterocyclic group, an unsubstituted or substituted silyl group, a halogen atom, an alkoxycarbonyl group, a carboxyl or a cyano group, and R5 and R6 represent an unsubstituted or substituted alkyl group, an unsubstituted or substituted alkoxy group or an unsubstituted or substituted aryl group. The letters a, b, c and d each represent an integer of 0 to 3. When multiple R3, R4, R5 and R6 groups are present, they may be the same or different.] |
| US09331281B2 |
Bank structures for organic electronic devices
Embodiments in accordance with the present invention relate generally to the use of polycycloolefinic polymers as a structure defining material in organic electronic devices, and more specifically to separators, insulating structures or bank structures of such devices and to organic electronic devices comprising such structures, to processes for preparing such structures and to organic electronic devices encompassing such structures. |
| US09331277B2 |
One transistor and one resistive random access memory (RRAM) structure with spacer
The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer on the bottom electrode having a width that is same as a width of the top portion of the bottom electrode; a capping layer over the bottom electrode; a spacer surrounding the capping layer; and, a top electrode on the capping layer having a smaller width than the resistive material layer. The RRAM cell further includes a conductive material connecting the top electrode of the RRAM structure to a metal layer. |
| US09331276B2 |
Nonvolatile resistive memory element with an oxygen-gettering layer
A nonvolatile resistive memory element includes an oxygen-gettering layer. The oxygen-gettering layer is formed as part of an electrode stack, and is more thermodynamically favorable in gettering oxygen than other layers of the electrode stack. The Gibbs free energy of formation (ΔfG°) of an oxide of the oxygen-gettering layer is less (i.e., more negative) than the Gibbs free energy of formation of an oxide of the adjacent layers of the electrode stack. The oxygen-gettering layer reacts with oxygen present in the adjacent layers of the electrode stack, thereby preventing this oxygen from diffusing into nearby silicon layers to undesirably increase an SiO2 interfacial layer thickness in the memory element and may alternately be selected to decrease such thickness during subsequent processing. |
| US09331275B2 |
Switching device structures and methods
Switching device structures and methods are described herein. A switching device can include a vertical stack comprising a material formed between a first and a second electrode. The switching device can further include a third electrode coupled to the vertical stack and configured to receive a voltage applied thereto to control a formation state of a conductive pathway in the material between the first and the second electrode, wherein the formation state of the conductive pathway is switchable between an on state and an off state. |
| US09331267B2 |
Electronic device having buried gate and method for fabricating the same
Electronic devices having semiconductor elements and methods for fabricating such devices including, a method for fabricating an electronic device including a semiconductor memory, which includes: forming a sacrificial layer on a substrate including a first region and a second region; selectively etching the sacrificial layer and the substrate of the first region to form a trench; forming a first gate that fills a part of the trench in the first region; forming a gate protection layer on the first gate to fill the remaining part of the trench; removing the sacrificial layer of the first region to form a grooved portion surrounded by the gate protection layer; forming a conductive plug to cover the grooved portion; removing the sacrificial layer of the second region; and forming a second gate on the substrate of the second region. |
| US09331265B2 |
Non-volatile memory with linear hot-electron injection technique and strain gauge using the same
A linear hot-electron injection technique is provided for a non-volatile memory arrangement. The non-volatile memory is comprised of: a floating gate transistor; a capacitor with a first terminal electrically coupled to the gate node of the floating gate transistor; a current reference circuit electrically coupled to the source node of the floating gate transistor; and a feedback circuit electrically coupled between the source node of the floating gate transistor and a second terminal of the capacitor. The feedback circuit operates to adjust a voltage at the gate node of the floating gate transistor in accordance with a source-to-drain voltage across the floating gate transistor. |
| US09331264B1 |
Microelectromechanical resonators having degenerately-doped and/or eutectic alloy resonator bodies therein
A microelectromechanical resonator includes a resonator body having a semiconductor region therein that may be degenerately doped with boron. This high level of doping facilitates the formation of a eutectic alloy within the resonator body in response to resistive heating. The formation of a lattice-strained eutectic alloy within the resonator body supports reductions in the temperature coefficient of frequency (TCF) of the resonator over a relatively large temperature range. |
| US09331259B2 |
Intrinsic adaptive and autonomic piezotransformer circuits
An intrinsic piezoelectric transformer circuit a piezoelectric transformer circuit is provided that has a primary side component including first and second electrodes, a secondary side component including first and second electrodes, and at least one tertiary component including first and second electrodes. A power bridge is provided which includes one or more switches, each switch has a gate terminal that is directly connected to the second electrode of the tertiary component of the piezoelectric transformer. The first electrode of the tertiary component of the piezoelectric transformer is connected to a reference for the one or more switches of the power bridge. The first electrode of the primary component of the piezoelectric transformer is electrically connected to a power bridge output and the second electrode of the primary component of the piezoelectric transformer is connected to a ground terminal. |
| US09331254B2 |
Light emitting device
Pkg resin crack is suppressed after dicing.A light emitting device 1 where a light emitting device 2 that emits light is mounted on a lead frame 3 and that uses a resin cavity molding package 5 having an integrally molded lead frames 3, 4 constituting electrodes that correspond to the light emitting element 2 and resin, wherein roundness is given to a part or all of a cutting plane corner part of a retention section (hanger lead 3a, 4a) that become a cause of crack generation due to the retention sections (hanger leads 3a, 4a) of the lead frames giving stress concentration to resin at the time of cutting by a blade 7. |
| US09331253B2 |
Light emitting diode (LED) component comprising a phosphor with improved excitation properties
A light emitting diode (LED) component comprises an LED having a dominant wavelength in a range of from about 425 nm to about 475 nm, and a first phosphor and a second phosphor are in optical communication with the LED. The first phosphor has a peak emission wavelength in the range of from about 600 nm to about 700 nm, and the second phosphor has a peak emission wavelength in the range of from about 500 nm to about 600 nm. An excitation spectrum of the first phosphor includes, at excitation wavelengths longer than 530 nm, no intensities greater than about 60% of a maximum intensity of the excitation spectrum. |
| US09331250B1 |
Light emitting device with anti-total-internal-reflection capability
A light emitting device includes: a light emitting layered structure; an electrode unit connected to the light emitting layered structure and including a transparent electrode layer of a primary metal oxide which is stacked on the light emitting layered structure along a stacking direction; and a total-internal-reflection suppression material dispersed in the transparent electrode layer and containing a secondary metal oxide that is different from the primary metal oxide. The secondary metal oxide has a concentration gradient within the transparent electrode layer along the stacking direction. The light output power of the light emitting device may be increased by about 44% as compared to a conventional light emitting device. |
| US09331247B2 |
Light-emitting element having a reflective structure with high efficiency
A light-emitting element includes a reflective layer; a first transparent layer on the reflective layer; a light-emitting stack having an active layer on the first transparent layer; and a cavity formed in the first transparent layer. |
| US09331242B2 |
Optoelectronic device and method for manufacturing same
An optoelectronic device comprises a substrate; pads on a surface of the substrate; semiconductor elements, each element resting on a pad; a portion covering at least the lateral sides of each pad, the portion preventing the growth of the semiconductor elements on the lateral sides; and a dielectric region extending in the substrate from the surface and connecting, for each pair of pads, one of the pads in the pair to the other pad in the pair. A method of manufacturing an optoelectronic device is also disclosed. |
| US09331240B2 |
Utlraviolet light emitting devices and methods of fabrication
An ultraviolet light emitting semiconductor chip, its use in a LED, and methods of its fabrication are disclosed. The semiconductor chip can include a buffer layer of AlxGa1-xN, where 0 |
| US09331236B2 |
Engineered substrates having epitaxial formation structures with enhanced shear strength and associated systems and methods
Engineered substrates having epitaxial formation structures with enhanced shear strength and associated systems and methods are disclosed herein. In several embodiments, for example, an engineered substrate can be manufactured by forming a shear strength enhancement material at a front surface of a donor substrate and implanting ions a depth into the donor substrate through the shear strength enhancement material. The ion implantation can form a doped portion in the donor substrate that defines an epitaxial formation structure. The method can further include transferring the epitaxial formation structure from the donor substrate to a front surface of a handle substrate. The shear strength enhancement material can be positioned between the epitaxial formation structure and the front surface of the handle substrate and bridge defects in the front surface of the handle substrate. |
| US09331234B2 |
Semiconductor light emitting device and method for manufacturing semiconductor light emitting device
According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting layer. The p-type semiconductor layer includes a first p-side layer, a second p-side layer, and a third p-side layer. A concentration profile of Mg of a p-side region includes a first portion, a second portion, a third portion, a fourth portion, a fifth portion, a sixth portion and a seventh portion. The p-side region includes the light emitting layer, the second p-side layer, and the third p-side layer. A Mg concentration of the sixth portion is not less than 1×1020 cm−3 and not more than 3×1020 cm−3. The Al concentration is 1/100 of the maximum value at a second position. A Mg concentration at the second position is not less than 2×1018 cm−3. |
| US09331232B2 |
Process for annealing photovoltaic encapsulation polymer film
A process for annealing photovoltaic polymer encapsulation film (3), the film comprising polymer molecules substantially oriented along a machine direction, characterized in that the film is heated, supported on a support surface of support means (12), with heating means to a relaxation temperature to increase the isotropy of the polymer molecules such that the film is at least partly annealed, the support means (12) comprising a fluid (13) between the film (3) and the support surface. |
| US09331230B2 |
LED die dispersal in displays and light panels with preserving neighboring relationship
A method of dispersing semiconductor chips from a wafer of semiconductor chips onto a substrate while preserving the neighboring relationship of each chip to each adjacent chip is disclosed. The method includes dispersing the wafer into sequential columns of semiconductor chips with a first pitch between columns while preserving the neighboring relationship and sequentially dispersing the columns of semiconductor chips into rows of individual chips with a second pitch between rows onto a substrate while preserving the neighboring relationship. |
| US09331224B2 |
Photovoltaic roofing elements, photovoltaic roofing systems, methods and kits
The present invention relates generally to the photovoltaic generation of electrical energy. The present invention relates more particularly to photovoltaic roofing products for use in photovoltaically generating electrical energy. One aspect of the invention is a photovoltaic roofing element comprising: a flexible roofing substrate; a photovoltaic element disposed on the flexible roofing substrate; and an electrical connector operatively coupled to the photovoltaic element, wherein the flexible roofing substrate has formed therein a recess shaped to at least partially receive the electrical connector. |
| US09331222B2 |
Photovoltaic device
A photovoltaic device comprising: a base (1), a photovoltaic assembly (8) and a baffle plate (5), wherein the photovoltaic assembly is arranged in an inclined manner on the base from bottom up in a direction from front to rear, and behind the photovoltaic assembly, the baffle plate is arranged in an inclined manner on the base from bottom up in a direction from rear to front. The baffle plate reduces the profile coefficient and decreases the uplift by the action of wind load. |
| US09331210B2 |
Field effect transistor and method for manufacturing semiconductor device
A structure with which the zero current of a field effect transistor using a conductor-semiconductor junction can be reduced is provided. A floating electrode (102) including a conductor or a semiconductor and being enclosed by an insulator (104) is formed between a semiconductor layer (101) and a gate (105) so as to cross the semiconductor layer (101) and the floating electrode (102) is charged, whereby carriers are prevented from flowing from a source electrode (103a) or a drain electrode (103b). Accordingly, a sufficiently low carrier concentration can be kept in the semiconductor layer (101) and thus the zero current can be reduced. |
| US09331209B2 |
Nonvolatile memory and three-state FETs using cladded quantum dot gate structure
The present invention discloses structures and method of fabricating cladded quantum dot gate nonvolatile memory and three-state field-effect transistor devices that can be scaled down to sub-22 nm dimensions and embedded along side with other functional circuits. Another innovation is the design of transport channel, which comprises an asymmetric coupled well structure comprising two or more wells. This structure enhances the retention time in nonvolatile memory by increasing the effective separation between channel charge and the quantum dots located in the floating gate. The cladded quantum dot gate FETs can be designed in Si, InGaAs—InP and other material systems. The 3-state FET devices form the basis of novel digital circuits using multiple valued logic and advanced analog circuits. One or more layers of SiOx-cladded Si quantum dots can also be used as high-k dielectric layer forming the gate insulator over the transport channel of a sub-22 nm FET. |
| US09331201B2 |
Multi-height FinFETs with coplanar topography background
A semiconductor structure is provided that has semiconductor fins having variable heights without any undue topography. The semiconductor structure includes a semiconductor substrate having a first semiconductor surface and a second semiconductor surface, wherein the first semiconductor surface is vertically offset and located above the second semiconductor surface. An oxide region is located directly on the first semiconductor surface and/or the second semiconductor surface. A first set of first semiconductor fins having a first height is located above the first semiconductor surface of the semiconductor substrate. A second set of second semiconductor fins having a second height is located above the second semiconductor surface, wherein the second height is different than the first height and wherein each first semiconductor fin and each second semiconductor fin have topmost surfaces which are coplanar with each other. |
| US09331200B1 |
Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; and forming a first epitaxial layer, a second epitaxial layer, and a silicide layer in the substrate adjacent to the gate structure. Preferably, the first epitaxial layer, the second epitaxial layer, and the silicide layer comprise SiGeSn. |
| US09331194B2 |
Semiconductor device and method for manufacturing semiconductor device
A MOS semiconductor device has a MOS structure, including a p− region that surrounds an n+-type source region and has a net doping concentration lower than a concentration of a p-type impurity in a surface of a p-type well region, and a gate electrode that is provided on top of the surface of the p-type well region sandwiched between the n+-type source region and a surface layer of an n− layer, with a gate insulator disposed between the p-type well region and the gate electrode. This configuration can make the gate insulator thicker without increasing a gate threshold voltage, and help improve the reliability of the gate insulator and reduce the gate capacitance. |
| US09331193B2 |
Circuit arrangement
A circuit arrangement with at least a source contact (7), a gate contact (6), and a Schottky-Reverse contact (2), which is embodied as a Schottky-contact above a transistor channel and connected to the source contact such that in a return operation electrons can flow from a drain contact (5, 5.1, 5.2) via the Schottky-Reverse contact to the source contact. The circuit arrangement includes at least two transistor sections (A, A′, B, B′), with a first of the transistor sections (A, A′) including the Schottky-Reverse contact and a second of the transistor section (B, B′) being embodied without the Schottky-Reverse contact. The two transistor sections (A, A′, B, B′) are arranged alternating and embodied such that at least in a forward operation electrons can flow in a transistor channel from a source contact (7) to the drain contact (5, 5.1, 5.2), circumventing an area of influence (12) of the Schottky-Reverse contact. |
| US09331191B2 |
GaN device with reduced output capacitance and process for making same
A GaN transistor with reduced output capacitance and a method form manufacturing the same. The GaN transistor device includes a substrate layer, one or more buffer layer disposed on a substrate layer, a barrier layer disposed on the buffer layers, and a two dimensional electron gas (2DEG) formed at an interface between the barrier layer and the buffer layer. Furthermore, a gate electrode is disposed on the barrier layer and a dielectric layer is disposed on the gate electrode and the barrier layer. The GaN transistor includes one or more isolation regions formed in a portion of the interface between the at least one buffer layer and the barrier layer to remove the 2DEG in order to reduce output capacitance Coss of the GaN transistor. |
| US09331189B2 |
Low voltage nanoscale vacuum electronic devices
An electronic device including a first conducting layer, a second conducting layer, and an insulating layer provided between the conducting layers. At least one side wall extends from the first conducting layer to the second conducting layer and includes at least a portion of the first conducting layer, the second conducting layer and the insulating layer. A bias voltage is applied between the first and second conducting layers, wherein responsive to the bias voltage, a two dimensional electron system is induced at least in one of the first conducting layer and the second conducting layer, and wherein electrons from the two dimensional electron system are emitted from the side wall side wall as a result of Coulombic repulsion and travel in air from the one of the first conducting layer and the second conducting layer to the other of the first conducting layer and the second conducting layer. |
| US09331187B2 |
Bipolar transistor
P-type second semiconductor layers each interposed between a corresponding pair of n-type first semiconductor layers reduce the apparent doping concentration in the entire collector layer without reducing the doping concentrations in the first semiconductor layers. This improves the linearity of capacitance characteristics and enables sufficient mass productivity to be achieved. Interposing each of the second semiconductor layers between the corresponding pair of the first semiconductor layers reduce the average carrier concentration over the entire collector layer, which allows a wide depletion layer to be formed inside the collector layer and, as a result, reduces base-collector capacitance. |
| US09331184B2 |
Sonos device and method for fabricating the same
A silicon-oxide-nitride-oxide-silicon (SONOS) device is disclosed. The SONOS device includes a substrate; a first oxide layer on the substrate; a silicon-rich trapping layer on the first oxide layer; a nitrogen-containing layer on the silicon-rich trapping layer; a silicon-rich oxide layer on the nitrogen-containing layer; and a polysilicon layer on the silicon-rich oxide layer. |
| US09331179B2 |
Metal gate and gate contact structure for FinFET
An embodiment includes a substrate, wherein a portion of the substrate extends upwards, forming a fin, a gate dielectric over a top surface and sidewalls of the fin, a liner overlaying the gate dielectric, and an uninterrupted metallic feature over the liner a portion of the liner overlaying the gate dielectric, wherein the liner extends from a top surface of the uninterrupted metallic feature and covers sidewalls of the metallic feature, and wherein the gate dielectric, liner, and uninterrupted metallic feature collectively form a gate, a gate contact barrier, and a gate contact. |
| US09331173B2 |
Semiconductor device having a carbon containing insulation layer formed under the source/drain
A semiconductor arrangement and method of formation are provided herein. A semiconductor arrangement includes a metal connect in contact with a first active region and a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes recessing the metal connect over the STI region to form a recessed portion of the metal connect. Forming the recessed portion of the metal connect in contact with the first active region and the second active region mitigates RC coupling, such that a first gate is formed closer to a second gate, thus reducing a size of a chip on which the recessed portion is located. |
| US09331171B2 |
Manufacturing method for forming semiconductor structure
The present invention provides a manufacturing method of a semiconductor structure, comprising the following steps. First, a substrate is provided, a first dielectric layer is formed on the substrate, a metal gate is disposed in the first dielectric layer and at least one source/drain region (S/D region) is disposed on two sides of the metal gate, a second dielectric layer is then formed on the first dielectric layer, a first etching process is then performed to form a plurality of first trenches in the first dielectric layer and the second dielectric layer, wherein the first trenches expose each S/D region. Afterwards, a salicide process is performed to form a salicide layer in each first trench, a second etching process is then performed to form a plurality of second trenches in the first dielectric layer and the second dielectric layer, and the second trenches expose the metal gate. |
| US09331167B2 |
Nonvolatile semiconductor storage device and method for manufacturing the same
According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage device including: a semiconductor substrate; a source region and a drain region that are formed in the semiconductor substrate so as to be separated from each other and so as to define a channel region therebetween; a tunnel insulating film that is formed on the channel region; an insulative charge storage film that is formed on the tunnel insulating film; a conductive charge storage film that is formed on the insulative charge storage film so as to be shorter than the insulative charge storage film in a channel direction; an interlayer insulating film that is formed on the conductive charge storage film; and a gate electrode that is formed on the interlayer insulating film. |
| US09331166B2 |
Selective dielectric spacer deposition for exposing sidewalls of a finFET
Angled directional ion beams are directed to sidewalls of a gate structure that straddles at least one semiconductor fin. The directions of the angled directional ion beams are contained within a vertical plane that is parallel to the sidewalls of the at least one semiconductor. A pair of gate spacers are formed on sidewalls of the gate structure by accumulation of the deposited dielectric material from the angled directional ion beams and without use of an anisotropic etch, while the sidewalls of the semiconductor fins parallel to the directional ion beams remain physically exposed. A selective epitaxy process can be performed to form raised active regions by growing a semiconductor material from the sidewalls of the semiconductor fins. |
| US09331164B2 |
Silicon carbide semiconductor device
A silicon carbide semiconductor device includes: a silicon carbide semiconductor layer; and an electrode layer in contact with the silicon carbide semiconductor layer. In a case where the electrode layer is equally divided into two in a thickness direction in one cross section of the electrode layer in the thickness direction to obtain a first region facing the silicon carbide semiconductor layer and a second region opposite to the silicon carbide semiconductor layer, an area of a carbon portion containing the carbon in the first region is wider than an area of the carbon portion in the second region. At an interface region located up to 300 nm from an interface between the silicon carbide semiconductor layer and the electrode layer, the carbon portion includes a plurality of portions disposed with a space interposed therebetween, and a ratio of area occupied by the carbon portion is not more than 40%. |
| US09331159B1 |
Fabricating transistor(s) with raised active regions having angled upper surfaces
Methods of fabricating transistors having raised active region(s) with at least partially angled upper surfaces are provided. The method includes, for instance: providing a gate structure disposed over a substrate, the gate structure including a conformal spacer layer; forming a raised active region adjoining a sidewall of the conformal spacer layer; providing a protective material over the raised active region; selectively etching-back the sidewall of the conformal spacer layer, exposing a side portion of the raised active region below the protective material; and etching the exposed side portion of the raised active region to partially undercut the protective material, wherein the etching facilitates defining, at least in part, an at least partially angled upper surface of the raised active region of the transistor. |
| US09331158B2 |
Transistor devices and methods
The present disclosure includes transistor devices and methods. In one embodiment, a transistor includes a gate, a source, and a drain. According to one aspect of the disclosure, different resistive paths in the drain are compensated using different gate-to-drain capacitances. According to another aspect of the disclosure, current enters a drain at a center tap point and flows symmetrically outward under two adjacent gates to two adjacent sources. |
| US09331156B2 |
Semiconductor device and method for manufacturing the same
To manufacture a highly reliable semiconductor device by giving stable electric characteristics to a transistor. An oxide semiconductor film is deposited by a sputtering method with the use of a polycrystalline sputtering target. In that case, partial pressure of water in a deposition chamber before or in the deposition is set to be lower than or equal to 10−3 Pa, preferably lower than or equal to 10−4 Pa, more preferably lower than or equal to 10−5 Pa. Thus, a dense oxide semiconductor film is obtained. The density of the oxide semiconductor film is higher than 6.0 g/cm3 and lower than 6.375 g/cm3. |
| US09331149B2 |
Method for low temperature bonding and bonded structure
A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces. |
| US09331145B2 |
Lateral double diffused MOS transistors and methods of fabricating the same
A lateral double diffused MOS transistor including substrate of a first conductivity type, drift region of a second conductivity type and body region of the first conductivity type disposed in the substrate, source region of the second conductivity type disposed in the body region, drain region of the second conductivity type disposed in the drift region, isolation layer disposed in the drift region to surround sidewalls of the drain region, gate insulation layer and gate electrode sequentially stacked generally on the body region, first field plate extending from the gate electrode to overlap the drift region and to overlap a portion of the isolation layer, second field plate disposed above the isolation layer spaced apart from the first field plate, and coupling gate disposed above the isolation layer generally between the drain region and the second field plate, wherein the coupling gate is electrically connected to the second field plate. |
| US09331142B2 |
Zener diode having a polysilicon layer for improved reverse surge capability and decreased leakage current
A semiconductor device such as a Zener diode includes a first semiconductor material of a first conductivity type and a second semiconductor material of a second conductivity type in contact with the first semiconductor material to form a junction therebetween. A first oxide layer is disposed over a portion of the second semiconductor material such that a remaining portion of the second semiconductor material is exposed. A polysilicon layer is disposed on the exposed portion of the second semiconductor material and a portion of the first oxide layer. A first conductive layer is disposed on the polysilicon layer. A second conductive layer is disposed on a surface of the first semiconductor material opposing a surface of the first semiconductor material in contact with the second semiconductor material. |
| US09331140B2 |
Semiconductor devices having hybrid capacitors and methods for fabricating the same
A semiconductor device includes a plurality of capacitors disposed on a substrate and a support pattern supporting upper portions and lower portions of the capacitors. Each of the capacitors includes a lower electrode, an upper electrode, and a dielectric layer between the lower and upper electrodes. The lower electrode includes a first electrode portion electrically connected to the substrate and having a solid shape and a second electrode portion stacked on the first electrode portion and having a shape comprising an opening therein. The support pattern includes an upper pattern contacting sidewalls of top end portions of the lower electrodes and a lower pattern vertically spaced apart from the upper pattern. The lower pattern contacts sidewalls under the top end portions of the lower electrodes. |
| US09331135B2 |
Organic light emitting display
The present disclosure provides an organic light emitting display including: a first substrate including a display area where an organic light emitting device is formed and a non-display area where a plurality of pads are formed, a second substrate facing and spaced apart from the first substrate, a pattern formed in the non-display area of the first substrate and having openings, and an adhesive layer formed between the first substrate and the second substrate and covering a portion of the pattern. |
| US09331125B2 |
Solid-state imaging device using plasmon resonator filter
According to one embodiment, a solid-state imaging device includes: a first inorganic photoelectric converter; a semiconductor substrate that includes a light-receiving face to which light is to be incident and a circuit-formed surface on which a circuit including a readout circuit is formed, the light-receiving face facing the first inorganic photoelectric converter, the semiconductor substrate including a second inorganic photoelectric converter thereinside; and a first part including a microstructure arranged between the first inorganic photoelectric converter and the second inorganic photoelectric converter. |
| US09331118B2 |
Sensor and method for color photosensor array with shielded, deep-penetration, photodiodes for color detection
A photosensor has a masking layer having an opening over a central photodiode and a first adjacent photodiode, the first adjacent photodiode covered by the masking layer and located sufficiently near the central photodiode that at least some light admitted through the opening over the central photodiode reaches the first adjacent photodiode through the central photodiode. The photosensor also has a second adjacent photodiode; the second adjacent photodiode covered by the masking layer and located sufficiently near the first adjacent photodiode that at least some light admitted through the opening over the central photodiode is capable of reaching the second adjacent photodiode through the first adjacent photodiode. Circuitry is provided for reading the photodiodes and generating a blue, a green, and a red channel signal by processing signals read from the photodiodes. |
| US09331117B2 |
Sensor and lithographic apparatus
A backside illuminated sensor comprising a supporting substrate, a semiconductor layer which comprises a photodiode comprising a region of n-doped semiconductor provided at a first surface of the semiconductor layer, and a region of p-doped semiconductor, wherein a depletion region is formed between the region of n-doped semiconductor and the region of p-doped semiconductor, and a layer of p-doping protective material provided on a second surface of the semiconductor layer, wherein the first surface of the semiconductor layer is fixed to a surface of the supporting substrate. |
| US09331115B2 |
Image sensor having a gapless microlenses
An image sensor includes a plurality of photosensitive devices arranged in a semiconductor substrate. A planar layer is disposed over the plurality of photosensitive devices in the semiconductor substrate. A plurality of first microlenses comprised of a lens material is arranged in first lens regions on the planar layer. A plurality of lens barriers comprised of the lens material is arranged on the planar layer to provide boundaries that define second lens regions on the planar layer. A plurality of second microlenses comprised of the lens material is formed within the boundaries provided by the plurality of lens barriers that define the second lens regions on the planar layer. The plurality of lens barriers are integrated with respective second microlenses after a reflow process of the plurality of second microlenses. |
| US09331113B2 |
Wide-field lensless fluorescent imaging on a chip
An imaging device uses a fiber optic faceplate (FOF) with a compressive sampling algorithm for the fluorescent imaging of a sample over an large field-of-view without the need for any lenses or mechanical scanning. The imaging device includes a sample holder configured to hold a sample and a prism or hemispherical glass surface disposed adjacent the sample holder on a side opposite the lower surface of the sample holder. A light source is configured to illuminate the sample via the prism or the hemispherical surface, wherein substantially all of the light is subject to total internal reflection at the lower surface of the sample holder. The FOF is disposed adjacent to the lower surface of the sample holder, the fiber optic array having an input side and an output side. The device includes an imaging sensor array disposed adjacent to the output side of the fiber optic array. |
| US09331106B2 |
Pixel structure and fabrication method thereof
A fabrication method of a pixel structure includes the following steps. A first metal layer is patterned to form a source electrode and a drain electrode. A semiconductor material layer is patterned to form a channel layer and a pixel pattern. A first insulation layer is formed to cover the channel layer, the source electrode, the drain electrode and the pixel pattern. A gate electrode is formed on the first insulation layer located above the channel layer. A second insulation layer is formed to cover the gate electrode and the first insulation layer. A pixel opening is formed in the first insulation layer and the second insulation layer to expose a partial region of the pixel pattern. The partial region of the pixel pattern exposed by the pixel opening is modified so as to form a pixel electrode electrically connected to the drain electrode. |
| US09331105B2 |
Array substrate, manufacturing method thereof and display device
The invention discloses an array substrate, a manufacturing method thereof and a display device. The array substrate includes a gate, an active layer, a source and a drain on a substrate, and a pixel electrode located above the drain and lapped with the drain, and a part of the pixel electrode lapped with the drain is a lapping part of the pixel electrode; the array substrate further includes a first insulation layer located below the pixel electrode and in contact with the drain, the first insulation layer extends along the edge of the lapping part towards a direction away from the lapping part, part of the drain to be in contact with the lapping part is exposed from the first insulation layer, and the plane where the upper surface of the first insulation layer is located is lower than the plane where the upper surface of the drain is located. |
| US09331103B1 |
Liquid crystal display and manufacturing method thereof
A liquid crystal display includes a substrate, a gate line disposed on the substrate and including a bottom gate electrode, a first insulating layer covering the gate line, an active member including a channel which is disposed on the first insulating layer and overlaps the bottom gate electrode and a source electrode and a drain electrode at both end sides of the channel, a pixel electrode on the same layer as the active member, a second insulating layer covering the active member and the pixel electrode, a data line on the second insulating layer and connected to the active member, a passivation layer covering the data line, where the active member and the pixel electrode include an oxide semiconductor and the first insulating layer is a silicon nitride layer which includes a fluorine atom in the range of about 10 atm % to about 35 atm %. |
| US09331102B2 |
Liquid crystal display
A liquid crystal display includes: a first substrate; a gate line on the first substrate; a gate insulating layer on the gate line; a semiconductor layer on the gate insulating layer; a data line and a drain electrode on the semiconductor layer; a passivation layer covering the data line and the drain electrode; a common electrode on the passivation layer; an interlayer insulating layer on the common electrode; a pixel electrode on the interlayer insulating layer; an additional insulating layer on the pixel electrode; a second substrate opposite to the first substrate; and a black matrix on the second substrate, and including a vertical portion covering the data line and a horizontal portion covering the gate line and the drain electrode, where an empty portion is defined through the additional insulating layer in a portion corresponding to the black matrix. |
| US09331098B2 |
Semiconductor-on-insulator integrated circuit with reduced off-state capacitance
An integrated circuit assembly comprises an insulating layer, a semiconductor layer, a handle layer, a metal interconnect layer, and transistors. The insulating layer has a first surface, a second surface, and a hole extending from the first surface to the second surface. The semiconductor layer has a first surface and a second surface, the first surface of the semiconductor layer contacting the first surface of the insulating layer. The handle layer is coupled to the second surface of the semiconductor layer. The metal interconnect layer is coupled to the second surface of the insulating layer, the metal interconnect layer being disposed within the hole in the insulating layer. The transistors are located in the semiconductor layer. The hole in the insulating layer extends to at least the first surface of the semiconductor layer. The metal interconnect layer electrically couples a plurality of the transistors to each other. |
| US09331095B2 |
Vertically-integrated nonvolatile memory devices having laterally-integrated ground select transistors
Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines. |
| US09331094B2 |
Method of selective filling of memory openings
A method of fabricating a semiconductor device, such as a three-dimensional monolithic NAND memory string, includes providing an opening having a different sidewall material exposed on a sidewall of the opening than a bottom material exposed on a bottom of the opening, selectively forming a sacrificial material on the bottom of the opening but not on the sidewall of the opening, selectively forming a first layer on the sidewall of the opening but not on the sacrificial material located on the bottom of the opening, and selectively removing the sacrificial material to expose the bottom material on the bottom of the opening such that the first layer remains on the sidewall of the opening. |
| US09331092B2 |
Methods for forming contact landing regions in split-gate non-volatile memory (NVM) cell arrays
Methods and related structures are disclosed for forming contact landing regions in split-gate NVM (non-volatile memory) systems. A dummy select gate structure is formed while also forming select gates for split-gate NVM cells. A control gate layer is formed over the select gates and the dummy select gate structure, as well as an intervening charge storage layer. The control gate material will fill in gaps between the select gate material and the dummy select gate material. A non-patterned spacer etch is then used to etch the control gate layer to form a contact landing region associated with the dummy select gate structure while also forming spacer control gates for the split-gate NVM cells. The disclosed embodiments provide improved (e.g., more planar) contact landing regions without requiring additional processing steps and without increasing the pitch of the resulting NVM cell array. |
| US09331091B1 |
3D NAND memory with socketed floating gate cells and process therefor
A 3D NAND memory has vertical NAND strings across multiple memory layers above a substrate, with each memory cell of a NAND string residing in a different memory layer. Word lines in each memory layer each has a series of socket components aligned to embed respective floating gates of a group memory cells. In this way, the word line to floating gate capacitive coupling is enhanced thereby allowing a 4 to 8 times reduction in cell dimension as well as reducing floating-gate perturbations between neighboring cells. At the same time floating-gate to floating-gate crosstalk is reduced. The memory is fabricated by using odd and even subarrays of vertical shafts on a multi-layer slab to create at different times odd and even socket components that overlap to form continuous word lines with socket components. A self-aligned 4-masks process is employed on the multi-layer slab. |
| US09331090B2 |
Compact three dimensional vertical NAND and method of making thereof
A NAND device has at least a 3×3 array of vertical NAND strings in which the control gate electrodes are continuous in the array and do not have an air gap or a dielectric filled trench in the array. The NAND device is formed by first forming a lower select gate level having separated lower select gates, then forming plural memory device levels containing a plurality of NAND string portions, and then forming an upper select gate level over the memory device levels having separated upper select gates. |
| US09331089B2 |
Semiconductor memory device and method of fabricating the same
The semiconductor device includes a semiconductor substrate having a first active area defined by a first isolation layer; a gate insulating layer formed on the semiconductor substrate; a first conductive layer formed on the gate insulating layer; a dielectric layer formed on the first conductive layer; at least one first contact hole passing through the dielectric layer; a second conductive layer, formed on the dielectric layer, the second conductive layer filling the at least one first contact hole to contact the first conductive layer; and at least one first contact plug connected to the second conductive layer in the first active area, wherein the at least one first contact plug is offset from the at least one first contact hole to overlap the dielectric layer. |
| US09331087B2 |
Method of manufacturing a nonvolatile memory device
A method of manufacturing a nonvolatile memory device comprises forming a gate insulating layer and a first conductive layer over a semiconductor substrate that defines a first area in which selection lines will be formed and a second area in which word lines will be formed, performing an etch process to lower a height of the first conductive layer in the first area, forming a dielectric layer and a second conductive layer over the first conductive layer with a height that is different from the height of the first conductive layer, and performing a gate patterning process to form the selection lines and the word lines. |
| US09331086B2 |
Integrated circuit with trimming
An integrated circuit is provided, which comprises at least one first group each having at least one analog unit; and at least one second group each having at least one electronically settable semi-permanent switching unit coupled to the at least analog unit of the first group for trimming the first group and having at least one many-times-programmable and non-volatile cell (MTP). Each many-times-programmable cell (MTP) comprises at least one MOS transistor having a floating gate (FG) with a tunnel oxide (TO) and a first capacitor coupled to the floating gate (FG). The capacitance of the first capacitor is substantially larger than a gate-channel capacitance of the MOS transistor. |
| US09331082B2 |
Three-dimensional semiconductor device
A semiconductor device includes a stacked structure having first conductive layers stacked stepwise and first insulating layers interposed between the first conductive layers, wherein undercuts are formed under the first conductive layers and each of the first conductive layers includes a first region covered by the first conductive layer and a second region extending from the first region, contact pads coupled to the second regions of the respective first conductive layers, and a liner layer formed on the contact pads and filling the undercuts. |
| US09331079B2 |
Semiconductor device and method of manufacturing the same
A method of manufacturing a semiconductor device is provided. The method includes providing a semiconductor substrate, forming a plurality of fins on the semiconductor substrate, forming a plurality of shallow trench isolation (STI) structures on the semiconductor substrate on opposite sides of the fins, forming a dummy gate on the fins, forming gate spacers on opposite sides of the dummy gate, etching a first portion of the STI structures disposed outside a gate region, the first portion having a first predetermined thickness, forming an interlayer dielectric over the semiconductor substrate, removing the dummy gate, etching a second portion of the STI structures disposed in the gate region, the second portion having a second predetermined thickness, and forming a high-k dielectric layer and a metal gate in an area where the dummy gate is removed. |
| US09331078B2 |
Thin film transistor device
According to one embodiment, provided is a thin film transistor device with further improved area efficiency. First contact regions of a first semiconductor layer portion are formed with the first channel region therebetween in a predetermined direction and doped with an N-type impurity, one of the first contact regions electrically connected with a shared electrode, while the other electrically connected with a first electrode. Second contact regions of a second semiconductor layer portion are formed with the second channel region therebetween in the predetermined direction and doped with a P-type impurity, one of the second contact regions electrically connected with the shared electrode, while the other electrically connected with a second electrode. The first and second contact regions are partially disposed alternately and adjacently in a direction intersecting with the predetermined direction. |
| US09331077B2 |
Semiconductor device and manufacturing method of semiconductor device
A semiconductor device includes: a first conductivity type transistor and a second conductivity type transistor, wherein each of the first conductivity type transistor and the second conductivity type includes a gate insulating film formed on a base, a metal gate electrode formed on the gate insulating film, and side wall spacers formed at side walls of the metal gate electrode, wherein the gate insulating film is made of a high dielectric constant material, and wherein offset spacers are formed between the side walls of the metal gate electrode and the inner walls of the side wall spacers in any one of the first conductivity type transistor and the second conductivity type transistor, or offset spacers having different thicknesses are formed in the first conductivity type transistor and the second conductivity type transistor. |
| US09331076B2 |
Group III nitride integration with CMOS technology
A method of forming a structure that can be used to integrate Si-based devices, i.e., nFETs and pFETs, with Group III nitride-based devices is provided. The method includes providing a substrate containing an nFET device region, a pFET device region and a Group III nitride device region, wherein the substrate includes a topmost silicon layer and a <111> silicon layer located beneath the topmost silicon layer. Next, a trench is formed within the Group III nitride device region to expose a sub-surface of the <111> silicon layer. The trench is then partially filled with a Group III nitride base material, wherein the Group III nitride material base material has a topmost surface that is coplanar with, or below, a topmost surface of the topmost silicon layer. |
| US09331067B2 |
BigFET ESD protection that is robust against the first peak of a system-level pulse
Embodiments of an electrostatic discharge (ESD) protection device and a method of operating an ESD protection device are described. In one embodiment, an ESD protection device includes a bigFET configured to conduct an ESD pulse during an ESD event. The bigFET includes a backgate terminal, a source terminal, and a current distributor connected to the backgate terminal and the source terminal and configured to homogeneously activate a parasitic bipolar junction transistor of the bigFET in response to a current that is generated in the bigFET during the ESD pulse. Other embodiments are also described. |
| US09331063B2 |
Semiconductor device
A semiconductor device simplifies the manufacturing process. The device includes a protective chip which has a surface Zener diode to protect a light emitting chip with an LED formed therein from surge voltage. The protective chip is mounted over a wiring electrically coupled through a metal wire to an anode electrode coupled to a p-type semiconductor region whose conductivity type is the same as that of the semiconductor substrate of the chip. The anode electrode of the protective chip is electrically coupled to the back surface of the chip without PN junction, so even if the back surface is in contact with the wiring, no problem occurs with the electrical characteristics of the Zener diode. This eliminates the need to form an insulating film on the back surface of the chip to prevent contact between the back surface and the wiring, thus simplifying the manufacturing process. |
| US09331061B2 |
Parallel connection methods for high performance transistors
Parallel transistor circuits with reduced effects from common source induction. The parallel transistors include physical gate connections that are located electrically close to one another. The parallel circuits are arranged such that the voltage at the common gate connection resulting from transient currents across common source inductance is substantially balanced. The circuits include switching circuits, converters, and RF amplifiers. |
| US09331060B2 |
Device including two power semiconductor chips and manufacturing thereof
A device includes a first power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The device further includes a second power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The first and second power semiconductor chips are arranged one above another, and the first face of the first power semiconductor chip faces in the direction of the first face of the second power semiconductor chip. In addition, the first power semiconductor chip is located laterally at least partially outside of the outline of the second power semiconductor chip. |
| US09331058B2 |
Package with SoC and integrated memory
A semiconductor package includes a processor die (e.g., an SoC) and one or more memory die (e.g., DRAM) coupled to a ball grid array (BGA) substrate. The processor die and the memory die are coupled to opposite sides of the BGA substrate using terminals (e.g., solder balls). The package may be coupled to a printed circuit board (PCB) using one or more terminals positioned around the perimeter of the processor die. The PCB may include a recess with at least part of the processor die being positioned in the recess. Positioning at least part of the processor die in the recess reduces the overall height of the semiconductor package assembly. A voltage regulator may also be coupled to the BGA substrate on the same side as the processor die with at least part of the voltage regulator being positioned in the recess a few millimeters from the processor die. |
| US09331055B2 |
Semiconductor package and method for fabricating the same
A semiconductor package includes a package substrate on which a substrate pad is disposed, a structure disposed over the package substrate, a semiconductor chip disposed over the structure using an adhesive member having a magnetic material layer disposed therein, a chip pad disposed on a top surface of the semiconductor chip, and a bonding wire coupling the substrate pad and the chip pad. |
| US09331049B2 |
Bonding structure of bonding wire
The invention is aimed at providing a bonding structure of a copper-based bonding wire, realizing low material cost, high productivity in a continuous bonding in reverse bonding for wedge bonding on bumps, as well as excellent reliability in high-temperature heating, thermal cycle test, reflow test, HAST test or the like. The bonding structure is for connecting the bonding wire onto a ball bump formed on an electrode of a semiconductor device, the bonding wire and the ball bump respectively containing copper as a major component thereof. The bonding structure comprises a concentrated layer A provided at an interface of a bonding part of the ball bump and the bonding wire, wherein the concentration of a metal R other than copper in the concentrated layer A is not less than ten times the average concentration of the metal R in the ball bump; and a concentrated layer B provided at an interface of a bonding part of the ball bump and the electrode, wherein the concentration of the metal R in the concentrated layer B is not less than ten times the average concentration of the metal R in the ball bump. |
| US09331040B2 |
Manufacture of coated copper pillars
The present invention relates to a method for forming a copper pillar on a semiconducting substrate, the copper pillar having an underbump metallization area comprising a metal less noble than copper and optionally a solder bump on the top portion, and having a layer of a second metal selected from tin, tin alloys, silver, and silver alloys deposited onto the side walls of said copper pillar. A layer of a first metal which is more noble than copper is deposited onto the entire outer surface of the copper pillar prior to deposition of the second metal layer. The layer of a second metal then has at least a reduced number of undesired pin-holes and serves as a protection layer for the underlying copper pillar. |
| US09331028B2 |
Electric field gap device and manufacturing method
Substrate material is oxidized around side walls of a set of channels. A shielding structure means there is more oxide growth at the top than the bottom with the result that the non-oxidized substrate material area between the channels forms a tapered shape with a pointed tip at the top. These pointed substrate areas are then used to form cathodes. |
| US09331021B2 |
Chip-on-wafer package and method of forming same
A package according to an embodiment includes a first device package and a fan-out RDL disposed over the first device package. The fan-out RDL extends past edges of the first device package. The first device package comprises a first die having a first redistribution layer (RDL) disposed on a first substrate, a second die having a second RDL disposed on a second substrate, an isolation material over the first die and extending along sidewalls of the second die, and a conductive via. The first RDL is bonded to the second RDL, and the first die and the second die comprise different lateral dimensions. At least a portion of the conductive via extends from a top surface of the isolation material to contact a first conductive element in the first RDL. |
| US09331018B2 |
Semiconductor arrangement and formation thereof
One or more techniques for forming a semiconductor arrangement and resulting structures formed thereby are provided herein. The semiconductor arrangement includes a power divider comprising a transmission line and a resistor, where the transmission line is over and connected to an active area input, a first active area output and a second active area output. The semiconductor arrangement has a smaller chip size than a semiconductor arrangement where the transmission line is not over the active area input, the first active area output and the second active area output. The smaller chip size is due to the active area input, the first active area output and the second active area output being formed closer to one another than would be possible in a semiconductor arrangement where the transmission line is formed between at least one of the active area input, the first active area output or the second active area output. |
| US09331016B2 |
SOC design with critical technology pitch alignment
An SOC apparatus includes a plurality of gate interconnects with a minimum pitch g, a plurality of metal interconnects with a minimum pitch m, and a plurality of vias interconnecting the gate interconnects and the metal interconnects. The vias have a minimum pitch v. The values m, g, and v are such that g2+m2≧v2 and an LCM of g and m is less than 20 g. The SOC apparatus may further include a second plurality of metal interconnects with a minimum pitch of m2, where m2>m and the LCM of g, m, and m2 is less than 20 g. |
| US09331014B1 |
Tunable power distribution network and method of use thereof
An improved power distribution network comprises a substrate, an integrated circuit mounted on the substrate, first and second tunable decoupling capacitors mounted on the substrate, and a third decoupling capacitor formed in the integrated circuit. The power supply pin is connected to the first, second, and third capacitors; and the first and second capacitors are connected to the third capacitor as well. The capacitance values of the first and second tunable decoupling capacitors may be adjusted to reduce the magnitude of the system level impedance at least at those frequencies having substantial signal jitter to power noise sensitivity. |
| US09331013B2 |
Integrated capacitor
A structure includes first, second, and third conductive leaf structures. The first conductive leaf structure includes a first conductive midrib and conductive veins. The second conductive leaf structure is electrically connected to the first conductive leaf structure, and includes a second conductive midrib, conductive veins extending toward the first conductive midrib, and conductive veins extending away from the first conductive midrib. The third conductive leaf structure includes a third conductive midrib between the first conductive midrib and the second conductive midrib, conductive veins extending toward the first conductive midrib, and conductive veins extending toward the second conductive midrib. |
| US09331012B2 |
Method for fabricating a physical unclonable interconnect function array
A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer. |
| US09331003B1 |
Integrated circuit packaging system with pre-molded leadframe and method of manufacture thereof
An integrated circuit packaging system, and method of manufacture thereof, includes: lead islands; a pre-molded material surrounding a bottom of the lead islands; a device over a portion of the lead islands and having electrical connections to another portion of the lead islands, the electrical connections over areas of the another portion of the lead islands over areas covered by the pre-molded material; and an encapsulation over the device and the lead islands. |
| US09330994B2 |
Semiconductor device and method of forming RDL and vertical interconnect by laser direct structuring
A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. An insulating layer is formed over the semiconductor die and encapsulant. A first channel including a first conductive surface is formed in the insulating layer by laser radiation. A laser-activated catalyst is infused in the insulating layer to form the first conductive surface in the first channel upon laser radiation. A vertical interconnect is formed through the encapsulant. A first conductive layer is formed in the first channel over the first conductive surface. A second channel including a second conductive surface is formed in the encapsulant by laser radiation. The catalyst is infused in the encapsulant to form the second conductive surface in the second channel upon laser radiation. A second conductive layer is formed in the second channel over the second conductive surface. An interconnect structure is formed over the first conductive layer. |
| US09330992B2 |
Wiring substrate for a semiconductor device having differential signal paths
A semiconductor device is provided with improved resistance to noise. Conductive planes are respectively formed over wiring layers. One wiring layer is provided with a through hole land integrally formed with a through hole wiring. In other wiring layers located over the wiring layer with the through hole land, openings are respectively formed in the conductive planes. The area of each of the openings is larger than the plane area of the through hole land. |
| US09330990B2 |
Method of endpoint detection of plasma etching process using multivariate analysis
Disclosed is a method for determining an endpoint of an etch process using optical emission spectroscopy (OES) data as an input. Optical emission spectroscopy (OES) data are acquired by a spectrometer attached to a plasma etch processing tool. The acquired time-evolving spectral data are first filtered and demeaned, and thereafter transformed into transformed spectral data, or trends, using multivariate analysis such as principal components analysis, in which previously calculated principal component weights are used to accomplish the transform. A functional form incorporating multiple trends may be used to more precisely determine the endpoint of an etch process. A method for calculating principal component weights prior to actual etching, based on OES data collected from previous etch processing, is disclosed, which method facilitates rapid calculation of trends and functional forms involving multiple trends, for efficient and accurate in-line determination of etch process endpoint. |
| US09330985B2 |
Automated hybrid metrology for semiconductor device fabrication
Methods and systems are provided for fabricating and measuring features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves fabricating a feature of the semiconductor device structure on a wafer of semiconductor material, determining a hybrid recipe for measuring the feature, configuring a plurality of metrology tools to implement the hybrid recipe, and obtaining a hybrid measurement of the feature in accordance with the hybrid recipe. |
| US09330983B1 |
CMOS NFET and PFET comparable spacer width
A method including forming a p-type field effect transistor (pFET device) and an n-type field effect transistor (nFET device) each having sidewall spacers on opposite sidewalls of a dummy gate, conformally forming a first liner on the nFET device and depositing a fill material directly on the first liner of the nFET device, protecting the nFET device while growing an epitaxy in a source drain region of the pFET device, conformally forming a second liner above and in direct contact with the pFET device, including the epitaxy in the source drain regions of the pFET device, and along a vertical sidewall of a remaining portion of the fill material above the nFET device, depositing a first inter level dielectric above the second liner, and protecting the pFET device and the first inter level dielectric while growing a second epitaxy in a source drain region of the nFET device. |
| US09330972B2 |
Methods of forming contact structures for semiconductor devices and the resulting devices
One method disclosed herein includes, among other things, a method of forming a contact structure to a source/drain region of a transistor device. The transistor device includes a gate structure and a gate cap layer positioned above the gate structure. The method includes forming an extended-height epi contact structure that is conductively coupled to the source/drain region. The extended-height epi contact structure includes an upper surface that is positioned at a height level that is above a height level of an upper surface of the gate cap layer. The method further includes performing an etching process to trim at least a lateral width of a portion of the extended-height epi contact structure, and, after performing the etching process, forming a metal silicide material on at least a portion of the trimmed extended-height epi contact structure and forming a conductive contact on the metal silicide material. |
| US09330969B2 |
Air gap formation between bit lines with top protection
Air gaps are formed between bit lines by etching to remove sacrificial material from between bit lines. Bit lines are protected from etch damage. Sacrificial material may be selectively oxidized prior to deposition of bit line metal so that protective oxide lies along sides of bit lines during etch. Portions of protective material may be selectively formed on tops of bit lines prior to etching sacrificial material. |
| US09330968B1 |
Method of fabricating integrated circuit
A method of fabricating an integrated circuit includes the following steps. A first reticle is used to form a first pattern and a first alignment mark and a second reticle is used to form a second pattern and a second alignment mark in a same layer. A third reticle is aligned to the first alignment mark and the second alignment mark, to obtain an overlay correction value; additionally, a third reticle is aligned to the first alignment mark to obtain a first overlay correction value, a third reticle is aligned to the second alignment mark to obtain a second overlay correction value, and a total overlay correction value is obtained by trading off the first overlay correction value and the second overlay correction value. The third reticle is used to form a third pattern by aligning the third reticle with the total overlay correction value. |
| US09330967B2 |
Method of fabricating a semiconductor device with reduced leak paths
A method of fabricating a semiconductor device with reduced leak paths is disclosed. The method comprises etching a void in non-conductive material in the semiconductor device to provide a conduction path between isolated material, forming a non-conductive surface layer on an unintended conductive item adjacent to the void, and filling the void with a conductive material. Forming a non-conductive surface layer may comprise oxidizing a surface surrounding the void. Forming a non-conductive surface layer may comprise oxidizing a side wall of the void. Forming a non-conductive surface layer may comprise oxidizing a surface surrounding the void using plasma oxidation operations. Forming a non-conductive surface layer may comprise oxidizing a side wall of the void using plasma oxidation operations. The unintended conductive item may comprise a conductive impurity or conductive residue. The void may comprise a trench or a hole for a via. |
| US09330965B2 |
Double self aligned via patterning
A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer. |
| US09330960B2 |
Semiconductor devices including capacitors
A semiconductor device includes a first capacitor structure, a second capacitor structure, and an insulation pattern. The first capacitor structure includes a first lower electrode, a first dielectric layer and a first upper electrode sequentially stacked on a substrate. The second capacitor structure includes a second lower electrode, a second dielectric layer and a second upper electrode sequentially stacked on the substrate, and is adjacent to the first capacitor structure. The insulation pattern partially fills a space between the first and second capacitor structures, and an air gap is formed between the first and second capacitor structures on the insulation pattern. |
| US09330959B2 |
Isolated semiconductor layer in bulk wafer by localized silicon epitaxial seed formation
An integrated circuit may be formed by forming a buried isolation layer in an isolation recess in a single-crystal silicon-based substrate. Exposed lateral surfaces of the substrate at the buried isolation layer are covered with a dielectric sidewall. A seed trench is formed through the buried isolation layer to expose the substrate. A single-crystal silicon-based seed layer is formed through the seed trench, extending above the top surface of the buried isolation layer. A silicon-based non-crystalline layer is formed contacting the seed layer. A cap layer is formed over the non-crystalline layer. A radiant-induced recrystallization process converts the non-crystalline layer to a single-crystal layer aligned with the seed layer. The cap layer is removed and the single-crystal layer is planarized, leaving an isolated semiconductor layer over the buried isolation layer. |
| US09330958B2 |
Process for fabricating a heterostructure limiting the formation of defects
The invention relates to a process for fabricating a heterostructure comprising at least one thin layer and a carrier substrate made of a semiconductor, the process comprising: bonding a first substrate made of a single-crystal first material, the first substrate comprising a superficial layer made of a polycrystalline second material, to a second substrate so that a bonding interface is created between the polycrystalline layer and the second substrate; removing from the free surface of one of the substrates, called the donor substrate, a thickness thereof so that only a thin layer is preserved; generating a layer of amorphous semiconductor material between the first substrate and the bonding interface by amorphization of the layer of polycrystalline material; and crystallizing the layer of amorphous semiconductor material, the newly crystallized layer having the same orientation as the adjacent first substrate. |
| US09330955B2 |
Support ring with masked edge
A support ring for semiconductor processing is provided. The support ring includes a ring shaped body defined by an inner edge and an outer edge. The inner edge and outer edge are concentric about a central axis. The ring shaped body further includes a first side, a second side, and a raised annular shoulder extending from the first side of the ring shaped body at the inner edge. The support ring also includes a coating on the first side. The coating has an inner region of reduced thickness region abutting the raised annular shoulder. |
| US09330954B2 |
Substrate-to-carrier adhesion without mechanical adhesion between abutting surfaces thereof
Wafer to carrier adhesion without mechanical adhesion for formation of an IC. In such formation, an apparatus has a bottom surface of a substrate abutting a top surface of a support platform without adhesive therebetween. A material is disposed around the substrate and on the top surface of the support platform. The material is in contact with a side surface of the substrate to completely seal an interface as between the bottom surface of the substrate and the top surface of the support platform to retain abutment of the top surface and the bottom surface. |
| US09330946B1 |
Method and structure of die stacking using pre-applied underfill
Structures and processes for die stacking using an opaque or translucent pre-applied underfill material generally include selectively applying a low surface tension material to at least a portion of an alignment mark surface on a die; and applying the opaque or translucent underfill material to the die surface, wherein the underfill material does not wet or adhere to the low surface tension material such that the alignment mark surface is free of underfill material. |
| US09330945B2 |
Integrated circuit package system with multi-chip module
An integrated circuit package system with multi-chip module is provided including: providing an upper substrate having an upper chip thereon; positioning a lower chip under the upper chip, the lower chip having bottom interconnects thereon; encapsulating the upper chip and the lower chip with a chip encapsulant on the upper substrate with the bottom interconnects exposed; mounting the lower chip over a lower substrate with a gap between the chip encapsulant and the lower substrate; and filling the gap with a package encapsulant or chip attach adhesive. |
| US09330943B2 |
Low cost repackaging of thinned integrated devices
A method for mounting and embedding a thinned integrated circuit within a substrate is provided. In one embodiment, the thinned integrated circuit can receive one or more biasing substrate layers on a first surface of the thinned integrated circuit. When the thinned integrated circuit is embedded within a supporting substrate, such as a printed circuit board, the biasing substrate layers can position the thinned integrated circuit toward a centerline of the printed circuit board. Positioning the thinned integrated circuit toward the centerline can increase the resistance to breakage. |
| US09330942B2 |
Semiconductor device with wiring substrate including conductive pads and testing conductive pads
Miniaturization and high-performance of a semiconductor device are promoted, which has a package on package (POP) structure in which a plurality of semiconductor packages is stacked in a multistage manner. A testing conductive pad for determining the quality of a conduction state of a microcomputer chip and a memory chip is arranged outside a conductive pad for external input/output and thereby the route of a wire that couples the microcomputer chip and the memory chip to the testing conductive pad is reduced in length. Further, the wire that couples the microcomputer chip and the memory chip to the testing conductive pad is coupled to a pad in the outer row among conductive pads in two rows to be coupled to the microcomputer chip. |
| US09330940B2 |
Semiconductor device and manufacturing method thereof
There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 μm or more. |
| US09330932B1 |
Methods of fabricating features associated with semiconductor substrates
Some embodiments include a method in which a mixture of polynucleotide structures comprises a set of surface shapes. Surface shapes of some polynucleotide structures are complementary to surface shapes of other polynucleotide structures. The complementary surface shapes lock together along interfaces between adjacent polynucleotide structures to incorporate the polynucleotide structures into a polynucleotide mask. The polynucleotide mask is used during fabrication of features associated with a semiconductor substrate. Some embodiments include a method in which a semiconductor substrate comprises registration regions configured to adhere individual polynucleotide structures to specific locations of the semiconductor substrate. The adhered polynucleotide structures are incorporated into a polynucleotide mask which is used during fabrication of features associated with the semiconductor substrate. |
| US09330928B2 |
Methods for selective etching of a multi-layer substrate
A method is disclosed for the selective etching of a multi-layer metal oxide stack comprising a platinum layer on a TiN layer on an HfO2 or ZrO2 layer on a substrate. In some embodiments, the method comprises a physical sputter process to selectively etch the platinum layer, followed by a plasma etch process comprises CHF3 and oxygen to selectively etch the TiN, HfO2 or ZrO2 layers with respect to the substrate. |
| US09330923B1 |
Non-volatile memory and method of manufacturing the same
A semiconductor process includes the steps of providing a semiconductor substrate with a logic region and a memory region, defining memory gates on the memory region, forming a conformal spacer layer on the memory gates and the semiconductor substrate, and performing an etch process on the conformal spacer layer, such that the conformal spacer layer on sidewalls of the memory gates transforms into spacers, and the conformal spacer layer between the memory gates transforms into a concave block covering the semiconductor substrate between the memory gates. |
| US09330918B2 |
Edge termination by ion implantation in gallium nitride
A method of making an edge terminated semiconductor device includes providing a GaN substrate having a GaN epitaxial layer grown thereon and exposing a portion of the GaN epitaxial layer to ion implantation. The energy dose is selected to provide a resistivity that is at least 90% of maximum achievable resistivity. The method also includes depositing a conductive layer over a portion of the implanted region. |
| US09330907B2 |
Material quality, suspended material structures on lattice-mismatched substrates
Suspended structures are provided using selective etch technology. Such structures can be protected on all sides when the selective undercut etch is performed, thereby providing excellent control of feature geometry combined with superior material quality. |
| US09330906B2 |
Stress relieving semiconductor layer
A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers. |
| US09330903B2 |
Method of manufacturing semiconductor device, substrate processing apparatus and non-transitory computer-readable recording medium
Provided a method including forming a laminated film where a first film and a second film are laminated on a substrate by performing a cycle a predetermined number of times under a condition where a borazine ring structure in a fourth process gas is maintained. The cycle includes: (a) forming the first film by performing a first set a predetermined number of times, wherein the first set includes supplying a first process gas and supplying a second process gas to the substrate; and (b) forming the second film by performing a second set a predetermined number of times, wherein the second set includes supplying a third process gas and supplying the fourth process gas to the substrate. |
| US09330900B2 |
Layer-by-layer deposition of carbon-doped oxide films through cyclical silylation
Embodiments of the present invention generally relate to methods of forming carbon-doped oxide films. The methods generally include generating hydroxyl groups on a surface of the substrate using a plasma, and then performing silylation on the surface of the substrate. The hydroxyl groups on the surface of the substrate are then regenerated using a plasma in order to perform an additional silylation. Multiple plasma treatments and silylations may be performed to deposit a layer having a desired thickness. |
| US09330899B2 |
Method of depositing thin film
A method for forming a silicon germanium oxide thin film on a substrate in a reaction space may be performed using an atomic layer deposition (ALD) process. The process may include at least one cycle comprising a germanium oxide deposition sub-cycle and a silicon oxide deposition sub-cycle. The germanium oxide deposition sub-cycle may include contacting the substrate with a germanium reactant, removing excess germanium reactant, and contacting the substrate with a first oxygen reactant. The silicon oxide deposition sub-cycle may include contacting the substrate with a silicon reactant, removing excess silicon reactant, and contacting the substrate with a second oxygen reactant. The films of the present disclosure exhibit desirable etch rates relative to thermal oxide. Depending on the films' composition, the etch rates may be higher or lower than the etch rates of thermal oxide. |
| US09330892B2 |
Simultaneous inorganic mass spectrometer and method of inorganic mass spectrometry
An inorganic mass spectrometer capable of measuring a relevant and large or the full mass spectral range simultaneously may include a suitable ion source (e.g., an ICP mass spectrometer with an ICP ion source), an ion transfer region, ion optics to separate ions out of a plasma beam, a Mattauch-Herzog type mass spectrometer with a set of charged particle beam optics to condition the ion beam before an entrance slit, and a solid state multi-channel detector substantially separated from ground potential and separated from the potential of the magnet. |
| US09330891B2 |
Plasma processing method and plasma processing apparatus
A plasma processing method of the present disclosure includes attaching a Si-containing material or a N-containing material to an electrostatic chuck that is provided in a processing container and attached with a reaction product containing C and F, in a state where a workpiece is not mounted on the electrostatic chuck; adsorbing the workpiece by the electrostatic chuck attached with the Si-containing material or the N-containing material when the workpiece is carried into the processing container; processing the workpiece with plasma; and separating the workpiece processed with plasma from the electrostatic chuck attached with the Si-containing material or the N-containing material. |
| US09330889B2 |
Plasma generation device with microstrip resonator
A plasma generation device, a system including a plasma generation device, and a method of generating plasma and vacuum UV (VUV) photons are described. In a representative embodiment, plasma generation device, includes: a substrate having a first surface and a second surface; a resonant ring-shaped structure disposed over the first surface of the substrate, the resonant ring-shaped structure having dimensions selected to support at least one standing wave having more than one electric field maximum along a length of the resonant ring-shaped structure; a ground plane disposed on the second surface of the substrate; and an apparatus configured to provide a gas at locations of the electric field maxima. |
| US09330885B2 |
Method of stack patterning using a ion etching
The embodiments disclose a method of stack patterning, including loading a stack into a stationary stack stage, rotating one or more ion beam grid assemblies substantially concentrically aligned with the stationary stack stage to etch the stack and controlling the operation of the one or more ion beam grid assemblies to achieve substantial axial uniformity of the etched stack. |
| US09330882B2 |
Particle beam detector
A particle beam detector is disclosed. The particle beam detector can include a particle beam receiving portion configured to convert particle beam energy to heat, and a plurality of temperature measuring devices disposed about the particle beam receiving portion. A location of a particle beam on the particle beam receiving portion can be determined by a temperature difference between at least two of the plurality of temperature measuring devices. |
| US09330879B2 |
Bremstrahlung target for intensity modulated X-ray radiation therapy and stereotactic X-ray therapy
Direct write electron-beam-to-x-ray converters are described, which may be programmed to focus x-rays into an arbitrary shape to provide spatial and intensity modulation to irradiate a malady such as a tumor. An integrated structure of the electron beam to x-ray converter comprises a collimating grid containing a target fluid. The collimating grid comprises a plurality of individual cells enclosed in a housing assembly. An electron beam aimed at a selected individual cell of the collimating grid may be converted to an x-ray beam within the target fluid. |
| US09330875B2 |
Method for determining a circuit element parameter
A method for determining a circuit element parameter in a ground fault circuit interrupter circuit. An electrical signal provided to a first node is used to generate another electrical signal at a second node. The electrical signal at the second node is multiplexed with a modulation signal to generate a modulated signal that is then filtered and converted into a digital representation of a portion of the circuit element parameter. The electrical signal at the second node is multiplexed with the modulation signal after it has been phase shifted to produce a modulated signal that is filter and converted into a digital representation of another portion of the circuit element parameter. In another aspect, a slope based solenoid self-test method is used for self-testing in a GFCI circuit. Alternatively, a method for determining a wiring fault is provided using a digital filter. |
| US09330871B2 |
Relay
A relay includes: a fixed terminal on which a fixed contact is provided; a movable terminal on which a movable contact is provided; a cam that has an elliptical circumference shape, and is rotatable while a portion of the circumference shape is contacting a surface of the movable terminal; and a driving unit that rotates the cam so that respective portions located at one ends of a major axis and a minor axis of the elliptical circumference shape alternately contact the surface of the movable terminal; wherein when the portion located at one end of the major axis of the elliptical circumference shape of the cam contacts the surface of the movable terminal, the movable terminal is deformed elastically so that the movable contact contacts the fixed contact. |
| US09330870B2 |
AC line powered relay driving circuits
Disclosed are exemplary embodiments of relay drive circuits. In an exemplary embodiment, a relay drive circuit generally includes a first diode, a second diode, a third diode, a first transistor, a second transistor, a first capacitor, and a second capacitor. The relay drive circuit is operable to transform an AC voltage to a DC voltage, and then use the DC voltage to control on/off of the relay. |
| US09330868B2 |
Contact assembly for a vacuum circuit breaker
A contact assembly and a vacuum circuit breaker for interrupting an electrical current are disclosed. The contact assembly includes an outer field generating element for generating a first axial magnetic field (AMF), and an inner field generating element for generating a second AMF opposite to the first AMF. The inner field generating element can be coaxial with the outer field generating element and can have a smaller diameter than the outer field generating element. The outer field generating element can be cup-shaped and slotted with non-radial slots to generate the first AMF. The contact assembly can include an innermost conducting element for nominal current conduction and coaxially adjusted with the inner field generating element. |
| US09330864B2 |
Pivoting electrical switch
The embodiments discussed herein relate to electrical switches. Specifically, the embodiments include a pivoting switch that translates a rotational movement of a portion of the pivoting switch into a linear movement for toggling a button. The pivoting switch can include a pin that extends into a bracket in order to define and limit a rotational movement of the pivoting switch. The pivoting switch can further include a switch cavity that can force a knob of the button to move with the pivoting switch. The embodiments can further include an electrical switch having a welded cover plate. The welded cover plate can include arms that extend across and are welded to one or more surfaces of the electrical switch. The welded cover plate provides a more secure retaining mechanism for the electrical switch in order to reduce bending of certain portions of the electrical switch when the electrical switch is toggled. |
| US09330862B2 |
Keyboard device
The present invention discloses a keyboard device. The keyboard device includes a sheet, a membrane switch, an actuating component, and a protrusion keycap structure. The membrane switch is disposed on a side of the sheet. The actuating component is disposed on a side of the membrane switch far away from the sheet and is for pressing the membrane switch to actuate the membrane switch. The protrusion keycap structure is disposed on a side of the actuating component far away from the membrane switch and is for driving the actuating component to actuate the membrane switch upon being pressed. The protrusion keycap structure includes a mylar film. |
| US09330860B2 |
Handle operating device for circuit breaker
The present disclosure relates to a handle operating device for a circuit breaker, and there is provided a handle operating device including a connecting rod configured to transfer power for operating a manual operating handle that manually operates the on/off of a circuit breaker from the outside; a movable frame connected to the connecting rod to be movably coupled to an outer surface of a circuit breaker case in a direction parallel to the operating direction of the manual operating handle; a movable member provided at the movable frame in an interlocking manner to move the manual operating handle; a slot hole is formed on the moving member in an inclined manner from the moving direction of the manual operating handle; and a fastening member fastened to the movable member and movable frame through the slot hole. |
| US09330858B2 |
Power tool
A power tool, especially an angle grinder, includes at least one grip housing, at least one switching unit that has at least one latch element arranged on the grip housing, and at least one bearing unit configured to mount the latch element such that it is mobile at least with respect to the grip housing. When the latch element is actuated, the bearing unit is configured to guarantee a stroke movement of the latch element along a trajectory of a value greater zero, starting from an end of the latch element closer to the connecting region of the grip housing in the direction of an end of the latch element away from the connecting region, which end is configured to be gripped. |
| US09330852B2 |
Tantalum capacitor and method of manufacturing the same
There is provided a tantalum capacitor including: a capacitor body containing tantalum powder and having a tantalum wire exposed to one end thereof; a positive electrode lead frame including a positive electrode terminal part and a positive electrode connection part formed by upwardly bending a portion of the positive electrode terminal part from the outside toward the inside and connected to the tantalum wire; a negative electrode lead frame having the capacitor body mounted thereon; and a molded part formed to enclose the capacitor body while exposing a lower surface of the positive electrode terminal part of the positive electrode lead frame and a lower surface of the negative electrode lead frame. |
| US09330851B2 |
Electrode material for aluminum electrolytic capacitor, and method for producing same
An electrode material for an aluminum electrolytic capacitor, comprising, as constituent elements, sintered body of a powder of at least one member selected from the group consisting of aluminum and aluminum alloys, and an aluminum foil substrate supporting the sintered body thereon, wherein (1) the powder has an average particle size D50 of 0.5 to 100 μm, (2) the sintered body is formed on one surface or both surfaces of the aluminum foil substrate and has a total thickness of 10 to 1,000 μm, (3) the porosity of the sintered body is 35 to 49% by volume, and (4) the sintered body is obtained by applying a rolling process to a film made from a composition comprising a powder of at least one member selected from the group consisting of aluminum and aluminum alloys, and subsequently sintering the film. |
| US09330848B2 |
Electronic component, electronic-component-embedded substrate, and method for producing electronic component
An electronic component includes a body and first and second external electrodes arranged on an external surface of the body. An edge portion of the first external electrode and an edge portion of the second external electrode face each other on the body. The first and second external electrodes each include a copper-metal-containing layer and a protective copper oxide layer covering the copper-metal-containing layer within the edge portion of the first and second external electrodes, respectively. |
| US09330844B2 |
Multilayer ceramic capacitor and mounting board therefor
There is provided a multilayer ceramic capacitor including: a ceramic body having dielectric layers laminated in a width direction thereof; an active region in which capacitance is formed, by including first and second internal electrodes alternately exposed to end surfaces of the ceramic body while having the dielectric layer interposed therebetween; an upper margin part prepared above the active region; a lower margin part prepared below the active region on the dielectric layer and being thicker than the upper margin part; and first and second external electrodes, wherein, when half of thickness of the ceramic body is denoted by A, thickness of the lower margin part is denoted by B, half of thickness of the active region is denoted by C, and thickness of the upper margin part is denoted by D, 1.047≦(B+C)/A≦1.562 is satisfied. |
| US09330841B2 |
Base metal combination electrode of electronic ceramic component and manufacturing method thereof
The present invention provides a base metal combination electrode of electronic ceramic component and manufacturing method thereof, wherein said base metal combination electrode comprises a first base metal electrode layer covering on two sides of said electronic ceramic chip and a second base metal electrode layer covering on said first base metal electrode layer, the manufacturing method for base metal combination electrode of electronic ceramic component comprises using thermal spray equipment to spray the electrode material to the surface of electronic ceramic chip. Comparing with using silver paste or copper paste only, it reduces the cost of electrode material without destroying the function of the electrode. The manufacturing method for base metal combination electrode of the present invention has simple technological process, high preparation efficiency and low cost, and it reduces the production cost of electrode of the electronic ceramic component on the whole. |
| US09330840B2 |
Apparatus for manufacturing field pole magnetic body
An apparatus for manufacturing a field pole magnetic body formed by laminating magnet segments produced by cutting and dividing a permanent magnet and to be arranged in a rotary electric machine includes a housing part adapted to successively house a plurality of the magnet segments having adhesive applied to cut surfaces with the cut surfaces facing each other and has an inner side surface adjacent to outer side surfaces of the housed magnet segments, and a pressing unit adapted to press the magnet segments housed in the housing part toward a bottom part of the housing part in a longitudinal direction. The magnet segments are restrained in a width direction and a thickness direction by the inner side surface of the housing part when the magnet segments are pressed by the pressing unit. |
| US09330835B2 |
Signal transmitting apparatus
A signal transmitting apparatus using a plane coil for a sending coil and a receiving coil respectively, so that the outer diameters of the sending coil and the receiving coil can be decreased, and a signal can be stably transmitted from a sending side to a receiving side. The signal transmitting apparatus is provided with: a sending coil driven by an inputted signal; a receiving coil configured to output a received signal in response to the sending coil being driven; a pre-processing circuit to which the received signal outputted by the receiving coil is inputted; and a detecting circuit configured to detect the inputted signal from a signal outputted by the pre-processing circuit. |
| US09330833B2 |
Power supply with low electro-magnetic interference and inductor for power supply with low electro-magnetic interference
A power supply circuit includes an input configured to receive an input voltage, an output configured to supply an output voltage, at least one inductor, at least one diode, and at least one switch. The inductor may have a parasitic capacitance less than about 100 pF. Related inductors are also disclosed. |
| US09330831B2 |
Common mode filter and power supply device having the same
A common mode filter and a power supply device having the same are provided. The common mode filter includes a first inductor having a first winding number, a second inductor facing the first inductor and having a second winding number, a first intermediate terminal branching from an intermediate portion of a coil of the first inductor, and a second intermediate terminal branching from an intermediate portion of a coil of the second inductor. The effects of two filters are obtained from one common mode filter and the volume is reduced, so that a light, thin, short, and short module is provided. |
| US09330827B2 |
Method of manufacturing inductors for integrated circuit packages
A process of making inductors for integrated circuit packages may involve forming an inductor upon a magnetic film on a package substrate. Conductors coupled either to a die or a voltage converter extend perpendicularly through the film to conductive plates, defining current paths through and across the film. |
| US09330824B2 |
Direct drive generator-equipped with flux pump and integrated cryogenics
This invention relates generally to a generator having a rotor with a rotor structure, a set of flux pumps secured to the rotor structure and a cooling system secured to the rotor structure for cooling each one of the flux pumps. The flux pump includes separate superconducting loops in separate layers with each superconducting loop including a plurality of sections in revolutions in its respective layer. Each cooling system includes a compressor, heat exchanger, expansion valve, and cryocooler inline with one another. The rotor is rotatably mounted to a stator component through a bearing. A power supply circuit includes components integrated within the rotor for providing power to the flux pump and the compressor. |
| US09330823B1 |
Integrated circuit structure with inductor in silicon interposer
An integrated circuit structure can include an interposer having a plurality of conductive layers and a die coupled to the interposer through an internal interconnect structure. The integrated circuit structure can include an inductor implemented within at least one of the conductive layers of the interposer. The inductor can include a first terminal and a second terminal. The first terminal and the second terminal can be coupled to the internal interconnect structure. |
| US09330821B2 |
Magnetic nanoparticles
Methods for preparing magnetic nanoparticles comprising metal, metal carbide, metal nitride, metal sulfide, metal phosphide, metal oxide or a mixture thereof are disclosed. Methods for preparing magnetic nanoparticles having a core comprising metal, metal carbide, metal nitride, metal sulfide, metal phosphide, or a mixture thereof and a metal oxide shell are also disclosed. The methods comprise the solution-phase decomposition of a precursor at elevated temperature then exposure of the reaction mixture to an oxidizing medium, such as air. |
| US09330820B2 |
Method for making electrically conductive three-dimensional structures
Methods are provided for fabricating three-dimensional electrically conductive structures. Three-dimensional electrically conductive microstructures are also provided. The method may include providing a mold having at least one microdepression which defines a three-dimensional structure; filling the microdepression of the mold with at least one substrate material; molding the at least one substrate material to form a substrate; and depositing and patterning of at least one electrically conductive layer either during the molding process or subsequent to the molding process to form an electrically conductive structure. In one embodiment, the three-dimensional electrically conductive microstructure comprises an electrically functional microneedle array comprising two or more microneedles, each including a high aspect ratio, polymeric three dimensional substrate structure which is at least substantially coated by an electrically conductive layer. |
| US09330819B2 |
Semi-finished wire for a Nb3Sn superconducting wire
A semi-finished wire (1) for a Nb3Sn superconducting wire (45) has a multiplicity of elements containing Nb packed against each other (6). The elements containing Nb (6) each have a rod containing Nb (7) and an enclosure containing Cu (8) surrounding the latter. The semi-finished wire also has a structure containing Sn (5) and a matrix containing Cu (4) in which the structure containing Sn (5) is disposed and on and/or in which the elements containing Nb (6) are disposed. The enclosures containing Cu (8) of the elements containing Nb (6), contain Sn. The semi-finished wire is suitable for manufacturing an Nb3Sn superconducting wire with which further improved superconducting current-carrying capacity is achieved. |
| US09330817B2 |
Enameled flat wire
An enameled flat wire includes a flat wire and an enamel coating. The difference in thickness of the enamel coating on flat surfaces between a maximum thickness and a minimum thickness is equal to or less than 25% of the predetermined thickness. The enamel coating prior to baking includes a maximum surface curvature on each of the rounded corners of the wire, and a depression on at least one of the flat surfaces of the wire, the depression has a maximum surface curvature. The maximum surface curvature of the depression is larger than the maximum surface curvature of the enamel coating prior to baking on at least one of the rounded corners thereof. |
| US09330815B2 |
Cable structures with insulating tape and systems and methods for making the same
Cable structures with insulating tape and systems and methods for making the same are provided. In some embodiments, a cable may include a first group of conductors extending along a length of the cable, a tape wrapped directly around the first plurality of conductors along the length of the cable, and a second group of conductors extending along the length of the cable, where the tape electrically isolates the first group of conductors from the second group of conductors. The second group of conductors may extend around the tape or the tape may be wrapped directly around the second group of conductors. The tape may be a polymeric tape that may or may not include an adhesive. |
| US09330813B2 |
Conductive path structure and wire harness
A conductive path structure includes a conductor that includes a first conductive portion and a second conductive portion which are connected to each other through a cut-off facilitating portion, a first covering member that covers the first conductive portion and the cut-off facilitating portion, and a second covering member that covers the second conductive portion and the cut-off facilitating portion. The second covering member covers the cut-off facilitating portion through the first covering member. The second covering member slidably covers the first covering member. |
| US09330803B2 |
Radiation therapy apparatus with an aperture assembly and associated methods
A radiation therapy apparatus includes a housing, a radiation source carried by the housing, and at least one aperture assembly carried by the housing. The aperture assembly includes a radiation aperture body having a shaped opening therein to control a radiation dosing profile, and an aperture holder with an aperture-receiving passageway therein receiving the radiation aperture body, and having a recessed end. A cover is received within the recessed end of the aperture holder and retains the radiation aperture body within the aperture holder. The cover has an opening aligned with the shaped opening in the radiation aperture body. The radiation aperture body, the aperture receiving passageway of the aperture holder and the opening of the cover have angled interfaces therebetween. A radiation filter is carried by the housing. |
| US09330797B2 |
Jet pump beam weldless keeper lock plate
A lock plate for a locking device of a jet pump beam, the locking device including a locking sleeve including a lower portion, may include a beam bolt opening sized to receive the locking sleeve, and a spring arm including plurality of spring a ratchet teeth sized to mesh with locking sleeve ratchet teeth included in the lower portion of the locking sleeve, the spring arm being structured such that the spring arm has both i) an engaged position where the locking sleeve is in the beam bolt opening and at least a portion of the capture feature overlaps vertically with an upper surface of the lower portion of the locking sleeve, and ii) a disengaged position where the locking sleeve is in the beam bolt opening and the capture feature does not overlap vertically with the upper surface. |
| US09330796B2 |
Stable startup system for a nuclear reactor
A stable startup system includes a reactor vessel containing coolant, a reactor core submerged in the coolant, and a heat exchanger configured to remove heat from the coolant. The stable startup system further includes one or more heaters configured to add heat to the coolant during a startup operation and prior to the reactor core going critical. |
| US09330795B2 |
Method for preparing a mixed fuel comprising uranium and at least one actinide and/or lanthanide applying a cation exchange resin
The invention relates to a method for preparing a fuel based on oxide, carbide, and/or oxycarbide comprising uranium and at least one actinide and/or lanthanide component, comprising the following steps: a step for preparing a load solution consisting in a nitric solution comprising said actinide and/or lanthanide in the form of actinide and/or lanthanide nitrates and uranium as a hydroxylated uranyl nitrate complex; a step for passing said solution over a cation exchange resin comprising carboxylic groups, with which the actinide and/or the lanthanide in cationic form and the uranium as uranyl remain bound to the resin; a heat treatment step of said resin so as to obtain said fuel. |
| US09330791B2 |
Memory systems and methods of managing failed memory cells of semiconductor memories
A memory system includes a memory controller configured to replace a memory block including a failed memory cell with a unit cache block of a cache memory in response to detection of the failed memory cell in the memory block. The unit cache block is smaller than a minimum size of a memory cell array capable of being blocked by an operating system, and the unit cache block has substantially the same storage capacity as the memory block. |
| US09330789B2 |
Short-checking methods
In an embodiment, a short-checking method includes charging a data line to an initial voltage while activating a memory cell coupled to the data line, allowing the data line to float while continuing to activate the memory cell, sensing a resulting voltage on the data line after a certain time, and determining whether a short exists in response to a level of the resulting voltage. |
| US09330781B2 |
Nonvolatile memory device and memory system including the same
A nonvolatile memory device is provided. The nonvolatile memory device includes a memory cell array, an anti-fuse cell array, a sense amplifier, a page buffer, and a control logic. The memory cell array includes memory cells connected to word lines and bit lines. The anti-fuse cell array stores setting information for controlling the memory cell array. The anti-fuse cell array includes anti-fuse cells connected to the bit lines. The sense amplifier is connected to the bit lines to sense the memory cells or the anti-fuse cells. The page buffer stores data that is read out from the memory cells or the anti-fuse cells. The control logic controls the sense amplifiers and the page buffer to read out data from the memory cell array or the anti-fuse cell array. |
| US09330780B1 |
Semiconductor device including a memory block and method of operating the same
A semiconductor device and method of operating the same are provided. The semiconductor device may include a memory block including drain select transistors connected to bit lines, source select transistors connected to a common source line, and memory cells connected between the drain select transistors and the source select transistors. The semiconductor device may include an operation circuit configured to repeatedly perform a program operation and a program verifying operation to increase threshold voltages of the drain select transistors to a target level. The operation circuit may be configured to apply a level lower than a verifying voltage initially applied to the drain select transistors for the program verifying operation. The level being lower than a normal level. The operation circuit may be configured to increase the verifying voltage to the normal level whenever the program verifying operation is repeated. |
| US09330778B2 |
Group word line erase and erase-verify methods for 3D non-volatile memory
An erase operation for a 3D stacked memory device assigns storage elements to groups according to an expected erase speed. The storage elements are then erased according to their group to provide a more uniform erase depth and a tighter erase distribution. In one approach, the control gate voltages are set differently for the different groups to slow down the storage elements which are expected to have a faster programming speed. An erase or inhibit status can be set for all groups together. In another approach, the control gate voltages are common for the different groups but an erase or inhibit status is set for each group separately. |
| US09330771B2 |
Semiconductor device
A semiconductor device includes memory strings each including a drain select transistor, memory cells and a source select transistor, which are connected between a bit line and a common source line and suitable for operating based on voltages applied to a drain select line, word lines and a source select line, respectively, and an operation circuit suitable for performing a pre-program operation, an erase operation and a post-program operation on the memory strings. The operation circuit sequentially performs erase operations on the drain select transistors included in the memory strings. |
| US09330768B2 |
Semiconductor memory device, memory system including the same and operating method thereof
A semiconductor memory device, a memory system including the same and an operating method thereof are set forth. The semiconductor memory device includes a memory cell array having a plurality of memory cells, peripheral circuits configured to perform a program operation using an incremental step pulse programming (ISPP) method on selected memory cells from among the plurality of memory cells. The semiconductor memory device includes an additional program using set program voltages to set memory cells, and a control logic configured to control the peripheral circuits to perform the program in the manner of the ISPP method and the additional program. |
| US09330764B2 |
Array fanout pass transistor structure
A device, such as an integrated circuit including memory, includes an array of memory cells on a substrate. A row/column line, such as a local word line or local bit line, is disposed in the array. The row/column line includes a pass transistor structure comprising a semiconductor strip in a first patterned layer over the substrate. The semiconductor strip includes a semiconductor channel body, a contact region on one side of the semiconductor channel body, and an extension on another side of the semiconductor channel body, which reaches into the memory cells in the array. A select line in a second patterned layer crossing the semiconductor channel body is provided. The pass transistor structure can be implemented in a fanout structure for row/column lines in the array. |
| US09330763B1 |
Operation modes for an inverted NAND architecture
Methods for performing memory operations on a memory array that includes inverted NAND strings are described. The memory operations may include erase operations, read operations, programming operations, program verify operations, and erase verify operations. An inverted NAND string may include a string of inverted floating gate transistors or a string of inverted charge trap transistors. In one embodiment, an inverted floating gate transistor may include a tunneling layer between a floating gate of the inverted floating gate transistor and a control gate of the inverted floating gate transistor. The arrangement of the tunneling layer between the floating gate and the control gate allows electrons to be added to or removed from the floating gate via F-N tunneling between the floating gate and the control gate. The inverted NAND string may be formed above a substrate and oriented such that the inverted NAND string is orthogonal to the substrate. |
| US09330756B2 |
Apparatuses and methods for sensing using an integration component
The present disclosure includes apparatuses and methods for sensing a resistance variable memory cell. A number of embodiments include circuitry to provide a programming signal to a memory cell in the array, the programming signal associated with programming the memory cell to a particular data state; and determine, via an integration component, if a data state of the memory cell changes to a different data state responsive to the programming signal being provided. |
| US09330753B2 |
Memory sanitation using bit-inverted data
Method and apparatus for sanitizing a memory using bit-inverted data. In accordance with various embodiments, a memory location is sanitized by sequential steps of reading a bit value stored in a selected memory cell of the memory, inverting the bit value, and writing the inverted bit value back to the selected memory cell. The memory cell may be erased between the reading and writing steps, as well as after the writing step. Random bit values may be generated and stored to the memory cell, and run-length limited constraints can be used to force bit-inversions. |
| US09330751B2 |
SRAM wordline driver supply block with multiple modes
A wordline driver supply block supporting multiple operation modes of a memory of a microprocessor in a device for reducing power consumption thereof. |
| US09330749B1 |
Dynamic selection of output delay in a memory control device
In an example, a memory control device includes an output circuit, an output delay unit, and a write-levelization controller. The output circuit is coupled to provide an output signal comprising a data signal or data strobe signal for a synchronous dynamic random access memory (SDRAM) system having a plurality of ranks. The output delay unit is coupled to apply an output delay to a bitstream to be transmitted to generate the output signal. The output delay includes an aggregate of a de-skew delay and a write-levelization delay. The write-levelization delay controller is coupled to adjust the write-levelization delay for each write transaction to the SDRAM system of a plurality of write transactions based on a selected rank of the plurality of ranks. The de-skew delay is the same across the plurality of ranks for each of the plurality of write transactions. |
| US09330747B2 |
Non-volatile latch using spin-transfer torque memory device
Described is an apparatus of a non-volatile logic (NVL), the apparatus comprises: a sensing circuit to sense differential resistance; a first magnetic-tunneling-junction (MTJ) device coupled to the sensing circuit; a second MTJ device coupled to the sensing circuit, the first and second MTJ devices operable to provide differential resistance; and a buffer to drive complementary signals to the first and second MTJ devices respectively. |
| US09330744B2 |
MRAM with magnetic material surrounding contact plug
An electronic device includes semiconductor memory, and the semiconductor memory includes a contact plug which is disposed over a substrate and extends in a vertical direction; a variable resistance element which is coupled to the contact plug and includes a first magnetic layer having a variable magnetization direction, a second magnetic layer having a pinned magnetization direction, and a tunnel barrier layer interposed between the first magnetic layer and the second magnetic layer; and a third magnetic layer which surrounds a sidewall of the contact plug and has a same magnetization direction as the second magnetic layer. |
| US09330743B2 |
Memory cores of resistive type memory devices, resistive type memory devices and method of sensing data in the same
A memory core of a resistive type memory device includes at least a first resistive type memory cell coupled to a bit-line, a first resistance to voltage converter and a bit-line sense amplifier. The first resistance to voltage converter is coupled to the bit-line at a first node. The first resistance to voltage converter converts a resistance of the first resistive type memory cell to a corresponding voltage based on a read column selection signal. The bit-line sense amplifier is coupled to the bit-line at the first node and is coupled to a complementary bit-line at a second node. The bit-line sense amplifier senses and amplifies a voltage difference of the bit-line and the complementary bit-line in response to a sensing control signal. |
| US09330740B1 |
First-in first-out circuits and methods
A first first-in first-out (FIFO) circuit includes a storage circuit, a second first-in first-out (FIFO) circuit, and a third first-in first-out (FIFO) circuit. The storage circuit stores write data at a write address in response to a write clock signal. The storage circuit outputs read data from a read address in response to a read clock signal. A write pointer indicating the write address is synchronized with the write clock signal. A read pointer indicating the read address is synchronized with the read clock signal. The second first-in first-out (FIFO) circuit synchronizes the write pointer with the read clock signal. The third first-in first-out (FIFO) circuit synchronizes the read pointer with the write clock signal. |
| US09330737B2 |
Allocating memory address space between DIMMs using memory controllers
A memory controller enters a memory mode, allocating memory address space within a pair of dual in line memory modules (DIMMs) such that each DIMM of the pair contains unallocated memory address space corresponding to allocated memory space in the other DIMM. The memory controller enters another memory mode, modifying the allocation of the memory address space from a first DIMM of the pair of DIMMs to a second DIMM of the pair of DIMMs. The data is moved from allocated memory address space of the first DIMM to unallocated memory address space in the second DIMM. |
| US09330735B2 |
Memory with deferred fractional row activation
Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the sub-row to be activated. |
| US09330731B2 |
Circuits in strap cell regions
A circuit comprises a first transistor and a second transistor in a strap cell region between a first memory array and a second memory array of a memory device. The first transistor includes a first node connected to a first data line, and a second node connected to a second data line. The first node and the second node of the first transistor are complementary to each other in voltage level. Further, the second transistor includes a first node connected to the second data line, and a second node connected to the first data line. The first node and the second node of the second transistor are complementary to each other in voltage level. |
| US09330726B1 |
System capable of integrating user-entered game event data with corresponding video data
A mobile application is disclosed enabling a first sporting event spectator to efficiently record game actions and a second sporting event spectator to simultaneously record real-time video of the game actions. Using a mobile device having a touch screen, the first user can efficiently, and with limited user interaction, indicate fast paced game actions of players engaged in a sport. Using a separate mobile device, or a video system in communication with a network, the second user can record video of a presently occurring game in which the game actions occur. A system in communication with the first and second users' devices can receive indications of game actions, and receive video of the game, and associate each indicated game action with a portion of the video of the game action. The system may, for example, use these associations to generate an index that enables users to view descriptions of the game actions and jump to corresponding video clips. |
| US09330724B2 |
Data recording method, data erasure method, data display method, storage device, storage medium, and program
The objective of the present invention is to manage reference movies using an index file, without causing the user to be perplexed. The reference movies are generated because of, for instance, the upper limit of the file size. The index file manages sets of information regarding the files being managed. Examples of these sets of information are information for determining whether or not a file is presented to the user, information for determining whether or not a file is original, and information indicating whether or not nondestructive editing has been done. Based on such information, the erasure, displaying a list, and so on are carried out. Thus, it is possible to manage the reference movies using the index file, without causing the user to be perplexed. |
| US09330722B2 |
Methods and architecture for indexing and editing compressed video over the world wide web
A system and method is provided for editing and parsing compressed digital information. The compressed digital information may include visual information which is edited and parsed in the compressed domain. In a preferred embodiment, the present invention provides a method for detecting moving objects in a compressed digital bitstream which represents a sequence of fields or frames of video information for one or more captured scenes of video. |
| US09330720B2 |
Methods and apparatus for altering audio output signals
Methods, systems and computer readable media for altering an audio output are provided. In some embodiments, the system may change the original frequency content of an audio data file to a second frequency content so that a recorded audio track will sound as if a different person had recorded it when it is played back. In other embodiments, the system may receive an audio data file and a voice signature, and it may apply the voice signature to the audio data file to alter the audio output of the audio data file. In that instance, the audio data file may be a textual representation of a recorded audio data file. |
| US09330718B2 |
Techniques for adding interactive features to videos
Techniques are disclosed for adding interactive features to videos to enable users to create new media using a dynamic blend of motion and still imagery. The interactive techniques can include allowing a user to change the starting time of one or more subjects in a given video frame, or only animate/play a portion of a given frame scene. The techniques may include segmenting each frame of a video to identify one or more subjects within each frame, selecting (or receiving selections of) one or more subjects within the given frame scene, tracking the selected subject(s) from frame to frame, and alpha-matting to play/animate only the selected subject(s). In some instances, segmentation, selection, and/or tracking may be improved and/or enhanced using pixel depth information (e.g., using a depth map). |
| US09330714B2 |
Tape media kiss-contact read verification
A supplemental module that includes one or more read elements periodically engages a magnetic recording medium, and the read elements generate an electrical signal corresponding to transitions written to the magnetic recording medium by a write element. A computer receives information representative of the electrical signal and determines if a quality metric of the magnetic recording medium derived from the electrical signal is within a defined range. If the quality metric is not within the defined range, a defined action is performed by the computer. |
| US09330712B2 |
Data conversion method on storage medium, apparatus and program
In a data conversion auxiliary module which is at a higher level than a file system in a disk management hierarchy, data stored in a storage medium, which becomes an object, is successively accessed. Then, a data conversion module captures a sector-unit access request to a device driver from the file system, converts data of a sector which is returned from the device driver, and writes the conversion data in the sector. Thereby, data conversion can be executed on a specific region of the storage medium, which is associated with the data in the storage medium. |
| US09330708B2 |
Erasing recorded data by utilizing read head and write head
Techniques for reducing the time required for erasing specific data recorded on a tape medium. A specific group of records is erased without preliminarily locating the erasure end position. This is carried out by simultaneously utilizing three heads, that is, two read heads and one write head, to detect the erasure end position during data erasure. Various embodiments are applicable to tape media as well as other storage media. Various embodiments are not only applicable as a file system cooperating as a combination of hardware (H/W) and software (S/W), but also applicable in systems, such as databases, that directly use storage without an intermediary file system. |
| US09330704B2 |
Optical information recording device, optical information recording and reproducing device, optical information recording method, optical information recording and reproducing method, and optical element
The optical information recording and reproducing method realizes an increased number of multiplexing in recording and favorably stabilized signal recording in a manner of uniforming media consumption in angle-multiplexed recording by changing a phase of signal light on a pixel basis in a manner in which the speed of a phase change on a pixel basis is constant or is greater than or equal to a certain speed in a page and between pages when the driving speed of a phase mask changes at the time of recording. The optical information recording and reproducing method, while moving an optical element that adds phase information to a light flux which includes two-dimensional page data information in a direction that is perpendicular to an optical axis of the light flux, records the page data on the recording medium by adding the phase information to the light flux. |
| US09330702B2 |
Thermally-assisted magnetic recording head having a heat sink
A thermally-assisted magnetic recording head includes a main pole, a waveguide, a plasmon generator, and a heat sink. The heat sink includes a first metal layer, a second metal layer, and an intermediate layer. The intermediate layer is interposed between the first metal layer and the second metal layer. Each of the first and second metal layers is formed of a metal material. The intermediate layer is formed of a material that is higher in Vickers hardness than the metal material used to form the first metal layer and the metal material used to form the second metal layer. |
| US09330701B1 |
Dynamic track misregistration dependent error scans
Systems and methods are disclosed for using track misregistration values, representing an amount of off-track deviation of a write element, to dynamically increment error scan counters for proximate storage areas. In certain embodiments, an apparatus may comprise a processor configured to perform a write operation to record data to a target track of a data storage medium using a write element, determine an amount of deviation of the write element from a center line of the target track, and increment an error scan counter for an area of the data storage medium proximate to the target track based on the amount of deviation. |
| US09330700B2 |
Magnetic tape storage medium
A magnetic tape storage medium includes at least one servo band with at least two sub-bands along a longitudinal extension of the medium. Servo bursts are written to the sub-bands to determine positional information of the medium. A first of the sub-bands includes a first burst with at least one servo stripe inclined at a first non-zero angle with respect to a direction orthogonal to the longitudinal extension of the medium followed by a second burst comprising at least one servo stripe inclined at a second non-zero angle with respect to the direction orthogonal to the longitudinal extension of the medium, which second angle is different from the first angle. A second of the sub-bands includes a first burst having at least one servo stripe followed by a second burst having at least one servo stripe, the first and the second bursts parallel to each other. |
| US09330694B1 |
HDD microactuator having reverse poling and active restraining layer
A PZT microactuator such as for a hard disk drive is a multi-layer PZT in which a first layer of PZT material that is disposed away from the side of the microactuator that is bonded to the suspension, responds to an actuation voltage differently than does a second layer of PZT material that is closer to the suspension, thus acting as a constraining layer and thus increasing stroke sensitivity of the microactuator. The first layer of PZT material can be made to respond differently than the second layer by not being activated, by being thicker that the second layer, or by being reverse poled as compared to the second layer. The effective stroke length of the microactuator is increased by the presence and effect of constraining layer. |
| US09330693B1 |
Suspension circuit trace employing stacked traces and windowed stainless steel layer
An electrical circuit for a disk drive suspension has a first signal trace above a grounded support layer which is typically stainless steel, and a second signal trace below the support layer, the two signal traces typically being opposite polarities of a differential signal pair. The support layer between the two signal traces is windowed, and the two traces are physically separated by a distance that equals the nominal thickness of the support layer plus the thicknesses of the top and bottom dielectric layers that separate the signal traces from the support layer. The physical separation combined with the windowing reduces the impedance and increases the bandwidth of the differential pair. The impedance can be controlled by the percentage of windowing in the support layer. |
| US09330691B1 |
Microwave assisted magnetic head
According to one embodiment, a microwave assisted magnetic head includes a spin torque oscillator, and if driving current of the spin torque oscillator is zero, a magnetization direction of the spin injection layer is identical regardless of polarity of recording current, and if the driving current of the spin torque oscillator is not zero, the magnetization direction of the spin injection layer changes in response to the polarity of the recording current. |
| US09330687B2 |
Microwave-assisted recording head with stable oscillation
A magnetic recording head for microwave-assisted magnetic recording is disclosed. In one embodiment, a magnetic recording head is for applying a magnetic field from a main pole of said magnetic recording head for recording data to a disk. Further comprising a spin torque oscillator adjacent to said magnetic recording head and is for generating a high-frequency magnetic field at a stable frequency and amplitude. Further comprising a capacitor connected to an upper electrode of said spin torque oscillator via a first resistor and a lower electrode of said spin torque oscillator via a second resistor. |
| US09330677B2 |
Method and apparatus for generating a noise reduced audio signal using a microphone array
A method and apparatus for generating a noise reduced output signal from sound received by a first and second microphone arranged as a microphone array. The method includes transforming sound received by the first microphone into a first input signal and sound received by a second microphone into a second input signal and calculating, for each of the frequency components, a weighted sum of at least two intermediate signals calculated from the input signals by means of complex valued transfer functions and real valued Equalizer functions. The method includes a weighing function with range between zero and one, with quotients of signal energies of the intermediate functions as arguments of the weighing function, and generating the noise reduced output signal based on the weighted sum of the intermediate functions and based on the weighted sum of the first and second intermediate function at each of the frequency components. |
| US09330676B2 |
Determining whether speech interference occurs based on time interval between speech instructions and status of the speech instructions
A method to filter out speech interference is provided. The method includes defining a time threshold by using a probability distribution model. When a current instruction from a speech input is recognized, a reference instruction recognized from the speech input is obtained. The current instruction is recognized right after the recognition of the reference instruction, wherein the reference instruction and the current instruction correspond to a first time point and a second time point respectively. The method includes determining whether speech interference occurs according to a comparison result of the time threshold and an interval between the first time point and the second time point as well as a state corresponding to the first time point. The method includes filtering out the reference instruction and the current instruction if the speech interference occurs, and outputting the reference instruction or the current instruction if the speech interference does not occur. |
| US09330672B2 |
Frame loss compensation method and apparatus for voice frame signal
A frame loss compensation method and apparatus for audio signals are disclosed. The method includes: when a first frame immediately following a correctly received frame is lost, judging a frame type of the first lost frame, and when the first lost frame is a non-multi-harmonic frame, calculating MDCT coefficients of the first lost frame by using MDCT coefficients of one or more frames prior to the first lost frame; obtaining an initially compensated signal of the first lost frame according to the MDCT coefficients of the first lost frame; and performing a first class of waveform adjustment on the initially compensated signal of the first lost frame and taking an adjusted time-domain signal as a time-domain signal of the first lost frame. The apparatus includes a frame type judgment module, an MDCT coefficient acquisition module, an initial compensation signal acquisition module and an adjustment module. |
| US09330671B2 |
Energy conservative multi-channel audio coding
The invention relates to the technical field of audio encoding and/or decoding technologies, and thus concerns an overall encoding procedure and associated decoding procedure. The encoding procedure involves at least two signal encoding processes (S1-S3) operating on signal representations of a set of audio input channels, as well as residual encoding (S7-S8). It also involves a dedicated process (S4-S6) to estimate and encode energies of the audio input channels. Each encoding process is associated with a corresponding decoding process. In the overall decoding procedure the decoded signals from each encoding process are preferably combined such that the output channels are close to the input channels in terms of energy and/or quality. Normally, the combination step also adapts to the possible loss of one or more signal representation in part or in whole, such that the energy and quality is optimized with the signals at hand in the decoder. In this way, the overall quality of the output channels is improved. |
| US09330670B2 |
Computing device and signal enhancement method
A computing device provides a resonance algorithm to process digital signal data according to a principle of physical resonance. The resonance algorithm determines a division length n of digital signal data according to a frequency f1 of an audio signal to be detected and a sampling frequency f2, which is used for sampling the digital signal data by a coder.Furthermore, the resonance algorithm divides the digital signal data into a serial of data segments by the division length n, and obtains enhanced digital signal data by accumulating a number m of the data segments. |
| US09330668B2 |
Sharing voice application processing via markup
A system is described for processing voice applications comprising a client device (10) having associated data indicative of its computing capability. The system has access to a plurality of scripts specifying tasks to be performed in a voice-based dialog between a user and the system. The scripts are interpretable at a browser level. A server (20) selects an appropriate script for the client device (10) based on the associated data. An interpreter layer processes the selected script to determine a first set of instructions to be performed on the client device (10) and a second set of instructions to be performed on the server (20) for the dialog. Computation is thus shared between the client device and the server based on the computational capability of the client. |
| US09330667B2 |
Method and system for endpoint automatic detection of audio record
A method and system for endpoint automatic detection of audio record is provided. The method comprises the following steps: acquiring a audio record text and affirming the text endpoint acoustic model for the audio record text; starting acquiring the audio record data of each frame in turn from the audio record start frame in the audio record data; affirming the characteristics acoustic model of the decoding optimal path for the acquired current frame of the audio record data; comparing the characteristics acoustic model of the decoding optimal path acquired from the current frame of the audio record data with the endpoint acoustic model to determine if they are the same; if yes, updating a mute duration threshold with a second time threshold, wherein the second time threshold is less than a first time threshold. This method can improve the recognizing efficiency of the audio record endpoint. |
| US09330665B2 |
Automatic updating of confidence scoring functionality for speech recognition systems with respect to a receiver operating characteristic curve
Automatically adjusting confidence scoring functionality is described for a speech recognition engine. Operation of the speech recognition system is revised so as to change an associated receiver operating characteristic (ROC) curve describing performance of the speech recognition system with respect to rates of false acceptance (FA) versus correct acceptance (CA). Then a confidence scoring functionality related to recognition reliability for a given input utterance is automatically adjusted such that where the ROC curve is better for a given operating point after revising the operation of the speech recognition system, the adjusting reflects a double gain constraint to maintain FA and CA rates at least as good as before revising operation of the speech recognition system. |
| US09330663B2 |
Initiating actions based on partial hotwords
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, receiving audio data; determining that an initial portion of the audio data corresponds to an initial portion of a hotword; in response to determining that the initial portion of the audio data corresponds to the initial portion of the hotword, selecting, from among a set of one or more actions that are performed when the entire hotword is detected, a subset of the one or more actions; and causing one or more actions of the subset to be performed. |
| US09330661B2 |
Accuracy improvement of spoken queries transcription using co-occurrence information
Techniques disclosed herein include systems and methods for voice-enabled searching. Techniques include a co-occurrence based approach to improve accuracy of the 1-best hypothesis for non-phrase voice queries, as well as for phrased voice queries. A co-occurrence model is used in addition to a statistical natural language model and acoustic model to recognize spoken queries, such as spoken queries for searching a search engine. Given an utterance and an associated list of automated speech recognition n-best hypotheses, the system rescores the different hypotheses using co-occurrence information. For each hypothesis, the system estimates a frequency of co-occurrence within web documents. Combined scores from a speech recognizer and a co-occurrence engine can be combined to select a best hypothesis with a lower word error rate. |
| US09330660B2 |
Grammar fragment acquisition using syntactic and semantic clustering
A method and apparatus are provided for automatically acquiring grammar fragments for recognizing and understanding fluently spoken language. Grammar fragments representing a set of syntactically and semantically similar phrases may be generated using three probability distributions: of succeeding words, of preceding words, and of associated call-types. The similarity between phrases may be measured by applying Kullback-Leibler distance to these tree probability distributions. Phrases being close in all three distances may be clustered into a grammar fragment. |
| US09330658B2 |
User intent analysis extent of speaker intent analysis system
A speaker intent analysis system and method for validating the truthfulness and intent of a plurality of participants' responses to questions. A computer stores, retrieves, and transmits a series of questions to be answered audibly by participants. The participants' answers are received by a data processor. The data processor analyzes and records the participants' speech parameters for determining the likelihood of dishonesty. In addition to analyzing participants' speech parameters for distinguishing stress or other abnormality, the processor may be equipped with voice recognition software to screen responses that while not dishonest, are indicative of possible malfeasance on the part of the participants. Once the responses are analyzed, the processor produces an output that is indicative of the participant's credibility. The output may be sent to proper parties and/or devices such as a web page, computer, e-mail, PDA, pager, database, report, etc. for appropriate action. |
| US09330655B2 |
Increasing the number of cylinders in an internal combustion engine in a virtual fashion
A device to generate an engine noise and a method to generate the engine noise at a time period between two directly successive ignition events of an internal combustion engine wherein the engine noise increases the number of cylinders of the internal combustion engine in a virtual fashion. |
| US09330654B2 |
Active noise cancellation decisions in a portable audio device
Active noise cancellation (ANC) circuitry is coupled to the input of an earpiece speaker in a portable audio device, to control the ambient acoustic noise outside of the device and that may be heard by a user of the device. A microphone is to pickup sound emitted from the earpiece speaker, as well as the ambient acoustic noise. Control circuitry deactivates the ANC in response to determining that an estimate of how much sound emitted from the earpiece speaker has been corrupted by noise indicates insufficient corruption by noise. In another embodiment, the ANC decision is in response to determining that an estimate of the ambient noise level is greater than a threshold level of an audio artifact that could be induced by the ANC. Other embodiments are also described and claimed. |
| US09330649B2 |
Selecting audio samples of varying velocity level
Systems and methods for selecting audio samples in response to musical stimuli are provided. In some embodiments, an audio sample can be selected based on the excitation state of an instrument. A musical stimulus can be received, and a current excitation level associated with previously received musical stimuli calculated. An audio sample can be selected for playback using the current excitation level. In some embodiments, audio samples having different velocity levels can be selected in response to repeated musical stimuli. A first instance of a musical stimulus having a first velocity level can be received, and a first audio sample corresponding to the first velocity level played back. A second instance of the musical stimulus having the first velocity level can be received, and a second audio sample corresponding to a second velocity level can be selected for playback. The first and second audio samples can have different audio characteristics. |
| US09330639B1 |
Adjustable pitch stop for the tremolo bar of an electric guitar
An adjustable pitch stop for a tremolo bar of an electric guitar, the adjustable pitch stop having a generally C-clamp or U-shaped clamp and set screw to secure the pitch stop to the tremolo bar, the C-clamp having a tubular member attached thereto, there being a threaded male member slidably secured through the tubular member, the threaded male member having an adjustment knob positioned at one end to adjust the positioning of the male threaded member, the male threaded member having a stop member at the opposing end for contact with the body of the electric guitar, the being interposed between the adjustment knob and the tubular member, a first locking nut, there being disposed a second locking nut and biasing component secured between the stop member and the tubular member allowing the presetting of two descending notes. |
| US09330638B2 |
Tremolo device for a stringed musical instrument
The tremolo device can be used in stringed musical instruments, and more particularly in electric guitars. It provides a simplified construction allowing easier usage and improved sustain, wherein, in the front portion of the rear string saddle (5) an opening (5f) is formed, which axis is nonparallel to and does not intersect the saddle assembly shaft (7) axis and also does not intersect the string (29) axis. In the opening (5f) the fine tuning spring (6) is disposed, reaching the opening bottom with one end and with the other—the back wall of the front string saddle (4). |
| US09330637B1 |
Bi-directional loading clamp improvement
A bi-directional clamping device for string musical instruments includes a forward end closer the nut and a rearward end further the nut fashioned to be operable to receive a string inserted essentially unimpeded in a first direction, the first direction extending in the direction of the strings typically from the rearward end of the clamping device towards the nut and further fashioned to be operable to optionally receive a string inserted essentially unimpeded in a second direction, the second direction extending in the direction of the strings typically towards the rearward end of the clamping device from the nut. The arrangement further allows for larger diameter strings with taper cores, etc. to be clamped in order to meet requirements for extended range instruments. |
| US09330635B1 |
Strap free ergonomic guitar with stabilizing sound box rest pocket and optional gripping pad
The sound box of a guitar is modified to add a concave shaped pocket that can be placed at various locations along the sound box body in order to be used to rest against the thigh of the instrumentalist while in the sitting position. An optional rubber gripping pad can be attached to the sound box rest pocket to add additional gripping power if desired. The sound box rest pocket can be applied to both electric and acoustic guitars and eliminates the need to wear guitar straps when playing in the sitting position. The sound box rest pocket does not negatively affect the quality of the sound produced from the guitar. |
| US09330633B2 |
Display control device, method, and non-transitory computer readable medium storing program
A method including causing a projection apparatus that outputs projection light to a predetermined display area to project and display a first image including plural figures such that the plural figures are respectively displayed in plural positions of a projection area that is projected by the projection light, specifying a figure of which brightness value is a maximum among the displayed plural figures so as to specify a brightness center point at which the brightness value is a maximum in the projection area, and causing the projection apparatus to project and display a second image indicating the specified brightness center point. |
| US09330630B2 |
Methods and systems for display source light management with rate change control
Elements of the present invention relate to systems and methods for modifying or adjusting a display source light illumination level based on power consumption goals. In some embodiments, a rate control parameter may be used to limit the rate at which the illumination level is varied. In some embodiments, image content analysis may be used to determine the value of the rate control parameter. |
| US09330629B2 |
Dynamically adjusting color characteristics of electronic content
Exemplary embodiments involve a viewer application dynamically adjusting the color balance of electronic content displayed on a display device. A viewer application can determine color information for a display device and generate a color correction filter based on color information for the display device and color information used by electronic content to specify the test color. The viewer application can receive display data representing at least a portion of the electronic content and apply the color correction filter to the display data to provide a color-corrected version of the display data for display by the display device. The viewer application can obtain the color information from a device driver application for the display device or from a separate data file. |
| US09330628B2 |
Drive circuit, display panel, display device and drive method
A drive circuit of a display panel, a display panel, a display device and a method of driving a display device are provided. The circuit comprises: j select circuits and j data line signal output circuits, j is an integer greater than or equal to 2. Each data line is connected with a select circuit, different data lines are connected with different select circuits, each select circuit is connected with the j data line signal output circuits, each select circuit can control the data line connected therewith to be connected with one of these j data line signal output circuits and to control the data line connected therewith to be disconnected from the other ones of these j data line signal output circuits; so pixels at different locations can be scanned by powering the data lines connected with the pixels using the different data line signal output circuits. |
| US09330627B2 |
Self-adaptive multi-region common voltage regulation system and method
The present disclosure discloses a system of self-adaptively adjusting Multi-area common voltage, comprising a plurality of photosensitive devices, for sensing luminous quantity from the different areas so as to obtain and transmit flicker values corresponding to the different areas; a multiplexing element, connected with the plurality of photosensitive devices; a calculation and comparison unit, for continuously receiving the flicker values which are sensed by the plurality of photosensitive devices in a time sequence, calculating actual display condition, and comparing the actual display condition with an optimal display condition; and an common voltage adjusting and outputting unit, connected with the calculation and comparison unit, for adjusting the value of the current output common voltage if the optimal display condition is not met and remaining the value of the current output common voltage unchanged if the optimal display condition is met. The present disclosure can achieve automatically adjustment of the common voltage and thus increase the productivity. |
| US09330624B1 |
VCOM amplifier with fast-switching gain
Electronic devices with a VCOM display panel are configured to provide a common voltage VCOM to a VCOM display panel backplane, referred to as a VCOM reference plane. The common voltage is supplied by a VCOM application circuit coupled to the VCOM reference plane. The VCOM application circuit includes a VCOM amplifier having a closed-loop gain. The VCOM application circuit is configurable to quickly adjust the closed-loop gain so as to adjust the settling characteristics of the common voltage VCOM output by the VCOM application circuit. The VCOM application circuit having adjustable closed-loop gain also reduces the amount of power to be dissipated, and therefore the amount of heat generation, in the VCOM amplifier. |
| US09330623B2 |
Display device and method for driving the same
A display device including a display panel which includes pixels connected to gate lines and data lines; and an image display control unit controlling an input image signal to be converted into a data signal and, thereby, display an image on the display panel. The image display control unit outputs the data signal so that a position of an image being displayed on the display panel is changed when the image signal is the same for a preselected time period and sets a next position change time period of the image according to a distance between an original position of the image and a changed position of the image. |
| US09330621B2 |
Display device with improved luminance
A display device is provided. The display device includes a display unit having pixels arranged in a two-dimensional matrix, each pixel including additive mixture subpixels and a luminance adjustment subpixel, and a signal control unit controlling a luminance at a maximum gray scale in the luminance adjustment subpixel depending on an external light illuminance. |
| US09330620B2 |
Driving method of field sequential display
A driving method of a field sequential display apparatus is provided. First, a plurality of scan lines of the field sequential display apparatus are sequentially driven according to a scanning sequence in a first period of a first field, wherein the first field is in a first frame. Next, the scan lines are sequentially driven according to an opposite sequence in a second period of the first field, wherein the opposite sequence is in the reverse order of the scanning sequence. Finally, the scan lines are simultaneously driven or not driven in a third period of the first field. Consequently, the disclosed driving method can promote the uniformity of the image brightness. |
| US09330608B2 |
Power management method and display device thereof
A power management method a display device utilizes the same are disclosed. The power management method, adopted by the display device, includes: increasing, by a control circuit, brightness of a lighting device, wherein the lighting device is configured to illuminate a display panel device; detecting, by an overload detection circuit, whether an overload has been triggered by the increased brightness; and when the overload has been triggered by the increased brightness, recording, by a power capacity determination circuit, a maximal predetermined brightness that is used prior to the overload is triggered, while showing an on-screen-display (OSD) warning message on a display of the display device for reminding the user. When the brightness of the lighting device reaches the maximal predetermined brightness and the power capacity determination circuit detects no overload, this indicates the power capacity is sufficient for supplying power to the display device. |
| US09330604B2 |
Organic light-emitting diode pixel circuit, drive method thereof, and display device
The present invention belongs to the field of display technology, and provides an OLED pixel circuit, a drive method thereof and a display device, which may solve the problem of relatively complicated control circuit and manufacturing process of an existing in-cell touch screen. In the OLED pixel circuit of the present invention, the data writing unit is for writing power supply voltage signal and data line voltage signal into the storage unit; the storage unit is for supplying voltage to the drive unit; the touch detecting unit is for sensing touch and generating a detecting signal; the drive unit is for converting the detecting signal into a touch output signal and for providing drive current for the OLED; and the light-emitting control unit is for turning on the drive unit and the OLED. The present invention may allow the touch display device to be thinner and lighter. |
| US09330603B2 |
Organic light emitting diode display device and method of driving the same
Discussed is an OLED display device that can compensate for the deviation of a threshold voltage and also prevent deterioration of an OLED, and a method of driving the same, wherein the OLED display device includes first to fifth transistors, a driving transistor including gate, source and drain electrodes, a capacitor for sensing a threshold voltage of the driving transistor, and an OLED. |
| US09330602B2 |
Display device that switches light emission states multiple times during one field period
A scan driving circuit includes a shift register unit and a logic circuit unit. The start of a start pulse of an output signal STp+1 of a p+1′th shift register is situated between the start and end of a start pulse of the output signal STp of a p′th shift register, and one each of a first enable signal through a Q′th enable signal exist in sequence between the start of the start pulse of the output signal STp and the start of the start pulse of the output signal STp+1. The operations of a (p′, q)′th NAND circuit are restricted based on period identifying signals, such that the NAND circuit generates scanning signals based only on a portion of the output signal STp corresponding to the first start pulse, the signal obtained by inverting the output signal STp+1, and the q′th enable signal ENq. |
| US09330597B2 |
Pixel and organic light emitting display using the same
A pixel having a simplified structure can compensate for the threshold voltage of a driving transistor thereof. The pixel includes an organic light emitting diode (OLED) having a cathode electrode coupled to a second power source, a storage capacitor coupled between a data line and a first node, a second transistor having a first electrode coupled to a first power source, a second electrode coupled to an anode electrode of the OLED, and a gate electrode coupled to the first node, a first transistor coupled between the first node and the second electrode of the second transistor, a gate electrode of the first transistor being coupled to a current scan line, and a third transistor coupled between the second electrode of the second transistor and the anode electrode of the OLED, a gate electrode of the third transistor being coupled to a control line. |
| US09330596B2 |
Pixel capable of displaying an image with uniform brightness and organic light emitting display using the same
A pixel capable of displaying an image with uniform brightness. The pixel includes an organic light emitting diode (OLED), a first transistor for controlling an amount of current supplied from a first power source coupled to a first electrode to the OLED, a second transistor coupled between a gate electrode of the first transistor and an initial power source to be turned on when a second scan signal is supplied to a second scan line, a first capacitor coupled between the gate electrode of the first transistor and the first power source, and a second capacitor whose first terminal is coupled to a first electrode of the first transistor. |
| US09330594B2 |
Power consumption controller, image processor, self-luminous display apparatus, elelcrtonic equipment, power consumption control method and computer program
The prior art power consumption control techniques convert the video signal (gray level) in one way or another based on the estimated power consumption level. The present invention proposes a power consumption controller which includes (a) a power consumption calculation section which sequentially calculates the power consumption level of a self-luminous display device based on a video signal input from the beginning of each frame up to the time of calculation, (b) a power consumption status determination section which determines whether the calculated power consumption level exceeds a reference value for comparison by constantly comparing the two levels. If this is the case, the same section detects the timing at which the power consumption exceeds the reference value for comparison and (c) a peak brightness control section which controls the peak brightness of the self-luminous display device if the power consumption level exceeds the reference value for comparison based on the detected timing. |
| US09330593B2 |
Stage circuit and organic light emitting display using the same
A stage circuit includes an outputting unit having a first node and a second node, the output unit configured to supply a voltage of a first power supply or a voltage of a third input terminal to an output terminal in accordance with voltages applied to the first node and the second node, a first driver configured to control the voltage of the second node in accordance with signals of a first input terminal, a second input terminal, and the third input terminal, and a second driver configured to control the voltage of the first node in accordance with the signal of the second input terminal and the voltage of the second node. |
| US09330582B1 |
Motive sign apparatus
A motive sign apparatus for broadcasting a sign up and down and back and forth to gain attention. The motive sign apparatus includes a mobile cart having a housing with side walls; an actuator assembly disposed inside the housing and including an actuator; and a sign support assembly in communication with the actuator. |
| US09330579B2 |
Patient wristband
A form having a printable nylon taffeta face ply and a liner ply where the face ply is die cut to form one or more blank detachable wristbands having first and second ends. The face ply is adhered to the liner ply by a pressure sensitive adhesive included on at least a portion of its bottom surface and the pressure sensitive adhesive is included on the face ply around the periphery of the one or more wristbands and on a bottom surface of the first and second ends of each of the wristbands. Each of the first and second ends of the wristbands is provided with tamper evident indicia. |
| US09330574B1 |
In-flight generation of RTA-compliant optimal profile descent paths
A on-aircraft computer device predicts aircraft states (e.g., altitude, speed, flight path angle, and fuel consumption) at any given time, while utilizing a Deterministic Genetic Algorithm to search 4-D flight path candidates that can comply with all path constraints to produce a feasible 4-D path candidate as a final OPD flight path to arrive at a metering waypoint in a specified time window. |
| US09330572B2 |
Vehicle warning device
A warning control device is provided with a detection device for detecting a mobile body moving in a direction intersecting with the path of the host vehicle. The warning control device performs a warning operation when the host vehicle and the mobile body approach each other. The warning control device calculates the intersecting distance, which is the distance to the host vehicle from a predicted intersecting position between the path of the host vehicle and the path of the mobile body. The shorter the calculated intersecting distance, the earlier becomes the timing of the warning operation executed by the warning control device. |
| US09330566B2 |
Signal light priority system utilizing estimated time of arrival
Systems and methods for requesting modification of traffic flow control systems that combine satellite position navigation systems and dead reckoning technology with secure radio communications to accurately report a vehicle's real-time location and estimated arrival times at a series of signal lights within a traffic grid or at a distant signal light, while enabling signal controllers to accommodate priority requests from these vehicles, allowing for these vehicles to maintain a fixed schedule with minimal interruption to other grid traffic. |
| US09330565B2 |
Traffic bottleneck detection and classification on a transportation network graph
Traffic congestion detection, classification and identification includes analysis of link-speed data representative of vehicular speed and capacity on one or more roadway segments to determine non-linear, multi-segment traffic bottlenecks in a transportation network graph. Link-speed data is processed to detect bottleneck conditions, classify bottlenecks and bottleneck-like traffic features according to their complexity, and identify sustained or recurring bottlenecks. Such a system and method of traffic congestion detection, classification and identification provides a framework for using this link-speed data to detect the head and queue of bottlenecks on a directed graph representing the transportation network, classify the resulting bottlenecks and bottleneck-like traffic features according to the shape of their queue, and identify and measure sustained or recurrent bottlenecks even when the location, or head, of the bottleneck varies slightly across multiple time periods or across multiple days. |
| US09330563B2 |
Synchronized metrology in power generation and distribution networks
Phasor Measurement Units (PMUs) tend to be specialized and expensive—relegated to only key points in power distribution networks, and are generally reliant on GPS technology. The present disclosure details how any smart meter—using wireless communication—can perform sub-microsecond-grade synchrophasor measurements. Other aspects concern smart meter-based determination of A, B or C phase of the tri-phase power network. This can involve count-stamp enabling message packets sent to and/or from a smart meter, and then associating such count-stamps to local measurements of power phase by a metrology unit. Once a network of such enabled smart meters and other devices is formed, sub-microsecond metropolitan-wide and entire region-wide synchronizing time standard can calibrate local measurements of power phase, where simple A, B and C phase determination is one low hanging fruit application of such. Low cost aggregate monitoring of metropolitan-wide synchrophasors promises a next chapter of importance for that relatively recent art. |
| US09330557B2 |
Cargo and door sensor
Implementations for a system to receive a message indicating that an ambient light level measured by an ambient light sensor within a container exceeds a first threshold value or falls below a second threshold value; in response to the message indicating that the ambient light level exceeds the first threshold value, activate a cargo sensor; and in response to the message indicating that the ambient light level falls below the second threshold value, de-activate the cargo sensor. |
| US09330555B2 |
Tracking exposure to electromagnetic fields
A method of tracking electromagnetic field, EMF, exposure of a user, comprising storing an aggregate EMF exposure value for the user, the aggregate EMF exposure value indicating EMF exposure due to use of one or more devices by the user; obtaining an estimate of EMF exposure associated with use of a particular one of the devices by the user; revising the aggregate EMF exposure value for the user in dependence upon the estimated EMF exposure; comparing the aggregate EMF exposure value to a threshold; and transmitting a signal related to use of the one or more devices if the aggregate EMF exposure value exceeds the threshold. |
| US09330546B2 |
System and method for automatically producing haptic events from a digital audio file
In an embodiment, a system and method for automatically converting a plurality of events in a plurality of channels in a structured representation sequence into haptic events. The method comprises calculating an event score for each event of the sequence in one or more channels. The method also comprises calculating a cumulative score based on the event scores in the one or more channels. The method includes selectively designating haptic events to the events based on the event scores in one or more selected channels, wherein the haptic events are output by a haptic actuator. This may be done by the system by calculating properties of the sound or by taking already existing values associated with those properties to efficiently produce haptic events. |
| US09330540B2 |
Customization apparatus and method
Systems for and methods of customizing at least one gaming apparatus is provided. The at least one gaming apparatus is operated as a slot machine game. The system includes a storage unit for storing a plurality of themes. Each of the plurality of themes includes a first set of full-motion videos associated with a first body portion of a plurality of actors, a second set of full-motion videos associated with a second body portion of the plurality of actors, and a third set of full-motion videos associated with a third body portion of the plurality of actors. The system includes a circuit configured to receive a selection of a theme from the plurality of themes. The circuit is further configured to cause the at least one gaming apparatus to display the first set, the second set, and the third set of videos for the selected theme. |
| US09330538B2 |
Methods and systems for conducting games of chance
A computer-implemented method that includes programming a computer machine to perform the steps of: providing game slips to game players, where each games slip has game options and one of the game options is a first game option that includes a non-verified outcome of an event; receiving the game slips that include selected game options where one selected game option includes the first game option; determining odds of the first game option based on: 1-P, where P is the probability of a verified outcome of the event, a financial criterion of the game provider, and the selected game options; providing and receiving acceptance of the odds; determining whether the event has resulted in the verified outcome or the non-verified outcome; and determining, for each game player that selected the first game option, a prize based on the accepted odds when the event results in a non-verified outcome. |
| US09330536B2 |
Presenting and controlling wagering game play
Some examples described include a system to perform operations that include accessing a user account responsive to communication with a plug-in of a web browser. In some examples, the operations further include providing gaming information associated with the user account. The plug-in is configured to present the gaming information in a graphical-user-interface object of the web browser. The graphical-user-interface object is separate from a main display area of the web browser. In some examples, the operations further include, based on user interaction with the graphical-user-interface object, providing content that is related to the gaming information for presentation via the main display area of the web browser. |
| US09330534B2 |
Game apparatus for discharging free gifts
Provided is a game apparatus for discharging free gifts. The game apparatus for discharging the free gifts, including: a betting button unit that sets betting sums of money; a gift showcase that includes two or more betting zones according to the betting sums of money, the betting zones in which the free gifts are displayed; lamps that enable the two or more betting zones to be distinguished from each other; an extruder that is driven to be moved forward or backward, in a direction (Z) in which the free gifts are displayed, within a plane located at an outer side of the gift showcase; and a control unit that controls the extruder to be moved to a betting zone corresponding to a betting sum of money set through the betting button unit. |
| US09330529B2 |
Game terminal configured for interaction with jukebox device systems including same, and/or associated methods
Portable coin-operated video game systems and methods are provided. Portable interactive entertainment devices are removably secured to stands. The portable interactive entertainment devices may be unsecured in response to a user providing currency or a credit card or in response to a remote control signal. The portable interactive entertainment devices may include touch screens and allow users to play video games and access data and devices connected to a local area network and a wide area network. |
| US09330525B2 |
Transmissive display having multiple switchable regions of a diffuser film layer assembly
A switchable transmissive display for a gaming system has an underlying display mode and a full video mode. The switchable transmissive display includes a first underlying display and a second display overlaying the first display. The second display includes a transmissive liquid crystal panel, a backlight assembly and a switchable diffuser film layer. The backlight assembly includes a transmissive aperture behind which the first underlying display is positioned. The second display also includes a supplemental backlight directed at the aperture. The second display has a first mode where the switchable diffuser film layer is transparent to allow viewing the first display and a second mode where the switchable diffuser film layer is translucent to obscure the transmissive aperture and an image is displayed. The switchable diffuser film layer distributes light to provide substantially homogeneous light intensity across the back of the transmissive liquid crystal panel. |
| US09330524B2 |
Varying thickness armrest with integrated multi-level button panel
A gaming system includes a display mounted to a cabinet and configured to display an outcome of a wagering game, the outcome being randomly selected from a plurality of outcomes in response to receiving a wager. The gaming system further includes an armrest panel mounted to the cabinet and including a support padding having a wall thickness defined by an exterior surface and an interior surface. The wall thickness varies along a cross-section of the support padding. The armrest panel further includes a plurality of buttons integrated in the support padding for receiving inputs from a player, the plurality of buttons including a first button mounted on a first elevation of the support padding and a second button mounted on a second elevation of the support padding. The first elevation is higher than the second elevation relative to the interior surface. |
| US09330516B2 |
Apparatus for receiving and sorting disks
An apparatus for receiving and sorting disks includes a wheel having at least one well for receiving a disk, a motor coupled to the wheel, a collecting device positioned relative to the wheel, a disk sensor, an ejector, and a controller. The collecting device has at least a first collector and a second collector configured for receiving disks. The disk sensor is configured to detect a value of a parameter of a disk received in the well and generate a parameter value signal. The ejector is coupled to the wheel proximate the well and configured to eject a disk from the well in a plane parallel to a bottom surface of the wheel in response to an eject signal. The controller is operably coupled with the disk sensor and the ejector. |
| US09330514B2 |
Systems and methods for locking device management
A system for locking device management is disclosed. A server can transmit locking device programming instructions for a locking device to a mobile device based on a locking device programming trigger. The mobile device can search for the locking device and transmit the programming instructions to the locking device via wireless signals. The locking device can communicate with the mobile device via wireless signals and execute the programming instructions. |
| US09330509B2 |
Method for obtaining product feedback from drivers in a non-distracting manner
A feedback system for a motor vehicle infotainment system is disclosed in which information about the state of the motor vehicle, including the infotainment system, and the mobile device may be collected and sent to a remote server that is responsible for receiving and/or organizing such feedback. A user may initiate a feedback process by pressing a dedicated button, issuing a voice command, performing a specific gesture, or other input action. The feedback system may collect a variety of data and create a notice on the mobile device so that a user may submit feedback at a time during which the user will not be operating the motor vehicle. |
| US09330507B2 |
System and method for selecting individual parameters to transition from text-to-graph or graph-to-text
A system and method for selecting individual parameters to transform from text-to-graph and graph-to-text is disclosed. The system includes a display device having a display screen for showing multiple views, including a non-graph view and a graph view. The non-graph view includes a plurality of demarcated portions, each having a graph selection element, a parameter identifier that corresponds to the graph selection element, and a current parameter value that corresponds to the graph selection element. The graph selection element may be selected to show a graph view. The graph view includes a first parameter identifier and a first current parameter value each corresponding to the selected graph selection element, a text selection element, and a graph of multiple parameter values associated with the first parameter identifier. Upon selection of the text selection element, the screen returns to the non-graph view. |
| US09330504B2 |
3D building model construction tools
A method for correcting 3D building objects is provided. Construction tools available within the visualization tool provide edge squaring and edge snapping of the 3D building objects, correcting incoherent angles and planes resulting from errors formed during the construction of the building model. Specified angular thresholds for perpendicular axis and parallel planes are provided in the construction tools to identify inaccuracies within selected buildings and new buildings are redrawn. |
| US09330502B2 |
Mixed reality simulation methods and systems
Mixed reality simulation in general, and more specifically to mixed reality simulation devices and systems for training purposes, for example in the medical field, may be provided. For example, a mixed reality simulation method for rendering on a display a mixed reality scenario of a virtual environment adapted to a physical environment, may comprise acquiring, with a sensor, a position of a physical environment object; identifying a mismatch between a physical environment surface and a virtual environment surface, the mismatch depending on the physical environment object position and a mixed reality scenario parameter; and computing a mapping displacement for a virtual environment surface based on the identified mismatch. |
| US09330498B2 |
Path connecting a first point to a second point in a three-dimensional scene
It is proposed a computer-implemented method, system and program product designing a path connecting a first point to a second point in a three-dimensional scene. The method comprises: providing the first point coupled with a first vector; providing the second point coupled with a second vector; and providing a set of paths by following at the most three portions of a parallelepiped, the parallelepiped comprising the provided first point on a first vertex and the provided second point on a second vertex, a portion of the parallelepiped being an edge, a diagonal of a face, a space diagonal. |
| US09330497B2 |
User interface devices for electrophysiology lab diagnostic and therapeutic equipment
In an electrophysiology (EP) lab, a bedside interface device allows an EP physician to directly control various diagnostic and therapeutic systems, including an electro-anatomic mapping system. The bedside interface device can include a computer with wireless communication capability as well as a touch-responsive display panel and voice recognition. The bedside interface device can also be a hand-graspable wireless remote control device that is configured to detect motions or gestures made with the remote control by the physician, allowing the physician to directly interact with the mapping system. The bedside interface device can also be a motion capture camera configured to determine motion patterns of the physician's arms, legs, trunk, face and the like, which are defined in advance to correspond to commands for the mapping system. The bedside interface device may also include voice recognition capabilities to allow a physician to directly issue verbal commands to the mapping system. |
| US09330496B2 |
Three dimensional coordinate location device, method for same, and program
There is provided a 3-dimensional coordinate specifying device which can accurately specify a set or sets of optional coordinates in a 3-dimensional space by a simple manipulation. The 3-dimensional coordinate specifying device includes a standard plane setting section 22 for setting an optional standard flat plane 31 in a 3-dimensional space, a standard point determining section 23 for determining values of coordinates of an optional point on the set standard flat plane 31, a light beam emitting section 25 for emitting an imaginary light beam 33 at an optional angle from the determined standard point 32, a point specifying section 26 for specifying an optional point on the emitted imaginary light beam, and a coordinate calculating section 27 for calculating 3-dimensional coordinates of the specified point. |
| US09330495B2 |
Extending DX11 GPU for programmable vector graphics
The present disclosure provides for path rendering including receiving, with a graphics processing unit (GPU), data indicative of a path segment of a path to be rendered. The systems and methods render the path segment by performing a fill of the path segment, which includes tessellating the path segment into a first plurality of primitives including a triangle per primitive, storing a first plurality of primitives in a stencil buffer, and drawing a bounding box of the path segment and rendering the bounding box with a stencil test enabled. The systems and methods also stroke the path segment, including tessellating the path into a second plurality of primitives, re-tessellating the second plurality of primitives, cutting the second plurality of primitives according to a dash pattern, creating a cap at a location of a cut, and creating a triangulation of a stroke and rasterizing the stroke based on the triangulation. |
| US09330490B2 |
Methods and systems for visualization of 3D parametric data during 2D imaging
Methods and systems for visualization of 3D parametric data in a 2D image. The set of 3D parametric data includes a plurality of voxels in 3D space each associated with at least one parametric value, and the set of 2D image data includes information about a known camera position and a known camera orientation at which the 2D image was obtained. A graphical representation is generated of the parametric values of the voxels corresponding to a viewing surface in 3D space. A virtual 2D view of the viewing surface is determined. The 2D image is displayed registered with the graphical representation of the parametric values of the voxels corresponding to the virtual 2D view. |
| US09330487B2 |
Apparatus and method for processing 3D images through adjustment of depth and viewing angle
An apparatus for processing a three-dimensional (3D) image is provided. The apparatus includes a motion estimation module and a motion interpolation module. The motion estimation module estimates a motion vector between a first object in a first-eye image and a second object in a second-eye image. The first object is the same as or similar to the second object. The motion interpolation module multiplies the motion vector by a first shift ratio to generate a first motion vector. The motion interpolation module generates a shifted first object by interpolation according to the first motion vector and the first object. |
| US09330480B2 |
Image processing apparatus having a plurality of image processing blocks that are capable of real-time processing of an image signal
An image processing apparatus is provided which offers higher versatility than conventional image processing apparatuses. When an input signal to a spatial filtering block is a monochrome signal that contains Y component only, a selector selects its input terminal and a selector selects its input terminal. Then, a low-pass filter output signal of a programmable spatial filter is inputted to a spatial filter, and a low-pass filter output signal of the spatial filer is inputted to a spatial filter. That is, the programmable spatial filter and the spatial filters are connected in series (in cascade), and the cascade-connected three spatial filters perform filtering operation. In this example, low-pass filters with 5H5 taps are connected in cascade in three stages, which enables low-pass filtering with 13H13 taps. |
| US09330479B2 |
Display system, display apparatus, and method for controlling display system for displaying one image by combining two images
A display system for displaying one image on a display surface by combining a first image displayed by a first display apparatus and a second image displayed by a second display apparatus, wherein: the first display apparatus displays a first index image at a position which is close to the image displayed by the second display apparatus and which is included in a display range of the first display apparatus, the first index image having a predetermined color and the image having luminances which are changed in a direction parallel to a side adjacent to the image displayed by the second display apparatus; and the first display apparatus corrects the image displayed by the first display apparatus on the basis of a designated position of the first index image. |
| US09330478B2 |
Augmented reality creation using a real scene
The creation of augmented reality is described using a real scene. In one example, a process includes observing a real scene through a camera of a device, observing a user gesture through the camera of the device, presenting the scene and the gesture on the display of the device, generating a virtual object and placing it in the scene based on the observed user gesture, and presenting the virtual object in the real scene on the display. |
| US09330477B2 |
Surgical stereo vision systems and methods for microsurgery
Surgical stereo vision systems and methods for microsurgery are described that enable hand-eye collocation, high resolution, and a large field of view. A digital stereo microscope apparatus, an operating system with a digital stereo microscope, and a method are described using a display unit located over an area of interest such that a human operator places hands, tools, or a combination thereof in the area of interest and views a magnified and augmented live stereo view of the area interest with eyes of the human operator substantially collocated with the hands of the human operator. |
| US09330475B2 |
Color buffer and depth buffer compression
In an example, a method of coding graphics data comprising a plurality of pixels includes performing, by a graphics processing unit (GPU), multi-sample anti-aliasing to generate one or more sample values for each pixel of the plurality of pixels. The method may also include determining whether pixels comprise edge pixels, where the determination comprises identifying, for each pixel, differing sample values. The method may also include encoding the pixels based on the edge pixel determination. |
| US09330474B1 |
Distinguishing between stock keeping units using a physical dimension of a region depicted in an image
The disclosure includes a system and method for distinguishing between stock keeping units of similar appearance that vary in size. An image recognition application receives an image including a shelving unit stocking a plurality of items, identifies each item in the image, generates a region of interest for each identified item in the image, identifies a physical dimension of a portion of region depicted in the image, determines a dimension of the region of interest for each identified item and the portion of region in pixels, determines a pixel-to-physical dimension ratio using the dimension in pixels of the portion of region and the physical dimension of the portion of region depicted in the image, and determines a stock keeping unit identifier of each identified item in the image based on the pixel-to-physical dimension ratio and the dimension of the region of interest for each identified item. |
| US09330472B2 |
System and method for distorted camera image correction
The invention provides an image processing method for processing a sequence of images, comprising the steps of: obtaining, from a visual sensor, at least two images of the sequence of images, detecting whether the images include a distortion, determining an image warping function at least partially compensating the distortion, applying the determined warping function to the image(s) including the distortion, and calculating by a processing unit, and outputting, an optical flow as a displacement vector field form the images. |
| US09330466B2 |
Methods and apparatus for 3D camera positioning using a 2D vanishing point grid
Methods and apparatus for three-dimensional (3D) camera positioning using a two-dimensional (2D) vanishing point grid. A vanishing point grid in a scene and initial camera parameters may be obtained. A new 3D camera may be calculated according to the vanishing point grid that places the grid as a ground plane in a scene. A 3D object may then be placed on the ground plane in the scene as defined by the 3D camera. The 3D object may be placed at the center of the vanishing point grid. Once placed, the 3D object can be moved to other locations on the ground plane or otherwise manipulated. The 3D object may be added as a layer in the image. |
| US09330462B2 |
Object information acquiring apparatus and control method of object information acquiring apparatus
An object information acquiring apparatus that acquires information inside an object by receiving an acoustic wave that has arrived from inside the object through a layer having an acoustic impedance that is different from that of the object, and analyzing the acoustic wave, the object information acquiring apparatus comprises an acoustic wave probe that receives an acoustic wave and converts the acoustic wave into an electric signal; a whole image generation unit that generates a whole image, which is an image indicating information inside the object, based on the electric signal after the conversion; a partial image generation unit that extracts a partial image, which is a part of the whole image, from the whole image; and a similar image search unit that searches an area similar to the partial image, from the whole image. |
| US09330460B2 |
Treatment recommending system of plant symptoms, method and non-transitory computer-readable medium
A treatment recommending system of plant symptom includes an operation interface, an image capture unit, a processing unit and a storage unit for storing plant symptom data and diagnostic data. The processing unit may find target contour data presenting a plant part according to symptom description and symptom characteristic data. The image capture unit obtains plant image data corresponding to the target contour data. The processing unit analyzes the plant image data, and coordinates with the symptom characteristic data to determine corresponding treatment recommendation data. |
| US09330456B2 |
Systems and methods for regularized Fourier analysis in x-ray phase contrast imaging
A method of regularization of x-ray phase contrast imaging (XPCi) system measurement data includes obtaining air scan data of the XPCi system prior to the presence of an object undergoing imaging, performing Fourier analysis of the air scan data, computing air coefficients from the result of the performing step, obtaining object scan data of an object undergoing imaging on the XPCi system, regularizing the object scan data, and calculating at least one of absorption image data, differential phase image data, and dark field image data by using object coefficients. A system configured to implement the method and a non-transitory computer-readable medium are disclosed. |
| US09330455B2 |
Diagnostic support apparatus and diagnostic support method
The diagnostic support apparatus includes a feature quantity calculation unit vectorizing a test image into shift-invariant feature quantities, a base representation unit transforming the shift-invariant feature quantities of the test image into a linear combination of base vectors with first coefficients, the base vectors being calculated from a plurality of vectors representing shift-invariant feature quantities of a plurality of normal structural images including no lesion site, a lesion determination unit determining that the test image includes a lesion site when a difference between the first coefficients and second coefficients is greater than a determination threshold value, the second coefficients being used to transform shift-invariant feature quantities calculated from one of the normal structural images into a linear combination of the base vectors, and an output unit outputting a result of the determination by the lesion determination unit. |
| US09330451B2 |
Method and apparatus for detecting defect of backlight module
According to embodiments of the invention, there are disclosed a method and an apparatus for detecting defect of a backlight module. Images that show components in the backlight module are acquired with a plurality of preset angles relative to a surface of the backlight module. The acquired images that show the components in the backlight module are analyzed, so as to determine whether a defect presents in the components in the backlight module. |
| US09330446B2 |
Method and apparatus for processing image
Provided are a monitoring system and an operating method thereof, and more particularly, an image processing method and apparatus for removing a motion blur of a wide dynamic range (WDR) image by using a machine learning algorithm. The image processing method includes: generating an overlap image by overlapping a first image having a predetermined exposure time and a second image having an exposure time different from that of the first image; detecting a region of interest (ROI) in which a motion blur occurs in the overlap image; and performing a motion blur removing operation of changing an image in the ROI to any one of the first image and the second image by applying a first machine learning algorithm. |
| US09330445B2 |
Local contrast enhancement method and apparatus
A local enhancement method is provided, including: dividing an image into a plurality of blocks, which include a first block and a second block adjacent to the first block; generating histograms of the blocks respectively; generating enhancement functions of the blocks respectively based on the corresponding histograms, wherein the enhancement functions include at least a first contrast enhancement function of the first block and a second contrast enhancement function of the second block; and for each pixel in the blocks: generating a first enhanced pixel value for a current pixel of the first block based on the first contrast enhancement; generating a second enhanced pixel value for the current pixel of the first block based on the second contrast function of the second block; and generating a final enhanced pixel value for the current pixel based on the first and second enhanced pixel values. |
| US09330443B1 |
Noise reduction in image domain for spectral computed tomography
A computed tomography (CT) imaging system is provided including processing circuitry configured to obtain a plurality of basis images that are combined to generate a target image; de-noise the basis images using a noise-reduction method to generate de-noised basis images; calculate noise maps of the basis images by subtracting the de-noised basis images from the basis images; calculate a weight for each of the noise maps using the target image and the calculated noise maps; and generate a reduced-noise target image using the target image, the calculated noise maps, and the calculated weights. |
| US09330441B2 |
Automated selection of filter parameters for seismic analysis
A filter selection technique is described for automatically selecting filters and filter parameters to apply to a given input data. The technique first receives input data and accesses a library storing information from previously analyzed data. The technique selects an entry from the library where the entry contains data that is correlated with the input data. The technique then applies a filter to the input data. The filter and filter parameters are determined by the selected entry. |
| US09330440B2 |
Medical image processing apparatus and method for synthesizing and displaying medical image generated using multi-energy X-ray
A medical image processing apparatus may include an image data generator to generate image data corresponding to at least two different energy bands by using an X-ray, an ROI processor to highlight a tissue of interest classified based on a predetermined characteristic to be distinguished from a normal tissue, in the generated image data, and a display to alternately display first image data in which the tissue of interest is not highlighted, and second image data in which the tissue of interest is highlighted to be distinguished from the normal tissue. |
| US09330437B2 |
Method for automatically generating presentation slides containing picture elements
A computer-implemented method for intelligently generating presentations, the method comprising the steps of: analysing the variation in colours of pixels in the digital image; and, if the variation is below a predetermined threshold, applying one or more rules to increase visibility of the digital image in the presentation. |
| US09330433B2 |
Data distribution fabric in scalable GPUs
In on embodiment, a hybrid fabric interconnects multiple graphics processor cores within a processor. The hybrid fabric interconnect includes multiple data channels, including programmable virtual data channels. The virtual data channels carry multiple traffic classes of packet-based messages. The virtual data channels and multiple traffic classes may be assigned one of multiple priorities. The virtual data channels may be arbitrated independently. The hybrid fabric is scalable and can support multiple topologies, including multiple stacked integrated circuit topologies. |
| US09330428B2 |
Method and apparatus for modifying a video stream to encode metadata
A watermark encoder receives a current video image together with current metadata associated with the current image. A metadata delay also makes available to the watermark decoder delayed metadata associated respectively with four or more of the preceding. Then the watermark encoder modifies pixel values of the current image not only to encode the current metadata but also the delayed metadata. At a decoder, if metadata for the current image is corrupted or missing, it can be recovered from one of the succeeding images. |
| US09330423B2 |
Method and apparatus for providing a personal value for an individual
A method and apparatus for generating a personal value for a user are disclosed. For example, the method collects data associated with the user, wherein the data that is collected comprises social connection data, enhances the data that is collected, receives a request, and generates a response to the request by using a personal value for the user, where the personal value is generated from the data that is enhanced. |
| US09330419B2 |
Social network system with social objects
A social network system provides a social network that receives from an application a business object and an associated system of record and generates a social object that corresponds to the business object and that comprises the system of record. The social network assigns one or more members to the social object and associates a wall to the social object. The wall displays changes to the system of record, as well as other activity related to the social object. |
| US09330418B2 |
System and method for creating a family tree data structure
A tree building system that accesses data from a social networking site and, in some embodiments, other data sites having information that may pertain to the relationships between users of the social networking site. A rules engine within the system implements logic for analyzing the data from the social networking site. The system provides a candidate list of possible relatives for selection by a user and solicits information from the user through the use of guided questions. |
| US09330417B2 |
Recognition system
According to various embodiments, a user may pursue defined achievements through reading books. As the user accomplishes the achievements, the user may receive mementos that can serve as a tangible indicator of what the user has accomplished. The mementos may be visible to others on a website, such as a social networking website. |
| US09330410B2 |
Data-driven color coordinator
A color selection and coordination system including a database of predetermined color relationships implementing a data-driven color model. A starting color is associated with a first color in the color database. One or more predefined color palettes associated with the first color may be retrieved, each palette including one or more coordinating colors, the coordinating colors being predetermined based on the first color and a color coordination algorithm. |
| US09330405B2 |
Methods and apparatus for fast item identification
Methods and apparatus are provided for fast item identification. A plurality of sensors capture data for an unknown item that is moved past the sensors. The data is processed to produce a plurality of physical attributes related to the unknown item. The physical attributes are used to search a database of physical attributes for a large number of known items where the unknown item is one of the known items. A small set of known items are selected where the physical attributes of the known items match the physical attributes of the unknown item. Further processing of the selected set of known items identifies the unknown item as one of the set of known items. |
| US09330404B2 |
Applying screening information to search results
Applying screening information to search results is disclosed, including: receiving a search request for products, wherein the search request comprises one or more search conditions and a set of user information; retrieving screening information associated with the set of user information, wherein the screening information indicates one or both of seller information and product information to exclude from search results; determining a plurality of search results based at least in part on the one or more search conditions and determining a search result from the plurality of search results to be excluded based at least in part on the screening information; and returning one or more search results from the plurality of search results other than the search result determined to be excluded. |
| US09330397B2 |
Return coupon holder
A return coupon holder is described for holding a return coupon issued in a store in conjunction with a customer's merchandise return transaction. The return coupon holder is preferably sized large enough to discourage the customer from stowing the coupon away, such as in a handbag. Additionally, holders may be of different types that visually or electronically convey information about a category associated with the customer's return transaction. Thus, salespersons may accordingly provide appropriate customer service to the customer. The holder categories may indicate an approximate dollar value of the return transaction, a type of merchandise returned, a return payment method, an assessment of the profitability of the customer, an assessment of the risk of fraud associated with the return transaction, and the like. A computer decision system may select holder type. Some embodiments of the coupon holder are fitted with a device that allow tracing of the customer's movements while still in the store. |
| US09330395B2 |
System, method and computer readable medium for determining attention areas of a web page
During an interaction with a web page, user interface events are recorded and augmented with page layout data from the document object model. An event stream is formed with the page layout data and communicated to an event server. The event server processes the event stream to determine a location at which the events were generated and determines attention data for each event stream that indicates where a user's attention was directed during an interaction. The attention data for a plurality of event streams is aggregated to determine common or popular areas of interest of the web page. |
| US09330394B2 |
Content management with hierarchical content rules
Computing apparatus, computer-readable storage medium, and method associated with application of content rules to content. The computing apparatus may have a processor and a content management service to be operated on the processor. The content management service may receive content rules, each content rule specifying one or more criteria for application of the content rule to one or more instances of content. The content management service may identify one or more instances of content that match the criteria specified by the content rules. The content management service may apply one or more of the content rules to the identified one or more instances of content in a hierarchical manner based on a specificity of the criteria, wherein a rule specifying more specific criteria is applied with priority over a rule specifying less specific criteria. Other embodiments may be described and/or claimed. |
| US09330389B2 |
Facilitating establishing trust for conducting direct secure electronic transactions between users and service providers via a mobile wallet
Methods and systems are provided for supporting electronic transactions, including transactions that are provided with per-user, per-device and per-domain security across domains of multiple service providers. |
| US09330388B2 |
Facilitating establishing trust for conducting direct secure electronic transactions between a user and airtime service providers
Methods and systems are provided for supporting electronic transactions, including transactions that are provided with per-user, per-device and per-domain security across domains of multiple service providers. |
| US09330383B1 |
Message dispatcher for payment system
A payment reader includes a contactless interface for communicating with a contactless device. The payment reader has a processor that executes instructions stored in memory, and the instructions include instructions for a plurality of firmware modules including a message dispatcher module and a plurality of functional modules. The functional modules generate messages and the message dispatcher module stores the messages in a queued data structure such as a stack or a queue. The messages are provided to the functional modules from the queued data structure. Some of the messages are timed messages that are returned to the queued data structure. |
| US09330381B2 |
Portable multifunction device, method, and graphical user interface for viewing and managing electronic calendars
In accordance with some embodiments, a computer-implemented method is performed at a portable multifunction device with a touch screen display. The touch screen display includes a long axis, a short axis, a portrait view and a landscape view. The computer-implemented method includes executing a calendar application. In response to detecting the portable multifunction device in a first orientation that comprises a substantially vertical orientation of the long axis, a calendar is displayed for a first time period in the portrait view. In response to detecting the portable multifunction device in a second orientation that comprises the substantially vertical orientation of the short axis, a calendar is displayed for a second time period in the landscape view. The second time period is longer than and includes the first time period. |
| US09330380B2 |
Method and system for managing one or more recurrencies including exclusionary schedule
The present disclosure discloses methods and systems for managing one or more recurrencies. The method includes defining one or more recurrency tasks, each task having associated recurrency parameters. The method further includes identifying a recurrency period wherein the one or more recurrency tasks are disaggregated into individual scheduled events over the span of the recurrency period. Thereafter, a user-defined exclusionary schedule is applied to the disaggregated set of events. Subsequently, the edited recurrent tasks are output in a pre-defined file format. |
| US09330376B2 |
System and method for assigning a business value rating to documents in an enterprise
A system and method for managing information in an enterprise is disclosed. In one embodiment, the method comprises receiving a document from a component of an enterprise network, determining one or more characteristics associated with the document, assigning a priority score to a user associated with the document, assigning a business value rating to the document, and performing an operation with the document based on the business value rating. In another embodiment, the system includes a processor operable to receive a document, determine one or more characteristics associated with the document, determine a priority score to a user associated with the document, assign a business value rating to the document, and perform an operation with the document based on the business value rating. |
| US09330368B2 |
Routing service requests based on lowest actual cost within a federated virtual service cloud
A method for providing a virtual cloud service at the lowest actual cost can begin with an optimal transaction handler of a federated virtual service cloud maintaining a virtual resource pool of transactional units. Each transactional unit can represent a service application deployed to a cloud service provided by a cloud service provider having a usage-based service cost model that allows transactional units to be placed in an inactive state to suspend its operating expense. Operational metrics data for the cloud service providers can be continuously captured. In response to a service request, the transactional unit that meets fulfillment requirements of the service request and incurs a lowest actual cost can be determined based upon cost factors derived from the operational metrics data, the usage-based service cost model, and a current usage state of the virtual resource pool. The received service request can be routed to the determined transactional unit. |
| US09330367B2 |
Frozen precipitation treatment analysis system
A frozen precipitation treatment analysis system may include, in one embodiment, an electronic mobile device and a Global Positioning System (GPS). The mobile device may have software that uses the GPS and inputted information to produce a work flow plan for treating frozen precipitation at a site. In another embodiment, a frozen precipitation treatment analysis system may include an electronic mobile device and a virtual map of a site requiring frozen precipitation treatment analysis. The mobile device may have software that uses the virtual map and inputted information to determine the area of the site and/or other factors related to the frozen precipitation treatment analysis. |
| US09330366B2 |
System and method for collaboration via team and role designation and control and management of annotations
A system and methodology for collaborating. The system and method utilize a plurality of computing appliances, each assigned a respective team designation and a respective role designation. Team control logic is responsive to a respective said team designation, to control operation of each respective said computing appliance to operate as a part of a group. Within a defined Team, the plurality of computing appliances operate having a defined set of roles. Role control logic controls operations of a respective one of the computing appliances in accordance with functionality as defined responsive to the respective said role designation for that respective one of the plurality of computing appliances. Each of the plurality of computing appliances is assigned a respective team designation and a respective role designation. Memory storage is structured as a plurality of mapped data layers, for associative storage of user input mapped by user to a respective one of the data layers. Thereafter, responsive to the respective team control logic and the role control logic, each of at least two of the plurality of computing appliances utilizes a respective associated said data layer in the memory for associated storage of annotation data representative of annotations as originated at that respective one, for the at least two of the plurality of computing appliances. Display logic selects which of the plurality of data layers are selected data layers utilized to locally generate a display presentation that is provided at each of at least two of the plurality of computing appliances. |
| US09330364B2 |
System and methods for third-party access to a network-based system for providing location-based upcoming event information
A system and methods for third-party access to a network-based system for providing location-based upcoming event information are described. The location-based upcoming event information may be accessed from the network-based system by a server-side web application implemented by a third party. The server-side web application may be configured to communicate with the network-based system that provides online marketplace and ticket fulfillment services and to generate a query based upon the location of a user and other event criteria. The server-side web application may communicate the query to the network-based system and, in response, receive location-based upcoming event information which may be displayed to a user as a list and/or information on a map. The location-based upcoming event information may comprise an aggregate of ticket inventory available from multiple online marketplaces providing the user with multiple purchasing options. |
| US09330363B2 |
Method and article of manufacture for ensuring fair access to information using propagation delays to determine when to release object locks
Locks placed on corresponding objects held in a plurality of databases located at different nodes in a network during replication are released in accordance with fairness criteria. Propagation delays are determined between a transaction initiating node and one or more other nodes in the network. An object is locked during a transaction being executed at the transaction initiating node. Corresponding objects are locked at one or more other nodes in the network that are manipulated as a result of the replication Upon determining that the object locks should be released, the propagation delays are used to determine when to release the object locks so that all of the object locks at the one or more other nodes are released in accordance with the fairness criteria. |
| US09330361B1 |
Inferring the presence of an entity within an identifier space based on the behaviors of unrelated entities
Embodiments of the invention build models to predict the likelihood of entities that operate in a given identifier space also operating in a disjoined identifier space based on a source panel of entities that operate in one or both of the identifier spaces. In operation, a model building engine builds a model based on features associated with the source panel and features associated with standard populations in the given identifier space. The model is used to determine whether the target entity is more similar to those entities in the source panel that operate only in the given identifier space or those entities in the source panel that operate in both identifier spaces. |
| US09330360B1 |
Recommendation engine rationalization
In some embodiments, techniques for rationalizing a recommendation include determining a recommended item for a user using a first recommendation engine, wherein the first recommendation engine receives as an input first behavioral data associated with a user, and generates an identifier corresponding to a recommended item; creating a rationalization for the recommended item using a first rationalization engine, wherein the first rationalization engine receives as inputs the recommended item and second behavioral data associated with the user, and generates a rationalization, wherein the rationalization includes a constructed rationalization of why the recommended item is recommended for the user, and wherein the creation of the rationalization is not based solely on an actual reason the first recommendation engine determined the recommended item; associating the rationalization for the recommended item with the recommended item; and providing the recommended item and associated rationalization. |
| US09330359B2 |
Degree of closeness based on communication contents
In one example, a method may include monitoring contents of communications between a first user and a second user, determining a degree of closeness between the first user and the second user utilizing an ontological model, with the degree of closeness being based at least in part on the contents of communications between the first user and the second user, and updating the degree of closeness based at least in part on a frequency of communications between the first user and the second user. |
| US09330358B1 |
Case-based reasoning system using normalized weight vectors
A system and method include comparing a context to cases stored in a case base, where the cases include Boolean and non-Boolean independent weight variables and a domain-specific dependency variable. The case and context independent weight variables are normalized and a normalized weight vector is determined for the case base. A match between the received context and each case of the case base is determined using the normalized context and case variables and the normalized weight vector. A skew value is determined for each category of domain specific dependency variables and the category of domain specific dependency variables having the minimal skew value is selected. The dependency variable associated with the selected category is then displayed to a user. |
| US09330357B1 |
Method, apparatus, and computer program product for determining a provider return rate
Provided herein are systems, methods and computer readable media for classifying a provider of products, services or experiences as a provider that should be engaged based on a predicted return rate for any products, services or experiences that may be offered and purchased by a consumer. An example method may comprise supplying a classifying model with a dataset, wherein the dataset comprises an identification of a provider and a plurality of attributes corresponding to the provider and identifying a class of the provider in accordance with the plurality of corresponding attributes, wherein the identification is determined based on one or more patterns determinative of a return rate by the classifying model. |
| US09330356B2 |
Apparatus and methods for developing parallel networks using a general purpose programming language
Apparatus and methods for developing parallel networks. Parallel network design may comprise a general purpose language (GPC) code portion and a network description (ND) portion. GPL tools may be utilized in designing the network. The GPL tools may be configured to produce network specification language (NSL) engine adapted to generate hardware optimized machine executable code corresponding to the network description. The developer may be enabled to describe a parameter of the network. The GPC portion may be automatically updated consistent with the network parameter value. The GPC byte code may be introspected by the NSL engine to provide the underlying source code that may be automatically reinterpreted to produce the hardware optimized machine code. The optimized machine code may be executed in parallel. |
| US09330354B2 |
Radio IC device
A radio IC device that can be used in a plurality of frequency bands for RFID tags and that is compact and has superior radiation characteristics is provided. A spiral line electrode portion and a first side electrode, extending from an inner end thereof, of a capacitor electrode portion are provided on a top surface of a sheet-shaped substrate, and a second side electrode arranged to face the first side electrode and a crossing line electrode are provided on a bottom surface of the substrate. A first radio IC chip is arranged at a location in the line electrode portion, and a second RFID tag radio IC is arranged so as to be connected to a front-to-back connection portion and an end of an electric-field radiation electrode portion. The radio IC chip rectifies an RF signal in a first frequency band and outputs and supplies power to the second RFID tag radio IC. |
| US09330346B2 |
Printing device, printing method for printing device, and print medium
A printing device includes a labeling information forming unit which, on a print medium where a dot group is printed in advance, selectively turns a dot of the dot group into a non-display state and thereby forms labeling information including a dot pattern. |
| US09330345B2 |
Memory card and memory card adaptor
A memory card includes a card body, an interface terminal and an attachment mechanism for detachably mounting the card to an adaptor of an electronic device. The interface terminal is disposed at a central portion of a major surface of the card body. The attachment mechanism is located at an outer peripheral portion of the card body that surrounds the central portion. The adaptor has a recess whose shape complements that of the major surface of the card body, and socket exposed at a central portion of the bottom of the recess. Thus, the memory card may be inserted face down into the adaptor. |
| US09330343B2 |
Image analysis apparatus mounted to vehicle
An image analysis apparatus picks up an image of a region ahead of a vehicle using a camera, and allows a control unit to analyze picked-up image data generated by the camera to learn a focus-of-expansion position. The control unit controls the learning performance as follows. Specifically, the control unit does not start the learning performance for the focus-of-expansion position until a state where a detection value of a vehicle speed exceeds a reference speed exceeds a specified duration of time. When the state where a detection value of a vehicle speed exceeds a reference speed exceeds the specified duration of time, the learning performance for the focus-of-expansion position is started from this time point. The specified duration of time may be determined on the basis of statistics on the durations of simulated runs of the vehicle performed on a chassis dynamometer in a vehicle inspection. |
| US09330341B2 |
Image index generation based on similarities of image features
Embodiments of the present application relate to an image index generation method, system, a device, and a computer program product. An image index generation method is provided. The method includes selecting an image included in an image library for which an image index is to be generated, determining at least one target region included in the image, extracting visual features from the determined at least one target region, determining a similarity value of the selected image and image included in the image library based on the extracted visual features, determining image categories to which the images belong to based on the determined similarity values among the images, and assigning category identifiers to the images in accordance with an identifier assignment method, the identifier assignment method assigns the same category identifiers to images belonging to the same image category, and different category identifiers to images belonging to different image categories. |
| US09330340B1 |
Noise estimation for images using polynomial relationship for pixel values of image features
Implementations relate to estimating noise in images using a polynomial relationship for pixel values of image features. In some implementations, a computer-implemented method to estimate noise in an image includes determining a plurality of patches of pixels in the image. For each patch of pixels, the method determines feature pixels in the patch that are included in a particular image feature at least partially depicted in the patch. The method determines an error estimate for each patch of pixels, where each error estimate is based on an amount by which pixel values of the feature pixels in the patch of pixels are different from an estimated polynomial relationship between the feature pixels in the patch of pixels. One of the error estimates is selected as a noise level estimate for the image. |
| US09330336B2 |
Systems, methods, and media for on-line boosting of a classifier
Systems, methods, and media for on-line boosting of a classifier are provided, comprising: receiving a training sample; for each of a plurality of features, determining a feature value for the training sample and the feature, using the feature value to update a histogram, and determining a threshold for a classifier of the feature; for each of the plurality of features, classifying the training sample using the threshold for the classifier of the feature and calculating an error associated with the classifier; selecting a plurality of best classifiers from the classifiers; and, for each of the plurality of best classifiers, assigning a voting weight to the one of the plurality of best classifiers. |
| US09330335B2 |
Diagnostic support apparatus and diagnostic support method
A diagnostic support apparatus includes a base vector matching unit configured to match test image base vectors used for a base representation of a test image feature quantity of a test image and normal image base vectors used for a base representation of a normal image feature quantity of a normal image, a lesion determination unit configured to determine that the test image includes an image of a lesion site when a difference between a test image base coefficient and a normal image base coefficient is greater than a threshold, the test image base coefficient being a coefficient with which the test feature quantity is transformed to the base representation, and the normal image base coefficient being a coefficient with which the normal feature quantity is transformed to the base representation, and a determination result output unit configured to output a result of the determination by the lesion determination unit. |
| US09330333B2 |
Method and apparatus for image content-based automatic brightness detection
A method and apparatus for image automatic brightness detection. The method includes determining region of interest (ROI) candidates in an image, extracting features from each of the ROI candidates, selecting the optimum ROI based on weighted score of each of the ROI candidate, and calculating brightness value of the selected optimum ROI candidate as brightness feedback. The method and apparatus for image automatic brightness detection according to embodiments of the present invention, can automatically detect the point of interest for clinicians, and then provide a more accurate feedback to the imaging system, in order to provide a more efficient dose management in the imaging system and thus to achieve constant image quality without wasting any dose, thereby further optimizing the dose/IQ performance and the high efficient utilization of the system. |
| US09330332B2 |
Fast computation of kernel descriptors
An approach to computation of kernel descriptors is accelerated using precomputed tables. In one aspect, a fast algorithm for kernel descriptor computation that takes O(1) operations per pixel in each patch, based on pre-computed kernel values. This speeds up the kernel descriptor features under consideration, to levels that are comparable with D-SIFT and color SIFT, and two orders of magnitude faster than STIP and HoG3D. In some examples, kernel descriptors are applied to extract gradient, flow and texture based features for video analysis. In tests of the approach on a large database of internet videos used in the TRECVID MED 2011 evaluations, the flow based kernel descriptors are up to two orders of magnitude faster than STIP and HoG3D, and also produce significant performance improvements. Further, using features from multiple color planes produces small but consistent gains. |
| US09330331B2 |
Systems and methods for offline character recognition
A method, non-transitory computer readable medium and character recognition device for character recognition includes a character recognition device for receiving an image representing a character comprising one or more strokes. A set of first parameters associated with each of the one or more first strokes is determined. Each of the one or more first strokes is compared with the associated set of first parameters with a plurality of stored sets of second parameters, where each of the plurality of stored second strokes is associated with a stored set of second parameters. A second stroke is identified from among the plurality of stored second strokes corresponding to each of the one or more first strokes based on the comparison. The character is identified based on the identified one or more second strokes. |
| US09330323B2 |
Redigitization system and service
A system and method to error correct extant electronic documents is disclosed. An electronic document may be rasterized to obtain a pixel representation of the electronic document (e.g., raster image). One or more optical character recognition (OCR) tasks may be performed on the raster image of the electronic document. Errors discovered by the OCR tasks may be corrected and a customized error corrected version of the electronic document may be created and stored. If the author of the electronic document is known, the raster image may be compared to a personalized tf*idf error dictionary associated with the author to determine known OCR errors specific to the author. The raster image may also be compared to a personalized electronic error dictionary associated with the author to determine known typographical errors specific to the author. |
| US09330321B2 |
Method of processing an image of a visual scene
An image of a visual scene, comprising a plurality of pixels. is acquired and an associated range map is either determined therefrom or separately acquired. Elements of the range map comprise distances from the camera for each pixel of the image. In one aspect, either the image or the range map is processed with a connected-components sieve filter that locates clusters of pixels or elements that are connected to one another along either adjacent rows, columns or diagonally. In another aspect, a cross-range value of range-map element is compared with a down-range-responsive cross-range threshold of a boundary of a collision-possible space and the pixel or element is nulled or ignored if associated with a location that is not in the collision-possible space. The collision-possible space is responsive to an operating condition of a vehicle from which the image is acquired. |
| US09330319B2 |
Apparatus for compensating camera image and operating method thereof
Disclosed is a camera image compensating apparatus for a vehicle, including a detecting unit which detects a base line and a vehicle body contour line; a coordinate storing unit which stores a first reference image coordinate value and a second reference image coordinate value; a first coordinate calculating unit which calculates a first base line image coordinate value and calculates a first vehicle body contour line image coordinate value; a coordinate comparing unit which compares the first reference image coordinate value and the first base line image coordinate value and compares the second reference image coordinate value and the first vehicle body contour line image coordinate value; and a correcting unit which calculates angle change information of the camera, calculates correction information based on the angle change information, and corrects the camera parameter using the correction information. |
| US09330311B1 |
Optical character recognition
Systems and methods for analyzing letters in an image of text are described. For each letter, a number of properties are determined and the letters are classified into letterform classes. The properties may include independent letter properties based on only the letter itself, such as a slanted bounding box encompassing the letter. The properties may also include dependent letter properties that are based, in part, on other letters, such as adjacent letters or letters in the same word or line. |
| US09330307B2 |
Learning based estimation of hand and finger pose
A method for processing data includes receiving a depth map of a scene containing a human hand, the depth map consisting of a matrix of pixels having respective pixel depth values. The method continues by extracting from the depth map information based on the depth values in a plurality of positions distributed over the human hand and processing the information in order to estimate respective candidate positions of the finger joints. The pose of the human hand is estimated by choosing a combination of the positions of the finger joints, responsively to anatomical constraints of the hand, that gives a hand configuration that is most anatomically probable among the candidate positions. |
| US09330304B2 |
Information processing apparatus and method for controlling the same
An information processing apparatus detects a moving member that moves in a background area and that includes an object other than a recognition target. The apparatus sets a partial area as a background undetermined area if the moving member is present in the background area and sets a partial area as a background determined area if it is regarded that the recognition target is not present in the background area in each of the partial areas set as the background undetermined area. The apparatus recognizes an operation caused by the recognition target that moves in the background determined area. |
| US09330302B2 |
Polarized gaze tracking
Embodiments that relate to determining gaze locations are disclosed. In one embodiment a method includes shining light along an outbound light path to the eyes of the user wearing glasses. Upon detecting the glasses, the light is dynamically polarized in a polarization pattern that switches between a random polarization phase and a single polarization phase, wherein the random polarization phase includes a first polarization along an outbound light path and a second polarization orthogonal to the first polarization along a reflected light path. The single polarization phase has a single polarization. During the random polarization phases, glares reflected from the glasses are filtered out and pupil images are captured. Glint images are captured during the single polarization phase. Based on pupil characteristics and glint characteristics, gaze locations are repeatedly detected. |
| US09330297B2 |
Methods and systems for video-based chew counting via feature tracking
A system and method of video-based chew counting by receiving image frames from a video camera, determining feature points within the image frames from the video camera, generating a motion signal based on movement of the feature points across the image frames from the video camera, and determining a chew count based on the motion signal. |
| US09330293B2 |
Article with visual code, visual code reading apparatus and information conveying method
An article to which a visual code is attached, wherein the visual code includes: a frame pattern which is formed in the shape of a polygonal or round ring by arranging multiple pattern elements; a symbol pattern placing area which is formed inside the frame pattern, and in which a symbol pattern can be placed; an internal information pattern which is formed as a part of the frame pattern and indicates the presence or the absence of the symbol pattern in the symbol pattern placing area; and a guide pattern which is placed on, inside or near the frame pattern, and is used for a visual code reading apparatus having an optical reading function to recognize a positional relationship between the frame pattern and the visual code reading apparatus. |
| US09330290B2 |
Barcode reader having multiple illumination systems and multiple sets of imaging optics
A barcode reader comprises a first lens assembly with a first field of view and a first optical path for first illumination from the first field of view to project to a first image sensor section. The barcode reader further comprises a second lens assembly with a second field of view and a second optical path for second illumination from the second field of view to project to a second image sensor section. The barcode reader further comprises a first illumination system positioned outside of the first field of view projecting the first illumination into the first field of view at a first angle from the first optical path. The barcode reader further comprises a second illumination system positioned between the second lens assembly and a point from which the first illumination system projects the first illumination into the first field of view. |
| US09330284B1 |
Broadcast refresh of RFID tag persistence
A reader may broadcast a refresh command to a population or subpopulation of tags and thereby refresh and extend the persistence time of a tag flag, such as an inventoried flag. The characteristics, timing, and other details of this broadcast refresh command may be determined based on the state of a reader, environmental, tag-population, and/or tag-capability conditions and parameters. The refresh command may be a Select command of the Gen2 Specification, in which case parameters of the Select command specify the refresh operation. |
| US09330281B2 |
Method for performing coding resource management, and associated processing circuit
A method for performing coding resource management is provided, where the method is applied to a processing circuit. The method includes: with regard to a specific coding operation, selecting a specific module from a hardware module and a program module; and performing the specific coding operation by utilizing the specific module. In particular, the step of selecting the specific module from the hardware module and the program module further includes: based upon at least one characteristic of the specific coding operation, default settings, and/or user settings, selecting the specific module from the hardware module and the program module. An associated processing circuit is also provided. |
| US09330279B2 |
System and method for blocking elements of application interface
A method, system and computer program product for blocking access to restricted elements of application interface and covering the restricted elements by trusted interface elements. The system includes an analyzer module, a database of restricted elements and a blocking module. The analyzer module is configured to detect interface elements of an active application rendered on a computer or a mobile device. The analyzer module determines if an application interface element is restricted by comparing the application interface element against the known restricted interface elements from the database. If the restricted element is detected, the analyzer module sends the data about the restricted element to the blocking module. The blocking module covers the restricted interface element by a trusted interface element or by an image. |
| US09330278B1 |
Service profiles for associating data services with applications
Service profiles for associating data services with applications are described, including receiving a first input from a user identifying a first service to include in a service profile; receiving a second input from the user identifying a second service to include in the service profile, the second service is associated with the user; receiving a third input from the user defining one or more boundaries of one or more of the first service and the second service; receiving a fourth input from the user indicating association of the service profile with one of the at least one application; storing the service profile with information of the first service, the second service, and the association with the one of the at least one application; and based on the service profile, determining whether to grant access to the first service and second service by the at least one application. |
| US09330275B1 |
Location based decryption
Described herein are systems, devices and methods for decrypting content based on location. A media device may decrypt content based on determination of a location-based decryption event. The location-based decryption event may include the media device being located within a location previously defined as authorized to decrypt the content. The location-based decryption event may also include the media device being located within a predetermined distance of a designated reference object. |
| US09330273B2 |
Systems and methods for increasing compliance with data loss prevention policies
A computer-implemented method for increasing compliance with data loss prevention policies may include (1) identifying a file that is subject to a data loss prevention policy, (2) determining a classification of the file according to the data loss prevention policy, (3) identifying a graphical user interface that is configured to display a representation of the file, and (4) enhancing the representation of the file within the graphical user interface with a visual indication of the classification of the file according to the data loss prevention policy. Various other methods, systems, and computer-readable media are also disclosed. |
| US09330272B2 |
Head-mounted display apparatus with enhanced security and method for accessing encrypted information by the apparatus
There are provided a head-mounted display (HMD) apparatus and a method for accessing encrypted information by the apparatus, in which the head-mounted display apparatus with enhanced security according to an embodiment of the present invention includes a biometric information input unit that receives biometric information of a user; a communication module that transmits or receives information to or from a server; a memory that stores encrypted information; a processor that transmits the biometric information received through the biometric information input unit to a user authentication server through the communication module, receives access privilege information from the user authentication server, and decrypts the encrypted information stored in the memory based on the received access privilege information; and a display unit that displays the decrypted information through the processor. |
| US09330268B2 |
Storage devices with secure debugging capability and methods of operating the same
A device includes a first bus, a second bus, a processor configured to communicate with a storage circuit through the first bus and to communicate with a debug host through the second bus and a control circuit configured to inhibit transfer of data from the second bus to the debug host while receiving authentication information from the debug host and to enable transfer of data from the second bus to the debug host responsive to authentication of the received authentication information. The control circuit may be configured to inhibit data transfer from the second bus to the debug host by causing dummy data to be transmitted to the debug host over a transmit channel between the device and the debug host. |
| US09330267B2 |
Filtering confidential information in voice and image data
Confidential information included in image and voice data is filtered in an apparatus that includes an extraction unit for extracting a character string from an image frame, and a conversion unit for converting audio data to a character string. The apparatus also includes a determination unit for determining, in response to contents of a database, whether at least one of the image frame and the audio data include confidential information. The apparatus also includes a masking unit for concealing contents of the image frame by masking the image frame in response to determining that the image frame includes confidential information, and for making the audio data inaudible by masking the audio data in response to determining that the audio data includes confidential information. The playback unit included in the apparatus is for playing back the image frame and the audio data. |
| US09330261B2 |
Proving age and integrity of website pages
Systems and methods are disclosed which enable the establishment of file dates and the absence of tampering, even for documents held in secrecy and those stored in uncontrolled environments, but which does not require trusting a timestamping authority or document archival service. A trusted timestamping authority (TTSA) may be used, but even if the TTSA loses credibility or a challenger refuses to acknowledge the validity of a timestamp, a date for an electronic document may still be established. Systems and methods are disclosed which enable detection of file duplication in large collections of documents, which can improve searching for documents within the large collection. |
| US09330256B2 |
Location based process-monitoring
Disclosed are systems, apparatus, devices, methods, computer program products, and other implementations, including a method that includes determining location of a device, and controlling monitoring of behavior of one or more processes executing on the device based on the determined location of the device to identify potential one or more security-risky processes from the monitored one or more executing processes. In some embodiments, controlling the monitoring of the behavior of the one or more processes may include one or more of, for example, adjusting frequency of the monitoring of the one or more processes based on the determined location of the device, adjusting level of detail obtained for the monitored behavior of the one or more processes based on the determined location of the device, and/or adjusting features being observed for the monitored one or more processes based on the determined location of the device. |
| US09330255B2 |
Method and system for monitoring a computer system
In one embodiment, a method for monitoring a computer system that includes activating and controlling a target processor by way of an electromagnetic signal. The method also includes generating a key for a computer security method via processor readable instructions stored on a first memory device; transmitting the key to the target processor via an electromagnetic signal; and requesting the target processor to perform the computer security method on a target memory device via an electromagnetic signal, where the computer security method uses the key as a seed. |
| US09330254B1 |
Systems and methods for preventing the installation of unapproved applications
The disclosed computer-implemented method for preventing the installation of unapproved applications may include (1) determining that the computing device is pre-configured with a set of approved applications and (2) preventing the installation of unapproved applications onto the computing device by (a) monitoring processes running on the computing device via a daemon executing in the background of the computing device, (b) detecting, by monitoring the processes running on the computing device, an attempt to launch a process that facilitates the installation of applications onto the computing device, and (c) in response to detecting the attempt to launch the process, terminating the process before the process can facilitate the installation of an application onto the computing device. Various other methods, systems, and computer-readable media are also disclosed. |
| US09330251B1 |
Authenticating ferroelectric random access memory (F-RAM) device and method
A memory device including a ferroelectric memory array is described. In one embodiment, the ferroelectric memory array includes a user memory space. The memory device includes control logic configured to provide external read and write access for a host system to the user memory space upon authentication between the host system and the memory device. The host system accesses the user memory space and communicates with the control logic through address, data and control buses. The memory device further includes memory interface configured to interface between the address, data and control buses and the control logic, and through which the host system communicates with the control logic, and a cipher engine in communication with the control logic and the memory interface, the cipher engine comprising a random number generator and an encryption/decryption block. Other embodiments are also described. |
| US09330249B2 |
Information terminal
In an information terminal including a touch panel defining a plurality of touch points for security data entry by selecting and designating the touch points forming a prescribed graphic security pattern, the first touch point is confirmed only when a pointing member has continued to remain within a prescribed region surrounding the touch point for more than a first prescribed time period while the remaining touch points can be confirmed on a less rigorous condition so that the first touch point can be confirmed only when the user intentionally designates the first touch point, and an inadvertent confirmation of an unintended touch point as the first touch point can be effectively avoided. |
| US09330248B2 |
User authentication apparatus of portable terminal
A user authentication apparatus safely uses resources by forming a communication channel between a plurality of execution environments through user authentication in a portable terminal providing the plurality of execution environments based on a virtualization solution, and prevents private information from being illegally leaked by hacking by not directly exposing a PIN number or a password a user inputs using a virtual keyboard and a keyboard coordinate when authenticating the user. |
| US09330246B2 |
System and method for inhibiting access to a computer
A computer security system which prevents an unauthorized user from accessing the computer system when an authorized user has already logged onto the computer system and has temporarily left the workstation. The computer security system generally includes a sensor which is configured to detect the presence of a person in the region around a workstation and a processing unit which logs out of the computer when a person is no longer present in the region. An optional calibration tool may be provided to set the sensitivity of the sensor and prevent accidental logging out when the authorized user is still present in the region around the workstation. |
| US09330243B2 |
Method for biometrically controlling device access and device therefor
A method and device for user authorization is presented herein. The authorization device may be integrated in a display interface configured to receive an infrared input signal. The device may include a means for converting the infrared signal into an electric signal. The device may further include a processor configured to analyze the electrical signal. The processor may further be configured to provide an authorization of a user based on the analysis of the electrical signal. |
| US09330242B2 |
Even more subscription media on demand
An electronic media distribution/play system includes a service facility that has a communications network interface and maintains a data file catalog. The catalog is sent over the network to requesting users, and the system processes payments from customers in establishing file access authorizations. Encrypted user-selected files and a player program are transmitted to each customer for metered access to received data files as limited by the authorization, and customers can make additional selections and play the encrypted files freely while the authorization remains established. The system can transmit the data files from local storage, and also provide links to encrypted files that are stored at remote vendor facilities. Authorizations can be for selected portions or class levels of the catalog, and for terms measured as calendar time, play time, and collective number of plays. Also disclosed is a method for facilitating the distribution and accessing of electronic files. |
| US09330236B2 |
Healthcare assurance system
Systems and methods for healthcare assurance system are provided. A first set of confidential health information for an identified patient may be accessed, may be derived from a first data source, and may include first medical indicia corresponding to an indication of a first health condition and/or an indication of a first healthcare service. A second set of confidential health information may be accessed, may be derived from a second data source, and may include second medical indicia corresponding to an indication of a second health condition and/or an indication of a second healthcare service. Healthcare rules that include criteria indicating comorbidity conditions may be accessed. The first and second sets of confidential health information may be correlated to the healthcare rules. A comorbidity condition may be identified based on the first medical indicia, the second medical indicia, and the correlating. A prompt regarding the comorbidity condition may be provided. |
| US09330234B1 |
Method, apparatus and computer program to provide access to client records and data resources
A method, computer program and apparatus are disclosed that include accessing client data records, such as, medical records. The method for may include, for example, receiving a data file at a file server comprising client records information. The method may also include forwarding the file to a database and adding the file to a record in the database, creating a database file and storing the database file on the file server, and scheduling a call to at least one client, the call including a portion of the information included in the received data file. The method may further provide performing the call, monitoring the call, and may also include updating the client records information stored in the database based on the additional information provided by the at least one client. |
| US09330232B2 |
Displaying and navigating computer-aided detection results on a review workstation
Display and navigation for multiple computer-aided detection (CAD) detections is described. A medical image is displayed to a viewer, and a request is received to instantiate CAD-assisted viewing. A timewise presentation sequence for the CAD detections is automatically computed according to a predetermined sequencing criterion. For each CAD detection, an expanded presentation window is displayed for its associated location in the medical image, the expanded presentation windows being displayed according to the timewise presentation sequence. Also described is a navigational tool comprising a plot of an operating curve onto which a computed feature associated with the CAD algorithm can be mapped, the operating curve characterizing an application of the CAD algorithm to a reference database of mammographic cases having known diagnoses. The navigational tool further comprises a plurality of CAD pointer icons spatially distributed therealong according to mappings of the computed feature for the CAD detections onto the operating curve. |
| US09330231B2 |
Method for determining a flow behavior of a medium
A method for determining a flow behavior of a medium uses at least one analysis device placed inside the medium. The at least one analysis device is freely moveable in the medium and supplies data characterizing at least one property of the medium flow behavior to a data evaluation device. The at least one property of the medium flow behavior is determined by the data evaluation device on the basis of the data in selected areas or in all areas through which the at least one analysis device flows with the medium. |
| US09330221B2 |
Mask-aware routing and resulting device
Methods for routing a metal routing layer based on mask design rules and the resulting devices are disclosed. Embodiments may include laying-out continuous metal lines in a semiconductor design layout, and routing, by a processor, a metal routing layer using the continuous metal lines according to placement of cut or block masks based on cut or block mask design rules. |
| US09330217B2 |
Holdtime correction using input/output block delay
Various techniques are provided to correct for hold time violations using input/output (I/O) block hardware of a programmable logic device (PLD) without requiring additional mapping, placement, or routing operations. In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD. The method also includes assigning components of the PLD to perform the operations. The method also includes routing a signal path among the components. The method also includes detecting a hold time violation for the signal path at an I/O block of the PLD. The method also includes selectively adjusting a variable delay cell of the I/O block to correct the hold time violation. |
| US09330214B2 |
Phase noise reduction in voltage controlled oscillators
A voltage controlled oscillator (VCO), a method of designing a voltage controlled oscillator, and a design structure comprising a semiconductor substrate including a voltage controlled oscillator are disclosed. In one embodiment, the VCO comprises an LC tank circuit for generating an oscillator output at an oscillator frequency, and an oscillator core including cross-coupled semiconductor devices to provide feedback to the tank circuit. The VCO further comprises a supply node, a tail node, and a noise by-pass circuit connected to the supply and tail nodes, in parallel with the tank circuit and the oscillator core. The by-pass circuit forms a low-impedance path at a frequency approximately twice the oscillator frequency to at least partially immunize the oscillator core from external noise and to reduce noise contribution from the cross-coupled semiconductor devices. |
| US09330212B2 |
Recording medium in which circuit simulator program is stored, and device and method for generating eye pattern
An eye pattern is generated by: simulating a rising step response to a rising step signal input into the circuit and a falling step response to a falling step signal input into the circuit; analyzing a result of the simulating of the rising step response and the falling step response; generating, on the basis of a result of the analyzing, an upper-part test pattern that defines a shape of an upper part of an eye of an eye pattern and a lower-part test pattern that defines a shape of a lower part of the eye of the eye pattern; and simulating a response to the upper-part test pattern and the lower-part test pattern both input into the circuit. This procedure rapidly generates a precise eye pattern. |
| US09330210B2 |
Sand art simulation system and method
The present invention provides a sand art simulation system and method, which transfers an image into sand art. Analyze contour lines and feature points of objects in the image to find out which contour line can be drawn at the same time. Divide the image into a plurality of blocks, and analyze sand spilling ways at each block. Simulate sand floating in the air, moving and heaping to make a sand-spread plane. Then draw the contour lines on the sand-spread plane to show the sand art of the image. |
| US09330209B1 |
Characterizing an entity in an identifier space based on behaviors of unrelated entities in a different identifier space
Models are built based on existing histories in one identifier space to infer features of entities in a different identifier space. A source model is built using features of an archetypical population in a given identifier space and the standard population. A join panel, i.e., a set of entities operating across both the given identifier space and a second disjoined identifier space, is scored using the source model. Based on the scores and features associated with the entities in the join panel within the second identifier space, a target model specific to the second identifier space is built. An audience of entities within the second identifier space can then be scored using the target model to identify entities that are similar to the archetypical population. |
| US09330203B2 |
Real-time event feedback
Methods, systems and devices are provided for presenting event feedback information regarding participants to an event. A first radio of a first participant device carried by a first participant receives a first checkpoint communication from a checkpoint device at a first checkpoint located along a first course of the event. The first checkpoint communication includes a first checkpoint identifier and a first event time reflecting when the first participant crossed the first checkpoint. A first checkpoint event time is determined based upon the first checkpoint identifier and the first event time. Also, the first checkpoint event time is displayed on the first participant device. Further, a checkpoint device and an event server may be used to in presenting the event feedback information. |
| US09330191B2 |
Identifying changes for online documents
Techniques and systems are disclosed for providing changed content identification for an online document that is accessed by a user or user agent. A reference point for an online document that a user or user agent is interested in accessing is identified, comprising a stored prior version of the document. The prior version of the document is retrieved, when the user or user agent accesses the online document, such as by using the reference point. Elements of the prior version are compared with elements of a current version of the document, to determine whether there are differences between the versions. If changes are identified between the prior version and the current version, the current version is automatically updated with visual or auditory representations that identify those changes of content. |
| US09330190B2 |
Method and system for providing data handling information for use by a publish/subscribe client
A method for providing data handling information for use by a client of a pub/sub service to handle data published by the pub/sub service includes receiving a subscription request to a data tuple that includes source data from a client of the pub/sub service. When the request is received, a first subscription is provided for the client to the data tuple and a second subscription, distinct from the first subscription, is automatically provided for the client to a data handling tuple that is associated with the data tuple and that includes data handling information defining how the source data of the data tuple is to be handled by the client. A first notification message including the source data is generated and a second notification message, distinct from the first notification message, is generated that includes the data handling information. |
| US09330184B2 |
Methods and systems for machine learning to discover application compatibility status
A system and method is provided for discovering application compatibility status, the method being performed by one or more processors, the method comprising receiving a request for determining compatibility of a first application with a platform and organizing a plurality of data points associated with the first application into a plurality of elements. The method also comprises comparing the plurality of elements with a plurality of elements associated with one or more analyzed applications, wherein the one or more analyzed applications have been previously analyzed for compatibility with the platform. The method further comprises identifying a compatibility status of the first application with the platform based on the comparison; and providing, for display, the compatibility status of the first application. |
| US09330182B2 |
Social network analysis
This invention is generally directed to one or more systems or methods relating to social network analysis. More specifically, this invention is generally directed to one or more systems or methods relating to personal communication networks and the analysis of personal-communication-network data. |
| US09330181B2 |
Methods and apparatuses for document processing at distributed processing nodes
Briefly, the disclosure describes embodiments of methods or apparatuses for document processing at distributed processing nodes. |
| US09330179B2 |
Configuring web crawler to extract web page information
Web crawling configuration includes: obtaining a webpage comprising a plurality of receiving a user selection of a node in the webpage; presenting a set of web crawling configuration options pertaining to a web crawling action to be performed with respect to the node, the set of web crawling configuration options depending at least in part on a type of an element included in the node and comprising: a first option to perform a first web crawling action in the event that the node include a first type of the element; and a second option to perform a second web crawling action in the event that the node includes a second type of the element; receiving a user input specifying the web crawling configuration option; and storing user specified web crawling configuration option, performing the web crawling action on the node according to the user input, or both. |