| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 181 | Gaming system, gaming device and method for utilizing bitcoins | US13231509 | 2011-09-13 | US08449378B2 | 2013-05-28 | Richard E. Michaelson; Kehl T. Lesourd |
| The gaming system may enable a player to wager an amount of bitcoins on one or more plays of one or more primary or base games. If a player wagers an amount of bitcoins on a play of a game, the gaming system may determine and display an outcome for the play of the game. The gaming system then may determine if any award may be associated with the determined outcome. If an award having a value greater than zero is associated with the determined outcome, the gaming system may provide the determined award to the player, such as an amount of bitcoins. | ||||||
| 182 | FAST RETRY OF TRANSMITTING RANDOM ACCESS PREAMBLE USING BITMAP INFORMATION | US12665662 | 2008-06-19 | US20100331003A1 | 2010-12-30 | Sung-Jun Park; Young-Dae Lee; Seung-June Yi; Sung-Duck Chun |
| A fast retry of transmitting a random access preamble by determining an existence of a random access response during a random access procedure in an Evolved Universal Mobile Telecommunications System (E-UMTS) evolved from Universal Mobile Telecommunications System (UMTS) or a Long Term Evolution System (LTE). | ||||||
| 183 | METHOD AND SYSTEM FOR REDUCING POWER CONSUMPTION IN BITCOIN MINING VIA WATERFALL STRUCTURE | EP15855579.7 | 2015-10-29 | EP3213189A1 | 2017-09-06 | GILBOA, Assaf; SHTEINGART, Zvi; LEVIN, Kobi; COREM, Guy |
| A method and engine for hash calculation, the method comprising receiving data blocks via an input module, providing clock cycles by a clock module, calculating a hash from a received data block by a process module including a data pipeline and a state pipeline, the hash calculation comprising: an input data block to the data pipeline, the data block includes a sequence of data words including X data words, wherein X is a known number, calculating, in every other clock cycle of the clock module, an new data word based on the last calculated X data words, and performing a stage of the state pipeline in each clock cycle of the clock module, in which a state is calculated based on input from the data pipeline, the input includes the last calculated X data words, and outputting the hash via an output module every predetermined number of clock cycles. | ||||||
| 184 | METHOD AND SYSTEM FOR REDUCING POWER CONSUMPTION IN BITCOIN MINING VIA DATA INPUT HOPPING | EP15843903.4 | 2015-09-21 | EP3198783A1 | 2017-08-02 | GILBOA, Assaf; SHTEINGART, Zvi; LEVIN, Kobi; COREM, Guy |
| A method and engine for hash calculation, the method comprising receiving data blocks via an input module, providing clock cycles by a clock module, calculating a hash from a received data block by a process module including a data pipeline and a state pipeline, the hash calculation comprising: receiving an input data block to the data pipeline, calculating, in every other clock cycle of the clock module, an induced data block based on the previous data block, and performing a stage of the state pipeline in each clock cycle of the clock module, in which a state is calculated based on input from the data pipeline, and outputting the hash via an output module. | ||||||
| 185 | ACCELERATING BITMAP REMOTING BY IDENTIFYING AND EXTRACTING 2D PATTERNS FROM SOURCE BITMAPS | US14285794 | 2014-05-23 | US20140254926A1 | 2014-09-11 | Nadim Y. Abdo; Voicu Anton Albu; Charles Lawrence Zitnick, III |
| Systems, methods and computer-readable storage media are disclosed for accelerating bitmap remoting by extracting non-grid tiles from source bitmaps. A server takes a source image, identifies possibly repetitive features, and tiles the image. For each tile that contains part of a possibly repetitive feature, the server replaces that part with the dominant color of the tile. The system then sends to a client a combination of new tiles and features, and indications to tiles and features that the client has previously received and stored, along with an indication of how to recreate the image based on the tiles and features. | ||||||
| 186 | METHOD AND DEVICE FOR ENCODING A HIGH-DYNAMIC RANGE IMAGE INTO A BITSTREAM AND/OR DECODING A BITSTREAM REPRESENTING A HIGH-DYNAMIC RANGE IMAGE | PCT/EP2014/078940 | 2014-12-22 | WO2015097118A1 | 2015-07-02 | OLIVIER, Yannick; LASSERRE, Sebastien; LELEANNEC, Fabrice; TOUZE, David |
The present invention generally relates to a method for encoding an image into a bitstream. The method is characterized in that it comprises: - encoding (1100) into the bitstream an illumination map determined (1000) from the image; and - encoding (1200) into the bitstream a signalization data indicating that the bitstream comprises the illumination map. The invention relates also a method and device for decoding a bitstream and also the bitstream itself. |
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| 187 | SYSTEM, DEVICE, AND METHOD FOR STREAMING A MULTIMEDIA FILE ENCODED AT A VARIABLE BITRATE | PCT/US1998/008304 | 1998-04-21 | WO99000986A1 | 1999-01-07 | |
| Data is encoded at a variable bitrate (210, 220) and formed into packets (230) having a server time stamp. The server time stamps are constructed so that the streaming of the packets will be substantially constant, not variable, and equal to a desired, bugeted bandwidth, such as one corresponding to fully utilizing a modem link. to schedule the sending of packets, the server (240) uses the server time stamp, rather than, for example, the play-back time stamp. By having the data encoded at a variable bitrate, the otherwise-unused capacity, i.e., the capacity not used by the server, can be used to send packets needed in the future. This is accomplished by the server time stamps scheduling packets for transmission that will not be needed until the future. | ||||||
| 188 | Bitcoin kiosk/ATM device and system integrating enrollment protocol and method of using the same | US14245971 | 2014-04-04 | US09135787B1 | 2015-09-15 | Mark Russell; John W. Russell |
| A standalone Bitcoin kiosk/ATM device including a bill validator, bill dispenser, printer, one or more scanners/readers, touch screen display, processor/controller and wireless internet connection means (e.g. modem). An enrollment and security protocol involves a processor programmed to run executable instructions, said executable instructions causing said processor to facilitate: (i) receipt of a customer's mobile phone number via the user interface; (ii) transmission of a text message including a random code to the mobile phone of the customer; (iii) receipt and confirmation of the random code entered by the customer via the user interface; (iv) receipt of a PIN entered by the customer via the user interface; (v) receipt of a palm vein pattern via the biometric interface; (vi) receipt of a customer photo via the camera; and (vii) receipt of identification data including photo via the ID scanner/reader. | ||||||
| 189 | 제 1 비트 전송속도를 갖는 제 1 신호와 제 1 비트 전송속도보다 큰 제 2 비트 전송속도를 갖는 제 2 정보신호의 기록 및 재생 | KR1019997006711 | 1998-11-23 | KR1020000070473A | 2000-11-25 | 리카에르트알베르트마리아아르놀드 |
| 본발명은, 제 1 및제 2 기록모드에서제 1 및제 2 정보신호를각각기록하는기록장치에관한것이다. 이장치는 2개의동일한신호처리부(12, 22)를사용하여정보를신호처리함으로써, 기록하기에적합한신호를얻는다(도 1). 더구나, 이기록장치를사용하여기록된신호의재생을위한재생장치가개시된다. | ||||||
| 190 | COMPRESSION CIRCUITRY FOR GENERATING AN ENCODED BITSTREAM FROM A PLURALITY OF VIDEO FRAMES | US12020668 | 2008-01-28 | US20080123748A1 | 2008-05-29 | Martin Bolton |
| Data is discrete cosine transformed and streamed to a processor where quantized and inverse quantized blocks are generated. A second streaming data connection streams the inverse quantized blocks to an inverse discrete cosine transform block to generate reconstructed prediction error macroblocks. An addition circuit adds each reconstructed prediction error macroblock and its corresponding predictor macroblock to generate a respective reconstructed macroblock. The quantized macroblocks are zig-zag scanned, run level coded and variable length coded to generate and encoded bitstream. | ||||||
| 191 | Method for compressing defective bitmap data, and method and device for displaying defective bitmap | JP2007284150 | 2007-10-31 | JP2009110627A | 2009-05-21 | FUJIMI TAKAHIRO; SEKINE HIROAKI |
| PROBLEM TO BE SOLVED: To efficiently compress data while determining defect modes by keeping logical information regarding a defective bit and data of physical amount information regarding a method for compressing defective bitmap data and a method and a device for displaying the defective bitmap. SOLUTION: After converting data of a defective bit into logical information, the logical information is converted into physical position information of the defective bit. Then, types of defective modes are determined from the physical position information, and defective bit groups are separated for each mode, and converted into coordinate information as a group for each separated defective bit group. COPYRIGHT: (C)2009,JPO&INPIT | ||||||
| 192 | METHOD FOR SEARCHING FOR FLASH VIDEO TAG IN BITSTREAM AND SEARCHING APPARATUS THEREOF | PCT/CN2010/075184 | 2010-07-15 | WO2012006784A1 | 2012-01-19 | CUI, Jun |
A method for searching for a flash video (FLV) tag in a bitstream includes the following steps: setting a first start position and a first search length related to a first search process, wherein the first search length indicates a bitstream length of the first search process performed upon the bitstream; starting the first search process upon the bitstream from the first start position to search for the FLV tag; when the FLV tag is not found in the first search length, setting a second start position related to a second search process immediately following the first search process, wherein the first start position and the second start position are separated by a time period equaling a sum of the first search length and a first skip length corresponding to the first search process; and starting the second search process upon the bitstream from the second start position to search for the FLV tag. |
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| 193 | METHOD AND APPARATUS FOR REFERRING TO BITSTREAM ADDRESS RELATED INFORMATION DERIVED FROM SEGMENT OF MULTI-TILE PICTURE TO DETERMINE BITSTREAM START ADDRESS OF TILE OF MULTI-TILE PICTURE | US14142929 | 2013-12-30 | US20140192899A1 | 2014-07-10 | Chih-Ming Wang; Chia-Yun Cheng; Yung-Chang Chang |
| A tile processing method includes at least the following steps: parsing a bitstream of at least a multi-tile picture for deriving bitstream address related information from a segment header of at least a specific segment of the multi-tile picture; and utilizing a tile processing circuit for receiving at least the bitstream address related information and referring to at least the received bitstream address related information to determine a bitstream start address of a specific tile of the multi-tile picture. | ||||||
| 194 | VIDEO PROCESSING APPARATUS CAPABLE OF GENERATING OUTPUT VIDEO PICTURES/SEQUENCE WITH COLOR DEPTH DIFFERENT FROM COLOR DEPTH OF ENCODED VIDEO BITSTREAM | US13726547 | 2012-12-25 | US20140177730A1 | 2014-06-26 | Yung-Chang Chang |
| A video processing apparatus includes a control unit, a storage device, a video decoder and a video processor. The control unit is arranged for generating a color depth control signal. The video decoder is coupled to the storage device, and arranged for decoding an encoded video bitstream and accordingly generating decoded video pictures (sequence) to the storage device. The video processor is coupled to the control unit and the storage device, and arranged for referring to the color depth control signal to enable a target video processing mode selected from a plurality of supported video processing modes respectively corresponding to different output color depths, and processing picture data derived from the data buffered in the storage device under the target video processing mode to generate output video pictures (sequence) to a display apparatus. | ||||||
| 195 | METHOD AND APPARATUS FOR INHIBITING THE PROGRAMMING OF UNSELECTED BITLINES IN A FLASH MEMORY SYSTEM | PCT/US2016/019112 | 2016-02-23 | WO2016160177A1 | 2016-10-06 | TRAN, Hieu, Van; LY, Anh; VU, Thuan; NGUYEN, Hung, Quoc |
Various embodiments for inhibiting the programming of memory cells coupled to unselected bit lines while programming a memory cell coupled to a selected bit line in a flash memory array are disclosed. Various embodiments for compensating for leakage current during the programming of memory cells coupled to a selected bit line in a flash memory array also are disclosed. |
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| 196 | СПОСОБ УЧЁТА ИМУЩЕСТВЕННЫХ И ИНЫХ ИМЕНОВАННЫХ ЕДИНИЦ В ОДНОУРОВНЕВЫХ ЦИФРОВЫХ СРЕДАХ ТИПА BITCOIN И NEXT | PCT/RU2016/000083 | 2016-02-17 | WO2016137360A2 | 2016-09-01 | ЕРМОЛАЕВ, Дмитрий Сергеевич |
| 197 | GAMING PLATFORM SYSTEM AND METHOD FOR INTERACTIVE PARTICIPATION BY PLAYERS WITH SUCCESSES AND LOSSES TRANSACTED USING BITCOIN | PCT/US2015/013962 | 2015-01-30 | WO2015117029A1 | 2015-08-06 | EDWARDS, Kingsley; COLMAR, Edward |
A system and method is disclosed that is directed to a gaming platform that is adaptable for integration with existing competitive skill-based gaming system that will permit participating players to transact wins and losses in Bitcoin. |
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| 198 | Gaming Platform System and Method for Interactive Participation by Players with Successes and Losses Transacted Using Bitcoin | US14611036 | 2015-01-30 | US20150209678A1 | 2015-07-30 | Kingsley EDWARDS; Edward COLMAR |
| A system and method is disclosed that is directed to a gaming platform that is adaptable for integration with existing competitive skill-based gaming system that will permit participating players to transact wins and losses in Bitcoin. | ||||||
| 199 | VIDEO PROCESSING APPARATUS CAPABLE OF GENERATING OUTPUT VIDEO PICTURES/SEQUENCE WITH COLOR DEPTH DIFFERENT FROM COLOR DEPTH OF ENCODED VIDEO BITSTREAM | US15208626 | 2016-07-13 | US20160323589A1 | 2016-11-03 | Yung-Chang Chang |
| A video processing apparatus includes a control unit, a storage device, a video decoder and a video processor. The control unit is arranged for generating a color depth control signal. The video decoder is coupled to the storage device and the control unit, and arranged for referring to the color depth control signal to enable a target video decoding mode selected from a plurality of supported video decoding modes respectively corresponding to different output color depths, and decoding an encoded video bitstream under the target video decoding mode to generate decoded video pictures (sequence) to the storage device. The video processor is coupled to at least the storage device, and arranged for processing picture data derived from the data buffered in the storage device to generate output video pictures (sequence) to a display apparatus. | ||||||
| 200 | BIT-LIKELIHOOD CALCULATING APPARATUS AND BIT-LIKELIHOOD CALCULATING METHOD | US14437938 | 2013-10-03 | US20150295748A1 | 2015-10-15 | Akinori Ohashi; Yasunori Noda |
| A bit-likelihood calculating apparatus includes an initial-bit-likelihood calculating unit obtaining an inter-transmission-signal-point distance corresponding to N, a region number indicating a determination region of a transmission signal point nearest from data, and inter-nearest-point distance from a transmission signal point of initial bit=0 nearest to the data and a transmission signal point of initial bit=1 nearest to the data, and calculating likelihood of initial bit of the data serving as initial term of a recurrence formula for recursively calculating bit likelihood, an i-th-bit-likelihood calculating unit calculating, when N is 2 or larger, difference between inter-nearest-point distance with respect to (i−1)th bit and inter-nearest-point distance with respect to i-th bit and calculating likelihood of i-th bit of the data from likelihood of (i−1)th bit and the difference using the recurrence formula, and a processing-step control unit controlling calculation processing for bit likelihood based on N. | ||||||
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