| Document | Document Title |
|---|---|
| US11405584B1 |
Smart audio muting in a videoconferencing system
A smart muting method for a teleconference or videoconference participant includes detecting audio of an audio-video stream; analyzing video data of the audio-video stream with respect to the detected audio; determining that the audio corresponds to an intended communication, based on the analyzing video data of the audio-video stream with respect to the detected audio; and rendering the audio, responsive to determining that the audio corresponds to an intended communication. |
| US11405580B2 |
Event camera hardware
A method of producing an image frame from event packets received from an event camera comprises: forming a tile buffer sized to accumulate event information for a subset of image tiles, the tile buffer having an associated tile table that determines a mapping between each tile of the image frame for which event information is accumulated in the tile buffer and the image frame. For each event packet: an image tile corresponding to the pixel location of the event packet is identified; responsive to the tile buffer storing information for one other event corresponding to the image tile, event information is added to the tile buffer; and responsive to the tile buffer not storing information for another event corresponding to the image tile and responsive to the tile buffer being capable of accumulating event information for at least one more tile, the image tile is added to the tile buffer. |
| US11405574B2 |
Imaging device with first temperature detection element and second temperature detection element for temperature reference
An imaging device includes: a first temperature detection element 16 that detects temperature on the basis of infrared rays; a second temperature detection element 17 for temperature reference; and a drive circuit 10A including a switch circuit 101 including a butterfly switch circuit, a first current source 82A, a second current source 82B, a differential circuit 83, and an analog-digital conversion circuit 84. The first temperature detection element 16 and the second temperature detection element 17 are connected to a first input end 101A and a second input end 101B of the switch circuit. A first output end 101C and the first current source 82A are connected to a first input end 83A of the differential amplifier. A second output end 101D of the switch circuit and the second current source 82B are connected to a second input end 83B of the differential amplifier. An output end 83C of the differential amplifier is connected to an input portion of the analog-digital conversion circuit 84. |
| US11405571B2 |
Solid-state imaging apparatus and electronic apparatus
Changing the analog gain for each of columns while suppressing an expansion of area and an increase in power consumption. A solid-state imaging apparatus (1, 1A) according to an embodiment includes: converters (10A to 10D) connected to a vertical signal line (VSL) extending from a pixel array unit (30); a voltage generator (20) that is connected to a plurality of voltage lines and outputs reference voltages having mutually different voltage values individually to the plurality of voltage lines; wiring lines (L10 to L31, L20 to L23) connecting the converter and the plurality of voltage lines; and switches (SW0 to SW3) provided on the wiring line and configured to perform changeover of the voltage lines connected to the converter to one of the plurality of voltage lines. |
| US11405570B2 |
Imaging device, imaging system, and semiconductor chip
According to one disclosure, a first semiconductor chip in which a plurality of pixels are formed and a second semiconductor chip stacked on the first semiconductor chip and including analog-to-digital conversion units are provided. A comparator includes a differential amplifier circuit that outputs a first signal, a source ground circuit that includes an input transistor to which the first signal is input and a load transistor cascade-connected to the input transistor and outputs a second signal from a connection node of the input transistor and the load transistor, and a current compensation circuit that includes a current control transistor to which the second signal is input and a current source transistor cascade-connected to the current control transistor and in which the current control transistor causes a second current to flow that changes complementarily with respect to a change of a first current flowing in the source ground circuit. |
| US11405568B2 |
Imaging apparatus and electronic device
A first and second pixel units that perform FD addition are provided. The first pixel unit includes: a first switch transistor of which one source/drain electrode is connected to an FD; and a reset transistor that is connected between another source/drain electrode of the first switch transistor and a power supply node. The second pixel unit includes: a second switch transistor of which one source/drain electrode is connected to an FD; a third switch transistor of which one source/drain electrode is connected to another source/drain electrode of the second switch transistor; and a capacitive element that is connected between another source/drain electrode of the third switch transistor and a reference potential node. The respective other source/drain electrodes of the first switch transistor and the second switch transistor are electrically connected with each other. |
| US11405566B2 |
Imaging element, imaging apparatus, image data processing method, and program
An imaging element includes a reading circuit, a memory that is capable of storing read captured image data, and an output circuit that outputs output image data based on the captured image data to an outside, in which the reading circuit reads out the captured image data using a first reading method or a second reading method having a smaller read data amount than the first reading method, in a case of the first reading method, a first frame rate corresponds to a second frame rate, in a case of the second reading method, the first frame rate is a frame rate lower than in the case of the first reading method, and the first and second reading methods are switched in accordance with a motion of a subject. |
| US11405563B2 |
Spatial alignment transform without FOV loss
This disclosure provides devices, methods, computer-readable medium, and means for spatial alignment transform. In some aspects, a device may perform operations including capturing a first image of a scene using a first sensor at a first zoom ratio, capturing a second image of the scene using a second sensor at a second zoom ratio, the first image having a different field-of-view (FOV) than the second image, determining a translation matrix based on one or more spatial misalignments between the first image and the second image, determining a confidence associated with the translation matrix, in response to the confidence being greater than a confidence threshold, determining a weighting factor based on the first zoom ratio, the second zoom ratio, and a current zoom ratio of the device, applying the weighting factor to the translation matrix, and warping the first image to the second image using the weighted translation matrix. |
| US11405562B2 |
Image processing apparatus, method of controlling the same, image capturing apparatus, and storage medium
An image processing apparatus comprises a first acquisition unit configured to acquire an image shot by continuous shooting while emitting a flash; a second acquisition unit configured to acquire light emission information of the flash in the continuous shooting; a detection unit configured to detect a light emission variation of the flash based on the light emission information; a setting unit configured to set a parameter of a virtual light source for correcting a variation of brightness of the image shot by the continuous shooting due to the light emission variation based on a result of detecting the light emission variation; and a correction unit configured to correct the image shot by the continuous shooting based on the set parameter of the virtual light source. |
| US11405561B2 |
Imaging device and imaging method
An imaging device that images a disease site as a subject includes a camera body, a light unit that is provided in the camera body and includes a first light source and a second light source that have different characteristics, and a filter unit that includes at least one independent filter capable of being positioned on and retracted from an optical axis of the camera body. The imaging device performs continuous imaging by imaging in a state in which the subject is illuminated with light from the first light source and, via a first mode, the filter is positioned on or retracted from the optical axis and, thereafter, imaging in a state in which the subject is illuminated with light from the second light source and, via a second mode that differs from the first mode, the filter is positioned on or retracted from the optical axis. |
| US11405556B2 |
Processing device for processing shake detection signal and control method therefor
A signal processing device includes an acquisition unit configured to acquire a first shake detection signal indicating a detection result of a lens shake detection unit included in an interchangeable lens and a second shake detection signal indicating a detection result of a camera shake detection unit included in a body unit and a determination unit configured to determine a correction amount which is used to correct the first shake detection signal based on the first shake detection signal and the second shake detection signal. The determination unit changes a process parameter for determining the correction amount in accordance with information regarding the camera shake detection unit or information regarding the second shake detection signal. The process parameter includes at least one of a restriction frequency and a gain for the correction amount. |
| US11405555B2 |
Information processing apparatus, image capturing apparatus, information processing method, and storage medium
There is provided an information processing apparatus. A detecting unit detects a first motion amount of an object from an image obtained through first shooting carried out repeatedly at predetermined intervals of time. A converting unit converts the first motion amount into a first motion blur amount that will arise in second shooting, on the basis of the predetermined intervals of time and a shutter speed used in the second shooting. A determining unit determines a first shutter speed adjustment step size on the basis of a difference between the first motion blur amount and a first target motion blur amount that is lower than the first motion blur amount. A changing unit changes the shutter speed of the second shooting at the first shutter speed adjustment step size in response to a first shutter speed changing unit being operated. |
| US11405554B2 |
Control method and device for electronic device, electronic device, and storage medium
A control device includes a processor and a memory storing instructions that, when executed by the processor, cause the processor to obtain state information of an electronic device through one or more sensors of the electronic device and control an electronic image stabilization (EIS) function of the electronic device to be in an off state or an on state based on the state information. |
| US11405552B2 |
Image-capture control
In a camera-enabled electronic device, photo capture is triggered by a press-and-hold input only if the holding duration of the press-and-hold input is greater than a predefined threshold duration. A press-and-hold input shorter in duration than the threshold triggers video capture. Thus, a short press triggers video capture, while a long press triggers photo capture. |
| US11405551B2 |
Imaging apparatus
An imaging apparatus, for capturing a subject image and recording image data on a recording medium, includes: a recording medium connector configured to attach the recording medium detachably; a communication host connected to the recording medium connector via a first communication bus, configured to access the recording medium via the first communication bus to write data to the recording medium or read data from the recording medium; and a processor configured to control power supply, wherein in a case where a period in which the communication host does not access the recording medium is equal to or longer than a predetermined period, the processor stops power supply to the recording medium and the recording medium connector, and stops power supply to the communication host. |
| US11405540B2 |
Camera module
A printed circuit board of a camera module according to various embodiments of the disclosure includes: a ground portion constructed on the printed circuit board; a conductive member which is disposed to cover the ground portion and includes a first opening at a location corresponding to the ground portion; and an adhesive layer which is interposed between the printed circuit board and the conductive member and includes a second opening at a location corresponding to the ground portion, wherein the conductive member may be electrically coupled to the ground portion through a solder constructed on the first opening and the second opening. Other embodiments are also possible. |
| US11405537B2 |
Camera assembly and electronic device having the same
A camera assembly and an electronic device having the same are provided. The camera assembly includes a main board, a cover plate, a camera, an infrared lamp and a deflection member. The mainboard and the cover plate are arranged parallel to and spaced apart from each other. The camera and the infrared lamp are arranged on a side of the main board facing towards the cover plate, and spaced apart from each other. The deflection member is arranged on a side of the cover plate facing towards the main board, and is opposite to the camera. The deflection member is configured to deflect infrared light emitted by the infrared lamp towards a direction of a central axis of the camera. |
| US11405528B2 |
Information processing device and information processing method for avoiding leakage of information
An information processing device and an information processing method capable of effectively implementing sales promotion measures for promoting product purchase via an EC company while avoiding leakage of personal information are provided. The information processing device includes a processing unit that performs mask processing or mosaic processing on a predetermined area of a captured image acquired by capturing at least one of a purchase history, a delivery statement, and an email provided to a user by at least one electronic commerce company, and a determination unit that determines whether the captured image that has been processed includes predetermined information. |
| US11405527B2 |
Image processing apparatus and control method to restrict a function that is made available by an authority
An image processing apparatus includes a providing unit configured to provide, to a second user given an authority of tenant administrator from a first user having an authority of shared office administrator, a function of designating an allowable number of print sheets with respect to a tenant to which the second user belongs or a third user who belongs to the tenant to which the second user belongs, wherein, in a case where the third user, when authenticated, uses a print processing function, the third user is allowed to use the print processing function up to an allowable number of print sheets designated by the second user, who is a tenant administrator of the tenant to which the third user belongs. |
| US11405525B2 |
Image processing apparatus, control method, and product capable of improving compression efficiency by converting close color to background color in a low light reading mode
A mechanism capable of improving the compression efficiency of image data generated by performing the dark reading is provided. An image processing apparatus comprising a reading unit configured to read a document and generate image data, a reading mode setting unit configured to set a reading mode of the reading unit to a first reading mode or a second reading mode, in which the document is read with the amount of light less than that in the first scanning mode, a background color determining unit configured to determine a background color in the image data generated by the reading unit, and a conversion image generating unit configured to generate image data, in which a color close to the background color in the image data is converted into the background color, in a case that the second reading mode is set. |
| US11405522B2 |
Information processing apparatus and information processing method
The present technology relates to an information processing device, and an information processing method, each of which enables to reduce a confirmation load put on a user before a task is executed. The information processing device according to one embodiment of the present technology has the feature of, on the basis of relationship between a first cost required in a case where execution of a predetermined task has been a mistake and a second cost that is allowed by a user for the predetermined task that has been executed by mistake, calculating a confirmation degree of confirming the user as to whether or not to execute the predetermined task, and performing the confirmation by contents corresponding to the calculated degree. The present technology can be applied to an agent apparatus that operates using a voice UI. |
| US11405521B2 |
Electronic device for processing file including multiple related pieces of data
An electronic device is provided. The electronic device includes a housing, a wireless communication circuit, a camera configured to generate raw image data, at least one processor, and a memory. The memory stores instructions configured, when executed, to enable the processor to process first image data corresponding to raw image data via a first algorithm and generate second image data, process the first image data or the second image data via a second algorithm and generate third image data, the second algorithm being different from the first algorithm, generate a first file including the second image data and the third image data, receive priority information from an external electronic device via the wireless communication circuit, generate a second file including the second image data and the third image data based on the priority information, and transmit the second file via the wireless communication circuit to the external electronic device. |
| US11405519B2 |
Information processing apparatus and information processing method
An information processing apparatus includes a communication unit, a determination unit, a power mode setting unit, an input process unit, and a registration unit. The communication unit receives a communication packet. The determination unit determines whether the communication packet received by the communication unit in a second power mode of first and the second power modes meets at least one of a plurality of determination conditions included in determination condition information. The second power mode is lower in electric power consumption than the first power mode. The power mode setting unit switches a power mode from the second power mode to the first power mode on the basis of a result of determination performed by the determination unit. The input process unit receives user operation. The registration unit registers the determination conditions in the determination condition information on the basis of the user operation received by the input process unit. |
| US11405517B2 |
Image reading device and image forming apparatus including the same
In an image reading device including a document platen, a document holder, multiple light sources, and a close contact type image sensor, the light sources are sequentially turned on and the image sensor individually reads light of multiple different colors reflected from a document in a main scanning direction. When the document holder is opened, in an area determination process, a first scanning area where a difference between output values of the image sensor when the light sources are sequentially turned on is within a predetermined threshold value range, and a second scanning area where the difference is outside the predetermined threshold value range are determined in an entire scanning area of the image sensor. A document size in the main scanning direction is detected based on a position of a boundary in the main scanning direction between the first and second scanning areas determined in the area determination process. |
| US11405514B2 |
Electronic apparatus and image forming apparatus
An image forming apparatus includes a display device that displays a plurality of setting items related to an operation of an electronic apparatus, an operation device and a touch panel to be operated by a user, and a controller that sets a value of each of the setting items on a screen of the display device according to an input made through the operation device and the touch panel, initializes the values of the respective setting items, when a total reset mode is set through the operation device and the touch panel, and initializes, when an individual reset mode is set through the operation device and the touch panel, and resetting of the setting items on the screen of the display device is instructed through the touch panel, the value of the setting item about which the resetting has been instructed. |
| US11405513B2 |
Printer control automation from document annotation
Techniques to parse an electronic document to extract a comment and topological features of the electronic document to which the comment is attached, transform the comment into one or more printing command and one or more parameters of the printing command, generate a printed document from the electronic document, and apply the printing command and parameters of the printing command specifically to the topological features to which the comment is attached when generating the printed document. |
| US11405511B1 |
System and method to deliver messages and documents using a global registry
A method performed by at least one computer processor of a message delivery system includes generating a mapping among registry identifiers, destination identifiers, and preferred transmission methods of a plurality of users. Each user's destination identifier is associated with at least one delivery address for receipt of electronic package transmissions by the respective user. An outbound delivery request is received and includes a specified destination identifier for delivery of an electronic package. If the specified destination identifier is included in the mapping table, the mapping table is used to identify, based on the specified destination identifier, a preferred transmission method for transmitting the electronic package. The electronic package is transmitted using the preferred transmission method. |
| US11405510B2 |
Image reader determines if read image data of test pattern satisfies predetermined condition before resuming reading of test pattern
An image reading apparatus, having a placement table, a reader to read an image recorded on the recordable medium placed on the placement table while moving in one direction, a memory storing information concerning a test pattern, and a controller, is provided. The controller is configured to, when instructed to read the test pattern, control the reader to stop reading to pause before reading the test pattern completely, while the reader pauses, based on read data generated from an outcome of reading of the test pattern so far and the information concerning the test pattern, determine whether the read data satisfies a predetermined condition, and when the read data satisfies the predetermined condition, control the reader to resume reading the test pattern, but when the read data does not satisfy the predetermined condition, control the reader to abort reading the test pattern and output an error alerting signal. |
| US11405508B2 |
TDD time slot splitting
The invention discloses a method for a cellular communications system, in which traffic is sent in frames, each frame comprising a first number of subframes, with a second number of said subframes being available for at least either uplink or downlink traffic. At least one of said second number of subframes is made to comprise at least three parts, as follows: One part which is utilized for uplink traffic, One part which is utilized for downlink traffic, One part which is utilized as a guard period, with said guard period part being scheduled between the uplink and the downlink parts. The duration of at least two of said three parts may be varied to fit the current system need. |
| US11405506B2 |
Prompt feature to leave voicemail for appropriate attribute-based call back to customers
Systems and methods are provided for attribute-based client callbacks. A client is prompted to leave a voice message. Attributes are extracted from the voice message and, based on the attributes, tokens created for the selection of an appropriate agent is connected to the client, such as having skills or attributes matching one or more tokens. A callback application server transmits prompts and receives requests for client callbacks. an interaction manager determines agent availability and arranges callback handling, and a session management server initiates callbacks to connect the selected agent with the client. |
| US11405505B1 |
Methods for simultaneous interaction on a web page by a customer and customer service representative
A computer-implemented method and system for enhancing interaction between a customer using a client computer and a customer service representative of a company using a workstation. A Web session is commenced on a Web site for the client computer of the customer, wherein the Web session includes displaying a first Web page to the customer. A telephonic interaction is commenced between the customer and the customer service representative and a split screen is displayed on the workstation. The split screen including the first Web page and a second Web page, wherein the second Web page is only viewable by the customer service representative. An application is caused to be moved from the second Web page to the first Web page for review and interaction by the customer via the client computer. |
| US11405504B1 |
System and methods for using real-time context to proactively start a communication with a customer through a different device
Systems, apparatuses, and methods for providing support or service to a customer, such as a user of a service or product. The support or service may include one or more of assistance with operation, registration, configuration, trouble shooting, account creation, installation of software, replacement, repair, payment for services, and obtaining coverage under a warranty. A bootstrap code or other form of data is generated by a customer support provider and is transferred to the customer and used to authenticate the customer and enable access to securely stored contextual information regarding the device and/or identification information regarding the customer. The code may be provided by the customer support provider to a company and then provided to the customer. |
| US11405499B2 |
Do-not-disturb method and terminal
A do-not-disturb method and a terminal are provided. The method includes: displaying, by the terminal, an interface of a first application, then, if the interface of the first application includes a media playing window, and the first application is in a media do-not-disturb mode, determining whether any first media playing in the window was triggered by a playing operation of a user. If the playing of the first media in the window was triggered by the playing operation of the user, the method includes playing the corresponding media, and if the playing of the first media in the window was not triggered by the playing operation of the user, the method includes pausing or stopping play of the corresponding media. This method can avoid automatic playing of media, to reduce resource waste, data traffic consumption, a processing load of a mobile phone, and power consumption. |
| US11405490B2 |
Smart data transmission protocol optimized for speed and importance
A method of transmitting data between a first computer and a second computer. The method involves the first computers obtaining data for transmission to the second computer, the data including a first type of data and a second type of data. Each type of data has an associated transmission priority, the first type of data has a receipt requirement and the second type of data does not have a receipt requirement. The method further involves the first computer buffering the obtained data in buffer(s), reading the data from the buffer(s) and transmitting the data to the second computer according to the transmission priorities. For the first type of data, the first computer determine, by reference to an expected acknowledgement message from the second computer, whether the transmitted data has been received by the second computer and, if it is determined not to have been received, retransmitting the data to the second computer. |
| US11405487B2 |
System and method for unidirectional communication management system
The present invention provides a system for managing communication requests between client and server over secured communication network unidirectional communication paths, comprising of at least one of the following physical or virtual modules: a. a first unidirectional communication path comprised of at least one RX receiver and TX transceiver enabling to transmit request from the client to the server; b. a second unidirectional communication path comprised of at least one RX receiver and TX transceiver enabling to transmit response to request from the server to the client; c. a client communication management module for managing all incoming requests from the client by indexing said request; d. a web communication management module for managing all received replies from the server based on request index. |
| US11405483B2 |
Relay device and non-transitory computer readable medium storing program
A relay device includes a receiving unit that receives image data from an image processing apparatus and a control unit that controls an update unit that updates log-in information to be generated in a cloud service device in a case where the received image data is transferred to the cloud service device, and the log-in information for the cloud service device is held. |
| US11405480B1 |
Card engine integration with backend systems
A client application can be configured to render user interface cards, based on card data provided by a remote card engine. An API Response as Card (ARC) engine can intercept a communication between the client application and the card engine, and determine that the communication is associated with another backend system. The ARC engine can request that the backend system perform an account action associated with a user account. The ARC engine can provide information derived from a response from the backend system, reflecting a result of the account action, to the card engine. The card action can generate card data associated with the result of the account action performed by the backend system, and the client application can use the card data to render and display a corresponding card, even if neither the client application nor the card engine are natively configured to interface with the backend system. |
| US11405473B2 |
Systems and methods for ensuring continued access to media of a playlist despite geographic content restrictions
Systems and methods are described herein for detecting information that indicates that a user will be traveling from a first geographic location to a second geographic location, and responsively accessing a playlist indicated by a profile of the user that indicates a plurality of streaming media that the user intends to consume. Control circuitry may then compare data corresponding to each streaming media of the plurality of streaming media to a database to determine whether each streaming media of the plurality of streaming media is accessible to the user at the second geographic location, and may determine that a subset of the plurality of media is not accessible to the user at the second geographic location. In response to determining that the subset is not accessible to the user at the second geographic location, the control circuitry may download each media of the subset. |
| US11405469B2 |
System and method for personalized virtual reality experience in a controlled environment
A system and method for initiating a personalized virtual reality session via a virtual reality communication system in a controlled environment is disclosed. The system includes a profile subsystem configured to store an inmate profile of the inmate of the controlled environment. The system also includes a virtual reality subsystem that retrieves the inmate profile associated with the inmate from the profile subsystem, initiates the virtual reality session involving a first communication device used by the inmate of the controlled environment, and personalizes the virtual reality session based on the inmate profile. The system also includes a communication subsystem configured to transmit information related to the virtual reality session to a monitoring system. |
| US11405467B2 |
Automated initialization in a luminaire or other radio frequency positioning node based system
A luminaire-based positioning system including a plurality of luminaires, each respective luminaire including a luminaire identifier. The system includes a gateway including a luminaire node map of commissioned luminaires with a commissioned luminaire identifier and commissioned location coordinates of each commissioned luminaire. The gateway includes an undesignated luminaire roster of undesignated luminaires with a set of undesignated location coordinates. Further, the gateway includes a plurality of projected received signal strength indication (RSSI) values. Additionally, the gateway includes programming to determine an association of an uncommissioned luminaire to a safest fit undesignated luminaire of the undesignated luminaire roster. Further, programming to assign to the uncommissioned luminaire the set of undesignated location coordinates of the safest undesignated luminaire. Additionally, programming to adjust the luminaire node map by adding a new set of commissioned location coordinates with the uncommissioned luminaire identifier that most safely fit the determined set of uncommissioned location coordinates. |
| US11405462B1 |
Systems, methods, and computer program products for testing of cloud and onboard autonomous vehicle systems
Provided are systems, methods, and computer program products for monitoring, testing, or debugging transportation services, generating or transmitting an initiating message from a global manager cloud to an external service cloud, to invoke a transportation as a service (TaaS) message from external service clouds that comprise confirmation, also including generating or transmitting a simulated message from the global manager cloud to mirror the TaaS message, or a portion, transmitted on a TaaS link from the external service cloud to the on-vehicle modem, determining, a confidence threshold for a capability or security of the TaaS link, validating AV service data sent from the global manager cloud to a TaaS component in an on-vehicle black box of the autonomous vehicle system, validating AV compute data sent from the autonomous vehicle system to the TaaS component in the on-vehicle black box, validating TaaS message data received from the external service cloud. |
| US11405458B2 |
Sending and receiving data using multiple objects with a single storage request
A data transmitting method includes obtaining a plurality of first objects, where each of the first objects includes an amount of data that is less than or equal to a first data amount threshold, encapsulating the first objects to generate a second object, where the second object includes the first objects, and sending the second object to a server in an object storage system. |
| US11405455B2 |
Elastic scaling in a storage network environment
Disaggregated storage clusters are disclosed. These disaggregated storage clusters include a plurality of storage targets coupled to each other through a switch and including storage targets including storage and data services storage targets. Data and requests can for storage areas maintained by the storage cluster can be routed between the target of the storage clusters based on pipeline definitions for those storage areas. |
| US11405451B2 |
Data pipeline architecture
A method and a system for managing data flows and data processing operations with respect to a platform are provided. The method includes: executing a first set of microservice applications for coordinating data flows with respect to a data repository; executing a second set of microservice applications for coordinating data processing operations; and executing a third set of microservice applications for performing metadata processing that relates to the data flows and the data processing operations. The system provides an architecture that is designed for delivering information with speed, scale, and quality to diverse destinations and use cases and providing advanced data processing to support real-time streaming processes and aggregated batch processes. |
| US11405442B2 |
Dynamic rotation of streaming protocols
A method and apparatus for dynamic rotation of streaming protocols are disclosed. In the method and apparatus, a first portion of content is streamed to a client device in accordance with a first content delivery protocol. Further, information indicating client device attributes, network conditions or usage conditions is received. A plurality of content delivery protocols including the first content delivery protocol are evaluated based at least in part on the received information to identify a content delivery protocol for streaming the a second portion of the content. |
| US11405440B2 |
Content distribution device and content distribution method
A content distribution device sends control data or content data to a first content receiving device over a wireless communication channel in a first frequency band. The device also sends the content data to a second content receiving device via a wired communication channel or via a wireless communication channel in a second frequency band that is different from the first frequency band. The device detects a performance reduction of the wired communication channel or the wireless communication channel in the second frequency band. In response to the detection, the device starts to send the content data to the second content receiving device via the wireless communication channel in the first frequency band while sending of the control data or the content data to the first content receiving device. |
| US11405432B2 |
Communication apparatus, base station, and codec mode switching method
A UE includes an EUTRA-CMR reception unit that receives a codec mode request (EUTRA-CMR) including a codec mode that is determined by an eNB in accordance with a radio condition of the UE, a mode switching notification unit that notifies an encoder of switching to the codec mode included in the received codec mode request; and a mode switching acknowledgement unit that transmits a response message to the eNB when confirming that the encoder switches the codec mode. |
| US11405428B2 |
Method and system for policy management, testing, simulation, decentralization and analysis
A method of managing supply chain risks having a supply chain risk analysis implementation, includes loading from a data storage or a memory, supply chain data for a supply chain which indicates information about the supply chain; mapping the supply chain data to a consistent input model; automatically analyzing, by an analytics module implemented on a processor, the input model to detect supply chain anomalies indicating the supply chain risks; producing an analysis results output of the analyzed input model; and outputting the analysis results output of the detected supply chain anomalies to the memory, the data storage, a display, or a message. A supply chain risk analysis system includes the processor, the data storage or the memory that stores the supply chain data for the supply chain which indicates information about the supply chain. The processor is configured to perform the processes. |
| US11405427B2 |
Multi-domain policy orchestration model
The present technology pertains to a system, method, and non-transitory computer-readable medium for orchestrating policies across multiple networking domains. The technology can receive, at a provider domain from a consumer domain, a data request; receive, at the provider domain from the consumer domain, at least one access policy for the consumer domain; translate, at the provider domain, the at least one access policy for the consumer domain into at least one translated access policy understood by the provider domain; apply, at the provider domain, the at least one translated access policy understood by the provider domain to the data request; and send, at the provider domain to the consumer domain, a response to the data request. |
| US11405426B2 |
Comparing network security specifications for a network to implement a network security policy for the network
A system compares two network security specifications expected to implement the same network security policy for a network and identifies possible discrepancies between them. The system generates a representation of relations between subnetworks of the network for each network security specification. The representation efficiently stores permitted connections between subnetworks. The system compares the representations corresponding to the two network security specifications to identify discrepancies across the two network security specifications. If discrepancies are identified across the two network security specifications the system generating a report identifying the discrepancies. |
| US11405425B2 |
Rich token rejection system
Authenticating computing entities. A method includes at an identity provider, providing a first access token to an entity for use by the entity in obtaining resources from a resource provider. The method further includes, at the identity provider, receiving response information from the entity. The response information from the entity is provided to the entity from the resource provider as a result of the resource provider enforcing policy at the resource provider. At the identity provider, a second access token is provided to the entity. The second access token is provided based on the response information, such that the second access token can be used by the entity to obtain the resources from the resource provider. |
| US11405424B1 |
Displaying a firewall policy interface
A device may generate a display of a firewall policy management GUI. The device may generate a display in the firewall policy management GUI of a list of existing firewall policies and a firewall policy interface that is adjacent to the list of existing firewall policies in a same view of the firewall policy management GUI. The device may generate a display in the firewall policy management GUI of at least one of a plurality of candidate sources for a new firewall policy, a plurality of candidate destinations for the new firewall policy, or a plurality of candidate security configurations for the new firewall policy. The device may display, in the firewall policy interface, at least one of a first column that includes two or more sources, a second column that includes two or more destinations, or a third column that includes two or more security configurations. |
| US11405419B2 |
Preventing advanced persistent threat attack
Methods, systems for preventing an APT attack and non-transitory machine-readable storage mediums are disclosed. In one aspect, communication data is obtained in a network, association analysis is performed for the communication data, threat data is obtained from the communication data based on an association analysis result, each piece of the obtained threat data is mapped to a corresponding APT attack phase based on a kill chain model; and for each piece of threat data, prevention is performed for a network entity associated with the piece of the threat data based on prevention strategies corresponding to the plurality of APT attack phases. |
| US11405416B2 |
Method and device for identifying security threats, storage medium, processor and terminal
A method, device, storage medium, processor and terminal are for identifying security threats. In an embodiment, the method includes collecting a plurality of security-related security events, each security event containing a plurality of fields; for a first security event of the plurality of security events, searching one or more second security events related to the first security event from the plurality of security events according to one or more fields of the plurality of fields of the first security event, one or more second security events and the first security event forming event graphs; calculating the weights of the event graphs; and sorting the event graphs according to the weights. |
| US11405413B2 |
Anomaly lookup for cyber security hunting
Performing anomaly lookup on data sources that include an entity related to an alert. One or more entities related to an alert and a date when the alert occurred are received. The alert may indicate that an anomaly in data collected from a various data sources may be present in at least one of the data sources. The various data sources are searched for the one or more entities around the alert date to determine which of the data sources include the one or more entities. For those data sources including the one or more entities, an anomaly lookup procedure is performed on the data sources during a first time window to determine an initial set of suspicious anomalies. |
| US11405412B2 |
Inline anomaly detection for multi-request operations
A method is described for a proxy to mitigate attacks from web application clients based on context of web application layer requests. The method includes receiving a plurality of web application layer requests from a web application layer client; aggregating a first set of requests from the plurality of web application layer requests, wherein the first set of requests are part of a first session; determining a profile based on the first set of requests, wherein the profile describes a baseline of expected behavior for a user of the web application layer client; and determining a first threat value associated with the first set of requests based on the first set of requests and the profile, wherein the first threat value describes the likelihood that the first set of requests are part of an attack on one or more web application servers. |
| US11405411B2 |
Extraction apparatus, extraction method, computer readable medium
An extraction apparatus can obtain a first alert and a second alert that are generated, when an anomaly occurs in a control system, in order to provide notification of the anomaly. The extraction apparatus includes: a classification unit configured to generate association information associating the first alert with the second alert; a learning unit configured to learn a generation pattern of the second alert when the anomaly occurs due to a cause other than a cyber-attack based on the association information generated by the classification unit and a generation pattern of the first alert when the anomaly occurs due to a cause other than a cyber-attack; and an extraction unit configured to extract, from among the second alerts, the second alert generated due to a cyber-attack based on the generation pattern of the second alert that is learned by the learning unit and output the extracted second alert. |
| US11405404B2 |
Dynamic privilege allocation based on cognitive multiple-factor evaluation
In an embodiment, a method for allocating privileges on a computer network includes calculating a permission level based at least in part on a login context associated with a login request for connection to a network from a user via a client device, adjusting the calculated permission level such that a resulting first adjusted permission level does not exceed a previous permission level assigned to the client device, assigning the first adjusted permission level to the client device, collecting activity data representative of network activity by the user while logged in to the network, and classifying, using a classifier model, at least a portion of the activity data to generate a second adjusted permission level for the client device. |
| US11405402B2 |
System and method for implementing a computer network
A method for implementing a private computer network over which digital assets can be securely managed, the method comprising: implementing an autonomous network agent on each of a plurality of network devices that are communicable over a digital communications medium, the autonomous network agent being operable to execute a network program that is embodied as program code in a blockchain that is stored and synchronised by the respective network devices, the network program defining permissible network defined digital asset types and corresponding functions. |
| US11405401B2 |
Determining and applying assurance levels for application operations security
A system and method of providing security for an application. A request to use an application to perform an operation using information is received from an operator by a computer system. In response to receiving the request, an operator identity assurance level of the operator and characteristics of the operation using the information are determined. An operation assurance level for the operation is determined based on the characteristics of the operation using the information. It is determined whether the operator identity assurance level of the operator satisfies the operation assurance level for the operation. The operator is allowed to use the application to perform the operation using the information in response to a determination that the operator identity assurance level of the operator satisfies the operation assurance level for the operation. |
| US11405397B2 |
Methods and apparatus to deconflict malware or content remediation
Methods, apparatus, systems, and articles of manufacture to deconflict malware or content remediation are disclosed. An example apparatus includes a site redirector to identify a first request to be transmitted from a client device to a destination site identified by a uniform resource locator (URL), a site verifier to determine whether the first request indicates that a user has authorized navigation to the destination site, and a URL encoder to, in response to determining that the user has authorized the navigation to the destination site, generate a data field based the domain of the destination site, the site redirector to transmit a second request to a network security monitor, the second request to indicate to the network security monitor that the user has authorized the navigation to the destination site, the second request including the data field and the URL. |
| US11405395B2 |
Accessing an internet of things device using blockchain metadata
The computer-implemented invention provides a method and corresponding system for controlling access to and/or use of an internet-enabled resource. The invention uses an electronic ledger such as, for example, the Bitcoin blockchain. The resource may be an IoT device or system. Access to the resource is permitted or enabled upon provision of a cryptographic key e.g. a private key which corresponds to a public key which has been stored in memory. In one embodiment, the public key is stored in a DHT. Access to the resource is prevented or disabled by removing the public key from memory, and using a redeem script of a second blockchain Transaction to spend a tokenised output of a first blockchain Transaction. The second transaction detokenizes the token (or ‘coloured coin’) contained within the first Transaction. In order to prevent further access to the resource, an encrypted message is sent to the internet-enabled resource, wherein the message communicates a public key and the redeem script. The resource then checks whether the public key in the message matches that stored in memory and, if it does, removes the stored version of the public key from memory. The resource then uses the redeem script to perform the detokenization. |
| US11405394B2 |
Trust broker system for managing and sharing trust levels
This disclosure is related to devices, systems, and techniques for controlling access to network services based on a trust ledger. In some examples, a trust broker system enables a relying party to control network service access of client device, where the trust broker system comprises one or more computing devices configured to maintain a trust ledger including a trust account balance (TAB) associated with each user of a set of users, where the TAB associated with each user of the set of users represents a value used to determine whether the respective user is permitted to access a resource. |
| US11405393B2 |
Calls to web services via service proxy
Techniques to handle calls to web services via a service proxy are disclosed herein. In one embodiment, a technique includes an intermediate server receiving a request from a client device to the web service at a target server. In response to receiving the request, the intermediate server can authenticate the received request from the client device and upon successful authentication of the received request, forward the request to the targeted server and invoking the web service to process the forwarded request because the intermediate server is authenticated with the target server. The technique can also include receiving, at the intermediate server, data from the target server that represents execution results of the request by the web service at the target server. Upon receiving the data, the intermediate server can then forward to the client device, the data representing execution results of the request by the web service at the target server. |
| US11405387B1 |
Biometric electronic signature authenticated key exchange token
A method of generating a biometric electronic signature authenticated key exchange (“BESAKE”) token. The method begins when a biometric sample captured from a signing party is received. A secret knowledge factor is received. An encryption key is generated using the secret knowledge factor as an input to a password authenticated key exchange protocol. The biometric sample is encrypted with the encryption key. The BESAKE token is generated and includes the encrypted biometric sample and a signing party identifier associated with the secret knowledge factor. The BESAKE token can be verified using a decryption key generated using a stored knowledge factor as an input to the password authenticated key exchange protocol. The secret knowledge factor is retrieved based on the signing party identifier. The identity of the signing party can be authenticated by decrypting the biometric sample from the BESAKE token using the decryption key and matching the decrypted biometric sample. |
| US11405386B2 |
Electronic device for authenticating user and operating method thereof
Certain embodiments of the disclosure relate to an electronic device for authenticating a user by using user's biometric information, and an operating method thereof. For example, an electronic device according to an embodiment may include: a communication circuit; a biometric sensor; and a processor operatively connected with the communication circuit and the biometric sensor, and the processor is configured to: obtain first biometric information of a user by using the biometric sensor; generate second biometric information for authenticating the user, based on concatenation of the first biometric information and unique information corresponding to the user; and transmit the second biometric information to an authentication server through the communication circuit, where the authentication server authenticates fourth biometric information by comparing the fourth biometric information to the second biometric information, and where the fourth biometric information is generated based on concatenation of third biometric information of the user and the unique information. |
| US11405385B2 |
Alternate user communication routing for a one-time credential
The invention relates to alternate user communication routing for a one-time credential. When a user is determined to be an unauthorized user, the unauthorized user may be provided with an alternative one-time credential (e.g., one-time password, or the like) in response to the user trying to take an action (e.g., to access the organization systems in order to access information). When the unauthorized user tries to utilize the alternative one-time credential, the organization may identify the user as unauthorized and determine how to respond to the unauthorized user. In addition to the alternative one-time credential, one or more additional alternate treatments may be presented to the unauthorized user in order to identify, track, and/or prevent access by the unauthorized user. |
| US11405381B2 |
Tag-based access permissions for cloud computing resources
Example techniques for permitting access to cloud computing resources based on tags are described. In an example, a user is permitted to access a resource provided by a cloud computing platform based on a comparison of identifier of the user with an identifier specified in an access tag associated with the resource. |
| US11405380B2 |
Systems and methods for using imaging to authenticate online users
Systems and methods are disclosed for authenticating an identity of an online user. One method includes receiving from the user, through a first device, a request to access a web page associated with the user's online account; transmitting to the user an image that contains a unique ID and a URL of an authentication server; and receiving from the user, through the first device, an authentication request containing the unique ID. The method also includes receiving from the user, through a second device, a log-in ID associated with the user and the unique ID; and authenticating the identity of the user to grant the user access, through the first device, to the web page associated with the user's online account. |
| US11405379B1 |
Multi-factor message-based authentication for network resources
An authentication process that provides secure and verified access to content, such as content presented on websites. At a first instance, users may be validated using a first token, at a second instance, users may be validated or authorized using the first token and an email address, and at a third instance, users may be validated or authorized using the first token, the email address, and the second token. Therein users are authenticated and provided access to the websites. During the authentication process and the during separate instances (or times), if the multiple token(s) are invalid and/or the email address is associated with an unauthorized user, access to the website may be denied. |
| US11405378B2 |
Post-connection client certificate authentication
A network access control (NAC) device detects a connection of an endpoint device at a network switch coupled to a network and restricts access of the endpoint device to prevent the endpoint device from accessing resources of the network. The NAC device establishes a connection with the endpoint device, validates a client certificate corresponding to the endpoint device to authenticate the endpoint device as a corporate device and grants the endpoint device access to the resources of the network. |
| US11405376B2 |
System and method for single sign-on technical support access to tenant accounts and data in a multi-tenant platform
Shown is single sign-on support access to tenant accounts in a multi-tenant service platform involving a proxy user account in an identity provider for a tenant account on the service platform having security metadata associated therewith, mapping in the identity provider maps a support user to a proxy user identifier, a corresponding security endpoint in the service platform and mapping of the proxy user account identifier to the tenant account and security metadata. The identity provider authenticates a request to access the tenant account on the service platform, obtains the security credentials for the proxy user identifier, and sends a security assertion with the proxy user identifier and the security metadata to the security endpoint. The endpoint receives and validates the security assertion against the mapping for the proxy user identifier to the tenant account and the security metadata in the service platform, and permits access by the support user to the tenant account in the service platform. |
| US11405369B1 |
Distributed encrypted session resumption
Technologies are provided for generating an encrypted session resumption ticket and using the encrypted session resumption ticket to resume a secure session. As part of establishing a secure session with a client, a server can use a common key that is accessible by multiple servers and secret data (such as a private key, etc.) for a tenant associated with the secure session request to generate a session key. The session key can be used to encrypt a session resumption ticket. The client can transmit the encrypted session resumption ticket to another server to re-establish a secure session. The another server can retrieve the common key and the secret data for the tenant, and can use them to generate the session key. The another server can then decrypt the encrypted session resumption ticket using the session key and use the decrypted session resumption ticket to resume a secure session. |
| US11405365B2 |
Method and apparatus for effecting a data-based activity
A third-party intermediary manages a protocol that prohibits the third-party intermediary from substantively accessing data content that, at least in part, underlies received protocol-compliant requests. By one approach, these teachings provide for preventing substantive access to data information that is included within the protocol-compliant request as one or more functions of data, parts of which data may be in tokenized or untokenized form, wherein the values of the functions are generated using secrets, at least one of which is unavailable to the third-party intermediary. By one approach, tokens comprised of data in tokenized form are generated using secrets, at least one of which is unavailable to the third-party intermediary. |
| US11405361B1 |
Securing connections with edge devices that are incapable of encrypted transport layer connections
An IoT service of a provider network may secure connections with IoT devices that are incapable of encrypted transport layer connections. The IoT service may expose a private endpoint of the IoT service into an isolated virtual network of a client. The provider network may provide a private pathway for traffic between the private endpoint and the isolated virtual network. The IoT service may receive, at the private endpoint from a remote edge device of the client, a request to connect to the IoT service. In response, the IoT network may determine that the request was received from the isolated virtual network of the client. In response to determining that he request was received from the isolated virtual network of the client, the IoT service may authenticate the private endpoint and establish a connection with the remote edge device. |
| US11405355B2 |
Identification device, identification method, and identification program
An identification device specifies a boundary which divides rows of IP addresses, which are included in an IP address block and sorted in a predetermined order, into a plurality of parts based on AS numbers, e2LDs, PTR records, etc. of the IP addresses. When the number of the IP addresses included in the part divided by the boundary is equal to or more than a parameter N, which can be arbitrarily set, an identification unit identifies the IP addresses included in the part as dynamic IP addresses. |
| US11405353B2 |
System and method for generating concurrently live and test versions of DNS data
A system for concurrently facilitating publishing a current version of a plurality of Domain Name System (DNS) records for a domain name and storing a next version of the plurality of DNS records for the domain name, the system comprising a record selection module for obtaining selected data of registry data associated with the domain name stored in a registry database; a DNS Security (DNSSEC) signing system having at least one signing module for digitally signing the selected data of the registry data; a distribution system for coordinating concurrent generation of the current version and the next version; and the distribution system and signing system cooperating to, in part, generate the current version according to a first set of generation instructions and transmit the current version to one or more authoritative servers of the DNS in a first transmission path that bypasses storing the current version in the registry database. |
| US11405342B2 |
Surfacing attachments in email search suggestion dropdown
Presenting search suggestions within a messaging application that include attachments without searching messages for the attachments is provided. Messages are received at a computer and managed by a messaging application. A query for suggestions is received via the messaging application. The query is performed by the messaging application without querying the messages that have been received through the messaging application. Suggested search results are provided by the messaging application. The suggestions include attachments that were received via a message through the messaging application. In one or more aspects, the suggested search results also provide other attachments that were received by other than the messaging application. |
| US11405340B2 |
Personality reply for digital content
A computer-implemented method is described. The method includes a computing system receiving an item of digital content from a user device. The computing system generates one or more labels that indicate attributes of the item of digital content. The computing system also generates one or more conversational replies to the item of digital content based on the one or more labels that indicate attributes of the item of digital content. The method also includes the computing system selecting a conversational reply from among the one or more conversational replies and providing the conversational reply for output to the user device. |
| US11405339B1 |
Managing exchange of instant messages using an assigned communication code
A computerized method of managing exchange of instant messages (IM) that includes establishing a foundation for secure communication with an initiator; receiving a request from the initiator to generate an instant messaging code (IM code), the IM code is used as an identifier of the initiator, the request includes at least one IM code property that facilitates regulation of instant messages (i) originated by any one of at least one participant in an exchange of instant messages with the initiator, or (ii) received by anyone of the at least one participant in an exchange of instant messages with the initiator; generating the IM code according to the at least one IM code property and distributing the IM code, for use by anyone of the at least one participant; identifying that an active participant of the at least one participant inputs the IM code; selectively regulating instant messages originated by or received by the active participant according to the IM code properties; using the foundation to establish a secure communication channel between the initiator and the at least one participant; and exchanging secure message between the initiator and the at least one participant. |
| US11405337B2 |
Systems and methods for generating dynamic conversational responses using ensemble prediction based on a plurality of machine learning models
Methods and systems are described for generating dynamic interface options using machine learning models. The dynamic interface options may be generated in real time and reflect the likely goals and/or intents of a user. The machine learning model may provide these features by interpreting multi-modal feature inputs. For example, the machine learning model may include a first machine learning model, wherein the first machine learning model comprises a convolutional neural network, and a second machine learning model, wherein the second machine learning model performs a Weight of Evidence (WOE) analysis. |
| US11405335B2 |
Managing network traffic in virtual switches based on logical port identifiers
Described herein are systems, methods, and software to enhance network traffic management. In one implementation, a first host identifies a packet to be transferred from a first virtual machine on the first host to a second virtual machine on a second host. In response to identifying the packet, the first host identifies a source logical port for the first virtual machine, and transferring a communication to the second host, wherein the communication encapsulates the data packet and the source logical port. Once the packet is received by the second host, the second host may use the source logical port to determine a forwarding action for the packet. |
| US11405325B2 |
In-band-telemetry-based path MTU size determination system
A path MTU size determination system includes a source host device that generates and transmits a path MTU size discovery packet. A plurality of switch devices in the path MTU size determination system provide a network path that couples a destination host device to the source host device. Each of the switch devices is configured to receive the path MTU size discovery packet transmitted by the source host device, provide a switch identity of that switch device and a MTU size supported by that switch device in a MTU size reporting header included in the MTU size discovery packet, and forward the path MTU size discovery packet. One of the switch devices will operate to determine a lowest MTU size in the MTU size reporting header, and another of the switch devices will cause the source host device to provide the lowest MTU size as its path MTU size. |
| US11405321B2 |
5G filters for virtual network functions
Security filters may protect communication and data traversing and communicating between programs in a hosted container system. In addition, an orchestration system may specifically address the creation and behavior of security filters that manage the behavior of virtual network functions residing in containers. |
| US11405319B2 |
Tool port throttling at a network visibility node
Systems and methods are disclosed for analyzing traffic received at a network visibility node to determine traffic levels relative to capacity at tools communicatively coupled to the network visibility node and throttling traffic when the traffic levels exceed tool capacity. In an illustrative embodiment, streams received at a network visibility node are analyzed to predict a traffic level for a given traffic flow. The predicted level of traffic for a given traffic flow is used to decide whether to forward traffic associated with the given traffic flow to a tool port of the network visibility node that is communicatively coupled to an external tool. |
| US11405315B2 |
Multi-hop physical layer data collection protocol
Disclosed embodiments utilize a layer three and/or layer four protocol to collect physical layer properties along a multi-hop network path between a source node and a destination node. The use of a layer three or layer four protocol provides an ability to span multiple links or networks between the source node and destination node, while also collecting the physical layer properties. Once physical layer properties along a network path can be understood, decisions relating to the configuration of the network path and/or whether to communicate via the network path are improved. |
| US11405308B2 |
Automatic discovery of route reflection peering end-points
An auto-discovery route reflector (auto-discovery-RR) may obtain a route from an originating network device and may update a data structure to include at least some information contained in the route. The auto-discovery-RR may identify, based on the data structure, a plurality of target network devices, wherein the plurality of target network devices includes at least one route reflector (RR) and at least one route reflector client (RR-client). The auto-discovery-RR may send the route to the plurality of target network devices to facilitate establishment of a connection between the originating network device and at least one target network device of the plurality of target network devices. |
| US11405306B2 |
Technique for dynamic discovery, update and propagation of multicast stream capabilities in a capability-aware network
Systems and methods provide for the dynamic discovery, update and propagation of multicast streams capabilities in a network. An endpoint can be coupled to a first hop router in a network environment. The first hop router can discover multicast flow characteristics information associated with the endpoint and propagate the multicast flow characteristics information of the endpoint to additional network nodes in the network environment. The first hop router and at least a portion of the additional network nodes can form one or more multicast flows associated with the endpoint through the network environment using the multicast flow characteristic information associated with the endpoint. |
| US11405303B2 |
Intelligent decision-making method and device for UAV formation information interaction topologies in communication interference
An intelligent decision-making device and method for UAV formation information interaction topologies in communication interference, comprising: acquiring a three-dimensional UAV formation without communication interference, an initial communication network D1 and an initial information interaction topology T1; acquiring communication links A0 interrupted by UAV formation with communication interference; acquiring interrupted communication links A1 in T1 based on A0 and T1; determining whether A0 affects T1; if not, T1 being the final information interaction topology; if yes, acquiring substitute reverse arcs of A1 and substituting A1 with them to obtain an information interaction topology T2; determining whether T2 is a three-dimensional persistent graph; if yes, T2 being the final information interaction topology; if not, acquiring an undirected graph R1 corresponding to T2; acquiring spare edges based on R1; and adding an arc corresponding to a spare edge in T2 based on the spare edges to obtain a final information interaction topology. |
| US11405301B1 |
Service analyzer interface with composite machine scores
Provided are systems and methods for determining and displaying service performance information via a graphical user interface. In one embodiment, a system can provide, for each of one or more machines associated with a service: obtaining performance data for the machine; and comparing the performance data for the machine to one or more predefined performance thresholds for the machine to determine a health status for the machine; and determining a health status for the service based at least in part on the health status of at least one of the one or more machines associated with the service. |
| US11405300B2 |
Methods and systems to adjust resources and monitoring configuration of objects in a distributed computing system
Methods and systems automatically adjusting resources and monitoring configurations of objects of a distributed computing system in response to changes to application programs. Methods search event messages for information indicating a change in execution of an object. The information is used to determine resource allocation rules of infrastructure resources by and a monitoring configuration for the object. Expected impacts on the infrastructure resource are determined from the rules. When an expected impact is greater than an associated impact threshold, use of the infrastructure resources may be adjusted to accommodate the changes. The adjustments include scaling up or down the infrastructure resources. When the object is a virtual object, the virtual object may be migrated from one server computer to another server computer within the distributed computer system. The monitoring configuration is used to adjust tools that monitor the objects of the distributed computing system. |
| US11405296B1 |
Automated validation of network matrices
Passive monitoring by network devices can be used to validate a network traffic matrix, which aggregates end-to-end traffic demands between source-destination pairs in the network. Using information regarding the physical and logical topology of the network during the same time period as the traffic matrix, a model of the network is generated. Traffic load on each link between network devices in the network is predicted using the model and the traffic matrix. Actual traffic loads on each link are determined from the passive monitoring data from each network device. By comparing the predicted load with the actual load on each link, a measure of the validity or accuracy of the traffic matrix is obtained. The disclosed techniques can also be applied to validate a network loss matrix. |
| US11405292B2 |
Network management, monitoring, modelling, and troubleshooting of communication gateways
A system includes multiple different types of monitor resources to monitor attributes of communication through a gateway of subscriber domain. The communication system receives identities of communication devices operated in a network of a subscriber domain and, via a first monitor resource, monitors traffic flow associated with the communication devices. A second monitor resource of the communication system monitors latency associated with communications from the gateway resource to the communication devices. A third monitor resource of the communication system monitors spectral energy in upstream and downstream ports of the communication system to determine a health of same. A communication management resource communicates the monitored information to a remote management resource that provides modeling, storage, and/or display of the respective monitor to a user. |
| US11405291B2 |
Generate a communication graph using an application dependency mapping (ADM) pipeline
This disclosure generally relates to a method and system for generating a communication graph of a network using an application dependency mapping (ADM) pipeline. In one aspect of the disclosure, the method comprises receiving network data (e.g., flow data and process information at each node) from a plurality of sensors associated with a plurality of nodes of the network, determining a plurality of vectors and an initial graph of the plurality of nodes based upon the network data, determining similarities between the plurality of vectors, clustering the plurality of vectors into a plurality of clustered vectors based upon the similarities between the plurality of vectors, and generating a communication graph of the network system based upon the plurality of clustered vectors. |
| US11405286B2 |
Internet address structure analysis, and applications thereof
An analysis system automates IP address structure discovery by deep analysis of sample IPv6 addresses using a set of computational methods, namely, information-theoretic analysis, machine learning, and statistical modeling. The system receives a sample set of IP addresses, computes entropies, discovers and mines address segments, builds a network model of address segment inter-dependencies, and provides a graphical display with various plots and tools to enable a network analyst to navigate and explore the exposed IPv6 address structure. The structural information is then applied as input to applications that include: (a) identifying homogeneous groups of client addresses, e.g., to assist in mapping clients to content in a CDN; (b) supporting network situational awareness efforts, e.g., in cyber defense; (c) selecting candidate targets for active measurements, e.g., traceroutes campaigns, vulnerability assessments, or reachability surveys; and (d) remotely assessing a network's addressing plan and address assignment policy. |
| US11405284B1 |
Generating network link utilization targets using a packet-loss-versus-link utilization model
A method and system are described for automatically determining network utilization bounds in order to meet per-link packet loss rate targets through the network. A loss-verses-utilization model is continuously re-generated as part of a feedback loop to update link utilization targets. A target loss rate can be used to generate a link utilization target value using the model. The link utilization target value can be used in a variety of network update models, such as traffic engineering, capacity planning and risk management. Updates can be applied to individual network links, network devices as a whole, or groups of devices (based on type or position in the network). |
| US11405283B2 |
Connections and accesses for hierarchical path computation element (PCE)
Disclosed herein are various embodiments for constructing an abstract domain topology. In one embodiment, a Path Computation Element (PCE) is configured as a parent PCE to at least one child PCE. Each of the child PCEs is responsible for providing path computational services for a domain. Communication is established between the parent PCE and the at least one child PCE. The parent PCE receives from each of its child PCEs domain connection information corresponding to the domain of each child PCE. The parent PCE builds and maintains an abstract domain topology based on the domain connection information that it receives from its child PCEs. In one embodiment, the domain connection information is communicated from the child PCE to the parent PCE by adding a new notification-type (NT) and notification-value (NV) to a notification object in a Path Computation Element Communication Protocol (PCEP) notification message. |
| US11405279B2 |
Virtualized software-defined network
A method may include generating a set of instructions for a set of devices in software-defined network (SDN) to monitor a set of characteristics. The method may also include sending the set of instructions to the set of devices in the SDN via a control plane that is isolated from a packet forwarding path. The method may further include receiving monitor data via the control plane from at least one device of the set of devices in the SDN. The method may also include determining a change to a set of parameters of the SDN. The method may include generating a policy based on the change to the set of parameters of the SDN. The method may include sending the policy to the set of devices in the SDN. |
| US11405278B2 |
Validating tunnel endpoint addresses in a network fabric
Systems, methods, and computer-readable media are disclosed for validating endpoint information for nodes in a network. A network assurance appliance is configured to retrieve an actual tunnel endpoint address for an endpoint in communication with a network fabric via a leaf node in the network fabric, identify a reference tunnel endpoint address for the endpoint, and determine that there is an inconsistency based on a comparison of the actual tunnel endpoint address with the reference tunnel endpoint address. |
| US11405271B2 |
Method for reducing power consumption and device
A method and a device related to the field of mobile terminals and for reducing power consumption of a terminal device when the terminal device enters a doze mode, where after detecting that screen-off duration of the terminal device is greater than first duration, the terminal device sends a transmission control protocol reset packet to an application server of a to-be-controlled application to enable the application server to disconnect a Transmission Control Protocol (TCP) connection to the terminal device. |
| US11405270B2 |
Mobile device connection device and mobile device remote plug-and-play system
The present invention provides a mobile device connection device and a mobile device remote plug-and-play system. The mobile device connection device includes a USB port connected to a mobile device and a communication module for wireless communication with a WiFi access point (AP), and the mobile device connection device performs wireless communication through the WiFi AP. Instant plugging and unplugging can be achieved, the distance limitation can also be overcome, and the user experience is good. |
| US11405268B2 |
Fine grained network management to edge device features
Network management systems and methods are provided. A system is provided that includes an event database that provides a mapping of multimodal sensor data to events of devices coupled to a network, such as operational or behavioral events. A network management engine obtains a set of multimodal sensor data relating to a device, which may include sensor measurement or output data relating to each of multiple device operation or behavior parameters. The engine determines, utilizing the mapping, a match of the set of multimodal sensor data to a specific event associated with the device. Based at least in part on the determined match, the engine causes generation or updating of event data associated with the specific event, the data being accessible by network management software of the network management system. |
| US11405267B2 |
Policy-based temporal domain configuration architecture
Systems and methods address automated temporally based configuration management of a procurement/deployment process that may be used at one or more data centers. A set of current configuration attributes and current parameter settings are maintained for a one or more data centers. Information may be obtained from a purchasing system describing a future device. Prior to actual arrival of the future device, the configuration for that future device may be defined. Upon detection of the uniquely identified future device being communicatively coupled to a management network, the previously defined configuration may be applied. Abstraction from a high-level to vendor specific configuration commands may also be incorporated to allow management of devices from multiple vendors. |
| US11405263B2 |
Using self-operation cases to identify and resolve issues causing network slice reselection
A database stores self-operation cases for slice reselection requests received by a network function virtualization (NFV) system. The self-operation cases include reasons, contexts, remedial actions, and results of the remedial actions for the slice reselection requests. A set of detection rules identifies at least one issue causing the slice reselection requests based on reasons for the slice reselection requests and contexts of the slice reselection requests. The set of detection rules are applied to the self-operation cases to identify the at least one issue and a remedial action is selected to address the at least one issue. The remedial action is performed to reconfigure the NFV system and the processor determines whether the remedial action successfully resolved the at least one issue. Setting status flags for affected cells or slices prevents slice reselections to the affected cells or slices until the at least one issue is resolved. |
| US11405256B2 |
Apparatus and method for receiving quadrature amplitude modulated “QAM” symbol
Techniques are presented for receiving Quadrature Amplitude Modulated (QAM) symbols from a transmitter via a transmission path. In one example, a demodulator is configured to down-convert an incoming Radio Frequency (RF) signal to a baseband signal and convert the baseband signal to digital samples, and output the digital samples. A demapper is configured to receive the digital samples output from the demodulator and output data encoded in QAM symbols. The demapper is further configured to: determine from a constellation of QAM symbols a subset of QAM symbols that a digital sample from the demodulator may represent; apply an offset to each QAM symbol in the subset of QAM symbols of the constellation to result in a subset of offset QAM symbols; determine which QAM symbol in the subset of offset QAM symbols the digital sample most likely represents; and output data representing a determined QAM symbol. |
| US11405252B2 |
Method and apparatus for synchronization signal design
A method of a base station (BS) for transmitting synchronization signals in a wireless communication system. The method comprises generating a primary synchronization signal (PSS) including one of multiple PSS sequences that is generated based on a M-sequence of length 127 in a frequency domain, wherein the PSS indicates part of cell identification (ID) information using a cyclic shift performed on the M-sequence generating the PSS; generating a secondary synchronization signal (SSS) including one of multiple SSS sequences that is generated based on multiple BPSK modulated M-sequences of length 127 in the frequency domain, wherein the SSS indicates the cell ID information using cyclic shifts performed on the M-sequences generating the SSS; and transmitting, to a user equipment (UE), the PSS and SSS over downlink channels. |
| US11405247B2 |
Impulse-radio receiver and method
A communication device and method include a reconfigurable receiver that is reconfigurable between communication, ranging and radar modes. The reconfigurable receiver includes a mixer configured to mix digital samples with a carrier phase estimate signal and configured to generate in-phase digital samples based on the carrier phase estimate. The reconfigurable receiver further includes a symbol correlator configured to correlate against the in-phase digital samples and generate correlated data, and a symbol binning unit configured to bin the correlated data and generate a first order channel impulse response estimate. The reconfigurable receiver yet further includes a multiplexer configured to switch the digital samples to the symbol binning unit when the reconfigurable receiver is configured in radar mode and to switch the correlated data to the symbol binning unit when the reconfigurable receiver is configured in a ranging mode. |
| US11405244B2 |
Single carrier transmission with adaptive roll-off factor for ultra reliable and low latency communication systems
A single carrier transmission that minimizes spectral efficiency loss and reduces out of band emission by using adaptive filtering in a block where different filter parameters are used for different symbols within a block. |
| US11405242B2 |
Methods and circuits for decision-feedback equalization with early high-order-symbol detection
A PAM-4 DFE receives an input signal distorted by inter-symbol interference (IS I) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). An immediate value of the MSB is used to select a set of IS I offsets used to resolve the LSB. Resolved values of the prior values of the MSB and LSB are then used to select the IS I offset for the immediate symbol. |
| US11405241B2 |
Digital isolator
According to one embodiment, a digital isolator includes a first metal portion, a first insulating portion, a second metal portion, a third metal portion, and a first layer. The first insulating portion is provided on the first metal portion. The second metal portion is provided on the first insulating portion. The third metal portion includes first, second, and third portions. The first portion is provided around the first metal portion in a direction perpendicular to a first direction. The second portion is provided on a portion of the first portion with a first conductive layer interposed. The third portion is provided on the second portion and provided around the second metal portion in the perpendicular direction. The first layer contacts the first conductive layer and an other portion of the first portion and is provided around a bottom portion of the second portion. |
| US11405239B2 |
Smart control apparatus, system, method, and computer-readable recording media for a wireless network
An apparatus, system, method, and computer-readable recording media perform smart control in a wireless network, which includes a plurality of wireless devices. Configuration parameters are obtained to set one wireless device as an active master device in the wireless network. The active master device receives updates in the configuration parameters and learned station (STA) information, and periodically transmits the updates to the configuration parameters and the learned STA information to the other wireless devices in the wireless network. Any one of the other wireless devices in the wireless network can use the updates to the configuration parameters and the learned STA information to be set as a new active master device in the wireless network when the active master device becomes out of network. |
| US11405238B2 |
Controlling device and method implemented thereon for ethernet virtual private netwok
A controlling device is disclosed for Ethernet virtual private network (EVPN). According to an embodiment, the controlling device determines a first provider (P) device which is to handle broadcast, unknown unicast or multicast (BUM) traffic from a first provider edge (PE) device in an EVPN instance, on behalf of remaining PE devices in the same EVPN instance. The controlling device performs route reflection from the remaining PE devices to the first PE device such that the first PE device knows that BUM traffic needs to be forwarded to the first P device. The controlling device configures the first P device such that upon receipt of BUM traffic from the first PE device, the first P device can forward the BUM traffic to the remaining PE devices. |
| US11405237B2 |
Unencrypted client-only virtual private network
There is disclosed in one example a computing apparatus, including: a hardware platform, including a processor and a memory; and executable instructions encoded in the memory to provide a client-only virtual private network (VPN) including a VPN client and a VPN server implementation on a single physical device, wherein the VPN client is configured to communicatively couple to the VPN server and to provide proxied Internet protocol (IP) communication services. |
| US11405235B2 |
Modular vehicle sensing, assisting connected system
A modularized system for assembling electronic systems within vehicles, including a hardware connection unit embedded in a vehicle, a plurality of modules in the vehicle, communicating with the hardware connection unit, either by direct support or by an adaptor, and communicating with each other either by wired or by wireless communication, and a cellular device in the vehicle, communicating with the hardware connection unit and with one or more cloud services, and downloading firmware and software for the modules from the one or more cloud services, wherein the system is viewed and modified using a dedicated smartphone application or a cloud dashboard. |
| US11405232B2 |
Device control apparatus, device control system, device control method, and recording medium
A control apparatus is connected to another control apparatus that is connected to a network. The control apparatus acquires control information of another device controlled by the other control apparatus. The control apparatus, during control of the other device connected to the other control apparatus, executes a predetermined command having a format that is a same as that of an interface in the control apparatus and to which an identifier other than that of the control apparatus is appended, the control apparatus using a response from the other control apparatus as a result for the executed command. |
| US11405231B2 |
Data learning server, and method for generating and using learning model thereof
Disclosed is a data learning server according to an embodiment. The data learning server includes a communicator configured to be communicable with an external device, a learning data acquisition unit configured to acquire production information of a home appliance and operation information using the communicator, a model learning unit configured to generate or update a learning model using the product information and the operation information, and a storage configured to store a learning model trained to estimate a new trouble detection pattern related to the trouble item as a result of the generating or updating learning model. Various embodiments are available.The data learning server may estimate a new trouble detection pattern related to a trouble of a home appliance using rule-based or AI algorithm. When estimating a region of interest using the AI algorithm, the data learning server may use machine learning, neural network, or deep learning algorithm. |
| US11405228B1 |
Management of communication bridges between disparate chat rooms
Certain aspects of the disclosure are directed to communication bridging in a telecommunication system. According to a specific example, a Voice over Internet Protocol (VoIP) communication server is provided comprising a uniform resource locator (URL) generation module configured and arranged to form a communication bridge between a first protocol-disparate chat room and a second protocol-disparate chat room in response to receipt of a request from a participant of one of the chat rooms. The URL generation module can identify the participant as being associated with a customer, and redirect the participant to a customer-specific account provided by the communication bridging service. Using the customer-specific account, the URL generation module can generate a URL associated with the communication bridge. Using the generated URL an assimilation and processing module can translate chat messages received, and transmit the translated chat messages between the first chat room and the second chat room. |
| US11405226B1 |
Methods and apparatus for assessing network presence
Methods and apparatus for assessing network presence. In an embodiment, a method is provided for determining a presence score. The method includes transmitting a quick response (QR) code and a sound signal, receiving an image of the QR code and a sound clip of the sound signal, and determining a presence score associated with a user device based on at least one of a comparison of the QR code to the image of the QR code and a comparison of the sound signal to the sound clip. |
| US11405225B1 |
Collaboration platform recommendation tool
An optimal collaboration platform of a plurality of collaboration platforms is identified. Activity of the user is monitored. A change from a current collaboration platform to the identified optimal collaboration platform is recommended based on a ranking of the plurality of collaboration platforms and the activity of the user. The recommendation is transmitted to the user. A determination is made whether the user accepts the transmitted recommendation. In response to determining that the user has accepted the transmitted recommendation, the optimal platform is initiated. |
| US11405223B2 |
Device of physically unclonable function with transistors, and manufacturing method
In accordance with an embodiment, a physically unclonable function device includes a set of transistor pairs, transistors of the set of transistor pairs having a randomly distributed effective threshold voltage belonging to a common random distribution; a differential read circuit configured to measure a threshold difference between the effective threshold voltages of transistors of transistor pairs of the set of transistor pairs, and to identify a transistor pair in which the measured threshold difference is smaller than a margin value as being an unreliable transistor pair; and a write circuit configured to shift the effective threshold voltage of a transistor of the unreliable transistor pair to be inside the common random distribution. |
| US11405220B2 |
Moving target authentication protocols
In one implementation, the disclosure provides systems and methods for generating a secure signature using a device-specific and group-specific moving target authentication protocol. According to one implementation, generating the secure signature entails determining a state of a first device in association with a select time interval. The state of the first device is defined by one or more time-variable characteristics of the first device. The device computes an output for a signing function that depends upon the determined state of the first device associated with the first time interval. |
| US11405215B2 |
Generation of a secure key exchange authentication response in a computing environment
Aspects of the invention include generation of a secure key exchange (SKE) authentication response by a responder node of a computing environment. A computer-implemented method includes receiving an authentication request message at a responder channel on the responder node from an initiator channel on an initiator node to establish a secure communication, the receiving at a local key manager (LKM) executing on the responder node. A state check is performed based on a security association of the initiator node and the responder node. A validation of the authentication request message is performed. A proposal list of the authentication request message is checked. An authentication response message is built based at least in part on a successful state check, a successful validation, and selecting an encryption algorithm from the proposal list. The authentication response message is sent from the LKM to the responder channel. |
| US11405214B2 |
Secure transmission
A method for providing evidential data includes establishing one or more first secret tokens; obtaining one or more data items from one or more sensors; modifying the data item(s) with at least one of the first secret token(s) to provide one or more modified data items; generating a respective first hash value for each of the modified data item(s); generating a second hash value for a data set including each of the first hash values but excluding the data item(s); transmitting a first message including the data item(s), the first hash value(s) and the second hash value; obtaining one or more transaction identifiers which include one or more static identifiers; transmitting an indication of the static identifiers; and establishing one or more second secret tokens after transmission of the first message, the second secret token(s) for combining with one or more second data items for generating a second message. |
| US11405213B2 |
Low latency post-quantum signature verification for fast secure-boot
In one example an apparatus comprises a computer readable memory, an XMSS verification manager logic to manage XMSS verification functions, a one-time signature and public key generator logic, a chain function logic to implement chain function algorithms, a low latency SHA3 hardware engine, and a register bank communicatively coupled to the XMSS verification manager logic. Other examples may be described. |
| US11405210B2 |
Authentication system
An authentication system includes: ECUs constituting on-vehicle network and server device communicating with the ECU. The ECU stores ID and encryption key set individually to the ECU and used for authenticating data exchanged between the ECUs. The server device stores the ID and encryption key of the ECU. The ECU includes: first CPU configured to perform: generating authentication data; generating authentication code by encrypting the authentication data using the encryption key; and transmitting the ID, authentication data, and authentication code to the server device. The server device includes: second CPU configured to perform: acquiring the ID transmitted from the ECU; retrieving the encryption key of ECU corresponding to the ID acquired; acquiring the authentication data and authentication code transmitted from the ECU; and authenticating the ECU using the encryption key retrieved. |
| US11405207B2 |
Dynamic implementation and management of hash-based consent and permissioning protocols
The disclosed exemplary embodiments include computer-implemented systems, apparatuses, and processes that dynamically implement and manage hash-based consent and permissioning protocols. By way of example, an apparatus may obtain consent data that identifies one or more elements of data accessible to an application program executed by a device. The apparatus may generate a consent document for the application program based on at least a portion of the consent data, and may compute a consent hash value representative of the consent document. The apparatus may also generate and transmit permissioning data that includes at least the consent hash value to the device. The permissioning data may, for example, include information that instructs the executed application program to store the consent hash value within a local memory of the device and to associate the consent hash value with an access token of the executed application program. |
| US11405205B2 |
Method and system for recording point to point transaction processing
A method for providing a multi-service platform to entities includes the storage of profiles for a plurality of entities involved in services with other entities, including point to point and business to business transactions, including entities not registered, that can be claimed by each entity, where each entity can provide for roles and hierarchies of authorized users of the platform for that entity, and where the platform is configured to provide, among other services, registration of procurement status for purchase orders in a digital ledger that provides for auditability and immutability. |
| US11405202B2 |
Key processing method and apparatus
A key processing method includes receiving, in a trusted execution environment, an initial key from a file encryption system in a normal execution environment, decrypting, in the trusted execution environment, the initial key to obtain a file key, storing, in the trusted execution environment, the file key in a key register of a storage controller, where the file encryption system in the normal execution environment is forbidden to access the key register, obtaining, in the trusted execution environment, a key index of the file key in the key register, where the key index indicates a storage location of the file key in the key register, and sending, in the trusted execution environment, the key index to the file encryption system. |
| US11405200B1 |
Multilevel split keys for wallet recovery
A system for key storage and recovery includes an interface and a processor. The interface is configured to receive an indication to create a set of recovery encryption key shares. The processor is configured to receive a selection of one or more trusted entities from one or more categories; create a set of recovery encryption key shares based at least in part on one or more recovery encryption keys; and for a trusted entity of the trusted entities: 1) determine a trusted entity public key associated with the trusted entity; encrypt a recovery encryption key share of the set of recovery encryption key shares with the trusted entity public key to generate a trusted entity encrypted recovery encryption key share; and provide the trusted entity encrypted recovery encryption key share to the trusted entity. |
| US11405199B2 |
Determining key server type and key server redundancy information to enable encryption
Provided are a computer program product, system, and method for determining key server type and key server redundancy information to enable encryption. A first key server type for a first protocol is indicated in a key server type field in response to determining a current protocol used to communicate with the key server comprises the first protocol. A query information request is submitted to the key server to determine a key server type in response to determining that the current protocol comprises the second protocol. The second key server type indicated in the response to the query information request is indicated in the key server type field in response to the response indicating the second key server type. The first or second type of key server indicated in the key server type field is used to determine information to include in a key retrieval request. |
| US11405196B2 |
Authenticate transactions of secured file in blockchain
Disclosed is a system and method for authenticating secured file transactions in a tri-party setup. The system comprises of a first agent module, a second agent module, a server arrangement, and a distributed ledger communicably coupled with each other. The system is configured to store a hash corresponding to a transaction in the distributed ledger. The system is further configured to validate a first agent module and a server arrangement to authenticate transfer of secured files. |
| US11405194B2 |
Anti-counterfeiting system and method of use
A method for associated at least one tamper-proof seal with an anti-counterfeiting system, allowing that system to verify the provenance of an associated item, and said system itself is provided for. By generating a series of serial numbers, hashes, verification codes, fixing said serial number and verification code to a tamper proof seal, and providing a means for a user to check those codes against a corresponding computerize database, a system and method for allowing an end-user to check the provenance of a real-world good is disclosed. |
| US11405193B2 |
Encrypted photographing method and system based on fingerprint recognition
An encrypted photographing method based on fingerprint recognition, and a system thereof are disclosed. The method may include: when detecting starting an encrypted photographing mode, obtaining an unlocking fingerprint for starting the encrypted photographing mode; when detecting a photographing instruction, generating an original photo and generating a key pair based on the unlocking fingerprint wherein the key pair may include an encryption key and a decryption key; encrypting the original photo according to the encryption key so as to generate an encrypted photo; and generating a corresponding system directory according to the decryption key, and saving the encrypted photo to the generated system directory. The present disclosure improves the security of a photo, and avoids leaking the content of an encrypted photo. |
| US11405191B2 |
Guaranteed encryptor authenticity
Embodiments described herein provide cryptographic techniques to enable a recipient of a signed message containing encrypted data to verify that the signer of the message and the encryptor of the encrypted data are the same party, or at the least, have joint possession of a common set of secret cryptographic material. These techniques can be used to harden an online payment system against interception and resigning of encrypted payment information. |
| US11405190B2 |
Agreement of exchange keys on the basis of two static asymmetric key pairs
A method for setting up a subscriber identity module for agreeing one or several exchange keys, between a subscriber identity module and a provisioning server includes generating one or several exchange keys from keys of the provisioning server and of the subscriber identity module on a production server and are transmitted into the subscriber identity module and stored, so that the subscriber identity module is put particularly into a state as though it had generated the exchange keys itself. In a method for agreeing one or several exchange keys, between a subscriber identity module and a provisioning server, the subscriber identity module sends its public key to the provisioning server, which subsequently generates the exchange keys. |
| US11405188B2 |
Method for secure transferring of information through a network between an origin virtual asset service provider and a destination virtual asset service provider
The invention is related to a method for secure transferring of information through a network between an origin Virtual Asset Service Provider and a destination Virtual Asset Service Provider, in a hostile environment, where every entity (party member, network node) must proof its entitlement of the information being exchanged. Hostile environment means that neither any entity/network node nor the network as a whole can be trusted. The present method doesn't require other party member/network node or database to secure information transfer. Neither it requires any other trusted entity or server to guarantee or provide proof of ownership of exchange information. The present method for communicating securely between electronic devices uses asymmetric key encryption.The invention comprises also a computer program product comprising program code stored on a non-transitory computer readable medium, said program code comprising computer instructions for performing the inventive method. |
| US11405185B2 |
Methods and architectures for secure ranging
Embodiments described herein enable the generation of cryptographic material for ranging operations in a manner that reduces and obfuscates potential correlations between leaked and secret information. One embodiment provides for an apparatus including a ranging module having one or more ranging sensors. The ranging module is coupled to a secure processing system through a hardware interface to receive at least one encrypted ranging session key, the ranging module to decrypt the at least one encrypted ranging session key to generate a ranging session key, generate a sparse ranging input, derive a message session key based on the ranging session key, and derive a derived ranging key via a key derivation cascade applied to the message session key and the sparse ranging input, the derived ranging key to encrypt data transmitted during a ranging session. |
| US11405180B2 |
Blockchain-based automation architecture cybersecurity
To provide a trusted, secure, and immutable record of transactions within a process plant, techniques are described for utilizing a distributed ledger in process control systems. The distributed ledger may be maintained by nodes which receive transactions broadcasted from field devices, controllers, operator workstations, or other devices operating within the process plant. The transactions may include process plant data, such as process parameter data, product parameter data, configuration data, user interaction data, maintenance data, commissioning data, plant network data, and product tracking data. The distributed ledgers may also be utilized to execute smart contracts to allow machines such as field devices to transact by themselves without human intervention. In this manner, recorded process parameter values and product parameter values may be retrieved to verify the quality of products. Moreover, regulatory data may be recorded in response to triggering events so that regulatory agencies can review the data. |
| US11405178B2 |
Communication apparatus and control method
A communication apparatus includes a communication unit having a first storage area of a predetermined size in which access from another apparatus is permitted and a second storage area of the predetermined size in which access from the other apparatus is permitted, and an encryption unit to generate concatenated encrypted data by using a block encryption method to encrypt a plurality of pieces of data which are to be read out by the other apparatus and encrypted. Data different from the concatenated encrypted data is held in the second storage area, and the concatenated encrypted data generated by the encryption unit is of a size not exceeding the predetermined size and is held in the first storage area. In addition, the size of padding data included in the concatenated encrypted data is smaller than a total size of padding data generated by individually encrypting the plurality of pieces of data. |
| US11405173B2 |
Receiver for high precision synchronization in a shared medium
Some embodiments include an apparatus, method, and computer program product for high precision device synchronization of electronic devices in a shared medium. Some embodiments include a first electronic device that utilizes a combination of synchronization techniques to synchronize with a second electronic device. The first electronic device receives a first signal from the second electronic device that includes network-based synchronization data and marker data, and performs network-based synchronization with the second electronic device at a first synchronization accuracy. The first electronic device receives a second signal, and uses the marker data and phase lock synchronization to detect a frequency change of the second signal received, as well as to determine a corresponding time marker. The first electronic device updates a clock of the first electronic device based at least on the corresponding time marker, the network-based synchronization data, and the marker data. |
| US11405169B2 |
Method and device for transmitting and receiving data by using multiple carriers in mobile communication system
To solve the above-mentioned problem, the method for transmitting and receiving a signal by user equipment (UE) through one or more cells, according to one embodiment of the present specification, comprises the steps of: receiving, from a base station, a first message indicating whether one or more cells usable by the UE are enabled; determining which cells to enable or disable on the basis of the first message; and enabling or disabling the selected cells. According to the embodiment of the present specification, by aggregating carriers amongst different base stations, a possibility for the UE to transmit and receive high-speed data through carrier aggregation can increase. |
| US11405167B2 |
BWP frequency hopping configuration method, network device and terminal
Provided in the present disclosure is a BWP frequency hopping configuration method, a network device and a terminal. The method includes: sending, by a network device, first configuration information of a transmission physical channel to a terminal, wherein the first configuration information is used for indicating at least one frequency domain offset respectively configured for each BWP in at least one BWP. |
| US11405164B2 |
Coordinated access point time division multiple access
This disclosure provides methods, devices and systems for sharing time resources of a wireless medium. Particular implementations relate more specifically to coordinated AP (CAP) time-division-multiple-access (TDMA) techniques for sharing the time resources of a transmission opportunity (TXOP). According to such techniques, a coordinated AP that wins contention and gains access to the wireless medium for the duration of a TXOP may share its time resources with other coordinated APs. To share its time resources, the winning AP may partition the TXOP into multiple TXOP segments each including respective time resources representing a sub-duration of the TXOP. For example, the winning AP may assign, grant or allocate (hereinafter used interchangeably) itself one or more of the time resources and also allocate each of one or more remaining time resources to one or more other ones of the coordinated APs. |
| US11405160B2 |
Method and device in communication node used for wireless communication
The disclosure provides a method and device in communication node used for wireless communication. A first node receives a first signaling, transmits a first bit block set in a first air interface resource block, receives a second signal in a second air interface resource block, and transmits a third signal in a third air interface resource block. The first signaling is used for determining the first air interface resource block, and the first air interface resource block is used for determining the second air interface resource block; the second signal and the third signal indicate whether the first bit block set is correctly received respectively; the first signaling indicates a first time interval. The above method simplifies the design of downlink signalings for allocation of sidelink resources and reduces signaling overheads. |
| US11405156B2 |
Techniques for tracking reference signal with concentrated power per tone
Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive, based at least in part on one or more coverage enhancement requirements associated with the UE, a tracking reference signal (TRS) indication that indicates a set of resources corresponding to a TRS. The UE may receive the TRS, wherein the TRS includes a plurality of tones, wherein a transmission power for each tone of the plurality of tones is inversely proportional to a bandwidth difference between a bandwidth of the TRS and a reference bandwidth associated with the TRS. Numerous other aspects are provided. |
| US11405155B2 |
Non-coherent millimeter-wave communication techniques
Wireless communication techniques that utilize a general purpose (GP) reference signal for non-coherent millimeter-wave communication are discussed. The GP reference signal may have a special structure allowing it to be flexibly used by a mobile device for multiple purposes. A base station may determine a repetition factor for a repetitive intra-symbol GP reference signal mapping based on an event that triggered transmission of the GP reference signal. The base station may also map the GP reference signal to resource elements of a symbol based, at least in part, on the determined repetition factor of the repetitive intra-symbol GP reference signal mapping. The base station may also transmit the mapped GP reference signal. A mobile device may receive the GP reference signal and modify at least one parameter of a plurality of parameters based, at least in part, on processing of the GP reference signal. |
| US11405148B2 |
Communication system, communication device, method, and recording medium of program
A receive terminal setting a non-delivery determination time for determining that a next data packet is not delivered after transmitting an acknowledgement (ACK) packet for a received data packet; when the next data packet is not delivered within the non-delivery determination time, the receive terminal repeatedly transmits a retransmission request (RACK) packet prompting the transmission of the next data packet; a transmit terminal specifies a non-delivered data packet using time difference information based on the time-of-day information of the received ACK packet and RACK packet and retransmits the specified data packet to the receive terminal; the time-of-day information here is a time stamp added by the receive terminal to each of the ACK packet and RACK packet when transmitted, or a time stamp added by the transmit terminal to each of the ACK packet and RACK packet when received. |
| US11405146B2 |
User equipment, electronic device, wireless communication method, and storage medium
The present invention relates to a user equipment, an electronic device, a wireless communication method, and a storage medium. The user equipment according to the present invention comprises a processing circuit configured to: demodulate a downlink signal from a network side device to obtain a Physical Downlink Control Channel (PDCCH) comprised in the downlink signal; and determine, according to the content of Downlink Control Information (DCI) born on the PDCCH, whether to implement Hybrid Automatic Repeat Request (HARD) feedback for the DCI. The use of the user equipment, the electronic device, the wireless communication method, and a computer readable storage medium according to the present invention can improve the reliability of control information born on a PDCCH. |
| US11405142B2 |
Use of different data rates for polling in a multi-rate network
A first node operates in a network. The first node sends a polling message to a second node over a link at a first data rate, receiving an acknowledgement message from the second node. Based at least in part on receiving the acknowledgement message, the first node determines the second node is available to receive an information message. Based at least in part on the determining the second node is available to receive the information message, the first node sends the information message to the second node over the link at a second data rate. The second data rate is based at least on an indication of observed behavior of the link and the first data rate is based at least on the second data rate. For example, the first node may determine the first data rate to be a next slowest available data rate than the second data rate. |
| US11405139B2 |
Code block group (CBG) level retransmission in wireless communication system
A method of data retransmission can include receiving a transport block (TB) including code block groups (CBGs) corresponding to a first hybrid automatic repeat request (HARQ) process from a transmitter at a receiver in a wireless communication system, and transmitting a TB/CBG indicator along with HARQ retransmission information from the receiver. The HARQ retransmission information includes a HARQ acknowledgement (HARQ-ACK) feedback or a retransmission indication for the first HARQ process. The TB/CBG indicator indicates whether the HARQ-ACK feedback or the retransmission indication is TB-level or CBG-level. |
| US11405137B2 |
Receiver, transmitter, communication network, data signal and method improving a retransmission process in a communication network
Data to be transmitted over a channel from a transmitter to a receiver is encoded to obtain a codeword. The codeword is defined by a plurality of variable nodes associated with a plurality of the check nodes of a bipartite graph representing the code. The codeword is transmitted over the channel such that certain variable nodes are transmitted prior to other variable nodes. The certain variable nodes are associated with a subset of the check nodes of the bipartite graph and define a subcodeword known at the receiver. At the receiver, a decodability of the transmitted codeword is estimated using the subcodeword prior to receiving all variable nodes of the codeword. |
| US11405135B2 |
Decoding method and decoding apparatus
A decoding method performed by a receive end device is disclosed. The decoding method includes: receiving a first bit signal; performing level-M forward error correction (FEC) decoding on the first bit signal to obtain a second bit signal, where M is a positive integer greater than zero; checking the second bit signal to obtain a first check result; performing level-(M+1) FEC decoding on the second bit signal based on the first check result to obtain a third bit signal; and, upon determining that M+1 reaches a first preset threshold, performing data processing on the third bit signal to obtain a fourth bit signal, where the fourth bit signal is used by the receive end device to obtain service data transmitted by a transmit end device. |
| US11405134B2 |
Apparatus and method for communicating data over an optical channel
An optical module processes first FEC (Forward Error Correction) encoded data produced by a first FEC encoder. The optical module has a second FEC encoder for further coding a subset of the first FEC encoded data to produce second FEC encoded data. The optical module also has an optical modulator for modulating, based on a combination of the second FEC encoded data and a remaining portion of the first FEC encoded data that is not further coded, an optical signal for transmission over an optical channel. The second FEC encoder is an encoder for an FEC code that has a bit-level trellis representation with a number of states in any section of the bit-level trellis representation being less than or equal to 64 states. In this manner, the second FEC encoder has relatively low complexity (e.g. relatively low transistor count) that can reduce power consumption for the optical module. |
| US11405132B2 |
Apparatuses and methods for managing blind searches
Systems, methods, apparatuses, and computer program products for managing or monitoring of the control channel in new radio (NR) through blind searches are provided. One method may include determining whether a channel estimation limit has been reached for a user equipment. When it is determined that the channel estimation limit has been reached, the method may include selecting blind decoding candidate(s) to be dropped from different control resource set(s) or search space set(s), and removing the selected blind decoding candidate(s) from a set of monitored candidates. |
| US11405131B2 |
AI-based error detection and correction in 5G/6G messaging
Artificial intelligence procedures are disclosed for localizing faults in corrupted messages in 5G and 6G, and for correcting those faults based on measured parameters such as backgrounds and message signals. Message faults can be caused by noise or interference from a variety of sources with a wide range of properties. An AI model with multiple adjustable variables may be “trained” using a large number of message events, including faulted messages, to determine which message elements are likely faulted, based on input parameters such as modulation quality, SNR, and other signal properties. The receiving entity can then attempt a grid search to correct the faulted message elements, or request a retransmission. For field use by base stations and user devices, an algorithm may be developed based on the AI model, and configured to predict which message elements are likely faulted. By detecting and correcting message faults, networks may increase reliability and reduce latency while avoiding most retransmission costs and delays, according to some embodiments. |
| US11405126B1 |
Simplified radio frequency emissions tester and method of use thereof
A testing device is provided that evaluates the operating performance of radio frequency (RF) emitting devices such as a counter-unmanned aircraft system (C-UAS) device. The testing device allows an operator, with limited RF knowledge, to conduct testing on a C-UAS device and quickly verify functionality in any location with no data analysis. The testing device provides a simplified and portable method to test the RF output of devices such as C-UAS. Since C-UAS devices use RF power to disrupt their UAS target, the performance can be assessed by verifying the RF power level emitted by the C-UAS device. In order to do this the testing device measures and assesses the RF power levels in the bands that the C-UAS device emits radio frequency energy. |
| US11405125B2 |
TORminator system and associated methods
A TORminator module is disposed with a switch linecard of a rack. The TORminator module receives downlink electrical data signals from a rack switch. The TORminator module translates the downlink electrical data signals into downlink optical data signals. The TORminator module transmits multiple subsets of the downlink optical data signals through optical fibers to respective SmartDistributor modules disposed in respective racks. Each SmartDistributor module receives multiple downlink optical data signals through a single optical fiber from the TORminator module. The SmartDistributor module demultiplexes the multiple downlink optical data signals and distributes them to respective servers. The SmartDistributor module receives multiple uplink optical data signals from multiple servers and multiplexes them onto a single optical fiber for transmission to the TORminator module. The TORminator module coverts the multiple uplink optical data signals to multiple uplink electrical data signals, and transmits the multiple uplink electrical data signals to the rack switch. |
| US11405124B2 |
Wireless communication system, parent station apparatus and wireless communication method
A master station device is connected to a slave station device that emits a transmission signal received by light via an optical transmission path from a plurality of antenna elements. The master station device includes an optical signal output unit that outputs optical signals of a plurality of wavelengths, a phase adjustment unit that adjusts, for each wavelength, a phase of the transmission signal based on phase rotation that the optical signal is to undergo while being transmitted through the optical transmission path and a phase in one of the antenna elements corresponding to the wavelength of the optical signal, an optical modulation unit that modulates, for each wavelength, the optical signal output by the optical signal output unit with the transmission signal the phase of which is adjusted in accordance with the wavelength of the optical signal, and an optical combining unit that multiplexes the optical modulated signal of each wavelength and outputs the multiplexed signal to the optical transmission path. The slave station device includes an optical demultiplexing unit that demultiplexes the optical modulated signal transmitted through the optical transmission path and an optical/electric conversion unit that outputs the transmission signal obtained by converting the optical modulated signal of each wavelength into an electric signal to one of the plurality of the antenna elements corresponding to the wavelength. |
| US11405118B2 |
Electronic device in wireless communication system and wireless communication method with multiple channel access determination
Disclosed are an electronic device in a wireless communication system, and a wireless communication method. The wireless communication system comprises multiple unlicensed carriers. The electronic device comprises: one or more processing circuits configured to: configure each of a plurality of unlicensed carriers to be a primary channel or a secondary channel, so as to obtain at least two primary channels and at least one secondary channel; perform a first channel detection process over each of the primary channels to detect whether each of the primary channels is idle, and perform a second channel detection process over each of the secondary channels to detect whether each of the secondary channels is idle; and perform downlink data transmission over the primary channel determined to be idle by means of the channel detection or over the primary and secondary channels determined to be idle by means of the channel detection. By utilizing the electronic device and the wireless communication method, the probability of access to an unlicensed carrier is improved. |
| US11405117B2 |
Method for determining a characteristic of a receiver in a medium, and system implementing this method
Method for determining a characteristic of detection and/or identity information and/or location information of a receiver, wherein: a) a primary wave is emitted by an antenna, b) adjustable elements are controlled with a plurality of sets of parameters, to modify the propagation of a primary wave and/or of a secondary wave coming from the receiver, and c) signals received by the antenna are saved, and d) the characteristic of the receiver in the medium is determined based on the signals received for each set of parameters. |
| US11405116B2 |
Systems and methods for mitigating in-phase and quadrature mismatch
A method of optimizing at least one IQMC parameter value for an IQMC includes: generating a set of tested IQMC candidate parameter values by performing an iterative method including selecting a first IQMC candidate parameter value for the at least one parameter of the IQMC; determining, using the first IQMC candidate parameter value, a performance metric value that comprises at least one of (i) an image rejection ratio (IRR) value, (ii) a signal-to-interference-plus-noise ratio (SINR) value, or (iii) a signal-to-image ratio (SImR) value; and determining a second IQMC candidate parameter value that is an update to the first IQMC candidate parameter value. The method of optimizing at least one IQMC parameter value for an IQMC further includes determining an IQMC candidate parameter value of the set of tested IQMC candidate parameter values that optimizes the performance metric. |
| US11405115B2 |
Generation of entangled qubit states
A method includes receiving Bell pairs. Photons are obtained in a Greenberger-Hom-Zeilinger (GHZ) state by providing, to a first beam splitter, a photon from a first Bell pair and a photon from a second Bell pair. The first beam splitter is coupled with a first output channel and a second output channel. Obtaining the photons in the GHZ state further includes providing, to a second beam splitter, a photon from a third Bell pair and a photon from a fourth Bell pair. The second beam splitter is coupled with a third output channel arid a fourth output channel. Obtaining the photons in the GHZ state further includes providing a photon output from the second output channel as a first input to a detector and a photon output in the third output channel a second input to the first detector. |
| US11405114B1 |
Automatic power control for an optical receiver
An optical receiver includes an optical amplifier that is optically connected to a local oscillator (LO) and a plurality of optical hybrid mixers of the optical receiver and that is electrically connected to a controller. The optical amplifier is configured to receive an optical LO signal from the LO, receive a voltage value associated with an optical input signal of the optical receiver, control a power of the optical LO signal based on the voltage value, and provide, after adjusting the power of the optical LO signal, the optical LO signal to the plurality of optical hybrid mixers. The controller, is configured to determine the voltage value associated with the optical input signal and cause the voltage value to be provided to the optical amplifier. |
| US11405113B2 |
Frequency agile microwave radiometer, hyperspectral microwave radiometer and methods of operation
A hyperspectral radiometer may comprise one or more antennas, a electro-optical modulator modulating the received RF signal onto an optical carrier to generate a modulated signal having at least one sideband; a filter filtering the modulated signal to pass the sideband to a photodetector; and a photodetector producing an electrical signal from which information of the RF signal can be extracted. In some examples, the optical sideband may be spatially dispersed to provide a plurality of spatially separate optical components to the photodetector, where the spatially separate optical components having different frequencies and correspond to different frequencies of the received RF signal. In some examples, the passed sideband may be mixed with an optical beam having a frequency offset from the optical carrier to form a combined beam having at least one optical signal component having a beat frequency from which information of the RF signal can be extracted. |
| US11405105B2 |
System for optical free-space transmission of a string of binary data
High power, high speed VCSEL arrays are employed in unique configurations of arrays and sub-arrays. Placement of a VCSEL array behind a lens allows spatial separation and directivity. Diffusion may be employed to increase alignment tolerance. Intensity modulation may be performed by operating groups of VCSEL emitters at maximum bias. Optical communications networks with high bandwidth may employ angular, spatial, and/or wavelength multiplexing. A variety of network topologies and bandwidths suitable for the data center may be implemented. Eye safe networks may employ VCSEL emitters may be paired with optical elements to reduce optical power density to eye safe levels. |
| US11405104B1 |
Method and system for longitudinal performance monitoring of an optical communication line
Systems and methods for longitudinal performance monitoring of an optical communication line communicably connecting a transmitting device to a receiving device for transmitting a signal therebetween. The method comprises receiving the signal at the receiving device, the signal having been affected by propagative impairments accumulated along the optical communication line, generating, at the receiving device, a linear signal based on the received signal, generating, based on the linear signal, a plurality of signal templates, and determining correlation values between the received signal and each signal template of the plurality of signal templates, each correlation value being indicative of a local longitudinal performance of the optical communication line. |
| US11405095B2 |
5G new radio beam refinement procedure
Apparatuses, systems, and methods for a wireless device to perform methods to implement mechanisms for a UE to request a beam quality measurement procedure. A user equipment device may be configured to perform a method including performing transmitting a request to perform a beam quality measurement procedure for downlink receptions (e.g., a P3 procedure) to a base station/network entity, receiving instructions to perform the beam quality measurement procedure from the base station, and transmitting results of the beam quality measurement procedure to the base station. In some embodiments, transmission of the request may be response to at least one trigger condition and/or detection of a condition at the UE. The request may include an indication of a preferred timing offset. The instructions to perform the beam quality measurement procedure may include a schedule for the beam quality measurement. |
| US11405094B2 |
Default quasi co-location assumption after beam failure recovery for single-downlink control information-based multiple transmit receive point communication
Default QCL assumptions for UEs and base stations to apply after identifying a new beam in response to beam failure detection are provided for single-DCI multi-TRP communication. In one aspect, a default QCL assumption for PDSCH after beam failure detection may be applied based on TCI states corresponding to a lowest codepoint among the TCI codepoints containing two different states. In another aspect, a default QCL assumption for PDSCH after beam failure detection may be applied based on at least one of: a lowest CORESET-ID in a latest monitored slot, a selected RS index during beam failure recovery, CORESET-0, or a first TCI state corresponding to the lowest TCI codepoint indicating two TCI states. Additionally, default QCL assumptions for UEs and base stations to apply during beam failure recovery are provided for single-DCI multi-TRP communication when the UE is not configured with a set of beam failure detection resources. |
| US11405087B1 |
Systems and methods for dynamically adjusting reporting periodicity
Systems and methods are provided for dynamically changing channel state information (CSI) reporting periodicity for a wireless device communicating with an access node within a wireless network. The methods and systems identify a wireless device in an undesirable location based on an antenna a sector power ratio of an antenna deployed by the access node within the wireless network. Further, the method determines an existing CSI reporting frequency for the wireless device reporting to the access node and dynamically, in response to the determination, changes the CSI reporting frequency for the wireless device to enable more frequent CSI reporting to the access node. |
| US11405086B2 |
Channel state information (CSI) acquisition for dynamic MIMO transmission
Certain aspects of the present disclosure provide techniques for dynamic switching of reference transmission schemes used by a UE for CSI measurement and reporting. |
| US11405084B1 |
Sounding for uplink multi-user transmission beamforming in wireless networks
Systems and methods are provided for transmitting, by an access point, a trigger frame to a plurality of stations on a network. The trigger frame can be associated with a start of a sounding procedure for the plurality of stations to uplink (UL) beamform with the access point. A corresponding response frame can be received by the access point from each station of the plurality of stations. The corresponding response frame can be synchronized with other response frames in reception time. A beamforming feedback can be generated for the plurality of stations. At least a portion of the beamforming feedback can be transmitted to at least one station of the plurality of stations. A data transmission from the at least one station can be beamformed based on the portion of the beamforming feedback. |
| US11405083B2 |
Un-manned aerial vehicle comprising an antenna element panel
The present disclosure relates to an un-manned aerial vehicle having a control unit, a body part and an antenna arrangement that includes an antenna element panel and at least one antenna port that is adapted to provide at least one antenna beam that is electrically steerable to at least two different directions. The aerial vehicle further has a direction unit that connects the antenna element panel to the body part, where the direction unit is adapted to set the antenna element panel in at least two different positions relative the body part. |
| US11405082B2 |
Dynamic scheduling of user equipment (UE) antenna resources
Certain aspects of the present disclosure provide techniques for dynamically scheduling antenna resources of a wireless node, such as, antenna panels of a user equipment (UE). In some cases, a first node (e.g., a UE) performs, with two or more other nodes, a first beam sweep procedure across two or more antenna resources of the first node on two or more wireless interfaces, generates or obtains scheduling information based on results of the first beam sweep procedure, wherein the scheduling information indicates which of the antenna resources is scheduled for which wireless interfaces, and communicates with the other nodes on the wireless interfaces according to the scheduling information. |
| US11405081B2 |
Method for performing MU-MIMO beamforming training in wireless LAN system, and method and device for supporting MU-MIMO beamforming training
The present invention relates to a method for performing MU-MIMO beamforming training, the method comprising: receiving a MIMO beamforming setup frame including identification information of a station participating in MU-MIMO beamforming training, in an MU-MIMO beamforming setup subphase; receiving a BRP frame in an MU-MIMO beamforming training subphase; and performing MU-MIMO beamforming training using the BRP frame, if the identification information of the station included in the MIMO beamforming setup frame responds to the STA and a TA field and an RA field of the BRP frame are the same as a MAC address of an initiator that has transmitted the MIMO beamforming setup frame. |
| US11405074B2 |
NFC interface with energy management function
An NFC interface with an energy management function. The NFC interface has an independent energy antenna, and the NFC interface comprises an energy management module and an energy storage module, wherein the energy management module is electrically connected to the energy storage module; and the energy management module is used for charging the energy storage module according to electric energy collected by the energy antenna, and is further used for cutting off charging to the energy storage module when the energy storage module pulls down a voltage collected by the energy antenna to a first voltage threshold value. By means of adding an energy management module to dynamically manage collected energy, the present invention can greatly improve the energy receiving power of an NFC interface, and also carries out storage management on the electric energy, thereby allowing an apparatus with such an NFC interface to collect more energy; and can output more NFC energy to the outside, so that the NFC interface has more extensive use. |
| US11405071B2 |
User terminal and radio communication method
Inter-slot frequency hopping of an uplink channel/signal is appropriately controlled. A user terminal according to the present invention includes: a transmission section that transmits an uplink data channel over a plurality of slots; and a control section that controls frequency hopping of the uplink data channel between the plurality of slots. |
| US11405070B2 |
Radio transceivers
A radio transceiver device comprises a transmit amplifier, a receive amplifier, an impedance matching circuit portion, and an antenna connection node for connection to an antenna. The impedance matching circuit portion is arranged between the antenna connection node and each of the transmit and receive amplifiers. The impedance matching circuit portion comprises a switch and an inductor and is arranged such that, in a receive mode of operation, the switch is first state and incoming signals from the antenna pass to the receive amplifier via the inductor. In a transmit mode of operation, the switch is in a second state and the transmit amplifier is coupled to a power supply rail VDD via the inductor. |
| US11405068B2 |
Bi-directional single-ended transmission systems
Systems for bi-directional single-ended transmission are described. For example, a system may include a receiver with a first differential input terminal and a second differential input terminal, wherein the first differential input terminal is coupled to a first node and the second differential input terminal is coupled to a second node; a transmitter with an output terminal coupled to a third node; a first inductor connected between the first node and the third node; a second inductor connected between the second node and the third node; and a shunt resistor connected between the third node and a ground node. |
| US11405066B2 |
Apparatus and method for supporting an article
Modular mounting systems for supportably engagement of one or more devices. The systems may include corresponding attachment members and carrier members for selective supportive engagement of one or more devices relative to a base. The attachment members and carrier members may be magnetically engageable. Various form factors for devices, base members, carrier members, attachment members, and other portions of the system are described. |
| US11405064B1 |
Bypass path reuse as feedback path in frontend module
Methods and devices for processing of RF signals according to different gain modes are presented. According to one aspect, an active amplification mode is provided by switchable active paths coupled to respective input RF signals and a passive attenuation mode is provided by switchable passive paths coupled to the respective RF signals. According to another aspect, a common switchable feedback path coupled to the switchable active paths is used to provide an active attenuation mode. Coupling of the common switchable feedback path to the switchable active path is provided by switches of the switchable passive paths, including for coupling both ends of the common switchable feedback path or just one end. |
| US11405063B2 |
Radio tray assemblies
Described herein are radio tray assemblies that include space for a specific radio and its power supply and that additionally provide cooling and power conversion and control functionalities. The disclosed radio tray assemblies are designed to have a form factor compatible with legacy radio systems (e.g., MIDS-LVT) while enabling installation of a new radio system (e.g., MIDS-JTRS). The disclosed radio tray assemblies are configured so that the radio and its power supply are secured to a tray so that the radio and power supply are side-by-side and parallel lengthwise. A cooling module or assembly of the disclosed radio tray assemblies is disposed immediately behind the radio and its power supply and is configured to cool these units using forced air cooling directed lengthwise through the radio and its power supply. A power converter and controller module converts input power into the power required by the radio power supply. |
| US11405062B1 |
Startup circuit device, filter and receiver
The present disclosure discloses a startup circuit device, a filter and a receiver. The startup circuit device is applicable to the filter that includes a fully-differential operational amplifier and a common-mode feedback circuit device connected in sequence. Both the first startup input terminal and the first startup output terminal are connected to a first amplification input terminal of the fully-differential operational amplifier, and both the second startup input terminal and the second startup output terminal are connected to a second amplification input terminal of the fully-differential operational amplifier. The startup circuit device is configured to adjust a received input voltage to a target voltage during startup of the fully-differential operational amplifier, and output the target voltage to the fully-differential operational amplifier, such that the fully-differential operational amplifier operates at the target voltage, and stability of the fully-differential operational amplifier during the startup can be improved effectively. |
| US11405060B2 |
Electronic device
The present disclosure provides an electronic device. The electronic device includes a body and a display screen. The display screen is fixed to the body. A back of the body includes a spacing area not covered by the display screen, the spacing area including a conductor layer. The electronic device further includes an antenna of the electronic device disposed in the spacing area to emit or receive radio frequency signals. The antenna includes the conductor layer. |
| US11405058B2 |
Stopping criteria for layered iterative error correction
The present disclosure includes apparatuses and methods related to stopping criteria for layered iterative error correction. A number of methods can include receiving a codeword with an error correction circuit, iteratively error correcting the codeword with the error correction circuit including parity checking the codeword on a layer-by-layer basis and updating the codeword after each layer. Methods can include stopping the iterative error correction in response to a parity check being correct for a particular layer. |
| US11405056B2 |
Magic state distillation using inner and outer error correcting codes
Examples are disclosed that relate to, on a quantum computing device, distilling magic states encoded in a [[n,k,d]] block code comprising an outer code. One example provides a method comprising preparing encoded noisy magic states using data qubits, and measuring Clifford stabilizers on the data qubits, thereby applying an inner code. The method further comprises initializing output qubits and initiating a teleportation of distilled magic states derived from the encoded noisy magic states to the output qubits. The method further comprises measuring X-stabilizers on the data qubits, postselecting based on the outcomes, measuring each data qubit destructively utilizing Z-stabilizers, and applying one or more postselection conditions to the data qubits to complete the teleportation of the distilled magic states to the output qubits. |
| US11405055B2 |
Methods and apparatus for error correction coding with triangular factorization of generator matrix
An encoder apparatus for reliable transfer of a source data block d in a communication system includes an outer transform configured to receive a data container block v and compute an outer transform block u, whereby u=vGout for an outer transform matrix Gout. The encoder apparatus also includes an inner transform configured to receive the outer transform block u and compute a transmitted code block x, whereby x=uGin for an inner transform matrix Gin. The data container block v is obtained from the source data block d and a frozen data block a. The frozen data block a is a predetermined block of symbols. The outer transform matrix Gout and the inner transform matrix form a triangular factorization of a transform matrix G, which optionally is a non-triangular matrix, while the outer transform matrix Gout and the inner transform matrix Gin are strictly upper- and lower-triangular matrices, respectively. |
| US11405053B2 |
Parallel decompression of compressed data streams
In various examples, metadata may be generated corresponding to compressed data streams that are compressed according to serial compression algorithms—such as arithmetic encoding, entropy encoding, etc.—in order to allow for parallel decompression of the compressed data. As a result, modification to the compressed data stream itself may not be required, and bandwidth and storage requirements of the system may be minimally impacted. In addition, by parallelizing the decompression, the system may benefit from faster decompression times while also reducing or entirely removing the adoption cycle for systems using the metadata for parallel decompression. |
| US11405048B2 |
Sigma delta modulator device and sigma delta modulation method
A sigma delta modulator device includes a sampling circuit, a digital to analog converter circuit, an integrator circuit, and an analog to digital converter circuit. The sampling circuit is configured to sample an input signal, in order to generate a first signal. The digital to analog converter circuit is configured to convert a first digital signal to be a combination of a first reference voltage and a common mode voltage, in order to generate a second signal, in which the first reference voltage is one of a positive reference voltage and a negative reference voltage. The integrator circuit is configured to perform integration according to the first signal and the second signal, in order to generate a third signal. The analog to digital converter circuit is configured to quantize the third signal to generate an output signal, and to generate the first digital signal according to the output signal. |
| US11405047B2 |
Sampling switch circuits
A sampling switch circuit, comprising: an input node, connected to receive an input voltage signal to be sampled; a sampling transistor comprising a gate terminal, a source terminal and a drain terminal, the source terminal connected to the input node; a potential divider circuit connected to the input node and a track-control node to provide a track-control voltage signal dependent on the input voltage signal at the track-control node; a hold-control node connected to receive a hold-control voltage signal; an output node connected to the drain terminal of the sampling transistor; and switching circuitry configured to connect the gate terminal of the sampling transistor to the track-control node or to the hold-control node in dependence upon a clock signal. |
| US11405046B2 |
Low-noise switched-capacitor circuit
Herein disclosed are multiple embodiments of a signal-processing circuit that may be utilized in various circuits, including conversion circuitry. The signal-processing circuit may receive an input and produce charges on multiple different capacitors during different phases of operation based on the input. The charges stored on two or more of the multiple different capacitors may be utilized for producing an output of the signal-processing circuit, such as by combing the charges stored on two or more of the multiple different capacitors. Utilizing the charges on the multiple different capacitors may provide for a high level of accuracy and robustness to variations of environmental factors, and/or a low noise level and power consumption when producing the output. |
| US11405043B1 |
Phase calibration with half-rate clock for injection-locking oscillators
A clock generation circuit has an injection-locked oscillator, a frequency doubler circuit, low pass filters and a calibration circuit. The injection-locked oscillator has an input coupled to a half-rate clock signal. The frequency doubler circuit has inputs coupled to outputs of the injection-locked oscillator. Each of the low pass filters has an input coupled to one of a plurality of outputs of the frequency doubler circuit. The calibration circuit includes comparison logic that receives outputs of the low pass filters. The calibration circuit has an output coupled to a control input of a source of a supply current in the injection-locked oscillator. In one example, the source of the supply current is a current digital to analog converter. |
| US11405042B2 |
Transceiver carrier frequency tuning
In described examples, a method of operating a transceiver with a transmitter and a receiver includes generating a frequency reference. In the transmitter: A phase locked loop (PLL) generates a first voltage controlled oscillator (VCO) control voltage responsive to the frequency reference. A VCO in the transmitter generates a transmitter VCO signal responsive to the first VCO control voltage, and the PLL is locked to the transmitter VCO signal. In the receiver: A signal is received. A receiver VCO generates a receiver VCO signal responsive to the first or a second VCO control voltage. The receiver VCO signal is multiplied by the received signal to generate an I component, and by the received signal phase shifted by 90° to generate a Q component. The second VCO control signal is generated responsive to the I component and the Q component. |
| US11405041B2 |
Programmable frequency DLL
A DLL circuit that has a programmable output frequency is provided. In various embodiments, the DLL circuit comprises an input configured to receive an input clock defining an input clock period; an output configured to provide a DLL output clock; a delay line configured to receive the input clock, wherein the delay line comprises a plurality of delay stages, each configured to generate one of a plurality of delay line output clocks, each of the delay line output clocks having a phase relative to the input clock based on a delay of the delay line; a clock generation circuit, configured to generate the DLL output clock based on a selected plurality of the delay line output clocks; and a control circuit configured to select which of the delay line output clocks the clock generation circuit uses to generate the DLL output clock. |
| US11405040B2 |
Logic configuration techniques
Various implementations described herein are directed to a device having logic circuitry with multiple inversion stages. One or more of the multiple inversion stages may be configured to operate as first inversion logic with a first number of transistors. One or more of the multiple inversion stages may be configured to operate as second inversion logic with a second number of transistors that is greater than the first number of transistors. |
| US11405036B2 |
Proximity sensor and door handle device including the same
A proximity sensor including a first substrate, a second substrate, a first connecting member, at least one first electrode, and a detection part. The first substrate is disposed in the vicinity of a first detection space. The second substrate is disposed on an opposite side of the first substrate to the first detection space. The second substrate faces the first substrate. The first connecting member connects the first substrate and the second substrate. The at least one first electrode is provided on the first substrate and configured such that a signal from the at least one first electrode changes in response to a change in a first capacitance caused by a detection target approaching to the first detection space. The detection part is provided on the second substrate and configured to detect the approach of the detection target based on the signal from the at least one first electrode. |
| US11405034B1 |
Body resistor bypass for RF FET switch stack
A FET switch stack and a method to operate a FET switch stack. The FET switch stack includes a stacked arrangement of body bypass FET switches connected across respective common body resistors. The body bypass FET switches bypass the respective common body resistors during the OFF steady state of the FET switch stack and do not bypass the respective common body resistors during the ON steady state. |
| US11405033B2 |
Methods, apparatus, and systems to drive a transistor
Methods, apparatus, and systems are disclosed to drive a transistor. An example apparatus includes a regulator including a first input terminal adapted to be coupled to a control terminal of a transistor, a first output terminal, and a second output terminal, a first stage including a first input terminal coupled to the first output terminal of the regulator and an output terminal adapted to be coupled to the control terminal of the transistor, and a second stage including an input terminal coupled to the second output terminal of the regulator, and an output terminal adapted to be coupled to the control terminal of the transistor. |
| US11405031B1 |
Gate resistor bypass for RF FET switch stack
A common gate resistor bypass arrangement for a stacked arrangement of FET switches, the arrangement including a series combination of an nMOS transistor and a pMOS transistor connected across a common gate resistor. During at least a transition portion of the transition state of the stacked arrangement of FET switches, the nMOS transistor and the pMOS transistor are both in an ON state and bypass the common gate resistor. On the other hand, during at least a steady state portion of the ON steady state and the OFF steady state of the stacked arrangement of FET switches, one of the nMOS transistor and the pMOS transistor is in an OFF state and the other of the nMOS transistor and the pMOS transistor is in an ON state, thus not bypassing the common gate resistor. |
| US11405029B2 |
Duty adjustment circuit, and delay locked loop circuit and semiconductor memory device including the same
A duty adjustment circuit, and a delay locked loop circuit and a semiconductor memory device including the same are provided. The duty adjustment circuit includes a pulse generator configured to generate a pulse signal at a constant pulse width regardless of a frequency of a reference clock signal, based on frequency information, a code generator configured to generate a first predetermined number of delayed pulse signals by delaying the pulse signal, as a first code in response to the pulse signal, and a duty adjuster configured to receive a delay clock signal, and generate a duty correction clock signal by adjusting a slope of rising transition and a slope of falling transition of the delay clock signal in response to the first code and a second code. |
| US11405028B1 |
Accurate peak detector
A peak detector including an input transistor, an isolation transistor, at least one load transistor, a buffer, a control transistor, a current source and at least one resistor. The isolation transistor isolates the input and load transistors from the supply voltage for power supply rejection. The buffer, control transistor, current source and resistor(s) bias the input transistor to remain in a saturation region and each load transistor to remain in a triode region. The buffer may be a unity gain buffer. The control transistor may match each load transistor with matching threshold voltages. An input bias circuit may be included to bias an input node to a direct-current voltage. The load transistor(s) may be biased to have so that the output voltage is proportional to a peak voltage of the input node. The peak detector may be configured to detect multiple inputs and may have shared circuitry. |
| US11405027B1 |
System and method for measuring delays of delay elements
In accordance with an embodiment a circuit includes: a plurality of delay elements coupled in series, each delay element including an input node and an output node; a multiplexer having inputs coupled to the output node of each delay element of the plurality of delay elements; and a time measurement circuit including a time amplifier having an input coupled to an output of the multiplexer, and a counter coupled to an output of the time amplifier. |
| US11405017B2 |
Acoustic matrix filters and radios using acoustic matrix filters
There are disclosed acoustic filters and radios incorporating the acoustic filters. A filter includes a first filter port, a second filter port, and n sub-filters, where n is an integer greater than one. Each sub-filter has a first sub-filter port connected to the first filter port and a second sub-filter port connected to the second filter port. A first acoustic resonator is connected from the first filter port to ground, and a second acoustic resonator is connected from the second filter port to ground. The first and second acoustic resonators are configured to create respective transmission zeros adjacent to a lower edge of a passband of the filter. |
| US11405011B2 |
Methods and apparatuses for selective communication between tag and reader using filter
The present disclosure relates to a method and apparatus for selective communication between a tag and a reader using a filter. According to an embodiment of the present disclosure, a communication method between a tag and a reader using a filter performed by a reader includes generating a filter based on tag information of the tag to collect data, transmitting the generated filter to the tag, and receiving data from a tag that selected through a filtering operation of the transmitted filter. |
| US11405009B2 |
RF amplifier including gain/phase compensator
Disclosed is a radio frequency (RF) amplifier having channel selectivity. The RF amplifier includes a main path including an amplifier, and a feedforward path including a gain/phase compensator, a high-pass filter, and a mixer. |
| US11405008B2 |
Switching power supply, semiconductor integrated circuit device, and differential input circuit
This switching power source 100 has: a switching output circuit 110 which drives an inductor current IL by turning on and off an upper switch 111 and a lower switch 112 and generates an output voltage VOUT from an input voltage PVDD; a lower current detection unit 210 which detects the inductor current IL flowing through the lower switch 112 during an ON-period of the lower switch 112 and acquires lower current feedback information Iinfo; an error amplifier 140 which outputs voltage feedback information Vinfo including information on an error between the output voltage VOUT (feedback voltage FB) and a reference voltage REF; an information synthesis unit 220 that generates synthesis feedback information VIinfo by synthesizing Iinfo with Vinfo; and an information holding unit 230 which samples Vinfo during the ON-period of the lower switch 112. |
| US11405006B1 |
Amplifying circuit and optical navigation device
An amplifying circuit, which can operate in one of a sample mode and a hold mode, comprising: an amplifier; a current providing circuit, configured to provide a first bias current to the amplifier in a power saving time interval when the amplifying circuit operates in the sample mode, and configured to provide a second bias current to the amplifier when the amplifying circuit operates in the hold mode; wherein the first bias current is smaller than the second bias current. |
| US11405002B2 |
Harmonic rejection mixing circuit device and receiver
The present disclosure discloses a harmonic rejection mixing circuit device and a receiver. In the harmonic rejection mixing circuit device, outputs of first and fourth mixers are combined with the input terminal of the fourth mixer being connected to a capacitor, the first mixer samples a first group of local oscillator (LO) signals, and the fourth mixer phase-invertedly samples the first group of LO signals, thus the noise introduced by a fundamental LO signal input to the first mixer may be eliminated using the double balance feature of the fourth mixer core, thereby ensuring a high signal-to-noise ratio of the receiver. Similarly, the noises introduced by fundamental LO signals input to second and third mixers may be eliminated respectively using the double balance features of the fifth and sixth mixer cores, thereby lowering the noise figure to ensure a high signal-to-noise ratio of the receiver. |
| US11404997B2 |
Photovoltaic shingles and methods of installing same
A system includes a plurality of photovoltaic shingles installed on a roof deck, each of the shingles having a first layer including a head lap portion, and a second layer including at least one solar cell. A first photovoltaic shingle overlays at least a part of the head lap portion of a second photovoltaic shingle. The system includes at least one wireway installed proximate to a first end of at least the first photovoltaic shingle. |
| US11404993B2 |
Motor drive system and robot
A motor drive system includes a motor, a drive control circuit controlling driving of the motor, a power supply device having a first power supply coupled to a reference potential and a second power supply series-coupled to the first power supply, and supplying a second voltage as a sum value of a first voltage as an output voltage of the first power supply and an output voltage of the second power supply to the drive control circuit, and a monitoring circuit detecting the first voltage and the second voltage and shutting off or reducing electric power supply to the drive control circuit when the detected first voltage becomes a predetermined first set value or more or the detected second voltage becomes a predetermined second set value or more, wherein electric power for driving is supplied to the monitoring circuit from between the first power supply and the second power supply. |
| US11404987B2 |
Motor and driving device using same
The present application discloses a linear motor having a housing with an accommodation space, stoppers fixed on the housing and set at intervals, a vibrator sliding between the stoppers and a power coil driving the vibrator to reciprocate motion. The stopper includes a first iron core fixed on the housing and an auxiliary coil twinned on the first iron core. The motor also includes a positioning sensor used to sense the motion of the vibrator to obtain a feedback signal. According to the feedback signal detected by the positioning sensor, the auxiliary coil and/or the power coil act on the vibrator so as to adjust the reciprocating motion of the vibrator between the stoppers. The effect of the motion of the plan of present application is good and control precision is high. |
| US11404986B2 |
Torque control based on rotor resistance modeling in induction motors
A control system for an induction motor executes an on-board, dynamic model to estimate rotor resistance and control the torque output by the induction motor. The model includes equations to calculate stator and rotor temperatures and/or resistances based on combinations of voltage and current data, electrical frequency, rotor speed, switching patterns, and air flow rates during operation of the induction motor. The control system updates the model based on feedback collected during the operation of the induction motor, including the difference between the actual observed stator temperature and the stator temperature predicted by the model. The model is updated to converge the predicted stator temperature on the actual observed stator temperature, and corresponding updates are made to the rotor resistance estimations to provide more accurate estimations of the rotor resistance and improve the accuracy of the induction motor torque output. |
| US11404981B2 |
Motor controller
The present disclosure provides a motor controller which can effectively stop a motor at a specific position in a short period of time, and can achieve an orientation operation quickly. A motor controller is configured to stop a rotary shaft, and includes: a first time period calculator that calculates a target stop position and an acceleration at a time of positioning, a first time period that is to be taken by the rotary shaft to stop at the target stop position; a second time period calculation unit that calculates the target stop position and the acceleration at the time of positioning, a second time period that is to be taken by the rotary shaft to stop at the target stop position; a comparison unit that compares the first time period with the second period; and an orientated stop control unit that controls and stops the motor. |
| US11404978B2 |
Braking circuit and paper lifting device
A breaking circuit applied to a motor comprises an actuator, an anti-reverse component and a limiting resistor. The actuator comprises a first electricity transmission terminal, a second electricity transmission terminal and a controlled terminal, with the controlled terminal configured to be connected with a power supply port, and the first electricity transmission terminal configured to be electrically connected with a power input terminal of the motor. The anti-reverse component is electrically connected between the controlled terminal and the first electricity transmission terminal of the actuator. The limiting resistor is electrically and serially connected with the first electricity transmission terminal or the second electricity transmission terminal of the actuator. When power supplied from the power supply port to the power input terminal is stopped, the actuator is conducted to form a discharge path from the power input terminal through the limiting resistor to a low electric potential end. |
| US11404976B2 |
Dielectric nano-fluid for electrostatic machines and actuators
An electrostatic machine employs a high dielectric fluid comprised of a dielectric liquid with suspended dielectric particles. Electrorheological effects are minimized through small particle sizes and steric coatings on those particles limiting the minimum particle-to-particle distance. Low particle volume densities provide greater torque density with managed reduced viscosity. |
| US11404973B2 |
Generalized equivalent circuit model of MMC-HVDC for power system simulation
A method to simulate a circuit includes receiving at least one circuit requirement and at least one Modular Multilevel Converter (MMC) parameter; determining an operating mode and switching states of an arm circuit; determining each capacitor current based on the switching states and an arm current; determining capacitor voltage and arm voltage; and generating an equivalent circuit model to simulate MMC-based HVDC systems and DC grids in a hybrid AC and DC power system. |
| US11404971B2 |
Converter for converting an electromagnetic wave in a continuous electric current
The present invention relates to a converter for converting an electromagnetic wave in a continuous electric current.Particularly, said converter comprises at least one antenna and at least one rectifier for transforming said alternating electric current in a continuous electric current, where said at least one rectifier is connected in series to said antenna.In particular, said antenna is configured to pick up an electromagnetic wave and resonate at the frequency of said electromagnetic wave, so as to generate an alternating electric current having a frequency equal to the frequency of said electromagnetic wave and said rectifier comprises a quantum diode for rectifying at high speed said alternating electric current. |
| US11404969B2 |
Inverter system
An inverter system is provided, by which the magnitudes of currents flowing through inverter modules are substantially equal. The inverter system includes multiple inverter modules connected in parallel, where input terminals of all the multiple inverter modules are connected to a same direct current input bus, and output terminals of all the multiple inverter modules are connected to a same alternating current output bus. An input contact S1 of the direct current input bus and an output contact S2 of the alternating current output bus are such located that a difference between impedances of any two branches between S1 and S2 does not exceed a preset value. |
| US11404967B2 |
Interleaved converters with integrated magnetics
Three-phase interleaved LLC and CLLC resonant converters, with integrated magnetics, are described. In various examples, the primary sides of the phases in the converters rely upon a half-bridge configuration and include resonant networks coupled to each other in delta-connected or common Y-node configurations. The secondary sides of the phases can rely upon a full-bridge configurations and are coupled in parallel. In one example, the transformers of the phases in the converters are integrated into one magnetic core. By changing the interleaving structure between the primary and secondary windings in the transformers, resonant inductors of the phases can also be integrated into the same magnetic core. A multi-layer PCB can be used as the windings for the integrated magnetics. |
| US11404966B2 |
Isolated multi-phase DC/DC converter with reduced quantity of blocking capacitors
The present disclosure provides an isolated multi-phase DC/DC converter with a reduced quantity of blocking capacitors. In one aspect, the converter includes a multi-phase transformer having a primary circuit and a secondary circuit magnetically coupled to the primary circuit, the primary circuit having a first quantity of terminals, and the secondary circuit having a second quantity of terminals; a third quantity of blocking capacitors, each being electrically connected in series to a respective one of the terminals of the primary circuit; and a fourth quantity of blocking capacitors, each being electrically connected in series to a respective one of the terminals of the secondary circuit. The third quantity is one less than the first quantity. The fourth quantity is one less than the second quantity. |
| US11404964B2 |
Rectifier circuit and power supply unit
A transient current in a rectifier circuit is effectively reduced. In the rectifier circuit, a current flows from a power supply to a coil when a transistor is turned ON. When the transistor is turned OFF, the current of the coil flows into a second rectifier. |
| US11404963B2 |
Electronic circuit with minimized variation in output voltage of DC-DC converter, control system with electronic circuit and method for controlling electronic circuit
An electronic circuit to which DC power is supplied, by a DC-DC converter is provided. The electronic circuit includes at least one PLL circuit configured to synchronize a phase of an output signal of the PLL circuit with a phase of a clock signa; at least one logic circuit configured to operate according to the output signal; and a control circuit configured to output a control signal for switching an operation mode of the DC-DC converter from a PFM mode to a PWM mode, upon detecting that the clock signal is input to the PLL circuit. |
| US11404958B2 |
Random code generator and associated random code generating method
A random code generator includes a power source, a sensing circuit, a first memory cell and a second memory cell. A first terminal of the first memory cell is connected with the power source. A second terminal of the first memory cell is connected with the sensing circuit. A first terminal of the second memory cell is connected with the power source. A second terminal of the second memory cell is connected with the sensing circuit. The power source provides a supplying voltage to both the first memory cell and the second memory cell during an enrollment. A random code is then determined according to the resistance difference between the first memory cell and the second memory cell after the enrollment. |
| US11404955B2 |
Method for controlling fault using switching technique of three phase four wire interlinking converter
A method for controlling a fault of a three phase four wire interlinking converter system according to one embodiment of the present disclosure comprises obtaining a first d-q-o coordinate plane based on an internal phase angle of output voltage produced from each phase of an inverter; converting the first d-q-o coordinate plane to a second d-q-o coordinate plane based on the o-axis configured differently from the first d-q-o coordinate plane; obtaining an output voltage vector for determining a fault location by performing d-q transform on the second d-q-o coordinate plane; determining occurrence of a fault and an area related to the fault based on the output voltage vector; and in the occurrence of the fault, allocating a zero voltage vector to the area related to the fault. |
| US11404954B2 |
Pulse width modulation interleaving
A pulse width modulation (PWM) interleaving system is provided. The PWM interleaving system includes active harmonic filters (AHFs). The AHFs are disposed in parallel with each other and with a load. The AHFs are electrically coupled to a common coupling point that is electrically interposed between a grid and the load. The AHFs are configured to affect, by PWM, a characteristic of current flowing between the grid and the load. The PWM interleaving system further includes a controller operably coupled to the AHFs and configured to synchronize the PWMs of the AHFs to thereby cancel ripple currents propagating towards the grid. |
| US11404951B2 |
Power converter and related system
Embodiments of the present disclosure disclose a power converter and a related system. The power converter includes a controller and a power conversion circuit. The power conversion circuit is configured to convert an input power of an input power supply into an output power of a load, where the input power supply is an external power supply connected to the power converter. The controller is configured to control on/off of the first switch element, to implement connection/disconnection between the input power supply and the inductive element; and control the unidirectional conduction circuit to be turned on before the first switch element is turned on in the power conversion cycle. |
| US11404945B2 |
Stator assembly method and stator assembly apparatus
A stator assembly method of assembling a stator that includes a stator core that includes a slot that has an opening that opens on one side in a radial direction, a coil that includes a slot-housed portion housed in the slot, and insulation disposed between the slot and the slot-housed portion, the method including disposing the insulation in the slot; opening a portion of the insulation on the one side in the radial direction by inserting a first guide jig into the insulation, which is disposed in the slot, along a center axis direction of the stator core, after disposing the insulation; and inserting the slot-housed portion into the slot via the opening by moving the coil and the first guide jig together toward the other side in the radial direction with respect to the stator core, after opening the portion of the insulation. |
| US11404944B2 |
Method for manufacturing MSO coil and device for manufacturing same
Disclosed is a method for manufacturing an MSO coil, comprising: a pressing step of forming a bent surface on a part of a unit coil layer, which has a ring shape such that both ends thereof face each other, thereby endowing both ends of the unit coil layer with a height difference; a fixing step of connecting and fixing a plurality of unit coil layers to each other, each unit coil layer having the bent surface formed thereon, such that the first end of both ends of a unit coil layer having the bent surface formed thereon contacts the second end of both ends of another unit coil layer having the bent surface formed thereon; and a bonding step of bonding connection parts defined by contact of the first and second ends of each of the plurality of unit coil layers that are connected and fixed to each other. |
| US11404940B2 |
Brushless direct current motor
A brushless DC motor, including a base, an insulation seat, a rotor assembly, a revolving shaft, a stator assembly, a control panel, a Hall circuit board, and an end cover. The revolving shaft is connected to the rotor assembly. The rotor assembly includes a housing and a plurality of magnetic tiles. The housing includes an inner wall and a cavity defined by the inner wall. The plurality of magnetic tiles is disposed on the inner wall. The stator assembly is disposed in the cavity. The base includes a cylindrical sleeve extending from a center of the base to the cavity of the rotor assembly. The stator assembly is connected to the cylindrical sleeve; two ends of the cylindrical sleeve are provided with a first bearing and a second bearing, respectively; and two ends of the revolving shaft are supported by the first bearing and the second bearing, respectively. |
| US11404930B2 |
Insulator, and stator and motor comprising same
An insulator includes a part to be wound with a coil, a first flange, and a second flange. The first flange is formed at the side of the part closer to a core segment, and includes a coil guide groove that guides the coil to the part. The second flange is formed at the side closer to a distal end of a tooth. The coil guide groove includes a first groove extending at an acute angle θ from an inner surface of the first flange. |
| US11404927B2 |
Stator
The present invention relates to a stator. In a stator winding arrangement structure of a drive motor in which hairpin segments in a shape of a hairpin, each having two legs, are inserted into a stator core having a plurality of slots, and legs of the hairpin segments positioned opposite to the stator core are bent and joined to circuitry-form a serial coil bundle, a stator winding of the drive motor is composed of three or more phases and each of the phases consists of two or more successively adjacent slots. An arrangement structure of hairpin segments mounted in the stator core having a plurality of slots of a hairpin drive motor according to the present invention is modified to form a parallel circuit, and a coil extending over the same outermost layer is removed. In addition, structural stability and production yield of the hairpin segments may be improved. |
| US11404923B2 |
Electric motor and stator assembly
A stator assembly has a motor housing of a cylindrical shape and a stator fixed to an inner peripheral wall of the motor housing by a shrink fitting process. A stator core of the stator includes a projecting portion in contact with the motor housing and a stopper portion, which is smaller than the projecting portion in a radial direction. The stopper portion is in contact with the motor housing in an actual-use temperature range. The projecting portions and the stopper portions are alternately arranged in a circumferential direction in a cyclic manner. A cycle unit is composed of one or more than one projecting portion and one or more than one stopper portion. Multiple stator core sheets are built up in such a way that the cycle units are alternately arranged in an axial direction and neighboring stator core sheets are displaced in the circumferential direction by a predetermined shift angle. A curvature radius of the projecting portion at a position, at which the projecting portion is in contact with the motor housing, is smaller than a radius of a circumscribed circle of the projecting portion. |
| US11404916B2 |
Electronic circuit, module, and system
A convenient electronic circuit in which a switch can be switched through electric power obtained using weak radio waves is provided. An electronic circuit includes: a power supply configured to output direct current (DC) electric power; a switch which switches a connection state between the power supply and a load; a first power conversion circuit which converts electric power obtained using first radio waves received by a first antenna capable of receiving the first radio waves in a first direction into DC electric power and which outputs the converted DC electric power from a first DC power output terminal; a second power conversion circuit which converts electric power obtained using second radio waves received by a second antenna capable of receiving the second radio waves in a second direction different from the first direction into DC electric power and outputs the converted DC electric power from a second DC power output terminal; and a control circuit which controls a connection state of the switch such that it is in a conduction state when the first power conversion circuit outputs DC electric power due to the reception of the first radio waves by the first antenna and controls the connection state of the switch such that it is in a non-conduction state when the second power conversion circuit outputs DC electric power due to the reception of the second radio waves by the second antenna. |
| US11404914B2 |
Wireless power transmitters and associated base stations for through-structure charging
A power transmitter for wireless power transfer at an operating frequency selected from a range of about 87 kilohertz (kHz) to about 360 kHz is disclosed. The power transmitter includes a control and communications unit and an inverter circuit configured to receive input power and convert the input power to a power signal. The power transmitter further includes a coil configured to transmit the power signal to a power receiver, the coil formed of wound Litz wire and including at least one layer. The power transmitter further includes a shielding comprising a magnetic backing and a magnetic wall, the magnetic wall and magnetic backing defining a cavity, the magnetic wall including a top surface, the cavity extending, at least, from the magnetic backing to the coil, the coil positioned proximate to the top surface. |
| US11404913B2 |
Induction charging for a portable electronic device with a grip attachment
Induction charging devices and methods are disclosed for a portable electronic device that has a reception coil coupled to a power source and an outwardly projecting attachment mounted thereon. In some versions, the devices include a housing having a wall with an outwardly facing charging surface and a recess sized to receive the attachment with the portable electronic device disposed on the charging surface. In some versions, devices can include an attachment device coupled to a rear of a housing that can releasably secure to a portion of a vehicle and a mount coupled to a front of the housing configured to receive a portion of the attachment therein to secure the portable electronic device to the housing. A charging assembly within the housing can include a transmission coil disposed so that with the recess or mount receiving the attachment therein, the transmission and reception coils are sufficiently aligned to charge the power source of the portable electronic device. |
| US11404907B2 |
Distributed voltage control for power networks
Systems, methods, techniques and apparatuses of power network control are disclosed. One exemplary embodiment is a power network comprising a plurality of zones each including a plurality of measurement devices structured to measure electrical characteristics of the corresponding zone, a zone controller structured to receive measurements from the plurality of measurement devices, a distributed energy resource (DER), and a load. Each zone controller is structured to receive a set of local measurements from the plurality of measurement devices of the corresponding zone, calculate a sensitivity matrix using the received set of local measurements, determine whether a voltage violation has occurred in the corresponding zone, determine a DER set point using the received set of local measurements in response to determining the voltage violation has occurred in the corresponding zone, and transmit the DER set point to the DER. |
| US11404905B2 |
Self configuring modular electrical system
This matrix-like power/communications system is a decentralized array of scalable self-configuring modular electrical components that are easily physically and electrically replaceable and combinable into any series, parallel or bypassed state with any power supply and bi-directional data communications input; resulting in an autonomous system survivable in the harshest environments including physical shock, vibration, vacuum, radiation, thermal, and electromagnetic interference; and provides a communication interface for external control or monitoring, simultaneously being capable of reconfiguring itself if an internal battery cell failure occurs by switching in a spare cell(s) to replace a dead cell within the system for maintaining uninterrupted power and communications during the upset event, while being capable of reconfiguring itself autonomously into an arrangement of series/parallel states for charge/discharge while enabling cell balancing and continual monitoring of all individual cell parameters, and only using two wires for all component interconnection. |
| US11404903B2 |
Lighting system including a power backup device
A system may include a light source. A converter may be configured to convert an AC voltage to a DC operating voltage during normal operation. A power backup device may be coupled to the converter. A current source may have a first terminal configured to receive the DC operating voltage during regular operation and a second terminal configured to provide a pulse-width modulated (PWM) signal to an anode end of the light source. A switching device may have a first connecting terminal coupled to the anode end of the light source, a second connecting terminal coupled to the power backup device, and a control terminal coupled to the converter. The switching device may be configured to open a switch between the first connecting terminal and the second connecting terminal during normal operation and close the switch upon detecting an interruption of the DC operating voltage at the control terminal. |
| US11404902B2 |
Converter assembly
A converter assembly including a source connection system including a primary source connection, and a plurality of secondary source connections, a load connection system including a load connection, a secondary source bus bar system, a switch system including a plurality of switch units each connected electrically between a corresponding secondary source connection and the secondary source bus bar system, and at least one converter module including a DC link and a secondary source side converter. Each switch unit of the switch system includes a first switch and a second switch connected in parallel, wherein the first switch has a higher switching speed than the second switch, and the second switch has a lower conduction losses than the first switch. |
| US11404900B2 |
Power supply device and method for providing power supply device
A power supply device includes a combination of one power supply module of a plurality of power supply modules having different power supply performances and one controller of a plurality of controllers having different functions, which are selectively combined. Each of the plurality of power supply modules includes a power supply module side connection portion common to the plurality of power supply modules, and each of the plurality of controllers includes a controller side connection portion common to the plurality of controllers and connectable to the power supply module side connection portion, to allow the one power supply module and the one controller are selectively combined. |
| US11404896B2 |
Method and device for charging lithium ion battery
A method for charging a lithium ion battery includes: acquiring a polarization attribute of the lithium ion battery, the polarization attribute including a maximum charging current under which no lithium plating occurs at an anode of the lithium ion battery; determining, according to the polarization attribute, multiple sections of constant charging currents which have current values decreasing sequentially in a sectional charging sequence; charging the lithium ion battery in sections with the multiple sections of constant charging currents respectively, and after charging in each section, leaving the lithium ion battery standing or discharging the lithium ion battery with a preset discharging current less than the maximum charging current; and performing constant-voltage charging with taking a constant-current cut-off voltage as a constant voltage when a voltage of the lithium ion battery reaches the constant-current cut-off voltage. |
| US11404890B1 |
Storage case and charging device for VR equipment
The present disclosure provides a storage case and charging device. The storage case and charging device for a VR equipment includes a lower housing having an accommodation groove for accommodating the VR equipment; an upper housing covering the accommodation groove and detachably connected with the lower housing; a battery disposed in the lower housing; and a first charging plug disposed in the accommodation groove and electrically connected to the battery. The first charging plug is configured for inserting into and electrically connecting to a first charging port of the VR equipment for charging the VR equipment. |
| US11404883B2 |
Charging apparatus, charging program, and charging method
A charging apparatus, a charging method, and the like that can prevent deterioration in a battery by appropriate current adjustment and shorten charging time are provided. A charging apparatus (1) performs charging of a battery (31) with a constant current until a voltage of the battery (31) reaches a predetermined voltage and, after the predetermined voltage is achieved, performs charging of the battery (31) while controlling the current so as to keep the voltage constant. A deterioration measuring unit (31) detects a deterioration condition in the battery (31). A current and voltage adjusting unit (11) specifies an additional current in accordance with the deterioration condition. A power supplying unit (12) supplies the additional current to the battery (31) in addition to the constant current. Such a deterioration condition is specified by a voltage difference or a temperature difference detected by supplying a single amount of current for a certain period. |
| US11404873B2 |
Power system operation assisting device and method, and oscillation suppression system
This power system operation assisting device is provided with: a multiple signal frequency specifying unit that uses, as inputs, measured data of an object to be measured and a frequency specifying parameter for calculating a frequency component of the measured data to calculate an oscillation frequency; a generation source candidate calculation unit that uses, as an input, the calculated oscillation frequency to calculate a generation source candidate of an unstable oscillation occurring in a power system; a generation source guarantee test unit that calculates the guarantee test result of the generation source candidate; and a display unit that displays the oscillation frequency, the generation source candidate, and the guarantee test result. |
| US11404872B2 |
Airport electric vehicle charging system
In an embodiment, an airport electric vehicle charging system includes a current transducer electrically coupled with a power source; a solid state converter electrically coupleable with an aircraft at or near an airport gate and configured to provide and maintain power to the aircraft; and a controller. The system further includes a first feedback loop between the controller and the current transducer; a second feedback loop between the controller and the solid state converter; and a battery charger electrically coupled with the power source and configured to charge one or more electric vehicles. The first feedback loop provides a first feedback signal generated by the current transducer to the controller. The second feedback loop provides a second feedback signal generated by the solid state converter to the controller. The battery charger is configured to consume power from the power source in accordance with the first and second feedback signals. |
| US11404869B2 |
Apparatus for distributing DC bus power and control power over common conductors in a distributed DC bus system
A system for distributing DC bus voltage and control power to multiple motors includes a rectifier front end supplying a DC bus voltage and a DC control voltage. Both the DC bus voltage and the DC, control voltage are distributed via a common set of conductors. Diodes are operatively connected between the DC control voltage and the common set of conductors. The diodes allow forward conduction of the DC control voltage and distribution of control power to distributed devices when the DC bus voltage is not present. Once the DC bus voltage is present, the diodes block conduction of the DC control voltage. Each of the distributed devices are configured with an internal power supply that is operative to generate an internal control voltage from either the DC control voltage or the DC bus voltage. |
| US11404864B2 |
Wireless power receiving device and control method thereof
An electronic device acting as a power receiving device and a control method. The electronic device includes a battery, a coil, a reception circuit electrically connected to the coil, a charger a current sensing circuit, and at least one control circuit. The charger supplies a specified voltage to a system and controls the state of charge of the battery by using the voltage supplied from the reception circuit. The current sensing circuit is configured to sense an inrush current caused by the system. The at least one control circuit is configured to transmit a first control signal for requesting to increase a transmission voltage supplied from an external electronic device when an inrush current is detected through the current sensing circuit. |
| US11404863B2 |
Power supplies with limited power protection and relevant control methods
A power supply is configured to limit its output power, converting an input voltage on a primary side into a bus voltage on a secondary side. A current-sense resistor detects a bus current output from the power supply to provide a current-sense signal. A bus switch is electrically connected to a secondary winding on the secondary side, configured to selectively supply power to the bus voltage. A power delivery controller controls the bus switch in response to the current-sense signal and a power detection signal on the secondary side. The power delivery controller provides a power threshold in response to the bus voltage, compares the power detection signal with the power threshold, and turns off the bus switch to stop supplying power to the bus voltage if the power detection signal exceeds the power threshold, thereby limiting the output power of the power supply. |
| US11404862B2 |
Method, control unit, and electrical network
A method is described for operating an electrical system, in particular, of a motor vehicle, which includes at least one electrical consumer, at least one energy source for electrical energy, and at least one control unit, the consumer being test activated by the control unit for the purpose of initializing a start of the system and a voltage level of an electrical voltage in the system being monitored and compared to a predefinable minimum value, and the activation being interrupted if the voltage level falls below the minimum value, and the consumer being subsequently test reactivated. It is provided that the number of the interruptions is counted and the consumer is deactivated at least for a predefinable period of time upon reaching a predefinable maximum number. |
| US11404860B2 |
Detection of a protective conductor failure by means of an active shield
Method for detecting a protective conductor failure inside a cable including a plurality of conductors, in which at least one conductor has a shield and this shield is respectively connected to a potential at a first end and at a second end of the cable, wherein, in order to drive its potential to a predefined potential value, the shield is actively electrically supplied at at least one end of the cable. In this case, the cable may be a charging cable which is connected, by the first end, to a charging pole and is connected, by the second end, to a battery configured to be installed in an electric vehicle, and the shield is actively supplied at the first end of the cable which is connected to the charging pole. |
| US11404859B2 |
Method and apparatus for introducing a cable into a conduit
An apparatus (10 which is to be inserted into a longitudinally extending conduit includes at least one longitudinally extending compartment (11) formed by attached the ends of a sheet of material (12) together. Another sheet of material (15) has one end attached to the compartment (11) and has compatible fastening elements (16, 17) on its opposed ends. A cable (19) may be positioned adjacent to the sheet of material (15) and it is folded around the cable (19) to form an additional compartment (18). The apparatus (10) may then be inserted into a conduit. |
| US11404856B2 |
Cable termination and method of manufacture
A cable termination includes a cable end of a cable having a protective outer jacket and an overmolded sealant. The cable termination is manufactured using a method having the steps of providing a cable end of a cable having a protective outer jacket, preparing the protective outer jacket of the cable end such as to promote adhesion with a sealant, and overmolding the cable end with a sealant. |
| US11404855B2 |
Method of connecting a first cable to a second cable, cable arrangement, and cable connection device for connecting a first cable to a second cable
A method for connecting a first cable to a second cable with an adhesive tape to form a cable chain includes: arranging a free end region of the first cable parallel to and spaced from a first end region of the second cable; providing the adhesive tape folded in its longitudinal direction to form opening tabs at its first and opposite second ends with an adhesively coated side of the adhesive tape partially adhering to itself; and enclosing a part of the first cable free end region and a part of the second cable first end region with the adhesive tape such that the first cable free end region has a greater distance from the first adhesive tape end and the second adhesive tape end than the second cable first end region and is detachably connected to the second cable first end region. |
| US11404852B2 |
Power distribution units for equipment
In one or more embodiments, a power distribution unit may include: multiple power distribution module (PDM) receptacles, in which each PDM receptacle is configured to receive a PDM along a longitudinal axis of the PDM receptacle and is configured with multiple conductors disposed along a plane orthogonal to the longitudinal axis; first multiple power outlets coupled to a first PDM receptacle of the multiple PDM receptacles, in which the first multiple power outlets are configured to provide first single-phase power to first multiple information handling systems housed by a rack; and second multiple power outlets coupled to a second PDM receptacle of the multiple PDM receptacles, in which the second multiple power outlets are configured to provide second single-phase power to second multiple information handling systems housed by the rack. In one or more embodiments, a monitoring device of the power distribution unit may monitor one or more environmental attributes. |
| US11404851B2 |
Building automation device which can be recessed in an electrical box
The invention relates to a building automation device which can be recessed in an electrical box, which adapts to the various communication requirements, which comprises a communication module with a communication bus, an application module which implements the functionality of the device, and a bus connector between the two modules, in which said bus connector serves to supply and transfer data, the communication module comprises a first base, the application module comprises a second base, during use, second side faces of the second base are inserted into a first opening of the first base, and the first base is joined to the second base via first attachment means. |
| US11404850B2 |
Dual grating-coupled lasers
In an example embodiment, a system includes a first grating-coupled laser (GCL) that includes a first laser cavity optically coupled to a first transmit grating coupler configured to redirect horizontally-propagating first light, received from the first laser cavity, vertically downward and out of the first GCL. The system also includes a second GCL that includes a second laser cavity optically coupled to a second transmit grating coupler configured to transmit second light vertically downward and out of the second GCL. The system also includes a photonic integrated circuit (PIC) that includes a first receive grating coupler optically coupled to a first waveguide and configured to receive the first light and couple the first light into the first waveguide. The PIC also includes a second receive grating coupler optically coupled to a second waveguide and configured to receive the second light and couple the second light into the second waveguide. |
| US11404847B2 |
Optical member, laser module including said optical member, and laser device
The present disclosure provides an optical member for use in a laser module that includes a surface emitting laser, the optical member being capable of detecting damage (cracking, peeling, and the like), a method for manufacturing the optical member, a laser module including the optical member, and a laser device. |
| US11404846B2 |
Laser device
A laser device (1) includes: a branch waveguide (23) configured to split light propagating from an optical amplifier (10) into a plurality of light beams and output the plurality of light beams; a multi-core waveguide (27) including a plurality of waveguide cores (24 to 26) configured to carry the plurality of light beams input from the branch waveguide (23); and a light reflector (31) optically coupled to a light input/output end of the multi-core waveguide (27). The waveguide cores (24 to 26) are configured to extend along the same direction, and placed in proximity to one another to enable optical coupling between adjacent waveguide cores of the waveguide cores (24 to 26). |
| US11404843B2 |
Light emission device
A light emission device includes: a base part; one or more semiconductor laser devices disposed on an upper surface of the base part; a frame body having a flat region that is above the lower surface of the base part and outside a region in which the one or more semiconductor laser devices are disposed, the frame body having a throughhole that extends from an upper surface to a lower surface of the flat region; an electrical conduction member disposed on a lower surface side of the flat region, the electrical conduction member including on an upper surface thereof a first conductive region and an insulative region, such that the first conductive region and the insulative region are located in a region defined by the throughhole of the frame body in a top plan view; and wiring having an end that is bonded to the first conductive region. |
| US11404838B2 |
Preformed solder-in-pin system
A method for inserting preformed solder members into connector pins for use with electrical connectors. The method generally includes a connector pin having an open cavity at one end, into which a preformed solder member can be first inserted and then pressed, rather than melted, in place, such that voids and air spaces within the cavity are substantially eliminated. The method allows for inserting solder members in high quantities, where the preformed solder members are placed in a fixture and the fixture is placed on a shaker table, so that solder members can be inserted into large numbers of connector pins that are pre-installed in connector grommets, largely simultaneously. |
| US11404837B1 |
Robust impedance controlled slip rings
A slip ring for transferring electrical signals between rotating and static elements of a device includes a rotating element, a static element, an electrical contact assembly, including a plurality of subassemblies, contacting the rotating element and static element, one subassembly including a deformable PCB, and a spring element positioned to supply an axially aligned force to a face of the PCB to facilitate electrical contact between the PCB and other electrical contacts elements on another subassembly. |
| US11404836B2 |
Perpendicular electrical connector for wiring
An electrical connector includes wiring with first and second wires. Each of the first and second wires have a conductor covered in insulation. The insulation includes webbing that interconnects the first and second wires to one another. The first and second wires have a stripped portion that exposes the conductors. A housing has first and second housing portions. The first housing portion receives the stripped portions. The second housing portion includes first and second spring features respectively configured to engage the stripped portions of the first and second wires when the first and second housing portions are secured to another in an assembled connector condition. |
| US11404834B2 |
Overhead door light power connection system
A lighting system for a door having a plurality of wheels that roll in a rail to support the door in an opened configuration and a closed configuration, the rail having an interior bounded by a pair of opposing U-shaped channels, and the system including at least one light attached to the door, a rail contact fixedly mounted in the interior of the rail, a door contact mounted on the door and electrically connectable to the at least one light, the door contact structured to move entirely within the interior of the rail and to contact the rail contact only in response to the door being in the opened configuration to convey sourced electricity to at least one light to illuminate the light in response to the door contact making electrical contact with the rail contact when the door is in the opened position. |
| US11404832B2 |
Connector assembly for electrically connecting two cables
A connector assembly for connecting a cable to an electrical component includes a plug unit and a mating plug unit, which each have an outer conductor element, an insulator element and an inner conductor element. The insulator element is disposed within the outer conductor element and includes an inner conductor channel in which the inner conductor element is disposed. The insulator element of the plug unit forms a plug profile that extends around the inner conductor channel and has at least one projection and/or depression. The insulator element of the mating plug unit forms a mating plug profile that corresponds to a negative of the plug profile. The plug unit and the mating plug unit are connectable to one another in such a way that the plug profile and the mating plug profile rest against each other, at least in some areas. |
| US11404828B2 |
Connector assembly
A connector assembly includes a connector, a circuit board having a first soldering pin and a second soldering pin electrically connected with the first soldering pin, a cable having a wire with a conductor, and an outer shield housing mounted on the circuit board and covering the connector, the cable, and the circuit board. The connector includes a shield housing, an insulation body disposed in the shield housing, and a conductive terminal held in the insulation body. The conductive terminal is soldered to the first soldering pin. The conductor is soldered to the second soldering pin. |
| US11404827B2 |
Connector locking mechanism
A connector locking mechanism includes a housing that includes an arm having a locking member for locking on one side and a working end on the other side and a CPA member, movably built in between a non-mating position and a complete mating position, having an arm pressing projection and an inclined surface. When mating, a mating connector is inserted into a mating opening, one side of the arm swivels on the leg portion as a fulcrum by the arm pressing projection to approach the mating connector, and the locking member is locked with the locking projection. When releasing mating, the CPA member is moved to the non-mating position, the inclined surface contacts the working end of the arm, the arm swivels moving away from the housing of the mating connector, and the locking member is released from the locking projection of the mating connector. |
| US11404821B2 |
First connector, second connector and electrical connector assembly
The present disclosure provides a first connector, a second connector and an electrical connector assembly. The first connector includes a connector main body, an elastic latching member and a position assurance slider. A positioning post and two locking protrusions protrude from an upper surface of the housing of the connector main body; two locking protruding portions protrude from inner sides of the two locking protrusions respectively toward each other. The elastic portion of the elastic latching member is suspended above the upper surface of the housing. The position assurance slider is positioned between the housing and the elastic latching member and can slide in a front-rear direction; during sliding of the locking portion of the position assurance slider in the front-rear direction, the locking portion cooperates with the locking protruding portion so that the elastic latching member is in a locking state or a non-locking state; when the elastic latching member is in the locking state, the tongue of the position assurance slider is positioned below the elastic portion to block the elastic portion from moving downwardly, so that prevent unlatching of the latching hook. The present disclosure is simple in structure and can realize firm locking. |
| US11404818B1 |
Wedge connector assembly with sequential shear bolts
An electrical connector assembly, including a bolt having a tapered distal end; a wedge having a top surface and a bottom surface defining a first aperture extending between and through the top and bottom surfaces, and dimensioned to receive the bolt therethrough; a shell having a top surface, a bottom surface, a first end, and a second end, the shell further defining a first and a second channels, the channels being separated by a middle portion and to receive the wedge therebetween; the shell further having a second aperture extending between the top surface to the bottom surface of the shell and dimensioned to receive the bolt therethrough, wherein the second aperture is configured to be positioned to align and pair with the first aperture when the wedge is positioned between the first and second channels. |
| US11404815B2 |
Sealed connector with triggered mating and method of using same
A scaled connector has a sealed plug and a sealed receptacle, each including a housing, support, bladder assembly, tagger assembly, and contacts coupled to the equipment. The bladder assembly includes an expandable bladder, and a seal plate earned by the expandable bladder between an expanded position about an opening in the housing and a contracted position a distance from the opening. The trigger assembly includes rod(s) extendable through the bladder and the seal plate. When the housing of the sealed receptacle is matingly connected to the housing of the sealed plug, the trigger assemblies extends through the seal plates and into triggered engagement with each oilier, a passageway through the seal plates are open, and the contacts of the sealed plug extend through the passageways and into engagement with the contact of the sealed receptacle. |
| US11404814B2 |
Stacked connector
A connector is provided with a first housing 10A and a second housing 10B to be arranged to cover a first facing surface 11A of the first housing 10A. The first housing 10A includes bearing portions 21 provided on a front end side and lock receiving portions 22 provided behind the bearing portions 21. The second housing 10B includes shaft portions 42 provided on a front end side and to be rotatably supported in the bearing portions 21, and partial locking portions 43 provided behind the shaft portions 42. The partial locking portions 43 lock the lock receiving portions 22 to temporarily hold the second housing 10B in a state inclined rearward from the shaft portions 42 away from the first facing surface 11A. |
| US11404812B2 |
Connector
A connector includes a female terminal, an insulative housing, and a cover component. The female terminal includes a mating segment, a holding segment, and a bent segment. The mating segment has a mating axial direction, the holding segment has an accommodation channel, and a wire is disposed in the accommodation channel. The accommodation channel has an accommodation-channel axial direction. The bent segment is connected to the mating segment and the holding segment. The insulative housing includes a mating accommodation channel and a holding accommodation channel, which communicate with each other. The mating segment of the female terminal is disposed in the mating accommodation channel, and the holding segment and the wire are disposed in the holding accommodation channel. The cover component is covered on the insulative housing, and has a buckling convex portion. The buckling convex portion abuts against a buckling shoulder on the insulative housing. |
| US11404811B2 |
Small form factor interposer
A short, high density interposer. The interposer has multiple contacts, with upwards and downwards-facing contact surfaces. Each of the contacts may be formed as a beam stamped from a sheet of metal. Two sheets of metal may be used in forming the interposer. A first sheet may be stamped with upwards facing contacts. A second sheet may be stamped with downwards facing contacts. Bases of the beams on the first sheet may be fused with bases of the beams on the second sheet, creating a conducting path through the interposer, with compliant contacts at each end. The joined contacts may be separated from the sheets from which they are stamped and held together with an insulative base of the interposer. Beams shaped to form contacts in the interposer may be closely spaced when stamped in a sheet of metal and may have a low height. |
| US11404802B2 |
Locking grounding clamp
A grounding clamp includes a safety lock-out which locks the operation of the clamp in the absence of a cooperating hot-stick. The lock-out employs a clutch which prevents the translation of the clamping members relative to one another until the clutch is disengaged. The cooperating hot-stick is required for the disengagement of the clutch. |
| US11404801B2 |
Connector locking wire operating mechanism capable of buffering impact on a push rod
A connector locking wire operation mechanism capable of buffering an impact on a push rod includes a body provided with a push rod rotatable along an arcuate track and a cam rotatable about a circular hole. A sector notch capable of accommodating the cam and leaving sufficient space is provided at an inner side of the push rod. The push rod and the cam are cooperatively rotatable about a common rotation axis. Both sides of the cam are in contact with the push rod and a spring plate respectively. |
| US11404795B2 |
Liquid crystal antenna and manufacturing method and driving method thereof, and communication device
A liquid crystal antenna, a manufacturing method and a driving method thereof, and a communication device are disclosed. The liquid crystal antenna includes a first substrate and a second substrate provided opposite to each other, a liquid crystal layer, a plurality of microstrip patch antenna structures and a ground electrode. The liquid crystal layer and the plurality of microstrip patch antenna structures are located between the first substrate and the second substrate; the ground electrode is located on a side of the first substrate away from the liquid crystal layer. Each of the plurality of microstrip patch antenna structures is configured to receive a voltage signal that controls deflection of liquid crystal molecules in the liquid crystal layer and to receive or transmit a microwave signal. |
| US11404794B2 |
Multi-layer, multi-steering antenna array for millimeter wave applications
Examples disclosed herein relate to a multi-layer, multi-steering (“MLMS”) antenna array for millimeter wavelength applications. The MLMS antenna array includes a superelement antenna array layer comprising a plurality of superelement subarrays, in which each superelement subarray of the plurality of superelement subarrays includes a plurality of radiating slots for radiating a transmission signal. The MLMS antenna array also includes a power division layer configured to serve as a feed to the superelement antenna array layer, in which the power division layer includes a dielectric layer interposed between a plurality of conductive layers. The MLMS antenna array also includes a top layer disposed on the superelement antenna array layer. The top layer may include a superstrate or a metamaterial antenna array. Other examples disclosed herein include a radar system for use in an autonomous driving vehicle. |
| US11404791B2 |
Cylindrical antenna assembly
An antenna assembly includes an antenna carrier having a cylindrical body with a side wall extending between a top and a bottom and extensions extending from the side wall at the bottom at different radial positions. An antenna is coupled to the body having a film supporting first and second antenna elements having first and second feed lines and first and second antenna lines. The feed lines extend along corresponding extensions and the antenna lines wrap helically around the side wall. The antenna assembly includes clip terminals coupled to the extensions being electrically coupled to corresponding feed lines. The clip terminals have terminating ends configured to be electrically terminated to host conductors. |
| US11404788B1 |
Surface mount antenna elements for use in an antenna array
An antenna element comprises one or more directors, a resonator, and a three dimensional ground assembly. Parts of the antenna element are arranged on three metal layers. A top layer has an unconnected metal bar which forms a beam director, a resonator and a top part of the ground assembly. The resonator is an integral piece substantially in the form of a loop connected to a feed line and a feed line terminal ending. The feed line terminal ending serves as the ground plane for the feed line as well as providing impedance matching from the external transceiver circuit to the resonator. The ground assembly includes a top layer ground connected to a plurality of metallized half cylindrical hole channels (or metallized via holes) which connect to a ground terminal in a bottom layer. |
| US11404787B2 |
Magnetic-field generating circuit
A magnetic-field generating circuit includes a transformer antenna that includes a transformer including a primary coil and a secondary coil and a resonant capacitor connected in parallel to the secondary coil of the transformer and that generates a magnetic field. Moreover, an AC power supply circuit is provided that supplies an AC voltage serving as a driving voltage to the primary coil of the transformer antenna. The secondary coil and the resonant capacitor form a parallel resonant circuit whose resonant frequency is set to be equal to a frequency of the AC voltage supplied from the AC power supply circuit. |
| US11404785B2 |
Antenna module and user equipment
The antenna module includes: a first radiator having an opening; a second radiator located inside the opening, the second radiator being spaced apart from the first radiator; a first feed point located on the first radiator, the first feed point being configured for transmitting a wireless signal in a first frequency band; and a second feed point located on the second radiator, the second feed point being configured for transmitting a wireless signal in a second frequency band. The second frequency band differs from the first frequency band. |
| US11404779B2 |
On-chip phased array calibration systems and methods
Aspects of this disclosure relate to systems and methods for calibration of antenna arrays. The calibration may be based on determining a reference value for the beamformer derived from measurements of phase and/or amplitude for each channel within the beamformer. The measurements of phase and/or amplitude can be stored in non-volatile memory. Using a difference between the reference value and the measured values for each channel, a portion of a global configuration table may be copied to each channel's memory. Each channel can be separately calibrated based on the portion of the global configuration table copied to the local memory of each channel. |
| US11404774B2 |
Broadband dual antenna system
A broadband dual-antenna system provided herein comprises: a dielectric substrate including a first surface and a second surface; a grounding plane on the dielectric substrate; a loop metal branch located on the first surface and connected to the grounding plane; a coupling metal branch located on the second surface and connected to the grounding plane, the vertical projection of the coupling metal branch and that of the loop metal branch on the second surface partially overlap; a first metal branch located on the second surface and the coupling metal branch; a second metal branch located on the second surface and the coupling metal branch; a first signal source located on the second surface and connected to the first metal branch and the grounding plane; and a second signal source located on the second surface and connected to the second metal branch and the grounding plane. |
| US11404773B1 |
Additively-manufactured omnidirectional antenna
A method for making an antenna comprises creating a digital antenna file defining dimensional characteristics of a radiating support structure and a ground support structure; uploading the digital antenna file to an additive-manufacturing device; manufacturing the radiating support structure and ground support structure with the additive-manufacturing device; coating one side of the radiating support structure and ground support structure with a conductive ink; attaching the radiating support structure and ground support structure together; fixing a radio frequency connector to the conductive ink on the radiating support structure and the ground support structure. The radiating support structure and the ground support structure are attached together with a dielectric adhesive. The radio frequency connector is a coaxial cable; its center conductor is connected to the conductive coating of the radiating support structure and its outer conductor is connected to the conductive coating of the ground support structure using a conductive adhesive. |
| US11404772B2 |
Nozzle cap multi-band antenna assembly
A nozzle cap assembly includes a nozzle cap including a base, the base defining a top end and a bottom end; and a nut positioned opposite from the bottom end; an enclosure positioned between the top end of the base and the nut, the enclosure defining a cavity within the enclosure; at least one antenna positioned within the cavity. |
| US11404771B2 |
Singular process printed antenna with feed network and systems and methods related to same
Antennas, systems and methods may be implemented using a feed network with optional balanced to unbalanced conductor (balun) structure printed on one or more varying surfaces (e.g., sides, faces, etc.) of antenna substrates of various shapes including, but not limited to, flat, cylindrical, hemispherical and conical-shaped antenna substrates. Both antenna element/s and feed network/s may be printed onto one or more varying surfaces of a single common antenna substrate, such as printed onto both interior and exterior surfaces of the same hollow antenna substrate. |
| US11404764B2 |
Electronic device including plurality of antennas
An electronic device is disclosed. An electronic device according to an embodiment may include: a first Printed Circuit Board (PCB), a second PCB, a Radio Frequency (RF) transceiver disposed on the first PCB, a Flexible Printed Circuit Board (FPCB) coupled with the first PCB and the second PCB and electrically coupled with the RF transceiver, the FPCB including a transmission line of a wireless communication signal, an amplifier disposed on the second PCB and electrically coupled with the RF transceiver by the FPCB, a first antenna electrically coupled with the amplifier through the second PCB and configured to receive a wireless communication signal corresponding to a first frequency, and a second antenna electrically coupled with the amplifier through the second PCB and configured to receive a wireless communication signal corresponding to a second frequency. The first antenna and the second antenna may be disposed closer to the second PCB than the first PCB in the electronic device. The amplifier may amplify a wireless communication signal received from the first antenna and second antenna. |
| US11404762B2 |
Antenna system
The disclosure relates to an antenna system [1] comprising a mast [7], in turn comprising a base section [2b] and an extendable section [a], and an antenna [6]. The antenna [6] is arranged to be rotatable and the extendable section [2a] comprises a plurality of telescopic sections [8] whereby the extendable section [2a] may adopt a retracted configuration and a deployed configuration. The mast [7] is foldable in relation to a platform [5] in a vertical plane [PLxy] essentially parallel to the longitudinal direction of the extendable section [LD-es] and to the longitudinal direction of the base section [LD-bs] by means of a first pivot joint [9]. According to the disclosure the antenna system [1] may be arranged to the platform [5], wherein the platform [5] may be in form of a vehicle [5-v], whereby an antenna arrangement [101] is formed. The disclosure further relates to methods of avoiding oscillations for an antenna system [1] and/or an antenna arrangement [101], and to a method of undeploying an antenna arrangement [101]. |
| US11404761B2 |
Method for depositing an electrically conductive metal onto at least one portion of the inner surface of an internal cavity of a waveguide
A method for depositing an electrically conductive metal onto at least one portion of the inner surface (3) of an internal cavity (2) of a waveguide (1) includes: preparing a suspension containing at least one liquid and at least one precursor of the electrically conductive metal in suspension in said at least one liquid; coating at least one portion of the inner surface (3) of the internal cavity (2) of the waveguide (1) with the suspension, and heat-treating at least said portion of the inner surface (3) of the internal cavity (2) of the waveguide (1) coated with the suspension. A method for manufacturing a metallized waveguide can implement this deposition method. |
| US11404756B2 |
Pouch film and secondary battery including the same
Embodiments of the present invention provides a pouch film. In manufacturing a secondary battery, a gas may be generated when reacting an electrode assembly with an electrolyte. After the generated gas is discharged, the pouch film may be sealed. In this case, a deformation part may be formed in the gas chamber section which serves as a passage for discharging the gas, specifically, in the gas chamber passage, thus to prevent the electrolyte from flowing backward and maintain shapes of the gas chamber inlet during injecting the electrolyte. |
| US11404754B2 |
Secondary battery
A conductive member is disposed near a side of the sealing plate facing an electrode assembly with a first insulating member disposed therebetween. The conductive member has a conductive-member opening portion. The conductive member is connected to a positive electrode terminal that projects toward au outside of the battery from the sealing plate. The conductive-member opening portion of the conductive member is sealed by a deformation plate. The deformation plate is connected to a first positive-electrode current collector of a current collecting member, which is electrically connected to positive electrode plates. The deformation plate is deformed in response to an increase in pressure in a rectangular exterior body, and the conductive path between the positive electrode plate and the positive electrode terminal is broken in response to the deformation of the deformation plate. A cover is disposed between the first positive-electrode current collector and the electrode assembly. |
| US11404752B2 |
Cylindrical secondary battery including welding pole
A cylindrical secondary battery includes a jelly-roll type electrode assembly, a cylindrical battery case for receiving the jelly-roll type electrode assembly, and a cap assembly mounted to the open upper end of the cylindrical battery case. The jelly-roll type electrode assembly includes a long sheet type positive electrode and a long sheet type negative electrode wound with a separator interposed between the positive electrode and the negative electrode. A welding pole is formed on the bottom surface of the cylindrical battery case so as to extend perpendicularly thereto. |
| US11404748B2 |
Electrode/separator layered body and nickel zinc battery equipped therewith
An electrode-separator assembly is provided that can drastically facilitate assembly of a LDH separator-equipped nickel-zinc battery without the work, structure, or components for the complete separation of a positive-electrode chamber from a negative-electrode chamber. The electrode-separator assembly includes a positive-electrode plate, a negative-electrode plate, a layered double hydroxide (LDH) separator for separation of the positive-electrode plate from the negative-electrode plate, and a resin frame having an opening to which the LDH separator and the positive-electrode plate are fitted or joined. The positive-electrode plate has a smaller face than the negative-electrode plate. The negative-electrode plate has a clearance area that does not overlap with the positive-electrode plate over a predetermined width from the outer peripheral edge of the negative-electrode plate. The peripheral end faces of the LDH separator, and a segment of the separator adjacent to the positive-electrode plate and corresponding to the clearance area, are covered with the resin frame. |
| US11404747B1 |
Ceria coatings and structures for zinc-based battery separators
A zinc-based battery includes a non-sintered separator system including a polymer separator and a coating on the polymer separator. The coating includes cellulose acetate that prevents metallic zinc penetration into the separator, and ceria bound with the cellulose acetate that chemically oxidizes metallic zinc to zinc oxide. |
| US11404741B2 |
Battery system having waterproof structure
In a battery system, an output lead is exposed at an opening of an outer case, and the outer case accommodates a cradle mounting a lead plate and disposed at a fixed position. The cradle includes an upper plate allowing the lead plate to be disposed on the upper plate, a peripheral wall disposed around the lead plate, a drainage hole opened in the upper plate, and a drainage channel for water flowing from the drainage hole. The outer case is provided with a drainage opening allowing water flowing from the drainage channel to be externally drained. The lead plate includes a planar part disposed inside the peripheral wall, and a rising part crossing over the peripheral wall. Entering water flowing from the opening flows from the drainage hole and passes through the drainage channel to be externally drained out of the drainage opening of the outer case. |
| US11404740B2 |
Side impact protection of battery enclosures
A system for protecting a battery enclosure of a vehicle, comprising of a structural blocker configured to be fixedly attached to a side portion of the battery enclosure. The side portion faces a lateral direction, extending along a vehicle axis that extends between a front and a rear of a vehicle. The battery enclosure includes at least one cross member oriented along a lateral direction, wherein the structural blocker is configured to be aligned with an end of the cross member and localized to a region of the side portion proximate to the end of the cross member. The structural blocker is configured to transfer a side load from a structural component of the vehicle to the cross member. |
| US11404735B2 |
Immersed heat dissipation device for power battery
The present invention relates to an immersed heat dissipation device for power battery, comprising a battery heat dissipation module, a battery unit, a liquid refrigerant, a main inlet pipe and a main outlet pipe, wherein the battery heat dissipation module is a structure of sealed box that contains the liquid refrigerant, and a plurality of the battery heat dissipation modules are connected to each other and arranged in the heat dissipation device for power battery. The battery can be effectively cooled and the temperature of the battery can be effectively controlled, and ensure a uniform temperature for the battery unit, thereby improving the performance and life of the power battery of new energy vehicle. |
| US11404732B2 |
Battery pack
A battery pack is capable of maximizing or increasing a cooling effect of a module by concurrently performing conduction-type heat dissipation by a heat dissipation member extended from the inside to the outside of the module, and convection-type heat dissipation by a duct and a cooling fan. A battery pack includes: at least one module including a plurality of unit cells, a plurality of spacers between the unit cells, and a module case accommodating the unit cells and the spacers; a plurality of heat dissipation members inserted into the module and extended from the inside to the outside of the module; a duct including an opening and provided at one side of the module; and a cooling fan connected to the opening of the duct. |
| US11404731B2 |
Lead needle and lead slime separator for treating thin lead grid of waste lead-acid storage battery
A lead needle and lead slime separator for treating thin lead grid of waste lead-acid storage battery, includes: a barrel body, corrosion-resistant and wear-resistant balls, a feed device, a bracket device, a discharge device and a driver. A feed hole is arranged at one end of the barrel body, a discharge port is arranged at the other end of the barrel body. The feed device is mounted at the feed hole, and the discharge device is mounted at the discharge hole. The bracket device is connected to the barrel body, the driver is connected to the barrel body. The corrosion-resistant and wear-resistant balls are arranged in the barrel body. The separator can make the thin lead grid separation complete, clean and impurity-free. It does not need to be melted at high temperature in the melting furnace. |
| US11404728B2 |
Method and system to separate optically measured coupled parameters
A system includes a first optical sensor sensitive to both a parameter of interest, Parameter1, and at least one confounding parameter, Parameter2 and a second optical sensor sensitive only to the confounding parameter. Measurement circuitry measures M1 in response to light scattered by the first optical sensor, where M1=value of Parameter1+K*value of Parameter2. The measurement circuitry also measures M2 in response to light scattered by the second optical sensor, where M2=value of Parameter2. Compensation circuitry determines a compensation factor, K, for the confounding parameter based on measurements of M1 and M2 taken over multiple load/unload cycles or over one or more thermal cycles. The compensation factor is used to determine the parameter of interest. |
| US11404724B2 |
Electrolyte solution including multi-cyano compound additive and battery including the same
The present application relates to the field of energy storage materials, and particularly, to an electrolytic solution and a battery using the electrolytic solution. The electrolytic solution of the present application contains an additive, the additive including a multi-cyano compound represented by formula (I). The multi-cyano compound of the present application has a stronger complexation with a transition metal on the surface of a positive electrode material, and therefore a protective film can be formed on the surface of the positive electrode material, and the dissolution of the transition metal is effectively suppressed; the surface activity of the positive electrode material is reduced, thereby suppressing side reactions, such as the decomposition of the electrolytic solution on the surface of the positive electrode material; and the cycle performance and storage performance of a battery under wide range of working voltage and wide range of operating temperature conditions are thus improved. |
| US11404723B2 |
Silyl ester phosphinates as electrolyte additives
A non-aqueous electrolyte composition containing (i) at least one aprotic organic solvent; (ii) a compound of formula (I) (iii) at least one ion containing conducting salt; and (iv) optionally one or more additives. |
| US11404720B2 |
Method for producing lithium titanium phosphate
An X-ray diffractometrically single-phase lithium titanium phosphate can be obtained by an industrially advantageous method. Provided is a method for producing the lithium titanium phosphate having a NASICON structure represented by the following general formula (1): Li1+xMx(Ti1−yAy)2−x(PO4)3 (1), and provided is a method comprising a first step of preparing a raw material mixed slurry (1) comprising, at least, titanium dioxide, phosphoric acid and a surfactant, a second step of heat treating the raw material mixed slurry (1) to obtain a raw material heat-treated slurry (2), a third step of mixing the raw material heat-treated slurry (2) with a lithium source to obtain a lithium-containing raw material heat-treated slurry (3), a fourth step of subjecting the lithium-containing raw material heat-treated slurry (3) to a spray drying treatment to obtain a reaction precursor containing, at least, Ti, P and Li, and a fifth step of firing the reaction precursor. |
| US11404719B2 |
Protective anode coatings for high energy batteries
Materials for coating a metal anode in a high energy battery, anodes coated with the materials, and batteries incorporating the coated anodes are provided. Also provided are batteries that utilize the materials as electrolytes. The coatings, which are composed of binary, ternary, and higher order metal and/or metalloid oxides, nitrides, fluorides, chlorides, bromides, sulfides, and carbides limit the reactions between the electrolyte and the metal anode in a battery, thereby improving the performance of the battery, relative to a battery that employs a bare anode. |
| US11404718B2 |
Solid electrolyte material and battery
Provided is a solid electrolyte material represented by the following composition formula (1) Li3−3δ−aY1+δ−aMaCl6−x−yBrxIy Formula (1) where M is one or more kinds of elements selected from the group consisting of Zr, Hf, and Ti; −1<δ<2; 0 |
| US11404710B2 |
Assembled portion of a solid oxide fuel cell and methods for inspecting the same
An intermediate solid oxide fuel cell (SOFC) stage and methods for inspecting an assembled portion of an SOFC are presented. One method for inspecting an assembled portion of an SOFC includes applying a pneumatic constraint to a fluid, where the fluid is in communication with the assembled portion of the SOFC, determining a quality control parameter of the assembled portion of the SOFC in response to the pneumatic constraint, and ascertaining health of the assembled portion of the SOFC based on the quality control parameter. The assembled portion of the SOFC includes a metallic interconnect, where the metallic interconnect includes a flow field. |
| US11404704B2 |
Method for producing a separator plate for a fuel cell and a method for producing a fuel cell stack with such separator
A production method for a fuel cell separator comprises the steps of providing a powder blend of at least 70% carbon powder, 0.5-5% PTFE, PolyTetraFluoroEthylene, and 0-20% thermoplastic polymer different from PTFE. The powder is sedimented as slurry in a suspension, excess liquid removed from the slurry, and the remaining slurry press-moulded into a shape of a separator plate, for example for use in a fuel cell stack. |
| US11404703B2 |
Conductive, anti-corrosive material
A proton-exchange-membrane fuel cell bipolar plate includes a metal substrate having a bulk portion and a surface portion including an anticorrosive, conductive binary phosphide material having a formula (I): AxPy (I), where A is an alkali metal, alkaline earth metal, transition metal, post-transition metal, or metalloid, x, y is each a number independently selected from 1 to 15, and the binary phosphide material is configured to impart anticorrosive and conductive properties to the metal substrate. |
| US11404700B2 |
Positive electrode for lithium air batteries with excellent stability, method of manufacturing the same, and lithium air battery including the same
Disclosed are a positive electrode for lithium air batteries with excellent stability, a method of manufacturing the same, and a lithium air battery including the same, and a lithium air battery with improved stability by including the positive electrode. The positive electrode may include a conductive material and an ionic liquid such that the process of manufacturing the lithium air battery may be simplified, and the stability of the lithium air battery may be further improved as the result of inhibition of side reactions. |
| US11404693B2 |
Cathode additive, preparation method thereof, and cathode and lithium secondary battery comprising the same
The present disclosure relates to a cathode additive, a method for preparing the same, and a cathode and a lithium secondary battery including the same. More specifically, one embodiment of the present disclosure provides a cathode additive that can offset an irreversible capacity imbalance, and increase the initial charge capacity of a cathode. |
| US11404691B2 |
Method of manufacturing battery electrode material
A method of manufacturing a battery electrode material in slurry form to be coated on a sheet-shaped current collector, the battery electrode material containing an electrode active material made of electrolytic manganese dioxide (EMD) and containing an aqueous binder. The method includes, as a process of mixing and kneading raw materials of the battery electrode material by using water as a solvent, mixing the electrode active material; mixing the binder; and mixing a neutralizing agent, the neutralizing agent being lithium hydroxide (LiOH). |
| US11404680B2 |
Pixel bank manufacturing method, pixel bank structure, pixel structure, and display panel
A pixel bank manufacturing method, a pixel bank structure, a pixel structure, and a display panel are provided. The method includes providing a base substrate, wherein a plurality of anode thin film layers are manufactured on the base substrate; coating a photoresist layer used for covering the plurality of anode thin film layers on the base substrate; performing a photolithography on the photoresist layer by an exposing patterning structure, and baking to cure a remained photoresist layer after the photolithography to form a first bank layer; the exposing patterning structure is a structure that full via holes, first half via holes, a plurality of blind via holes, and second half via holes are arranged repeatedly; forming a second bank layer on the first bank layer; the second bank layer is a black bank layer. |
| US11404672B2 |
Flexible display panel, flexible display device, and manufacturing method thereof enhancing bending endurance
The present disclosure provides a display panel, manufacturing method thereof, and a display device. The display panel includes a substrate, a functional layer formed on the substrate, and an encapsulation layer formed on the functional layer. The encapsulation layer includes an inorganic layer on the functional layer, the inorganic layer includes a first oxide layer and a second oxide layer, and a ratio of the number of atomic layers of the first oxide layer to the number of atomic layers of the second oxide layer ranges from 1:4 to 3:1. |
| US11404660B2 |
Flexible organic light-emitting display (OLED) and spring component
Provided herein are a flexible organic light-emitting display (OLED) and a spring component. The film layers are pulled one on one by spring components to make the film layers flat when being unfolded and free of irreversible deformation when being folded. A lubricating layer is disposed between adjacent film layers so that the action force between the adjacent film layers is reduced, thereby making the flexible organic light-emitting display (OLED) flat and free of creases when being unfolded. |
| US11404659B2 |
Organic optoelectronic device
Disclosed is an optoelectronic device including a first electrode and a second electrode facing each other, a hole transport layer and an light emitting layer disposed between the first electrode and the second electrode, wherein the hole transport layer includes a compound represented by Chemical Formula 1 or a polymer thereof and the light emitting layer includes a perovskite compound. Definitions of Chemical Formula 1 are the same as described in the detailed description. |
| US11404656B2 |
Light-emitting device, light-emitting apparatus, electronic device, and lighting device
A light-emitting device with low driving voltage and favorable reliability is provided. The light-emitting device includes an electron-injection layer between a cathode and a light-emitting layer. The electron-injection layer is a mixed film of a metal and an organic compound having a function of interacting with the metal as a tridentate or tetradentate ligand, and the metal atom and the organic compound form SOMO. |
| US11404654B2 |
Compound containing iridium complex with aza dibenzo group and organic light emitting device comprising same
Provided is a compound of Chemical Formula 1: wherein: among X1 to X4, one of X1 and X2, X2 and X3, or X3 and X4 are linked with * in the following Chemical Formula 2, and of the remaining two, one is hydrogen, and the other is R3: R1 and R2 are each independently hydrogen, deuterium, halogen, cyano, amino, a substituted or unsubstituted C1-60 alkyl, a substituted or unsubstituted C1-60 haloalkyl, a substituted or unsubstituted C1-60 alkoxy, a substituted or unsubstituted C1-60 haloalkoxy, a substituted or unsubstituted C3-60 cycloalkyl, a substituted or unsubstituted C2-60 alkenyl, a substituted or unsubstituted C6-60 aryl, a substituted or unsubstituted C6-60 aryloxy, or a substituted or unsubstituted C2-60 heterocyclic group containing one or more heteroatoms selected from the group consisting of N, O and S; one of R3 is hydrogen, and the other is —Si(R4)(R5)(R6), R4 to R6 are each independently hydrogen, deuterium, cyano, a substituted or unsubstituted C1-60 alkyl, a substituted or unsubstituted C3-60 cycloalkyl, a substituted or unsubstituted C6-60 aryl, or a substituted or unsubstituted C2-60 heteroaryl containing at least one selected from the group consisting of N, O and S; and n is an integer of 0 to 2, and an organic light emitting device including the same. |
| US11404649B2 |
Electroluminescent bridged metal complexes for use in electronic devices
The present invention relates to metal complexes and to electronic devices, especially organic electroluminescent devices, comprising these metal complexes. The metal complex is, for example, represented by a compound formula (1) M(L)n(L′)m, containing a substructure M(L)n of the formula (2), and where M is iridium or platinum. |
| US11404647B2 |
Organic compound for organic light emitting diode and organic light emitting diode including same
Disclosed herein are an organic light emitting compound represented by [Chemical Formula 1] below and an organic light emitting diode comprising same. In [Chemical Formula 1], the substituents R1 to R5, R11 to R18, R21 to R22, and R31 to R40, the linkers L1 to L3, and m1 and m2 are as defined in the description: |
| US11404645B2 |
Direct singlet capture organic molecules with short emission decay time and application thereof in optoelectronic devices
The invention relates to novel pure organic emitter molecules and optoelectronic devices containing these organic emitter molecules. According to the invention, in the optoelectronic device, after the excitation of an organic molecule, relaxation and intersystem crossing processes also result from the almost isoenergetic charge transfer triplet state (3CT) for the direct rapid occupation and emission of the charge transfer singlet state (1CT), so that a 1CT→S0 fluorescence occurs without a thermal activation. |
| US11404644B2 |
Organic functional compounds, mixtures, formulations, organic functional thin films and preparation methods therefor and organic electronic devices
An organic functional compound, having a general formula of ASG)p; wherein A is an organic group having an optoelectronic function; the structural formula of SG is selected from the group consisting of wherein is selected from the group consisting of an aryl containing 5-40 ring-forming atoms and a heteroaryl containing 5-40 ring-forming atoms; R1 and R2 are each independently selected from the group consisting of H, D, F, CN, an alkyl, an aromatic ring group, an aromatic heterocyclic group, an amino, a silyl, a germyl, an alkoxy, an aryloxy, and a siloxy group; and p is an integer greater than or equal to 1. |
| US11404640B2 |
Vapor deposition mask, frame-equipped vapor deposition mask, and method for producing organic semiconductor element
A vapor deposition mask includes a metal mask and a resin mask having an opening. An inner wall surface for composing the opening has an inflection point in a thicknesswise cross section of the resin mask. When an intersection of a first surface, not facing the metal mask, of the resin mask and the inner wall surface is set to be a first intersection, an intersection of a second surface, facing the metal mask, of the resin mask and the inner wall surface is set to be a second intersection, and there is set a first inflection point first positioned from the first intersection toward the second intersection, an angle formed by a line connecting the first intersection and the first inflection point and the first surface is larger than an angle formed by a line connecting the first inflection point and the second intersection and the second surface. |
| US11404633B2 |
Method for forming MTJS with lithography-variation independent critical dimension
Some examples relate to a method for forming a semiconductor device. The method comprises forming a pattern definition stack over a substrate, the pattern definition stack comprising a transfer layer, an interlayer arranged over the transfer layer, and a patterning layer arranged over the interlayer. The method further comprises forming a first opening in the patterning layer to expose an upper surface of the interlayer and etching the interlayer with an at least partially isotropic etchant through the first opening to form a recessed cavity. The method further comprises forming a conformal layer over the interlayer and the patterning layer to fill the first opening, and etching the conformal layer and the transfer layer with an anisotropic etch to form a second opening in the transfer layer. The method also comprises depositing a hard mask material in the second opening. |
| US11404632B2 |
Magnetoresistive memory device including a magnesium containing dust layer
Magnetoelectric or magnetoresistive memory cells include a magnesium containing nonmagnetic metal dust layer located between a free layer and a dielectric capping layer. |
| US11404629B2 |
Treating solution supply apparatus
A treating solution supply apparatus which supplies a treating solution for treating a substrate includes a liquid passage for allowing the treating solution to flow therethrough; and a pump including a chamber with a variable volume for receiving and feeding the treating solution from/to the liquid passage, and a chamber driver electrically driven to vary the volume of the chamber. The liquid passage, chamber, and chamber driver are arranged in the stated order laterally. |
| US11404626B2 |
Vibrator device, method of manufacturing vibrator device, electronic apparatus, and vehicle
A vibrator device including a vibrator element, an IC substrate including a semiconductor substrate configured of a semiconductor having a first conductive type and a circuit electrically coupled to the vibrator element, the first conductive type being any one of an N-type and a P-type, and a lid directly bonded to the semiconductor substrate and configured of a semiconductor having the first conductive type. |
| US11404624B2 |
Fabrication of a quantum device
In a masking phase, a first segment of an amorphous mask is formed on an underlying layer of a substrate. The first segment comprises a first set of trenches exposing the underlying layer. In the masking phase, a second segment of the amorphous mask is formed on the underlying layer. The second segment comprises a second set of trenches exposing the underlying layer. The segments are non-overlapping. An open end of one of the first set of trenches faces an open end of one of the second set of trenches, but the ends are separated by a portion of the amorphous mask. In a semiconductor growth phase, semiconductor material is grown, by selective area growth, in the first and second sets of trenches to form first and second sub-networks of nanowires on the underlying layer. The first and second sub-networks of nanowires are joined to form a single nanowire network. |
| US11404623B2 |
Method of manufacturing bulk type thermoelectric element
The present invention relates to a method of manufacturing a bulk type thermoelectric element implemented so as to simplify the manufacturing process as well as to reduce the manufacturing cost. The method of manufacturing a bulk type thermoelectric element includes the steps of: preparing two types of P-type and N-type substrates by slicing a thermoelectric element material; bonding P-type pellets formed on the P-type substrate and N-type pellets formed on the N-type substrate to each other to alternately engaging with each other, and then polishing (grinding) the bottom of each substrate to form a P/N layer in which the P-type pellets and the N-type pellets are cross-formed; and assembling ceramic substrates with conductive electrode pads (PAD) on the top and the bottom of the P/N layer to complete a thermoelectric element. |
| US11404622B2 |
Insulated heat transfer substrate, thermoelectric conversion module, and method for manufacturing insulated heat transfer substrate
An insulated heat transfer substrate includes a heat transfer layer formed of aluminum or an aluminum alloy, a conductive layer provided on one surface side of the heat transfer layer, and a glass layer formed between the conductive layer and the heat transfer layer, in which the conductive layer is formed of a sintered body of silver, and a thickness of the glass layer is in a range of 5 μm or larger and 50 μm or smaller. |
| US11404621B2 |
Mg-Sb-based thermoelement, preparation method and application thereof
Provided by the present invention is a magnesium-antimony-based (Mg—Sb-based) thermoelement, a preparation method and application thereof. The Mg—Sb-based thermoelement comprises: a substrate layer of a Mg—Sb-based thermoelectric material positioned in the center of the thermoelement, transitional layers that are attached to the two surfaces of the substrate layer, and two electrode layer that are respectively attached to the surfaces of the two transitional layers; the transitional layers are made of a magnesium-copper alloy and/or magnesium-aluminum alloy, and the electrode layer is made of copper. The transitional layer and the electrode layer which are developed in the present invention and which are suitable for a Mg—Sb-based thermoelectric material have great significance and prospects in application. The electrode layer enable the Mg—Sb-based thermoelectric material to have an opportunity to enter the market and realize commercialization. Compared with the existing bismuth telluride thermoelectric devices in the market, the thermoelectric device prepared has lower costs, may simultaneously save the rare element tellurium, and is beneficial in saving energy and protecting the environmental. |
| US11404619B2 |
Light-emitting diode module and assembly with a light-emitting diode module
In one embodiment, the light-emitting diode module comprises a carrier and a plurality of light-emitting diodes. Thereby, several types of light-emitting diodes are present. The light-emitting diodes can be controlled individually or in groups electrically independently of one another. The light-emitting diodes each comprise a first and a second electrical contact. The carrier comprises several electrically conductive main layers, between each of which there is an electrically insulating intermediate layer. The contacts of the light-emitting diodes are attached to a carrier upper side on one of the first main layers. Starting from the first contacts, electrical through-connections are each connected directly to a carrier underside with a last main layer of the main layers. Starting from the second contacts, electrical through-connection each terminate at a penultimate main layer of the main layers, wherein the penultimate main layer is located inside the carrier. |
| US11404617B2 |
Method for manufacturing image display device
A liquid photocurable resin composition not containing a thermal polymerization initiator is applied to a surface of a light-transmitting cover member having a light-shielding layer or a surface of an image display member, irradiated with ultraviolet rays under an atmosphere where the oxygen concentration is significantly decreased and cured, to form a light-transmitting cured resin layer. Subsequently, the image display member and the light-transmitting cover member are stacked through the light-transmitting cured resin layer to manufacture an image display device of the present invention. |
| US11404616B2 |
Micro LED display module with excellent color tone and high brightness
A method of manufacturing a micro light emitting diode (LED) display module. The method of manufacturing a micro LED display module may include: pressing a plurality of micro LEDs disposed on a substrate to which an adhesive layer is applied, to electrically connect the plurality of micro LEDs to electrode pads of the substrate; performing testing to detect whether at least one of the plurality of micro LEDs is defective in a state in which the plurality of micro LEDs are pressurized and the adhesive layer is uncured; and based on detecting that at least one of the plurality of micro LEDs is defective, performing control to harden the adhesive layer. |
| US11404612B2 |
LED device having blue photoluminescent material and red/green quantum dots
A light-emitting device includes a plurality of light-emitting diodes, a first cured composition over a first subset of the light-emitting diodes, and a second cured composition over a second subset of light-emitting diodes. The first cured composition includes a first photopolymer and a blue photoluminescent material that is an organic, organometallic, or polymeric material, embedded in the first photopolymer. The second cured composition includes a second photopolymer and a nanomaterial embedded in the second photopolymer. The nanomaterial is selected to emit red or green light in response. |
| US11404608B2 |
Light emitting device with reflective sidewall
Embodiments of the invention include a light emitting device including a substrate and a semiconductor structure including a light emitting layer. A first reflective layer surrounds the light emitting device. A wavelength converting element is disposed over the light emitting device. A second reflective layer is disposed adjacent a first sidewall of the wavelength converting element. |
| US11404603B2 |
Nitride semiconductor light-emitting element
A nitride semiconductor light-emitting element includes an active layer including an AlGaN-based barrier layer, a p-type contact layer located on an upper side of the active layer, and an electron blocking stack body located between the active layer and the p-type contact layer. The electron blocking stack body includes a first electron blocking layer and a second electron blocking layer. The first electron blocking layer is located on the active layer side and has a higher Al composition ratio than an Al composition ratio in the barrier layer. The second electron blocking layer is located on the p-type contact layer side and has a lower Al composition ratio than an Al composition ratio in the barrier layer. |
| US11404601B2 |
Conductive micro LED architecture for on-wafer testing
LED donor substrates and conductive architectures for on-wafer testing are described. In an embodiment, an array of LEDs is supported by an array of electrically conductive stabilization posts. The electrically conductive stabilization posts can be coupled with a test pad for on-wafer testing prior to transferring the LEDs to a receiving substrate. |
| US11404597B2 |
Solar cell and method of manufacturing the same
Provided are a solar cell having a good conversion efficiency in which damage to a p-n junction structure is prevented when an antireflection film is removed, and a method of manufacturing such a solar cell. |
| US11404596B1 |
Balancing a pair of avalanche photodiodes in a coherent receiver
System and methods implemented in a coherent receiver having a pair of Avalanche Photodiodes (APD) include adjusting one or more of a reverse bias voltage (VAPD) on a P-path (VAPDP) and on an N-path (VAPDN) responsive to an output (PIN,CM) that indicates electrical power of an AC common-mode input signal; adjusting a Transimpedance Amplifier (TIA) common-mode AC response, AdjCM_AC_Response, responsive to an output (POUT,CM) that indicates electrical power of an AC common-mode output signal; and/or adjusting one or more of VAPDP and VAPDN responsive to received signal Signal-to-Noise Ratio (SNR). |
| US11404594B2 |
Positive-intrinsic-negative (PIN) photosensitive device, manufacturing method thereof, and display panel
A positive-intrinsic-negative (PIN) photosensitive device is provided. A p-type semiconductor layer composed of molybdenum oxide and having valence band energy between valence band energy of an intrinsic semiconductor layer and an upper electrode is used to replace a p-type semiconductor layer used in a conventional PIN photodiode, so that the PIN photodiode may be prepared without using borane gas. More, a difference between valence band energy of the p-type semiconductor layer and the intrinsic semiconductor layer is used to transport holes located in a valence band, so that it is unnecessary to use an active layer of a thin film transistor, so that the PIN photosensitive device may be stacked on the thin film transistor to reduce aperture ratio loss of a display panel. |
| US11404593B2 |
Double-sided electrode type solar cell and solar cell module
A solar cell module which exhibits high output while ensuring connection strength between solar cells; and a solar cell suitable for the solar cell module. In the solar cell, a region on a first surface and at a first edge of a substrate that is not covered by a p-type transparent oxide electrode layer is defined as a “region A,” and a region on the first surface and at a second edge opposite to the first edge of the substrate and not covered by the p-type transparent oxide electrode layer is defined as a “region B.” The area of the region A is larger than the area of the region B. |
| US11404592B2 |
Room temperature printing method for producing a PV layer sequence and PV layer sequence obtained using the method
PV layer sequences and corresponding production methods which can reliably provide a PV function with a long service life despite very low production costs. This is achieved by a reactive conditioning process of inorganic particles as part of a room-temperature printing method; the reactive surface conditioning process adjusts the PV activity in a precise manner, provides a kinetically controlled reaction product, and can ensure the desired PV activity even when using technically pure starting materials with 97% purity. In concrete embodiments, particles are printed in composite so as to form sub-sections on a support. Each sub-section has a reductively treated section and an oxidatively treated section, and the sections have PV activity with opposite signs. The sections can be cascaded in rows via upper-face contacts, and a precise light-dependent potential sum can be tapped via a PV measuring group. |
| US11404591B2 |
Methods and apparatuses for improved barrier and contact layers in infrared detectors
An infrared detector and a method for forming it are provided. The detector includes absorber, barrier, and contact regions. The absorber region includes a first semiconductor material, with a first lattice constant, that produces charge carriers in response to infrared light. The barrier region is disposed on the absorber region and comprises a superlatice that includes (i) first barrier region layers comprising the first semiconductor material, and (ii) second barrier region layers comprising a second semiconductor material, different from, but lattice matched to, the first semiconductor material. The first and second barrier region layers are alternatingly arranged. The contact region is disposed on the barrier region and comprises a superlattice that includes (i) first contact region layers comprising the first semiconductor material, and (ii) second contact region layers comprising the second semiconductor material layer. The first and second contact region layers are alternatingly arranged. |
| US11404586B1 |
Transistors with enhanced dopant profile and methods for forming the same
A planar insulating spacer layer is formed over a substrate, and a vertical stack of a gate electrode, a gate dielectric layer, and a first semiconducting metal oxide layer may be formed thereabove. The first semiconducting metal oxide layer includes atoms of a first n-type dopant at a first average dopant concentration. A second semiconducting metal oxide layer is formed over the first semiconducting metal oxide layer. Portions of the second semiconducting metal oxide layer are doped with the second n-type dopant to provide a source-side n-doped region and a drain-side n-doped region that include atoms of the second n-type dopant at a second average dopant concentration that is greater than the first average dopant concentration. Various dopants may be introduced to enhance performance of the thin film transistor. |
| US11404585B2 |
Semiconductor device and method for manufacturing semiconductor device
A manufacturing method of a semiconductor device in which the threshold is adjusted to an appropriate value is provided. The semiconductor device includes a semiconductor, a source or drain electrode electrically connected to the semiconductor, a first gate electrode and a second gate electrode between which the semiconductor is sandwiched, an electron trap layer between the first gate electrode and the semiconductor, and a gate insulating layer between the second gate electrode and the semiconductor. By keeping a potential of the first gate electrode higher than a potential of the source or drain electrode for 1 second or more while heating, electrons are trapped in the electron trap layer. Consequently, threshold is increased and Icut is reduced. |
| US11404584B2 |
Array substrate and method of preparing the same
The present disclosure provides an array substrate and a method of preparing the same. The array substrate includes a substrate, a gate, a gate insulation layer, an active layer, a crystallization layer, an oxide layer, a source/drain metal layer, and a passivation layer. After the crystallization layer is prepared, a mask plate is not removed and is used to protect an upper surface of the crystallization layer from oxidation reaction. Then, an oxide layer is formed on sidewalls of the crystallization layer and the active layer. The oxide layer is used to obstruct the source/drain metal layer from contacting the active layer. The source/drain metal layer is only in contact with the crystallization layer, thereby reducing a path of leakage current and achieving a purpose of reducing the leakage current. |
| US11404581B2 |
Wimpy vertical transport field effect transistor with dipole liners
A semiconductor structure may include a bottom source drain, a top source drain, a gate stack. The top source drain is above the gate stack and the bottom source drain is below the gate stack. The semiconductor structure may also include a bottom spacer and a top spacer. The gate stack is between the bottom spacer and the top spacer. The bottom spacer and the top spacer each comprise a dipole liner. The dipole liner includes a first layer and a second layer. The second layer may be in direct contact with the first layer. The second layer may be made of different material than the first layer. The first layer may be made of silicon oxide. The second layer may be made of silicon nitride or aluminum oxide. The first layer may be in direct contact with the gate stack, the top source drain, and the bottom source drain. |
| US11404577B2 |
Semiconductor device and method of forming doped channel thereof
A method includes forming a dielectric cap over a semiconductor substrate; forming a dummy gate structure over the dielectric cap; forming gate spacers on opposite sidewalls of the dummy gate structure and on a top surface of the dielectric cap; removing the dummy gate structure to form a gate trench between the gate spacers and exposing the dielectric cap; and performing an ion implantation to form a doped region in the semiconductor substrate through the dielectric cap. |
| US11404569B2 |
Sidewall spacer structure to increase switching performance of ferroelectric memory device
Various embodiments of the present disclosure are directed towards an integrated chip including a ferroelectric structure overlying a substrate. A pair of source/drain regions are disposed in the substrate. A gate dielectric layer overlies the substrate and is spaced laterally between the pair of source/drain regions. The ferroelectric structure overlies the gate dielectric layer. The ferroelectric structure includes a ferroelectric layer and a sidewall spacer structure, where the sidewall spacer structure continuously laterally wraps around the ferroelectric layer. The ferroelectric layer comprises a first metal oxide and the sidewall spacer structure comprises a second metal oxide different than the first metal oxide. |
| US11404567B2 |
Trench-gate field effect transistor with improved electrical performances and corresponding manufacturing process
A field effect transistor has a semiconductor layer with a top surface extending in a horizontal plane, and an active area defined in which are trench gate regions, which extend in depth with respect to the top surface and have an insulating coating layer and a conductive inner layer, and source regions, adjacent to the trench gate regions so as to form a conductive channel extending vertically. The trench gate regions have a plurality of first gate regions, which extend in length in the form of stripes through the active area along a first direction of the horizontal plane, and moreover a plurality of second gate regions, which extend in length in the form of stripes through the same active area along a second direction of the horizontal plane, orthogonal to, and crossing, the first gate regions. In particular, the first gate regions and second gate regions cross in the active area, joining with a non-zero curvature radius. |
| US11404566B2 |
Semiconductor device
A semiconductor device includes an active region, a gate ring region surrounding a periphery of the active region, and a source ring region surrounding a periphery of the gate ring region. The semiconductor device has a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, and a second electrode. The semiconductor device has, in the active region, first semiconductor regions of the first conductivity type, a gate insulating film, first gate electrodes, an interlayer insulating film and a first first-electrode, and has, in the source ring region, a third semiconductor region and a second first-electrode. In the source ring region, a second semiconductor region of the first or second conductivity type is provided at a bottom of the third semiconductor region, directly below the second first-electrode in a depth direction of the semiconductor device. |
| US11404562B2 |
Tunneling field effect transistors
Disclosed herein are tunneling field effect transistors (TFETs), and related methods and computing devices. In some embodiments, a TFET may include: a first source/drain material having a p-type conductivity; a second source/drain material having an n-type conductivity; a channel material at least partially between the first source/drain material and the second source/drain material, wherein the channel material has a first side face and a second side face opposite the first side face; and a gate above the channel material, on the first side face, and on the second side face. |
| US11404557B2 |
Method of forming a high electron mobility transistor
A method of forming a high electron mobility transistor (HEMT) includes a first III-V compound layer and a second III-V compound layer disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are disposed on the second III-V compound layer. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A capping layer is disposed on the second III-V compound layer. |
| US11404556B2 |
FET using trench isolation as the gate dielectric
A semiconductor device includes a Silicon-on-Insulator (SOI) substrate including a top device layer, a buried oxide (BOX) layer, and a bottom handle portion. A filled trench is lined with a trench dielectric layer that extends to at least the BOX layer, defining an inner and an outer portion of the device layer. A field effect transistor (FET) includes an inner portion, a source region having a source contact thereto and a drain region having a drain contact thereto, each doped a first doping type. A gate region has a gate contact that is separated from the inner portion by the trench dielectric. The source and drain region are separated by a body region doped a second doping type having a body contact. |
| US11404553B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device includes a source/drain region, a body region, a first gate structure, and a second gate structure. The source/drain region and the body region are in a substrate. The first and second gate structures are above the substrate. The source/drain region and the body region are on opposite sides of the first gate structure. The second gate structure is spaced apart from the first gate structure. The source/drain region, the body region, and the first gate structure are on a same side of the second gate structure. |
| US11404550B2 |
Semiconductor device and method for manufacturing the same
According to one embodiment, a semiconductor device includes first, and second conductive members, first, second, and third semiconductor regions, and an insulating part. A direction from the first conductive member toward the second conductive member is along a first direction. The first semiconductor region includes first and second partial regions. A second direction from the first partial region toward the second partial region crosses the first direction. The first conductive member is between the first partial region and the second conductive member. A direction from the second partial region toward the second semiconductor region is along the first direction. A direction from the second conductive member toward the second semiconductor region is along the second direction. The third semiconductor region is between the second partial region and the second semiconductor region. The insulating part includes a first insulating region, a second insulating region, and a third insulating region. |
| US11404548B2 |
Capacitance reduction for backside power rail device
The present disclosure describes a method to form a backside power rail (BPR) semiconductor device with an air gap. The method includes forming a fin structure on a first side of a substrate, forming a source/drain (S/D) region adjacent to the fin structure, forming a first S/D contact structure on the first side of the substrate and in contact with the S/D region, and forming a capping structure on the first S/D contact structure. The method further includes removing a portion of the first S/D contact structure through the capping structure to form an air gap and forming a second S/D contact structure on a second side of the substrate and in contact with the S/D region. The second side is opposite to the first side. |
| US11404536B2 |
Thin-film transistor structures with gas spacer
An integrated circuit includes a base, a first transistor structure on or above the base, and a second transistor structure on or above the base, where the second transistor structure is spaced from the first transistor structure. An insulator material at least partially encapsulates an airgap or other gas pocket laterally between the first transistor structure and the second transistor structure. The gas pocket is at least 5 nm in height and at least 5 nm wide according to an embodiment, and in some cases is as tall or taller than active device layers of the transistor structures it separates. |
| US11404531B2 |
Display screens and display terminals
A display screen includes a first display area and a second display area that are adjacent to each other. The first display area is connected to the second display area. The display screen further includes a first display panel and a second display panel. The first display panel includes a first substrate, a first electrode layer formed on the first substrate, a first pixel definition layer formed on the first electrode layer, a second electrode layer formed on the first pixel definition layer, and electrode lead-out wires. The first electrode layer includes first electrodes. The first electrode is adjacent to the second display panel. The second electrode layer includes second electrodes. The second electrodes respectively intersect across the first electrodes. The electrode lead-out wires are respectively connected with the first electrodes, and respectively extend in parallel with the second electrodes in the same direction. |
| US11404526B2 |
Display substrate and display device
The present disclosure provides a display substrate and a display device. The display substrate comprises a base, a plurality of display units arranged on the base, a signal line and a control unit, wherein the signal line is configured to connect adjacent two display units of the plurality of display units; at least a part of the signal line is made of a shape memory material, and the part is deformed to different degrees under different excitation conditions; the control unit is configured to detect deformation of the base and apply a corresponding excitation condition to the signal line according to the deformation of the base, so that the signal line is in a deformation state adaptive to the deformation of the base. |
| US11404525B2 |
Display device and method for manufacturing display device
A terminal of a flexible organic EL display device is formed using a third conductive member being a second metal layer exposed through an opening of a second resin layer. In the opening of the second resin layer, a protruding portion being formed using a third resin layer being a layer lower than the second resin layer and the third conductive member being the second metal layer overlap each other. |
| US11404524B2 |
Display panel, display module, and electronic device
A display panel, a display module, and an electronic device are provided. The display panel includes a third metal layer including a signal line, and a conductive layer including a connection portion. The connection portion is connected to the signal line. A pixel definition layer is disposed on the conductive layer, and the pixel definition layer includes a first opening region and a second opening region. A cathode is disposed in the second opening region and disposed on the pixel definition layer. The cathode is connected to the connection portion. |
| US11404523B2 |
Display device
A display device includes a data line extending in a first direction, a scan line extending in a second direction crossing the first direction, a wire extending in the second direction, and a bridge electrically connecting the wire to the data line, where the wire includes a branch protruding from the wire in the first direction, and the bridge overlaps the data line and the branch of the wire. |
| US11404522B2 |
Display device having first and second gates disposed on a first side of an active area and a pattern disposed on a second side of the active area
A display device including: a panel including pixels, a pixel including: an LED; a capacitor between a first voltage line and a node; a first transistor between the first voltage line and a first electrode of the LED; a second transistor between a data line and a source of the first transistor; a third transistor between the node and a drain of the first transistor; a fourth transistor between the node and a second voltage line; a fifth transistor between the first voltage line and the source of the first transistor; a sixth transistor between the first electrode and the drain of the first transistor; and a seventh transistor between the second voltage line and the first electrode, the third and fourth transistor including: an active area including metal oxide; first and second gates above the active area; and a pattern below the active area. |
| US11404521B2 |
Display apparatus including power supply line and fan-out portion
A display apparatus includes a first substrate including a display area and a peripheral area on a side of the display area, a second substrate facing the first substrate, a fan-out portion arranged in the peripheral area and including a plurality of wires, a power supply line arranged over the fan-out portion and in the peripheral area, an insulating layer arranged between the plurality of wires and the power supply line, and a sealing portion arranged in the peripheral area. The sealing portion surrounds a periphery of the display area and attaches the first substrate and the second substrate to each other. The peripheral area includes an overlapping area in which the fan-out portion, the power supply line, and the sealing portion overlap one another. The power supply line arranged in the overlapping area includes a first conductive layer and a second conductive layer arranged on the first conductive layer. |
| US11404519B2 |
Organic light emitting display device
An organic light emitting display device may include a first active pattern disposed on a substrate and including a first region, a second region, and a third region; a first gate electrode disposed on the first active pattern and forming a first transistor together with the first region and the second region; a second gate electrode disposed on the first active pattern and forming a second transistor together with the second region and the third region; a third gate electrode disposed on the first gate electrode, overlapping the second region, and forming a storage capacitor together with the first gate electrode; a metal pattern disposed between the first active pattern and the third gate electrode and overlapping the second region; and an organic light emitting diode electrically connected to the first transistor, the second transistor, and the storage capacitor. |
| US11404518B2 |
Display panel with dummy pixels and black lines in transmission area
A display panel includes a substrate including a display area and a transmission area arranged in the display area which is surrounded by a first side extending in a first direction, a second side extending in a second direction crossing the first direction, a third side facing the first side, and a fourth side facing the second side, pixels arranged in the display area, a first black line extending from the transmission area to the first side in a third direction different from the second direction and arranged with dummy pixels which do not emit light, and a second black line extending from the transmission area to the second side in a fourth direction different from the first direction and arranged with the dummy pixels which do not emit light, wherein the transmission area is arranged closer to the first and second sides than the third and fourth sides. |
| US11404515B2 |
Display substrate and manufacturing method thereof, and display device
A display substrate and a manufacturing method thereof, and a display device, are disclosed. The display substrate includes a base substrate and a thin film transistor (TFT) array, including a plurality of TFTs. A first electrode in each TFT includes a first portion and a second portion, a height of the second portion being greater than a height of the first portion in a direction perpendicular to the base substrate, wherein the first portion forms a groove with respect to the second portion and a wall of the groove comprises the second portion of the first electrode of a thin film transistor adjacent to the TFT. A bottom of the groove is the first pixel electrode of a light emitting element, wherein an organic light emitting functional layer is deposited in the groove on the first pixel electrode, and the second pixel electrode on the organic light emitting functional layer. |
| US11404514B2 |
Display device including irregularly-shaped gate disposed below driving thin-film transistor
A display device, including an irregularly-shaped display area disposed with a plurality of irregularly-shaped display pixels and at least one attachment device; and a pixel display area disposed adjacent to the irregularly-shaped display area; wherein each of the irregularly-shaped display pixels comprises an irregularly-shaped gate disposed below a driving thin-film transistor, and the irregularly-shaped gate changes a light-emitting brightness of the irregularly-shaped display pixel according to an adjustment voltage signal to balance light-emission uniformity of the irregularly-shaped display area and the pixel display area. |
| US11404512B2 |
Display apparatus including auxiliary pixels
A display apparatus includes a substrate that includes a sensor area, a first non-display area at least partially surrounding the sensor area, and a display area at least partially surrounding the first non-display area. A plurality of auxiliary pixels is disposed in the sensor area. The plurality of auxiliary pixels is configured for passive matrix driving. A plurality of main pixels is disposed in the main display area and is configured for active matrix driving. |
| US11404506B2 |
Display device
A display device includes a plurality of subpixels each including a transmission portion and a light emitting portion on a substrate, wherein the light emitting portion includes a driving transistor and an organic light emitting diode connected to the driving transistor, and an extension line extending from a drain electrode of the driving transistor and a first electrode of the organic light emitting diode are connected to each other in the transmission portion. |
| US11404502B2 |
Display substrate and manufacturing method thereof, display panel
A display substrate, a manufacturing method thereof and a display panel are provided. The display substrate includes a base and a pixel defining layer provided on the base, the pixel defining layer includes a plurality of sub-pixel regions, and at least one storage tank defined by the pixel defining layer is provided in each of the plurality of sub-pixel regions, and at an identical height with respect to the base, in a length direction of the storage tank, an end portion of the storage tank and a portion between two end portions of the storage tank differ in wettability to a storage material. |
| US11404498B2 |
Display device having fingerprint sensing function and method of operating the same
A display device includes a display unit displaying an image, a fingerprint sensing unit disposed on one surface of the display unit and including fingerprint sensing pixels to sense a fingerprint, and a readout circuit providing a selection signal to the fingerprint sensing unit to select a predetermined amount of fingerprint sensing pixels from the fingerprint sensing pixels as a sensing area and receiving a fingerprint sensing signal from the sensing area. The readout circuit accumulates the fingerprint sensing signal provided from the fingerprint sensing pixels in the sensing area during a test mode and calculates a compensation value based on a difference between the accumulated fingerprint sensing signal and a reference value. |
| US11404497B2 |
Organic light emitting display device
An organic light emitting display device includes: a substrate including pixel areas and a pixel separating area; a plurality of pixels; a plurality of spacers in the pixel separating area and spaced apart from each other; and a touch electrode unit disposed over the plurality of pixels and spacers. The touch electrode unit includes first touch electrodes arranged in a first direction and second touch electrodes arranged in a second direction. The touch electrode unit includes a plurality of touch pattern unit blocks repeatedly arranged. Each touch pattern unit block includes portions of each of neighboring first touch electrodes and portions of each of neighboring second touch electrodes. The spacers of each touch pattern unit block corresponds to a plurality of spacer pattern unit blocks repeatedly arranged. Each spacer pattern unit includes at least one spacer and is smaller than the touch pattern unit block. |
| US11404491B2 |
Display panel having black matrix layer in direct contact with conductive layer and method of manufacturing the same
A display panel and a method of manufacturing the same are provided. The method includes: forming a color filter layer on a glass substrate, the color filter layer including a plurality of color resist matrices having a plurality of colors; forming a black matrix layer between the color resist matrices having the plurality of colors, the black matrix layer including a plurality of black matrices, wherein the black matrices have electrical conductivity, and a position of the black matrices corresponds to a position of a transparent electrode. In the above manner, uniformity of light emission of the display panel can be effectively improved. |
| US11404489B2 |
Display substrate capable of alleviating color separation, and display device
A display substrate, a manufacturing method thereof and a display device are provided. The display substrate includes: a driver circuit layer, a planarization layer and light-emitting units, each light-emitting unit includes an anode, a cathode and an organic light emitting layer located between the anode and the cathode, and the anode is connected to a driving electrode of the driver circuit layer through a via hole in the planarization layer. The organic light emitting layer includes: at least one pixel repetition unit, each pixel repetition unit includes multiple pixels, and each pixel includes multiple sub-pixels with different colors. Via holes in the planarization layer that correspond to same colored sub-pixels of at least two pixels in the same pixel repetition unit have different via hole positions, the via hole position being a relative position of a projection of a via hole in the planarization layer within corresponding sub-pixel. |
| US11404486B2 |
Display substrate, manufacturing method thereof and display device
The present application relates to a display substrate, a manufacturing method thereof, and a display device. The display substrate includes a base plate, a plurality of pixel structures on the base plate, and a color resist layer on a side of the plurality of pixel structures away from the base plate. The color resist layer includes a plurality of color resist blocks, each color resist block corresponding to one or more of the plurality of pixel structures. Light emitted from each of the plurality of pixel structures has the same color as the color resist block corresponding thereto. |
| US11404485B2 |
Array substrate, method of fabricating array substrate, and display panel
The present disclosure generally relates to display technologies. An array substrate may include a plurality of first pixel units and a plurality of second pixel units arranged in alternating manner. Each of the plurality of first pixel units may include a first plurality of subpixels, each of the first plurality of subpixels comprising a functional stack that has a thickness of from 180 to 360 nm. Each of the plurality of second pixel units may include a second plurality of subpixels, each of the second plurality of subpixels comprising a functional stack that has a thickness of from 80 to 140 nm. |
| US11404475B2 |
Semiconductor sensor device and semiconductor sensor device manufacturing method
Connection with a wiring structure can be reliably achieved, whereby a semiconductor sensor device and a semiconductor sensor device manufacturing method with increased reliability are provided. A semiconductor sensor device in which a multiple of signal lines and a sensor detection portion are disposed includes a conductive film, disposed on a substrate, that configures the signal lines and whose upper face is exposed by an aperture portion of a width smaller than a width of the signal lines, a conductive member formed on the conductive film and electrically connected to the conductive film via the aperture portion, and a wiring structure, formed on an upper face of the conductive member, of an air bridge structure that connects the signal lines or the signal lines and the sensor detection portion, wherein an upper surface of the conductive member is in contact with the wiring structure, and a side face is exposed. |
| US11404472B2 |
Display module and display apparatus including light blocking layer with openings having regular intervals therebetween
A display module includes a substrate, a plurality of LEDs that are disposed on the substrate and irradiate light, and a light blocking layer that covers the plurality of LEDs, and fills intervals among the plurality of LEDs, each interval of the intervals being a distance between two adjacent LEDs of the plurality of LEDs, and wherein the light blocking layer includes a plurality of openings formed such that a top surface of each of the plurality of LEDs is exposed. |
| US11404467B2 |
Image sensor and system including the image sensor
An image sensor includes: a pixel array outputting a pixel signal; and a column wiring unit including at least one first column routing wiring extending from the pixel array and including a first connection wiring portion and a protrusion and at least one second column routing wiring including a second connection wiring portion, wherein a sum of lengths of the at least one first connection wiring portion and the protrusion is substantially identical to a length of the at least one second connection wiring portion; and a readout circuit receiving the pixel signal from the column wiring unit. |
| US11404465B2 |
Epitaxial semiconductor liner for enhancing uniformity of a charged layer in a deep trench and methods of forming the same
Photodetectors, transistors, and metal interconnect structures may be formed on a front side of the semiconductor substrate. A trench is formed through a backside surface of the semiconductor substrate toward the front side by an anisotropic etch process, which provides a vertical or tapered surface with a first root-mean-square surface roughness greater than 0.5 nm. A single crystalline semiconductor liner is deposited by performing an epitaxial growth process at a growth temperature less than 500 degrees Celsius on the vertical or tapered surface of the trench. A physically exposed side surface of the single crystalline semiconductor liner may have a second root-mean-square surface roughness less than 0.5 nm. At least one dielectric metal oxide liner having a uniform thickness may be formed on the physically exposed side surface to provide a uniform negatively charged film, which may be advantageously used to reduce dark current and white pixels. |
| US11404464B2 |
Image sensing device and method of forming the same
An image sensing device is provided. The image sensing device includes a substrate, a plurality of photosensitive elements, a dielectric layer, a reflector, a color filter, and a microlens structure. The substrate has a first pixel and a second pixel adjacent to the first pixel, and the substrate has a front side and a back side opposite the front side. The photosensitive elements are disposed in the substrate. The dielectric layer is disposed on the back side of the substrate. The reflection is disposed on the front side of the substrate and has a parabolic surface. The color filter layer is disposed on the dielectric layer. The microlens structure is disposed on the color filter layer. |
| US11404462B2 |
Imaging element and imaging apparatus
Image quality of an imaging element having a configuration in which pixels having color filters are arranged two-dimensionally is prevented from being lowered. An imaging element includes a plurality of pixels and incident light attenuation sections. The pixel includes a color filter transmitting incident light having a predetermined wavelength, and a photoelectric conversion section that produces an electric charge according to the light transmitted through the color filter. The incident light attenuation section is disposed between the color filters of the adjacent pixels, is configured to be different in surface height from the color filters, and attenuates light not transmitted through the color filter but incident on the photoelectric conversion section of the pixel where the color filter is disposed. |
| US11404457B2 |
Image sensor
An image sensor may include a substrate including a plurality of unit pixel regions and having first and second surfaces facing each other. Each of the unit pixel regions may include a plurality of floating diffusion parts spaced apart from each other in the substrate, storage nodes provided in the substrate to be spaced apart from and facing the floating diffusion parts, a transfer gate adjacent to a region between the floating diffusion parts and the storage nodes, and photoelectric conversion parts sequentially stacked on one of the first and second surfaces. Each of the photoelectric conversion parts may include common and pixel electrodes respectively provided on top and bottom surfaces thereof and each pixel electrode may be electrically connected to a corresponding one of the storage nodes. |
| US11404456B2 |
Photoelectric conversion device
A photoelectric conversion device includes a pixel area, the pixel area including a plurality of pixels arranged in a matrix, each pixel comprising a photoelectric conversion portion, a floating diffusion, and a transfer gate, the transfer gate controlling transfer of charges generated in the photoelectric conversion portion to the floating diffusion. The photoelectric conversion portion is shifted relatively to the transfer gate depending on a position thereof in the pixel area. The shifting direction is a direction perpendicular to a charge transfer direction from the photoelectric conversion portion to the floating diffusion. |
| US11404454B2 |
Image sensing device
An image sensing device includes a sensing module, a moving module, and an invisible light transmitter. The sensing module includes several pixel sets. Each of the pixel sets includes several sub-pixels and one or more invisible light sensor. The sub-pixels and the invisible light sensor are arranged into an array. The moving module is connected to the sensing module. The moving module is used to move the sensing module. The invisible light transmitter is disposed corresponding to the sensing module. The invisible light sensor is used to sense an invisible light transmitted from the invisible light transmitter. |
| US11404452B2 |
Display panel and manufacturing method thereof
A manufacturing method of a display panel comprises: providing a first substrate; forming active switches on the first substrate; providing a second substrate disposed opposite to the first substrate; forming a color filter layer on the first substrate or the second substrate; and forming at least one spacer unit on the first substrate or the second substrate. The spacer unit comprises a photosensitive spacer material comprising two different wavelengths of light initiators. |
| US11404448B2 |
Display substrate, manufacturing method thereof, and display device
A display substrate, a manufacturing method thereof, and a display device are disclosed. The display substrate includes: a base substrate, the base substrate includes a bonding region; and a connection terminal located in the bonding region of the base substrate, the connection terminal includes a first conductive layer and a second conductive layer being in contact with each other, the first conductive layer and the second conductive layer are overlapped with each other in a direction perpendicular to the base substrate. |
| US11404446B2 |
Display panel, gate electrode driving circuit, and electronic device
A display panel, a gate electrode driving circuit, and an electronic device are provided. The display panel includes a first metal layer including a first gate electrode; a second metal layer including a first source electrode, a first drain electrode, and a second gate electrode; two ends of a polycrystalline silicon semiconductor layer electrically connected to the first source electrode and the first drain electrode respectively; a third metal layer including a second source electrode and a second drain electrode; and two ends of a metal oxide semiconductor layer electrically connected to the second source electrode and the second drain electrode respectively. |
| US11404445B2 |
Display device and display driving method
The application provides a display device and a display driving method. The display device includes a display, a housing, and a camera module arranged between the display and the housing. The display panel comprises a first display area and a second display area. Orthographic projection of the camera module on the display is located in the first display area. Membrane structure in the first display area is composed of transparent materials. |
| US11404442B2 |
Protective structure and fabrication methods for the peripheral circuits of a three-dimensional memory
Embodiments of a semiconductor memory device include a substrate having a first region with peripheral devices, a second region with one or more memory arrays, and a third region between the first and the second regions. The semiconductor memory device also includes a protective structure for peripheral devices. The protective structure for peripheral devices of the semiconductor memory device includes a first dielectric layer and a barrier layer disposed on the first dielectric layer. The protective structure for peripheral devices of the semiconductor memory device further includes a dielectric spacer formed on a sidewall of the barrier layer and a sidewall of the first dielectric layer, wherein the protective structure is disposed over the first region and at least a portion of the third region. |
| US11404434B2 |
Three-dimensional semiconductor memory device
A semiconductor memory device includes horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other in a first direction. Memory structures are disposed on the horizontal patterns. The memory structures include source structures and electrode structures. A division structure is disposed between adjacent horizontal patterns in the first direction and is configured to separate the source structures of adjacent memory structures from each other. An etch stop pattern is disposed between the horizontal patterns at a level lower than a level of the source structures. The etch stop pattern is connected to a lower portion of the division structure. |
| US11404433B2 |
Vertical memory devices
A vertical memory device includes gate electrodes disposed on a substrate and spaced apart from each other in a vertical direction. A channel extends in the vertical direction and is positioned adjacent to the gate electrodes. A tunnel insulation pattern is disposed on a portion of an outer sidewall of the channel that is adjacent to each of the gate electrodes. Charge trapping pattern structures are disposed between the tunnel insulation pattern and each of the gate electrodes. Each of the charge trapping pattern structures includes upper and lower charge trapping patterns spaced apart from each other in the vertical direction. Blocking pattern structures are between the charge trapping patterns and each of the gate electrodes. A first portion of the channel that is adjacent to the tunnel insulation pattern has a thickness in a horizontal direction that is smaller than a thickness of other portions of the channel. |
| US11404430B2 |
Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a semiconductor substrate; a first conductor layer provided above the semiconductor substrate and including silicon; a plurality of second conductor layers provided above first conductor layer and stacked apart from each other in the first direction; and a first pillar extending in the first direction through the second conductor layers and including intersection portions where the first pillar intersects the second conductor layer, the intersection portions each functioning as a memory cell transistor, wherein the first conductor layer includes a first region which is in contact with the first pillar and includes at least one element of arsenic (As), phosphorus (P), carbon (C), or boron (B). |
| US11404429B2 |
Three-dimensional semiconductor memory devices
Three-dimensional (3D) semiconductor memory devices are provided. A 3D semiconductor memory device includes an electrode structure on a substrate. The electrode structure includes gate electrodes stacked on the substrate. The gate electrodes include electrode pad regions. The 3D semiconductor memory device includes a dummy vertical structure penetrating one of the electrode pad regions. The dummy vertical structure includes a dummy vertical semiconductor pattern and a contact pattern extending from a portion of the dummy vertical semiconductor pattern toward the substrate. |
| US11404424B2 |
Static random access memory with magnetic tunnel junction cells
Disclosed herein are related to a memory cell including magnetic tunneling junction (MTJ) devices. In one aspect, the memory cell includes a first layer including a first transistor and a second transistor. In one aspect, the first transistor and the second transistor are connected to each other in a cross-coupled configuration. A first drain structure of the first transistor may be electrically coupled to a first gate structure of the second transistor, and a second drain structure of the second transistor may be electrically coupled to a second gate structure of the first transistor. In one aspect, the memory cell includes a second layer including a first MTJ device electrically coupled to the first drain structure of the first transistor and a second MTJ device electrically coupled to the second drain structure of the second transistor. In one aspect, the second layer is above the first layer. |
| US11404421B2 |
Semiconductor storage device
A semiconductor storage device according to the present embodiment includes a plurality of first wires provided above a surface of a semiconductor substrate to extend in a first direction, and a plurality of second wires provided above the first wires to extend in a second direction crossing the first direction. A plurality of capacitor elements are arranged every other intersection region among intersection regions between the first wires and the second wires as viewed from above the surface of the semiconductor substrate. A plurality of transistors are provided above the capacitor elements to correspond thereto, respectively. A first distance between two of the capacitor elements, which are adjacent to each other in the first direction, is narrower than a second distance between two of the capacitor elements, which are adjacent to each other in the second direction. |
| US11404416B2 |
Low resistance fill metal layer material as stressor in metal gates
An Integrated Circuit (IC) device includes a first plurality of semiconductor layers over a substrate, a first gate dielectric layer and a first gate electrode. The first gate electrode includes a first fill metal layer and a work function metal layer disposed between the first gate dielectric layer and the first fill metal layer. The IC device further includes a second plurality of semiconductor layers over the substrate, a second gate dielectric layer and a second gate electrode. The second gate electrode includes a second fill metal layer directly contacting the second gate dielectric layer. A top surface of the second fill metal layer extends above a topmost layer of the second plurality of semiconductor layers. The material of the semiconductor layers has a midgap. The work function metal layer has a work function lower than the midgap. The fill metal layer has a work function higher than the midgap. |
| US11404414B2 |
Integrated device comprising transistor coupled to a dummy gate contact
An integrated device that includes a substrate, a first transistor located over the substrate, where the first transistor includes a gate. The integrated device includes a first gate contact coupled to the gate of the first transistor, where the first gate contact is configured to be electrically coupled to an interconnect of the integrated device. The integrated device includes a second gate contact coupled to the gate, where the second gate contact is directly electrically coupled to only the gate. |
| US11404410B2 |
Semiconductor device having different voltage regions
A semiconductor device includes a substrate having a first region and a second region, a first gate structure disposed on the substrate within the first region, a first S/D region, a first S/D contact, a second gate structure on the substrate within the second region, a second S/D region and a second S/D contact. The first S/D region is disposed in the substrate within the first region and beside the first gate structure. The first S/D contact is connected to the first S/D region. The second S/D region is disposed in the substrate within the second region and beside the second gate structure. The second S/D contact is connected to the second S/D region. The contact area between the second S/D region and the second S/D contact is larger than a contact area between the first S/D region and the first S/D contact. |
| US11404409B2 |
Electrostatic discharge protection circuit
An electrostatic discharge (ESD) protection circuit is coupled between first and second power supply buses. The ESD protection circuit includes a detection circuit; a pull-up circuit, coupled to the detection circuit, comprising at least a first n-type transistor; a pull-down circuit, coupled to the pull-up circuit, comprising at least a second n-type transistor; and a bypass circuit, coupled to the pull-up and pull-down circuits, wherein the detection circuit is configured to detect whether an ESD event is present on either the first or the second bus so as to cause the pull-up and pull-down circuits to selectively enable the bypass circuit for providing a discharging path between the first and second power supply buses. |
| US11404405B2 |
Semiconductor device including a repeater/buffer at upper metal routing layers and methods of manufacturing the same
A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include polycrystalline silicon. The upper metal routing layer M3 or higher may include cobalt. |
| US11404400B2 |
Micro LED based display panel
Light emitting structures and methods of fabrication are described. In an embodiment, LED coupons are transferred to a carrier substrate and then patterned to LED mesa structures. Patterning may be performed on heterogeneous groups of LED coupons with a common mask set. The LED mesa structure are then transferred in bulk to a display substrate. In an embodiment, a light emitting structure includes an arrangement of LEDs with different thickness, and corresponding bottom contacts with different thicknesses bonded to a display substrate. |
| US11404399B2 |
Chip transfer substrate, chip transfer device and chip transfer method
The present disclosure provides a chip transfer substrate, a chip transfer device and a chip transfer method. The chip transfer substrate includes a substrate, a plurality of bases spaced apart from each other on the substrate, the plurality of bases being configured to carry micro light emitting diodes (Micro LEDs) to be transferred and being movable on the substrate; and a plurality of distance adjusting components each arranged between two adjacent bases and configured to adjust a distance between the two adjacent bases. |
| US11404396B2 |
Semiconductor device comprising memory semiconductor chip in which memory cell is laminated on semiconductor substrate
This semiconductor device includes a memory semiconductor chip in which a plurality of memory cells are laminated on a semiconductor substrate, a planar buffer chip which is a semiconductor chip that comprises a plurality of buffer circuits which hold data read from the memory cell and data written to the memory cell and which output the held data in accordance with the number of bit lines of the plurality of memory cells, and an electrical connection structure which electrically connects the bit lines of the memory cells of the memory semiconductor chips and the buffer circuits of the planar buffer chips to each other in a thickness direction of the memory semiconductor chip and the planar buffer chip. The electrical connection structure electrically connects the bit lines of the plurality of memory cells in the thickness direction through a penetration electrode penetrating at least the plurality of memory cells in the thickness direction. |
| US11404393B2 |
Wire bonding method and wire bonding device
A wire bonding method includes bringing a capillary and a wire inserted through the capillary into pressure contact with a bonding point of a lead placed on an XY stage to bond the wire to the lead, including moving the XY stage in a state in which the capillary is in pressure contact with the lead to move the capillary along a movement locus including a plurality of arc portions. |
| US11404389B2 |
In-situ component fabrication of a highly efficient, high inductance air core inductor integrated into substrate packages
Embodiments include one or more air core inductors (ACIs) and a method of forming the ACIs. The ACI includes a first inductor loop on a substrate. The first inductor loop has a first line and a second line. The first line has a first thickness that is greater than a second thickness of the second line. The ACI also includes a dielectric over the substrate and the first and second lines. The first line has a top surface above a top surface of the second line. The ACI further includes a second inductor loop on the dielectric and the first inductor loop. The second inductor loop has is coupled to the top surface of the first line of the first inductor loop. The first inductor loop may also have a third thickness, where the third thickness is the distance between the top surfaces of the first and second line. |
| US11404386B2 |
Semiconductor device package and method of manufacturing the same
A semiconductor device package and manufacturing method thereof are provided. The semiconductor device package includes a first conductive structure, a second conductive structure, a connection element, a conductive member, an encapsulant and a binding layer. The first conductive structure includes a first circuit layer. The second conductive structure is disposed over the first conductive structure. The connection element is disposed on and electrically connected to the first circuit layer. The conductive member protrudes from the second conductive structure. The encapsulant is disposed between the first conductive structure and the second conductive structure. The binding layer is disposed between the second conductive structure and the encapsulant. |
| US11404382B2 |
Semiconductor package including an embedded semiconductor device
A semiconductor package is provided including a package substrate. The package substrate includes a substrate pattern and a substrate insulation layer at least partially surrounding the substrate pattern. The package substrate has a groove. An external connection terminal is disposed below the package substrate. An embedded semiconductor device is disposed within the groove of the package substrate. The embedded semiconductor device includes a first substrate. A first active layer is disposed on the first substrate. A first chip pad is disposed on the first active layer. A buried insulation layer is disposed within the groove of the package substrate and at least partially surrounds at least a portion of a lateral surface of the embedded semiconductor device. A mounted semiconductor device is disposed on the package substrate and is connected to the package substrate and the embedded semiconductor device. |
| US11404380B2 |
Semiconductor package structure and method for manufacturing the same
A semiconductor package structure includes at least one first semiconductor die, at least one second semiconductor die and an encapsulant. The first semiconductor die has a first surface and includes a plurality of first pillar structures disposed adjacent to the first surface. The second semiconductor die is electrically connected to the first semiconductor die. The encapsulant covers the first semiconductor die and the second semiconductor die. A lower surface of the encapsulant is substantially coplanar with an end surface of each of the first pillar structures and a surface of the second semiconductor die. |
| US11404376B2 |
Interconnection structure, fabricating method thereof, and semiconductor device using the same
A semiconductor device includes a semiconductor substrate, a contact region present in the semiconductor substrate, and a silicide present on a textured surface of the contact region. A plurality of sputter ions is present between the silicide and the contact region. Since the surface of the contact region is textured, the contact area provided by the silicide is increased accordingly, thus the resistance of an interconnection structure in the semiconductor device is reduced. |
| US11404367B2 |
Method for forming semiconductor device with self-aligned conductive features
A method for forming a semiconductor device structure is provided. The method includes forming a conductive layer over a semiconductor substrate and forming a sacrificial layer over the conductive layer. The method also includes partially removing the sacrificial layer to form a first dummy element. The method further includes etching the conductive layer with the first dummy element as an etching mask to form a conductive line. In addition, the method includes partially removing the first dummy element to form a second dummy element over the conductive line. The method also includes forming a dielectric layer to surround the conductive line and the second dummy element and removing the second dummy element to form a via hole exposing the conductive line. The method further includes forming a conductive via in the via hole. |
| US11404365B2 |
Direct attachment of capacitors to flip chip dies
An integrated circuit package includes a substrate, a flip chip die, and a capacitor. The flip chip die is attached to the substrate via die-to-substrate interconnects. The capacitor is attached to the flip chip die via capacitor-to-die interconnects so that the capacitor occupies a region between the flip chip die and the substrate. Such placement of the capacitor on a flip chip die has the advantage of reducing the distance between the capacitor and its core, thereby reducing unwanted line inductance and series resistance effects. Integrated circuit performance is thereby enhanced. |
| US11404364B2 |
Multi-layer embedded magnetic inductor coil
A microelectronics package comprises a substrate that comprises a dielectric and at least two conductor layers within the dielectric, and an inductor structure having a magnetic core at least partially within the dielectric and extending at least between a first conductor layer and a second conductor layer. The inductor structure comprises at least one conductor that extends horizontally at least partially within the magnetic core. The conductor extends in the z-direction within the magnetic core between the first conductor layer and the second conductor layer. One or more vias extend within the dielectric adjacent to the magnetic core between the first conductor layer and the second conductor layer. The conductor of the inductor has a length extending through the magnetic core that is greater than a width of the conductor. |
| US11404363B2 |
Connection terminal unit
A connection terminal unit that can be appropriately connected to terminal connection portions of a semiconductor module including a semiconductor element and that can reduce a projection area when seen in a direction orthogonal to a direction along a chip surface is realized. Connection terminal unit includes plurality of connection terminals facing and connected to plurality of terminal connection portions of semiconductor module, and terminal mold portion holding connection terminals. Terminal mold portion has abutment portion that abuts against semiconductor module or base material holding semiconductor module. Abutment portion has vertical abutment portion that abuts against semiconductor module or base material from vertical direction that is a direction in which connection terminals face terminal connection portions, and side abutment portion that abuts against semiconductor module or base material from at least two directions that are different from each other and intersect with vertical direction. |
| US11404357B2 |
Semiconductor device
A dielectric film is disposed on a semiconductor substrate, and a conductor including a bent section is arranged between the semiconductor substrate and the dielectric film. A pad is disposed on the dielectric film. The pad is covered with a protective film. The protective film has an opening through which an upper surface of the pad is exposed. The bent section in the conductor and the pad overlap each other as seen in plan view, and an inside corner and an outside corner in the bent section are chamfered. |
| US11404356B2 |
Electronic device with die pad and leads, and method of manufacturing
An electronic device includes an electronic component provided with a first electrode pad, a die pad including an obverse surface facing in a first direction with the electronic component mounted on the obverse surface, a first lead, a second lead, and a first connection member electrically connecting the first electrode pad and the first lead to each other. The first lead and the second lead are disposed, as viewed in the first direction, on a same side of the die pad in a second direction perpendicular to the first direction. The first lead includes a first pad portion and a first extended portion. The first connection member is bonded to the first pad portion. The first extended portion extends from the first pad portion up to a position located between the die pad and the second lead as viewed in the first direction. |
| US11404354B2 |
Power control modules
A power control module includes a power device having a first side and a second side opposite from the first. The power control module includes a printed wiring board (PWB) spaced apart from the first side of the power device. The PWB is electrically connected to the power device. A heat sink plate is soldered to a second side of the transistor for heat dissipation from the transistor. The PWB and/or the heat sink plate includes an access hole defined therein to allow for access to the transistor during assembly. A method of assembling a power control module includes soldering at least one lead of a power device to a printed wiring board (PWB), pushing the power device toward a heat sink plate, and soldering the power device to the heat sink plate. |
| US11404352B2 |
Semiconductor device with through-substrate via and its method of manufacture
A dielectric layer is arranged on a main surface of a semiconductor substrate, a metal layer providing a contact area is embedded in the dielectric layer, a top metal is arranged on an opposite main surface of the substrate, and an electrically conductive interconnection through the substrate, which comprises a plurality of metallizations arranged in a plurality of via holes, connects the contact area with the top metal. The plurality of metallizations is surrounded by an insulating layer penetrating the substrate. |
| US11404349B2 |
Multi-chip packages and sinterable paste for use with thermal interface materials
In some embodiments a semiconductor die package includes a package substrate, a plurality of dies each attached to the package substrate, a layer of a thermally conducting sintered paste over the top of each die, a layer of flexible polymer thermal interface material over the sintered paste, and a heat spreader over and thermally connected to the polymer thermal interface material. |
| US11404348B2 |
Semiconductor package carrier board, method for fabricating the same, and electronic package having the same
A semiconductor package carrier board, a method for fabricating the same, and an electronic package having the same are provided. The method includes forming on a circuit structure a graphene layer that acts as an insulation heat dissipating layer. Since the heat conductivity of the graphene layer is far greater than the heat conductivity of ink (about 0.4 W/m·k), which is used as solder resist, the heat of the semiconductor package carrier board can be conducted quickly, and thus can avoid the problem that the heat will be accumulated on the semiconductor package carrier board. |
| US11404345B2 |
Advanced integrated passive device (IPD) with thin-film heat spreader (TF-HS) layer for high power handling filters in transmit (TX) path
A semiconductor package is described. The semiconductor package includes a passive substrate and a first integrated passive device (IPD) in a first interlayer-dielectric (ILD) layer on the passive substrate. The semiconductor package also includes a second ILD layer on the first ILD layer. The semiconductor package further includes a second IPD in a third ILD layer on the second ILD layer. The semiconductor package also includes a thermal mitigation structure on inductive elements of the second IPD. |
| US11404342B2 |
Package structure comprising buffer layer for reducing thermal stress and method of forming the same
A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant. |
| US11404339B2 |
Fan out package with integrated peripheral devices and methods
A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices. |
| US11404335B2 |
Manufacturing method of carrier for semiconductor chip mounting thereon
A manufacturing method of a carrier for a semiconductor chip mounting thereon is provided. The method includes at least the following steps. A plurality of conductive connectors is formed on a fine redistribution structure to form a first portion, where the semiconductor chip is adapted to be mounted on the fine redistribution structure opposite to the conductive connectors. Each of the conductive connectors includes a bump and a solder cap formed on the bump, and the bump is directly connected to the fine redistribution structure. The first portion is disposed on a second portion, where the second portion includes a top redistribution structure directly connected to the solder cap and a second redistribution structure connected to the top redistribution structure, the first portion is disposed on the top redistribution structure, and a contact density of the top redistribution structure is denser than a contact density of the bottom redistribution structure. |
| US11404334B1 |
Testing circuit with shared testing pads located on the scribe line and testing method thereof
A testing circuit includes a command pad, a first circuit, a second circuit, a first latch, and a second latch. The command pad receives an operation command. The first integrated circuit performs a corresponding test operation according to the operation command and an internal selection signal. The second integrated circuit performs the corresponding test operation according to the operation command and an internal selection signal. The first latch provides the operation command to the first integrated circuit according to the internal selection signal. The second latch provides the operation command to the second integrated circuit according to the internal selection signal. |
| US11404330B2 |
Methods of detecting bonding between a bonding wire and a bonding location on a wire bonding machine
A method of determining a bonding status between wire and at least one bonding location of a semiconductor device is provided. The method includes the steps of: (a) bonding a portion of wire to at least one bonding location of a semiconductor device using a bonding tool of a wire bonding machine; and (b) detecting whether another portion of wire engaged with the bonding tool, and separate from the portion of wire, contacts the portion of wire in a predetermined height range, thereby determining if the portion of wire is bonded to the at least one bonding location. |
| US11404328B2 |
Semiconductor structure and manufacturing method thereof
The present disclosure provides a semiconductor structure and a manufacturing method thereof. The method includes: preparing a semiconductor substrate; sequentially forming an oxide layer and a sacrificial layer on the semiconductor substrate, the thickness of the oxide layer is a first thickness; forming a plurality of trenches in the semiconductor substrate, wherein the trenches extending from the sacrificial layer into the semiconductor substrate; forming an isolation dielectric layer on the plurality of trenches and the sacrificial layer, and removing the isolation dielectric layer on the sacrificial layer to form a plurality of isolation structures; forming a well region in the semiconductor substrate; processing the oxide layer by an etching process, so that the thickness of the oxide layer is equal to a second thickness, the first thickness is greater than the second thickness; and forming a polysilicon gate on the etched oxide layer. |
| US11404325B2 |
Silicon and silicon germanium nanowire formation
Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanostructure channels and NMOS transistors comprising silicon nanostructure channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanostructure channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanostructure channels for NMOS transistors. PMOS transistors having germanium nanostructure channels and NMOS transistors having silicon nanostructure channels are formed as part of a single fabrication process. |
| US11404317B2 |
Method for fabricating a semiconductor device including self-aligned top via formation at line ends
A method for fabricating a semiconductor device includes recessing a first odd hardmask and a first even hardmask to form recessed odd and even hardmasks, forming a first conductive hardmask including first conductive hardmask material on the recessed odd hardmask and a second conductive hardmask on the recessed even hardmask, and forming self-aligned vias at line ends corresponding to the first odd and even conductive lines based at least in part on the first and second conductive hardmasks. |
| US11404313B2 |
Selective tungsten deposition at low temperatures
Embodiments of the disclosure relate to methods of depositing tungsten. Some embodiments of the disclosure provide methods for depositing tungsten which are performed at relatively low temperatures. Some embodiments of the disclosure provide methods in which the ratio between reactant gasses is controlled. Some embodiments of the disclosure provide selective deposition of tungsten. Some embodiments of the disclosure provide methods for depositing tungsten films at a low temperature with relatively low roughness, stress and impurity levels. |
| US11404303B2 |
Cutting apparatus for cutting workpiece with cutting blade
A cutting apparatus for cutting a workpiece includes a cutting unit for cutting the workpiece with a cutting blade, a moving unit for moving the cutting unit, a delivery pad for delivering the workpiece, and a counterbalance assembly connected to the delivery pad, for applying a pull-up force to the delivery pad. The delivery pad holds the workpiece under suction while being mounted on the moving unit and delivers the workpiece by being moved by the moving unit while holding the workpiece under suction. |
| US11404302B2 |
Substrate susceptor using edge purging
A workpiece susceptor body can include a front face configured to support a workpiece, a back face opposite the front face, a workpiece contact zone at least partially forming a support boundary on an inner portion of the front face, and a plurality of axial channels disposed within the susceptor body. The workpiece contact zone can be disposed radially inward of an outer edge of a workpiece positioned on the front face in a processing configuration. Each of the plurality of axial channels may connect to corresponding openings extending into an outer portion of the front face. Each of the openings may be disposed radially outward of the workpiece contact zone of the susceptor body. |
| US11404295B2 |
Substrate processing apparatus
A substrate processing apparatus includes a container carrying in/out section on which a substrate conveyance container accommodating a substrate is placed; a processing unit that performs a process on the substrate; a conveyance space through which the substrate is conveyed; a substrate conveyor that conveys the substrate between the container carrying in/out section and the processing unit through the conveyance space; a first gas supply passage that supplies an atmosphere adjusting gas to the processing unit; a first gas discharge passage that discharges the atmosphere adjusting gas from the processing unit; a circulation passage that returns the atmosphere adjusting gas flowing out from the conveyance space to the conveyance space; a second gas supply passage that supplies the atmosphere adjusting gas to a circulation system constituted by the conveyance space and the circulation passage; and a second gas discharge passage that discharges the atmosphere adjusting gas from the circulation system. |
| US11404290B2 |
Method and apparatus for pulse gas delivery
In a pulse gas delivery system, a chamber is pre-charged to a prescribed pressure through an upstream valve. Thereafter, a downstream control valve is opened to control flow of the gas during a gas pulse. A dedicated controller may control the downstream control valve in a feedback loop during the pulse based on pressure and temperature detected during the pulse. |
| US11404286B2 |
Lead frame
A lead frame includes, as an outermost plating layer, a roughened silver plating layer having acicular projections and covering only top faces on the upper surface side of a lead frame substrate made of a copper-based material. The roughened silver plating layer has a crystal structure in which the crystal direction <101> occupies a largest proportion among the crystal directions <001>, <111>, and <101>. The lead frame can be manufactured with improved productivity owing to reduction in cost and operation time, and achieves remarkably high adhesion to sealing resin while keeping the total thickness of plating layers including the silver plating layer to be thin. |
| US11404283B2 |
Etching method
A method for etching a ruthenium film includes a first step of etching the ruthenium film by plasma processing using oxygen-containing gas, and a second step of etching the ruthenium film by plasma processing using chlorine-containing gas. The first step and the second step are alternately performed. In the first step and the second step, the ruthenium film is etched at a target control temperature for a target processing time that are determined based on a pre-obtained relation between an etching amount per one cycle including the first step and the second step as a set, a control temperature of the ruthenium film, and processing times of each of the first step and the second step. |
| US11404278B2 |
Optical component having variable depth gratings and method of formation
An optical grating component may include a substrate, and an optical grating, the optical grating being disposed on the substrate. The optical grating may include a plurality of angled structures, disposed at a non-zero angle of inclination with respect to a perpendicular to a plane of the substrate, wherein the plurality of angled structures are arranged to define a variable depth along a first direction, the first direction being parallel to the plane of the substrate. |
| US11404274B2 |
Source/drain structure for semiconductor device
The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over a first portion of the fin structure, and an epitaxial region formed in a second portion of the fin structure. The epitaxial region can include a first semiconductor layer and an n-type second semiconductor layer formed over the first semiconductor layer. A lattice constant of the first semiconductor layer can be greater than that of the second semiconductor layer. |
| US11404270B2 |
Microelectronic device substrate formed by additive process
A microelectronic device is formed by forming at least a portion of a substrate of the microelectronic device by one or more additive processes. The additive processes may be used to form semiconductor material of the substrate. The additive processes may also be used to form dielectric material structures or electrically conductive structures, such as metal structures, of the substrate. The additive processes are used to form structures of the substrate which would be costly or impractical to form using planar processes. In one aspect, the substrate may include multiple doped semiconductor elements, such as wells or buried layers, having different average doping densities, or depths below a component surface of the substrate. In another aspect, the substrate may include dielectric isolation structures with semiconductor material extending at least partway over and under the dielectric isolation structures. Other structures of the substrate are disclosed. |
| US11404269B2 |
Single crystal substrate with undulating ridges and silicon carbide substrate
A single crystal substrate is provided and is characterized in that the single crystal substrate has a foundation substrate provided with a plurality of first grooves, which include a first crystal face and a second crystal face opposed to the first crystal face in an inner face thereof, and the extending direction of which is a<110> direction, and a plurality of second grooves, the extending direction of which intersects with the first grooves, and in which the first grooves are formed in a displaced manner in a depth direction, and a transverse cross-sectional shape of the second groove is a shape in which straight lines are open at an opening angle less than 180°. Further, it is preferred that an angle formed by the first crystal face and the second crystal face is more than 70.6°. |
| US11404268B2 |
Method for growing GaN crystal and c-plane GaN substrate
A method for growing a GaN crystal suitable as a material of GaN substrates including C-plane GaN substrates includes: a first step of preparing a GaN seed having a nitrogen polar surface; a second step of arranging a pattern mask on the nitrogen polar surface of the GaN seed, the pattern mask being provided with a periodical opening pattern comprising linear openings and including intersections, the pattern mask being arranged such that longitudinal directions of at least part of the linear openings are within ±3° from a direction of an intersection line between the nitrogen polar surface and an M-plane; and a third step of ammonothermally growing a GaN crystal through the pattern mask such that a gap is formed between the GaN crystal and the pattern mask. |
| US11404264B2 |
Silicon doping for laser splash blockage
Semiconductor devices having silicon doping for laser splash protection, along with associated methods and systems, are disclosed herein. In one embodiment, a semiconductor device includes a silicon layer and a circuitry layer with a plurality of semiconductor devices. A doped silicon region is formed on a front side of the silicon layer upon which the circuitry layer is deposited. The doped silicon region is positioned under the circuitry layer. The doped silicon region has a dopant concentration of at least 1015 cm−3. |
| US11404259B2 |
Reliable and automatic mass spectral analysis
A method, mass spectrometer and computer readable medium for acquiring mass spectral data in raw profile; detecting presence of compounds and relevant time window; performing multivariate statistical analysis of raw profile data in a time window to determine compounds; obtaining separation time profiles for detected compounds containing respective time locations in a time window; and computing pure mass spectra for compounds based on separation time profiles or time locations. A method, mass spectrometer and computer readable medium for acquiring mass spectral data in raw profile of a known and unknown sample; combining mass spectral scans for a sample into a single mass spectrum across a separation time window; performing multivariate statistical analysis of the acquired mass spectral data and computing a distance measure between the known and unknown sample; and using the distance measure as an indication for an unknown sample belonging to a known sample or sample group. |
| US11404255B2 |
Sputtering method and sputtering apparatus
A sputtering method including: performing a pre-sputtering by emitting sputter particles from a target provided in a sputtering apparatus in a state where the target is shielded by a shielding portion of a shutter provided closed to the target to be capable of opening/closing the target; and, after the pre-sputtering, performing a main-sputtering by emitting the sputter particles from the target in a state where an opening of the shutter is aligned with the target thereby depositing the sputter particles on a substrate. When the pre-sputtering and the main-sputtering are repeatedly performed, a shutter position is changed during the pre-sputtering so as to change a position of the shielding portion aligned with the target. |
| US11404254B2 |
Insertable target holder for solid dopant materials
An ion source with an insertable target holder for holding a solid dopant material is disclosed. The insertable target holder includes a pocket or cavity into which the solid dopant material is disposed. When the solid dopant material melts, it remains contained within the pocket, thus not damaging or degrading the arc chamber. Additionally, the target holder can be moved from one or more positions where the pocket is at least partially in the arc chamber to one or more positions where the pocket is entirely outside the arc chamber. In certain embodiments, a sleeve may be used to cover at least a portion of the open top of the pocket. |
| US11404253B2 |
Plasma processing apparatus and analysis method for analyzing plasma processing data
According to the present invention, a plasma processing apparatus includes an analysis unit that obtains wavelengths of the light correlated with a plasma processing result, selects, from the obtained wavelengths, a wavelength having a first factor that represents a deviation in an intensity distribution of the light and is larger than a first predetermined value, and predicts the plasma processing result using the selected wavelength, or an analysis unit that obtains values computed using each of light intensities of a plurality of wavelengths and correlated with the plasma processing result, selects, from the obtained values, a value having a second factor that represents a deviation in a distribution of the obtained values and is larger than a second predetermined value, and predicts the plasma processing result using the selected value. |
| US11404249B2 |
Substrate processing apparatus
A substrate processing apparatus includes a process chamber, a stage that is disposed in the process chamber and on which a substrate is placeable, a moving mechanism, and a focus ring. The focus ring is disposed on the stage and includes an inner focus ring disposed close to the substrate placed on the stage, a middle focus ring that is disposed outside of the inner focus ring and is movable in a vertical direction by the moving mechanism, and an outer focus ring that is disposed outside of the middle focus ring. |
| US11404247B2 |
Ion current droop compensation
In some embodiments, a high voltage power supply is disclosed that provides a plurality of high voltage pulses without any voltage droop between two subsequent pulses. In some embodiments, a high voltage power supply is disclosed that provides a waveform of voltage versus time having a plurality of high voltage pulses having a voltage greater than 1 kV and with a substantially flat portion between pulse. In some embodiments, a high voltage power supply is disclosed that includes a snubber with a snubber resistor having a resistance of about 7.5 mΩ-1.25Ω; and a snubber capacitor having a capacitance of about 2 μF-35 μF. |
| US11404246B2 |
Nanosecond pulser bias compensation with correction
Some embodiments include a high voltage pulsing circuit comprising: a high voltage pulsing power supply; a transformer electrically coupled with the high voltage pulsing power supply; an output electrically coupled with the transformer and configured to output high voltage pulses with an amplitude greater than 1 kV and a pulse repetition frequency greater than 1 kHz; a bias compensation circuit arranged in parallel with the output the bias compensation circuit comprising; first inductance comprising the inductive elements and any stray inductance between the bias compensation circuit and the high voltage pulsing power supply; and second inductance comprising the inductive elements and any stray inductance between the bias compensation circuit and the output. |
| US11404244B1 |
High-resolution x-ray spectroscopy surface material analysis
A method of performing x-ray spectroscopy surface material analysis of a region of interest of a sample with an evaluation system that includes a scanning electron microscope (SEM) column and an x-ray detector, the method comprising: identifying an element expected to be within the region of interest; selecting a landing energy for a charged particle beam generated by the SEM column based on the identified element; scanning the region of interest with a charged particle beam set to the selected landing energy; detecting x-rays generated while the region of interest is scanned by the charged particle beam; and generating a two-dimensional image of the scanned region of interest based on the detected x-rays. |
| US11404240B2 |
Inspection devices and methods of inspecting a sample
According to various embodiments, an inspection device may include a chamber, a stage provided within the chamber, an electron emitter, a laser emitter, and a conductive probe. The stage may be configured to hold a sample. The electron emitter may be configured to emit an electron beam towards the stage, to generate a first electrical signal in the sample. The laser emitter may be configured to emit a laser beam towards the stage, to generate a second electrical signal in the sample. The conductive probe may be configured to receive from the conductive structure, at least one of the first electrical signal and the second electrical signal. |
| US11404236B2 |
X-ray tube
Provided is an X-ray tube. The X-ray tube includes a cathode electrode, an anode electrode vertically spaced apart from the cathode electrode, an emitter on the cathode electrode, a gate electrode disposed between the cathode electrode and the anode electrode, the gate electrode including an opening at a position corresponding to the emitter, and a spacer provided between the gate electrode and the anode electrode. The spacer includes an insulator and conductive dopants doped in the insulator. |
| US11404230B2 |
Fixing structure between metal part and plastic parts of relay/circuit breaker
The disclosure provides fixing structure between a metal part and a plastic part of a relay/circuit breaker, comprising a metal part, a first plastic part and a second plastic part. A positioning groove is disposed on the first plastic part, one portion of the metal part is inserted and positioned in the positioning groove, and the other portion of the metal part is positioned between the first plastic part, and the second plastic part; a through hole is disposed at the second plastic part near to the positioning groove, glue is dispensed into the positioning groove though the through hole. A first glue blocking rib suitably fitting with a corresponding side of the other portion is respectively disposed at a position of the first plastic part corresponding to both sides of the positioning groove to prevent the glue from following to an inside of the relay/circuit breaker. |
| US11404228B2 |
Smart acoustical electrical switch
An electrical switch responds to acoustic inputs. A microphone integrated into the electrical switch generates electrical signals in response to the acoustic inputs. A network interface integrated into the electrical switch provides addressable communication with controllers, computers, and other networked devices. The electrical switch may thus be installed or retrofitted into the electrical wiring of all homes and businesses. Users may thus speak voice commands, which are received by the electrical switch and sent for voice control of appliances and other automation tasks. |
| US11404227B1 |
Keyboard device
A keyboard device includes a casing and at least one supporting leg. The supporting leg includes a first supporting part, a second supporting part and a pivotal shaft. The supporting leg is pivotally coupled to an accommodation space of the casing through the pivotal shaft. The pivotal shaft is rotatable relative to the casing. Consequently, the supporting leg can be switched between a stored state and a supporting state. When the supporting leg is in the stored state, the supporting leg is accommodated within the accommodation space, and the accommodation space is covered by the first supporting part and the second supporting part. While the supporting leg is switched from the stored state to the supporting state, the first supporting part is pushed into the accommodation space in response to an external force, and the second supporting part is correspondingly moved away from the accommodation space. |
| US11404225B2 |
Low-voltage circuit breaker
A low-voltage circuit breaker comprising one or more electrical poles, each of said poles having an internal space with a contact area and an arc extinguishing area, a fixed contact assembly and a movable contact assembly being positioned in said contact area, said movable contact assembly being movable between a closed position in which it is into contact with said fixed contact assembly and an open position in which it is spaced apart from said fixed contact assembly, an arc chamber comprising a plurality of substantially parallel arc-breaking plates made of a ferromagnetic material being positioned in said arc extinguishing area. The low-voltage circuit breaker is characterized in that said arc chamber further comprises at least one arc-breaking plate which is at least partially made of a ceramic material. |
| US11404221B2 |
Electrolytic capacitor module, filter circuit and power converter
An electrolytic capacitor module includes at least two types of electrolytic capacitors (4-1, 4-2) having etching pits in electrode foils. The at least two types of electrolytic capacitors (4-1, 4-2) are different in length of the etching pits and are connected in parallel. The number of electrolytic capacitors to be mounted is the same or different. The electrolytic capacitors (4-1, 4-2) are each an electrolytic capacitor with an etching pit length of 27 [μm] or less or an electrolytic capacitor with an etching pit length over 27 [μm]. Such a configuration enhances performance of the electrolytic capacitors in a high-frequency region, keeps a rate of decrease in capacitance low in the high-frequency region, and enhances a ripple current capability in the high-frequency region. |
| US11404220B2 |
Solid electrolytic capacitor containing a barrier coating
A solid electrolytic capacitor comprising a capacitor element, anode lead extending from a surface of the capacitor element, an anode termination that is in electrical connection with the anode lead, a cathode termination that is in electrical connection with the solid electrolyte, and a casing material that encapsulates the capacitor element and anode lead is provided. A barrier coating is disposed on at least a portion of the anode termination and/or cathode termination and is in contact with the casing material. The coating contains a hydrophobic resinous material that includes an olefin polymer having a glass transition temperature of from about 20° C. to about 160° C. |
| US11404219B2 |
Electrolytic capacitor with improved connection part
In an embodiment an electrolytic capacitor includes a covering element configured to close an opening of a can comprising a capacitor element. A connection element comprises a lead tab for applying an electrical signal to the capacitor element and a rivet having a first head to fix the lead tab to the covering element. The connection element includes an upper washer arranged between the first head of the rivet and the lead tab. The lead tab has a first section having a first opening and a second section having a second opening. The lead tab is folded such that the first opening and the second opening of the lead tab are arranged above each other. The rivet is arranged in the first and second openings of the lead tab and in an opening of the upper washer. |
| US11404215B2 |
Capacitor
A capacitor is disclosed. In an embodiment a capacitor includes at least two winding elements, a first busbar and a second busbar, wherein the first busbar and the second busbar connect the winding elements in parallel to each other, and wherein the first busbar and the second busbar are arranged such that they overlap each other. |
| US11404214B2 |
Multilayer ceramic capacitor
When internal electrode layers are viewed in a stacking direction, the internal electrode layers include an internal electrode main body portion defining an effective region, and an internal electrode lead-out portion that leads to a first or second end surface of a stacked body, and a length of the internal electrode lead-out portion in a width direction of the stacked body is less than or equal to about ½ of a length of the internal electrode main body portion. The internal electrode layer includes a first region having relatively high continuity of a conductive component defining the internal electrode layer, and a second region having relatively continuity of the conductive component. A central portion of the internal electrode main body portion is defined by the first region, and a portion of the internal electrode lead-out portion is defined by the second region. |
| US11404206B2 |
Monitoring system
A monitoring system is described which comprises a sensor device for generating sensor data, the sensor device having a secondary coil, and a receiver device having a controller, and a primary coil for wirelessly communicating with the sensor device, the receiver device being operable to wirelessly charge the sensor device via inductive coupling between the primary and secondary coils. A quality factor of the primary coil is controllable, and the controller is operable to control the quality factor of the primary coil to be higher when the receiver device is wirelessly charging the sensor device than when the receiver device is receiving sensor data from the sensor device. As a result, the same coil can be used both for efficient power transfer (wireless charging) by using the coil in a (relatively) high quality factor mode, and for reliable data communications by using the coil in a (relatively) low quality factor mode. |
| US11404203B2 |
Magnetic unit and an associated method thereof
A magnetic unit is presented. The magnetic unit includes a magnetic core. The magnetic core includes a first limb and a second limb disposed proximate to the first limb, where a gap is formed between the first limb and the second limb. The magnetic unit further includes a first winding wound on the first limb. Moreover, the magnetic unit includes a conductive element disposed facing an outer periphery of the first winding, where the conductive element is configured to control a fringing flux generated at the gap. Further, the magnetic unit includes a heat sink operatively coupled to the conductive element, where the conductive element is further configured to transfer heat from at least one of the conductive element and the first winding to the heat sink. Moreover, a high frequency power conversion system and a method of operation of the magnetic unit is also presented. |
| US11404202B2 |
Planar transformer and DC-DC converter
A planar transformer includes: a primary side planar air core coil; a secondary side planar air core coil; a primary side planar core; and a secondary side planar core. The secondary side planar air core coil is arranged so as to be spaced from the primary side planar air core coil in the winding center axis direction of the primary side planar air core coil, the secondary side planar air core coil having a non-facing portion configured not to face the primary side planar air core coil in the winding center axis direction. The primary side planar core and the secondary side planar core are stacked on outer sides of the primary side planar air core coil and the secondary side planar air core coil in the directions of the winding center axes, respectively. |
| US11404199B2 |
Inductor
An inductor includes a coil having a winding portion of a conductor wound in a two-stage spiral shape and an extended portion extended from the winding portion, an element body containing the coil, and an outer electrode. The winding portion is arranged such that a winding axis intersects a first pair of surfaces, is substantially orthogonal to the first pair of surfaces as viewed from a second pair of surface side, and intersects a normal line on the first pair of surfaces as viewed from a third pair of surfaces side. Respective pairs of surfaces are opposed to one another, and the winding axis is inclined in a direction where an exposed portion exposed on a surface of the element body is positioned closer to an intermediate surface at an equal distance from respective first pair of surfaces relative to the normal line on the first pair of surfaces. |
| US11404198B2 |
Reactor
Provided is a reactor including a coil provided with two winding portions that are obtained by winding a winding wire such that axes of the winding portions are parallel to each other, and a magnetic core including a rectangular parallelepiped inner core portion disposed in each of the winding portions, and outer core portions that are disposed outside the winding portions and are for linking the inner core portions, in which at least one of two outer corner portions out of four corner portions of each of the inner core portions includes a corner chamfering portion that has been chamfered more than an inner corner portion that is opposite the outer corner portion, the four corner portions facing an inner circumferential surface of the winding portion and the two outer corner portions being disposed on the side of each winding portion that is distant from the other winding portion. |
| US11404197B2 |
Via for magnetic core of inductive component
Techniques for fabricating low-loss magnetic vias within a magnetic core are provided. According to some embodiments, vias with small, well-defined sizes may be fabricated without reliance on precise alignment of layers. According to some embodiments, a magnetic core including a low-loss magnetic via can be wrapped around conductive coils of an inductor. The low-loss magnetic vias can improve performance of an inductive component by improving the quality factor relative to higher loss magnetic vias. |
| US11404195B2 |
Reactor
Provided is a reactor that includes: a coil provided with a wound portion that is obtained by winding a winding wire, and has an exposed region with which a liquid coolant comes into direct contact; a magnetic core that is arranged inside and outside the wound portion, and forms a closed magnetic circuit; a sensor member configured to measure the temperature of the coil, the sensor member including a rod-shaped sensor body portion attached to the exposed region of the wound portion, and a wire coupled to the sensor body portion; and a sensor cover portion that covers surfaces of the outer periphery of the sensor body portion, except for a mounting surface for mounting to the wound portion and at least part of a coupling surface to which the wire is coupled. |
| US11404194B2 |
Transformer
A transformer includes a transformer body, a tank, a conservator, a plurality of support fittings, and at least one mounting seat. Transformer body includes an iron core and a winding. Tank includes an upper tank, a middle tank, and a lower tank that are bonded together to form an internal space accommodating transformer body. Conservator is arranged at a position above tank. The plurality of support fittings are arranged side by side at intervals to support conservator. At least one mounting seat is bonded to both a peripheral wall of upper tank and a peripheral wall of middle tank, and fixed to tank, and the plurality of support fittings are attached. |
| US11404189B2 |
Non-oriented electrical steel sheet and method for manufacturing the same
A non-oriented electrical steel sheet produced by hot rolling a steel slab containing, by mass %, C: not more than 0.0050, Si: 3.2 to 4.5%, Mn: 0.1 to 2.0%, P: not more than 0.020%, As: not more than 0.0030%, Sn+Sb: 0.005 to 0.10%, and one or two elements selected from Mo and W by a content ranging from 0.0020 to 0.10% in total, subjecting the resultant steel sheet to one cold rolling or two or more cold rollings including an intermediate annealing therebetween to achieve a final sheet thickness, and then subjecting the cold rolled sheet to finish annealing, a N2 content in an atmosphere in the finish annealing is set to not more than 20 vol %, and average strain rate in the first pass is set to not more than 4/sec, allowing the cold rolling property to improve with no degradation in magnetic property and no decrease in productivity. |
| US11404188B2 |
Calcined ferrite, and sintered ferrite magnet and its production method
A sintered ferrite magnet having a composition of metal elements of Ca, R, A, Fe and Co, which is represented by the general formula of Ca1-x-yRxAyFe2n-zCoz, wherein R is at least one of rare earth elements indispensably including La; A is Sr and/or Ba; x, y, z and n represent the atomic ratios of Ca, R, A, Fe and Co; 2n represents a molar ratio expressed by 2n=(Fe+Co)/(Ca+R+A); and x, y, z and n meet the conditions of 0.15≤x≤0.35, 0.05≤y≤0.40, (1-x-y)>y, 0 |
| US11404183B2 |
Apparatus for robotically routing wires on a harness form board
Apparatus for robot motion control and wire dispensing during automated routing of wires onto harness form boards. The robot includes a manipulator arm and a wire-routing end effector mounted to a distal end of the manipulator arm. The wire-routing end effector is configured for dispensing and routing a wire along a path through form board devices mounted to a harness form board. The wire-routing end effector is moved along a planned path under the control of a robot controller. An end effector path is provided with a set of processes that enable rapid, even fully automatic, development of robot motion controls for routing wires on harness form boards. The system uses a measurement encoder on the end effector that is routing individual wires on a wire harness form board to learn the length of each wire and its length variation. |
| US11404182B2 |
Conductive composite structure for electronic device, method of preparing the same, electrode for electronic device including the conductive composite structure, and electronic device including the conductive composite structure
Provided are a conductive composite structure for an electronic device, a method of preparing the conductive composite structure, an electrode for an electronic device including the conductive composite structure, and an electronic device including the conductive composite structure. The conductive composite structure may contain graphene and an organic composite layer including a conductive polymer having a work function of about 5.3 eV or lower, and has a sheet resistance deviation of about 10% or less. |
| US11404174B2 |
System and method for generating plasma and sustaining plasma magnetic field
A system for generating magnetized plasma and sustaining plasma's magnetic field comprises a plasma generator for generating magnetized plasma and a flux conserver in which the generated magnetized plasma is injected and confined. A central conductor comprises an upper central conductor and a lower central conductor that are electrically connected forming a single integrated conductor. The upper central conductor and an outer electrode form an annular plasma propagating channel. The lower central conductor extends out of the plasma generator and into the flux conserver such that an end of the inner electrode is electrically connected to a wall of the flux conserver. A power system provides a formation current pulse and a sustainment current pulse to the central conductor to form the magnetized plasma, inject such plasma into the flux conserver and sustain plasma's magnetic field. |
| US11404173B2 |
Double poloidal field coils
A poloidal field coil assembly for use in a tokamak. The poloidal field coil assembly comprises inner and outer poloidal field coils and a controller. The inner poloidal field coil is configured for installation inside a toroidal field coil of the tokamak. The outer poloidal field coil is configured for installation outside the toroidal field coil. The controller is configured to cause current to be supplied to the inner and outer poloidal field coils such that the combined magnetic field produced by the inner and outer poloidal field coils has a null at the toroidal field coil. |
| US11404163B2 |
Ventilation system
A ventilator system includes a ventilation device, and is configured to operate in a passive mode configured to transmit ventilation data in response to requests from a ventilation management system, or an active mode configured to automatically transmit ventilation data as the data becomes available. The system receives ventilation system data associated with operation of the ventilation device, modifies one or more operating parameters of the ventilation device based on the received ventilation system data, receives ventilator data associated with the ventilator device, determines an alarm associated with the ventilator device or a patient based on the received ventilator data and, responsive to determining the alarm, sends the alarm to a beginning of a transmission queue for transmitting the ventilation data to the ventilation management system, wherein the alarm is communicated over the network prior to other ventilation data in the transmission queue. |
| US11404160B2 |
Method and system for managing and editing data of a medical device
The invention relates to a method and to a system for managing and editing data of a medical device (2, 2′). According to the invention, separate memory areas (22-25) in a cloud storage (19) of a public cloud (13) are provided for at least two different types of medical data sets (P, W, C, B). The data sets (P, W, C, B) stored in a particular memory area (22-25) are each held available in such a way that said data sets (P, W, C, B) can be directly accessed from the Internet (16) if a subscription (18, 18) associated with the memory area (22-25) exists. In addition, at least one specifically associated application (31-34, 94, 95) for running on a user device (8, 9, 11, 12) is provided for each memory area (22-25), said application being designed to retrieve and/or display the data sets (P, W, C, B) contained in the associated memory area (22-25). |
| US11404157B2 |
Health information mapping system
A mapping system provides a graphical editor, consisting of a visual channel editor and a node configuration panel, for graphically defining channels for processing messages. Within the visual channel editor, the user is able to create a graphical representation of a channel by interconnecting representations of a source node, mapping nodes, condition nodes, and destination nodes. When a node is selected in the visual channel editor, the node configuration panel displays user interface controls in which the user specifies parameters for the selected node. The mapping system automatically generates scripts for implementing the functionality defined by the user input. In this manner, a user need not have any knowledge of scripting to define mappings to apply to messages. The mapping system may be used to perform mappings of messages of virtually any type, but has specific applicability to mapping messages between Health Information Technology (HIT) systems. |
| US11404154B2 |
Activity trends and workouts
The present disclosure generally relates to computer user interfaces, and more specifically to techniques for presenting activity trends and managing workouts. |
| US11404150B2 |
System and method for processing medical claims using biometric signatures
A computer-implemented system for processing medical claims is disclosed. The computer-implemented system includes a medical device configured to be manipulated by a user while the user performs a treatment plan; a patient interface associated with the medical device, the patient interface comprising an output configured to present telemedicine information associated with a telemedicine session; and a processor. The processor is configured to, during the telemedicine session, receive device-generated information from the medical device; generate a first biometric signature; using the device-generated information, generate a second biometric signature; using the first and second biometric signatures, generate a signature comparison; using the signature comparison, generate a signature indicator; and transmit the signature indicator. |
| US11404146B2 |
Managing user information—data type extension
Systems, methods, and computer-readable medium are provided for managing user information. For example, instructions for implementing a background process configured to manage a first set of data types may be received from a service provider. A data download that includes information about the new data type may also be received from the service provider. A request to access data corresponding to the new data type may be received from an application. Additionally, in some examples, the data corresponding to the new data type may be provided to the application based at least in part on interpreting the data download. |
| US11404143B2 |
Method and systems for the indexing of bioinformatics data
Method and apparatus for the indexing of genome sequence data produced by genome sequencing machines. The proposed method can be applied both to raw sequence data produced by sequencing machines and to those sequence reads that cannot be mapped on any reference sequence according to specific matching criteria. This invention describes a method to partition and index unaligned sequence reads to enable browsing and efficient selective access. |
| US11404137B1 |
Memory system and operating method of memory system
Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, a memory system may include a main core for executing an operation of a first layer and a plurality of sub-cores for executing an operation of a second layer, and the main core may control, when executing a shutdown command received from a host, the plurality of sub-cores so that a second sub-core stores a meta data segment to be processed by a first sub-core among the plurality of sub-cores. |
| US11404133B1 |
Valid translation unit count-based memory management
A method includes determining a first valid translation unit count (VTC) for a first block of memory cells, determining a second VTC for a second block of memory cells when the first VTC is below a VTC threshold corresponding to performance of a memory management operation, consolidating the first VTC and the second VTC when the consolidated first VTC and the second VTC equal or exceed the VTC threshold corresponding to the performance of the memory management operation, and executing the memory management operation utilizing the consolidated first VTC and the second VTC. |
| US11404131B2 |
Decision for executing full-memory refresh during memory sub-system power-on stage
A system includes a plurality of memory devices and a processing device (e.g., a controller), operatively coupled to the plurality of memory devices. The processing device is to detect a power-on of the system and determine a read-retry trigger rate (TR) of a subset of codewords of the plurality of memory devices during a time interval after an initialization of the memory component. The processing device is further to determine whether the TR satisfies a threshold criterion. In response to the TR not satisfying the threshold criterion, the processing device is to initialize a full-memory refresh of the plurality of memory devices. |
| US11404129B1 |
Power architecture for non-volatile memory
Methods, systems, and devices for power architecture for non-volatile memory are described. A memory device may be configured to operate in a first mode and a second mode (e.g., a low power mode). When operating in the first mode, a voltage may be supplied from a power source (e.g., a power management integrated circuit) to a memory array and one or more associated components via a regulator. When the memory device transitions to operate in the second mode, some of the components supplied from the power source may be powered by a charge pump. Control information associated with the memory array may be stored to the one or more components (e.g., to a cache) that are powered by a charge pump. |
| US11404124B2 |
Voltage bin boundary calibration at memory device power up
A first current bin boundary for a first voltage bin on a first target die of a set of dies at a memory device is identified by accessing a block family metadata table including an entry for each block family of a memory device. The first current bin boundary corresponds to a first block family associated with the first voltage bin. A first bin boundary offset between the first block family and a second block family corresponding to a first new bin boundary for the first voltage bin is determined. The first bin boundary is determined based on a calibration scan performed for the first voltage bin. A first new bin boundary for the first voltage bin is determined on each die of the set of dies based on the first bin boundary offset. |
| US11404122B2 |
Sub-block size reduction for 3D non-volatile memory
Systems and methods for reducing the size of sub-blocks within a physical memory block for a three-dimensional non-volatile memory using buried source lines are described. The physical memory block may be fabricated using dual buried source lines such that sub-blocks within the physical memory block may be individually selected in both a horizontal word line direction and a vertical NAND string direction. The physical memory block may include a plurality of sub-blocks that are individually selectable and that share bit lines and/or source-side select gate lines. The plurality of sub-blocks that are individually selectable may correspond with different portions of the same NAND string in which a first sub-block of the plurality of sub-blocks connects to a drain-side select gate for the NAND string and a second sub-block of the plurality of sub-blocks connects to a source-side select gate for the NAND string. |
| US11404121B2 |
Methods for writing ternary content addressable memory devices
Ternary content-addressable memory (TCAM) devices are described. The TCAMs described herein are designed to perform write operations—including data writes and mask writes—in a single clock cycle. For example, data input is written in a row of the TCAM during the first portion of a clock cycle, and a mask is written in another row of the TCAM during the second portion of the clock cycle. In one implementation, a first bus is used both for data write and key search operations, and a second bus is used both for mask write and search masking operations. In another implementation, a first bus is used both for data write and key search operations, a second bus is used for mask write operations, and a third bus is used for search masking operations. |
| US11404120B2 |
Refresh operation of a memory cell
Methods, systems, and devices for a refresh operation of a memory cell are described. A memory device may include a plurality of rows of memory cells. Each row of memory cells may undergo a quantity of access operations (e.g., read operations, write operations). During a read operation, a logic state of one or more memory cells may be determined by applying a read pulse having a first polarity. Based on the one or more memory cells storing a particular logic state (e.g., a first logic state), a refresh operation may be performed. During a refresh operation, a refresh pulse having a second polarity (e.g., a different polarity than the first polarity) may be applied to the one or more memory cells. |
| US11404119B1 |
Non-volatile memory device and challenge response method
A non-volatile memory device includes a data generation circuit and a reconfiguration processing circuit. The data generation circuit generates: third response data that is different from the first response data (PUF registration mode), when the reconfiguration writing is executed by the reconfiguration processing circuit and the first type of challenge data is obtained again after the reconfiguration writing is executed, after the first response data is generated; and fourth response data that is identical to the second response data (permanent PUF registration mode), when the reconfiguration writing is executed by the reconfiguration processing circuit and the second type of challenge data is obtained again after the reconfiguration writing is executed, after the second response data is generated. |
| US11404117B2 |
Self-selecting memory array with horizontal access lines
Methods, systems, and devices for self-selecting memory with horizontal access lines are described. A memory array may include first and second access lines extending in different directions. For example, a first access line may extend in a first direction, and a second access line may extend in a second direction. At each intersection, a plurality of memory cells may exist, and each plurality of memory cells may be in contact with a self-selecting material. Further, a dielectric material may be positioned between a first plurality of memory cells and a second plurality of memory cells in at least one direction. each cell group (e.g., a first and second plurality of memory cells) may be in contact with one of the first access lines and second access lines, respectively. |
| US11404116B2 |
Data storage based on data polarity
Methods, systems, and devices for storing and reading data at a memory device are described. A memory device may utilize one or more storage states to store data within a data word. The memory device may exhibit higher data leakage or more power consumption when storing or reading a first storage state compared to storing or reading one or more other storage states. In some cases, the memory device may generate a second data word corresponding to a first data word by modifying each symbol type of the first data word to generate a different symbol type for the second data word. A memory device may reduce the occurrence of a storage state associated with large data leakage, or high-power consumption, or both. Further, the memory device may generate and store an indicator indicating the transformation of a corresponding data word. |
| US11404115B2 |
Memory with write assist scheme
The disclosure introduces a write assist scheme that boost the word line of a selected memory cell by using a parasitic capacitor element coupled between the word line and a bit line of at least one unselected memory cell. The SRAM includes a word line, a first bit line, a second bit line, a first memory cell coupled to the first bit line and the word line, a second memory cell coupled to the second bit line and the word line, and a write assist circuit coupled to the second bit line. The write assist circuit is configured to clamp the second bit line to the word line during a write operation of the first memory cell. |
| US11404112B2 |
Low-voltage low-power memory device with read, write, hold, and standby assist voltages and operation method thereof
A memory device and an operation method thereof is disclosed. The memory device includes a static random access memory (SRAM) cell, a power-supply assist-voltage generator circuit, a source assist-voltage generator circuit, and a word-line assist-voltage generator circuit. The power-supply assist-voltage generator circuit, the source assist-voltage generator circuit, and the word-line assist-voltage generator circuit lower the effective supply voltage for un-accessed rows of memory cells in the hold mode, increase the effective supply voltage for accessed memory cells in the active mode, and lower the effective supply voltage further for all the SRAM cells in the standby mode to achieve a solution for active and standby power reduction besides achieving the stability and noise margins. |
| US11404111B2 |
Sensing techniques using a charge transfer device
Techniques are provided for sensing a signal associated with a memory cell capable of storing three or more logic states. To sense the memory cell (e.g., a signal associated with the memory cell), a charge may be transferred between a digit line and a node coupled with a plurality of sense components using a charge transfer device. Once the charge is transferred, at least some if not each of the plurality of sense components may sense the charge using one of a variety of sensing schemes. For example, the charge may be sensed by each sense component at a same time using a single fixed reference value, or at different times using different fixed reference values. Based on the charge being transferred or transferred with the node (e.g., using the charge transfer device) and each sense component sensing the charge, a logic state associated with the memory cell may be determined. |
| US11404110B2 |
Sense amplification device in memory
A sense amplification device is provided. The sense amplification device includes a first sense amplifier, a second sense amplifier, and a third sense amplifier. An input terminal of the first sense amplifier is coupled to a first bit line. An input terminal of the second sense amplifier is coupled to a second bit line. The third sense amplifier has a differential input pair and a differential output pair, wherein a first input terminal of the differential input pair is coupled to an output terminal of the first sense amplifier, a second input terminal of the differential input pair is coupled to an output terminal of the second sense amplifier, a first output terminal of the differential output pair is coupled to the input terminal of the first sense amplifier, and a second output terminal of the differential output pair is coupled to the input terminal of the second sense amplifier. |
| US11404106B2 |
Read only memory architecture for analog matrix operations
A read-only memory (ROM) computing unit utilized in matrix operations of a neural network comprising a unit element including one or more connections, wherein a weight associated with the computing unit is responsive to either a connection or lack of connection internal to the unit cell or between the unit element and a wordline and a bitline utilized to form an array of rows and columns in the ROM computing unit, and one or more passive or active electrical elements located in the unit element, wherein the passive or active electrical elements are configured to adjust the weight associated with the compute unit, wherein the ROM computing unit is configured to receive an input and output a value associated with the matrix operation, wherein the value is responsive to the input and weight. |
| US11404104B2 |
Semiconductor memory device capable of operating at high speed, low power environment by optimizing latency of read command and write command depending on various operation modes
A semiconductor memory device includes: a memory cell array including banks; a command/address buffer receiving a command/address based on a system clock; a data input/output circuit inputting/outputting data based on a data clock; a mode control circuit generating mode selection signals indicating different latencies according to a burst length signal and operation information on a first operation mode differentiated based on a ratio of the data clock to the system clock, and a second operation mode differentiated based on a bank mode; and a latency setting circuit setting a latency according to an activated one of the mode selection signals, generating an internal write command by delaying a write command at least by the set latency according to the system clock during a write operation, and generating an internal read command by delaying a read command by the set latency according to the system clock during a read operation. |
| US11404101B2 |
Memory system and semiconductor storage device configured to discharge word line during abrupt power interrupt
A memory system includes a semiconductor storage device, a power supply circuit that generates a first power, and a memory controller that operates based on the first power and transmits a command to the semiconductor storage device. The semiconductor storage device includes a first terminal, a second terminal, a word line, a first circuit, and a second circuit. The first power is input to the first terminal. A second power that can be used even after a voltage of the first terminal decreases is input to the second terminal. The word line is connected to a control gate of a memory cell transistor. The first circuit applies a voltage according to the command to the word line based on the first power input to the first terminal. The second circuit discharges charges of the word line by using the second power input to the second terminal when a voltage of the first terminal decreases. |