| Document | Document Title |
|---|---|
| US11095460B2 |
Certificate application operations
Implementations of this disclosure provide for certificate application operations. An example method includes sending, from a terminal device, a subscription topic name to a gateway to establish a data transmission channel between the terminal device and the gateway; receiving by the terminal device, via the data transmission channel, a certificate installation instruction from a certificate server; generating, by the terminal device, a user certificate request based on the certificate installation instruction; sending the user certificate request to the certificate server; and receiving, via the data transmission channel, a user certificate from the certificate server. |
| US11095453B2 |
Communication network system and count-value sharing method using count-value notification node with transmission node and reception node
A communication network system, in which a transmission node for transmitting a message is connected to a reception node for receiving the message, is configured to periodically transmit a count-value notification message to notify a count value, which is used to generate and check a message authentication code for the message, to the transmission node and the reception node. |
| US11095448B2 |
HASSH profiling mechanism
Techniques and structures to facilitate identification, authentication, authorization and accounting of a computing device is disclosed. A set of supported algorithms for transmission during a secure shell (SSH) clear packet exchange is received and a cryptographic hash is performed on the set of algorithms to generate a unique fingerprint. |
| US11095447B2 |
Method for using cryptography and authentication methods and systems for carrying out said method
The invention relates to a method to initiate the use of cryptography and authentication methods and to perform these methods. The method comprises the steps of: generating a URI (410), calling (420) a communication component (120) using the generated URI and a proprietory URI scheme; performing (430) the cryptography and authentication method by the local communication component (120); generating (440) at least one result (440) by the communication component (120). |
| US11095446B2 |
Cryptoasset custodial system with different rules governing access to logically separated cryptoassets and proof-of-stake blockchain support
Methods, and systems for secure storage and retrieval of information, such as private keys, useable to control access to a blockchain, include: receiving a request to take an action with respect to a vault of multiple different vaults in a cryptoasset custodial system, and each of the multiple different vaults has an associated policy map that defines vault control rules;authenticating, by a hardware security module, a policy map for the vault on which the action is requested based on a cryptographic key controlled by the hardware security module; checking the action against the policy map for the vault when the policy map for the vault is authenticated based on the cryptographic key controlled by the hardware security module; and effecting the action when the action is confirmed to be in accordance with the policy map for the vault. |
| US11095443B1 |
Proof-of-work based on runtime compilation
Techniques are provided for proof-of-work based on runtime compilation. Key generation code is partitioned into a set of code blocks. The key generation code generates an expected key value when compiled and executed. A shuffled set of code blocks is generated by reordering the set of code blocks. A client computing device is provided the shuffled set of code blocks and problem-solving code that, when executed at the client computing device, reconstructs the key generation code to generate a submission value by performing one or more compiling iterations. Each compiling iteration comprising reordering the shuffled set of code blocks to generate test code, and attempting to compile and execute the test code to generate the submission value. It is determined that the client computing device fully executed the problem-solving code based on the verifying the submission value. |
| US11095439B1 |
Systems and methods for centralized quantum session authentication
Systems, apparatuses, methods, and computer program products are disclosed for session authentication. An example method includes determining a first set of quantum bases, generating a first control signal indicative of the first set of quantum bases, and transmitting the first control signal over a communications network to a qubit encoder. The example method further includes determining a second set of quantum bases, generating a second control signal indicative of the second set of quantum bases, and transmitting the second control signal over the communications network to a qubit decoder. The example method further includes generating a third control signal indicative of an instruction to encode a set of bits and transmitting the third control signal over the communications network to the qubit encoder. |
| US11095436B2 |
Key-based security for cloud services
In providing cloud services, key-based security measures specific to a local network are utilized when an internal client terminal logs into the network to access cloud services, and when a remote client terminal connects directly to the cloud services. A cloud service computer references the credential authorization service of the local network, allowing key-based security measures of that network to be applied even when a remote client terminal connects directly to a cloud service computer. By referencing the local credential authorization service, it is possible to provide cloud services to different organizations that administer key-based security measures independently of each other. |
| US11095434B2 |
Shared blockchain data storage based on error correction code
Disclosed herein are methods, systems, and apparatus, including computer programs encoded on computer storage media, for storing blockchain data based on error correction code. One of the methods includes determining, by a blockchain node, block data associated with a current block of a blockchain; performing error correction coding of the block data to generate encoded data; dividing, based on one or more predetermined rules, the encoded data into a plurality of data sets; storing, based on the one or more predetermined rules, one or more data sets of the plurality of data sets; hashing each data set of remaining data sets of the plurality of data sets to generate one or more hash values corresponding to the remaining data sets; and storing the one or more hash values. |
| US11095430B2 |
Method and system of latency assessment in a packet data network
There are provided a method and system for assessing latency of ciphering end point of secure communication channel. The method comprises: generating a test traffic comprising a series of original data packets, wherein, for each original data packet, size of a given packet is uniquely indicative of the packet's place in a sequence of data packets in the series and enables unique correspondence with a size of the given packet upon its encryption; successively transmitting the original packets to the ciphering end point, whilst associating with respective departure time stamps; receiving encrypted packets from the ciphering end point and associating them with respective arrival time stamps; using a size of a given encrypted packet with a timestamp TSa to identify a size of a matching original packet, its place in the sequence of original packets and, thereby, its departure timestamp TSd, thus giving rise to a plurality of timestamp pairs (TSd; TSa). |
| US11095428B2 |
Hybrid system and method for secure collaboration using homomorphic encryption and trusted hardware
A device, system and method for secure collaborations on encrypted data in a hybrid environment of a homomorphic encryption (HE) enabled device and trusted hardware. A set of computations may be divided into a subset of linear computations and a subset of non-linear computations. The linear computations on the encrypted data may be executed using homomorphic encryption (HE) in the homomorphic encryption (HE) enabled device. The non-linear computations on the unencrypted data may be executed in the trusted hardware in an unencrypted domain and encrypting the result. The results of the linear and non-linear computations may be decrypted and merged to generate a result equivalent to executing the set of linear and non-linear computations on the unencrypted data. |
| US11095427B1 |
Transceiver with inseparable modulator demodulator circuits
A transceiver, including a modulation circuit configured to modulate a first digital word into a first modulated time signal; and a demodulation circuit configured to demodulate a second modulated time signal into a second digital word, wherein the modulation and demodulation circuits are operable without an external clock source, and inseparably share one or more same circuit elements. Also, a tunable delay line may be configured to set a time rate of the modulation, wherein the modulation circuit and the demodulation circuit inseparably share the tunable delay line. |
| US11095424B2 |
Method and apparatus for reformatting and retiming digital telecommunications data for reliable retransmission via USB
A method for retiming digital telecommunications data received by a digital logger from a plurality of T-carrier type telephone lines respectively having differing clock sources ensures efficient transmission of received digital audio data to a host computer via a Universal Serial Bus (“USB”) interface. Also the digital logger includes volatile memory for temporarily storing digital audio data received from the plurality of T-carrier type telephone lines for: 1. ensuring that the host computer receives digital audio data correctly via the USB interface; 2. buffering the digital audio data within the digital logger during interruptions in transmission of digital audio data from the digital logger via the USB interface; and 3. reducing audible latency of speech communications. |
| US11095421B2 |
Method and apparatus for monitoring and processing component carriers
A method and apparatus are described which perform bandwidth aggregation by simultaneously monitoring and processing a number of simultaneous, non-contiguous or contiguous component carriers in the downlink. A wireless transmit/receive unit (WTRU) can be configured by an evolved Node-B (eNodeB) to support additional component carriers. A pre-configured additional component carrier may be used. Various methods for activating and deactivating the additional component carrier are also described. |
| US11095419B2 |
Simultaneous bandwidth parts switching
A wireless device receives one or more first radio resource control (RRC) messages. The first RRC messages comprise one or more configuration parameters of a first cell and a second cell. A second RRC message is received. The second RRC message indicates a first change of a first active bandwidth part (BWP) of the first cell. Processing of the second RRC message is completed. A determination is made that the completing occurs during a time duration of a second change of a second active BWP of the second cell. Based on the determining, the first change of the first active BWP is delayed until the second change of the second active BWP is completed. |
| US11095418B2 |
Mitigating interference between base stations and microwave backhaul transceivers
Techniques for detecting and/or mitigating interference in a wireless network are discussed herein. An environment may include a base station in communication with one or more user equipment (UE) and one or more microwave backhaul transceivers. In some examples, the base station may and transceivers may communicate using frequencies in the same band (e.g., a millimeter frequency band). A geometry of devices in an environment can be determined. Further, interference can be detected based on a flexible portion of a transmission or a source identifier that can be included in a transmission. In some examples, the microwave backhaul transceivers may communicate via a same or similar millimeter frequency resources. Wireless resource(s) can be selected or otherwise determined for one or more components of the network to mitigate interference in the network. |
| US11095416B2 |
Wireless communication method using trigger information, and wireless communication terminal using same
Provided is a wireless communication terminal that communicates wirelessly. The wireless communication terminal includes: a transceiver; and a processor. The processor receiving trigger information from a base wireless communication terminal using the transceiver, and transmits an Aggregate-MAC Protocol Data Unit (A-MPDU) to the base wireless communication terminal based on the trigger information. |
| US11095415B2 |
Enhancements to reception reliability for data and control information
A user equipment and base station for enhancing reception reliability for control information or data information are provided. A method for operating the UE includes receiving: a first configuration for a CORESET and a second configuration for a second CORESET; a first PDCCH, in the first CORESET or the second CORESET, including a first DCI format; and a first PDSCH, scheduled by the first DCI format, including a TB. The method further includes transmitting a first PUCCH including a first HARQ-ACK codebook and a second PUCCH including a second HARQ-ACK codebook. HARQ-ACK information, in response to receiving the TB, is included in: the first HARQ-ACK codebook when the first PDCCH is received in the first CORESET and the second HARQ-ACK codebook when the first PDCCH is received in the second CORESET. |
| US11095414B2 |
Method and apparatus for sending and receiving control channel in wireless communication system
In a wireless communication system, a control channel is required in order to use limited resources effectively. However, the control channel resource is part of the system overhead, and thus reduces the data channel resource used for data transmission. In the long term evolution (LTE) system based on OFDM, one sub frame the consists of fourteen OFDM symbols wherein a maximum of three OFDM symbols are used for the control channel resource and remaining eleven OFDM symbols are used for the data channel resource. Therefore, the quantity of energy that can be transmitted for the control channel resource is extremely limited compared to the data channel resource. For this reason, the coverage of the control channel becomes less than that of the data channel, and even if a user can successfully receive the data channel, reception failure of a control channel sometimes results in failure of data recovery. In the present invention, in order to expand the coverage of the control channel to at least the coverage of the data channel, the time resource of the transmission resource wherein the control channel is transmitted is expanded and allocated for sending and receiving the control channel. By way of methods for extending the time resource are provided a method wherein a plurality of sub frames are used to transmit one control channel, and a method wherein a part of a data channel is used for the control channel. |
| US11095412B2 |
Uplink measurement reference signal transmission method, apparatus, and system
An uplink reference signal transmission method is disclosed. User equipment receives first configuration information of a first uplink measurement reference signal and second configuration information of a second uplink measurement reference signal from a wireless network device. The first configuration information is used to configure a time-frequency resource of the first uplink measurement reference signal, and the second configuration information is used to configure a time-frequency resource of the second uplink measurement reference signal. The first uplink measurement reference signal is a zero-power uplink measurement reference signal, and the second uplink measurement reference signal is a non-zero-power uplink measurement reference signal. The user equipment sends, based on the first configuration information and the second configuration information, the second uplink measurement reference signal on a time-frequency resource, other than the time-frequency resource of the first uplink measurement reference signal, in the time-frequency resource of the second uplink measurement reference signal. |
| US11095410B2 |
Transmission method and device based on uplink transmission indication information
A data transmission method, a base station, and a terminal are provided. The method corresponding to the base station includes sending SRS resource configuration information for uplink channel quality measurement and configuration information of a transmission layer quantity, wherein the configuration information of the transmission layer quantity includes a set of maximum quantities of transmission layers allowed to be transmitted by a terminal or the quantity of layers allowed to be transmitted by the terminal; determining uplink transmission indication information; determining a payload corresponding to the uplink transmission indication information according to the SRS resource configuration information and the configuration information of the transmission layer quantity; sending the uplink transmission indication information to the terminal using the payload. |
| US11095406B2 |
Methods, systems, and media for managing network connections
Methods, systems, and media for controlling network connections are provided. In some implementations, a method for controlling network connections is provided, the method comprising: determining, by a user device connection to an access point by a first network connection, that a second network connection is available; determining that the user device is in an idle state; while the user device is in the idle state, switching from the first network connection to the second network connection; monitoring network activity using the second network connection; switching back to the first network connection; generating a profile for the second network connection based at least in part on the monitored network activity; comparing the profile for the second network connection to a profile for the first network connection; selecting the second network connection based on the comparison; and in response to selecting the second network connection, switching to the second network connection. |
| US11095405B2 |
Electronic device and method for wireless communication
Provided are an electronic device and method for wireless communication. The electronic device comprises: a processing circuit used to determine, for each user, a cooperation range of the user on the basis of a statistical model indicating distribution of access points within a pre-determined range around the user and a communication quality requirement of the user; and a set of cooperative access points for the user determined on the basis of the cooperation range, wherein an access point in the set of cooperative access points is assigned to the user to perform cooperative transmission. |
| US11095403B2 |
Carrier activation in a multi-carrier wireless network
A wireless device may be instructed to activate one or more licensed cells and unlicensed cells. The wireless device may monitor a channel on an unlicensed cell and a licensed cell. The respective monitoring periods for the unlicensed cell and licensed cell may be different. |
| US11095402B2 |
Techniques for hybrid chase combining and incremental redundancy HARQ with polar codes
The present disclosure describes various examples of a method, an apparatus, and a computer-readable medium for wireless communications (e.g., 5G NR) using hybrid automatic repeat request (HARQ). For example, one of the methods includes generating a first codeword based on a first code block length, transmitting a first signal using the first codeword, generating a second codeword with incremental redundancy information based on a second code block length, generating a third codeword with repetition of at least a portion of the first codeword based on a third code block length, and transmitting a second signal using at least the second codeword or the third codeword. |
| US11095396B2 |
Efficient polar detection with dynamic control and optimization
Methods, systems, and devices for wireless communications are described. A wireless device, such as a user equipment (UE) may monitor for a decoding candidate of a codeword, wherein the codeword corresponds to a set of received bit metrics, and the decoding candidate corresponds to a plurality of information bits encoded using a polar code, determine a composite detection metric for the codeword for the decoding candidate, where the composite detection metric is derived from a subset of bit metrics for an intermediate polarization layer of the polar code, and determine a classification for performing a list decoding process on the codeword according to the decoding candidate based at least in part on the composite detection metric. |
| US11095394B2 |
Method by which terminal blind-decodes physical sidelink control channel (PSCCH) in wireless communication system, and terminal using same
A method by which a terminal blind-decodes a PSCCH in a wireless communication system is proposed. The method comprises: receiving a blind decoding configuration from a network; and performing blind decoding in a first TTI on the basis of the configuration, wherein the blind decoding includes: first blind decoding on a first PSCCH on the basis of the first TTI; and second blind decoding on a second PSCCH on the basis of a second TTI shorter than the first TTI, and the configuration controls the number of times of the first blind decoding and/or the number of times of the second blind decoding to be performed by the terminal in the first TTI. |
| US11095392B2 |
Handheld portable countermeasure device against unmanned systems
A portable countermeasure device is provided comprising one or more directional antennae, one or more disruption components and at least one activator. The portable countermeasure device further comprises a body having a dual-grip configuration, with the directional antennae are affixed to a removable plate on a front portion of the body. The one or more disruption components may be internally mounted within the device body. The dual-grip configuration allows an operator to use his body to steady and support the device while maintaining the antenna on target. The second grip is positioned adjacent the first grip, with the first grip angled toward the rear of the device and the second grip angled toward the front of the device. The portable countermeasure device is aimed at a specific drone, the activator is engaged, and disruptive signals are directed toward the drone, disrupting the control, navigation, and other signals to and from the drone. |
| US11095391B2 |
Secure WiFi communication
A first communication device determines a first spatial direction for beamforming toward a second communication device, and determines a second spatial direction that is orthogonal to the first spatial direction. The first communication device wirelessly transmits the data to the second communication device while performing beamforming in the first spatial direction, and simultaneously wirelessly transmits noise while performing beamforming in the second spatial direction. |
| US11095388B2 |
Optical amplification device and light amplification method
The de-multiplexing unit 2 de-multiplexes an inputted optical wavelength multiplexed signal into a first optical wavelength multiplexed signal having a first wavelength band and a second optical wavelength multiplexed signal having a second wavelength band in a longer wavelength band than the first wavelength band. The first optical amplifier 3 amplifies the first optical wavelength multiplexed signal. The second optical amplifier 4 amplifies the second optical wavelength multiplexed signal. The multiplexer 5 multiplexes the amplified first optical wavelength multiplexed signal and the amplified second optical wavelength multiplexed signal and outputs the multiplexed signal to a Raman amplifier 6. The first optical amplifier 3 adjusts the amplification rate of the first optical wavelength multiplexed signal so that the intensity of light in the second wavelength band is compensated for by the Raman effect in the Raman amplifier 6. |
| US11095387B2 |
Add/drop multiplexer, network system, transmission method, non-transitory computer readable medium, and management device
Provided is a wavelength path communication node device with no collision of wavelengths and routes, capable of outputting arbitrary wavelengths, and capable of outputting them to arbitrary routes. An add/drop multiplexer (11) includes a communication unit (101) that communicates an optical signal with at least one client device and at least one network and a control unit (102) that indicates a transfer destination of the optical signal according to an attribute of the received optical signal to the communication unit (101). The control unit (102) indicates an attenuation amount of the optical signal to the communication unit (101) for each connected device. When a connected device is changed, the control unit (102) instructs the communication unit (101) to change the attenuation amount. The communication unit (101) attenuates the optical signal with the attenuation amount indicated by the control unit (102) and transfers the attenuated optical signal to a transfer destination. |
| US11095385B2 |
Transmitting apparatus and mapping method thereof
A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme. |
| US11095380B2 |
Source identification using parallel accumulation and comparison of broadcast fingerprints
First fingerprint data is accumulated in a first fingerprint buffer of a channel identification server in parallel with accumulation of second fingerprint data in a second fingerprint buffer of the channel identification server. The first and second fingerprint data include multiple fingerprints representing broadcast content broadcast by corresponding broadcast sources during contiguous time periods, and accumulating the fingerprints includes appending newly received first fingerprints to previously received first fingerprints to generate continuous fingerprints. The channel identification server also receives an unmatched fingerprint representing broadcast content received from an unknown broadcast source by the end-user device. The unmatched fingerprint into probes, which are scrubbed against both first and second continuous fingerprints in an attempt to determine a match between the unmatched fingerprint and either the first or second continuous fingerprint. The unknown broadcast source is identified based on that determination. |
| US11095378B2 |
Wireless channel monitoring and simulation device with multi-input multi-output
A wireless channel monitoring and simulation device with multi-input multi-output (MIMO) is provided, which includes: a wireless channel monitor, configured to collect characteristic parameters of wireless channels in typical environments, and establish models based on the characteristic parameters; a model database, configured to store the characteristic parameter models and parameterize; an original signal, configured to input N different original signals; a wireless channel simulator, configured to simulate a typical channel environment according to the model database configuration, so that the original signal is the same as that in a real typical channel environment, and adopts a N-path output; an N-channel oscilloscope, configured to observe specific waveforms of N-path simulated signals; and a master computer software, configured to process, analyze, and store N-path output signals. The disclosure has many input and output channels, many simulation channel paths, many observable signal changes, flexible design, and fast signal processing speed. |
| US11095377B2 |
Methods and systems for determining morphology data
Techniques for more effectively and efficiently obtaining current morphology data are described. Measurement data is transmitted by user equipment to a central location such as a communication network or another entity such as in remote servers, e.g. the cloud. The recipient of such data, or a third party that receives such data from the recipient, utilizes the data, e.g. signal strength measurements and related data, to determine morphology data for corresponding geographic locations, e.g. altitude, longitude, and latitude. |
| US11095376B1 |
System and method for measuring residual phase noise of a frequency mixer
Residual noise of a frequency mixer is detected. A reference clock is used to generate a first radio frequency (RF) signal, a second RF signal and a third RF signal. The first RF signal and the second RF signal serve as input to the frequency mixer. The reference clock is used to generate a third RF signal. The reference clock is also used to control timing in a detector device. A second frequency mixer mixes an output of the DUT with the third RF signal to produce an input signal for a detector device. Mixing the output of the DUT with the third RF signal cancels at least some of the phase noise within the output signal of the DUT that results from phase noise in the first RF signal and from phase noise in the second RF signal. The detector device detects residual phase noise existing within the input signal for the detector device. |
| US11095373B2 |
Network architecture for independently routable digital subcarriers for optical communication networks
Optical network systems are disclosed, including a system comprising a transmitter including a digital signal processor operable to receive a plurality of independent data streams and output a plurality of digital signals based on the plurality of independent data streams, digital-to-analog circuitry operable to supply a plurality of analog signals based on the plurality of digital signals, a laser operable to supply an optical signal, a modulator operable to receive the optical signal and supply a modulated optical signal based on the plurality of analog signals, including a plurality of optical subcarriers, each of which being associated with a corresponding one of the plurality of independent data streams, a first one of the plurality of optical subcarriers having a first spectral width and a second one of the plurality of optical subcarriers having a second spectral width different than the first spectral width; and a first and a second receiver. |
| US11095372B2 |
Optical communication apparatus, wavelength calibration method, and program
An OLT (2) includes one or more optical receivers (22) configured to receive optical signals of respective different wavelengths obtained by an AWG filter (4) demultiplexing a wavelength-multiplexed signal addressed to the terminal itself, and a supervisory controller (23) configured to transmit, to an ONU (3), a wavelength adjustment instruction to transit a wavelength to be used by an optical transmitter (32) for transmission of an optical signal, to set a difference between an optical received power of an optical signal received by any of the optical receivers (22) and a reference value of the optical received power within a threshold, the ONU (3) being a transmission source of the optical signal. |
| US11095371B2 |
Optical transmitter and transmission method
An optical transmitter transmits a data signal. The optical transmitter includes an encoder configured to encode the data signal by selecting based on a bit sequence, a first symbol and a second symbol from a set of four symbols for each one of at least two transmission time slots. The optical transmitter further includes a modulator configured to use in each transmission time slot the first symbol to modulate a first carrier wave and the second symbol to modulate a second carrier wave, and to transmit the two carrier waves over orthogonal polarizations of an optical carrier. Symbols in consecutive transmission time slots have non-identical polarization states. |
| US11095369B2 |
Device and method for launching tranverse magnetic waves
Disclosed is a device communicably coupled to a power transmission line and capable of launching transverse electromagnetic waves onto the transmission line. The waves propagate data received from a data source connected to the device through a center conductor surrounded by a shield conductor. The device may include a reflector and a coupler adjacent to each other, the reflector electrically connected to the shield conductor and the coupler electrically connected to the center conductor at an unshielded connection point, wherein time-varying E-fields between the reflector and coupler are caused by the data received from the data source, and induce a transverse magnetic wave that propagates longitudinally along the surface of the transmission line. |
| US11095368B2 |
Transmission device, reception device, communication system, transmission method, reception method, and communication method
Provided is a device, which is a transmission device that can improve performance, that includes: a light source; and a transmitter that generates a modulated signal based on an input signal and transmits the modulated signal from the light source as visible light by changing a luminance of the light source in accordance with the modulated signal. The transmitter includes, in the modulated signal, a plurality of items of information related to service set identifiers (SSIDs) of a plurality of mutually different access points in a wireless local area network (LAN), and transmits the modulated signal from the light source. |
| US11095366B2 |
Visible light communication apparatus, lock device, and visible light communication method
The present disclosure discloses a visible light communication apparatus, a lock device, and a visible light communication method. The visible light communication method includes: transmitting, by at least two transmitting devices, visible light carrying respective corresponding information; and sending, by a receiving device, an instruction for correct matching upon determining, according to received superposed visible light, that the superposed visible light meets a preset condition; where the corresponding information includes at least one of a frequency, luminance, and a color of the visible light transmitted by the transmitting devices and a relative position of the transmitting devices to the receiving device. The method can improve security of visible light communication. |
| US11095365B2 |
Wide-angle illuminator module
A wide-angle illuminator module including a rigid support structure having a plurality of angled faces, a flexible circuit including one or more VCSEL arrays, each VCSEL array positioned over a face among the plurality of angled faces, each VCSEL array including a plurality of integrated microlenses with one microlens positioned over each VCSEL in the VCSEL array, and a driver circuit for providing electrical pulses to each VCSEL array, wherein the plurality of VCSEL arrays address illumination zones in a combined field of illumination. The support structure may also be a heatsink. The flexible circuit may be a single flexible circuit configured to be placed over the support structure or a plurality of flexible circuits, each including one VCSEL array. |
| US11095363B2 |
Beamformer for end-to-end beamforming communications system
Methods and systems are described for providing end-to-end beamforming. For example, end-to-end beamforming systems include end-to-end relays and ground networks to provide communications to user terminals located in user beam coverage areas. The ground segment can include geographically distributed access nodes and a central processing system. Return uplink signals, transmitted from the user terminals, have multipath induced by a plurality of receive/transmit signal paths in the end to end relay and are relayed to the ground network. The ground network, using beamformers, recovers user data streams transmitted by the user terminals from return downlink signals. The ground network, using beamformers generates forward uplink signals from appropriately weighted combinations of user data streams that, after relay by the end-end-end relay, produce forward downlink signals that combine to form user beams. |
| US11095360B2 |
Radio frequency (RF) communication system providing enhanced mobile vehicle positioning based upon reward matrices and related methods
A radio frequency (RF) communication system may include of mobile vehicles, with each mobile vehicle including RF equipment and a controller. The controller may be configured to operate the RF equipment, determine a reward matrix based upon possible positional adjustments of the mobile vehicle and associated operational parameters of the mobile vehicle, and implement a positional adjustment of the mobile vehicle based upon the reward matrix. The system may also include an oversight controller configured to update respective reward matrices of the mobile vehicles. |
| US11095356B2 |
Secondary cell recovery for secondary cell groups
Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment may receive, from a base station, information identifying a secondary cell group including a plurality of secondary cells. The user equipment may perform, after detecting a beam failure with a secondary cell of the secondary cell group, a beam failure recovery action associated with the secondary cell group. Numerous other aspects are provided. |
| US11095355B2 |
Prioritization in beam failure recovery procedures
Beam failure recovery procedures (BFR) are described for wireless communications. At least one transmission for a BFR procedure may overlap with a scheduled transmission. A wireless device may prioritize a transmission for a BFR procedure, for example, by dropping the scheduled transmission and transmitting the at least one transmission the BFR procedure. |
| US11095354B2 |
Method and apparatus for transmitting and receiving reference signal and for scheduling
The present application provide a reference signal transmitting method, including: notifying a User Equipment (UE) of a grid index and a reference signal port index of the UE, wherein a coverage area of a base station is divided into grids, the grid index of the UE is an index of a grid where the UE is located; generating a reference signal based on the grid index; and transmitting the reference signal on corresponding time-frequency resources based on the grid index and the reference signal port index. The present application further provides a corresponding reference signal transmitting apparatus, and a scheduling method and apparatus. According to the technical solution provided by the present application, it is possible to increase the number of ports that the system can support at the same time with low reference resource overhead, and to ensure that the interference of the reference signal is controllable and eliminable, thereby ensuring transmission reliability. |
| US11095353B2 |
Use of low resolution analog-to-digital converter/digital-to-analog converter
Methods, systems, and devices for wireless communications are described. A wireless device, such as a base station and/or a user equipment (UE), may select a first resolution for a first analog-to-digital or digital-to-analog conversion process associated with a first wireless communication. The wireless device may determine that the first wireless communication is performed according to the first resolution. The wireless device may select, based at least in part on the determining, a second resolution for a second analog-to-digital or digital-to-analog conversion process associated with a second wireless communication, the first resolution being a lower resolution than the second resolution. |
| US11095351B2 |
Generating a channel state information (“CSI”) report
Apparatuses, methods, and systems are disclosed for generating a CSI report. One apparatus includes a transceiver that receives a set of reference signals transmitted from a base station and a processor that transforms the set of reference signals to obtain per-layer vectors of amplitude and phase coefficients of a DFT-compressed codebook. Here, the first element of the amplitude coefficient vector corresponding to one particular beam is unity and the first element of the phase coefficient vector corresponding to the particular beam is zero. The apparatus transmits CSI feedback that includes an indication of one or more elements of the vectors of amplitude coefficient vectors and phase coefficient vectors corresponding to at least one identified beam, and does not include the first element of the amplitude coefficient vector and the first element of the phase coefficient vector corresponding to the particular beam. |
| US11095347B1 |
Transmission of a two-port reference signal
There is provided mechanisms for transmitting a two-port reference signal from an analog antenna array of an antenna arrangement. The analog antenna array comprises antenna elements of two polarizations. All antenna elements of each polarization are connected to a respective physical antenna port. A method comprises generating two virtual antenna ports, one for each of the two ports of the reference signal. The method comprises feeding the reference signal from the two virtual antenna ports to the two physical antenna ports via a virtualization network. The method comprises transmitting, via the antenna elements, the reference signal from the two physical antenna ports over a composite beamwidth in different spatial coverage per polarization for each of the two physical antenna ports whereby the transmitted reference signal, over the composite beamwidth, varies between having rank 1 and rank 2. |
| US11095346B2 |
4TX codebook enhancement in LTE
Channel state information (CSI) feedback in a wireless communication system is disclosed. A precoding matrix is generated for multi-antenna transmission based on precoding matrix indicator (PMI) feedback, wherein the PMI indicates a choice of precoding matrix derived from a matrix multiplication of two matrices from a first codebook and a second codebook. In one embodiment, the first codebook comprises at least a first precoding matrix constructed with a first group of adjacent Discrete-Fourier-Transform (DFT) vectors. In another embodiment, the first codebook comprises at least a second precoding matrix constructed with a second group of uniformly distributed non-adjacent DFT vectors. In yet another embodiment, the first codebook comprises at least a first precoding matrix and a second precoding matrix, where said first precoding matrix is constructed with a first group of adjacent DFT vectors, and said second precoding matrix is constructed with a second group of uniformly distributed non-adjacent DFT vectors. |
| US11095345B2 |
Method and apparatus for enabling uplink MIMO
Methods and apparatuses enabling uplink multiple-input multiple-output (MIMO) are provided. A user equipment (UE) includes a transceiver and a processor operably connected to the transceiver. The transceiver is configured to receive an uplink (UL) grant for an UL transmission. The processor is configured to decode a precoding information field in downlink control information (DCI) associated with the UL grant. The precoding information field includes at least one precoding matrix indicator (PMI) corresponding to a plurality of precoders. The transceiver is further configured to precode a data stream according to the precoders indicated by the precoding information field and transmit the precoded data stream on an UL channel. |
| US11095338B2 |
Systems and methods for ultra wideband impulse radio transceivers
Ultra-Wideband (UWB) technology exploits modulated coded impulses over a wide frequency spectrum with very low power over a short distance for digital data transmission. Today's leading edge modulated sinusoidal wave wireless communication standards and systems achieve power efficiencies of 50 nJ/bit employing narrowband signaling schemes and traditional RF transceiver architectures. However, such designs severely limit the achievable energy efficiency, especially at lower data rates such as below 1 Mbps. Further, it is important that peak power consumption is supportable by common battery or energy harvesting technologies and long term power consumption neither leads to limited battery lifetimes or an inability for alternate energy sources to sustain them. Accordingly, it would be beneficial for next generation applications to exploit inventive transceiver structures and communication schemes in order to achieve the sub nJ per bit energy efficiencies required by next generation applications. |
| US11095336B1 |
Cyclic chirp calibration
A method, comprising: generating, by a signal source, a continuous chirp signal the chirp signal being generated by converting to analog form a plurality of digital samples, each of the plurality of digital samples being calculated, at least in part, by: (i) incrementing a first counter by a frequency slope value, (ii) incrementing a second counter by a current value of the first counter, and (iii) evaluating a periodic function based on a current value of the second counter; and transmitting the chirp signal from the signal source to a signal receiver, the chirp signal being transmitted over a communications channel that couples the signal source to the signal receiver, the chirp signal being transmitted as part of a test for detecting a phase response of the communications channel. |
| US11095335B2 |
Transciever circuit
An integrated circuit is disclosed. The integrated circuit includes a set of transceivers comprising a plurality of transceivers, all configured to transmit in the same transmit frequency band and receive in the same receive frequency band. Furthermore, the integrated circuit has a set of frequency synthesizers including a separate frequency synthesizer associated with each transceiver in the set of transceivers, wherein each frequency synthesizer in the set is configured to generate a local-oscillator (LO) signal to its associated transceiver. Moreover, the integrated circuit includes a control circuit configured to control the set of frequency synthesizers such that nearest neighbors in the set of frequency synthesizers generate LO signals at different frequencies (f1, f2, f3, f4). |
| US11095331B2 |
Electronic device, protective case for electronic device, and displaying method thereof
A case, an electronic device and a method are disclosed herein. The case is mountable onto the electronic device. The electronic device includes a display, a first sensor, a second sensor different than the first sensor, a processor operatively connected with the display, the first sensor, and the second sensor, and a memory operatively connected with the processor. The processor implements the method, including: display a screen on the display, detect, by the first sensor, whether a first part of a detachable peripheral device is mounted on an outer portion of the electronic device, obtain, by the second sensor, information from a second part of the detachable peripheral device, when the second part is coupled to the first part, and when the first part is detected through the first sensor, and the information is obtained through the second sensor, execute a screen split mode dividing the screen into regions. |
| US11095327B2 |
Method and apparatus for interference cancellation in full-duplex multi-cell networks
Techniques and architectures for multi-stage cancellation of self-interference (SI) and joint cancellation of mutual-interference (MI) and residual SI in signals received by devices of a full-duplex multi-cell network are disclosed. In various examples, channel estimations and interference cancellation operations are performed utilizing multiple orthogonal training signals transmitted by network devices during a common over-the-air training period. Training signals derived from the orthogonal training signals during transmission are utilized to generate SI estimation information and perform at least a first SI cancellation operation on a received signal that includes at least first and second orthogonal training signals. The received signal and orthogonal training signals are then used to estimate a MI channel impulse response and a (residual) SI channel impulse response for use in joint MI/SI cancellation operations on further received signals. Details regarding the design of the orthogonal training signals and a unique system-level delay calibration procedure are also provided. |
| US11095326B2 |
Wide bandwidth digital predistortion system with reduced sampling rate
A digital predistortion linearization method is provided for increasing the instantaneous or operational bandwidth for RF power amplifiers employed in wideband communication systems. Embodiments of the present invention provide a method of increasing DPD linearization bandwidth using a feedback filter integrated into existing digital platforms for multi-channel wideband wireless transmitters. An embodiment of the present invention utilizes a DPD feedback signal in conjunction with a low power band-pass filter in the DPD feedback path. |
| US11095324B2 |
Wireless transmission circuit and control method thereof
A wireless transmission circuit includes a first induction circuit, a second induction circuit, a detection circuit, a first signal adjustment circuit, and a third induction circuit. The first induction circuit is configured to receive a first signal outputted from a power amplifier. The second induction circuit is configured to output the received first signal as a second signal. The detection circuit is configured to detect a common mode signal associated with the first signal. The first signal adjustment circuit is configured to adjust a phase or an amplitude of the common mode signal to generate a third signal. The third induction circuit is configured to receive the third signal and be coupled to the second induction circuit to reduce a second harmonic in the second signal. |
| US11095323B2 |
Method for gateway signaling for miso operation and apparatus therefor
Disclosed herein are a gateway-signaling method for Multiple-Input Single-Output (MISO) operation and an apparatus for the same. An apparatus for transmitting a broadcast signal according to an embodiment of the present invention includes a predistortion unit for performing predistortion for decorrelating signals corresponding to transmitters using the number of transmitters used for MISO and a transmitter coefficient index that are identified using a timing and management packet transmitted through a Studio-to-Transmitter Link (STL), thereby generating a pre-distorted signal; and an RF signal generation unit for generating an RF transmission signal using the pre-distorted signal corresponding to the transmitter coefficient index. |
| US11095319B2 |
Wireless ranging using physical and virtual responders
An electronic device configures two or more virtual responders associated with different subsets of capabilities of a physical responder in the electronic device, where the physical responder comprises a radio-frequency (RF) transceiver and multiple antennas, and where a given virtual responder corresponds to the RF transceiver and a given antenna. Then, the electronic device performs, based at least in part on wirelessly communication with a second electronic device and using at least the virtual responders, measurements on wireless signals from the second electronic device to the electronic device, where the measurements correspond to a time of flight of the wireless signals. Next, the electronic device determines, based at least in part on the measurements, a range between the electronic device and the second electronic device, where the determination uses the measurements from different virtual responders to correct for an environmental condition and/or increase an accuracy of the determined range. |
| US11095313B2 |
Employing single error correction and triple error detection to optimize bandwidth and resilience under multiple bit failures
Single error correction (“SEC”) code and triple error detection (“TED”) code are used to optimize bandwidth and resilience under multiple bit failures. One or more errors in data stored in duplicated registers are detected and corrected using the SEC code and TED code where simultaneous read operations are produced with two copies of data for each of the duplicated registers for a multi-port banked memory array. The SEC code and TED code may be included in each of the two data copies of the simultaneous read operations. |
| US11095310B2 |
Error correction apparatus, operation method thereof and memory system using the same
An error correction apparatus may include: an input component configured to receive data; an error information generation component having a first error detection ability to detect L errors and a second error detection ability to detect K errors, where L is a positive integer and K is an integer larger than L, and configured to generate error information including the number of errors contained in the received data and the positions of the errors, based on the first error detection ability, and generate the error information based on the second error detection ability, when the error information is not generated on the basis of the first error detection ability; an error correction component configured to correct the errors of the received data based on the generated error information; and an output component configured to output the corrected data. |
| US11095307B2 |
Performing cyclic redundancy checks using parallel computing architectures
Apparatuses, systems, and techniques to compute cyclic redundancy checks use a graphics processing unit (GPU) to compute cyclic redundancy checks. For example, in at least one embodiment, an input data sequence is distributed among GPU threads for parallel calculation of an overall CRC value for the input data sequence according to various novel techniques described herein. |
| US11095306B2 |
Method and system for determining a sampling scheme for sensor data
A device and computer-executable method is provided for adaptively determining a sampling scheme to be applied at a first sensor from among a plurality of sensors for sampling sensor data values corresponding to a signal. A sparsifying transform for a subsequent sampling time window of the first sensor is predicted, wherein the sparsifying transform is determined based on a predictive model of the sparsity of the signal. Moreover, a subsampling parameter for the subsequent sampling time window is determined. The subsampling parameter corresponds to a number of sensor data values to be acquired within the sampling time window. This subsampling parameter is determined based on the predicted sparsifying transform. Further determined is a compressive sampling scheme for the subsequent sampling time window of the first sensor. The compressive sampling scheme is determined based on the predicted sparsifying transform. |
| US11095303B1 |
Single-ended to differential circuit
A single-ended to differential circuit is presented. The circuit may be a single-ended to differential integrator or a single-ended to differential amplifier. The circuit determines a first output and a second output voltage based on an input voltage, first and second reference voltages. The circuit has a first, a second and a third input memory element. The circuit in a first phase, samples a voltage indicative of the input voltage on the first input memory element. The circuit in the first phase, samples a voltage indicative of the first reference voltage on the second input memory element. The circuit in the first phase, samples a voltage indicative of the second reference voltage on the third input memory element. The circuit, in a second phase, determines the first and second output voltage based on the sampled voltages on the first, second, and third input memory elements. |
| US11095298B2 |
Fast bandwidth spectrum analysis
An apparatus includes a processor, a Phase-Locked Loop Waveform Generator (PLLWG), a Voltage Controlled Oscillator (VCO), a demodulator, signal conditioning circuitry, and an Analog-to-Digital Converter (ADC). The processor generates control command signals, receives a digital data input signal, and performs spectrum analysis on the digital data input signal. The PLLWG is coupled to the processor, receives the control command signals, and generates a charge pump output signal based on the control command signals. The VCO is coupled to the PLLWG, receives a tuning signal based on the charge pump output signal, and outputs a VCO output signal based on the tuning signal. The demodulator receives an incoming modulated signal and the VCO output signal, and outputs an analog output signal based on the incoming modulated signal and the VCO output signal. The ADC converts the analog output signal into the digital data input signal. |
| US11095297B2 |
Phase locked loop (PLL) circuit with voltage controlled oscillator (VCO) having reduced gain
A voltage controlled oscillator (VCO) circuit generates an output signal having a frequency which is dependent on a control voltage. A current is generated which is itself dependent on an amplitude of the VCO circuit. The generated current accordingly tracks, to an extent, the temperature behavior of the oscillator within the VCO circuit. The oscillator is driven by the sum of the generated current and a control current dependent on the control voltage. The control voltage may, for example, be generated by a phase lock loop (PLL). |
| US11095292B2 |
Frequency synthesis device with feedback loop
A frequency synthesis device includes a servo circuit for controlling an output frequency to an input reference frequency. The circuit includes a first phase accumulator clocked by the reference frequency, a phase comparison block, a loop filter and an oscillator. It further includes a feedback loop connecting the output to the comparison block, having a second phase accumulator clocked by the output frequency. The comparison block includes T phase comparators with logic gates receiving respectively T first logic signals from the servo circuit on T first inputs and T second logic signals from the feedback loop on T second inputs, the T first and second signals having logic levels that continuously depend on values provided by the first and second accumulators according to at least one multi-phase correspondence matrix. |
| US11095291B2 |
Time measurement circuit, system having a PWM signal generator circuit and a time measurement circuit, and corresponding integrated circuit
A time measurement includes a multiphase clock generator and a phase sampling circuit. The multiphase clock generator generates a sequence of a given number n of phase shifted clock phases, wherein one of the phase shifted clock phases represents a reference clock signal. The phase sampling circuit is configured to generate a phase value indicative of a number of fractions 1/n of the clock period of the clock phases elapsed between an edge of the reference clock signal and an instant when an asynchronous event signal is set. The phase sampling circuit includes first through fourth sub-circuits, which respectively generate or determine first through fourth control signals. |
| US11095288B2 |
Switchbox
Switchboxes are especially used in integrated circuits with programmable logic (e.g. FPGAs). They are used to establish configurable signal paths between logic blocks. The present invention is based on the task to present a switchbox with a small number of multiplexers and configuration bits, which can both forward a signal in signal direction and can implement a change of direction.The task is solved by using switchboxes consisting of direction multiplexers and at least one direction change multiplexer. Thus the signal direction can be changed arbitrarily without increasing the size of the direction change multiplexers. |
| US11095286B2 |
Electrostatic discharge clamp topology
A clamping circuit comprises a first field-effect transistor (FET) having a gate, a source, and a drain, a diode, a first voltage source, and coupling circuitry configured to couple the first voltage source to the drain of the first FET and the diode to the source of the first FET. |
| US11095283B2 |
Drive control apparatus for driving a switching element including a sense element
A drive control apparatus for a switching element drives a switching element including a sense element, and includes a drive circuit that provides a gate driving signal to the switching element, a transient characteristic absorbing circuit that absorbs a transient characteristic of the sense element when the switching element is turned on, and a determination circuit that determines an overcurrent or a short-circuit state of the switching element from an output of the sense element. |
| US11095281B2 |
Gate drive control method for SiC and IGBT power devices to control desaturation or short circuit faults
A gate-drive controller for a power semiconductor device includes a master control unit (MCU) and one or more comparators that compare the output signal of the power semiconductor device to a reference value generated by the MCU. The MCU, in response to a turn-off trigger signal, generates a first intermediate drive signal for the power semiconductor device and generates a second intermediate drive signal, different from the first drive signal, when a DSAT signal indicates that the power semiconductor device is experiencing de-saturation. The MCU generates a final drive signal for the power semiconductor when the output signal of the one or more comparators indicates that the output signal of the power semiconductor device has changed relative to the reference value. The controller may also include a timer that causes the drive signals to change in predetermined intervals when the one or more comparators do not indicate a change. |
| US11095275B1 |
Loadable true-single-phase-clocking flop
Techniques are described for implementing a true-single-phase-clocking (TSPC) flop with loading functionality. For example, the a loadable TSPC flop can receive input signals, including at least a clock input signal, a SET signal, and a RESET signal. Responsive to one configuration of the input signals, the loadable TSPC flop operates in a normal mode, in which its output node toggles responsive to the clock input signal. Responsive to another configuration of the input signals, the loadable TSPC flop operates in a reset loading mode, such that the Qb output node is loaded and held to a predetermined reset value. Responsive to another configuration of the input signals, the loadable TSPC flop operates in a set loading mode, such that the Qb output node is loaded and held to a predetermined set value that is a complement of the predetermined reset value. |
| US11095274B1 |
Pre-discharged bypass flip-flop circuit
A pre-discharged edge-triggered flip-flop, in which internal nodes determinative of an output signal are discharged to VSS prior to an evaluation phase of a clock signal, is provided to enable improved clock-to-output response times when provided with a rising edge of a clock pulse. In operation, during a pre-discharge phase of the clock signal, multiple internal nodes of a differential master latch circuit of the flip-flop are discharged to VSS. In response to a rising edge of the clock signal signaling the beginning of an evaluation phase, one of the internal nodes (selected depending on the logical value of an input signal to the flip-flop) is charged to VDD while other of the internal nodes remain at VSS. A single clock signal inverter is disposed between the input clock signal and a multiplexer providing the output data signal. |
| US11095271B2 |
Equalizer and transmitter including the same
An integrated circuit for generating an equalized signal, according to a channel, from serial data includes a shift register that extracts a symbol sequence from the serial data. A data storage stores values of an equalized digital signal corresponding to potential symbol sequences corresponding to a filter coefficient sequence. A lookup table outputs the equalized digital signal of a value corresponding to the extracted symbol sequence. A digital-to-analog converter (DAC) converts the equalized digital signal into the equalized signal. A controller refreshes the lookup table, based on at least one of values stored in the data storage and values included in the lookup table, in response to a control signal. |
| US11095266B2 |
Slanted apodization for acoustic wave devices
A device includes a die and an interdigital transducer on the die. The interdigital transducer includes a first bus bar, a second bus bar, and a number of electrode fingers. The first bus bar is parallel to the second bus bar. The electrode fingers are divided into a first set of electrode fingers and a second set of electrode fingers. The first set of electrode fingers extend obliquely from the first bus bar towards the second bus bar. The second set of electrode fingers extend obliquely from the second bus bar towards the first bus bar, and are parallel to and interleaved with the first set of electrode fingers. By providing the electrode fingers oblique to the bus bars, spurious transverse modes may be suppressed while maintaining the quality factor, electromechanical coupling coefficient, and capacitance of the device. |
| US11095252B1 |
Mixer circuitry with noise cancellation
An electronic device may include wireless circuitry with a baseband processor, a transceiver, a front-end module, and an antenna. The transceiver may include mixer circuitry. The mixer circuitry may include switches controlled by oscillator signals. The mixer circuitry may also include oscillator phase noise cancelling capacitors controlled by inverted oscillator signals. Operated in this way, the mixer circuitry exhibits improved noise figure performance. |
| US11095251B1 |
Performance calculation system, performance calculation method, and electronic device
A performance calculation method suitable for a chip is provided. The chip includes oscillator circuit systems configured to generate oscillation signals and to sense operation states of the chip to adjust periods of the oscillation signals. The method includes following operations: when the chip is in a first operation state, constructing a first function according to the periods of the oscillation signals and a first performance value of the chip; when the chip is in a second operation state, constructing a second function according to the periods of the oscillation signals and a second performance value of the chip; adjusting coefficients of the first or second function according to trajectories of graphs of the first and second functions, so that the graphs of the first and second functions intersect at a coordinate point; constructing a performance function of the chip according to the first and second functions. |
| US11095250B2 |
Circuit device, oscillator, electronic apparatus, and vehicle
The circuit device includes a current generation circuit and a current-voltage conversion circuit. The current generation circuit generates a temperature compensation current based on a temperature detection voltage from the temperature sensor and temperature compensation data. The current-voltage conversion circuit converts the temperature compensation current into the temperature compensation voltage. The current generation circuit performs a fine adjustment of the temperature compensation current based on lower bits of the temperature compensation data, and performs a coarse adjustment of the temperature compensation current based on higher bits of the temperature compensation data. |
| US11095248B2 |
Solar junction box
A solar junction box for a solar panel having at least one photovoltaic cell and a foil electrically connected to the at least one cell including a housing having a base and a cover coupled to the base. The base and the cover define a cavity. The base has a mounting wall including a mounting surface configured to be mounted to the solar panel including a foil opening at the mounting surface. A contact assembly is received in the cavity having a terminal including a foil contact configured to be terminated to the foil. The foil contact has a transition leg transitioning into the foil opening to interface with the foil and a mating leg configured to be mated with the foil. The mating leg extends at or beyond the mounting wall. |
| US11095246B1 |
Redundant electric motor drive
A system may be provided that may include an integrated motor drive configured to couple to a motor. The integrated motor drive may include a first converter that may be configured to electrically couple with a winding assembly of the motor. The first converter may include at least first conversion circuitry configured to form a first electrical excitation waveform and second conversion circuitry coupled in parallel to the second conversion circuitry and configured to form a second electrical excitation waveform. The first converter may also include a first transformer configured to form a first summation electrical excitation waveform from the first electrical excitation waveform and the second electrical excitation waveform that drives the motor. |
| US11095244B2 |
Motor drive device and motor drive system
A motor drive device receiving AC power supplied from an AC source and driving a motor includes: a converter circuit converting the AC power into DC power; an inverter circuit converting the DC power into AC power to drive the motor; and a current detector detecting input current flowing on the AC side of the converter circuit. The motor drive device also includes a converter device and an inverter device. The converter device includes a control unit performing control such that input current or input power supplied to the converter circuit does not exceed an upper limit, based on a value detected by the current detector. The inverter device includes a control unit detecting voltage of a DC bus connecting the converter circuit and the inverter circuit, and limiting the output power of the inverter circuit when a detection value of the bus voltage decreases to a set lower limit. |
| US11095241B2 |
Motor control device and motor control method
According to one embodiment, there is provided a motor control device including a detection circuit, a control circuit and a drive circuit. The detection circuit detects, in a direct current motor with a first coil and second coil, a first parameter related to an induced voltage generated in the first coil and a second parameter related to an induced voltage generated in the second coil. The control circuit changes, according to a difference between the first parameter and the second parameter, at least one of a first amplitude control value of a current of the first coil and a second amplitude control value of a current of the second coil. The drive circuit drives, according to the changed amplitude control value, the first coil and the second coil, respectively. |
| US11095240B2 |
Electric motor in propulsion system with auxiliary power generation
A propulsion system having an electric motor and corresponding method. A controller is configured to receive a torque request and selectively command the electric motor. The controller has a processor and tangible, non-transitory memory on which instructions are recorded for a method of generating an auxiliary power. The controller is configured to obtain a desired auxiliary power and a delta factor (δ). The delta factor is set as a speed modifier (Δω=δ) when the cosine of an angle (θ), between a constant torque unit vector and a decreasing voltage ellipse unit vector, is less than a predefined threshold. A modified rotor speed is obtained as a sum of an original rotor speed and a speed modifier (Δω). The controller is configured to obtain modified stator current commands based on the modified rotor speed and torque request. The auxiliary power is generated by commanding the modified stator current commands. |
| US11095238B2 |
Electric tool and control method of electric tool
An electric tool includes a motor, a drive circuit, a power supply and a controller. The motor includes a rotor and first, second, and third phase windings. The drive circuit is electrically connected to the first, second, and third phase windings and drives the motor to output power. The power supply is electrically connected to the drive circuit and supplies power to the first, second, and third phase windings through the drive circuit. The controller is connected to the drive circuit and outputs a control signal to control the drive circuit. The controller controls the drive circuit according to a rotation position of the rotor when a voltage of the power supply is less than or equal to a preset voltage threshold so that the first, second, and third phase windings are simultaneously connected to the power supply. |
| US11095235B2 |
Vibration type actuator for relatively moving vibrating body and contact body, electronic device, and method for inspecting friction material
A vibration type actuator uses a friction material of which a depth of impregnation with a resin can be easily measured in a non-destructive manner. The vibration type actuator has a vibrating body including an electro-mechanical energy conversion element and an elastic body; and a contact body configured to come into contact with the vibrating body. The vibration type actuator has a structure in which at least one of a friction portion of the contact body coming into contact with the vibrating body and a friction portion of the vibrating body coming into contact with the contact body has a metallic portion including a pore that is impregnated with a resin containing a fluorescent material. |
| US11095234B2 |
Triboelectric nanogenerators
The present disclosure relates to novel triboelectric nanogenerators with flexible polymeric dielectric layer comprising liquid metal particles, and method of making and using the novel triboelectric nanogenerators. |
| US11095232B2 |
Hybrid I-T type multi-level converters
A multi-level converter includes a plurality of capacitors coupled in series between first and second nodes of a DC port and coupled to one another at n−2 first intermediate nodes. The converter also includes a switching circuit including at least one first switch configured to couple the first node of the DC port to an input/output node, at least one second switch configured to couple the second node of the DC port to the input/output node, and at least three third switches configured to couple respective ones of the first intermediate nodes to the input/output node. The converter further includes a control circuit configured to control the first, second and third switches to provide an n-level converter. |
| US11095226B2 |
Switching power supply device having failure protection function, and method for controlling the same
A switching power supply device includes a voltage conversion transformer, a primary-side control semiconductor device, a rectification and smoothing circuit, an output voltage detection circuit, a failure detection circuit, and a switch. The primary-side control semiconductor device generates a driving signal which controls a switching element connected to a primary winding of the transformer. The rectification and smoothing circuit is connected to a secondary winding of the transformer. The output voltage detection circuit detects a secondary-side output voltage of the transformer and transmits a feedback signal corresponding to the output voltage to the primary-side control semiconductor device through an insulated signal transmitter. The failure detection circuit detects a failure on a secondary side of the transformer. The switch cuts off a current flowing to the insulated signal transmitter if the failure detection circuit detects a failure. |
| US11095225B2 |
Power supply apparatus and control method thereof
A control method for a power supply apparatus is provided. Firstly, at least one of an output voltage or an output current of the resonant converter is sampled. Then, an error signal is generated according to a reference value and at least one of the output voltage or the output current. While the resonant converter is in a burst mode, a first switching signal and a chopping signal are generated according to the error signal. The chopping signal has a chopping period and a duty cycle. The chopping period and the duty cycle are dynamically adjusted according to the error signal. Then, a second switching signal is generated according to the chopping signal and the first switching signal. A switch unit of the resonant converter is turned on or turned off according to the second switching signal. |
| US11095221B1 |
Constant on-time controller and buck regulator device using the same
A constant on-time controller (COT) includes: a voltage dividing circuit to generate a feedback voltage according to an output voltage of a buck regulator; a current ripple extracting circuit to sense a current from an inductor of a buck regulator, and generate an extracted ripple current having no DC component according to a sensed current; a one-shot on-timer to output a constant-on time control signal according to a regulator input voltage of the buck regulator and the output voltage; a comparing circuit to output a comparison result according to a reference voltage signal, the feedback voltage and the extracted ripple current; and a logic circuit to generate a control signal to the buck regulator according to the comparison result and the constant-on time control signal. The current ripple extracting circuit detects the DC component in the present cycle, and compares the detected DC component with the next cycle. |
| US11095215B2 |
Multi-capacitor bootstrap circuit
Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. The first transistor comprises a drain terminal coupled to an input voltage node, a source terminal coupled to a first node, and a gate terminal coupled to a second node. The second transistor comprises a drain terminal coupled to a third node, a source terminal coupled to a fourth node, and a gate terminal coupled to a fifth node. The third transistor comprises a drain terminal coupled to a sixth node, a source terminal configured to couple to a gate terminal of a switching transistor, and a gate terminal coupled to a seventh node. The first capacitor is coupled between the first node and the third node. The second capacitor is coupled between the fourth node and the sixth node. |
| US11095214B2 |
Start-up circuit and operation method thereof
A startup circuit initializes a voltage of a capacitor of a switch-capacitor regulator. The startup circuit includes a voltage forming circuit and a control unit. The voltage forming circuit selectively electrically connected to the top and the bottom of the capacitor. In a first operation phase, the voltage forming circuit is electrically connected to the top and bottom of the capacitor, and the top and bottom of the capacitor are connected to each other, and the voltages of the top and bottom are set as a preset high voltage. In a second operation phase, the voltage forming circuit disconnects the top and the bottom, and generates current flowing out from the bottom of the capacitor until the voltage cross the capacitor is equal to the preset initial voltage. In the third operation phase, the startup circuit is disconnected from the capacitor. |
| US11095212B2 |
Line loss compensating power supplies
An electrical power supply includes a power circuit for providing power to a load via a conductor, and a control circuit. The control circuit is configured to set an output voltage of the power circuit at different values to cause the load voltage at the load to change, sense an output current of the power circuit corresponding to each different value of the output voltage, determine an electrical resistance of the conductor based on the different output voltage values and their corresponding output current values, and set the output voltage of the power circuit at a defined value based on the determined resistance to compensate for a voltage drop of the conductor when the power circuit provides power to the load and to regulate the load voltage at the load at a desired value. Other example power supplies, control circuits and/or methods of regulating load voltages are also disclosed. |
| US11095211B2 |
Control method and switching device
A control method and a switching device are provided for a separately excited synchronous machine as a drive in a hybrid or electric vehicle. The switching device converts and/or distributes electrical energy within the vehicle, in particular the hybrid or electric vehicle, wherein an asymmetric full bridge is provided, in the bridge branch of which a rotor of an SSM is arranged. Switches are provided in the asymmetric full bridge in order to provide a pulse width modulation corresponding to a desired motor rotational speed and power of the SSM. The device is characterized in that it has a short-circuit branch extending in parallel with the bridge branch of the asymmetric full bridge, by which short-circuit branch the rotor of the SSM is able to be short-circuited. |
| US11095208B2 |
Control method, apparatus, device, and medium for power factor correction PFC circuit
Disclosed in embodiments of the present invention are a control method, apparatus, device, and medium for a power factor correction (PFC) circuit, used for solving the problems of high implementation costs and relatively severe THD that exist in existing PFC circuit control methods. The control method for a power factor correction (PFC) circuit, comprising: acquiring circuit parameter information of the PFC circuit; when determining that the circuit parameter information meets a preset switching condition, switching a control mode of the PFC circuit to be a continuous conduction mode (CCM). |
| US11095207B1 |
Power factor correction circuit with burst setting and method of operating the same
A power factor correction circuit with burst setting includes a conversion circuit, a control unit, and a burst setting circuit. The burst setting circuit respectively sets at least one burst period when an input power source is at a rising edge of a positive half cycle, a falling edge of the positive half cycle, the rising edge of a negative half cycle, and the falling edge of the negative half cycle, and provides a burst setting signal corresponding to the at least one burst period to the control unit so that the control unit limits the conversion circuit to perform a burst operation during the at least one burst period. |
| US11095206B2 |
AC-DC converter with boost front end having flat current and active blanking control
A power converter can include an input boost converter stage having an input configured to receive a rectified AC input voltage and an output configured to deliver a DC bus voltage and a second switching converter stage having an input configured to receive the DC bus voltage and an output configured to deliver a regulated output voltage. The input boost converter may be configured to be operated in a flat current mode to maintain a substantially constant DC bus voltage over a broad range of AC input voltages. The input boost converter may be further configured to be operated in an active blanking mode, wherein operation of the boost converter is prevented during a controlled blanking interval of each cycle of the rectified AC input voltage. The controlled blanking interval may be increased responsive at least in part to an increase in the AC input voltage and/or may be decreased responsive at least in part to a decrease in the AC input voltage. |
| US11095203B2 |
High-frequency line filter
In a high-frequency line filter for a converter, the converter has three phase connections for receiving a three-phase alternating signal from a three-phase voltage network and is adapted to convert the received three-phase alternating signal into an output signal for a load. The high-frequency line filter includes: a first filter path for establishing a conductive connection between a first phase connection of the three phase connections and a ground connection; a second filter path for establishing a conductive connection between a second phase connection of the three phase connections and the ground connection; and a third filter path for establishing a conductive connection between a third phase connection of the three phase connections and the ground connection. The high-frequency line filter includes a series connection of a pulse-proof capacitor and a parallel connection of at least two Y capacitors, the series connection being provided in each filter path. |
| US11095202B1 |
Method and apparatus for common-mode voltage cancellation
A common-mode voltage cancellation (CMVC) circuit, is disclosed. The circuit includes a first set of coupled inductors, each having a primary winding defining a first polarity, and a secondary winding. The secondary windings are electrically coupled in series. Each primary winding receives a phase voltage having a common mode voltage component from a respective input line. The circuit includes a second set of coupled inductors comprising at least one primary winding and at least one secondary winding The at least one primary winding receives a second voltage from the series connected secondary windings of the first set of coupled inductors. Each at least one secondary winding is coupled in series with a respective input line such that the common mode voltage component received on input lines will be reduced at an output of the set of secondary windings. |
| US11095198B2 |
Electric machine assembly with reduced rotor post leakage
An electric machine assembly includes a rotor formed from one or more magnetically conductive sheets having elongated magnetic flux barriers separated from each other in radial directions that radially extend away from an axis of rotation of the rotor. The magnetic flux barriers are separated from each other by magnetic flux carrier portions of the one or more magnetically conductive sheets. The assembly also includes a non-magnetic post coupled with the magnetic flux carrier portions of the one or more magnetically conductive sheets on opposite sides of at least one of the magnetic flux barriers. The non-magnetic post is elongated in the radial directions from a first magnetic flux carrier portion to a second magnetic flux carrier portion of the magnetic flux carrier portions on the opposite sides of the at least one magnetic flux barrier. |
| US11095196B2 |
Manufacturing method of motor core, manufacturing method of rotor core, and manufacturing method of rotor
A manufacturing method of a motor core includes laminating in an axial direction steel plates extending in a radial direction with respect to a central axis, each of the laminate steel plates including a base portion on a radially outer side of the central axis, annular portions separately disposed on a radially outer side of the base portion with penetrating portions therebetween, and connecting portions at predetermined intervals in a circumferential direction to extend in the radial direction and connect the base portion and the annular portions, the annular portions including coupling portions adjacent to both circumferential sides of the connecting portions, and cutting at least one of the two coupling portions adjacent to one connecting portion in the circumferential direction from an outer side to an inner side of the laminate steel plates in the radial direction with respect to the laminate steel plates that are laminated. |
| US11095195B2 |
Method and arrangement for assembling an electric motor or generator
A method of assembling an electric motor or generator having an annular first element mounted on a circumferential mounting surface of a second element, the method comprising placing a heating coil within an inner annular surface of the annular first element; applying a current to the heating coil to heat the inner annular surface of the annular first element to a temperature that results in the inner annular surface of the annular first element increasing in diameter to allow the annular first element to be mounted on or over the circumferential mounting surface of the second element; and cooling the annular first element to form an interference fit between the annular first element and the circumferential mounting surface of the second element. |
| US11095194B2 |
Method for producing stacked core
To suppress positional deviations of magnetic members of a stacked core and prevent damage thereto when the stacked core is attached to a case. A method for producing a stacked core including a stack of foil-shaped magnetic members for fixation to a case with a fastening bolt includes preparing magnetic members each having formed therein a positioning opening, and a tubular collar adapted to be fastened to the case with the fastening bolt inserted therethrough, the tubular collar having a first receiving face for a head of the fastening bolt and a second receiving face for the case, stacking the magnetic members while arranging the collar within the opening, impregnating gaps between the stacked magnetic members as well as gaps between the openings of the magnetic members and the outer peripheral face of the collar with resin, and integrating the magnetic members with the collar by curing the resin. |
| US11095193B2 |
Electronic power module for a power tool having an integrated heat sink
An electronic switch module for a power tool having an electric motor is provided, including a printed circuit board (PCB), power switches mounted on the PCB and configured to switchably supply electric power from a power source to the electric motor, a series of primary heat sinks mounted on the PCB in association with the power switches, and a secondary heat sink mounted on the primary heat sinks. Output wires attached to the PCB to facilitate electrical connection between the power switches and the electric motor are passed through a slot of the secondary heat sink. |
| US11095190B2 |
Power unit structure for vehicle
A power unit structure for a vehicle includes a motor disposed in a power unit room of the vehicle and configured to transmit a driving force to drive wheels of the vehicle, an electric power converter disposed in the power unit room of the vehicle, and an electric power distributor disposed in the power unit room of the vehicle. The electric power converter is configured to convert supplied electric power into electric power to be supplied to the motor and is disposed on an upper side of the motor. The electric power distributor is configured to distribute electric power supplied from a power supply to the electric power converter and is disposed at a position where at least a part of the electric power distributor overlaps the electric power converter in an up-down direction of the vehicle when viewed from a vehicle front-rear direction or a vehicle width direction. |
| US11095189B2 |
Driving mechanism
A driving mechanism is provided. The driving mechanism connects with a frame and a driving wheel by two ends thereof. The driving mechanism includes a motor housing, a motor assembly and a driving controller. The motor housing supports the frame and defines an inner space. The motor assembly is detachably assembled with the motor housing and located in the inner space. The motor assembly drives the driving wheel. The driving controller is detachably assembled with the motor housing, located in the inner space, and electrically connected with the motor assembly. |
| US11095188B2 |
Hollow rotor shaft for rotating electrical machine, associated rotor and method
The hollow rotor shaft for a rotating electrical machine includes two parts. A first part includes a first hollow cylindrical element and a second part includes a second hollow cylindrical element, whereby sections of a first end of the first and second elements are in contact and secured by securing means. |
| US11095185B2 |
Motor assembly
A motor assembly is provided, which includes a motor having a stator and a rotor rotatable relative to the stator, and a filter unit mounted to an outside of the motor. The filter unit includes an insulating housing and at least one filter element arranged in the housing and electrically connected to the motor. |
| US11095184B2 |
Magnetic seal for magnetically-responsive devices, systems, and methods
A magnetically-responsive device (100) having a magnetic seal (160,170) to retain magnetically responsive material within a defined space (150) is provided. The magnetically-responsive device (100) has a shaft (110), a rotor (130), a magnetic field generator (145), a magnetically-responsive medium and a magnetic seal (160,170). The seal (160,170) is preferably a non-contact seal (160,170) that does not deteriorate over time and generates little to no resistance. |
| US11095178B2 |
Motor having concentratedly-wound stator coil
A motor includes a stator that has pole cores and a stator coil comprised of unit coils each being concentratedly wound around a corresponding one of the pole cores. Each of the unit coils is comprised of first and second sub-coils that are stacked in two layers in a stacking direction. Each of the first and second sub-coils is spirally wound so that coil sides of the sub-coil overlap each other in an overlapping direction perpendicular to the stacking direction. Each of the unit coils also has, at a single place, a connecting portion that connects the first and second sub-coils of the unit coil. The connecting portion is provided in a coil end of the unit coil. For each of the first and second sub-coils of the unit coil, the connecting portion is located at an innermost periphery of the sub-coil in the overlapping direction of the sub-coil. |
| US11095175B2 |
Motor
The current invention relates to a magnetic pole arrangement comprising a plurality of magnetic pole assembles arranged back-to-back along a longitudinally extending axis of rotation X. Each providing flux to an air gap G. Each magnetic pole assembly comprising one or more magnetic poles pieces and two components of magnetic flux. The first component of magnetic flux provided by a plurality of axially magnetised axially displaced magnets arranged in circumferentially extending arrays. The second component of magnetic flux provided by a plurality of circumferentially magnetised magnets circumferentially spaced around the axis of rotation X. |
| US11095170B1 |
Wireless charging
A system and method for improving ASK packet transfer reliability and power dissipation efficiency at light-load or no-load conditions of a receiving device is provided. In an embodiment, the receiving device includes a dissipating element coupled to a rectifier. The dissipating element is connected to a reference voltage at a first duration corresponding to a transmission of the ASK packet. The dissipating element is disconnected from the reference voltage a second duration corresponding to an end of the transmission of the ASK packet. |
| US11095169B2 |
SWIPT signal receiver and SWIPT signal receiving method
A receiver that receives a simultaneous wireless information and power transfer (SWIPT) signal is provided. The receiver comprises an antenna configured to receive a SWIPT signal including a power signal and an information signal; an energy harvester configured to receive the SWIPT signal from the antenna when a communication mode is an energy harvesting (EH) mode; and an information decoder configured to receive the SWIPT signal from the antenna when the communication mode is an information decoding (ID) mode. |
| US11095166B2 |
Multiple beam wireless power transmission system
A system for transmitting wireless power from multiple sources to multiple receivers, in which the safety of the system is maintained in spite of the possibility that two beams may intersect in the transmission space, thereby generating power or power density levels which exceed those at which the safety mechanisms of the system were designed to operate. The paths of the beams are known from the transmission positions and directions, and from the positions and orientations of the receivers, as measured by positioning devices on them. When an intersection, or near intersection of beams is determined, the system is triggered to reduce the safety risk by attenuating or turning off, or by diverting, one or more of the beams. In addition, since a reflected beam's path may not be readily discernable, the system can ascertain if one of the beams has undergone a reflection, by looking for displayed mirror images. |
| US11095164B2 |
Wireless power transfer
A method of generating a DC power from incident RF waves, includes, in part, measuring the amount of power being received by a device generating the DC power, and controlling the phases of the RF waves being transmitted by a multitude of RF transmitters in accordance with the measured power. A programmable test load is optionally used at the device to measure the received power. The device optionally includes, an antenna, an RF-to-DC converter to generate the DC power, an impedance matching/transformation circuit, and an RF load/matching circuit. |
| US11095156B2 |
Power conversion device and non-contact power supplying system
A power conversion device comprises an inner coil which can transmit power between an external coil by coupling magnetically with the external coil, an inverter whose AC side is connected to the inner coil and power conversion can be performed between the AC side and a DC side and a bidirectional DC/DC converter which comprises an intermediate capacitor, is connected to the DC side of the inverter and can perform power conversion bidirectionally between a DC power source, which is connected to a side which is opposite to the side of the inverter, and the inverter, wherein in switching operation from power reception to power transmission where power reception operation is switched to power transmission operation, after control of discharging charges which are accumulated in the intermediate capacitor is performed, the power transmission operation is started. |
| US11095149B2 |
Uninterruptible power supply
In an uninterruptible power supply, first connection members that connect input side-switches of a plurality of uninterruptible power supply modules to each other and that connect output-side switches of the plurality of uninterruptible power supply modules to each other, and second connection members connected in parallel to the first connection members are disposed at positions accessible from a front side of the uninterruptible power supply modules. |
| US11095146B2 |
HW and methods for improving safety protocol in wireless chargers
An over-voltage protection circuit and methods of operation are provided. In one embodiment, a method includes monitoring a voltage at an output of a rectifier, a voltage at an output of a voltage regulator, or a combination thereof. The method further includes determining the over-voltage condition based on the monitoring; and in response to determining the over-voltage condition, regulating the voltage at the output of the rectifier in accordance with a voltage difference between the voltage at the output of the rectifier and the voltage at the output of the voltage regulator. |
| US11095144B2 |
Wireless charging cradle
A wireless charging cradle for stowing and charging an electronic device includes a block that is resiliently compressible. A recess is positioned in an upper face of the block and is configured to position an electronic device of a user. A battery is selectively positionable in a slot that extends into a front of the block. A wireless charging pad is coupled to the block and is positioned at a lower end of the recess. The wireless charging pad is operationally coupled to the battery and is configured to charge the electronic device that is positioned in the recess. |
| US11095143B2 |
Battery control unit
A battery control unit includes an estimation device, a setting device, and a control device. When an open circuit voltage of the battery falls within a range of a flat region, the setting device sets the control storage amount to a first storage amount determined from the lower limit voltage of the flat region, the control device charges the battery until the open circuit voltage becomes a first voltage exceeding the upper limit voltage of the flat region after a vehicle comes into a drivable state, and the setting device sets a storage amount estimated by the estimation device to a control storage amount until the open circuit voltage reaches the first voltage, and sets a second storage amount determined from the open circuit voltage to the control storage amount after the open circuit voltage reaches the first voltage. |
| US11095129B2 |
Capacitor based power system and unmanned vehicle with the capacitor based power system thereof
The present disclosure provides an unmanned vehicle comprising a device to be powered; a capacitor energy storage system (CESS) and controller board for at least temporarily powering and operating the device to powered. Further, the CESS includes one or more metacapacitors as an energy storage medium. Additionally, the disclosure provides a capacitor energy storage cell composed of the at least one metacapacitor and a DC-voltage conversion device, where the output voltage of the metacapacitor is the input voltage of the DC-voltage conversion device. Still further, the CESS may be comprised of a module of said capacitor energy storage cells, or a system of modules of said capacitor energy storage cells. |
| US11095127B2 |
Method for real-time scheduling of multi-energy complementary micro-grids based on rollout algorithm
The invention relates to a method for real-time scheduling of multi-energy complementary micro-grids based on a Rollout algorithm, which is technically characterized by comprising the following steps of: Step 1, setting up a moving-horizon Markov decision process model for the real-time scheduling of the multi-energy complementary micro-grids with random new-energy outputs, and establishing constraint conditions for the real-time scheduling; Step 2, establishing a target function of the real-time scheduling; Step 3, dividing a single complete scheduling cycle into a plurality of scheduling intervals, and finding one basic feasible solution meeting the constraint conditions for the real-time scheduling based on a greedy algorithm; and Step 4, finding a solution to the moving-horizon Markov decision process model for the real-time scheduling of the multi-energy complementary micro-grids by using the Rollout algorithm based on the basic feasible solution from Step 3. With the consideration of the fluctuations in the new-energy outputs, the present invention solves the problems of low speed and low efficiency of a traditional algorithm at the same time, enabling high-speed efficient multi-energy complementary micro-grid real-time scheduling. |
| US11095126B2 |
Anti-islanding protection system
Provided is an anti-islanding protection system. The system is applied to a low-voltage distributed generation resource (DGR) and includes a box, a reverse power protector, a protection module and an output controller. The reverse power protector has an end connected to a first current transformer and has another end connected to the output controller. The reverse power protector is configured to provide reverse power protection for the low-voltage DGR. The output controller has an end connected to the protection module and the reverse power protector and has another end connected to a grid-connection switch of the low-voltage DGR. The output controller is configured to control the grid-connection switch to turn off when reserve power is detected. The protection module has an end connected to a second current transformer and has another end connected to the output controller. The protection module is configured to provide low-frequency protection, over-frequency protection, over-voltage protection and low-voltage protection for the low-voltage DGR. |
| US11095121B2 |
Electrostatic discharge protection circuit having variable schmitt trigger characteristics
An electrostatic protection circuit with variable Schmitt trigger characteristics is provided. The electrostatic protection circuit uses a Schmitt trigger circuit to protect an integrated circuit against an overvoltage. The Schmitt trigger circuit includes first and second branches bridged between a power supply rail and a ground rail. The Schmitt trigger circuit operates with a narrow hysteresis width when the second branch is connected in parallel to the first branch and with a wide hysteresis width when the second branch is not connected in parallel to the first branch. The electrostatic protection circuit discharges an overvoltage of the power supply rail using a narrow hysteresis width when a weak overvoltage is applied to the power supply rail, and discharges an overvoltage of the power supply rail using a wide hysteresis width when a strong overvoltage is applied to the power supply rail. |
| US11095116B2 |
Fuse life management in an electric mobile application
A system includes a vehicle including a motive electrical power path; a power distribution unit having a current protection circuit disposed in the motive electrical power path, the current protection circuit comprising a fuse; a controller, comprising: a fuse status circuit structured to determine a fuse event value; a fuse management circuit structured to provide a fuse event response based on the fuse event value; and a fuse life description circuit structured to determine a fuse life remaining value, wherein the fuse event value comprises a representation that the fuse life remaining value is below a threshold value, and wherein the fuse management circuit is further structured to provide the fuse event response further based on the fuse life remaining value. |
| US11095115B2 |
System, method, and apparatus for power distribution in an electric mobile application using a combined breaker and relay
A system includes a housing; and a breaker/relay device positioned in the housing, wherein the breaker/relay device is configured to interrupt a motive power circuit for an electrical vehicle system, where the housing is disposed on the electrical vehicle system, where the breaker/relay device includes a physical opening response portion responsive to a first current value in the motive power circuit, and a controlled opening response portion responsive to a second current value in the motive power circuit, where the physical opening response portion is structured to be adjustable to at least one adjustment operation. |
| US11095113B2 |
Systems and methods for lightning protection in power distribution modules
A power distribution system includes a solid state power controller (SSPC). The SSPC includes a microcontroller having at least one voltage sense input. The microcontroller is configured to selectively allow a current through the SSPC in response to a common mode voltage to ground and/or a SSPC differential voltage meeting or exceeding a respective pre-determined threshold. A method of operating a SSPC includes determining whether at least one of a common mode voltage to ground or a SSPC differential voltage meet or exceed a respective pre-determined threshold. The method includes selectively allowing a current through the SSPC in response to at least one of the common mode voltage to ground or the SSPC differential voltage meeting or exceeding the respective pre-determined threshold. |
| US11095111B2 |
Systems and methods for transient pulse protection
Systems and methods described herein a sensor integrated circuit (IC) is provided having a protection circuit configured to protect circuitry within the IC from a transient pulse on a connection (i.e., power pin) to a power supply that is configured to provide power to the IC. The protection circuit can be disposed in a current path between a power pin of the IC and additional circuitry or nodes within the IC, such as but not limited to, a regulator or a bi-directional current source. The protection circuit includes a reverse blocking device having a first terminal coupled to the power supply at which a predetermined power supply voltage is provided and a second terminal coupled to an input of the regulator. |
| US11095110B1 |
Energy harvesting from fault currents
Methods and systems for protecting one or more flexible alternating current transmission system (FACTS) devices in a high voltage (HV) power transmission line are disclosed. The system may include a circuit breaker to de-energize the HV power transmission line when a fault current is detected on the HV power transmission line, and to determine whether the fault current has cleared. The system may further include a power supply to harvest energy from the fault current. The system may further include a bypass switch coupled to protect the FACTS devices by providing a controllable conduction path around the FACTS devices when the bypass switch is activated. And the system may further include a fault current harvesting circuit (FHC) and an actuator operating in conjunction to control the bypass switch based on the harvested energy. |
| US11095107B2 |
Electronic protection device
An electronic protection device (1) for a LV electric line (100) including one or more conductors (P, N), comprising: one or more pairs of electric contacts (2) electrically connectable with corresponding conductors of said electric line and adapted to be mutually coupled or decoupled, said electric contacts being coupled when said protection device is in a closed state and being decoupled when said protection device is in a tripped state or open state; a control unit (3) comprising a controller (31) including data processing resources, said controller being capable of testing the operating conditions of said electronic protection device; a signalling arrangement (7) including one or more signalling devices (71) driven by said controller. Said signalling arrangement comprises a first signalling device (71) adapted to provide light signals (L1, L2, L3) indicative of the operating conditions for said electronic protection device, when said electronic protection device is in a closed state. |
| US11095106B2 |
Configurable electrical receptacles
This invention relates to configurable electrical receptacles and more particularly to electrical receptacles that accept in-situ replacement of an insert providing a specific functionality within an electrical receptacle which is configurable to function or user accessible feature. |
| US11095103B2 |
Disintegrating binders for multi-member cable
A multi-member cable includes at least a first cable element and a second cable element. The first and second cable elements may extend in parallel, be stranded in a helical winding pattern, or be stranded in a reverse-oscillatory winding pattern, along the length of the cable. At least one binder is helically wrapped about the first and second cable elements to hold them together. The binder is formed of a material which disintegrates when exposed to a particular liquid or heat. In a preferred embodiment, the binder may be formed of polyvinyl-alcohol (PVA). |
| US11095102B2 |
Repurposing pipeline for electrical cable
The disclosure relates to the field of electric power infrastructure and repurposing existing oil and gas pipeline, or other pipelines which are no longer in use for their original purpose, for installation of conduits and electrical cables/conduits, typically underground, for electric power transmission. |
| US11095097B2 |
Integrated semiconductor optical amplifier and laser diode at visible wavelength
An integrated semiconductor optical amplifier-laser diode (SOA-LD) device includes a laser diode (LD) section fabricated on a substrate, a semiconductor optical amplifier (SOA) section fabricated on the substrate adjacent to the LD section; and a trench formed at least partially between the LD section and SOA section to electrically isolate the LD section and the SOA section while maintaining optical coupling between the LD section and the SOA section. |
| US11095095B2 |
Low cost external cavity diode lasers
External cavity diode laser (ECDL) devices and methods for producing the same are described that allows ECDLs to be readily produced and configured to operate at a desired range of wavelengths, while allowing tunability of the output wavelength. One ECDL includes a laser gain chip including a gain medium, a first reflective surface at a first end of the gain medium, and a second surface at a second end of the gain medium opposite to the first reflective surface. The second surface has a facet that forms an angle approximately equal to Brewster's angle for light having a first wavelength. The ECDL further includes a diffraction grating positioned to receive light that passes through the second surface, to operate as a mirror in the external cavity diode laser, and to allow a portion of the light to be directed outside of the external cavity diode laser as output light. |
| US11095093B2 |
Laser driver with high-speed and high-current and current modulating method thereof
A laser driver with high-speed and high-current and current modulating method thereof is invented. The laser driver includes a first driving unit and a second driving unit, each driving unit including a pre-drive amplifier circuit and a main drive amplifier circuit. The pre-drive amplifier circuit includes a first differential transistor pair circuit, a differential voltage conversion circuit, a DC common mode level reduction circuit and a first cascode current mirror circuit. The main drive amplifier circuit includes a second differential transistor pair circuit, a bandwidth boost circuit, a matching circuit and a second cascode current mirror circuit. The present invention avoids the enhancement of chip area caused by the use of passive inductors peaking mode to enhance bandwidth, and reduces the cost of chip, design complexity and circuit power consumption. |
| US11095090B2 |
Laser module and laser projection device
A laser module includes an encapsulating support, at least one laser, a sealing gasket, and a pressing plate. Each laser includes a supporting plate and a laser body that is fixed to the supporting plate. The supporting plate is fixed on the encapsulating support, and a surface of an end of the laser body away from the supporting plate is a light exit end face. The sealing gasket is located on a surface of the supporting plate close to the light exit end face, and the sealing gasket has a first opening at a position corresponding to the laser body. A pressing plate is located on a surface of the sealing gasket away from the supporting plate; the pressing plate is fixedly connected to the encapsulating support, and the pressing plate has a second opening at a position corresponding to the first opening. |
| US11095086B2 |
Amplification optical fiber, fiber laser device, and optical resonator
An amplification optical fiber includes: a core; an inner cladding having a refractive index lower than a refractive index of the core, wherein an active element pumped by pumping light is entirely doped to the core, and a relative effective refractive index difference of light in an LP01 mode is greater than or equal to 0.05% and a relative effective refractive index difference of light in an LP21 mode is less than 0.05% in light propagating through the core. |
| US11095084B1 |
Laser system with isolated optical cavity
In various embodiments, laser resonator modules produce output beams via manipulation of input beams on opposite sides of the module. The input beams are emitted by one or more beam emitters that may be cooled using a liquid coolant cavity. The liquid coolant cavity may be isolated from optical elements utilized to manipulate the input beams, at least in part, by an isolation wall protruding from the base plate of the resonator module. |
| US11095074B2 |
Electric connection plug with locking function
The present invention provides an electrical connection plug, comprising: a housing; an electrical connection point provided on the housing, to achieve electrical connection with a receptacle, wherein the receptacle has a jack; a locking component and an actuating component, both of which are provided on the housing, wherein the locking component is used to be inserted into the jack. The locking component comprises a latch, which is connected to the actuation component to be driven by the actuation component to move with respect to the housing, wherein the latch is provided with a first inclined surface; a locking plate, which is provided outside the latch, wherein the locking plate is provided with a second inclined surface corresponding to the first inclined surface. The present invention achieves the locking between the electrical connection plugs in a new way. |
| US11095069B2 |
Coupling member for electrical connection
A wet-mateable coupling member for making an electrical connection having: a body having a cavity wall which defines an internal cavity, and a hollow sleeve located inside the internal cavity. The sleeve is arranged in the internal cavity to define: an outer chamber between the sleeve and the cavity wall. The sleeve defines an inner chamber inside the sleeve. The sleeve has an electrically-insulating layer and an electrically-conductive layer. The electrically-conductive layer defines an outer surface of the sleeve in the outer chamber and has a semi-conductive layer, the semi-conductive layer being a conductive elastomer. An electrical contact is adapted to be housed inside the inner chamber and configured for making the electrical connection. |
| US11095067B2 |
Electrical connector with waterproof structure
The present invention provides a connector with waterproof structure and the manufacturing method, comprising: an base, providing the support of components in the connector; housing, enclose the components inside of the connector; the connecting groove, located on the base with slot shape; the connecting unit, mounted on the connecting groove and penetrated out with the base; the first retaining block, disposed between the connecting groove and the outer wall of the housing, separating the upper end of the base into a plurality of waterproof compartments, wherein the waterproof compartment is filled with waterproof glue; and the upper lid, upper lid, sealing the upper end of the base to achieve the purpose of preventing moisture and dust particles from entering the connector. |
| US11095066B2 |
Electrical apparatus
An electrical apparatus may include: a housing accommodating an electrical device; and a connector connected to an outer surface of the housing, in which the connector includes: a connector body including a terminal electrically connected to the electrical device; an upper shell covering a back surface of the connector body; a lower shell fixed to a lower portion of the connector body and to which a shield tube surrounding a cable connected to the terminal is fixed; and a guard plate fixed to the lower shell and extending between the upper shell and the connector body. |
| US11095059B2 |
Connector
A connector includes: half body parts each including a connector body, and a plurality of terminals attached to the body; end parts formed on both ends of the body formed by allowing the bodies to abut each other; and reinforcing brackets attached to the respective end parts. Each of the bodies is a member integrated with the terminals by primary insert molding, and includes a protrusion extending in the longitudinal direction and holding the terminals, and an embedded part connected to both ends in the longitudinal direction of the protrusion. The end part includes a covering part covering at least the embedded part of each of the bodies, and the covering part is a member integrated with the embedded part and the bracket by secondary insert molding. The connector allows for the spacing between protrusions to be narrowed, simplifying manufacturing, reducing size, and improving reliability. |
| US11095058B2 |
Multichannel connector and assembly thereof
A multichannel connector assembly includes a plug connector comprising an insulation body, a plurality of conductive terminals, and a shield housing enclosing outside the insulation body, and a socket connector comprising an insulation base, a plurality of docking terminals housed in the insulation base, and a shell enclosing outside the insulation base. The shell includes an inter-buckling portion elastically deformable and provided with an inter-buckling protruding portion and an inter-contacting protruding portion. The inter-buckling protruding portion is capable of engaging with an opposite connector, and the inter-contacting protruding portion is capable of forming a grounded potential connection to the opposite connector by elastically deforming. A ring side portion provided by the shield housing, the base portion and the side end portions provided by the insolation body encircle to form a cut-off region where the conductive terminal soldering portion is arranged. |
| US11095057B2 |
Contact with a press-fit fastener
An electrically conductive contact is disclosed and includes a fastening section integrally joined between a body and a tapered lead-in section. The fastening section is adapted for press-fitting into a hole of a substrate, such as a printed circuit board. The fastening section includes a pair of beams with a web joined in-between. The web has a center portion disposed between a pair of ramp portions. Each of the ramp portions has a sloping planar surface. The center portion has an opening extending therethrough and is offset in a normal direction. The fastening section is configured such that when the fastening section is press-fit into the hole of the substrate, the beams deflect both laterally and angularly. |
| US11095056B2 |
Electrical connector with reduce distance between electrical terminals
An electrical connector includes a seat and two electrical terminals. The two electrical terminals are disposed within the seat. Each electrical terminal includes a terminal body and a mounting portion. Each terminal body includes a front end, a rear end, and two lateral edges opposite to each other. The two lateral edges are connected to the front end and the rear end. The mounting portion is extending from the rear end. The terminal body further includes one or more bending wings formed on one of the two lateral edges. The bending wing is located on an inner side of the terminal body. The inner sides of the terminal bodies face each other, and the terminal bodies of the two electrical terminals are arranged in parallel, and the mounting portions of the electrical terminals are located at different heights so as to be arranged in misalignment. |
| US11095052B2 |
Wiring terminal
Disclosed is a wiring terminal, which includes: a conductive member, an elastic piece and a handle; when the handle is in a first position, the elastic piece resists the conductive member under an acting of an elastic force; and when the handle moves from the first position to a second position along a sliding track, the handle acts on the elastic piece to deform the elastic piece, and separate from the conductive member to form a gap for facilitating a wire drawing or a wire plugging. Compared with the existing wiring terminal with a rotary wrench, a wiring terminal provided in the present embodiment may use a tool to drive a handle to move, which may effectively avoid the case where the wire is loosened due to the misoperation causing the open of the handle after the wire is connected. |
| US11095049B2 |
Aluminum electric wire crimping terminal, crimping device and crimping method
An aluminum electric wire crimping terminal formed by connecting an aluminum electric wire and a crimping terminal includes a low compression concave portion and a high compression concave portion in a crimping portion. The high compression concave portion compresses a plurality of core wires with a stronger compression force than a compression force of the low compression concave portion. |
| US11095048B2 |
Multiple band antenna structures
Various antenna designs are presented that can be used to provide for wireless communication in electronic devices, such as wearable electronic devices. Various embodiments provide antenna structures and designs that can support multiple frequency bands in a relatively compact space. Various embodiments utilize a slot and patch antenna design to support multiple frequency bands. Other embodiments utilize a slot and inverted “F” antenna (IFA) assembly, hybrid slot antenna assembly, or external slot antenna assembly. A split ring antenna assembly can also be used, where individual segments of the ring antenna can support specific frequency bands. Other embodiments utilize a dielectrically loaded planar inverted “F” antenna (PIFA) assembly to support various frequency bands. |
| US11095045B2 |
Slow wave structure for millimeter wave antennas
Length matching and phase matching between circuit paths of differing lengths is disclosed. Two signals are specified to arrive at respective path destinations at a predetermined time and with a predetermined phase. An IC provides a first electronic signal over a first conductive path to a first destination and a second electronic signal over a second conductive path to a second destination. A first slow wave structure comprises the first conductive path and a second slow wave structure comprises the second conductive path. The effective relative permittivity of the first slow wave structure is tuned such that the first electronic signal arrives at its destination at a first time and at a first phase, and the effective relative permittivity of the second slow wave structure is tuned such that the second electronic signal arrives at its destination at a second time and at a second phase. |
| US11095032B2 |
Antenna structure
An antenna structure includes a ground plane, a first radiation element, a second radiation element, a third radiation element, and a fourth radiation element. A closed slot is formed in the ground plane. The first radiation element has a feeding point. The first radiation element is coupled to a first shorting point on the ground plane. The second radiation element is coupled to a second shorting point on the ground plane. The second radiation element is adjacent to the first radiation element. The third radiation element is coupled to the feeding point. The fourth radiation element is coupled to a third shorting point on the ground plane. The fourth radiation element is adjacent to the third radiation element. The first radiation element, the second radiation element, the third radiation element, and the fourth radiation element are all disposed inside the closed slot. |
| US11095024B2 |
Radome for base station antenna
A radome for a base station antenna comprises a cover and a bracket. The cover spans over radiators of the base station antenna. The cover includes a front wall, first and second side walls that extend rearwardly from the front wall, and first and second rear flanges that extend inwardly from the respective first and second side walls. The bracket includes a body and first and second mounting flanges that extend forwardly from the body. The first and second mounting flanges cooperate with the respective first and second rear flanges of the cover to connect the cover to the bracket. The radome has an aesthetic appearance, and reduces the possibility that a screw is loosened as a result of lateral wind forces. |
| US11095021B2 |
Wearable device including mutli-band antenna
A wearable device including an outer housing including first, second, and side surfaces, wherein a metal frame is formed on at least a portion of the side surface, a display, a printed circuit board (PCB), a communication circuit disposed on the PCB, and a ground area provided in the PCB, wherein a metal frame is electrically connected to the communication circuit at a first point of the metal frame and is selectively connected to the ground area at a second point of the metal frame, and wherein the communication circuit is configured to transmit and/or receive a signal in a first frequency band by a first electrical path formed if the second point is not connected to the ground area, and transmit and/or receive a signal in a second frequency band by a second electrical path formed if the second point is connected to the ground area. |
| US11095019B2 |
Radio communication device and board
In a radio communication device which employs a millimeter wave, a contact failure which can occur in a case where maintenance is repeatedly carried out is suppressed. A radio communication device (1) includes: a first substrate (11) which includes a radio communication circuit (RFIC 12) that processes a high frequency signal; and a second substrate (21) which includes a baseband circuit (baseband IC 22) that processes the baseband signal. A terminal (14d) to which the baseband signal is supplied from the second substrate (21) is provided in a vicinity of an edge (11a) of the first substrate (11), and the second substrate (21) includes a card-edge connector (23) which supplies the baseband signal to the terminal (14d). |
| US11095017B2 |
Electronic device having angle of arrival detection capabilities
An electronic device may be provided with wireless circuitry that includes first, second, and third antennas used to determine the position and orientation of the electronic device relative to external equipment. The antennas may include patch elements on respective substrates mounted to a flexible printed circuit. Each substrate may include fences of conductive vias that are coupled to ground and that laterally surround the corresponding patch element. Control circuitry may identify phase differences between the first and second antennas and between the second and third antennas and may identify an angle of arrival of received ultra-wideband signals using the phase differences. The control circuitry may compare the phase differences to a set of predetermined surfaces of phase differences to identify environmental loading conditions for the antenna. The control circuitry may correct the angle of arrival using offsets identified based on the environmental loading conditions. |
| US11095011B2 |
RF stripline circulator devices and methods
Microwave circulators are an essentially component in many microwave systems and whilst the waveguide technologies they are implemented in have evolved their design today still employs procedures that are typically approximate and have no regular approach, which in many instances is through dependence on empirical equations or considered a trade secret that gives an edge to commercial suppliers of microwave and RF circulators. The result is expensive isolators where high performance is required as they are merely selected out or require manual tuning. Further, for broadband systems, designer's resort to dividing into sub-bands deploying multiple narrower band circulators. Accordingly, the inventors present a design methodology based on an accurate closed form solution allowing the selection of suitable ferrite specifications for the required operating bandwidth as well as calculating the ferrite disc impedance allowing the necessary matching network to be designed and the circulator design completed. |
| US11095009B2 |
Partial dielectric loaded septum polarizer
In an example embodiment, a waveguide device comprises: a first common waveguide; a polarizer section, the polarizer section including a conductive septum dividing the first common waveguide into a first divided waveguide portion and a second waveguide divided portion; a second waveguide coupled to the first divided waveguide portion of the polarizer section; a third waveguide coupled to the second divided waveguide portion of the polarizer section; and a dielectric insert. The dielectric insert includes a first dielectric portion partially filling the polarizer section. The conductive septum and the dielectric portion convert a signal between a polarized state in the first common waveguide and a first polarization component in the second waveguide and a second polarization component in the third waveguide. |
| US11095008B2 |
Positive electrode plate and electrochemical device
This application relates to a positive electrode plate and an electrochemical device. The positive electrode plate includes a current collector, a safety coating, a difficultly soluble layer and a positive active material layer, wherein the safety coating, the difficultly soluble layer and the positive active material layer are successively disposed on the current collector; wherein the safety coating includes a polymer matrix, a conductive material and an inorganic filler; wherein the difficultly soluble layer includes a binder and a conductive agent, and wherein the binder of the difficultly soluble layer has a solubility in an oil solvent smaller than the solubility of the polymer matrix of the safety coating in such oil solvent. |
| US11095006B2 |
Battery receiving terminal structure
A terminal structure satisfies the relationships of D1 |
| US11095004B2 |
Clamping system and method for laser welding battery foils to a battery tab
A method for laser welding a plurality of battery foils to a battery tab that does not include ultrasonic welding and includes clamping the plurality of battery foils and the battery tab together. Each of the plurality of battery foils has a thickness that is between 0.004 millimeters and 0.03 millimeters. The battery tab has a thickness that is between 0.1 millimeters and 0.5 millimeters. The method further includes laser welding the plurality of battery foils to the battery tab. |
| US11095003B2 |
Energy storage apparatus
Provided is an energy storage apparatus which includes: a plurality of energy storage devices arranged in a first direction; a plurality of bus bars electrically connecting the energy storage devices; and a bundle portion configured by bundling a plurality of electric wires connected to the energy storage device or the bus bar. The bundle portion is configured such that a base portion of the bundle portion is disposed at a position along the energy storage devices. The position is an intermediate position of the plurality of the energy storage devices in the first direction. The bundle portion is configured to change a direction thereof using the base portion as an initiation point. |
| US11095002B2 |
Battery pack
A battery pack includes a series of battery cells, a series of bus bars electrically connecting the series of battery cells, and a terminal member. The terminal member includes a first metal layer extending from an internal connection position connected to at least one of the series of bus bars to an external connection position for supplying output power of the battery pack. The terminal member also includes a second metal layer covering the first metal layer at the external connection position. The second metal layer includes a second metal different from a first metal of the first metal layer. Therefore, the battery pack has an improved structure for stable and low-resistance connection. |
| US11094998B2 |
Ceramic-coated separators for lithium-containing electrochemical cells and methods of making the same
A ceramic-coated separator for a lithium-containing electrochemical cell and methods of preparing the ceramic-coated separator are provided. The ceramic-coated separator may be manufactured by preparing a slurry that includes one or more lithiated oxides and a binder and disposing the slurry onto one or more surfaces of a porous substrate. The slurry may be dried to from a ceramic coating on the one or more surfaces of the porous substrate so as to create the ceramic-coated separator. The ceramic coating may include one or more lithiated oxides selected from Li2SiO3, LiAlO2, Li2TiO3, LiNbO3, Li3PO4, Li2CrO4, and Li2Cr2O7. |
| US11094996B2 |
Additive to ceramic ion conducting material to mitigate the resistive effect of surface carbonates and hydroxides
A method of modifying a carbonate layer formed on a surface of an electrochemical cell component is provided. The surface includes a ceramic oxide. The carbonate layer includes a carbonate and is substantially non-conductive to lithium ions and sodium ions. The method includes contacting the carbonate layer with a modifying agent to form a mixture and causing the modifying agent to incorporate into the carbonate layer and form a modified hybrid layer including a eutectic mixture of the modifying agent and the carbonate. The modified hybrid layer is conductive to lithium ions and sodium ions. |
| US11094995B2 |
Membranes, separators, batteries, and methods
In accordance with at least selected embodiments, novel or improved porous membranes or substrates, separator membranes, separators, composites, electrochemical devices, batteries, methods of making such membranes or substrates, separators, and/or batteries, and/or methods of using such membranes or substrates, separators and/or batteries are disclosed. In accordance with at least certain embodiments, novel or improved microporous membranes, battery separator membranes, separators, energy storage devices, batteries including such separators, methods of making such membranes, separators, and/or batteries, and/or methods of using such membranes, separators and/or batteries are disclosed. In accordance with at least certain selected embodiments, a separator for a battery which has an oxidation protective and binder-free deposition layer which is stable up to 5.2 volts or more, for example, up to 7 volts, in a battery is disclosed. The deposition layer is preferably a thin, very thin or ultra-thin deposition on a polymeric microporous membrane applied via a binder-free and solvent-free deposition method. By employing such an ultra-thin deposition layer, the energy density of a battery may be increased. In accordance with at least particular embodiments, the battery separator membrane described herein is directed to a multi-layer or composite microporous membrane battery separator which may have excellent oxidation resistance and may be stable in a high voltage battery system up to 5.2 volts or more. In accordance with at least other certain selected embodiments, the present invention is directed to a separator for a battery which has a conductive deposition layer which is stable up to at least 5.2 volts or higher in a battery. |
| US11094988B2 |
Regenerative electrical power system with state of charge management in view of predicted and-or scheduled stopover auxiliary power requirements
Systems and methods to control recapture and use of energy to provide an APU include a vehicle having an electrically powered drive axle to provide supplemental torque to the vehicle to supplement primary motive forces applied through a separate drivetrain powered by a fuel-fed engine of the vehicle. The vehicle further includes an energy store to supply the electrically powered drive axle with electrical power or receive energy recovered using the electrically powered drive axle. The vehicle also includes the APU coupled to receive electrical power from the energy store for stopover operation and without idling of the fuel-fed engine. Further, the vehicle includes a hybrid control system for managing, based on an estimated travel time to a stopover location, an SoC of the energy store while the vehicle travels over a roadway to provide a target SoC of the energy store when the vehicle arrives at the stopover location. |
| US11094987B2 |
Battery pack to support and fix battery module
Disclosed is a battery pack, which includes a battery module having a plurality of battery cells; a pack housing configured to accommodate the battery module; and a flexible rib formed at an inner side of the pack housing and having elasticity, the flexible rib pressing the battery module in contact with the battery module. |
| US11094985B2 |
Secondary battery and top cover assembly thereof
The present disclosure provides a top cover assembly of a secondary battery. The top cover assembly includes: a top cover plate and a gas exhaust valve mounted in the top cover plate. The gas exhaust valve includes a valve body, a valve sleeve and a valve cover. The valve body includes a valve part, and the valve part is provided with a gas exhaust hole that communicates with an interior of the secondary battery. The valve cover seals and is connected to the valve body to form an accommodation space. The valve sleeve is located in the accommodation space, and the valve sleeve covers the valve part. A gas exhaust passage is disposed between the valve sleeve and the valve part, the valve cover is provided with a venting hole that communicates with outside, and the gas exhaust passage communicates with the gas exhaust hole and the venting hole. |
| US11094976B2 |
Methods for electrochemical cell remediation
Embodiments described herein relate generally to methods for the remediation of electrochemical cell electrodes. In some embodiments, a method includes obtaining an electrode material. At least a portion of the electrode material is rinsed to remove a residue therefrom. The electrode material is separated into constituents for reuse. |
| US11094975B2 |
Electrolyte level sensing system and method for battery monitoring
An electrolyte monitoring system is disclosed which has an interface module and a sensor assembly. The sensor assembly is attachable to an exterior wall surface of a battery cell for monitoring a level of an electrolyte within the battery cell. The sensor assembly may include an infrared (IR) sensor and a cradle. The IR sensor may be configured to communicate with the interface module and to detect when the electrolyte level within the battery cell drops below a predetermined level. The cradle is configured to be affixed to the exterior wall surface of the battery cell at a desired elevational position in relation to the electrolyte level in the cell. The cradle enables mounting and removal of the IR sensor from the cradle without an external tool. |
| US11094966B2 |
High efficiency electrolytes for high voltage battery systems
Disclosed herein are embodiments of an electrolyte that is stable and efficient at high voltages. The electrolyte can be used in combination with certain cathodes that exhibit poor activity at such high voltages with other types of electrolytes and can further be used in combination with a variety of anodes. In some embodiments, the electrolyte can be used in battery systems comprising a lithium cobalt oxide cathode and lithium metal anodes, silicon anodes, silicon/graphite composite anodes, graphite anodes, and the like. |
| US11094964B2 |
Rechargeable electrochemical cell
A rechargeable electrochemical cell includes a positive electrode having a recharged potential, a negative electrode, and a charge-carrying electrolyte. The rechargeable electrochemical cell further includes an active material having the following structure. (I) |
| US11094963B2 |
Alkali ion conducting plastic crystals
A solid electrolyte represented by general formula LiySiRx(MO4), where x is an integer from 1 to 3 inclusive, y=4−x, each R present is independently C1-C3 alkyl or C1-C3 alkoxy, and M is sulfur, selenium, or tellurium. Methods of making the solid electrolyte include combining a phenylsilane and a first acid to yield mixture including benzene and a second acid, and combining at least one of an alkali halide, and alkali amide, and an alkali alkoxide with the second acid to yield a product d represented by general formula LiySiRx(MO4)y. The second acid may be in the form of a liquid or a solid. The phenylsilane includes at least one C1-C3 alkyl substituent or at least one C1-C3 alkoxy substituent, and the first acid includes at least one of sulfuric acid, selenic acid, and telluric acid. |
| US11094961B2 |
Multi-layered electrode for rechargeable battery including binder having high crystallinity
An electrode for a rechargeable battery, includes: a primer coating layer including PVdF as a first binder and a conductive material formed on a current collector; and an electrode composite layer including a second binder and an electrode active material formed on the primer coating layer, wherein crystallinity of the first binder is 58 or greater. |
| US11094956B2 |
High pressure hydrogen electrical power generator
A hydride heat engine produces electricity from a heat source, such as a solar heater. A plurality of metal hydride reservoirs are heated by the heating device and a working fluid comprises hydrogen is incrementally move from one metal hydride reservoir to a success metal hydride reservoir. The working fluid is passed, at a high pressure, from the last of the plurality of metal hydride reservoirs to an electro-chemical-expander. The electro-chemical-expander has an anode, a cathode, and an ionomer therebetween. The hydrogen is passed from the anode at high pressure to the cathode at lower pressure and electricity is generated. The solar heater may be a solar water heater and the hot water may heat the metal hydride reservoirs to move the hydrogen. The working fluid may move in a closed loop. |
| US11094955B2 |
Apparatus and method for manufacturing membrane-electrode assembly of fuel cell
A manufacturing apparatus of a membrane-electrode assembly for a fuel cell includes: an electrode film sheet supply unit supplying a first electrode film sheet including a first electrode film coated with an anode layer and a second electrode film sheet including a second electrode film coated with a cathode layer; an electrolyte membrane sheet supply unit supplying the electrolyte membrane between the anode layer of the first electrode film sheet and the cathode layer of the second electrode film sheet; a drive bonding roll rotatable by an operation of a first driver; and a driven bonding roll movable closer to or farther apart from the drive bonding roll and pressing the electrolyte membrane and the first and second electrode film sheets with the drive bonding roll. In particular, an engraved portion and an embossing portion are alternately formed on a circumference of the drive bonding roll. |
| US11094947B2 |
Resin frame equipped membrane electrode assembly for fuel cell and method of producing the same
A resin frame equipped membrane electrode assembly includes an MEA having different sizes of components, and a resin frame member. A resin melt portion is provided for the resin frame member. The inside of a first gas diffusion layer is impregnated with resin as a part of the resin melt portion. A thin portion is provided at an outermost peripheral portion of the resin frame member through a step at an outermost peripheral portion of the resin melt portion, and the thin portion is thinner in a thickness direction than the resin melt portion. |
| US11094943B2 |
Processing apparatus for gas-diffusion layer sheets
The processing apparatus includes: a first roller 10 around which a gas-diffusion layer sheet (carbon paper CP) is wound, the gas-diffusion layer sheet being an electrically conductive porous member; a second roller 20 configured to take up the carbon paper CP wound around the first roller 10; and a processing oven configured to heat process a portion of the carbon paper CP, the portion having been fed from the first roller 10 but not yet taken up by the second roller 20. A heat-resistant lead LE is provided, the heat-resistant lead LE having a length at least extending from the first roller 10 to the second roller 20 through the processing oven, being configured to be taken up by the second roller 20, and being bonded to the carbon paper CP impregnated with a thermosetting resin AD. |
| US11094939B2 |
Sulfur-based active material
The present invention provides a sulfur-based active material prepared using an inexpensive polymer material as a starting material and a method of preparing the sulfur-based active material. A non-aqueous electrolyte secondary battery such as a lithium-ion secondary battery provided with an electrode comprising the sulfur-based active material has a large charging and discharging capacity and an excellent cyclability. |
| US11094934B2 |
Electrode slurry, electrode and process for producing the same, and secondary battery
An electrode slurry contains (A) a cellulose fiber and (C) an electrode active material, the electrode active material (C) contains at least a silicon particle and may contain a silicon particle and a carbonaceous particle. The slurry may further contain (B) a carboxymethyl-group-containing cellulose ether or a salt thereof. The average fiber length L (1 to 750 μm) of the cellulose fiber (A) is larger than the average particle size DSi (1 nm to 1 μm) of the silicon particle as the electrode active material (C). The average particle size ratio L/DSi is 5 to 15,000. The electrode slurry can improve a discharge capacity and is useful for forming an electrode of a non-aqueous secondary battery (lithium-ion secondary battery) that can maintain a high discharge capacity after repeated charging and discharging. |
| US11094932B2 |
Hydrogen storage alloy
A hydrogen storage alloy suitable for prescribed pretreatment, that is, pretreatment wherein mechanical pulverization is performed after pulverizing a hydrogen storage alloy and absorbing/desorbing hydrogen is provided. The hydrogen storage alloy comprises a parent phase having a CaCu5-type, that is, an AB5-type crystal structure, wherein the A site is constituted from a rare earth element containing La; and the B site does not contain Co and contains at least Ni, Al, and Mn, with the ratio (Mn/Al) of the content of Mn (molar ratio) to the content of Al (molar ratio) being 0.60 or more and less than 1.56, and the ratio (La/(Mn+Al)) of the content of La (molar ratio) to the total content of the content of Al (molar ratio) and the content of Mn (molar ratio) being more than 0.92. |
| US11094931B2 |
Negative electrode active material for lithium ion secondary battery, negative electrode for lithium ion secondary battery, and lithium ion secondary battery
A negative electrode active material for a lithium ion secondary battery includes silicon oxide particles, each of which has carbon on at least a portion of its surface, in which: a ratio (PSi/PSiO2) of an intensity of an X-ray diffraction peak at 2θ of from 27° to 29°, which is derived from Si, to an intensity of an X-ray diffraction peak at 2θ of from 20° to 25°, which is derived from SiO2, is within a range of from 1.0 to 2.6, when CuKα radiation having a wavelength of 0.15406 nm is used as a radiation source; and a ratio (SH2O/SN2) of a specific surface area calculated from moisture adsorption at 298 K to a specific surface area calculated from nitrogen adsorption at 77 K is 0.60 or less. |
| US11094922B2 |
Methods for producing nonaqueous electrolyte secondary battery and electrode thereof
A negative electrode active material slurry is applied to one surface of a strip-shaped negative electrode core so as to form multiple lines of the negative electrode active material slurry, the lines extending in an X direction and being spaced from each other in a Y direction. Subsequently, while keeping the negative electrode core aloft, first hot air is blown toward the negative electrode core from at least a lower side in a vertical direction, and then, while keeping the negative electrode core aloft, first cooling air having a lower temperature than the first hot air is blown toward the negative electrode core from at least the lower side in the vertical direction so as to decrease the temperature of the negative electrode core to 40° C. or lower. |
| US11094920B2 |
Apparatus and method for manufacturing belt-like electrode
An apparatus for manufacturing a belt-like electrode including: a pair of press rolls configured to press a belt-like current collector foil with an electrode mixture layer along a longitudinal direction in a thickness direction of the electrode mixture layer; and a stretching roll configured to stretch a non-forming part which is the current collector foil without the electrode mixture layer in respective ends in a width direction is provided. The stretching roll includes: a first roll opposed to the electrode mixture layer formed in the current collector foil; and a pair of second rolls arranged in respective ends of the first roll in an axial direction and opposed to the non-forming part, and a central axis of the first roll is deviated with respect to a central axis of the pair of second rolls in a direction away from the stretched current collector foil. |
| US11094919B2 |
Method of vacuum drying film layer and display device
The present disclosure provides a method of vacuum drying a film layer and a display device, the method includes: placing a substrate on which a film layer material is formed in a vacuum drying environment, wherein the film layer material contains a solvent and a solute for forming the film layer; in a first stage, evaporating and condensing the solvent in the film layer material on an upper cover plate, wherein the film layer material still contains an amount of solvent to form a soft film having fluidity; in a second stage, re-condensing a portion of the solvent condensed on the upper cover plate onto the substrate to increase the fluidity of the soft film on the substrate; and repeating the first stage and the second stage, vacuuming to completely evaporate the solvent and cure the film layer after forming a substantially flat film layer. |
| US11094918B2 |
Pixel defining layer, display substrate and manufacturing methods thereof
The present disclosure provides a pixel defining layer, a display substrate and manufacturing methods thereof, and relates to the field of display technology. The pixel defining layer is located on a base substrate, and configured to define a plurality of pixel regions. The pixel defining layer includes: a defining layer body, and a heat generating substance located in the defining layer body. The heat generating substance is configured to cause a temperature on a side of the defining layer body proximal to the base substrate to be lower than a temperature on a side of the defining layer body distal from the base substrate. |
| US11094917B2 |
Cover plate for organic electroluminescent display device and method for manufacturing the same, organic electroluminescent display device and display apparatus
The present disclosure proposes a cover plate for an organic electroluminescent display device and a method for manufacturing the same. The cover plate for the organic electroluminescent display device includes: an auxiliary electrode disposed on a substrate to be electrically connected to an electrode of the organic electroluminescent display device; and a light reflection suppression structure disposed on the auxiliary electrode and configured to suppress reflection of light from a surface of the auxiliary electrode. The present disclosure further proposes an organic electroluminescent display device and a display apparatus. |
| US11094910B2 |
Pixel display component, screen display component, display screen, and terminal
A pixel display component used in a display screen, includes a light-emitting unit and an anode. The anode includes a first anode portion and a second anode portion arranged in a direction parallel to the display screen. The first anode portion includes a light-transmitting material, and the second anode portion includes a non-light-transmitting material. The light-emitting unit is arranged between a cathode and the anode of the display screen, and the anode is arranged between a substrate of the display screen and the light-emitting unit. |
| US11094909B2 |
Thin film of metal oxide, organic electroluminescent device including the thin film, photovoltaic cell including the thin film and organic photovoltaic cell including the thin film
A thin film of amorphous metal oxide includes zinc (Zn), silicon (Si) and oxygen (O), the atomic ratio of Zn/(Zn+Si) being 0.30 to 0.95. |
| US11094906B2 |
Display panel
A display panel is provided, which includes a light-emitting structure. The light-emitting structure includes an anode positioned on a thin film transistor layer, a luminescent material layer positioned on the anode, and a cathode covering the luminescent material layer. The light-emitting structure further includes a cathode reflective layer and a quantum dot film. The cathode reflective layer is positioned above the cathode and is electrically insulated from the cathode by a reflective isolation layer. The quantum dot film is positioned in the reflective isolation layer that is between the cathode and the cathode reflective layer. |
| US11094900B2 |
Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device includes the steps of: forming a first metal interconnection in a first inter-metal dielectric (IMD) layer; performing a treatment process to rough a top surface of the first metal interconnection; and forming a carbon nanotube (CNT) junction on the first metal interconnection. Preferably, the treatment process further includes forming protrusions on the top surface of the first metal interconnection, in which the protrusions and the first metal interconnection comprise same material. |
| US11094895B2 |
OLED display substrate, display panel and manufacturing method thereof
An OLED display substrate, an OLED display panel and manufacturing methods thereof are provided. The OLED display substrate includes a substrate including a main display region, plural side display regions outside plural edges of the main display region, respectively, and plural corner display regions outside every two adjacent edges of the main display region and around intersections of the every two adjacent edges, respectively; and plural display elements on the main display region, the plural side display regions, and the plural corner display regions of the substrate, respectively. At least the plural corner display regions of the substrate are made of a flexible material, plural openings are provided in each of the plural corner display regions, and each opening in each corner display region does not overlap any one of the display elements on the corner display region. |
| US11094886B2 |
Organic electroluminescent element and electronic device
An organic electroluminescence device includes an anode, a cathode, a first emitting layer, and a second emitting layer disposed between the first emitting layer and the cathode, the first emitting layer containing a first host material in a form of a first compound represented by a formula (101) below, the second emitting layer containing a second host material in a form of a second compound represented by a formula (2) below, the first emitting layer and the second emitting layer being in direct contact with each other. |
| US11094885B2 |
Fullerene derivatives and photoelectric device and image sensor
Disclosed are a fullerene derivative including a substituent represented by Chemical Formula 1, and a photoelectric device, an image sensor, and an electronic device including the fullerene derivative. In Chemical Formula 1, X, Ar, and R1 to R3 are the same as defined in the detailed description. |
| US11094882B2 |
Method of manufacturing memory device
A method of manufacturing a memory device includes forming a transistor on a substrate, forming a lower interlayer insulating layer covering the transistor, forming a hydrogen supply layer on the lower interlayer insulating layer, forming a hydrogen blocking layer on the hydrogen supply layer, annealing the transistor, the lower interlayer insulating layer, and the hydrogen supply layer, forming a memory cell on the hydrogen blocking layer after the annealing, and forming an upper interlayer insulating layer surrounding the memory cell and having a third average hydrogen concentration less than the second average hydrogen concentration. |
| US11094876B2 |
Piezoelectric steering engine of bistable and control method thereof
A piezoelectric steering engine of bistable includes a base, four torsion units respectively fixed on the base, and four stiffness devices respectively located at a free end of the four torsion units. The four torsion units share the same structure, and are sequentially arranged at an interval of 90° in a same plane. The four stiffness devices share the same structure and are all connected to rudder blades. Every torsion unit includes a cantilever beam, a first macro-fiber composite actuator and a second macro-fiber composite actuator both of which are respectively attached to two opposite surfaces of the cantilever beam. A first stiffness device includes an elastic ring and a bearing pad mounted inside the elastic ring. After the cantilever beam passes through the bearing pad, a torque is exerted on the cantilever beam by the elastic ring through the bearing pad, resulting in the buckling of the cantilever beam. |
| US11094875B2 |
Methods for manufacturing ultrasound transducers and other components
The disclosed technology features methods for the manufacture of electrical components such as ultrasound transducers. In particular, the disclosed technology provides methods of patterning electrodes, e.g. in the connection of an ultrasound transducer to an electrical circuit; methods of depositing metal on surfaces; and methods of making integrated matching layers for an ultrasound transducer. The disclosed technology also features ultrasound transducers produced by the methods described herein. |
| US11094873B2 |
Transmon qubits with self defined junctions
A method of making a Josephson junction in a superconducting qubit includes providing a substrate having a convex structure with a first face and a second face meeting at an edge; depositing a first layer of superconducting material on the first face; oxidizing the first layer to form a layer of oxide material on a surface of the first layer; and depositing a second layer of the superconducting material on the second face. A portion of the second layer is in contact with a portion of the layer of oxide material at or in the vicinity of the edge such that the portion of the layer of oxide material is sandwiched between a portion of the first layer and the portion of the second layer to define a Josephson junction at or in the vicinity of the edge. |
| US11094872B2 |
Apparatus for thermoelectric generation on HVAC pipes
There is described an apparatus for converting heat dissipated from a pipe of a refrigeration cycle into electric power. The pipe has an outer surface from which heat dissipates. The apparatus comprises at least one TEG receptacle for installing a thermoelectric generator therein, the TEG receptacle comprising a cold side and a hot side. The apparatus further comprises at least one conductive body in thermal contact with at least a portion of the outer surface of the pipe and adapted to conduct the heat from the outer surface of the pipe to the hot side of at least one TEG receptacle. The apparatus further comprises one heat sink for each one of the at least one TEG receptacle, in thermal contact with the cold side thereof. |
| US11094870B2 |
Surface-mountable pixel packages and pixel engines
A method of making a surface-mountable pixel engine package comprises providing an array of spaced-apart conductive pillars and an insulating mold compound laterally disposed between the conductive pillars on a substrate together defining a planarized surface. Pixel engines comprising connection posts are printed to the conductive pillars so that each of the connection posts is in electrical contact with one of the conductive pillars. The pixel engines are tested to determine known-good pixel engines. An optically clear mold compound is provided over the planarized surface and tested pixel engines. Optically clear mold compound is adhered to a tape and the substrate is removed. The optically clear mold compound, the insulating mold compound, the conductive pillars, the optically clear mold compound, and the tested pixel engines are singulated to provide pixel packages that comprise the pixel engines and the known-good pixel engines are transferred to a reel or tray. |
| US11094868B2 |
Method for producing an illumination device and illumination device
A method for producing an illumination device may include providing a plurality of optoelectronic semi-conductor components that each have a semi-conductor layer sequence for generating radiation where the semiconductor components each have at least one contact surface on one side and are held by a common carrier. The method may further include electroplating each contact surface of the semi-conductor components using a solder material, applying the semi-conductor components having the solder material to a substrate, and melting and soldering the contact surfaces onto the surfaces. |
| US11094867B2 |
Display device and method of manufacturing the same
A display device and a method of manufacturing the same are provided. A display device includes: a substrate, a pixel circuit on the substrate, the pixel circuit including: a gate electrode, a drain electrode, and a source electrode, a vertical LED element on the substrate, the vertical LED element including: a first electrode, an active layer under the first electrode, and a second electrode under the active layer, an encapsulation film surrounding the vertical LED element, the encapsulation film exposing a portion of a side of the second electrode, a first connection electrode electrically connected to the first electrode, and a second connection electrode electrically connected to the second electrode. |
| US11094866B2 |
Method for producing an optoelectronic component, and optoelectronic component
A method for producing an optoelectronic component and an optoelectronic component are disclosed. In an embodiment a method includes providing a semiconductor chip having an active region for radiation emission, applying a seed layer on the semiconductor chip, wherein the seed layer includes a first metal and a second metal being different from the first metal, and wherein the second metal is less noble than the first metal, applying a structured photoresist layer directly to the seed layer and applying a solder layer at least to regions of the seed layer which are not covered by the photoresist layer, wherein a ratio of the first metal to the second metal in the seed layer is between 95:5 to 99:1. |
| US11094862B2 |
Semiconductor device with through holes on bonding parts and bonding method thereof
A bonding method of a semiconductor device is disclosed. The method includes steps of forming a plurality of holes on two bonding parts of a main substrate, respectively; disposing a semiconductor device on the main substrate, and aligning the two bonding parts with two conduction parts of the semiconductor device; aligning a laser to the conduction parts and operating the laser to emit a laser beam from a lower part of the main substrate, wherein the laser beam passes through the holes of the bonding part to strike on the conduction part, so as to melt each conduction part to bond with the bonding part. With configuration of the holes, the conduction parts and the bonding part can be smoothly bonded by using laser, so as to achieve the purpose of transferring the semiconductor device. |
| US11094858B2 |
Tape, encapsulating process and optical device
A tape includes at least one tape unit. The tape unit includes a base structure having a first portion and a second portion. The first portion has a first surface and a second surface opposite to the first surface. The second portion protrudes from the second surface of the first portion, and has a third surface opposite to the first surface of the first portion and a lateral surface extending between the second surface and the third surface. An area of the first portion from a top view is greater than an area of the second portion from a top view. |
| US11094855B2 |
Strain-inducing nanostructures for spectral red-shifting of light emitting devices
A nanostructure fabricated on a semiconductor light-emitting device induces strain in the active region. The active device includes at least one quantum heterostructure, in which the strain changes the extent of Quantum Confined Stark Effect, and thus modifies the wavelength of light emission. By mixing strain relaxation and strain induction effects there is a spectral broadening of the light emission, providing polychromatic light emission. |
| US11094852B2 |
Multiple LED light source lens design in an integrated package
Light emitting diode (LED) packages and LED displays utilizing the LED packages are disclosed. LED packages can have a plurality of cavities with each having one or more LEDs. The LEDs can be individually controllable so that the LED package emits the desired color combination of light from the package. The LED packages are arranged with an encapsulant over the cavities that shape the LED package emission to a wide angle or pitch. Some of the LED packages can have three cavities, while others can have four or more cavities. The packages can comprise an encapsulant that forms lenses over the cavities and continues beyond the cavities to cover surfaces of the LED package body. The body can include different anchoring features to improve package reliability by anchoring the encapsulant to the body. One embodiment of an LED display according to the present invention comprises a plurality of LED packages, at least some having a plurality of cavities. Each of the packages comprises a lens over each cavity to produce an emission of the LEDs that has a wider angle compared to the emission without the lens. A potting material can be included between adjacent ones of the LED packages and overlaps the package encapsulant to further improve reliability. |
| US11094849B2 |
Light emitting diode display
A light emitting diode display includes a driving substrate, a plurality of micro light-emitting devices, a first common electrode, and a second common electrode. The micro light-emitting devices are arranged on the driving substrate. Each of the micro light-emitting devices includes an epitaxial structure, a first type electrode, and a second type electrode. The first common electrode is disposed on the driving substrate and located between the second type electrodes of the micro light-emitting devices, wherein the first common electrode exposes at least a portion of an upper surface of each of the second type electrodes. The second common electrode is located between the second type electrodes of the micro light-emitting devices and electrically connected to the first common electrode, wherein the second common electrode does not directly contact the micro light-emitting devices. |
| US11094848B2 |
Light-emitting diode chip structures
Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED chip structures are disclosed. LED chip structures are disclosed that include reduced bonding topography between active LED structures and carrier submounts. For certain LED chip structures, active LED structures are formed on a growth substrate and subsequently bonded to a carrier substrate. Bonding between active LED structures and carrier submounts is typically provided by metal bonding materials. By providing reduced bonding topography between active LED structures and carrier submounts, bonding strength of metal bonding materials may be improved. Electrical connection configurations for certain layers of active LED structures are disclosed that promote reduced bonding topography. Peripheral border configurations of carrier submounts are also disclosed with that promote reduced bonding topography along the peripheral borders. |
| US11094845B2 |
Method of producing light-emitting diode chips and light-emitting diode chip
A method of producing light-emitting diode chips includes A) and C)-F) in order: A) providing a growth substrate, C) producing a structural layer, the structural layer including Alx1Ga1-x1-y1Iny1N, where-in y1≥0.5, and a plurality of structural elements with a mean height of at least 50 nm so that a side of the structural layer facing away from the growth substrate is rough, D) producing a cover layer on the structural layer, the cover layer forming the structural layer true to shape and including Alx2Ga1-x2-y2Iny2N, wherein x2≥0.6, E) producing a planarization layer on the cover layer, a side of the finished planarization layer is flat and the planarization layer includes Alx3Ga1-x3-y3Iny3N, wherein x3+y3≤0.2, and F) growing a functional layer sequence that generates radiation on the planarization layer. |
| US11094844B2 |
Optoelectronic semiconductor chip with two separate light emitting layers
An optoelectronic semiconductor chip includes a p-type semiconductor region, an n-type semiconductor region, an active layer disposed between the p-type semiconductor region and the n-type semiconductor region and formed as a multiple quantum well structure and having alternating quantum well layers and barrier layers, the quantum well layers emitting a first radiation in a first wavelength range, and at least one further quantum well layer disposed outside the multiple quantum well structure that emits a second radiation in a second wavelength range, wherein the first wavelength range is in an infrared spectral range invisible to a human eye, and the second wavelength range includes wavelengths at least partially visible to the human eye. |
| US11094842B2 |
Heterojunction photovoltaic device and fabrication method
A photovoltaic device and method include a doped germanium-containing substrate, an emitter contact coupled to the substrate on a first side and a back contact coupled to the substrate on a side opposite the first side. The emitter includes at least one doped layer of an opposite conductivity type as that of the substrate and the back contact includes at least one doped layer of the same conductivity type as that of the substrate. The at least one doped layer of the emitter contact or the at least one doped layer of the back contact is in direct contact with the substrate, and the at least one doped layer of the emitter contact or the back contact includes an n-type material having an electron affinity smaller than that of the substrate, or a p-type material having a hole affinity larger than that of the substrate. |
| US11094840B2 |
Photovoltaic system with non-uniformly cooled photovoltaic cells
One or more embodiments of the present invention are directed to a photovoltaic system. The system comprises photovoltaic cells, arranged side-by-side to form an array of photovoltaic cells. It further involves a cooling device, which comprises one or more layers, wherein the layers extend opposite to the array of photovoltaic cells and in thermal communication therewith, for cooling the cells, in operation. The one or more layers are structured such that a thermal resistance of the photovoltaic system varies across the array of photovoltaic cells, so as to remove heat from photovoltaic cells of the array with different heat removal rates, in operation. One or more embodiments of the present invention are further directed to related systems and methods for cooling such photovoltaic systems. |
| US11094838B2 |
Texturization method of silicon wafers, product obtained therefrom and preparation method of solar cells
The present disclosure relates to a method for preparing nano-textured surface on single side of a silicon wafer, including the following steps: (1) superimposing two silicon wafers to obtain a first silicon wafer superimposition structure; the side on which the silicon wafers is superimposed is recorded as an attached surface, and the side exposed outside is recorded as an exposed surface; and (2) performing nano-textured surface etching on the first silicon wafer superimposition structure; and providing each silicon wafer with nano-textured surface on the exposed surface and a nano-textured surface etched strip on the edge of the attached surface. In the present disclosure, while the nano-textured surface etching is performed, the edge of the attached surface is etched with nano-textured surface by selecting a specific etching rate, which reduces the pulling force for detaching the wafers and reduces the fragmentation rate during the detaching process. |
| US11094837B2 |
Integrated photodetector
An integrated circuit that includes a substrate, a photodiode, and a Fresnel structure. The photodiode is formed on the substrate, and it has a p-n junction. The Fresnel structure is formed above the photodiode, and it defines a focal zone that is positioned within a proximity of the p-n junction. In one aspect, the Fresnel structure may include a trench pattern that functions as a diffraction means for redirecting and concentrating incident photons to the focal zone. In another aspect, the Fresnel structure may include a wiring pattern that functions as a diffraction means for redirecting and concentrating incident photons to the focal zone. In yet another aspect, the Fresnel structure may include a transparent dielectric pattern that functions as a refractive means for redirecting and concentrating incident photons to the focal zone. |
| US11094833B2 |
Semiconductor device including memory using hafnium and a method of manufacturing the same
A memory cell, which is a nonvolatile memory cell, includes a gate dielectric film having charge storage layer capable of holding charges, and a memory gate electrode formed on the gate dielectric film. The charge storage layer includes an insulating film containing hafnium, silicon, and oxygen, an insertion layer formed on the insulating film and containing aluminum, and an insulating film formed on the insertion layer and containing hafnium, silicon, and oxygen. |
| US11094831B2 |
Semiconductor nanowire device having cavity spacer and method of fabricating cavity spacer for semiconductor nanowire device
Semiconductor nanowire devices having cavity spacers and methods of fabricating cavity spacers for semiconductor nanowire devices are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires including a discrete channel region. A common gate electrode stack surrounds each of the discrete channel regions of the plurality of vertically stacked nanowires. A pair of dielectric spacers is on either side of the common gate electrode stack, each of the pair of dielectric spacers including a continuous material disposed along a sidewall of the common gate electrode and surrounding a discrete portion of each of the vertically stacked nanowires. A pair of source and drain regions is on either side of the pair of dielectric spacers. |
| US11094827B2 |
Semiconductor devices with uniform gate height and method of forming same
The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to replacement metal gate processes and structures for multi-gate transistor devices having a short channel and a long channel component. |
| US11094826B2 |
FinFET device and method of forming same
A FinFET device and a method of forming the same are provided. The method includes forming semiconductor strips over a substrate. Isolation regions are formed over the substrate and between adjacent semiconductor strips. A first recess process is performed on the isolation regions to expose first portions of the semiconductor strips. The first portions of the semiconductor strips are reshaped to form reshaped first portions of the semiconductor strips. A second recess process is performed on the isolation regions to expose second portions of the semiconductor strips below the reshaped first portions of the semiconductor strips. The second portions of the semiconductor strips are reshaped to form reshaped second portions of the semiconductor strips. The reshaped first portions of the semiconductor strips and the reshaped second portions of the semiconductor strips form fins. The fins extend away from topmost surfaces of the isolation regions. |
| US11094824B2 |
Forming a sacrificial liner for dual channel devices
A semiconductor device includes one or more fins. Each fin includes a top channel portion formed from a channel material, and a bottom substrate portion formed from a same material as an underlying substrate. An isolation dielectric layer is formed between and around the bottom substrate portion of the one or more fins. A single oxide layer is formed in direct contact with the bottom substrate portion of each fin, between the bottom substrate portion of each fin and the isolation dielectric layer. A gate dielectric is formed over the one or more fins and between a straight sidewall of at least a top portion of the single oxide layer and an adjacent sidewall of the one or more fins, in contact with both the straight sidewall and the bottom substrate portion. |
| US11094823B2 |
Stress induction in 3D device channel using elastic relaxation of high stress material
A method for inducing stress in a device channel includes forming a stress adjustment layer on a substrate, the stress adjustment layer including an as deposited stress due to crystal lattice differences with the substrate. A device channel layer is formed on the stress adjustment layer. Cuts are etched through the device channel layer and the stress adjustment layer to release the stress adjustment layer to induce stress in the device channel layer. Source/drain regions are formed adjacent to the device channel layer. |
| US11094820B2 |
Mobile ferroelectric single domain wall implementation of a symmetric resistive processing unit
A method of fabricating a symmetric element of a resistive processing unit (RPU) includes forming a substrate with a channel region connecting two doped regions, and forming a source above one of the two doped regions and a drain above the other of the two doped regions. A gate is formed above the channel region, and a bar ferroelectric is disposed above the channel region and below the gate. |
| US11094799B2 |
Thin film transistor and manufacturing method thereof, array substrate and display device
A thin film transistor includes: a bottom gate electrode; a bottom gate electrode insulating layer, a semiconducting active layer and a first insulating layer which are disposed on the bottom gate electrode in sequence; a source electrode and a drain electrode which are disposed at a side of the first insulating layer away from the bottom gate electrode; vias disposed in the first insulating layer at positions which correspond to the source electrode and the drain electrode respectively; and ohmic contact layers disposed on and covering the semiconducting active layer at positions corresponding to the vias respectively. Each of the source electrode and the drain electrode is in contact with a corresponding one of the ohmic contact layers through a corresponding one of the vias. |
| US11094795B2 |
Semiconductor device and method for manufacturing the same
The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a gate electrode, a drain region, a source region, an isolating layer, a plurality of metal contacts, a plurality of conductive plugs, and a contact liner. The gate electrode is disposed on the substrate. The drain region and the source region are disposed in the substrate and on opposite sides of the gate electrode. The isolating layer is disposed over the substrate and the gate electrode. The metal contacts are disposed in the gate electrode, the source region, and the drain region. The conductive plugs are disposed in the isolating layer and electrically coupled to the metal contacts. The contact liner surrounds the conductive plugs. The present disclosure further provides a method for manufacturing the semiconductor device. |
| US11094792B2 |
Manufacturing method of split gate structure and split gate structure
A manufacturing method of a split gate structure includes steps of forming a mask oxide layer on the substrate, performing photolithography and etching on the mask oxide layer and the substrate, forming a trench, removing the mask oxide layer, forming a bottom oxide layer on a bottom part and a side wall of the trench and a surface of the substrate, forming a silicon nitride layer on the trench, removing a part of the bottom oxide layer, forming a gate oxide layer on part of the side wall and the surface, forming a gate poly layer on the trench, removing the silicon nitride layer, forming an inter-poly oxide layer on the gate poly layer, and forming a shield poly layer on the trench, thereby benefiting the increasing of the thickness of the inter-poly oxide layer, so that the advantages of improving the characteristics of the split gate structure are achieved. |
| US11094791B1 |
Vertical transistor device with source/drain regions comprising a twi-dimensional (2D) material and methods of making such vertical transistor devices
One illustrative device disclosed herein includes a bottom source/drain region and a top source/drain region positioned vertically above at least a portion of the bottom source/drain region, wherein each of the bottom source/drain region and the top source/drain region comprise at least one layer of a two-dimensional (2D) material. The device also includes a substantially vertically oriented semiconductor structure positioned vertically between the bottom source/drain region and the top source/drain region and a gate structure positioned all around an outer perimeter of the substantially vertically oriented semiconductor structure for at least a portion of the vertical height of the substantially vertically oriented semiconductor structure. |
| US11094790B2 |
Silicon carbide semiconductor device
A present invention includes the following: a third impurity region having a second conductivity type and disposed in an outer peripheral region that is the outer periphery of a cell arrangement region in which a unit cell is disposed; a field insulating film disposed in the outer peripheral region; an interlayer insulating film; a first main electrode disposed on the interlayer insulating film. The third impurity region includes a fourth impurity region having the second conductivity type, having a higher impurity concentration than the third impurity region. A gate wire and a gate pad are disposed in the outer peripheral region. The fourth impurity region is adjacent to the cell arrangement region, surrounds at least a region below the gate pad, and is electrically connected to the first main electrode. |
| US11094779B2 |
Semiconductor device having an edge termination region comprising a first edge termination region of a second conductivity type adjacent to a second edge termination region of a first conductivity type
An edge delimits a semiconductor body in a direction parallel to a first side of the semiconductor body. A peripheral area is arranged between the active area and edge. A first semiconductor region of a first conductivity type extends from the active area into the peripheral area. A second semiconductor region of a second conductivity type forms a pn-junction with the first semiconductor region. A first edge termination region of the second conductivity type arranged at the first side adjoins the first semiconductor region, between the second semiconductor region and edge. A second edge termination region of the first conductivity type arranged at the first side and between the first edge termination region and edge has a varying concentration of dopants of the first conductivity type which increases at least next to the first edge termination region substantially linearly with an increasing distance from the first edge termination region. |
| US11094776B2 |
Structure and formation method of semiconductor device with magnetic element covered by polymer material
A structure and a formation method of a semiconductor device are provided. The method includes forming a passivation layer over a semiconductor substrate. The method also includes forming a magnetic element over the passivation layer. The method further includes forming an isolation layer over the magnetic element and the passivation layer. The isolation layer includes a polymer material. In addition, the method includes forming a conductive line over the isolation layer, and the conductive line extends across the magnetic element. |
| US11094774B2 |
Organic light emitting diode display device
A display device may include a first substrate, a pixel, a contact electrode, and a side electrode. The pixel may overlap a first face of the first substrate. The contact electrode may be electrically connected to the pixel. A first face of the contact electrode may overlap the first face of the first substrate. The side electrode may be positioned beyond the first substrate. A first face of the side electrode may directly contact a second face of the contact electrode. The second face of the contact electrode may be not parallel to the first face of the contact electrode. |
| US11094773B2 |
Display device
Provided is a display device including a substrate including a display area and a non-display area; a thin-film transistor and a display element on the display area; an organic insulating layer between the thin-film transistor and the display element; a first power supply voltage line arranged to correspond to one side of the display area in the non-display area; a second power supply voltage line spaced apart from the first power supply voltage line; and an inorganic protective layer that covers at least a portion of the second power supply voltage line. The second power supply voltage line includes a first region and a second region. The first region has a stack of a first conductive layer, a second conductive layer, and the organic insulating layer. The second region has a stack of the first conductive layer and the inorganic protective layer. |
| US11094772B2 |
Display panel and display device with compensation sub-pixels
The present disclosure provides a display panel having sub-pixels that include light-emitting sub-pixels and compensation sub-pixels located in a first display area. A density of sub-pixels in a first semi-transmissive area and in a second semi-transmissive area is smaller than a density of sub-pixels in a second display area. The first display area, the first semi-transmissive area, and the second semi-transmissive area have a same density of light-emitting sub-pixels. First pixel columns are provided in the first display area. Second pixel columns are provided in the second display area. A first data line passes through the first pixel column, and a second data line passes through the second pixel column. |
| US11094770B2 |
Array substrate and display panel
An array substrate and a display panel are provided. The display panel includes the array substrate. A bending region and a non-bending region are defined in the array substrate. The non-bending region includes a flexible substrate layer, a composite buffer layer, a source drain layer, a flattening layer and a pixel definition layer that are laminated one another. The bending region includes the flexible substrate layer, the source drain layer, the flattening layer and the pixel definition layer that are laminated one another. Alternatively, thickness of the composite buffer layer located in the bending region is less than thickness of the composite buffer layer located in the non-bending region. |
| US11094769B2 |
Organic light-emitting diode display
An organic light-emitting diode display is disclosed. In one aspect, the display includes a substrate including a pixel area and a peripheral area surrounding the pixel area and an organic light-emitting element formed in the pixel area and including a first electrode, an organic emission layer, and a second electrode. The display also includes a common voltage line formed in the peripheral area and configured to provide a common voltage to the second electrode, wherein the common voltage line and the first electrode are formed of the same material. |
| US11094766B2 |
Array substrate, display panel, and display device
An array substrate, a display panel and a display device are provided. The array substrate includes a plurality of pixel units, wherein each pixel unit includes a storage capacitor including at least three electrode plates parallel to each other, the at least three electrode plates parallel to each other include a first electrode plate, a second electrode plate and a third electrode plate, the first electrode plate is electrically connected to the second electrode plate, the third electrode plate is disposed between the first electrode plate and the second electrode plate, and the first electrode plate and the second electrode plate each have a portion facing towards the third electrode plate. |
| US11094765B2 |
Array substrate, manufacturing method thereof, and display panel
The present disclosure relates to an array substrate, manufacturing method thereof, and a display panel. The array substrate includes a substrate, at least a first top gate TFT and at least a first bottom gate TFT disposed on the substrate and located in each sub-pixel region; a gate of the first top gate TFT and a gate of the first bottom gate TFT are formed in a same layer with same material, an active layer pattern of the first top gate TFT and an active layer pattern of the first bottom gate TFT are respectively arranged on two sides of the gate, and orthographic projections of the active layer pattern of the first top gate TFT and the active layer pattern of the first bottom gate TFT on the substrate are spaced from each other in a first direction. |
| US11094759B2 |
Display device and method of manufacturing display device
A manufacturing method of a display device according to an embodiment of the present invention includes: forming a damming part in a component mounting area of a flexible base material having a display area provided with a plurality of pixels and the component mounting area where a component is mounted; and applying a resin composition to the component mounting area of the base material in a condition in which the component is mounted thereon, in this order. An outer periphery of the applied resin composition reaches a lateral surface of the damming part. |
| US11094758B1 |
Organic light emitting diode (OLED) display device
The present application discloses an OLED display device including an OLED display panel. The OLED display panel has a first display area and a second display area disposed around the first display area, wherein a first pixel electrode layer in the first display area includes at least a two-layered indium tin oxide (ITO) conductive layer, and a second pixel electrode layer in the second display area is a three-layered ITO/Ag/ITO conductive layer. |
| US11094756B2 |
OLED integrated digitizer and method of preparing the same
A digitizer module is formed on a film substrate which is used as a substrate of an OLED module and stacked with the OLED module, thereby providing an OLED integrated digitizer applicable to a flexible display device. |
| US11094754B2 |
Organic light emitting display device and method of fabricating thereof
An organic light emitting display device and a method of fabricating thereof are discussed. The organic light emitting display device according to an example includes a plurality of first bank layers arranged along a first direction and a second direction on a substrate to define a plurality of pixels; a plurality of second bank layers disposed along the first direction on the first bank layers to divide the columns of pixels having different colors; an organic light emitting layer in each pixel; at least one first pocket pixel unit at both sides of the pixel having the smallest area; and a first dummy organic light emitting layer in the first pocket pixel unit. |
| US11094753B2 |
Organic light emitting diode display device and method of fabricating the same
An organic light emitting diode display device includes a substrate; a plurality of driving elements and a plurality of light emitting diodes on the substrate; and at least one dummy pattern on the substrate and including a first electrode, a dummy layer, and a second electrode, wherein the first electrode and the dummy layer are electrically separated from each other. |
| US11094750B2 |
Flexible display panel and preparation method thereof
The flexible display panel includes a plurality of pixel units, each of the pixel units includes a plurality of sub-pixels having at least three emitting colors, and the sub-pixels with a same emitting color are arranged along a predetermined stretching direction. |
| US11094744B2 |
Interconnect landing method for RRAM technology
The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a memory device over a substrate and forming an inter-level dielectric (ILD) layer over the memory device. The ILD layer is selectively etched to define a first cavity that exposes a top of the memory device and to define a second cavity that is laterally separated from the first cavity by the ILD layer. The second cavity is defined by a smooth sidewall of the ILD layer that extends between upper and lower surfaces of the ILD layer. A conductive material is formed within the first cavity and the second cavity. |
| US11094730B2 |
Solid-state imaging device having through electrode provided therein and electronic apparatus incorporating the solid-state imaging device
There is provided a solid-state imaging device including: one or more photoelectric conversion elements provided on side of a first surface of a semiconductor substrate; a through electrode coupled to the one or more photoelectric conversion elements, and provided between the first surface and a second surface of the semiconductor substrate; and an amplifier transistor and a floating diffusion provided on the second surface of the semiconductor substrate, in which the one or more photoelectric conversion elements are coupled to a gate of the amplifier transistor and the floating diffusion via the through electrode. |
| US11094729B2 |
Semiconductor device and method of manufacturing the same, and electronic apparatus
A semiconductor device is provided as a back-illuminated solid-state imaging device. The device is manufactured by bonding a first semiconductor wafer with a pixel array in a half-finished product state and a second semiconductor wafer with a logic circuit in a half-finished product state together, making the first semiconductor wafer into a thin film, electrically connecting the pixel array and the logic circuit, making the pixel array and the logic circuit into a finished product state, and dividing the first semiconductor wafer and the second semiconductor being bonded together into microchips. |
| US11094728B2 |
Image pickup device and electronic apparatus
The present technology relates to an image pickup device and an electronic apparatus that are configured to enhance characteristics. A solid-state image pickup device includes a photoelectric conversion section that is arranged on a semiconductor substrate and configured to photoelectrically convert an incident light, a moth-eye section that includes recesses and projections formed on a surface on a light incident side in the semiconductor substrate and has, when a cross section approximately parallel to a direction toward the photoelectric conversion section from the light incident side is viewed, a recessed portion protruding toward the side of the photoelectric conversion section, the recessed portion having a curvature or a polygonal shape, and a region that is arranged adjacent to and opposite to the photoelectric conversion section of the moth-eye section and has a refractive index different from a refractive index of the semiconductor substrate. |
| US11094727B2 |
Camera module, molding photosensitive assembly thereof, manufacturing method thereof and electronic device
Provided are a camera module, a molding photosensitive assembly and manufacturing method thereof, and an electronic device. The molding photosensitive assembly comprises a molding portion, at least one photosensitive chip and at least one circuit board, wherein the photosensitive chip is provided on the circuit board, the molding portion comprises a molding portion main body, the molding portion main body is made of a transparent material, and the molding portion main body, the photosensitive chip and the circuit board form an integral structure by means of a molding technique, so as to facilitate production. |
| US11094725B2 |
Solid-state imaging device, method of manufacturing the same, and electronic apparatus
Solid-state imaging devices, methods of producing a solid-state imaging device, and electronic apparatuses are provided. More particularly, a solid-state image device includes a silicon substrate, and at least a first photodiode formed in the silicon substrate. The device also includes an epitaxial layer with a first surface adjacent a surface of the silicon substrate, and a transfer transistor with a gate electrode that extends from the at least a first photodiode to a second surface of the epitaxial layer opposite the first surface. In further embodiments, a solid-state imaging device with a plurality of pixels formed in a second semiconductor substrate wherein the pixels are symmetrical with respect to a center point is provided. A floating diffusion is formed in an epitaxial layer, and a plurality of transfer gate electrodes that are each electrically connected to the floating diffusion by one of the transfer gate electrodes is provided. |
| US11094717B2 |
Transistor and display device
It is an object to manufacture a highly reliable display device using a thin film transistor having favorable electric characteristics and high reliability as a switching element. In a bottom gate thin film transistor including an amorphous oxide semiconductor, an oxide conductive layer having a crystal region is formed between an oxide semiconductor layer which has been dehydrated or dehydrogenated by heat treatment and each of a source electrode layer and a drain electrode layer which are formed using a metal material. Accordingly, contact resistance between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer can be reduced; thus, a thin film transistor having favorable electric characteristics and a highly reliable display device using the thin film transistor can be provided. |
| US11094716B2 |
Source contact and channel interface to reduce body charging from band-to-band tunneling
An apparatus is provided which comprises: a source and a drain with a semiconductor body therebetween, the source, the drain, and the semiconductor body on an insulator, a buried structure between the semiconductor body and the insulator, and a source contact coupled with the source and the buried structure, the source contact comprising metal. Other embodiments are also disclosed and claimed. |
| US11094715B2 |
Three-dimensional memory device including different height memory stack structures and methods of making the same
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. The alternating stack includes a first region in which all layers of the alternating stack are present and a second region in which at least a topmost one of the electrically conductive layers is absent. First memory opening fill structures extend through the first region of the alternating stack, and second memory opening fill structures extend through the second region of the alternating stack. The first memory opening fill structures have a greater height than the second memory opening fill structures. Pocket doping regions extending over a respective subset of topmost electrically conductive layers for the memory opening fill structures can be formed to provide higher threshold voltages and to enable selective activation of vertical semiconductor channels connected a same bit line. |
| US11094711B2 |
Memory device
A memory device includes a channel element, a memory element, and an electrode element. The channel element includes a first channel portion, a second channel portion, and a middle channel portion between the first channel portion and the second channel portion. The first channel portion has a first sidewall channel surface and a second sidewall channel surface opposing to the first sidewall channel surface. The middle channel portion has a third sidewall channel surface and a fourth sidewall channel surface opposing to the third sidewall channel surface. The first sidewall channel surface and the second sidewall channel surface of the first channel portion are outside the third sidewall channel surface and the fourth sidewall channel surface of the middle channel portion respectively. A memory cell is defined in the memory element between the channel element and the electrode element. |
| US11094710B2 |
Semiconductor device including stepped structure and supporting structure
A semiconductor device includes a first stepped structure including a first portion and a second portion, a second stepped structure including a third portion on the second portion of the first stepped structure, a first supporting structure penetrating the first portion of the first stepped structure, and a second supporting structure penetrating the second portion of the first stepped structure and the third portion of the second stepped structure. The first supporting structure includes a sidewall having a substantially constant slope, and the second supporting structure includes a sidewall having an inflection point. |
| US11094708B2 |
Vertical-type memory device
A vertical-type memory device includes a plurality of gate electrode layers spaced apart from one another and stacked on a substrate, and extending by different lengths in a first direction and forming a staircase structure, a first interlayer insulating layer covering the staircase structure of the plurality of gate electrode layers, and a plurality of gate contact plugs penetrating the interlayer insulating layer and respectively in contact with the gate electrode layers. The plurality of gate electrode layers include lower gate electrode layers disposed adjacently to the substrate, and upper gate electrode layers disposed on the lower gate electrode layers, so that the lower gate electrodes are between the substrate and the upper gate electrode layers. The plurality of gate contact plugs include lower gate contact plugs connected to the lower gate electrode layers, and upper gate contact plugs connected to the upper gate electrode layers. The upper gate contact plugs have top-most portions disposed at a height higher than a height of top surfaces of the lower gate contact plugs. |
| US11094706B2 |
NAND unit cells
Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed. The alternating layers may be patterned into a plurality of vertical columns that are spaced from one another by openings. The openings may be lined with tunnel dielectric, charge-storage material and blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed within the lined openings. Some embodiments include methods of forming NAND unit cells. Columns of alternating n-type material and p-type material may be formed. The columns may be lined with a layer of tunnel dielectric, a layer of charge-storage material, and a layer of blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed between the lined columns. Some embodiments include semiconductor constructions, and some embodiments include NAND unit cells. |
| US11094701B2 |
Layout structure of storage cell and method thereof
A method of forming a storage cell includes: forming a transistor on a semiconductor substrate; forming a plurality of fuses in at least one conductive layer on the semiconductor substrate to couple a connecting terminal of the transistor; forming a bit line to couple the plurality of fuses; and forming a word line to couple a control terminal of the transistor. |
| US11094700B2 |
Well strap structures and methods of forming the same
An integrated circuit structure includes: a well region having a first conductivity type; a semiconductor structure extending away from the well region from a major surface of the well region, the semiconductor structure having the first conductivity type; a source/drain feature disposed on the semiconductor structure, the source/drain feature having a second conductivity type different from the first conductivity type; an isolation layer laterally surrounding at least a portion of the semiconductor structure; a dielectric layer disposed on the isolation layer, where at least a portion of the source/drain feature is disposed in the dielectric layer; and a conductive plug continuously extending through the dielectric layer and the isolation layer to physically contact the major surface of the well region, wherein the conductive plug is coupled to a power supply line to bias the well region. |
| US11094698B2 |
Semiconductor storage device
A semiconductor storage device according to the present embodiment includes a plurality of first wires provided above a surface of a semiconductor substrate to extend in a first direction, and a plurality of second wires provided above the first wires to extend in a second direction crossing the first direction. A plurality of capacitor elements are arranged every other intersection region among intersection regions between the first wires and the second wires as viewed from above the surface of the semiconductor substrate. A plurality of transistors are provided above the capacitor elements to correspond thereto, respectively. A first distance between two of the capacitor elements, which are adjacent to each other in the first direction, is narrower than a second distance between two of the capacitor elements, which are adjacent to each other in the second direction. |
| US11094697B2 |
Vertical two-transistor single capacitor memory cells and memory arrays
Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. |
| US11094695B2 |
Integrated circuit device and method of forming the same
An integrated circuit device includes a first device and a second device. The first device is disposed within a first circuit region, the first device including a plurality of first semiconductor strips extending longitudinally in a first direction. Adjacent ones of the plurality of first semiconductor strips are spaced apart from each other in a second direction, which is generally perpendicular to the first direction. The second device is disposed within a second circuit region, the second circuit region being adjacent to the first circuit region in the first direction. The second device includes a second semiconductor strip extending longitudinally in the first direction. A projection of a longitudinal axis of the second semiconductor strip along the first direction lies in a space separating the adjacent ones of the plurality of first semiconductor strips. |
| US11094694B2 |
Buried channel semiconductor device and method for manufacturing the same
A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins. |
| US11094693B2 |
Layout method
A semiconductor device includes circuit active fin lines and circuit gate lines intersecting each other in a circuit active region, dummy active fin lines and dummy gate lines intersecting each other in a dummy active region, the active fin lines and the dummy active fin lines having same width and pitch, and the circuit gate lines and the dummy gate lines having same width and pitch, wherein at least some of the dummy active fin lines are aligned with and collinear with respective circuit active fin lines, and at least some of the dummy gate lines are aligned with and collinear with respective circuit gate lines. |
| US11094690B2 |
On-chip IEC ESD protection using parasitic PNP devices
A semiconductor device having a P type substrate, an N type layer on the P type substrate that forms a PN junction therewith and the P type region, N type region and P type substrate form at least one parasitic PNP transistor. |
| US11094688B2 |
Isolation architecture
The subject technology provides for an architecture that isolates two interfaces of a circuit with an isolating communication element while also protecting against overstress transients such as electro-static discharge (ESD) and other electrical overstress (EOS) transients across the isolating communication element that can be significantly larger than the ESD rating of the isolating communication element, and/or that may be repeated in succession. The subject technology provides isolation using a two die implementation with an isolation interface including an isolation tub in each die, or a single die containing both isolation tubs in the die. The two dice include respective substrates that are connected together and float with respect to any signal or ground. The isolation enables a large offset voltage on the order of hundreds of volts to exist between the sides. Being relatively large, each isolation tub can handle a significant amount of energy. |
| US11094687B2 |
Temperature characteristic adjustment circuit
This invention aims at providing a temperature characteristic adjustment circuit capable of adjusting the temperature characteristic to various positive and negative temperature characteristics with an excessively small characteristic variation and capable of suppressing an increase in the chip area and the current consumption with a simple circuit configuration. A temperature characteristic adjustment circuit has a current source having a nonvolatile storage element having a control gate region and a source region and driven by the application of a bias between the control gate region and the source region and an output circuit not having a nonvolatile storage element, in which the temperature dependency of an output signal originating from the temperature dependency of the current amount of a current output from the current source is adjusted by the nonvolatile storage element. |
| US11094684B2 |
Edge cut debond using a temporary filler material with no adhesive properties and edge cut debond using an engineered carrier to enable topography
A semiconductor device assembly that includes a first side of a semiconductor device supported on a substrate to permit the processing of a second side of the semiconductor device. A filler material deposited on the semiconductor device supports the semiconductor device on the substrate. The filler material does not adhere to the semiconductor device or the substrate. Alternatively, the filler material may be deposited on the substrate. Instead of a filler material, the substrate may include a topography configured to support the semiconductor device. Adhesive applied between an outer edge of the first side of the semiconductor and the substrate bonds the outer edge of the semiconductor device to the substrate to form a semiconductor device assembly. A second side of the semiconductor device may then be processed and the outer edge of the semiconductor device may be cut off to release the semiconductor device from the assembly. |
| US11094683B2 |
Bonded nanofluidic device chip stacks
A method of producing a bonded chip stack is described. A first nanofluidic device chip having a first through-wafer via is formed. A second nanofluidic device chip having a second through-wafer via is formed. The first nanofluidic device chip and the second nanofluidic device chip are washed with a detergent solution. A first surface of the first nanofluidic device chip and a second surface of the second nanofluidic device chip are activated by treating the first surface and the second surface with an activation solution. The first nanofluidic device chip and the second nanofluidic device chip are arranged in a stack. The first through-wafer via is aligned with the second through-wafer via in a substantially straight line. The stack of first and second nanofluidic device chips is subjected to annealing conditions. |
| US11094680B2 |
Packages and methods of forming packages
Various packages and methods of forming packages are discussed. According to an embodiment, a package includes a processor die at least laterally encapsulated by an encapsulant, a memory die at least laterally encapsulated by the encapsulant, and a redistribution structure on the encapsulant. The processor die is communicatively coupled to the memory die through the redistribution structure. According to further embodiments, the memory die can include memory that is a cache of the processor die, and the memory die can comprise dynamic random access memory (DRAM). |
| US11094679B2 |
White light source system
According to one embodiment, there is provided a white light source system. P(λ), B(λ) and V(λ) satisfy an equation (1) below in a wavelength range of 380 nm to 780 nm. The white light source system satisfies an expression (2) below in a wavelength range of 400 nm to 495 nm: ∫380780P(λ)V(λ)dλ=∫380780B(λ)V(λ)dλ (1) where P(λ) is a light emission spectrum of white light, B(λ) is a light emission spectrum of blackbody radiation of a color temperature correspond to a color temperature of the white light, and V(λ) is a spectrum of a spectral luminous efficiency. |
| US11094678B2 |
Light emitting device having insulation pattern
A light emitting device includes: a substrate; a first electrode and a second electrode on the substrate and spaced apart from each other; a light emitting diode between the first electrode and the second electrode and connected to the first and second electrodes; a first contact on the first electrode; and a second contact on the second electrode. The first contact contacts the first electrode and a first portion of the light emitting diode, and the second contact contacts the second electrode and a second portion of the light emitting diode. |
| US11094675B2 |
Micro light emitting diode device including different-type epitaxial structures having respective connection portions of different thicknesses
A method for manufacturing a micro light emitting diode device is provided. A plurality of first type epitaxial structures are formed on a first substrate and the first type epitaxial structures are separated from each other. A first connection layer and a first adhesive layer are configured between the first type epitaxial structures and the first substrate. The first connection layer is connected to the first type epitaxial structures. The first adhesive layer is located between the first connection layer and the first type epitaxial substrate. The Young's modulus of the first connection layer is larger than the Young's modulus of the first adhesive layer. The first connection layer located between any two adjacent first type epitaxial structures is removed so as to form a plurality of first connection portions separated from each other. Each of the first connection portions is connected to the corresponding first type epitaxial structure. |
| US11094672B2 |
Composite IC chips including a chiplet embedded within metallization layers of a host IC chip
Composite IC chip including a chiplet embedded within metallization levels of a host IC chip. The chiplet may include a device layer and one or more metallization layers interconnecting passive and/or active devices into chiplet circuitry. The host IC may include a device layer and one or more metallization layers interconnecting passive and/or active devices into host chip circuitry. Features of one of the chiplet metallization layers may be directly bonded to features of one of the host IC metallization layers, interconnecting the two circuitries into a composite circuitry. A dielectric material may be applied over the chiplet. The dielectric and chiplet may be thinned with a planarization process, and additional metallization layers fabricated over the chiplet and host chip, for example to form first level interconnect interfaces. The composite IC chip structure may be assembled into a package substantially as a monolithic IC chip. |
| US11094671B2 |
Package with thinned substrate
A package includes a substrate, an Under-Bump Metallurgy (UBM) penetrating through the substrate, a solder region over and contacting the UBM, and an interconnect structure underlying the substrate. The interconnect structure is electrically coupled to the solder region through the UBM. A device die is underlying and bonded to the interconnect structure. The device die is electrically coupled to the solder region through the UBM and the interconnect structure. An encapsulating material encapsulates the device die therein. |
| US11094670B2 |
Semiconductor device assemblies including multiple shingled stacks of semiconductor dies
A semiconductor device assembly includes a substrate having a plurality of external connections, a first shingled stack of semiconductor dies disposed directly over a first location on the substrate and electrically coupled to a first subset of the plurality of external connections, and a second shingled stack of semiconductor dies disposed directly over a second location on the substrate and electrically coupled to a second subset of the plurality of external connections. The semiconductor device assembly further includes an encapsulant at least partially encapsulating the substrate, the first shingled stack and the second shingled stack. |
| US11094661B2 |
Bonded structure and method of manufacturing the same
A highly reliable bonded structure having excellent thermal fatigue resistance characteristics and thermal stress relaxation characteristics is provided. The bonded structure of the present invention comprises a first member, a second member capable of being bonded to the first member, and a bonding part interposed between a first bond surface at the first member side and a second bond surface at the second member side to bond the first member and the second member. The bonding part has at least a bonding layer, a reinforcing layer, and an intermediate layer. The bonding layer is composed of an intermetallic compound and bonded to the first bond surface. |
| US11094658B2 |
Substrate, electronic substrate, and method for producing electronic substrate
A substrate is capable of effectively reinforcing a connecting portion between an electronic component and the substrate. The substrate is a substrate on which a first electronic component having a plurality of bumps is to be mounted, and includes a base portion including an insulator and having, on the upper face thereof, at least one groove portion configured to store a tip portion of at least one of the bumps, and includes an electrode formed on at least the bottom face of the groove portion. |
| US11094655B2 |
Semiconductor structure and method for forming the same
A method for forming a semiconductor structure is provided. The method includes forming a seed layer over a substrate and forming a first mask layer over the seed layer. The method also includes forming a first trench and a second trench in the first mask layer and forming a first conductive material in the first trench and the second trench. The method further includes forming a second mask layer in the first trench and over the first conductive material, and forming a second conductive material in the second trench and on the first conductive material. A first conductive connector is formed in the first trench with a first height, a second conductive connector is formed in the second trench with a second height, and the second height is greater than the first height. |
| US11094648B2 |
Power module
A power module includes a base plate, a ceramic insulating substrate bonded on the base plate, and a semiconductor element bonded on the ceramic insulating substrate, wherein a surface of the base plate on a side opposite to the ceramic insulating substrate has a warp with a convex shape, and a linear thermal expansion coefficient α1 (×10−6/K) of the base plate and a linear thermal expansion coefficient α2 (×10−6/K) of the ceramic insulating substrate when a temperature decreases in the range of 25° C. to 150° C. satisfy the following Expression (1). α 1 - α 2 ( α 1 + α 2 ) / 2 × 100 ≤ 10 ( 1 ) |
| US11094644B2 |
Integrated circuit with scribe lane patterns for defect reduction
In examples, a method of manufacturing an integrated circuit comprises locating a photomask between a light source and a semiconductor wafer having a photoresist layer in a wafer scribe lane of the wafer, wherein the photomask comprises: a first mask scribe lane pattern; a second mask scribe lane pattern matching the first mask scribe lane pattern; and at least one circuit pattern of the integrated circuit located between the first and second mask scribe lane patterns. The method further includes illuminating the photomask to produce in the photoresist layer of the wafer scribe lane a first exposed portion corresponding to the second mask scribe lane pattern; locating the first mask scribe lane pattern between the light source and the first exposed portion; and illuminating the photomask, wherein the first mask scribe lane pattern substantially shields non-exposed portions of the photoresist layer of the wafer scribe lane from light exposure. |
| US11094639B2 |
Semiconductor package
The present disclosure provides a manufacturing method of a semiconductor packaging, including forming a redistribution layer (RDL) on a carrier, defining an active portion and a dummy portion of the RDL, and placing a semiconductor die over the dummy portion of the RDL. The present disclosure also provides a manufacturing method of a package-on-package (PoP) semiconductor structure, including forming a first redistribution layer (RDL) on a polymer-based layer of a carrier, defining an active portion and a dummy portion of the first RDL, placing a semiconductor die over the dummy portion of the first RDL, a back side of the semiconductor die facing the first RDL, forming a second RDL over a front side of the semiconductor die, the front side having at least one contact pad, and attaching a semiconductor package at the back side of the semiconductor die. |
| US11094636B2 |
Semiconductor package and method of manufacturing the semiconductor package
A semiconductor package includes a mold substrate, at least one semiconductor chip disposed in the mold substrate and including chip pads, and a redistribution wiring layer covering a first surface of the mold substrate and including a first redistribution wiring and a second redistribution wiring stacked in at least two levels to be electrically connected to the chip pads. The first redistribution wiring includes a signal line extending in a first region, and the second redistribution wiring includes a ground line in a second region overlapping with the first region. The ground line has a plurality of through holes of polygonal column shapes. |
| US11094633B2 |
Bridge die design for high bandwidth memory interface
A microelectronic package bridge can comprising a plurality of ground layers, and a plurality of signal layers interwoven with the plurality of ground layers. Each of the signal layers can include a plurality of electrically conductive pathways. Each of the electrically conductive pathways can be arranged to form an electrical connection between one of a first plurality of bumps of a first die and one of a second plurality of bumps of a second die. Each of the plurality of electrically conductive pathways can have a length substantially equal to one another. |
| US11094632B2 |
Semiconductor device with air gap and method for preparing the same
The present disclosure provides a semiconductor device and a method for preparing the semiconductor device. The semiconductor device includes a plurality of spacer bit lines disposed over a substrate; a plurality of dielectric pillars disposed over the substrate, between the plurality of spacer bit lines; and a sealing dielectric layer disposed over the plurality of spacer bit lines and the plurality of dielectric pillars such that air gaps are formed between the sealing dielectric layer and the substrate. |
| US11094630B2 |
Formation of semiconductor devices including electrically programmable fuses
A method for fabricating a semiconductor device including an electrically programmable fuse includes forming conductive material within one or more openings formed through a dielectric material disposed on a first electrode, and forming one or more second electrodes by planarizing the conductive material. Forming the conductive material includes forming one or more voids encapsulated by the conductive material such that the one or more voids have boundaries defined in part by portions of the conductive material corresponding to fuse links disposed between the one or more voids and the dielectric material. |
| US11094626B2 |
Methods of forming interconnect structures in semiconductor fabrication
A method of fabricating a semiconductor interconnect structure includes forming a via in a dielectric layer, depositing a ruthenium-containing conductive layer over a top surface of the via and a top surface of the dielectric layer, and patterning the ruthenium-containing conductive layer to form a conductive line over the top surface of the via, where a thickness of the conductive line is less than a thickness of the via. |
| US11094622B2 |
Packaged semiconductor devices and methods of packaging thereof
Packaging methods for semiconductor devices and methods of packaging thereof are disclosed. In some embodiments, a device includes a packaging apparatus and contact pads disposed on the packaging apparatus. The contact pads are arranged in an array of rows and columns. The contact pads include first contact pads proximate a perimeter region of the packaging apparatus and second contact pads disposed in an interior region of the packaging apparatus. A dam structure that is continuous is disposed around the second contact pads. The contact pads comprise a mounting region for a semiconductor device. |
| US11094621B2 |
Display panel
A display panel includes a substrate having an active zone, a pad zone, an external component zone, and a fan-out zone, a plurality of light-emitting elements disposed in the active zone, and a plurality of wire structures. The wire structures include a first wire structure and a second wire structure. The first wire structure includes a plurality of first inner connecting ends, a plurality of first outer connecting ends, and a first body. The second wire structure includes a plurality of second inner connecting ends, a plurality of second outer connecting ends, and a second body. The first wire structure has a first current A1, the second wire structure has a second current A2, and A1>A2. A number of the first inner connecting ends of the first wire structure is N1, a number of the second inner connecting ends of the second wire structure is N2, and N1>N2. |
| US11094620B2 |
Integrated capacitor with extended head bump bond pillar
A microelectronic device has a die with a first electrically conductive pillar, and a second electrically conductive pillar, mechanically coupled to the die. The microelectronic device includes a first electrically conductive extended head electrically coupled to the first pillar, and a second electrically conductive extended head electrically coupled to the second pillar. The first pillar and the second pillar have equal compositions of electrically conductive material, as a result of being formed concurrently. Similarly, the first extended head and the second extended head have equal compositions of electrically conductive material, as a result of being formed concurrently. The first extended head provides a bump pad, and the second extended head provides at least a portion of a first plate of an integrated capacitor. A second plate may be located in the die, between the first plate and the die, or on an opposite of the first plate from the die. |
| US11094613B2 |
Semiconductor structure and manufacturing method thereof
A semiconductor structure and the manufacturing method thereof are provided. A semiconductor structure includes a semiconductor substrate, a plurality of interconnecting layers, a first connector, and a second connector. The semiconductor substrate includes a plurality of semiconductor devices therein. The interconnecting layers are disposed over the semiconductor substrate and electrically coupled to the semiconductor devices. The first connector is disposed over the plurality of interconnecting layers and extends to be in contact with a first level of the plurality of interconnecting layers. The second connector is disposed over the plurality of interconnecting layers and substantially leveled with the first connector. The second connector extends further than the first connector to be in contact with a second level of the plurality of interconnecting layers between the first level of the plurality of interconnecting layers and the semiconductor substrate, and the first connector is wider than the second connector. |
| US11094612B2 |
Semiconductor devices including through-silicon-vias and methods of manufacturing the same and semiconductor packages including the semiconductor devices
A semiconductor device can include a substrate that has a surface. A via structure can extend through the substrate toward the surface of the substrate, where the via structure includes an upper surface. A pad structure can be on the surface of the substrate, where the pad structure can include a lower surface having at least one protrusion that is configured to protrude toward the upper surface of the via structure. |
| US11094611B2 |
Liquid cooled heat dissipation device
A heat dissipating device which is liquid cooled includes a base and at least one heat dissipation fin connected to the base. The base includes a first cavity. The at least one heat dissipation fin comprising a second cavity communicating with the first cavity, the second cavity and the first cavity together form an accommodation cavity for accommodating a working fluid which forcefully applies cooling upon being heated sufficiently to be vaporized. |
| US11094608B2 |
Heat dissipation structure including stacked chips surrounded by thermal interface material rings
The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer. |
| US11094602B2 |
Semiconductor device package
A semiconductor device package includes a carrier, a first interposer disposed and a second interposer. The second interposer is stacked on the first interposer, and the first interposer is mounted to the carrier. The combination of the first interposer and the second interposer is substantially T-shaped. |
| US11094601B2 |
Semiconductor element and method for producing the same
A semiconductor element includes an element body and a test electrode. The element body has a principal surface facing in a thickness direction and a first side surface facing in a direction orthogonal to the principal surface and connected to the principal surface. The test electrode is disposed on the principal surface and is adjacent to the boundary between the principal surface and the first side surface. The element body is provided with a plurality of dents that straddle the boundary and are recessed from both the principal surface and the first side surface. The plurality of dents are arranged along the boundary. |
| US11094599B2 |
Semiconductor structure and manufacturing method thereof
A semiconductor structure including a substrate, a complementary metal oxide semiconductor (CMOS) device, a bipolar junction transistor (BJT), and a first interconnect structure is provided. The substrate has a first side and a second side opposite to each other. The CMOS device includes an NMOS transistor and a PMOS transistor disposed on the substrate. The BJT includes a collector, a base and an emitter. The collector is disposed in the substrate. The base is disposed on the first side of the substrate. The emitter is disposed on the base. A top surface of a channel of the NMOS transistor, a top surface of a channel of the PMOS transistor and a top surface of the collector of the BJT have the same height. The first interconnect structure is electrically connected to the base at the first side of the substrate and extends to the second side of the substrate. |
| US11094598B2 |
Multiple threshold voltage devices
The present disclosure relates to semiconductor structures and, more particularly, to multiple threshold voltage devices and methods of manufacture. The structure includes: a gate dielectric material; a gate material on the gate dielectric material, the gate material comprising different thickness in different regions each of which are structured for devices having a different Vt; and a workfunction material on the gate material. |
| US11094597B2 |
Structure and formation method of semiconductor device with fin structures
A structure and a formation method of a semiconductor device are provided. The method includes forming a first semiconductor fin and a second semiconductor fin over a semiconductor substrate. The second semiconductor fin is wider than the first semiconductor fin. The method also includes forming a gate stack over the semiconductor substrate, and the gate stack extends across the first semiconductor fin and the second semiconductor fin. The method further includes forming a first source/drain structure on the first semiconductor fin, and the first source/drain structure is p-type doped. In addition, the method includes forming a second source/drain structure on the second semiconductor fin, and the second source/drain structure is n-type doped. |
| US11094584B2 |
Method of forming semiconductor device including polysilicon structures
A method of making a semiconductor device includes depositing a first polysilicon layer over a substrate. The method further includes forming a barrier layer over the first polysilicon layer. The method further includes patterning the first polysilicon layer. The method further includes depositing a second polysilicon layer over the barrier layer, wherein the depositing of the second polysilicon layer includes increasing a grain size of the first polysilicon layer, and causing at least one grain boundary in the first polysilicon layer to contact the barrier layer. |
| US11094581B2 |
IC structure with air gaps and protective layer and method for manufacturing the same
Provided is an integrated circuit structure and a method for manufacturing the same. The integrated circuit structure comprises a substrate; a plurality of interconnecting structures on the substrate, each of the interconnecting structures comprises side surfaces and a top surface, the side surfaces directly define air gaps therebetween isolating the interconnecting structures from each other; and a planar protective layer on top of the plurality of interconnecting structures covering all of the air gaps. The protective layer comprises a sheltering film and a supporting film. |
| US11094579B2 |
Method of forming shallow trench isolation structure
A method of forming a semiconductor structure includes depositing a mask layer over a substrate. The method includes etching the substrate to define a first opening. The method includes depositing a sacrificial material in the first opening. The method includes depositing a dielectric liner along sidewalls of the first opening, wherein a bottom surface of the dielectric liner contacts the sacrificial material. The method includes removing the sacrificial material. The method includes etching the substrate to enlarge the first opening to define a second opening. The second opening includes a first portion extending a first depth from the dielectric material in a first direction perpendicular to a top surface of the substrate, and a second portion extending in a second direction, parallel to the top surface of the substrate. The method includes removing the dielectric liner. The method includes filling the second opening with a dielectric material. |
| US11094578B2 |
Semiconductor structure and method for manufacturing the same
A semiconductor structure and a method for manufacturing the same are disclosed. The semiconductor structure includes a semiconductor substrate, a multi-layer stack, a switch device, and an air void. The multi-layer stack is buried in the semiconductor substrate. The multi-layer stack includes a first filling layer and a second filling layer under the first filling layer, the first filling layer has a first etching rate, the second filling layer has a second etching rate, and the first etching rate and the second etching rate are different. The switch device is disposed over the semiconductor substrate. The air void is formed in the multi-layer stack and under the switch device. The air void is surrounded by dielectric filling material. |
| US11094576B1 |
Methods for producing a 3D semiconductor memory device and structure
A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer; forming first alignment marks and control circuits including first single crystal transistors; forming at least one second level above the first level; performing a first etch step including etching first holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching second holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where the etching first holes includes performing a lithography step aligned to the first alignment marks. |
| US11094571B2 |
Apparatus to increase transferspeed of semiconductor devices with micro-adjustment
An apparatus for executing a direct transfer of a semiconductor device die from a first substrate to a second substrate. The apparatus includes a first substrate conveyance mechanism movable in two axes. A micro-adjustment mechanism is coupled with the first substrate conveyance mechanism and is configured to hold the first substrate and to make positional adjustments on a scale smaller than positional adjustments caused by the first substrate conveyance mechanism. The micro-adjustment mechanism includes a micro-adjustment actuator having a distal end and a first substrate holder frame that is movable via contact with the distal end of the micro-adjustment actuator. A second frame is configured to secure the second substrate such that a transfer surface is disposed facing the semiconductor device die disposed on a surface of the first substrate. A transfer mechanism is configured to press the semiconductor device die into contact with the transfer surface of the substrate. |
| US11094570B2 |
Load port having movable member that abuts a pin
A load port includes a first pin projecting on a dock plate and provided on the dock plate so as to be pushed down, and a first detection unit provided on the base portion and configured to detect that the dock plate is located at a first position. The first detection unit includes a movable member capable of displacing in a moving direction of the dock plate, and a first sensor configured to detect the displacement of the movable member. The movable member is arranged at a position to abut against the first pin that is in a pushed down state in a process in which the dock plate moves from a second position to the first position. |
| US11094568B2 |
Processing apparatus, abnormality detection method, and storage medium
A processing apparatus includes a chamber configured to accommodate a substrate to be processed, a nozzle provided in the chamber and configured to supply a processing solution to the substrate, a flow rate measuring part configured to measure a flow rate of the processing solution supplied to the nozzle, a flow path opening/closing part configured to open and close a supply flow path of the processing solution to the nozzle, and a controller configured to output a close signal causing the flow path opening/closing part to perform a closing operation that closes the supply flow path. The controller is configured to detect an operation abnormality of the flow path opening/closing part based on an accumulated amount of the flow rate measured by the flow rate measuring part after outputting the close signal. |
| US11094567B2 |
Mounting apparatus and method for manufacturing semiconductor device
A mounting apparatus for manufacturing a semiconductor device by bonding a semiconductor chip (12) to a mounted object that is a substrate (30) or another semiconductor chip (12) is provided. The mounting apparatus includes: a stage (120) on which the substrate (30) is placed, a mounting head (124) that is capable of moving relative to the stage (120) and bonds the semiconductor chip (12) to the mounted object, and an irradiation unit (108 that irradiates, from a lower side of the stage (120), an electromagnetic wave transmitting through the stage and heating the substrate (30). The stage (120) has a first layer (122) formed on an upper surface side, and the first layer (122) has a greater thermal resistance in a plane direction than the thermal resistance in a thickness direction. |
| US11094566B2 |
Substrate heating apparatus including heater under substrate support and substrate processing apparatus using the same
A substrate heating apparatus includes: a substrate support configured to substantially horizontally support a substrate; a heater provided below the substrate support substantially parallel to the substrate, and having a predetermined planar shape; and a side portion extending downward from an outer peripheral portion of the heater. |
| US11094564B2 |
Processing liquid supplying apparatus, substrate processing apparatus and processing liquid supplying method
A processing liquid supplying apparatus supplies a processing liquid to a processing unit which processes a substrate. The processing liquid supplying apparatus includes a supply pipe to which a processing liquid inside a processing liquid tank that stores the processing liquid is fed and which supplies the processing liquid, which is fed from the processing liquid tank, to the processing unit, a return pipe which is branched and connected to the supply pipe to return a processing liquid inside the supply pipe to the processing liquid tank, a first heating unit which heats a processing liquid inside an upstream-side portion to be heated that is set in the supply pipe upstream from a branched position to which the return pipe is connected, a second heating unit which heats a processing liquid inside a downstream-side portion to be heated that is set in the supply pipe downstream from the branched position, a cooling unit which cools a processing liquid inside a portion to be cooled that is set in the return pipe, and a first filter which is interposed in the supply pipe upstream from the upstream-side portion to be heated and removes particles in a processing liquid. |
| US11094560B1 |
Encapsulated semiconductor package
A method of manufacturing a semiconductor package includes mounting and electrically connecting a semiconductor die to a substrate. The semiconductor die and the substrate are encapsulated to form an encapsulation. Via holes are laser-ablated through the encapsulation and conductive material is deposited within the via holes to form vias. A first buildup dielectric layer is formed on the encapsulation. Laser-ablated artifacts are laser-ablated in the first buildup layer. The laser-ablated artifacts in the first buildup layer are filled with a first metal layer to form a first electrically conductive pattern in the first build up layer. The operations of forming a buildup layer, forming laser-ablated artifacts in the buildup layer, and filling the laser-ablated artifacts with an electrically conductive material to form an electrically conductive pattern can be performed any one of a number of times to achieve the desired redistribution. |
| US11094559B2 |
Method of fastening a semiconductor chip on a lead frame, and electronic component
A method of attaching a semiconductor chip on a lead frame includes A) providing a semiconductor chip, B) applying a solder metal layer sequence to the semiconductor chip, wherein the solder metal layer sequence includes a first metallic layer including indium or an indium-tin alloy, C) providing a lead frame, D) applying a metallization layer sequence to the lead frame, wherein the metallization layer sequence includes a fourth layer including indium and/or tin arranged above the lead frame and a third layer including gold arranged above the fourth layer, E) forming an intermetallic intermediate layer including gold and indium, gold and tin or gold, tin and indium, G) applying the semiconductor chip to the lead frame via the solder metal layer sequence and the intermetallic intermediate layer, and H) heating the arrangement produced in G) to attach the semiconductor chip to the lead frame. |
| US11094552B2 |
Method for etching recessed structures
A method for manufacturing recessed micromechanical structures in a wafer. A first etching mask and a second etching mask are patterned on the horizontal face of the wafer. The second etching mask defines at least one recess area and the first etching mask defines at least one etch-control area within the at least one recess area. The placement, number and dimensions of the etch-control areas influence the vertical etch rate of the recessed structure. Adjacent structures can be etched to different recess depths by selecting suitable etch-control areas. |
| US11094551B2 |
Plasma processing method and plasma processing apparatus
A plasma processing method performed using a plasma processing apparatus includes a first step of forming a first film on a pattern formed on a substrate and having dense and coarse areas, and a second step of performing sputtering or etching on the first film. |
| US11094547B2 |
Method for producing wiring structure
Provided is a method for producing a wiring structural body provided with a wiring pattern, the method including a first step of forming an insulating layer on a surface of a silicon substrate along at least a region for forming the wiring pattern, a second step of forming a boron layer on the insulating layer along the region, and a third step of forming a metal layer on the boron layer by plating. |
| US11094543B1 |
Defect correction on metal resists
A method for forming a semiconductor device includes depositing a metal resist layer over a layer to be patterned that is formed over a substrate; patterning the metal resist layer using a lithography process to form a patterned metal resist layer and expose portions of the layer to be patterned; selectively depositing a silicon containing layer over the patterned resist layer by exposing the substrate to a gas mixture comprising a silicon precursor, the silicon containing layer being preferentially deposited over a top surface of the metal resist layer; and performing a surface cleaning process by exposing the layer to be patterned and the patterned metal resist layer covered with the silicon containing layer to a plasma process with an etch chemistry comprising a halogen or hydrogen. |
| US11094535B2 |
Selective passivation and selective deposition
Methods for selective deposition, and structures thereof, are provided. Material is selectively deposited on a first surface of a substrate relative to a second surface of a different material composition. A passivation layer is selectively formed from vapor phase reactants on the first surface while leaving the second surface without the passivation layer. A layer of interest is selectively deposited from vapor phase reactants on the second surface relative to the passivation layer. The first surface can be metallic while the second surface is dielectric, or the second surface is dielectric while the second surface is metallic. Accordingly, material, such as a dielectric, can be selectively deposited on either metallic or dielectric surfaces relative to the other type of surface using techniques described herein. Techniques and resultant structures are also disclosed for control of positioning and shape of layer edges relative to boundaries between underlying disparate materials. |
| US11094534B2 |
Surface oxidation method for wafer
A surface oxidation method for a wafer, the method comprises: raising a temperature on the wafer in an oxidation atmosphere, the temperature is raised from a start temperature to a target temperature at a temperature raising rate greater than 5° C./min, the temperature is raised in a vertical furnace tube of an annealing furnace, the vertical furnace tube includes a gas intake conduit arranged on a side wall, the gas intake conduit includes a gas inlet arranged to be proximate to a bottom of the vertical furnace tube and a gas outlet arranged to be proximate to a top of the furnace tube, the wafer overlying the vertical furnace tube; and isothermally oxidizing the wafer at the target temperature in the oxidation atmosphere. |
| US11094533B2 |
Doped and undoped vanadium oxides for low-k spacer applications
A microelectronic device on a semiconductor substrate comprises: a gate electrode; and a spacer adjacent to the gate electrode, the spacer comprising: a the low-k dielectric film comprising one or more species of vanadium oxide, which is optionally doped, and an optional silicon nitride or oxide film. Methods comprise depositing a low-k dielectric film optionally sandwiched by a silicon nitride or oxide film to form a spacer adjacent to a gate electrode of a microelectronic device on a semiconductor substrate, wherein the low-k dielectric film comprises a vanadium-containing film. |
| US11094531B2 |
Semiconductor structure and method for forming the same
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a gate, and a phosphorus containing dielectric layer. The gate is on the substrate. The phosphorus containing dielectric layer is on the gate. The phosphorus containing dielectric layer has a varied phosphorus dopant density distribution profile. |
| US11094528B2 |
Surface treatment of substrates using passivation layers
Processes and apparatuses for the treatment of semiconductor workpieces are provided. In some embodiments, a method can include placing the workpiece in a processing chamber. The processing chamber can be separated from a plasma chamber by a separation grid assembly. The method can include forming a passivation layer on the workpiece in the processing chamber using radicals generated in a first plasma in the plasma chamber. The method can include performing a surface treatment process on the workpiece in the processing chamber using a second plasma generated in the plasma chamber. |
| US11094525B2 |
Method for cleaning semiconductor wafer
A method for cleaning a semiconductor wafer, including: supplying a semiconductor wafer whose surface has an oxide film formed thereon with a cleaning solution capable of removing the oxide film; and cleaning, while rotating, the semiconductor wafer to remove the oxide film formed on the surface of the semiconductor wafer. The oxide film is removed such that a rotational speed of the semiconductor wafer is 300 rpm or more after the cleaning with the cleaning solution is started and before a water-repelling surface is attained, and then the rotational speed of the semiconductor wafer is changed to 100 rpm or less to completely remove the oxide film. A method for cleaning a semiconductor wafer by which both surface roughness improvement and surface defect suppression can be achieved. |
| US11094524B2 |
Substrate processing method and substrate processing apparatus
A substrate processing method includes a substrate holding step of horizontally holding a substrate, a liquid film forming step of supplying a processing liquid onto the upper surface of the substrate to form a liquid film of the processing liquid covering the upper surface of the substrate, a liquid film-removed region-forming step of partially eliminating the processing liquid from the liquid film of the processing liquid to form a liquid film-removed region in the liquid film of the processing liquid, a liquid film-removed region enlarging step of enlarging the liquid film-removed region toward the outer periphery of the substrate, and a hydrogen fluoride atmosphere-holding step of keeping the ambient atmosphere at the boundary between the liquid film-removed region and the liquid film of the processing liquid as an atmosphere of hydrogen fluoride-containing vapor, in parallel with the liquid film-removed region enlarging step. |
| US11094522B2 |
Multiturn time-of-flight mass spectrometer and method for producing the same
To compensate for the distortion of the loop-flight electric field with a higher level of accuracy, a multiturn time-of-flight mass spectrometer 1 includes: a main electrode 21 configured to generate, within a predetermined loop-flight space, a loop-flight electric field which is an electric field that makes an ion fly in a loop orbit multiple times, the main electrode having an opening 24 or 25 through which ions are introduced into or extracted from the loop-flight space; a compensating-electrode attachment part 23 made of an insulating material and fixed to the main electrode; and a compensating electrode 22 configured to compensate for a distortion of the loop-flight electric field which occurs in the vicinity of the opening, the compensating electrode being fixed to the compensating-electrode attachment part directly or via a substrate 221 and located in the vicinity of the opening. |
| US11094519B2 |
Collision surface for improved ionisation
An apparatus for performing ambient ionisation mass and/or ion mobility spectrometry is disclosed. The apparatus comprises a substantially cylindrical, tubular, rod-shaped, coil-shaped, helical or spiral-shaped collision assembly; and a first device arranged and adapted to direct analyte, smoke, fumes, liquid, gas, surgical smoke, aerosol or vapour onto said collision assembly. |
| US11094515B2 |
Sputtering apparatus and sputtering method
A sputtering apparatus has a vacuum chamber capable of arranging a target material and a substrate therein so as to face each other, a DC power supply capable of electrically being connected to the target material, and a pulsing unit pulsing electric current flowing in the target material from the DC power supply, in which plasma is generated in the vacuum chamber to form a thin film on the substrate, including an ammeter measuring electric current flowing in the pulsing unit from the DC power supply, a power supply controller performing feedback control of the DC power supply so that a current value measured by the ammeter becomes a prescribed value and a pulse controller indicating a pulse cycle shifted from a control cycle of the DC power supply by the power supply controller to the pulsing unit. |
| US11094514B2 |
Rotatable sputtering target
A rotatable sputtering target has a target material, a back tube and a joint piece. The joint piece is disposed between the target material and the back tube. The joint piece has a compressible structure and an electrically and thermally conductive adhesive. Particularly, the compressible structure being a compressible blanket or a compressible sheet has multiple through holes and thus the electrically and thermally conductive adhesive is filled in the through holes and then directly formed between the target material and the back tube. Using the joint piece to joint the target material and the back tube not only maintains the joint strength but also elevates the tolerable power of the rotatable sputtering target, which can increase the sputtering efficiency. |
| US11094513B2 |
Sputtering apparatus including cathode with rotatable targets, and related methods
Certain example embodiments relate to sputtering apparatuses that include a plurality of targets such that a first one or ones of target(s) may be used for sputtering in a first mode, while a second one or ones of target(s) may be used for sputtering in a second mode. Modes may be switched in certain example embodiments by rotating the position of the targets, e.g., such that one or more target(s) to be used protrude into the main chamber of the apparatus, while one or more target(s) to be unused are recessed into a body portion of a cathode of (e.g., integrally formed with) the sputtering apparatus. The targets may be cylindrical magnetic targets or planar targets. At least one target location also may be made to accommodate an ion beam source. |
| US11094507B2 |
Power generation systems and methods for plasma stability and control
Embodiments are described herein for power generation systems and methods that use quadrature splitters and combiners to facilitate plasma stability and control. For one embodiment, a quadrature splitter receives an input signal and generates a first and second signals as outputs with the second signal being ninety degrees out of phase with respect to the first signal. Two amplifiers then generate a first and second amplified signals. A quadrature combiner receives the first and second amplified signals and generates a combined amplified signal that represents re-aligned versions of the first and second amplified signals. The power amplifiers can be combined into a system to generate a high power output to a processing chamber. Further, detectors can generate measurements used to monitor and control power generation. The power amplifiers, system, and methods provide significant advantages for high-power generation delivered to process chambers for plasma generation during plasma processing. |
| US11094505B2 |
Substrate processing apparatus, storage medium and substrate processing method
Examples of a substrate processing apparatus include a signal transmitter that outputs a command signal, and an RF generator that receives the command signal, starts to output traveling wave power simultaneously with a first transition of the command signal, measures a delay time, which is a time period after the first transition of the command signal until a predetermined power-applied state is achieved on a receiving side of the traveling wave power, and stops outputting the traveling wave power when the delay time elapses after a second transition of the command signal. |
| US11094499B1 |
Apparatus of charged-particle beam such as electron microscope comprising sliding specimen table within objective lens
The present invention provides an apparatus of charged-particle beam such as an electron microscope including a specimen table that can slide on a planar surface around the lower pole piece of the objective lens. The specimen table is confined in a specimen stage having one elastic protrusion and one or more elastic force receiving parts (e.g three permanent protrusions) that contact and press the table. When the specimen is under microscopic examination, disturbing vibration cannot generate a force sufficient to overcome the limiting friction between the specimen table and the planar surface of the objective lens. The invention exhibits numerous technical merits such as minimal or zero vibration noise, and improved image quality, among others. |
| US11094498B2 |
Monochromator and charged particle beam system
There is provided a monochromator capable of reducing angular dispersion in electron rays. In the monochromator, a first Wien filter and a second Wien filter are arranged symmetrically with respect to a first plane of symmetry. A third Wien filter and a fourth Wien filter are arranged symmetrically with respect to a second plane of symmetry. A pair of the first and second Wien filters and a pair of the third and fourth Wien filters are arranged symmetrically with respect to a third plane of symmetry. The first through fourth Wien filters produce their respective electromagnetic fields which are identical in sense and strength. |
| US11094497B2 |
X-ray source target
In one embodiment, an X-ray source includes a source target configured to generate X-rays when impacted by an electron beam. The source target includes one or more thermally conductive layers; and one or more X-ray generating layers interleaved with the thermally conductive layers, wherein at least one X-ray generating layer comprises regions of X-ray generating material separated by thermally conductive material within the respective X-ray generating layer. |
| US11094496B2 |
Device for controlling electron flow and method for manufacturing said device
A device for controlling electron flow is provided. The device comprises a cathode, an elongate electrical conductor embedded in a diamond substrate, an anode, and a control electrode provided on the substrate surface for modifying the electric field in the region of the end of the conductor. A method of manufacturing the device is also provided. |
| US11094495B1 |
Alkali semi-metal films and method and apparatus for fabricating them
Methods and systems for fabricating a film, such as, for example, a photocathode, having a tailored band structure and thin-film components that can be tailored for specific applications, such as, for example photocathode having a high quantum efficiency, and simple components fabricated by those methods. |
| US11094490B2 |
Method and apparatus for automatic engagement of arc reduction technology
An automatic actuator assembly including a passive actuator assembly and a detection assembly is operatively coupled to an arc reduction assembly. The passive actuator assembly is coupled to the arc reduction assembly and structured to move the arc reduction assembly between a disengaged, first configuration and an engaged, second configuration. |
| US11094486B2 |
Magnetic trigger arrangement
A trigger arrangement for a scanning system can include a sealed housing configured to support a scanning device, a trigger, and an actuation device configured to control functionality of the scanning device. A first magnet can be positioned outside of the sealed housing and can be configured to be selectively moved by the trigger. A second magnet configured to be repelled by the first magnet can be positioned inside of the sealed housing. A connecting member that supports the second magnet can be configured to transfer force from the second magnet to the actuation device. Some configurations can provide tactile feedback to a user when the trigger is used. |
| US11094485B2 |
Medium voltage contactor
A contactor for medium voltage electric systems including: one or more electric poles; for each electric pole, a fixed contact and a corresponding movable contact reversibly movable between a first position, at which the movable contact is decoupled from the fixed contact, and a second position, at which the movable contact is coupled with the fixed contact; an electromagnetic actuator including a magnetic yoke having a fixed yoke member and a movable yoke member, the movable yoke member reversibly movable between a third position corresponding to the first position of the movable contacts, at which the movable yoke member is decoupled from the fixed yoke member, and a fourth position, corresponding to the second position of the movable contacts, at which the movable yoke member is coupled with the fixed yoke member, the electromagnetic actuator including an excitation circuit assembly including an excitation coil wound around the magnetic yoke and electrically connected with an auxiliary electric power supply to be fed with an excitation current to generate an excitation magnetic flux to move the movable yoke member from the third position to the fourth position or to maintain the movable yoke member in the fourth position; an opening springs operatively coupled with the movable yoke member to move the movable yoke member from the fourth position to the third position; a kinematic chain to operatively connect said movable yoke member with said movable contacts. The electromagnetic actuator including camping circuit assembly comprising a damping coil arranged to form a conductive loop adapted to be at least partially enchained with the excitation magnetic flux generated by the excitation current flowing along the excitation coil, when the auxiliary electric power supply provides the excitation current to the excitation coil, so that a secondary current circulates along the damping coil when the excitation magnetic flux is subject to a transient. |
| US11094484B2 |
Insulating medium for an electric energy transmission device
An insulating medium for an electric energy transmission device is a fluid at room temperature and atmospheric pressure and has at least the following components ≥50% by volume to ≤98% by volume of synthetic air, and ≥2% by volume to ≤50% by volume of an organic fluorine compound. An electric arc extinguishing medium and a fluid-insulated electric energy transmission device are also provided. |
| US11094481B2 |
Keyswitch capable of identifying keycap change
A keyswitch capable of identifying keycap change includes a substrate, a keycap, a resilient component, an optical detection module and a processor. The keycap is disposed above the substrate and includes a reflective element. The optical detection module is disposed on the substrate and adapted to receive an optical signal reflected from the reflective element. The processor is disposed on the substrate and electrically connected to the optical detection module. The processor is adapted to analyze the optical signal for acquiring a type and a movement of the keycap. The keyswitch further includes a supporting component and a membrane. An end of the supporting component is connected to the keycap, and the other end of the supporting component is connected to the substrate. The membrane has light penetrating property and is disposed above the optical detection module. |
| US11094480B2 |
Keyboard device
A keyboard device includes a substrate, a membrane circuit board, a flexible printed circuit board, a first fixing board, and a second fixing board. The substrate includes a top surface, a bottom surface, and a side edge. The substrate further includes an offset protrusion protruding from the top surface and forms a recessed area on the bottom surface. The membrane circuit board is disposed on the top surface. The membrane circuit board includes an outlet area correspondingly disposed on the offset protrusion. The flexible printed circuit board is disposed on the bottom surface. The flexible printed circuit board includes a fixed portion, a folded portion, and an electrical connection end. The fixed portion is received in the recessed area. The first fixing board is correspondingly disposed on the offset protrusion. The second fixing board is correspondingly received in the recessed area and assembled with the first fixing board. |
| US11094478B2 |
Clad material for electric contacts and method for producing the clad material
The present invention is a clad material for an electric contact, including a base material composed of a Cu-based, precipitation-type age-hardening material, and a contact material composed of an Ag alloy bonded to the base material. On a bonded interface between the contact material and the base material, a width of a diffusion region including Ag and Cu is 2.0 μm or shorter. The clad material is produced by bonding each other the contact material and the base material having undergone solutionizing and age-hardening beforehand, suppressing the diffusion region from expanding after bonding. The present invention is capable of providing an electric contact, which achieves higher conductivity, without sacrificing property of the Cu-based, precipitation-type age-hardening material. |
| US11094477B2 |
Tensioning gear mechanism for tensioning a stored-energy spring of a spring-type stored-energy drive
A charging mechanism charges a stored-energy spring of a stored-energy spring mechanism. The charging mechanism contains a charging gear coupled to the stored-energy spring, an intermediate shaft coupled to the charging gear, an idler gear, a freewheel coupled to the idler gear, a locking mechanism for releasably locking the charging gear in a charged state of the stored-energy spring, and a dog clutch that couples the freewheel to the intermediate shaft to charge the stored-energy spring and uncouples same from the intermediate shaft in the charged state of the stored-energy spring. The dog clutch contains a first clutch block that is non-rotatably coupled to the intermediate shaft, a second clutch block connected to the freewheel, and a synchronizer ring disposed between the clutch blocks and is non-rotatably coupled to the first clutch block, the synchronizer ring is pressed against the second clutch block when the dog clutch is closed. |
| US11094473B2 |
All-day solar cell system integrating high capacity photochromic storage and discharge
The invention provides an all-day solar cell system that is capable of simultaneously generating and storing electricity, which allows efficient photocharge during the day and discharge at night. |
| US11094471B2 |
Electrolytic capacitor
An electrolytic capacitor includes a capacitor element and a liquid. The capacitor element includes an anode foil, a cathode foil disposed to face the anode foil, and a conductive polymer layer that is disposed between the anode foil and the cathode foil. A first layer including at least one selected from the group consisting of carbon, nickel, a nickel compound, titanium, and a titanium compound is disposed on the cathode foil. The conductive polymer layer includes a conductive polymer. A proportion of water in the liquid ranges from 0.1% by mass to 6.0% by mass, inclusive. |
| US11094470B2 |
Multilayer ceramic capacitor
A multilayer ceramic capacitor includes a stacked body including dielectric layers and internal electrodes. External electrodes are provided on end surfaces of the stacked body. The internal electrodes include a first internal electrode, a second internal electrode, a third internal electrode, a fourth internal electrode, a fifth internal electrode, and a sixth internal electrode. The first internal electrode and the second internal electrode, and the third internal electrode and the fourth internal electrode are provided on a dielectric layer in a same plane, and the fifth internal electrode and the sixth internal electrode are provided on a dielectric layer in a same plane different from the dielectric layer on which the first internal electrode and the second internal electrode, and the third internal electrode and the fourth internal electrode are provided. |
| US11094468B2 |
Multilayer ceramic electronic component
A multilayer ceramic electronic component includes a ceramic body including dielectric layers and first and second internal electrodes alternately laminated with respective dielectric layers disposed therebetween to be exposed to first and second external surfaces of the ceramic body, and first and second external electrodes disposed on the first and second external surfaces of the ceramic body and connected to corresponding internal electrodes, among the first and second internal electrodes, respectively. The dielectric layer includes a portion, disposed between the first and second external electrodes, having a thickness of 3.5 micrometers or more to 3.7 micrometers or less. |
| US11094467B2 |
Multilayer ceramic capacitor and board having the same
A multilayer ceramic capacitor includes a ceramic body having a plurality of dielectric layers stacked therein, and first and second internal electrodes alternately disposed with at least one among the plurality of dielectric layers interposed therebetween. The first internal electrodes include first and second lead portions exposed to a mounting surface of the ceramic body, and disposed to be spaced apart from each other in a length direction of the ceramic body. The second internal electrodes include a third lead portion exposed to the mounting surface of the ceramic body, and disposed between the first and second lead portions in the length direction of the ceramic body. |
| US11094465B2 |
Electronic component with external electrodes including conductive resin layer
An element body of a rectangular parallelepiped shape includes a principal surface arranged to constitute a mounting surface, a pair of side surfaces opposing each other and adjacent to the principal surface, and a pair of end surfaces opposing each other and adjacent to the principal surface and the pair of side surfaces. An external electrode includes a sintered metal layer disposed on an end portion of the element body, and a conductive resin layer including a portion positioned on the principal surface and a portion positioned on the sintered metal layer. An end edge of the sintered metal layer is positioned closer to the end surface than a maximum thickness position of the portion positioned on the principal surface. A thickness of the conductive resin layer gradually decreases from the maximum thickness position to the portion positioned on the sintered metal layer. |
| US11094463B2 |
Method for manufacturing spherical ceramic-glass nanocomposite dielectrics for multilayer ceramic capacitor applications
Spherical ceramic-glass nanocomposite dielectrics made from ceramics and glasses that are separately pre-milled by mechanical ball milling using selected ball-to-powder weight ratios and combined to form a mixture that is ball milled. A stable liquid suspension of the milled mixture including an added dispersant such as polyacrylic acid to improve uniformity is spray dried through a nozzle and recovered product is annealed. The novel dielectrics have a microstructure where ceramic primary particles are uniformly distributed and fully embedded in a glass matrix. The dielectrics have a mean particle size of about 1-20 um and a sphericity of about 0.8 or higher which are suitable for fabricating multilayer ceramic capacitors for high temperature applications. The novel dielectrics afford decreased sintering temperature, enhanced breakdown strength, lower dielectric lose tangent, and lower costs. Calcium titanate zirconate with manganese-doping-based or barium titanate-based dielectric ceramics and alkali-free borosilicate glass produce superior nanocomposite dielectrics. |
| US11094462B2 |
Multilayer ceramic electronic component
A multilayer ceramic electronic component includes a laminate, a first external electrode on a first end surface of the laminate, and a second external electrode on a second end surface of the laminate. The laminate includes a central layer portion in which each first internal electrode layer and each second internal electrode layer oppose each other with a dielectric ceramic layer therebetween, peripheral layer portions sandwiching the central layer portion in a lamination direction, and side margins sandwiching the central layer portion and the peripheral layer portions in a width direction. The side margins each include multiple ceramic layers laminated in the width direction, and the ceramic layers include an inner layer disposed closest to the laminate and an outer layer disposed farthest from the laminate. |
| US11094460B2 |
Capacitor component
A capacitor component includes: a body including a dielectric layer and first and second internal electrodes alternately disposed with the dielectric layer interposed therebetween; first and second external electrodes including first and second connection portions, and first and second band portions extending onto portions of a surface from the first and second connection portions, respectively; first and second plating layers disposed on the first and second band portions, respectively; humidity resistant layers disposed between the first and second external electrodes, disposed on the first and second external electrodes, and having openings respectively exposing portions of the first and second band portions. The first and second plating layers are disposed in the openings of the humidity resistant layers, respectively, and are in contact with the first and second band portions, respectively. |
| US11094459B2 |
Substrates with integrated three dimensional inductors with via columns
This disclosure relates generally to substrates having three dimensional (3D) inductors and methods of manufacturing the same. In one embodiment, the 3D inductor is a solenoid inductor where the exterior edge contour of the winding ends is substantially the same and substantially aligned with the exterior edge contour of the exterior edge contour of conductive vias that connect the windings. In this manner, there is no overhang between the windings and the conductive vias. In another embodiment of the 3D inductor, via columns connect connector plates. The via column attachment surfaces of each of the conductive vias in each of the columns is the same and substantially aligned. In this manner, carrier pads are not needed and there is no overhand between the conductive vias. |
| US11094458B2 |
Coil component and method for manufacturing the same
A coil component includes a magnetic body and an external electrode disposed on an external surface of the magnetic body. The magnetic body includes a support member including a through hole, filled with a magnetic material, and a via hole, a coil disposed on at least one surface of the support member, and a magnetic material encapsulating the coil and the support member. A first conductive layer is disposed on a side surface of the via hole formed in the support member and the at least one surface of the support member. The via hole is filled with a portion of the second conductive layer disposed on the first conductive layer. |
| US11094457B2 |
Method for manufacturing laminated iron core
A method for manufacturing a laminated iron core includes preheating a laminated body in which a plurality of iron core pieces are laminated and which includes a resin filling hole, measuring a temperature of the laminated body after preheating the laminated body, determining whether or not the temperature measured is within a predetermined range, feeding the laminated body into a molding device in a case where it is determined that the temperature is within the predetermined range, and filling the resin filling hole of the laminated body with a resin material in the molding device. |
| US11094456B2 |
Wireless power transmission device
A wireless power transmission device is disclosed. The wireless power transmission device comprises a first coil and a second coil electromagnetically coupled to the first coil without contacting the first coil. A portion of one of the first coil and the second coil extends through a space defined by the other of the first coil and the second coil. |
| US11094455B2 |
Module with reversely coupled inductors and magnetic molded compound (MMC)
A device includes a first inductor and a second inductor reversely coupled with the first inductor, wherein the first and second inductors have overlapping windings. The device also includes a housing for the first and second inductor, wherein the housing is filled with a magnetic molding compound. |
| US11094453B2 |
Electronic device and method for manufacturing electronic device
A substrate includes primary side terminal holes into which the primary side terminals are inserted, secondary side terminal holes into which the secondary side terminals are inserted, and a slit disposed between the primary side terminal holes and the secondary side terminal holes. A transformer is mounted from the side of a mounting surface of the substrate. An insulating member is inserted into the slit from the side of a soldering surface of the substrate. The insulating member includes a protrusion portion that protrudes outside an area defined by virtual lines which are direct extension lines of the width of the slit to the side of the soldering surface. The protrusion portion is formed at a position more distant from the substrate than an end position of the shortest terminal of the primary side terminals and the secondary side terminals from the soldering surface of the substrate. |
| US11094452B2 |
Power converter
A power converter includes a magnetic core, a plurality of windings, a plurality of metal sidewalls, a first insulating member, and a second insulating member. The plurality of windings are each wound around the magnetic core and bent to have a portion extending in a direction in which the magnetic core extends. The plurality of metal sidewalls are disposed outside the plurality of windings and extend in the direction in which the magnetic core extends. The first insulating member is disposed between the plurality of windings and between the windings and the magnetic core. The second insulating member is disposed on an outside of the plurality of windings and in contact with each of the plurality of sidewalls and each of the plurality of windings. The second insulating member has a thermal conductivity higher than a thermal conductivity of the first insulating member. |
| US11094446B2 |
Rogowski coil with low permeability core
A Rogowski coil includes a magnetic core and a winding. The magnetic core includes an encircling body. The winding includes a conductive wire. The winding is disposed in a generally helical coil about the core body. |
| US11094444B2 |
Coil component
A coil component including a multilayer body, at least one coil provided inside the multilayer body, and outer electrodes disposed on at least one surface of the multilayer body. The multilayer body includes a first magnetic layer, an insulating layer laminated on the first magnetic layer, and a second magnetic layer laminated on the insulating layer. The coil has, at both ends thereof, lead-out portions, each of which extends up to the surface of the multilayer body and is connected to a respective one of the outer electrodes. The outer electrodes are each present over surfaces of the first magnetic layer, the insulating layer, and the second magnetic layer, and a width of a portion of at least one of the outer electrodes contacting the insulating layer is larger than widths of each of portions of that outer electrode contacting the first and second magnetic layers. |
| US11094439B2 |
Grooved, stacked-plate superconducting magnets and electrically conductive terminal blocks
Described herein are concepts, system and techniques which provide a means to construct robust high-field superconducting magnets using simple fabrication techniques and modular components that scale well toward commercialization. The resulting magnet assembly—which utilizes non-insulated, high temperature superconducting tapes (HTS) and provides for optimized coolant pathways—is inherently strong structurally, which enables maximum utilization of the high magnetic fields available with HTS technology. In addition, the concepts described herein provide for control of quench-induced current distributions within the tape stack and surrounding superstructure to safely dissipate quench energy, while at the same time obtaining acceptable magnet charge time. The net result is a structurally and thermally robust, high-field magnet assembly that is passively protected against quench fault conditions. |
| US11094438B2 |
Feedback control for no-insulation high-temperature superconducting magnet
An active feedback controller for a power supply current of a no-insulation (NI) high-temperature superconductor (HTS) magnet to reduce or eliminate the charging delay of the NI HTS magnet and to linearize the magnet constant. |
| US11094435B2 |
Bushing element and system composed of a separator and a bushing element
The invention relates to a bushing element for providing an electrically conductive connection through a separator, comprising an element body for positive or at least substantially positive insertion into a bushing receptacle of the separator, the element body comprising a continuously electrically conductive conducting portion for providing the electrically conductive connection and at least one electrically insulating portion for insulating the conducting portion against an inner surface of the bushing receptacle that encloses the conducting portion peripherally at least in part. The invention further relates to a system that is composed of a separator and a bushing element for providing an electrically conductive connection through the separator, the separator having a bushing receptacle into which the bushing element is inserted in a positive or at least substantially positive manner. |
| US11094433B2 |
Braided flat conductive tape
A method of forming a flat conductor that includes aligning multiple strands of flat conductive tape adjacent to each other, and braiding the strands of flat conductive tape to each other by sequentially bending one of the strands of flat conductive tape over the other strands of flat conductive tape to create a braided flat conductive tape. Each end of the braided flat conductive tape is connected to an electrical assembly for carrying electrical current therethrough. |
| US11094426B2 |
Vacuum chamber arrangement for charged particle beam generator
The invention relates to charged particle beam generator comprising a charged particle source for generating a charged particle beam, a collimator system comprising a collimator structure with a plurality of collimator electrodes for collimating the charged particle beam, a beam source vacuum chamber comprising the charged particle source, and a generator vacuum chamber comprising the collimator structure and the beam source vacuum chamber within a vacuum, wherein the collimator system is positioned outside the beam source vacuum chamber. Each of the beam source vacuum chamber and the generator vacuum chamber may be provided with a vacuum pump. |
| US11094425B2 |
Thermionic power cell
A thermionic (TI) power cell includes a heat source, such as a layer of radioactive material that generates heat due to radioactive decay, a layer of electron emitting material disposed on the layer of radioactive material, and a layer of electron collecting material. The layer of electron emitting material is physically separated from the layer of electron collecting material to define a chamber between the layer of electron collecting material and the layer of electron emitting material. The chamber is substantially evacuated to permit electrons to traverse the chamber from the layer of electron emitting material to the layer of electron collecting material. Heat generated over time by the layer of radioactive material causes a substantially constant flow of electrons to be emitted by the layer of electron emitting material to induce an electric current to flow through the layer of electron collecting material when connected to an electrical load. |
| US11094423B2 |
Nuclear fuel failure protection method
A method that provides a more direct indication of peak fuel rod centerline temperature and peak fuel rod clad temperature than conventionally inferred from the power distribution by directly and continuously measuring the fuel temperatures of the fuel pellets in one or more of the hottest fuel elements in the core. The peak fuel rod clad temperature is then obtained from the maximum measured peak fuel rod centerline temperature in combination with the maximum coolant core exit temperature and the minimum coolant flow rate. |
| US11094418B2 |
Optimized biological measurement
According to an example aspect of the present invention, there is provided an apparatus comprising a memory configured to store sensor data obtained from a person, and at least one processing core configured to perform a determination, based at least partly on the stored sensor data, concerning whether conditions are propitious to a biological measurement, and responsive to the conditions being determined to be propitious, to cause a triggering signal to be initiated concerning the biological measurement. |
| US11094416B2 |
Intelligent management of computerized advanced processing
Systems and methods are disclosed for automatically managing how and when computerized advanced processing techniques (for example, CAD and/or other image processing) are used. In some embodiments, the systems and methods discussed herein allow users, such as radiologists, to efficiently interact with a wide variety of computerized advanced processing (“CAP”) techniques using computing devices ranging from picture archiving and communication system (“PACS”) workstations to handheld devices such as smartphone and tablets. Furthermore, the systems and methods may, in various embodiments, automatically manage how data associated with these CAP techniques (for example, results of application of one or more computerized advanced processing techniques) are used, such as how data associated with the computerized analyses is reported, whether comparisons to prior abnormalities should be automatically initiated, whether the radiologist should be alerted of important findings, and the like. |
| US11094415B2 |
System, method and apparatus for cognitive oral health management
Approaches presented herein enable cognitive oral health management. Specifically, data from at least one internet of things (IoT) sensor and data from at least one visual image sensor are collected over time for a user via one or more sensors operatively coupled with one or more personal daily oral care devices as the user is performing a periodic oral care activity with the one or more personal daily oral care devices. Collected data are subjected to cognitive diagnostics to identify abnormalities in a user's oral healthcare regimen and physiological abnormalities within the oral cavity by categorizing data. A report for a medical professional may be generated providing recommendation of potential diagnoses and treatment options. |
| US11094413B1 |
Time-based resource allocation for long-term integrated health computer system
Provided is a system configured to allocate healthcare resources for population health management using time values, health scores, or health condition labels stored in a population of records. |
| US11094406B2 |
Medical product dispensing systems and methods
Methods and systems for transferring restricted distribution medical products to an over-the-counter general sales environment are provided. Methods and systems of dispensing non-prescription, behind-the-counter medical products from a vending machine in a general sales location are also provided. In some embodiments, methods and systems are provided for dispensing a medical product from a vending machine in a general sales location based, at least in part, on biometric data collected from the purchaser and, in some instances, based on self-selection and/or de-selection criteria, is provided. Further, methods and systems of switching prescription medical products to non-prescription, over-the-counter medical products are provided. |
| US11094404B2 |
Electronic medical record integration
Techniques for electronic medical record (EMR) integration are described. A middleware application may receive a command from a third-party application via an electronic network. The command may conform to a unified data format specified by a unified data model. The command may include a request to retrieve data from or write data to an EMR system. The middleware application may convert, using a mapping registrar, the command into a data format compatible with the EMR system. The middleware application may transmit, via another electronic network, the converted command to the EMR system. The middleware application may receive a response from the EMR system. The middleware application may convert, using a mapping registrar, the response into a result that may conform to the unified data format. The middleware application may transmit the converted result to the third-party application. |
| US11094403B2 |
Method and apparatus for collecting test data from use of a disposable test kit
A method of collecting test data from use of a disposable test kit, the method comprising the steps of: a code reader scanning a unique test identifier provided on the disposable test kit; an identification module identifying from the scanned unique test identifier a type of test performed by the disposable test kit; the code reader scanning a patient identifier; the identification module identifying from the scanned patient identifier a patient who has used the disposable test kit; a display and selection module automatically displaying on a display screen each of all possible distinct outcomes associated with the identified test as a selectable option; a user selecting one of the displayed all possible distinct outcomes for collection as test data; an association module automatically associating the test data with the patient; and the user activating storage of the test data to a data storer. |
| US11094400B2 |
System, method and apparatus for processing patient information and feedback
An apparatus system and method for processing patient data pursuant to a monitoring period, wherein received patient feedback data is processed and structured to provide a selectable keyword cloud to a display. The keyword cloud may include a plurality of at least one of symptoms, complications and patient conditions, wherein the keyword cloud is structured by a processor for display in accordance with previous patient feedback data during at least part of the monitoring period. |
| US11094396B2 |
Methods for fluorescence data correction
Method of processing real-time PCR data, comprising: c) receiving a plurality of fluorescence melting curve data of real time PCR-experiments performed by a real-time PCR device with at least two fluorescence channels, and configured to perform the following steps multiple times, while increasing a temperature: i) at first moments in time measuring a first temperature value and a first radiation value corresponding to a first fluorescence channel; ii) at second moments in time measuring a second temperature value and a second radiation value corresponding to a second fluorescence channel; d) storing the plurality of temperature values and radiation values; e) determining a plurality of time-shifted second radiation values by linearly interpolating between two measured second radiation values, using weighting factors defined by the measured temperature values; f) after performing step e), calculating color corrected first radiation values, and color corrected second radiation values. |
| US11094395B2 |
Retention voltage management for a volatile memory
An apparatus includes a memory circuit that includes a plurality of sub-arrays. The memory circuit is configured to implement a retention mode according to test information indicating voltage sensitivities for the plurality of sub-arrays. The apparatus also includes a voltage control circuit coupled to a power supply node. The voltage control circuit is configured, in response to activation of the retention mode for the plurality of sub-arrays, to generate, based on the test information, at least two different retention voltage levels for different ones of the plurality of sub-arrays. The at least two different retention voltage levels are lower than a power supply voltage level of the power supply node. |
| US11094391B2 |
List insertion in test segments with non-naturally aligned data boundaries
A processor memory is stress tested with a variable list insertion depth using list insertion test segments with non-naturally aligned data boundaries. List insertion test segments are interspersed into test code of a processor memory tests to change the list insertion depth without changing results of the test code. The list insertion test segments are the same structure as the segments of the test code and have non-naturally aligned boundaries. The list insertion test segments include list insertion segments and load/store segments. The list insertion segments locate a current memory location using a fixed segment at a known location. The load/store segments load and store list elements in memory. |
| US11094387B2 |
Multi-fuse memory cell circuit and method
A multi-fuse memory cell is disclosed. The circuit includes: a first fuse element electrically coupled to a first transistor, a gate of the first transistor is electrically coupled to a first selection signal; a second fuse element electrically coupled to a second transistor, a gate of the second transistor is electrically coupled to a second selection signal, both the first transistor and the second transistor are grounded; and a programming transistor electrically coupled to the first fuse element and the second fuse element, wherein a gate of the programming transistor is electrically coupled to a programming signal. |
| US11094384B2 |
Dynamic reference current sensing
A sensing circuit includes a current generating circuit and a sensing circuit. The current generating circuit includes a first portion configured to generate a first mirrored current corresponding to a first reference cell programmed to a low logical value, a second portion configured to generate a second mirrored current corresponding to a second reference cell programmed to a high logical value, and a transistor configured to generate a reference voltage by conducting a first reference current equal to a sum of the first mirrored current and the second mirrored current. The sensing circuit includes a sense amplifier configured to generate an output voltage having a logical value based on a second reference current and a cell current of a memory cell, the second reference current being generated from the reference voltage. |
| US11094383B2 |
Selective page calibration based on hierarchical page mapping
A computer-implemented method, according to one embodiment, includes: detecting that a calibration of a first page group has been triggered, and evaluating a hierarchical page mapping to determine whether the first page group correlates to one or more other page groups in non-volatile memory. In response to determining that the first page group does correlate to one or more other page groups in the non-volatile memory, a determination is made as to whether to promote at least one of the one or more other page groups for calibration. In response to determining to promote at least one of the one or more other page groups for calibration, the first page group and the at least one of the one or more other page groups are calibrated. Moreover, each of the page groups includes one or more pages in non-volatile memory. |
| US11094382B2 |
Semiconductor memory device including page buffers
A semiconductor memory device includes a plurality of page buffers defined in active regions of a substrate; and a plurality of wiring lines disposed over the page buffers, and coupled to the page buffers through contacts. The plurality of wiring lines may include contact portions which are coupled with the contacts, respectively. The plurality of wiring lines may be configured into a bent shape such that the contact portions are offset toward center lines of the active regions. |
| US11094376B2 |
In-memory compute array with integrated bias elements
An in-memory compute (IMC) device includes a compute array having a first plurality of cells. The compute array is arranged as a plurality of rows of cells intersecting a plurality of columns of cells. Each cell of the first plurality of cells is identifiable by its corresponding row and column. The IMC device also includes a plurality of computation engines and a plurality of bias engines. Each computation engine is respectively formed in a different one of a second plurality of cells, wherein the second plurality of cells is formed from cells of the first plurality. Each computation engine is formed at a respective row and column intersection. Each bias engine of the plurality of bias engines is arranged to computationally combine an output from at least one of the plurality of computation engines with a respective bias value. |
| US11094375B2 |
Concurrent read and reconfigured write operations in a memory device
A method of controlling a memory device can include: receiving, by an interface, a write command from a host; beginning execution of a write operation on a first array plane of a memory array in response to the write command, where the memory array includes a plurality of memory cells arranged in a plurality of array planes; receiving, by the interface, a read command from the host; reconfiguring the write operation in response to detection of the read command during execution of the write operation; beginning execution of a read operation on a second array plane in response to the read command; and restoring the configuration of the write operation after the read operation has at least partially been executed. |
| US11094372B1 |
Partial writing method of dram memoryl device to reduce power consumption associated with large voltage swing of internal input/output lines
A semiconductor memory and a partial writing method are provided. The semiconductor memory includes a memory bank, a write amplifier circuit, a plurality of input/output pins and a plurality of address pins. The write amplifier circuit is coupled to the memory bank through a plurality of internal input/output lines. The plurality of input/output pins are coupled to the write amplifier circuit through a plurality of input lines. A part of plurality of address pins receive a column address instruction, and at least one of another part of the plurality of address pins receive an operation code. The semiconductor memory determines a part of the internal input/output lines for transmitting input data according to the operation code, and operates the write amplifier circuit to perform a partial writing mode according to the operation code so as to write the input data into the memory bank according to the column address instruction. |
| US11094368B2 |
Memory, memory chip and memory data access method
A memory, a memory chip and a memory data access method are provided. The memory of the disclosure includes a plurality of memory chips. Each of the plurality of memory chips includes a first bank group, a second bank group and a read amplifier and a write amplifier. The first bank group includes a plurality of first memory banks. The second bank group includes a plurality of second memory banks. The read amplifier and the write amplifier are separately coupled to the first bank group and the second bank group. The read amplifier and the write amplifier are configured to independently access different bank groups. |
| US11094363B2 |
Reduced peak self-refresh current in a memory device
Devices and methods include organizing memory units of a memory device into a number of groups. The devices and methods also include self-refreshing each group of memory units on different corresponding sequential clock pulses of a self-refresh clock. Specifically, at least one of each group of memory units counts pulses of a self-refresh clock and invokes a self-refresh after every nth pulse of a cycle of pulses while not invoking a self-refresh on all other pulses of the cycle of pulses. |
| US11094359B2 |
High retention multi-level-series magnetic random-access memory
A magnetic memory pillar structure having a plurality of magnetic memory elements connected in series, wherein switching of individual memory elements in the pillar structure can be accomplished based on differing switching current values of the magnetic memory elements. Each of the plurality of memory elements advantageously have similar retention values in spite of the different switching current values (latency values) as a result of a precessional spin current injection structure provided in the memory element or memory elements having the lower switching current value. |
| US11094358B2 |
Semiconductor chip manufacturing process for integrating logic circuitry, embedded DRAM and embedded non-volatile ferroelectric random access memory (FERAM) on a same semiconductor die
An apparatus is described. The apparatus includes a semiconductor chip that includes logic circuitry, embedded dynamic random access memory (DRAM) cells and embedded ferroelectric random access memory (FeRAM) cells. |
| US11094357B2 |
Memory devices with user-defined tagging mechanism
A memory device includes a memory array with memory blocks each having a plurality of memory cells, and one or more current monitors configured to measure current during post-deployment operation of the memory device; and a controller configured to identify a bad block within the memory blocks based on the measured current, and disable the bad block for preventing access thereof during subsequent operations of the memory device. |
| US11094354B2 |
First order memory-less dynamic element matching technique
A quantizer generates a thermometer coded signal from an analog voltage signal. Data weighted averaging (DWA) of the thermometer coded signal is accomplished by controlling the operation of a crossbar switch controlled by a switch control signal to generate an output DWA signal. The output DWA signal is latched to generate a latched output DWA signal which is processed along with bits of the thermometer coded input signal in feedback loop to generate the switch control signal. The latching of the output DWA signal is performed in an input register of a digital-to-analog converter which operates to convert the latched output DWA signal to a feedback analog voltage from which the analog voltage signal is generated. The switch control signal specifies a bit location for a beginning logic transition of the output DWA signal cycle based on detection of an ending logic transition of the latched DWA signal. |
| US11094352B2 |
Removing mechanism of storage device
A removable mechanism for a hard drive is revealed. The removable mechanism includes an upper substrate and a base plate hanged and sliding below the upper substrate, and a control handle and a sliding board are set between the upper substrate and the base plate to carry each other. The control handle controls a pivot element sliding on an opening of the base plate. By carrying each other to carry a stop element of the base plate, the stop element slides on a concave opening for dismounting a storage device inserted to the removable drawing mechanism. Thereby, the present application is convenient for dismounting the storage device. |
| US11094351B2 |
System and method for representing long video sequences
Systems and procedures for transforming video into a condensed visual representation. An example procedure may include receiving video comprised of a plurality of frames. For each frame, the example procedure may create a first representation, reduced in one dimension, wherein a visual property of each pixel of the first representation is assigned by aggregating a visual property of the pixels of the frame having the same position in the unreduced dimension. The example procedure may further form a condensed visual representation including the first representations aligned along the reduced dimension according to an order of the frames in the video. |
| US11094348B2 |
Disc library storage system and disc cartridge used thereof
A disc library storage system and a disc cartridge thereof are provided. The disc library storage system includes a disc library, a disc drive tower, a disc transport device and a disc changing device. The disc library accommodates multiple discs. The disc drive tower accommodates multiple disc drives. The disc drives read data of the discs. The disc transport device moves the discs from the disc library to the disc drive tower and to the disc library. The disc changing device places a disc cartridge including an outer casing and a disc tray. The disc tray accommodates at least one replacement disc. The disc changing device has a pull-out state, in which the disc tray is received in the outer casing, and a close state, in which the disc tray is drawn from the outer casing and the disc transport device unloads the replacement disc from the disc tray. |
| US11094343B2 |
Magnetic tape having characterized magnetic layer and magnetic recording and reproducing device
The magnetic tape includes a non-magnetic support; and a magnetic layer including ferromagnetic powder and a binding agent on the non-magnetic support, in which an absolute value ΔN of a difference between a refractive index Nxy measured regarding an in-plane direction of the magnetic layer and a refractive index Nz measured regarding a thickness direction of the magnetic layer is 0.25 to 0.40, and a logarithmic decrement acquired by a pendulum viscoelasticity test performed regarding a surface of the magnetic layer is equal to or smaller than 0.050. |
| US11094341B1 |
Magnetic disk device
According to one embodiment, a magnetic disk device includes a magnetic disk, a magnetic head, a first actuator that moves the magnetic head to a predetermined position on the magnetic disk, a second actuator that is provided in the first actuator and adjusts a position of the magnetic head, a control unit that controls operations of the first actuator and the second actuator, and a storing unit that stores a coefficient of an approximation polynomial calculated based on an approximation formula for approximating voltage dependency of a gain of the second actuator. When controlling the operation of the second actuator, the control unit calculates the gain amplitude of the second actuator from the approximation polynomial in which the coefficient is used and amplitude of a voltage input to the second actuator. |
| US11094339B1 |
Methods of manufacturing one or more sliders that includes a second lapping process after patterning, and related sliders
The present disclosure relates to kiss lapping sliders after patterning an air bearing surface pattern, followed by applying a protective overcoat to the air bearing surface. The present disclosure also involves related sliders. |
| US11094337B2 |
Cough detection device, cough detection method, and recording medium
A cough detection device including: an acoustic feature extractor that extracts at least one acoustic feature from acoustic data output by a microphone array according to a sound received; a first identifier that performs identification of the sound based on the at least one acoustic feature to determine whether the sound is a cough sound; a direction estimator that estimates an arrival direction of the sound from the acoustic data; an image selector that selects, from first image data indicating an image obtained by capturing a scene in which the sound occurs, second image data indicating an area corresponding to the arrival direction estimated; and a second identifier that performs identification of the image based on the second image data to determine whether a coughing action is shown in the image. |
| US11094335B1 |
Systems and methods for automatic detection of plagiarized spoken responses
Systems and methods are provided for automatic detection of plagiarized spoken responses during standardized testing of language proficiency. A first spoken response to a speaking task that elicits spontaneous speech and a second spoken response to a source-based speaking task that is assumed to be non-plagiarized are digitally recorded. A first and second sets of speaking proficiency features are calculated for the first and the second spoken response, respectively. The first spoken response is classifying as plagiarized or non-plagiarized based on the comparison between the first and the second set of speaking proficiency features. Corresponding apparatuses, systems, and methods are also disclosed. |
| US11094334B2 |
Sound processing method and apparatus
The present invention discloses a sound processing method and apparatus. The method is applied to a non-video-call scenario. The method includes: when it is detected that a camera of a terminal is in a shooting state, collecting a sound signal by using the two microphones at the top of the terminal; calculating an interaural level difference between the two microphones based on collected sound signals according to a preset first algorithm; determining whether the interaural level difference meets a sound source direction determining condition; if the determining condition is met, determining, based on the interaural level difference, whether the sound signal includes a rear sound signal, where the rear sound signal is a sound signal whose sound source is located behind the camera; and if it is determined that the sound signal includes a rear sound signal, filtering out the rear sound signal from the sound signal. |
| US11094333B2 |
Device and method for stereo noise cancellation
A method of noise cancellation comprises providing a first estimated output signal based on an input signal and a first prior far-end channel filter and a second prior far-end channel filter corresponding to a prior frame, updating a first current far-end channel filter corresponding to a current frame according to the first estimated output signal and the first prior far-end channel filter, providing a second estimated output signal based on the input signal, the first current far-end channel filter, and the second prior far-end channel filter, updating a second current far-end channel filter corresponding to the current frame according to the second estimated output signal and the second prior far-end channel filter, and providing a resultant signal based on the input signal, the first current far-end channel filter, and the second current far-end channel filter. |
| US11094331B2 |
Post-processor, pre-processor, audio encoder, audio decoder and related methods for enhancing transient processing
An audio post-processor for post-processing an audio signal having a time-variable high frequency gain information as side information includes: a band extractor for extracting a high frequency band of the audio signal and a low frequency band of the audio signal; a high band processor for performing a time-variable modification of the high frequency band in accordance with the time-variable high frequency gain information to obtain a processed high frequency band; and a combiner for combining the processed high frequency band and the low frequency band. Furthermore, a pre-processor is illustrated. |
| US11094327B2 |
Audible input transcription
One embodiment provides a method, comprising: capturing, at an information handling device, audible input from at least one user; providing, on a display device operatively coupled to the information handling device, at least one transcription suggestion, wherein the at least one transcription suggestion is associated with a portion of the audible input; and inputting, responsive to receiving a selection input on the at least one transcription suggestion, the at least one transcription suggestion into an underlying application. Other aspects are described and claimed. |
| US11094324B2 |
Accumulative multi-cue activation of domain-specific automatic speech recognition engine
A method includes detecting a keyword within an audio stream. The keyword is one of multiple keywords in a database, in which each of the multiple keywords relates to at least one of multiple domains in the database. The database stores a first confidence weight for each of the multiple keywords that are related to a first domain among the multiple domains. Each first confidence weight indicates a probability that a corresponding keyword relates to the first domain. The method includes determining whether a first confidence weight of the keyword is at least equal to an activation threshold value associated with the first domain. The method includes, in response to the first confidence weight of the keyword meeting the activation threshold value, activating a DS-ASR engine corresponding with the first domain to perform speech-to-text conversion on the audio stream. |
| US11094322B2 |
Optimizing speech to text conversion and text summarization using a medical provider workflow model
A method, a system, and a computer program product are provided. Speech signals from a medical conversation between a medical provider and a patient are converted to text based on a first domain model associated with a medical scenario. The first domain model is selected from multiple domain models associated with a workflow of the medical provider. One or more triggers are detected, each of which indicates a respective change in the medical scenario. A corresponding second domain model is applied to the medical conversation to more accurately convert the speech signals to text in response to each of the detected one or more triggers. The corresponding second domain model is associated with a respective change in the medical scenario of the workflow of the medical provider. A clinical note is provided based on the text produced by converting the speech signals. |
| US11094312B2 |
Voice synthesis method, voice synthesis apparatus, and recording medium
A voice synthesis method designates a target feature of a voice to be synthesized; specifies harmonic frequencies for a plurality of respective harmonic components of the voice and an amplitude spectrum envelope of the voice; specifies a harmonic amplitude distribution of each of the plurality of respective harmonic components based on (i) the target feature, (ii) the amplitude spectrum envelope, and (iii) the harmonic frequency specified for the respective harmonic component, the harmonic amplitude distribution representing a distribution of amplitudes in a unit band with a peak amplitude corresponding to the respective harmonic component; and generates a frequency spectrum of the voice with the target feature based on harmonic amplitude distributions specified for each of the plurality of respective harmonic components and the amplitude spectrum envelope. |
| US11094307B2 |
Electronic musical instrument and method of causing electronic musical instrument to perform processing
An electronic musical instrument includes a playing operator, and a sound source which performs processing of receiving, in response to a user operation on the playing operator, a sound generation instruction according to playing operation information including the pitch information indicating the certain pitch and sound volume information indicating a certain volume, and generating sound according to the certain pitch and the certain volume, based on excitation data generated by multiplying partial data by a window function, the partial data being included in excitation signal waveform data generated based on a plurality of waveform data items which are respectively different from each other in sound intensity in the certain pitch. |
| US11094305B2 |
Information processing device, tempo detection device and video processing system
An information processing device, a tempo detection device and a video processing system are provided. A beat of a piece of performed music is detected from a musical viewpoint. The information processing device includes: an acquisition part that acquires samples of musical sound signals in a time series; an evaluation part that has an adaptive filter using the acquired samples of the musical sound signals as reference signals and using samples of musical sound signals acquired a predetermined time earlier than the samples of the musical sound signals as input signals; and a tempo determination part that sequentially inputs the samples of the musical sound signals to the adaptive filter and determines a tempo corresponding to a musical sound based on a filter coefficient when a value of the filter coefficient of the adaptive filter converges. |
| US11094302B2 |
Effect imparter for musical instrument
An effect imparter for a musical instrument includes a wire bundle including at least one snare, and a plate that has a hook configured to be hooked by a string and that is fixed to a first end portion of the wire bundle. |
| US11094300B2 |
Stringed instrument with optimized energy capture
A stringed instrument, such as an acoustic, electric, or semi-acoustic electric guitar or bass, can employ a stringpath assembly that consists of a tail structure connected to a head structure via a plurality of strings with the tailpiece consisting of a body disposed between a bridge mechanically fastened to a tailpiece with each string of the plurality of strings continuously extending from the bridge through the body to the tailpiece to efficiently capture vibration of the plurality of the strings. |
| US11094297B2 |
Electrically enabled sound post for stringed musical instruments
A sound post assembly for a musical instrument, comprising two or more mechanically movable parts that allow for a length adjustment of the sound post assembly and one or more electrical components. In an example embodiment, the electrical components are configured to electrically measure the force exerted by the sound post on the upper and lower walls of the instrument's sound box. In some embodiments, the electrical components may operate to mechanically change the length of the sound post assembly through an electrical actuator, such as a piezo-electric actuator or an electro-magnetic motor. Also disclosed are example safety mechanisms and methods of wiring and interfacing said sound post assembly with a control unit. |
| US11094296B2 |
Varying display refresh rate
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for enabling a variable refresh rate on a display. One of the methods includes receiving, from a content presentation device, a first signal set to a first value; completing generation of first visual content; and after completing the generation of the first visual content, determining that the first signal is set to the first value and a second threshold duration of time has not expired; sending, to the content presentation device, the first visual content, wherein sending the first visual content causes the content presentation device to change the first signal from the first value to the second value; and after sending the first visual content, receiving, from the content presentation device, the first signal set to the second value. |
| US11094286B2 |
Image processing apparatus and image processing method
An image processing apparatus for generating data of an image and outputting the generated data to a display device, includes a meta data acquiring unit configured to acquire meta data used for a correcting process for correcting the image in the display device, a corrector configured to perform at least part of the correcting process on the image, using the meta data, and an image output unit configured to acquire data of the corrected image from the corrector and output the acquired data to the display device. |
| US11094283B2 |
Head-wearable presentation apparatus, method for operating the same, and medical-optical observation system
A method for operating a head-wearable presentation apparatus is provided. The method comprises the steps of: capturing data that are representative of at least one state variable of the head of a person wearing the head-wearable presentation apparatus, evaluating the captured data in order to determine the at least one state variable of the head, and modifying a degree of transparency of at least one playback arrangement of the head-wearable presentation apparatus if the at least one state variable of the head corresponds to a predetermined state variable. |
| US11094279B2 |
Pixel compensation method, pixel compensation device and display device
A pixel compensation method, a pixel compensation device and a display device are provided. The pixel compensation method includes: determining a target sub-pixel to be compensated in a display area; setting at least one charged sub-pixel connected to a same data line as the target sub-pixel, as a reference sub-pixel; acquiring a compensation value of the target sub-pixel; and compensating a display parameter of the target sub-pixel based on the compensation value. |
| US11094277B2 |
Shift register and driving method thereof, gate drive circuit and display apparatus
A shift register, a gate drive circuit, a display apparatus and a driving method of the shift register are provided. The shift register includes an input subcircuit, a first and a second output subcircuits, a trigger signal input terminal, a first and a second signal output terminals, a first and a second clock terminals and a pull-up node, a control terminal and an output terminal of the input subcircuit are electrically coupled to the trigger signal input terminal and the pull-up node, respectively, for providing a valid signal received by the control terminal of the input subcircuit to the pull-up node. The shift register is provided with the first and second output subcircuits which share the same input subcircuit, greatly reducing the number of devices and thus greatly simplifying the structure of the cascaded shift registers and reducing the area of the whole display apparatus. |
| US11094276B2 |
Gate driver, display apparatus including the same and method of driving display panel using the same
A gate driver includes a gate signal generating part, a switching part and a switching controlling part. The gate signal generating part is configured to generate a gate signal including a precharge time and a normal charge time using a compensated gate on voltage and a gate off voltage. The switching part is disposed between the gate signal generating part and a gate line. The switching part is configured to apply a compensated gate signal to the gate line. The switching controlling part is configured to generate a switching control signal for controlling an operation of the switching part. |
| US11094270B2 |
Display device and drive method therefor
A display device and a drive method, the display device including: an edge-lit backlight module; a liquid crystal display panel positioned on the light-emergent side of the edge-lit backlight module; and a polymer liquid crystal film positioned between the liquid crystal display panel and the edge-lit backlight module, and including a plurality of closely arranged independent dimming areas, each dimming area being configured for independent control of light transmittance. The present display device takes advantage of the characteristics of the polymer liquid crystal film, loading different driving voltages in different dimming areas and changing the transmittance of the polymer liquid crystal film. |
| US11094269B2 |
Display device and display system
A display device includes: a liquid crystal display panel including a liquid crystal between two substrates; and first, second, and third light sources emitting light in different colors. A light emission period includes a first light emission period in which luminance of the first light source is higher than luminance of the second and third light sources, and at least one of the second and third light sources emits light, a second light emission period in which the luminance of the second light source is higher than the luminance of the first and the third light sources, and at least one of the first and third light sources emits light, and a third light emission period in which the luminance of the third light source is higher than the luminance of the first and second light sources, and at least one of the first and second light sources emits light. |
| US11094260B2 |
Pixel circuit, display panel, display device, and driving method
A pixel circuit, a display panel, a display device, and a method of driving a display device are provided. The pixel circuit includes a driving sub-circuit, a first data writing sub-circuit, a second data writing sub-circuit, and a storage sub-circuit. The first data writing sub-circuit is configured to write a first data voltage to a first terminal of the storage sub-circuit in a case of being turned on under control of a first data scanning signal; the second data writing sub-circuit is configured to write a second data voltage to a second terminal of the storage sub-circuit in a case of being turned on under control of a second data scanning signal; and the driving sub-circuit is configured to drive a light emitting element to emit light under control of the voltage at the first terminal of the storage sub-circuit. |
| US11094258B2 |
Pixel circuit
A pixel circuit includes: a main circuit including: a driving transistor that includes a gate terminal connected to a first node, a first terminal connected to a second node, and a second terminal connected to a third node; and an organic light-emitting element connected to the driving transistor and configured to control the organic light-emitting element by controlling a driving current corresponding to a data signal applied via a data line to flow into the organic light-emitting element; and a sub circuit including: a first compensation transistor that includes a gate terminal configured to receive a first gate signal, a first terminal connected to the first node, and a second terminal connected to a fourth node; and a second compensation transistor that includes a gate terminal configured to receive a second gate signal, a first terminal connected to the fourth node, and a second terminal connected to the third node. |
| US11094256B2 |
Display device and driving method thereof
A display device and a driving method thereof are provided. The display device includes: a display panel including a plurality of pixels; a timing controller for calculating an On-Pixel Ratio (OPR) of input image data with respect to an arbitrary frame, and correcting the input image data, based on the OPR; and a data driver for generating a data signal, based on the corrected image data, and providing the data signal to the display panel. The OPRs are calculated in units of pixel rows. |
| US11094247B2 |
Driving apparatus of light emitting diode display device for compensating emission luminance gap
A driving apparatus of a light emitting diode (LED) display device is provided. The driving apparatus includes a timing control circuit. The timing control circuit outputs a plurality of driving control signals to a gate driving circuit on an LED display panel of the LED display device. Wherein, the plurality of driving control signals includes a first driving control signal and a second driving control signal, and the pulse width of the first driving control signal in a first horizontal line period is different from the pulse width of a second driving control signal in a second horizontal line period preceding to the first horizontal line period. |
| US11094246B2 |
Operating module for display and operating method, and electronic device supporting the same
An electronic device is provided. The electronic device may include a display driver module configured to, in response to receiving display data, divide the display data into a plurality of segments corresponding to a plurality of display regions, compare the display data in the plurality of segments to determine whether the display data in at least one segment is substantially same as the display data in another segment, and based on the comparison outcome, selectively amplify a first display signal generated from the display data in the at least one segment or a second display signal generated from the display data in the another segment. |
| US11094244B2 |
Scanning circuit, driver circuit, touch display panel, receiving switching circuit and driving method
A scanning circuit, a driver circuit, a touch display panel, a receiving switching circuit and a driving method are disclosed. The scanning circuit includes a function switching circuit and a plurality of shift register units that are cascaded. Each shift register units includes a control terminal and a shift scanning output terminal, and is configured to output a first output signal at the shift scanning output terminal; the function switching circuit includes a mode switching input terminal, a control signal output terminal and a mode scanning output terminal, and the control signal output terminal and the mode scanning output terminal are respectively connected to the control terminals and the shift scanning output terminals of the plurality of shift register units. The function switching circuit is configured to output the control signal to the control terminals or to output a second output signal to the shift scanning output terminals. |
| US11094239B2 |
Shift register and driving method thereof, gate driving circuit and display device
A shift register and driving method thereof, a gate driving circuit and a display device are provided. The shift register includes a first input unit, a second input unit, a pull-up control unit, a pull-down control unit, an output control unit and an output reset unit, wherein the first input unit, the second input unit, the pull-up control unit, the pull-down control unit and the output control unit are coupled to a first node, and the pull-up control unit, the pull-down control unit and the output reset unit are coupled to a second node. |
| US11094237B2 |
Display device with connection board and method of testing pad contact state thereof
A display device includes a display panel including first to fourth panel pads and a connection board including first to fourth connection board pads coupled to the first to fourth pads, respectively. The first and second panel pads are electrically connected to each other, and the third and fourth panel pads are electrically connected to each other. The connection board includes a driving circuit which generates a first test result signal based on a first panel test signal transmitted to the first connection board pad and a first panel feedback signal received from the second connection board pad, generates a second test result signal based on a second panel test signal transmitted to the third connection board pad and a second panel feedback signal received from the fourth connection board pad, and sequentially outputs the first and second test result signals as a test result signal. |
| US11094235B2 |
Vehicle bodywork display screen
A bodywork panel for a vehicle such as a racing car or a racing motorcycle is fitted with one or more optically clear panels, which are profiled to follow the aerodynamic form of the bodywork panel. A flexible reflective display screen, for examples based on e-paper, is mounted to an inner face of each optically clear panel such that an image on the display screen is visible outside the vehicle through the optically clear panel. A paint finish on the bodywork panel continues over a peripheral region of each optically clear panel, concealing a join between it and the bodywork panel. Images displayed on the display screens via a display controller can thus appear like painted graphics on the bodywork panel, except that they may be changed as desired. Thus, graphics on the vehicle, such as advertising and sponsorship logos, can be changed at will during a race. Leathers worn by racing motor cyclists can be fitted with similar display screens mounted behind optically clear flexible plastic panels sewn to the leathers. |
| US11094234B2 |
System and method for ground-based advertising
An advertising unit includes a transparent or translucent cover. A back unit includes a base as well as first and second side ridges which extend from, and along, side edges of the base. A track defined by the first and second side ridges is configured to receive the cover in a sliding arrangement. The space between said cover and said back unit defines a cavity configured to receive one or more advertisements. |
| US11094232B2 |
Display set and display method
In a viewing object display set, it is possible to prevent a reduction in a sense of reality when a viewing object is seen. Specifically, the display set for viewing the viewing object includes the viewing object that is attached to a display surface and an object for visual effect that is provided on a viewing position side with respect to the viewing object and shields at least a portion of the viewing object. The object for visual effect is arranged so as to shield the boundary between the viewing object and the display surface. |
| US11094227B1 |
Magnetic exterior shutter product
The current invention is directed to a magnetic exterior shutter product. The magnetic exterior shutter product comprises a cutout and/or shutter. The cutout is attached to a first fastener wherein the first fastener comprises a first magnetic or ferromagnetic material. A first adhesive may attach the first fastener to the cutout. The cutout may be magnetically attached to an exterior shutter. The shutter may comprise a shutter front surface, a shutter rear surface, and a second fastener comprising a second magnetic or ferromagnetic material wherein the second fastener is attached to the shutter front surface, the shutter rear surface, or embedded between the shutter front surface and the shutter rear surface. |
| US11094226B2 |
Resin molding
A resin molding is provided. The resin molding includes an optically transparent plate-shaped portion, which has a first surface having a smooth surface portion, and a second surface having plural sections, wherein each of the plural sections has a width and includes one or more convex portions which have one or more ridge lines extending in a ridge line direction. The ridge line direction of the one or more convex portions of at least one of the plural sections is different from the ridge line direction of the one or more convex portions of one or more of others of the plural sections. When the first surface of the resin molding is observed from outside, the resin molding has metallic appearance. |
| US11094222B2 |
Hands-on learning play controlled video display
Embodiments describe an approach for concurrently managing a video display and an application user interface. Embodiments describe generating a translucent mask video display over a computer-implemented application and displaying a video in the translucent mask video display over the computer-implemented application. Additionally, embodiments describe detecting user activity associated with the computer-implemented application and pausing the video in the translucent mask video display when the user activity is detected. Responsive to an end to the user activity, embodiments describe translating the detected user activity as a set of computer operations, outputting the set of computer operations for performance on the computer-implemented application, and resuming the video in the translucent mask video display. |
| US11094220B2 |
Intelligent augmented reality for technical support engineers
A support method, system, and computer program product, include identifying a repair or a maintenance task, determining an expertise level of the local engineer, receiving a procedure for performing the repair or the maintenance task, the procedure including a series of steps, instructional information associated with each step, and technical information associated with the repair or the maintenance task, based on the expertise level of each engineer, filtering the instructional information, and the technical information in the procedure to exclude information already known by the engineer, presenting, via an augmented reality device, a first step of the series of steps and the associated filtered information. |
| US11094218B2 |
System and method for improving reading skills of users with reading disability symptoms
A system and method for teaching users reading comprehension. In an aspect, user's educational teaching system and method utilizes visual representations on a user's device display of a focusing point called a Bindu and a viewpoint called a Mind's Eye to assist in the learning of words. The combination of the Bindu with the Mind's Eye force a user to align the two with one another in order to present an unobstructed view of a 3-D representation of 2-D letters, numbers, punctuations, and words. |
| US11094216B2 |
System and method for music score simplification
A musical system may include one or more storage media, at least one processor, one or more sensors corresponding to keys of a musical instrument, and a display. The storage media may be configured to store a set of instructions for modifying a music score for a user based on a performance level of the user. The at least one processor may be configured to communicate with the one or more storage media. When executing the set of instructions, the processor is directed to determine a user performance level of a user and provide a modified music score for the user based on the user performance level. The sensors may be configured to sense a motion of at least one key of the keys and generate a key signal accordingly. The display may be configured to display the modified music score. |
| US11094213B2 |
Communications system for prompting student engaged conversation
A system for prompting student engaged conversation, the system receives a student entered limited descriptive entry at a first remote terminal, stores the entry, e.g., in a central database, and sends a notification of the entry to a teacher of the student at a second remote terminal. The system may also send a second notification regarding the entry to a parent of the student at a third remote terminal. The second notification may be triggered by a teacher response or submission in response to the first notification. The first and second notifications may be sent using any of a text, a voicemail, an e-mail, a display message, an application operating at a mobile device, and a program operating a remote terminal. |
| US11094209B1 |
Location determination when satellite navigation system is inaccessible
The disclosed method may include (1) receiving, at a receiving vehicle from a first transmitting vehicle, a first wireless signal carrying first data indicating a first location of the first transmitting vehicle, (2) determining a first bearing from which the first wireless signal is received at the receiving vehicle, (3) receiving, at the receiving vehicle from a second transmitting vehicle, a second wireless signal carrying second data indicating a second location of the second transmitting vehicle, (4) determining a second bearing from which the second wireless signal is received at the receiving vehicle, and (5) determining a receiving location of the receiving vehicle by triangulation using the first location, the first bearing, the second location, and the second bearing. Various other methods, systems, and computer-readable media are also disclosed. |
| US11094201B2 |
Method, device and system for vehicle positioning
The present disclosure provides a system, a method and an apparatus for vehicle positioning. The method includes: acquiring positioning information pre-stored in a roadside device while a vehicle is moving, the positioning information including direction information and/or position information associated with a position of the roadside device; determining a current position of the vehicle based on position information determined by a vehicle-mounted positioning device and the positioning information acquired from the roadside device. |
| US11094200B2 |
Dynamic processing system for roadside service control and output generation
Aspects of the disclosure relate to a dynamic processing system for roadside service control and output generation. A computing platform may receive map interface information. The computing platform may generate and display a map interface that includes a visual identifier that is centrally located on the map interface and corresponds to a location of the computing platform. The computing platform may receive a location adjustment input adjusting the map interface. The visual identifier may remain centrally located on the map interface while the location adjustment input is received and may correspond to a vehicle location after the location adjustment input is received. After receiving the location adjustment input and based at least in part on a received location confirmation input, the computing platform may send a disabled vehicle indication, which may include the vehicle location and cause dispatch of a service vehicle to the vehicle location. |
| US11094196B2 |
Apparatus and method for controlling a rear cross traffic alert
An apparatus for controlling a rear cross traffic alert includes: a parking form determiner that determines a parking form of a vehicle using at least one of sensing information or parking space information; a reference angle setter that sets a reference angle for controlling a rear cross traffic alert in accordance with the parking form; and a traffic alert controller that controls generation/non-generation of a traffic alert using a result of comparison between an incidence angle, which is formed by a movement path of another vehicle detected inside a rear cross traffic alert area of the vehicle and a longitudinal reference line of the vehicle, and the reference angle if a rear cross traffic alert start condition of the vehicle is satisfied. |
| US11094191B2 |
Distributed safety infrastructure for autonomous vehicles and methods of use
Systems and methods for assisting navigation of traffic participants are described herein. An exemplary method may commence with collecting street object data by at least one sensor mounted on one of a plurality of poles. The street object data may be associated with at least one street object within a range of the at least one sensor. The method may continue with analyzing the street object data and generating street object metadata corresponding to the at least one street object. The method may continue with broadcasting the street object metadata to at least one traffic participant within the range. The street object metadata may be used to provide at least one warning to the at least one traffic participant of traffic conditions to allow the at least one traffic participant to take at least one proactive action. |
| US11094190B2 |
Method and device for using telecommunication networks to control media and entertainment devices
A system and method for controlling media devices over telecommunication networks is disclosed. In particular embodiments, the system and method utilize cellular telecommunication networks. The present system and method allows a user to control and, in some instances, unify a multitude of devices over the telecommunication network. Through telecommunication networks, such as cellular networks, media and entertainment can be shared between multiple devices. |
| US11094188B2 |
System and method for monitoring an individual
In accordance with one or more embodiments herein, a system for monitoring an individual within predetermined facilities 500 in order to determine whether there is a need for setting an alert is provided. The system 100 comprises: a personal module 200 to be worn by the monitored individual, the personal module 200 comprising at least one motion sensor 220; at least one node module 300, with which the personal module 200 is arranged to communicate; a storage means 320; and at least one processing device 210, 310, 160. The at least one processing device 210, 310, 160 may be arranged to: receive sensor data from the at least one motion sensor 220 in the personal module 200; determine whether the received sensor data indicates a specific alert state among a plurality of predetermined alert states, the alert states comprising at least a FALL alert state, to be used if a probable fall has been detected for the monitored individual, and an OUT OF BED alert state, to be used if it has been detected that the monitored individual is probably getting out of bed; determine the distance between the personal module 200 and the at least one node module 300; determine the location of the personal module 200 within the facilities 500 based at least on the determined distance together with information retrieved from the storage means 320 regarding the layout of the facilities 500 within which the monitoring of the individual takes place; and set an alert based at least on whether the received sensor data indicates an alert state and whether the determined location fulfils a predetermined location condition, indicating whether the individual is located in a certain room, such as e.g. the bedroom 530. |
| US11094186B2 |
Systems and methods for managing alarm data of multiple locations
A method for managing alarm data of multiple physical locations. The method includes receiving a plurality of sets of alarm data. Each of the plurality of sets of alarm data corresponds to a respective physical location. Each of the plurality of sets of alarm data includes a respective occurrence value corresponding to each of a plurality of alarm categories. The method includes receiving a list indicating one or more alarm preferences. of the or more alarm preferences are associated with one or more priority values. The method includes arranging, responsive to identifying a first of the one or more alarm preferences that indicates a first subset of the alarm categories, a ranking of the plurality of sets of alarm data based on respective occurrence values of the first set of alarm categories. The method includes displaying, via a user interface, the ranking of the plurality of sets of alarm data. |
| US11094182B2 |
Using sensors to detect movement of light fixtures
A light fixture can include a housing and a sensor device having a sensor that measures at least one parameter associated with a position of the housing. The light fixture can also include a controller coupled to the sensor device. The controller can receive multiple measurements of the at least one parameter taken by the sensor device. The controller can also evaluate each measurement against at least one range of acceptable values. The controller can further send a notification when a measurement falls outside the at least one range of acceptable values. The notification can state that the housing is moved out of position and requires attention. |
| US11094181B2 |
Methods for managing operational data associated with connected devices based on policy
This disclosure relates to the analysis of data generated by one or more connected systems and devices. Operational data obtained by one or more connected devices and/or systems, such as a connected thermostat and/or wind turbine system, may be used to detect and/or predict impending failures and/or suboptimal performance. By detecting and/or predicting anomalous system and device performance, various actions may be taken to improve system and device performance and mitigate failure conditions. |
| US11094180B1 |
Sensing peripheral heuristic evidence, reinforcement, and engagement system
Systems and methods for identifying a condition associated with an individual in a home environment are provided. Sensors associated with the home environment detect data, which is captured and analyzed by a local or remote processor to identify the condition. In some instances, the sensors are configured to capture data indicative of electricity use by devices associated with the home environment, including, e.g., which devices are using electricity, what date/time electricity is used by each device, how long each device uses electricity, and/or the power source for the electricity used by each device. The processor analyzes the captured data to identify any abnormalities or anomalies, and, based upon any identified abnormalities or anomalies, the processor determines a condition (e.g., a medical condition) associated with an individual in the home environment. The processor generates and transmits a notification indicating the condition associated with the individual to a caregiver of the individual. |
| US11094179B2 |
Delivery management system, management server, delivery management method, and storage medium of program
A delivery management system includes: an authentication unit that authenticates a user; a storage unit that stores identification information on an article stored in a storage area that is a target article associated with the user; and a control unit that, when an article carried out by the authenticated user from the storage area is the same as the target article, permits the user to exit the storage area. |
| US11094176B2 |
State indicating devices and state indicating methods thereof
A state indicating device, which is adapted in an electronic device, includes a state detecting circuit, a controller, a driving circuit, and an LED device. The state detecting circuit is configured to detect an operation state of the electronic device to generate a detection signal. The controller generates a control signal according to the detection signal. The driving circuit generates a driving signal according to the control signal. The LED device displays an indication state according to the driving signal, in which the indication state is configured to indicate the operation state. |
| US11094172B2 |
Real time playing card valuation
Technologies and implementations for determining advantages in a card game via a video capture device are generally disclosed. |
| US11094167B2 |
Inspection system and inspection device
Provided is an inspection system capable of inspecting a plurality of gaming coins housed in a case in the state housed in the case. The inspection system (1) inspects the game chips (C) which incorporates the wireless tag storing the first game chip information and to which the optically readable second game chip information is added on the side. The inspection system (1) comprises a case (100) for stacking and storing a plurality of game chips (C) and an inspection device (200) for inspecting gaming coins (C) housed in the case (100). The inspection device (200) comprises an RFID reader (221) for reading the RFID tag (503) of the gaming chips (C) housed in the case (100) and acquiring the first gaming chip information; an infrared camera (225) and a visible light camera (226) for optically reading the side surface of the gaming chips (C) housed in the case (100) to obtain second gaming chip information; a determination unit (231) that determines whether the gaming chips (C) passes or not for each case (100) based on the acquired first gaming chip information and the acquired second gaming chip information. |
| US11094165B2 |
Gaming system, gaming device, and method providing one or more alternative wager propositions if a credit balance is less than a designated wager amount
Various embodiments of gaming systems, gaming devices, and methods of the present disclosure provide one or more alternative wagering propositions to a player when the player's credit balance is less than (or, in certain embodiments, less than or equal to) a designated wager amount. If the player accepts one of the alternative wager propositions, the player risks an amount of the player's remaining credit balance for a chance to win an alternative award. If the player wins the alternative award, the gaming system enables the player to play one or more plays of the wagering game at the designated wager amount. If the player does not win the alternative award, the gaming system reduces the player's credit balance by the amount risked. |
| US11094162B2 |
Methods and systems for interacting with a player using a gaming machine
A gaming system includes a frame, a gaming machine coupled to the frame, and an interactive device extending about at least a portion of a periphery of the frame. The gaming machine includes a presentation device configured to present a message associated with an interaction of a player with the gaming system. The interactive device is configured to detect the interaction of the player with the interactive device, and present feedback to the player based on the detection of the interaction of the player with the interactive device. |
| US11094160B2 |
Gaming system and a method of gaming
A gaming method and system, the method comprising providing one or more reels in a spinning reel game, the reels being displayed as three dimensional and displayed as provided with game symbols along and around the reels, displaying spinning of the reels and thereby sequentially displaying at least some of the game symbols displayed as provided along the reels, displaying rotating of the reels and thereby sequentially displaying at least some of the game symbols displayed as provided around the reels, stopping the spinning and the rotating of each of the reels at a respective stop position, and determining a game outcome based on at least some of the game symbols displayed when each of the reels is in its respective stop position. |
| US11094159B2 |
Storage container for a storage and delivery station for drugs
A storage container for a storage and delivery station for drugs is provided. The storage container includes a retainer for preventing a multiple drug portions from being delivered simultaneously. The storage container includes a housing that surrounds a receiving chamber and has a circular cylindrical section and a base surface, and a separating device disposed rotatably in the circular cylindrical section and having multiple projections and channels. Each projection has a surface, the uppermost points of the surface defining an upper receiver boundary plane. The storage container also includes a retainer with a fastening section and a retaining section, the retaining section preventing entry of the drug portions into a channel aligned with a delivery opening, and at least one cam for removing drug portions from the retaining section, the cam being movable above the upper receiver boundary plane over the retaining section. |
| US11094157B2 |
Card reader
In a card reader (1), if a shutter member (10), being located at a block position for blocking a card transfer path (3), rotates toward a deep side of the card reader, the shutter member moves to an open position. In a part within a surface of a side of the card transfer path in a thickness direction of the card (2), at a side deeper than the shutter member, there are formed only an open part (31) and an open part (32); the open part being for preventing an interference of the shutter member, rotating toward the open position, with the main body frame (4), as well as ejecting a foreign object out of the card transfer path; the open part being for preventing an interference of a movable component (21), placed so as to face the card transfer path, with the main body frame. |
| US11094156B2 |
Paper sheet processing device
A bill processing apparatus which is capable of reliably supplying information on a bill to the bill housing body side. The paper sheet processing apparatus has a bill housing part being capable of housing a bill inserted from a bill insertion slot, and also a reader/writer which wirelessly transmits information on the bill inserted from the bill insertion slot. The bill housing part has a coil antenna which wirelessly receives the information transmitted from the reader/writer, and a storage part which stores the information on the bill received from the coil antenna. |
| US11094155B2 |
Bill handling machine and bill handling method
The present invention makes it possible to restrain a bill from being taken out from a money withdrawal section during a transaction while the convenience of a conventional bill handling machine is maintained. The present invention is a bill handling machine to deposit and withdraw a bill with a customer over the counter, and the bill handling machine includes: a money deposit section having a money deposit opening to deposit a bill; a money withdrawal section arranged adjacently to the money deposit section and having a money withdrawal opening to withdraw a bill and a shutter to open and close the money withdrawal opening; and a control section to transport a reject bill to the money withdrawal opening. |
| US11094146B1 |
Intelligent electrical system for vehicle
An electrical system for a vehicle may include a main power supply and a power supply controller electrically connected to the main power supply and configured to selectively electrically connect the main power supply to, and disconnect the main power supply from, a vehicle subsystem. The electrical system may also include a supervisor power supply controller configured to receive signals indicative of an operational status of the vehicle, and determine, based at least in part on the signals, expected signals associated with operation of a plurality of vehicle subsystems. The supervisor power supply controller may also receive signals associated with operation of a vehicle subsystem, and determine that the signals associated with operation of the vehicle subsystem are indicative of a fault. The supervisor power supply controller may cause the power supply controller associated with the vehicle subsystem to disconnect the vehicle subsystem from the main power supply. |
| US11094142B2 |
On-line authorization in access environment
A method is disclosed. The method includes interacting with a gate access device that is capable of preventing access to a location, where the gate access device subsequently sends an authorization request message to an issuer for approval, the authorization request message including a request to charge a predetermined amount of money to pay for access to a location, and entering the location if the gate access device receives an authorization response message indicating that the charge is authorized. |
| US11094141B1 |
Method and apparatus for generating a composite 2D slice to enhance visualization
A 3D image processing system uses a three-dimensional dataset comprising voxels wherein said three-dimensional dataset is generated by performing imaging of a volume containing items. The image processing system performs segmentation of the three-dimensional dataset to generate segmented items. Each segmented item can be processed using a different image processing algorithm. For example, the skull can be processed using a first image processing algorithm (e.g., bone algorithm) and the brain can be processed using a second algorithm (e.g., soft tissue algorithm). A composite three-dimensional image is generated with the skull optimally displayed with the bone algorithm and the brain optimally displayed with the soft tissue algorithm. The composite images are displayed via 2D slice(s) to improve diagnosis. |
| US11094140B2 |
Systems and methods for generating and intelligently distributing forms of extended reality content
A system for facilitating cross-platform extended reality content sharing is configurable to receive a model file that includes a model, create a plurality of extended reality (XR) model or scene files based on the model file, create a universal link, and send the universal link to a developer system. Each of the plurality of XR model or scene files is formatted for rendering a representation of the model on a different, particular XR rendering platform included in a list of XR rendering platforms. The universal link is operable to configure an end user device to send a request for an XR model or scene file. The universal link points to an endpoint that comprises logic operable to determine, based on the request, a particular XR model or scene file that is formatted for rendering a representation of the model using an XR rendering platform associated with the end user device. |
| US11094139B2 |
Method and device to simulate, visualize and compare surface models
A method and device to simulate, visualize and compare 3D surfacesMethod and device to visualize a composition of two matched surface models (M1) and (M2) in order to privilege the visualization of the silhouette of the second representation (R2) of the second surface model (M2), that is, the surface elements which are the most tangent to the viewing direction defined by the optical center (C) of a virtual camera and the point (P) of the surface of the second surface model (M2) considered, and to visualize it by transparency on top of the first surface model (M1).The disclosure is intended in particular to compare anatomical subjects before and after simulation or surgical or aesthetic procedures. |
| US11094138B2 |
Systems for linking features in medical images to anatomical models and methods of operation thereof
A medical imaging system configured to link acquired images to markers or tags on an anatomical illustration, based, at least in part on spatial and anatomical data associated with the acquired image. The medical imaging system may be further configured to generate a diagnostic report including the anatomical illustration containing the markers. The diagnostic report may allow a user to select a marker to view information associated with an acquired image and/or the acquired image. Multiple images may be associated with a marker, and/or multiple markers may be associated with an image. A set of 2D and/or 3D anatomical illustrations may be generated which contains markers from multiple diagnostic reports and updated automatically for an individual patient's anatomical model by the application to reflect measurements and/quantitative findings related to organ, tissue, and vessel size, location, deformation, and/or obstruction. |
| US11094137B2 |
Employing three-dimensional (3D) data predicted from two-dimensional (2D) images using neural networks for 3D modeling applications and other applications
The disclosed subject matter is directed to employing machine learning models configured to predict 3D data from 2D images using deep learning techniques to derive 3D data for the 2D images. In some embodiments, a system is described comprising a memory that stores computer executable components, and a processor that executes the computer executable components stored in the memory. The computer executable components comprise a reception component configured to receive two-dimensional images, and a three-dimensional data derivation component configured to employ one or more three-dimensional data from two-dimensional data (3D-from-2D) neural network models to derive three-dimensional data for the two-dimensional images. |
| US11094135B1 |
Automated measurement of interior spaces through guided modeling of dimensions
Introduced here computer programs and associated computer-implemented techniques for establishing the dimensions of interior spaces. These computer programs are able to accomplish this by combining knowledge of these interior spaces with spatial information that is output by an augmented reality (AR) framework. Such an approach allows two-dimensional (2D) layouts to be seamlessly created through guided corner-to-corner measurement of interior spaces. |
| US11094131B2 |
Augmented reality apparatus and method
A method of providing an augmented reality image comprises recording a basic image including a subject and a first background using a recording device, extracting a subject image from the basic image, and providing the extracted subject image to a display device for combining with a second background. At A the sending person using the app to record a moving image of their own head—ie a video—which is separated from the background by the app (the background being automatically discarded). The image is then sent to a recipient who, at B, sees the head speak to them either on their desktop or in the camera view of the smart phone/tablet if they so choose. |
| US11094129B2 |
Wearable electronic glasses display instructions as virtual hand gestures
First wearable electronic glasses (WEG) capture an image of a real obiect and provide the image to second WEG. The second WEG capture hand gestures performing a task on the obiect, and the first WEG displays the hand gestures that show how to perform the task on the real obiect being displayed through the first WEG. |
| US11094124B1 |
Augmented reality pharmaceutical interface
Methods and systems may provide an augmented reality (AR) pharmaceutical interface to a client electronic device such as a mobile smartphone. The AR pharmaceutical interface may identify one or more prescription products (e.g., consumable products or medical devices) appearing in a field of view of a camera of the electronic device. Based upon the identified prescription product(s), the AR pharmaceutical interface may provide augmentations such as visual overlays, audial feedback, and/or other information associated with the identified prescription product(s). In some implementations, the AR pharmaceutical interface may facilitate other prescription-related functions, such as refills and/or transfers, by launching a dedicated prescription application at the electronic device. |
| US11094121B2 |
Mobile application for signage design solution using augmented reality
A method of generating an augmented reality (AR) signage solution including acquiring an image of a structure, establishing scaling information for the image by correlating dimensional information of the structure to points in the image, obtaining jurisdictional signage rules, designing a layout for signage on the structure in compliance with the jurisdictional signage rules, depicting in AR the acquired image and signage layout, and generating production documentation after obtaining user approval. The method including detecting the location of one or more obstructions on the structure and incorporating the obstruction locations in the signage layout. The method including adjusting the orientation of the acquired structure image within the AR to reduce skew of the structure in relation to a viewing perspective. A system and non-transitory computer-readable medium are also disclosed. |
| US11094116B2 |
System and method for automatic generation of a three-dimensional polygonal model with color mapping from a volume rendering
Systems and methods are provided for automatically generating a three-dimensional (3D) polygonal model with color mapping from a volume rendering. The method includes generating a volume rendering from volumetric data. The method includes receiving a user selection to launch model and color generation. The method includes automatically generating a 3D mask from the volume rendering by segmenting at least one object in the volume rendering in response to the user selection. The method includes automatically generating a 3D mesh for the at least one object based on the 3D mask in response to the user selection. The method includes automatically computing mesh colors based on the volume rendering in response to the user selection. The mesh colors are applied to the 3D mesh to generate a multi-color 3D polygonal model. The method includes automatically outputting the multi-color 3D polygonal model in response to the user selection. |
| US11094113B2 |
Systems and methods for modeling structures using point clouds derived from stereoscopic image pairs
A system for modeling a roof structure comprising an aerial imagery database and a processor in communication with the aerial imagery database. The aerial imagery database stores a plurality of stereoscopic image pairs and the processor selects at least one stereoscopic image pair among the plurality of stereoscopic image pairs and related metadata from the aerial imagery database based on a geospatial region of interest. The processor identifies a target image and a reference image from the at least one stereoscopic pair and calculates a disparity value for each pixel of the identified target image to generate a disparity map. The processor generates a three dimensional point cloud based on the disparity map, the identified target image and the identified reference image. The processor optionally generates a texture map indicative of a three-dimensional representation of the roof structure based on the generated three dimensional point cloud. |
| US11094110B2 |
Method, apparatus and electronic device for processing image
The application shows a method, an apparatus, and an electronic device for processing an image. The method includes: obtaining an image of a first rendering style; obtaining an image of a second rendering style according to the image of the first rendering style and a first preset processing model; generating at least one first intermediate gradient image according to the image of the first rendering style, the image of the second rendering style, and a second preset processing model, the at least one first intermediate gradient image comprising an image in a process of gradient from the image of the first rendering style to the image of the second rendering style; generating a first gradient video according to the image of the first rendering style, at least one first intermediate gradient image, and an image of the second rendering style. |
| US11094103B2 |
General purpose register and wave slot allocation in graphics processing
Example techniques are described for generating graphics content by obtaining texture operation instructions corresponding to a texture operation, in response to determining at least one of insufficient general purpose register space is available for the texture operation or insufficient wave slots are available for the texture operation, generating an indication that the texture operation corresponds to a deferred wave, executing the texture operation, sending, to a texture processor, initial texture sample instructions corresponding to the texture operation that was executed, and receiving texture mapped data corresponding to the initial texture sample instructions. |
| US11094100B1 |
Compound animation in content items
An online system presents a content item to users and receives selections of reaction icons from the users. The online system generates a background animation with the selected reaction icons and a foreground animation to be layered on top of the background animation. The online system sends the background and foreground animations to a client device to be cached. Further, the online system presents the content item to a viewing user associated with the client device and receives a selection of a reaction icon from the viewing user. The online system selects a subset of the users based on the viewing user's affinity to the users, retrieves images of the selected users, and send the images to the client device. The client device customizes the background and foreground animations based on the images and the viewing user's reaction icon to generate a compound animation for display to the viewing user. |
| US11094099B1 |
Enhanced hybrid animation
Systems and methods are described for applying a unifying visual effect, such as posterization, to all or most of the visual elements in a film. In one implementation, a posterization standard includes a line work standard, a color palette, a plurality of color blocks characterized by one or more hard edges, and a gradient transition associated with each of the hard edges. The visual elements, including live actors and set pieces, are prepared in accordance with the posterization standard. The actors are filmed performing live among the set pieces. The live-action segments can be composited with digital elements. The result is a combination of both real and stylized elements, captured simultaneously, to produce an enhanced hybrid of live action and animation. |
| US11094098B2 |
Method for creating an animation summarizing a design process of a three-dimensional object
A computer-implemented method for creating an animation summarizing a design process of a three-dimensional object, comprising the steps of: a) acquiring design data during at least one design session; b) automatically identifying time points of said session or sessions corresponding to milestones of the design process, and storing data representing statuses of the three-dimensional object at said milestones; and c) generating and displaying an animation of the design process, including displaying a graphical representation of a timeline (B) providing access to milestone data. A computer program product, non-transitory computer-readable data-storage medium and computer system for carrying out such a method. |
| US11094094B2 |
System and method for removing hard tissue in CT image
A system and method for CT image reconstruction are provided. The method may include: obtaining raw data set related to an object; generating a first image set based on the raw data set, wherein the first image set includes a first full quality image and a first max field of view image; generating one or more reference images based on the first max field of view image; generating a first bone information image based on the one or more reference images; generating a second image set based on the raw data set, wherein the second image set includes a second full quality image; generating a second bone information image based on the one or more reference images; correcting hardening beam artifact of the second full quality image based on the second bone information image to generate a hardening beam artifact corrected image. |
| US11094093B2 |
Color processing program, color processing method, color sense inspection system, output system, color vision correction image processing system, and color vision simulation image processing system
A computer is caused to execute processing of transforming a first color information indicating a first color in a first color space into a second color information in a second color space which is an opponent color space different from the first color space, according to a type of a color vision and a color vision strength indicating a degree of the color vision; calculating, in the second color space, a third color information having a predetermined color difference with respect to the transformed second color information; and transforming the calculated third color information into a fourth color information indicating a second color in the first color space, according to a type of a color vision and a color vision strength indicating a degree of the color vision. |
| US11094090B1 |
Compressive sensing based image capture using diffractive mask
Some embodiments provide a novel compressive-sensing image capture device and a method of using data captured by the compressive-sensing image capture device. The novel compressive-sensing image capture device includes an array of sensors for detecting electromagnetic radiation. Each sensor in the sensor array has an associated mask that blocks electromagnetic radiation from portions of the sensor. In some embodiments, a diffractive mask is used to direct incoming light from a same object to different sensors in a sensing array. Some embodiments of the invention provide a dynamic mask array. In some embodiments, a novel machine trained network is provided that processes image capture data captured by the compressive-sensing image capture device to predict solutions to problems. |
| US11094083B2 |
Utilizing a critical edge detection neural network and a geometric model to determine camera parameters from a single digital image
The present disclosure relates to systems, non-transitory computer-readable media, and methods for utilizing a critical edge detection neural network and a geometric model to determine camera parameters from a single digital image. In particular, in one or more embodiments, the disclosed systems can train and utilize a critical edge detection neural network to generate a vanishing edge map indicating vanishing lines from the digital image. The system can then utilize the vanishing edge map to more accurately and efficiently determine camera parameters by applying a geometric model to the vanishing edge map. Further, the system can generate ground truth vanishing line data from a set of training digital images for training the critical edge detection neural network. |
| US11094081B2 |
Searching virtual content information
For searching virtual content information, a processor searches the virtual content information including a virtual object contour. The processor further retrieves an image based on the virtual content information. |
| US11094079B2 |
Determining a pose of an object from RGB-D images
A system and method for detecting a pose of an object is described. An augmented reality display device accesses first sensor data from an image sensor and a depth sensor of the augmented reality display device. The first sensor data includes a first plurality of images of an object and corresponding depth data relative to the augmented reality display device and the object. The augmented reality display device detects first features corresponding to the object by applying a convolutional neural network to the first sensor data, forms a plurality of training clusters based on the first features, and stores the plurality of training clusters in a training database. |
| US11094077B2 |
System and process for mobile object tracking
Embodiments include system and processes for tracking objects using a camera. An optical marker dictionary including one or more optical markers is generated, the optical markers being optically distinct indicators. An optical marker within the optical marker dictionary is associated with and affixed to an object. A processor is in communication with the camera, receiving image data from the camera and applying computer vision to the image data in order to detect the presence of one or more optical markers within the optical marker dictionary within the image data. The processor determines camera position information and applies computer vision to the image data in order to determine relative position information for the detected optical markers and projects a position from the camera to a detected optical marker. |
| US11094069B2 |
Template based anatomical segmentation of medical images
A mechanism is provided in a data processing system comprising a processor and a memory, the memory comprising instructions executed by the processor to specifically configure the processor to implement a multi-atlas segmentation engine. An offline registration component performs registration of a plurality of atlases with a set of image templates to thereby generate and store, in a first registration storage device, a plurality of offline registrations. The atlases are annotated training medical images and the image templates are non-annotated medical images. The multi-atlas segmentation engine receives a target image. An image selection component selects a subset of image templates in the set of image templates based on the target image. An online registration component performs registration of the subset of image templates with the target image to generate a plurality of online registrations. The multi-atlas segmentation engine retrieves offline registrations corresponding to the subset of image templates from the first registration storage device. The multi-atlas segmentation engine performs segmentation of the target image based on the retrieved offline registrations corresponding to the subset of image templates and the plurality of online registrations. The segmentation applies labels to anatomical structures present in the target image based on the retrieved offline registrations and the plurality of online registrations to thereby output a modified target image. |
| US11094068B2 |
Image processing method and image processor
An image processing method is for detecting the edge of a well where cells are analyzed, from image data obtained by capturing the well and surroundings of the well, and an edge coordinate group for the well is extracted from the image data. If a plurality of edge coordinate groups has been extracted, edge candidates for the well are generated for each of the plurality of edge coordinate groups. Then, an edge candidate that satisfies a predetermined reference value is selected from among the generated edge candidates. If a plurality of edge candidates has been selected, relative evaluations are conducted to determine the edge of the analysis region from among the plurality of edge candidates. |
| US11094063B2 |
Brushing apparatus for physical anomaly detection
A method for monitoring and detecting physical anomalies may include receiving, by a processor and from a camera of a brushing apparatus, an image of a body from a predetermined distance away from the body. The method may further include detecting, by the processor, an atypical contour of the image that indicates a physical anomaly. The method may further include generating, by the processor, a notification in response to detecting the atypical contour that indicates the physical anomaly. |
| US11094061B1 |
Systems, methods, and devices for medical image analysis, diagnosis, risk stratification, decision making and/or disease tracking
The disclosure herein relates to systems, methods, and devices for medical image analysis, diagnosis, risk stratification, decision making and/or disease tracking. In some embodiments, the systems, devices, and methods described herein are configured to analyze non-invasive medical images of a subject to automatically and/or dynamically identify one or more features, such as plaque and vessels, and/or derive one or more quantified plaque parameters, such as radiodensity, radiodensity composition, volume, radiodensity heterogeneity, geometry, location, and/or the like. In some embodiments, the systems, devices, and methods described herein are further configured to generate one or more assessments of plaque-based diseases from raw medical images using one or more of the identified features and/or quantified parameters. |
| US11094060B1 |
Systems, methods, and devices for medical image analysis, diagnosis, risk stratification, decision making and/or disease tracking
The disclosure herein relates to systems, methods, and devices for medical image analysis, diagnosis, risk stratification, decision making and/or disease tracking. In some embodiments, the systems, devices, and methods described herein are configured to analyze non-invasive medical images of a subject to automatically and/or dynamically identify one or more features, such as plaque and vessels, and/or derive one or more quantified plaque parameters, such as radiodensity, radiodensity composition, volume, radiodensity heterogeneity, geometry, location, and/or the like. In some embodiments, the systems, devices, and methods described herein are further configured to generate one or more assessments of plaque-based diseases from raw medical images using one or more of the identified features and/or quantified parameters. |
| US11094052B2 |
Method of counting sheet materials
A method of counting sheet materials applied to a pile of sheet materials, comprising the steps of: receiving an image of the pile of sheet materials; obtaining a grayscale value of a plurality of pixels along a first image axis direction of the image to form an one dimensional first array; performing binarization of the first elements of the first array with a first threshold value to form an one dimensional second array; obtaining the number of the second elements of a first value appearing between two second elements of a second value in the second array to form a third array; dividing the elements of the third array into a first cluster and a second cluster with a second threshold value; counting the number of the third elements belonging to the first cluster and defining said number as the number of the first sheet materials. |
| US11094048B2 |
Image inspection device, image forming device, and computer-readable recording medium storing a program
An image inspection device which enables the user to know the cause of an abnormality in a read image. The image inspection device includes: an image reader outputting a read image generated by reading an image formed on a sheet of paper by an image forming device; an image inspection section inspecting the read image and outputting an inspection result which takes the read image determined not to have an abnormality as a normal image and the read image determined to have the abnormality as an abnormal image; an inspection result report generator generating an inspection result report according to the read image and the inspection result; an inspection result report output section outputting the inspection result report; and a controller performing control to cause the inspection result report output section to output the normal image and the abnormal image in a comparable manner. |
| US11094045B2 |
Systems and methods for image processing
According to aspects of the present disclosure, methods, systems, and media for processing an image are provided. A system may include at least one computer-readable storage medium including a set of instructions for processing an original image, and at least one processor in communication with the at least one computer-readable storage medium. When executing the set of instructions, the system is directed to obtain a first luminance image of the original image; decompose the first luminance image to provide a plurality of first decomposed images; adjust pixel frequencies in at least some of the plurality of first decomposed images to generate a plurality of second decomposed images; generate a second luminance image of the original image based on the plurality of second decomposed images; and determine a final image of the original image based on the first luminance image, the second luminance image, and the original image. |
| US11094041B2 |
Generation of bokeh images using adaptive focus range and layered scattering
A method includes determining, using at least one processor, a depth of range of focus for a scene. The method also includes determining, using the at least one processor, multiple layers associated with the scene based on the depth of focus range, where each layer is associated with image data having a different range of disparity values. The method further includes blending, using the at least one processor, the layers to produce an image having a Bokeh effect in a foreground and a background, and focused image data within the depth of focus range. The multiple layers include at least a first layer associated with the foreground, a second layer associated with the depth of focus range, and a third layer associated with the background. |
| US11094040B2 |
Noise detection method for time-series vegetation index derived from remote sensing images
A noise detection method for time-series vegetation index (TSVI) derived from remote sensing images. Firstly, unit root test is used to classify observation values of each pixel into a stationary series or a non-stationary series; for the non-stationary, an appropriate mathematical model is used to model discrete TSVI, then differences between actual observation values and prediction values of the model are calculated and recorded as a deviation. As the deviation has removed seasonal components, the non-stationary series is transformed into a stationary series. For a stationary series or deviation data, noise detection is performed based on the assumption that observation values are distributed within a certain range around mean values; then model fitting and noise detection are iteratively carried out with remained observation values—until the iterations reached the maximum number or no noise is detected at one iteration. The time series is then converted back to image space to obtain a noise mask and optimized. The present invention can obtain an accurate noise mask and improve reliability of land surface-related applications. |
| US11094034B2 |
Determining appropriate medical image processing pipeline based on machine learning
Mechanisms are provided to implement an automated medical image processing pipeline selection (MIPPS) system. The MIPPS system receives medical image data associated with a patient electronic medical record and analyzes the medical image data to extract evidence data comprising characteristics of one or more medical images in the medical image data indicative of a medical image processing pipeline to select for processing the one or more medical images. The evidence data is provided to a machine learning model of the MIPPS system which selects a medical image processing pipeline based on a machine learning based analysis of the evidence data. The selected medical image processing pipeline processes the medical image data to generate a results output. |