| Document | Document Title |
|---|---|
| US10264000B2 |
Malicious website access method and apparatus
A malicious website access method and apparatus are provided. The method includes: determining whether a website is a malicious website; and acquiring a non-executable preview interface of a web page of the malicious website for a terminal to display, if the website is a malicious website. A user may view, through a non-executable preview interface, information about a website to be accessed by the user. Moreover, because a terminal does not access a malicious website directly, the terminal is not exposed to malicious websites, thereby enhancing security of the terminal. |
| US10263998B1 |
Automated determination of relevance of a security alert to one or more other security alerts based on shared markers
A processing device in one embodiment comprises a processor coupled to a memory and is configured to obtain a plurality of security alerts in a computer network, to process the security alerts to extract a plurality of markers from each of the security alerts, to compute at least one relevance score relating a given one of the security alerts to another one of the security alerts based at least in part on distance measures computed between markers shared by the given security alert and the other security alert, and to adjust at least one operating characteristic of a network security system of the computer network based at least in part on the relevance score. The relevance score may be computed as a function of a number of markers shared by the given security alert and the other security alert. |
| US10263997B2 |
Data integrity verification
A system performs cryptographic operations utilizing information usable to verify validity of plaintext. To prevent providing information about a plaintext by providing the information usable to verify the validity of the plaintext, the system provides the information usable to verify validity of the plaintext to an entity on a condition that the entity is authorized to access the plaintext. The information usable to verify validity of the plaintext may be persisted in ciphertext along with the plaintext to enable the plaintext to be verified when decrypted. |
| US10263994B2 |
Authorized delegation of permissions
Systems and methods are described for delegating permissions to enable account access to entities not directly associated with the account. The systems determine a delegation profile associated with a secured account of at least one customer. The delegation profile includes a name, a validation policy that specifies principals which may be external to the account and which are permitted to assume the delegation profile, and an authorization policy that indicates the permitted actions within the account for those principals which are acting within the delegation profile. Once the delegation profile is created, it can be provided to external principals or services. These external principals or services can use the delegation profile to obtain credentials for performing various actions in the account using the credentials of the delegation profile. |
| US10263991B2 |
Remote profile security system
A method comprises storing, at the server computer system, user profile information for the remote user. The user profile information for the remote user (or a link to the user profile information) is encrypted using authentication information. The user profile information is associated with user identification information, at the server computer system, using the authentication information, which is selectively made available by the remote user via the network to the server computer system in order to enable the server computer system to associate the user profile information with the user identification information. |
| US10263990B2 |
Mode-based access control method and device
Provided is a mode-based access control method that includes: making a security mode list which indicates security setting states of devices existing in a home network; setting a specific security mode selected from the modes on the security mode list; and making the devices perform functions thereof in the specific security mode. Also, provided is a mode-based access control device includes: an authentication unit which checks information on a user and authenticates the user; a mode configuration unit which makes a security mode list indicating the security setting state of devices forming a home network; a mode setting unit which sets a specific security mode selected from modes on the security mode list; and an operating unit which causes the devices to perform functions thereof in the specific security mode. |
| US10263989B2 |
Method for matching multiple devices, and device and server system for enabling matching
The present invention relates to a method for matching multiple devices, and a device and a server system for enabling the matching thereof. A matching method includes receiving first characteristic information on a biological state of a user from a first device, receiving second characteristic information associated with or generated according to the biological state of the user from a second device, and matching the first device with the second device on the basis of the first characteristic information and the second characteristic information. The user is granted a permission for the first device when the first device authenticates the user on the basis of identification information of the user, and the user is granted the same or equivalent permission for the second device when the first device is matched with the second device. |
| US10263988B2 |
Protected container key management processors, methods, systems, and instructions
A processor of an aspect includes a decode unit to decode an instruction. The instruction to indicate a first structure in a protected container memory and to indicate a second structure in the protected container memory. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to determine whether a status indicator is configured to allow at least one key to be exchanged between the first and second structures, and is to exchange the at least one key between the first and second structures when the status indicator is configured to allow the at least one key to be exchanged between the first and second structures. |
| US10263977B2 |
Directory driven mailbox migrations
An example method for migrating communication data from a source server to a target server includes obtaining, using a computing device, a set of credentials to access the source server, and accessing the source server using the set of credentials. The method also includes requesting, automatically by the computing device, a directory structure associated with communication data from the source server, populating, by the computing device, the target server using the directory structure, requesting the communication data from the source server, and populating the target server with the communication data. |
| US10263974B2 |
Methods, apparatuses and computer program products for utilizing visual authentication tokens as cross-platform credentials
An apparatus is provided for facilitating cross-platform authentication. The apparatus may include at least one memory and at least one processor configured to detect that a visual token includes data indicating one or more authentication credentials for accessing a communication device in response to scanning the visual token. The computer program code may further cause the apparatus to communicate the authentication credentials of the detected visual token to the communication device to request the communication device to determine whether the authentication credentials are valid for a user. The computer program code may further cause the apparatus to enable access to the communication device in response to receiving an indication from the communication device that the authentication credentials of the detected visual token are valid. Corresponding computer program products and methods are also provided. |
| US10263970B1 |
System, method and architecture for secure sharing of customer intelligence
A key master service capable of operating on a service provider in a network enables is disclosed. The key master enables authorized parties to securely exchange client information without compromising client security. One feature of the key master service is the generation of a unique key for each client. All parties in an authorized universe access, exchange and modify client information by referencing the universal key, rather than using known client identifiers. Client information is further secured by advantageously applying an obfuscation function to the data. Obfuscated client information is stored together with the universal key as keyed client data at the client and/or server, where it may be directly accessed by the service provider or third parties. Because client information is stored and exchanged without the ability to discern either the client identity or the nature of the information, such information is secured against malicious third-party interception. |
| US10263969B2 |
Method and apparatus for authenticated key exchange using password and identity-based signature
Disclosed herein are an apparatus and method for authenticated key exchange using a password and an identity-based signature, by which robustness is provided in order to prevent a server impersonation attack when a password is exposed, and by which a client may be provided with convenient authentication using an ID and a password. |
| US10263964B2 |
Secure time-to-live
Determining whether to allow access to a message is disclosed. A message is received from a sender. The message is associated with a first time-to-live (TTL) value. A determination is made that the first time-to-live value has not been exceeded. The determination is made at least in part by obtaining an external master clock time. In response to the determination, access is allowed to the message. |
| US10263956B2 |
Physical level-based security system for data security of security terminal and method using the same
A physical level-based security system for data security of a security terminal and a method using the system. The security system includes at least one normal terminal corresponding to an external network, a security terminal corresponding to an internal network and storing sensitive data, and an interface device for transmitting input information of a user to any one of the at least one normal terminal and the security terminal, and providing unidirectional transmission service from the at least one normal terminal to the security terminal. |
| US10263954B2 |
Identifying the source and destination sites for a VoIP call with dynamic-IP address end points
In a voice-over-IP communications network, call data records include dynamically assigned IP signaling addresses such as IPv6 signaling addresses used in provisioning communications sessions. Those dynamically assigned IP signaling addresses are computed from customer site identification codes using a reversible algorithm. The algorithm can then be reversed to compute a customer site identification code from an IP signaling address contained in a call data record, allowing the communications network provider to perform quality monitoring and diagnostics based on call data records. |
| US10263953B2 |
Automated website generation via integrated domain registration, hosting provisioning, and website building
Methods of the present inventions allow for generating and providing an enhanced domain name. An exemplary method may comprise providing an enhanced domain to a second party. The enhanced domain may comprise a domain name, a web space automatically enabled and associated with the domain name, and at least one application automatically enabled and associated with the domain name. |
| US10263949B1 |
Determining and utilizing one or more attributes of IP addresses
Methods related to determining and utilizing one or more attributes to associate with an IP addresses. Attributes are determined based on request data provided with requests from an IP address and one or more available secondary information sources. Attributes may include physical locations and/or category designations for the IP address. One or more attributes may be assigned a likelihood value indicative of likelihood that the attribute is associated with the IP address. Some implementations are directed to utilizing the attributes and likelihood values to identify likely fraudulent information provided with requests. Some implementations are directed to utilizing the attributes and likelihood values to provide advertisements in response to requests from IP addresses. |
| US10263944B2 |
Location aware sticky notes
In one embodiment, a request to share a message is received from a first user. The request includes a first location, the message, and note-access criteria for sharing the message based on one or more groups of second users. A particular second user is identified having a second location that is within a threshold distance of the first location. Based on the note-access criteria and one or more groups associated with the particular second user, it is determined that the message should be shared with the particular second user, the message is sent to the particular second user, and a location of the first user is determined to be within a predetermined distance from the first location. If the first user is currently within the predetermined distance, a notification is sent to the first user informing the first user that the message was sent to the particular second user. |
| US10263943B2 |
Automatic relevance-based information inclusion in electronic communication
A system and method includes receiving, with a processor, an electronic communication from a user device associated with a sender of the electronic communication, the electronic communication being directed to a recipient member of an online social networking system. An entity is determined with which the sender is associated. Relevance scores of information to the entity and to the recipient are determined by comparing social network data regarding the recipient with the entity. At least some of the information is incorporated to the electronic communication based on the relevance scores of the information. A network interface transmits the electronic communication with the at least some of the information added to a user device associated with the recipient. |
| US10263939B1 |
Requesting additional content based on triggers
A social networking system receives information regarding an activity performed by a user of the social networking system. A determination is made as to whether an activity trigger is satisfied based on the received information. Responsive to a determination that the trigger is satisfied, additional content regarding the activity is requested from the user. |
| US10263938B2 |
Message processing method and apparatus
Embodiments of the present invention provide a message processing method and apparatus, and relate to the field of communications technologies. The method includes: comparing a message feature of a currently processed message with a specified tracking feature; determining a user corresponding to the message as a target user when determining that the message feature matches the tracking feature; and reporting a signaling message of the target user to a network management server. In the present invention, a network fault is quickly located, and network connection efficiency is improved. |
| US10263925B2 |
Method, device and medium for sending message
A method, a device and a medium for sending message are provided. The method includes: determining whether opposite terminal communication information of an opposite terminal user is acquired; generating a first friend-adding prompt according to the opposite terminal communication information if the opposite terminal communication information is acquired; sending local terminal communication information to the opposite terminal to enable the opposite terminal to generate a second friend-adding prompt according to the local terminal communication information, the second friend-adding prompt being used to prompt the opposite terminal user to add the local terminal user as a friend. |
| US10263923B2 |
Messaging system apparatuses circuits and methods of operation thereof
A method for managing a messaging system for receiving at a messaging server a message addressed, storing the message, transmitting a notification of the presence of the message at the messaging server, receiving a request to retrieve the message, validating the first mobile messaging client device, transmitting the message and a message attribute from the messaging server to the first mobile messaging client device, and receiving at the messaging server from the first mobile messaging client device a message management notification generated by the first mobile messaging client device in connection with managing the message in accordance with the message attribute at the first mobile messaging client device. |
| US10263919B1 |
Buffer assignment balancing in a network device
Techniques for more optimally balancing operations across a set of buffers, such as in buffering packets in a network device or in other contexts, are disclosed. The techniques make use of an ordered list of buffers from which the next available buffer is selected for each operation, as needed. The buffers are first prioritized based on the state(s) of the relevant buffers and/or other factors. The resulting ordered list is then processed using re-ordering logic. This re-ordering logic may, for example, randomly or pseudo-randomly trade the positions of various sets of buffers within the prioritized list. Among other effects, the re-ordering logic thus reduces buffer skew problems from delayed propagation of buffer state information and other issues. In an embodiment, the re-ordering logic is divided into multiple levels of processing, with each level separately passing through the list. Each level of processing may utilize differently configured re-ordering logic. |
| US10263918B2 |
Local fault tolerance for managing alternative networks for high quality of service communications
Methods and systems are provided. Exemplary methods may include: providing a first data packet to a first interface, the first data packet including a first address and being received from a computing device, the computing device being at a premises and coupled to a third interface, the first interface coupled to a first broadband connection received at the premises, the first broadband connection being coupled to a service using a first data network; determining at least one second data packet to be received at the first interface from the service is lost or delayed; supplying a second address to the computing device for communications with the service, in response to the determining; receiving from the computing device a third data packet including the second address; modifying the third data packet including replacing the second address with the first address; and giving the modified third data packet to a second interface. |
| US10263914B2 |
Method and system to speed up flow routing in SDN network
A method is executed by a network device in a network including a plurality of network devices. The network device implements a software defined networking (SDN) controller, where the SDN controller controls a first switch and a second switch in a network. The method improves packet processing performance in the network by reorganizing flow entries to decrease time to match active flows. The method includes receiving flow statistics for a first flow from the first switch, determining, based on the flow statistics for the first flow, that the first flow has a traffic usage that exceeds a pre-defined threshold, and in response to determining that the first flow has a traffic usage that exceeds the pre-defined threshold, programming the second switch to create a new flow table for processing the first flow or to increase a priority for matching a flow entry for the first flow within an existing flow table. |
| US10263912B2 |
Systems and methods for suspended playback
In an approach, a first application executing on a first computer acquires, one or more resources of the first computer, wherein the one or more resources include one or more shared resources that are shared among applications of the first computer. The first application receives a media stream from a second computer and presents playback of the media stream. In response to detecting that priority within the first computer has shifted to a second application, the first application pauses playback of the media stream and releases the one or more shared resources while retaining one or more remaining resources that relate to a session context. In response to detecting that priority has shifted back to the first application, the first application re-acquires the one or more shared resources and resumes playback of the media stream based on the one or more remaining resources. |
| US10263911B2 |
System and method for resource management
System and method for resource management are disclosed. These include receiving, by a virtualized network function (VNF) manger (VNFM) entity, from a network functions virtualization orchestrator (NFVO) entity a granting indication including a granting granularity in which the NFVO entity permits the VNFM entity to perform multiple VNF management operations for one or more VNFs, determining, by the VNFM entity, that a first VNF management operation is in a scope of permission based on the granting indication upon the first VNF management operation being triggered, and sending, by the VNFM entity, a first resource allocation request for the first VNF management operation to a virtual infrastructure manager (VIM) entity. |
| US10263909B2 |
System, method, and computer program for managing network bandwidth by an endpoint
A computer program embodied on a tangible computer readable medium includes computer code for identifying a plurality of incomplete tasks by a management server, computer code for determining by the management server, for each of the plurality of incomplete tasks, a priority associated with the task, computer code for determining by the management server an availability of network bandwidth, and computer code for managing, by the management server, the network bandwidth, based on the priority associated with each of the plurality of incomplete tasks and the availability of network bandwidth. |
| US10263908B1 |
Performance management for query processing
The processing of search queries for a customer using a set of resource can balance performance with cost, in order to ensure that the processing satisfies customer performance requirements while attempting to minimize the cost to the customer for obtaining that performance. In addition to dynamically updating the allocation of resources used to process the requests, such as to change the number or sizes of allocated resources, the number of indexes to be searched can be updated as well. For example, a search index can be divided into two sub-indexes against which queries can be executed concurrently in order to reduce the latency by about a half. Adjustments to the indexes and resources can be balanced to minimize cost while retaining performance, which can include rejoining sub-indexes or reducing the number of resource as appropriate. |
| US10263907B2 |
Managing virtual network ports
Managing virtual network ports on a physical server to provide a virtual server access to a group of storage resources through a network. A storage access group representing a group of storage resources is generated. A virtual server is generated on a hypervisor executed on the physical server. Access to the network is activated for the virtual server. A management console is provided for creating and managing the storage access group providing access to the group of storage resources for the virtual server from one or more physical servers. The management console includes a virtual server management facility and a storage access group facility. The virtual server management facility allows for managing virtual server definitions and activating, deactivating, and migrating virtual servers. The storage access group facility allows for managing virtual network port descriptions, administrating network port names, and creating, activating and deactivating virtual network ports. |
| US10263905B2 |
Distributed flexible scheduler for converged traffic
A distributed flexible scheduler that dynamically balances network and storage traffic across links is proposed. The scheduler takes into account the bandwidth requirements of workloads provisioned in a cluster and dynamically distributes the network traffic and the storage traffic accordingly. There are three schemes involved in the proposed distributed flexible scheduler. In a first approach of Equal Distribution, network and storage traffic is distributed evenly across the links. In a second approach of Storage Preferred distribution, the aggregate storage bandwidth requirements of workloads exceed the network bandwidth requirements. In a third approach of Network Preferred distribution, the aggregate network bandwidth requirements of workloads exceed the storage bandwidth requirements. |
| US10263904B2 |
Kind of self-adaptive network congestion control method based on SCPS-TP
A kind of self-adaptive network congestion control method based on SCPS-TP, which includes the following steps: The SCPS-TP's gateway source-end receives and transmits the packets to destination end; Judge if there is new packet received in accordance with the analyzed ACK; If there is no new packet received, when the duplicate ACK counter increase to a certain value, change the window size's growth pattern to linear self-adaptive pattern; If there is new packet received, the congestion control is in the exponential growth pattern. After window is enlarged, Diff is bigger than the set threshold value and the congestion control method is changed to linear self-adaptive pattern; If congestion control is in the linear self-adaptive pattern, adjust window size in accordance with Diff; The SCPS-TP's gateway source-end sends the packets in the packet loss buffer to destination end and sends new packets in accordance with the size of congestion window. |
| US10263899B2 |
Enhanced customer service for mobile carriers using real-time and historical mobile application and traffic or optimization data associated with mobile devices in a mobile network
Systems and methods of enhanced customer service for mobile carriers using real-time and historical mobile application and traffic or optimization data associated with mobile devices in a mobile network are disclosed. The data can be tracked by a client-side and/or a server-side reporting engine and usage analytics engine. Reports can also be generated by the system from the data and provided to the customer service/call center, such as trend charts showing optimization efficiency of traffic over a network and battery consumption vs. application load for a mobile device as a function of time. |
| US10263898B2 |
System and method for implementing universal cloud classification (UCC) as a service (UCCaaS)
Disclosed is a system and method of providing transport-level identification and isolation of container traffic. The method includes assigning, by a software-defined-network (SDN) controller in an SDN-enable cloud environment, a service-ID to a service, a tenant-ID to a tenant and/or workload-ID to yield universal cloud classification details, and extracting, from a data flow, the universal cloud classification details. The method includes receiving a policy, generating flow rules based on the policy and universal cloud classification details, and transmitting the flow rules to an openflow application to confine packet forwarding decisions for the data flow. |
| US10263894B2 |
Method and apparatus for network congestion control based on transmission rate gradients
A method and apparatus for congestion control for acknowledged communication over networks detects congestion based on trends of flight size and transmission rate in order to adapt a congestion window in accordance with a detection result. Such congestion detection enables, for example, distinguishing between the congestion with or without unfair competition. Moreover, the measured transmission rate or its trend can be filtered to compensate for time variations. An end node or a proxy can be used for congestion control. |
| US10263892B2 |
Compression method and system for user friendly address in mesh networking
A method for operating a mesh network is described. The method includes using a protocol comprising an address and a payload, wherein the address and payload are restricted. The method also includes using a hash function to generate an address from a description, wherein the description uses ASCII characters, wherein a message uses the description as an address and wherein the description is transformed into the address using the hash function and added together with the message into the payload, assigning the generated address to a device, wherein the device is part of a mesh network, and in a transmission from a source to the device, providing the generated address within the payload. |
| US10263876B2 |
Adaptive service timeouts
Disclosed are various embodiments for a timeout management application. Latency data for executing services is obtained. The used service capacity is calculated. If the service capacity is outside of a predefined range, the timeout of a selected service is reconfigured. |
| US10263875B2 |
Real-time processing capability based quality adaptation
The quality of a media stream transmitted to a client device is dynamically adapted based on real-time availability of resources on the client device. Central processing unit resources, memory availability, buffer usage, graphics processing unit usage, etc., are continuously monitored to evaluate the ability of a device to handle media streams of particular quality levels. When it is determined that resources at a client device temporarily can not handle a high quality media stream, a lower quality stream is selected and provided to the client device without having to establish a new session. |
| US10263873B2 |
Method and system for determining short-timescale traffic rates from time-stamped packet data
A method and system for determining short-timescale traffic rates from time stamped packet data is described. The method and system provides for the calculation of traffic rates, or bandwidths, in bits-per-second or packets-per-second over short time windows, using time-stamped packet records as input. |
| US10263871B2 |
Adverse event data capture and alert systems and methods
Electronic capture of adverse event information includes selective input of adverse event information into a machine in response to prompt provided to the user based on a site visit. Such adverse event information is forwardable to a location over a communication link. The machine produces one or more alerts, if adverse event information has been input, after a prescribed period of time has transpired unless the machine is informed that the same information has already been forwarded to the location. In a preferred embodiment, the customer is a clinician. Optionally, received adverse event information can be parsed to audit whether any of the information, in fact, concerns an adverse event. Systems and software concerning related technological improvements are disclosed. |
| US10263870B2 |
Suspending and resuming virtual machines in a network
A method is provided for suspending and resuming virtual machines in a network in dependence of network activity. The method includes providing a virtual machine manager. The virtual machine manager monitors network traffic of the virtual machines on a network bridge in a network layer using data packet analysis to detect dedicated network protocol traffic. More particularly, the monitoring of network traffic of the virtual machines may include: logging network addresses of the virtual machines of the network; combining logged network addresses with information about suspending or resuming virtual machines based on filtering rules being provided for such combination; and sending information about the network addresses of active and suspended virtual machines for virtual network adapters assigned to the virtual machines to the virtual machine manager. |
| US10263868B1 |
User-specific policy enforcement based on network traffic fingerprinting
A method for applying a user-specific policy in a network. The method includes identifying a historical portion of network traffic of the network as associated with a user, analyzing, by a computer processor, the historical portion of network traffic to generate a fingerprint of the user, wherein the fingerprint represents characteristics of user activity in the network, identifying, by the computer processor, an ongoing portion of network traffic of the network as associated with the user, analyzing, by the computer processor and based on the fingerprint, the ongoing portion of network traffic to determine a match, wherein the match is determined at a time point within the ongoing portion of network traffic, and applying, in response to determining the match, the user-specific policy to the ongoing portion of network traffic subsequent to the time point. |
| US10263863B2 |
Real-time configuration discovery and management
Embodiments are directed to monitoring network traffic in a network. A network monitoring engine may monitor networks to collect characteristics associated with network flows. The network monitoring engine may be arranged to identify entities on the network based on characteristics associated with the network flows. The network monitoring engine may provide entity profiles based on the identified entities and the characteristics. A configuration management engine may compare the entity profiles with configuration item (CI) entries in a database. The configuration management engine may provide discrepancy notices based on differences discovered during the comparison. Accordingly, the network monitoring engine may execute one or more policies to perform one or more additional actions based on the one or more discrepancies notices. Also, the configuration management engine may perform audits of an organization's information technology infrastructure to identify one or more violations of compliance policies. |
| US10263856B2 |
Dynamic highlight
Embodiments disclosed herein generally relate to techniques for providing a visualization of connectivity between components in a computer network. One embodiment provides a method which includes receiving a configuration of a network comprising a plurality of components within a physical layer and a virtual layer. The method also includes generating a resource diagram identifying connections that are accessible among the components of the physical layer and components of the virtual layer. The method further includes, upon receiving a selection of one of the components, determining a subset of the plurality of components that are connected to the selected component, and altering the resource diagram to provide a visualization, within the resource diagram, of the connections between the selected component and the determined subset of the plurality of components. |
| US10263853B2 |
Dynamic optimization of simulation resources
The present invention dynamically optimizes computing resources allocated to a simulation task while it is running. It satisfies application-imposed constraints and enables the simulation application performing the simulation task to resolve inter-instance (including inter-server) dependencies inherent in executing the simulation task in a parallel processing or other HPC environment. An intermediary server platform, between the user of the simulation task and the hardware providers on which the simulation task is executed, includes a cluster service that provisions computing resources on hardware provider platforms, an application service that configures the simulation application in accordance with application-imposed constraints, an application monitoring service that monitors execution of the simulation task for computing resource change indicators (including computing resource utilization and application-specific information extracted from output files generated by the simulation application) as well as restart files, and a computing resource evaluation engine that determines when a change in computing resources is warranted. |
| US10263849B2 |
System and method for generating discovery profiles for discovering components of computer networks
Generating discovery profiles for discovering components of a computer network using agent software can include receiving a command from a client device to generate a discovery profile for an agent software instance. A network subnet and at least one network gateway address can be obtained from the agent software instance, which network subnet and at least one network gateway address can be associated with a network interface of the computing device operating the agent software. At least one other network subnet can be obtained from the agent software instance by sending instructions to the agent software instance to identify the at least one other network subnet using the at least one network gateway address. A discovery profile including the network subnet and the at least one other network subnet can then be generated for the agent software instance. |
| US10263847B2 |
Policy validation
Some embodiments provide method for managing a set of computing resources. The method receives information for a set of resources. The information for each resource indicates a set of policies bound to the resource. The policies as bound to the resources are for application by several policy engines. For each of several of the resources, the method determines whether the policies bound to the resource violate a set of policy validation rules. For a subset of the resources for which a violation exists, the method disables at least one of the policies from being applied to the resource by the several policy engines. |
| US10263846B2 |
Device management apparatus, and device management system
A device management apparatus includes a reception unit configured to receive a setting value of a setting item to be set on one or more devices, the setting value being contained in first setting information representing a range of values settable on a first device among the devices; a conversion unit configured to convert the setting value, based on second setting information representing a range of values settable on a second device among the devices, and the first setting information; and an application request unit configured to request the second device to apply the setting value after being converted by the conversion unit, to the second device. |
| US10263841B1 |
System, method and apparatus for configuring a node in a sensor network
A system, method and apparatus for configuring a node in a sensor network. A sensor service can enable sensor applications to customize the collection and processing of sensor data from a monitoring location. In one embodiment, sensor applications can customize the operation of nodes in the sensor network via a sensor data control system. |
| US10263840B2 |
Subnet stretching via layer three communications
Systems and methods for stretching a subnet that do not require level 2 (L2) communications to be handled are provided. A user may gradually migrate VMs or applications instead of migrating an entire subnet at one time, may fail-over specific VMs without failing-over an entire subnet or renumbering IP addresses, may deploy applications to the cloud without the need to create a VPN, or may enable hybrid network connectivity without modifying routes or (re)configuring edge routers, among other benefits. The domains over which the subnet are stretched include a virtual gateway which is associated with the layer-3 (L3) addresses of the other domains. L3 communications within the domain are routed within that domain, and L3 communications within the subnet in another domain are intercepted by the local gateway, are passed to the remote gateway of the other domain, and are forwarded to the destination while leveraging L3 communications. |
| US10263838B2 |
Assigning resources to a workload that utilizes embedded computing entities
A method for managing the assignment of computing resources within a networked computing environment. The method includes a computer processor receiving, within the networked computing environment, a workload comprised of a plurality of objects that includes a first set of objects. The method further includes identifying a first embedded computing entity that is associated with the first set of objects. The method further includes deploying an instance of the first embedded computing entity to a first network accessible computing resource. The method further includes copying the first set of objects of the workload from one or more network accessible storage devices to the first network accessible computing resource that includes the deployed instance of the first embedded computing entity. The method further includes processing the workload based, at least in part, on executing the instance of the first embedded computing entity within the first network accessible computing resource. |
| US10263827B2 |
Information bridge between manufacturer server and monitoring device on a customer network
A monitoring device is in communication with a computer, including a memory, over a first network. The computer is further in communication with a server over a second network. A method for providing device information from the monitoring device to the server includes accessing a device web page stored on the monitoring device using a browser application operating on the computer. The monitoring device measures a utility characteristic and stores data indicative of the utility characteristic on a memory. The method further includes receiving a file from the monitoring device, including the device information. The device information includes at least device model information that identifies a model or type of the monitoring device. The method further includes storing the file in the memory of the computer, accessing a server web page stored on the server using the browser application operating on the computer, and transmitting the file to the server. |
| US10263826B1 |
Method of initiating execution of mainframe jobs from a virtual tape server
In one embodiment, a method can include notifying, from a mainframe, a virtual tape server that the mainframe is available to accept a job over a virtual tape channel. The method can also include, responsive to receiving at least one job data message of the job, sending, from the mainframe, a job receipt confirmation to the virtual tape server. |
| US10263825B2 |
Method and device for transmitting synchronization signal for D2D (device to device) communication in wireless communication system
The present invention relates to a method of detecting a synchronization signal for D2D (device to device) communication of a terminal in a wireless communication system. More particularly, the method includes detecting a first synchronization signal and a second synchronization signal on a specific sub-frame for a synchronization signal period set for D2D communication, wherein the first synchronization signal is generated based on a first of predefined sets of root indexes, the second synchronization signal is generated based on a second of predefined sets of root indexes, and the first set of root indexes and the second set of root indexes are made up of different indexes. |
| US10263824B2 |
Method and device for estimating frequency offset of reception signal
A method for estimating a frequency offset of a reception signal and, more particularly, a signal processing method which can be applied to a receiver modem in a wireless communication system, are provided. The method includes using an absolute value within a specific time area in an inverse discrete fourier transform (IDFT) output of a decorrelation signal between a reception signal and a reference signal, and enabling a highly approximate estimation of a frequency offset through only a single decorrelation test using a characteristic of a predetermined permutation of a signal. |
| US10263818B2 |
Integrity check techniques for multi-channel activity detection
Methods, systems, and devices for wireless communication are described. In some wireless communications systems, a wireless device may identify a set of at least two wireless communications channels that are available for communication with another wireless device. In some examples, the wireless device may identify at least one channel of the set, and may select integrity check information that indicates the identified wireless channel(s) that are available. The wireless device may then transmit the integrity check information during a first time period. In some examples, a wireless device may receive wireless communication that includes integrity check information on a subset of channels. The wireless device may then determine, based on the integrity check information, whether the identified subset of channels is the same as the actual subset of channels used for transmission of the wireless communications. |
| US10263812B2 |
Decision feedback equalizer for single-ended signals to reduce inter-symbol interference
The present invention is directed to communication systems and methods thereof. More specifically, an embodiment of the present invention includes a buffer that is coupled to a reference terminal. A shift register stores decision levels for post-cursor positions. A plurality of switches converts the decision levels to equalization currents during an equalization process. The equalization currents are converted to equalization voltage terms by one or more load resistors. The buffer is provided between the reference terminal and the one or more load resistors. There are other embodiments as well. |
| US10263807B2 |
Hierarchical statistics acceleration
A method for operating a network includes receiving, by a statistics engine of a network device, a channel identifier in connection with a statistic of an input frame. The channel identifier identifies a channel of a virtual network structure, and the input frame is received by the network device via the channel of the virtual network structure. The method further includes traversing, by a statistics engine and in response to the receiving the channel identifier in connection with the statistic, a hierarchical data structure based on the channel identifier. The hierarchical data structure comprises hierarchical statistic attributes of the virtual network structure. The method further includes selecting, by the statistics engine based on the traversing and from the hierarchical statistic attributes, linked statistic attributes that are linked to the channel identifier in the hierarchical data structure, incrementing, by the statistics engine based on the statistic, an existing value of each of the linked statistic attributes to generate an incremented value, and presenting, subsequent to the incrementing the existing value, the hierarchical statistic attributes. |
| US10263806B2 |
Network system of railcar
The present invention provides a network system of a railcar, the network system being capable of efficiently performing maintenance work. One example of the network system of the railcar of the present invention includes: intra-car networks (N1 to N3) to which first and second apparatuses are connected; an inter-car network (NA) for transmission of information between the apparatuses mounted on different cars; routers (R1 to R3) each provided and connected between the corresponding intra-car network (N1 to N3) and the inter-car network (NA) and each including a network address translation portion configured to mutually convert a private address of the first apparatus and an IP address of the inter-car network (NA); and a maintenance transmission path forming unit configured to form a transmission path through which the transmission and reception of the information are performed between a maintenance terminal (5) and a maintenance target apparatus selected from the first and second apparatuses, the transmission path not passing through the network address translation portion of the car on which the maintenance target apparatus is mounted. |
| US10263805B2 |
Directional wireless drop systems for broadband networks and related methods
Directional wireless drop systems are provided. These systems include a tap unit that is connected to a communications line of the broadband network; a cable modem unit connected to the tap unit; a plurality of wireless routers connected to the cable modem unit; and a directional antenna unit that is connected to at least a first of the wireless routers. Each wireless router is associated with a respective one of a plurality of subscriber premises that are served by the directional wireless drop system and is configured to communicate with at least one device that is located at the respective one of plurality of subscriber premises. |
| US10263804B2 |
Method for operating one or more service systems
A method for operating one or more service systems by an analyzing computer including a memory and a processor includes receiving one or more received control requests (RCR) for controlling one or more resources of one or more service systems and anticipating one or more future control requests (ACR) based on one or more of the RCR, one or more prior stored control requests, and/or one or more already served control requests (SCR). The method further includes assessing an impact of selected control requests (CR) on resources of the one or more service systems, wherein the selected CR include one or more of the RCR and/or one or more of the ACR. In addition, the method includes determining, by the AE, that an assessed impact of at least one of the selected CR results in one or more adverse situation rules (ASR) violations. |
| US10263803B2 |
System and method for providing network support services and premises gateway support infrastructure
A service management system communicates via wide area network with gateway devices located at respective user premises. The service management system remotely manages delivery of application services, which can be voice controlled, by a gateway, e.g. by selectively activating/deactivating service logic modules in the gateway. The service management system also may selectively provide secure communications and exchange of information among gateway devices and among associated endpoint devices. An exemplary service management system includes a router connected to the network and one or more computer platforms, for implementing management functions. Examples of the functions include a connection manager for controlling system communications with the gateway devices, an authentication manager for authenticating each gateway device and controlling the connection manager and a subscription manager for managing applications services and/or features offered by the gateway devices. A service manager, controlled by the subscription manager, distributes service specific configuration data to authenticated gateway devices. |
| US10263800B2 |
Method and device for receiving a multimedia broadcast multicast service in a mobile communication system
The present disclosure relates to a method and device for receiving a multimedia broadcast multicast service (MBMS) in a mobile communication system. The method for receiving the MBMS of a terminal in the mobile communication system according to an embodiment of the present disclosure is characterized in that it includes: determining whether service area ID (SAI) information on a serving cell is broadcast during the MBMS; receiving the SAI information on the serving cell when it is determined that the SAI information is broadcast; determining, by using the received SAI information of the serving cell, whether an SAI of the MBMS matches the SAI of the serving cell; and changing the cell reselection priority of the frequency of the serving cell to the highest priority if it is determined that the SAI of the MBMS matches the SAI of the serving cell. |
| US10263798B2 |
Validating hypertext transfer protocol messages for a toll-free data service
A device may receive network traffic. The device may determine that the network traffic includes a hypertext transfer protocol (HTTP) message. The device may determine, based on the HTTP message, that the network traffic is associated with a toll-free data service. The toll-free data service may cause a first party to be billed for data usage associated with the network traffic by a second party. The device may perform validation operations, based on validation information included in the HTTP message, to determine whether to provide the network traffic or drop the network traffic. The network traffic may be provided when the validation operations are successful, and may be dropped when the validation operations are unsuccessful. The device may cause the first party or the second party to be billed for the data usage based on the network traffic being associated with the toll-free data service. |
| US10263796B2 |
Systems and methods for managing power based on media asset consumption
Systems and methods are provided herein for managing, based on a portion of media asset consumed, power consumption of user equipment. A media guidance application may, upon determining that user inactivity time at a user equipment exceeds a threshold inactivity time, determine that a media asset currently being presented at the user equipment has not reached its end point. The media guidance application may then determine a playback duration for which the media asset has been presented. The media guidance application may, upon determining that the playback duration exceeds a threshold playback duration, continue monitoring user activity at the user equipment until the end point for the media asset is reached to determine an updated user inactivity time. The media guidance application may determine that the updated inactivity time exceeds the threshold inactivity time and in response, perform a power management process to reduce power consumption of the user equipment. |
| US10263791B2 |
Acceleration of online certificate status checking with an internet hinting service
Examples for acceleration of online certificate status checking with an Internet hinting service are disclosed. For example, one method includes receiving, by a computing device from a hinting server, hint information comprising certificate information; receiving, from a remote computing device, a certificate in response to a request to establish secure communications with the remote computing device; and determining a validity of the certificate based on the certificate information. |
| US10263789B1 |
Auto-generation of security certificate
A service provider network includes a certificate manager that auto-generates and auto-renews security certificates for customers of the provider network. The security certificates may be usable to implement a Secure Sockets Layer (SSL) protocol, or other types of security protocols. The certificate manager generates a public key, private key pair for the customer, generates the certificate signing request (CSR) on behalf of the customer, transmits the CSR to the certificate authority (CA), and binds the resulting CA-generated certificate and private key to whatever internet-facing service the customer chooses (e.g., a load balancer). |
| US10263788B2 |
Systems and methods for providing a man-in-the-middle proxy
A method for operating a secure man-in-the-middle proxy includes intercepting an attempt to establish a connection between an application and a network server associated with a whitelisted hostname, establishing a secure connection to the network server, checking the secure connection against the stored combination of certificate, encryption protocol, and encryption cipher for the whitelisted hostname, and forwarding traffic between the application and the network server at the whitelisted hostname if the secure connection matches the stored combination of certificate, encryption protocol, and encryption cipher for the whitelisted hostname. |
| US10263785B1 |
Cryptography method and system for securing data via electronic transmission
Securing information is increasingly difficult. With technological advances and tools/information sharing between hackers it is becoming even more difficult to ensure that sensitive data remains secure. Disclosed are systems and methods for uniquely securing data for each communication. The disclosed systems and methods allow for transmitting data across multiple boundaries (national, linguistic, operating system, platform, brand, etc.), while maintaining the desired security of the originator's data. |
| US10263773B2 |
Method for updating a public key
A method for updating a public key is provided. The method includes: acquiring, by a transmitting-end device, a first hash value calculated based on a first current public key; generating a first update public key and a first update private key; generating an update string such that a hash value of a hash function calculated based at least on the first update public key and the update string is equal to the first hash value; calculating, by a receiving-end device, a second hash value based at least on the first update public key and the update string according to the hash function; and verifying the first update public key by comparing the first hash value and the second hash value. |
| US10263770B2 |
Data protection in a storage system using external secrets
A system, method, and computer-readable storage medium for protecting a set of storage devices using a secret sharing scheme in combination with an external secret. An initial master secret is generated and then transformed into a final master secret using an external secret. A plurality of shares are generated from the initial master secret and distributed to the storage devices. The data of each storage device is encrypted with a device-specific key, and this key is encrypted using the final master secret. In order to read the data on a given storage device, the initial master secret reconstructed from a threshold number of shares and the external secret is retrieved. Next, the initial master secret is transformed into the final master secret using the external secret, and then the final master secret is used to decrypt the encrypted key of a given storage device. |
| US10263764B2 |
Auto-adaptive digital clock system and method for optimizing data communications
A method for optimizing data communications includes receiving a plurality of data and comparing a size of the plurality of data to a preset fixed data packet size. The method also includes transmitting the plurality of data within the preset fixed data packet size in response to the size of the plurality of data corresponding to the preset fixed data packet size. The method additionally include dynamically, autonomously adjusting a clock frequency for formatting data packets to format one or more data packets that accommodate the size of the plurality of data with minimal fill data in response to the size of the plurality of data being different from the preset fixed data packet size. The method further includes formatting the one or more data packets in response to dynamically, autonomously adjusting the clock frequency. |
| US10263762B2 |
Physical layer circuitry for multi-wire interface
The present invention provides pad arrangements, termination circuits, clock/data recovery circuits, and deserialization architecture for a physical layer circuitry including a four-signal or six-signal physical medium attachment sublayer (PMA). |
| US10263761B2 |
Clock and data recovery having shared clock generator
This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter. |
| US10263759B2 |
Signal presence detection circuit and method
In some embodiments, the circuits (and methods) may include a reference generator configured to generate a reference signal. The circuits (and methods) may also include a signal presence detection module configured to perform calibration on itself, during a calibration phase, based upon the reference signal. The signal presence detection module may be further configured to receive an input signal. The signal presence detection module may be further configured to perform detection, during a signal amplitude detection phase, of a state of the input signal. According to some embodiments, the circuits (and methods) may include a peak detector of the signal presence detection module shared by the calibration and the detection. In some embodiments of the circuits (and methods), the reference generator may be unpowered during the signal amplitude detection phase. The calibration and the detection may share the peak detector based upon time division multiplexing. |
| US10263757B2 |
Filter circuit and module
A filter circuit includes: a first transmission filter connected between a first antenna terminal and a first transmission terminal; a second transmission filter connected between the first antenna terminal and a second transmission terminal; a first reception filter connected between a second antenna terminal and a first reception terminal, the second antenna terminal being connected to an antenna different from an antenna to which the first antenna terminal is connected; and a second reception filter connected between the second antenna terminal and a second reception terminal. |
| US10263756B2 |
Asymmetric TDD in flexible use spectrum
A method according to an embodiment of the invention includes receiving and transmitting signals over a time division duplex (TDD) communication path. Signals are sent over the TDD communication path via a first portion and are received via a second portion of a first frequency band, wherein the first portion uses a smaller spectrum bandwidth than the second portion. The first frequency band is adjacent to a second frequency band and to a third frequency band. The second frequency band includes a first temporally-asymmetric TDD communication path having a third portion and a fourth portion. The third frequency band includes a second temporally-asymmetric TDD communication path having a fifth portion and a sixth portion. |
| US10263753B2 |
Sub-channel selection based on transmit power
In order to improve the quality of communication between electronic devices, one or more sub-channels used during communication between the electronic devices are dynamically modified based on one or more performance metrics and allowed transmit powers of the sub-channels. In particular, when the one or more performance metrics indicate that a distance between the electronic devices falls within a mid-range of distances, the one or more performance metrics may be used to guide selective changes to the sub-channels used during the communication based on the allowed transmit powers. The changes to the sub-channels used during the communication may increase, decrease or leave the total bandwidth unchanged. Moreover, by changing the sub-channels used during the communication, the allowed transmit power(s) of the sub-channel(s) used may be increased, which may improve the performance during the communication. |
| US10263748B2 |
Method and apparatus for transmitting uplink data and user equipment
A method and an apparatus for transmitting an uplink data and a user equipment is provided, the method includes: inserting multiple phase noise tracking reference signal (PT-RS) groups into a user data to be sent in time domain, according to a predefined interval; wherein each group of the phase noise tracking reference signal includes one or multiple PT-RS(s) of adjacent sampling points in the time domain; transforming the inserted multiple phase noise tracking reference signal groups together with the user data to be sent into frequency domain through a discrete Fourier transform (DFT) followed with a subcarrier mapping, and then with a transformation through an inverse fast Fourier transform (IFFT), to obtain an uplink DFT-S-OFDM waveform; and transmitting the uplink DFT-S-OFDM waveform. Embodiments of this disclosure may increase the accuracy of tracking the uplink phase noise and the possible system residual frequency shift and Doppler frequency shift, and may improve the system performance. |
| US10263745B2 |
Reciprocal channel sounding reference signal allocation and configuration
Systems and techniques are disclosed to enhance the efficiency of available bandwidth between UEs and base stations. A UE transmits a sounding reference signal to the base station, which characterizes the uplink channel based on the SRS received and, using reciprocity, applies the channel characterization for the downlink channel. The base station may form the beam to the UE based on the uplink channel information obtained from the SRS. As the downlink channel changes the base station needs updated information to maintain its beamforming, meaning it needs a new SRS. Transmission of the SRS takes resources; to minimize this, the UE or the base station can determine a period during which the downlink channel will predictably remain coherent and set up a schedule for sending SRS. Alternatively, the UE or the base station can determine on demand that the channel is losing coherence and initiate an on demand SRS. |
| US10263739B2 |
Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals
An apparatus for transmitting broadcast signals includes an encoder to encode service data, a mapper to map the encoded service data, and a time interleaver to interleave the mapped service data. The time interleaver includes a cell interleaver to interleave cells in a FEC block of the mapped service data, where the cell interleaver performs linearly writing the cells in the FEC block into a memory and randomly reading the cells in the FEC block according to a permutation sequence. The permutation sequence varies in every FEC block by using a shift value. The apparatus also includes a block interleaver to interleave the cell interleaved service data, where the block interleaver includes column-wise writing FEC blocks of the cell interleaved service data into a TI memory, and diagonal-wise reading the FEC blocks from the TI memory by skipping a part of cells included in the TI memory, and a convolutional interleaver to interleave the block interleaved service data. |
| US10263733B2 |
User apparatus and transmittal acknowledgement information transmission method
A user apparatus configured to communicate with a base station in a mobile communication system that supports carrier aggregation formed by a plurality of cells including a first cell and a second cell that uses a Transmission Time Interval (TTI) length different from a TTI length of the first cell, including a reception unit configured to receive downlink data transmitted from the base station in the second cell, and generate transmittal acknowledgement information for the downlink data; and a transmission unit configured to bundle a plurality of pieces of transmittal acknowledgement information, generated in the reception unit, for a plurality of pieces of downlink data into one piece of transmittal acknowledgement information to transmit the bundled transmittal acknowledgement information to the base station in the first cell. |
| US10263732B2 |
Self-describing error correction of consolidated media content
Presented herein are downstream recovery (error correction) techniques for an aggregated/consolidated media stream. In one example, a consolidated media stream that includes source media packets from one or more sources is sent to one or more downstream receiving devices. Based on the source media packets, one or more self-describing recovery packets for downstream error correction of the source media packets are generated. The self-describing recovery packets include a mapping to the source media packets used to generate the self-describing recovery packets, thereby avoiding the addition of error correction information in the consolidated media stream. The one or more self-describing recovery packets are sent to each of the downstream receiving devices as a separate stream. |
| US10263731B2 |
Transmitter and signal processing method thereof
A transmitter is provided, which includes: an encoder configured to generate a low density parity check (LDPC) codeword comprising information word bits, first parity bits and second parity bits based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a constellation mapper configured to map the interleaved LDPC codeword on constellation points, wherein the first parity bits are generated based on one of parity submatrices constituting the parity check matrix and the second parity bits are generated based on another of the parity submatrices constituting the parity check matrix. |
| US10263727B2 |
System and method for mitigating narrowband interference
A system and method for mitigating interference of a radio frequency (RF) signal includes a receiver configured to include: a decomposition module that decomposes a received RF signal into sub-bands via a multi-stage filter, each sub-band being configured to operate on real and imaginary components of the RF signal, and each stage being scaled for separating time-frequency content of the desired signal from time-frequency content of the interference; a mitigation module that suppresses the interference of the RF signal in each sub-band by zeroing an output of a respective sub-band when the frequency content exceeds a predetermined threshold; and a reconstruction module that reconstructs the RF signal from the mitigation module minus the interference. The receiver is configured to determine whether the multi-stage filter is to be reinitialized with updated time and frequency resolution requirements to improve system response. |
| US10263717B1 |
Method of synchronizing pause process and system of synchronizing pause process
A method for synchronizing a pause process during playback compress: delivering a pause release instruction, and a first period for which a first audio device is paused, simultaneously, the steps being performed by the first audio device. The method also comprises (i) receiving the pause release instruction, and the first period, and (ii) adjusting a playback of the audio data based on a difference between the first period and a second period for which a second audio device is paused, the steps being performed by the second audio device. |
| US10263713B2 |
Location of a source of passive intermodulation in a frequency selective device
A location is identified of at least one PIM (passive intermodulation) source in a frequency selective device by applying an excitation waveform to the frequency selective device and measuring a PIM response signature of the frequency selective device. The PIM response signature is a characteristic of PIM produced in response to the excitation waveform. The measured PIM response signature is compared with each of a plurality of example PIM response signatures, each of the plurality of example PIM response signatures corresponding to a characteristic of PIM expected for a respective location of a PIM source in the frequency selective device. The location of the at least one PIM source within the frequency selective device is determined on the basis of the comparison. |
| US10263712B2 |
Submarine optical cable shore landing apparatus
An optical communications apparatus includes a subsea cable, first and second landing stations, a splitter/combiner unit connected to an end of the subsea cable, and first and second legs connecting the splitter/combiner unit to the first and second landing stations, respectively. Each of the subsea cable and first and second legs includes an optical fiber configured to carry optical communications and an electrical conductor configured to carry electrical power. The splitter/combiner unit is configured to duplicate optical signals carried by the subsea cable in both the first and second legs. The first and second legs are configured to provide redundant electrical power connections to the subsea cable via the splitter/combiner unit. |
| US10263710B2 |
Electronic device associated with a photovoltaic module to optimise the throughput of a bidirectional VLC transmission
The invention relates to a bidirectional wireless communication device which is based on the use of light, including emitting modules, each emitting amplitude- and/or phase-modulated light; and a receiving module made up of: a photodetector illuminated by said modulated light and generating a modulated electrical signal in response to said modulated light; and a processing module for processing the signal generated by said photodetector. The receiving module includes an electronic means positioned between the photodetector and the signal-processing module and capable of matching the impedance of the photodetector to maximize the signal-to-noise ratio of the electrical signal by minimizing distortions of said electronic signal associated with incorrect impedance matching at the output of the photodetector, while maximizing the level of the modulated electrical signal and the throughput of transmitted data. |
| US10263707B2 |
Electro-optical modulator with differential bias control
Embodiments of the present disclosure are directed toward techniques and configurations for an apparatus comprising an electro-optical modulation device with a bias control and adjustment. In some embodiments, the apparatus may comprise an electro-optical modulator having first and second arms, to modulate light passing through the first and second arms in response to an input data signal, and output a corresponding optical data signal. The apparatus may further comprise a control module coupled with the electro-optical modulator, to differentially adjust respective phases of first or second light portions passing through the first and second arms, to achieve a bias point for the optical data signal. The bias point may define a desired power output of the apparatus that corresponds to the optical data signal. Other embodiments may be described and/or claimed. |
| US10263705B1 |
Multi-layer system capacity planning
A software-defined network multi-layer controller (SDN-MLC) may communicate with multiple layers of a telecommunication network. The SDN-MLC may have an optimization algorithm that helps in capacity planning of the telecommunications based on the management of multiple layers of the telecommunication network. |
| US10263703B2 |
Optical transceiver module for communications in DAS systems
The optical transceiver module installable on the Master Unit side of a DAS system connectable to a plurality of Remote Units, comprises an uplink connector and a downlink connector connectable to a radio base station, first and second optical connectors connectable to the Remote Units, a downlink path for the connection between the downlink connector and the first and second optical connector, and an uplink path for the connection between the uplink connector and the first and second optical connectors, wherein the uplink path comprises a first coupler of the WDM type and a second coupler of the WDM type connected, respectively, to the first optical connector and to the second optical connector, and wherein the uplink path comprises first and second demultiplexers connected, respectively, to the outputs of the first coupler and of the second coupler and adapted to separate the optical signals coming from the Remote Units. |
| US10263697B2 |
Method and apparatus for monitoring chromatic dispersion in optical communications network
The present disclosure discloses a method and an apparatus for monitoring chromatic dispersion in an optical communications network. The method includes: performing coherent mixing of a to-be-monitored signal with a first optical signal and a second optical signal to obtain two analog electrical signals, where center frequencies of the first optical signal and the second optical signal are located on two sides of a center frequency of the to-be-monitored signal, and a difference between the center frequencies of these two optical signals equals a Baud rate; converting the two analog electrical signals into two corresponding first time domain power signals; determining a value of a time delay between these two time domain power signals; and obtaining, according to a correspondence between the value of the time delay and the chromatic dispersion, the fiber chromatic dispersion generated in a process of transmitting the to-be-monitored signal. |
| US10263696B2 |
Monitoring a fiber optic cable for intrusion using a weighted algorithm
An optical fiber is monitored for changes in a monitor signal caused when the fiber is subjected to vibration, motion, or handling typical of an intrusion attempt and for triggering an alarm condition in response by one or more sensors. The sensor emits data on each disturbance event including the existence of the disturbance event and a value associated with the disturbance event dependent on an intensity of the disturbance. The arrangement herein provides an algorithm to analyze the disturbance events which calculates for each event a score dependent on the presence of the event and the value associated with the event, generates a summation of the scores in a FIFO and when the summation of the scores exceeds a predetermined threshold within a predetermined time period, the processor emits a signal triggering the alarm condition. |
| US10263693B2 |
Architecture of deployable feed cluster, compact antenna and satellite including such an architecture
A deployable feed cluster architecture comprises a support and an array of radiofrequency RF sources, each RF source comprising a radiofrequency RF chain and of a radiating element, the RF chain being provided with input/output ports. The architecture comprises a deployable panel that is rotatably articulated about an axis of rotation, the array of RF sources mounted on the panel, the panel being rotatably movable between a first position in which the array of RF sources is stowed on the support and a second position in which the array of RF sources is deployed. |
| US10263689B2 |
Transmission power control based on position of moving platform and prevailing emission restrictions
Apparatus for communications management in respect of a moving platform having a dynamic planner (40) configured to generate a communications plan utilising one or more of a plurality of communications planning strategies, at least one platform application (14, 16, 18, 20, FIG. 1), and a communications system (42) configured to effect wireless data communication of data received from a platform application by means of one or more supported communications links in accordance with said communications plan, wherein said apparatus comprises an interface function between said dynamic planner (40) and said communications system (42), said interface function including a communications executive module (141) and a communications management module (41), said communications executive module (141) being configured to receive, from said communications system (42), condition data representative of a prevailing situational and/or environmental condition affecting a current communications plan during mission execution, generate re-plan request data and transmit said re-plan request data to said communications management module (41); said communications management module (41) being configured to generate plan request data in response to said re-plan request data and transmit said plan request data to said dynamic planner (40), said plan request data being configured to cause said dynamic planner (40) to generate a revised communications plan and transmit said revised communications plan to said communications system (42), wherein said plan request data is generated by said communications management module (41) by selecting a strategy from said plurality of communications planning strategies, based at least on said condition data, and generating said plan request data including data representative of said selected strategy. |
| US10263684B2 |
Wireless system using different bands in the transmit and receive direction and applying frequency shifts for bandwidth expansion
A wireless access point is configured to communicate in millimeter wave frequency bands in the downlink direction and in sub-6 GHz frequency bands in the uplink direction. The wireless access point includes a signal processing circuit configured to generate different spatial streams signals and a frequency shift circuit configured to apply different frequency shifts to the different spatial streams signals. The wireless access point includes a mixer driven by a local oscillator, which up-converts the frequency shifted signals to millimeter wave frequency band signals, wherein the millimeter wave frequency band signals are transmitted by a MIMO transmit antenna array. A wireless communication device applies different frequency shifts to the different spatial streams signals after down-converting the signals received at a higher millimeter wave frequency to a lower frequency below 6 GHz. The wireless communication device applies no frequency-shifts to different spatial streams signals transmitted at lower frequency below 6 GHz. |
| US10263681B2 |
Method and apparatus for reporting periodic channel state information in mobile communication system using massive array antennas
The present disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. The present disclosure proposes a method and an apparatus for determining channel state information (CSI) to be reported according to a plurality of channel state reporting priority if periodic channel state information reporting collide with each other, and reporting the channel state information. |
| US10263677B2 |
Methods and systems for enabling feedback in wireless communication networks
Aspects of the present invention provide additional MAC functionality to support the PHY features of a wireless communication system framework. The additional MAC functionality aids in enabling feedback from wireless terminals to base stations. In some aspects of the invention the feedback is provided on an allocated feedback channel. In other aspects of the invention the feedback is provided by MAC protocol data units (PDU) in a header, mini-header, or subheader. The feedback may be transmitted from the wireless terminal to the base station autonomously by the wireless terminal or in response to an indication from the base station that feedback is requested. Aspects of the invention also provide for allocating feedback resources to form a dedicated feedback channel. One or more of these enhancements is included in a given implementation. Base stations and wireless terminals are also described upon which methods described herein can be implemented. |
| US10263672B2 |
Integer forcing scheme for multi-user MIMO communication
The present disclosure relates to a 5G or pre-5G communication system for supporting a higher data transmission rate successive to a 4G communication system such as LTE. The present disclosure provides a communication method of a Base Station (BS) using an Integer Forcing (IF) scheme in a Multi-User Multiple-Input and Multiple-Output (MU-MIMO) communication system, the method including: receiving a reception signal including a desired signal transmitted from at least one User Equipment (UE) served by the BS and an interference signal transmitted from at least one UE served by a neighboring BS; determining an IF filter considering the interference signal based on information on the interference signal received from the neighboring BS; filtering the reception signal using the determined IF filter; and detecting or decoding at least one of the desired signal and the interference signal using the filtered reception signal. |
| US10263668B2 |
Dual-band wireless headphones
Embodiments of wireless audio systems, wireless transceivers, and methods for wirelessly communicating audio information are disclosed herein. In one example, a wireless audio system includes a primary wireless transceiver and a secondary wireless transceiver. The primary wireless transceiver includes a first radio frequency (RF) module configured to receive, from an audio source, first audio information at a first frequency. The primary wireless transceiver further includes a second RF module configured to transmit second audio information at a second frequency lower than the first frequency. The second audio information is generated based on the first audio information. The secondary wireless transceiver includes a third RF module configured to receive, from the second RF module, the second audio information at the second frequency. The first RF module implements a first short-range wireless communication protocol. Each of the second and third RF modules implements a second short-range wireless communication protocol amended from the first short-range wireless communication protocol. |
| US10263657B2 |
Determining and controlling radiation absorption in a user terminal
An instantaneous value for the specific absorption rate of user terminal is determined, the instantaneous value is compared to a predetermined threshold; and the voice call and data transfer capabilities of the user terminal are controlled on the basis of the comparison and the call connection and data transfer status of the user terminal. |
| US10263649B2 |
Fully integrated power amplifier employing transformer combiner with enhanced back-off efficiency
A fully integrated power amplifier (PA) employing a transformer combiner with enhanced back-off efficiency includes a first PA to amplify a first radio frequency (RF) signal and a second PA to amplify a second RF signal. A first variable capacitor is coupled between differential output nodes of the first PA. A second variable capacitor is coupled between differential output nodes of the second PA. The differential outputs of the first PA and the second PA are coupled via respective first and second transformers to a load. Capacitance values associated with the first and second variable capacitors are dynamically adjustable based on an amplitude of the RF signal to achieve a desired power efficiency at an output power level. |
| US10263648B2 |
Low cost millimeter wave receiver and method for operating same
A low cost millimeter wave receiver and method for operating same is disclosed. In one embodiment, the method comprises receiving the first signal, converting the first signal of the first bandwidth into an intermediate frequency band, splitting the converted first signal into N of intermediate signals, each having a bandwidth less than the digital processor bandwidth, wherein N is an integer greater than one, downconverting each of the N intermediate signals to the second frequency band, processing the downconverted plurality of signals with the digital processor to generate N processed signals, upconverting each of the N processed signals to the intermediate frequency band, converting the upconverted signals to the third frequency band, and transmitting the converted signals. |
| US10263644B1 |
Hybrid architecture for LDPC channel coding in data center
Methods and systems are presented in this disclosure for implementing forward error correction in cloud and data center storage devices based on low-density parity-check (LDPC) channel coding. A forward error correction circuit presented herein includes a first LDPC decoder configured to perform hard-decision LDPC decoding of data read from a storage medium through a first read channel. The forward error correction circuit further includes a hybrid LDPC decoder selectively configurable to perform a selected one of hard-decision LDPC decoding and soft-decision LDPC decoding of data read from the storage medium through a second read channel, wherein, responsive to a control signal generated based, at least in part, on one or more parameters indicative of condition of the storage medium, the hybrid LDPC decoder is switchable between hard-decision LDPC decoding and soft-decision LDPC decoding. |
| US10263643B2 |
Method and system of multi-fold data protection for high-density storage appliance with improved availability and robustness
A first set of data is encoded using a first code to obtain a first-code codeword which includes the first set of data and first-code parity information. The first set of data is stored on a plurality of drives, wherein the first set of data is distributed amongst the plurality of drives. A second set of data is encoded using a second code to obtain a second-code codeword which includes the second set of data and second-code parity information. The second-code codeword is stored on the plurality of drives, wherein the second set of data and second-code parity information are distributed amongst the plurality of drives. |
| US10263640B2 |
Low density parity check (LDPC) decoder with pre-saturation compensation
Method and apparatus for decoding data. In some embodiments, an LDPC decoder has a variable node circuit (VNC) with a plurality of variable nodes configured to store bit reliability values of m-bit code bits. A check node circuit (CNC) has a plurality of check nodes configured to perform parity check operations upon n-bit messages from the VNC. Each n-bit message is formed from a combination of the bit reliability values and stored messages from the check nodes. A pre-saturation compensation circuit is configured to maintain a magnitude of each n-bit message received by the CNC below a saturation limit comprising the maximum value that can be expressed using p bits, with p less than n and each of the n-bit messages received by the CNC having a different magnitude. The pre-saturation compensation circuit may apply different scaling and/or bias factors to the n-bit messages over different decoding iterations. |
| US10263639B2 |
Managing soft information in high-capacity solid state drive
A technique for managing soft information decoding for a solid state drive (SSD) is disclosed. The technique includes performing soft decoding of data read from an SSD using at least some of a plurality of soft information tables and monitoring a set of one or more soft information properties associated with the plurality of soft information tables. The technique also includes adjusting the at least some of the plurality of soft information tables based at least in part on the set of the one or more soft information properties and repeating the soft decoding of data read from the SSD using at least the one or more adjusted soft information tables. |
| US10263638B2 |
Lossless compression method for graph traversal
To enable lossless compression, an auxiliary bitmap is used to provide side information about the graph bitmap. Each bit in the auxiliary bitmap represents a word in the graph bitmap. A zero bit in the auxiliary bitmap means that the corresponding word in the graph bitmap is not transmitted. Therefore, it is set to the default value, λ, during decompression. This default value could be either an all-zeros word, or all-ones word depending on the BFS step. A one bit in the auxiliary bitmap means that the corresponding word in the graph bitmap is transmitted. |
| US10263635B2 |
Method and apparatus for mitigation of outlier noise
Method and apparatus for nonlinear signal processing include mitigation of outlier noise in the process of analog-to-digital conversion and adaptive real-time signal conditioning, processing, analysis, quantification, comparison, and control. Methods, processes and apparatus for real-time measuring and analysis of variables include statistical analysis and generic measurement systems and processes which are not specially adapted for any specific variables, or to one particular environment. Methods and corresponding apparatus for mitigation of electromagnetic interference, for improving properties of electronic devices, and for improving and/or enabling coexistence of a plurality of electronic devices include post-processing analysis of measured variables and post-processing statistical analysis. |
| US10263632B2 |
Method and system for gain control for time-interleaved analog-to-digital convertor (ADC)
Methods and systems are provided for gain control during communications. A first electronic device may communicated data to a second electronic device; may monitor conditions and/or parameters affecting estimated reception performance at the second electronic device; and may communicated to the second electronic device, via a connection separate from and different than a connection used in communicating the data, information relating to the monitored conditions, to enable adjusting functions relating to reception of the data at the second electronic device. Based on the received information, at least one reception related function in the second electronic device may be controlled. The controlling may include determining, based on the received information, adjustments to the at least one reception related function or to a related parameter. The at least one reception related function may include applying gain to at least a portion of signals received by the second electronic device. |
| US10263625B1 |
TDC circuit and PLL circuit
A TDC circuit includes a plurality of delay elements connected in series. The TDC circuit includes a reference signal supply circuit that randomly selects one of the plurality of delay elements to supply a reference signal. The TDC circuit includes a plurality of latch circuits that latch a clock signal in response to outputs of the plurality of delay elements. The TDC circuit includes an output circuit that codes output signals output from the plurality of latch circuits and outputs a digital code indicating a relative time relationship of the clock signal with respect to the reference signal. |
| US10263621B2 |
Level shifter with improved voltage difference
A level shifter that comprises an input operating in an input voltage domain and an output for outputting an output signal in an output voltage domain. The level shifter further includes an inverter circuit operating in the input voltage domain for inverting an input signal to create an inverted input signal. The level shifter also includes an intermediate circuit operating in an intermediate voltage domain for generating an intermediate signal. An output buffer circuit generates the output signal based at least in part on the inverted input signal and the intermediate signal. |
| US10263619B1 |
Low leakage isolation cell
An isolation cell clamps a signal passing from a first, powered-down power domain to a second, power-on power domain. To reduce leakage current, some of the circuits and devices are connected to a voltage supply of the first or “from” power domain, while other circuits and devices are connected to a voltage supply of the second or “to” power domain. |
| US10263616B1 |
Radio frequency switch
A radio frequency switch having a first node, a second node, and a plurality of switch cells that are coupled in series between the first node and the second node is disclosed. Each of the plurality of switch cells is made up of a main field-effect transistor (FET) having a main drain terminal, a main source terminal, a main gate terminal, and a main body terminal. Further included is a first body bias FET having a first drain terminal coupled to the main gate terminal, a first gate terminal coupled to the main drain terminal, a first body terminal coupled to the main body terminal, and a first source terminal, and a second body bias FET having a second drain terminal coupled to the main gate terminal, a second body terminal coupled to the main body terminal, and a second source terminal coupled to the first source terminal. |
| US10263615B2 |
Circuit and method for driving a device through drive cycles
Methods and circuitry for driving a device through drive cycles wherein each drive cycle has a plurality of drive stages are disclosed. An example of the circuitry includes an output for coupling the circuitry to the device and a plurality of drive slices coupled in parallel to the output. Control circuitry selectively activates individual drive slices in the plurality of drive slices during each stage of a drive cycle. |
| US10263614B2 |
Systems and methods to switch radio frequency signals for greater isolation
In semiconductor switches, the isolation can be limited by the capacitive coupling between the switch input and the switch output. Ultra-high isolation can be achieved by adding a coupled transmission line to the semiconductor switch. The coupled transmission line introduces inductive coupling, which cancels at least a part of the capacitive coupling between the switch input and the switch output. |
| US10263613B2 |
Safety-oriented load switching device and method for operating a safety-oriented load switching device
A safety-oriented load switching device for the electric switching of an automation component, the device including a first branch circuit and a second branch circuit which extend from a respective supply-side supply connection to a respective load-side load connection, wherein a switching assembly including a parallel circuit of a switching means designed for an opening and a closing of the respective branch circuit and of a resistor means is formed in each branch circuit, and further including at least one measuring point located between the switching assembly and the load connection, and wherein a potential measuring device, which is electrically connected to a reference point and configured for providing a potential-dependent measuring signal, is connected to the measuring point. |
| US10263610B2 |
Control method and control circuit for switch circuit and switch circuit device
The present invention provides a control method and a control circuit for a switch circuit and a corresponding switch circuit device. The control circuit comprises: an acquiring module, configured to acquire first time; a comparing module, connected with the acquiring module and configured to compare first time with first fixed time; and an adjusting module, connected with the comparing module. The adjusting module adjusts a cycle of a turn-on signal of a first switch transistor to second fixed time when the first time is less than the first fixed time. The adjusting module adjusts the sum of second time and the first fixed time to the second fixed time to achieve spread spectrum when the first time is more than the first fixed time. The control circuit for the switch circuit provided by the present invention is used for controlling the switch circuit for spread spectrum. |
| US10263609B2 |
Oven controlled crystal oscillator device cover
A device cover for temperature control of a component device includes at least one heating element enclosed using the device cover, and multiple sections. Each section is located at a distinct location on the device cover and includes a reflection angle for the distinct location. The reflection angle is configured to reflect heat to the component device enclosed using the device cover, the heat originating from the at least one heating element. |
| US10263604B2 |
Triangular wave generator
A triangular wave generator includes a wave generator configured to generate a triangular wave according to a clock signal and a control signal. The triangular wave generator further includes a wave controller configured to adjust a value of the control signal in a correction mode. The control signal includes a first bias control signal, a second bias control signal, and a capacitance control signal. |
| US10263603B2 |
Method for managing the operation of a synchronous retention flip-flop circuit exhibiting an ultra-low leakage current, and corresponding circuit
The synchronous retention flip-flop circuit comprises a first circuit module suitable for being powered by an interruptible power source and a second circuit module suitable for being powered by a permanent power source. The first circuit module includes first and second latch stages, which are configured to store at least one datum while said interruptible power source is supplying power, transmitting means suitable for being controlled by a second control signal and configured to deliver said at least one datum to the second circuit module before an interruption of said interruptible power source, the second circuit module being configured to preserve said at least one datum during said interruption, and restoring means suitable for being controlled by a first control signal and configured to restore said at least one datum at the end of said interruption. Only the second control signal remains active during interruption of the interruptible power source. |
| US10263602B2 |
Surface acoustic wave filter with temperature sensor
Aspects of this disclosure relate to a surface acoustic wave filter with an integrated temperature sensor. The integrated temperature sensor can be a resistive thermal device configured as a reflective grating for a surface acoustic wave resonator, for example. A radio frequency system can provide over temperature protection by reducing a power level of a radio frequency signal provided to the surface acoustic wave filter responsive to an indication of temperature provided by the integrated temperature sensor satisfying a threshold. |
| US10263601B2 |
Tunable bulk acoustic resonator device with improved insertion loss
A tunable BAW filter device operating in an allocated channel of a predetermined frequency band includes a voltage source and multiple BAW resonators. The voltage source selectively provides non-zero DC bias voltage based on a location of the allocated channel within the frequency band. Each BAW resonator has a resonance frequency, and includes a bottom electrode, a piezoelectric layer and a top electrode disposed over the piezoelectric layer, the top electrode being electrically connected to the voltage source via a resistor. The voltage source is activated, applying the non-zero DC bias voltage to the top electrode of each BAW resonator, when the location of the allocated channel is near an upper or lower corner of the frequency band. The resonance frequency of each BAW resonator is shifted in response to the non-zero DC bias voltage toward a center of the frequency band, improving insertion loss of the BAW filter device. |
| US10263600B2 |
Band-pass filter and branching filter
A branching filter includes a first band-pass filter provided between a common port and a first signal port, and a second band-pass filter provided between the common port and a second signal port. The first band-pass filter includes a first LC resonant circuit and a first resonant circuit section provided in series. The first resonant circuit section includes a first acoustic wave resonator. The second band-pass filter includes a second LC resonant circuit and a second resonant circuit section provided in series. The second resonant circuit section includes a second acoustic wave resonator and an inductor connected in parallel. |
| US10263591B1 |
Device and method for reduction of electrical noise from pulsed signal devices
A device and method for reducing ground currents and electromagnetic interference in pulsed signal devices are described. In one embodiment, the device may include, in addition to regular filtering components and circuits, a separate noise-suppressing choke in the ground wire to reduce current in the ground wire that causes damage to bearings and electrical overstress. Such choke may be of a saturation type that offers high inductance and good noise-blocking properties in normal operating conditions and sufficiently low impedance at fail currents which provides proper tripping of safety circuits. |
| US10263590B2 |
Electronic component
An electronic component including a substrate, a capacitor lower electrode disposed on the substrate, an inorganic dielectric layer disposed on the substrate to cover the lower electrode, a capacitor upper electrode disposed directly on the inorganic dielectric layer and facing the lower electrode via the inorganic dielectric layer, and a coil disposed on the inorganic dielectric layer and electrically connected to the lower electrode or the upper electrode. |
| US10263589B2 |
Noise filter
A noise filter is provided with a filter circuit including a first condenser and a second condenser; the first condenser and the second condenser are connected in parallel with each other by a first wiring lead for connecting one terminal of the first condenser with one terminal of the second condenser and a second wiring lead for connecting the other terminal of the first condenser with the other terminal of the second condenser; the first wiring lead and the second wiring lead are arranged in such a way as to intersect each other odd-number times. |
| US10263584B1 |
Calibration of a dual-path pulse width modulation system
A system may include a digital pulse width modulator subsystem, a first path coupled to an output of the digital pulse width modulator subsystem, a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator, a controller to select between the first path and the second path for processing a signal based on one or more characteristics of the signal, wherein a first gain of the first path and a second gain of the second path are approximately equal at the time of switching selection between the first path and the second path or vice versa, in order to minimize artifacts due to the switching. |
| US10263582B1 |
Variable gain amplifier with gain-based compensation
The present disclosure describes variable gain amplifiers with gain-based compensation. In some embodiments, a variable gain amplifier (VGA) includes a gain stage, an output stage, a compensation stage, and a capacitor coupled between respective outputs of the gain stage and compensation stage. A gain of the VGA is configured, based on a gain setting, to amplify signals received by the variable gain amplifier. A gain of the compensation stage is configured, based on the gain setting, to alter an effective capacitance of the capacitor, which is applied to the output of the gain stage for compensation of the VGA. By altering the effective capacitance based on the gain setting of the VGA, compensation capacitance is adjusted continuously with changes in the gain setting and at a similar resolution. In various embodiments, the continuous adjustment of the compensation capacitance across different gain levels prevents discontinuities in amplifier compensation. |
| US10263580B2 |
Power supplying apparatus for neural activity recorder reducing common-mode signal applied to electrodes connected to the neural activity recorder
Disclosed is a differential voltage supplying apparatus configured to supply, to a neural activity recorder, an input signal generated by combining, with a direct current (DC) power supply, a common-mode signal determined from a voltage applied to a detection electrode and a reference electrode connected to the neural activity recorder, and improve a common-mode rejection ratio of the neural activity recorder and generate a DC power supply. |
| US10263574B2 |
Radio frequency receiver
A radio frequency receiver device comprises: a receiver input arranged to receive signals having one or more frequency components within a frequency spectrum; a filter having a filter output impedance; and an amplifier comprising: an amplifier input (134a, 134b) connected to the filter output; an amplifier output 72a, 72b); at least one radio frequency input transistor (144a, 144b); and a feedback circuit including at least one feedback resistor (146a, 146b). The device is arranged to be selectably operable in: a first mode wherein the amplifier has first feedback resistance and transconductance values respectively such that the amplifier input impedance and the filter output impedance are substantially the same; and a second mode having second feedback resistance and transconductance values such that upon connection of a predetermined external impedance matching circuit (160) between the filter and the amplifier, the amplifier input impedance and the filter output impedance are substantially the same. |
| US10263572B2 |
Radio frequency apparatus and method with dual variable impedance components
A radio frequency (RF) transmitter apparatus and method are provided with dual variable impedance components. Included is at least one RF transmitter with a power amplifier and a filter. Further, a first variable impedance component is in electrical communication between the filter and an antenna port. Also included is a second variable impedance component in electrical communication between the power amplifier and the filter. |
| US10263567B2 |
Amplifier circuit
An amplifier circuit includes a first transistor; a first resistor to which a first potential is applied, the first resistor being connected to an emitter of the first transistor; a second resistor to which a second potential is applied, the second resistor being connected to a collector of the first transistor; and a signal control circuit configured to apply, to a base of the first transistor, a voltage that has been level-shifted based on an average value of a voltage at the collector of the first transistor, the signal control circuit being provided between the collector and the base of the first transistor. |
| US10263559B2 |
Synchronous machine controller
When a failure of current detection parts occurs while a synchronous machine is operating, the failure of the current detection parts is detected and the operation of the synchronous machine is continued. An open-loop control part for performing control without using the detected current values of the current detection parts and a closed-loop control part for performing control using the detected current values are included, and a failure of the current detection parts is detected while the open-loop control part is operating. |
| US10263551B2 |
Method for controlling regulating device for regulating automotive vehicle alternator, corresponding regulating device and alternator
The method of control according to the invention slaves a DC voltage generated by the alternator to a predetermined setpoint value by controlling an excitation current flowing in an excitation circuit comprising an excitation winding of a rotor of the alternator. The excitation current is controlled by means of a semiconductor switch, in turn controlled by a control signal having a predetermined period. The method comprises a detection of a failure of the excitation circuit. At least one short-circuit of the excitation winding is detected. According to another characteristic of the method, the control signal is generated on the basis of a combination of a setpoint signal formed by pulses of the predetermined period exhibiting a duty ratio representative of the setpoint value and of a detection signal indicative of the short-circuit. |
| US10263549B2 |
Driving device with stepper motor
A driving device includes a case with a cover mounted thereto. A transmission device is received in the case and has a stepper motor and a gear reduction unit which includes multiple gears engaged with each other. The stepper motor drives the gear reduction unit which is connected to an object. A circuit board is connected with the transmission device and provides power to the stepper motor and controls the stepper motor. A sensing device has a sensor and a detector which is connected to one of the gears of the gear reduction unit. When the gear reduction unit drives the detector to pass the sensor, the sensor sends a signal to the circuit board which keeps on providing the power to the stepper motor. When no signal is sent to the circuit board by the sensor, the circuit board cuts off the power to the stepper motor. |
| US10263548B2 |
Method and system for feedback-controlling
Disclosed are a method and a system for feedback-controlling including controlling a current supply unit in a controller so that an output applied to a driving unit from the current supply unit is repeatedly turned on/off by predetermined period and duty. The method also includes feedback-controlling of an output value of the controller applied to the current supply unit from the controller so that the output of the current supply unit follows a target value. The feedback-controlling includes an integration control process and stops the integration control process in the period that the current supply unit turns off the output thereof. |
| US10263547B2 |
Permanent magnet motor control for electric subsea pump
A method includes monitoring electrical output in an open control loop from a variable speed drive to a remote permanent magnet motor, the variable speed drive electrically connected to the permanent magnet motor via a power transmission line. The method includes, in response to detecting a variation in the electrical output at the variable speed drive, synchronizing a frequency of a rotor shaft of the permanent magnet motor with a constant electromagnetic field frequency of a stator of the permanent magnet motor for a predetermined period of time. After the predetermined period of time, the method includes increasing the electromagnetic field frequency of the stator to an operational frequency threshold to accelerate the frequency of the rotor shaft of the permanent magnet motor. In response to reaching the operational frequency threshold, the method includes determining an internal position of the rotor based on the variable electromagnetic field frequency. |
| US10263543B2 |
Electric tool system
A power tool system includes a battery pack, a charger connectable to the battery pack, and a power tool body connectable to the battery pack. The battery pack includes a battery pack memory that stores identification information in a smallest unit allowing for communication with the charger and the power tool body. Each of the charger and the power tool body includes a device memory that stores at least one piece of identification information of a usable battery pack. Each of the charger and the power tool body or the battery pack includes a determination unit that determines whether or not the at least one piece of identification information stored in the device memory includes the identification information stored in the battery pack memory. |
| US10263542B2 |
Plate, transducer and methods for making and operating a transducer
A plate, a transducer, a method for making a transducer, and a method for operating a transducer are disclosed. An embodiment comprises a plate comprising a first material layer comprising a first stress, a second material layer arranged beneath the first material layer, the second material layer comprising a second stress, an opening arranged in the first material layer and the second material layer, and an extension extending into opening, wherein the extension comprises a portion of the first material layer and a portion of the second material layer, and wherein the extension is curved away from a top surface of the plate based on a difference in the first stress and the second stress. |
| US10263540B2 |
Suppression of a DC component in a transformer of a voltage converter
The present invention relates to a voltage converter comprising a primary side which has a full bridge device which is configured for the purpose of receiving a first DC voltage from a voltage source at a first amplitude and to transmit same to a primary coil arranged in the primary side, comprising a control unit which is designed for the purpose of controlling the full bridge device using PWM signals having phases shifted counter to one another, wherein the control unit is configured to detect an asymmetry in the current supplied to the primary coil based on a current profile in the primary coil, wherein the control unit is designed to compensate for a detected asymmetry by adjusting the PWM signals. The present invention further relates to a corresponding method. |
| US10263536B2 |
Apparatus and method for control of multi-inverter power converter
A control apparatus includes a control logic circuit that is configured to generate control signals for controlling at least two inverters (e.g., 3-phase inverters) that are coupled in parallel. The control logic circuit is configured to sample output currents present in common load terminals of the inverters, and to compare the sampled currents to generated current references. The output currents may be sampled, and/or the current references generated, at a fixed rate. Errors between the sampled currents and current references are evaluated against hysteresis dead bands around the current references. The control signals are generated based on (i) retrieved modulator output values for a selected one of the inverters and (ii) the errors as evaluated against the hysteresis dead bands. The control logic circuit may implement first and second counters for coordinating the current reference generation, sampling the output currents, retrieving the modulator output values, etc. |
| US10263535B2 |
Method and device for voltage balancing of DC bus capacitors of neutral-point clamped four-level inverter
A method and a device for voltage balancing of DC bus capacitors of an NPC four-level inverter are disclosed. The method includes: determining an optimal zero-sequence voltage, determining an actual reference voltage of each phase based on the optimal zero-sequence voltage; comparing respectively three preset carrier signals with the actual reference voltage of each phase to obtain three first control signals; determining three duty-cycle adjustment values based on a voltage of the intermediate bus capacitor; adjusting correspondingly the three first control signals based the three duty-cycle adjustment values to obtain three second control signals; inputting correspondingly the three second control signals to three first switches of an upper bridge corresponding to each phase; and inputting correspondingly complementary signals of the three second control signals to three second switches of a lower bridge corresponding to each phase. |
| US10263532B2 |
Multiple power sources for a switching power converter controller
An electronic system includes two power supplies to supply an operating voltage to a switching power converter. The first power supply, referred to as a start-up power supply, includes a first source follower transistor to conduct a start-up current for a controller and supply an operating voltage for the controller. The controller controls operation of the switching power converter. A second power supply, referred to as an auxiliary power supply, includes a second source follower transistor to conduct a steady-state operational current for the controller and supply an operating voltage for the controller. In at least one embodiment, once the second power supply begins supplying the operating voltage to the controller, the start-up power supply automatically ceases supplying the start-up current to the controller. |
| US10263527B1 |
Power converter
To provide a power converter not to stop a DC power conversion of the power converter, when there is no abnormality in the main circuit of the power converter, and the command signal of output voltage has an abnormality. A power conversion circuit is provided with a voltage command upper limit circuit that upper-limits the voltage signal which is inputted to the switching control circuit by a preliminarily set upper limit voltage, wherein the voltage command upper limit circuit is provided with a Zener diode or a shunt regulator, wherein the Zener diode or the shunt regulator upper-limits the voltage signal by an upper limit voltage corresponding to Zener voltage or shunt voltage, and wherein a voltage command represented by the upper limit voltage is set to a voltage less than the protection determination voltage of the output overvoltage protection circuit. |
| US10263524B2 |
Multi-phase parallel converter and controlling method therefor
A multi-phase parallel converter can include: sampling circuits corresponding to power stage circuits to form a plurality of phases of the multi-phase parallel converter, where each sampling circuit samples an inductor current of a corresponding power stage circuit, and generates a sense signal; a current-sharing circuit that generates a current-sharing control signal according to a superimposed signal that is generated by adding the sense signal to a bias voltage signal; switching control circuits corresponding to the power stage circuits, where each switching control circuit receives the current-sharing control signal, and controls a switching operation of a corresponding power stage circuit; and a bias voltage generator that generates the bias voltage signal to gradually increase/decrease when a selected phase is to be disabled/enabled. |
| US10263523B1 |
Programmable pulse time limit for switching DC-DC converters
A DC-DC converter with a programmable pulse time limit. A charge pulse begins when the output voltage reaches a minimum threshold and terminates in response to a discharge indication, in which charge current flows through an inductive element while the charge pulse is provided. The discharge indication is provided to initiate a discharge pulse when the charge current reaches a peak threshold, which terminates in response to a reset indication. Current is discharged from the inductive element during the discharge pulse. A zero crossing detector provides the reset indication when the discharge current reaches a minimum level. A programmable timing circuit limits a duration of either one or both of the charge pulse and the discharge pulse to prevent hangup or excessive output voltage ripple. The DC-DC converter may include a memory that stores a digital value used to program the programmed time duration of the programmable timing circuit. |
| US10263519B2 |
Resonant virtual supply booster for synchronous digital circuits having a predictable evaluate time
A booster for a digital circuit block provides speed and reliability at lower static power supply voltages, reducing overall power consumption of the circuits. The booster includes a transistor that couples a dynamic power supply node to a static power supply and is disabled in response to a boost clock. An inductor and capacitance, which may be the block power supply shunt capacitance, coupled to the dynamic power supply resonates so that the voltage of the dynamic power supply increases in magnitude to a value greater the static power supply voltage. A boost transistor is included in some embodiments to couple an edge of the clock to the dynamic power supply, increasing the voltage rise. Another aspect of the booster includes multiple boost transistors controlled by different boost clock phases so that the resonant boost circuit is successively stimulated to increase the amount of voltage rise. |
| US10263518B2 |
System and method for switched power supply with delay measurement
According to an embodiment, a method of operating a switching power supply includes applying a periodic switching signal to a first switch that is coupled to an output node, detecting an offset delay between applying the periodic switching signal and a change in voltage of the output node, calculating a corrected midpoint of a half phase of the periodic switching signal based on the offset delay, generating a sampling pulse based on the corrected midpoint, and sampling a current at the output node according to the sampling pulse. |
| US10263517B2 |
Voltage boosting circuit capable of modulating duty cycle automatically
The present invention relates to a voltage boosting circuit capable of modulating duty cycle automatically, which comprises an inductor, a switching module, and a control circuit. The inductor is coupled to an input for receiving an input power. The switching module is coupled among the inductor, a ground, and an output for switching so that the input power can charge the inductor and produce charged energy, or for switching so that the charged energy of the inductor can discharge to the output and produce an output voltage. The control circuit outputs at least a control signal according to the charged energy and the output voltage for controlling the switching module to switch the inductor and provide the input power to the output, to switch the charged energy of the inductor to discharge to the output, or to switch the input power to charge the inductor. |
| US10263506B2 |
Circuit arrangement and method for gate-controlled power semiconductor devices
A switch module includes a collector connection, an emitter connection, and a gate connection. The switch module includes a plurality of parallel connected switching elements, e.g., insulated-gate bipolar transistors, each having a collector electrode electrically connected to the collector connection, an emitter electrode electrically connected to the emitter connection, and a gate electrode electrically connected to the gate connection. A fault protection device is operatively electrically connected between the gate connection and the switching elements and comprises passive electrical components which are selected such that in the event of a fault in at least one of the plurality of switching elements, a gate-emitter voltage is provided to the gate electrodes of non-faulty switching elements in a passive manner. |
| US10263504B2 |
Synchronizing interval data despite loss of time
A meter mechanism and method are disclosed for recording relative interval data accumulated when the meter loses real time due to a power failure and synchronizing the relative interval data with real-time intervals in the meter memory. The disclosed meter mechanism and method ensure that all usage is accounted for while the meter is online, the metered usage is closer to the actual interval boundaries in which the usage occurred, accounts for all real time intervals in a day, and is power fail tolerant during both the analysis and synchronization. |
| US10263501B2 |
Vibration generator and electronic device having the same
A vibration generator including a coil, a plunger including a first shaft and a second shaft, and a frame. The first shaft is received in the coil such as to be movable in a first direction. The second shaft extends in a second direction orthogonal to the first direction, is disposed on the other side in the first direction relative to the coil with a gap therebetween. The first and second shafts are partly made of a magnetic material so as to be magnetically attractable to the coil and thereby movable to one side in the first direction. The frame is fixed to the first and second shafts at positions on the one and other sides, respectively, in the first direction relative to the coil, and elastically deformable at least partly as a result of movement of the first and second shafts. |
| US10263500B2 |
Electrical machine including a magnetic flux weakening apparatus
An electric machine includes a rotor having a magnetic field generating device for generating a magnetic flux. A flux changing apparatus of the electric machine includes an axially displaceable body that is disposed axially outside the magnetic field generating device for changing a magnetic flux within a gap between the rotor and a stator in dependence upon an axial position of the body relative to the rotor. The flux changing apparatus includes an adjusting device for axially adjusting the axial position of the body relative to the rotor. The adjusting device includes an actuator and an adjusting element. The actuator acts on the body via the adjusting element. The adjusting element engages the body and/or the actuator in such a manner that a rotational movement of the body can be decoupled from the adjusting element, a housing of the electric machine, the rotor and/or the actuator. |
| US10263499B2 |
Motor
A motor includes: a motor main body; a power board including a switching element and electrically connected to the motor main body; a control board electrically connected to the power board and disposed on an axial counter output side of the motor main body; a control board holder attached to the motor main body to hold the control board; a sensor magnet located on a counter output side of a stator and fixed to a shaft; a rotation sensor attached to the control board to face the sensor magnet; and a power board case directly or indirectly attached to the motor main body to hold the power board. The power board is positioned radially outward of the motor main body. Board surfaces of the power board are inclined with respect to board surfaces of the control board. |
| US10263498B2 |
Cooled stator winding with temperature detection element configuration for improved accuracy
A rotating electric machine includes a rotor, a stator, a temperature detecting element, and a cooling apparatus. The stator includes a stator core that is disposed so as to oppose the rotor in a radial direction of the rotating electric machine, and a stator winding that is wound around the stator core. The temperature detecting element is set in the stator winding. The cooling apparatus drips a liquid coolant onto coil end portions of the stator winding, thereby performing cooling. The stator winding has a plurality of input and output lines that are electrically connected to an external apparatus. At least one input or output line among the plurality of input and output lines is disposed vertically above the temperature detecting element. |
| US10263493B2 |
Vibratory sieving machine
In a vibratory sieving machine having two rotary shafts provided with eccentric spindles disposed parallel to each other, motors are disposed so as to reduce the capacity or power consumption of the motors required in the vibratory sieving machine, and to drive the two rotary shafts independently, and a rotary drive control mechanism is configured such that either one of the two rotary shafts can be started upon a start, while the other of the two rotary shafts can be started after a rotary drive state of the one of the two rotary shafts is transferred to a stationary state. |
| US10263490B2 |
Apparatus and method for fixing power line terminal in motor
An apparatus for fixing a power line terminal may include a terminal guide configured to be mounted at one end of a motor cover to support a motor coil terminal and to have an upper surface provided with a plurality of insertion grooves, and a plurality of insert nuts configured to be inserted into the plurality of insertion grooves, the insert nuts manufactured separate from the terminal guide. |
| US10263489B2 |
Motor housing and motor including same
The present invention provides a housing of a motor including a bearing pocket portion which is formed to protrude from an inner lower portion of the housing and in which an accommodation space of a bearing configured to support a shaft is formed and a shaft hole through which the shaft passes is formed in a bottom surface thereof, wherein the bearing pocket portion includes a stepped portion, the stepped portion protrudes upward along a circumference of the shaft hole, and an accommodation groove is formed between the stepped portion and an inner wall of the bearing pocket portion, thereby providing an advantageous effect of preventing foreign materials discharged from the housing of the motor, the wave washer, the bearing, and the like from exiting through the shaft hole. |
| US10263485B2 |
Alternator with integrated engine controller
An engine control system includes an engine, crankshaft, and a flywheel. The flywheel is coupled to the crankshaft of the engine and includes a number of magnets arranged axially along a first side. The system further includes a printed circuit board including a number of coils integrated into the circuit board. The printed circuit board is positioned such that a first face of the printed circuit board is positioned parallel to the first side of the flywheel. Power is generated by the flywheel rotating and causing the magnetic fields associated with the magnets to induce a current though the coils integrated into the printed circuit board. |
| US10263484B2 |
Stator of rotary electric machine
A stator for a rotary electric machine includes a stator core, three-phase coils, and a neutral point connection conductor. The three-phase coils are wound around the stator core. The neutral point connection conductor is connected to each of the three-phase coils. The neutral point connection conductor includes a linear conductor that is bent. The linear conductor includes two end portions and an overlapping portion in which the conductor is folded back and doubled up. One of the two end portions is connected to one-phase coil of the three-phase coils. The other of the two end portions is connected to another-phase coil of the three-phase coils. The overlapping portion is connected to the remaining-phase coil of the three-phase coils. |
| US10263483B2 |
Stator winding for a transverse flux machine and method for the production of a stator winding
The invention relates to a stator winding for a transversal flow machine, the stator winding (98) being embodied as a cord (244) and said cord (244) having a plurality of individual wires (242). Said stator winding (98) is embodied as a coil with several windings (245), characterized in that one or more windings (245) are layered in the axial direction or radial direction. |
| US10263482B2 |
Permanent magnet embedded-type rotating electric machine and manufacturing method thereof
Cracking and flying around of permanent magnets in a permanent magnet embedded-type rotating electric machine is prevented. Thermally hardening FRP is used as a reinforcement sheet, and the reinforcement sheet is wrapped around the periphery of a permanent magnet and caused to adhere to the surface of the permanent magnet by being thermally hardened. Subsequently, the permanent magnet to which the reinforcement sheet is adhering is embedded in magnet embedding holes of the rotor. The surface of the reinforcement sheet after thermal hardening is in a state of not being attached to the inner wall surface of the magnet embedding holes. Consequently, no stress caused by the difference between the linear expansion coefficients of the rotor and permanent magnets acts on the permanent magnets when the temperature of the rotor rises, and cracking of the permanent magnets can thus be prevented. |
| US10263481B2 |
Electric motor or generator
An electric motor or generator having a stator with stator teeth for mounting electrical coils and a rotor, wherein the stator has a first surface that is substantially perpendicular to an axis of rotation of the rotor and the rotor has a second surface that is formed in substantially the same radial position as the stator's first surface, wherein upon the rotor being pivoted perpendicular to the axis of rotation of the rotor the first surface and the second surface are arranged to prevent the rotor coming into contact with the stator teeth. |
| US10263480B2 |
Brushless electric motor/generator
Disclosed are various embodiments for a motor/generator comprising: a rotor adapted to rotate about a longitudinal axis, the rotor comprising a first partial toroidal magnetic cylinder defining a semi-circular tunnel, wherein the plurality of magnets forming the first partial toroidal magnetic cylinder have substantially all like poles facing inward toward the semi-circular tunnel, the semi-circular tunnel having an entrance and an exit forming an open throat defined by a space between the entrance and the exit, and a stator positioned about the longitudinal axis within a rotational path of the rotor. |
| US10263476B2 |
Transmitter board allowing for modular antenna configurations in wireless power transmission systems
A transmitter including a transmitter board comprising multiple electrical ports, each port configured to: receive any of a plurality of antenna boards, and provide electrical signals to a received antenna board. Each respective antenna board comprises antenna elements configured to transmit radio frequency (RF) power waves using the provided signal. The transmitter board further includes a processor configured to: determine whether antenna boards are connected to respective ports of the multiple electrical ports, and after determining that a respective antenna board has been received at a respective port: (i) instruct the transmitter board to provide, via the respective electrical port, electrical signals to the antenna board, and (ii) control transmission of RF waves by antenna elements of the respective antenna board to cause each of the RF waves to constructively interfere with at least one other RF wave at a receiver device located within a transmission field of the transmitter. |
| US10263472B2 |
Contactless power transfer system and power transmission device
A contactless power transfer system includes a power supply ECU configured to control an inverter to stop power transmission from a power transmission unit when a current generated in the power transmission unit exceeds a predetermined threshold value due to short-circuiting of a power reception coil. The power supply ECU estimates a coupling state between a power transmission coil and the power reception coil, and changes the predetermined threshold value in accordance with the estimated coupling state. |
| US10263471B2 |
Multiple interleaved coil structures for wireless power transfer
In one embodiment, a multiple interleaved coil structure for wireless power transfer includes a plurality of incomplete coils, each of the plurality of incomplete coils configured such that an alternating current flowing in the incomplete coil produces a magnetic field, and at least one interconnect between the plurality of incomplete coils, the at least one interconnect including a plurality of conductors arranged in such a way that the alternating current flowing in the plurality of conductors does not produce a magnetic field. Each of the plurality of incomplete coils includes a plurality of non-contiguous segments arranged in such a way that the incomplete coil will emit magnetic flux in response to an applied alternating current. The multiple interleaved coil structure can be implemented in a wireless power transmitter or a wireless power receiver. |
| US10263468B2 |
Apparatus for transmitting data and energy between two objects moving relative to one another
The invention relates to an apparatus for the transmission of data and energy between two objects moving relative to one another about a common axis of rotation. The objects each comprise coils which are disposed opposite and are spaced apart axially with respect to the axis of rotation such that an energy transmission between the coils is possible by inductive coupling. A respective electrode carrier having a respective electrical conductor is provided coaxially to and rotationally fixed with respect to the respective coils, wherein the electrode carriers are disposed opposite and spaced apart axially and the electrical conductors are arranged such that a data transmission between the electrical conductors is possible by electrical coupling. The electrical conductors are circular or part-circular and are concentric to the axis of rotation of the relative movement. In addition, the respective coil windings and electrical conductors are arranged concentric to one another. The respective coil carriers and electrode carriers are formed in one piece and as a respective circuit board. A respective arrangement of conductive material for shielding is provided between the first coil and the electrical conductor coaxial thereto and/or between the second coil and the electrical conductor coaxial thereto. The arrangement for the electrical shielding comprises bores in the circuit board in the radial region between the coil and the electrical conductor in which bores conductive material is located. The invention furthermore relates to a laser scanner having such a transmission apparatus in accordance with the invention. |
| US10263466B2 |
Magnetic field shaping for inductive power transfer
An IPT system magnetic flux device for generating or receiving a magnetic flux, has a magnetically permeable core and at least one coil magnetically associated with the core. A shield repels magnetic flux and is located on the opposite side of the core such that the shield includes an outer portion that extends beyond at least part of the perimeter of the core. |
| US10263465B2 |
Radiative wireless power transmission
A wireless power transmission system (100) includes a conductive waveguide (110) at least partially filled with a dielectric material (115), the waveguide extending along a first direction (e.g., z-axis) from a first end (111a) to an opposing end (111b) thereof, the waveguide having a bottom face (112), a top face (114) and a pair of side faces (116a, 116b) that together form a substantially rectangular cross-section of the waveguide, the top face having a plurality of slots (118) oriented substantially orthogonal to the first direction and distributed between the first end and the opposing end, the slots separated from each other by a first distance (l1) measured along the first direction. In one illustrative embodiment, the waveguide includes a plurality of barriers (120) interleaved with the plurality of slots, the barriers separated from each other by the first distance, each of the barriers extending between the top and bottom faces and having a barrier cross-section with an area smaller than an area of the waveguide cross-section and an input port (130) coupled with the first end of the waveguide, the input port configured to receive an input waveform (101) to be guided by the waveguide. |
| US10263462B2 |
Electrical system control using simulation-based setpoint determination, and related systems, apparatuses, and methods
The present disclosure is directed to systems and methods for controlling an electrical system using simulation-based setpoints. Some embodiments include control methods that enable recalculation of the optimal setpoints during demand windows. Some embodiments include a multi-mode controller to control an electrical system in a charge mode and a demand mode. Some embodiments include techniques for load and generation learning and prediction. Some embodiments include consideration of external data, such as weather. |
| US10263461B2 |
Smart DC microgrid parking structures using power line communications
A power system for a vehicle parking structure is disclosed. The power system comprises: a DC voltage bus arranged throughout the vehicle parking structure and configured to distribute DC power throughout the vehicle parking structure; at least one DC power source operably connected to the DC voltage bus and configured to provide DC power to the DC voltage bus; a plurality of DC loads arranged throughout the vehicle parking structure and operably connected to the DC voltage bus, the plurality of DC loads being configured to operate using DC power from the DC voltage bus; and a control system operably connected to the DC voltage bus and configured to communicate with at least one DC load in the plurality of DC loads using data signals transmitted via the DC voltage bus. |
| US10263458B2 |
Uninterruptible power supplies with control capabilities
A distributed low voltage power system can include a primary power source that distributes line voltage power during a first mode of operation and fails to distribute the line voltage power during a second mode of operation. The system can also include a secondary power supply coupled to the primary power source, where the secondary power supply includes a controller and an energy storage device. The system can further include a power distribution module (PDM) coupled to the primary power source and the secondary power supply, where the PDM includes a first power transfer device and a first output channel. The system can also include at least one first LV device coupled to the first output channel of the PDM, where the at least one first LV device operates using a reserve LV signal based on the reserve signal during the second mode of operation. |
| US10263456B1 |
Integrated three-port bidirectional DC-DC converter for renewable energy sources
A three-port bidirectional DC-DC converter for grid-interactive renewable energy source system applications. The three-phase topology is suitable for residential power requirements. The control of the backup battery system and the renewable energy source system are naturally decoupled. In addition, the port interface with the renewable energy is current type, which can implement maximum power point tracking (MPPT) and soft switching under wide variations in the renewable energy source terminal voltage. |
| US10263452B2 |
Wireless charging control method and apparatus in wireless power transmission system
The present disclosure provides a wireless charging control method. The wireless charging control method in an apparatus having a wireless power reception module, includes sensing an event in a wireless charging mode, determining whether the sensed event is a predetermined wireless-charging indirect-associated event, when the sensed event is a predetermined wireless-charging indirect-associated event, identifying a wireless charging operation corresponding to the wireless-charging indirect-associated event and controlling wireless charging according to the identified wireless charging operation. |
| US10263449B2 |
Battery charging systems and methods
A loudspeaker battery charging device comprises a three-position selector that establishes one of a first, second, or third charging mode for charging a battery of a loudspeaker. The first charging mode pertains to an off state of the loudspeaker. The second charging mode pertains to an on state of the loudspeaker. The third charging mode pertains to a fast charge state of the loudspeaker. A controller receives a signal from the three-position power switch indicating a selected charging mode of the first, second, or third charging mode. A switch circuit outputs a first power-supplying level in response to the first or second charging mode and outputs a second power-supplying level higher than the first power-supplying level in response to the third charging mode. |
| US10263448B2 |
Power storage system and method of controlling the same
A power storage system supplies electric power to a load, and includes: a secondary battery; a capacitor connected in parallel to the secondary battery; and a controller performing control to prioritize charging and discharging of the capacitor over charging and discharging of the secondary battery. |
| US10263443B2 |
Power capacity indicator
A wireless electronic device is provided which comprises a rechargeable power supply and a power capacity indicator unit. The power capacity indicator unit comprises one or more sensors configured to detect that the wireless electronic device is out of a base charger and is in an idle state for a predetermined idle threshold. The one or more sensors are further configured to detect when a power level of the rechargeable power supply is within at least one predetermined power threshold range. The control unit is configured to activate at least one power status indicator corresponding to the at least one predetermined power threshold range when the wireless electronic device is detected to be out of the base charger and in the idle state for the predetermined idle threshold, and the detection of the power level of the rechargeable power supply is within at least one predetermined power threshold range. |
| US10263439B2 |
Method and apparatus for protecting battery
Various example embodiments of the present disclosure disclose a method and an apparatus for protecting a battery in an electronic device. According to various example embodiments of the present disclosure, the electronic device includes: a battery configured to supply power to the electronic device; a timer configured to maintain time information of the electronic device; a thermistor configured to measure a temperature of the battery; and a processor electrically connected with the battery, the timer, and the thermistor, and the processor is configured to: determine a state of the battery when the electronic device is powered off; cause the electronic device to enter a suspend mode to protect the battery based on a result of the determining; be woken up by the timer in a sleep state accompanied by entering of the suspend mode, and acquire state information of the battery; and perform a function related to battery protection of the battery based on the acquired state information. |
| US10263438B2 |
Battery management system for vehicle
A battery management system for a vehicle is provided. The system is capable of preventing vehicle malfunction by preventing overcharge and over-discharge of a low-voltage battery by providing a controller that is configured to receive power transmitted from a first connection line and power transmitted from a second connection line. The battery management system includes a relay configured to electrically connect and disconnect power that is supplied from a battery to loads. The system also includes a controller configured to receive a first regular power transmitted through a connection line between the battery and the relay and a second regular power transmitted through a connection line between the relay and the loads. The controller is further configured to turn the relay on and off. |
| US10263437B1 |
Tabletop mobile device recharger
A tabletop mobile device recharging station is capable of simultaneously recharging a plurality of electronic devices including laptops, mobile phones, and tablets. A plurality of retractable power harnesses enable recharging through USB cables by transmission of a variable quantity of electrical energy following compliance with a predetermined condition, i.e., payment of a fee. The recharging station is also capable of wireless recharging and direct conversion of AC to appropriate levels of DC current to effect recharging. |
| US10263426B2 |
System stabilizing control device and method
A system stabilizing controller for estimating and controlling stability of a power grid includes a collection unit collecting grid information including a power flow amount from the power grid and a calculation unit calculating a generator shedding amount at a fault observation point on the basis of the grid information and estimating a correlation line on the basis of the power flow amount and generator shedding amount. The calculation unit determines a generator phase angle curve that is the relationship between the internal generator phase angle of a generator connected to the power grid and the power flow amount, determines a stability limit power flow amount on the basis of the amounts of generator acceleration energy and deceleration energy in the generator phase angle curve, determines a stability limit generator shedding amount corresponding to the stability limit power flow amount, and estimates a correlation line including a stability limit point. |
| US10263425B2 |
Power transmission network
A power transmission network including a single-phase or multi-phase AC electrical system, a converter including an AC terminal, a point of common coupling, a phase reactance connecting the common coupling to each AC terminal, and a transmission medium to interconnect the common coupling and the electrical system. The network includes a controller to: process the voltage and current at the common coupling to compute a state vector; derive a converter demand by combining the state vector with control parameters, including the capacitance of the power transmission medium presented at the common coupling and the impedance of the phase reactance; and operate the converter according to demand controlling the voltage at each terminal and/or the common coupling to inhibit any perturbation in the converter voltage from a target converter voltage or range resulting from the interaction between the capacitance of the power transmission medium and the impedance of the phase reactance. |
| US10263423B2 |
Method for controlling an electrical installation from a remote location
A method for controlling an electrical installation from a remote control station is provided, the installation including a coupling network powering one or more electrical loads, a main switch to connect a main power source to the network, and an auxiliary switch to connect an auxiliary power source to the network, the method including synchronizing the auxiliary power source with the main power source including a phase of measuring electric data relative to the main power source and to the auxiliary power source and a verification phase, from the remote station, to ensure that the measured data relative to the main and auxiliary power sources is compatible; sending an order to close the auxiliary switch from the remote control station; sending an order to open the main switch from the remote station; and checking, from the remote station, that the loads are correctly powered by the auxiliary power source. |
| US10263422B2 |
Shutdown controlling method for power system
A shutdown controlling method is applied to a system that has a host computer, a PDU and multiple electric apparatus connected to the PDU. The PDU has multiple outlets and stores preset shutdown periods for the outlets respectively. The PDU communicates with the electric apparatus and obtains their required shutdown periods. When PDU is controlled to cut off an outlet, the PDU determines whether the preset shutdown period of the outlet is larger than the required shutdown period. If yes, the PDU cuts out the AC power of the outlet. If not, the PDU cancels the shutdown command and notifies the host computer. Therefore, a manager may update the preset shutdown period of the outlet to ensure that each electric apparatus has enough time to be safely shut down. |
| US10263420B2 |
Bi-directional snapback ESD protection circuit
An ESD protection circuit having a discharging transistor and a body snatching circuit. The discharging transistor is electrically coupled between a first node and a second node. The gate and the body of the discharging transistor are electrically coupled together. The body snatching circuit receives the voltages at the first and second nodes and outputs either the voltage at the first node or the voltage at the second node based on which of these two voltages have a lower value. The output voltage of the body snatching circuit is provided to the body of the discharging transistor. |
| US10263419B2 |
Transient voltage protection circuits, devices, and methods
A transient voltage protection circuit includes a first input/output pad, a second input/output pad, and a trigger circuit coupled between the first input/output pad and the second input/output pad. The trigger circuit includes a first trigger element which includes a first input/output node, a second input/output node, a third input/output node, and a first substrate diode coupled to the third input/output node of the first trigger element. The trigger circuit further includes a first resistor coupled between the first input/output node of the first trigger element and the second input/output node of the first trigger element. The trigger circuit further includes a second trigger element which includes a first input/output node, a second input/output node, a third input/output node, wherein the second input/output node of the first trigger element is coupled to the first input/output node of the second trigger element, and a second substrate diode coupled to the third input/output node of the second trigger element. The trigger circuit further includes a second resistor coupled between the first input/output node of the second trigger element and the second input/output node of the second trigger element. |
| US10263417B2 |
Transient voltage suppressing integrated circuit
A transient voltage suppressing (TVS) integrated circuit includes an input output pin, a ground pin, a substrate, a first TVS die and a second TVS die. The substrate provides a common bus. The first TVS die is disposed on the substrate, and includes a first input output terminal and a first reference ground terminal. The second TVS die is disposed on the substrate and includes a second input output terminal and a second reference ground terminal. The second reference ground terminal is electrically coupled to the first reference ground terminal through the common bus, and the first input output terminal is coupled to the first input out pin, and the second input output terminal is coupled to a ground pin. |
| US10263416B2 |
Overvoltage protection apparatus and method
An overvoltage protection apparatus and method. The overvoltage protection apparatus includes: a determining unit, having an input end connected to an input end of the apparatus and an output end connected to an input end of a soft-start unit, and configured to determine whether an input voltage at the input end of the apparatus exceeds a preset protection voltage; and the soft-start unit, having an input end connected to the input end of the apparatus and an output end connected to an output end of the apparatus, where if the determining unit determines that the input voltage does not exceed the preset protection voltage and remains stable in a preset delay time, the soft-start unit delivers the input voltage to the output end of the apparatus; and otherwise, the soft-start unit does not deliver a voltage signal to the output end of the apparatus. |
| US10263411B2 |
Electronic fuse system and a method therefore
The disclosure relates to an electronic fuse system, and to a method for an electronic fuse system. The method comprises determining (201) if the number of engaged electronic circuit breaker modules (108) has changed compared to the stored configuration. Upon determining that the number of engaged electronic circuit breaker modules (108) has changed, determining (202) if the configuration of the electronic fuse system has changed by means of comparing a stored configuration in the power distribution controller (105) and a stored configuration in the electronic circuit breaker module (108). Upon determining that the configuration of the electronic fuse system has changed, determining (203) if a stored configuration is available from the bus (101). Upon determining (203) that a stored configuration is available from the bus, fetch (204) the stored configuration from the bus and start operation of the electronic fuse system according to the fetched configuration. Upon determining (203) that a stored configuration is not available from the bus, determining (205) if a stored configuration is available from the connectable external main processor. Upon determining (205) that a stored configuration is available from the connectable external main processor, fetch (206) the configuration from the connectable external main processor and start operation of the electronic fuse system according to the fetched configuration. Upon determining (205) that a stored configuration is not available from the connectable external main processor, start operation of the electronic fuse system according to a default configuration (207). |
| US10263409B2 |
Cable connecting assembly
A cable connecting assembly includes a tubular member, a securing member, a seal unit, and a hollow barrel member that defines an accommodating space. The tubular member is disposed in the accommodating space and has two annular grooves. The securing member has a coupling portion abutting against the tubular member and threadedly engaging the barrel member, and an abutment portion abutting against the barrel member. The seal unit includes two first seal rings respectively disposed in the annular grooves and sealingly contacting an inner surface of the barrel member, and a second seal ring sleeved on the coupling portion of the securing member and sealingly contacting the inner surface of the barrel member and the abutment portion of the securing member. |
| US10263407B1 |
Electric vehicle inverter module laminated bus bar
A laminated bus bar of an inverter module to power an electric vehicle is provided. The laminated bus bar can include a first insulating layer and a current layer disposed over the first insulting layer. The current layer can include an output terminal. The laminated bus bar can include a second insulating layer disposed over the current layer. The laminated bus bar can include a third insulating layer disposed over the second insulating layer. The laminated bus bar can include a first polarity (e.g., negative) layer disposed over the third insulating layer. The first polarity layer can include a first polarity (e.g., negative) input terminal. The laminated bus bar can include a fourth insulating layer disposed over the first polarity layer. The laminated bus bar can include a second polarity (e.g., positive) layer disposed over the fourth insulating layer and that includes a second polarity (e.g., positive) input terminal. |
| US10263402B2 |
Conductor cover applicator
Methods and applicators for applying tubular conductor cover to a cable. The applicator may retain a user's hand. The applicators may stop a user's hand from moving relative to the applicator in a direction opposed to a path of conductor cover passage through the applicator. An applicator for applying a tubular conductor cover to a cable, the conductor cover being split longitudinally to define a first longitudinal edge and a second longitudinal edge, the applicator comprising: a separator shaped to contact, in operation of the applicator, an interior surface of the conductor cover to spread open the first longitudinal edge and the second longitudinal edge along a portion of the conductor cover to allow the portion of the conductor cover to be applied to a cable; and a hand retainer connected to or forming part of the separator. A method of applying tubular conductor cover to a cable, the conductor cover being split longitudinally to define a first longitudinal edge and a second longitudinal edge, the method comprising: positioning a hand in a hand retainer connected to or forming part of a separator; spreading open the first longitudinal edge and the second longitudinal edge of a portion of the conductor cover with a separator, the separator contacting an interior surface of the conductor cover; and applying a length of conductor cover to the cable through the separator. |
| US10263401B2 |
Pressure tank, gas insulated switchgear using same, and pressure tank manufacturing method
To obtain a pressure tank that achieves a high manufacturing efficiency and does not hamper storage of an open/close portion such as a vacuum valve in a pressure tank. A pressure tank of the present invention includes: a tank body having at least one penetrating slit-shaped mortise and having a space formed inside the tank body; a reinforcing member having a tenon portion formed at an end thereof so as to be directed in one direction, and having an electric field relaxation portion on a side opposite to the tenon portion, the reinforcing member being attached to an inner wall surface of the tank body with the tenon portion inserted into the mortise; and a welding portion sealing and fixing the mortise and the tenon portion with no gap therebetween, the welding portion being formed by melting an end of the tenon portion from outside of the tank body. |
| US10263398B2 |
Direct-current distribution panel and migration device
A DC distribution panel unit and a migration device are stored in a DC distribution panel. The migration device and the DC distribution panel unit are configured to be compatible with each other in terms of a structure and a position of connection to a power supply of the DC distribution panel, a structure and a position of connection to loads, and a fixation position of fixation to the panel. The migration device and the DC distribution panel unit are replaceable with each other. |
| US10263385B1 |
Wavelength locker
An apparatus and method for calculating the frequency of the light. |
| US10263383B2 |
Gain fiber for high power lasers and amplifiers
An optical gain fiber for use in high power (e.g., greater than 500 W pump power) is proposed that is configured to exhibit a minimum bend radius such that the bend loss for the propagating LP01 mode is greater than about 0.03 dB/m. It has been discovered that this bend radius criteria, which is less stringent than that typically suggested in the art (e.g., bend loss less than about 0.03 dB/m), meets the modal stability requirements at high power operation, since the increase in operating temperature of the fiber laser or amplifier has been found to somewhat relax the bend radius requirement (which was heretofore only measured at “room temperature”, not “operating temperature”). Modal stability is defined in terms of a reduced presence of unwanted higher-order modes (such as the LP11 mode) in the amplified output signal. |
| US10263381B2 |
Sealed corrosion-resistant contacts
Contacts and connector assemblies that may be space efficient, provide direct connections to flexible circuit boards, provide corrosion resistance, prevent moisture leakage into an electronic device housing the connector assembly, are readily assembled, and have an aesthetically pleasing appearance. |
| US10263376B1 |
Connector cleaner
A connector cleaner having an elongate portion of material extending from a first end portion to a second end portion; a first paddle element extending from the first end portion, and wherein at least a portion of a first side surface of the first paddle element includes an abrasive element or portion; a second paddle element extending from the first end portion, wherein at least a portion of a first side surface of the second paddle element includes an abrasive element or portion, and wherein the first side surface of the first paddle element is positioned adjacent the first side surface of the second paddle element; and a singular paddle element extending from the second end portion of the elongate portion of material, and wherein at least a portion of a first side surface of the singular paddle element includes an abrasive element or portion. |
| US10263372B2 |
Electrical connector having insulative housing with a rear stepped portion assisting in formation of a waterproof sheet
An electrical connector includes: an insulative housing comprising a base portion defining a rearward surface and a tongue portion extending forwardly from the base portion; plural conductive terminals affixed to the insulative housing and each having a contacting portion exposed to the top and bottom surfaces of the tongue portion, a fixing portion embedded in the base portion, and a soldering portion extending backwardly out of the base portion; a shielding plate affixed to the insulative housing; a shielding shell covering the insulative housing and defining a sol space with the rearward surface of the base portion; and a waterproof sheet; wherein the base portion further comprises a stepped portion in the sol space, the waterproof sheet is formed by solidification of liquid insulative material flowing from the stepped portion to the rearward surface, and the waterproof sheet encloses the stepped portion. |
| US10263362B2 |
Fluidically sealed enclosure for window electrical connections
According to aspects of the present disclosure, a method of environmentally sealing an electrical joint formed between an electrical connection element and an electrical conductor disposed on a transparent pane is described. The method includes adhering a mechanically protective enclosure to the transparent pane to define an internal volume therebetween and filling at least a portion of the internal volume with a sealing material that inhibits ingress of liquid into the volume and provides a fluidic environmental barrier about the electrical joint. The electrical joint is disposed within the internal volume and spaced from the enclosure. |
| US10263361B1 |
Transition fitting for photovoltaic installations
A transition fitting for achieving a rain-tight transition at the entry of photovoltaic cables with EMT. The transition fitting includes a fitting body with an internal bore, a grommet seated within the bore, a nut for tightening the grommet against the fitting body, a compression fitting and a ground lug extending from the nut. A plurality of bores extend partially through the grommet. Photovoltaic (PV) cables may be inserted within one or more of the bores in the grommet and the nut tightened upon the fitting body to form a rain-tight fit around the PV cables. The skins of the grommet remain intact in any unused bores to maintain a rain-tight seal on any unused bores. The transition fitting will maintain a rain-tight seal at the entry of PV cables to EMT. The ground lug provides a means of grounding the EMT to the transition fitting. |
| US10263358B2 |
Connector module having a detachable floating connector assembly
A connector module (100) includes a base (1) including a front face (101), a rear face (102) opposite to the front face, a top face (103) connecting the front face and the rear face, and a mounting slot (104) extending through the front face and the rear face; a first connector assembly (2) mounted on the base; a second connector assembly (3) mounted on the base through the mounting slot along a rear to front direction, and extending beyond the front face for being mated with a mating connector; and a block member (4) mounted on the base with a portion projected into the mounting slot to block a rear end of the second connector assembly to prevent the second connector assembly from withdrawing from the base. |
| US10263355B2 |
Female terminal having a projection provided on a lower edge of a front covering wall to a position to overlap a bottom wall
A terminal (10) includes a rectangular tube (21) with a bottom wall (21A), side walls (21B) rising from both sides of the bottom wall (21A) and a ceiling wall (21C) facing the bottom wall (21A). A contact (22) is inside the rectangular tube (21) and is folded from a front edge of the bottom wall (21A). Front covering walls (30) are in a front end part of the rectangular tube (21) at positions to cover a folded portion (22D) of the contact (22) from the front. Projections (31) on lower edges of the front covering walls (30) project to positions to overlap with the bottom wall (21A) in a front-rear direction. Coupling walls (32) are at positions to couple the front covering walls (30) and the side walls (21B). The coupling walls (32) are flush with the side walls (21B) and located above lower ends of the projections (31). |
| US10263351B2 |
Orthogonal electrical connector system
In accordance with one embodiment, an electrical connector system can include an electrical signal connector and an electrical power connector. The electrical signal connector and the electrical power connector can be mounted on opposed surfaces of a printed circuit board. The electrical power connector can be constructed as a hermaphroditic power connector that includes at least one header power contact supported by a connector housing, and at least one receptacle power contact supported by the connector housing. |
| US10263347B2 |
Connecting structure and connecting method for electric cables
There is provided a connecting structure for electric cables. A first electric cable includes a first core and a first cover covering the first core. A portion of the first core is exposed from an end of the first cover. A second electric cable includes a second core made of a different metal from that of the first core and a second cover covering the second core. A portion of the second core is exposed from an end of the second cover. A tube is shrunk in a state where the tube accommodates thereinside the portion of the first core and the portion of the second core which are connected to each other. An inside of the tube except for the portion of the first core and the portion of the second core is filled with cured hot-melt. |
| US10263346B2 |
Single-package phased array module with interleaved sub-arrays
Embodiments of the present disclosure are directed to a single-package communications device that includes an antenna module with a plurality of independently selectable arrays of antenna elements. The antenna elements of the different arrays may send and/or receive data signals over different ranges of signal angles. The communications device may further include a switch module to separately activate the individual arrays. In some embodiments, a radio frequency (RF) communications module may be included in the package of the communications device. In some embodiments, the RF communications module may be configured to communicate over a millimeter-wave (mm-wave) network using the plurality of arrays of antenna elements. |
| US10263338B2 |
Display panel for front-side wireless communication
In some examples, an apparatus includes a display panel, a shielding layer having an opening formed within a periphery of the shielding layer, the shielding layer adjacent to a back side of the display panel, and an antenna adjacent to the back side of the display panel, wherein the shielding layer is received in the opening formed in the shielding layer, and does not extend beyond an edge of the display panel to allow for wireless communication with the apparatus from a front side of the display panel. |
| US10263335B2 |
Electronic device antennas having shared structures for near-field communications and non-near field communications
An electronic device may be provided with wireless circuitry. The wireless circuitry may include antenna structures such as an antenna resonating element arm and an antenna ground. A split return path may be coupled between the antenna resonating element arm and the antenna ground. The antenna structures may form one or more inverted-F antennas when operated at non-near-field communications frequencies. The antenna structures may be coupled to near-field communications transceiver circuitry using a conductive path. When operated at near-field communications frequencies, near-field communications signals may be conveyed using the conductive path, the antenna resonating element arm, the return path, and the antenna ground. A capacitor may be coupled between the conductive path and an antenna ground. The capacitor may short non-near-field communications signals to the antenna ground and block near-field communications signals from passing from the conductive path to the antenna ground. |
| US10263334B2 |
Antenna device and mobile terminal
The present disclosure provides an antenna device including: a peripheral frame made of a signal shielding material and provided with at least two micro seam bands which partition the peripheral frame into at least two frame bodies, the frame bodies including a first antenna, the micro seam band having at least one micro seam; a first matching circuit electrically coupled to the first antenna; and a first radio-frequency receiving and emitting circuit electrically coupled to the first matching circuit. The frame bodies further includes a second antenna including a second matching circuit and a second radio-frequency receiving and emitting circuit, the second matching circuit is electrically coupled between the second antenna and the second radio-frequency receiving and emitting circuit, and the two radio-frequency receiving and emitting circuits deal with different radio-frequency signals. The micro seam band further includes a frame strip. The present disclosure further provides a mobile terminal. |
| US10263333B2 |
Metal housing, antenna device, and mobile terminal
The present disclosure provides a metal housing; the metal housing includes a first edge and a second edge arranged opposite to each other, and a third edge and a fourth edge arranged opposite to each other. The third edge and the fourth edge are connected between the first edge and the second edge. A partitioning seam is provided in the metal housing so that at least one radiating part is formed in the metal housing. In the antenna device provided by embodiments of the present disclosure, the metal housing is enabled to be a radiator through a combination of the partitioning seam and a radiating circuit. The present disclosure further provides an antenna device and a mobile terminal. |
| US10263332B2 |
Antenna arrays with etched substrates
An electronic device may be provided with wireless communications circuitry and control circuitry. The wireless communications circuitry may include centimeter and millimeter wave transceiver circuitry and a phased antenna array. A dielectric cover may be formed over the phased antenna array. The phased antenna array may transmit and receive antenna signals through the dielectric cover. The dielectric cover may have first and second opposing surfaces. The second surface may face the phased antenna array and may have a curvature. The antenna elements of the phased antenna array may be formed on a dielectric substrate. The dielectric substrate may have one or more thinned regions between antenna elements of the phased antenna array to promote bending. The dielectric substrate may have a smaller thickness in the thinned region than in the regions under the antenna elements. The dielectric substrate may be totally removed in the thinned region. |
| US10263330B2 |
Antenna elements and apparatus suitable for AAS calibration by selective couplerline and TRX RF subgroups
An antenna arrangement includes an antenna element and a corresponding feeder line configured to feed a signal to and from the antenna element, and includes a portion of a couplerline spaced apart from but proximate to the antenna element, the feeder line, and a selectivity element. The portion of the couplerline is configured to receive via inductive coupling the signal from one or both of the feeder line and the antenna element, and to transmit a signal via inductive coupling to the feeder line and/or the antenna element. The antenna arrangement includes the selectivity element, which is spaced apart from but proximate to the antenna element, the feeder line, and the portion of the couplerline, and which is configured to select or not select the antenna element for coupling to the portion of the couplerline. An apparatus may include multiple antenna arrangements (with subgroups) and be configured for AAS calibration. |
| US10263322B2 |
Vehicle antenna
Disclosed is a vehicular antenna. The antenna, according to an embodiment of the present invention, comprises: a spring part which is perpendicularly disposed on the roof of a vehicle; and a metal part perpendicularly disposed on the top of the spring part. The metal part comprises: a first part extending from the body; a second part which extends from the body and is disposed to have a predetermined interval from the first part; and a third part which extends from the body, is disposed between the first and second parts, and is bent to form a predetermined angle with the first and second parts. |
| US10263319B2 |
Antenna with swappable radiation direction and communication device thereof
An antenna with swappable and selective radiation direction includes a first arm, a second arm electrically connected to the first arm, a third arm is electrically connected to the first arm, a first impedance tuning circuit coupled to the second arm for connecting the second arm to a ground or a first matching component according to a control signal, and a second impedance tuning circuit coupled to the third arm for connecting the third arm to the ground or a second matching component according to the control signal. By tuning impedance of the antenna, the antenna operates in a first mode corresponding to a first radiation direction or a second mode corresponding to a second radiation direction. |
| US10263318B2 |
Mobile terminal
A mobile terminal is disclosed. The mobile terminal includes a metal housing with an accommodation space, the metal shell including a metal housing having a metal cover, a metal ring disposed outside of the metal cover, and a metal rear housing; an antenna module received in the accommodation space. The antenna module includes a main board with a grounding terminal, the main board including a switching circuit connected with the grounding end of the main board electrically and an LDS antenna controlled by the switching circuit. The main board is connected with the metal cover and the metal ring electrically, the metal cover and the metal ring is coupled with the LDS antenna. |
| US10263316B2 |
Deployable reflectarray antenna structure
The invention is directed to deployable reflectarray antenna structure. In one embodiment, the deployable reflectarray antenna structure includes a pair of flexible electrical elements, a feed antenna, and a deployment mechanism that employs a plurality of tapes to respectively transition the pair of flexible electrical elements from an undeployed state in which the elements are folded towards a deployed state in which the deployment mechanism and electrical elements cooperate to form a reflectarray and a subreflector of a reflectarray antenna structure. Further, the deployment mechanism also operates to position the reflectarray and subreflector relative to one another and to the feed antenna so as to realize a reflectarray antenna structure. |
| US10263314B2 |
Coupling high-frequency signals with a power combiner
A power combiner in the form of a balanced LC combiner is provided. Inputs of the power combiner are isolated from one another via at least one RC matching element. The at least one RC matching element is dimensioned such that the connection between the inputs is at a stable potential during operation of the power combiner at at least one position. The power combiner can be formed in a planar design and have electrically conductive layers running parallel to one another. At least an inductor and a combiner capacitor are formed in the electrically conductive layers. A power combiner arrangement including the power combiner and high-frequency signal sources attached at least two inputs is also provided. The high-frequency signal sources can be in the form of frequency-agile transistor amplifiers. |
| US10263313B2 |
Guided wave coupler, coupling module and methods for use therewith
Aspects of the subject disclosure may include, for example, a coupler including a receiving portion that receives a first electromagnetic wave conveying first data from a transmitting device. A guiding portion guides the first electromagnetic wave to a junction for coupling the first electromagnetic wave to a transmission medium. The first electromagnetic wave propagates via at least one first guided wave mode. The coupling of the first electromagnetic wave to the transmission medium forms a second electromagnetic wave that is guided to propagate along the outer surface of the transmission medium via at least one second guided wave mode that differs from the at least one first guided wave mode. Other embodiments are disclosed. |
| US10263310B2 |
Waveguides and transmission lines in gaps between parallel conducting surfaces
A microwave device, such as a waveguide, transmission line, waveguide circuit, transmission line circuit or radio frequency part of an antenna system, is disclosed. The microwave device comprises two conducting layers arranged with a gap there between, and a set of periodically or quasi-periodically arranged protruding elements fixedly connected to at least one of said conducting layers, thereby forming a texture to stop wave propagation in a frequency band of operation in other directions than along intended waveguiding paths, thus forming a so-called gap waveguide. All protruding elements are connected electrically to each other at their bases at least via the conductive layer on which they are fixedly connected, and some or all of the protruding elements are in conductive or non-conductive contact also with the other conducting layer. A corresponding manufacturing method is also disclosed. |
| US10263308B2 |
Solar flow battery
A solar flow battery comprising: a positive compartment containing at least one positive electrode in contact with a positive electrolyte containing a first redox active molecule; a negative compartment containing at least one negative electrode in contact with a negative electrolyte containing a second redox active molecule, wherein said first and second redox active molecules remain dissolved in solution when changed in oxidation state; at least one of said negative or positive electrodes comprises a semiconductor light absorber; electrical communication means between said electrodes and an external load for directing electrical energy into or out of said solar flow battery; a separator component that separates the positive and negative electrolytes while permitting the passage of non-redox-active species; and means for establishing flow of the positive and negative electrolyte solutions past respective electrodes. Methods of using the solar flow battery for storing and releasing electrical energy are also described. |
| US10263293B2 |
Manufacturing method of lithium secondary battery
Provided is a method of preparing a lithium secondary battery which may simultaneously improve output characteristics and lifetime characteristics of the lithium secondary battery by preparing an electrode on which an SEI film is formed through a pretreatment process, putting an electrode assembly including the electrode in a battery case, and injecting an electrolyte thereinto. |
| US10263289B2 |
Solid state battery
A method of producing a solid state battery includes pre-coating a solid electrolyte surface with a metal to form a sacrificial layer and contacting a metal alloy with the sacrificial layer such that the sacrificial layer and the metal alloy react to form a eutectic liquid metal interface layer, at room temperature and between the electrolyte and a lithium anode, configured to alloy with the liquid metal interface layer at operating potential. |
| US10263286B2 |
Secondary battery electrolyte and secondary battery
The present invention relates to a secondary battery electrolyte, which contains a first fluorine-containing ether compound, a second fluorine-containing ether compound, and at least one selected from fluorine-containing phosphate ester compounds and sulfone compounds, wherein the fluorine substitution rate of the first fluorine-containing ether compound is lower than that of the second fluorine-containing ether compound, and the content of the first fluorine-containing ether compound is higher than that of the second fluorine-containing ether compound. According to the present invention, with respect to batteries operating at a high voltage, and batteries supposed to be used at a high temperature for a long period, there can be provided a lithium secondary battery suppressed in the decomposition reaction of the electrolyte and improved in the life characteristics. |
| US10263281B2 |
All-solid ion battery
The present invention provides an all-solid ion battery having improved stability and power characteristics and comprising: a powder-form solid electrolyte; a powder-form electrode active material; a first conductive polymer coating film coated on at least a portion of the solid electrolyte and capable of transporting ions; and a second conductive polymer coating film coated on at least a portion of the electrode active material and capable of transporting ions and electrons. |
| US10263280B2 |
9,10-Bis(1,3-dithiol-2-ylidene)-9,10-dihydroanthracene polymers and use thereof
The problem addressed was that of providing novel polymers which are preparable with a low level of complexity, with the possibility of controlled influence on the physicochemical properties thereof within wide limits in the course of synthesis, and which are usable as active media in electrical charge storage elements for high storage capacity, long lifetime and stable charging/discharging plateaus.9,10-Bis(1,3-dithiol-2-ylidene)-9,10-dihydroanthracene polymers consisting of an oligomeric or polymeric compound of the general formula I have been found. |
| US10263278B2 |
Battery, electrolyte, battery pack, electronic apparatus, electrically driven vehicle, electrical storage device, and electric power system
Provided is a battery including a positive electrode, a negative electrode, a separator, and an electrolyte that contains particles, a resin, and an electrolytic solution. The shape of the particles includes a plane, a plane rate of the particles is greater than 40% and equal to or less than 100%, and a refractive index of the particles is equal to or greater than 1.3 and less than 2.4. |
| US10263274B2 |
Fuel cell manifold including a coating to reduce the possibility of an electrical short
An illustrative example fuel cell manifold includes a manifold structure having at least one surface situated where the surface may be exposed to phosphoric acid. The surface has a coating that reduces a possibility of an electrical short between the manifold and the fuel cell stack adjacent the manifold if that surface is exposed to phosphoric acid during fuel cell operation. |
| US10263271B2 |
Redox type fuel cell
The present invention is to provide a redox type fuel cell that is able to quickly regenerate a mediator. The present invention is such a redox type fuel cell that a mediator is circulated in a cathode electrode, wherein a regenerator for oxidizing the mediator includes: a first chamber configured to store a mediator-containing solution; a second chamber configured to store an oxygen reduction reaction medium solution; a power source; a first electrode disposed in the first chamber and connected to a positive electrode of the power source: a second electrode disposed in the second chamber and connected to a negative electrode of the power source; an ion exchange path configured to connect the first chamber and the second chamber; and a gas supplier configured to supply an oxygen-containing gas into the second chamber. |
| US10263267B2 |
Battery pack manufacturing method using hot-melt fixing structure and battery pack manufactured using the same
Disclosed herein is a method of manufacturing a battery pack including a battery cell having an electrode assembly received in a battery case, made of a laminate sheet including a resin layer and a metal layer, together with an electrolytic solution. |
| US10263263B2 |
Frame body, cell frame for redox flow battery, and redox flow battery
There is provided a frame body used for a cell of a redox flow battery, that can improve heat dissipation of an electrolyte in a slit and can suppress rise of the temperature of the electrolyte. It is a frame body used for a cell of a redox flow battery, comprising: an opening formed inside the frame body; a manifold allowing an electrolyte to pass therethrough; and a slit which connects the manifold and the opening and forms a channel of the electrolyte between the manifold and the opening, the slit having a pair of sidewalls facing each other in a cross section orthogonal to a direction in which the electrolyte flows, the slit having, at at least a portion thereof in the slit's depthwise direction, a width narrowing portion allowing the sidewalls to have a spacing narrowed in the depthwise direction. |
| US10263262B2 |
Fuel cell with porous material-gasket integrated structure
Disclosed is a fuel cell with a porous material-gasket integrated structure, which can facilitate the flow of gas and water by stacking a porous material-gasket integrated structure, in which a porous material and a gasket are integrally molded, on a separator. In particular, the present invention provides a fuel cell with a porous material-gasket integrated structure, in which a porous material and a gasket are integrally molded and stacked on a separator such that the porous material is located between a manifold, through which gas is supplied, and a reaction surface, where an electrochemical reaction takes place, so as to serve as a diffuser for gas fed through the manifold. |
| US10263260B2 |
Electrode catalyst for fuel cell, method for producing the same, and polymer electrolyte fuel cell using the same
A method for producing an electrode catalyst for a fuel cell is provided. The electrode catalyst includes a carbon support and a catalyst supported on the carbon support. The catalyst is one of platinum and a platinum-alloy. The method includes supporting the catalyst on the carbon support; and treating the carbon support carrying the catalyst with a nitric acid and cleaning the treated carbon support, such that an amount of an acid present on the carbon support becomes in a range from 0.7 mmol to 1.31 mmol of the acid per gram of the electrode catalyst. |
| US10263259B2 |
Method for producing core-shell catalyst particles
The present invention is to provide a method for producing core-shell catalyst particles with high catalytic activity per unit mass of platinum. Disclosed is a method for producing core-shell catalyst particles including a core containing palladium and a shell containing platinum and covering the shell, wherein the method includes: a step of depositing copper on the surface of the palladium-containing particles by applying a potential that is nobler than the oxidation-reduction potential of copper to the palladium-containing particles in a copper ion-containing electrolyte, and a step of forming the shell by, after the copper deposition step and inside the reaction system kept at −3° C. or more and 10° C. or less, substituting the copper deposited on the surface of the palladium-containing particles with platinum by bringing the copper into contact with a platinum ion-containing solution in which platinum ions and a reaction inhibitor that inhibits a substitution reaction between the copper and the platinum, are contained. |
| US10263258B2 |
Air electrode material, air electrode, metal-air battery, and fuel cell
An air electrode material according to the present disclosure contains a plurality of composite particles, wherein each of the composite particles contains a core particle and a plurality of covering particles covering the core particle, the core particle is formed of a material with catalytic activity for an oxygen reduction reaction, the covering particles are formed of an electrically conductive material and are mechanically bonded to the core particles or other covering particles, and the median size of the core particles ranges from 100 to 1000 times the average primary particle size of the covering particles. |
| US10263256B2 |
Spinel type lithium nickel manganese-containing composite oxide
Relating to a 5 V-class spinel type lithium nickel manganese-containing composite oxide having an operating potential of 4.5 V or more with respect to a Li metal reference potential, the present invention proposes a composite oxide being capable of improving cycle properties while suppressing the amount of gas generation under high temperature environments and of increasing thermodynamical stability of a positive electrode in a fully charged state. Proposed is a spinel type lithium nickel manganese-containing composite oxide represented by a general formula [Li(LiaNiyMn2-a-b-y-z-αTibAlzMα)O4-σ] (where 0 |
| US10263254B2 |
Tin-containing compounds
The invention relates to novel materials of the formula: AuM1vM2wM3x02±δ wherein A is one or more alkali metals; M1 comprises one or more redox active metals with an oxidation state in the range +2 to +4; M2 comprises tin, optionally in combination with one or more transition metals; M3 comprises one or more transition metals either alone or in combination with one or more non-transition elements selected from alkali metals, alkaline earth metals, other metals, metalloids and non-metals, with an oxidation state in the range +1 to +5; wherein the oxidation state of M1, M2, and M3 are chosen to maintain charge neutrality and further wherein δ is in the range 0≤δ≤0.4; U is in the range 0.3 |
| US10263253B2 |
Method of preparing a vanadium oxide compound and use thereof in electrochemical cells
Electrochemical cell comprising an anode and a cathode is provided. The anode and the cathode independently comprises or consists essentially of a vanadium oxide compound having general formula MnV6O16, wherein M is selected from the group consisting of ammonium, alkali-metal, and alkaline-earth metal; and n is 1 or 2. Method of preparing a vanadium oxide compound having general formula MnV6O16 is also provided. |
| US10263252B2 |
Negative electrode for non-aqueous electrolyte secondary battery, and non-aqueous electrolyte secondary battery
A non-aqueous electrolyte secondary battery including a silicon material as a negative electrode active material has good discharge rate characteristics. A negative electrode according to an exemplary embodiment includes a negative-electrode current collector and a negative-electrode mixture layer formed on the current collector. The negative-electrode mixture layer contains graphite and a silicon material. A first region that extends from the surface of the mixture layer remote from the negative-electrode current collector in the thickness direction of the negative-electrode mixture layer and has a thickness equal to 40% of the thickness of the mixture layer contains a larger amount of the silicon material than a second region that extends from the surface of the mixture layer adjacent to the negative-electrode current collector and has a thickness equal to 40% of the thickness of the mixture layer. The first region has a lower density than the second region. |
| US10263251B2 |
Battery negative electrode, battery, and manufacturing method of battery negative electrode
A battery negative electrode includes a hydrogen storage alloy as a negative electrode active material, wherein the hydrogen storage alloy has a mean volume diameter within a range from 4 μm to 12 μm, and is disposed to be capable of being in contact with hydrogen in a hydrogen containing part in which hydrogen is contained. |
| US10263249B2 |
Carbon-silicon composite, method of preparing the same, and anode active material including the carbon-silicon composite
Provided are a carbon-silicon composite having improved capacity and cycle stability, and a method of preparing the same. More particularly, the present invention relates to a carbon-silicon composite, in which surfaces of silicon particles are coated with a carbon-based material that is doped with at least one type of doping atoms selected from the group consisting of nitrogen (N), phosphorous (P), boron (B), sodium (Na), and aluminum (Al), and a method of preparing the same. |
| US10263246B2 |
Lithiated and passivated lithium ion battery anodes
An electrode material includes a lithium active material composition. The lithium active material composition includes lithium and an active anode material. The lithium active material composition is coated with a lithium ion conducting passivating material, such that the electrode material is lithiated and pre-passivated. An electrode and a battery are also disclosed. Methods of making an electrode material, electrode and battery that are lithiated and pre-passivated are also disclosed. |
| US10263240B2 |
Sandwich cathode lithium battery with high energy density
A lithium electrochemical cell with increased energy density is described. The electrochemical cell comprises an improved sandwich cathode design with a second cathode active material of a relatively high energy density but of a relatively low rate capability sandwiched between two current collectors and with a first cathode active material having a relatively low energy density but of a relatively high rate capability in contact with the opposite sides of the two current collectors. In addition, a cathode fabrication process is described that increases manufacturing efficiency. The cathode fabrication process comprises a process in which first and second cathode active materials are directly applied to opposite surfaces of a perforated current collector and laminated together. The present cathode design is useful for powering an implantable medical device requiring a high rate discharge application. |
| US10263237B2 |
Cylindrical battery, and collector member used therefor, and manufacturing method thereof
A cylindrical battery according to one aspect of the present invention includes an electrode body in which a negative electrode plate and a positive electrode plate to which a plurality of positive electrode leads is connected are wound with a separator interposed therebetween; an electrolyte liquid; a cylindrical outer can having a bottom portion which receives the electrode body and the electrolyte liquid; and a sealing body sealing an open portion of the outer can. The positive electrode leads extend along an outer circumference portion of a collector member disposed on the electrode body and are connected to a surface of the collector member at an outer side of the battery. The collector member includes a collector plate to which the positive electrode leads are connected and a first insulating plate fitted to a surface of the collector plate at an inner side of the battery. |
| US10263235B2 |
Separator, nonaqueous electrolyte battery, battery pack, electronic device, electric vehicle, power storage device, and power system
A separator includes a substrate layer that is porous, and a surface layer that is provided on at least one main face of the substrate layer and that has an uneven shape. The surface layer includes first particles that are for forming convexities of the uneven shape and that are a main component of the convexities, second particles that have a smaller average particle size than the first particles, cover at least a part of a surface of the first particles, and cover at least a part of a surface of the substrate layer that is exposed between the first particles, and a resin material. |
| US10263232B2 |
Nonaqueous electrolyte secondary battery separator heating device and nonaqueous electrolyte secondary battery separator production method
A drying device includes a first cylindrical member and a second cylindrical member. The first cylindrical member has an outer peripheral surface having a surface temperature that is higher on one width wise side where an end is present than on the other widthwise side where another end is present, whereas the second cylindrical member has an outer peripheral surface having a surface temperature that is lower on the one widthwise side where an end is present than on the other widthwise side where another end is present. |
| US10263229B2 |
Battery block
Cells are arranged in a predetermined arrangement and are held by holding unit. The holding unit includes a first holding unit, a second holding unit, and a third holding unit. The first holding unit holds cells so as to partially cover the one side of the outer peripheral surfaces of the cells in the longitudinal direction. The second holding unit holds the cells so as to partially cover the other side of the outer peripheral surfaces of the cells in the longitudinal direction. The third holding unit holds the cells so as to cover a region that is covered with neither the first holding unit nor the second holding unit, of the outer peripheral surfaces of the cells in the longitudinal direction. |
| US10263228B2 |
Electric device including sealing member between attachment part and battery pack
The sealing property obtained when a battery pack is attached to an electric power tool is improved. An electric power tool to/from which a battery pack retaining a battery cell is attachable/detachable has: a tool main body being provided with an attachment part to/from which the battery pack is attached/detached; a guide groove which is provided in the attachment part and which determines a direction of the attachment/detachment of the battery pack; a device-side terminal which is provided in the attachment part and which is connected to a battery-side terminal provided in the battery pack; and a seal member which is provided in the attachment part and which seals a connecting part between the battery-side terminal and the device-side terminal. |
| US10263221B2 |
Method for manufacturing light-emitting device
A method for exposing an electrode terminal covered with an organic film in a light-emitting device without damaging the electrode terminal is provided. In a region of the electrode terminal to which electric power from an external power supply or an external signal is input, an island-shaped organic compound-containing layer is formed and the organic film is formed thereover. The organic film is removed by utilizing low adhesion of an interface between the organic compound-containing layer and the electrode terminal, whereby the electrode terminal can be exposed without damage to the electrode terminal. |
| US10263214B2 |
Optoelectronic component and method for producing an optoelectronic component
In various embodiments, an optoelectronic component is provided. The optoelectronic component includes an optically active layer structure on a surface of a planar substrate. The surface in a predefined region is free of optically active layer structure. The optoelectronic component further includes an encapsulation structure having an inorganic encapsulation layer. The inorganic encapsulation layer is formed on or above the optically active layer structure and the surface of the substrate in the predefined region. The inorganic encapsulation layer at least in the predefined region is formed in direct contact with the surface of the substrate. The surface of the substrate at least in the predefined region includes a structuring. The structuring is configured to increase the roughness of the surface. The substrate at least in the predefined region at the surface thereof includes or is formed from an inorganic material. |
| US10263208B2 |
Organic electro-luminescent display device
An organic electroluminescent display device according to an embodiment of the present invention includes a lower electrode, an upper electrode, an organic EL layer positioned between the lower electrode and the upper electrode and a light emitting material containing layer that contains a light emitting material and is arranged on an opposite side of the upper electrode from the organic EL layer. |
| US10263207B2 |
Perovskite light emitting device containing exciton buffer layer and method for manufacturing same
Provided are a perovskite light emitting device containing an exciton buffer layer, and a method for manufacturing the same. A light emitting device of the present invention comprises: an exciton buffer layer in which a first electrode, a conductive layer disposed on the first electrode and comprising a conductive material, and a surface buffer layer containing fluorine-based material having lower surface energy than the conductive material are sequentially deposited; a light-emitting layer disposed on the exciton buffer layer and containing an organic-inorganic hybrid perovskite light emitting body; and a second electrode disposed on the light-emitting layer. Accordingly, an organic-inorganic hybrid perovskite is formed with a combined FCC and BSS crystal structure in a nanoparticle light-emitting body; the present invention forms a lamellar structure in which an organic plane and an inorganic plane are alternatively deposited; and an exciton is bound by the inorganic plane, thereby being capable of expressing high color purity. |
| US10263204B2 |
Organic light-emitting display device
Disclosed herein is an organic light-emitting display device having a first flexible substrate; a second flexible substrate; a plurality of organic light-emitting pixels on the first flexible substrate and between the first flexible substrate and the second flexible substrate; an encapsulation unit covering the pixels; and an adhesive layer on the encapsulation unit. The Young's modulus of the adhesive layer is equal to or larger than a value so that the first flexible substrate is not deformed by bending stress when it is rolled up. |
| US10263197B2 |
Synthesis of four coordinated palladium complexes and their applications in light emitting devices thereof
Synthesis of four coordinated palladium complexes and their applications in light emitting devices thereof. |
| US10263193B2 |
Heterocyclic compound and organic light-emitting element using same
Disclosed are a heterocyclic compound represented by the following Chemical Formula having proper energy level, and excellent electrochemical stability and thermal stability, and an organic light emitting device using the same: |
| US10263191B2 |
Aromatic amine derivative, and organic electroluminescent element comprising the same
An aromatic amine derivative represented by the following formula (1) wherein at least one of Ar1 to Ar4 is a heterocyclic group represented by the following formula (2) wherein X1 is an oxygen atom or a sulfur atom. |
| US10263190B2 |
Difluorobithiophene-based donor-acceptor polymers for electronic and photonic applications
An organic compound, a donor-acceptor conjugated polymer, a formulation and a thin film, wherein a solution of the donor-acceptor conjugated polymer exhibits a peak optical absorption spectrum red shift of at least 100 nm when the donor-acceptor conjugated polymer solution is cooled from 140° C. to room temperature. |
| US10263185B2 |
Method of manufacturing OLED display device, mask, and method of designing mask
A method of manufacturing an OLED display deposits an OLED material onto an electrode surface of a substrate through a mask while moving a linear source having nozzles in a first direction. The mask has holes in a surface facing the linear source. Each hole has a first opening and a larger second opening located between the first opening and the linear source. θT<90−θM and SX>D1×tan θM are satisfied. D1 is a distance from the first opening to the electrode surface. θM is the largest incident angle in the first direction of the OLED material. SX is a distance in the first direction from an edge of the first opening to an adjacent sub-pixel electrode. θT is a taper angle defined by a line connecting the edge of the first opening and the edge of the second opening and the first direction. |
| US10263184B2 |
Switching device and non-volatile memory device including the same
A switching device includes a first switching element having a snap-back behavior characteristic, an output voltage of the first switching element decreasing when an input current increases from a turn-on threshold current of the first switching element. The switching device further includes a second switching element having a continuous-resistance behavior characteristic, an output voltage of the second switching element increasing when the input current increases from a turn-on threshold current of the second switching element. The turn-on threshold current of the first switching element is lower than the turn-on threshold current of the second switching element. |
| US10263177B2 |
Semiconductor device
The vertical Hall element includes: a second conductivity type semiconductor layer formed on a first conductivity type semiconductor substrate; a plurality of high-concentration second conductivity type electrodes formed in a straight line on a surface of the semiconductor layer having substantially the same shape, and spaced at a first interval; a plurality of electrode isolation layers each formed between two electrodes out of the plurality of electrodes to isolate the plurality of electrodes from one another having substantially the same shape, and spaced at a second interval; and a first added layer and a second added layer each formed along the straight line outside of the outermost electrodes, and each having substantially the same structure as that of each electrode isolation layer. |
| US10263176B2 |
Semiconductor device having vertical hall element
A vertical Hall element having an improved sensitivity and reduced offset voltage includes: a second conductivity type semiconductor layer formed on a semiconductor substrate and having an impurity concentration that is distributed uniformly; a second conductivity type impurity diffusion layer formed on the semiconductor layer and having a concentration higher than in the semiconductor layer; a plurality of electrodes formed in a straight line on a surface of the impurity diffusion layer, and each formed from a second conductivity type impurity region that is higher in concentration than the impurity diffusion layer; and a plurality of first conductivity type electrode isolation diffusion layers each formed between two electrodes out of the plurality of electrodes on the surface of the impurity diffusion layer, to isolate the plurality of electrodes from one another. |
| US10263175B2 |
Piezoelectric element and piezoelectric element-applied device
A piezoelectric element includes a first electrode, a second electrode, and a piezoelectric layer provided between the first and second electrodes. In the piezoelectric element, the piezoelectric layer is made from a perovskite composite oxide represented by Pb(Ni, Nb, Zr, Ti)O3 and the total of the Ni and Nb contents in the perovskite composite oxide is not less than 1 [mol %] and not more than 5 [mol %] based on a total content of elements contained in a B site. |
| US10263169B2 |
PEDOT:PSS composite films having enhanced thermoelectric properties
A PEDOT:PSS film having enhanced thermoelectric properties is doped with DMSO and a binary secondary dopant, such as PEO. The composition of such film causes the ratios of PEDOT in bipolaron states to be increased. As a result, the Seebeck coefficient, the electrical conductivities, and power factor of the film are increased, thereby increasing the efficiency of the film. Thus, a thermoelectric device that uses the film is able to achieve enhanced operating performance. |
| US10263164B2 |
Electronic component including a material comprising epdxysilane-modified polyorganosiloxane
The present invention relates to an optoelectronic component comprising a semiconductor (1) and a polyorganosiloxane. The polyorganosiloxane is obtainable by crosslinking a composition comprising a first organosiloxane having at least one terminal vinyl group, a second organosiloxane having at least one silicon-hydrogen bond and an alkoxysilane having at least one epoxy group. Additionally specified is a method of producing an optoelectronic component. |
| US10263162B2 |
Light emitting device and image displaying system
A light emitting device includes a light emitting element disposed on a substrate which emits blue light, a green phosphor that emits green light upon being excited by the blue light, a red phosphor that emits red light upon being excited by the blue light, and a transparent resin including the green phosphor and the red phosphor dispersed therein. The red phosphor is arranged to be in contact with the light emitting element and the substrate. The transparent resin includes a constitutional unit including an ionic liquid including a polymerizable functional group or a derivative of the ionic liquid. |
| US10263161B2 |
Resin molding, surface mounted light emitting apparatus and methods for manufacturing the same
The present invention provides a surface mounted light emitting apparatus which has long service life and favorable property for mass production, and a molding used in the surface mounted light emitting apparatus.The surface mounted light emitting apparatus comprises the light emitting device 10 based on GaN which emits blue light, the first resin molding 40 which integrally molds the first lead 20 whereon the light emitting device 10 is mounted and the second lead 30 which is electrically connected to the light emitting device 10, and the second resin molding 50 which contains YAG fluorescent material and covers the light emitting device 10. The first resin molding 40 has the recess 40c comprising the bottom surface 40a and the side surface 40b formed therein, and the second resin molding 50 is placed in the recess 40c. The first resin molding 40 is formed from a thermosetting resin such as epoxy resin by the transfer molding process, and the second resin molding 50 is formed from a thermosetting resin such as silicone resin. |
| US10263159B2 |
Light-emitter mounting package, light-emitting device, and light-emitting module
A light-emitter mounting package includes an insulating base, a wiring conductor, and a metal layer. The insulating base has a main surface including a recess in which a light emitter is mountable. The wiring conductor is arranged on a peripheral portion of a bottom surface of the recess that is adjacent to an inner wall of the recess. The insulating base has a side surface including a sloping surface adjacent to the main surface. The metal layer is spaced from the wiring conductor, and extends on the inner wall of the recess, the main surface, and the sloping surface. |
| US10263156B2 |
Light emitting diode structure
A light emitting diode structure including a substrate, a semiconductor epitaxial structure, a first insulating layer, a first reflective layer, a second reflective layer, a second insulating layer and at least one electrode. The substrate has a tilt surface. The semiconductor epitaxial structure at least exposes the tilt surface. The first insulating layer exposes a portion of the semiconductor epitaxial structure. The first reflective layer is at least partially disposed on the portion of the semiconductor epitaxial structure and electrically connected to the semiconductor epitaxial structure. The second reflective layer is disposed on the first reflective layer and the first insulating layer, and covers at least the portion of the tilt surface. The second insulating layer is disposed on the second reflective layer. The electrode is disposed on the second reflective layer and electrically connected to the first reflective layer and the semiconductor epitaxial structure. |
| US10263154B2 |
Light-emitting device and light-emitting device package comprising same
An embodiment relates to a light-emitting device comprising: a light-emitting structure which comprises a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer, and comprises a plurality of first recesses passing through the second conductive semiconductor layer and active layer and disposed on a part of an area of the first conductive semiconductor layer; a first electrode which is electrically connected to the first conductive semiconductor layer inside the plurality of first recesses; a conductive support substrate which is electrically connected to the first electrode; a second electrode which is electrically connected to the second conductive semiconductor layer; and an insulating layer which is disposed between the conductive support substrate and second conductive semiconductor layer, wherein a second recess passes through the first conductive semiconductor layer, second conductive semiconductor layer and active layer and is disposed on a part of an area of the insulating layer. |
| US10263153B2 |
Light-emitting diode (LED) display array, manufacturing method thereof, and wearable device
A light-emitting diode (LED) display array, a manufacturing method thereof and a wearable device are provided. The LED display array comprises a first substrate and a second substrate arranged oppositely to each other. At least one pixel unit is formed on a surface of the first substrate facing the second substrate. At least one drive unit is formed on a surface of the second substrate facing the first substrate. Each pixel unit on the first substrate corresponds to a drive unit on the second substrate. A metal block is formed between each pixel unit and the drive unit corresponding to the pixel unit. The pixel unit is electrically connected with the drive unit corresponding to the pixel unit through the metal block. |
| US10263151B2 |
Light emitting diodes
The present disclosure generally relates to semiconductor structures and, more particularly, to light emitting diodes and methods of manufacture. The method includes: forming fin structures with a doped core region, on a substrate material; forming a first color emitting region by cladding the doped core region of a first fin structure of the fin structures, while protecting the doped core regions of a second fin structure and a third fin structure of the fin structures; forming a second color emitting region by cladding the doped core region of the second fin structure, while protecting the doped core regions of the first fin structure and the third fin structure; and forming a third color emitting region by cladding the doped core region of the third fin structure, while protecting the doped core regions of the first fin structure and the second fin structure. |
| US10263147B2 |
Light emitting diode and fabrication method thereof
A light-emitting diode (LED) chip includes from bottom to up: a conductive substrate, a p-type nitride layer, an active layer, an n-type recovery layer, an n-type nitride layer and an n electrode, wherein, the n-type nitride layer has a nitride polarity crystal and a gallium polarity crystal, and the surfaces of the nitride polarity and the gallium polarity regions appear different in height, the n-type recovery layer surface approximate to the n-type nitride layer has consistent mixed polarity with the n-type nitride layer, and the surface far from the n-type nitride layer is a connected gallium polarity surface. |
| US10263146B2 |
Ultra-wideband, free space optical communication apparatus
Devices, systems, and methods for providing wireless personal area networks (PANs) and local area networks (LANs) using visible and near-visible optical spectrum. Various constructions and material selections are provided herein. According to one embodiment, a free space optical (FSO) communication apparatus includes a digital data port, an array of light-emitting diodes (LEDs) each configured to have a transient response time of less than 500 picoseconds (ps), and current drive circuitry coupled between the digital data port and the array of LEDs. |
| US10263142B2 |
Plasmonic light emitting diode
A light emitting diode includes a square quantum well structure, the quantum well structure including III-V materials. A dielectric layer is formed on the quantum well structure. A plasmonic metal is formed on the dielectric layer and is configured to excite surface plasmons in a waveguide mode that is independent of light wavelength generated by the quantum well structure to generate light. |
| US10263141B2 |
Semiconductor light-emitting device and method of manufacturing semiconductor light-emitting device
A semiconductor light-emitting device according to an embodiment of the present disclosure includes a nitride-based first light-emitting layer. The first light-emitting layer has an InaGa1−aN layer (a≥0), and has a plurality of first island-shaped regions that include InbGa1−bN (b>a) inside the InaGa1−aN layer. |
| US10263140B2 |
Semiconductor light-emitting device and method for manufacturing the same
The disclosed invention relates to a semiconductor light-emitting element comprising: a plurality of semiconductor layers which are provided with a growth substrate eliminating surface on the side where a first semiconductor layer is located; a support substrate which is provided with a first electrical pathway and a second electrical pathway; a joining layer which joins a first surface side of the support substrate with a second semiconductor layer side of the plurality of semiconductor layers, and is electrically linked with the first electrical pathway; a joining layer eliminating surface which is formed on the first surface, and in which the second electrical pathway is exposed, and which is open towards the plurality of semiconductor layers; and an electrical link for electrically linking the plurality of semiconductor layers with the second electrical pathway exposed in the joining layer eliminating surface. |
| US10263139B2 |
Fabrication method of nitride light emitting diodes
A fabrication method of a nitride semiconductor LED includes, an AlxInyGa1-x-yN material layer is deposited by CVD between an AlN thin film layer by PVD and a gallium nitride series layer by CVD, to reduce the stress effect between the AlN thin film layer and the nitride layer, improve the overall quality of the LED and efficiency. An AlN thin film layer is deposited on a patterned substrate having a larger depth by PVD, and a thin nitrogen epitaxial layer is deposited on the AIN thin film layer by CVD, which reduces the stress by reducing the thickness of the epitaxial layer and improves warpage of the wafer and electric uniformity of the single wafer; the light extraction efficiency is improved by using the large depth patterned substrate; further, the doping of high-concentration impurity in the active layer effectively reduces voltage characteristics without affecting leakage, thereby improving the overall yield. |
| US10263137B2 |
Light-emitting device
A light-emitting device includes an active structure, wherein the active structure includes a well layer and a barrier layer. A first semiconductor layer of first conductivity type and a second semiconductor layer of second conductivity type sandwich the active structure. A first intermediate layer is between the first semiconductor layer and the active structure, wherein the first semiconductor layer has a first band gap, the second semiconductor layer has a second band gap, the well layer has a third band gap, and the first intermediate layer has a fourth band gap, wherein the first band gap and the second band gap are both larger than the fourth band gap, and the fourth band gap is larger than the third band gap. A first window layer is on the first semiconductor layer, wherein the first intermediate layer includes Alz1Ga1-z1As, the first window layer includes Alz2Ga1-z2As, and z1>z2. |
| US10263134B1 |
Multijunction solar cells having an indirect high band gap semiconductor emitter layer in the upper solar subcell
The present disclosure provides a multijunction solar cell comprising: an upper solar subcell having an indirect band gap semiconductor emitter layer composed of greater than 0.8 but less than 1.0 mole fraction aluminum and a base layer, the emitter layer and the base layer forming a heterojunction solar subcell; and a lower solar subcell disposed beneath the upper solar subcell, wherein the lower solar subcell has an emitter layer and a base layer forming a photoelectric junction. In some embodiments, the emitter layer of the upper solar subcell is an n-type AlxGa1-xAs layer with 0.8 |
| US10263132B2 |
Solar energy devices
Solar energy device (100) comprising at least one of a photovoltaic cell or a solar thermal collector (101) having an absorption bandwidth in the infrared wavelength region of the solar spectrum; a visible light-transmitting reflector (103); and at least one of a graphic film or lighted display (105). The graphic film or a lighted display present is visible through the visible light-transmitting reflector. The solar energy devices can be used, for example, as a sign (e.g., an advertising sign or a traffic sign), on the side and/or roof, as well as in a window, of a building. |
| US10263130B2 |
Assembly method for a backsheet for photovoltaic panels with double contacting face conductive elements of the non-through type
Assembly method for backsheet for photovoltaic panels with conductive interface elements intended to simplify the electrical connection of the terminal points of the circuit to the back junction box. The conductive elements are of the non-through type through the backsheet, with double contacting face, and are integrated on the front side towards the cells within recessed seats and in correspondence of through-holes in such a way as to enable an electrical connection by contact from the back side through the holes, in a guided way, by means of respective conductive elements protruding and fastened to the junction box. In particular, such a simplified contacting solution can be realized with extreme precision, without manual operations and at extremely low costs, with an automated assembly method. |
| US10263125B2 |
Varactor diode with heterostructure
Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device, such as a varactor diode. The IC device includes a composite collector and heterostructure. A layer of wider band gap material is included as part of the collector at the collector/base interface. The presence of the wide band gap material may increase breakdown voltage and allow for increased hyperabrupt doping profiles in the narrower band gap portion of the collector. This may allow for increased tuning range and improved intermodulation (IMD) performance without the decreased breakdown performance associated with homojunction devices. Other embodiments may also be described and/or claimed. |
| US10263123B2 |
Electrostatic discharge device and method of fabricating the same
Provided are an electrostatic discharge (ESD) device and method of fabricating the same where the ESD device is configured to prevent electrostatic discharge which can be a cause to product failure. More particularly, the ESD device provided includes a Zener diode and a plurality of PN diodes by improving the architecture of an area wherein a Zener diode is configured compared to alternatives, to provide improved functionality when protecting against ESD events. |
| US10263120B2 |
Method for manufacturing semiconductor device and method for manufacturing liquid crystal display panel
An embodiment is a semiconductor device which includes a first oxide semiconductor layer over a substrate having an insulating surface and including a crystalline region formed by growth from a surface of the first oxide semiconductor layer toward an inside; a second oxide semiconductor layer over the first oxide semiconductor layer; a source electrode layer and a drain electrode layer which are in contact with the second oxide semiconductor layer; a gate insulating layer covering the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating layer and in a region overlapping with the second oxide semiconductor layer. The second oxide semiconductor layer is a layer including a crystal formed by growth from the crystalline region. |
| US10263119B2 |
Programmable device with high reliability for a semiconductor device, display system, and electronic device
A novel semiconductor device is provided. The semiconductor device includes a programmable logic device including a programmable logic element, a control circuit, and a detection circuit. The programmable logic device includes a plurality of contexts. The control circuit is configured to control selection of the contexts. The detection circuit is configured to output a signal corresponding to the amount of radiation. The control circuit is configured to switch between a first mode and a second mode in accordance with the signal corresponding to the amount of radiation. The first mode is a mode in which the programmable logic device performs processing by a multi-context method, and the second mode is a mode in which the programmable logic device performs processing using a majority signal of signals output from the logic element multiplexed by the plurality of contexts. |
| US10263118B2 |
Semiconductor device with oxide semiconductor layer
A semiconductor device with reduced parasitic capacitance is provided. A stack is formed on an insulating layer, the stack comprising a first oxide insulating layer, an oxide semiconductor layer over the first oxide insulating layer, and a second oxide insulating layer on the oxide semiconductor layer; a gate electrode layer and a gate insulating layer are formed on the second oxide insulating layer; a first low-resistance region is formed by adding a first ion to the second oxide semiconductor layer using the gate electrode layer as a mask; a sidewall insulating layer is formed on an outer side of the gate electrode layer; a second conductive layer is formed over the gate electrode layer, the sidewall insulating layer, and the second insulating layer; and an alloyed region in the second oxide semiconductor layer is formed by performing heat treatment. |
| US10263117B2 |
Semiconductor device
A semiconductor device having favorable electric characteristics is provided. An oxide semiconductor layer includes first and second regions apart from each other, a third region which is between the first and second regions and overlaps with a gate electrode layer with a gate insulating film provided therebetween, a fourth region between the first and third regions, and a fifth region between the second and third regions. A source electrode layer includes first and second conductive layers. A drain electrode layer includes third and fourth conductive layers. The first conductive layer is formed only over the first region. The second conductive layer is in contact with an insulating layer, the first conductive layer, and the first region. The third conductive layer is formed only over the second region. The fourth conductive layer is in contact with the insulating layer, the third conductive layer, and the second region. |
| US10263112B2 |
Vertical non-planar semiconductor device for system-on-chip (SoC) applications
Vertical non-planar semiconductor devices for system-on-chip (SoC) applications and methods of fabricating vertical non-planar semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a substrate, the semiconductor fin having a recessed portion and an uppermost portion. A source region is disposed in the recessed portion of the semiconductor fin. A drain region is disposed in the uppermost portion of the semiconductor fin. A gate electrode is disposed over the uppermost portion of the semiconductor fin, between the source and drain regions. |
| US10263109B2 |
Semiconductor devices including silicide regions and methods of fabricating the same
A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces. |
| US10263105B2 |
High voltage semiconductor device
In an embodiment, on an n−type SiC layer on an n+-type SiC semiconductor substrate and a p+ layer selectively formed on the n−type SiC layer, a p base layer is formed on which, a p+ contact layer is selectively formed. From a surface, an n counter layer penetrates the p base layer to the n−type SiC layer. A gate electrode layer is disposed via a gate insulating film, on an exposed surface of the p base layer between the p+ contact layer and the n counter layer; and a source electrode contacts the p+ contact layer and the p base layer. In a back surface, a drain electrode is disposed. A portion of the p+ layers are joined at a region of a drain electrode side of the n counter layer, by a joining unit and a p+ layer contacts a drain electrode side of the p+ layer. |
| US10263104B2 |
FET transistor on a III-V material structure with substrate transfer
A method of manufacturing a III-V semiconductor circuit; the method comprising: forming a first layer of a III-V material on a growth substrate; forming a second layer of a III-V material on the first layer of III-V material; forming a FET transistor having a source electrode and a drain electrode in contact with a top surface of the second layer of a III-V material; forming a top dielectric layer above the FET transistor; forming a metal layer above the top dielectric layer, wherein said metal layer is connected to said source electrode; attaching a handle substrate to a top surface of the metal layer; removing the growth substrate from the bottom of the first layer of a III-V material; and forming a bottom dielectric layer on the bottom of the first layer of a III-V material. |
| US10263103B2 |
Semiconductor apparatus
A semiconductor apparatus includes an electron transit layer formed of a nitride semiconductor over a substrate; an electron supply layer formed of a nitride semiconductor including In over the electron transit layer; a cap layer formed of a nitride semiconductor over the electron supply layer; an insulation film formed over the cap layer; a source electrode and a drain electrode formed over the electron transit layer or the electron supply layer; and a gate electrode formed over the cap layer. A quantum well is formed by the cap layer. |
| US10263102B2 |
Semiconductor device and method of manufacturing the same
An object of the present invention is to provide a semiconductor device capable of preventing an occurrence of oscillation of voltage and current and a method of manufacturing the same. A semiconductor device according to the present invention includes an n type silicon substrate and a first n type buffer layer formed in a back surface of the n type silicon substrate and having a plurality of peaks of concentration of protons whose depths from the back surface are different from each other. In the first n type buffer layer, a concentration gradient of the protons from the peak located in a position closer to the back surface toward the surface of the n type silicon substrate is smaller than a concentration gradient of the protons from the peak located in a position farther away from the back surface toward the surface. |
| US10263100B1 |
Buffer regions for blocking unwanted diffusion in nanosheet transistors
Embodiments of the invention are directed to a method of fabricating a semiconductor device. A non-limiting example of the method includes performing fabrication operations to form a nanosheet field effect transistor device. The fabrication operations include forming a sacrificial nanosheet and a channel nanosheet over a substrate, forming a diffusion barrier layer between the sacrificial nanosheet and the channel nanosheet, wherein a diffusion coefficient of the diffusion barrier layer is selected to substantially prevent a predetermined semiconductor material from diffusing through the diffusion barrier layer. |
| US10263097B2 |
Method of semiconductor arrangement formation
Methods of semiconductor arrangement formation are provided. A method of forming the semiconductor arrangement includes forming a first nucleus on a substrate in a trench or between dielectric pillars on the substrate. Forming the first nucleus includes applying a first source material beam at a first angle relative to a top surface of the substrate and concurrently applying a second source material beam at a second angle relative to the top surface of the substrate. A first semiconductor column is formed from the first nucleus by rotating the substrate while applying the first source material beam and the second source material beam. Forming the first semiconductor column in the trench or between the dielectric pillars using the first source material beam and the second source material beam restricts the formation of the first semiconductor column to a single direction. |
| US10263091B2 |
Multiple gate field effect transistors having oxygen-scavenged gate stack
A method includes forming a silicon cap layer on a semiconductor fin, forming an interfacial layer over the silicon cap layer, forming a high-k gate dielectric over the interfacial layer, and forming a scavenging metal layer over the high-k gate dielectric. An anneal is then performed on the silicon cap layer, the interfacial layer, the high-k gate dielectric, and the scavenging metal layer. A filling metal is deposited over the high-k gate dielectric. |
| US10263087B2 |
Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region
A memory is described. Generally, the memory includes a number of non-planar multigate transistors, each including a channel of semiconducting material overlying a surface of a substrate and electrically connecting a source and a drain, a tunnel dielectric layer overlying the channel on at least three sides thereof, and a multi-layer charge-trapping region overlying the tunnel dielectric layer. In one embodiment, the multi-layer charge-trapping region includes a first deuterated layer overlying the tunnel dielectric layer and a first nitride-containing layer overlying the first deuterated layer. Other embodiments are also described. |
| US10263085B2 |
Transistor with source field plates and non-overlapping gate runner layers
A transistor device includes a field plate that extends from a source runner layer and/or a source contact layer. The field plate can be coplanar with and/or below a gate runner layer. The gate runner layer is routed away from a region directly above the gate metal layer by a gate bridge, such that the field plate can extend directly above the gate metal layer without being interfered by the gate runner layer. Coplanar with the source runner layer or the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. By vertically overlapping the metal gate layer and the field plate, the disclosed HEMT device may achieve significant size efficiency without additional routings. |
| US10263083B2 |
Thin film transistor array substrate and display panel thereof
A thin film transistor array substrate comprises: a substrate, a plurality of thin film transistors disposed on the substrate, wherein each of the plurality of thin film transistors comprises: a gate electrode structure, an isolate protective layer disposed on the gate electrode structure, an active layer disposed on the isolate protective layer, a source electrode layer disposed on a side of the active layer and forming an ohmic contact with the active layer, a drain electrode layer disposed on other side of the active layer and forming an ohmic contact with the active layer, a first concentration doping layer disposed on the active layer and between the source electrode layer and the drain electrode layer, a passivation layer covered onto the active layer, the source electrode layer and the drain electrode layer, and a pixel electrode layer covered onto the passivation layer and the drain electrode layer. |
| US10263080B2 |
Transistor with fluorinated graphene spacer
An integrated circuit (IC) device may include a semiconductor structure. The semiconductor structure may include a source contact, a drain contact, and a gate. A first fluorocarbon spacer may be between the gate and the source contact. A second fluorocarbon spacer may be between the gate and the drain contact. |
| US10263079B2 |
Apparatus and methods for forming a modulation doped non-planar transistor
Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed, which may include forming a modulation doped heterostructure, comprising forming an active portion having a first bandgap and forming a delta doped portion having a second bandgap. |
| US10263077B1 |
Method of fabricating a FET transistor having a strained channel
Method for fabricating at least one FET transistor (100a, 100b) comprising: fabrication of at least one first semiconducting portion (114) that will form a channel of the FET transistor, fabrication of second semiconducting portions (122, 124, 126) that will be used to form source and drain regions, such that the first semiconducting portion is located between first ends of the second semiconducting portions and such that second ends of the second semiconducting portions opposite the first ends, are in contact with bearing surfaces, and comprising at least one semiconducting material for which the crystalline structure or the atomic organisation, can be modified when a heat treatment is applied to it; heat treatment generating a modification to the crystalline structure of the semiconducting material of the second semiconducting portions and creating a strain (128) in the first semiconducting portion. |
| US10263072B2 |
Integrated RF front end system
Systems and methods are disclosed for integrating functional components of front-end modules for wireless radios. Front-end modules disclosed may be dual-band front-end modules for use in 802.11ac-compliant devices. In certain embodiments, integration of front-end module components on a single die is achieved by implementing a high-resistivity layer or substrate directly underneath, adjacent to, and/or supporting SiGe BiCMOS technology elements. |
| US10263067B2 |
Chip capacitor circuit and structure therefor
A radio frequency (RF) chip capacitor circuit and structure are provided. The circuit and structure include a plurality of capacitors connected in series. Each capacitor of the plurality includes a first plate formed from a first metal layer and a second plate formed from a second metal layer. A first two adjacent capacitors of the plurality include first plates formed in a first contiguous portion of the first metal layer or second plates formed in a second contiguous portion of the second metal layer. Each capacitor of the plurality may include a dielectric layer disposed between the first plate and the second plate. |
| US10263065B2 |
Metal resistor forming method using ion implantation
Methods of forming a metal resistor are provided. The methods may include: depositing a metal layer, e.g., tungsten, on a substrate; and forming the metal resistor by implanting a semiconductor species, e.g., silicon and/or germanium, into the metal layer to form a semiconductor-metal alloy layer from at least a portion of the metal layer. In certain embodiments, an adhesion layer may be deposited by ALD prior to metal layer depositing. The metal resistor has a sheet resistance that remains substantially constant prior to and after subsequent annealing. |
| US10263062B2 |
Flexible display
A flexible display is disclosed. In one aspect, the display includes at least one first pattern including a plurality of display elements configured to display an image and extending in a first direction. The display device also includes at least one second pattern extending in a second direction and overlapping at least a portion of the first pattern. The second pattern has a curved shape in the first direction and the second direction crosses the first direction. The first and second patterns form at least one cavity region defining a space therebetween and the first and second patterns form a mesh structure. |
| US10263059B2 |
Light emitting device
A light emitting device is provided which can prevent a change in gate voltage due to leakage or other causes and at the same time can prevent the aperture ratio from lowering. A capacitor storage is formed from a connection wiring line, an insulating film, and a capacitance wiring line. The connection wiring line is formed over a gate electrode and an active layer of a TFT of a pixel, and is connected to the active layer. The insulating film is formed on the connection wiring line. The capacitance wiring line is formed on the insulating film This structure enables the capacitor storage to overlap the TFT, thereby increasing the capacity of the capacitor storage while keeping the aperture ratio from lowering. Accordingly, a change in gate voltage due to leakage or other causes can be avoided to prevent a change in luminance of an OLED and flickering of screen in analog driving. |
| US10263057B2 |
Organic light emitting display panel and manufacturing method thereof
The present disclosure discloses an OLED panel, including: a substrate and a driving thin film transistor, a switching thin film transistor, a storage capacitor, an organic light emitting device, and a light emitting device formed on the substrate, an external voltage signal is stored in the storage capacitor via the switching thin film transistor, the external voltage signal controls a magnitude of on-current of the driving thin film transistor to control the gray scale of the organic light emitting device. The present disclosure further discloses a manufacturing method of OLED panel. In the present disclosure, the drain of the low temperature polysilicon thin film transistor is in contact with the bottom electrode of the organic light emitting device so that the current supplied to the organic light emitting device is stabilized; metal-oxide-semiconductor thin-film transistor has a low leakage current, so that a better circuit-closing effect can be achieved. |
| US10263053B2 |
Organic light-emitting diode display and method for manufacturing the same
Provided is an OLED display that includes, for example, a substrate having a plurality of pixel regions defined in a matrix; a thin film transistor in each pixel region; an anode connected to the thin film transistor in each pixel region; and a bank covering an edge of the anode and having an inside boundary at a first distance from the edge of the anode and an outside boundary at a second distance from the edge of the anode. |
| US10263052B2 |
Display panel, display method thereof and manufacturing method thereof
A display panel, a display method thereof, and a manufacturing method thereof are provided. The display panel includes a plurality of sub-pixel units. Each of the sub-pixel units includes a first display area and a second display area; the first display area includes an active emitting display unit; and the second display area is configured to switch between a transparent state and an opaque state. |
| US10263046B2 |
Organic EL display panel and method of manufacturing organic EL display panel
An organic EL display panel having a plurality of pixels arranged, the pixels each including blue, green and red sub-pixels, includes: a substrate; a first pixel electrode layer, a first hole injection layer, a first hole transport layer and a blue organic light-emitting layer provided in regions of the blue sub-pixels over the substrate in this order from the substrate side; a second pixel electrode layer, a second hole injection layer, a second hole transport layer and a green organic light-emitting layer provided in regions of the green sub-pixels over the substrate in this order from the substrate side; a third pixel electrode layer, a third hole injection layer, a third hole transport layer and a red organic light-emitting layer provided in regions of the red sub-pixels over the substrate in this order from the substrate side; and a counter electrode layer provided over the blue, green and red organic light-emitting layers. |
| US10263042B2 |
Organic photoelectric device and image sensor
An organic photoelectric device includes a first electrode and a second electrode facing each other, and an active layer between the first electrode and the second electrode, wherein the active layer includes an n-type semiconductor compound that is transparent in a visible ray region and represented by Chemical Formula 1, and a p-type semiconductor compound having a maximum absorption wavelength in a wavelength region of about 500 nm to about 600 nm of a visible ray region. |
| US10263040B2 |
Memory device and method of manufacturing the same
A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer. The first memory cell has a side surface slope so as to have a width gradually decreasing toward its upper portion. |
| US10263039B2 |
Memory cells having resistors and formation of the same
The present disclosure includes memory cells having resistors, and methods of forming the same. An example method includes forming a first conductive line, forming a second conductive line, and forming a memory element between the first conductive line and the second conductive line. Forming the memory element can include forming one or more memory materials, and forming a resistor in series with the one or more memory materials. The resistor can be configured to reduce a capacitive discharge through the memory element during a state transition of the memory element. |
| US10263037B2 |
Electronic device
An electronic device may be provided to include: first and second active regions arranged adjacent to each other in a second direction; a gate structure extended in the second direction; a first source region and a first drain region formed in the first active region; a second source region and a second drain region formed in the second active region; a source line contact formed over the first and second source regions and connected to the first and second source regions; a source line connected to the source line contact over the source line contact and extended in a first direction; first and second stacked structures formed over the first and second drain regions; and first and second bit lines formed over the first and second stacked structures, wherein the first and second bit lines are extended in the first direction. |
| US10263035B2 |
Magnetoresistive random access memory devices and methods of manufacturing the same
An MRAM device includes a lower electrode on a substrate, an MTJ structure on the lower electrode, a metal oxide pattern on the MTJ structure, a conductive pattern on at least a portion of a sidewall of the metal oxide pattern, and an upper electrode on the metal oxide pattern and the conductive pattern. The conductive pattern has a thickness varying along the sidewall of the metal oxide pattern in a plan view. |
| US10263032B2 |
Photodiode with different electric potential regions for image sensors
An image sensor pixel is disclosed. The pixel may include a photodiode having a first region with a first potential and a second region with a second, higher potential, with the second region being offset in depth from the first region in a semiconductor chip. A storage node may be positioned at substantially the same depth as the second region of the photodiode. A storage gate may be operable to transfer charge between the photodiode and the storage node. |
| US10263029B2 |
Photoelectric conversion device and manufacturing method of the photoelectric conversion device
A manufacturing method includes a first process for forming a first gate electrode for a first MOS transistor and a second gate electrode for a second MOS transistor on a substrate including a semiconductor region defined by an insulator region for element isolation, a second process for masking a portion located above the semiconductor region of the first gate electrode to introduce an impurity to a source-drain region of the first MOS transistor, and a third process for forming a first conductor member being in contact with the portion of the first gate electrode through a first hole disposed on an insulator member covering the substrate and a second conductor member being in contact with the second gate electrode through a second hole disposed on the insulator member. |
| US10263022B2 |
RGBZ pixel unit cell with first and second Z transfer gates
An image sensor is described having a pixel array. The pixel array has a unit cell that includes visible light photodiodes and an infra-red photodiode. The visible light photodiodes and the infra-red photodiode are coupled to a particular column of the pixel array. The unit cell has a first capacitor coupled to the visible light photodiodes to store charge from each of the visible-light photodiodes. The unit cell has a readout circuit to provide the first capacitor's voltage on the particular column. The unit cell has a second capacitor that is coupled to the infra-red photodiode through a first transfer gate transistor to receive charge from the infra-red photodiode during a time-of-flight exposure. The first capacitor is coupled to the infra-red photodiode through a second transfer gate transistor to receive charge from the infra-red photodiode during the time-of-flight exposure. |
| US10263021B2 |
Global shutter pixels having shared isolated storage capacitors within an isolation structure surrounding the perimeter of a pixel array
Disclosed herein is an electronic device including an integrated circuit substrate, with a pixel array area within the integrated circuit substrate. A first deep trench isolation structure is formed in the integrated circuit substrate about a perimeter of the pixel array area. First, second, third, and fourth pixels are within the pixel array area and spaced apart from one another. A storage capacitor area is within the integrated circuit substrate and interior to the first deep trench isolation structure. A second deep trench isolation structure is formed in the integrated circuit substrate about a perimeter of the storage capacitor area. The second deep trench isolation structure may serve to electrically isolate the storage capacitor area from the first, second, third, and fourth pixels. |
| US10263019B2 |
Flexible panel and method for manufacturing the same
A flexible panel includes a substrate, a first insulating layer, a second insulating layer, a sacrificial layer, and a metal wiring layer. The substrate has an active area, a peripheral area, and an intermediate area. The first insulating layer is in the three areas of the substrate, and the first insulating layer in the intermediate area has a first pattern. The second insulating layer is on the first insulating layer. The second insulating layer in the intermediate area has a first opening extending along a first direction, so that the second insulating layer does not cover the first pattern of the first insulating layer. The sacrificial layer is between the first insulating layer and the second insulating layer in the intermediate area, and does not cover the first pattern of the first insulating layer. The metal wiring layer extends between the active area and the peripheral area. |
| US10263017B2 |
Pixel structure, display panel and manufacturing method of pixel structure
A pixel structure, a display panel and a manufacturing method of the pixel structure are disclosed. The pixel structure includes: gate lines extending in parallel in a first direction; data lines extending in parallel in a second direction; and a plurality of pixel units defined by the gate lines and the data lines. One of the data lines is disposed between two pixel units which are adjacent to each other in the first direction, and two of the gate lines are disposed between two pixel units which are adjacent to each other in the second direction. Each of the pixel units comprises two pixel regions which are arranged side by side in the first direction, each of the pixel regions comprises a pixel electrode, and each of the pixel units comprises a unitary common electrode which covers the two pixel regions. |
| US10263016B2 |
Active matrix substrate and method for producing the same
An active matrix substrate includes a first TFT (10), a second TFT (20) disposed per pixel, and a circuit including the first TFT. The first and second TFTs each include a gate electrode (102A, 102B), a gate insulating layer (103), an oxide semiconductor layer (104A, 104B), and source and drain electrodes in contact with an upper surface of the oxide semiconductor layer. The oxide semiconductor layer (104A, 104B) has a stacked structure including a first semiconductor layer (104e, 104c) in contact with the source and drain electrodes and a second semiconductor layer that is disposed on a substrate-side of the first semiconductor layer and that has a smaller energy gap than the first semiconductor layer. The oxide semiconductor layers (104A) and (104B) are different from each other in terms of the composition and/or the number of stacked layers. The first TFT has a larger threshold voltage than the second TFT. |
| US10263014B2 |
Fin-type field-effect transistor
This invention relates to a fin field-effect transistor semiconductor structure. The method of forming the semiconductor structure can include patterning a plurality of precursor fins on a semiconductor layer having a layer portion A and a layer portion B. The semiconductor layer can be located on a substrate. The layer portion B can be selectively etched to form B fins and a top half of precursor fins. The layer portion A can be selectively etched to form A fins and the substrate can be etched to form a bottom half of the decoupling fins. The precursor fins can be removed to expose the A fins, the decoupling fins, and the B fins. One of the A fins and the B fins can form n-type fins and the other can form p-type fins. |
| US10263013B2 |
Method of forming an integrated circuit (IC) with hallow trench isolation (STI) regions and the resulting IC structure
Disclosed is an integrated circuit (IC) formation method, wherein trenches are formed within a semiconductor layer to define semiconductor mesa(s). Instead of immediately filling the trenches with an isolation material and performing a planarizing process to complete the STI regions prior to device formation, the method initially only form sidewall spacers within the trenches on the exposed sidewalls of the semiconductor mesa(s). After the sidewall spacers are formed, device(s) (e.g., field effect transistor(s), silicon resistor(s), etc.) are formed using the semiconductor mesa(s) and, optionally, additional device(s) (e.g., polysilicon resistor(s)) can be formed within the trenches between adjacent semiconductor mesas. Subsequently, middle of the line (MOL) dielectrics (e.g., a conformal etch stop layer and a blanket interlayer dielectric (ILD) layer) are deposited over the device(s), thereby filling any remaining space within the trenches and completing the STI regions. Also disclosed is an IC structure formed using the method. |
| US10263010B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device includes a first semiconductor layer, a second semiconductor layer spaced apart from the first semiconductor layer and disposed on the first semiconductor layer, a gate stack structure disposed on the second semiconductor layer, a third semiconductor layer positioned between the first and second semiconductor layers, and a channel pillar passing through the gate stack structure, the second semiconductor layer and the third semiconductor layer and extending into the first semiconductor layer. |
| US10263004B2 |
Semiconductor device and method of manufacturing
The present disclosure relates to a method of forming sidewall spacers configured to improve dielectric fill between adjacent gate structures. In some embodiments, the method may be performed by depositing a sidewall spacer material over a first gate structure and a second gate structure. A first etching process is performed on the sidewall spacer material to form a first intermediate sidewall spacer surrounding the first gate structure and a second sidewall spacer surrounding the second gate structure. A masking material is formed over the substrate. Parts of the first intermediate sidewall spacer protrude outward from the masking material, while the second sidewall spacer is completely covered by the masking material. A second etching process is then performed on the parts of the first intermediate sidewall spacer protruding outward from the masking material to form a first sidewall spacer recessed below an uppermost surface of the first gate structure. |
| US10263001B2 |
Method of forming semiconductor memory device
A method of forming semiconductor memory device including following steps. Firstly, a substrate having a memory cell region and a peripheral region is provided, and a first semiconductor layer is formed on the substrate within the periphery region. Next, an insulating layer and a second semiconductor layer are formed on the substrate, and the second semiconductor layer covers the substrate, the first semiconductor layer and the insulating layer. Then, a sacrificial layer is formed on the second semiconductor layer, wherein top surfaces of the sacrificial layer within the memory cell region and the periphery region are coplanar. Following these, a removing process is performed to remove the sacrificial layer, the second semiconductor layer and the insulating layer, to expose the first semiconductor layer. After that, a top surface of the first semiconductor layer is leveled with a top surface of the second semiconductor layer. |
| US10263000B2 |
Device comprising capacitor and forming method thereof
A device including a capacitor includes an isolation structure, a first control gate, a first selective gate and a first dielectric layer. The isolation structure is disposed in a substrate. The first control gate and the first selective gate are disposed directly above the isolation structure. The first dielectric layer is vertically sandwiched by the first control gate and the first selective gate, thereby constituting the capacitor. The present invention also provides a method of forming the device including the capacitor. |
| US10262997B2 |
High-voltage LDMOSFET devices having polysilicon trench-type guard rings
A high-voltage semiconductor device including a semiconductor layer formed on a substrate is provided. A first well region having a first conductivity type and a second well region having a second conductivity type are formed in the semiconductor layer. Source and drain regions are respectively formed in the first and second well regions. A gate structure is disposed on the semiconductor layer. A first isolation trench structure is disposed in the semiconductor layer and surrounds the first and second well regions. The first isolation trench structure includes a first polysilicon layer filling a first trench and having the second conductivity type, a first heavy doping region formed in an upper portion of the first polysilicon layer and having the second conductivity type, and a first insulating liner disposed on sidewalls of the first trench and surrounding the first polysilicon layer. |
| US10262996B2 |
Third type of metal gate stack for CMOS devices
A third type of metal gate stack is provided above an isolation structure and between a replacement metal gate n-type field effect transistor and a replacement metal gate p-type field effect transistor. The third type of metal gate stack includes at least three different components. Notably, the third type of metal gate stack includes, as a first component, an n-type workfunction metal layer, as a second component, a p-type workfunction metal layer, and as a third component, a low resistance metal layer. In some embodiments, the uppermost surface of the first, second and third components of the third type of metal gate stack are all substantially coplanar with each other. In other embodiments, an uppermost surface of the third component of the third type of metal gate stack is non-substantially coplanar with an uppermost surface of both the first and second components of the third type of metal gate stack. |
| US10262994B2 |
FinFET LDMOS devices with additional dynamic control
A FinFET semiconductor device having semiconductor body including a source region of a first type, and a drain region of a second type, and a drain-region shallow trench isolation (STI) disposed in the drain region. The device includes a plurality of fins attached to the semiconductor body and extending across the semiconductor body, a channel gate disposed over a section of the plurality of fins; a supplemental gate disposed on the drain-region STI. |
| US10262988B2 |
Electrostatic discharge protection device
An electrostatic discharge protection device and a method of making the same. The device includes a device area located on a semiconductor substrate. The device also includes an array of coextensive, laterally spaced fingers located within the device area. Each finger includes an elongate source and an elongate drain separated by an elongate gate. The fingers are electrically connected in parallel for conducting an electrostatic discharge current during an electrostatic discharge event. The device further includes a plurality of body contact regions. A layout of the body contact regions is graded such that a greater number of the body contact regions, larger body contact regions, or both are located towards a periphery of the device area than towards a central part of the device area. The layout of the body contact regions may encourage triggering of the electrostatic discharge protection device within the central part of the device area. |
| US10262987B2 |
Electrostatic discharge protection circuit
The present invention provides an ESD protection circuit electrically connected between a high voltage power line and a low voltage power line, and the ESD protection circuit includes a bipolar junction transistor (BJT) and a trigger source. A collector of the BJT is electrically connected to the high voltage power line, and an emitter and a base of the BJT are electrically connected to the low voltage power line. The trigger source is electrically connected between the base of the BJT and the high voltage power line. |
| US10262986B2 |
Protection device and method for fabricating the protection device
A protection device as provided includes a doped well with a first-type impurity, formed in a substrate. A first semiconductor terminal with a second-type impurity is formed on the doped well. A second semiconductor terminal with a second-type impurity is formed on the doped well separating from the first semiconductor terminal. The first semiconductor terminal is connected to a voltage level and a second semiconductor terminal is connected to a ground voltage. |
| US10262985B2 |
Circuits and methods for lowering leakage in ultra-low-power MOS integrated circuits
A block of logic gates has MOS transistors whose body terminals are connected with a body voltage rail and whose source terminals are connected with a logic reference voltage rail. The logic reference voltage rail is connected to the body voltage rail via a resistor. The resistor creates a negative feedback loop for leakage currents that stabilizes a reverse body bias voltage and reduces the influence of temperature, voltage, and process variations.The block may be NMOS, PMOS, or CMOS. In the case of CMOS, there are two body voltage rails, powered by a voltage source, two logic reference voltage rails, and two resistors. The reverse body bias voltages over the two resistors may be stabilized by decoupling capacitors. The two resistors may be trimmable. The resistors may be calibrated such that leakage currents are at a minimum value and the logic gates can switch just fast enough. |
| US10262982B2 |
Integrated circuits with standard cell
The present invention provides an integrated circuit with a standard cell of an inverter. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Two long contact plugs disposed at one side of the gate structure; two short contact plugs disposed at the other side of the gate structure; a gate contact plug disposed on the gate structure; Plural via plugs disposed on the long contact plugs, the short contact plugs and the gate contact plugs; A metal layer includes the first metal line, the second metal line, a third metal line and a fourth metal line. |
| US10262981B2 |
Integrated circuit, system for and method of forming an integrated circuit
A method of forming an integrated circuit is disclosed. The method includes generating, by a processor, a layout design of the integrated circuit, outputting the integrated circuit based on the layout design, and removing a portion of a conductive structure of the integrated circuit to form a first conductive structure and a second conductive structure. Generating the layout design includes generating a standard cell layout having a set of conductive feature layout patterns, placing a power layout pattern with the standard cell layout according to at least one design criterion, and extending at least one conductive feature layout pattern of the set of conductive feature layout patterns in at least one direction to a boundary of the power layout pattern. The power layout pattern includes a cut feature layout pattern. The cut feature layout pattern identifies a location of the removed portion of the conductive structure of the integrated circuit. |
| US10262980B2 |
LED module
The invention relates to an LED module with a circuit which comprises an LED (106) and a resonant circuit (106, 108, 110) for coupling in energy for operation of the LED, wherein the circuit is formed without connections and is fully encapsulated in the LED module. |
| US10262966B2 |
Methods for surface attachment of flipped active components
An active substrate includes a plurality of active components distributed over a surface of a destination substrate, each active component including a component substrate different from the destination substrate, and each active component having a circuit and connection posts on a process side of the component substrate. The connection posts may have a height that is greater than a base width thereof, and may be in electrical contact with the circuit and destination substrate contacts. The connection posts may extend through the surface of the destination substrate contacts into the destination substrate connection pads to electrically connect the connection posts to the destination substrate contacts. |
| US10262965B2 |
Display device and manufacturing method thereof
A display device includes: a flexible substrate having a display area for displaying an image and a peripheral area outside the display area; a first pad electrode in the peripheral area of the flexible substrate; and a driver connected to the first pad electrode. The driver includes: a circuit board including a driving circuit; a second pad electrode on one side of the circuit board and facing the first pad electrode; a convex structure on one side of the second pad electrode and having an oval cross-section; and a bump electrode on one side of the convex structure and connected to the first pad electrode. The bump electrode includes a column covering the convex structure and a convex portion extending from one side of the column and protruding to the first pad electrode. |
| US10262963B2 |
Conductive barrier direct hybrid bonding
A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region. |
| US10262961B2 |
Semiconductor devices having discretely located passivation material, and associated systems and methods
Semiconductor devices having discretely located passivation material are disclosed herein. In one embodiment, a semiconductor device assembly can include a bond pad having a bonding surface with a process artifact. A passivation material can be positioned to at least partially fill a portion of the process artifact. A conductive structure can be positioned to extend across the bonding surface of the bond pad. |
| US10262957B2 |
Millimeter wave integrated circuit with ball grid array package including transmit and receive channels
An integrated circuit (IC) package includes an IC die and a wave channel that electrically couples the IC die to a solder ball array. The wave channel is configured to resonate at an operating frequency band of the IC die. |
| US10262953B2 |
Semiconductor device
A semiconductor device includes a heat dissipating unit that includes a primary part made of a first metal material and an embedded part that is embedded in a front surface of the primary part and that is made of a second metal material, a front surface of the heat dissipating unit having a mounting region on which a rear surface of a semiconductor element substrate is mounted so as to dissipate heat generated by the semiconductor element; and a sealing member that seals the semiconductor element, the substrate, and a sealed region of the front surface of the heat dissipating unit, wherein the embedded part is formed in the sealed region, and an absolute difference of the linear expansion coefficient of the second metal material and that of the sealing member is less than or equal to 25% of a value of the linear expansion coefficient of the sealing member. |
| US10262951B2 |
Radiation hardened microelectronic chip packaging technology
A novel radiation hardened chip package technology protects microelectronic chips and systems in aviation/space or terrestrial devices against high energy radiation. The proposed technology of a radiation hardened chip package using rare earth elements and mulitlayered structure provides protection against radiation bombardment from alpha and beta particles to neutrons and high energy electromagnetic radiation. |
| US10262950B1 |
Visible alignment markers/landmarks for CAD-to-silicon backside image alignment
A metal oxide semiconductor (MOS) integrated circuit (IC) has a plurality of fiducial standard cells of different cell sizes. The different cell sizes are non-equally utilized. The plurality of fiducial standard cells are placed to have a random offset from a uniform global placement pattern. Each of the fiducial standard cells has at least four power rails and various sets of active regions. The power rails extend in a first direction. The active regions are provided adjacent to the power rails but are disconnected from contacts and interconnects and thus do not draw power from the power rails. Instead, the active regions are disjoint and collinear thereby creating islands of active regions among spacings of inactive regions. These inactive regions more easily allow electromagnetic radiation to pass through thereby allowing the MOS fiducial standard cell to be visible for a CAD-to-silicon backside image alignment even with 7 nm feature sizes. |
| US10262947B2 |
Active chip on carrier or laminated chip having microelectronic element embedded therein
A structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within the cavity. The first chip may have vias extending from the cavity to the front surface and via conductors within these vias serving to connect an additional microelectronic element to the active elements of the first chip. The structure may have a volume comparable to that of the first chip alone and yet provide the functionality of a multi-chip assembly. A composite chip incorporating a body and a layer of semiconductor material mounted on a front surface of the body similarly may have a cavity extending into the body from the rear surface and may have an additional microelectronic element mounted in such cavity. |
| US10262939B2 |
Configurable routing for packaging applications
Various structures having a fuse and methods for forming those structures are described. An embodiment is a method. The method comprises attaching a first die to a first side of a component using first electrical connectors. After the attaching, at least one of (i) the first die comprises a first fuse, (ii) the first side of the component comprises a second fuse, (iii) a second side of the component comprises a third fuse, the second side being opposite the first side, or (iv) a combination thereof. The method further comprises after the attaching the first die to the first side of the component, blowing the first fuse, the second fuse, the third fuse, or a combination thereof. |
| US10262937B2 |
Integrated circuit device
An integrated circuit device includes at least one fin-type active region, a gate line on the at least one fin-type active region, and a source/drain region on the at least one fin-type active region at at least one side of the gate line. A first conductive plug is connected to the source/drain region and includes cobalt. A second conductive plug is connected to the gate line and spaced apart from the first conductive plug. A third conductive plug is connected to each of the first conductive plug and the second conductive plug. The third conductive plug electrically connects the first conductive plug and the second conductive plug. |
| US10262936B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device according to the present embodiment includes a stacked body having an end which is step-shaped and a contact in each of the steps of the end. Each of the steps includes alternating a plurality of conductive layers and a plurality of insulating layers. The contact includes a plurality of conductive films contacting each of the conductive layers, and a plurality of insulating films contacting each of the insulating layers, the insulating films being provided between the conductive films. |
| US10262934B2 |
Three plate MIM capacitor via integrity verification
A three plate MIM capacitor structure includes a three plate MIM capacitor, a first wire in a metal layer above/below the three plate MIM, a second wire below/above the three plate MIM, a third wire below/above the three plate MIM, a first via connected to the first test wire, a second via connected to a middle plate of the three plate MIM, and a third via connected to the top and bottom plates of the three plate MIM. The test structure may verify the integrity the MIM capacitor by applying a potential to the first test wire, applying ground potential to both the second test wire and the third test wire, and detecting leakage current across the first wire and the second and third wires or detecting leakage current across the second wire and the third wire. |
| US10262933B2 |
Semiconductor package
A semiconductor package includes a substrate, a first semiconductor chip and a second semiconductor chip adjacent to each other on the substrate, and a plurality of bumps on lower surfaces of the first and second semiconductor chips. The first and second semiconductor chips have facing first side surfaces and second side surfaces opposite to the first side surfaces. The bumps are arranged at a higher density in first regions adjacent to the first side surfaces than in second regions adjacent to the second side surfaces. |
| US10262929B2 |
Semiconductor device with lead frame
A semiconductor device and a semiconductor device manufacturing method that may prevent positional displacement of an electronic component mounted on a lead frame. The semiconductor device includes a lead frame, and an electronic component that has a protruding or recessed structure at a bonding face that bonds to the lead frame and is bonded to the lead frame, in a state in which a portion of the lead frame is fitted together with the protruding or recessed structure. |
| US10262925B2 |
Semiconductor device and method of manufacturing semiconductor device
A semiconductor device includes a base plate to which a stacked substrate is bonded, the stacked substrate being mounted on a semiconductor chip. The semiconductor device further includes a heat sink mounted to the base plate, via thermal paste and a metal ring. A center hole of the metal ring is provided to face the semiconductor chip and the thermal paste fills the center hole. Further, the metal ring is formed using a material having about a same hardness as the heat sink, or a material having a lower hardness than the hardness of the heat sink. |
| US10262923B2 |
Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus
A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side. |
| US10262921B2 |
Semiconductor module
A semiconductor module includes a baseplate, a cover element attached to the baseplate so that detaching the cover element from the baseplate requires material deformations, and a semiconductor element in a room defined by the baseplate and the cover element. The semiconductor element is in a heat conductive relation with the baseplate and an outer surface of the baseplate is provided with laser machined grooves suitable for conducting heat transfer fluid. The laser machining makes it possible to make the grooves after the semiconductor module has been assembled. Therefore, regular commercially available semiconductor modules can be modified, with the laser machining, to semiconductor modules as disclosed. |
| US10262915B2 |
Thermally enhanced semiconductor package with thermal additive and process for making the same
The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a first mold compound component, and a thermally enhanced mold compound component. The first mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally enhanced mold compound component includes a lower portion filling a lower region of the cavity and residing over the upper surface of the thinned flip chip die, and an upper portion filling an upper region of the cavity and residing over the lower portion. A first average thermal conductivity of the lower portion is at least 1.2 times greater than a second average thermal conductivity of the upper portion. |
| US10262914B2 |
Resin composition for encapsulation, and semiconductor device
Provided is a resin composition for encapsulation used for encapsulating a power semiconductor element formed from SiC, GaN, Ga2O3, or diamond, the resin composition for encapsulation including a thermosetting resin (A) and silica (B), in which the silica (B) includes Fe, the content of Fe is equal to or less than 220 ppm with respect to the total amount of the silica (B), and the resin composition is in a granular form, a tablet form, or a sheet form. |
| US10262913B2 |
Wafer level package solder barrier used as vacuum getter
An electronic device and methods of manufacture thereof. One or more methods may include providing a lid wafer having a cavity and a surface surrounding the cavity and a device wafer having a detector device and a reference device. In certain examples, a solder barrier layer of titanium material may be deposited onto the surface of the lid wafer. The solder barrier layer of titanium material may further be activated to function as a getter. In various examples, the lid wafer and the device wafer may be bonded together using solder, and the solder barrier layer of titanium material may prevent the solder from contacting the surface of the lid wafer. |
| US10262910B2 |
Method of feature exaction from time-series of spectra to control endpoint of process
Methods and systems for using a time-series of spectra to identify endpoint of an etch process. One method includes accessing a virtual carpet that is formed from a time-series of spectra for the etch process collected during a training operation. And, running a fabrication etch process on a fabrication wafer, such that while the fabrication etch process is performed portions of a carpet defined from a time-series of spectral is generated for the fabrication etch process. Then, comparing the portions of the carpet of the fabrication etch process to the virtual carpet. End pointing is processed for the fabrication etch process when said comparing indicates that a desired metric has been reached for the fabrication wafer. In one example, said portions of the carpet include a current frame of captured spectra and at least one previous frame of captured spectra. The portions of the carpet of the fabrication etch process are fitted to the virtual carpet to identify a virtual frame number and associated floating parameters that are used in a correlation to predicted a value for the metric. Further, each of the carpets produced during the training operation and the virtual carpet are defined by a polynomial. The coefficients of the carpets produced during the training operation are a subset of the coefficients of the polynomial of the virtual carpet. |
| US10262909B2 |
Semiconductor device and method for manufacturing the same
Semiconductor layer is formed on semiconductor substrate. Semiconductor layer has a plurality of well regions in a surface remote from semiconductor substrate. Semiconductor layer includes drift region in addition to the plurality of well regions. The plurality of well regions each include body region, source region, and contact region. Source region is in contact with body region. Contact region is in contact with both body region and source region. Body region, source region, and source wire are at an identical potential because of contact region. Semiconductor layer includes ineffective region R at the surface remote from semiconductor substrate. |
| US10262906B2 |
Method of producing a functional inlay and inlay produced by the method
The method of manufacturing a functional inlay, comprises at least the steps of: (1) providing a substrate with a wire antenna embedded therein and with an aperture wherein two wire antenna portions are positioned over said aperture; (2) acquiring the positions and the dimensions of said wire antenna portions and of said aperture; (3) determining if the acquired positions and dimensions meet predetermined tolerances; (4) if the acquired dimensions and positions meet said tolerances, then placing a chip in fie aperture so that said wire portions are positioned over connections pads of said chip and then bonding said wire portions to said connection pads. |
| US10262903B2 |
Boundary spacer structure and integration
The present disclosure relates to semiconductor structures and, more particularly, to an N-P boundary spacer structure used with finFET devices and methods of manufacture. The method includes forming a plurality of first fin structures, forming a blocking layer between a first fin structure of the plurality of fin structures and a second fin structure of the plurality of fin structures, and forming an epitaxial material on the first fin structure, while blocking the epitaxial material from extending onto the second fin structure by at least the blocking layer formed between the first fin structure and the second fin structure. |
| US10262901B2 |
Fabrication of a vertical fin field effect transistor with reduced dimensional variations
A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins. |
| US10262900B2 |
Wimpy device by selective laser annealing
A method for co-integrating wimpy and nominal devices includes growing source/drain regions on semiconductor material adjacent to a gate structure to form device structures with a non-electrically active material. Selected device structures are masked with a block mask. Unmasked device structures are selectively annealed to increase electrical activity of the non-electrically active material to adjust a threshold voltage between the selected device structures and the unmasked device structures. |
| US10262895B2 |
Method for forming semiconductor device
The present invention provides a method for fabricating a semiconductor device, comprising at least the steps of: providing a substrate in which a memory region and a peripheral region are defined, the memory region includes a plurality of memory cells, each memory cell includes at least a first transistor and a capacitor, the peripheral region compress a second transistor, a first insulating layer is formed within the memory region and the peripheral region by an atomic layer deposition process, covering the capacitor of the memory cells in the memory region and the second transistor in the peripheral region, and a second insulating layer is formed, overlying the first insulating layer and the peripheral region. Finally, a contact structure is formed within the second insulating layer, and electrically connecting the second transistor. |
| US10262891B2 |
Substrate having two semiconductor materials on insulator
A method for forming a semiconductor device includes forming a first insulator layer on a first substrate of a first semiconductor material, implanting hydrogen ions into the first substrate to form a hydrogen-implanted layer, forming a recessed region in the first substrate, forming a second semiconductor material in the recessed region, and forming a second insulator layer over the second semiconductor material and the first substrate. The method also includes providing a second substrate with a third insulator layer disposed thereon, bonding the first substrate with the second substrate, and removing a lower portion of the first substrate at the hydrogen-implanted layer. A portion of the first substrate is removed to expose a surface of the second semiconductor material in the recessed region, thereby providing a layer of the first semiconductor material adjacent to a layer of the second semiconductor material on the second insulator layer. |
| US10262890B1 |
Method of forming silicon hardmask
A method for manufacturing a semiconductor device includes patterning a plurality of fins on a semiconductor substrate, wherein a hardmask is formed on each of the plurality of fins, forming a dielectric layer on the semiconductor substrate between the plurality of fins, removing the hardmasks from each of the plurality of fins, forming a plurality of cap layers in place of the removed hardmasks on each of the plurality of fins, wherein the plurality of cap layers comprise at least one of amorphous silicon and polycrystalline silicon, and selectively recessing the dielectric layer with respect to the plurality of cap layers. |
| US10262886B2 |
Electrostatic chuck device
Disclosed is an electrostatic chuck device for increasing electrostatic adsorptive force for a focus ring and uniformly cooling the focus ring. In such a device, a mounting table has a holder in the periphery of a placing surface along the circumferential direction of a focus ring, the holder has a pair of banks in the circumferential direction, and an annular groove formed between these banks, and in at least a bank on an outer circumferential position of the focus ring among the pair of the banks, a micro-protruding part including a plurality of micro-protrusions is on a surface facing the focus ring, or convex parts are on a bottom of the groove. The convex parts do not contact the focus ring, and the pair of banks or plurality of micro-protrusions contacts the focus ring and electrostatically adsorbs the focus ring in coordination with the convex parts. |
| US10262884B2 |
Systems, apparatus, and methods for an improved load port
Embodiments provide systems, apparatus, and methods for an improved load port that includes a frame supporting a dock and a carrier opener; an elevator operable to raise and lower the carrier opener; an isolation compartment within which the elevator is operable to move, the isolation compartment including a volume isolated from a volume of an equipment front end module (EFEM); and a purge supply within the isolation compartment operable to purge the isolation compartment of reactive gas trapped within the isolation compartment. Numerous additional aspects are disclosed. |
| US10262883B2 |
Method for improving performance of a substrate carrier
A method of modifying a substrate carrier to improve process performance includes depositing material or fabricating devices on a substrate supported by a substrate carrier. A parameter of layers deposited on the substrate is then measured as a function of their corresponding positions on the substrate carrier. The measured parameter of at least some devices fabricated on the substrate or a property of the deposited layers is related to a physical characteristic of substrate carrier to obtain a plurality of physical characteristics of the substrate carrier corresponding to a plurality of positions on the substrate carrier. The physical characteristic of the substrate carrier is then modified at one or more of the plurality of corresponding positions on the substrate carrier to obtain desired parameters of the deposited layers or fabricated devices as a function of position on the substrate carrier. |
| US10262880B2 |
Cover plate for wind mark control in spin coating process
Techniques disclosed herein provide an apparatus and method of spin coating that inhibits the formation of wind marks and other defects from turbulent fluid-flow, thereby enabling higher rotational velocities and decreased drying times, while maintaining film uniformity. Techniques disclosed herein include a fluid-flow member, such as a ring or cover, positioned or suspended above the surface of a wafer or other substrate. The fluid-flow member has a radial curvature that prevents wind marks during rotation of a wafer during a coating and spin drying process. |
| US10262879B2 |
Mold device
According to one embodiment, a mold device includes a first mold. The first mold includes a substrate clamping surface, a cavity, a suction part, a vent, first and second intermediate cavities and an opening/closing part. The substrate clamping surface contacts a surface of a processing substrate. The cavity is recessed from the substrate clamping surface. The suction part is recessed from the substrate clamping surface. The vent is provided on a path between the cavity and the suction part, and is recessed from the substrate clamping surface to a vent depth. The first intermediate cavity is provided between the vent and the suction part, and is recessed from the substrate clamping surface. The second intermediate cavity is provided between the first intermediate cavity and the suction part, and is recessed from the substrate clamping surface to a second intermediate cavity depth. The opening/closing part opens and closes the path. |
| US10262877B2 |
Apparatus and method for reducing substrate sliding in process chambers
Methods and apparatus for processing a substrate are disclosed herein. In some embodiments, an apparatus for processing a substrate includes: a substrate support having a substrate supporting surface including an electrically insulating coating; a substrate lift mechanism including a plurality of lift pins configured to move between a first position disposed beneath the substrate supporting surface and a second position disposed above the substrate supporting surface; and a connector configured to selectively provide an electrical connection between the substrate support and the substrate lift mechanism before the plurality of lift pins reach a plane of the substrate supporting surface. |
| US10262868B1 |
Self-aligned planarization of low-K dielectrics and method for producing the same
A method of forming a uniform self-aligned low-k layer with a large process window for inserting a memory array with pillar/convex topography and the resulting device are provided. Embodiments include forming a substrate with a first region and a second region; forming a first low-K layer over the substrate; forming an oxide layer over the first low-K layer; forming a spacer over the oxide layer; etching the spacer to expose the oxide layer in the first region; removing the oxide layer and a portion of the first low-K layer in the first region and a portion of the oxide layer and a portion of the spacer in the second region; removing the spacer in the second region; cleaning the first low-K layer and the oxide layer, a triangular-like shaped portion of the oxide layer remaining; and forming a second low-K layer over the substrate. |
| US10262867B2 |
Fast-gas switching for etching
A method for etching a layer in a plasma chamber with an inner injection zone gas feed and an outer injection zone gas feed is provided. The layer is placed in the plasma chamber. A pulsed etch gas is provided from the inner injection zone gas feed at a first frequency, wherein flow of pulsed etch gas from the inner injection zone gas feed is ramped down to zero. The pulsed etch gas is provided from the outer injection zone gas feed at the first frequency and simultaneous with and out of phase with the pulsed etch gas from the inner injection zone gas feed. The etch gas is formed into a plasma to etch the layer, simultaneous with the providing the pulsed etch gas from the inner injection zone gas feed and providing the pulsed gas from the outer interjection zone gas feed. |
| US10262864B2 |
Point-of-use enrichment of gas mixtures for semiconductor structure fabrication and systems for providing point-of-use enrichment of gas mixtures
Point-of-use enrichment of gas mixtures for semiconductor structure fabrication, and systems for providing point-of-use enrichment of gas mixtures, are described herein. In an example, a system for fabricating a semiconductor structure includes a process chamber for processing a substrate of a semiconductor structure. A gas supply is coupled to the process chamber. A point-of-use gas enrichment module is coupled to the gas supply. The point-of-use gas enrichment module is configured to concentrate a first gas composition to provide a second gas composition to the gas supply for the process chamber. The second gas composition has a relative amount of a hydride species greater than a relative amount of corresponding hydride species in the first gas composition. |
| US10262862B1 |
Method of forming fine interconnection for semiconductor devices
The present disclosure provides a method of forming fine interconnection for semiconductor devices. The method includes the following steps: A substrate is provided. A first core layer is formed over the substrate. The first core layer includes a base portion, a plurality of extending line portions extending from the base portion along a first direction, and a plurality of isolated line portions isolated from the base portion. Subsequently, a spacer is formed on the sidewalls of the first core layer. A second core layer is then formed to over the substrate. The second core layer includes a plurality of surrounding line portions surrounding the plurality of isolated line portions, and includes a plurality of enclosed line portions enclosed by the plurality of extending line portions. The spacer is removed to form a plurality of openings between the first core layer and the second core layer. The first core layer and the second core layer are alternately arranged along a second direction perpendicular to the first direction after removing the spacer. |
| US10262860B2 |
Method of fabricating electrodes, method of fabricating thin film transistor, method of fabricating array substrate, thin film transistor, array substrate, and display apparatus
The present application discloses a method of fabricating a plurality of electrodes. The method includes forming a hydrophobic pattern containing a hydrophobic material on a base substrate, the hydrophobic pattern has a first ridge on a first edge of the hydrophobic pattern, the hydrophobic pattern has a thickness at the first ridge greater than that in a region outside a region corresponding to the first ridge; removing a portion of the hydrophobic pattern outside the region corresponding to the first ridge; and forming a first electrode on a first side of the first ridge and a second electrode on a second side of the first ridge. |
| US10262856B2 |
Selective oxidation of transition metal nitride layers within compound semiconductor device structures
Methods for integrating transition metal oxide (TMO) layers into a compound semiconductor device structure via selective oxidation of transition metal nitride (TMN) layers within the structure. |
| US10262854B2 |
Deposition of SiN
Methods and precursors for forming silicon nitride films are provided. In some embodiments, silicon nitride can be deposited by atomic layer deposition (ALD), such as plasma enhanced ALD. In some embodiments, deposited silicon nitride can be treated with a plasma treatment. The plasma treatment can be a nitrogen plasma treatment. In some embodiments the silicon precursors for depositing the silicon nitride comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%). In some embodiments, a method for depositing silicon nitride films comprises a multi-step plasma treatment. |
| US10262852B2 |
Atmospheric pressure ionization method
An atmospheric pressure ionization method uses: a gas flow passage control unit (26) and a gas outlet nozzle (24) configured to jet argon gas to an atmospheric atmosphere; a needle electrode (19) arranged between an outlet port of the gas outlet nozzle (24) and an introduction port of an ion introduction pipe (6) that includes a tip end portion formed into a two-sheeted hyperboloid of revolution having a radius of curvature of 1 μm or more and less than 30 μm; a needle electrode support mechanism (20); and an electric power generation unit (22) configured to apply a voltage to the needle electrode (19). The atmospheric pressure ionization method includes: applying a voltage of 1.8 kV or more to the needle electrode (19) from the voltage generation unit (22) to generate a dark discharge; exciting the argon gas with the dark current; and causing the excited argon gas and the sample to react with each other, to thereby ionize the sample. |
| US10262849B2 |
Active stabilization of ion trap radiofrequency potentials
Disclosed are improved methods and structures for actively stabilizing the oscillation frequency of a trapped ion by noninvasively sampling and rectifying the high voltage RF potential at circuit locations between a step-up transformer and a vacuum feedthrough leading to the ion trap electrodes. We use this sampled/rectified signal in a feedback loop to regulate the RF input amplitude to the circuit. By employing techniques and structures according to the present disclosure we are advantageously able to stabilize a 1 MHz trapped ion oscillation frequency to <10 Hz after 200 s of integration, representing a 34 dB reduction in the level of trap frequency noise and drift, over a locking bandwidth of up to 30 kHz. |
| US10262847B2 |
Photomultiplier tube and method of making it
A photomultiplier tube (PMT) suitable for detecting a photon, comprising: an electron ejector configured for emitting primary electrons in response to an incident photon; a detector configured for collecting electrons and providing an output signal representative of the incident photon; and a series of vertical electrodes between the electron ejector and the detector, wherein each of the vertical electrodes is configured for emitting secondary electrons in response to incident electrons, and each of the vertical electrodes is parallel to a straight line connecting the electron ejector and the detector. |
| US10262846B2 |
Apparatus and methods for focussing electrons
An apparatus for generating and focusing electrons is provided. The apparatus has an emissive material configured to emit an electron, an electron target, and an electrical potential gradient generator configured to generate an electrical potential gradient within the emissive material. The electrical potential gradient is oriented so as to vary from positive to negative in the general direction toward the electron target. In operation, an electron emitted from the emissive materials is deflected away from the emissive material and generally toward the electron target. The apparatus may be incorporated in scientific analytical equipment such as an electron multiplier. |
| US10262844B2 |
Oxide sintered body and method for manufacturing the same, sputtering target, and semiconductor device
There is provided an oxide sintered body including indium, tungsten and zinc, wherein the oxide sintered body includes a bixbite type crystal phase as a main component and has an apparent density of higher than 6.6 g/cm3 and equal to or lower than 7.5 g/cm3, a content rate of tungsten to a total of indium, tungsten and zinc in the oxide sintered body is higher than 0.5 atomic % and equal to or lower than 5.0 atomic %, a content rate of zinc to the total of indium, tungsten and zinc in the oxide sintered body is equal to or higher than 1.2 atomic % and equal to or lower than 19 atomic %, and an atomic ratio of zinc to tungsten is higher than 1.0 and lower than 60. There are also provided a sputtering target including this oxide sintered body, and a semiconductor device. |
| US10262842B2 |
Analysis method and semiconductor etching apparatus
There is provided a method of analyzing data obtained from an etching apparatus for micromachining a wafer using plasma. This method includes the following steps: acquiring the plasma light-emission data indicating light-emission intensities at a plurality of different wavelengths and times, the plasma light-emission data being measured under a plurality of different etching processing conditions, and being obtained at the time of the etching processing, evaluating the relationship between changes in the etching processing conditions and changes in the light-emission intensities at the plurality of different wavelengths and times with respect to the wavelengths and times of the plasma light-emission data, and identifying the wavelength and the time of the plasma light-emission data based on the evaluation result, the wavelength and the time being to be used for the adjustment of the etching processing condition. |
| US10262841B2 |
Plasma monitoring device
A plasma monitoring device includes a fixing unit, a plasma measuring unit disposed to be in contact with the fixing unit, and measuring a luminous intensity of emitted light of a plasma to output a luminous intensity measurement value, a reference light source unit irradiating reference light having a uniform luminous intensity to the plasma measuring unit, and a control unit receiving the luminous intensity measurement value to calculate a luminous intensity value of the emitted light, controlling a voltage applied to the reference light source unit to uniformly control a luminous intensity of the reference light, comparing a luminous intensity of the reference light irradiated to the plasma measuring unit with a previously stored luminous intensity reference value to detect a correction factor, and applying the correction factor to a luminous intensity value of the emitted light to correct the luminous intensity measurement value. |
| US10262837B2 |
Plasma uniformity control by gas diffuser hole design
Embodiments of a gas diffuser plate for distributing gas in a processing chamber are provided. The gas distribution plate includes a diffuser plate having an upstream side and a downstream side, and a plurality of gas passages passing between the upstream and downstream sides of the diffuser plate. The gas passages include hollow cathode cavities at the downstream side to enhance plasma ionization. The depths, the diameters, the surface area and density of hollow cathode cavities of the gas passages that extend to the downstream end can be gradually increased from the center to the edge of the diffuser plate to improve the film thickness and property uniformity across the substrate. The increasing diameters, depths and surface areas from the center to the edge of the diffuser plate can be created by bending the diffuser plate toward downstream side, followed by machining out the convex downstream side. Bending the diffuser plate can be accomplished by a thermal process or a vacuum process. The increasing diameters, depths and surface areas from the center to the edge of the diffuser plate can also be created computer numerically controlled machining. Diffuser plates with gradually increasing diameters, depths and surface areas of the hollow cathode cavities from the center to the edge of the diffuser plate have been shown to produce improved uniformities of film thickness and film properties. |
| US10262835B2 |
Plasma processing equipment and plasma generation equipment
A plasma processing equipment includes a vacuum processing chamber, an insulating material, a gas inlet, a high frequency induction antenna provided at an upper outside of the vacuum processing chamber, a magnetic field coil, a yoke for controlling distribution of a magnetic field in the vacuum processing chamber, a high frequency power supply for generating plasma and supplying a high frequency current to the antenna, and a power supply for supplying power to the magnetic field coil. The antenna is divided into n high frequency induction antenna elements are arranged in tandem on one circle so that a high frequency current delayed sequentially by λ (wavelength of high frequency power supply)/n flows clockwise through the antenna elements arranged in tandem via a delay unit, and a magnetic field is applied from the magnetic field coil to generate electron cyclotron resonance (ECR) phenomenon. |
| US10262833B2 |
Temperature controlled ion source
An ion source with improved temperature control is disclosed. A portion of the ion source is nestled within a recessed cavity in a heat sink, where the portion of the ion source and the recessed cavity are each shaped so that expansion of the ion source causes high pressure thermal contact with the heat sink. For example, the ion source may have a tapered cylindrical end, which fits within a recessed cavity in the heat sink. Thermal expansion of the ion source causes the tapered cylindrical end to press against the recessed cavity in the heat sink. By proper selection of the temperature of the heat sink, the temperature and flow of coolant fluid through the heat sink, and the size of the gap between the heat sink and the ion source, the temperature of the ion source can be controlled. |
| US10262831B2 |
Method and system for weak pattern quantification
A weak pattern identification method includes acquiring inspection data from a set of patterns on a wafer, identifying failing pattern types on the wafer, and grouping like pattern types of the failing pattern types into a set of pattern groups. The weak pattern identification method also includes acquiring image data from multiple varied instances of a first pattern type grouped in a first group, wherein the multiple varied instances of the first pattern type are formed under different conditions. The weak pattern identification method also includes comparing images obtained from common structures of the instances of the first pattern type to identify local differences within a portion of the first pattern type. Further, the weak pattern identification method includes identifying metrology sites within the portion of the first pattern type proximate to a location of the local differences within the portion of the first pattern type. |
| US10262829B2 |
Protection circuit assembly and method for high voltage systems
A circuit assembly and method use a breakover device that changes states in response to a change in electric energy in a helper circuit that supplies current from a power source to a powered system. The helper circuit includes an inductive element connected with the powered system. The breakover device is in a non-conducting state prior to a discharge event from the powered system to prevent the current from the power source from being conducted through the resistive element. The breakover device changes to a conducting state responsive to the powered system discharging current into the helper circuit. The breakover device conducts the current that is discharged from the powered system through the resistive element to reduce the electric energy in the helper circuit from the current that is discharged. |
| US10262827B2 |
Fault state indication device for circuit breaker
A fault state indication device for a circuit breaker includes: a contact group; and a transmission assembly and an indication assembly that are mounted inside a housing. The contact group implements a normally open contact group and a normally closed contact group. The transmission assembly acts on a contact support, different open and closed states of the contact group are realized via the contact support. The indication assembly indicates a fault state, the indication assembly is linked with the circuit breaker, and carries out a corresponding state indication in response to a fault. |
| US10262820B2 |
High voltage circuit breaker, system, vacuum interrupter module and associated drive module
A high voltage circuit breaker comprises a vacuum interrupter module, a drive module, and an actuator. The vacuum interrupter module has a vacuum interrupter housing and a pair of electrical contacts disposed in the vacuum interrupter housing. At least one of the pair of electrical contacts is movable relative to the other of the pair of electrical contacts to engage and disengage the electrical contacts from one another for switching a high voltage on and off. The drive module has a drive module housing and a drive member coupled with the at least one movable electrical contact. A central part of the drive member is disposed in the drive module housing and insulated from an ambient air. The actuator is coupled to the drive member and moves the pair of electrical contacts relative to one another. |
| US10262819B2 |
Vacuum circuit breaker
Disclosed is a vacuum circuit breaker (1) including a vacuum interrupter (3) accommodated in a ground tank (2) filled with insulating gas. At least one of a fixed electrode (10) and a movable electrode (11) of the vacuum interrupter (3) uses an electrode material in which particles containing a solid solution of a heat resistant element and Cr are finely and uniformly dispersed and in which Cu textures as a high conductive component are finely and uniformly dispersed. The electrode material contains 20 to 70% by weight of Cu, 1.5 to 64% by weight of Cr and 6 to 76% by weight of the heat resistant element relative to a weight of the electrode material. The particles of the solid solution in the electrode material have an average particle size of 20 μm or smaller. |
| US10262815B2 |
Button locking device
A button locking device includes a panel, a button installed on the panel, a bottom plate installed under the button, a first cylinder spring installed between the button and the bottom plate for resetting the button, an actuator assembly installed between the panel and the bottom plate, a toggle member installed under the button and pushed by the actuator assembly to rotate from a first position to a second position and rotated from the second position to the first position. At the first position, the toggle member stops the button from moving downward. At the second position, the toggle member allows the button to move downward. The present invention has the features of simple structure, convenient operation, low power consumption, high safety, and broad scope of applicability. |
| US10262814B2 |
Low travel switch assembly
A low travel switch assembly and systems and methods for using the same are disclosed. The low travel dome may include a domed surface having upper and lower portions, and a set of tuning members integrated within the domed surface between the upper and lower portions. The tuning members may be operative to control a force-displacement curve characteristic of the low travel dome. |
| US10262810B1 |
Moveable contact support structure and supporting method
An exemplary contactor assembly includes, among other things, a moveable contact that moves back and forth between an electrically coupled position with a plurality of stationary contacts, and an electrically decoupled position with the stationary contacts. A support structure is configured to limit flexing of the moveable contact when in the electrically coupled position. An exemplary support method includes, among other things, transitioning a moveable contact from an electrically decoupled position to an electrically coupled position with a plurality of stationary contacts. The method further includes limiting a flexing movement of the moveable contact with a support structure. |
| US10262809B2 |
Electric energy storage device having improved terminal structure
An electric energy storage device has an inner terminal disposed in a cylindrical metal case and connected to an electrode of a bare cell, wherein the inner terminal includes a plate-shaped terminal body having a circular outer circumference; at least one electrolyte impregnation hole formed through the terminal body in a thickness direction; a flange located at the outer circumference of the terminal body and extending perpendicular to a plane of the terminal body; and a spacer formed to protrude at a periphery of at least one impregnation hole among the impregnation holes or formed by protruding a part of the plane of the terminal body. |
| US10262808B2 |
Conductive composite and capacitor utilizing the same
A conductive composite is provided, which includes a conductive conjugated polymer and a mixture. The mixture includes (a) boron oxide, and (b) sulfur-containing compound, nitrogen-containing compound, or a combination thereof. A capacitor is also provided, which includes an anode electrode, a dielectric layer on the anode electrode, a cathode electrode, and an electrolyte between the dielectric layer and the cathode electrode, wherein the electrolyte includes the described conductive composite. |
| US10262807B2 |
Electrode foil, winding capacitor, electrode foil manufacturing method, and winding capacitor manufacturing method
An electrode foil that progresses an enlargement of the surface area of a dielectric film and that barely causes cracks which would even break a core part at the time of winding, a winding capacitor obtained by winding the electrode foil, an electrode foil manufacturing method, and a winding capacitor manufacturing method are provided. An electrode foil is formed of a belt-like foil, and has a surface enlarged part, a core part, and a plurality of separation parts. The surface enlarged part is formed on the surface of the foil, and the core part is a part remained when excluding the surface enlarged part within the foil. The separation part extends in a width direction of the belt in the surface enlarged part, dividing the surface enlarged part. The plurality of separation parts share bending stress when the electrode foil is wound, preventing concentration of stress. |
| US10262803B1 |
High voltage fringe-effect capacitor
A multilayer chip capacitor includes electrodes comprised of numerous, closely spaced conductive layers interposed within a dielectric laminate. Adjacent conductive layers are essentially non-overlapping, so that fringe capacitance between opposing electrodes provides substantially all of the capacitance. The conductive layers may be shaped to form a non-planer boundary between electrodes. An additional high frequency integrated capacitor is formed from external electrode plates. The non-planar electrode boundary principle is also applied to discoidal capacitors in the form of a non-concentric electrode boundary. |
| US10262799B2 |
Multilayer ceramic capacitor
A multilayer ceramic capacitor includes a multilayer body and first and second outer electrodes that include first and second base electrode layers, respectively, first and second electroconductive resin layers, respectively, and first and second plating layers, respectively. The first and second base electrode layers are only located on the end surfaces of the multilayer body. The first and second electroconductive resin layers reach portions of the surfaces of the primary surfaces and portions of the surfaces of the lateral surfaces of the multilayer body. The first and second plating layers cover at least a portion of the base electrode layers and at least a portion of the electroconductive resin layers. |
| US10262796B2 |
Dielectric composition and electronic component
A dielectric composition is provided. The dielectric composition includes a tungsten bronze type complex oxide expressed by a chemical formula (K1-xNax)Sr2Nb5O15 as a main component, x satisfying 0≤x≤0.50, wherein the dielectric composition includes a secondary phase of at least one or more selected from: MgO.SiO2; BaO.2MgO.2SiO2; and 2MgO.B2O3; or the dielectric composition includes a tungsten bronze type complex oxide expressed by a chemical formula (K1-xNax)Sr2Nb5O15 as a main component, x satisfying 0≤x≤0.40, wherein the dielectric composition includes: MgO; BaO; B2O3; SiO2; and P2O5 as a first accessory component in a total content of 2.5 mol to 20.0 mol per 100 mol of the main component. |
| US10262795B2 |
Multilayer ceramic electronic component including ceramic-metal compound layers
A multilayer ceramic electronic component includes a ceramic body in which dielectric layers and internal electrodes are alternately disposed. Ceramic-metal compound layers are disposed on interfaces between the internal electrodes and the dielectric layers. Additionally, in some examples, spaces between adjacent internal electrodes are fully occupied by the dielectric layers and the dielectric layers contain a ceramic-metal compound containing metal particle. The ceramic-metal compound layer may have an embossing type configuration or a dendrite type configuration. |
| US10262793B2 |
Manufacturing method of surface mounted inductor
A manufacturing method of a surface mounted inductor involves using a coil and a tablet in a molding die. The coil is placed on the tablet. The coil and the tablet are arranged in the molding die and pressurized and compressed to the size of the cavity in the molding die at a first temperature. The coil and the tablet are pressurized in the molding die at a second temperature higher than the first temperature to form a formed body incorporating the coil. |
| US10262792B2 |
Near field communication for field devices
A device for wireless communication with a process automation field device. The device may include an inductive interface in the field device embodied to couple with a complementary inductive interface of a service tool. The field device inductive interface may be embodied to inductively transfer data to the service tool and to inductively receive data and energy from the service tool. The energy received from the service tool may be sufficient for operating the field device's inductive interface. A method of wireless communication is also disclosed. |
| US10262786B2 |
Stepped-width co-spiral inductor structure
A stepped-width, co-spiral inductor structure includes a first exterior layer having a first exterior width. The stepped-width, co-spiral inductor structure also includes a first interior layer coupled to the first exterior layer. The first interior layer includes a first interior width that is wider than the first exterior width of the first exterior layer. The stepped-width, co-spiral inductor structure further includes a second exterior layer coupled to the first interior layer. The second exterior layer includes a second exterior width that is narrower than the first interior width of the first interior layer. |
| US10262785B2 |
Press-clamp with clamping force sensor for electric transformer winding
A press-clamp for an electric transformer winding formed by an upper plate having a free inner face with a first concentric circular protrusion, and an outer face joined to a concentric nut that can be screwed along a threaded bolt; a clamping force sensor having a ring-shaped body; and a lower plate having a peripheral wall defining a cavity with a second concentric protrusion and housing the ring-shaped body of the clamping force sensor and the upper plate by its inner face, the ring-shaped body of the clamping force sensor placed concentrically when aligned with the first protrusion and the second protrusion. |
| US10262783B2 |
Stack-type inductor element and method of manufacturing the same, and communication device
A stack-type inductor element includes a stack including a magnetic element layer, a coil conductor pattern provided in the stack and the magnetic element layer defines a magnetic element core, a plurality of first pad electrodes provided on one main surface of the stack, and a plurality of second pad electrodes provided on the other main surface of the stack so as to be symmetric to the plurality of first pad electrodes. One end and the other end of the coil conductor pattern are electrically connected to two of the plurality of first pad electrodes, respectively, and the plurality of second pad electrodes are all electrically open. |
| US10262780B2 |
Analytical instrument inductors and methods for manufacturing same
Analytical instrument inductors are provided that can include bundled wired conductive material about a substrate. Analytical instrument inductors are also provided that can include: a tubular substrate defining a plurality of flanges extending outwardly from a core of the substrate wherein opposing flanges define portions of the core; at least one pair of wires wound about a first portion of the core and between at least two flanges, the pair of wires extending to and wound about a second portion of the core; and wherein the one pair of wires are operatively coupled to an analytical instrument to provide inductance. Methods for preparing an instrument inductor are provided. The methods can include bundling wires about and within multiple exterior openings of a hollow-cored substrate; and connecting each of the bundles across the openings. |
| US10262779B2 |
R-T-B-based magnet material alloy and method for producing the same
Provided is an R-T-B-based magnet material alloy including an R2T14B phase which is a principal phase and R-rich phases which are phases enriched with the R, wherein the principal phase has primary dendrite arms and secondary dendrite arms diverging from the primary dendrite arms, and regions where the secondary dendrite arms have been formed constitute a volume fraction of 2 to 60% of the alloy, whereby excellent coercive force can be ensured in R-T-B-based sintered magnets even when the amount of heavy rare earth elements added to the alloy is reduced. The inter-R-rich phase spacing is preferably at most 3.0 μm, and the volume fraction of chill crystals is preferably at most 1%. Furthermore, the secondary dendrite arm spacing is preferably 0.5 to 2.0 μm, and the ellipsoid aspect ratio of R-rich phase is preferably at most 0.5. |
| US10262777B2 |
Compound having exponential temperature dependent electrical resistivity, use of such compound in a self-regulating heating element, self-regulating heating element comprising such compound, and method of forming such compound
A novel compound having exponential temperature dependent electrical resistivity comprises an electrically insulating bulk material (11), electrically conductive particles (12) of a first kind, and electrically conductive particles (13) of a second kind covered by a lubricant. The bulk material holds the particles of the first and second kinds in place therein; the particles of the second kind are smaller than the particles of the first kind; the particles of the second kind are more in number than the particles of the first kind; and the particles of the second kind have higher surface roughness than the particles of the first kind, wherein the particles of the second kind comprise tips (13a) and the particles of the first kind comprise even surface portions (12a). The particles of the first and second kinds are arranged to form a plurality of current paths (14) through the compound, wherein each of the current paths comprises galvanically connected particles of the first and second kinds and a gap (14a) between a tip (13a) of one of the particles of the second kind and an even surface portion (12a) of one of the particles of the first kind, which gap is narrow enough to allow electrons to tunnel through the gap via the quantum tunneling effect. The bulk material has a thermal expansion capability such that it expands with temperature, thereby increasing the gap widths (w) of the current paths, which in turn increases the electrical resistivity of the compound exponentially. |
| US10262775B2 |
Energy efficient noise dampening cables
Energy efficient noise dampening coaxial and twisted pair cables include certain layers to improve the quality of signals transmitted over the cables. A coaxial cable includes a conductive core, a first insulating layer surrounding the conductive core, a metal shield layer surrounding the first insulating layer, a second insulating layer surrounding the metal shield layer, a carbon material layer surrounding the second insulating layer, and a protective sheath wrapping the carbon material layer. A twisted pair cable section includes a core section. The core section includes a carbon material core, an insulating layer surrounding the carbon material core, and a metal shield layer surrounding the insulating layer. A plurality of twisted pair cables are disposed in sections or compartments defined by the core section, and between the core section and a protective sheath. Methods for constructing the cables are also disclosed. |
| US10262771B2 |
Method for manufacturing a torque balanced electromechanical cable
An electromechanical cable that is crush-resistant and torque balanced is provided as well as a method for manufacturing a crush-resistant and torque balance electromechanical cable. The cable can include a core having a conductor surrounded by a first jacket layer, a second jacket layer surrounding the first jacket layer, a first armor layer surrounding second jacket layer, a third jacket layer surrounding the first armor layer, a second armor layer surrounding the third jacket layer, and a fourth jacket layer surrounding the second armor layer. The first armor layer can be constructed as a plurality of wires and compressed partially into the second jacket layer. The second armor layer can be constructed from a plurality of three-wire strands and/or single wires and compressed partially into the third jacket layer. The three-wire strands can be symmetric or asymmetric and can be compacted or non-compacted. |
| US10262769B2 |
Wire harness
A wire harness includes a flat shielded cable, a first device connected to one end of the flat shielded cable, and a second device connected to the other end of the flat shielded cable. The flat shielded cable includes a plurality of conductors arranged in parallel, an insulating jacket section that covers the plurality of conductors and has an exposed conductor section which exposes a part of at least one of the conductors, and a shielding member that covers an outer periphery of the jacket section. A signal is transmitted from the first device to the second device through a conductor other than the conductor provided with the exposed conductor section. The at least one of the conductors is connected to a ground at a position between the exposed conductor section and the second device. |
| US10262761B1 |
Apparatus and methods for causing selection of an advertisement based on prevalence of a healthcare condition in a plurality of geographic areas
A computer system and method causes selection of an advertisement based on the prevalence of a healthcare condition in each of a plurality of geographic areas. The prevalence is calculated by an entity that matches healthcare data with consumer data to determine, in each of the geographic areas, how many individuals have an unidentified healthcare condition. The entity is unable to identify the healthcare condition without decoding data received in response to a certification that the entity no longer has access to any data associating the individuals with the unidentified healthcare condition code, so that the privacy of the personal healthcare information is maintained. |
| US10262758B2 |
Scoring, evaluation, and feedback related to EMS clinical and operational performance
A method for evaluating emergency medical service according to embodiments of the present invention includes receiving emergency medical service data from a database, filtering the emergency medical service data based on a selection criteria to form a filtered emergency medical service data set, determining a first score from the filtered emergency medical service data set, where the first score indicates objective clinical performance quality for the filtered emergency medical service data set, determining a second score from the filtered emergency medical service data set, where the second score indicates objective operational performance quality for the filtered emergency medical service data set, merging the first score and the second score to form a composite score; and visually displaying the composite score to a user. |
| US10262757B2 |
Enhanced pathology diagnosis
A system includes a microscope configured to magnify a pathology sample, a camera positioned to record magnified pathology images from the microscope, a pathology database including reference pathology images, and a display configured to show the magnified pathology images. A processing apparatus is coupled to the camera, the pathology database, and the display. The processing apparatus includes instructions that when executed by the processing apparatus cause the system to perform operations. The operations include comparing the magnified pathology images to the reference pathology images included in the pathology database; identifying one or more regions of interest in the magnified pathology images; and alerting, using the display, a user of the microscope to the one or more regions of interest in the magnified pathology images while the pathology sample is being magnified with the microscope. |
| US10262756B2 |
System for gap in care alerts
The present invention is a gap in care alert system for alerting someone associated with a patient (including in one embodiment the patient himself) that a gap in heath care will soon occur or in another embodiment that a gap in care has occurred for the patient based on the occurrence of a triggering event and the absence of a follow-up event occurring. Health insurance claims data may be used in the process to determine gaps in care. |
| US10262755B2 |
Detecting cancer mutations and aneuploidy in chromosomal segments
The invention provides methods, systems, and computer readable medium for detecting ploidy of chromosome segments or entire chromosomes, for detecting single nucleotide variants and for detecting both ploidy of chromosome segments and single nucleotide variants. In some aspects, the invention provides methods, systems, and computer readable medium for detecting cancer or a chromosomal abnormality in a gestating fetus. |
| US10262754B2 |
Fine grained online remapping to handle memory errors
An error in a physical memory realization at a physical memory address is detected. A first physical memory line corresponding to the physical memory address is determined. It is ensured that a duplicate of data content associated with the first physical memory line is associated with a second physical memory line. The physical memory address is remapped to use the second physical memory line for data content. |
| US10262753B2 |
Auxiliary test device, test board having the same, and test method thereof
The test board may include sockets in which a plurality of devices-under-test (DUTs) is inserted, and an auxiliary test device connection tree electrically connected to the sockets. The auxiliary test device connection tree includes at least one first auxiliary test device receiving and outputting a test request from an external apparatus, and at least one second auxiliary test device generating a test clock and a test pattern in response to the test request outputted from the at least one first auxiliary test device, performing a test operation about at least one among the DUTs using the generated test pattern, and outputting whether or not of an error of the test operation to the at least one first auxiliary test device. |
| US10262752B2 |
Method and apparatus for identifying erroneous data in at least one memory element
A method for identifying erroneous data in at least one memory element, particularly a register, that includes at least one flip-flop that is intended to allow reliable detection of soft errors. To this end, writing of data to the at least one memory element involves at least one write security bit being produced from these data and stored in an associated security memory element, wherein at least one output security bit is computed from the data continuously in the same way as for writing and is compared with the corresponding write security bit. |
| US10262741B2 |
Read and write control circuit and method of flash chip, and AMOLED application circuit
A read and write control circuit for a flash chip is disclosed which includes a timing control circuit for generating a read and write timing signal for the flash chip, and a first non-volatile memory for storing a plurality of flags corresponding to a plurality of blocks in the flash chip, each of the flags indicating whether a respective one of the blocks that corresponds thereto has been written to normally. Also disclosed is a read and write control method of a flash chip, as well as an AMOLED application circuit having the read and write control circuit for use in an electrical compensation mechanism. |
| US10262738B2 |
Content addressable memory cell and content addressable memory
In order to provide a technique for reducing an area of a content addressable memory cell and suppressing a leak current in a content addressable memory which calculates similarity, a content addressable memory cell of the present invention, comprising: a resistance network which includes plural current paths, a logic circuit for selecting a current path in response to input data, and a variable-resistance-type non-volatile memory element that is arranged on at least one current path and stores data and whose resistance value is changed according to a result of logical calculation based on the input data and the stored data; and a charge/discharge circuit which is connected with the resistance network and a match line and whose delay time from inputting a signal through the match line until outputting the signal is changed according to the result of logical calculation based on the input data and the stored data. |
| US10262737B2 |
Semiconductor integrated circuit
According to one embodiment, a semiconductor integrated circuit includes a ROM, an SRAM, a memory and a selector. The ROM stores initialization data. At least part of the initialization data is writable to the SRAM. The memory stores information indicating whether data is written to the SRAM. The selector outputs one of data supplied from the SRAM and data supplied from the ROM in accordance with the information stored in the memory. |
| US10262735B2 |
Devices and methods to program a memory cell
Subject matter disclosed herein relates to memory devices and, more particularly, to programming a memory cell. |
| US10262732B2 |
Programmable array logic circuit and operating method thereof
This disclosure introduces a programmable array logic (PAL) circuit and a method which are capable of preventing a read disturbance effect on memory cells of the PAL circuit. The PAL circuit comprises a memory array coupled to a plurality of input lines and a plurality of source lines, a plurality of input transition detection (ITD) circuits, a pulse generator and a plurality of sense amplifiers. The plurality of ITD circuits detect a transition in level of the plurality of input signals in the input lines. The pulse generator generates an enable signal according to the transition in level of the input signals. The sense amplifiers are enabled to sense the voltage levels of the source lines when the transition in levels of the input signals is detected, and the sense amplifiers are disabled when no transition in levels of the input signals is detected. |
| US10262727B2 |
Gradiometric flux qubit system
One example includes a flux qubit readout circuit. The circuit includes a gradiometric SQUID that is configured to inductively couple with a gradiometric flux qubit to modify flux associated with the gradiometric superconducting quantum interference device (SQUID) based on a flux state of the flux qubit. The circuit also includes a current source configured to provide a readout current through the gradiometric SQUID during a state readout operation to determine the flux state of the gradiometric flux qubit at a readout node. |
| US10262725B1 |
Selective bit-line sensing method and storage device utilizing the same
A selective bit-line sensing method is provided. The selective bit-line sensing method includes the steps of: generating a neuron weights information, the neuron weights information defines a distribution of 0's and 1's storing in the plurality of memory cells of the memory array; and selectively determining either the plurality of bit-lines or the plurality of complementary bit-lines to be sensed in a sensing operation according to the neuron weights information. When the plurality of bit-lines are determined to be sensed, the plurality of first word-lines are activated by the artificial neural network system through the selective bit-line detection circuit, and when the plurality of complementary bit-lines are determined to be sensed, the plurality of second word-lines are activated by the artificial neural network system. |
| US10262721B2 |
Apparatuses and methods for cache invalidate
The present disclosure includes apparatuses and methods for cache invalidate. An example apparatus comprises a bit vector capable memory device and a channel controller coupled to the memory device. The channel controller is configured to cause a bulk invalidate command to be sent to a cache memory system responsive to receipt of a bit vector operation request. |
| US10262720B2 |
Semiconductor device
A semiconductor device includes: a first cell; a second cell; a first match line and a second match line; a first search line pair, first data being transmitted through the first search line pair; a second search line pair, second data being transmitted through the second search line pair; a first logical operation cell connected to the first search line pair and the first match line, and configured to drive the first match line based on a result of comparison between information held by the first and second cells and the first data; and a second logical operation cell connected to the second search line pair and the second match line, and configured to drive the second match line based on a result of comparison between information held by the first and second cells and the second data. |
| US10262719B1 |
DRAM and refresh method thereof
The present disclosure provides a dynamic random access memory (DRAM) and a method of operating the same. The DRAM includes a memory array, a refresh device and an access device. The refresh device is configured to perform a self-refresh operation on the memory array, wherein the self-refresh operation is interrupted in response to an access command. The access device is configured to access the memory array in response to the access command and the interruption of the self-refresh operation. |
| US10262716B2 |
Temperature dependent modes of operation of a semiconductor memory device
A first threshold temperature is maintained for operating a solid state drive (SSD) in a first mode. A second threshold temperature is maintained for operating the SSD in a second mode in which read and write operations are performed at a higher rate than in the first mode, wherein the second threshold temperature is higher than the first threshold temperature. The SSD is switched from the first mode to the second mode, in response to an operating temperature of the SSD exceeding the first threshold temperature. |
| US10262715B2 |
Multiple plate line architecture for multideck memory array
Methods, systems, and devices for multiple plate line architecture for multideck memory arrays are described. A memory device may include two or more three-dimensional arrays of ferroelectric memory cells overlying a substrate layer that includes various components of support circuitry, such as decoders and sense amplifiers. Each memory cell of the array may have a ferroelectric container and a selector device. Multiple plate lines or other access lines may be routed through the various decks of the device to support access to memory cells within those decks. Plate lines or other access lines may be coupled between support circuitry and memory cells through on pitch via (OPV) structures. OPV structures may include selector devices to provide an additional degree of freedom in multideck selectivity. Various number of plate lines and access lines may be employed to accommodate different configurations and orientations of the ferroelectric containers. |
| US10262707B2 |
Semiconductor memory device for stably reading and writing data
In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column. |
| US10262706B1 |
Anti-floating circuit
An anti-floating circuit including a first pull-high circuit, a first pull-low circuit and a first control circuit is provided. The first pull-high circuit includes a first P-type transistor and a second P-type transistor and is coupled to a first power terminal. The first pull-low circuit includes a first N-type transistor and a second N-type transistor and is coupled to a second power terminal. A first path is between the first P-type transistor and the first N-type transistor. A second path is between the second P-type transistor and the second N-type transistor. A third path is between the first P-type transistor and the second power terminal. In the first mode, the control circuit turns on the first and second paths and turns off the third path. In the second mode, the control circuit turns off the first and second paths and turns on the third path. |
| US10262693B2 |
Direct media feed enhanced recordings
The systems and methods discussed herein relate to technology for enhancing media recordings of a live event based on a media feed corresponding to the live event. The media recordings may be media items that include audio and image data captured by a user device. The user device may be associated with a member of an audience that is experiencing the live event. The user device may generate the media item using one or more sensory input devices and may receive additional media data via a media feed. The media feed may include media data that corresponds to the live event and includes content that is similar to the media item recorded by the user device but may have been derived from a higher quality recording or include supplemental data. The media data may then be used to enhance the media item. |
| US10262692B2 |
Method and system for automatic television production
It is provided a method for a computerized, server autonomously producing a TV show of a sports game in a scene. The method includes receiving from several video cameras a stream of video images of the scene for capturing a panoramic view of the scene, analyzing the stream of video images for allowing definition of several frame streams, determining location data of the frame streams accordingly, and rendering an active frame stream with images imaging a respective portion of the panoramic view of the scene. The method includes also transmitting for broadcasting a stream of image frames imaging the respective portion of the panoramic view. The step of analyzing the stream of video images includes identifying a playing object, tracking the playing, object and identifying players. The method also includes calibrating the cameras using points in the playing field. The method may include analyzing the stream of video images for identifying an event in the scene for switching between the active frame stream and a different frame stream. Also, the method may include directing a directed sensor to a region of interest in accordance with location data of the active, frame stream. |
| US10262691B1 |
Systems and methods for generating time lapse videos
Video information may define spherical video content having a duration. Spherical video content may define visual content viewable from a point of view as a function of progress through the spherical video content. Path information may define a path selection for the spherical video content. Path selection may include movement of a viewing window within the spherical video content. The viewing window may define extents of the visual content viewable from the point of view as the function of progress through the spherical video content. Time lapse parameter information may define at least two of a time portion of the duration, an image sampling rate, and a time lapse speed effect. A time lapse video may be generated based on the video information, the path information, and the time lapse parameter information. |
| US10262689B2 |
Nesting disk separator plates for use in hard disk drives
A hard disk drive with a multiple disk stack normally utilizes disk separator plates near the disk surfaces to reduce wind induced vibrations in the disks and the read/write heads. The manufacturing methods currently used to make these separator plates, metal casting and machining, or injection molded plastic, or extruding and machining, or cold forging tends to be expensive and creates unwanted weight and bulk without the desired precision. Stamping disk separator plates from metal provides exceptional dimensional control at reduced cost, but cannot readily provide the thicknesses required. Stamping and extruding the offsets, or stamping and folding the offsets, is a manufacturing process that provides the required dimensions for the offsets, and dimensional control and reduced cost. |
| US10262688B1 |
Method for screening tunnel valve tape heads for magnetic noise
A computer-implemented method for screening a multichannel head, according to one embodiment, includes measuring a channel signal to noise ratio value for each read transducer over a plurality of sense currents, wherein each transducer is one of a plurality of transducers in a multichannel head. The measured channel signal to noise ratio values are compared to a specification of a pre-defined value. The multichannel head is dispositioned to enable the multichannel head to perform to the specification of the pre-defined value, if possible. |
| US10262685B2 |
Low profile multidentate lubricants for use at sub-nanometer thicknesses in magnetic media
In one embodiment, a multidentate perfluoropolyether (PFPE) lubricant has the formula Se-So-Si-SL-Si-So-Se, where each So includes at least one perfluoroethyl ether unit, SL is a linker segment, and each Se and Si include at least one functional group configured to attach to a surface. In another embodiment, a multi dentate PFPE lubricant has the formula Se-So(a)-Si-Sm-Si-So(b)-Se, where each So(a), So(b), and Sm include at least one perfluoroethyl ether unit with the proviso that Sm has a different number of perfluoroethyl ether units than at least one of So(a) and So(b), and each Se and Si include at least one functional group configured to attach to a surface. |
| US10262682B2 |
Segmented magnetic recording write head for writing timing-based servo patterns
An apparatus according to one embodiment includes a plurality of first modules each having a first write transducer, and a plurality of second modules each having a second write transducer. Planes of deposition of write gaps of the second write transducers are oriented at an angle of greater than 4 degrees relative to planes of deposition of write gaps of the first write transducers. An apparatus according to another embodiment includes a first module having a plurality of first write transducers, and a second module having a plurality of second write transducers. Planes of deposition of write gaps of the second write transducers are oriented at an angle of greater than 4 degrees relative to planes of deposition of write gaps of the first write transducers. |
| US10262681B2 |
Reliable data reading with data set screening by error injection
According to one embodiment, a system includes a controller configured to determine whether a position error signal (PES) is invalid while reading data from a magnetic medium using at least one data channel. An invalid PES indicates off-track reading or a defect in the magnetic medium. The controller is also configured to determine whether a PES value is above a first predetermined threshold in response to a determination that the PES is valid. Moreover, the controller is configured to inject error bits into a data stream in place of corresponding bits of decoded data in response to a determination that the PES is invalid, a determination that the PES value is above the first predetermined threshold, or a determination that the PES is invalid and the PES value is above the first predetermined threshold. Other systems and methods are described in accordance with more embodiments. |
| US10262680B2 |
Variable sound decomposition masks
Variable sound decomposition masking techniques are described. In one or more implementations, a mask is generated that incorporates a user input as part of the mask, the user input is usable at least in part to define a threshold that is variable based on the user input and configured for use in performing a sound decomposition process. The sound decomposition process is performed using the mask to assign portions of sound data to respective ones of a plurality of sources of the sound data. |
| US10262677B2 |
Systems and methods for removing reverberation from audio signals
Disclosed herein are systems and methods for removing reverberation from signals. The systems and methods can be applicable to audio signals, for example, to voice, musical instrument sounds, and the like. Signals such as the vowel sounds in speech and the sustained portions of many musical instrument sounds can be composed of a fundamental frequency component and a series of harmonically related overtones. The systems and methods can exploit the intrinsically high degree of mutual correlation among the overtones. When such signals are passed through a reverberant channel, the degree of mutual correlation among the partials can be reduced. An inverse channel filter for the removal of reverberation can be found by employing an adaptive filter technique that maximizes the cross-correlation among signal overtones. |
| US10262676B2 |
Multi-microphone pop noise control
Disclosed is a method and a headset for reducing pop-noise in voice communication between a user and a far-end device. The headset has a first, a second and a third electro-acoustic input transducer for reception of audio input signals. The headset also has a first beamformer to provide a voice signal. The first beamformer is configured to optimize the voice-to-background noise ratio. The headset comprises a second beamformer configured for providing a pop-noise signal. The pop-noise signal is based on the first input signal from the first input transducer, the second input signal from the second input transducer, and a third input signal from the third input transducer. The second beamformer is adaptively configured to cancel voice and background noise while not cancelling pop-noise. The headset compares the pop-noise signal to the voice signal to determine time periods and frequency bands having pop-noise. |
| US10262672B2 |
Audio processing for speech
A method, a device, and a non-transitory storage medium are described in which a power of late reverberation of a speech signal is estimated based on early samples of the speech signal. The power of the late reverberation may be subtracted linearly or non-linearly from the speech signal. |
| US10262671B2 |
Audio coding method and related apparatus
An audio coding method and a related apparatus are disclosed. The audio coding method includes: estimating reference linear prediction efficiency of a current audio frame; determining an audio coding scheme that matches the reference linear prediction efficiency of the foregoing current audio frame; and performing audio coding on the foregoing current audio frame according to the audio coding scheme that matches the reference linear prediction efficiency of the foregoing current audio frame. The technical solutions provided in embodiments of the present disclosure help reduce overheads of audio coding. |
| US10262667B2 |
Audio decoder and method for providing a decoded audio information using an error concealment modifying a time domain excitation signal
An audio decoder for providing a decoded audio information on the basis of an encoded audio information. The audio decoder has an error concealment configured to provide an error concealment audio information for concealing a loss of an audio frame, wherein the error concealment is configured to modify a time domain excitation signal obtained for one or more audio frames preceding a lost audio frame, in order to obtain the error concealment audio information. |
| US10262666B2 |
Processor, method and computer program for processing an audio signal using truncated analysis or synthesis window overlap portions
A processor for processing an audio signal has: an analyzer for deriving a window control signal from the audio signal indicating a change from a first asymmetric window to a second window, or indicating a change from a third window to a fourth asymmetric window, wherein the second window is shorter than the first window, or wherein the third window is shorter than the fourth window; a window constructor for constructing the second window using a first overlap portion of the first asymmetric window, wherein the window constructor is configured to determine a first overlap portion of the second window using a truncated first overlap portion of the first asymmetric window, or wherein the window constructor is configured to calculate a second overlap portion of the third window using a truncated second overlap portion of the fourth asymmetric window; and a windower for applying the first and second windows or the third and fourth windows to obtain windowed audio signal portions. |
| US10262661B1 |
User identification using voice characteristics
Embodiments of methods, systems, and storage medium associated with providing user records associated with characteristics that may be used to identify the user are disclosed herein. In one instance, the method may include obtaining features of an individual, determining identifying characteristics associated with the obtained features, and initiating a search for a record associated with the individual based in part on the identifying characteristics associated with the obtained features, and, based on a result of the search, a verification of the record associated with the individual. The method may further include receiving at least a portion of the record associated with the individual, based at least in part on a result of the verification. The verification may be based in part on a ranking associated with the record. Other embodiments may be described and/or claimed. |
| US10262659B2 |
Hotword recognition
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for receiving audio data corresponding to an utterance, determining that the audio data corresponds to a hotword, generating a hotword audio fingerprint of the audio data that is determined to correspond to the hotword, comparing the hotword audio fingerprint to one or more stored audio fingerprints of audio data that was previously determined to correspond to the hotword, detecting whether the hotword audio fingerprint matches a stored audio fingerprint of audio data that was previously determined to correspond to the hotword based on whether the comparison indicates a similarity between the hotword audio fingerprint and one of the one or more stored audio fingerprints that satisfies a predetermined threshold, and in response to detecting that the hotword audio fingerprint matches a stored audio fingerprint, disabling access to a computing device into which the utterance was spoken. |
| US10262656B2 |
Multi-tier intelligent infrastructure management systems for communications systems and related equipment and methods
Methods of identifying available connector ports on rack mounted equipment use an image capture device to capture an image of a front face of an equipment rack. The captured image is compared to at least one stored image. A patch cord insertion status of at least one connector port included on an item of equipment that is mounted on the equipment rack is then determined based at least in part on the comparison of the captured image to the at least one stored image. |
| US10262655B2 |
Augmentation of key phrase user recognition
Examples for augmenting user recognition via speech are provided. One example method comprises, on a computing device, monitoring a use environment via one or more sensors including an acoustic sensor, detecting utterance of a key phrase via data from the acoustic sensor, and based upon the selected data from the acoustic sensor and also on other environmental sensor data collected at different times than the selected data from the acoustic sensor, determining a probability that the key phrase was spoken by an identified user. The method further includes, if the probability meets or exceeds a threshold probability, then performing an action on the computing device. |
| US10262648B2 |
Method for controlling interference in audio service and terminal
A method for controlling interference in an audio service and a terminal, where the method includes sending, by a first terminal, a first message using a short-range wireless communications technology when executing an audio service, determining, by a second terminal according to the first message, whether the second terminal supports interference control, and adjusting, by the second terminal, a setting of the second terminal according to the interference control parameter when the second terminal supports the interference control, and the second terminal falls within a controlled range. It can be learned that in a process in which the first terminal performs interference control on the second terminal, the first terminal may send the first message to the second terminal without a need of a noise reduction device such that the second terminal adjusts the setting of the second terminal. |
| US10262647B1 |
Clippable multi-tone whistle
Example clippable multi-tone whistles, as well as systems and methods for manufacturing the same are described. An example clippable multi-tone whistle may comprise: a clip attached to a whistle body. The whistle body comprises a flat surface under the clip; a first opening configured to allow air flow to come into the whistle body; and on the flat surface a second opening configured to allow air flow to come out of the whistle body. The second opening is at least partially blocked by the clip, which controls direction of one or more air flows coming out of the second opening. The whistle part is configured to generate a plurality of different sound tones in accordance with user finger movements around the clip and the second opening. The whistle may further comprise a glass breaker, a length scale, and a bolt action switch, which may function as a fire starter. |
| US10262646B2 |
Multi-source switched sequence oscillator waveform compositing system
The present disclosure is directed to multi-source switched sequence oscillator waveform compositing system that allows for real-time modulation of a specific fraction of the cycle period within the output waveform, resulting in a greater and more dynamic number of waveform variations than simple assembly of various shapes. |
| US10262645B1 |
Method and system for artificial reverberation using modal decomposition
In general, the present invention relates to a method and system for synthesizing artificial reverberation using modal analysis of a room or resonating object. In one embodiment of the inventive system, a collection of resonant filters is employed, each driven by the source signal, and their outputs summed. With filter resonance frequencies and dampings tuned to the modal frequencies and decay times of the acoustic space or resonating object being simulated, and filter gains set according to the source and listener positions within the space or object, any number of acoustic spaces and resonant objects may be simulated. |
| US10262643B1 |
MIDI mapping system and process for multiple chord and arpeggio triggering
Systems and processes that use MIDI mapping technology for multiple chord and arpeggio triggering are disclosed, including a multiple chord and arpeggio triggering MIDI mapping system and process that assigns, selects, and records chord and multi-arpeggio functions into a digital audio workstation (DAW) host program or an internalized sequencer and a two-phase multiple chord and time-delayed arpeggio triggering MIDI mapping process for recording a chord progression and enabling multi-arpeggio functions of the chords in the chord progression to be worked on at any time-delayed instance after recording the chord progression. The system divides output from a MIDI controller into chord generators and arpeggiators to allow users to define full chords with a single key selection, while also making immediate or time-delayed single key selections for different arpeggios. |
| US10262640B2 |
Musical performance support device and program
A musical performance support device includes: a tempo analysis unit that analyzes a tempo of musical piece sound data, the musical piece sound data indicating a musical piece sound; a sound generation unit that generates a sound based on the analyzed tempo, the generated sound indicating a beat of the musical piece sound data; and a sound processing unit that adds the generated sound to the musical piece sound. |
| US10262638B2 |
Interactive performance direction for a simultaneous multi-tone instrument
A musical instrument performance solution is described. Labels with visual indicators provide a reference to performers such that a proper combination of instrument inputs may be selected at the appropriate time. The visual indicators include colors and/or shapes. The visual indicators may be presented using differently-colored lyrical text, where each color corresponds to a set of notes. Each set of notes may for a chordal group such as a triad. The visual indicators may be associated with labels that are able to be adhered to various instrument inputs such as keys of a keyboard or piano. |
| US10262634B2 |
Bow for stringed instruments
A stringed instrument bow includes an elongated stick (102) having a head (110) and a frog (112) holding a ribbon of bow hair (108). The head and frog are configured such that bow hair (108) held under tension between the head and the frog forms a longitudinally twisted ribbon as held. |
| US10262629B2 |
Display device
A display device in one aspect of the present disclosure includes an object detection unit that detects an object positioned ahead of a host vehicle, a distance detection unit that detects a distance between the host vehicle and the object, a display unit that projects and displays information on the object onto a windshield of the host vehicle; and a display control unit that controls the display unit. The display control unit reduces a display brightness or a display area when the distance between the host vehicle and the object is smaller than a first threshold as compared to when the distance between the host vehicle and the object is equal to or larger than the first threshold and stops the display when the distance between the host vehicle and the object is smaller than a second threshold that is smaller than the first threshold. |
| US10262628B2 |
Display method
A display method includes: receiving an input signal; performing a color separation process on the input image to generate color information and an intensity image; performing a filtering process on the intensity image to generate an intensity coarse image and an edge image; generating a color coarse image according to the intensity coarse image and the color information; performing a pure color analysis on the color coarse image to generate a first pure color coarse image, a second pure color coarse image and a third pure color coarse image; and displaying the first pure color coarse image, the second pure color coarse image, the third pure color coarse image and the edge image in a first time period, a second time period, a third time period and a fourth time period respectively. |
| US10262627B2 |
Methods, systems, and media for managing output of an HDMI source
Mechanisms for managing output of an HDMI source are provided. In accordance with some implementations of the disclosed subject matter, a method for controlling output of an HDMI source is provided, the method comprising: establishing a connection between the HDMI source and an HDMI sink at a first address of a consumer electronic control bus of the HDMI sink; sending a request for an identity of the active source connected to the HDMI sink; monitoring signals on the consumer electronic control bus; receiving a message over the consumer electronic control bus identifying a second address on the consumer electronic control bus different from the first address as an address of an active source; setting a status of the HDMI source as inactive in response to receiving the message; and inhibiting output of video from the HDMI source to the HDMI sink in response to the status being set as inactive. |
| US10262625B2 |
Display device and display method
A display device includes: a first detection unit that detects an external signal from a second external device via a second connection unit, and outputs a first detection result indicating presence of an external signal; and a control unit that determines whether the second external device is connected with a second input unit based on the first detection result, and performs control so that a video signal to be supplied to a display unit is switched from a first video signal to a second video signal to cause the display unit to display an image based on the second video signal in a case where the control unit that determines that the second external device is connected with the second input unit. |
| US10262623B2 |
Methods of operating application processors and display systems with display regions having non-rectangular shapes
In a method of operating an application processor to control a display device including a non-rectangular valid display region, screen information regarding the non-rectangular valid display region is received, and a plurality of pieces of valid pixel data selected based on the screen information and corresponding to the non-rectangular valid display region are output to the display device. |
| US10262622B2 |
Low power display on mode for a display device
This application relates to systems, methods, and apparatus for transitioning a display device between operating modes using a single dedicated pin of a circuit connected to the display device. The dedicated pin can receive a packet signal corresponding to an operating mode for the display device, and the circuit can thereafter cause the display device to transition into the desired operating mode in response to receiving the packet signal. The operating mode can be a low power on mode where an interface connected to the circuit is deactivated and at least some circuitry of the display device is throttled or powered off. The display device can be driven in an all black state while in the low power on mode, thereby allowing the display device to more quickly transition out of the low power on mode compared to when the display device is completely off. |
| US10262621B2 |
Display device for mitigation of DC voltage stress, and driving method thereof
Disclosed are a display device and a driving method thereof, which when a frame having a long time length and a frame having a short time length are alternately provided, prevent a DC voltage stress from being accumulated. One frame of a plurality of frames may be driven in the line inversion method, and a polarity may be delayed up to a next frame, thereby allowing polarities to be alternately supplied. Therefore, a time length of the positive voltage may be the same as that of the negative voltage, and thus, the positive voltage and the negative voltage may be continuously supplied based on a frequency of another frame, thereby solving a problem where the DC voltage stress is accumulated due to a difference between the time length of the positive voltage and the time length of the negative voltage. |
| US10262618B2 |
Gate driver on array circuit and liquid crystal display using the same
A GOA circuit includes GOA circuit units. Each GOA circuit has a holding module A first transistor and a second transistor in the holding module holds the voltage imposed on the first control node to be at high voltage level. Also, the transistors form a direct current passage between the first control node and a first fixed voltage at high voltage level so the voltage imposed on the first control node is not lowered due to electricity leakage. The GOA circuit unit can resolve the problem of easy leakage of electricity. When the scanning signals are output by the GOA circuit unit, the stability is highly ensured. |
| US10262615B2 |
Shift register, driving method, and gate electrode drive circuit
A shift register includes: a plurality of clock signal terminals; and a plurality of input terminals. The plurality input terminals are configured to provide input signals under control by one or more clock signals from one or more of the plurality of clock signal terminals to realize both a forward scan and a backward scan of the shift register. |
| US10262611B2 |
Display device and display method thereof
The present disclosure illustrates a display device. The displaying device comprises a display panel, at least one scan driving unit and a data driving unit. The display panel is divided into display regions respectively having pixel sets. At least one scan driving unit having scanning lines couples to the pixel sets. The at least one scan driving unit outputs scanning signals to corresponding display regions upon receiving a first control signal. The data driving unit outputs data signals to the corresponding display regions upon receiving a second control signal. In response to respectively receiving the first or second control signals, the scan driving unit outputs the scanning signals or the data driving unit outputs the data signals to the corresponding display regions, so as to simultaneously scan the display regions respectively having the pixel sets in sequence with corresponding scanning patterns. |
| US10262608B2 |
Display device and driving method thereof
A display device includes a display unit including a plurality of pixels, a plurality of gate lines and a plurality of data lines which are connected to the plurality of pixels, a data driver applying data voltages to the plurality of data lines, and a gate driver delaying and outputting first gate signals applied to gate lines among the plurality of gate lines in a first sub-frame included in one frame and advancing and outputting second gate signals which are applied to remaining gate lines among the plurality of gate lines in a second sub-frame. |
| US10262605B2 |
Electronic display color accuracy compensation
Systems, methods, and non-transitory media are presented that provide for improving color accuracy. An electronic display includes a display region having multiple pixels each having multiple subpixels. The electronic device also includes a display pipeline coupled to the electronic display. The display pipeline is configured to receive image data and perform white point compensation on the image data to compensate for a current drop in the display to cause the display to display a target white point when displaying white. The display pipeline also is configured to correct white point overcompensation on the image data to reduce possible oversaturation of non-white pixels using the white point compensation. Finally, the display pipeline is configured to output the compensated and corrected image data to the electronic display to facilitate displaying the compensated and corrected image data on the display region. |
| US10262600B2 |
Method and apparatus for grayscale adjustment
A method and apparatus for grayscale adjustment are provided. The method includes steps of: obtaining pixel grayscale values or at least one region grayscale value of an original image; selecting a predetermined grayscale compensation interval, from multiple predetermined grayscale compensation intervals, which corresponds to the pixel grayscale values or the region grayscale value as a ready-to-use grayscale compensation interval; obtaining a grayscale compensation value which corresponds to the ready-to-use grayscale compensation interval; and performing compensation on pixel grayscale values of the original image according to the grayscale compensation value. |
| US10262594B2 |
Pixel driver circuit, pixel driving method, display panel and display device
A pixel driver circuit includes a driving transistor, a first storage capacitor, a second storage capacitor, a threshold compensation unit, a data writing and a light-emitting control unit. The threshold compensation is configured to control the driving transistor to be turned on at a threshold compensation stage and discharge toward a resetting voltage line until the driving transistor is turned off. The data writing is configured to write a data voltage into a gate electrode of the driving transistor at a data writing stage. The light-emitting control is configured to enable the driving transistor to be turned on at a light-emitting stage, so as to drive a light-emitting element to emit light. |
| US10262592B2 |
Sub-pixel of organic light emitting display device and organic light emitting display device including the same
A sub-pixel of an organic light emitting display device comprising an organic light emitting diode connected to a first node; a driving transistor comprising a first electrode, a second electrode connected to the first node, and a gate electrode connected to a second node; a first capacitor connected between the first node and the second node; a second capacitor connected between a programming line and the second node; a first transistor comprising a first electrode connected to the first electrode of the driving transistor, a second electrode connected to the second node, and a gate electrode connected to a scan line; and the first capacitor and the second capacitor are configured to couple the voltage of the first node and the voltage of the second node based on the programming voltage applied to the programming line. |
| US10262582B2 |
Image sticking compensating device and display device having the same
A image sticking compensating device according to example embodiments includes a degradation calculator configured to calculate a degradation weight based on input image data, and to calculate degradation data of a frame, an accumulator configured to accumulate the degradation data, and to generate age data using the accumulated degradation data, and a compensator configured to determine a grayscale compensation value corresponding to the age data and an input grayscale of the input image data, and to output age compensation data by applying the grayscale compensation value to the input image data. |
| US10262571B2 |
Method and apparatus for controlling image display of WOLED display apparatus and display apparatus
The present disclosure provides a method and an apparatus for controlling image display of a WOLED display apparatus and a WOLED display apparatus. The method includes: converting gray scale data of respective lights with various colors inputted by a signal source into brightness data of the respective lights with various colors; acquiring brightness adjustment data of white sub-pixel lights and brightness adjustment data of the respective lights with various colors on the basis of the brightness data of the respective lights with various colors and proportions of the respective lights with various colors in the white sub-pixel lights; converting the brightness adjustment data of white sub-pixel lights and brightness adjustment data of the respective lights with various colors into gray scale data and outputting and displaying the gray scale data. The above method and apparatus provides a simple calculating method when adjusting the display data and may eliminate color cast. |
| US10262566B2 |
Shift register, gate driving circuit and display apparatus
A shift register is disclosed which includes at least one shift register unit group. Each shift register unit group includes a plurality of stages of shift register units cascaded to one another, each of the plurality of stages of shift register units including a pull-up node and a pull-up node reset terminal. The pull-up node of an (n+k)-th stage of shift register unit of each shift register unit group is connected to the pull-up node reset terminal of an n-th stage of shift register unit of the shift register unit group. Also disclosed are a gate driving circuit and a display apparatus. |
| US10262563B2 |
LED display
This application provides a LED display by utilizing flexible wires and the locations of the conductive pins on the bottom side of each single color LEDs or full color LEDs to make each of the single color LEDs or full color LEDs mount on each pixel defined by the flexible wires formed on a transparent substrate, and this LED display is characterized in separating the wires crossing with each other by a so-called bridge technology and utilizing a single-layered substrate to save costs of processes and materials. |
| US10262561B2 |
Self laminating labels
A labeling assembly is shown and described herein. A labeling assembly for laminating labels may include a label sheet, a laminating sheet and an alignment member. The alignment member may allow folding of the label sheet and laminating sheet. The label sheet may include a facestock sheet and a liner sheet. Labels may be pre-cut in the facestock sheet. The laminating sheet may include a laminae film sheet and a liner sheet. Protective covers may be pre-cut in the liner sheet and laminae overlays may be pre-cut in the laminae film sheet. The protective covers may be removed to expose an adhesive portion of the laminae overlay. The label sheet and the laminating sheet may be folded onto each other at the alignment member. The laminae overlay may include an image thereon and adhere to the label to form a removable laminated label. |
| US10262558B2 |
Celestial globe assembly
A celestial globe assembly includes a celestial body pointing pen. The celestial body pointing pen includes a light emitting mechanism. The celestial body pointing pen includes a reference marking at a bottom end. The celestial globe assembly includes a celestial globe. The celestial globe includes a spherical body. The spherical body has at least one star marking on a surface of the spherical body. The celestial globe assembly includes a celestial body recording cover. The celestial body recording cover is in semi-spherical shape. The celestial body recording cover is at least partially transparent such that a user can see through. |
| US10262555B2 |
Facilitating awareness and conversation throughput in an augmentative and alternative communication system
Speech generating devices, communication systems, and methods for communicating using the devices and systems are disclosed herein. In certain examples, a communication system is configured to receive a generated communication, establish a connection between a speech generating device and a computing device subsequent to receipt of the generated communication, and transmit the generated communication to the computing device. In other examples, a computing device is configured to establish a connection with a speech generating device, and receive a transmission generated by the speech generating device following the connection, the transmission including previously generated communications or real-time communication segments or proxies. In other examples, a speech generating device is configured to establish a connection with one or more computing devices, receive one or more suggestions from at least one computing device during generation of the communication, and display a suggestion on the display device as a shortcut input key. |
| US10262552B2 |
Ball movement state measuring system and method thereof
In a ball movement state measuring system with a ball, a sensing module, a wireless communication module, a power supply and an induction coil, the speed, rotation speed, rotation axis and trace of the ball at first movement state are calculated based on first accelerated speed and first angular velocity of the ball at first movement state and first movement result is obtained by the processor. The speed, rotation speed, rotation axis and trace of the ball at second movement state are calculated based on speed and rotation axis of the ball at first movement state, second accelerated speed and environment parameter of the ball at second movement state and second movement result is obtained by the processor. The ball is forced by gravity, applied force and air resistance at first movement state, and the ball is forced by gravity, air resistance and centripetal force at second movement state. |
| US10262550B2 |
Dynamic feedback and scoring of transcription of a dictation
An automated system and method for transcription of a dictation presents a transcription exercise to a student that allows continuous student keyboarding of text while providing real time feedback of correct, incorrect, and misplaced characters as well as visually pointing out the location of missing letters and missing words. The real time designation is shown using differences in typeface style or color and using a scoring system that factors in substantially all keystrokes. Not only is final correctness assessed, but also the difficulty in getting to the final state of correctness is assessed. |
| US10262548B2 |
Methods and systems for virtual problem based learning
A computer-implemented method includes selecting, by a virtual problem-based learning (PBL) system, information indicative of a medical profile of a patient; accessing, by the virtual PBL system, information indicative of a team of students using the virtual PBL system; generating, by the virtual PBL system and based on the medical profile, an medical PBL schema comprising a medical problem to be solved by the team of students; generating a plurality of sections in the medical PBL schema, with each section promoting solving of the medical problem, and with each section associated with (i) a private work environment for a student to privately analyze the medical problem, and (ii) a shared, anonymous work environment for the students to view analysis performed by other students in solving the medical problem; and transmitting, to one or more client systems used by the students participating in the virtual problem-based learning system, the medical PBL schema. |
| US10262541B2 |
Convoy travel control apparatus
This convoy travel control apparatus includes: a communication portion; a travel control portion; and a joining control portion, wherein when an own vehicle is travelling in convoy, if the communication portion has received, from an independent vehicle not incorporated in group of convoy vehicles travelling in convoy, request information to incorporate the independent vehicle into the group of convoy vehicles, then the joining control portion determines a positional relationship between a position of the group of convoy vehicles and a position of the independent vehicle, and wherein according to the determined positional relationship, then the joining control portion exercises control, which is for incorporating the independent vehicle into the group of convoy vehicles, on the group of convoy vehicles via the communication portion. |
| US10262539B2 |
Inter-vehicle warnings
A host vehicle includes: motor(s), sensors, processor(s) configured to: (a) iterate a series of future properties, comprising future positions, of nearby first and second vehicles based on determined current properties thereof; (b) associate a blindspot with an iterated future position of the second vehicle; (c) determine whether a future position of the first vehicle occupies the blindspot; (d) if so, transmit a message to the second vehicle including a message activation time. |
| US10262537B1 |
Autonomous optimization of parallel parking space utilization
In an example embodiment, a computer-implemented method is disclosed that broadcasts a request for a parking space, receives response(s) from responsive vehicle(s), and extracts set(s) of response data from the received response(s). Each set corresponds to a responsive vehicle and includes a vehicle attribute and a situational context for that corresponding responsive vehicle. The method further generates a dynamic parking model based on the vehicle attribute and the situational context included in each set of response data. The dynamic parking model maps estimated position(s) of the responsive vehicle(s) and further identifies, for each responsive vehicle, estimated unutilized distance(s) between the responsive vehicle and surrounding object(s) corresponding to the responsive vehicle. The method further determines, from the responsive vehicle(s), a group of one or more relocatable vehicles based on the dynamic parking model, and instructs the group to relocate to create the requested parking space. |
| US10262536B2 |
Method and apparatus for charging station monitoring
A system includes a processor configured to receive indication that a chargeable vehicle is within proximity to a known charging point. The processor is also configured to determine if the charging point is available for immediate use. The processor is further configured to notify a vehicle driver if the charging point is available for immediate use and offer an option to receive notification when a charging point is available for use if the charging point is not available for immediate use. |
| US10262534B2 |
System for avoiding collision with multiple moving bodies
When turning right (left) at an intersection and crossing an oncoming vehicle lane, this system makes it possible to avoid blocking travel of or colliding with a moving body moving in the oncoming vehicle lane due to stopping in the oncoming vehicle lane, and to avoid colliding with a moving body after crossing the oncoming vehicle lane. Given two or more moving bodies present in the advancement direction on the path of the local vehicle, the external environment is detected before the local vehicle intersects with the path of a first moving body, which will first intersect the local vehicle path; if at least two moving bodies are detected, i.e., the first moving body and a second moving body which has a path in which the position of intersection with the path of the local vehicle is further than the position of intersection between the path of the local vehicle and the path of the first moving body, then a first intersection time, at which the first position of intersection between the planned path of the local vehicle and the predicted path of the first moving body is reached, and a second intersection time, at which a second position of intersection between the planned path of the local vehicle and the predicted path of the second moving body is reached, are calculated, and on the basis of the difference between the first intersection time and the second intersection time, the deceleration relative to the first moving body and the second moving body is changed. |