最新美国发明专利
Document Document Title
US09948349B2 IOT automation and data collection system
A system and method for automating a deployment site served by a distributed antenna system (DAS) is disclosed. The deployment site is configured with a plurality of remote antenna units (RAU). At least one of the plurality of remote antenna units includes a first transceiver for uplinking and downlinking a signal of a cellular service and at least one second transceiver for uplinking a signal of at least one electrical element. Data from the at least one second transceiver received from an electrical element is collected and routed to an electrical element data collector configured to aggregate the collected data. Adjustments to and optimization of a device within the deployment site are based on the collected data.
US09948347B2 Calibrating a transceiver circuit
A method of calibrating a transceiver circuit including transmission circuitry for processing an input signal to produce an output signal including the input signal modulated onto a carrier signal, and reception circuitry arranged to take a modulated signal including a signal modulated onto a carrier signal and to output the signal demodulated from the carrier signal. The method includes: selectively coupling the transmission circuitry to the reception circuitry; introducing a reference signal into the transmission circuitry, the reference signal causing a plurality of components of different frequencies to be present in a calibration signal in the reception circuitry; measuring the power, and typically the received signal strength indication (RSSI) of the calibration signal including the plurality of components; and adjusting operation of the transmission and reception circuitry to increase the amplitude of a first set of the components relative to the amplitude of a second set of the components.
US09948340B2 Wearable modular mobile device including a rotatable display
There is disclosed a mobile terminal including a base body wearable on a user's body, a module body detachably coupled to the base body, a rotary unit coupled to a rear surface of the module body or an upper surface of the base body, the rotary unit comprising a rotary hinge portion provided in a center of the rotary unit, and a first coupling portion and a second coupling portion provided in a rear surface of the rotary unit and a front surface of the base body or a front surface of the rotary unit and a rear surface of the module body, respectively, the second coupling portion detachably coupled to the first coupling portion. The module body may be relatively rotated with respect to the base body. Accordingly, the functions of the mobile terminal can be converted and intuitive operation can be performed.
US09948335B2 Signal processing device, control method thereof, control procedure and recording medium
The invention relates to a signal processing device, a control method thereof, a control procedure and a recording medium, which is unnecessary to increase a memory capacity for implementing sampling to determine a filter parameter. The signal processing device includes a data acquiring element (10), acquiring signals of a time series, i.e. time series signals from a sensor; a filtering element (21), performing a filtering operation according to frequencies; a transfer element (30), transferring the time series signals; and a filter parameter determination element (50), performing frequency analysis to the time series signals within a pre-specified interval, i.e. a specified interval to determine a filter parameter.
US09948334B2 Systems and methods for cancellation of cross-coupled noise
Systems and methods for canceling cross-coupled satellite signals in a LNB IC include receiving a first satellite signal at a first input of the LNB IC and filtering the first satellite signal using a first adaptive filter, the first adaptive filter having first filter coefficients; combining the adjusted first satellite signal with a second satellite signal received at a second input of the LNB IC to generate a first combined satellite signal; measuring the total output power of the combined satellite signal; changing the filter coefficients of the first adaptive filter; remeasuring the total output power of the first combined satellite signal after the changing of the first filter coefficients to determine whether the total power of the first combined satellite signal has decreased.
US09948329B2 Radio-frequency integrated circuit (RFIC) chip(s) for providing distributed antenna system functionalities, and related components, systems, and methods
Radio-frequency (RF) integrated circuit (RFIC) chip(s) allow for the integration of multiple electronic circuits on a chip to provide distributed antenna system functionalities. RFIC chips are employed in central unit and remote unit components, reducing component cost and size, increasing performance and reliability, while reducing power consumption. The components are also easier to manufacture. The RFIC chip(s) can be employed in distributed antenna systems and components that support RF communications services and/or digital data services.
US09948319B2 Data compression/decompression system, data compression method and data decompression method, and data compressor and data decompressor
In a data compression method, a data string is compressed in units of symbols, each of the symbols being data having a fixed length. Then, a conversion table in which an entry indicating a correspondence between two or more pre-conversion symbols and one post-conversion symbol is registered is searched, and if it is determined that two or more consecutive symbols in the data string are not registered as two or more pre-conversion symbols, an entry in which the two or more consecutive symbols are registered as two or more pre-conversion symbols is registered in the conversion table, and the two or more consecutive symbols are output without conversion, and if two or more consecutive symbols in the data string are registered as two or more pre-conversion symbols in an entry in the conversion table, the two or more consecutive symbols are converted into one post-conversion symbol, the one post-conversion symbol being in correspondence with the two or more consecutive symbols in the entry.
US09948317B2 Time-based delay line analog to digital converter
An analog-to-digital converter includes differential digital delay lines, a circuit including a set of delay elements included in the differential digital delay lines, and another circuit including another set of delay elements included in the differential digital delay lines. The first circuit is configured to generate data representing an analog to digital conversion of an input. The second circuit is configured to calibrate a source to the differential digital delay lines.
US09948316B1 Analog-to-digital converter and CMOS image sensor including the same
An analog-to-digital converter includes a ramp signal generation unit suitable for decreasing a voltage range of a ramp signal in reverse proportion to a multiple of a gain and repeatedly generating the ramp signal by the multiple of the gain; a comparator suitable for repeatedly outputting a comparison signal by the multiple of the gain in response to the ramp signal; and a counter suitable for performing a counting operation in response to the comparison signal.
US09948315B2 Digital to analog converter including logical assistance
Digital to analog converters (DAC) are used to convert digital signals to analog values. The digital system providing data to the analog converter may be highly tasked. A DAC is provided with some in built logic to assist in reducing the load on the devices driving the DAC. The DAC may include a library of functions that it can apply to the input words to modify transitions in the analog output words. The DAC may further include a health checking system for monitoring the digital words being supplied to the DAC and raising a concern, and taking action if required, if the sequence of words is unlikely to be correct or beyond the target operating range.
US09948309B2 Differential odd integer divider
A differential odd integer divider provides low power and compact sub-harmonics of an applied square or sinusoidal clock signal with self-aligned 50% duty cycle. The odd integer divider circuit includes a set of low power delay cells connected in a ring fashion. Each delay cell includes two differential dual port inputs connected to the gates of MOS transistors. For instance, these odd integer dividers include a series of low power latch circuits that are custom configured for minimum headroom and low power consumption. These output phasors can then be combined with an appropriate weight factor to provide a near-sinusoidal waveshape from the input square waveshape. Intrinsic 50% duty cycle maybe shortened or stretched by using combinatorial logic circuits.
US09948308B2 Multi-modulus prescaler with improved noise performance
Design techniques for multi-modulus prescaler circuits that minimize the input-to-output delay dependence on the modulus control state or history. The feed-forward signal path inside a multi-modulus prescaler is identified, as well as all feedback paths connected to the feed-forward signal path. In various embodiments, one or more of several techniques may be applied to reduce capacitive load variations and signal coupling due to the modulus control state or history. For at least one component coupled to the feed-forward signal path and having a feedback path, a buffered feedback path may be created separate but parallel to a buffered feed-forward signal path. Double buffers may be added to some feedback paths directly coupled to the feed-forward path so that the forward signal path is not affected by load variations in such feedback paths.
US09948306B2 Configurable gate array based on three-dimensional printed memory
The present invention discloses a configurable gate array based on three-dimensional printed memory (3D-P). It comprises an array of configurable computing elements, an array of configurable logic elements and a plurality of configurable interconnects. Each configurable computing element can selectively realize a math function from a math library. It comprises a plurality of 3D-P arrays storing the look-up tables (LUT) for the math functions in the math library.
US09948300B1 Apparatuses and methods for partial bit de-emphasis
Apparatuses and methods for partial bit de-emphasis are provided. An example apparatus includes an output driver and control circuit. The output driver includes a pull-up circuit including one or more pull-up legs, and a pull-down circuit including one or more pull-down legs. The control circuit may be coupled to the output driver and configured to receive an input signal having a first logical value and a second logical value, and in response to determining the logical transition has occurred from the second logic value to the first logic value, cause the pull-up circuit and pull-down circuit respectively to enter a first state for a duration of a first portion of a bit period and to enter a second state for a duration of a second portion of the bit period proceeding the first portion.
US09948293B1 Transmitter driver circuits and methods
An integrated circuit includes first and second transmitter driver circuits. The first transmitter driver circuit includes a first pull-up circuit and a first pull-down circuit that are configured as a first voltage mode driver to drive a first single-ended output signal to a first pad during a voltage mode operation. The second transmitter driver circuit includes a second pull-up circuit and a second pull-down circuit that are configured as a second voltage mode driver to drive a second single-ended output signal to a second pad during the voltage mode operation. The first and second pull-up circuits and the first and second pull-down circuits drive a differential output signal to the first and second pads during a current mode operation when the first and second transmitter driver circuits are configured as a current mode driver.
US09948292B2 Bidirectional integrated CMOS switch
A bidirectional integrated CMOS switch is provided which is capable of switching voltages beyond the range of the supply and ground potentials. The switch is composed of NMOS and PMOS transistors as the switch conductor path, a diode bridge, and control circuitry to turn the switch on and off by means of low voltage logic, regardless of the voltages on the switch terminals. The device and method of the invention enables the switching of high voltage loads operating at arbitrary or floating voltages relative to the low voltage power supply and ground, and provides on/off control of the switch with ordinary low voltage logic levels. The invention provides bidirectional switching without conducting through the parasitic body diodes of the CMOS devices.
US09948289B2 System and method for a gate driver
In accordance with an embodiment, method of controlling a switching transistor includes applying a first voltage to a first node of a switchable tank circuit, where the first node is coupled to a control node of the switching transistor, the first voltage has a first polarity with respect to a reference terminal of the switching transistor, and the first voltage is configured to place the switching transistor into a first state. After applying the first voltage, the switchable tank circuit is activated, where a voltage of the first node transitions from the first voltage to a second voltage that is configured to place the switching transistor in a second state different from the first state. The switchable tank circuit is deactivated after the voltage of the first node attains the second polarity.
US09948287B2 Level-shift circuits compatible with multiple supply voltage
A level-shift circuit, receiving a supply voltage and a input signal, includes a pre-stage voltage conversion circuit and a post-stage voltage conversion circuit. The pre-stage voltage conversion circuit includes a first voltage protection module generating an inner conversion voltage and a first voltage conversion module converting the input signal into a pre-stage output signal according to the inner conversion voltage. The post-stage voltage conversion circuit includes a second voltage protection module generating a first inverse output signal, a first output signal, a second inverse output signal, and a second output signal. The transistors of the pre-stage voltage conversion circuit and the post-stage voltage conversion circuit have a punch-through voltage. The level-shift makes the stress of the transistors less than the punch-through voltage when the supply voltage is greater than the punch-through voltage, and remains the driving capability when being less than the punch-through voltage.
US09948283B2 Semiconductor device
When a signal of high amplitude is outputted, a drain-to-source voltage exceeding a withstand voltage may be applied. The semiconductor device according to the present invention includes a level shift circuit that outputs a high amplitude signal from the input of a low amplitude logical signal. The level shift circuit includes a series coupling circuit, a first gate control circuit coupled to a first power supply, a second gate control circuit coupled to a second power supply of a potential higher than the potential of the first power supply, and a potential conversion circuit arranged between the first gate control circuit and the series coupling circuit. The potential conversion circuit supplies a first level potential, which is lower than the potential of the first power supply and higher than the potential of the reference power supply, to a gate of an N-channel MOS transistor of the series coupling circuit.
US09948281B2 Positive logic digitally tunable capacitor
Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.
US09948280B1 Two-capacitor-based filter design method and two-capacitor-based filter
Disclosed is a two-capacitor-based filter design method comprising: determining a frequency f1 and a fractional bandwidth ratio FBW; selecting a first and a second capacitors according to f1 and FBW, in which a resonant frequency fC1 of the first capacitor is equal to f1×(1−N×FBW), a resonant frequency fC2 of the second capacitor is equal to f1×(1+M×FBW), and each of N and M is a positive number less than one; and determining a length of a first transmission line according to fC1 and a signal speed, and determining a length of a second transmission line according to fC2 and the signal speed. The first capacitor is coupled between a center of the first transmission line and ground, the second capacitor is coupled between a center of the second transmission line and ground, and the first and second transmission lines are connected in series.
US09948278B2 Filter device having a filter connection conductor line including parallel connected conductor lines
In a filter device, a first filter and a second filter are connected to a common connection point by a filter connection conductor line including a first conductor line portion, and a parallel connection area with an electrical length shorter than that in a single conductor line is provided in the first conductor line portion.
US09948277B2 Method of optimizing input impedance of surface acoustic wave filter
Methods of designing band-pass filters are disclosed. A baseline filter design is established, the baseline filter design including a plurality of surface acoustic wave resonators having respective resonant frequencies, the surface acoustic wave resonators organized by resonant frequency into two or more groups. One or more alternative filter designs are established, each alternative filter design derived from the baseline filter design by reordering the resonant frequencies of two or more surface acoustic wave resonators within at least one of the two or more groups. A respective performance metric related to input impedance over a pass band is calculated for each of the baseline filter design and the alternative filter designs. A final filter design is selected from the baseline filter design and the alternative filter designs based on the respective performance metrics.
US09948273B1 Temperature stable MEMS resonator
A resonant member of a MEMS resonator oscillates in a mechanical resonance mode that produces non-uniform regional stresses such that a first level of mechanical stress in a first region of the resonant member is higher than a second level of mechanical stress in a second region of the resonant member. A plurality of openings within a surface of the resonant member are disposed more densely within the first region than the second region and at least partly filled with a compensating material that reduces temperature dependence of the resonant frequency corresponding to the mechanical resonance mode.
US09948265B2 Inductor capacitor tank for resonator
An inductor capacitor (LC) tank includes a first inductor and a first tunable capacitive array. The first inductor has a first terminal and a second terminal, and the first tunable capacitive array has a first terminal and a second terminal. The first tunable capacitive array is at a path branching from a first point between the first terminal and the second terminal of the first inductor, the first terminal of the first tunable capacitive array is coupled to the first point, and the second terminal of the first tunable capacitive array and the second terminal of the first inductor are coupled to a reference voltage.
US09948262B2 Adaptive supply voltage for a power amplifier
In one embodiment, a signal-processing apparatus for generating an amplified output signal based on an input signal is provided. The apparatus comprises: an amplifier configured to generate the output signal, wherein the amplifier is configured to receive a supply voltage; and a limiter configured to inhibit increases in the input signal power level from being applied to the amplifier, wherein the limiter comprises: a variable attenuator configured to selectively attenuate the input signal before being applied to the amplifier; wherein the limiter integrates over a voltage difference between a current measure of attenuated input signal power level and a limiter threshold level to control a level of attenuation applied by the variable attenuator to the input signal.
US09948259B2 Noise-based gain adjustment and amplitude estimation system
Methods and systems for amplitude estimation and gain adjustment using noise as a reference are described. An example receiver can include an antenna and a front end amplifier coupled to the antenna. The receiver can also include a detector circuit coupled to the front end amplifier. The receiver can be configured to determine a power of a received signal at the antenna based on a gain of the receiver. The gain of the receiver can be determined based on a noise figure of the front end amplifier and a noise amplitude.
US09948252B1 Device stack with novel gate capacitor topology
Systems, methods and apparatus for practical realization of an integrated circuit comprising a stack of transistors operating as an RF amplifier are described. As stack height is increased, capacitance values of gate capacitors used to provide a desired distribution of an RF voltage at the output of the amplifier across the stack may decrease to values approaching parasitic/stray capacitance values present in the integrated circuit which may render the practical realization of the integrated circuit difficult. Coupling of an RF gate voltage at the gate of one transistor of the stack to a gate of a different transistor of the stack can allow for an increase in the capacitance value of the gate capacitor of the different transistor for obtaining an RF voltage at the gate of the different transistor according to the desired distribution.
US09948251B2 Low noise amplifier (LNA) system
A low noise amplifier (LNA) system having a constant noise factor (Const-NF) mode and a constant third-order intercept (Const-IP3) mode is disclosed. The LNA system includes an LNA core and a trade-off bias network coupled to the LNA core to selectably bias the LNA core to realize the Const-NF mode and the Const-IP3 mode. The trade-off bias network is made up of selectable Const-NF circuitry and selectable Const-IP3 circuitry. The LNA system further includes a bias switching controller that is configured to enable the selectable Const-NF circuitry and disable the selectable Const-IP3 circuitry to select the Const-NF mode in response to a first condition and to disable the selectable Const-NF circuitry and enable the selectable Const-IP3 circuitry to select the Const-IP3 mode in response to a second condition.
US09948248B2 Low noise amplifier circuit
An amplifier for converting a single-ended input signal to a differential output signal. The amplifier comprises a first transistor, a second transistor, a third transistor and a fourth transistor. The first transistor, configured in common-source or common-emitter mode, receives the single-ended input signal and generates a first part of the differential output signal. The second transistor, also configured in common-source or common-emitter mode, generates a second part of the differential output signal. The third and fourth transistors are capacitively cross-coupled. The amplifier further comprises inductive degeneration such that a source or emitter of the first transistor is connected to a first inductor and a source or emitter of the second transistor is connected to a second inductor.
US09948241B2 Apparatus and methods for reducing inductor ringing of a voltage converter
Apparatus and methods for reducing inductor ringing of a voltage converter are provided. In certain configurations, a voltage converter includes an inductor connected between a first node and a second node, a plurality of switches, and a bypass circuit having an activated state and a deactivated state. The switches includes a first switch connected between a battery voltage and the first node, a second switch connected between the first node and a ground voltage, a third switch connected between the second node and the ground voltage, and a fourth switch connected between the second node and the output. The bypass circuit includes a first pair of transistors connected between the first node and the second node and configured to turn on to bypass the inductor in the activated state and to turn off in the deactivated state.
US09948236B2 Resonator having distributed transconductance elements
A method includes forming a resonator comprising a plurality of switched impedances spatially distributed within the resonator, selecting a resonant frequency for the resonator, and distributing two or more transconductance elements within the resonator based on the selected resonant frequency. Distributing the two or more transconductance elements may include non-uniformly distributing the two or more transconductance elements within the resonator.
US09948234B2 Spectrum shaping voltage to current converter
A voltage controlled oscillator (VCO) is disclosed. The VCO includes an amplifier that receives a control signal and a feedback signal and generates an amplified output signal based on the difference between the control signal and the feedback signal. The VCO also includes circuitry to generate an oscillating output signal based on the amplifier output signal. Additionally, the VCO includes a feedback amplifier that generates the feedback signal based on the output of the amplifier. The feedback amplifier includes a first resistor connected in parallel with a second resistor, the second resistor having an adjustable resistance.
US09948230B2 Device for controlling a motor vehicle alternator, and corresponding alternator
The invention relates to a device for controlling an alternator of the type that controls a DC voltage (B+A) generated by the alternator (11) according to a predetermined set voltage (U0) by monitoring the intensity of an energizing current (IEXC) flowing through an energizing circuit of the alternator. According to the invention, the device includes a voltage-control loop (7) and a temperature-control loop (17) which comprises a temperature sensor supplying a current temperature (T) of components of the alternator, a subtracter (19) supplying a temperature error (ϵt) between the current temperature (T) and a maximum acceptable temperature (Tmax) and a control module (20) supplying a maximum admissible energizing percentage (rmax) in accordance with the temperature error according to a predetermined control law.
US09948227B2 Divided phase AC synchronous motor controller
A circuit for a motor comprises at least two phase windings forming one half of motor phase windings of the circuit and at least two other phase windings forming another half of the motor phase windings of the circuit. A direct current (DC) power supply receives alternating current (AC) power transferred from one or more of the motor phase windings and converts the AC power to DC power. A first stage power switch circuit comprising at least one power switch is connected between the at least two phase windings on the one half of the motor phase windings of the circuit and between the at least two other phase windings on the other half of the motor phase windings of the circuit. A second stage power switch circuit comprising at least one other power switch is connected between the one half of the motor phase windings of the circuit and the other half of the motor phase windings of the circuit, the at least one other power switch to receive AC power from one or more of the motor phase windings. At least one non-collapsing DC power supply component prevents the DC power supply from collapsing when the at least one power switch is on.
US09948226B2 Apparatus for driving voice coil actuator of camera and method thereof
An apparatus for driving a voice coil actuator of a camera and a method thereof are provided. The driving apparatus performs input shaping based on a resonance frequency of a voice coil actuator and damping of vibration in the voice coil actuator to generate a control signal using a shaping signal as an initial input from an unshaped control signal, and thereby drives the voice coil actuator using the control signal subjected to input shaping. The shaping signal is provided to remove the resonance of the voice coil actuator, and may be a pure shaping signal, such as a multi-step shaping signal or a toggle shaping signal, or a convoluted shaping signal obtained by convoluting such pure shaping signals. The driving apparatus may significantly reduce residual vibration and may enhance an auto-focus function of the voice actuator using input shaping control based on damping.
US09948225B2 Drive and method
A drive, including an electric motor, which is supplied by a rectifier, the rectifier including a time-discrete closed-loop control structure, which regulates the stator current of the electric motor by setting the voltage applied at the motor, the current of the motor being acquired in time-discrete fashion, the closed-loop control structure including a first closed-loop controller whose setpoint is the output value of a first non-linear transfer member, and whose actual value is the output value of a second non-linear transfer member, the input value of the first non-linear transfer member being the setpoint of a first current component of the current, the input value of the second non-linear transfer member being the actual value of a first current component of the current.
US09948224B1 System and method for sensorless control of electric machines using magnetic alignment signatures
A system and method for position sensorless control of an AC electric machine is disclosed. A drive system for driving an AC electric machine provides a primary current excitation to drive the AC electric machine, the primary current excitation comprising a current vector having a magnitude and angle. The drive system injects a carrier signal to the AC electric machine that is superimposed onto the current vector, with the carrier signal being selected to generate a carrier response signal that has sensitivity to magnetic alignment information of the AC electric machine at its operating point. The drive system measures at least one magnetic alignment signature of the AC electric machine from the generated carrier response signal and controls an orientation of the current vector using the measured at least one magnetic alignment signature, so as to achieve a desired magnetic operation of the AC electric machine.
US09948222B2 Drive method for non-contact power supply device, non-contact power supply device, and non-contact power supply system
A power supply device (2) is provided with a push-type power generator (4). When a push-button (5) on the push-type power generator (4) is pushed, a variable voltage is generated by a piezoelectric element (6) that excites a primary coil (L1). A high-frequency inverter (8) is activated by the variable voltage, exciting the primary coil (L1), and an alternating field is generated from the primary coil (L1). Secondary power can be supplied by means of the alternating field even if a secondary coil (L2) of an electrical device (10), disposed on a surface of a wall (1) opposite the surface on which the charging device (2) is disposed, is not in contact with the power supply device (2). The secondary coil (L2) of the electrical device (10) causes a light-emitting diode (LED1) to illuminate using secondary power obtained by non-contact power supply.
US09948221B2 Method and system for eliminating low frequency oscillation between generators
A method and system for eliminating the low-frequency oscillation between generators. By way of measuring the absolute rotor angle of a generator and controlling the rotor rotational speed, the absolute rotor angles obtained through measurement are the same when each GPS pulse per second signal arrives. The absolute rotor angles are angles of the internal potential Eq of the generator leading a GPS reference vector. Through the absolute rotor angle, zero steady state error control of the frequency and the rotor angle is achieved and the position of the generator rotor can remain unchanged in the PPS determined rotating coordinate system, thus suppressing the low-frequency oscillation better even without the need of remote measurement and achieving automatic local balance of active power during variation of loads. Accordingly, the power fluctuation on transmission lines is decreased while safe and stable operation of a large-scale interconnected power grid is achieved.
US09948213B2 Magnetostrictive power supply for bottom hole assembly with rotation-resistant housing
A power supply includes a rotor having an undulated surface (658, 858, 958, 10, 58) and a magnetostrictive material disposed adjacent to the undulated surface. The undulated surface alternatingly compresses the magnetostrictive material as the rotor rotates, inducing an electric current in a conductor coupled to the magnetostrictive material.
US09948212B2 Method and technique to control MEMS DVC control waveform for lifetime enhancement
The present invention generally relates to a method of operating a MEMS DVC while minimizing impact of the MEMS device on contact surfaces. By reducing the drive voltage upon the pull-in movement of the MEMS device, the acceleration of the MEMS device towards the contact surface is reduced and thus, the impact velocity is reduced and less damage of the MEMS DVC device occurs.
US09948207B2 Inverter control apparatus
There is provided an inverter control apparatus, a capacitor being provided on an AC side of the inverter. The apparatus includes a system voltage detector detects a system voltage, a differentiation unit calculates a differential value of the system voltage, a correction current instruction value calculator calculates a correction current instruction value for correcting a current instruction value set for an output current of the inverter, based on the differential value of the system voltage, a current instruction value correction unit corrects the current instruction value, based on the correction current instruction value, and a controller controls the inverter based on the current instruction value.
US09948206B2 Multilevel power conversion device with flying capacitor
A multilevel power conversion device includes: N (N≥1) direct current voltage sources; a first flying capacitor; a second flying capacitor; and a phase module of a M phase (M≥2) being configured to output, from the output terminal, a potential of one of the input terminals, or a potential obtained by adding or subtracting the voltage of the capacitor to or from the potential of the one of the input terminals, by selectively controlling the respective switching elements in an ON/OFF manner.
US09948205B2 AC line filter and AC-to-DC rectifier module
An AC line filter module includes AC-to-DC rectification circuitry. The rectification circuitry includes four low forward voltage rectifiers coupled together as two high-side rectifiers and two low-side rectifiers, where each low forward voltage rectifier includes an NPN bipolar transistor and a parallel-connected diode. A current splitting pair of inductors splits a return current so that a portion of the current is supplied to the collector of an NPN bipolar transistor that is on, and so that the remainder of the current is supplied to the base of the transistor that is on. Both low-side rectifiers are driven by these current splitting inductors. A pair of base current return diodes provides base current return paths. Due to the use of NPN bipolar transistors and no PNP bipolar transistors, manufacturing cost is reduced and efficiency is improved as compared to an implementation that uses low forward voltage rectifiers having PNP transistors.
US09948204B2 Method and apparatus for controlling resonant converter output power
A method and apparatus for controlling power conversion. In one embodiment, the method comprises computing a voltage ratio based on a voltage conversion in a resonant converter; comparing the voltage ratio to a threshold; and controlling, independent of switching frequency of the resonant converter, power output from the resonant converter based on whether the voltage ratio satisfies the threshold.
US09948203B2 Direct-current power supply device and electric motor driving device
A direct-current power supply device includes a reactor, one end of which is connected to one output end of an alternating-current power supply, a switching unit for short-circuiting the other end of the reactor and the other output end of the alternating-current power supply, a rectifying unit configured to rectify an alternating-current voltage supplied from the alternating-current power supply and generate a voltage equal to or higher than a double voltage, a smoothing capacitor connected to the rectifying unit via backflow preventing diodes and configured to smooth a direct-current voltage output from the rectifying unit, and a control unit configured to control the switching unit and stop the supply of the alternating-current voltage to the rectifying unit in a predetermined period after a predetermined time has elapsed from a zero cross point of the alternating-current voltage output from the alternating-current power supply.
US09948200B2 Charge and discharge circuit, control method for charge and discharge circuit, control device for charge and discharge circuit, and direct power converter
A first capacitor is connected between first and second power supply lines. A reactor is connected in series with the first power supply line or the second power supply line. A single-phase AC voltage is applied to a rectifying circuit. The rectifying circuit, which includes the first capacitor and the reactor, outputs a rectified voltage to the first and second power supply lines. A buffer circuit includes a second capacitor provided between the first and second power supply lines. The buffer circuit discharges the second capacitor at a controllable duty ratio. A booster circuit boosts the rectified voltage to charge the second capacitor. A DC current to be input to the booster circuit is reduced more as a voltage across the reactor is higher.
US09948198B2 Resonant converter and switching power supply device
A resonant inverter includes a first switch element and a second switch element that are alternately turned on and off, a first capacitor and a second capacitor, a first inverter section constituted by the first switch element and the first capacitor, and a second inverter section constituted by the second switch element and the second capacitor. A first coil and the first capacitor constitute a first resonant circuit included in the first inverter section, and the first coil and the second capacitor constitute a second resonant circuit included in the second inverter section, thereby forming a resonant converter.
US09948194B2 DC/DC converter including phase shift control
In a DC/DC converter, a first switching circuit is connected between a first winding of a transformer and a DC power supply, and a second switching circuit is connected between a second winding and a battery. In charging the battery, a control circuit controls respectively phase shift amounts of first and second diagonal elements in the first and second switching circuits relative to the drive phase of a first reference element in the first switching circuit. During a step-up charge control period, if charge current is positive or zero, the control circuit performs control so that the phase shift amount becomes greater than the phase shift amount by an amount exceeding a short-circuit prevention time for the switching elements, allowing step-up operation to be performed, improving controllability in step-up control.
US09948193B2 Galvanically isolated DC-DC converter with bidirectional data transmission
A galvanic isolation is provided between a first circuit and a second circuit. A first galvanically isolated link is configured to transfer power from a first circuit to a second circuit across the galvanic isolation. A second galvanically isolated link is configured to feed back an error signal from the second circuit to the first circuit across the galvanic isolation for use in regulating the power transfer and further configured to support bidirectional data communication between the first and second circuits across the galvanic isolation.
US09948190B2 Power control module for an electronic converter, related integrated circuit, electronic converter and method
A power control module for an electronic converter is disclosed. The electronic converter includes a power stage comprising two input terminals for receiving a first power signal and two output terminals for providing a second power signal. The electronic converter includes, moreover, a control circuit configured to control operation of the power stage as a function of a feedback control signal. In particular, the power control module includes a pre-elaboration module configured to generate a reference signal as a function of the feedback control signal and a first signal being representative of a voltage applied to the two input terminals. An error amplifier is configured to generate a modified control signal as a function the reference signal and a second signal being representative of a current flowing through the two input terminals.
US09948184B2 Current balance method for multiphase switching regulators
A regulator circuit includes a multiphase ramp generator circuit, an amplifier circuit configured to receive a plurality of phase sense signals and provide a plurality of respective error signals, and an adder circuit configured to receive the error signals and ramp generator signals. The ramp generator signals are received from the multiphase ramp generator circuit and the adder circuit is configured to provide a plurality of respective adjusted ramp generator signals. The regulator can be a multiphase switching regulator circuit.
US09948182B2 LC pulse forming network substitution for rayleigh networks in pulsed power applications
A DC-DC power converter having a power source, a load, and a transmission line terminated at one end. A first switch is electrically connected between the power source and a second end of the transmission line and movable between an open and a closed position. A second switch is electrically connected between the second end of the transmission line and the load and is movable between an open and a closed position. A switch control circuit switches the first and second switches between their respective open and closed positions. A pulse forming network forms the transmission line to store the charge in the transmission line.
US09948181B2 Circuits and methods to linearize conversion gain in a DC-DC converter
Described examples include DC-DC power conversion systems, apparatus and methods for linearizing a DC-DC circuit conversion gain, including a gain circuit providing an output signal according to a gain value and the difference between a first compensation signal and a threshold signal, and a switching circuit selectively operative when the first compensation signal exceeds the threshold signal to linearize the conversion gain by providing a second compensation signal for pulse width modulation of at least one DC-DC converter switch according to the threshold signal and the gain circuit output signal.
US09948180B2 Switching regulator input current sensing circuit, system, and method
A Buck switching regulator includes first Buck switching regulator circuitry is operable to generate a first output voltage from an input voltage and operable to generate a first sensed voltage having a value that is proportional to an output current being provided by the first Buck switching regulator circuitry. The first Buck switching regulator circuitry receives an input current and operates at a first duty cycle determined by a duty cycle signal. Input current sensing circuitry includes second Buck switching regulator circuitry coupled to the first Buck regulator switching circuitry to receive the duty cycle signal and to receive the first sensed voltage as an input voltage to the second Buck switching regulator circuitry. The second Buck switching regulator circuitry is operable responsive to the duty cycle signal to generate a second output voltage from the first sensed voltage. The second output voltage has a value that is proportional to the input current being supplied to the first Buck switching regulator circuitry. Such a Buck switching regulator can be utilized in a variety of different types of electronic systems, such as laptop computer systems, and can also be used in charging systems in laptop computer and other types of electronic systems.
US09948178B2 Semiconductor device including plurality of booster units
A semiconductor device includes a charge pump circuit having a plurality of booster units which are connected in series between an input terminal and an output terminal, each of the plurality of booster units includes: a main transistor that is diode-connected so as to cause a forward current to flow in a direction from an internal input terminal toward an internal output terminal; a sub-transistor that is connected between a first terminal of the main transistor and a back-gate terminal of the main transistor and has a control terminal connected to a second terminal of the main transistor; a resistor that connects the second terminal of the main transistor and the back-gate terminal of the main transistor; and a capacitor that is connected between the internal output terminal and a clock wire.
US09948175B2 Soft-start control system and method for an isolated DC-DC converter with secondary controller
A DC-DC converter for supplying a gradually increasing voltage via a soft start circuit from a first powered domain to a second unpowered domain. The powered domain may be connected to a primary winding of a first transformer, and the unpowered domain may be connected to the secondary winding of the first transformer. The unpowered domain may respond to an applied voltage from the soft start circuit by supplying a feedback signal to the powered domain via a feedback circuit. The feedback signal indicates the power supplied from the secondary winding of the first transformer to the unpowered domain is satisfactory.
US09948173B1 Systems and methods for short-time fourier transform spectrogram based and sinusoidality based control
A method of controlling the stability of a power converter in a closed-loop control system. The method includes inputting a variable to be controlled such as an output voltage of the power converter to a compensator or mathematical function for processing; determining, using the compensator, an error signal representative of a difference between the output voltage and a reference voltage; evaluating an energy content in a short-time Fourier transform spectrogram of the error signal from the compensator and/or evaluating the sinusoidality shape of the error signal; updating a transfer function of the compensator and other system parameters in accordance with the energy content or sinusoidality.
US09948172B2 Power converter for eliminating ripples
A ripple-eliminating power converter includes a first voltage converter configured to output a first voltage by stepping up or down a DC voltage supplied from a battery cell; a second voltage converter configured to receive the first voltage outputted from the first voltage converter and output a second voltage by stepping up or down the first voltage; and a ripple-eliminating capacitor disposed between the first voltage converter and the second voltage converter to transfer a DC component of the first voltage to the second voltage converter by eliminating an AC component included in the first voltage.
US09948171B1 Positive displacement inductive pump
A positive displacement inductive pump includes a central piston formed of a ferromagnetic material having non-ferromagnetic end pistons that extend from each of its opposite ends. Stationary end walls are mounted to opposite ends of a housing and are centrally bored. First and second inductive coils are alternately energized, causing the central piston and the end pistons to conjointly reciprocate within an axial bore and the end wall central bores, respectively. First and second check valves are positioned outboard of each end wall and allow valve-controlled ingress and egress of material into and out of the axial and central bores. The relative diameters of the central piston and the end pistons are changed to control the relationship between the magnetic force applied and the output pressure for a given volume of fluid.
US09948168B2 Manufacturing method of a stator
A manufacturing method of a stator for manufacturing a stator by mounting a concentrated winding coil wound with a square wire conductor on each of a plurality of teeth in a stator core and welding end of the concentrated winding coil to corresponding end of another concentrated winding coil, characterized in that a first set of concentrated winding coils and a second set of concentrated winding coils are mounted on the teeth, and the welding of each end in the first set of concentrated winding coils and corresponding end in the second set of concentrated winding coils is started while a third set of concentrated winding coils is mounted on the teeth.
US09948167B2 Rotor of motor which uses magnets to achieve variation-free torque
A rotor (10) of a motor includes a rotor core (11) and a plurality of magnets (14a, 14b) which are arranged at a circumferential surface of the rotor core or at the inside of the rotor core, the length of a magnet of the plurality of magnets in the axial direction of the rotor core determined in accordance with the residual magnetic flux density of the magnet. The axial direction length of the magnet is preferably determined by multiplying a reference axial direction length of the magnet with the residual magnetic flux density of the magnet and dividing this by a reference residual magnetic flux density of the magnet.
US09948165B2 Inverter-integrated electric compressor
Provided is an inverter-integrated electric compressor which has improved assembly properties and assembly precision, and improved productivity. In this inverter-integrated electric compressor, a P-N terminal is provided on the inverter device main substrate, and a power source-side cable can be connected to the P-N terminal by inserting a connector provided at one end; by arranging and mounting multiple high-voltage electric components on the back of the main substrate in the area where the P-N terminal is arranged, a filter circuit is provided on the main substrate. The multiple high-voltage electric components are integrally coupled via fitting units provided on the housing cases of one another and are arranged in a prescribed position on the back of the main substrate with a positioning means provided on one of the housing cases.
US09948164B2 Linear motor having optimized power
Linear motor having optimized power, including a U-shaped profiled stator housing, which forms an inner installation space for receiving a winding packet consisting of multiple coils. The installation space is delimited on the cover side by a carriage driven so it is longitudinally displaceable by magnetic force on the stator housing, on which carriage a length scale is fastened, opposite to which a position sensor is arranged in the stator housing. The installation area for the arrangement of the winding packet in the stator housing is uninfluenced by the position sensor also arranged in the stator housing.
US09948162B2 Power tool
A power tool (1; 90) includes a motor (17) having a stator (18) and a rotor (19). The stator (18) includes front and rear insulators (21, 22) respectively disposed forward and rearward of a stator core (20) in an axial direction thereof. At least six coils (23) are respectively wound on the stator (18) such that the coils (23) are wound through the front and rear insulators (21, 22). Winding wires (23a) respectively electrically connect circumferentially-adjacent pairs of the coils (23). A short circuiting device (25) short circuits respective pairs of windings (23a) that are located diagonally or diametrically across from one another.
US09948161B2 Rotor assembly for an electric machine and method for producing a rotor assembly
A rotor assembly for an electric machine includes a rotor having an axis of rotation extending in an axial direction of the rotor and at least one first hole extending parallel to the axis of rotation and radially spaced from the axis of rotation by a first radial distance, and at least one first balancing element for compensating an unbalance of the rotor in rotation about the axis of rotation. The at least one first balancing element can be provided in the at least one first hole and can be fastened in the at least one first hole by means of a press fitting connection between the at least one first hole and the at least one first balancing element. Thus, a simple and economical possibility of balancing the rotor is provided.
US09948159B2 Stator supporting structure for rotating electrical machine and rotating electrical machine including the same
A rotating electrical machine includes an annular stator, a motor case, and an inner frame. The motor case is disposed radially outward of the stator with a prescribed radial gap. The inner frame fixedly supports one end of the stator in the axial direction of the motor case. The inner frame includes a bolt fastening portion coupled to the one end of the stator without being coupled to the motor case, a bolt fastening portion coupled to the motor case without being coupled to the one end of the stator, and a connecting portion connecting the bolt fastening section and the bolt fastening section. The radial rigidity at the connection section of the inner frame is configured to be lower than the radial rigidity of a bottom section of the motor case.
US09948155B2 Sealed robot drive
A transport apparatus including a housing, a drive mounted to the housing, and at least one transport arm connected to the drive where the drive includes at least one rotor having at least one salient pole of magnetic permeable material and disposed in an isolated environment, at least one stator having at least one salient pole with corresponding coil units and disposed outside the isolated environment, where the at least one salient pole of the at least one stator and the at least one salient pole of the rotor form a closed magnetic flux circuit between the at least one rotor and the at least one stator, and at least one seal configured to isolate the isolated environment where the at least one seal is integral to the at least one stator.
US09948148B2 Power transmitting apparatus, method of controlling the same, and power transmission system
Foreign substance detection can be performed with a simple configuration in a power transmission system. A power transmitting apparatus that wirelessly transmits power to a power receiving apparatus, the power transmitting apparatus comprises: determination means for, in a case where an initial impedance value and the detected output impedance value do not match and there is no change in the output impedance value between before and after the transmission of a predetermined detection signal, determining that a foreign substance is present within a predetermined power transmission range, and, in a case where the initial impedance value and the detected output impedance value do not match and there is a change in the output impedance value between before and after the transmission of the predetermined detection signal, determining that a power receiving apparatus is present within the predetermined power transmission range.
US09948145B2 Wireless power transfer for a seat-vest-helmet system
Wireless power transfer system include: a seat configured to support a human and including a first resonator featuring a conductive coil formed by a plurality of loops that each encircle a common first axis, a layer of magnetic material, and a conductive shield; an article of clothing featuring a second resonator having a conductive coil formed by a plurality of loops that each encircle a common second axis, so that when the article of clothing is worn by the human and the human is seated in the seat, the first and second axes are aligned; and a first electronic apparatus positioned in the seat and coupled to the first resonator, and configured to deliver electrical power to the first resonator so that during operation of the system, power is transferred wirelessly from the first resonator to the second resonator.
US09948144B2 Power transmission system and power transmission device used for power transmission system
A power transmission device wirelessly transmits power to a power receiving device rectifying a voltage received and supplying the voltage to a load circuit. The power transmission device includes a power transmitter that makes capacitance or electromagnetic coupling to the power receiver and transmits electric power to the power receiver, a power supply unit that generates electric power to be transmitted to the power receiving device and supplies the electric power to the power transmitter, a load impedance detector that detects a load impedance of the power receiving device based on an electric signal detected in the power transmission device, and a controller that controls the electric power to be generated by the power supply unit such that an output voltage of the rectifying circuit of the power receiving device is equal to or lower than a predetermined voltage based on a detection result of the load impedance detector.
US09948143B2 Contactless power-supply system, contactless adapter, and power-supply device
A contactless adapter (30) installed in a notebook computer (20) has a plug part (31), a telescopic arm (34), a power circuit part (35), and a power-receiving part (40). The power-receiving part (40) is provided with a secondary coil (41) and has a rotatably linked fixed base plate (42) and a rotating base plate (43). Power can be supplied without contact to the notebook computer (20) from a power-supply device (10) via the contactless adapter (30) by expanding the fixed base plate (42) and the rotating base plate (43) to cause the secondary coil (41) to face the primary coil (11) of the power-supply device (10) provided inside the tabletop (2) of a desk (1).
US09948140B2 High efficiency control system for the conversion of electrical energy to thermal energy
An improved control arrangement is used in a high power rectifier and comprises two or more power controllers ganged together in parallel. Each power controller rectifies an AC voltage signal using zero voltage crossing switching to produce a binary switched signal and each power controller is connected to an independent connectable load. Each power controller includes a fast acting binary power switch that selectively connects the respective independent connectable load to the rectified AC voltage signal. The control arrangement selectively activates the power controllers to define a desired connected load. This high power rectifier and control arrangement is advantageously used to provide fast up down power regulation to a grid by selective storage of thermal energy and deriving power from the thermal energy storage system to add fill in power to the grid.
US09948135B2 Systems and methods for identifying sensitive objects in a wireless charging transmission field
Embodiments disclosed herein may generate and transmit power waves that, as result of their physical waveform characteristics (e.g., frequency, amplitude, phase, gain, direction), converge at a predetermined location in a transmission field to generate a pocket of energy. Receivers associated with an electronic device being powered by the wireless charging system, may extract energy from these pockets of energy and then convert that energy into usable electric power for the electronic device associated with a receiver. The pockets of energy may manifest as a three-dimensional field (e.g., transmission field) where energy may be harvested by a receiver positioned within or nearby the pocket of energy.
US09948133B2 Wireless charging method, wireless charging device, and wireless charging system
A wireless charging method includes obtaining charging information of a plurality of electronic devices, and charging the plurality of electronic devices in sequence according to the charging information of the plurality of electronic devices. For each electronic device, a charging resonance frequency is chosen and accordingly the corresponding wireless charging power is provided for charging.
US09948132B2 Wireless charging method and apparatus for handheld mobile terminal
Provided are a wireless charging method and a wireless charging apparatus for a handheld mobile terminal. The method includes: detecting a state of an earphone cord of the handheld mobile terminal in real time (S101); when it is detected that the earphone cord is in the to-be-charged twisted state, connecting the earphone cord, as an electricity receiving coil, to a charging apparatus (S102); after the earphone cord is connected as the electricity receiving coil to the charging apparatus, placing the handheld mobile terminal on or near a charging plate provided with an electricity transmitting coil to enable electromagnetic coupling (S103); and obtaining electric energy, by the handheld mobile terminal, through the electromagnetic coupling between the electricity transmitting coil and the electricity receiving coil, to wirelessly charge a battery of the handheld mobile terminal (S104). Convenience can be brought to a user and the user experience can be improved.
US09948131B2 Multiple-orientation wireless charging
A system includes a charging station and one or more receiving devices receiving wireless power from the charging station. The charging station includes an orientation adaptable antenna (OAA). The OAA may generate a magnetic field component parallel to the plane of the OAA to charge devices oriented at 90 degrees with respect to the OAA. The OAA may generate a magnetic field along different directions within the plane parallel to the OAA. The OAA may be able to adjust the direction of the field to couple to devices with antennas in different orientations. The OAA may further produce a magnetic field normal to the plane of the OAA. The OAA may adjust the relative strengths the various directional components of the magnetic field to align the field normal to the antennas of the receiving devices in up to three dimensions, simultaneously charge receiving devices in different orientations, or both.
US09948130B2 Power supply apparatus
A power supply apparatus includes a power supply unit that wirelessly supplies power to an electronic apparatus, a communication unit that performs a wireless communication with the electronic apparatus, and a control unit that controls a timing for switching a communication process performed by the communication unit and a power supply process performed by the power supply unit.
US09948126B2 Portable terminal having wireless charging module
A portable terminal is provided, including a cover member which is detachably provided at a rear surface of a main body of a terminal, a resonant antenna for a reception unit provided inside of the cover member, a reception circuit unit provided inside of the main body, and a connection unit for connecting the resonant antenna for a reception unit with the reception circuit unit. The portable terminal efficiently receives the signal power provided from a charger by arranging the resonant antenna inside of the cover member, and minimizes the thickness of the portable terminal by providing the reception circuit unit inside of the main body of the terminal.
US09948121B2 Hybrid power type of automatic grease gun
A hybrid power type of an automatic grease gun includes a storage tank to store grease, a discharge part to discharge the grease from the storage tank, a drain port to drain out the grease which is discharged from the discharge part, and a power supply part to supply power to the discharge part, to supply power, which is received from moving equipment in connection with the power of the moving equipment, to a rechargeable battery as power to be charged in the rechargeable battery, to first supply the power charged in the rechargeable battery to the discharge, and to automatically and directly supply the power of the moving equipment to the discharge part when the rechargeable battery is fully discharged.
US09948116B2 Power storage system
A power storage system includes a power storage device and a controller. The power storage device includes a plurality of power storage stacks connected in series. The controller controls a discharge processing based on voltage values of power storage elements in each power storage stack. The controller determines an abnormal state according to a voltage fluctuation after the voltage values are made uniform. The controller performs a first processing when the following conditions i) and ii) are satisfied and performs a second processing when the following conditions i) and iii) are satisfied. The condition i) is that the power storage elements included in the plurality of power storage stacks are divided into a plurality of groups, each group consists of the power storage elements included in a same power storage stack. The condition ii) is that the voltage values of the power storage elements are different in each group. The condition iii) is that, in the plurality of groups in each of which the voltage values are made uniform, the voltage values are different among the plurality of groups.
US09948114B2 Power supply apparatus
A power supply apparatus includes a power supply unit that wirelessly supplies power to an electronic apparatus, a communication unit that communicates with the electronic apparatus, and a control unit that controls, based on whether information regarding the electronic apparatus that is received from the electronic apparatus is updated by the electronic apparatus, power to be supplied from the power supply apparatus to the electronic apparatus.
US09948112B2 Apparatuses and related methods for detecting coil alignment with a wireless power receiver
A wireless power receiver may include a receive coil configured to generate an AC power signal responsive to wireless power transfer from a wireless power transmitter, and control logic configured to detect misalignment of the receive coil and a transmit coil of the wireless power transmitter responsive to a determination of efficiency of wireless power transfer therebetween. A method for operating a wireless power receiver may include detecting misalignment between a receive coil and a transmit coil of a wireless power transmitter responsive to detecting monitoring a value indicative of efficiency of wireless power transfer between the wireless power transmitter and the wireless power receiver, and causing an indication to be provided to a user to assist with correcting the misalignment.
US09948109B2 Power management systems for accepting adapter and solar power in electronic devices
The disclosed embodiments provide a power management system that supplies power to components in an electronic device. The power management system includes a system microcontroller (SMC) and a charger. During operation, the power management system accepts power from at least one of a power adapter and a solar panel. Next, the power management system supplies the power to components in the electronic device without using a converter circuit between the solar panel and the power management system.
US09948108B2 DC-bus controller for an inverter
Provided are DC-bus voltage or DC-bus current controller methods and circuits, for a voltage or current source inverter. A mean value calculator provides an output signal comprising the mean value of the DC-bus voltage or current, which is used as a feedback signal in a closed loop of the voltage or current source inverter controller, such that a ripple in the DC-bus voltage or current is substantially prevented from entering the closed-loop. In some embodiments a droop controller, which may be adaptive, is used in the closed loop with reverse proportional gain. The adaptive droop controller may provide a constant or variable DC-bus voltage or current. Embodiments regulate the DC-bus voltage or current to an optimized value such that power losses for load and grid conditions are minimized or reduced, and voltage and current ripple is minimized. Embodiments may be used in voltage and current source inverters connected to the utility power distribution grid, in power generation systems, in distributed generation systems, and renewable energy systems.
US09948105B2 Data control system
Disclosed embodiments relate to a data control system. In some embodiments, the data control system includes a transmission module configured to add synchronization signal information to data included in a first data stream to generate a second data stream, and a plurality of control modules configured to receive the second data stream from the transmission module. In some embodiments, the data includes power information.
US09948103B2 Method for the computer-aided control of the power in an electrical grid
A method for computer-aided control of power in an electrical grid is provided. The electrical grid has a redetermined rated frequency and includes network nodes that are interconnected via power supply lines, each of the nodes supplying power to or drawing power from the electrical grid. At least part of the nodes are provided with proportional controllers, for which a reference power and/or a proportionality factor is set, and which control the power that is supplied or drawn by each network node based on the difference between the frequency of the voltage in each network node and the rated frequency of the electrical grid. The reference power and the proportionality factor of at least some of the proportional controllers are determined on the basis of solving an optimization problem. The stability and robustness of the operation of the electrical grid is optimized without the need for carrying out complex simulations.
US09948101B2 Passive peak reduction systems and methods
The systems and methods disclosed herein relate to management of peak electrical demand as registered by an electrical utility meter of an electrical utility customer. The metered demand level of the customer may be monitored over a first portion of a demand charge measuring period, then a cumulative amount of energy consumed by the customer in the first portion and a projected total energy consumed during the demand charge measuring period may be calculated. Next, an offset energy amount may be determined that is the amount required to bring a net amount of energy consumed by the customer during the demand charge measuring period to lie within a target value range for the demand charge measuring period. A power source such as a battery may then be controlled to provide the offset energy amount to the customer over a second portion of the demand charge measuring period.
US09948099B1 Identifying and mitigating risk associated with weather conditions
A system to mitigate weather exposure risk includes a processor operatively coupled to memory. The processor is configured to generate predicted energy consumption based on a model for expected energy usage in response to detection of a weather event, and compare the predicted energy consumption data with energy consumption data. An alert is generated based at least in part on the comparison, and the alert is sent to one or more entities over one or more networks via one or more delivery methods.
US09948094B1 Power level switching circuit for a dual port adapter
A power brick includes a first port configured to provide power to a first computing device, a second port configured to provide power to a second computing device, a first switch coupled to the first port and configured to select one of a first power configuration and a second power configuration based on a load associated with the second port, and a second switch coupled to the second port and configured to select one of the first power configuration and the second power configuration based on the load associated with the second port.
US09948093B2 Device and method for discharging an energy accumulator in a high-voltage grid
The invention relates to a device and method for discharging an energy accumulator (C), in particular an intermediate circuit capacitor, in a high-voltage grid (3), in particular in a direct current intermediate circuit in a motor vehicle, having a direct current converter (5) connected downstream of the high-voltage grid (3), a low-voltage grid (4) connected downstream of the direct current converter (5), an power grid (7) connected downstream of the direct current converter (5) and parallel to the low-voltage grid (4) for supplying energy to a control circuit (9) of the direct current converter (5), and a first controllable switching element (S) which is connected to the connecting line between the direct current converter (5) and the low-voltage grid (4) and by means of which, in the event of a disturbance of the low-voltage grid (4), the direct current converter (5) and the power grid (7) can be disconnected from the low-voltage grid (4). The power grid (7) is connected to the direct current converter (5) via a first electrical component (10; 20) which prevents a backflow of current from the power grid (7) into the direct current converter (5).
US09948090B2 Semiconductor device
Provided is a semiconductor device making it possible to promote area reduction while maintaining ESD resistance. The semiconductor device includes a power wire, a ground wire and a protection circuit provided between the power wire and the ground wire so as to cope with electrostatic discharge. The protection circuit includes a first transistor, a first resistive element, a second transistor, a first capacitive element, a first inverter and a protection transistor. A gate width of the second transistor is narrower than a gate width of the first transistor.
US09948083B2 Automatic splice water drip nose cone
A device for preventing the intrusion of water or other liquids into the interior of an automatic splice. The device may be constructed in a single-piece or two-piece design and includes a series of fingers that contact the cable stranding and wick water away from the cable and out of the connector. These fingers could be integrally molded into the cable cone or molded as a separate piece and inserted. They could also be constructed of any typical brush material such as metal, plastic, rubber, or fiber. The fingers could be arranged in a variety of configurations.
US09948075B2 Cable conduit shape holder device and method
A cable conduit shape holder device, for maintaining the arc of curvature of PVC conduit deployed at corners of building walls during structural construction. The cable conduit shape holder device comprises an arc-shaped, open-sided tubular section having a predetermined length, for externally encapsulating a tubular cable conduit when placed thereon, such that when the section is mounted on a portion of the tubular cable conduit, the section maintains formation of a curved shape in a portion of the tubular cable conduit extending for the predetermined length.
US09948072B2 Mounting system for arranging electric devices, for example, especially in switchgear cabinets
A mounting system (1) includes in switchgear cabinets a horizontal mounting strip (3) with a front face to which an electrical device (2) can be secured. The mounting strip (3) has a locking flange (63) on its rear side lying opposite the device (2) that is to be secured. The locking flange, onto which another component (65) of the mounting system (1) can be directly locked or can be indirectly secured by a lockable adapter element (66), extends in the longitudinal direction of the mounting strip (3).
US09948069B2 Spark plug
A spark plug wherein least one of a center electrode and a ground electrode includes a shaft portion and an electrode tip joined to one surface of the shaft portion. The shaft portion includes a first core formed of a material containing copper and a first outer layer that is formed of a material having higher corrosion resistance than the first core and covers at least part of the first core. The electrode tip includes a second outer layer that is formed of a material containing a noble metal and forms the outer surface of the electrode tip and a second core that is formed of a material having a higher thermal conductivity than the second outer layer and is at least partially covered with the second outer layer.
US09948066B2 Spark plug
A spark plug having a center conductor, an insulator surrounding the center conductor, a body surrounding the insulator, and a center electrode connected in an electrically conductive manner to the center conductor, wherein the center electrode delimits a spark gap with its front face. The spark plug has two bar-shaped ground electrodes that are connected in an electrically conductive manner to the body, that delimit the spark gap, and that are adjacent to one another and spaced apart from one another in the region of the spark gap.
US09948064B2 Method of manufacturing semiconductor device, and semiconductor device
A method of manufacturing a semiconductor device includes a step of forming a mesa portion including an active layer above a substrate, and an n-type layer above the active layer, a step of forming a current confinement portion on left and right of the mesa portion, the current confinement portion including a p-type current blocking layer, an n-type current blocking layer above the p-type current blocking layer, and an i-type or p-type current blocking layer above the n-type current blocking layer, and a p-type doping step of diffusing p-type impurities into the i-type or p-type current blocking layer, an upper portion of the n-type current blocking layer, and left and right portions of the n-type layer to change the upper portion of the n-type current blocking layer and the left and right portions of the n-type layer to p-type semiconductors.
US09948060B2 Semiconductor laser device
This semiconductor laser device includes a semiconductor laser chip and a spatial light modulator SLM optically coupled to the semiconductor laser chip. The semiconductor laser chip LDC includes an active layer 4, a pair of cladding layers 2 and 7 sandwiching the active layer 4, a diffraction grating layer 6 optically coupled to the active layer 4, and a drive electrode E3 that is disposed between the cladding layer 2 and the spatial light modulator SLM and supplies an electric current to the active layer 4, and the drive electrode E3 is positioned within an XY plane and has a plurality of openings as viewed from a Z-axis direction and has a non-periodic structure.
US09948058B2 Method and apparatus for determining optical fibre characteristics
An optical amplifier assembly for determining a parameter of an optical fiber configured to amplify an optical signal being propagated therethrough, the assembly comprising: at least one amplifier pump light source assembly configured to transmit light at a plurality of wavelengths into the optical fiber; a receiver configured to receive light that has propagated through at least part of the optical fiber; and a processor configured to determine the parameter of the optical fiber based on the received light.
US09948057B2 Optical amplifier, optical amplifying system, wavelength converter, and optical communication system
An optical amplifier includes: an optical amplifying fiber; and a pump light source that supplies pump light to the optical amplifying fiber, the pump light being used for parametrically amplifying signal light input to the optical amplifying fiber by using a non-linear optical effect of the optical amplifying fiber. The fluctuation of the zero-dispersion wavelength of the optical amplifying fiber in the longitudinal direction is within the limit of 0.5 nm/100 m.
US09948056B2 High-Q amplified resonator
Ring resonators and methods of making and using the same are disclosed. In certain embodiments, a ring resonator may include a waveguide comprising a pump bus and a signal bus disposed adjacent a ring guide, the pump bus and signal bus configured to couple electromagnetic signals to and from ring guide, wherein at least a portion of the waveguide comprises erbium-doped silica and a cladding material disposed adjacent the waveguide, wherein the cladding material exhibits an index of refraction that is lower than an index of refraction of the waveguide, wherein the ring resonator exhibits a propagation loss of less than 2 dB/m.
US09948049B2 Starter post relocation assembly
An electrical post relocation assembly is configured for use with an electrical component of a vehicle. The electrical component includes a first and second components post configured to be coupled to first and second cables, respectively. The electrical post relocation has first and second relocation posts. The first relocation post is formed from a first electrical conductor and has a first end configured to be coupled to the first component post. A second end of the first relocation post is configured to be coupled to the first terminal fitting of the first cable. Similar to the first relocation post, the second relocation post is also formed from an electrical conductor. A first end of the second relocation post is configured to be coupled to the second component post, and a second end of the second relocation post is configured to be coupled to the second terminal.
US09948044B2 Electrical and mechanical connector
Systems and methods for electrical connections between electrical components or flow paths are described. Systems can include a pin having a proximal end and a distal end, a proximal groove disposed between and spaced vertically from the proximal end and the distal end, and a distal groove disposed between and spaced vertically from the proximal groove and the distal end. A proximal garter spring can be disposed around the pin at least partially within the proximal groove, and a distal garter spring can be disposed around the pin at least partially within the distal groove. The proximal garter spring and distal garter spring can be configured to compress in order to mechanically and electrically couple a first electrical flow path and a second electrical flow path.
US09948043B2 Hybrid neutral plug on bar with distributed pitch
A neutral bus bar 150 is provided for an electrical distribution apparatus, such as an electrical panel 100. The neutral bus bar includes an elongated body 152 that includes a plurality of wire connectors 154 and plug-on neutral landing sections 156 distributed along a length of the body. Each wire connector includes a side hole 172 and a top landing hole 184 on the body. The top landing hole can receive a hold down screw 176 to secure an electrical wire received in the side hole 172 from a wire-type circuit breaker. Each plug-on neutral landing section is able to receive a plug-on neutral clip from a plug-on neutral type circuit breaker. Adjacent plug-on neutral landing sections have at least one wire connector arranged therebetween on the body. The plug-on neutral landing sections are also distributed with a pitch spacing that corresponds to a pole spacing of circuit breakers connectable on the electrical distribution apparatus.
US09948042B2 Connector insert assembly
Connector inserts having retention features with good reliability and holding force. These connector inserts may include ground contacts that provide an insertion portion having a reduced length. These connector inserts may be reliable, have an attractive appearance, and be readily manufactured.
US09948041B2 Electrical receptacle connector for providing grounding and reducing electromagnetic interference
An electrical receptacle connector includes a metallic shell, an insulated housing received in the metallic shell, receptacle terminals, and a grounding plate. The receptacle terminals and the grounding plate are at the insulated housing. The insulated housing includes a base portion and a tongue portion extending from the base portion. The grounding plate includes a plate body, extension arms, and contact regions. The front of the plate body is near to a front lateral surface of the tongue portion, and the rear of the plate body is extending to the base portion. The plate body is between the receptacle terminals. The extension arms are extending from the plate body. The contact regions are formed on the extension arms and in contact with an inner wall of the shell body. Accordingly, the grounding plate is in contact with the metallic shell for providing grounding and reducing the electromagnetic interference.
US09948040B1 Connector
A connector includes an insulated housing, four connecting terminals, three pins and a plug. The insulated housing has a containing space and a disposing surface, and the disposing surface is located in the containing space. The connecting terminals are separately disposed in the containing space of the insulated housing and located on the disposing surface. The pins are separately disposed in the containing space of the insulated housing and extend from the disposing surface toward a direction away from the disposing surface, and the connecting terminals surround the pins. The plug is disposed in a center of the containing space of the insulated housing and located on the disposing surface. The plug is beneficial to rotate and has no directionality. The plug includes a plurality of conductive rings, the conductive rings are separately arranged along the direction away from the disposing surface, and the pins surround the plug.
US09948035B2 Circuit board assembly and method for manufacturing the same
Provided are a circuit board assembly that can prevent contact between connection terminals due to whiskers even if whiskers grow from the connection terminals and a method for manufacturing an insert molded product. A cover body of a circuit board assembly has a plurality of partition walls that form a plurality of grooves each accommodating a corresponding one of connection terminals. The partition walls restrain the inner surface of a second cover of the cover body from entering the grooves when an external pressure is applied to a part of the cover body which covers the connection terminals. The partition walls also prevent contact between adjoining ones of the connection terminals when whiskers grow.
US09948034B2 Connector and electrical wire unit
A connector having favorable crosstalk characteristics and common conversion characteristics and high noise immunity is provided. The connector includes a first connector having at least one pair of first terminals disposed in one housing and a second connector that includes at least one pair of second terminals disposed in another housing, and configured to be connected to the one pair of first terminals. The connector includes at least one first terminal surrounding conductors fixed inside the one housing, individually surrounding the pairs of first terminals, and are insulated from other members, and at least one second terminal surrounding conductors are fixed inside the other housing, individually surrounding the pairs of second terminals, and are insulated from other members. When the first terminals are respectively connected to the second terminals, the first terminal surrounding conductors are respectively connected to the corresponding second terminal surrounding conductors as well.
US09948032B2 Electrical plug connector optimized for installation
An electrical plug connector for a vehicle comprises a plug with a plug casing in which a contact chamber is formed, an electrical contact part arranged in the contact chamber, a locking bolt for releasably attaching a plug-in contact to the contact part, and a socket to be plugged with the plug, a socket casing and a plug-in contact attached thereto. The plug connector has a locking slide attachable to the plug casing that is mounted on the casing for displacement at least into a locking position in a direction transverse to the plugging direction of the plug, to lock the plug to the socket. The locking slide has a guide slot extending substantially transversely to the plugging direction and having an inclined plane to guide the locking bolt of the contact part as it is moved into the locking position.
US09948031B2 Electrical connector
An electrical connector includes a housing including a receiving portion for inserting a flat conductive member; a plurality of terminals arranged in a terminal arrangement direction; a movable member; and a fixing metal member. The movable member includes a supported portion and an engaging portion. The supported portion is supported on the housing to be movable between an open position and a closed position. The engaging portion engages with the flat conductive member when the movable member is situated at the closed position. The fixing metal member includes a fixing portion to be fixed to an electrical circuit board; a regulating portion for restricting the movable member; and an engaging section for engaging with the movable member. The fixing metal member includes leg portions extending toward the electrical circuit board. The fixing portion, the regulating portion, and the engaging portion are disposed on the leg portions.
US09948030B1 Lever-type electrical connector body and related electrical connector assembly
A lever-releasable first electrical connector body includes a housing that includes a set of electrical connectors and a lever rotatably mounted in the housing for rotation between retracted and extended positions. When the first connector body is engaged with a second electrical connector body to form electrical connections with the set of electrical connectors, the lever is normally in the retracted position. Rotation of the lever to the extended position causes an end of the lever to engage and urge the second electrical connector away from the first electrical connector.
US09948029B1 Peripheral device coupling
A self-aligning mechanism is described and may include a first coarse guide component connected to a first device and a second coarse guide component connected to a second device, the first coarse guide component configured to interact with the second coarse guide component to positionally align a connector pair, the coarse guide components configured to prevent a connector from being inserted into a connector receptacle until the connector and the connector receptacle are positionally aligned. The mechanism may also include a first fine guide component connected to the first device and a second fine guide component connected to the second device, the first fine guide component configured to interact with the second fine guide component to rotationally align the connector with the connector receptacle, the fine guide components configured to prevent the connector from being inserted into the connector receptacle until the connector and the connector receptacle are rotationally aligned.
US09948027B2 High power electrical connector with strain relief
A high power electrical connector that includes a housing that has an interface end for mating with a complimentary connector and a cable termination end opposite the interface end for terminating a high power cable. The housing is insulative. An extended anchor member is fixed to an outer surface of the housing. The extended anchor member has a locking end, a strain relief end, and an intermediate extended body therebetween separating the locking end and the strain relief end. A gripping member has a coupling end coupled to the extended anchor member at the strain relief end thereof, and a flexible body configured to provide strain relief to the high power cable.
US09948020B1 Lid-equipped power socket structure
A lid-equipped power socket structure comprises at least one or more electric power sockets and an electric power plug, wherein the electric power plug is electrically connected to the electric power sockets through a set of power line materials, and the electric power socket comprises a socket body, a lid body internally having a gasket, and an external cladding shell, in which the external cladding shell can be sleeve installed onto the outer surface of the socket body; in addition, the external cladding shell may be pivotally connected to the lid body via a torsion spring such that the lid body can be lifted up or placed down onto the surface of the socket body, in which, when the lid body covers on the surface of the socket body, the gasket of the lid body can abut against the 3-holed socket on the surface of the electric power socket thereby achieving the objective of water-proof.
US09948015B2 Three-in-two card connector and mobile terminal including three-in-two card connector
The card connector includes a card connector base and a limiting structure. The card connector base includes a first area and a second area, the limiting structure includes a first limiting part and a second limiting part; the first limiting part is used to limit a first data card in the first area, and the second limiting part is used to limit a second data card or a third data card in the second area; a first spring plate group is disposed in the first area and is configured to electrically connect to edge connectors of the first data card; a second spring plate group and a third spring plate group are disposed in different positions of the second area; the second spring plate group is configured to electrically connect to edge connectors of the second data card; the third spring plate group is configured to electrically connect to edge connectors of the third data card.
US09948010B2 Method for dish reflector illumination via sub-reflector assembly with dielectric radiator portion
A method for illuminating a dish reflector of a reflector antenna, including providing a waveguide coupled to a vertex of a dish reflector at a proximal end, a sub-reflector supported by a dielectric block coupled to a distal end of the waveguide, the dielectric block provided with a dielectric radiator portion proximate the distal end of the waveguide. An RF signal passing through the waveguide and the dielectric block to reflect from the sub-reflector through the dielectric block and at least partially through the dielectric radiator portion to the dish reflector illuminates the dish reflector with a maximum signal intensity and/or signal intensity angular range that is spaced outward from the vertex area of the dish reflector.
US09948008B2 Method for achieving multiple beam radiation vertical orthogonal field coverage by means of multiple feed-in dish antenna
A method for achieving multiple beam radiation vertical orthogonal field coverage by means of multiple feed-in dish antenna, comprising using a total metallic disc and plural feed-in antenna components, wherein it is possible to generate multiple sets of radiation beams by applying multiple sets of feed-in antenna components, and the coverage ranges created by different radiation beams may uniformly distribute there between so as to generate multiple communication service coverage areas. Moreover, since the field formed by the reflection of the total metallic disc is characterized in vertical orthogonality, advantages such as effectively increased coverage, improved energy utilization and radiation beam switches or the like can be provided.
US09948007B2 Subterranean antenna including antenna element and coaxial line therein and related methods
An antenna assembly may be positioned within a wellbore in a subterranean formation. The antenna assembly includes a tubular antenna element to be positioned within the wellbore, and an RF coaxial transmission line to be positioned within the tubular antenna element. The RF coaxial transmission line includes a series of coaxial sections coupled together in end-to-end relation, each coaxial section including an inner conductor, an outer conductor surrounding the inner conductor, and a dielectric therebetween. Each of the outer conductors has opposing threaded ends defining overlapping mechanical threaded joints with adjacent outer conductors.
US09948001B2 Portable terminal
A portable terminal comprises a display and an antenna for wireless communication made of a metal. At least a part of the antenna includes a metallic decoration. The display and the metallic decoration are located in a manner visually recognizable from a specific surface.
US09947991B2 Radio communication device
A radio communication device includes a body structural material such as a metal casing, a planar coil antenna which is disposed inside the body structural material so as to face the body structural material and includes a coil pattern and a coil opening, and a first slit pattern which is provided in the body structural material, intersects the coil pattern at at least two locations on the coil pattern in a plan view, and is not connected to an edge portion of the body structural material. Thus, mechanical strength is ensured, and predetermined communication performance is ensured.
US09947990B2 Coil apparatus of mobile terminal
A coil apparatus of a mobile terminal is disclosed, comprising: a metal coil embedded, in a flat spiral shape, in an inner side of a rear cover of a mobile terminal; an analog switch connected between the metal coil, a wireless charging chip and a signal receiving chip. The embodiment of the present document combines an antenna for receiving a frequency modulated signal with a wireless charging coil, and uses a same group of coils, and embeds the metal coil in the inner side of the rear cover of the mobile terminal, which increases the area of the coil and lengthens the length of the coil, simultaneously improves the efficiency of the wireless charging and the performance for receiving the frequency modulated signal.
US09947983B2 Contactless signal conduit structures
Conduit structures for guiding extremely high frequency (EHF) signals are disclosed herein. The conduit structures can include EHF containment channels that define EHF signal pathways through which EHF signal energy is directed. The conduit structures can minimize or eliminate crosstalk among adjacent paths within a device and across devices.
US09947981B1 Waveguide module comprising a first plate with a waveguide channel and a second plate with a raised portion in which a sealing layer is forced into the waveguide channel by the raised portion
The various technologies presented herein relate to utilizing a sealing layer of malleable material to seal gaps, etc., at a joint between edges of a waveguide channel formed in a first plate and a surface of a clamping plate. A compression pad is included in the surface of the clamping plate and is dimensioned such that the upper surface of the pad is less than the area of the waveguide channel opening on the first plate. The sealing layer is placed between the waveguide plate and the clamping plate, and during assembly of the waveguide module, the compression pad deforms a portion of the sealing layer such that it ingresses into the waveguide channel opening. Deformation of the sealing layer results in the gaps, etc., to be filled, improving the operational integrity of the joint.
US09947978B1 Orthomode transducer
An orthomode transducer (OMT) configured as a compact three port septum polarizer waveguide where one of the three ports is configured to propagate linear orthogonally polarized signals, and an edge of the septum facing that port has a profile including three or more segments with respective facing edges spaced at diverse respective distances from the one of the three ports that is configured to propagate linear orthogonally polarized signals. The three or more segments include one or both of a notch and a protrusion.
US09947976B2 System and method for regulating the temperature of an electrochemical battery
A system and method regulate the temperature of an electrochemical battery. The system can be incorporated in a hybrid or electric motor vehicle including at least two electrical-energy-accumulating elements, each element including at least one electrochemical cell. The system increases the intensity of the value of the current flowing through the battery up to a first threshold value and includes a module for disconnecting and connecting an electrical-energy-accumulating element.
US09947975B2 Battery coolant circuit control
A vehicle includes a traction battery arranged to be cooled by a chiller of a refrigerant system, and a radiator of a coolant system. The coolant system includes a proportioning valve having a pair of first and second outlets that each selectively receives a proportion of coolant flowing into the valve depending upon a position of the valve. The coolant system further includes a chiller loop connected to the first outlet and arranged to convey coolant to the chiller, and a radiator loop connected to the second outlet and arranged to convey coolant to the radiator. A controller is configured to, in response to the refrigerant system being ON, actuate the proportioning valve to proportion the coolant between the first and second outlets such that heat transfer through the chiller is limited to a chiller capacity.
US09947974B2 Heating system and battery system
A heating system includes: an alkaline secondary battery and a controller. The alkaline secondary battery includes: a power generating element configured to be charged or discharged; and a battery case that accommodates the power generating element in a hermetically sealed state. The controller is configured to control charging and discharging of the alkaline secondary battery, and, when an internal pressure of the alkaline secondary battery is higher than or equal to a first threshold, execute a heating process for heating the alkaline secondary battery by decreasing the internal pressure through discharging of the alkaline secondary battery. The heating process is a process of raising a temperature of the alkaline secondary battery.
US09947973B2 Cell mounting module for at least one electrical energy storage cell, cell mounting system and method for manufacturing a cell mounting system
A cell mounting module for at least one electrical energy storage cell, including a module body device having a module region which has at least one cell accommodating recess for accommodating and mounting the at least one electrical energy storage cell, an electrical connection region having at least two electrical pole terminals, and a coolant connection region having at least one coolant inlet for supplying a coolant and at least one coolant outlet for discharging the coolant; at least one electrical connector which is designed to electrically connect the two electrical pole terminals of two identical cell mounting modules; and at last one mechanical connecting means which is designed to connect the at least one coolant inlet and the at least one coolant outlet of two identical cell mounting modules in a fluid-tight manner.
US09947969B2 Thin film lithium ion battery
A method for forming a thin film lithium ion battery includes, under a same vacuum seal, forming a stack of layers on a substrate including an anode layer, an electrolyte, a cathode layer and a first cap over the stack of layers to protect the layers from air. Under a same vacuum seal, the stack of layers is etched with a non-reactive etch process in accordance with a hardmask, and a second cap layer is formed over the stack of layers without breaking the vacuum seal. Contacts coupled to the cathode and the anode are formed.
US09947959B2 Non-aqueous electrolyte battery having porous polymer layer between laminate film and battery device
A non-aqueous electrolyte battery includes a battery device in which a positive electrode is faced to negative electrode through a separator; a non-aqueous electrolyte; a laminate film which is formed by laminating a metal layer, an outside resin layer formed in outer face of the metal layer, and an inside resin layer formed in the metal layer, and in which the battery device and the non-aqueous electrolyte is packaged by heat welding and housed; a positive electrode lead which is electrically connected to the positive electrode, and drawn from portion heat-welded of the laminate film to an exterior thereof; a negative electrode lead which is electrically connected to the negative electrode, and drawn from portion heat-welded of the laminate film to an exterior thereof; and a porous polymer layer containing, as a component, vinylidene fluoride formed between the laminate film and the battery device.
US09947954B2 Fuel cell stack
A fuel cell stack includes seven current collecting members and six fuel cells that are alternate stacked with reference to the stacking direction. Each of the six fuel cells includes an anode, a cathode and a solid electrolyte layer that is disposed between the anode and the cathode and contains a zirconia-based material as a main component. The six fuel cells include a first fuel cell disposed in the center with reference to the stacking direction, and a second fuel cell disposed in one end with reference to the stacking direction. An intensity ratio of tetragonal crystal zirconia to cubic crystal zirconia in a Raman spectrum of the solid electrolyte layer of the first fuel cell is greater than an intensity ratio of tetragonal crystal zirconia to cubic crystal zirconia in a Raman spectrum of the solid electrolyte layer of the second fuel cell.
US09947953B2 High efficiency, reversible flow battery system for energy storage
The present invention relates to a reversible solid oxide electrochemical cell that may operate in two modes: a discharge mode (power generation) and a charge mode (electrolytic fuel production). A thermal system that utilizes a SOFB and is inclusive of selection of operating conditions that may enable roundtrip efficiencies exceeding about 80% to be realized is disclosed. Based on leverage of existing solid oxide fuel cell technology, the system concept is applicable to energy storage applications on the kW to MW scale.
US09947951B2 Fuel cell module
An object is to provide a highly efficient and small-sized fuel cell module. To achieve this object, a cell stack 10, a reformer 20, and an evaporator 30 are accommodated together in a casing 50. The reformer 20 and the evaporator 30 are formed as vertical structures independently juxtaposed to each other and are disposed adjacent to the cell stack. The reformer 20 and the evaporator 30 are heated with exhaust gas resulting from combustion of off-gas released from the cell stack 10. Exhaust gas flow paths respectively are disposed to the reformer 20 and the evaporator 30 so as to let the combustion exhaust gas pass through in a vertical direction for heating the reformer and the evaporator. The exhaust gas flow paths of the reformer 20 and the evaporator 30 are connected in series through a connection pipe 60 above the reformer 20 and the evaporator 30.
US09947950B2 Systems and methods for initiating voltage recovery in a fuel cell system
Systems and methods for initiating voltage recovery procedures in a fuel cell system based in part on an estimated specific activity over the life of a fuel cell catalyst are presented. In certain embodiments, SA loss of catalyst and electrochemical surface area loss of a FC system may be estimated. An output voltage of the FC system may be estimated based on the estimated SA loss and the electrochemical surface area loss. An amount of recoverable voltage loss may be determined based on a comparison between the estimated output voltage and a measured output voltage. Based on the determined amount of recordable voltage loss, a FC system control action (e.g., a voltage recovery procedure) may be initiated.
US09947943B2 Flow field plate for a fuel cell
A flow field plate for a bipolar plate or bipolar plate assembly of a fuel cell or a fuel cell stack has an electrode facing front side, a backside and at least a cooling fluid manifold for supplying cooling fluid to the flow field plate. The backside includes a cooling fluid flow field for substantially uniformly distributing the cooling fluid over the flow field plate. The flow field plate further includes a cooling fluid sub-manifold which is adapted to provide cooling fluid from the cooling fluid manifold to a cooling fluid flow field. The cooling fluid sub-manifold is fluidly disconnected from the cooling fluid flow field, a bipolar plate or bipolar plate assembly including a flow field plate, as well as a fuel cell or fuel cell stack including such a flow field plate and/or bipolar plate or such a bipolar plate assembly.
US09947939B2 Use of an anode catalyst layer
A method of operating a fuel cell having an anode, a cathode and a polymer electrolyte membrane disposed between the anode and the cathode, includes feeding the anode with an impure hydrogen stream having low levels of carbon monoxide up to 5 ppm, and wherein the anode includes an anode catalyst layer including a carbon monoxide tolerant catalyst material, wherein the catalyst material includes: (i) a binary alloy of PtX, wherein X is a metal selected from the group consisting of rhodium and osmium, and wherein the atomic percentage of platinum in the alloy is from 45 to 80 atomic % and the atomic percentage of X in the alloy is from 20 to 55 atomic %; and (ii) a support material on which the PtX alloy is dispersed; wherein the total loading of platinum group metals (PGM) in the anode catalyst layer is from 0.01 to 0.2 mgPGM/cm2.
US09947936B2 Oxygen reduction catalyst and method for producing same
The present invention concerns an oxygen reduction catalyst comprising composite particles in which primary particles of a titanium compound is dispersed into a carbon structure, wherein the composite particles have titanium, carbon, nitrogen and oxygen as constituent elements, and with regard to a ratio of number of atoms of each of the elements when titanium is taken as 1, a ratio of carbon is larger than 2 and 5 or less, a ratio of nitrogen is larger than 0 and 1 or less, and a ratio of oxygen is 1 or more and 3 or less, and an intensity ratio (D/G ratio) of D band peak intensity to G band peak intensity in a Raman spectrum is in the range of 0.4 to 1.0. The oxygen reduction catalyst according to the present invention has satisfactory initial performance and excellent start-stop durability.
US09947934B2 Catalyst and electrode catalyst layer, membrane electrode assembly, and fuel cell using the catalyst
The present invention has an object to provide a catalyst having excellent oxygen reduction reaction activity. The present invention relates to a catalyst comprising a catalyst support and a catalyst metal supported on the catalyst support, wherein a specific surface area of the catalyst per support weight is 715 m2/g support or more or a covering ratio of the catalyst metal with an electrolyte is less than 0.5, and an amount of an acidic group of the catalyst per support weight is 0.75 mmol/g support or less.
US09947933B2 Cathode, lithium air battery including same, and preparation method thereof
An air battery cathode including an organic-inorganic composite material including lyophobic nanopores, the organic-inorganic composite material including a porous metal oxide, and a lyophobic layer on a surface of a pore of the porous metal oxide and having a contact angle of greater than about 90°; and a binder. Also a lithium air battery including the cathode, and a method of manufacture the cathode.
US09947932B2 Lithium-air battery cathodes and methods of making the same
A lithium-air battery cathode having increased mesopore and macropore volume and methods of making the cathode are provided. In at least one embodiment, a plurality of mesopores is present in the cathode having a porosity of 1 to 70 percent. In another embodiment, a plurality of macropores are present in the cathode having a porosity of 5 to 99 percent. In one embodiment, the mesopores and macropores are imprinted using a sacrificial material. In another embodiment, the mesopores and macropores are imprinted by applying a template. In another embodiment, the mesopores and macropores are formed by coating cathode material onto a porous substrate.
US09947928B2 Nonaqueous electrolyte secondary battery
The initial charge/discharge efficiency and cycle characteristics of a nonaqueous electrolyte secondary battery are improved. Provided is a nonaqueous electrolyte secondary battery including a positive electrode, a negative electrode, a porous layer placed on the negative electrode, a separator, and a nonaqueous electrolyte. The porous layer has flat voids. The minor axis direction of each flat void is perpendicular to the plane direction of the porous layer and the major axis direction of the flat void is parallel to the plane direction of the porous layer. The ratio of the major axis to the minor axis of the flat void preferably ranges from 1.4 to 2.2.
US09947927B2 Production method for negative electrode for all-solid-state battery, and negative electrode for all-solid-state battery
An object of the present invention is to provide a production method for suppressing the deformation of a negative electrode in the production of a negative electrode for an all-solid-state battery using turbostratic carbon and a solid electrolyte.The problem described above can be solved by a production method for a negative electrode for an all-solid-state battery comprising the steps of: (1) coating a carbonaceous material having a true density of from 1.30 g/cm3 to 2.10 g/cm3 determined by a butanol method with a solid electrolyte; and (2) pressure-molding the solid electrolyte-coated carbonaceous material.
US09947925B2 Negative electrode for lithium-ion secondary battery
Provided are an anode active material for lithium ion rechargeable batteries and an anode, which are capable, when used in a lithium ion rechargeable battery, of providing excellent charge/discharge capacity and cycle characteristics, and also high rate performance, as well as a lithium ion rechargeable battery using the same. The anode active material contains particles having a crystal phase represented by RAx, wherein R is at least one element selected from the group consisting of rare earth elements including Sc and Y but excluding La, A is Si and/or Ge, and x satisfies 1.0≤x≤2.0, and a crystal phase consisting of A. The material is thus useful as an anode material for lithium ion rechargeable batteries.
US09947922B2 Porous silicon-based particles, method of preparing the same, and lithium secondary battery including the porous silicon-based particles
Provided are a porous silicon-based particle including a silicon (Si) or SiOx(0
US09947913B2 Method for welding metal tab of electrode layer for cable battery and electrode manufactured thereby
Disclosed are a method of welding a metal tab of an electrode layer for a cable battery and an electrode manufactured thereby. This welding method, suitable for welding a metal tab to an electrode including a current collector for a cable battery, a conductive layer formed on the outer surface of the current collector, and a polymer film layer formed on the inner surface of the current collector, includes: a) removing a portion of the conductive layer using a pulse laser, thus exposing the surface of the current collector positioned thereunder, and b) welding a metal tab to the surface of the current collector, thus enabling the welding of a metal tab and an electrode for a cable battery, which has been difficult to achieve using a conventional welding process.
US09947910B2 Energy storage apparatus and spacer
Provided is an energy storage apparatus where a spacer includes: a base disposed orthogonal to a first direction; a first restricting portion and a second restricting portion extending from an end portion of the base in a second direction orthogonal to the first direction; a first projecting portion projecting from the base and the first restricting portion; and a second projecting portion projecting from the base and the second restricting portion. The first projecting portion includes: a first portion extending in the second direction on one surface of the base; and a second portion extending to a distal end in the first restricting portion, and is continuously formed at least from an end portion of the first portion on a first-restricting-portion side to a distal end of the second portion. The second projecting portion includes: a third portion which extends in the second direction on the other surface of the base and disposed at the position different from the first portion in a third direction; and a fourth portion extending to a distal end on the second restricting portion, and is continuously formed at least from an end portion of the third portion on a second-restricting-portion side to a distal end of the fourth portion. The distal end of the second portion and the distal end of the fourth portion are disposed at the same position in the third direction.
US09947905B2 Fabric battery
A battery includes a plurality of battery cells between first and second electrically conductive fabrics. The first electrically conductive fabric includes a first battery terminal. The second electrically conductive fabric includes a second battery terminal. The first electrically conductive fabric and the second electrically conductive fabric are framed to provide an enclosed region. The plurality of battery cells are arranged in parallel between the first electrically conductive fabric and the second electrically conductive fabric within the enclosed region. Each of the plurality of battery cells is configured to establish an electrical connection, at least temporarily, with the first battery terminal through the first electrically conductive fabric and the second battery terminal through the second electrically conductive fabric.
US09947904B2 Vapor deposition method for producing an organic EL panel
The present invention (i) uses a mask unit (80) including: a shadow mask (81) that has an opening (82) and that is smaller in area than a vapor deposition region (210) of a film formation substrate (200) and; a vapor deposition source (85) that has a emission hole (86) for emitting a vapor deposition particle, the emission hole (86) being provided so as to face the shadow mask (81), the shadow mask (81) and the vapor deposition source (85) being fixed in position relative to each other, (ii) adjusts an amount of a void between the shadow mask (81) and the film formation substrate (200), (iii) moves at least a first one of the mask unit (80) and the film formation substrate (200) relative to a second one thereof while uniformly maintaining the amount of the void between the mask unit (80) and the film formation substrate (200), and (iv) sequentially deposit the vapor deposition particle onto the vapor deposition region (210) through the opening (82) of the shadow mask (81). This makes it possible to form a high-resolution vapor deposition pattern on a large-sized substrate.
US09947891B2 OLED packaging method and OLED packaging structure
The present invention provides an OLED packaging method and an OLED packaging structure. The OLED packaging method includes the following steps: providing a TFT substrate (1) and a package lid (2); forming air channels (21) on the package lid (2); forming an OLED device (11) on the TFT substrate (1); coating a loop of desiccant (12) on the TFT substrate (1) along an outer circumference of the OLED device (11) and coating a loop of a dam (13) along an outer circumference of the desiccant (12); laminating the TFT substrate (1) and the package lid (2) together; and pressing the TFT substrate (1) and the package lid (2) together and applying irradiation of ultraviolet light to cure the dam (13). The method effectively eliminates the issue of resin flushing caused by a difference of air pressures inside and outside the packaging structure in bonding the package lid and the TFT substrate so as to improve the property of water resistance, enhance mechanical strength of the packaging structure, and improve packaging effectiveness.
US09947890B2 Electro-optical device and electronic apparatus
An electro-optical device includes an element substrate that includes a display region in which a plurality of light emitting elements are arranged in matrix form and a terminal region in which mounting terminals are arranged on an outer side of the display region, a protective substrate that faces a plurality of light emitting element side of the element substrate, and a joining substrate that is joined to the terminal region of the element substrate, and includes a connection terminal. A sealing film, which seals the plurality of light emitting elements, is also formed in the terminal region on the element substrate. The mounting terminal is connected to the connection terminal. Portions in which the sealing film is removed, and which join to the joining substrate in the electro-optical device are present.
US09947889B2 Transparent electrode, electronic device, and organic electroluminescent element
A transparent electrode comprising a nitrogen-containing layer, and an electrode layer provided adjacent to the nitrogen-containing layer and having silver as a main component. The nitrogen-containing layer is configured using a compound containing nitrogen atoms, wherein the effective unshared electron pair content [n/M] is 2.0×10−3≤[n/M], n being the number of unshared electron pairs that are not involved in aromaticity and that are not coordinated with the metal from among the unshared electron pairs of the nitrogen atoms, and M being the molecular weight.
US09947879B2 Anthracene derivative and organic electroluminescence element using same
An anthracene derivative represented by the following formula (1): wherein in the formula (1), L1 is selected from a single bond and a linking group, and the linking group is selected from a divalent arylene group, a divalent heterocyclic group, and a group formed by linking of 2 to 4 of divalent arylene groups and/or divalent heterocyclic groups. Ar1 is selected from the following formulas (2) and (3). In the formulas (2) and (3), X is selected from an oxygen atom and a sulfur atom. In the formula (2), any one of R11 to R14 is used for bonding to L1. In the formula (3), any one of R21 to R24 is used for bonding to L1. Ar2 is selected from a substituted or unsubstituted aryl group including 6 to 50 ring carbon atoms and a substituted or unsubstituted heterocyclic group including 5 to 50 ring atoms.
US09947878B2 Organic light-emitting device
The present specification relates to an organic light emitting diode.
US09947875B2 Amine derivatives, material for organic electroluminescent device and organic electroluminescent device including the same
A material for an organic electroluminescent device having high emission efficiency and an organic electroluminescent device including the same. An amine derivative of an embodiment of the inventive concept is represented by Formula (1).
US09947871B2 Surface modifier for metal electrode, surface-modified metal electrode, and method for producing surface-modified metal electrode
A surface modifier for a metal electrode containing a reactive silyl compound represented by General Formula (1) Rf—X-A-SiR13-n(OR2)n  (1) wherein, Rf is an aryl group having 6 to 10 carbon atoms that may have an alkyl substituent having 1 to 5 carbon atoms or an alkyl group having 1 to 10 carbon atoms, wherein at least one hydrogen atom is replaced with a fluorine atom, X represents a divalent group selected from —O—, —NH—, —C(═O)O—, —C(═O)NH—, —OC(═O)NH—, and —NHC(═O)NH—, or a single bond, A represents a straight chain, branched chain or cyclic aliphatic divalent hydrocarbon group having 1 to 10 carbon atoms, an aromatic divalent hydrocarbon group having 6 to 10 carbon atoms, or a single bond, R1 is a monovalent hydrocarbon group having 1 to 3 carbon atoms, R2 represents a monovalent hydrocarbon group having 1 to 3 carbon atoms, an acetyl group, a propanoyl group, or a hydrogen atom, and n is an integer of 1 to 3, a metal electrode surface-modified with the surface modifier, and a method for producing a surface-modified metal electrode are provided.
US09947869B2 Method for making nano-heterostructure
The present disclosure relates to a method for making nanoscale heterostructure. The method includes: providing a support and forming a first carbon nanotube layer on the support, and the first carbon nanotube layer comprises a plurality of first source carbon nanotubes; forming a semiconductor layer on the first carbon nanotube layer; covering a second carbon nanotube layer on the semiconductor layer, and the second carbon nanotube layer comprises a plurality of second source carbon nanotubes; finding and labeling a first carbon nanotube in the first carbon nanotube layer and a second carbon nanotube in the second carbon nanotube layer; removing the plurality of first source carbon nanotubes and the plurality of second source carbon nanotubes; and annealing the multilayer structure.
US09947867B2 Amorphous carbon resistive memory element with lateral heat dissipating structure
A method of fabricating a resistive memory element having a layer structure includes: providing a substrate; depositing a first electrode on an upper surface of the substrate; forming a layer of confining material on an upper surface of the first electrode so as to define a cavity having a maximal lateral dimension that is less than 60 nm along a direction parallel to an average plane of the first electrode, the confining material having a thermal conductivity greater than 0.5 W/(m·K); depositing a resistively switchable material as an amorphous compound comprising carbon to fill the cavity; and depositing a second electrode on an upper surface of the resistively switchable material.
US09947862B2 Magnetoresistive memory device
According to one embodiment, a magnetoresistive memory device includes a first magnetic layer in which a magnetization direction is variable, a first nonmagnetic layer provided on the first magnetic layer, a second magnetic layer provided on the first nonmagnetic layer, a magnetization direction of the second magnetic layer being invariable, and a second nonmagnetic layer provided on the first magnetic layer, which is opposite the first nonmagnetic layer. The first magnetic layer includes Mo.
US09947859B2 Electronic device and method for fabricating the same
An electronic device that includes a first structure including a first magnetic layer, a second magnetic layer, and a tunnel barrier layer which is interposed between the first magnetic layer and the second magnetic layer; and a second structure disposed over the first structure, and including a magnetic correction layer for correcting a magnetic field of the first structure, wherein a width of a bottom surface of the second structure is larger than a width of a top surface of the first structure.
US09947858B2 Curable organopolysiloxane composition for transducers and applications of such curable silicone composition for transducers
The present invention provides a curable organopolysiloxane composition capable of producing a cured article that can be used as a transducer and provided with excellent mechanical characteristics and/or electrical characteristics. The present invention also relates to a novel curable organopolysiloxane composition for transducer use comprising a curable organopolysiloxane composition, dielectric inorganic fine particles having a specific dielectric constant of greater than or equal to 10, and fine particles having a specific dielectric constant of less than 10.
US09947855B2 Thermoelectric conversion element and method of manufacturing the same, and heat radiation fin
A thermoelectric conversion element includes: a magnetic body having a magnetization; and an electromotive body formed of material exhibiting a spin orbit coupling and jointed to the magnetic body. The magnetic body has an upper joint surface jointed to the electromotive body. The upper joint surface has concavities and convexities.
US09947851B2 LED package
The present invention provides a LED package in which deterioration in heat radiation performance is suppressed. The LED package comprises a substrate, a light-emitting device mounted on the substrate, sealing resin sealing the light-emitting device and mixed with phosphor, a heat sink provided on a rear surface of the substrate, and a rear electrode provided on the rear surface of the substrate and electrically connected to the light-emitting device. The heat sink is provided at a distance from the rear electrode in a region except for the rear electrode. The heat sink is divided into eighteen small heat sinks by grooves formed in a rectangular lattice pattern. When the LED package is mounted on a mounting substrate, the gas generated from solder is efficiently discharged through the grooves to the outside, thereby suppressing the generation of air bubbles between the heat sink and the solder.
US09947850B2 Substrate for light emitting devices and light emitting device
In order to provide a substrate for light emitting devices having high heat radiating properties, dielectric strength voltage properties, light reflectivity, and excellent mass productivity, a substrate (5) includes an intermediate layer (11) containing ceramic which is formed on the surface of the aluminum base (10) by using an aerosol deposition method.
US09947849B2 Light emitting device
Disclosed herein is a light emitting device manufactured by separating a growth substrate in a wafer level. The light emitting device includes: a base; a light emitting structure disposed on the base; and a plurality of second contact electrodes disposed between the base and the light emitting structure, wherein the base includes at least two bulk electrodes electrically connected to the light emitting structure and an insulation support disposed between the bulk electrodes and enclosing the bulk electrodes, the insulation support and the bulk electrodes each including concave parts and convex parts engaged with each other on surfaces facing each other, and the convex parts including a section in which a width thereof is changed in a protrusion direction.
US09947848B2 Semiconductor light emitting device and method for producing the same
A semiconductor light emitting device includes a lead frame 1 covered by a resin package 2. The lead frame 1 includes first and second leads 1A and 1B facing each other. The first and second leads 1A and 1B include inner lead sections 11 and 12 covered with the package 2, respectively. The first and second leads 1A and 1B include outer lead sections 13 protruding from package 2 ends. First and second exposed surfaces 51 and 52 are exposed from the package 2 in the first and second lead lower surfaces, respectively. The first lead 1A is longer than the second lead 1B. An LED 3 is mounted on the first lead upper surface. The second lead 1B includes second end portions 15 extending in the second exposed surface 52 from the both ends of the facing surface toward the first lead 1A.
US09947844B1 Package for ultraviolet emitting devices
Embodiments of the invention include a light emitting diode including a semiconductor structure including an active layer disposed between an n-type region and a p-type region. The active layer emits UV radiation. A first metal layer is in direct contact with the p-type region. A second metal layer is in direct contact with the n-type region. The first and second metal layers are both formed on a first side of the semiconductor structure. A transparent optic is optically coupled to a major surface of the light emitting diode.
US09947843B2 Method of producing a cover element and an optoelectronic component, cover element and optoelectronic component
A method of producing a cover element for an optoelectronic component includes producing a frame having a multiplicity of openings, wherein the frame is made of a material having embedded particles of TiO2, ZrO2, Al2O3, AlN, SiO2, or another optically reflective material and/or an embedded colored pigment; introducing a material into a multiplicity of the openings; and dividing the frame.
US09947841B2 Light emitting device having light guider
A light emitting device includes a light emitting element, a wavelength converter, a light transmissive member, a light guider, and a light transmitting layer. The light emitting element has an element upper surface, an element lower surface, and an element side surface. The wavelength converter has a converter lower surface. The wavelength is provided to be connected to the light emitting element such that the converter lower surface faces the element upper surface. The converter lower surface has an exposed region that does not face the element upper surface. The light guider guides light from the light emitting element to the wavelength converter. The light guider covers the element side surface and the exposed region. The wavelength converter has a converter upper surface. The light transmitting layer has a layer lower surface facing the converter upper surface. The converter upper surface is smaller than the layer lower surface.
US09947838B2 Method of producing a multicolor LED display
A method produces a multicolor LED display, the display including an LED luminous unit having a multiplicity of pixels. First subpixels, second subpixel and third subpixels contain an LED chip that emits radiation of a first color, wherein a first conversion layer that converts the radiation into a second color is arranged at least above the second subpixels and a second conversion layer that converts the radiation into a third color is arranged above the third subpixels. At least one process step is carried out in which the first or second conversion layer is applied or removed in at least one defined region above the pixels, wherein a portion of the LED chips is electrically operated, and wherein the region is defined by the radiation generated by the operated LED chips, generated heat or a generated electric field.
US09947835B2 Light-emitting element and light-emitting package comprising same
A light emitting device includes a substrate; a plurality of light emitting cells disposed on the substrate to be spaced apart from one another, the light emitting cell having a via hole passing through the second conductive type semiconductor layer, the active layer and a part of the first conductive type semiconductor layer; a first electrode layer electrically connected to the first conductive type semiconductor layer at a bottom of the via hole; a second electrode layer disposed on the second conductive type semiconductor layer; and a first passivation layer, electrically separating the first electrode layer from the second electrode layer, wherein the first electrode layer of one light emitting cell is electrically connected to the second electrode layer of another light emitting cell adjacent to the one light emitting cell.
US09947833B2 Semiconductor light-emitting element and semiconductor light-emitting device
A semiconductor light-emitting element comprises: a semiconductor structure layer including a first semiconductor layer having a first conductivity type, a light-emitting layer and a second semiconductor layer having a second conductivity type opposite to the first conductivity type being laminated in sequence; a first electrode including a first electrode layer formed on the first semiconductor layer and a first contact electrode connected to the first electrode layer at a position displaced from a center of the first electrode layer in an intra-layer direction of the first electrode layer; and a second electrode extending through the first electrode layer, the first semiconductor layer and the light-emitting layer and being connected to the second semiconductor layer.
US09947831B2 Light emitting diode device having III-nitride nanowires, a shell layer and a continuous layer
A light emitting diode (LED) includes a plurality of Group III-nitride nanowires extending from a substrate, at least one Group III-nitride pyramidal shell layer located on each of the plurality of Group III-nitride nanowires, a continuous Group III-nitride pyramidal layer located over the at least one Group III-nitride pyramidal shell layer, and a continuous pyramidal contact layer located over the continuous Group III-nitride pyramidal layer. The at least one Group III-nitride pyramidal shell layer is located in an active region of the LED. The plurality of Group III-nitride nanowires are doped one of n- or p-type. The continuous Group III-nitride pyramidal layer is doped another one of p- or n-type to form a junction with the plurality of Group III-nitride nanowires. A distance from a side portion of the continuous contact layer to the plurality of Group III-nitride nanowires is shorter than a distance of an apex of the continuous contact layer to the plurality of Group III-nitride nanowires.
US09947827B2 Front-side emitting mid-infrared light emitting diode
A device emitting mid-infrared light that comprises a semiconductor substrate of GaSb or closely related material. The device can also comprise epitaxial heterostructures of InAs, GaAs, AISb, and related alloys forming light emitting structures cascaded by tunnel junctions. Further, the device can comprise light emission from the front, epitaxial side of the substrate.
US09947825B2 Method of manufacturing solar cell
Disclosed is a manufacturing method of a solar cell, including forming a photoelectric converter including an amorphous semiconductor layer, forming an electrode connected to the photoelectric converter, and performing a post-treatment by providing light to the photoelectric converter and the electrode.
US09947823B2 Group-IV solar cell structure using group-IV or III-V heterostructures
Device structures, apparatuses, and methods are disclosed for photovoltaic cells that may be a single junction or multijunction solar cells, with at least a first layer comprising a group-IV semiconductor in which part of the cell comprises a second layer comprising a III-V semiconductor or group-IV semiconductor having a different composition than the group-IV semiconductor of the first layer, such that a heterostructure is formed between the first and second layers.
US09947822B2 Bifacial photovoltaic module using heterojunction solar cells
One embodiment of the present invention provides a bifacial solar panel. The bifacial solar panel includes a first transparent cover on a first side of the solar panel, a second transparent cover on a second side of the solar panel, a plurality of solar cells sandwiched between the first cover and the second cover, and one or more lead wires for outputting power generated by the solar panel. The lead wires are positioned on an edge of the solar panel without shading the first and second sides of the solar panel. A respective solar cell comprises a photovoltaic structure, a first metal grid on the first side of the photovoltaic structure, which allows the solar cell to absorb light from the first side, and a second metal grid on the second side of the photovoltaic structure, which allows the solar cell to absorb light from the second side.
US09947821B2 High concentration doping in silicon
A silicon device, has a plurality of crystalline silicon regions. One crystalline silicon region is a doped crystalline silicon region. Deactivating some or all of the dopant atoms in the doped crystalline silicon region is achieved by introducing hydrogen atoms into the doped 5 crystalline silicon region, whereby the hydrogen coulombicly bonds with some or all of the dopant atoms to deactivate the respective dopant atoms. Deactivated dopant atoms may be reactivated by heating and illuminating the doped crystalline silicon region to break at least some of the dopant-hydrogen bonds while maintaining conditions to create a high concentration of neutral hydrogen atoms whereby 10 some of the hydrogen atoms diffuse from the doped crystalline silicon region without rebinding to the dopant atoms.
US09947818B2 Solar cell module
A solar cell module includes a solar cell panel including a plurality of solar cells sealed between a front surface member and a back surface member with a sealing material, and a frame supporting a peripheral edge portion of the solar cell panel. The frame includes a main body portion, a fitting portion which is located above the main body portion and in which the peripheral edge portion of the solar cell panel is to be fitted. The frame further includes an inner flange portion provided at a part of the main body portion below the fitting portion and not below a bottom portion of the main body portion and extending in a direction inward from the peripheral edge portion of the solar cell panel.
US09947817B2 Three-dimensional photovoltaic devices including non-conductive cores and methods of manufacture
Various stamping methods may reduce defects and increase throughput for manufacturing metamaterial devices. Metamaterial devices with an array of photovoltaic bristles, and/or vias, may enable each photovoltaic bristle to have a high probability of photon absorption. The high probability of photon absorption may lead to increased efficiency and more power generation from an array of photovoltaic bristles. Reduced defects in the metamaterial device may decrease manufacturing cost, increase reliability of the metamaterial device, and increase the probability of photon absorption for a metamaterial device. The increase in manufacturing throughput and reduced defects may reduce manufacturing costs to enable the embodiment metamaterial devices to reach grid parity.
US09947805B2 Nanowire-based mechanical switching device
Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.
US09947797B2 Semiconductor device and method for manufacturing the same
Homogeneity and stability of electric characteristics of a thin film transistor included in a circuit are critical for the performance of a display device including said circuit. An object of the invention is to provide an oxide semiconductor film with low hydrogen content and which is used in an inverted staggered thin film transistor having well defined electric characteristics. In order to achieve the object, a gate insulating film, an oxide semiconductor layer, and a channel protective film are successively formed with a sputtering method without being exposed to air. The oxide semiconductor layer is formed so as to limit hydrogen contamination, in an atmosphere including a proportion of oxygen. In addition, layers provided over and under a channel formation region of the oxide semiconductor layer are formed using compounds of silicon, oxygen and/or nitrogen.
US09947793B1 Vertical pillar-type field effect transistor and method
Disclosed is a method of forming a vertical pillar-type field effect transistor (FET). One or more semiconductor pillars are formed by epitaxial deposition in one or more openings, respectively, that extend through a first dielectric layer and that have high aspect ratios in two directions. The first dielectric layer is etched back and the following components are formed laterally surrounding the semiconductor pillar(s): a first source/drain region above and adjacent to the first dielectric layer, a second dielectric layer on the first source/drain region, a gate on the second dielectric layer and a gate cap on the gate. The gate cap extends over the top surface(s) of the semiconductor pillar(s). A recess is formed in the gate cap to expose at least the top surface(s) of the semiconductor pillar(s) and a second source/drain region is formed within the recess. Also disclosed is the vertical pillar-type FET structure.
US09947792B2 Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first fin-shaped structure thereon; forming a spacer adjacent to the first fin-shaped structure; using the spacer as mask to remove part of the substrate for forming a second fin-shaped structure, in which the second fin-shaped structure comprises a top portion and a bottom portion; and forming a doped portion in the bottom portion of the second fin-shaped structure.
US09947785B2 Junction field effect transistor and manufacturing method therefor
The present invention relates to a junction field effect transistor. The junction field effect transistor comprises a substrate (10), a buried layer in the substrate, a first well region (32) and a second well region (34) that are on the buried layer, a source lead-out region (50), a drain lead-out region (60), and a first gate lead-out region (42) that are in the first well region (32), and a second gate lead-out region (44) in the second well region (34). A Schottky junction interface (70) is disposed on the surface of the first well region (32). The Schottky junction interface (70) is located between the first gate lead-out region (42) and the drain lead-out region (60), and is isolated from the first gate lead-out region (42) and the drain lead-out region (60) by means of isolation structures. The present invention also relates to a manufacturing method for a junction field effect transistor.
US09947784B2 High voltage lateral extended drain MOS transistor with improved drift layer contact
An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain end diffused link between the buried drift region and the drain contact, and a concurrently formed channel end diffused link between the buried drift region and the channel, where the channel end diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain end diffused link.
US09947778B2 Lateral bipolar junction transistor with controlled junction
A method of forming a lateral bipolar junction transistor (LBJT) that includes providing a germanium containing layer on a crystalline oxide layer, and patterning the germanium containing layer stopping on the crystalline oxide layer to form a base region. The method may further include forming emitter and collector extension regions on opposing sides of the base region using ion implantation, and epitaxially forming an emitter region and collector region on the crystalline oxide layer into contact with the emitter and collector extension regions. The crystalline oxide layer provides a seed layer for the epitaxial formation of the emitter and collector regions.
US09947777B2 Semiconductor device and method for manufacturing semiconductor device
Provided is a semiconductor device having favorable reliability. A manufacturing method of a semiconductor device comprising the steps of: forming a first oxide semiconductor having an island shape; forming a first conductor and a second conductor over the first oxide semiconductor; forming an oxide semiconductor film over the first oxide semiconductor, the first conductor, and the second conductor; forming a first insulating film over the oxide semiconductor film; forming a conductive film over the first insulating film; removing part of the first insulating film and part of the conductive film to form a first insulator and a third conductor; forming a second insulating film covering the first insulator and the third conductor; removing part of the oxide semiconductor film and part of the second insulating film to form a second oxide semiconductor and a second insulator and to expose a side surface of the first oxide semiconductor; forming a third insulator in contact with the side surface of the first oxide semiconductor and with a side surface of the second oxide semiconductor; forming a fourth insulator in contact with the third insulator; and performing a microwave-excited plasma treatment to the third insulator and the fourth insulator.
US09947776B2 Method for manufacturing semiconductor device including memory cell of nonvolatile memory, capacitance element, and transistors
To reduce a manufacturing cost of a semiconductor device in which a high breakdown voltage transistor and a trench capacitive element in which a part of an upper electrode is embedded in a trench formed in a main surface of a semiconductor substrate are mixed together.After an insulating film is formed over a main surface of a semiconductor substrate so as to cover a trench formed in the main surface of the semiconductor substrate, the insulating film is processed to form an upper electrode of a capacitive element, a gate insulating film which insulates the semiconductor substrate to be a lower electrode, and a gate insulting film of a high breakdown voltage transistor.
US09947770B2 Self-aligned trench MOSFET and method of manufacture
A trench metal-oxide-semiconductor field effect transistor (MOSFET), in accordance with one embodiment, includes a drain region, a plurality of gate regions disposed above the drain region, a plurality of gate insulator regions each disposed about a periphery of a respective one of the plurality of gate regions, a plurality of source regions disposed in recessed mesas between the plurality of gate insulator regions, a plurality of body regions disposed in recessed mesas between the plurality of gate insulator regions and between the plurality of source regions and the drain region. The MOSFET also includes a plurality of body contact regions disposed in the each body region adjacent the plurality of source regions, a plurality of source/body contact spacers disposed between the plurality of gate insulator regions above the recessed mesas, a source/body contact disposed above the source/body contact spacers, and a plurality of source/body contact plugs disposed between the source/body contact spacers and coupling the source/body contact to the plurality of body contact regions and the plurality of source regions.
US09947767B1 Self-limited inner spacer formation for gate-all-around field effect transistors
A semiconductor devices and methods of forming the same include forming a layer of activating material on sidewalls of a stack of alternating layers of channel material and sacrificial material. The layer of activating material is annealed to cause the activating material to react with the sacrificial material and to form insulating spacers at ends of the layers of sacrificial material. The layer of activating material is etched away to expose ends of the layers of channel material. Source/drain regions are formed on the ends of the layers of channel material.
US09947760B2 Method for manufacturing an emitter for high-speed heterojunction bipolar transistors
A method for manufacturing a bipolar junction transistor is provided. A layer stack is provided that comprises a semiconductor substrate having a trench isolation; an isolation layer arranged on the semiconductor substrate, wherein the first isolation layer comprises a recess forming an emitter window; lateral spacers arranged on sidewalls of the emitter window; a base layer arranged in the emitter window on the semiconductor substrate; and an emitter layer arranged on the isolation layer, the lateral spacers and the base layer. A sacrificial layer is provided on the emitter layer thereby overfilling a recess formed by the emitter layer due to the emitter window. The sacrificial layer is selectively removed up to the emitter layer while maintaining a part of the sacrificial layer filling the recess of the emitter layer. The emitter layer is selectively removed up to the isolation layer while maintaining the filled recess of the emitter layer.
US09947754B1 Manufacturing method of array substrate and LCD panel
The invention provides a manufacturing method of array substrate, wherein a light-shielding layer is disposed on the semiconductor layer, the light-shielding layer is a light-absorbing positive photo-resist, the light-shielding layer uses the same layer design as the photo-resist layer used for etching the semiconductor layer, after etching the semiconductor layer, the photo-resist layer is baked to obtain the light-shielding layer smaller than the semiconductor layer to shield the irradiation on the semiconductor layer to reduce the current leakage; then ohmic contact layer is formed at both ends of the semiconductor layer by phosphorus ion-implantation. In the LCD panel, the light-shielding layer is disposed on the semiconductor layer, the light-shielding layer serves both as an etching stopper and light-shielding, and can replace the BM of the conventional CF substrate to block light irradiation on the semiconductor layer, reduce leakage current, simplify panel structure, and improve aperture ratio.
US09947752B2 Semiconductor device having protection film with recess
A semiconductor device may include a semiconductor substrate, a first metal film covering a surface of the semiconductor substrate; a protection film covering a peripheral portion of a surface of the first metal film; and a second metal film covering a range extending across a center portion of the surface of the first metal film and a surface of the protection film, wherein a recess may be provided in the surface of the protection film, and a part of the second metal film may be in contact with an inner surface of the recess.
US09947751B2 Semiconductor device and method of manufacturing the same
A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type provided on the first semiconductor region, a third semiconductor region of the first conductivity type provided on the second semiconductor region, a first insulating part provided in the first semiconductor region, a first electrode provided in the first semiconductor region, the first insulating part disposed between the first electrode and the first semiconductor region, a second insulating part provided on the first electrode, a gate electrode provided on the second insulating part, a gate insulating part provided between the gate electrode and the second semiconductor region, and a second electrode provided on the second semiconductor region and on the third semiconductor region, and is electrically connected to the second semiconductor region, the third semiconductor region, and the first electrode.
US09947750B2 Silicon carbide semiconductor switching device and method of manufacturing silicon carbide semiconductor switching device
A silicon carbide semiconductor switching device having a planar metal oxide semiconductor insulated gate structure. The silicon carbide semiconductor switching device includes a silicon carbide semiconductor substrate having a bandgap wider than that of silicon, a drift layer formed on the silicon carbide semiconductor substrate, a base region selectively formed in the drift layer at a top surface thereof, a source contact region selectively formed in the base region at a top surface thereof, a trench formed in the drift layer at the top surface thereof, the trench having a depth that is shallower than a depth of the source contact region, a gate electrode embedded in the trench, a top surface of the gate electrode being substantially flush with a top surface of the source contact region, and an interlayer insulating film formed on the top surfaces of the source contact region and the gate electrode.
US09947749B2 Thin film compositions and methods
Certain embodiments of the present invention include a versatile and scalable process, “patterned regrowth,” that allows for the spatially controlled synthesis of lateral junctions between electrically conductive graphene and insulating h-BN, as well as between intrinsic and substitutionally doped graphene. The resulting films form mechanically continuous sheets across these heterojunctions. These embodiments represent an element of developing atomically thin integrated circuitry and enable the fabrication of electrically isolated active and passive elements embedded in continuous, one atom thick sheets, which may be manipulated and stacked to form complex devices at the ultimate thickness limit.
US09947748B2 Dielectric isolated SiGe fin on bulk substrate
A method for forming fins on a semiconductor device includes etching trenches into a monocrystalline substrate to form first fins and forming a first dielectric layer at bottoms of the trenches. Second fins of a material having a different composition than the substrate are grown on sidewalls of the trenches. A second dielectric layer is formed over the second fins. The first fins are removed by etching. The second fins are processed to form fin field effect transistor devices.
US09947746B2 Bipolar junction transistor device and method for fabricating the same
A bipolar junction transistor (BJT) device includes a semiconductor substrate, a first doping region with a first conductivity, a second doping region with a second conductivity, a third doping region with the first conductivity, at least one stacked block and a conductive contact. The first doping region is formed in the semiconductor substrate. The second doping region is formed in the first doping region. The at least one stacked block is formed on and insulated from the second doping region. The third doping region is formed in the second doping region and disposed adjacent to the at least one stacked block. The conductive contact electrically connects the at least one stacked block with the third doping region.
US09947744B2 Nanowire semiconductor device including lateral-etch barrier region
A semiconductor device includes a semiconductor-on-insulator wafer having a buried oxide layer. The buried oxide layer includes therein opposing etch barrier regions and a gate region between the etch barrier regions. The semiconductor device further includes at least one nanowire having a channel portion interposed between opposing source/drain portions. The channel portion is suspended in the gate region. A gate electrode is formed in the gate region, and completely surrounds all surfaces of the suspended nanowire. The buried oxide layer comprises a first electrical insulating material, and the etch barrier regions comprising a second electrical insulating material different from the first electrical insulating material.
US09947742B2 Power semiconductor device
A power semiconductor device includes: a substrate; an anode electrode and a cathode electrode disposed on the substrate; a well region disposed inside the substrate in a lower portion of the anode electrode, and having p-type conductivity; an NISO region disposed in a lower portion of the well region inside the substrate, and having a first n-type impurity concentration; and an n-type buried layer disposed in a lower portion of the NISO region, and having a second impurity concentration greater than the first n-type impurity concentration, inside the substrate.
US09947740B1 On-chip MIM capacitor
A method for forming an on-chip capacitor with complementary metal oxide semiconductor (CMOS) devices includes forming a first capacitor electrode between gate structures in a capacitor region while forming contacts to source and drain (S/D) regions in a CMOS region. Gate structures are cut in the CMOS region and the capacitor region by etching a trench across the gate structures and filling the trench with a dielectric material. The gate structures and the dielectric material in the trench in the capacitor region are removed to form a position for an insulator and a second electrode. The insulator is deposited in the position. Gate metal is deposited to form gate conductors in the CMOS region and the second electrode in the capacitor region.
US09947732B2 Organic light emitting diode display device
Disclosed is an organic light emitting diode (OLED) display device including a substrate including a pixel region and a boundary region outside the pixel region. The pixel region comprises an area having a short side and a long side. The pixel region comprises an array of pixels to emit light. The OLED display device includes a substrate in the pixel region and in the boundary region The OLED display device further includes a first electrode of a light emitting device in the pixel region over the substrate, a first bank covering edges of the first electrode in the pixel region on the substrate in the boundary region, wherein a width of an edge of the first bank along the short side of the pixel region is different from a width of an edge of the first bank along the long side of the pixel region, and a second bank on a portion of the first bank in the boundary region.
US09947728B2 Hybrid MEMS OLED display
A hybrid display includes a blue LED backlight layer, at least one shutter element, a frontplane having multiple sub-pixels, and a backplane operatively connected to the frontplane and the at least one shutter element. The backplane and the at least one shutter element are positioned between the backlight layer and the frontplane.
US09947727B2 Organic light emitting display device and method of manufacturing the same
An organic light emitting display device realizes slimness, having flexibility, and effectively reducing or preventing visibility of reflected external light, which includes an organic light emitting panel, a first adhesive layer on the organic light emitting panel, a touch electrode array being in contact with the first adhesive layer, a separation layer on the touch electrode array, and a cover film on the separation layer.
US09947726B2 Foldable display
A foldable display device according to one or more exemplary embodiments of the present invention includes: a first supporting member; a second supporting member coupled to the first supporting member and configured to be rotated with respect to the first supporting member; an ultra-elastic sheet adhered to the first supporting member and the second supporting member; and a display module adhered to the ultra-elastic sheet.
US09947725B2 Display device
A plurality of pixels P and a plurality of light-transmitting regions L are alternately disposed such that a light-transmitting region M1 is disposed between two pixels closest to each other in a X-direction and a light-transmitting region M2 is disposed between two pixels closest to each other in a Y-direction. Each of the light-transmitting regions is divided into a plurality of divided regions by a plurality of wirings WX and a plurality of wirings WY. The divided regions include first regions and second regions that are different from each other in widths in at least one of the X-direction and the Y-direction.
US09947724B2 Ultralow power carbon nanotube logic circuits and method of making same
A method of fabricating a CMOS logic device with SWCNTs includes forming a plurality of local metallic gate structures on a substrate by depositing a metal on the substrate; forming a plurality of contacts on the substrate; and depositing the SWCNTs on the substrate, and doping a certain area of the SWCNTs to form the CMOS logic device having at least one NMOS transistor and at least one PMOS transistor. Each of the NMOS and PMOS transistors has a gate formed by one of the local metallic gate structures, and a source and a drain formed by two of the contacts respectively. The gate of each PMOS transistor and the gate of each NMOS transistor are configured to alternatively receive at least one input voltage. At least one of the drain of the PMOS transistor and the drain of the NMOS transistor is configured to output an output voltage.
US09947721B2 Thermal insulation for three-dimensional memory arrays
Methods, systems, and devices for a three-dimensional memory array are described. Memory cells may transform when exposed to elevated temperatures, including elevated temperatures associated with a read or write operation of a neighboring cell, corrupting the data stored in them. To prevent this thermal disturb effect, memory cells may be separated from one another by thermally insulating regions that include one or several interfaces. The interfaces may be formed by layering different materials upon one another or adjusting the deposition parameters of a material during formation. The layers may be created with planar thin-film deposition techniques, for example.
US09947720B2 Three-dimensional memory apparatuses and methods of use
A three dimensional (3D) memory array may include a plurality of memory cells. An example 3D memory array may include an electrode plane and a memory material disposed through and coupled to the electrode plane. A memory cell included in the memory material is aligned in a same plane as the electrode plane, and the memory cell is configured to exhibit a first threshold voltage representative of a first logic state and a second threshold voltage representative of a second logic state. A conductive pillar is disposed through and coupled to the memory cell, wherein the conductive pillar and electrode plane are configured to provide a voltage across the memory cell to write a logic state to the memory cell.
US09947715B2 Manufacturing method of semiconductor device
The present invention makes it possible to improve the performance of a semiconductor device.After anisotropic etching is applied to an insulating film covering a gate electrode of a transfer transistor and a sidewall spacer is formed over the sidewall of the gate electrode, a damaged layer formed in the interior of a semiconductor substrate by the anisotropic etching is removed by oxidizing the surface of the semiconductor substrate, forming a sacrificial oxide film, and removing the sacrificial oxide film.
US09947713B2 Detection substrate and manufacturing method thereof, and detector
A detection substrate and a manufacturing method thereof, and a detector are provided. The detection substrate comprises a base substrate, a thin film transistor, a PIN photodiode and a scintillation layer. The thin film transistor and the PIN photodiode are provided above a first face of the base substrate and the scintillation layer is provided above a second face of the base substrate. The visible light obtained after the X-ray passes through the scintillation layer is directly irradiated on the PIN photodiode after passing through the base substrate with relative high transmittance, thus preventing intensity of the light irradiated on the PIN photodiode from being weakened, and improving light utilization efficiency of the detection substrate.
US09947712B2 Matrix type integrated circuit with fault isolation capability
Technology is described for selectively disconnecting a communal module (e.g., horizontal power and signal distribution network) from conductive traces (e.g., vertical columns) that are coupled to cell elements. In one example, a matrix type integrated circuit includes a two dimensional (2D) array of cell elements, a plurality of conductive traces, a communal module, and a plurality of switches. Each cell element in the 2D array provides a similar function. The plurality of conductive traces is substantially parallel to a first axis of the 2D array. Each conductive trace is coupled to a conductive interconnect of cell elements adjacent to the conductive trace. The communal module is configured to provide distribution of at least one electrical signal to the cell elements in the 2D array via at least two conductive traces that are substantially parallel to the first axis.
US09947701B2 Low noise device and method of forming the same
A low noise device includes an isolation feature in a substrate. The low noise device further includes a gate stack over a channel in the substrate. The gate stack includes a gate dielectric layer extending over a portion of the isolation feature, and a gate electrode over the gate dielectric layer. The low noise device further includes a charge trapping reducing structure adjacent to the isolation feature. The charge trapping reducing structure is configured to reduce a number of charge carriers adjacent an interface between the isolation feature and the channel.
US09947699B2 Manufacturing method of dual gate oxide semiconductor TFT substrate and substrate thereof
A method for manufacturing a dual gate oxide semiconductor TFT substrate utilizes a halftone mask to implement a photo process, which not only accomplishes patterning to an oxide semiconductor layer but also obtains an oxide conductor layer with ion doping. The method implements patterning to a bottom gate isolation layer and a top gate isolation layer at the same time with one photolithographic process. The method implements patterning to second and third metal layers at the same time to obtain a first source, a first drain, a second source, a second drain, a first top gate and a second top gate with one photolithographic process. The method implements patterning to a second flat layer, a passivation layer and a top gate isolation layer at the same time with one photolithographic process. The number of photolithographic processes involved is reduced to nine so as to simplify the manufacturing process.
US09947696B2 LTPS TFT substrate structure and method of forming the same
A method of forming an LTPS TFT substrate includes: Step 1: providing a substrate and depositing a buffer layer; Step 2: depositing an a-Si layer; Step 3: depositing and patterning a silicon oxide layer; Step 4: taking the silicon oxide layer as a photomask and annealing the a-Si layer with excimer laser, so that the a-Si layer crystalizes and turns into a poly-Si layer; Step 5: forming a first poly-Si region and a second poly-Si region; Step 6: defining a heavily N-doped area and a lightly N-doped area on the first and second poly-Si regions, and forming an LDD area; Step 7: depositing and patterning a gate insulating layer; Step 8: forming a first gate and a second gate; Step 9: forming via holes; and Step 10: forming a first source/drain and a second source/drain.
US09947691B2 Array substrate, manufacturing method thereof and display panel
An array substrate, a manufacturing method thereof and a display panel are disclosed. The array substrate comprises: a base substrate (200) and gate lines (202), data lines (205) and a plurality of pixel units (20). Each pixel unit (20) includes a first thin-film transistor (TFT), a pixel electrode (208) and at least second TFT connected in series with the first TFT. The pixel electrode (208) is connected with a drain electrode (207) of the second TFT; a source electrode (206′) of the second TFT is connected with a drain electrode (207) of the first TFT; and a source electrode (206) of the first TFT is connected with the data line (205). The array substrate can reduce the leakage current when the TFTs are switched off.
US09947690B2 Display panel
A display panel is disclosed. The display panel includes a first substrate, a display layer, a first conductive layer, a first insulation layer, a first protective layer, and a second insulation layer. The first substrate includes an active area and a peripheral area located adjacent to the active area. The display layer is disposed over the first substrate. The first conductive layer is disposed over the first substrate and located in the peripheral area. The first insulation layer is disposed between the first substrate and the first conductive layer. The first protective layer covers the first conductive layer. The second insulation layer is disposed over the first protective layer. The display panel according to the disclosure has better corrosion resistance to improve its reliability.
US09947689B2 Semiconductor device structure with 110-PFET and 111-NFET current flow direction
A FinFET comprises a hybrid substrate having a top wafer of (100) silicon, a handle wafer of (110) silicon, and a buried oxide layer between the top wafer and the handle wafer; a first set of fins disposed in the top wafer and oriented in a <110> direction of the (100) silicon; and a second set of fins disposed in the handle wafer and oriented in a <112> direction of the (110) silicon. The first set of fins and the second set of fins are aligned.
US09947688B2 Integrated circuits with components on both sides of a selected substrate and methods of fabrication
Novel integrated circuits (SOI ICs), and methods for making and mounting the ICs are disclosed. In one embodiment, an IC comprises a first circuit layer of the IC formed from an active layer of an SOI wafer. The first circuit layer is coupled to a first surface of buffer layer, and a second surface of the buffer layer is coupled to a selected substrate comprising an insulating material. The selected substrate may be selected, without limitation, from the following types: sapphire, quartz, silicon dioxide glass, piezoelectric materials, and ceramics. A second circuit layer of the IC are formed, coupled to a second surface of the selected substrate. In one embodiment of a mounted IC, the first circuit layer is coupled to contact pads on a package substrate via solder bumps or copper pillars. The second circuit layer is coupled to contact pads on the package substrate via wire bonds.
US09947682B2 Three dimensional non-volatile memory with separate source lines
A three dimensional stacked non-volatile memory device comprises alternating dielectric layers and conductive layers in a stack, a plurality of bit lines below the stack, and a plurality of source lines above the stack. There is a separate source line for each bit line. Each source lines is connected to a different subset of NAND strings. Each bit line is connected to a different subset of NAND strings. Multiple data states are verified concurrently. Reading is performed sequentially for the data states. The data states are programmed concurrently with memory cells being programmed to lower data states having their programming slowed by applying appropriate source line voltages and bit line voltages.
US09947678B2 Wing-type projection between neighboring access transistors in memory devices
A flash memory device is disposed on a semiconductor substrate. The flash memory device includes flash memory cells arranged in rows and columns. Respective flash memory cells include respective access transistors and respective floating gate transistors. The respective access transistors have respective access gates, and the respective floating gate transistors have respective control gates arranged over respective floating gates. First and second wordlines extend substantially in parallel with one another and correspond to first and second rows which neighbor one another. The first wordline is coupled to access gates of access transistors along the first row. The second wordline is coupled to access gates of access transistors along the second row. Nearest edges of the first and second wordlines include at least one wing which extends laterally outward from a sidewall of one of the first and second wordlines towards a sidewall the other of the first and second wordlines.
US09947676B2 NVM memory HKMG integration technology
The present disclosure relates to an integrated circuit (IC) that includes a HKMG hybrid non-volatile memory (NVM) device and that provides small scale and high performance, and a method of formation. In some embodiments, the integrated circuit includes a memory region having a NVM device with a pair of control gate electrodes separated from a substrate by corresponding floating gates. A pair of select gate electrodes are disposed at opposite sides of the pair of control gate electrodes. A logic region is disposed adjacent to the memory region and has a logic device with a metal gate electrode disposed over a logic gate dielectric and having bottom and sidewall surfaces covered by a high-k gate dielectric layer. The select gate electrodes or the control gate electrodes comprise metal and have bottom and sidewall surfaces covered by the high-k gate dielectric layer.
US09947674B2 Static random-access memory (SRAM) cell array
A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent pull-up FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.
US09947673B1 Semiconductor memory device
The present invention provides a semiconductor memory device, includes at least one static random access memory (SRAM) cell, wherein the SRAM cell includes a first pick-up node, and a dielectric oxide SRAM (DOSRAM), disposed in a first dielectric layer and disposed above the SRAM cell when viewed in a cross section view, wherein the DOSRAM includes an oxide semiconductor filed effect transistor (OSFET) and a capacitor, a source of the OSFET is electrically connected to the first pick-up node of the SRAM cell through a via structure, and at least parts of the first dielectric layer are disposed between the source of the OSFET and the via structure, and the capacitor is disposed above the OSFET and electrically connected to a drain of the OSFET when viewed in the cross section view.
US09947670B2 Semiconductor device
A static random access memory (SRAM) device includes an inverter including a ninth first-conductivity-type semiconductor layer formed on a semiconductor substrate; a first pillar-shaped semiconductor layer which is formed on the semiconductor substrate and in which a first first-conductivity-type semiconductor layer, a first body region, a second first-conductivity-type semiconductor layer, a first second-conductivity-type semiconductor layer, a second body region, and a second second-conductivity-type semiconductor layer are formed from the substrate side in that order; a first gate insulating film formed around the first body region; a first gate formed around the first gate insulating film; a second gate insulating film formed around the second body region; a second gate formed around the second gate insulating film; and a first output terminal connected to the second first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer.
US09947666B2 Semiconductor device structures including buried digit lines and related methods
Methods of forming semiconductor device structures include forming trenches in an array region and in a buried digit line end region, forming a metal material in the trenches, filling the trenches with a mask material, removing mask material in the trenches to expose a portion of the metal material, and removing the exposed portion of the metal material. A plurality of conductive contacts is formed in direct contact with the metal material in the buried digit line end region. Methods of forming a buried digit line contact include forming conductive contacts physically contacting metal material in trenches in a buried digit line end region. Vertical memory devices and apparatuses include metallic connections disposed between a buried digit line and a conductive contact in a buried digit line end region.
US09947661B2 Semiconductor device and method of manufacturing the same
A semiconductor device, and a method of manufacturing the same, includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a dummy gate structure provided between the first and second gate structures, a first source/drain region between the first gate structure and the dummy gate structure, a second source/drain region between the second gate structure and the dummy gate structure, a connection contact provided on the dummy gate structure, and a common conductive line provided on the connection contact. The dummy gate structure extends in the first direction. The connection contact extends in the second direction to connect the first source/drain region to the second source/drain region. The common conductive line configured to a voltage to the first and second source/drain regions through the connection contact.
US09947657B2 Semiconductor device and a method for fabricating the same
A semiconductor device includes a fin field effect transistor. The semiconductor device includes a first gate electrode, a first source/drain (S/D) region disposed adjacent to the first gate electrode, a first S/D contact disposed on the first S/D region, a first spacer layer disposed between the first gate electrode and the first S/D region, a first contact layer in contact with the first gate electrode and the first S/D contact, and a first wiring layer integrally formed with the first contact layer. There is no interface between the first contact layer and the first wiring layer in a cross sectional view, and the first contact layer has a smaller area than the first wiring layer in plan view.
US09947647B2 Method and system for over-voltage protection using transient voltage suppression devices
A method of fabricating an overvoltage protection device and an over-voltage circuit protection device are provided. The over-voltage circuit protection device includes a plurality of transient voltage suppression (TVS) devices coupled in electrical parallel.
US09947644B2 Semiconductor package
A semiconductor package is provided. The semiconductor package may include a plurality of memory chips, which are mounted on a top surface of a package substrate, and a plurality of controller chips, which are vertically stacked on at least one of top and bottom surfaces of the package substrate.
US09947641B2 Wire bond support structure and microelectronic package including wire bonds therefrom
A microelectronic package may include a substrate having first and second regions, a first surface and a second surface remote from the first surface; at least one microelectronic element overlying the first surface within the first region; electrically conductive elements at the first surface within the second region; a support structure having a third surface and a fourth surface remote from the third surface and overlying the first surface within the second region in which the third surface faces the first surface, second and third electrically conductive elements exposed respectively at the third and fourth surfaces and electrically connected to the conductive elements at the first surface in the first region; and wire bonds defining edge surfaces and having bases electrically connected through ones of the third conductive elements to respective ones of the second conductive elements and ends remote from the support structure and the bases.
US09947639B2 Semiconductor module
A semiconductor module (10A) according to one embodiment includes a plurality of first and second transistor chips (hereinafter, first and second transistors) (12A, 12B) and a substrate (90). In each of the first and second transistors, first and second main electrode pads (18, 20) are each electrically connected together; the second main electrode pads of the first transistors are electrically connected to the first main electrode pads of the second transistors; control electrode pads of the first and second transistors are respectively connected to first and second control electrode wiring patterns (94, 98) on the substrate via first and second resistance parts (13A, 13B); and the first and second resistance parts respectively have a plurality of first and second resistance elements (72A, 72B) each connected to the corresponding control electrode pad, and first and second linking parts (74A, 74B) respectively linking the plurality of first and second resistance elements together.
US09947638B2 Device and method for permanent bonding
A method and corresponding device for permanent bonding of a first layer of a first substrate to a second layer of a second substrate on a bond interface, characterized in that a dislocation density of a dislocation of the first and/or second layer is increased at least in the region of the bond interface before and/or during the bonding.
US09947636B2 Method for making semiconductor device with lead frame made from top and bottom components and related devices
A method for making a semiconductor device may include bonding a top lead frame component, having recesses, with a bottom lead frame component to form a lead frame, the top and bottom lead frame components each including metal. The method may include mounting an IC on the lead frame, encapsulating the IC and the lead frame, and removing portions of the bottom lead frame component to define contacts for the IC.
US09947632B2 Semiconductor device and method of making a semiconductor device
A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, one or more contacts located on the major surface and an encapsulant covering at least the major surface. A peripheral edge of each contact defines a contact area on the major surface. The device also includes one or more bond pads located outside the encapsulant. Each bond pad is electrically connected to a respective contact located on the major surface of the substrate by a respective metal filled via that passes through the encapsulant. A sidewall of each respective metal filled via, at the point at which it meets the respective contact, falls inside the contact area defined by the respective contact when viewed from above the major surface of the substrate, whereby none of the metal filling each respective via extends outside the contact area of each respective contact.
US09947631B2 Surface finishes for interconnection pads in microelectronic structures
A surface finish may be formed in a microelectronic structure, wherein the surface finish may include an interlayer comprising a refractory metal, phosphorus, and nickel, with the refractory metal having a content of between about 2 and 12% by weight and the phosphorus having a content of between about 2 and 12% by weight with the remainder being nickel. In one embodiment, the refractory metal of the interlayer may consist of one of tungsten, molybdenum, and ruthenium. In another embodiment, the interlayer may comprise the refractory metal being tungsten having a content of between about 5 and 6% by weight and phosphorus having a content of between about 5 and 6% by weight with the remainder being nickel.
US09947630B2 Package with solder regions aligned to recesses
A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad.
US09947627B2 Guard ring structure and method for forming the same
A guard ring structure having a semiconductor substrate with a circuit region encircled by a first ring and a second ring. At least one of the first and second ring includes: a plurality of separated doping regions formed in various top portions of the semiconductor substrate, providing P-N junction or N-P junction on bottom of the plurality of separated doping regions; and an interconnect element formed over the semiconductor substrate, covering at least portion of the plurality of separated doping regions.
US09947624B2 Semiconductor package assembly with through silicon via interconnect
The invention provides a semiconductor package assembly with a TSV interconnect. The semiconductor package assembly includes a first semiconductor package mounted on a base, having: a semiconductor die, a semiconductor substrate, and a first array of TSV interconnects and a second array of TSV interconnects formed through the semiconductor substrate, wherein the first array and second array of TSV interconnects are separated by an interval region. The assembly further includes a second semiconductor die mounted on the first semiconductor package, having a ground pad thereon. One of the TSV interconnects of the first semiconductor package has a first terminal coupled to the ground pad of the second semiconductor die and a second terminal coupled to an interconnection structure disposed on a front side of the semiconductor substrate.
US09947622B2 Ultrathin superlattice of MnO/Mn/MnN and other metal oxide/metal/metal nitride liners and caps for copper low dielectric constant interconnects
An electrical device including an opening in a low-k dielectric material, and a copper including structure present within the opening for transmitting electrical current. A liner is present between the opening and the copper including structure. The liner includes a superlattice structure comprised of a metal oxide layer, a metal layer present on the metal oxide layer, and a metal nitride layer that is present on the metal layer. A first layer of the superlattice structure that is in direct contact with the low-k dielectric material is one of said metal oxide layer and a final layer of the superlattice structure that is in direct contact with the copper including structure is one of the metal nitride layers.
US09947619B2 Coupling structures for signal communication and method of making same
Techniques and mechanism to provide signal communication with vias variously extending in a substrate. In an embodiment, a first capacitor and a second capacitor are coupled in parallel with one another each between a first via and a second via, the first via to receive a first signal. Respective portions of the first signal are concurrently communicated from the first via to the second via with the first capacitor and the second capacitor, respectively. In another embodiment, the first signal is one signal of a differential signal pair further comprising a second signal which is received at a third via. Respective portions of the second signal are concurrently communicated from the third via to a fourth via with a third capacitor and a fourth capacitor, respectively. The third capacitor and the fourth capacitor are coupled in parallel with one another each between the third via and the fourth via.
US09947618B2 Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates
In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A, 120E.B) are provided above the substrate that wrap around the conductive vias' protrusions (114′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.
US09947616B2 High power MMIC devices having bypassed gate transistors
Monolithic microwave integrated circuits are provided that include a substrate having a transistor and at least one additional circuit formed thereon. The transistor includes a drain contact extending in a first direction, a source contact extending in the first direction in parallel to the drain contact, a gate finger extending in the first direction between the source contact and the drain contact and a gate jumper extending in the first direction. The gate jumper conductively connects to the gate finger at two or more locations that are spaced apart from each other along the first direction.
US09947615B2 Electronic circuit and camera
An electronic circuit includes a generating circuit for generating a first group of signals and a second group of signals, and a transmission path for transmitting the first group of signals and the second group of signals. The first group of signals are composed of signals synchronized with a first edge that is one of the rising edge and the falling edge of a reference clock, and the second group of signals are composed of signals synchronized with a second edge that is the other of the rising edge and falling edge. The transmission path includes first transmission lines for transmitting the signals composing the first group and second transmission lines for transmitting the signals composing the second group, and the first and second transmission lines are alternately arranged.
US09947611B2 Through hole arrays for flexible layer interconnects
Disclosed is an integrated circuit arrangement including a two sided circuit board, having a first surface and a second surface. A plurality of electrical conductors is incorporated as part of the two sided circuit board. An array of through holes extend through the first surface and the second surface, arranged in a pattern and are configured to provide a common electrical connection area, wherein the common electrical connection area is associated with a portion of a particular one of the plurality of electrical conductors.
US09947609B2 Integrated circuit stack
In some examples, an integrated circuit system includes a plurality of integrated circuit layers. At least one of the integrated circuit layers includes an integrated circuit die, which may not include any through-silicon vias that provide a pathway to an adjacent integrated circuit layer, and an interposer portion, which includes electrically conductive through-vias. The interposer portion may facilitate communication of the integrated circuit die with other integrated circuit layers of the integrated circuit system. In some examples, the stacked integrated circuit system may include more than one integrated circuit die, which may be in the same integrated circuit layer as at least one other integrated circuit die, or may be in a different integrated circuit layer.
US09947608B2 Method of manufacture for a semiconductor device
A method of manufacture for a semiconductor device is disclosed. The method includes providing a semiconductor stack structure that includes a device terminal of a semiconductor device, and having a first surface and a buried oxide (BOX) layer attached to a wafer handle. Another step includes disposing a polymeric layer that includes a polymer and an admixture that increases thermal conductivity of the polymer onto the first surface of the semiconductor stack structure. Another step involves removing the wafer handle from the BOX layer to expose a second surface of the semiconductor stack structure, and yet another step involves removing a portion of the semiconductor stack structure to expose the device terminal.
US09947601B1 Integrated circuit including NCEM-enabled, side-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
An integrated circuit, in the form of a wafer, die, or chip, includes multiple standard cell-compatible fill cells, configured to enable non-contact electrical measurements. Such fill cells include mesh pads that contain at least three conductive stripes disposed between adjacent gate stripes. Such fill cells further include geometry to enable non-contact evaluation of side-to-side shorts and/or leakages.
US09947595B2 Semiconductor device structure with gate spacer having protruding bottom portion and method for forming the same
A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on the sidewall of the gate stack structure, and the gate spacers include a top portion and a bottom portion adjoined to the top portion, and the bottom portion slopes to a top surface of the substrate. The semiconductor device structure further includes an epitaxial structure formed adjacent to the gate spacers, and the epitaxial structure is formed below the gate spacers.
US09947593B2 Extra gate device for nanosheet
A method for forming semiconductor devices includes forming a highly doped region. A stack of alternating layers is formed on the substrate. The stack is patterned to form nanosheet structures. A dummy gate structure is formed over and between the nanosheet structures. An interlevel dielectric layer is formed. The dummy gate structures are removed. SG regions are blocked, and top sheets are removed from the nanosheet structures along the dummy gate trench. A bottommost sheet is released and forms a channel for a field effect transistor device by etching away the highly doped region under the nanosheet structure and layers in contact with the bottommost sheet. A gate structure is formed in and over the dummy gate trench wherein the bottommost sheet forms a device channel for the EG device.
US09947592B2 FinFET devices and methods of forming the same
FinFET devices and methods of forming the same are disclosed. One of the FinFET devices includes a substrate, multiple gates and a single spacer wall. The substrate is provided with multiple fins extending in a first direction. The multiple gates extending in a second direction different from the first direction are provided respectively across the fins. Two of the adjacent gates are arranged end to end. The single spacer wall extending in the first direction is located between the facing ends of the adjacent gates and is in physical contact with a gate dielectric material of each of the adjacent gates.
US09947589B1 Methods of forming a gate contact for a transistor above an active region and the resulting device
A transistor is formed above an active region. The transistor includes a gate structure, a first gate cap layer and a first sidewall spacer positioned adjacent sidewalls of the gate structure. Source/drain contacts are formed adjacent the first sidewall spacer. The first gate cap layer and a portion of the first sidewall spacer are removed to define a gate contact cavity that exposes a portion of the gate structure and an upper portion of the SD contacts. A second spacer and a conductive gate plug are formed in the gate contact cavity. Upper portions of the SD contacts positioned adjacent the second spacer are removed to define a gate cap cavity. A second gate cap layer is formed in the gate cap cavity. An insulating layer is formed above the second gate cap layer. A first conductive structure is formed in the insulating layer conductively coupled to the gate structure.
US09947588B1 Method for manufacturing fins
A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is performed to the fins. A thermal process is performed after the ion implantation. An insulating layer is formed on the substrate, and the fins are embedded in the insulating layer. Thereafter, a portion of the insulating layer is removed to form an isolation structure on the substrate, and the fins are exposed from a top surface of the isolation structure. The insulating layer is formed after the ion implantation and the thermal process. Or, the isolation structure is formed before the ion implantation, or between the ion implantation and the thermal process.
US09947587B2 Method of forming fin structure of semiconductor device
A method of forming a fin structure of a semiconductor device, such as a fin field effect transistor (FinFET) is provided. In an embodiment, trenches are formed in a substrate, and a liner is formed along sidewalls of the trenches, wherein a region between adjacent trenches define a fin. A dielectric material is formed in the trenches. Portions of the semiconductor material of the fin are replaced with a second semiconductor material and a third semiconductor material, the second semiconductor material having a different lattice constant than the substrate and the third semiconductor material having a different lattice constant than the second semiconductor material. Portions of the second semiconductor material are oxidized.
US09947586B2 Tunneling fin type field effect transistor with epitaxial source and drain regions
A method of forming semiconductor devices may begin with forming gate structures over fin structures on sidewalls of at least two mandrels. The mandrels are removed to provide gate structures having a first pitch and gate structure spacers having a second pitch. A first conductivity type epitaxial semiconductor material is formed on the exposed portions of the fin structures. Masking is formed in the first pitch space. The first conductivity type epitaxial semiconductor material is removed from a second space pitch. A second conductivity type epitaxial semiconductor material is formed in the second space pitch.
US09947584B2 Systems and methods for controlling release of transferable semiconductor structures
The disclosed technology relates generally to methods and systems for controlling the release of micro devices. Prior to transferring micro devices to a destination substrate, a native substrate is formed with micro devices thereon. The micro devices can be distributed over the native substrate and spatially separated from each other by an anchor structure. The anchors are physically connected/secured to the native substrate. Tethers physically secure each micro device to one or more anchors, thereby suspending the micro device above the native substrate. In certain embodiments, single tether designs are used to control the relaxation of built-in stress in releasable structures on a substrate, such as Si (1 1 1). Single tether designs offer, among other things, the added benefit of easier break upon retrieval from native substrate in micro assembly processes. In certain embodiments, narrow tether designs are used to avoid pinning of the undercut etch front.
US09947583B2 Method of semiconductor integrated circuit fabrication
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.
US09947582B1 Processes for preventing oxidation of metal thin films
Processes are provided herein for protecting metal thin films from oxidation when exposed to an oxidizing environment, such as the ambient atmosphere. The processes may comprise a protective treatment including exposing the metal thin film to a silicon-containing precursor at a temperature of about 200° C. or less in order to selectively adsorb a silicon-containing protective layer on the metal thin film. The silicon-containing protective layer may reduce or substantially prevent the underlying metal thin film from oxidation.
US09947579B2 Copper interconnect structure with manganese oxide barrier layer
Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.
US09947578B2 Methods for forming low-resistance contacts through integrated process flow systems
Methods for forming metal contacts having tungsten liner layers are provided herein. In some embodiments, a method of processing a substrate includes: exposing a substrate, within a first substrate process chamber, to a plasma formed from a first gas comprising a metal organic tungsten precursor gas or a fluorine-free tungsten halide precursor to deposit a tungsten liner layer, wherein the tungsten liner layer is deposited atop a dielectric layer and within a feature formed in a first surface of the dielectric layer of a substrate; transferring the substrate to a second substrate process chamber without exposing the substrate to atmosphere; and exposing the substrate to a second gas comprising a tungsten fluoride precursor to deposit a tungsten fill layer atop the tungsten liner layer.
US09947573B2 Lateral PiN diodes and schottky diodes
Lateral PiN diodes and Schottky diodes with low parasitic capacitance and variable breakdown voltage structures and methods of manufacture are disclosed. The structure includes a diode with breakdown voltage determined by a dimension between p- and n-terminals formed in an i-region above a substrate.
US09947572B2 Substrate processing apparatus
In a substrate processing apparatus, a shield plate includes a first chucking magnetic material (441). The shield plate is moved up and down by a chamber opening-and-closing mechanism. A substrate holding part includes a movable chuck member (412) and a fixed chuck member. The movable chuck member (412) includes a second chucking magnetic material (442). When the shield plate is moved down, the shield plate comes in close proximity to the upper surface of a substrate (9), and the first chucking magnetic material (441) comes in close proximity to the second chucking magnetic material (442). The substrate (9) is held by magnetic action between the first chucking magnetic material (441) and the second chucking magnetic material (442). It is thus possible to hold the substrate (9) with a simple structure.
US09947563B2 Wafer container with air-tight device
A wafer container is provided. The wafer container includes a housing, a door and an air-tight device. The housing has a room with an opening formed therein, and a door frame surrounding the opening. The door fits in the door frame to close the opening. The air-tight device is disposed around the door, located between the door and the door frame, and having a protruding part extending toward the room. The protruding part has an early-stage pressure-adjusting element configured to exhaust a first gas from the room by pumping a second gas into the room when the door is closed.
US09947560B1 Integrated circuit package, and methods and tools for fabricating the same
An integrated circuit (IC) package, assembly tool and method for assembling an IC package are described herein. In a first example, an IC package is provided that includes a package substrate, at least a first integrated circuit (IC) die and a cover. The first integrated circuit (IC) die is mechanically and electrically coupled to the package substrate via solder connections. The cover is bonded to the package substrate. The cover encloses the first IC die and is laterally offset from a peripheral edge of the package substrate.
US09947558B2 Method for conditioning silicon part
A method for conditioning and cleaning a silicon part is provided. The silicon part is heated to a temperature of at least 300° C. in the presence of oxygen to form an outer surface of the silicon part into silicon oxide. The silicon part is placed in a wet bath wherein the bath is a solution that selectively etches silicon oxide with respect to silicon.
US09947556B2 Substrate cleaning apparatus, substrate cleaning method, and storage medium
There are provided first and second cleaning members which are configured to clean a central zone in a rear surface of a wafer when the wafer held by an absorption pad is horizontally held, and configured to clean a peripheral zone in the rear surface of the wafer when the wafer is held by the spin chuck. Due to the provision of the first and second cleaning members, detergency can be improved as compared with a case in which only one cleaning member is used. The first and second cleaning members are configured to be horizontally turned by a common turning shaft. When the central zone in the rear surface of the wafer is cleaned, the turning shaft is located to be overlapped with the wafer. Since the turning shaft is located by using the moving area of the wafer, a size of an apparatus can be reduced.
US09947555B2 Semiconductor manufacturing apparatus and method of manufacturing semiconductor device
In one embodiment, a semiconductor manufacturing apparatus includes a wafer retaining module configured to retain a wafer by a chuck pin and to rotate the wafer. The apparatus further includes a wafer cleaning module configured to retain a cleaning member for cleaning a surface of the wafer and to rotate the cleaning member around a first rotation axis that is perpendicular to the surface of the wafer, the wafer cleaning module cleaning the surface of the wafer by moving the cleaning member on the surface of the wafer while the cleaning member contacts the wafer and rotates. The wafer cleaning module retains and rotates the cleaning member so that the first rotation axis does not pass through a contact region of the cleaning member with respect to the wafer.
US09947551B2 Chip package structure and manufacturing method thereof
A chip package structure and the manufacturing method thereof are provided. Firstly, a conductive frame including a bottom plate and a plurality of partition plates is provided. The bottom plate has a supporting surface and a bottom surface opposite thereto, and the partition plates protrude from the supporting surface to define a plurality of the accommodating regions. Subsequently, a plurality of chips is provided, and each of the chips is correspondingly accommodated in each of the accommodating regions with a back surface facing to the supporting surface. Thereafter, the conductive frame is cut to form a plurality of separated chip package structures.
US09947550B2 Film forming method and method of manufacturing thin film transistor
Provided is a film forming method to minimize decreases in the electrical resistance of an oxide semiconductor film even when a fluorinated silicon nitride film is formed directly on the oxide semiconductor film. The film forming method includes: a surface treatment process in which a substance including an oxide semiconductor film on a substrate is prepared, plasma is generated using a mixed gas of oxygen and hydrogen which contains hydrogen at a rate of 8% or less (not including 0), and plasma is used to treat surface of oxide semiconductor film; a film formation process in which a fluorinated silicon nitride film (a SiN:F film) is subsequently forming on oxide semiconductor film by a plasma CVD method in which plasma is generated using a raw material gas containing silicon tetrafluoride gas and nitrogen gas; and an annealing process in which substrate and film thereon are subsequently heated.
US09947548B2 Self-aligned single dummy fin cut with tight pitch
A method of forming a semiconductor device and resulting structures having a dummy semiconductor fin removed from within an array of tight pitch semiconductor fins by forming a first spacer including a first material on a substrate; forming a second spacer including a second material on the substrate, the second spacer adjacent to the first spacer; and applying an etch process to the first spacer and the second spacer; wherein the etch process removes the first spacer at a first etch rate; wherein the etch process removes the second spacer at a second etch rate; wherein the first etch rate is different than the second etch rate.
US09947547B2 Environmentally green process and composition for cobalt wet etch
An environmentally green wet etch process for selective removal of cobalt metal generally includes applying water that is free of added buffers, acids, and/or bases to a substrate including exposed cobalt metal. The process can be utilized to form recesses where desired such as may be implemented for metal contact fill, metal gate fill, interconnect fill, or the like.
US09947546B2 Semiconductor integrated circuit device with a surface and method of manufacturing the same
A semiconductor integrated circuit device and a method of manufacturing the same are disclosed. A semiconductor wafer having a surface step is prepared. A first material layer is formed on an upper surface of the semiconductor wafer so that a protrusion is formed in a portion thereof corresponding to an edge region of the semiconductor wafer. A second material layer is formed on the first material layer.
US09947545B2 Methods for gate formation in circuit structures
Methods for forming a gate structure of a circuit structure are provide. The methods for forming the gate structure may include: forming a first gate pattern in a gate mask layer, the forming including a first etching of rounded corner portions of the first gate pattern; forming a second gate pattern in the gate mask layer, the second gate pattern at least partially overlapping the first gate pattern, the forming including a second etching of rounded corner portions of the second gate pattern; and, etching the gate mask layer using the first gate pattern and second gate pattern to form the gate structure.
US09947539B2 Plasma poisoning to enable selective deposition
Atomic layer deposition in selected zones of a workpiece surface is accomplished by transforming the surfaces outside the selected zones to a hydrophobic state while the materials in the selected zones remain hydrophilic.
US09947538B2 Semiconductor device manufacturing method including heat treatment
A method for manufacturing a semiconductor device may include the following steps: preparing a semiconductor structure that comprises a substrate and a first fin member, wherein the first fin member is connected to the substrate and comprises a first semiconductor portion; providing a first-type dopant member that directly contacts the first semiconductor portion, comprises first-type dopants, and is at least one of liquid and amorphous; and performing heat treatment on at least one of the first-type dopant member and the first semiconductor portion to enable a first portion of the first-type dopants to diffuse through a first side of the first-type dopant member into the first semiconductor portion.
US09947536B2 Semiconductor power device and method for producing same
A method for producing a semiconductor power device includes forming a gate trench from a surface of the semiconductor layer toward an inside thereof. A first insulation film is formed on the inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.
US09947534B2 Coating treatment method with airflow control, and non-transitory recording medium having program recorded thereon for executing coating treatment with airflow control
A coating treatment apparatus supplying a coating solution to a front surface of a rotated substrate and diffusing the supplied coating solution to an outer periphery side of the substrate to thereby apply the coating solution on the front surface of the substrate includes: a substrate holding part holding a substrate; a rotation part rotating the substrate held on the substrate holding part; a supply part supplying a coating solution to a front surface of the substrate held on the substrate holding part; and an airflow control plate provided at a predetermined position above the substrate held on the substrate holding part for locally changing an airflow above the substrate rotated by the rotation part at an arbitrary position.
US09947530B2 Method of manufacturing nitride semiconductor substrate
A method of manufacturing a nitride semiconductor substrate includes providing a silicon substrate having a first surface and a second surface opposing each other, growing a nitride template on the first surface of the silicon substrate in a first growth chamber, in which a silicon compound layer is formed on the second surface of the silicon substrate in a growth process of the nitride template, removing the silicon compound layer from the second surface of the silicon substrate, growing a group III nitride single crystal on the nitride template in a second growth chamber, and removing the silicon substrate from the second growth chamber.
US09947527B2 Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device according to the invention includes the step S1 of cleaning the silicon carbide substrate 1 surface, the step S2 of bringing a material gas into a plasma and irradiating the atoms contained in the material gas to silicon carbide substrate 1 for growing silicon nitride film 2 on silicon carbide substrate 1, the step S3 of depositing silicon oxide film 3 on silicon nitride film 2 by the ECR plasma CVD method, and the step S4 of annealing silicon carbide substrate 1 including silicon nitride film 2 and silicon oxide film 3 formed thereon in a nitrogen atmosphere. By the method of manufacturing a semiconductor device according to the invention, a semiconductor device that exhibits excellent interface properties including an interface state density and a flat band voltage is obtained.
US09947523B2 Method of transmitting ions through an aperture
A mass spectrometer includes: an ion source; an aperture; a flight region arranged between the ion source and aperture for separating ions according to their mass to charge ratio; and ion optics arranged and configured for causing ions to be reflected or deflected while they separate according to mass to charge ratio in the flight region and such that the ions are focussed to a geometrical focal point at the aperture so that the ions are transmitted through the aperture. The multi-reflecting or multi-deflecting ion optics provides a relatively long flight path for the ions, while naturally converging the ion beam to a focus. As this focus is arranged at the aperture, it enables the aperture to be made relatively small while still maintaining high ion transmission efficiency.
US09947519B2 Computational method and system for deducing sugar chains using tandem MSn spectrometry data
Based on the m/z of a precursor ion used in an MS2 analysis of a test sugar chain, a plurality of sugar-chain structure candidates are extracted from a sugar-chain database in which various sugar-chain structures are related to m/z (S2). Product ions that can be generated by cutting one sugar-chain bond are calculated for each sugar-chain structure candidate (S3). For each combination of two sugar-chain structure candidates, the product ions of one candidate are compared with those of the other to extract characteristic product ions for each sugar-chain structure candidate, and their m/z values are calculated (S4). Whether or not an MS2 spectrum of the test sugar chain has a peak located at m/z of any of the characteristic product ions is determined, and based on the determination result, the sugar-chain structure candidates are narrowed down (S5) and the obtained result is shown on a display unit (S6).
US09947518B2 Combined tandem mass spectrometry and ion mobility mass spectrometry
A method of analyzing ions is disclosed comprising performing an initial multi-dimensional survey scan comprising separating parent ions according to a first physico-chemical property and separating the parent ions according to a second physico-chemical property. At least one parent ion of interest from the initial multi-dimensional survey scan is determined, the at least one parent ion of interest having a first value or range of the first physico-chemical property and a second value or range of the second physico-chemical property. Then, during a subsequent single cycle of separation, the method further comprises separating parent ions according to the first physico-chemical property. If the parent ions have a value or range of the first physico-chemical property which corresponds with the first value or range, then the method further comprises selecting parent ions of interest having a value or range of the first physico-chemical property which corresponds with the first value or range and which also have a value or range of the second physico-chemical property which corresponds with the second value or range. If the parent ions have a value or range of the first physico-chemical property which does not correspond with the first value or range then the method further comprises separating the parent ions according to the first physico-chemical property and separating the parent ions according to the second physico-chemical property.
US09947517B1 Adjustable extended electrode for edge uniformity control
Embodiments described herein generally related to a substrate processing apparatus. In one embodiment, a process kit for a substrate processing chamber disclosed herein. The process kit includes a first ring having a top surface and a bottom surface, an adjustable tuning ring having a top surface and a bottom surface, and an actuating mechanism. The bottom surface is supported by a substrate support member. The bottom surface at least partially extends beneath a substrate supported by the substrate support member. The adjustable tuning ring is positioned beneath the first ring. The top surface of the adjustable tuning ring and the first ring define an adjustable gap. The actuating mechanism is interfaced with the bottom surface of the adjustable tuning ring. The actuating mechanism is configured to alter the adjustable gap defined between the bottom surface of the first ring and the top surface of the adjustable tuning ring.
US09947515B2 Microwave surface-wave plasma device
A processing system is disclosed, having a power transmission element with an interior cavity that propagates electromagnetic energy proximate to a continuous slit in the interior cavity. The continuous slit forms an opening between the interior cavity and a substrate processing chamber. The electromagnetic energy may generate an alternating charge in the continuous slit that enables the generation of an electric field that may propagate into the processing chamber. The electric field may interact with process gas in the processing chamber to generate plasma for treating the substrate. The interior cavity may be isolated from the process chamber by a dielectric component that covers the continuous slit. The power transmission element may be used to control plasma density within the process chamber, either by itself or in combination with other plasma sources.
US09947510B2 Method for supplying gas, and plasma processing apparatus
In the exemplary embodiment, a method for supplying a gas is provided. This method includes supplying a processing gas to each of a central gas inlet portion and a peripheral gas inlet portion through a first branch line and a second branch line; closing a valve at a downstream side in a gas line for an additional gas, and filling the additional gas in a tube between the valve and an upstream flow rate controller; opening the valve after filling the additional gas, and supplying a high frequency power to one of an upper electrode and a lower electrode from a high frequency power supply after opening the valve.
US09947507B2 Method for preparing cross-sections by ion beam milling
The disclosure provides a method for preparing a cross-section of a sample by milling with a focused ion beam. The cross-section is to be prepared at a pre-defined position. The method includes excavating a trench by milling in a first milling direction. The first milling direction leads away from the position of the cross-section to be prepared. The method also includes excavating the cross-section by enlarging the trench by milling in the reversed milling direction. The second milling direction leads towards the position of the cross-section to be prepared, whereupon the milling is completed at the position where the cross-section is to be cut. The desired largest milling depth is achieved at the completion of this milling step.
US09947503B2 Magnetic shielding of an X-ray emitter
An x-ray emitter includes a housing. In an embodiment, the housing includes a diamagnetic or paramagnetic housing material and a plurality of ferromagnetic particles. In an embodiment, the ferromagnetic particles are aligned substantially along closed paths. A medical device includes an embodiment of the x-ray emitter. A method is further for producing an embodiment of the x-ray emitter.
US09947497B2 Integrated connector having sense and switching conductors for a relay used in a battery module
Relays having internal connections on both sides of their switches may be used in conjunction with a connector that integrates both the normal relay switch control lines with the sensing conductors of a control module for a battery module of an energy storage device. In this manner, sensing conductors may be routed along with the switch control lines for the relay instead of separately as described above. This integration reduces the complexity and cost associated with the energy storage device, because it reduces the number of separately routed lines and also eliminates the external connections for at least some of the sensing conductors.
US09947494B2 Flip switch timer decorator switch clip
A clip member that attaches to the actuator of a flip switch timer for a toggle switch to allow the flip switch timer to actuate a decorator switch between on and off positions. The clip member may include a connector or fastener including a pair of arms having clips for engaging a slot on the actuator. A lever arm on the switch engages the raised end of a decorator switch when the actuator, and thus the clip member, are moved linearly within the flip switch timer.
US09947488B2 Electrical switch ganging system and method
A fastener is provided for ganging or joining two or more switch handles to one another. The fastener includes a head at one end and an elongated shank extending from the head. The shank includes a threaded portion adjacent the head that threadingly engages one of the switch handles. The shank extends longitudinally from the threaded portion through the threadingly engaged switch handle and through one or more additional switch handles to gang the switch handles to one another.
US09947484B2 Electrolyte solution and electrochemical device
An electrolyte solution intended for use in electrochemical devices which can achieve a high capacitance retention ratio even after long-term use at high voltage. The electrolyte solution of the present invention includes a mononitrile compound (I), at least one compound (II) selected from dinitrile compounds and trinitrile compounds, and a quaternary ammonium salt (III). The amount of the compound (II) in the electrolyte solution is 0.05 to 5% by mass.
US09947481B2 Lubricant-impregnated surfaces for electrochemical applications, and devices and systems using same
In certain embodiments, the invention relates to an electrochemical device having a liquid lubricant impregnated surface. At least a portion of the interior surface of the electrochemical device includes a portion that includes a plurality of solid features disposed therein. The plurality of solid features define a plurality of regions therebetween. A lubricant is disposed in the plurality of regions which retain the liquid lubricant in the plurality of regions during operation of the device. An electroactive phase comes in contact with at least the portion of the interior surface. The liquid lubricant impregnated surface introduces a slip at the surface when the electroactive phase flows along the surface. The electroactive phase may be a yield stress fluid.
US09947476B2 Multilayer ceramic capacitor, multilayer ceramic capacitor series including the same, and multilayer ceramic capacitor mount body including the same
A body of a multilayer ceramic capacitor includes an inner layer portion and first and second outer layer portions sandwiching the inner layer portion therebetween. The inner layer portion includes an area extending from a conductive layer positioned closest to a first main surface to a conductive layer positioned closest to a second main surface in the stacking direction. The height of the body is smaller than the width of the body. The height of the inner layer portion is smaller than the width of the inner layer portion. The first outer layer portion includes a dielectric layer positioned closest to the first main surface. The second outer layer portion includes a dielectric layer positioned closest to the second main surface, and is thicker than the first outer layer portion. The total height of the first and second outer layer portions is smaller than the height of the inner layer portion.
US09947475B2 Ceramic capacitor and method for manufacturing same
A ceramic capacitor includes first and second first internal electrodes respectively including first and second extended portions that respectively include a plurality of ceramic columns penetrating the first and the second extended portions, respectively, in a thickness direction. The first extended portion includes a first high ceramic-column density portion in which ceramic columns are provided at intervals of about 20 μm or less along the length direction of the extended portion. The second extended portion includes a second high ceramic-column density portion in which ceramic columns are provided at intervals of about 20 μm or less along the length direction of the extended portion.
US09947472B2 Multilayer capacitor and installation structure of multilayer capacitor
In a multilayer capacitor, both a dimension in a thickness direction of a first terminal electrode on the first end surface and a dimension in the thickness direction of a second terminal electrode on the second end surface are greater than a minimum distance in the thickness direction between a first effective portion of a first inner electrode and a second main surface and a minimum distance in the thickness direction between a second effective portion of a second inner electrode and the second main surface.
US09947467B2 Protected capacitor system and method
A protected capacitor system/method implementing enhanced transient over-voltage suppression is disclosed. The system/method incorporates one or more surge suppression devices (SSDs) proximally located and in parallel with a capacitor structure to produce an overall protected capacitor structure having enhanced reliability and simultaneous ability to resist transient overvoltage conditions. The SSDs are formed from series combinations of transient voltage surge suppressors (TVSs) (metal oxide varistor (MOV), diode for alternating current (DIAC), and/or silicon diode for alternating current (SIDAC)) and corresponding shunt diode rectifiers (SDRs) and placed in parallel across a capacitor structure to locally suppress voltage transients across the capacitor structure in excess of the voltage rating of the capacitor structure. The parallel shunting TVS/SDR pairs may be integrated into a printed circuit board (PCB) assembly that is externally attached to the capacitor structure or encapsulated in an enclosure incorporating the capacitor structure.
US09947458B2 Coil component
A coil component includes two or more coils configuring a common mode choke coil and functions as an inductor against a normal mode AC current. A coil component includes a pot-type core formed in a box-like shape, a flat plate core, coils, and a partition core formed of a magnetic substance. The coils are accommodated inside the pot-type core and form a common mode choke coil by making the central axes thereof substantially match each other. Further, each of end portions of the coils function as outer electrodes. The partition core is provided between the coils.
US09947451B1 Ignition coil
An ignition coil includes a low voltage terminal for connection with a battery and a high voltage terminal for connection with a spark plug. An assembly of windings interconnects the terminals. The ignition coil further includes a case containing the windings and the terminals. The case is configured for use with a cylinder head cover having a cylindrical bore with a key projecting radially inward of the bore. A cylindrical portion of the case has a central axis, a rotational locator surface, and an insertion guide groove configured to receive the key in the bore. A helical section of the groove is configured to receive the key when the case is in a first rotational orientation. The helical section is further configured for the rotational locator surface to move into abutment with the key upon rotation of the case from the first rotational orientation to a second rotational orientation.
US09947443B2 Chip resistor
A chip resistor includes a base member, a resistive element formed on the base member, a first inner electrode held in contact with a first end portion of the resistive element, a second inner electrode held in contact with a second end portion of the resistive element, a first reverse surface electrode reaching a first end portion of the base member, and a second reverse surface electrode reaching a second end portion of the base member. The length of the first and the second reverse surface electrodes is in a range of 2/10 to 3/10 of the length of the base member. Also, the length of the first and the second reverse surface electrodes is greater than the length of the first and the second inner electrodes.
US09947442B2 High-voltage bushing and high-voltage installation with the bushing
A high-voltage bushing has an internal conductor and an insulating body which surrounds the internal conductor along its longitudinal direction. The internal conductor is routed out of the insulating body at a head end of the high-voltage bushing. A fastening flange is arranged on the insulating body at an end opposite the head end. An outer housing encloses the internal conductor and the insulating body from the fastening flange up to and including the head end in a moisture-tight manner. A high-voltage installation has a high-voltage conductor which is routed through a housing wall of the high-voltage installation by way of the novel high-voltage bushing.
US09947440B2 Mounting cable and method for manufacturing mounting cable
A mounting cable includes: a coaxial cable including: a core wire made of a conductive material; an internal insulator covering an outer periphery of the core wire; a shield covering an outer periphery of the internal insulator; and a jacket covering an outer periphery of the shield with an insulator, the coaxial cable having one end portion on which the core wire, the internal insulator and the shield are exposed; a cable fixing unit that fixes one end portion of the exposed core wire and has a connection surface on which an end face of the core wire is exposed; and a conductor having one end electrically and mechanically connected to the exposed shield and having the other end fixed to the cable fixing unit. An end portion of the conductor is exposed on the connection surface of the cable fixing unit.
US09947438B2 Lightweight and flexible impact resistant power cable and process for producing it
The present disclosure relates to an impact resistant, multipolar power cable (10) comprising, a plurality of cores (1), each core (1) comprising at least one conductive element (3) and an electrical insulating layer (5) in a position radially external to the at least one conductive element (3). The cores (1) are stranded together so as to form an assembled element providing a plurality of interstitial zones (2). An expanded polymeric filler (6) fills the interstitial zones (2) between the plurality of cores (1). An expanded impact resistant layer (7) is in a position radially external to the expanded polymeric filler (6) and comprises a polymer that differs from the expanded polymeric filler (6).
US09947437B2 Metal sheathed cable designed on the basis of torque balance and design method thereof
A metal sheathed cable includes an optical unit and a control unit helically twisted together, a grounding wire unit distributed in the gaps between the optical unit and the control unit to form an inner layer cable core, a filler watertightly filled into gaps among the optical unit, the control unit and the grounding wire unit, and a taped covering arranged outside the inner layer cable core; a power unit and a filling core helically twisted around the inner layer cable core, the grounding wire unit distributed in the gap between the power unit and the filling core, the filler watertightly filled into gaps among the power unit, the grounding wire unit and the filling core, and the taped covering arranged outside the outer layer cable core; an inner protective layer wrapped outside the outer layer core, and a sheathing layer twisted outside the inner protective layer.
US09947435B2 Wire harness
A wire harness includes electric wires, and an electromagnetic wave suppression member that includes a restricting member and an annular magnetic core, the restricting member being provided to cover a periphery of the electric wires and including an inner wall portion more rigid than the electric wires, and the magnetic core being provided around the inner wall portion. The restricting member includes fixing portions formed to fix the electromagnetic wave suppression member to a fixing target.
US09947434B2 Tethers for airborne wind turbines using electrical conductor bundles
A tether may include a core, a hybrid layer surrounding the core, and a jacket surrounding the hybrid layer. The hybrid layer may include a plurality of strength members, and a plurality of electrical conductor bundles. Each electrical conductor bundle of the plurality of electrical bundles may include a compliant element, a plurality of electrical conducting elements surrounding the compliant element, and an insulating layer surrounding the plurality of electrical conducting elements.
US09947428B2 Atomic beam source
An atomic beam source includes a tubular cathode that includes an emission portion that includes an emission port through which an atomic beam can be emitted, a rod-shaped first anode disposed inside the cathode, and a rod-shaped second anode disposed inside the cathode and spaced from the first anode. At least one selected from the group consisting of a shape of the cathode, a shape of the first anode, a shape of the second anode, and a positional relationship between the cathode, the first anode, and the second anode is predetermined so that emission of sputter particles resulting from collision of cations, which have been generated by plasma between the first anode and the second anode, with at least one selected from the cathode, the first anode, and the second anode is reduced.
US09947426B2 High voltage supply for compact radiation generator
Disclosed is a radiation logging tool, comprising a tool housing; a compact generator that produces radiation; a power supply coupled to the compact generator; and control circuitry. Embodiments of the compact generator comprise a generator vacuum tube comprising a source generating charged particles, and a target onto which the charged particles are directed; and a high voltage supply comprising a high voltage multiplier ladder located laterally adjacent to the generator vacuum tube. The high voltage supply applies a high voltage between the source and the target to accelerate the charged particles to a predetermined energy level. The compact generator also includes an electrical coupling between an output of the high voltage supply and the target of the generator vacuum tube to accommodate the collocated positions of the generator vacuum tube and the high voltage power supply.
US09947424B2 Coating type radiation-shielding material and radiation-shielding elastomer material
An object of the invention is to provide a radiation-shielding material that has a high radiation-shielding capability and can be easily coated, molded and sheeted. Metals or the like having a radiation-shielding capability are blended with an elastomer precursor in a high concentration thereby providing a radiation-shielding material that has a higher radiation-shielding capability than ever before and can be easily coated, molded and sheeted in any desired configuration.
US09947423B2 Nanofuel internal engine
A nanofuel engine including an inventive nanofuel internal engine, whereby nuclear energy is released in the working fluid and directly converted into useful work, with the qualities of an economical advanced small modular gaseous pulsed thermal reactor. Scientific feasibility is established by studying the behavior of nuclear fuels in configurations designed to support a fission chain reaction. Nanofuel is defined as nuclear fuel suitable for use in an internal engine, comprised of six essential ingredients, and can be created from clean fuel or from the transuranic elements found in light-water reactor spent nuclear fuel in a proliferation resistant manner. Three essential ingredients ensure the nanofuel is inherently stable, due to a negative temperature coefficient of reactivity. Reciprocating and Wankel (rotary) internal engine configurations, which operate in an Otto cycle, are adapted to support a fission chain reaction. Dynamic engine cores experience a decrease in criticality as the engine piston or rotor moves away from the top dead center position. In this inherent safety feature, the increase in engine core volume decreases the nanofuel density and increases the neutron leakage. Technological feasibility is demonstrated by examining potential engineering limitations. The nanofuel internal engine can be operated in two modes: spark-ignition with an external neutron source such as a fusion neutron generator; and compression-ignition with an internal neutron source. The structural integrity can be maintained using standard internal combustion engine design and operation practices. The fuel system can be operated in a closed thermodynamic cycle, which allows for complete fuel utilization, continuous refueling, and easy fission product extraction. Nanofuel engine power plant configurations offer favorable economic, safety, and waste management attributes when compared to existing power generation technology. The initial (first-of-a-kind) overnight capital cost is approximately $400 per kilowatt-electric. Obvious safety features include an underground installation, autonomous operation, and an ultra-low nuclear material inventory.
US09947421B2 Nuclear reactor with liquid metal coolant
A nuclear reactor with a liquid metal coolant includes a housing having a separating shell disposed therein. In the annular space between the housing and the separating shell are disposed at least one steam generator and at least one pump. Inside the separating shell there is an active region, above which a heat collector is disposed. The heat collector is in communication with the vertically central portion of the steam generator in order to separate a stream of liquid metal coolant into ascending and descending flows. Alternatively, the heat collector is in communication with the upper portion of the steam generator in order to create a counter-flow heat exchange regime. Below the reactor head is an upper horizontal cold collector with an unfilled level of coolant, and below the steam generator is a lower accumulating collector in communication with the upper cold collector.
US09947420B2 Magnetic field plasma confinement for compact fusion power
In one embodiment, a fusion reactor includes a plurality of internal magnetic coils suspended within an enclosure, one or more center magnetic coils coaxial with the plurality of internal magnetic coils, a plurality of encapsulating magnetic coils coaxial with the internal magnetic coils, and a plurality of mirror magnetic coils coaxial with the internal magnetic coils. The encapsulating magnetic coils maintain a magnetic wall that prevents plasma within the enclosure from expanding.
US09947418B2 Boosted channel programming of memory
Methods of operating a memory include generating a programming pulse for a programming operation having a plurality of steps prior to a program voltage level of the programming pulse, and generating a subsequent programming pulse for the programming operation having the plurality of steps prior to a program voltage level of the subsequent programming pulse, wherein a particular step of the plurality of steps of the programming pulse has a different magnitude than a corresponding step of the plurality of steps of the subsequent programming pulse.
US09947416B2 Nonvolatile memory device, operating method thereof and memory system including the same
A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.
US09947414B2 Nonvolatile memory device and operating method thereof
An operating method of a nonvolatile memory device is provided. The nonvolatile memory device includes first and second page buffers, and first and second bit lines connected thereto, respectively. First and second latch nodes of the first page buffer are charged to have a voltage having a first level according to data stored in a first latch of the first page buffer. After the charging of the first latch node is started, a sensing node of the second page buffer is pre-charged. The sensing node is connected to the second bit line. Data stored in the first latch is dumped into a second latch of the first page buffer during the pre-charging of the sensing node of the second page buffer.
US09947413B2 Method of initializing and programming 3D non-volatile memory device
A method of initializing and programming a 3D non-volatile memory device includes applying a first program voltage to a selected string selection line coupled to a selected memory layer among the plurality of memory layers; verifying whether threshold voltages of a plurality of string selection transistors reach a target value to determine the plurality of string selection transistors as programmed string selection transistors or unprogrammed string selection transistors; programming memory cell transistors of one or more of memory strings coupled with the programmed string selection transistors to have a predetermined threshold voltage, by applying a second program voltage to a selected wordline among the plurality of wordlines; and program-inhibiting channel lines of the programmed string selection transistors using the programmed memory cell transistors as screening transistors and applying a third program voltage to the selected string selection line to selectively program the unprogrammed string selection transistors.
US09947408B2 Semiconductor memory device that applies same voltage to two adjacent word lines for access
A semiconductor memory device includes a block of memory cells including first, second, and third memory cells, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, a third word line electrically connected to a gate of the third memory cell, and a control circuit configured to access the block in one of at least first and second modes to perform an operation thereon. When the control circuit accesses the block in the first mode, the same voltage is applied to the first and second word lines throughout the operation, and when the control circuit accesses the block in the second mode, the same voltage is applied to the second and third word lines throughout the operation.
US09947407B2 Techniques for programming of select gates in NAND memory
In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.
US09947406B2 Dynamic tag compare circuits employing P-type field-effect transistor (PFET)-dominant evaluation circuits for reduced evaluation time, and related systems and methods
Dynamic tag compare circuits employing P-type Field-Effect Transistor (PFET)-dominant evaluation circuits for reduced evaluation time, and thus increased circuit performance, are provided. A dynamic tag compare circuit may be used or provided as part of searchable memory, such as a register file or content-addressable memory (CAM), as non-limiting examples. The dynamic tag compare circuit includes one or more PFET-dominant evaluation circuits comprised of one or more PFETs used as logic to perform a compare logic function. The PFET-dominant evaluation circuits are configured to receive and compare input search data to a tag(s) (e.g., addresses or data) contained in a searchable memory to determine if the input search data is contained in the memory. The PFET-dominant evaluation circuits are configured to control the voltage/value on a dynamic node in the dynamic tag compare circuit based on the evaluation of whether the received input search data is contained in the searchable memory.
US09947405B2 Memristive dot product engine with a nulling amplifier
A method of obtaining a dot product using a memristive dot product engine with a nulling amplifier includes applying a number of programming voltages to a number of row lines within a memristive crossbar array to change the resistance values of a corresponding number of memristors located at intersections between the row lines and a number of column lines. The method also includes applying a number of reference voltages to the number of the row lines and applying a number of operating voltages to the number of the row lines. The operating voltages represent a corresponding number of vector values. The method also includes determining an array output based on a reference output and an operating output collected from the number of column lines.
US09947400B2 Methods for enhanced state retention within a resistive change cell
A method for improving the stability of a resistive change cell is disclosed. The stability of a resistive change memory cell—that is, the tendency of the resistive change memory cell to retain its programmed resistive state—may, in certain applications, be compromised if the cell is programmed into an unstable or metastable state. In such applications, a programming method using bursts of sub-pulses within a pulse train is used to drive the resistive change cell material into a stable state during the programming operation, reducing resistance drift over time within the cell.
US09947397B2 Crosspoint array decoder
Example implementations disclosed herein can be used to decode memory elements in a crosspoint array. In one example implementation, crosspoint array decoder includes a number of field effect transistor decoder switches corresponding to specific lines in a crosspoint array and a sense amplifier coupled to at least some of the field effect transistor decoder switches and includes a set of inference field effect transistors matched to the field effect transistor decoder switches to infer a stimulus voltage applied to a memory element in a crosspoint array.
US09947395B2 Programming techniques for non-volatile memories with charge trapping layers
Techniques are presented for the programming of a non-volatile memory in which multi-state memory cells use a charge trapping layer. When writing data onto a word lines, different data states are written individually, while programming inhibiting the other states, thereby breaking down the write operation into a number of sub-operations, one for each state to be written. This allows for improved timing and decreased power consumption.
US09947393B2 Semiconductor integrated circuit device
A semiconductor integrated circuit device includes a control unit which causes a column selection circuit to separate bit line pairs from a common bit line pair and causes a sense amplifier circuit to amplify a potential difference between the common bit line pair precharged by a precharge circuit, in response to a unique ID generation instruction.
US09947388B2 Reduced swing bit-line apparatus and method
Described is an apparatus which comprises: a bit-line (BL) read port; a first local bit-line (LBL) coupled to the BL read port; a second LBL; and one or more clipper devices coupled to the first and second LBLs. The apparatus allows for low swing bit-line to be used for large signal memory arrays. The low swing operation enables reduction in switching dynamic capacitance. The apparatus also describes a split input NAND/NOR gate for bit-line keeper control which achieves lower VMIN, higher noise tolerance, and improved keeper aging mitigation. Described is also an apparatus for low swing write operation which can be enabled at high voltage without degrading the low voltage operation.
US09947387B2 Systems and methods for reducing standby power in floating body memory devices
Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.
US09947386B2 Thermal aware data placement and compute dispatch in a memory system
A method of managing thermal levels in a memory system may include determining an expected thermal level associated with each of a plurality of locations in a memory structure, and for each operation of a plurality of operations addressed to the memory structure, assigning the operation to a target location of the plurality of physical locations in the memory structure based on a thermal penalty associated with the operation and the expected thermal level associated with the target location.
US09947383B1 Spin hall write select for magneto-resistive random access memory
A magneto-resistance random access memory (MRAM) cell includes a transistor, a wire and a magnetic tunnel junction (MTJ). The MTJ includes a fixed layer of fixed magnetic polarity electrically connected with the transistor, a free layer of variable magnetic polarity electrically connected with the wire and an insulator between the fixed and free layers. First current passed through the wire destabilizes the variable magnetic polarity of the free layer. Second current passed through the transistor in one of two directions during first current passage through the wire directs the variable magnetic polarity of the free layer toward a parallel or anti-parallel condition with respect to the fixed magnetic polarity of the fixed layer. A ceasing of the first current prior to a ceasing of the second current sets the variable magnetic polarity of the free layer in the parallel or anti-parallel condition.
US09947382B2 Electrically gated three-terminal circuits and devices based on spin hall torque effects in magnetic nanostructures apparatus, methods and applications
Three-terminal magnetic circuits and devices based on the spin-transfer torque (STT) effect via a combination of injection of spin-polarized electrons or charged particles by using a charge current in a spin Hall effect metal layer coupled to a free magnetic layer and application of a gate voltage to the free magnetic layer to manipulate the magnetization of the free magnetic layer for various applications, including nonvolatile memory functions, logic functions and others. The charge current is applied to the spin Hall effect metal layer via first and second electrical terminals and the gate voltage is applied between a third electrical terminal and either of the first and second electrical terminals. The spin Hall effect metal layer can be adjacent to the free magnetic layer or in direct contact with the free magnetic layer to allow a spin-polarized current generated via a spin Hall effect under the charge current to enter the free magnetic layer. The disclosed three-terminal magnetic circuits can also be applied to signal oscillator circuits and other applications.
US09947379B1 Device and methods for writing and erasing analog information in small memory units via voltage pulses
Devices and methods for non-volatile analog data storage are described herein. In an exemplary embodiment, an analog memory device comprises a potential-carrier source layer, a barrier layer deposited on the source layer, and at least two storage layers deposited on the barrier layer. The memory device can be prepared to write and read data via application of a biasing voltage between the source layer and the storage layers, wherein the biasing voltage causes potential-carriers to migrate into the storage layers. After initialization, data can be written to the memory device by application of a voltage pulse between two storage layers that causes potential-carriers to migrate from one storage layer to another. A difference in concentration of potential carriers caused by migration of potential-carriers between the storage layers results in a voltage that can be measured in order to read the written data.
US09947378B2 Semiconductor memory device, a memory module including the same, and a memory system including the same
A method of operating a memory controller includes: receiving a data signal from a memory device, wherein the data signal has an output high level voltage (VOH); determining a reference voltage according to the VOH; and comparing the data signal with the reference voltage to determine a received data value, wherein the VOH is proportional to a power supply voltage (VDDQ).
US09947377B2 Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses
Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses are disclosed. In one aspect, a first port within a DRAM system is coupled to a second port via a loopback connection. A signal is sent to the first port from a System-on-Chip (SoC), and passed to the second port through the loopback connection. The signal is then returned to the SoC, where it may be examined by a closed-loop engine of the SoC. A result corresponding to a hardware parameter may be recorded, and the process may be repeated until an optimal result for the hardware parameter is achieved at the closed-loop engine. By using a port-to-port loopback configuration, the DRAM system parameters regarding timing, power, and other parameters associated with the DRAM system may be trained more quickly and with lower boot memory usage.
US09947376B2 Vertical bit vector shift in memory
Examples of the present disclosure provide apparatuses and methods for vertical bit vector shift in a memory. An example method comprises storing a vertical bit vector of data in a memory array, wherein the vertical bit vector is stored in memory cells coupled to a sense line and a plurality of access lines and the vertical bit vector is separated by at least one sense line from a neighboring vertical bit vector; and performing, using sensing circuitry, a vertical bit vector shift of a number of elements of the vertical bit vector.
US09947365B2 Method, system and computer program product for editing movies in distributed scalable media environment
A movie editor converts a received movie into a proxy format, and creates a texture strip representing the frames of the movie. An editor can use the texture strip to edit the movie, rather than editing the movie directly. Deep tags and/or special effects can be defined for the texture strip using a graphical interface. The graphical interface enables movies to be combined into a playback product according to a control structure graphically presented in the graphical interface.
US09947364B2 Enhancing audio using multiple recording devices
In general, the subject matter described in this disclosure can be embodied in methods, systems, and program products for identifying that a first audio stream includes first, second, and third sources of audio. A computing system identifies that a second audio stream includes the first, second, and third sources of audio. The computing system determines that the first and second sources of audio are part of a first conversation. The computing system generates a third audio stream that combines the first source of audio from the first audio stream, the first source of audio from the second audio stream, the second source of audio from the first audio stream, and the second source of audio from the second audio stream, and diminishes the third source of audio from the first audio stream, and the third source of audio from the second audio stream.
US09947358B1 Laser diode unit with enhanced thermal conduction to slider
An apparatus comprises a slider having a trailing edge and a leading edge. A laser diode unit comprises a submount and a laser diode mounted to the submount. The submount includes a mounting surface affixed to a first surface of the slider at the trailing edge such that a first surface of the submount faces toward the leading edge of the slider. A thermally conductive material covers the first surface of the submount and at least a portion of the first surface of the slider. The thermally conductive material serves as a thermal conduction pathway between the submount and the slider.
US09947357B2 Read/write head with integrated switch network
A read/write head has a set of components that at least include: at least one clearance actuator; at least one read transducer configured to read from a magnetic recording medium; and at least one write transducer configured to write to the magnetic recording medium. A switch network is coupled to the set of components and configured to, in response to a control signal, couple a selected sub-combination of the components to a common set of signal lines. The coupling of the selected sub-combination facilitates operation in a selected mode of the read/write head.
US09947354B1 Utilization of multiple writer modules for simultaneously writing two times the number of data tracks in a compact form factor
In one general embodiment, an apparatus includes a first outer module having an array of writers, a second outer module having an array of writers, an inner module positioned between the outer modules, and a first actuator for shifting the first outer module. The shifting is relative to the inner module, in a cross-track direction by about one half of a center-to-center pitch of the writers of the first outer module. The inner module has an array of readers.
US09947352B1 Magnetic disk apparatus
According to one embodiment, a VCM resistance estimation unit estimates a VCM resistance in a voice coil motor based on an acceleration and a velocity of a magnetic head with a VCM voltage saturated, and an equivalent current force constant estimation unit estimates an equivalent current force constant of the voice coil motor based on the acceleration and the velocity of the magnetic head with the VCM voltage saturated.
US09947350B1 Method of detecting back electromotive force in electro-mechanical actuators, corresponding device and apparatus
A driver device coupled to a winding of an electro-mechanical actuator includes: a power stage driving the winding in a discontinuous mode by alternating conduction on-phases to off-phases, and a sensor circuit sensing a voltage across the winding in an off-phase, wherein, during such an off-phase the voltage across the winding includes a residual voltage which decays to zero. The power stage drives the winding from an on-phase to an off-phase by applying to the winding a reverse current pulse to invert the direction of flow of the current through the winding and produce an oscillation of the residual voltage, whereby the residual voltage includes a zero-crossing point after the current through the winding is exhausted. The sensor circuit senses the voltage across the winding at this zero-crossing point, whereby the voltage sensed across the winding at the zero-crossing point is indicative of the back electromotive force of the winding.
US09947348B1 Tunnel magnetoresistive sensor having leads supporting three-dimensional current flow
An apparatus, according to one embodiment, includes: a transducer structure having: a lower shield, an upper shield above the lower shield, a current-perpendicular-to-plane sensor between the upper and lower shields, an electrical lead layer between the sensor and one of the shields, and a spacer layer between the electrical lead layer and the one of the shields. The upper and lower shields provide magnetic shielding. The electrical lead layer is in electrical communication with the sensor. A conductivity of the electrical lead layer is higher than a conductivity of the spacer layer. A width of the electrical lead layer in a cross-track direction is greater than the width of a free layer of the sensor.
US09947344B2 Stabilizing layered structure for magnetic tape heads
An apparatus according to one embodiment includes an array of magnetic read transducers each having a current-perpendicular-to-plane sensor, magnetic shields on opposite sides of the sensor in an intended direction of media travel thereacross, and a stabilizing layered structure between at least one of the magnetic shields and the sensor. The stabilizing layered structure has an antiferromagnetic layer, a first ferromagnetic layer adjacent the antiferromagnetic layer, and a second ferromagnetic layer. The antiferromagnetic layer pins a magnetization direction in the first ferromagnetic layer along an antiferromagnetic polarized direction of the antiferromagnetic layer. An antiparallel coupling layer is positioned between the ferromagnetic layers such that a magnetization direction in the second ferromagnetic layer is opposite the magnetization direction in the first ferromagnetic layer.
US09947342B2 Method and apparatus for speech behavior visualization and gamification
The disclosed system and methods provide real-time information about how agents and customers sound as they are speaking, allowing a supervisor to continuously monitor how agents are doing. The system allows agents to visualize their own speech behavior performance during and after a conversation while viewing important comparative information about prior conversations, and gamifies conversations in real-time by providing visual comparison between the live conversations and various target metrics. The visualization in-turn enhances agent interactive skills such as active listening and mirroring, as well as decision-making skills based on observations of customer engagement and distress levels.
US09947337B1 Echo cancellation system and method with reduced residual echo
An echo canceller includes a fast Fourier transform (FFT) unit to provide frequency domain representation (FD) of an input. A multiband adaptive filter receives the FD of the input and provides an FD filter output, the adaptive filter is a finite input response (FIR) digital filter. Another FFT unit provides an FD of a microphone signal, and a summer adds the FD filter output to the FD of the microphone signal to provide echo-canceller FD output. A feedback subsystem uses the echo-canceller FD output to adjust filter coefficients of at least a first, a second, and a third frequency band of the multiband adaptive filter to minimize uncancelled output in the echo-canceller FD output. The feedback subsystem adjusts the filter coefficients of the second frequency band of the adaptive filter according to uncancelled output in the first, second, and third frequency bands of the echo-canceller FD output.
US09947336B2 Acoustic echo mitigation apparatus and method, audio processing apparatus and voice communication terminal
The present application provides an acoustic echo mitigation apparatus and method, an audio processing apparatus and a voice communication terminal. According to an embodiment, an acoustic echo mitigation apparatus is provided, including: an acoustic echo canceller for cancelling estimated acoustic echo from a microphone signal and outputting an error signal; a residual echo estimator for estimating residual echo power; and an acoustic echo suppressor for further suppressing residual echo and noise in the error signal based on the residual echo power and noise power. Here, the residual echo estimator is configured to be continuously adaptive to power change in the error signal. According to the embodiments of the present application, the acoustic echo mitigation apparatus and method can, at least, be well adaptive to the change of power of the error signal after the AEC processing, such as that caused by change of double-talk status, echo path properties, noise level and etc.
US09947334B2 Enhanced conversational communications in shared acoustic space
A multichannel acoustic system (MAS) comprises an arrangement of microphones and loudspeakers and a multichannel acoustic processor (MAP) to together enhance conversational speech between two or more persons in a shared acoustic space such as an automobile. The enhancements are achieved by receiving sound signals substantially originating from relatively near sound sources; filtering the sound signals to cancel at least one echo signal detected for at least one microphone from among the plurality of microphones; filtering the sound signals received by the plurality of microphones to cancel at least one feedback signal detected for at least one microphone from among the plurality of microphones; and reproducing the filtered sound signals for each microphone from among the plurality of microphones on a subset of loudspeakers corresponding that are relatively far from the source microphone.
US09947333B1 Voice interaction architecture with intelligent background noise cancellation
A voice interaction architecture has a hands-free, electronic voice controlled assistant that permits users to verbally request information from cloud services. The voice controlled assistant may be positioned in a room to receive voice commands from the user. The voice controlled assistant may also pick up background sources of speech, music, or other noise, such as from a television or stereo system, which may adversely impact the user's intended vocal input to the assistant. The assistant transmits the aggregated audio data (user command and background noise) over a network to the cloud services, which implements noise cancellation functionality to remove the background noise while isolating and preserving the user's command. Once isolated, the cloud serves can process and interpret the user input to perform some function, and return the response over the network to the voice controlled assistant for audible output to the user.
US09947332B2 Method and apparatus for automatic audio alignment in a hybrid radio system
A method of processing a digital radio broadcast signal includes: (a) determining a plurality of current correlation sample values representative of a time delay between samples in an analog audio sample stream and samples in a digital audio sample stream; (b) determining a current inversion status; (c) updating a delay history and an inversion status history; (d) checking the current correlation sample values for consistency with a first confidence threshold; (e) if consistency is found in step (d), determining if each of a first plurality of values in the delay history is consistent within a predetermined range of the current correlation sample values; (f) if consistency is found in step (e), determining if a value in the inversion status history is consistent with the current inversion status; and (g) if the consistency is found in step (f), allowing blending of an output to the digital audio sample stream.
US09947330B2 Context-based entropy coding of sample values of a spectral envelope
An improved concept for coding sample values of a spectral envelope is obtained by combining spectrotemporal prediction on the one hand and context-based entropy coding the residuals, on the other hand, while particularly determining the context for a current sample value dependent on a measure of a deviation between a pair of already coded/decoded sample values of the spectral envelope in a spectrotemporal neighborhood of the current sample value. The combination of the spectrotemporal prediction on the one hand and the context-based entropy coding of the prediction residuals with selecting the context depending on the deviation measure on the other hand harmonizes with the nature of spectral envelopes.
US09947329B2 Apparatus and method for encoding or decoding an audio signal using a transient-location dependent overlap
An apparatus for encoding an audio or image signal, includes: a controllable windower for windowing the audio or image signal to provide the sequence of blocks of windowed samples; a converter for converting the sequence of blocks of windowed samples into a spectral representation including a sequence of frames of spectral values; a transient location detector for identifying a location of a transient within a transient look-ahead region of a frame; and a controller for controlling the controllable windower to apply a specific window having a specified overlap length to the audio or image signal in response to an identified location of the transient, wherein the controller is configured to select the specific window from a group of at least three windows, wherein the specific window is selected based on the transient location.
US09947325B2 Decoder, encoder and method for informed loudness estimation employing by-pass audio object signals in object-based audio coding systems
A decoder for generating an audio output signal having one or more audio output channels is provided, having a receiving interface for receiving an audio input signal having a plurality of audio object signals, for receiving loudness information on the audio object signals, and for receiving rendering information indicating whether one or more of the audio object signals shall be amplified or attenuated, further having a signal processor for generating the one or more audio output channels of the audio output signal, configured to determine a loudness compensation value depending on the loudness information and depending on the rendering information, and configured to generate the one or more audio output channels of the audio output signal from the audio input signal depending on the rendering information and depending on the loudness compensation value. One or more by-pass audio object signals are employed for generating the audio output signal. Moreover, an encoder is provided.
US09947324B2 Speaker identification method and speaker identification device
A first similarity degree processor calculates first similarity degrees between a feature value in voice signal of each of first speakers and each feature value in a plurality of unspecified speaker models of a plurality of unspecified speakers. The processor specifies a plurality of the unspecified speaker models for which the first similarity degrees are equal to or greater than a prescribed value. The processor also associates and stores each of the first speakers and the specified unspecified speaker models. Additionally, the processor calculates, for each of the first speakers, a plurality of second similarity degrees between a feature value in a voice signal of a second speaker and each feature values in the unspecified speaker models associated with the first speakers and stored in a second speaker model storage. The processor further specifies the second speaker based on the second similarity degrees.
US09947323B2 Synthetic oversampling to enhance speaker identification or verification
An apparatus for oversampling audio signals is described herein. The apparatus includes one or more microphones to receive audio signals and an extractor to extract a set of feature points from the audio signals. The apparatus also includes a processing unit to determine a distance between each pair of feature points and an oversampling unit to generate a plurality of new feature points based the distance between each pair of feature points.
US09947322B2 Systems and methods for automated evaluation of human speech
Systems and methods for evaluating human speech. Implementations may include: a microphone coupled with a computing device comprising a microprocessor, a memory, and a display operatively coupled together. The microphone may be configured to receive an audible unconstrained speech utterance from a user whose proficiency in a language is being tested and provide a corresponding audio signal to the computing device. The microprocessor and memory may receive the audio signal and process the audio signal by recognizing a plurality of phones and a plurality of pauses and calculate a plurality of suprasegmental parameters using the plurality of pauses and the plurality of phones. The microprocessor and memory may use the plurality of suprasegmental parameters to calculate a language proficiency rating for the user and display the language proficiency rating of the user on the display associated with the computing device.
US09947321B1 Real-time interactive voice recognition and response over the internet
Methods and systems for handling speech recognition processing in effectively real-time, via the Internet, in order that users do not experience noticeable delays from the start until they receive responsive feedback. A user uses a client to access the Internet and a server supporting speech recognition processing. The user inputs speech to the client, which transmits the user speech to the server in approximate real-time. The server evaluates the user speech, and provides responsive feedback to the client, again, in approximate real-time, with minimum latency delays. The client upon receiving responsive feedback from the server, displays, or otherwise provides, the feedback to the user.
US09947320B2 Script compliance in spoken documents based on number of words between key terms
A method, computerized apparatus and computer program product for determining script compliance in interactions, the method comprising: receiving one or more indexed audio interaction; receiving a text representing a script; automatically extracting two or more key terms from the script; automatically generating a query representing the script, comprising: receiving one or more constraint associated with the at least two key terms; and determining spotted key terms of the key terms that appear in the indexed audio interactions; determining complied constraints based on a number of words difference between two key terms of the at least two key terms; and determining a relevance score for each of the indexed audio interactions, based on the spotted key terms and the complied constraints.
US09947318B2 System and method for processing an audio signal captured from a microphone
A system and method for processing an audio signal captured from a microphone may reproduce a known audio signal with an audio transducer into an acoustic space. The known audio signal may include content from one or more audio sources. A microphone audio signal may be captured from the acoustic space where the microphone audio signal comprises the known audio signal and one or more unknown audio signals. Processing control information may be accessed. The known audio signal may be reduced in the microphone audio signal responsive to the processing control information where the processing control information indicates one or more characteristics of a downstream audio processor that processes the microphone audio signal.
US09947309B2 Sonar transducer support assembly systems and methods
Techniques are disclosed for systems and methods for providing accurate and reliable compact sonar systems for mobile structures. In one embodiment, a sonar system includes a mounting bracket, a transducer support arm, and a pivoting mechanism pivotably coupling the transducer support arm to the mounting bracket such that, for forces acting on the transducer support arm that are less than a preselected kick-up level, the pivoting mechanism holds the transducer support arm against such forces and at a user selectable first angular position relative to the mounting bracket, and for forces acting on the transducer support arm that are equal to or greater than the preselected kick-up level, allows the transducer support arm to be moved by those forces to a second angular position relative to the mounting bracket.
US09947305B2 Bi-directional music synchronization using haptic devices
Systems and methods may provide for capturing one or more inbound wireless transmissions and identifying a remote user movement based on at least one of the one or more inbound wireless transmissions. Additionally, a local haptic output may be generated, by an actuator, based on the remote user movement. In one example, the actuator is a piezoelectric actuator.
US09947303B1 Adapter device for attaching a strap to a musical instrument provided with a strap button
An adapter device is disclosed for removably securing a carrying strap to a guitar or other musical instrument provided with a strap mounting button. The adapter device includes a housing defining a cavity for receipt of a clamp member movably mounted to the housing. The housing has a strap stud and a threaded nut for securing the housing to the carrying musical instrument. The clamp member has an elongate slot for receipt of a shaft of the mounting button of the musical instrument. The clamp member further includes an enlarged cavity for receipt of an enlarged circular head of the mounting button to prevent the mounting button from pulling out of the slot in the clamp member. A latch member is movably mounted to the housing and movable from an unlocking position to a locking position covering the clamp member and securing the clamp member within the cavity of the housing. tab is provided on the latch member to secure the latch member in the locking position.
US09947301B2 Piano musical notation
A musical notation for piano music includes a top line including right finger numbering denoting finger positions of fingers of the right hand on keys of a piano and a bottom line including left finger numbering denoting finger positions of fingers of the left hand on keys of the piano. Each of the right and left finger numbering includes the numbers 1, 2, 3, 4, and 5 that correspond to the thumb, the pointer finger, the middle finger, the right finger, and the pinky finger, respectively. Each of a right hand position change and a left hand position change is denoted by a symbol. A chord is denoted by stacked finger numbering.
US09947297B2 Method and apparatus for controlling a display
In a method of enhancing the appearance of a digital image on an electronic display, Ambient Light Sensor (ALS) and Screen Brightness (SB) inputs are combined with a calibration input 12 to generate a first strength parameter 22, including an alpha component that is dependent only upon the properties of the display. Then a further, content-based input 24 is also combined to generate a second strength parameter 26, including a beta component that is dependent only upon a content type, or a content quality, or both.
US09947295B2 Method of driving a display panel and a display apparatus for performing the same
A method of driving a display device including a display panel is provided. The display panel includes a plurality of gate lines. The gate lines are divided into a plurality of gate line groups. The method includes applying different gate delay values to each of the gate line groups to generate gate signals and outputting the gate signals to the gate lines. A first gate delay value is applied to at least one of the gate lines during a first frame and a second gate delay value different from the first delay value is applied to the at least one of the gate lines during a second frame.
US09947294B2 Power advantaged image data control
For power-advantaged image data control, a method, system, and apparatus are disclosed. The method includes identifying, by use of a processor, a power source state, determining whether display data includes a power-adverse image based, at least in part, on the power source state, and replacing the power-adverse image with a power-advantaged image in response to the display data including the power-adverse image. In some embodiments, the method includes converting the power-adverse image into the power-advantaged image. In some embodiments, the method includes notifying a user, in response to displaying the power-advantaged image, that the power-advantaged image is displayed in place of the power-adverse image, and providing the user a control to display the power-adverse image in place of the power-advantaged image.
US09947292B2 Image processing method and device
An image processing method and device are provided. The method includes: choosing content-associated sub pixels in an image to be processed; obtaining an initial color level value of each of the content-associated sub pixels in the image to be processed; adding to least one digit to an end of the initial color level value and assigning a preset value to each added digit so as to obtain a processed color level value; and replacing the initial color level value with the processed color level value.
US09947289B2 User interface apparatus and user interface method
A user interface apparatus and a method of improving user interface are provided. The user interface apparatus may detect a change in an incident light and may control a display to represent the detected change in the light to be overlaid on image content. Provided is a user interface apparatus including: a display configured to display image content; a detector configured to detect a change in an incident light; and a controller configured to control the display to overlay the detected change in the light on the image content.
US09947283B2 Display apparatus with testing functions and driving circuit and driving method thereof
The present invention provides a display apparatus, including: a display panel circuit which includes a panel load line and performs a scanning display operation; and a panel driving circuit. The panel driving circuit determines at least a test phase and a scanning display phase according to a display control signal generated by a timing control circuit, wherein the test phase is a partial time period when the panel driving circuit does not perform the scanning display operation. The panel driving circuit generates a test driving signal on the panel load line, and detects an electronic characteristic of the display panel circuit so as to determine a failure item thereof during the test phase according to a pre-determined test instruction. The panel driving circuit generates a display driving signal on the panel load line for the scanning display operation according to the display control signal during the scanning display phase.
US09947281B2 Shift register unit, gate drive device and display device
The present disclosure provides a shift register unit including a pull-up module, an input module, a pull-down control module, a pull-down module, a reset discharging module, a voltage dividing module, a holding module, and a far end pull-down module. The shift register unit is designed in a split manner in order to perform pull-down compensation to the output signal at the far end, saving the low voltage signal at the far end, thereby saving the space and facilitating the design. The present disclosure further provides a gate driving device and a display device using the shift register unit.
US09947278B2 Display method and device and computer-readable medium
A display method, device and a computer-readable medium are provided. The method includes: detecting whether there is any change in a displayed content for the display; in response to detecting that the displayed content for the display does not change, controlling the display to alternately update display data corresponding to a first portion and a second portion of display units in each row when the display unit comprises m rows of pixels; and in response to detecting that the displayed content for the display does not change, controlling the display to alternately update display data corresponding to a third portion and a fourth portion of display units in each column when the display unit comprises n columns of pixels. Herein m and n are positive integers. Thus, screen flicker caused by reduction of refresh frequency of a display while the display content does not change can be avoided.
US09947277B2 Devices and methods for operating a timing controller of a display
Methods and devices for reducing the power consumption of a frame buffer and timing controller of an electronic display are provided. By way of example, a method of operating an electronic display includes receiving image data from a processor of the electronic display, storing the image data to a buffer of the electronic display, reading the image data from the buffer to supply the image data to a column driver of the electronic display, determining whether an amount of image data stored in buffer is less than a threshold, and switching from reading the image data from the buffer to reading the image data directly from the processor when the amount of image data stored in buffer is less than the threshold.
US09947276B2 Display device, user terminal, and method for adjusting display device
A liquid crystal display device (1) includes an adjustment setting section (11), a color component adjusting section (14), and a background color setting section (12). In a case where the adjustment setting section (11) carries out color component adjustment, (i) the background color setting section (12) carries out a second process of setting a background color and (ii) the color component adjusting section (14) carries out a first process of converting a grayscale level of a picture element. In a case where the adjustment setting section (11) does not carry out the color component adjustment, (i) the background color setting section (12) does not carry out the second process and (ii) the color component adjusting section (14) does not carry out the first process.
US09947271B2 Threshold voltage detection circuit for OLED display device
A threshold voltage detection circuit for OLED display device includes a multiplexer connected between a detection IC and each of multiple sub-pixel driver circuits of a pixel driver unit. A second DC signal having first and second levels with the first level smaller than the detection control signal and the second level larger than the detection control signal is fed to each of the sub-pixel driver circuits, such that during detection of threshold of a driver TFT, the second DC signal is switched to the second level and during detection of threshold of an OLED, the second DC signal is switched to the first level and a data signal is set at the same level as the detection control signal to achieve detection of the threshold voltages of the OLED and driver TFT of each sub-pixel driver circuit.
US09947268B2 Display device and color conversion method
The display device includes an image display unit including a plurality of pixels each including first to third sub-pixels and a fourth sub-pixel for displaying an additional color component according to an amount of lighting of a self-emitting element; a conversion processing unit that receives a first input signal including first color information for display at a predetermined pixel, where the first input signal is obtained based on an input video signal, the conversion processing unit being configured to outputs a second input signal including second color information with a saturation reduced by an amount of saturation attenuation defined such that saturation variation falls within a predetermined range according to the first color information; and a fourth sub-pixel signal processing unit that outputs, to the image display unit, a third input signal including third color information with red, green, blue components and the additional color component that are converted based on the second color information.
US09947266B2 Drive circuit, display device and driving method
A retention unit which retains input data, and a light emission control unit which compensates a value of a drive current that flows to a light emission element based on the input data which is retained in the retention unit, are provided in each pixel unit of a display device. While the light emission control unit displays input data of an image of an Nth frame during a light emission period TL (N) by driving the light emission element, input data of an image of an (N+1)th frame is written to the retention unit which becomes a pair together with the light emission control unit, as processing in a write processing period TS (N+1) of the (N+1)th frame.
US09947262B2 Display on a stretchable substrate
A display comprises a plurality of autonomous pixels on a stretchable substrate. Each autonomous pixel comprises a display element and a control element arranged to sense an external stimulus and to generate, entirely within the autonomous pixel, a control signal to drive the display element based, at least in part, on a magnitude of the sensed external stimulus. The stretchable substrate comprises a plurality of less elastic regions separated by stretchable areas, where the less elastic regions are less stretchable than the surrounding stretchable areas and each control element of an autonomous pixel is located in or on a less elastic region of the stretchable substrate.
US09947261B2 Electro-optical module, power supply substrate, wiring substrate, and electronic apparatus
This invention provides an electro-optical module with reduced noise in driving voltage. The invention can include a power supply substrate that is arranged separately from the flexible substrate having a driver, so that the noise of the driving voltage supplied from the power supply substrate is reduced.
US09947260B2 AMOLED display device with demultiplexer comprising first to third switches turning on in rotation during frame image
A demultiplexer and an AMOLED display device are disclosed. The present disclosure relates to the technical field of display, whereby the technical problem of color distortion of image in the prior art can be solved. The demultiplexer comprises a first switch, a second switch, and a third switch used for charging a first sub pixel, a second sub pixel, and a third sub pixel of a pixel unit respectively, wherein the first switch, the second switch, and the third switch are turned on in rotation; and wherein for the pixel unit, in three frame images, the first switch is turned on first in one of said three frame images, the second switch is turned on first in another one of said three frame images, and the third switch is turned on first in a remaining one of said three frame images. The demultiplexer of the present disclosure can be used in small sized AMOLED display device.
US09947257B2 Pixel layout and display with varying area and/or luminance capability of same type sub-pixels in different composite pixels
A color display includes multiple composite pixels, each composite pixel including sub-pixels of more than one color type. Sub-pixels of at least one of the color types are provided with differing luminance capability in different composite pixels. Each composite pixel may include red, green and blue sub-pixels having different luminance capability in different composite pixels. The differing luminance capability may be achieved by providing sub-pixels of at least one of the color types of differing relative area. An image data processing unit (IDPU) receives input image data of a standard format, and modifies the input image data into output image data for display to account for a discrepancy between the luminance capability based on the differing luminance capability or differing size of each sub-pixel, and a luminance capability as expected based on the input image data. The IDPU then outputs the output image data to control the composite pixels.
US09947256B2 Integrated circuit device, electronic apparatus, and control method for electrooptic panel
An integrated circuit device includes: a timing information storage section that stores phase length information in correspondence with an index number; a waveform information storage section that stores waveform information related to a plurality of drive waveforms used in response to at least one display state; a timing control section that reads an index number included for each phase in the waveform information, reads phase length information corresponding to the index number from the timing information storage section, and sequentially generates a selection signal during a drive voltage application period corresponding to a plurality of phases; and a drive waveform selection section that selects a waveform value representing a drive voltage, out of a plurality of units of waveform information stored in the waveform information storage section, in accordance with the selection signal.
US09947255B2 Electronic device display with monitoring circuitry
An electronic device may have a flexible display such as an organic light-emitting diode display. A strain sensing resistor may be formed on a bent tail portion of the flexible display to gather strain measurements. Resistance measurement circuitry in a display driver integrated circuit may make resistance measurements on the strain sensing resistor and a temperature compensation resistor to measure strain. A crack detection line may be formed from an elongated pair of traces that are coupled at their ends to form a loop. The crack detection line may run along a peripheral edge of the flexible display. Crack detection circuitry may monitor the resistance of the crack detection line to detect cracks. The crack detection circuitry may include switches that adjust the length of the crack detection line and thereby allow resistances to be measured for different segments of the line.
US09947254B2 Liquid crystal display panel
The present invention provides a liquid crystal display panel. The array test circuit (200) comprises a test control unit including a N type thin film transistor and a P type thin film transistor, wherein one thin film transistor is employed to be the output thin film transistor, and the other thin film transistor is employed to be the voltage stabilization thin film transistor. When the liquid crystal display panel is in the normal display state, the test control signal (ATEN) controls the output thin film transistor to be deactivated and controls the voltage stabilization thin film transistor to be activated so that the voltage difference of the gate and the source of the output thin film transistor is zero. Thus, the leakages on the data lines in the active display area (100) are consistent.
US09947253B2 Display device and method of inspecting the same
There are provided a display device capable of detecting a defect of a scan driver. The display device includes pixels positioned in regions demarcated by scan lines and data lines, a scan driver including a plurality of stages connected to the scan lines, an inspection unit connected to the stages to detect whether the stages are defective, and including first transistors turned on when a control signal is supplied, and a timing controller supplying the control signal, wherein the timing controller detects a position of a defective stage by reducing a period during which the control signal is supplied.
US09947252B2 Array substrate and detecting method therefore, display panel, and display device for improved detection rate and accuracy of an array test
The present invention provides an array substrate and a detecting method therefor, a display panel and a display device. The array substrate comprises a plurality of data lines, a plurality of short circuit rings respectively provided at ends of the plurality of data lines, and a common wire connecting the plurality of short circuit rings in series, wherein, a switch unit is provided between the end of each data line and the corresponding short circuit ring, and the switch unit is configured to disconnect the data line with the corresponding short circuit ring in a testing stage. The present invention can improve the detection rate and accuracy rate in an array test.
US09947250B2 Stanchion capable of providing prompted information
A stanchion capable of providing prompted information comprises a post and a prompt device disposed in the post. The prompt device senses the queuing state and outputs the prompted information corresponding to the queuing state. Hence, the stanchion offers information favorable for the queue such as waiting time and other helpful functions available for being applied to prompt people in the queue as well in addition to partitioning the moving line of the queue.
US09947249B1 Segmented sign frame
A sign frame incorporates a plurality of segments each selected from straight, curved or hinged segments that are interchangeable and are telescopically connected to adjacent segments. The selection of curved and straight segments may provide for customization of the sign size, while selection of hinge segments can be integrated with other segments to provide a hinge support for the sign and sign frame and for convenient attachment to a pole or post.
US09947248B2 Lighting assembly with multiple lighting units
A lighting assembly includes an assembly body. A first lighting unit is attached to the assembly body. The first lighting unit includes a number of light emitting diodes (LEDs) and optical elements arranged over the LEDs such that each optical element overlies only one associated LED. The first lighting unit is configured to illuminate a substantially rectangular region. A second lighting unit is attached to the assembly body and spaced from the first lighting unit. The second lighting unit includes a number of LEDs and optical elements arranged over the plurality of LEDs such that each optical element overlies only one associated LED. The lighting assembly is configured to direct the light toward the substantially rectangular area such that the light illuminates the substantially rectangular area with a uniformity across the substantially rectangular area that achieves at most a 3:1 ratio of the average illumination to the minimum illumination.
US09947247B2 Perforated bib tie articles and methods of manufacture and use
A labelling tie (10) includes a tie portion (14), a wire assembly (24), and a bib portion (16) connected to the tie portion. The tie portion (10) has a first arm (18-R), a mid-segment, and a second arm (18-L). Spaced apart perforations (20) intersect each of the first and second arms. The wire assembly (24) has a retention wire (26) that spans across the first arm, the mid-segment, and the second arm. A sheet of labelling ties (62) includes separably connected labelling ties. A method attaches a labelling tie to an item or a group of items. The method includes wrapping the first arm (18-R) and second arm (18-L) around at least one object (12, 12′), allowing the first and second arms to meet at a location with a portion of the first arm and a portion of the second arm extending past the location, and twisting the first and second arm portions together, thereby securing the tie portion around the object(s).
US09947239B2 Data diagnostic evaluation device
A teaching aid to aid in evaluating data may include a frame member and an eye guide movably connected to the frame member to guide the user of the teaching aid in evaluating the data. The frame member may include a top frame wall, a pair of opposing a side frame walls to connect to the top frame wall and a bottom frame wall to connect to the pair of opposing side frame walls, and the frame member may include a divider wall to define a cavity for the data to be evaluated.
US09947235B2 Smart learning system using device social relation and method thereof
Disclosed are a smart learning system using a device social relation and a method thereof. The smart learning system includes a first device that generates a device social relation and shares learning content, and at least one second device that executes an event related to the learning content by acquiring the shared learning content when is included in the device social relation.
US09947234B2 Educational puzzle and writing device
An educational teaching device for children to learn and write the letters of the alphabet, numbers, or other elements in proper sequence. The device comprises an inner board surface with plurality of cavities and a separate plurality of puzzle pieces of elements corresponding to the configuration. Upon proper placement of puzzle pieces, indicators are activated resulting in the emission of visual or audible signaling. The educational puzzle and writing device also comprises a magnetic writing sheet or writing materials using a magnetic pen or writing implement with numbered arrow instructions.
US09947233B2 Method and system to improve safety concerning drones
A method and system for controlling access to restricted sectors in airspace. The method includes creating a multi-dimensional map of airspace, overlaying a sector having boundaries onto the map, wherein the sector contains a restricted flight zone and a buffer zone monitoring the flight of an unmanned aerial vehicle (UAV), sending a command to the UAV if the UAV enters the buffer zone; and generating a response if the UAV does not leave the sector based on the command.
US09947230B2 Planning a flight path by identifying key frames
A flight path of a physical aircraft vehicle is planned. A specification of a plurality of key locations within a virtual environment is received. A trajectory between the plurality of key locations is determined. A three-dimensional virtual preview of a flight on the trajectory is provided. Instructions for the physical aircraft vehicle to at least in part follow the trajectory is generated.
US09947226B2 Methods and systems for blind spot monitoring with dynamic detection range
A system and method are provided and include a blind spot monitoring system with a blind spot sensor that monitors a focus area within a blind spot detection area of a subject vehicle and that generates an alert when a secondary vehicle is detected within the focus area of the blind spot detection area. A controller receives data corresponding to an amount of traffic at a location of the subject vehicle, determines the level of traffic at the location of the subject vehicle based on the data, and reduces the focus area when the level of traffic is greater than a predetermined threshold.
US09947225B2 Apparatus and method for monitoring a target object
Embodiments of the present invention provide monitoring apparatus for monitoring a target object external to a vehicle. The apparatus is operable to determine whether the target object is a valid target object in dependence on a value of a maximum range Rmax from the vehicle at which the target object has been detected. The apparatus may be operable to pre-arm a braking system and optionally apply a braking system responsive to a determination that a risk of collision exists.
US09947214B2 Authentication apparatus, authentication method, authentication system, and container system
An authentication apparatus includes an authentication unit configured to perform authentication processing according to power generation information from a power generation unit configured to generate electric power from ambient energy.
US09947212B2 Wearable device configuration interaction
A method and system for interacting with a wearable device is provided. The method includes detecting, by a first wearable device of a first user, a body attachment band of a second wearable device of a second user physically interlinked with a body attachment band of the first wearable device. In response, operational attributes of the first wearable device are activated and a specified configuration between the body attachment band of the first wearable device and the body attachment band of the second wearable device is detected. Specified actions associated with the operational attributes are determined and a specified action is executed with respect to a first operational attribute. The specified action is executed with respect to the first wearable device and the second wearable device.
US09947207B2 Method and apparatus for detecting an obstructed view
A method and apparatus for detecting an obstructed surface are provided. The apparatus includes: at least one memory comprising computer executable instructions; and at least one processor configured to read and execute the computer executable instructions. The computer executable instructions cause the at least one processor to: detect a current draw from a generator; determine that a surface including a conductive coating is obstructed in response to the current draw being greater than a predetermined threshold; and output a signal to perform a function in response to determining that the surface is obstructed.
US09947202B1 Sensor data to identify catastrophe areas
A computer-implemented method for generating an automated response to a catastrophic event, that includes (1) analyzing a sample set of data generated in association with a catastrophic event to determine a threshold pattern; (2) receiving, with customer permission or affirmative consent, home sensor data from a smart home controller via wireless communication or data transmission, the home sensor data including data regarding at least one of (i) structural status; (ii) wind speed; (iii) availability of electricity; (iv) presence of water; (v) temperature; (vi) pressure; and/or (vii) presence of pollutants in the air and/or water; (3) determining, based upon or from computer analysis of the home sensor data, whether the home sensor data indicates a match to the threshold pattern; and (4) automatically generating a response if the home sensor data indicates a match to the threshold pattern. As a result, catastrophic events and responses thereto may be improved through usage of a remote network of home sensors.
US09947198B2 Systems and methods for context-aware transmission of longitudinal safety and wellness data wearable sensors
The present solution provides a system and a method for efficiently transmitting data recorded by a wearable sensor. More particularly, the systems and methods described herein enable the data/context-aware transmission of data. In some implementations, by classifying data into predefined categories and then transmitting the data using a transmitter configuration associated with each of the categories enables improved transmission reliability while also improving battery life.
US09947195B2 Article management system
In conventional article management systems, a problem has been presented in that the degree of control over how articles are managed has not been adequate. An article management system having: a line constituted by an open-type transfer line; a distribution area in which articles to be managed are placed, the articles to be managed being placed in the distribution area; an RF tag provided with a tag transmission unit for electromagnetic coupling with the line of the distribution area for the articles to be managed; a signal communication unit provided to the line; an antenna for electromagnetic coupling with the signal communication unit; and an RFID reader for sending out the transmission signal to the line via the antenna, and receiving a response signal output by the tag transmission unit via the line. Any variations in the operating characteristics of the tag transmission unit caused by the articles to be managed are detected as a result of variations in the intensity or phase of the signal reflected from the RF tag, whereby the presence of an article to be managed is detected.
US09947191B2 Monitoring system
A master device stores audio data and image data transmitted from an outdoor monitoring camera in an image memory and transmits the data to a mobile phone terminal, the mobile phone terminal includes a display/input unit, displays the image data and a predetermined icon on the display/input unit, and transmits a request signal for stopping the storage operation performed by the master device to the master device when a predetermined operation is performed on the predetermined icon, and the master device stops storing the audio data and the image data in the image memory.
US09947189B2 Home automation device for monitoring the movement of a swinging wing and method for enhancing the reliability of such a device
A home automation device includes a movement detector (20) including an accelerometer and a magnetometer, and a processing unit for processing the signals supplied by the accelerometer and the magnetometer. At least one memory stores a reference orientation of the detector. The processing unit, on detection of a reference event from the acceleration signals, is capable of replacing the reference orientation with the instantaneous orientation of the detector.
US09947187B2 Haptic notification system with rules for notification that can be altered to increase effectiveness
A system, method and program product for delivering haptic notifications to a user. A system is disclosed having: a plurality of wearable devices adapted to be worn on different parts of a user, wherein each wearable device is adapted to output a configurable haptic notification to the user; a host device that coordinates with at least two wearable devices to output a scheme of haptic notifications based on an associated rule in response to a detected event; and a learning system that analyzes feedback from the user to determine an efficacy of the scheme and causes the associated rule to be altered in response to the scheme being deemed ineffective.
US09947186B2 Haptic feedback controller
A haptic feedback element controller for a mobile device and a method of controlling a haptic feedback element for a mobile device is described. The haptic feedback element includes a processor having a processor output, a first processor input, and a second processor input, a control state module having an output coupled to the second processor input and configured to determine at least one operating state parameter of at least one of a haptic feedback element and a haptic feedback element amplifier; wherein the processor is configured to alter the amplitude of one or more frequency components of an input signal received on the first processor input in dependence of the at least one operating state parameter and to output a processed signal to a haptic feedback element amplifier having an output for coupling to a haptic feedback element. The haptic feedback element controller may maximize the drive signal up to mechanical and thermal limits without lifetime reduction of the haptic feedback element.
US09947183B2 Payment processing with automatic no-touch mode selection
A “no-touch” mobile checkout experience frees consumers from the need to manually locate and activate a mobile payment application in order to complete a transaction. The consumer simply brings his mobile device within close range of an interface console, which in various embodiments prompts the device to launch an application that causes display of a payment token without user action. If the consumer's device is not NFC-capable, the interface console can read a displayed token optically in the usual fashion.
US09947179B2 Standardized scoring wagering system
A network distributed processing system is disclosed, including a mobile computing device connected to a controller by a network, wherein the mobile computing device is constructed to execute an entertainment game; a server connected to the controller via a communication link, the server constructed to determine a result of a wagering event and provide the results of the wagering event to the controller; the controller connected to the mobile computing device by the network and connected to the server by the communication link, wherein the controller is constructed to: determine when a wagering event occurs during play of the entertainment game; request a resolution to the wagering event; receive a score value; receive an amount of real credit committed; map the score value to a standardized score value using the score value and the real credit commitment; and update an account of the player with the standardized score value.
US09947174B2 Computer system for multiple user, multiple event real-time online wagering
A computer system includes a server computer that handles transactions with user devices to create and manage events, create and manage user accounts and process wagers. Transactions regarding wagers in connection with events can be processed in real-time. The wagers are processed using a payoff function that rewards participation and accurate information, yet does not permit arbitrage or otherwise reward splitting a wager by participating under multiple identities. To compute a payoff, a first score is computed based on the probability estimate by a participant and the outcome. A second score is computed based on an aggregate of wagers of all other participants for each participant, where the first score for the participant is no more than the second score for at least one outcome. The payoff for the participant is then computed as a function of the first score and the second score.
US09947169B2 Operation unit and game machine
An operation portion support portion that moves in a Z direction in response to a pressing operation performed by a user, a first slide portion that is arranged at a position covering the periphery in the X direction and Y direction of the operation portion support portion and moves in the Y direction, which is orthogonal to the Z direction, due to the operation portion support portion moving in the Z direction, a second slide portion that is arranged at a position adjacent in the Y direction to the first slide portion and moves in the X direction, which is orthogonal to the Z direction and Y direction due to the first slide portion moving in the Y direction, and a biasing member that biases the second slide portion in the −X direction are included.
US09947168B2 Multiple pay combination gaming apparatus
A gaming machine is disclosed that provides a game in which a player of the gaming machine stakes a wager on one or more outcomes of the game that are represented as symbols arranged in an array of symbol display positions. The player controls the number of outcomes on which a wager is staked by operating a user interface. During play of the game the gaming machine causes a display to display indicia representative of the total number of outcomes selected but not display indicia representative of every available outcome and not display indicia of every selected outcome. Indicia representative of an individual outcome is displayed when that outcome defines a winning combination. A method of providing a graphical user interface for a gaming machine is also disclosed.
US09947162B2 Image acquisition device and image acquisition method
Light is emitted on one side of a paper sheet 100, which is being transported on a transport path, from a first light source 11, and light is emitted on other side of the paper sheet 100 from a second light source 21 and a fourth light source 22. A first light receiving sensor 14 receives a first reflected light, which is the light emitted by the first light source 11 and reflected from the one side of the paper sheet 100. A second light receiving sensor 24 receives a second reflected light, which is the light emitted by the second light source 21 and the fourth light source 22 and reflected from the other side of the paper sheet 100, and receives a transmitted light that is the light emitted by the first light source 11 and that has passed through the paper sheet 100.
US09947161B2 Disk image acquiring device and disk sorting device
Disk image acquiring device includes a guide for guiding a peripheral surface of a disk moving in a predetermined direction along a predetermined guide line, an imaging window defining an image-taking region on the one surface of the disk, a timing sensor to take images having a detection axis traversing a moving direction of the disk and outputting a timing signal as arrival of the disk at a predetermined position on the imaging window when the peripheral surface of the disk has been detected on the detection axis, and an imager which takes an image of the one surface of the disk via the imaging window based upon the timing signal, wherein a bisector of an angle between the guide line and the detection axis is utilized as a base line, and the imaging window is extended along the base line.
US09947158B2 Access control device commissioning
A system and method for enhancing the security associated with the commissioning of an access control device. According to certain embodiments, a commissioning activator is positioned to be accessible from one side of the installed access control device. Thus, the access control device may be installed such that the commissioning activator is accessible to individuals having access to a relatively secure side of the access control device. The displacement of the access control device may generate an activation signal that is detected by a processing device of the access control device. Upon detection of the activation signal, the processing device may activate an input/output device that may transmit an identification signal that is detected by a wireless configuration device. Following receipt of a connection request from the configuration device, the access control device and the configuration device can be connected such that commissioning of the access control device may proceed.
US09947148B2 Method and safety concept for recognizing defects in a drive system of a motor vehicle
A method and associated safety system are provided for the recognition of defects in a drive system of a motor vehicle, having an electronically controllable brake control system and having at least one electronically controlled driving engine, an electronically controllable clutch and/or having an electronically controllable transmission. An electronic braking control device is assigned to the brake control system, which braking control device is connected with an independent monitoring module. The independent monitoring module checks for an occurrence of an implausible braking torque, for detecting a defect in the drive system.
US09947145B2 System and method for providing inter-vehicle communications amongst autonomous vehicles
In one embodiment, a vehicle identifier (ID) and vehicle information of a first autonomous vehicle is transmitted to a cloud server over a network, where the cloud server is communicatively coupled to a plurality of autonomous vehicles. A list of one or more vehicle identifiers (IDs) are received from the cloud server. The vehicle IDs identify one or more autonomous vehicles are within a predetermined geographic proximity of the first autonomous vehicle. The first autonomous vehicle communicates with a second autonomous vehicle that is selected from the list of one or more autonomous vehicles via a wireless local area network to exchange an operational status of the first autonomous vehicle with the second autonomous vehicle.
US09947144B2 Error variance detection method of CAN communication system and the CAN communication system
An error variance detection method of CAN communication system according to an exemplary embodiment of the present invention may include storing an error information that corresponds to the communication error in a network management start message, if an communication error is occurred in the CAN communication system, by at least one of a plurality of slave ECU, transferring the network management start message to a master ECU, by at least one of a plurality of slave ECU, determining whether there is or is not the error information in response to the network management start message, by the master ECU, detecting the error information from the network management start message, if there is the error information, by the master ECU, and transmitting the error information detected by a demand of a diagnosis device to the diagnosis device, by the master ECU.
US09947137B2 Method for effect display of electronic device, and electronic device thereof
A method for effect display of an electronic device, and the electronic device thereof are provided. The method in the electronic device includes obtaining a correlation among a plurality of objects extracted from an image, and displaying at least any one of the plurality of objects by adding an effect, on the basis of the correlation. Further, other exemplary embodiments are also included in the present disclosure in addition to the aforementioned exemplary embodiments.
US09947136B2 Three-dimensional image data analysis and navigation
A system (100) is provided for analyzing image data representing image intensities of an image volume, the image intensities having a signal dynamic range. The system (100) comprises an analysis subsystem (140) for accessing display data defining a set of display settings for display of the image volume, each one of the set of display settings causing a different sub-range of the signal dynamic range to be mapped to a display dynamic range during the display. During operation, the analysis subsystem (140) analyzes the image data to identify, for each one of the set of display settings, a region of the image volume which comprises image intensities within the respective sub-range, thereby identifying a set of regions of interest, and generating analysis data (142) identifying the set of regions of interest. As such, the user is enabled to quickly navigate to regions in the image volume which contain meaningful visual information when displayed using the respective display settings.
US09947134B2 System and method for generating a dynamic three-dimensional model
The invention is a system for generating a dynamic three-dimensional model of a space, comprising a camera module (100) comprising an optical sensor adapted for recording image information of the space, and a depth sensor adapted for recording depth information of the space, and a modelling module (300) adapted for generating a dynamic three-dimensional model of the space on the basis of the image information and the depth information. In the system according to the invention the image information with the optical sensor and the depth information with the depth sensor are recorded at a plurality of discrete times. The system according to the invention comprises a synchronisation signal generating module determining synchronised with each other the discrete times associated with the image information and the discrete times associated with the depth information. In the system according to the invention the dynamic three-dimensional model is generated at a plurality of the discrete times of the image information and of the depth information, and at each of the discrete times the image information and the depth information associated with the given discrete time are integrated into the dynamic three-dimensional model on the basis of position and orientation of the camera module (100) at the given discrete time, which position and orientation are determined by the modelling module (300) on the basis of information provided by the sensors of the camera module (100) at the discrete times in an observation window. The invention is, furthermore, a method for generating a dynamic three-dimensional model of a space.
US09947133B2 Method and system for modeling light scattering in a participating medium
The disclosure provides an approach for simulating scattering in a participating medium. In one embodiment, a rendering application receives an image and depth values for pixels in the image, and generates multiple copies of the image associated with respective numbers of scattering events. The rendering application further applies per-pixel weights to pixels of the copies of the image, with the per-pixel weight applied to each pixel representing a probability of a light ray associated with the pixel experiencing the number of scattering events associated with the copy of the image in which the pixel is located. In addition, the rendering application applies a respective blur to each of the weighted copies of the image based on the number of scattering events associated with the weighted copy, sums the blurred weighted image copies, and normalizes the sum to account for conservation of energy.
US09947131B2 Graphics processing system
When rendering a scene that includes a complex object made up of many individual primitives, rather than processing each primitive making up the object in turn, a bounding volume which surrounds the complex object is generated and the scene is then processed using the bounding volume in place of the actual primitives making up the complex object. If it is determined that the bounding volume representation of the object will be completely occluded in the scene (e.g. by a foreground object), then the individual primitives making up the complex object are not processed. This can save significantly on processing time and resources for the scene.
US09947130B2 Method, apparatus, and computer program product for improved graphics performance
A method for improving performance of generation of digitally represented graphics. The method comprises: receiving a first representation of a base primitive; providing a set of instructions associated with vertex position determination; executing said retrieved set of instructions on said first representation of said base primitive using bounded arithmetic for providing a second representation of said base primitive, and subjecting said second representation of said base primitive to a culling process. A corresponding apparatus and computer program product are also presented.
US09947124B2 Motion control of active deformable objects
Techniques are proposed for animating a deformable object. A geometric mesh comprising a plurality of vertices is retrieved, where the geometric mesh is related to a first rest state configuration corresponding to the deformable object. A motion goal associated with the deformable object is then retrieved. The motion goal is translated into a function of one or more state variables associated with the deformable object. A second rest state configuration corresponding to the deformable object is computed by adjusting the position of at least one vertex in the plurality of vertices based at least in part on the function.
US09947122B2 Photo family tree builder
The photo family tree builder is a business process and a computerized method for creating a two-dimensional family tree product using software. The software allows users to organizes photos of related individuals, or couples in a family tree, according to actual family relationships. It provides cooperating templates consisting of: one or more seeds, a tree trunk with a crown: one or more branches and picture frames of leaves, hearts, love-knots, fruits or flowers of the tree, which helps the display, emulate a natural tree. The tree is expandable and capable of displaying any number of generations. It provides a way to use photos that are readily available of family members; without requiring new ones and it provides an inconspicuous and clear alternative for missing pictures. It accommodates the growth of families, through marriages, unions and births. Lastly, the picture frames and indicia tags contain a place for names and dates.
US09947120B2 Visualization of wellbore cleaning performance
A method for displaying performance of a wellbore drilling operation including wellbore cleaning includes defining drilling parameters for the drilling operation. The method includes defining a visualization tool including a boundary defined by the drilling parameters, where the boundary depicts an optimal rate of penetration (ROP). The method includes displaying the visualization tool with the optimal ROP, where the optimal ROP defines a maximum ROP for optimal wellbore cleaning based on the drilling parameters. The method includes displaying an actual rate of penetration (ROP) with respect to the optimal ROP on the visualization tool. The method further includes adjusting the actual ROP to match the optimal ROP.
US09947119B2 User interface framework for viewing large scale graphs on the web
Various embodiments provide a computer-implemented system and method providing a user interface framework for viewing large scale graphs. An example embodiment includes obtaining graph data including information related to a plurality of nodes, the plurality of nodes corresponding to search queries performed on a particular host site; constructing a plurality of sub-graphs, the sub-graphs being clusters of search results that are formed based on an amount of overlap among the search results produced from the search queries; rendering the graph by displaying each of the plurality of nodes at a respective absolute position within the graph and generating a plurality of tiles representing images of the plurality of sub-graphs; and displaying a sub-graph image corresponding to a selected position and zoom level.
US09947115B2 Visual music color control system
Described herein are various technologies pertaining to presenting, and configuring, digital objects on a display device for application with a visual music presentation. An interactive screen can be presented on a touchscreen of a display device, wherein a visual musician can interact with one or more components and/or features comprising the screen to control presentation of the digital objects. A portion of the screen can be configured to initially present a continuous hue spectrum, which can subsequently be replaced with a discrete hue spectrum. Further, a spectrum comprising naturally visible hues can be modified such that a plurality of hues in the spectrum are positioned equally across the spectrum, and further, brightness of respective hues can be modified to enable visually appealing visual music presentation.
US09947113B2 Controlling real-time compression detection
A detection learning module is used for enabling and/or disabling real-time compression detection by maintaining a history of real-time compression detection success for sampled data. The enabling or disabling of the real-time compression detection is based on a detection benefit function derived from a set of calculated heuristics indicating the real-time compression detection success on input streams. The detection benefit function is calculated based on at least one heuristic score.
US09947106B2 Method and electronic device for object tracking in a light-field capture
A method and an electronic device for object tracking in a sequence of light-field captures. A data acquisition unit acquires a sequence of light-field captures, wherein each light-field capture comprises a plurality of views. A feature determining unit determines features of an initial visual appearance model for an object of interest in a reference view of a first light-field capture. A feature matching unit matches the features in the reference view and in the further views of the first light-field capture. A feature discarding unit discards features that cannot be well matched in all views of the first light-field capture. An appearance model building unit builds an updated visual appearance model for the object of interest based on the remaining features. Finally, a movement tracking unit tracks the movement of the object of interest in the sequence of light-field captures using the visual appearance model.
US09947104B2 Preview visualisation of tracked nerve fibers
The invention relates to a medical data processing method for determining the position of a nerve fiber based on a diffusion image-based tracking method of tracking nerve fibers. In one example, the method encompasses comparing a set of tracked nerve fibers to a model of nerve fibers contained in atlas data.
US09947103B1 Learning method and learning device for improving image segmentation and testing method and testing device using the same
A method for improving image segmentation using a learning device including steps of: (a) if a training image is obtained, acquiring (2-K)th to (2-1)th feature maps through an encoding layer and a decoding layer, and acquiring 1st to Hth losses from the 1st to the Hth loss layers respectively corresponding to H feature maps, obtained from the H filters, among the (2-K)th to the (2-1)th feature maps; and (b) upon performing a backpropagation process, performing processes of allowing the (2-M)th filter to apply a convolution operation to (M−1)2-th adjusted feature map relayed from the (2-(M−1))th filter to obtain M1-th temporary feature map; relaying, to the (2-(M+1))th filter, M2-th adjusted feature map obtained by computing the Mth loss with the M1-th temporary feature map; and adjusting at least part of parameters of the (1-1)th to the (1-K)th filters and the (2-K)th to the (2-1)th filters.
US09947099B2 Reflectivity map estimate from dot based structured light systems
Systems and methods are provided for determining a depth map and a reflectivity map from a structured light image. The depth map can be determined by capturing the structured light image and then using a triangulation method to determine a depth map based on the dots in the captured structured light image. The reflectivity map can be determined based on the depth map and based on performing additional analysis of the dots in the captured structured light image.
US09947095B2 Image processing apparatus for providing image analysis and a method therefor
An image processing techniques and apparatuses providing image analysis that calculates a feature value of an input frame image; compares the feature value of the frame image with a feature value of a previous frame image or standard frame image to determine an area corresponding to a change of the feature value and a degree of the change of the feature value in the input frame image. A color-coded display of the corresponding area may be generated based on the degree of change.
US09947087B2 Systems and methods for determining image safety
Systems and methods are provided for determining the safety of an image, which may be used to determine whether an image is appropriate for a given purpose or for use in a given context. Determining the safety of the image may include analyzing the image to determine the amount of skin exposed in various key body areas of each human represented in the image, such as a photograph.
US09947086B2 Image adjustment based on locally flat scenes
Imaging systems and methods are disclosed that use locally flat scenes to adjust image data. An imaging system includes an array of photodetectors configured to produce an array of intensity values corresponding to light intensity at the photodetectors. The imaging system can be configured to acquire a frame of intensity values, or an image frame, and analyze the image frame to determine if it is locally flat. If the image frame is locally flat, then that image data can be used to determine gradients present in the image frame. An offset mask can be determined from the image data and that offset mask can be used to adjust subsequently acquired image frames to reduce or remove gradients.
US09947082B2 Image compensation method and apparatus
An image compensation method and apparatus is provided. The method may include: determining, as the second brightness value, a brightness value for which a SAD corresponding to the brightness value and the first brightness value is the minimum, in brightness parameters of a second image displayed at a second time; determining a membership degree corresponding to a target SAD; determining a motion compensation parameter corresponding to a first coordinate and a median frame interpolation parameter corresponding to the first coordinate; determining a brightness compensation parameter corresponding to the first coordinate based on the membership degree corresponding to the target SAD, the motion compensation parameter corresponding to the first coordinate and the median frame interpolation parameter corresponding to the first coordinate; performing an image compensation so as to display a compensated image at a time between the second time and the first time based on the brightness compensation parameter corresponding to the first coordinate.
US09947077B2 Video object tracking in traffic monitoring
A method and system are provided for tracking an object in a video sequence. The method includes selecting a tracking window in a current video frame, the tracking window including at least a location and a size associated with an object to be tracked, and adjusting the size of the tracking window based on an estimated change in a scale of the object, and using the adjusted tracking window for tracking the object in a subsequent video frame.
US09947074B2 Memory-aware matrix factorization
Embodiments include method, systems and computer program products for performing memory-aware matrix factorization on a graphics processing unit. Aspects include determining one or more types of memory on the graphics processing unit and determining one or more characteristics of each of the one or more types of memory. Aspects also include assigning each of a plurality of memory accesses of a matrix factorization algorithm to one of the one or more types of memory based on the one or more characteristics and executing the matrix factorization algorithm on the graphics processing unit.
US09947073B2 Memory-aware matrix factorization
Embodiments include method, systems and computer program products for performing memory-aware matrix factorization on a graphics processing unit. Aspects include determining one or more types of memory on the graphics processing unit and determining one or more characteristics of each of the one or more types of memory. Aspects also include assigning each of a plurality of memory accesses of a matrix factorization algorithm to one of the one or more types of memory based on the one or more characteristics and executing the matrix factorization algorithm on the graphics processing unit.
US09947072B2 Method and system of managing data files
Methods and systems of managing data files are described herein. One method includes updating a container file of data files having a container file metadata section and one or more empty records, each record of the one or more empty records having: (i) a data file section reserved for storing a data file, (ii) a file metadata section reserved for storing metadata about the data file, and (iii) a record metadata section including information about the record and having at least a record status mark indicating that the record is empty. The method includes setting the record status mark of the one or more empty records to being updated; writing one or more records containing the data file into the one or more empty records within the container file. After successfully writing the one or more records resetting the record status mark to valid.
US09947071B2 Texture pipeline with online variable rate dictionary compression
A graphics system supports variable rate compression and decompression of texture data and color data. An individual block of data is analyzed to determine a compression data type from a plurality of different compression data types having different compression lengths. The compression data types may include a compression data type for a block having a constant (flat) pixel value over n×n pixels, compression data type in which a subset of 3 or 4 values represents a plane or gradient, and wavelet or other compression type to represent higher frequency content. Additionally, metadata indexing provides information to map between an uncompressed address to a compressed address. To reduce the storage requirement, the metadata indexing permits two or more duplicate data blocks to reference the same piece of compressed data.
US09947066B2 Method, apparatus and system for inserting watermark data
An apparatus and method for a sensor network, machine-to-machine (M2M) communication, machine type communication (MTC), and Internet of things (IoT) are disclosed. The disclosure may be applied to, for example, intelligent services related to the above technologies, in conjunction with smart homes, smart buildings, smart cities, smart cars or connected cars, health care, digital education, retail business, security, and safety related services. The method includes generating first image data by resizing original image data to a predetermined size, inserting watermark data into the first image data, and adding difference data corresponding to the difference between the original image data and the first image data to second image data that is image data in which the watermark data is inserted.
US09947064B2 Image photographing apparatus and method for controlling the same
An image photographing apparatus and a method for controlling the image photographing apparatus are provided. The method includes outputting light so as to penetrate a projection and fall on an object, receiving first reflective light reflected from an object, obtaining a first image based on information of the first reflective light, controlling the projection using predetermined information to generate a controlled projection, receiving second reflective light using the controlled projection, obtaining a second image based on information of the second reflective light, and generating a depth map using the obtained first image and second image.
US09947062B2 Image forming apparatus and social security number registration system
An image forming apparatus includes a reading device that reads an image from a document, a storage device, and a central processing unit (CPU). The storage device stores therein an authentication kit, a scan extension kit, and a specific information collection program. The CPU executes the authentication kit to function as an authentication unit, the scan extension kit to function as a character recognition unit, and the specific information collection program to function as a specific information collection unit. The specific information collection unit acquires information of the user for which authentication passes from a user information management system that manages the information of the user. The specific information includes a character that represents a value of a specific item indicated in a specific document as the document and that is recognized by the character recognition unit; and the information of the user acquired from the user information management system.
US09947060B2 Information matching and match validation
Disclosed herein is a matching of multiple different social graphs to generate a combined social graph. Such a combined social graph may be searched and used in determining information to provide to a user, for example. An iterative metric learning approach may be used in matching multiple different social graphs. A mechanism is provided to validate a match from different social graphs. Match validation of data field matching is provided.
US09947059B2 Group formation and dynamic pricing for E-commerce in social networks
A system platform and associated methods are provided for implementing online reverse auctions in a social network platform (SNP). A fully-automated, live, reverse-auction based system is integrated into an SNP to enable buyers to initiate desired transactions and take advantage of a subscribers' network of friends, colleagues, co-workers, family members and connections by connecting buyers and sellers in a non-intrusive, targeted fashion. Sellers compete for buyers' business by providing dynamic, real-time seller-specific pricing while simultaneously optimizing the seller's target parameters such as price, inventory levels, profit, revenue and volume.
US09947057B2 Providing online promotions through social network platforms
Systems and methods for providing online promotions integrated with social network-based platforms are disclosed. Promotion details such as rules, offered prizes, incentives and descriptions, survey questions, display banners, terms and conditions, privacy policy, and social networks to integrate the promotion with, are provided by the sponsoring organization to a server. The server generates a custom promotion application or widget for integrating with the organization's social network webpage external to social networks. A participant enters the promotion through these webpages or other links and lists friends in the social network to receive an invitation to enter the promotion. Viral features such as friend invite features, newsfeeds, minifeeds, other features that display online activities of users and people in the users' social network, notifications, requests, and other social media-based platform features to deliver messages to members of the one or more social networks further spread the word about the organization's promotion.
US09947054B2 Real-time transaction data processing and reporting platform
A processing server may receive transaction data from one or more point of sale (POS) terminals in near real-time. Transaction data received from each of the POS terminals may be in a format that is specific to the POS terminal. Upon receiving the transaction data having the POS specific format, the processing server may convert the transaction data to a common format that is compatible with the operations of the processing server. Further, the processing server may index the converted transaction data into one or more categories. Responsive to indexing, the processing server may generate aggregate data from the indexed transaction data. Further, the processing server may receive a request for a data report associated with the aggregate data. Responsive to receiving the request, the processing server may generate the data report, format the data report to match a user preference, and transmit the data report for presentation.
US09947041B2 Dynamically determining bid increments for online auctions
Bidding activity is analyzed over a duration in which multiple bids are received in the auction. A bid increment is dynamically determined for the auction in response to auction activity. An online auction system can utilize the bid increment to determine or suggest the next bid that can be received in the auction for purpose of supplanting the current bid.
US09947037B2 Software recommendation services for targeted user groups
Computer-implemented methods and systems are provided for recommending one or more applications to users connected to one or more social networks. The computer-implemented method may include determining frequency of interaction between the users connected to the one or more social networks, analyzing behavioral patterns of the users connected to the one or more social networks, the behavioral patterns derived by considering at least the frequency of interaction between the users, and enabling at least one service provider to recommend one or more applications to one or more of the users based on the monitored behavioral patterns.
US09947036B2 Gift suggestion system
Systems and methods for suggesting gifts include associating a first item identifier with a first user in a database in response to receiving at least one implicit action by the first user that is directed to a first item having a first item type that is identified by the first item identifier. A second user device of a second user is then detected as located at a physical merchant location. An association between the first user and the second user is then retrieved. In response to the first user being associated with both the second user and the first item identifier in the database, that the first item type that is identified by the first item identifier is determined to be available at the physical merchant location. A gift suggestion is then provided for display on the second user device that identifies the first user and the first item type.
US09947033B1 Streaming data marketplace
A technology for a streaming data marketplace is provided. In one example, a method may include requesting to receive a first stream of data from a first source via the streaming data marketplace. The first stream of data may be received and then correlated and combined with data from a second source as a combined stream. The combined stream may then be published to the streaming data marketplace.
US09947031B2 Content access management in a social networking system for locally stored content
A content access management system receives an access determination requested identifying an access rule and a requesting user. The access rule may be created in advance by the content owner at the content access management system. The access rule may allow access to content objects based on the requesting user's biographic information, geographic information, affiliation information, payment information, or any other user characteristic. The user information may be entered by the requesting user at a social networking system interface for purposes unrelated to the content object or content owner. The content access management system retrieves the identified access rule and retrieves requesting user information based on the access rule. An access determination is made based on the retrieved access rule and requesting user information, and is transmitted to the content owner.
US09947030B1 Enhanced privacy with fewer cookies
Aspects relating to client server interactions using cookies are provided. A computer-implemented method is provided that includes receiving a request from a user for a first advertisement associated with a first advertiser, the request including first cookie data, the first cookie data including a first identifier specified for a first cookie, the first cookie being associated with a first group of advertisers including the first advertiser and a third advertiser, receiving a request from the user for a second advertisement associated with a second advertiser, the request including second cookie data, the second cookie data including a second identifier specified for a second cookie, the second cookie being associated with a second group of advertisers including the second advertiser and where the advertisers of the second group of advertisers are distinct from the advertisers of the first group of advertisers.
US09947028B1 System and method for increasing online conversion rate of potential users
A computer-implemented method of increasing the online conversion rate of potential users to a computer-hosted service is described. The method includes a computing device receiving a browser request from a potential user, the computing device receiving user-specific data as part of the browser request. The computing device inputs the user-specific data into a conversion model executed by the computing device and outputs a conversion score for the potential user based on the model. The computing device sends to the browser a marketing intervention if the conversion score falls below a pre-determined threshold value.
US09947019B2 Method and system for contextual profiling for object interactions and its application to matching symmetrical objects
A method for constructing a context profile within a system implementing symmetrical object profiles. The method includes establishing one or more contextual boundary parameters defining a context within which transactions occur. A plurality of transactions associated with the context is filtered using the contextual boundary parameters to obtain a pool of filtered transactions. Each of the transactions is conducted between at least two objects in the system including a plurality of objects associated with the symmetrical object profiles. An array of filtered objects including objects involved in at least one filtered transaction is established. Each filtered object is defined by a current version of a corresponding object profile and is associated with a corresponding transaction. The method includes generating a context object profile associated with the context that is based on attribute values of filtered object profiles associated with the array of filtered objects.
US09947017B2 Online content campaign classification
A content evaluation system includes a scanning server to scan web sites to determine metrics for online ads. The content evaluation system may include a content evaluation server to classify the online ads into campaign groups based on the metrics, and each group is associated with a different ad campaign.
US09947014B2 Determination and monetization of future location
A computer-implemented method for monetizing future location of users includes identifying indicator(s) retrieved from log data or an electronic declaration that indicate a possibility that a user will be at a specific location in the future; generating a probability that the user will be at the specific location in the future based on the indicator(s); and charging an advertiser a cost for an impression to which to serve a location-specific advertisement targeted to the user, the cost charged being greater when the probability is greater that the user will be at the specific location in the future. The method may be extended to targeting a group of users that expect to be at the same location at the future point in time. Monetization of future locations may depend on the quality and/or quantity of the log data and declarations of future locations and on a number of users in a group of users if monetized according to the group.
US09947009B1 Method and system for graphic and sonic encryption for securing data and electronic devices
A method of verifying a transaction between a first party and a second party using a first graphical symbol having at least a two-dimensional array of different segments arranged in a visually distinct pattern, or a first sonic symbol having different frequency magnitude segments over a desired time period. A second graphical or sonic symbol has only a portion of the segments of the first symbol. The first and second symbols are accessible by the first and second parties, respectively. The second symbol is compared to the first symbol and, if all of the segments of the second symbol match segments of the first symbol, the transaction between the first party and the second party is verified.
US09947008B1 Enhanced certificate authority
An enhanced certificate authority system and method allows for the enhanced security, validation and Multi-Factor Authentication of user's within a digital signature and transaction system through the creation and management of a user's Digital Identity certificate so that through an enhanced certificate authority a user's identity and bona fides may be both protected and established across a diversity of electronic devices and transactions.
US09947007B2 Payment information technologies
A method includes maintaining first payment card information for a cardholder. The method includes processing a first card not present transaction between the cardholder and a merchant. The first transaction based at least in part on the first information. The method includes generating second payment card information for the cardholder. The second information replacing the first information for subsequent use via the cardholder. The method includes receiving an input from the cardholder. The input indicating the merchant. The input based at least in part on the second information replacing the first information. The method includes sending the second information to the merchant based at least in part on the input. The method includes processing a second card not present transaction between the cardholder and the merchant. The second transaction based at least in part on the second information after the sending.
US09947006B2 Methods for risk management in payment-enabled mobile device
A payment-enabled mobile device receives, during a first tap of the mobile device on a proximity reader component of a point of sale (POS) terminal, first transaction context data for a current transaction, and receives during a second tap of the mobile device on the proximity reader component, second transaction context data for the current transaction. When the mobile device determines that the second tap is for the same transaction as the first tap, and that one of a customer verification method (CVM) status or a user acknowledgment status flag has been set, then it transmits a payment card account number to the POS terminal to consummate the transaction.
US09947003B2 Systems and methods for using gestures in financial transactions on mobile devices
A computer-implemented method for providing cardholder account information in response to gestures at a mobile computing device to facilitate a payment transaction is implemented by a mobile computing device coupled to a memory. The method includes receiving a first haptic gesture associated with a financial transaction, providing a plurality of payment method options retrieved from a data repository based upon the first haptic gesture, receiving a second haptic gesture comprising a payment method selection selected from the plurality of payment method options, and providing a plurality of cardholder account information for the financial transaction, the plurality of cardholder account information provided based at least in part on the payment method selection.
US09947002B2 Secure authorization of contactless transaction
Methods, systems, and machine-readable media are disclosed for securely authorizing a financial transaction utilizing an electronic payment credential. According to one embodiment, a method of authorizing a financial transaction utilizing an electronic payment credential can comprise maintaining information identifying an account associated with the electronic payment credential. The information can also identify one or more electronic devices authorized to use the electronic payment credential. A request to authorize the transaction can be received. The request can include information identifying an electronic device presenting the payment credential. The transaction can be authorized based at least in part on the information identifying the account. Authorizing can comprise determining the electronic device presenting the payment credential is one of the electronic devices authorized to use the electronic payment credential.
US09946997B1 Method and system for allocating deposits over a plurality of depository institutions
Computer system, computer-implemented method, and program product for managing transactions that include administering clients' deposits to and withdrawals from client transaction accounts; determining a client available deposit amount, Di, determining, for Di, a value of Ni banks for the respective client transaction account, wherein Ni is a whole number and (X) times (Ni) is equal to or less than 100, where X is a distribution percent value to be distributed to each of the Ni banks; allocating, the percentage, X, multiplied by the client deposit amount, Di, calculating, for the banks a respective net deposit amount; generating instructions to transfer funds; and updating.
US09946996B1 Methods, systems and articles for providing financial account information for setting up direct deposit of pay checks
Systems and methods for providing financial account information for an employee for setting up direct deposit of pay checks into a financial account of the employee. A financial services system receives a request from a payroll processor of an employer of the employee for account information for a financial account held by the employee, the request including personal information of the employee. The financial services system searches a database for a financial account held by the employee and identifies a financial account held by the employee by matching the personal information received in the request with corresponding information associated with a matching financial account stored in the database. The financial services system transmits the financial account information for the matching financial account sufficient to set up direct deposit to the payroll processor. The payroll processor then sets up direct deposit of the employee's pay checks into the matching financial account.
US09946995B2 System and method for collecting clearing information for implementing a global electronic funds transfer
A system and method is presented for receiving required information (i.e., clearing information) for performing a global electronic funds transfer. The system and method generates a form for receiving the clearing information from a user. The form includes clearing information fields that are each configured to accept an element of clearing information. The clearing information fields of the form are dynamically updated based on clearing information rules. The clearing information rules define a relationship between at least one of the clearing information fields and the clearing information received from the user. The dynamically updated form is provided to the user to input further clearing information.
US09946994B2 Techniques for providing insights relating to job postings
A method is disclosed for supplementing information that is to be presented to a user of a social-networking system with respect to a job posting. A request for a job posting stored in a database of a job hosting service is received from a client-computing device. The job posting is for a job opening of an employer and the request is associated with a first member of a social networking service. A snippet of a member profile of a second member of the social networking service is selected for presentation with the job posting. The snippet is extracted from the member profile based on an identification of a correspondence between information specified in the member profile and information specified in the job posting. Responsive to the request, the snippet is communicated to the client-computing device for presentation to the first member in conjunction with the job description.
US09946991B2 Methods using multi-dimensional representations of medical codes
Medical coding systems receive as input medical terms which coders classify into medical codes, used in the remuneration of medical procedures. A set of applicable medical codes can be determined by intersecting multidimensional data structures associated with the input terms and counting medical codes occupying regions of intersection. If the resulting set contains a single code, it is presented to the coder for verification. If the resulting set contains more than a single code, the coder can be questioned in a variety of ways to access, and select from, terminology options not implied by the originally provided input terms. The interactive process may also use the multidimensional data structures to regulate the order of questions, present decision aids, and select related procedure codes. The interaction concludes when the coder has fully specified the proper code or codes that describe the required procedure or procedures.
US09946990B2 System and method for determining product movement using a sensor
The present invention is a system and method for determining product movement using a sensor. Through the interaction of items placed on an array of sensors connected to a circuit board controller, the apparatus is configured to detect a change in capacitance caused by the interaction and thereby associate it with an item or groups of items. Detection and association of such signals recorded in a database with items displaced in a storage location permits a user to keep track of said items remotely through a computing device.
US09946989B2 Management and notification of object model changes
Techniques are disclosed for managing development of a model set comprised of one or more object models by a plurality of model developers. Each model developer may be considered an interested party. For example, when a model developer changes an area of the model, that person becomes the most interested party in other changes made to the same area. An automated mechanism is provided to track changes made to the model set and informs interested parties as changes are made or after changes are made to the model based on a weighting system. In one embodiment, the weighting system may be based on a distance from the changed portions and on the amount of time since a party last made a change to the same area.
US09946984B2 System and method for transporting a document between a first service provider and a second service provider
A system and method manages workflows exchanges a document between a first server associated with a first service provider and a second server associated with a second service provider over a network. A first workflow engine associated with the first service provider is configured to apply the document to a first workflow based on a first set of rules. A second workflow engine associated with the second service provider is configured to apply the document to a second workflow based a second set of rules. The first and second workflow engines run the first workflow at first service provider asynchronous to the second workflow at the second service provider. The system and method transports a document between the first service provider and second service provider. A first server encrypts the document to create an encrypted document and append an unencrypted header to the encrypted document. The header has a pairwise relationship identifier.
US09946970B2 Neural networks for encrypted data
Embodiments described herein are directed to methods and systems for performing neural network computations on encrypted data. Encrypted data is received from a user. The encrypted data is encrypted with an encryption scheme that allows for computations on the ciphertext to generate encrypted results data. Neural network computations are performed on the encrypted data, using approximations of neural network functions to generate encrypted neural network results data from encrypted data. The approximations of neural network functions can approximate activation functions, where the activation functions are approximated using polynomial expressions. The encrypted neural network results data are communicated to the user associated with the encrypted data such that the user decrypts the encrypted data based on the encryption scheme. The functionality of the neural network system can be provided using a cloud computing platform that supports restricted access to particular neural networks.
US09946966B2 Method and circuit for tuning an antenna circuit of an actively transmitting tag
Tuning an antenna circuit of an actively transmitting tag to a frequency of an interrogator carrier signal after the tag was inserted into a host device is accomplished by detecting presence of the interrogator carrier signal at a location of the actively transmitting tag and hereafter setting capacitances of capacitors and/or inductances of coils comprised in said antenna circuit in a way that resonance of said antenna circuit is established while the antenna circuit is excited by a magnetic field of said interrogator carrier signal. This allows automatic tuning of an antenna circuit of an actively transmitting tag after it was inserted together with a miniature card into a host device, such as a mobile telephone, personal digital assistant, tablet PC and similar devices.
US09946961B2 Image printing apparatus and method for controlling an image printing apparatus
An image printing apparatus including a communication interface, a printer, a user interface including an operation panel, a controller configured to control the printer and the user interface is provided. The controller is configured to receive preliminary data sent from an information processing apparatus through the communication interface; control the printer to perform a warm-up action; receive job data including image data through the communication interface; control the user interface to perform a receipt-notification and control the printer to start printing based on the image data; during a period from the receipt of the preliminary data until start of receiving the job data, withhold from accepting a cancellation command sent in response to user entering a cancellation operation; and after the start of receiving the job data, accept the cancellation command and cancel printing of the image based on the job data associated with to the entered cancellation command.
US09946955B2 Image registration method
An image registration method for registering a first image taken from a first viewpoint and a second image taken from a second viewpoint is disclosed. The method includes obtaining a first reference image by photographing a reference target from a first viewpoint; obtaining a second reference image by photographing the reference target from a second viewpoint; obtaining reference coordinate-difference values that indicate difference in coordinates of corresponding pixels between the first reference image and the second reference image; obtaining parallax registration-error values based on a distance of a photographing target from the first viewpoint and the second viewpoint; obtaining a registration result of a first image of the photographing target taken from the first viewpoint and the second image of the photographing target taken from the second viewpoint based on the reference coordinate-difference values; and correcting the registration result based on the parallax registration-error values.
US09946954B2 Determining distance between an object and a capture device based on captured image data
In various embodiments, methods, systems, and computer program products for determining distance between an object and a capture device are disclosed. The distance determination techniques are based on image data captured by the capture device, where the image data represent the object. These techniques improve the function of capture devices such as mobile phones by enabling determination of distance using a single lens capture device, and based on intrinsic parameters of the capture device, such as focal length and scaling factor(s), in preferred approaches. In some approaches, the distance estimation may be based in part on a priori knowledge regarding size of the object represented in the image data. Distance determination may be based on a homography transform and/or reference image data representing the object, a same type or similar type of object, in more approaches.
US09946950B2 Data processing apparatus, data processing method, and program
An aspect of the present invention provides a data processing apparatus, including: an image acquisition section that acquires a captured image depicting a road along which vehicles pass; a calibration section that computes a road parameter for converting coordinates in the captured image to coordinates in real space based on the captured image and road data related to the road; a vehicle lane region detection section that detects a vehicle lane region in the captured image based on the captured image and the road parameter; and a processing region setting section that, based on the vehicle lane region, sets a processing region in the vehicle lane region for detecting a vehicle passing.
US09946948B2 Article delivery system
When monitoring a logistics line and outputting a video image on a display, a privacy-protected video image processor uses an image of a first specific region corresponding to an area of the logistics line as it is among an original image captured by a capture, and performs mask processing on a person detected in an image of a region other than the first specific region.
US09946946B1 Systems and methods for recognizing symbols in images
A computer-implemented method comprises generating a description of a character symbol from a binarized image; comparing a template for the character symbol with the description of the character symbol based on a reference description, wherein the template comprises a grid of cells, a set of local features which may be present in the grid of cells, the reference description specifying which member of the set of local features should be present or absent in the grid of cells, and a threshold of an accepted deviation with the description of the character symbol; assigning a penalty value to the description of the character symbol via a cost function when a discrepancy exists based on the comparing; selecting the template as a match candidate for the character symbol when the penalty value is below the threshold; recognizing the character symbol based on the selecting.
US09946942B2 Method, apparatus and system for biometric identification
Method and apparatus for processing a biometric measurement signal using a computing device, including receiving biometric measurement records associated with a first biometric measurement generated by contact with a single individual, extracting, for each of the biometric measurement records, feature data including periodic features extracted from the biometric measurement records, determining, pairing data comprising candidate pairs between the feature data and defined profiles associated with a known individual, wherein a candidate pair is associated with one of the periodic features and one of the defined profiles associated with the known individual, determining, for the candidate pair, a similarity value based on the one of the periodic features and the one of the defined profiles associated with the known individual, and determining whether a match exists between the single individual and the known individual based on a combination of the similarity values determined for the candidate pairs.
US09946941B2 Lane detection
This disclosure relates generally to lane detection, and more particularly to method and systems for lane detection. In one embodiment, a method for lane detection is includes generating an edge image including inbound edges of lane-markings corresponding to a road image. Based on an adaptive thresholding of intensity of lane-markings from image strips selected from the image, a plurality of lane masks are extracted. A plurality of valid lane masks are selected from the plurality of lane masks based on a structure and intensity information of the plurality of valid lane masks in the image strips. An overlap between the inbound edges and the valid lane masks is determined to identify a plurality of edge segments of the pair of inbound edges belonging to the lane-markings. A set of valid edge segments of the pair of inbound edges are obtained based on the curvature information of the edge segments.
US09946938B2 In-vehicle image processing device and semiconductor device
An in-vehicle image processing device capable of appropriately monitoring areas forward of, around, and rearward of a vehicle is provided at low cost. The device is for mounting on a vehicle and includes a camera, an image processing unit, and a determination unit. With a reflector provided in front of the camera, the camera can image, for display in a frame at a time, a first area forward of the vehicle and a second area, e.g. an area around the vehicle. In the image processing unit supplied with such image data from the camera, either the first-area image or the second-area image is appropriately processed whereas image processing is omitted for the other image. Alternatively, both images are subjected to a same image processing. The determination unit supplied with vehicle speed information supplies appropriate control instruction information based on the current vehicle speed to the image processing unit.
US09946935B2 Object tracking device, object tracking method, and object tracking program
Tracking candidate storage means 81 stores a plurality of candidates for one or more objects to be tracked. Control means 82 controls a likelihood of each of the plurality of candidates. The tracking candidate storage means 81 stores, for each of the plurality of candidates, label information identifying which object the candidate corresponds to, position information indicating a position of the object, and a likelihood. The control means 82 controls the likelihood of a candidate, according to the label information of one or more other candidates around the candidate determined based on the position information of the candidate.
US09946934B2 Semantic representation module of a machine-learning engine in a video analysis system
A machine-learning engine is disclosed that is configured to recognize and learn behaviors, as well as to identify and distinguish between normal and abnormal behavior within a scene, by analyzing movements and/or activities (or absence of such) over time. The machine-learning engine may be configured to evaluate a sequence of primitive events and associated kinematic data generated for an object depicted in a sequence of video frames and a related vector representation. The vector representation is generated from a primitive event symbol stream and a phase space symbol stream, and the streams describe actions of the objects depicted in the sequence of video frames.
US09946930B2 Apparatus and method for verifying the identity of an author and a person receiving information
Apparatus for identifying a person who wishes to receive information, where identifying information for each of a plurality of registered individuals is stored in a database, calls for capturing images of an individual requesting information, and determining whether this individual is the same as one of the registered individuals. The stored identifying information includes images of a unique, observable biologic identifier on a body portion of each registered individual. The specificity of the identification process is enhanced by storing registered examples of altered biological information in the database, by allowing the information provider to induce an alteration in a biologic identifier of a requesting person at the time of the request, and by comparing the altered requesting person information to stored information. Further identification enhancement is obtained by rapidly altering the visual environment of the requesting person, and by providing the requested information to the retina of the requesting person.
US09946929B2 Method of detecting boundaries of the human eye
A method of generating a reliable image of an iris for subsequent optical analysis leading to identification or authentication of a mammal. The method comprises directing point light sources towards the iris, capturing a gray scale image of the iris and reflections of the point light sources, deriving a two tone image from the gray scale image, generating an image containing the true boundaries of the pupil, determining boundaries of the iris and generating an image containing the true boundaries of the iris, and generating a final image of the iris from the image containing the true boundaries of the iris. This establishes a reliable image of the iris. The process may further comprise conducting an identification or authentication process based on optical analysis of the final image of the iris and comparison with a pre-established data corresponding to a person whose identity has been confirmed.
US09946927B2 Method and system for marking an object having a surface of a conductive material
The present invention describes a method for marking an object (18), the object (18) having a surface of a conductive material. The method comprises a step of applying an electric spark to the surface such that the material is at least one of partially melted and partially ablated by the electric spark, thereby forming a pattern on the object (18). Further, the present application relates to a marking system (10) for marking an object (18) using a spark generator (12) having a counter electrode (14) and a connector (16) for electrically connecting the spark generator (12) to the surface of the object (18) to be marked. Further, the present application relates to an authenticating system for authenticating or identifying an object (18) marked by the above described method for marking the object (18).
US09946925B2 Terminal device, output system and output method
A terminal device connected to one or more output devices via a network, includes an output destination distribution control unit that reads out an output destination of output data for which outputting is requested by a user from first information in which a condition for output data and an output destination are in correspondence with each other; and a confirmation screen display determining unit that refers to second information in which a user and an output destination that is previously selected by the user to distribute output data are in correspondence with each other, and causes, when the output destination read out from the first information is not in correspondence with the user in the second information, to display a confirmation screen of the output destination.
US09946921B2 Monitoring device, monitoring method and monitoring program
A monitoring device includes a crowd behavior analysis unit 21 and an abnormality degree calculation unit 24. The crowd behavior analysis unit 21 specifies a behavior pattern of a crowd from input video. The abnormality degree calculation unit 24 calculates an abnormality degree from a change of the behavior pattern.
US09946920B1 Sensing element and fingerprint sensor comprising the sensing elements
A fingerprint sensor is disclosed. The fingerprint sensor includes a substrate, a sensing electrode, a shielding plate, a first pair of conductive plates and an amplifier. The sensing electrode is configured to detect a capacitance in response to a touch event on the fingerprint sensor, and configured to selectively receive or not receive an input voltage. The shielding plate is configured to selectively receive the input voltage or is coupled to a reference voltage level. The first pair of conductive plates includes a first plate selectively coupled to the sensing electrode. The amplifier includes an inverting terminal coupled to a second plate of the first pair of conductive plates, and a non-inverting terminal to receive a voltage that is a fraction of the input voltage. The sensitivity of the fingerprint sensor is directly proportional to the input voltage.
US09946917B2 Efficient determination of biometric attribute for fast rejection of enrolled templates and other applications
A biometric input system includes: a biometric sensor, configured to generate a biometric image comprising features of an input biometric object; and a processing system, configured to receive the biometric image, generate a feature map from the biometric image, perform a distance transform on the feature map, and determine an attribute of the biometric image from the distance transform. The processing system is further configured to compare the determined attribute of the biometric image with corresponding attributes of enrolled biometric images, and, based on the comparison, to eliminate enrolled biometric images from a matching process for the biometric image, wherein the matching process is performed after the elimination and comprises comparison of the biometric image to remaining enrolled biometric images based on one or more attributes of the biometric image other than the determined attribute.
US09946916B2 Capacitive fingerprint sensor and sensing panel thereof
A capacitive fingerprint sensor and a sensing panel are provided. The capacitive fingerprinting sensor includes a sensing circuit, a level switch, an output switch. The sensing circuit has a first capacitor providing a sensing voltage according to a first sensing driving signal. A control terminal of the level switch is coupled to the sensing circuit to receive the sensing voltage, a first terminal thereof receives a high voltage level, and a second terminal thereof provides a sensing determination signal. A control terminal of the output switch receives a second sensing driving signal, a first terminal thereof is coupled to the second terminal of the level switch to receive the sensing determination signal, and a second terminal thereof is coupled to a data line. The sensing determination signal is provided through the level switch to avoid a parasitic capacitance on a trace influencing a voltage level of the sensing determination signal.
US09946913B2 Electronic device
An electronic device is disclosed herein and includes a multi-functional power button and a processor, where the multi-functional power button includes a power switch and a fingerprint recognition module. The fingerprint recognition module is combined on the power switch, and the processor is coupled to the multi-functional power button. The fingerprint recognition module is configured to extract a fingerprint feature information. The processor is configured to determine whether the multi-functional power button is pressed or touched to respectively cause the power switch to generate a switching signal or cause the fingerprint recognition module to extract the fingerprint feature information.
US09946911B2 Fast retrieval of information embedded in an image
A binary bit-string is encoded in a circular image. The circular image encodes substrings of the bit-string in sectors of the circular image and includes redundant bits, error correcting codes, and metadata pertaining to the encoding scheme. To encode the bit-strings, a circular image is generated that includes a center ring and a first ring. Outward from the first ring, additional rings represent bits in the bit-string according to the width of each ring. The exterior of the image includes an outer boundary ring. The width of the boundary rings is used to define the widths representing the value of each ring. To extract a bit-string from an image, the center of the circular image is identified and a direction is selected to evaluate the image outward, determining the boundaries of each ring. The boundaries are analyzed to determine the width of each ring and the encoded bit values.
US09946902B2 Method for preventing an unauthorized use of biprocess components
This invention provides a system and apparatus that is able to authenticate and prevent illegal manufacturing and unauthorized operation of disposable bioprocess components. This invention utilizes a ferro-electric random access memory chip (FRAM) chip to store error-correctable information on a RFID tag attached to the disposable bioprocess components, where the error-correctable information is written in sequence into the memory chip, so that the redundant information can remain in the chip when the RFID tag and disposable bioprocess component is gamma-sterilized. Also, this invention includes a method for authenticating the disposable bioprocess component that reduces liability in that a counterfeit poor quality disposable component is not used on the hardware so the user will not file an unjustified complaint.
US09946896B2 Attribute information provision method and attribute information provision system
A user attribute information provision system processes attribute information of users while preventing a leakage of attribute information. A provision apparatus: selects an apparatus group forming a communication path; generates information registration request in which information of a predetermined user is concealed in data recognizable only to a correspondent of the provision apparatus; and transmits the information registration request to an access destination solving apparatus via the apparatus groups. The access destination solving apparatus: stores the information of the user indicated by the information registration request and information of a correspondent provision apparatus; receives an inquiry request from an inquiry apparatus; and transfers the inquiry request by way of the correspondent provision apparatus as the user to the provision apparatus as the inquiry destination via the provision apparatuses in the communication path, thereby causing the provision apparatus to return the attribute information of the user to the inquiry apparatus.
US09946895B1 Data obfuscation
Sensitive data can be obfuscated before being provided for processing (i.e., aggregating, sorting, grouping, or transforming) using a pair of keys to generate a token that contains the sensitive data. The token can include a synthetic initialization vector, generated using a first key, and a ciphertext portion including the sensitive data encrypted under a second key. This tokenization can be performed by a data service or by an intermediate service that acts as an overlay or proxy for the underlying data service. The tokenized data can be provided for processing, and can remain tokenized until being received by an entity or system having access to at least the second key. A receiving entity with access to the second key can decrypt the ciphertext to obtain the plaintext, and if the first key is available the entity can perform a further integrity check on the tokenized data.
US09946894B2 Data processing method and data processing device
Provided is a data processing method in a data processing device that is connected to an external storage device and that is equipped with a storage device, the method including: receiving a writing instruction to store first data in the storage device; dividing the first data into multiple pieces of division data; storing at least one or more of the pieces of division data in the external storage device; and storing second data different from the first data in the storage device, in which the second data is associated with the first data and the multiple pieces of division data. With the data processing method, security in data management can be improved.
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