| Document | Document Title |
|---|---|
| US09871563B2 |
Electronic device for transmitting data by inductive coupling and intracorporeal current
In a general aspect, an electronic device can include a device configured to transmit data by intracorporeal current. The device configured to transmit data by intracorporeal current can include a first electrode configured to be capacitively coupled with a body of a user or capacitively coupled in an intracorporeal current conduction path of the electronic device. The electronic device can further include a circuit configured to electrically bias the first electrode. The circuit can include an electric coil arranged near the first electrode. The electric coil can be configured to, in response to an alternating-current (AC) signal, generate an alternating magnetic field having field lines incident on the first electrode. The field lines incident on the first electrode can induce a current in the first electrode, where the current induces an electric field that generates an intracorporeal current. |
| US09871556B2 |
Generator of phase-modulated UWB pulses
An ultra-wideband pulse generator for radio communication with phase modulation at frequencies of multiple gigahertz comprises an oscillator formed by a pair of intersecting differential branches that have two outputs connected to an LC resonant load. The transmission of a UWB pulse is caused by the application of a supply current to the differential pair over a few nanoseconds. Two current-injecting branches are respectively connected to the outputs S and S′. The control of phase modulation consists in applying an injection current to a single branch to unbalance the differential pair at the start of the generation of the UWB pulse. Depending on the side from which the injection current is applied, the oscillation at the carrier frequency will initiate with one phase or an opposite phase. |
| US09871555B2 |
Wireless communications method, user equipment, base station and system
Embodiments of the present disclosure provide a wireless communications method, user equipment, a base station and a system, and relate to the field of wireless communications. The method includes: acquiring a frequency domain spreading factor, a symbol-level spreading factor and a transmission time interval-level spreading factor; and performing frequency domain spreading, symbol-level spreading and transmission time interval-level spreading on first to-be-sent information respectively according to the acquired spreading factors and sending first spread information; or, despreading, according to the acquired spreading factors, second spread information sent by a base station. |
| US09871552B2 |
Transceiver arrangement, communication device, method and computer program
A transceiver arrangement comprises a receiver arranged for frequency-division duplex communication with a communication network; a transmitter arranged for frequency-division duplex communication with the communication network; a transmission port for connecting to an antenna or wire; a first filter connected between an output of the transmitter and the transmission port and arranged to pass signals at transmitter frequency and attenuate signals at receiver frequency; a transformer having a primary winding and a secondary winding, wherein the primary winding has one of its terminals connected to the transmission port; a second filter connected between another of the terminals of the primary winding and a reference voltage and arranged to attenuate signals at transmitter frequency and pass signals at receiver frequency; and an adaptive impedance circuit arranged to provide an adjustable resistance, connected between the output of the transmitter and the junction between the second filter and the another of the terminals of the primary winding, and arranged to provide a contribution from the transmitter to the primary winding such that a common-mode rejection of a contribution from the transmitter provided at the transmission port occurs at receive frequency. A communication device, a method of controlling a transceiver arrangement, and a computer program are also disclosed. |
| US09871551B2 |
Customizable protective case for portable electronic device
A protective case for a portable electronic device includes a rigid plastic frame bonded to a stretchable rubber cover and a back panel insert that can be removably inserted into a pocket in the rear of the stretchable rubber cover and plastic frame. To position a device in the case, the device is simply inserted into the front opening of the rigid plastic frame and stretchable rubber cover such that the edges of the stretchable cover stretch over the device and secure the device in the case. A variety of different removable back panels allow the stand to be easily reconfigured to include a stand for the device case, a pocket adapted to hold payment cards, a folding style wallet, a mirror or a fabric covering. |
| US09871550B2 |
Protective enclosure for an electronic device
A protective enclosure for an electronic device includes a cushion layer and a structural layer. The cushion layer covers the back surface and side surfaces of the installed electronic device. The structural layer is disposed over the cushion layer and includes a back portion, a right side portion, and a left side portion. The structural layer includes a thinned region on the back portion. The thinned region has a thickness that is less than the thickness of the remainder of the back portion of the structural layer. The thinned region of the structural layer allows a section of the protective enclosure to bend away from the back surface of the electronic device for installation and removal of the electronic device from the protective enclosure. |
| US09871544B2 |
Specific absorption rate mitigation
Specific Absorption Rate (SAR) mitigation techniques are described herein. In one or more embodiments, a host device is configured to implement a SAR mitigation algorithm to maintain compliance with regulatory requirements. The SAR mitigation algorithm may be configured to control radio frequency transmissions (e.g., output levels) for one or more antennas of the host device based at least in part upon an arrangement of an accessory device relative to the host device. By so doing, the SAR mitigation algorithm accounts for adverse influences that accessory devices may have upon radio frequency (RF) emissions from the antennas in some arrangements. The SAR mitigation algorithm may be further configured to account for user presence indications along with accessory device arrangements and adapt transmission power levels accordingly. |
| US09871543B2 |
Miniature acoustic resonator-based filters and duplexers with cancellation methodology
A cancellation-based filter may have at least one frequency pass band and at least one frequency stop band. The cancellation-based filter may include a first group of one or more band pass filters, each having at least one acoustic resonator, the first group providing at least one frequency pass band for the cancellation-based filter; at least one hybrid coupler; and a second group of one or more band pass filters, each having at least one acoustic resonator, the second group coupled to at least one of the at least one hybrid couplers, wherein the at least one hybrid coupler and the second group of one or more band pass filters interact to provide at least one frequency stop band for the cancellation-based filter. |
| US09871542B2 |
Noise canceller device
A noise canceller device for removing interference signals from other systems and improving communication quality of a desired signal is provided. The noise canceller device comprises a first calculation unit performing cross-correlation processing on interference signals received by sub-antennas, a first peak detection unit detecting peaks of the interference signals, a first information acquisition unit acquiring first interference signal information, a composition unit composing the interference signals, a second calculation unit performing correlation processing between a signal received by a main antenna and the composed interference signal, a second peak detection unit detecting a peak of the composed interference signal, a second information acquisition unit acquiring second interference signal information, an interference signal replica generation unit generating an interference signal replica, and a removal unit subtracting the interference signal replica from the received signal by the main-antenna. |
| US09871539B2 |
Driver circuit for signal transmission and control method of driver circuit
A driver circuit for receiving a data input and generating an output signal to a termination element according to at least the first data input is provided. The driver circuit includes a first output terminal, a current mode drive unit and a voltage mode drive unit. The current mode drive unit is arranged for selectively outputting a first reference current from the first output terminal to the termination element according to the first data input, and selectively receiving the first reference current through the first output terminal according to the first data input. The voltage mode drive unit is arranged for coupling one of a first reference voltage and a second reference voltage different from the second reference voltage to the first output terminal according to the first data input. |
| US09871538B2 |
Method and apparatus for adjusting peak power capability
One of the embodiments of the present disclosure relates to a method for adjusting peak power capability of a power amplifier circuitry. The power amplifier circuitry comprises at least one main amplifier path and at least one peak amplifier path and is configured to output a signal combining amplified signals from the at least one main amplifier path and the at least one peak amplifier path. The method comprises calculating a PAPR of an input signal of the power amplifier circuitry; determining at least one configuration parameter of the at least one peak amplifier path depending upon the calculated PAPR of the input signal; and configuring the at least one peak amplifier path based on the determined at least one configuration parameter, thereby adjusting the peak power capability of the power amplifier circuitry. The present disclosure also relates to corresponding apparatus and wireless communication devices. |
| US09871536B1 |
Encoding apparatus, encoding method and search method
A computer generates a plurality of pieces of syntax information respectively corresponding to a plurality of words in a compression target document by analyzing relationships between the plurality of words. Next, the computer assigns a plurality of compression codes to the plurality of words and to the plurality of pieces of syntax information. Then, the computer outputs the plurality of compression codes with an arrangement of a specific order. |
| US09871531B1 |
Non-geometric scaling current steering digital to analog converter
Aspects of the present disclosure include a digital-to-analog converter (DAC). The DAC includes an output node and a plurality of equal sized cell transistors. Each of the plurality of equal sized cell transistors represents a distinct bit, the distinct bits including a least significant bit (LSB). The plurality of equal sized cell transistors are connected to the output node. The DAC includes at least one control circuit configured to modify a back gate voltage of one of the equal sized cell transistors representing the LSB to adjust a current output. |
| US09871529B1 |
Asynchronous SAR ADC with conversion speed control feedback loop
Systems and circuits for feedback control of an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) are described. An example system includes the asynchronous SAR ADC. A timing detector circuit is coupled to the asynchronous SAR ADC to receive one or more internal signals from the asynchronous SAR ADC. The timing detector circuit outputs a timing detector signal representing an internal timing of the SAR ADC. The timing detector signal is generated based on the one or more internal signals. A regulator circuit is coupled to the timing detector circuit to receive the timing detector signal. The regulator circuit is also coupled to the asynchronous SAR ADC to output a feedback signal to the asynchronous SAR ADC. The feedback signal is generated based on the timing detector signal to control the internal timing of the SAR ADC to match a target timing. |
| US09871526B2 |
Semiconductor device and electronic device including analog/digital converter
Noise in a semiconductor device including a photo sensor is reduced. The semiconductor device includes an analog/digital converter and a photo sensor including a photodiode. The analog/digital converter includes an oscillation circuit and a counter circuit. A first signal output from the photo sensor is input to the oscillation circuit. The oscillation circuit has a function of outputting a second signal obtained by a change in oscillation frequency of the first signal. The counter circuit has a count function by which addition or subtraction is performed by a control signal with the second signal used as a clock signal. The counter circuit performs subtraction during the reset operation of the photo sensor. The counter circuit performs addition during the selection operation of the photo sensor. Thus, the output value of the analog/digital converter can be corrected. |
| US09871524B2 |
Integrated circuit and cable assembly including the same
An integrated circuit embedded in a plug of a universal serial bus (USB) 3.1 type-C cable assembly is disclosed. The integrated circuit includes a first pin connected to an operation transmission line through which an operation voltage is transmitted, a second pin connected to a configuration channel (CC) line, a first resistor connected to the first pin, a ground line, and a switching circuit configured to connect the first resistor and the ground line using a channel voltage supplied to the second pin when the operation voltage is not applied, and disconnect the first resistor from the ground line based on the operation voltage. |
| US09871521B2 |
Level shifting circuit, apparatus and method of operating the same
A level shifting circuit includes an input circuit, a leakage divider circuit, a skew inverter circuit and a buffering circuit. The input circuit has an input terminal configured to receive an input voltage. The input circuit is configured to receive a first voltage and a second voltage. The leakage divider circuit is configured to receive a third voltage. The leakage divider circuit is connected to the input circuit. The skew inverter circuit is configured to receive the third voltage. The skew inverter circuit is connected to the leakage divider circuit and the input circuit. The buffering circuit has a terminal configured to output an output voltage. The buffering circuit is connected to an output terminal of the skew inverter circuit. The level shifting circuit is free of capacitors. |
| US09871518B2 |
Memory interface circuit capable of controlling driving ability and associated control method
A memory interface circuit includes a first variable impedance circuit coupled between a first supply voltage and a pad, and a second variable impedance circuit coupled between a second supply voltage and the pad; wherein when the first supply voltage changes, at least one of the first variable impedance circuit and the second variable impedance circuit is controlled to have different setting in response to the changing of the first supply voltage. |
| US09871516B2 |
Transmitting apparatus with source termination
In one embodiment, an apparatus for transmitting a signal with an improved termination is disclosed. The apparatus includes a driver to generate a differential mode signal superimposed on a common mode signal at a differential driver output of the driver. The differential driver output includes a first driver output and a second driver output. The apparatus also includes a termination circuit coupled between the first driver output and the second driver output. The termination circuit includes a capacitor connected to a node. The termination circuit also includes a first resistor and a first inductive element coupled in series between the first driver output and the node. In addition, the termination circuit includes a second resistor and a second inductive element coupled in series between the second driver output and the node. |
| US09871514B1 |
Methods and apparatus for continuous current limiting for FETS in high inductive load systems
An apparatus includes a FET device having a drain terminal, source terminal and a gate terminal; a first supply voltage coupled to the drain terminal of the FET; an output terminal coupled to the source terminal of the FET; a bias current supply coupled to the gate terminal of the FET; a second supply voltage coupled to the gate terminal of the FET; a current sensing circuit coupled to output a sense current proportional to the current flowing through the FET; a current limit comparator coupled to the sense current and comparing the sense current to a predetermined limit current; a pull down current circuit coupled to remove current from the gate terminal of the FET; a current time derivative circuit coupled to the sense current and outputting a sense rate current; and a circuit coupled to receive the sense rate current and coupled to the bias current supply. |
| US09871513B2 |
Semiconductor device
In activating a motor, a gate voltage with which a power semiconductor element may supply a rush current of the motor is generated by a charge pump circuit, when a certain time (time until the rush current ends) has elapsed after activating the motor, a timer circuit operates a gate clamp circuit, which reduces the gate voltage of the power semiconductor element to reduce the current-carrying capability of the power semiconductor element. Subsequently, when the motor has caused a short-circuit failure, the power semiconductor element, because its gate voltage is reduced by the gate clamp circuit in advance, supplies only a load short current corresponding to the reduced gate voltage. Accordingly, the heat generation due to the short-circuit current is also small and an increase in temperature is also suppressed. |
| US09871512B2 |
Switch stand-by mode isolation improvement
Systems, apparatuses and methods are disclosed providing a semiconductor die comprising a semiconductor substrate and a radio-frequency (RF) switch including one or more series field-effect transistors (FETs) and one or more shunt FETs, each of the one or more series FETs and one or more shunt FETs having a respective gate node, the RF switch being configured to receive an RF signal from a power amplifier module and provide the RF signal to an antenna. The semiconductor die may further comprise an internal regulator voltage source configured to provide an internal regulator voltage when the RF switch is in a stand-by mode and shunt arm control circuitry configured to provide the internal regulator voltage to the gate nodes of the one or more shunt FETs when the RF switch is in the stand-by mode. |
| US09871507B1 |
Generating an overdrive voltage for power switch circuitry
Techniques are disclosed relating to generating an overdrive voltage for power switch circuitry. In some embodiments, the value of the overdrive voltage is adjusted dynamically in order to reduce leakage current during power gating. In some embodiments, an apparatus includes a power switch circuit element configured to gate power to circuitry in the apparatus based on a control signal. In some embodiments, the power switch circuit element is powered by a supply voltage. In some embodiments, the apparatus also includes control circuitry configured to generate the control voltage at a different voltage level than the supply voltage, based on comparison of leakage current of ones of a plurality of replicas of the power switch circuit element. In some embodiments, the replicas are configured to receive different reference voltages as respective replica control signals. In various embodiments, the disclosed techniques may generate overdrive voltages that reduce leakage current during power gating. |
| US09871506B2 |
Switchable decoupling capacitors
Aspects of an integrated circuit are disclosed. The integrated circuit includes a first circuit configured to be powered by a first voltage source, a second circuit configured to be powered by a second voltage source, a decoupling capacitor, and a controller configured to switch the decoupling capacitor between the first and second voltage source. |
| US09871503B2 |
Semiconductor integrated circuit, latch circuit, and flip-flop circuit
A semiconductor integrated circuit connected between a first node and a second node includes first to fourth transistors. When a signal at the second node changes, the fourth transistor is turned on, and a potential obtained by shifting a third potential by the threshold of the fourth transistor is applied to the gate of the second transistor. |
| US09871498B2 |
RF interference choke device and RF testing apparatus incorporating the same
A radio frequency (RF) interference choke device includes a planar dielectric board formed with two first slots and two second slots that extend in a lengthwise direction of the dielectric board. The first/second slots are arranged symmetrically about a central line of the dielectric board parallel to the lengthwise direction, and have a first/second length associated with a first/second frequency band. A metal layer is attached to the dielectric board, and has a U-shaped first pattern surrounding the first slots, a U-shaped second pattern surrounding the second slots, and a strip-shaped third pattern extending along the central line and interconnecting the first and second patterns. |
| US09871494B2 |
Operational amplifier with class AB output
An operational amplifier includes an output stage, an input stage, a first auxiliary amplifier, and a second auxiliary amplifier. The output stage includes a first output transistor and a second output transistor. The input stage is configured to drive the output stage. The first auxiliary amplifier is coupled to an output of the input stage and to an input of the first output transistor. The first auxiliary amplifier is configured to bias the first output transistor for class AB operation and to isolate the input stage from a bias voltage applied to the first output transistor. The second auxiliary amplifier is coupled to the output of the input stage and to an input of the second output transistor. The second auxiliary amplifier is configured to bias the second output transistor for class AB operation, and to isolate the input stage from a bias voltage applied to the second output transistor. |
| US09871486B2 |
Inverter system
An inverter system includes: an inverter configured to receive utility AC power and step it up to a high-voltage power necessary for operation of a motor and supply the high-voltage power to the motor; a switch connected between the inverter and the motor and configured to be turned on and off such that an output voltage from the inverter is supplied to the motor or interrupted; a current detector configured to detect an output current from the inverter; and a controller configured to control the inverter system so that the inverter is interrupted if an output current value detected by the current detector is smaller than a predetermined reference current value for more than a predetermined reference duration. |
| US09871483B2 |
Controller for rotary electric machine drive apparatus
There is provided a controller for a rotary electric machine drive apparatus capable of reducing data-processing load and amount of memories required for a data processing which calculates a voltage command value of the converter which reduces power loss. A controller calculates the required minimum voltage which is required in the case of performing a maximum torque/current control is calculated; calculates a converter loss coefficient which is a coefficient of a polynomial representing a power loss characteristic of the converter; calculates an inverter loss coefficient which is a coefficient of a polynomial representing a power loss characteristic of the inverter; calculates a sum total of loss coefficients for each order of polynomials; calculates the low loss voltage which the sum total power loss becomes a minimum, based on the sum total loss coefficients for each order; sets to the voltage command value of the converter. |
| US09871468B2 |
Vibration-type driving device
A vibration-type driving device according to the present invention includes a plurality of vibrators in which contact portions perform an elliptical motion using a combination of vibrations in different vibration modes; and a driven object having contact regions that come into contact with the contact portions and move relative to the plurality of vibrators, wherein the contact regions for the individual vibrators differ in position so as not to overlap. |
| US09871467B2 |
Resonant converters including flying capacitors
Unique systems, methods, techniques and apparatuses of zero-voltage transition pulse width modulation resonant converters are disclosed. One exemplary embodiment is a zero-voltage transition PWM resonant converter comprising a DC bus, a first switching device, a second switching device, a resonant tank circuit, an auxiliary circuit having a flying capacitor and a plurality of auxiliary switching devices, and a controller. The controller is structured to control the first switching device, the second switching device, and the plurality of auxiliary switching devices to provide resonant operation of the tank circuit effective to provide a substantially zero voltage condition across the first switching device when turning the first switching device on or off and to provide a substantially zero voltage condition across the second switching device when turning the second switching device on or off. |
| US09871466B2 |
Inverter switching frequency control method and apparatus
An inverter control method, apparatus, and system are provided. The method in the embodiments of the present invention includes obtaining power distribution line graph of an inverter switch according to an output power and an input voltage that are of an inverter; when an area to which the inverter belongs is a first area and the inverter switch works at a second frequency, switching the inverter switch to a first frequency; and when the area to which the inverter belongs is a second area and the inverter switch works at the first frequency, switching the inverter switch to the second frequency. In the embodiments of the present invention, whether a working frequency of an inverter switch needs to be changed is determined according to an output power and an input voltage, which improves control efficiency, thereby effectively improving conversion efficiency of an inverter. |
| US09871462B2 |
Regenerative variable frequency drive with auxiliary power supply
A regenerative variable frequency drive includes an active converter connected to a DC bus that is connected to a first inverter that converts DC power to variable frequency, three phase AC power, and variable frequency, three phase AC power to DC power, and to a second inverter that converts DC power to three phase AC sine wave power. The converter converts single phase AC power to DC power and DC power to single phase AC power, and maintains a selected voltage on the DC bus. The converter has an active rectifier and a controller that drives the rectifier with a pulse width modulation according to a hybrid voltage switching scheme that switches the rectifier according to a unipolar voltage switching scheme through most of each cycle and switches the rectifier according to a bipolar voltage switching scheme around each zero crossing. |
| US09871458B2 |
Resonant rectifying device, control method and apparatus for resonant rectifying
A resonant rectifying device includes a transformer having a primary winding and a secondary winding, a primary-side circuit coupled to the primary winding of the transformer, and a secondary-side circuit coupled to the secondary winding of the transformer. The primary-side circuit includes a first field effect transistor (FET) and a second FET coupled in series between a voltage source and a ground, a capacitor, and an inductor. A first side of the capacitor is coupled to a point between the first and the second FETs. A second side of the capacitor is coupled to a first end of the inductor and one end of the primary winding. A second end of the inductor is coupled to the ground. The secondary-side circuit includes a third FET and a fourth FET coupled to a first end and a second end of the secondary winding, respectively. |
| US09871456B2 |
Voltage conversion device and method of operation
A voltage conversion device includes a transformer and at least one transistor. The transformer has a primary side and a secondary side, the secondary side being couplable to a load. The output voltage of the voltage conversion device is coupled across the load. The at least one transistor is coupled to the primary side of the transformer and regulates the output voltage of the voltage conversion device. The output voltage is partially a function of the duty cycle of the at least one transistor. The switching frequency of the at least one transistor is decreased in response to a transient increase in load current. |
| US09871453B2 |
Control circuit and method of a power converter
A feedback signal stabilized by a capacitor and related to an output voltage of a power converter is used to acquire the output power information of the power converter, and a control circuit uses a second clock not related to the switching frequency of the power converter to count a duration time of the feedback signal being higher than a threshold. When the duration time is higher than a preset time, an abnormal output power of the power converter is distinguished and the power converter will be turned off. The feedback signal will not vary severely even if the output terminal of the power converter is interfered, and the counted duration time will not be influenced when the switching frequency is changing caused by a load changing. |
| US09871452B2 |
Transformer, flyback converter and switching power supply with the same
A flyback converter can include: a power switch controlled to be turned on/off to control a current through a primary side; a first primary winding coupled between an input terminal and a first terminal of the power switch, where a dotted terminal of the first primary winding is coupled to a first terminal of the power switch; a second primary winding coupled between a second terminal of the power switch and a primary grounding terminal, where a dotted terminal of the second primary winding is coupled to the primary grounding terminal; a secondary winding configured between the first and second primary windings in a radial direction of a magnetic core, where the first primary winding, the second primary winding, and the secondary winding are wound around the magnetic core; and a secondary rectifier and filter circuit coupled with the secondary winding, and configured to generate a stable current/voltage. |
| US09871451B2 |
Systems and methods for voltage control and current control of power conversion systems with multiple operation modes
System and method for regulating a power conversion system. A system controller for regulating a power conversion system includes an operation-mode-selection component and a driving component. The operation-mode-selection component is configured to receive a first signal related to an output load of the power conversion system and a second signal related to an input signal received by the power conversion system and output a mode-selection signal based on at least information associated with the first signal and the second signal. The driving component is configured to receive the mode-selection signal and generate a drive signal based on at least information associated with the mode-selection signal, the driving signal corresponding to a switching frequency. |
| US09871450B2 |
Isolated step-up converter
An isolated step-up converter having first and second stages is described herein. The second stage can provide either DC or AC output based on the various topologies described. Resonance inductors and capacitors are used and tuned to a commutation frequency in some embodiments. Capacitors and inductors are also used in the first stage. |
| US09871449B2 |
Multiphase DC/DC converter with coupling inductors
A two-phase DC/DC converter includes, as an inductor array, a pair of inductors to which a DC input voltage is alternately applied with a phase difference of about 180 degrees through switching control of switching devices. A duty ratio is substantially in a range from 5% to 40%, and a coupling factor between the inductors is substantially in a range from −0.4 to −0.1. With this configuration, ripple current in the inductors can be made to be smaller than in the case in which there is no coupling between the inductors even when the duty ratio considerably varies. |
| US09871447B2 |
DC-DC converter
Provided is a DC-DC converter implemented in a small area with a fast transient response. The DC-DC converter includes: a power supply unit configured to supply an input voltage; an inductor connected between an output terminal where an output voltage is outputted and the power supply unit; an emulator connected to both ends of the inductor to generate a feedback voltage; and a control circuit configured to control the power supply unit through a time domain control based on the output voltage and the feedback voltage. |
| US09871446B2 |
Current mode control regulator with load resistor emulation
A current mode control regulator including a control circuit and a current generator. The control circuit regulates an output voltage based on a reference voltage using current mode control. The current generator applies an adjust current to a feedback current signal, in which the adjust current is proportional to a difference between a voltage indicative of the output voltage and the reference voltage to emulate an AC load resistance at an output of the current mode regulator. A load resistor emulator emulates an AC load resistor to increase the phase margin of current mode control regulator when operating without a battery coupled to the output, such as when the battery is physically removed or otherwise electrically disconnected. Operation is not substantially changed when the battery is connected, so that the desired phase margin is achieve with or without the battery. |
| US09871443B2 |
Power control circuit for setting triggering reference point of over current protection scheme
A power control circuit is provided, which includes a pin and a current source. The current source is electrically coupled to the pin and provides a reference current to the pin to generate a set voltage. The set voltage increases along with time after the current source provides the reference current to the pin. The power control circuit activates an over current protection scheme according to the set voltage. |
| US09871442B2 |
Zero-offset voltage feedback for AC power supplies
A high voltage AC measurement method and circuit is disclosed to measure with zero offset and mirrored distortion based on hybrid chopping and fully differential signal path. There is a scheme with hybrid chopping and dual mixed signal paths. It applies high frequency chopping to the voltage measurement signal before the low-voltage signal conditioning, then samples and converts it to digital with two simultaneous ADCs, and finally demodulate the chopped signal by software. This technique not only reduces DC errors and drift but also cancels the distortion asymmetry caused by ADC non-linearity. The resultant DC accuracy and resolution can be significantly smaller than 1 LSB. |
| US09871441B2 |
Current feedback method, current feedback circuit, driving circuit and switching power supply thereof
In one embodiment, a current feedback circuit can include: (i) a first current mirror circuit having an input terminal coupled to a source of a main power transistor of a switching power supply, and a control terminal configured to receive a PWM control signal, the first current mirror circuit being configured to generate a first mirror current; (ii) the first current mirror circuit and the main power transistor being on such that an output sampling current flows through the first current mirror circuit and the main power transistor when the PWM control signal is active; and (iii) a second current mirror circuit configured to generate an output feedback current that is in a predetermined direct proportion with the output sampling current, and is generated in accordance with the first mirror current. |
| US09871437B2 |
Fault current reduction structure of multi-level converter and apparatus using the fault current reduction structure
Provided are a multi-level converter having more than one converter arm in which a plurality of sub-modules are connected in series, multi-level converter comprising, a first bypass circuit connected in parallel to at least one sub-module included in more than one converter arm on a first side and including a first switching device, a second bypass circuit connected in parallel to more than one converter arm on a second side and including a diode, a second switching device included in more than one converter arm and having a first end connected in series to at least one sub-module and a second end connected to a first end of first bypass circuit at a single node and a third switching device included in more than one converter arm and having a first end connected in series to at least one sub-module and a second end connected to a first end of second bypass circuit at a single node. |
| US09871431B2 |
Spintronic generator
A spintronic generator that provides electrical power with the motive force of natural electron spin. The utilization of natural electron spin can be enhanced with carefully matched materials, weights, and magnetic waveforms which provide precise pulsed frequencies in resonance with the materials. This resonance of the magnetic pulses provides clean abundant power. A utilization of the Zero Point Energy results in a local environment temperature drop which can be one of the sources of motive force. The harvesting of electricity can be in standard induction pick up coils controlled by direct current motor controllers using an LRC tank circuit. |
| US09871426B1 |
Electrical machine with reduced windage
A rotating machine has a shaft rotatable about an axis, a rotor rotatable with the shaft, and a rotor end winding at an axial end of the rotor. A stator is spaced from the rotor and forms a gap therebetween. The stator comprises a stator winding. A fluid system directs fluid through to the stator. A baffle to diverts fluid away from the gap and toward the stator. |
| US09871425B2 |
Electric machine
An electric machine includes a housing which accommodates a stator and a rotor rotationally supported about an axis of rotation, and has a front/rear air inlet opening on a top face and an air outlet opening therebetween. A front/rear air conveying element draws into the air inlet openings air which is discharged from the air outlet opening during operation. A cooler is mounted on the top face of the housing, covering the air inlet openings and the air outlet opening in a hood-like manner, such that discharged air is fed back to the air inlet openings. The cooler has a front/rear partition arranged between the air outlet opening and the corresponding air inlet opening and extending upward from the top face. Air guiding elements are arranged in the housing and/or in the cooler for feeding discharged air at least partially to the respective other air inlet opening. |
| US09871421B2 |
Split-core type motor and method of manufacturing armature of split-core type motor
A split-core type motor makes work for connecting lead wires of split coils simple and efficient and reduces manufacturing costs and time taken to connect wires is realized. The split-core type motor includes a plurality of split coils formed by winding coils on split cores on which insulating members have been mounted; a stator formed by disposing the plurality of split coils in an annular shape; crimp terminals that connect lead wires of the split coils by being crimped so that the lead wires of the split coils correspond to a u phase, a v phase, and a w phase of a three-phase AC power source, and form terminals corresponding to the u phase, the v phase, and the w phase, respectively; and a resin mold part that covers the coils and the lead wires while power line connecting portions of the crimp terminals are exposed to the outside. |
| US09871419B2 |
Rotor of permanent-magnet embedded motor, and compressor, blower, and refrigerating/air conditioning device using the rotor
A rotor of a permanent-magnet embedded motor includes a rotor core having magnet insertion holes along a circumferential direction and a magnet inserted into each of the holes, wherein a gap is formed at opposite ends of a hole at a time of inserting the magnet therein, an outer peripheral face of the core is formed by a first curved surface formed from a magnetic pole center to between poles, with a radial distance from a shaft center of the core being largest at the pole center on the peripheral face, and a second curved surface formed from an interpolar portion toward the pole center to intersect with the first curved surface, with the radial distance from the shaft center being smallest in the interpolar portion on the peripheral face, and wherein a length of the first curved surface is larger than a length of the second curved surface. |
| US09871418B2 |
Sensorless electric machine
A rotor component that comprises a rotor circuit configured for use with either an interior permanent magnet (IPM) machine or a synchronous reluctance machine (SRM) that includes a pole circuit made of a conductive, non-magnetic material and has a midpoint that substantially aligns with a d-axis of the IPM or SRM. An electric machine with a similar rotor component therein or having a loop or ring of a conductive, non-magnetic material that is substantially concentric about a d-axis of the electric machine. |
| US09871416B2 |
Resonant type high frequency power supply device
A resonant type high frequency power supply device provided with a power semiconductor element that performs a switching operation at a high frequency exceeding 2 MHz, the resonant type high frequency power supply device including a variable inductor that makes an adjustment to the amplitude of a device output voltage. |
| US09871415B2 |
Transferring power to a mobile device
Embodiments of the disclosure may include a system for transferring power, the system having a donor mobile device. Such a donor mobile device may include processor(s) and a donor wireless power transfer mechanism coupled to the processor(s). In addition, the donor mobile device may include software application(s) that: (i) configure the donor wireless transfer mechanism on the donor mobile device to initiate power transfer; and (ii) transfer power using the donor wireless transfer mechanism. The system may also have a receptor mobile device including processor(s) and a receptor wireless power transfer mechanism coupled to the processor(s). Further, the receptor mobile device may include software application(s) that: (i) configure the receptor power transfer mechanism on the receptor mobile device to receive power; and (ii) receive and convert received power into electric current using the receptor power transfer mechanism. |
| US09871409B2 |
LPS architecture for UPS systems
According to one aspect, embodiments herein provide a UPS comprising a transformer including a first primary winding configured to be coupled to a DC source, a second primary winding configured to be coupled to an AC source, and at least one secondary winding, control logic, and at least one output line, wherein the control logic is configured, in a first mode of operation, to enable the first primary winding to generate, based on power received from the DC source, a first output voltage at the at least one output line, and to disable the second primary winding, and wherein the control logic is configured, in a second mode of operation, to enable the second primary winding to generate, based on power received from the AC source, a second output voltage at the at least one output line, and to disable the first primary winding. |
| US09871408B2 |
Distributing power between data centers
A data center operable using only electric power based on renewable energy. The data center includes at least one device driven by the electric power, a storage battery for storing the electric power, and a controller for switching the operating mode of the device over the course of time on the basis of predicted values for the amount of electric power generated using renewable energy, the amount of electric power stored in the storage battery, and the amount of electric power consumed by the device. |
| US09871405B2 |
Voltage regulating circuit
Disclosed is a voltage regulating circuit, comprising an input end, an output end, a protecting switch, a first switch, a second switch, a third switch, a first coil and a second coil. The third switch comprises a first terminal and a second terminal. The second terminal of the third switch is connected to a third terminal of the first switch. One end of the first coil is connected to a second terminal of the first switch, and the other end of the first coil is connected to a third terminal of the first switch. One end of the second coil is connected to a first terminal of the third switch, and the other end of the second coil is connected to a fourth terminal of the protecting switch. Different connections between switches and the transformer provide various voltage adjustments to reduce power loss and to increase power transformation efficiency. |
| US09871403B2 |
Power feeding apparatus for solar cell, and solar cell system
A power feeding apparatus for solar cells has: a voltage regulator, i.e., a voltage adjusting unit; a relay, i.e., a switch unit; and a control unit. The voltage regulator executes voltage adjustment with respect to an input voltage, and outputs, to a power output terminal, a voltage adjusted to a previously set voltage or lower. The relay is provided on a bypass line that is connected between a power input terminal and the power output terminal without having the voltage regulator therebetween, and the relay performs switching such that the bypass line is connected or interrupted. In the cases where the input voltage is equal to or lower than the predetermined voltage, the control unit performs control such that the bypass line is connected by means of the relay, and the input voltage is outputted from the power output terminal. |
| US09871401B2 |
Method and apparatus for controlling low-voltage battery charging
A method for controlling low-voltage battery charging may include determining a state-of-charge (SOC) of a low-voltage battery based on a voltage of the low-voltage battery. A base charging voltage is set according to the SOC of the low-voltage battery. A charging voltage of the low-voltage battery is set based on the base charging voltage, a vehicle operation mode, and a SOC of a high-voltage battery. |
| US09871396B2 |
System and method for controlling charge of an energy storage device from a renewable energy source
Systems and methods for controlling the charge of an energy storage device include determining an estimated energy production prediction for an energy source from a present time to a target time by which an energy storage device is desired to reach a top of charge (TOC) energy level when being charged by the energy source. An available amount of energy for storage at the energy storage device if the energy storage device is charged from the energy source at a first charge rate from the present time until the target time is determined. A present charge rate for the energy storage device is controlled to be the first charge rate when the available amount of energy is less than the energy storage capacity of the energy storage device and to be a second charge rate less than the first charge rate when otherwise. |
| US09871394B2 |
System and method for discharging a thyristor-switched capacitor
There are provided methods, devices, and systems relating to discharging thyristor-switched capacitors. For example, there is provided a method for discharging the capacitors of a thyristor-switched capacitor (TSC) device coupled to a transmission line. The method includes determining whether an angle of a voltage on the transmission line is within a threshold angle. Further, the method can include operating the device in a discharging mode when the angle is within the threshold angle and the threshold angle is in a predetermined set of threshold angles. |
| US09871389B2 |
Battery pack
A battery pack in the present disclosure comprises: a battery; a switching element that is provided in a discharge path from the battery to an external load and that is configured to complete or interrupt the discharge path; a control circuit that operates by receiving a supply of an electric power from the battery, that conducts an electric current through the switching element so as to allow discharge from the battery to the external load, and upon occurrence of an abnormality in the battery or the external load during the discharge, that interrupts the switching element so as to inhibit the discharge from the battery to the external load; and a protection circuit that monitors an operating condition of the control circuit and that interrupts the switching element when the control circuit is inoperative. |
| US09871382B2 |
Method and controller for continuously operating a plurality of electric energy generating machines during a high voltage condition
A method and a controller for continuously operating a plurality of electric energy generating machines during a high voltage condition at a point of common coupling of the plurality of electric energy generating machines are provided herein. The method includes a) sensing a voltage level at the point of common coupling exceeding a permitted voltage level; b) curtailing an active power output of the plurality of electric energy generating machines such that a reactive capability of the plurality of electric energy generating machines is increased; c) establishing a set point of an electric quantity being present at the point of common coupling such that a reactive electric component providable by the electric energy generating machines is increased; and d) controlling an electric energy generating machine based on the set point of the electric quantity such that the high voltage condition at common coupling is at least partially remedied. |
| US09871380B1 |
Methods and apparatus to protect solar power plants
A method and apparatus is disclosed that can monitor the solar power inverters in real-time both day and night, and generate surveillance alarms and actions when a solar power inverter is removed or disconnected from the AC powerline for unknown reasons. It offers a low cost and reliable surveillance means to help guard a residential-scale, commercial-scale, or utility-scale solar power system in real-time at all times. |
| US09871378B2 |
Paralleling module for a generator system
A power management system that includes a first enclosure and a second enclosure. A first generator is inside the first enclosure and a second generator is inside the second enclosure. The power management system further includes a paralleling enclosure and a paralleling module inside the paralleling enclosure. The paralleling module electrically connects the first generator to the second generator without opening the paralleling enclosure. The first generator includes an engine and an alternator. A first contactor is powered by the alternator to close the first contactor in order to provide an electrically conductive path from the alternator to an output. The second generator includes an engine and an alternator. A second contactor is powered by the alternator to close the contactor in order to provide an electrically conductive path from the alternator to the output. |
| US09871377B2 |
Device and method for cooperation control of EMS and DMS
The device for cooperation control of the EMS and the DMS comprises: a calculation unit for calculating an AQI index on the basis of target system information and power flow calculation data; a determination unit which determines whether or not to perform reactive power cooperation control switching of the DMS on the basis of the calculated AQI index and the amount of needed local reserve reactive power (Qreq), and which determines a suppliable reactive power capacity on the basis of the amount of needed local reserve reactive power (Qreq) and a suppliable reactive power range; and a control unit which transmits a cooperation control mode switching control signal so as to switch the DMS to a reactive power cooperation control mode if it is determined that reactive power cooperation control switching of the DMS is to be performed, and which controls the DMS to supply reactive power. |
| US09871376B2 |
Time based global optimization dispatching method
The invention provides a global optimization and dispatching method based on time scales. The method uses a target value system and a dispatch model. The global optimization and dispatching method takes input from the results from a variety of subtopics. The methods provide adjustment and optimization in accordance with the time scales that are given in the sub goal of each sub topic: long-term, mid-long-term, short-term, ultra short term and real time optimization. Smart distribution grid can improve operational efficiency, integrated application of new elements in the distribution network of distribution energy network, micro grid, energy storage device and non-linear loads. This invention is fully adapted to the smart grid trends, with a good prospective. |
| US09871373B2 |
Electrical overstress recording and/or harvesting
Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event. |
| US09871362B2 |
Electrical junction box
An electrical junction box including an upper case half having at least a first upper cable passage port, the upper case half opening forwardly and being rearwardly chamfered; a lower case half having at least a first lower cable passage port, the lower case half opening forwardly and being rearwardly chamfered; and a pair of hingedly attached pivot arms connected operatively to the upper and lower case halves, the pivot arms being adapted for facilitating movements of the upper case half between recessed and wire receiving positions, the upper case half overlying the lower case half upon movement to the recessed position, and the upper case half displacing forwardly from the recessed position upon movement toward the wire receiving position. |
| US09871361B2 |
Busbar holding structure
A busbar holding structure holds at least one of plural busbars to a wires routing body. The plural busbars electrically connect plural cell batteries constituting a battery assembly. The busbar holding structure includes a bottom wall, a partition wall erected from a portion of a peripheral edge of the bottom wall, a lock portion provided on the partition wall and configured to lock a side end portion of the busbar on the wires routing body, and a first projection that projects perpendicularly from the bottom wall and is to be fitted in a through-hole provided in the busbar. A fitting gap between the first projection and the through-hole is set so as to restrict an inclination angle of the busbar with respect to the first projection and to thereby prevent the busbar from being unlocked from the lock portion. |
| US09871355B2 |
Compact dual feeders for circuit breakers and related buckets and motor control centers (MCCs)
Dual starters and/or feeders are positioned in a unit housing to be offset from one another in a front to back direction to provide a compact configuration for a MCC cabinet. The dual starters or feeders can communicate with a respective external handle attached to an inwardly oriented shaft. The handles can be rotary handles that connect to a respective gear assembly that transforms rotational input to linear input. |
| US09871352B2 |
Spark plug
The spark plug includes: an insulator having a through hole that penetrates therethrough along an axial direction; a center electrode disposed on one end side of the through hole; a metal terminal disposed on the other end side of the through hole; and a conductive seal layer connected to at least one of the center electrode and the metal terminal. The conductive seal layer contains glass and a Cu—Zn alloy. A volumetric percentage of the Cu—Zn alloy in the conductive seal layer is greater than or equal to 44% and not greater than 55%. |
| US09871350B2 |
Manufacturable RGB laser diode source
A multi-wavelength light emitting device is manufactured by forming first and second epitaxial materials overlying first and second surface regions. The first and second epitaxial materials are patterned to form a plurality of first and second epitaxial dice. At least one of the first plurality of epitaxial dice and at least one of the second plurality of epitaxial dice are transferred from first and second substrates, respectively, to a carrier wafer by selectively etching a release region, separating from the substrate each of the epitaxial dice that are being transferred, and selectively bonding to the carrier wafer each of the epitaxial dice that are being transferred. The transferred first and second epitaxial dice are processed on the carrier wafer to form a plurality of light emitting devices capable of emitting at least a first wavelength and a second wavelength. |
| US09871348B2 |
Semiconductor laser device
An active layer is provided on a side closer to the second conductivity type cladding layer than a center of the light guide layer in the light guide layer. A first conductivity type low-refractive-index layer is formed between the first conductivity type cladding layer and the light guide layer and has a refractive index which is lower than a refractive index of the first conductivity type cladding layer. A layer thickness d of the light guide layer is a value at which a high-order mode equal to or higher than a first-order mode is permissible in a crystal growing direction by satisfying 2 π λ n g 2 - n c 2 d 2 ≧ π 2 . The active layer is disposed at a position where a light confinement of the active layer becomes smaller compared to a case in which the active layer is disposed at a center of the light guide layer while there is not the first conductivity type low-refractive-index layer. |
| US09871345B2 |
Crystalline color-conversion device
According to an embodiment, a crystalline color-conversion device includes an electrically driven first light emitter, for example a blue or ultraviolet LED, for emitting light having a first energy in response to an electrical signal. An inorganic solid single-crystal direct-bandgap second light emitter having a bandgap of a second energy less than the first energy is provided in association with the first light emitter. The second light emitter is electrically isolated from, located in optical association with, and physically connected to the first light emitter so that in response to the electrical signal the first light emitter emits first light that is absorbed by the second light emitter and the second light emitter emits second light having a lower energy than the first energy. |
| US09871343B2 |
Photonic transmitter with waveguide formed of particular opposing electrodes
This photonic transmitter includes a layer made of dielectric material, a sublayer made of doped III-V crystalline material extending directly over the layer made of dielectric material, a laser source including the sublayer made of doped III-V crystalline material, a modulator including a waveguide formed by proximal ends facing first and second electrodes and that segment of the layer made of dielectric material which is interposed between these proximal ends, and a zone composed only of one or more solid dielectric materials, which extends from a distal end of the second electrode to a substrate, and under the entirety of the distal end of the second electrode. |
| US09871341B2 |
Laser on silicon made with 2D material gain medium
A laser structure includes a substrate and a first dielectric layer formed on the substrate. A multi-quantum well is formed on the first dielectric layer and has a plurality of alternating layers. The alternating layers include a dielectric layer having a sub-wavelength thickness and a monolayer of a two dimensional material. |
| US09871336B2 |
Fiber amplifier
The present application provides an optical system. The optical system includes a fiber amplifier with an optically active doped fiber, a source of seed pulses, and a pump source. The doped fiber is doped with one or more active element(s) selected such that the seed pulses are amplified in intensity. The doped fiber has a negative (anomalous) group velocity dispersion in the region from the wavelength of the seed pulses to a threshold wavelength at which the magnitude of the optical loss of the doped fiber is greater than a gain due to stimulated Raman scattering. |
| US09871332B2 |
Electrical connector
An electrical connector connecting with a chip module includes a base with a receiving space and a cover covering on the base. The cover includes a first edge, a second edge, a third edge and a fourth edge. The four edges connect with each other to form four engaging portions, and a rectangular opening surrounded therein. The first edge is pivotally connected to the base. The cover includes an extending portion extending from the second edge. The cover includes four pressing portions located at four inner corners of the cover. |
| US09871330B2 |
Waterproof key apparatus
A waterproof key apparatus, as an electronic device, is provided. The waterproof key apparatus includes a main case, a key module attached to a side of the main case and comprises a key actuator, a window to which the key module is coupled, a universal serial bus (USB) coupling module and a printed circuit board (PCB) attached to an opposite side of the main case, with a dome sheet therebetween, a key bracket and an antenna cap coupled to the lower portion of the PCB, and a sealing part attached between the main case and the PCB to seal the rear surface of the PCB. |
| US09871329B1 |
Terminal assemblies suitable for power receptacles with thermal protection and associated methods
Terminal assemblies for power receptacles or switches or other electrical devices include a first terminal holding a first terminal screw and a second terminal adjacent the first terminal and holding a second terminal screw. The terminal assembly also includes a thermal protection plate having longitudinally opposed first and second end portions, the first end portion affixed to the first terminal and the second end portion attached to the second terminal. The thermal protection plate has an electrical conductive contact residing between the first and second end portions, closer to the second end portion than the first end portion. The thermal protection plate has a first material with a first thermal coefficient of expansion overlying or underlying a second material with a second thermal coefficient of expansion with the second thermal coefficient of expansion greater than the first thermal coefficient of expansion. |
| US09871327B2 |
Dual connector having ground planes in tongues
Connector receptacle assemblies that may be simple to manufacture, provide multiple receptacles, and provide a good ground contact path. One example may provide a connector receptacle assembly formed of a housing having a tongue that may include openings on one or more sides for contacts as well as openings on its sides for ground contacts. Another example may provide a connector receptacle assembly having at least two tongues, where each tongue may be aligned with a corresponding opening in a device enclosure. Another example may provide a connector receptacle assembly having a tongue with a center ground contact, where the center ground contact may be located between the top row and the bottom row of contacts. Another example may provide a connector receptacle assembly having a titanium-copper center ground contact. |
| US09871322B2 |
Connector
A connector includes a lever drawing and fitting a first housing and a second housing by moving from a temporary lock position to a final lock position. The lever includes a lever-side lock portion elastically deformable in a first direction away from a surface of the first housing, and including a reinforcing rib that enhances rigidity against a deformation of the lever-side lock protrusion. The first housing includes a housing-side lock portion which locks the lever-side lock portion when the lever is in the temporary lock position, which inhibits movement of the lever to the final lock position during locking, and which permits the lever to move to the final lock position when the locking is released. The second housing includes a lock releasing portion which pushes the lever-side lock portion in the first direction so as to release the locking. |
| US09871321B2 |
Electrical connection device
An electrical connection device (1), especially in the form of a connecting box, comprises a housing (2) having a wall (4) delimiting an inner space (3), electrical components (5) arranged in said inner space (3) and having at least two connecting portions (6, 7, 8), and at least two connecting holes (9, 10, 11) passing through the wall (4), through which external elements (12) connectable to the connecting portions (6, 7, 8) can be guided into the inner space (3). The connection device (1) further comprises a mechanical safety element (13) having a number of stop elements (14, 15, 16) that corresponds to the number of connecting portions (6, 7, 8), which stop elements (14, 15, 16) provide a mechanical stop for the external elements (12). |
| US09871311B2 |
Contact connection structure for removing oxide buildup
A contact connection structure includes: a first contact portion including an indent portion spherically protruding, the first contact portion including a plating layer formed on a surface of the first contact portion; and a second contact portion including a plating layer formed on a surface of the second contact portion. The indent portion of the first contact portion is slidable on a contact surface of the second contact portion. The indent portion of the first contact portion at a terminal insertion completed position is in contact with the second contact portion. The contact surface of the second contact portion includes an oxide-film shaving portion having an annular arc portion curved along a circumference portion of the indent portion. |
| US09871309B2 |
Connector
A connector is provided and includes a contact, a contact receiving housing, an insertion member, and a securing device. The contact includes a frame and a terminal section extending from a front end of the frame. The contact receiving housing includes a bottom wall and a pair of side walls extending from opposite sides of the bottom wall to define a contact receiving space. The insertion member extends from an end of the bottom wall and is positioned between the pair of side walls. The insertion member corresponds with an inner surface of the bottom wall. The securing device is positioned inside the contact receiving housing and secures the contact and the contact receiving housing in a fixed position. |
| US09871300B1 |
Steerable phased array antenna
Devices or apparatuses for adjusting a radiation angle of an antenna are described. An electronic device may include a strip, a first leaky-wave antenna (LWA) cell, and a second LWA cell. The first LWA cell can include a tunable component. The first LWA cell can also include a first conductive patch coupled to: a radio frequency (RF) feed on a first edge of the first conductive patch; a ground plane through a first via on a second edge of the first conductive patch; and a tunable component at a first corner between a third edge and a fourth edge of the first conductive patch. The second LWA cell can include a second conductive patch coupled to the ground plane through a second via on a second edge of the second conductive patch and coupled to the tunable component at a first corner between a first edge and a third edge of the second conductive patch. |
| US09871298B2 |
Rectifying circuit for multiband radio frequency (RF) energy harvesting
A radio frequency (RF) energy harvesting device (rectenna) includes an antenna structure configured to resonate at RF frequencies, and a rectifying circuit that facilitates harvesting multiband RF signals having low energy levels (i.e., tens of mW and below) by utilizing two Zero Bias Schottky diodes having different forward voltage and peak inverse voltage values. Positive voltage pulses from a captured RF signal generated on a first antenna end point are passed by the first diode to a first internal node where they are summed with a second RF signal generated on the second antenna end point (i.e., after being passed through a capacitor), thereby producing a first intermediate voltage having a substantially higher voltage level. Positive voltage pulses are then passed from the first internal node through the second diode to an output control circuit for conversion into a usable DC output voltage. |
| US09871297B2 |
Patch antenna element
An antenna element for transmission and/or reception of signals within a frequency band comprises a ground plane (4), a patch radiator (2), a connection point (14a) for connection of the antenna element to a feed network and a probe (8a) having two ends. The probe (8a) is located between the ground plane (4) and the patch radiator (2) and the patch radiator (2) is disposed in a parallel relationship with the ground plane (4) to form a resonant cavity between the patch radiator (4) and the ground plane (2). The antenna element comprises a transmission line (10a) which is disposed in a parallel relationship with the ground plane (4) and the transmission line (10a) is connected to an end (9a) of the probe (8a) and is arranged to have a length such that an impedance at the end (9a) of the probe is transformed. The transmission line (10a) is contained within the resonant cavity between the patch radiator (2) and the ground plane (4). |
| US09871289B2 |
Antenna structure and method for manufacturing the same
An antenna structure is provided. The antenna structure includes a metal sheet including an antenna branch and a grounding structure, wherein the antenna branch and the grounding structure are formed in one piece from the metal sheet, wherein the metal sheet has a top surface and a bottom surface, and the top surface and the bottom surface are opposite each other; a conductive glue disposed over the bottom surface of the metal sheet; and a supporting material disposed over a bottom surface of the conductive glue, wherein the supporting material is disposed corresponding to the antenna branch of the metal sheet. A method for manufacturing the antenna structure is also provided. |
| US09871282B2 |
At least one transmission medium having a dielectric surface that is covered at least in part by a second dielectric
Aspects of the subject disclosure may include, for example, a transmission medium for propagating electromagnetic waves. The transmission medium can have a first dielectric material for propagating electromagnetic waves guided by the first dielectric material, and a second dielectric material disposed on at least a portion of an outer surface of the first dielectric material for reducing an exposure of the electromagnetic waves to an environment that adversely affects propagation of the electromagnetic waves on the first dielectric material. Other embodiments are disclosed. |
| US09871278B2 |
Millimeter waveband filter and method of varying resonant frequency thereof
The millimeter waveband filter includes: a transmission line that is formed by a waveguide which propagates electromagnetic waves with a predetermined frequency range of a millimeter waveband from one end to the other end in a TE10 mode; and a pair of radio-wave half mirrors that are disposed opposite each other with a space interposed therebetween so as to block the inside of the transmission line and have planar shapes and a characteristic of transmitting a part of the electromagnetic waves with the predetermined frequency range and reflecting a part thereof. In the electromagnetic waves incident from the one end side of the transmission line, a frequency component centered on a resonant frequency of a resonator, which is formed between the pair of radio-wave half mirrors, is selectively output from the other end of the transmission line. |
| US09871275B2 |
Battery-state estimation device
A battery-state estimation device obtains, at a first timing, a first resistance value corresponding to a first open circuit voltage of a lithium-ion secondary battery and a second resistance value corresponding to a second open circuit voltage, which is higher than the first open circuit voltage, of the lithium-ion secondary battery. Further, the battery-state estimation device obtains, at a second timing which is different from the first timing, a third resistance value corresponding to the first open circuit voltage and a fourth resistance value corresponding to the second open circuit voltage. The battery-state estimation device determines presence or absence of lithium deposition in the lithium-ion secondary battery, based on a magnitude relation between a first variation amount of the third resistance value with respect to the first resistance value and a second variation amount of the fourth resistance value with respect to the second resistance value. |
| US09871274B2 |
Secondary battery with protection circuit module with label and release sheet
Provided is a battery pack, which can be prevented from being released from a label adhered to a frame or a battery cell due to distortion applied to the battery pack, thereby preventing noises from being generated during movement of an adhered surface of the label. A battery pack is also provided, which may prevent electrostatic discharge (ESD). The battery pack includes a battery cell, a protective circuit module (PCM) electrically connected to the battery cell, a frame accommodating the battery cell and the PCM, and a label adhered to the battery cell, the PCM and the frame while surrounding the same. A release sheet is attached to a region of the label surrounding the PCM. |
| US09871267B2 |
Laminated battery and manufacturing method therefor
A laminated battery provided with an electricity-producing element and an outer case. The electricity-producing element contains a positive electrode, a negative electrode, and an electrolyte. The outer case comprises two sheets of laminating film and includes the following: a containing section that contains the electricity-producing element; and a sealing section that is formed around the edge of the containing section by bonding the sheets of laminating film to each other. Corners are formed along the boundary between the containing section and the sealing section, and an adhesive resin layer in the sealing section is thicker in corner regions near the aforementioned corners than in other regions. |
| US09871261B2 |
Fuel cell stack enclosure
A fuel cell stack enclosure includes: a lower housing disposed under a fuel cell stack and having a bottom plate portion provided with a water outlet therein; a sealing cap closing the water outlet from an outside of the lower housing; and an elastic member elastically pulling the sealing cap toward the bottom plate portion of the lower housing. |
| US09871258B2 |
Stainless steel for fuel cell separators
A stainless steel having a low surface contact resistance for fuel cell separators is provided. The stainless steel has a Cr content of 16 to 40 mass % or more. The stainless steel includes a region having a fine textured structure on its surface, and the area percentage of the region is 50% or more, preferably 80% or more. The region having a fine textured structure is a region which has a structure having depressed portions and raised portions at an average interval between depressed portions or raised portions of 20 nm or more and 150 nm or less when observed with a scanning electron microscope. |
| US09871244B2 |
Method of fabricating structured particles composed of silicon or a silicon-based material and their use in lithium rechargeable batteries
Pillared particles of silicon or silicon-comprising material and a method of fabricating the same are disclosed. These particles may be used to create both a composite anode structure with a polymer binder, a conductive additive and a metal foil current collector, and an electrode structure. The structure of the particles overcomes the problems of charge/discharge capacity loss. |
| US09871242B2 |
Composite separator for lithium secondary battery, and lithium secondary battery using the composite separator
A composite separator and a lithium secondary battery including the composite separator, and the composite separator includes a separator; a first coating layer disposed on a surface of the separator and including a (meth)acrylic polymer and/or (meth)acrylic modified polyester resin; and a second coating layer disposed on another surface of the separator and including a vinylidene fluoride-based polymer. |
| US09871238B2 |
Secondary battery
To provide a secondary battery that can be prevented from exploding or catching fire due to the occurrence of a short circuit. The secondary battery (10) of the present invention includes an electric cell assembly that is, at least, partially enclosed by an extensible sheet (11) having a surface resistivity of 10−2 Ω/sq to 1010 Ω/sq, and is housed together with an electrolyte in a container (5), and in which positive electrodes (1) and negative electrodes (2) are stacked on each other or wound with a separator (3) interposed therebetween. |
| US09871237B2 |
Waterproof accommodating structure for battery
A battery-accommodating waterproof container includes a housing, a transmission base, a battery-holding seat and a locking cover module. The housing has a first opening, a second opening and a plurality of wedging holes. The transmission base is fixed on the first opening, and has a bottom board, an electricity transferring seat and a bottom-sealing element disposed between the bottom board and the housing. The battery-holding seat is received in the housing for receiving a battery therein. The electricity transferring seat transfers electricity of the battery outside the transmission base. The locking cover module is disposed on the second opening of the housing, and has a covering lid, a plurality of locking tabs and a pushing unit. The pushing unit drives the locking tabs to respectively wedge in the wedging holes of the housing, so as to retain the battery-holding seat in the housing. |
| US09871236B2 |
Lithium ion battery
A multi-core lithium ion battery includes a sealed enclosure and a support member disposed within the sealed enclosure. The support member includes a plurality of cavities and a plurality of lithium ion core members which are disposed the plurality of cavities. The battery further includes a plurality of cavity liners, each of which is positioned between a corresponding one of the lithium ion core members and a surface of a corresponding one of the cavities. |
| US09871234B2 |
Latch mechanism for battery retention
A latch mechanism for retaining a battery within a battery compartment. |
| US09871233B2 |
Rechargeable battery
A rechargeable battery includes an electrode assembly comprising electrodes having coated and uncoated regions and being located at opposite sides of a separator; a case accommodating the electrode assembly; a cap plate sealing the case and having terminal holes through which electrode terminals coupled to the uncoated regions extend; a gasket between each electrode terminal and the cap plate; and a first insulating plate between the cap plate and the electrode assembly and fastened to the gaskets. |
| US09871229B2 |
OVJP for printing graded/stepped organic layers
An emissive layer deposited in graded manner using a plurality of nozzles is disclosed. A mixtures ejected from the plurality of nozzles may contain varying concentrations of host-to-dopant material. The nozzles, as disclosed, may be arranged in a sequential manner such that the order of the sequence is based on varying concentration of the host-to-dopant material. The nozzles may be configured to translate relative to an area of a substrate to allow sequential deposition. |
| US09871225B2 |
Organic electroluminescence element
Provided is an organic electroluminescent element including a film substrate having thereon: at least one gas barrier layer, a light scatter layer, at least one smooth layer, and a light-emitting unit containing an organic functional layer interposed between a pair of electrodes, laminated in this order, wherein the light scatter layer contains a binder and light scatter particles having an average particle size of 0.2 μm or more to less than 1 μm; and the smooth layer contains an oxide or a nitride of silicone or niobium as a main component. |
| US09871219B2 |
Organic light emitting devices
The present invention provides an emissive region in organic light emitting devices having a combined emission from at least two emissive materials, a fluorescent blue emissive material and a phosphorescent emissive material. The emissive region may further comprise additional fluorescent or phosphorescent emissive materials. Preferably, the emissive region has three different emissive materials—a red emissive material, a green emissive material and a blue emissive material. Organic light emitting devices incorporating the emissive region provides a high color-stability of the light emission over a wide range of currents or luminances. |
| US09871216B2 |
Organic photoelectric conversion element and organic solar cell using the same
To provide an organic photoelectric conversion element whereby conversion efficiency is increased by morphology improvement in a power generation layer, and whereby short circuit current (Jsc) attenuation when irradiating light is simultaneously suppressed, and an organic solar cell using the same.An organic photoelectric conversion element having: a transparent first electrode; a power generation layer having a p-type organic semiconductor material and an n-type organic semiconductor material; and a second electrode, on a transparent substrate, in which the power generation layer is a bulk heterojunction power generation layer including the p-type organic semiconductor material and the n-type organic semiconductor material, and additionally includes a compound represented by either the following general formula (I) or general formula (II). |
| US09871215B2 |
Transistor manufacturing method and transistor
A transistor manufacturing method includes: forming a first insulator layer of which formation material is a fluorine-containing resin, on a substrate having a source electrode, a drain electrode, and a semiconductor layer so as to cover the semiconductor layer; forming a second insulator layer to cover the first insulator layer; forming a base film on at least part of a surface of the second insulator layer; and after depositing a metal which is an electroless plating catalyst on a surface of the base film, forming a gate electrode on the surface of the base film by electroless plating, wherein the forming of the base film is performed by applying a liquid substance which is a formation material of the base film to the surface of the second insulator layer, and the second insulator layer has a higher lyophilic property with respect to the liquid substance than the first insulator layer. |
| US09871214B2 |
Organic electroluminescent materials and devices
A compound having a Pt tetradentate structure of Formula I, is disclosed. In Formula I, rings A, B, and C each independently represent a 5- or 6-membered carbocyclic or heterocyclic ring; L1, L2, and L3 are each independently selected from the group consisting of a direct bond, BR, NR, PR, O, S, Se, C═O, S═O, SO2, SiRR′, GeRR′, alkyl, cycloalkyl, aryl, heteroaryl, and combinations thereof; X1, X2, and X3 are either carbon or nitrogen; X is O, S, or Se; R1, R2, R3, RA, RB, RC, R, and R′ are each independently selected from H and a variety of substituents; and any adjacent R1, R2, R3, RA, RB, RC, R, and R′ are optionally joined to form a ring. Formulations and devices, such as OLEDs, that include the compound of Formula I are also described. |
| US09871211B2 |
Electroactive materials
There is provided an electroactive material having Formula I wherein: Q is the same or different at each occurrence and can be O, S, Se, Te, NR, SO, SO2, or SiR3; R is the same or different at each occurrence and can be hydrogen, alkyl, aryl, alkenyl, or alkynyl; and R1 through R6 are the same or different and can be hydrogen, alkyl, aryl, halogen, hydroxyl, aryloxy, alkoxy, alkenyl, alkynyl, amino, alkylthio, phosphino, silyl, —COR, —COOR, —PO3R2, —OPO3R2, or CN. |
| US09871210B2 |
Naphthotriazole derivatives and organic electroluminescence devices
Naphthotriazole derivatives represented by the following general formula (1), wherein, Ar1 is an aromatic hydrocarbon group or an aromatic heterocyclic group, and A is a group that contains an aromatic heterocyclic group. The compound features excellent electron injection/transporting capability, a high hole-blocking power and a high stability in the form of a thin film, and can be used as a material for producing highly efficient and highly durable organic electroluminescent devices. |
| US09871208B2 |
Condensed cyclic compound and organic light-emitting device including the same
A condensed cyclic compound and an organic light-emitting device including the condensed cyclic compound, the condensed cyclic compound being represented by one of Formulae 1-1 to 1-8 described herein. |
| US09871205B2 |
Organic light-emitting device
Provided is an organic light-emitting device with a blue emission layer. The blue emission layer is an emission layer that emits blue light by a fluorescent emission mechanism. The blue emission layer includes a compound represented by Formula 4 below: |
| US09871203B2 |
Aromatic amine derivative, organic electroluminescent element and electronic device
An organic EL device that has a high efficiency and a long service life, an electronic apparatus containing the organic EL device, and a compound capable of providing the organic EL device. The compound is specifically represented by the following general formula (1): wherein in the general formula (1), Ar1 represents an organic group A represented by the following general formula (A-1); Ar2 represents the organic group A or an organic group B represented by the following general formula (B-1); and Ar3 represents the organic group B or an organic group C represented by the following general formula (C-1), provided that in the case where both Ar1 and Ar2 are the organic groups A, the organic groups A may be the same as or different from each other, in the general formula (A-1), R1 and R2 each represent a hydrogen atom, an alkyl group or an aryl group, and R1 and R2 may be bonded to each other to form a hydrocarbon ring; R3 to R6 each represent an alkyl group, a cycloalkyl group or an aryl group; and a, b, c and d each independently represent an integer of from 0 to 2, provided that R3 and R4 may be bonded to each other to forma hydrocarbon ring; and in the case where a or b is 2, adjacent groups of R3 or adjacent groups of R4 may be bonded to each other to form a hydrocarbon ring, in the general formula (B-1), Ar4 and Ar5 each represent an arylene group; Ar6 represents an aryl group; R7 to R9 each represent an alkyl group, a cycloalkyl group or an aryl group; e, f and g each represent an integer of from 0 to 2; and h and i each represent 0 or 1, provided that R7 to R9 may be bonded to each other to forma hydrocarbon ring; and in the case where e, f or g is 2, adjacent groups of R7, adjacent groups of R8 or adjacent groups of R9 may be bonded to each other to form a hydrocarbon ring, in the general formula (C-1), Ar7 represents an aryl group; R10 represents an alkyl group, a cycloalkyl group or an aryl group; and j represents an integer of from 0 to 2, provided that in the case where j is 2, adjacent groups of R10 may be bonded to each other to form a hydrocarbon ring. |
| US09871199B2 |
Light emissive plastic glazing having a multilayered configuration for illuminating passenger compartment
In an embodiment, a light emissive window assembly for providing illumination to an occupant compartment of an automobile comprises a window panel comprising a transparent viewing area and an emissive area, wherein the emissive area is configured to emit light into the occupant compartment and the transparent viewing area is not configured to emit light; wherein the emissive area comprises an abrasion resistant layer, an ultraviolet protective layer, a base layer, and an emissive layer; wherein the ultraviolet protective layer is located in between the abrasion resistant layer and the base layer; and wherein the base layer is located in between the ultraviolet protective layer and the emissive layer. |
| US09871197B2 |
Semiconductor memory device
A semiconductor memory device according to an embodiment includes: a plurality of first conductive lines stacked in a first direction above a semiconductor substrate and extending in a second direction; a second conductive line extending in the first direction; semiconductor layers arranged between the first conductive lines and the second conductive line and extending in the first direction; a conductive layer in contact with a bottom surface of the semiconductor layer with a first impurity of a first conductivity type; and variable resistance films arranged at intersections between the first conductive lines and the semiconductor layer, the semiconductor layer having a first semiconductor part arranged from the bottom surface of the semiconductor layer to a position equal to or lower than a bottom surface of the first conductive line at a lowermost layer in the first direction with a second impurity of a second conductivity type. |
| US09871196B2 |
Methods of forming memory devices having electrodes comprising nanowires
Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory cell. Electronic systems include such memory devices. |
| US09871189B2 |
Electronic device and method for fabricating the same
This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a Magnetic Tunnel Junction (MTJ) structure including a free layer having a variable magnetization direction, a pinned layer having a pinned magnetization direction, and a tunnel barrier layer interposed between the pinned layer and the free layer; a magnetic correction layer located under the MTJ structure and operates to reduce an influence of a stray magnetic field generated by the pinned layer; and an under layer located under the magnetic correction layer and including a metal oxide layer. |
| US09871185B2 |
Drive device using polymer actuator
A drive device includes a driven body provided on an opening of a case, and a polymer actuator which is bent and deformed in a height direction and movably supports the driven body in the height direction. A first conductive portion is provided on the case side, a second conductive portion is provided on the driven body side, and the first conductive portion and the second conductive portion configure a plurality of contact portions. When the driven body is raised by the polymer actuator, the first conductive portion and the second conductive portion come into contact with each other by the plurality of contact portions, and thus, the raised state of the driven body is detected. |
| US09871181B2 |
Production method of thermoelectric converter, production method of electronic device equipped with thermoelectric converter, and thermoelectric converter
As the first conductive paste, a paste is used which is made by adding an organic solvent to powder of alloy in which a plurality of atoms keep a given crystal structure constant. As the second conductive paste, a paste is used which is made by adding an organic solvent to powder of metal different in kind from the alloy. In a step of making the stack body, cavities are formed in the stack body. In a uniting step, the cavities work to facilitate flow of thermoplastic resin to absorb pressure acting in a direction different from a direction in which pressure exerted on the first conductive paste to unite the stack body, thereby resulting in an increase in pressure for the uniting to solid-state sinter the first conductive paste to make the first layer-to-layer connecting member. |
| US09871175B2 |
LED fluorescent cover and preparation method thereof
A Light Emitting Diode (LED) fluorescent cover comprises the following components by weight: 90-96% of single-component solid silicone rubber, 3-8% of fluorescent powder and 1-2% of vulcanizer; and the preparation method includes the following steps: step 1): using mixed compound of the single-component solid silicone rubber, as well as the fluorescent powder and the vulcanizer as raw material to mix, standing for 2-4 h after mixing with open mill or internal mixer; step 2): controlling temperature, pressure and vulcanization time of vulcanizing machine according to size of the fluorescent cover mold, using the vulcanizing machine to carry out first vulcanization to the raw material that is obtained from the step 1) and placed in the fluorescent cover mold; step 3): with combined action of blower gun, taking the fluorescent cover out slowly; step 4): baking the semi-finished product in a closed space at a temperature of 150-200° C. for 1-2 h. |
| US09871172B2 |
Semiconductor light emitting device package with wavelength conversion layer
A semiconductor light emitting device package is provided and includes a light emitting diode (LED) chip including a first electrode and a second electrode, the LED chip having a first surface on which the first electrode and the second electrode are disposed, and a second surface opposing the first surface; a dam structure disposed on the first surface, an outside edge of the dam structure being co-planar with an outside edge of the LED chip; and a wavelength conversion layer disposed on side surfaces of the LED chip, the second surface of the LED chip, and a surface of the dam structure, the wavelength conversion layer containing a wavelength conversion material. |
| US09871171B2 |
Light-emitting device and manufacturing method thereof
A light-emitting device comprises a light-emitting structure capable of emitting a light; an electrode formed on a side of the light-emitting structure; a transparent structure formed on a second side of the light-emitting structure, wherein the transparent structure is aligned to a region of the electrode, and comprises a first transparent layer and a second transparent layer around the first transparent layer; a contact structure formed on the second side of the light-emitting structure; and a reflective layer covering the transparent structure and the contact structure. |
| US09871167B2 |
Top emitting semiconductor light emitting device
Embodiments of the invention include a semiconductor structure including a light emitting layer sandwiched between an n-type region and a p-type region. A growth substrate is attached to the semiconductor structure. The growth substrate has at least one angled sidewall. A reflective layer is disposed on the angled sidewall. A majority of light extracted from the semiconductor structure and the growth substrate is extracted through a first surface of the growth substrate. |
| US09871165B2 |
Advanced electronic device structures using semiconductor structures and superlattices
Semiconductor structures and methods for forming those semiconductor structures are disclosed. For example, a p-type or n-type semiconductor structure is disclosed. The semiconductor structure has a polar crystal structure with a growth axis that is substantially parallel to a spontaneous polarization axis of the polar crystal structure. The semiconductor structure changes in composition from a wider band gap (WBG) material to a narrower band gap (NBG) material or from a NBG material to a WBG material along the growth axis to induce p-type or n-type conductivity. |
| US09871164B2 |
Nanostructure light emitting device and method of manufacturing the same
A nanostructure semiconductor light emitting device includes a base layer, an insulating layer, and a plurality of light emitting nanostructures. The base layer includes a first conductivity type semiconductor. The insulating layer is disposed on the base layer and has a plurality of openings through which regions of the base layer are exposed. The light emitting nanostructures are respectively disposed on the exposed regions of the base layer and include a plurality of nanocores having a first conductivity type semiconductor and having side surfaces provided as the same crystal planes. The light emitting nanostructures include an active layer and a second conductivity type semiconductor layer sequentially disposed on surfaces of the nanocores. Upper surfaces of the nanocores are provided as portions of upper surfaces of the light emitting nanostructures, and the upper surfaces of the light emitting nanostructures are substantially planar with each other. |
| US09871162B2 |
Method of growing nitride single crystal and method of manufacturing nitride semiconductor device
A method of growing a Group-III nitride crystal includes forming a buffer layer on a silicon substrate and growing a Group-III nitride crystal on the buffer layer. The method of growing of a Group-III nitride crystal is executed through metal-organic chemical vapor deposition (MOCVD) during which a Group-III metal source and a nitrogen source gas are provided. The nitrogen source gas includes hydrogen (H2) and at least one of ammonia (NH3) and nitrogen (N2). At least a partial stage of the operation of growing the Group-III nitride crystal can be executed under conditions in which a volume fraction of hydrogen in the nitrogen source gas ranges from 20% to 40% and a temperature of the silicon substrate ranges from 950° C. to 1040° C. |
| US09871160B2 |
Materials, systems and methods for optoelectronic devices
A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer. |
| US09871158B2 |
Efficiency enhancement of solar cells using light management
A photovoltaic cell includes a junction, formed from an n-type semiconductor material and a p-type semiconductor material, a trench, opening toward the light-incident side of the junction, for trapping reflected light, and two photon conversion layers. A first photon conversion layer, arranged at the light-incident side of the junction, converts photons from a higher energy to a lower energy suitable for absorption by the semiconductor material, and a second photon conversion layer, arranged at the opposite side of the junction, converts photons from a lower energy to a higher energy suitable for absorption by the semiconductor material. |
| US09871157B2 |
Method for producing concentrator photovoltaic unit, production apparatus used in the method, method for producing concentrator photovoltaic module, and production apparatus used in the method
Mutual alignment between a condenser lens and its power generating element can be performed easily and accurately.This method for producing a concentrator photovoltaic unit includes: a first step of emitting linear laser beams respectively toward incident positions 42 on an incident surface 13f1; and a second step of performing positional adjustment between a Fresnel lens 13f and a power generating element part 21, based on positional relationship between the power generating element part 21 and beam images respectively formed by the linear laser beams at a time when the beam images and the power generating element part 21 are seen along an optical axis S from the incident surface 13f1 side of the Fresnel lens 13f. Four incident positions 42 in the first step are set such that at least one pair of beam images, among the beam images respectively formed by the linear laser beams, cross each other at an optical axis point S1 of the Fresnel lens 13f when the power generating element part 21 side is seen along the optical axis S from the incident surface 13f1 side of the Fresnel lens 13f. |
| US09871156B2 |
Solar cell and method of manufacturing the same
A method of manufacturing a solar cell, including the steps of: forming an SiNx film over a second principal surface of an n-type semiconductor substrate; forming a p-type diffusion layer over a first principal surface of the n-type semiconductor substrate after the SiNx film forming step; and forming an SiO2 film or an aluminum oxide film over the p-type diffusion layer. |
| US09871155B2 |
Layer system for thin-film solar cells having an NaxIn1SyClz buffer layer
The present invention relates to a layer system (1) for thin-film solar cells with an absorber layer (4) that contains a chalcogenide compound semiconductor and a buffer layer (5) that is arranged on the absorber layer (4), wherein the buffer layer (5) contains NaxIn1SyClz with 0.05≦x<0.2 or 0.2 |
| US09871152B2 |
Solar cell and manufacturing method thereof
To provide a solar cell that reduces occurrence of a defect and has high photoelectric conversion efficiency. The solar cell includes a silicon substrate such as an n-type single-crystal silicon substrate single crystal with pyramid-shaped irregularities P formed thereon, and an amorphous or microcrystal semiconductor layer formed on the single-crystal silicon substrate. A flat part F is formed in a valley portion of the pyramid-shaped irregularities P provided on a surface of the single-crystal silicon substrate. With this configuration, a steep angle of 70° to 85° of a concave portion formed by a substantially (111) surface can be widened to between 115° and 135°. Accordingly, a change of atomic step morphology attributable to a rounded shape can be eliminated, thereby enabling to reduce epitaxial growth and defects in the amorphous or microcrystal semiconductor layer. |
| US09871150B1 |
Protective region for metallization of solar cells
Methods of fabricating a solar cell including metallization techniques and resulting solar cells, are described. In an example, a first and second semiconductor regions can be formed in or above a substrate, where a separation region is disposed between the first and second semiconductor regions. A protective region can be formed over the separation region. A first metal layer can be formed over the substrate, where the protective region prevents and/or inhibits damage to the separation region during the formation of the first metal layer. Conductive contacts can be formed over the first and second semiconductor regions. |
| US09871149B2 |
Solar cell and solar cell module
A solar cell module includes first and second solar cells and an interconnector for electrically connecting the first and second solar cells. The first solar cell and the second solar cell each include a plurality of first electrodes formed on a back surface of a semiconductor substrate, a plurality of second electrodes formed on the back surface of the semiconductor substrate, a first auxiliary electrode connected to the plurality of first electrodes, a second auxiliary electrode connected to the plurality of second electrodes, and an insulating member positioned on back surfaces of the first auxiliary electrode and the second auxiliary electrode. Each of the first solar cell and the second solar cell is formed as an individual integrated type element by connecting one semiconductor substrate and one insulating member. |
| US09871147B2 |
Photodetector
A photodetector including a substrate, a light absorption layer arranged over the substrate, the light absorption layer including a stack including a semiconductor layer that absorbs light of a wavelength having an electric field vector parallel to a normal direction of a substrate surface, a lower contact layer arranged on a first side of the light absorption layer, a lower electrode contacting with the lower contact layer, an upper contact layer arranged on a second side of the light absorption layer, and an upper electrode contacting with the upper contact layer. An uneven structure including polarization-selective shapes of projections or depressions on the second side of the upper contact layer is provided, the shapes of projections or depressions each having a size of a wavelength or less of incident light in the semiconductor layer and half the wavelength or greater and being periodically arranged in at least one direction. |
| US09871145B2 |
Semiconductor device, manufacturing method thereof, and electronic device
A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer. The second and third regions each include a region containing an element N (N is phosphorus, argon, or xenon). |
| US09871144B2 |
Thin film transistor substrate
A thin film transistor substrate includes a gate electrode disposed on a substrate; a semiconductor layer disposed on the substrate that partially overlaps the gate electrode and includes an oxide semiconductor material; and a source electrode and a drain electrode disposed on the semiconductor layer, where the drain electrode is spaced apart from the source electrode. The source electrode and the drain electrode each include a barrier layer and a main wiring layer, the a main wiring layer is disposed on the barrier layer, and the barrier layer includes a first metal layer disposed on the semiconductor layer, and a second metal layer disposed on the first metal layer. |
| US09871140B1 |
Dual strained nanosheet CMOS and methods for fabricating
A method includes: growing a lattice of alternating sheets of tensile strained silicon and relaxed silicon-germanium on a substrate; isolating a first portion of the lattice from a second portion of the lattice; forming source regions and drain regions on each of the first portion of the lattice and the second portion of the lattice; forming a first gate opening in the first portion of the lattice and a second gate opening in the second portion of the lattice; selectively removing the sheets of relaxed silicon-germanium from under the second gate opening in the second portion of the lattice; selectively removing portions of the sheets of tensile strained silicon from under the first gate opening in the first portion of the lattice; and increasing a germanium content in the relaxed silicon-germanium layers under the first gate opening in the first portion of the lattice. |
| US09871138B2 |
Semiconductor device and method of fabricating semiconductor device
The present invention provides a semiconductor device, including a substrate, two gate structures disposed on a channel region of the substrate, an epitaxial layer disposed in the substrate between two gate structures, a first dislocation disposed in the epitaxial layer, wherein the profile of the first dislocation has at least two non-parallel slanting lines, and a second dislocation disposed adjacent to a top surface of the epitaxial layer, and the profile of the second dislocation has at least two non-parallel slanting lines. |
| US09871136B2 |
Semiconductor device
A semiconductor device includes a substrate, an electrode layer disposed on the substrate, and a tri-layered gate-control stack sandwiched between the substrate and the electrode layer. The tri-layered gate-control stack includes a ferroelectric layer disposed on the substrate, a mid-gap metal layer sandwiched between the ferroelectric layer and the substrate, and an anti-ferroelectric layer. The anti-ferroelectric layer is sandwiched between the substrate and the mid-gap metal layer. Alternatively, the ferroelectric layer and the mid-gap metal layer are sandwiched between the anti-ferroelectric layer and the substrate. |
| US09871129B2 |
Thyristor, a method of triggering a thyristor, and thyristor circuits
A thyristor is disclosed comprising: a first region of a first conductivity type; a second region of a second conductivity type and adjoining the first region; a third region of the first conductivity type and adjoining the second region; a fourth region of the second conductivity type and comprising a first segment and a second segment separate from the first segment, the first segment and second segment each adjoining the third region; a first contact adjoining the first region; a second contact adjoining the first segment; and a trigger contact adjoining the second segment and separate from the second contact. |
| US09871126B2 |
Discrete semiconductor transistor
A discrete semiconductor transistor includes a gate resistor electrically coupled between a gate electrode terminal and a gate electrode of the discrete semiconductor transistor. A resistance R of the gate resistor at a temperature of −40° C. is greater than at the temperature of 150° C. |
| US09871123B2 |
Field effect transistor and manufacturing method thereof
A field effect transistor (FET) and a manufacturing method thereof are provided. The FET includes a substrate, a fin bump, an insulating layer, a charge trapping structure and a gate structure. The fin bump is disposed on the substrate. The insulating layer is disposed on the substrate and located at two sides of the fin bump. The charge trapping structure is disposed on the insulating layer and located at least one side of the fin bump. A cross-section of the charge trapping structure is L-shaped. The gate structure covers the fin bump and the charge trapping structure. |
| US09871122B2 |
Methods of fabricating a semiconductor device
A method of fabricating a semiconductor device includes providing a substrate that includes first and second main regions and a dummy region, and forming dummy active patterns on the dummy region. The first and second main regions are spaced apart from each other in a first direction and the dummy region includes a dummy connection region between the first and second main regions and first and second dummy cell regions spaced apart from each other in a second direction. First dummy active patterns, second dummy active patterns, and connection dummy active patterns connecting some of the first dummy active patterns to some of the second dummy active patterns are provided on the first and second dummy cell regions and the dummy connection region, respectively. |
| US09871118B2 |
Semiconductor structure with an L-shaped bottom plate
A semiconductor structure having an electrical contact that is connected to source/drain structures of two different transistors. The semiconductor structure has a vertical channel and a source/drain semiconductor structure connected to the vertical channel such that the source/drain semiconductor structure has a vertical side that is substantially planar with a vertical side of the first vertical channel. The source/drain semiconductor structure extends horizontally from its vertical side farther than the first vertical channel extends from its vertical side such that a width of the source/drain is greater than a width of the first vertical channel. The first source/drain semiconductor structure is located on a layer of substrate and the vertical channel is perpendicular relative to the layer of substrate. |
| US09871117B2 |
Vertical transistor devices for embedded memory and logic technologies
Vertical transistor devices are described. For example, in one embodiment, a vertical transistor device includes an epitaxial source semiconductor region disposed on a substrate, an epitaxial channel semiconductor region disposed on the source semiconductor region, an epitaxial drain semiconductor region disposed on the channel semiconductor region, and a gate electrode region surrounding sidewalls of the semiconductor channel region. A composition of at least one of the semiconductor regions varies along a longitudinal axis that is perpendicular with respect to a surface of the substrate. |
| US09871116B2 |
Replacement metal gate structures
Replacement metal gate structures with improved chamfered workfunction metal and self-aligned contact and methods of manufacture are provided. The method includes forming a replacement metal gate structure in a dielectric material. The replacement metal gate structure is formed with a lower spacer and an upper spacer above the lower spacer. The upper spacer having material is different than material of the lower spacer. The method further includes forming a self-aligned contact adjacent to the replacement metal gate structure by patterning an opening within the dielectric material and filling the opening with contact material. The upper spacer prevents shorting with the contact material. |
| US09871113B2 |
Semiconductor process
A semiconductor process including the following steps is provided. An epitaxial layer is formed on a substrate. An oxide layer is formed on the epitaxial layer, wherein the oxide layer includes a chemical oxide layer, a high-temperature oxide (HTO) layer or a surface modification oxide layer. An ion implant process is performed to the epitaxial layer to form a doped region in the epitaxial layer. The oxide layer is removed by using a diluted hydrofluoric acid (DHF) solution after performing the ion implant process, wherein a volume ratio of water to a hydrofluoric acid (HF) in the DHF solution is 200:1 to 1000:1. |
| US09871110B2 |
Semiconductor device
It is aimed to reduce a current concentration at the edge of the contact electrode.Provided is a semiconductor device including a semiconductor layer, a first trench electrode formed in the semiconductor layer on a front surface side thereof, and a second trench electrode formed in the semiconductor layer on the front surface side thereof so as to oppose the first trench electrode. Here, the first trench electrode is formed in a mesh-like pattern. The semiconductor layer may further include a first-conductivity-type region and a second-conductivity-type region having a different conductivity type than the first-conductivity-type region. The first trench electrode may be electrically connected to the first-conductivity-type region, and the second trench electrode may be electrically connected to the second-conductivity-type region. |
| US09871109B2 |
Semiconductor device
A semiconductor device according to the present invention includes, in a termination region, a p− type breakdown voltage holding region that is an impurity region formed in a predetermined depth direction from a substrate surface of an n− type substrate, a first insulating film formed on the n− type substrate so as to cover at least the p− type breakdown voltage holding region, a first field plate formed on the first insulating film, a second insulating film formed so as to cover the first field plate and the first insulating film, and a second field plate formed on the second insulating film. The first insulating film is thicker in a corner portion than in an X-direction straight portion and a Y-direction straight portion. |
| US09871108B2 |
Nitride semiconductor device
A nitride semiconductor device according to the present invention includes a nitride semiconductor layer having a gate, a source and a drain and a field plate on the nitride semiconductor layer electrically connected to the gate or the source, where when it is assumed that a drain voltage value where the value of COSS is reduced to one half of a value when a drain voltage is 0 V is V1, the dielectric breakdown voltage of the device is V2, a gate length is Lg, a field plate length is Lfp, a shallow acceptor concentration is NA, a deep acceptor concentration is NDA, a vacuum permittivity is ∈0 and the relative permittivity of the nitride semiconductor layer is ∈, formulas (1) and (2) below are satisfied. V1 |
| US09871107B2 |
Device with a conductive feature formed over a cavity and method therefor
An embodiment of a device includes a semiconductor substrate, a transistor formed at the first substrate surface, a first conductive feature formed over the first substrate surface and electrically coupled to the transistor, and a second conductive feature covering only a portion of the second substrate surface to define a first conductor-less region. A cavity vertically aligned with the first conductive feature within the first conductor-less region extends into the semiconductor substrate. A dielectric medium may be disposed within the cavity and have a dielectric constant less than a dielectric constant of the semiconductor substrate. A method for forming the device may include forming a semiconductor substrate, forming a transistor on the semiconductor substrate, forming the first conductive feature, forming the second conductive feature, forming the conductor-less region, forming the cavity, and filling the cavity with the dielectric medium. |
| US09871106B2 |
Heterogeneous pocket for tunneling field effect transistors (TFETs)
Embodiments of the disclosure described herein comprise a tunneling field effect transistor (TFET) having a drain region, a source region having a conductivity type opposite of the drain region, a channel region disposed between the source region and the drain region, a gate disposed over the channel region, and a heterogeneous pocket disposed near a junction of the source region and the channel region. The heterogeneous pocket comprises a semiconductor material different than the channel region, and comprises a tunneling barrier less than the bandgap in the channel region and forming a quantum well in the channel region to in crease a current through the TFET transistor when a voltage applied to the gate is above a threshold voltage. |
| US09871103B2 |
Semiconductor device
A semiconductor device includes a plurality of active regions including channel regions extending in a first direction on a semiconductor substrate and source/drain regions connected to the channel regions, a plurality of gate electrodes extending in a second direction different from the first direction to intersect the channel regions, a plurality of conductive lines electrically connected to at least one of the source/drain regions and the plurality of gate electrodes through a plurality of vias, and a power line disposed between the semiconductor substrate and the plurality of conductive lines and configured to supply a power supply voltage. |
| US09871102B2 |
Method of forming a single-crystal nanowire finFET
A semiconductor device and a method of forming the same, the semiconductor device includes a single crystal substrate, a source/drain structure and a nanowire structure. The source/drain structure is disposed on and contacts with the substrate. The nanowire structure is connected to the source/drain structure. |
| US09871098B2 |
Semiconductor device with suppressed decrease in breakdown voltage of an insulation film and manufacturing method of the same
A semiconductor device may include a semiconductor substrate in which a semiconductor element is provided, and an insulation film provided on the semiconductor substrate, in which the semiconductor substrate may include a first portion and a second portion which has a thickness thinner than a thickness of the first portion, an upper surface of the second portion may be positioned lower than an upper surface of the first portion, a recess extending in a thickness direction of the semiconductor substrate may be provided on the upper surface of the second portion located at a position where the first portion and the second portion adjoin to each other, and the insulation film may extend over from the first portion to the second portion, and fill the recess. |
| US09871092B2 |
Display device with reduced frame size
A display device includes contact holes opened in an insulating film outside of a display area in which pixels are arranged, and having a conductive film exposed in bottom portions, a first metal film formed to cover the contact holes and come in contact with the conductive film of the bottom portions, and a transparent conductive film formed on the first metal film. |
| US09871087B2 |
Organic light-emitting diode display having high aperture ratio and method for manufacturing the same
An organic light-emitting diode display can include a substrate in which an emission area and a non-emission area are defined; a first transparent conductive layer, a light shielding layer, a buffer layer and a semiconductor layer sequentially laminated on the non-emission area; a gate electrode superposed on the center region of the semiconductor layer, having a gate insulating layer interposed therebetween; a drain electrode coming into contact with one side of the semiconductor layer, having an interlevel insulating layer covering the gate electrode interposed therebetween, and formed of a second transparent conductive layer and a metal layer laminated thereon; a first storage capacitor electrode disposed under the interlevel insulating layer in the emission area and formed of the first transparent conductive layer; and a second storage capacitor electrode superposed on the first storage capacitor electrode, having the interlevel insulating layer interposed therebetween, and formed of the second transparent conductive layer. |
| US09871086B2 |
Display device and method for manufacturing display device
Provided is a display device, including: a substrate; signal lines including a gate line, a data line, and a driving voltage line that collectively define an outer boundary of a pixel area; a transistor connected to the signal line; a first electrode extending across the pixel area and formed on the signal line and the transistor, and connected to the transistor, the first electrode having a first portion overlying only the signal line and the transistor, and a second portion comprising all of the first electrode not included in the first portion; a pixel defining layer formed on only the first portion of the first electrode; an organic emission layer formed on substantially the entire second portion but not on the first portion; and a second electrode formed on the pixel defining layer and the organic emission layer. |
| US09871085B2 |
Organic light-emitting diode display panel
Disclosed is an organic light-emitting diode display panel, which may effectively reduce or prevent spreading of the peeling of an organic light-emitting layer by using a bar-shaped reversed spacer, regardless of the direction in which the organic layer peels off. The organic light-emitting diode display panel may include a reversed spacer, which is disposed on a bank insulation layer having an opening and includes a reversed-trapezoidal cross section, the reversed spacer having a bar shape when viewed from the front side of the organic light-emitting diode display panel. |
| US09871081B2 |
Flexible display device
A flexible display device is disclosed. In one aspect, the device includes a display substrate including a display area and a non-display area surrounding the display area, wherein the display area includes an emission element layer. An inorganic layer is formed over the display substrate in the display area and the non-display area, and a thin film encapsulation layer is formed over the inorganic layer and covering at least a portion of the inorganic layer. A plurality of dummy patterns are formed over the display substrate and the inorganic layer. The dummy patterns include a plurality of first dummy patterns formed in the non-display area of the display substrate not overlapping the inorganic layer, and a plurality of second dummy patterns formed in the non-display area of the of the display substrate overlapping the inorganic layer. |
| US09871079B2 |
Image sensor and electronic device including the same
An image sensor includes a semiconductor substrate integrated with at least a photo-sensing device, a plurality of first electrodes disposed on the semiconductor substrate, an organic photoelectric conversion layer disposed on the first electrodes, and a second electrode disposed on the organic photoelectric conversion layer. The first electrodes include a light-transmitting electrode and a metal layer interposed between the semiconductor substrate and the light-transmitting electrode. The organic photoelectric conversion layer disposed on the first electrodes and the photo-sensing device absorb and/or sense light in different wavelength regions from each other. An electronic device including the image sensor is also provided. |
| US09871077B2 |
Resistive memory device with semiconductor ridges
A memory device includes one or more first semiconductor ridges formed on a first semiconductor wafer. The first semiconductor ridges are configured to be first electrodes. The memory device also includes one or more second semiconductor ridges formed on a second semiconductor wafer. The second semiconductor ridges are configured to be second electrodes and are placed orthogonally on top of the first semiconductor ridges forming a crossbar structure, with sharp edges of the first semiconductor ridges coupled to sharp edges of the second semiconductor ridges. Each area of coupling of a first semiconductor ridge and a second semiconductor ridge is configured to be a memory cell. In addition, the memory device includes a compound layer covering the sharp edges of at least one of the first semiconductor ridges or the second semiconductor ridges. The compound layer is configured to be a switching layer. |
| US09871071B2 |
Solid-state imaging device, manufacturing method thereof, and electronic apparatus
A solid-state imaging device includes a plurality of photoelectric conversion portions each provided in a semiconductor substrate and receives incident light through a light sensing surface, and a pixel separation portion provided to electrically separate a plurality of pixels. At least a pinning layer and a light shielding layer are provided in an inner portion of a trench provided on a side portion of each of the photoelectric conversion portions in an incident surface side, the trench includes a first trench and a second trench formed to be wider than the first trench in a portion shallower than the first trench, the pinning layer is formed in an inner portion of the first trench to cover an inside surface of the second trench, and the light shielding layer is formed to bury an inner portion of the second trench at least via the pinning layer. |
| US09871070B2 |
Voltage biased metal shielding and deep trench isolation for backside illuminated (BSI) image sensors
A backside illuminated (BSI) image sensor for biased backside deep trench isolation (BDTI) and/or biased backside shielding is provided. A photodetector is arranged in a semiconductor substrate, laterally adjacent to a peripheral opening in the semiconductor substrate. An interconnect structure is arranged under the semiconductor substrate. A pad structure is arranged in the peripheral opening, and protrudes through a lower surface of the peripheral opening to the interconnect structure. A conductive layer is electrically coupled to the pad structure, and extends laterally towards the photodetector from over the pad structure. A method for manufacturing the BSI image sensor is also provided. |
| US09871066B2 |
Enhanced pixel for multiband sensing including a signal path to receive a flow of signals flowing through a control device
An imaging pixel including a control device to control flow of a charge signal from a photodetector. The control device has a variable impedance that varies in response to frequency of an input signal, the control device being biased to permit signals to flow through the control device dependent on the frequency of signals being output by the photodetector. The imaging pixel further includes a low-frequency signal path that receives a flow of signals that flow through the control device, and a high-frequency signal path independent of the low-frequency signal path and the control device, the high-frequency signal path receiving high-frequency signals included in the charge signal. |
| US09871063B1 |
Display driver semiconductor device and manufacturing method thereof
A display driver semiconductor device includes a high voltage well region being formed on a substrate, a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device is formed on the high voltage well region and includes a first gate insulating layer. The second semiconductor device is formed adjacent to the first semiconductor device and includes a second gate insulating layer. The third semiconductor device is formed adjacent to the second semiconductor device and includes a third gate insulating layer. The first insulating layer may be formed using a chemical vapor deposition (CVD) process and the second insulating layer is formed using a thermal oxide process. |
| US09871055B1 |
Vertical-type memory device
A vertical-type memory device may include a channel layer vertically extending on a substrate, a ground selection transistor at a side of the channel layer on the substrate, the ground selection transistor including a first gate insulation portion and a first replacement gate electrode, an etch control layer on the first replacement gate electrode, and a memory cell on the etch control layer, the memory cell including a second gate insulation portion and a second replacement gate electrode. The etch control layer may include a polysilicon layer doped with carbon, N-type impurities, or P-type impurities, or may include a polysilicon oxide layer comprising carbon, N-type impurities, or P-type impurities. A thickness of the first replacement gate electrode may be the same as a thickness of the second replacement gate electrode, or the first replacement gate electrode may be thicker than the second. |
| US09871054B2 |
Semiconductor device and method for manufacturing same
According to one embodiment, the stacked body includes a plurality of electrode layers stacked with an insulator interposed. The electrode layers have a plurality of terrace portions arranged in a stairstep configuration with a difference in levels. The insulating layer is provided above the terrace portions. The columnar portions extend in a stacking direction of the stacked body through the insulating layer and through the stacked body under the insulating layer. The columnar portions are insulative. The contact portions are provided at side surfaces of the columnar portions on the terrace portions. The contact portions are connected to the terrace portions. |
| US09871051B2 |
Stacked type semiconductor memory device and method for manufacturing the same
A semiconductor memory device according to an embodiment, includes a stacked body, first and second semiconductor pillars and a contact. The stacked body includes insulating films and electrode films stacked alternately along a first direction. A configuration of an end portion of the stacked body in a second direction is a stairstep configuration. A step is formed in the stairstep configuration for each of the electrode films. The first semiconductor pillars are disposed in a region of the stacked body where the steps are not formed. The second semiconductor pillars are disposed in a region of the stacked body where the steps are formed. The contact is disposed on the electrode film for each of the steps. When viewed from the first direction, the first and second semiconductor pillars are disposed at some of lattice points of a lattice. |
| US09871049B1 |
Static random access memory device and forming method thereof
A static random access memory device includes two body contacts and two resistive-switching devices. The body contacts are disposed in a wafer and are exposed from a back side of the wafer, wherein the body contacts electrically connect a static random access memory cell through a metal interconnect in the wafer. The resistive-switching devices connect the two body contacts respectively from the back side of the wafer. A method of forming a static random access memory device is also provided in the following. A wafer having two body contacts exposed from a back side of the wafer and a metal interconnect electrically connecting a static random access memory cell to the body contacts is provided. Two resistive-switching devices are formed to connect the two body contacts respectively from the back side of the wafer. |
| US09871048B1 |
Memory device
A memory device includes a pickup area extending along a first direction. The pickup area includes at least one N-pickup structure, distributing along an N-pickup line extending at the first direction. At least one P-pickup structure distributes by alternating with the N-pickup structure at the first direction and interleaves with the N-pickup structure at a second direction. The second direction is perpendicular to the first direction. Dummy pickup structure distributes along the first direction, opposite to the P-pickup structure with respect to the N-pickup line. Further, a cell area is beside the pickup area. The SRAM cells in the cell area form cell rows extending along the second direction. Each SRAM cell covers one N-type well region along the second direction and two P-type well regions along the second direction to sandwich the N-type well region. The N-pickup/P-pickup structures respectively provide first/second substrate voltage to the N-type/P-type well regions. |
| US09871040B2 |
Semiconductor device comprising a standard cell
Disclosed herein is a semiconductor device including two standard cells which are arranged adjacent to each other in an X direction. One of the two standard cells includes a plurality of first fins which extend in the X direction, and which are arranged along a boundary between the two standard cells in a Y direction. The other standard cell includes a plurality of second fins which extend in the X direction, and which are arranged along the boundary between the two standard cells in the Y direction. The plurality of second fins includes a dummy fin. |
| US09871036B2 |
Semiconductor device
A semiconductor chip includes a first circuit and a second circuit having different reference potentials. A first potential which is a reference potential of the first circuit is applied to the semiconductor chip through any of plural lead terminals, and a second potential which is a reference potential of the second circuit is applied to the semiconductor chip through any of plural lead terminals. A substrate of the semiconductor chip has a structure in which a buried insulating layer and a semiconductor layer of a first conductivity type are laminated on a semiconductor substrate such as a SOI substrate. A fixed potential is applied to the semiconductor substrate through a die pad and a lead terminal for a substrate potential. The fixed potential is applied to the semiconductor chip through a different route from the reference potential of the first circuit and the reference potential of the second circuit. |
| US09871033B2 |
Semiconductor integrated circuit device
Diffusion regions having the same conductivity type are arranged on a side of a second wiring and a side of a third wiring, respectively under a first wiring connected to a signal terminal. Diffusion regions are separated in a whole part or one part of a range in a Y direction. That is, under first wiring, diffusion regions are only formed in parts opposed to diffusion regions formed under the second wiring and third wiring connected to a power supply terminal or a ground terminal, and a diffusion region is not formed in a central part in an X direction. Therefore, terminal capacity of the signal terminal can be reduced without causing ESD resistance to be reduced, in an ESD protection circuit with the signal terminal. |
| US09871032B2 |
Gate-grounded metal oxide semiconductor device
A gate-grounded metal oxide semiconductor (GGMOS) device is disclosed. The GGMOS is an n-type (GGNMOS) transistor used as an electrostatic discharge (ESD) protection device. The GGMOS includes a base extension region under an elevated source. The elevated source and base extension regions increase Leff and reduce beta, increasing performance of the ESD protection. |
| US09871028B1 |
Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including tip-to-tip short configured fill cells, and the second DOE including chamfer short configured fill cells
A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOEs), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of tip-to-tip shorts, and the second DOE contains fill cells configured to enable NC detection of chamfer shorts. The process may further include obtaining NC measurements from the first and/or second DOE(s) and using such measurements, at least in part, to selectively perform additional processing, metrology or inspection steps on the wafer, and/or on other wafer(s) currently being manufactured. |
| US09871026B2 |
Embedded memory and power management subpackage
Embodiment of the present disclosure describe integrated circuit package assemblies that allow for relatively short connections between devices such as a processor and memory. In one embodiment, a package assembly includes a die embedded in a subpackage directly coupled to another die attached to the subpackage. In some embodiments the subpackage may also contain power management devices. In some embodiments the die embedded in the subpackage and/or the power management device may overlap, or be located in, a region defined by the die coupled to the subpackage such that they are located between the die coupled to the subpackage and a substrate underlying the subpackage. Other embodiments may be described and/or claimed. |
| US09871024B2 |
Light-emitting apparatus and illumination apparatus
A light-emitting apparatus is provided. The light-emitting apparatus includes a first and second light-emitting elements disposed on a substrate. A sealing layer is above the first and second light-emitting elements for sealing the first and second light-emitting elements. A first phosphor layer is above a first portion of the sealing layer. The first phosphor layer includes at least one first phosphor. A second phosphor layer is above a second portion of the sealing layer. The second phosphor layer includes at least one second phosphor. The first phosphor layer is configured to emit light, which is emitted as a result of emission by the first light-emitting element, having a first color. The second phosphor layer is configured to emit light, which is emitted as a result of emission by the second light-emitting element, having a second color different from the first color. |
| US09871021B2 |
Data storage device having multi-stack chip package and operating method thereof
Disclosed is a data storage device including a controller and a multi-stack chip package, and a method of operating a data storage device. The multi-stack chip package includes a first semiconductor chip arranged on a package substrate, a second semiconductor chip arranged on the first semiconductor chip, and a third semiconductor chip is arranged between the first and second semiconductor chips. The controller can control the first to third semiconductor chips by using a feature parameter measured from each semiconductor chip and a target value that may be originally designed by a memory vendor. |
| US09871018B2 |
Packaged semiconductor devices and methods of packaging semiconductor devices
Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming a mask coating over a carrier, coupling an integrated circuit die over the mask coating, and disposing a molding compound around the integrated circuit die. The method includes forming an interconnect structure over the integrated circuit die and the molding compound. |
| US09871016B2 |
Semiconductor package
Provided is a semiconductor package including a substrate; at least one semiconductor chip mounted on the substrate; a molding element, which is arranged on the substrate and encapsulates the at least one semiconductor chip; and a lattice element, which is arranged inside the molding element, where the lattice element includes a body having a plurality of openings. |
| US09871015B1 |
Wafer level package and fabrication method
A method of forming an electronic component package includes coupling a first surface of an electronic component to a first surface of a first dielectric strip, the electronic component comprising bond pads on the first surface; forming first via apertures through the first dielectric strip to expose the bond pads; and filling the first via apertures with an electrically conductive material to form first vias electrically coupled to the bond pads. The bond pads are directly connected to the corresponding first vias without the use of a solder and without the need to form a solder wetting layer on the bond pads. |
| US09871014B2 |
3D-joining of microelectronic components with conductively self-adjusting anisotropic matrix
3D joining of microelectronic components and a conductively self-adjusting anisotropic matrix are provided. In an implementation, an adhesive matrix automatically makes electrical connections between two surfaces that have electrical contacts, and bonds the two surfaces together. Conductive members in the adhesive matrix are aligned to automatically establish electrical connections between at least partially aligned contacts on each of the two surfaces while providing nonconductive adhesion between parts of the two surfaces lacking aligned contacts. An example method includes forming an adhesive matrix between two surfaces to be joined, including conductive members anisotropically aligned in an adhesive medium, then pressing the two surfaces together to automatically connect corresponding electrical contacts that are at least partially aligned on the two surfaces. The adhesive medium in the matrix secures the two surfaces together. |
| US09871012B2 |
Method and apparatus for routing die signals using external interconnects
Various aspects of an approach for routing die signals in an interior portion of a die using external interconnects are described herein. The approach provides for contacts coupled to circuits in the interior portion of the die, where the contacts are exposed to an exterior portion of the die. The external interconnects are configured to couple these contacts so that signals from the circuits in the interior portion of the die may be routed externally to the die. In various aspects of the disclosed approach, the external interconnects are protected by a packaging for the die. |
| US09871009B2 |
Semiconductor device and method
A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures. |
| US09871005B2 |
Semiconductor device package and method of manufacturing the same
A semiconductor device package includes a carrier, an electronic component disposed over a top surface of the carrier, and a package body disposed over the top surface of the carrier and covering the electronic component. The semiconductor device package further includes a shield layer, which in turn includes a first electrically conductive layer, a first magnetically permeable layer, and a second electrically conductive layer, where the first magnetically permeable layer is interposed between and directly contacts the first electrically conductive layer and the second electrically conductive layer. |
| US09871003B2 |
Mark forming method and device manufacturing method
A mark forming method includes: a step of forming, on a device layer of a wafer, an intermediate layer to which a polymer layer containing a block copolymer is adherable, the device layer including a shot area and a scribe line area; a step of removing a portion, of the intermediate layer, formed in the scribe line area; a step of exposing an image of a mark on the scribe line area and forming, based on the image of the mark, a mark including recessed portion; and a step of applying the polymer layer containing the block copolymer on the device layer of the wafer. When a circuit pattern is formed by using the self-assembly of the block copolymer, it is possible to form the mark simultaneously with the formation of the circuit pattern. |
| US09871001B2 |
Feeding overlay data of one layer to next layer for manufacturing integrated circuit
A method of manufacturing an integrated circuit includes the following steps. A substrate including a plurality of exposure fields is provided, and each of the exposure fields includes a target portion and a set of overlay marks. The substrate is exposed to form a first layer lithography pattern on the target portion for the respective exposure field by an exposure system. The overlay of the first layer lithography pattern and the target portion is measured by the set of overlay marks of each exposure field to obtain first overlay data for the respective exposure field by a measuring system. The first overlay data is fed to form a second layer lithography pattern. |
| US09871000B2 |
Semiconductor device and manufacturing method, and electronic apparatus
The present disclosure relates to a semiconductor device and a manufacturing method, and an electronic apparatus that enable manufacturing of a stacked structure with high precision. A solid-state image sensor includes a semiconductor substrate where a photodiode is formed, and an epitaxial layer where a transfer transistor to be stacked on the photodiode of the semiconductor substrate is formed, the epitaxial layer being formed by growing a crystalline layer with aligned crystal axes on the semiconductor substrate. A reentrant portion formed at an end portion of a registration measurement mark used for registration measurement to perform relative adjustment before and after a step of forming the epitaxial layer is formed to be distanced from a detection region for detecting the registration measurement mark by a predetermined distance. The present technology can be applied to, for example, various semiconductor devices having a stacked structure. |
| US09870996B1 |
Semiconductor device and method of fabricating the same
A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate, a plurality of gates and a plurality of plugs. The gates are disposed on the substrate and extend in a first direction. The gates include a first gate and a second gate. The first gate includes a first protruding portion extending in a second direction. The plugs are disposed parallel to one another on the substrate. The plugs include a first plug and a second plug. The first plug and the second plug cover the first gate and the second gate respectively. A central axis of the first plug is shifted from a central axis of the first gate toward the second direction, and a central axis of the second plug is shifted from a central axis of the second gate toward the second direction. |
| US09870994B2 |
Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an ultra low-k (ULK) dielectric layer on the substrate; forming a hard mask on the ULK dielectric layer; forming an opening in the hard mask and the ULK dielectric layer; forming a conductive layer in the opening and on the hard mask; planarizing the conductive layer; and removing the hard mask to expose the ULK dielectric layer so that the top surface of the ULK dielectric layer is lower than the top surface of the conductive layer. |
| US09870986B2 |
Single or multi chip module package and related methods
Implementations of a semiconductor device package may include: a plurality of electrical contacts on a first face of a die, at least one clip electrically and mechanically coupled with at least one electrical contact on a second face of the die where the second face of the die is on an opposing side of the die from the first face of the die. The at least one clip may include at least one lead in electrical communication with the at least one electrical contact on the second face of the die. A mold compound or an encapsulating compound may be included around the die and a majority of the at least one clip where a portion of the at least one lead and a portion of the plurality of electrical contacts on the first face of the die are not overmolded or encapsulated. The semiconductor package includes no lead frame. |
| US09870984B2 |
Power field-effect transistor (FET), pre-driver, controller, and sense resistor integration for multi-phase power applications
Techniques are described for integrating power field-effect transistors (FETs), pre-drivers, controllers, and/or resistors into a common multi-chip package for implementing multi-phase bridge circuits. The techniques may provide a multi-chip package with at least two high-side (HS) FETs and at least two low-side (LS) FETs, and place the at least two HS FETs or the at least LS FETs on a common die. Placing at least two FETs on a common die may reduce the number of die and the number of thermal pads (i.e., die pads) needed to implement a set of power FETs, thereby decreasing component count of a multi-phase bridge circuit and/or allowing a more compact, higher current density multi-phase bridge circuit to be obtained without significantly increasing thermal power dissipation of the circuit. |
| US09870979B2 |
Double-sided segmented line architecture in 3D integration
Embodiments of the present invention relate generally to electronic components such as semiconductor wafers and more particularly, to a double-sided three-dimensional (3D) hierarchal architecture scheme for multiple semiconductor wafers using an arrangement of through silicon vias (TSVs) and backside wiring. In an embodiment a first word line architecture may be formed on a front side of an IC chip and connected to a second word line architecture formed on a back side of the IC chip through intra-wafer, TSVs, thereby relocating required wiring to the back side of the IC chip. |
| US09870977B2 |
Semiconductor device with heat information mark
A semiconductor device includes a semiconductor package and a mark. The semiconductor package includes a semiconductor chip including a hot spot from which heat is generated, and a mold layer encapsulating the semiconductor chip. The mark is disposed on the semiconductor package. The mark is formed in a region of the semiconductor package that corresponds to a position of the hot spot. |
| US09870969B2 |
Substrate
The present invention relates to a substrate comprising a build-up and a solder resist layer disposed on the build-up. The solder resist layer has an upper surface facing away from the build-up. The solder resist layer has a plurality of grooves on its upper surface. The grooves of the solder resist layer can better eliminate or relieve the stress accumulated on large solder resist area induced by heat and/or material coefficient of thermal expansion mismatch of the substrate and thus can prevent and diminish warpage of the substrate or package. |
| US09870968B2 |
Repackaged integrated circuit and assembly method
A packaged integrated circuit for operating reliably at elevated temperatures is provided. The packaged integrated circuit includes a reconditioned die, which includes a fully functional semiconductor die that has been previously extracted from a different packaged integrated circuit. The packaged integrated circuit also includes a hermetic package comprising a base and a lid and a plurality of bond wires. The reconditioned die is placed into a cavity in the base. After the reconditioned die is placed into the cavity, the plurality of bond wires are bonded between pads of the reconditioned die and package leads of the hermetic package base or downbonds. After bonding the plurality of bond wires, the lid is sealed to the base. |
| US09870967B2 |
Plurality of seals for integrated device package
Semiconductor packages and methods of manufacturing semiconductor packages are described herein. In certain embodiments, the semiconductor package includes a substrate, a wall attached to the substrate, a first adhesive layer disposed between a bottom surface of the wall and a top surface of the substrate, and a second adhesive layer disposed around an outer perimeter of the first adhesive layer, the second adhesive layer disposed adjacent and contacting the wall, the second adhesive layer different from the first adhesive layer, wherein at least one of the first adhesive layer and the second adhesive layer connects the wall to electrical ground. |
| US09870965B2 |
Semiconductor device
Provided is a semiconductor device including a semiconductor substrate; a dummy trench that is formed on a front surface side of the semiconductor substrate; an emitter electrode that is formed above a front surface of the semiconductor substrate and includes a recessed portion that is a recess in an outer periphery thereof, as seen in a planar view; a dummy pad that is electrically connected to the dummy trench and has at least a portion thereof formed within the recessed portion, as seen in the planar view; and a dummy wire that electrically connects the emitter electrode and the dummy pad. |
| US09870964B1 |
Method of manufacturing semiconductor device by determining and selecting cooling recipe based on temperature
The present disclosure provides a technique including a method of manufacturing a semiconductor device, which is capable of improving a processing uniformity of a plurality of substrates. The method may include: (a) subjecting a substrate accommodated in one of a plurality of process chambers to a thermal process: (b) transferring the substrate processed in (a) by a transfer robot provided in a vacuum transfer chamber connected to the plurality of process chambers from the one of a plurality of process chambers to a loadlock chamber connected to the vacuum transfer chamber; and (c) cooling the substrate accommodated in the loadlock chamber by supplying an inert gas to the substrate accommodated in the loadlock chamber according to a cooling recipe. |
| US09870963B2 |
Endpoint booster systems and methods for optical endpoint detection
An endpoint booster transports an optical signal from inside of a plasma etch chamber through a viewport to an optical cable outside of the plasma etch chamber. The optical signal is analyzed to determine an endpoint of a plasma process. The endpoint booster inhibits process byproducts from accumulating on the viewport during the plasma process, which increases the time between chamber cleanings. The reduction in chamber downtime for cleaning increases production throughput. |
| US09870962B1 |
Integrated circuit including NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
An integrated circuit, in the form of a wafer, die, or chip, includes multiple standard cell-compatible fill cells, configured to enable non-contact electrical measurements. Such fill cells include mesh pads that contain at least three conductive stripes disposed between adjacent gate stripes. Such fill cells further include geometry to enable non-contact evaluation of interlayer overlap shorts and/or leakages. |
| US09870960B2 |
Capacitance monitoring using X-ray diffraction
A method includes measuring a difference between a primary X-ray diffraction peak and a secondary X-ray diffraction peak, the primary X-ray diffraction peak corresponds to an unstrained portion of a semiconductor substrate and the secondary X-ray diffraction peak corresponds to a strained portion of the semiconductor substrate, the difference between the primary X-ray diffraction peak and the secondary X-ray diffraction peak includes a delta shift peak that corresponds to changes in a crystal lattice caused by a stress applied to the strained portion of the semiconductor substrate, the delta shift peak includes variations in a deep trench capacitance. |
| US09870951B2 |
Method of fabricating semiconductor structure with self-aligned spacers
A method of fabricating a semiconductor with self-aligned spacer includes providing a substrate. At least two gate structures are disposed on the substrate. The substrate between two gate structures is exposed. A silicon oxide layer is formed to cover the exposed substrate. A nitride-containing material layer covers each gate structure and silicon oxide layer. Later, the nitride-containing material layer is etched to form a first self-aligned spacer on a sidewall of each gate structure and part of the silicon oxide layer is exposed, wherein the sidewalls are opposed to each other. Then, the exposed silicon oxide layer is removed to form a second self-aligned spacer. The first self-aligned spacer and the second self-aligned spacer cooperatively define a recess on the substrate. Finally, a contact plug is formed in the recess. |
| US09870950B2 |
Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device according to one or more exemplary embodiments of the present inventive concept includes forming a plurality of dummy gates on a substrate. Each of the dummy gates includes a gate mask disposed on an upper surface of each of the dummy gates. A spacer is disposed on at least two sides of the dummy gates. An insulating interlayer is formed on the gate mask and the spacer. A first polishing including chemical mechanical polishing is performed on portions of the gate mask and the insulating interlayer by using a slurry composite having a first mixing ratio. A second polishing including chemical mechanical polishing is formed on remaining portions of the gate mask and the insulating interlayer to expose upper surfaces of the plurality of dummy gates, by using a slurry composite having a second mixing ratio. |
| US09870949B2 |
Semiconductor device and formation thereof
A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a first wall extending along a first plane, the fin including a doped region defining a first furrow on a first side of the first plane. A dielectric is disposed within the first furrow, such that the dielectric is in contact with the first furrow between a first end of the dielectric and a second end of the dielectric. The first end is separated a first distance from the first plane. The dielectric disposed within the furrow increases the isolation of a channel portion of adjacent fins, and thus decreases current leakage of a FinFet, as compared to a FinFet including fins that do not include a dielectric disposed within a furrow. |
| US09870946B2 |
Wafer level package structure and method of forming same
An embodiment is a package including a first package component. The first package component including a first die attached to a first side of a first interconnect structure, a molding material surrounding the first die, and a second interconnect structure over the molding material and the first die, a first side of the second interconnect structure coupled to the first die with first electrical connectors. The first package component further includes a plurality of through molding vias (TMVs) extending through the molding material, the plurality of TMVs coupling the first interconnect structure to the second interconnect structure, and a second die attached to a second side of the second interconnect structure with second electrical connectors, the second side of the second interconnect structure being opposite the first side of the second interconnect structure. |
| US09870937B2 |
High productivity deposition reactor comprising a gas flow chamber having a tapered gas flow space
High productivity thin film deposition methods and tools are provided wherein a thin film semiconductor material layer with a thickness in the range of less than 1 micron to 100 microns is deposited on a plurality of wafers in a reactor. The wafers are loaded on a batch susceptor and the batch susceptor is positioned in the reactor such that a tapered gas flow space is created between the susceptor and an interior wall of the reactor. Reactant gas is then directed into the tapered gas space and over each wafer thereby improving deposition uniformity across each wafer and from wafer to wafer. |
| US09870936B2 |
Wafer carrier purge apparatuses, automated mechanical handling systems including the same, and methods of handling a wafer carrier during integrated circuit fabrication
A wafer carrier purge apparatus, an automated mechanical handling system, and a method of handling a wafer carrier during integrated circuit fabrication are provided. The wafer carrier purge apparatus includes a purge plate adapted for insertion into a carrier storage position. The purge plate includes a gas port and a gas nozzle in fluid communication with the gas port. The gas port receives a gas flow. The gas nozzle is adapted to contact an inlet port of a wafer carrier. The purge plate further includes a vacuum port and a vacuum nozzle in fluid communication with the vacuum port, spaced from the gas nozzle. The vacuum nozzle is adapted to capture gas that escapes from the wafer carrier through an outlet port of the wafer carrier. The purge plate is separate and removable from the carrier storage position. |
| US09870935B2 |
Monitoring system for deposition and method of operation thereof
A monitoring and deposition control system and method of operation thereof including: a deposition chamber for depositing a material layer on a substrate; a sensor array for monitoring deposition of the material layer for changes in a layer thickness of the material layer during deposition; and a processing unit for adjusting deposition parameters based on the changes in the layer thickness during deposition. |
| US09870932B1 |
Pressure purge etch method for etching complex 3-D structures
A method for etching a substrate and removing byproducts includes a) setting process parameters of a processing chamber for a selective dry etch process; b) setting process pressure of the processing chamber to a first predetermined pressure in a range from 1 Torr to 10 Torr for the selective dry etch process; c) selectively etching a first film material of a substrate relative to a second film material of the substrate in the processing chamber during a first period; d) lowering pressure in the processing chamber to a second predetermined pressure that is less than the first predetermined pressure by a factor greater than or equal to 4; and e) purging the processing chamber at the second predetermined pressure for a second period. |
| US09870926B1 |
Semiconductor device and manufacturing method thereof
A method of manufacturing a source structure for a p-type metal-oxide-semiconductor (PMOS) field effect transistor (FET) is provided. In the method, a first epitaxial layer comprising Si1-xGex is formed on a source region of an FET, a second epitaxial layer comprising Si1-yGey is formed on the first epitaxial layer, a third epitaxial layer comprising Si1-zGez is formed on the second epitaxial layer. Z is smaller than y. |
| US09870925B1 |
Quantum doping method and use in fabrication of nanoscale electronic devices
A novel doping technology for semiconductor wafers has been developed, referred to as a “quantum doping” process that permits the deposition of only a fixed, controlled number of atoms in the form of a monolayer in a substitutional condition where only unterminated surface bonds react with the dopant, thus depositing only a number of atoms equal to the atomic surface density of the substrate material. This technique results in providing a “quantized” set of possible dopant concentration values that depend only on the additional number of layers of substrate material formed over the single layer of dopant atoms. |
| US09870921B2 |
Cleaning method
Implementations of the present disclosure generally relate to methods and apparatuses for epitaxial deposition on substrate surfaces. More particularly, implementations of the present disclosure generally relate to methods and apparatuses for surface preparation prior to epitaxial deposition. In one implementation, a method of processing a substrate is provided. The method comprises etching a surface of a silicon-containing substrate by use of a plasma etch process, where at least one etching process gas comprising chlorine gas and an inert gas is used during the plasma etch process and forming an epitaxial layer on the surface of the silicon-containing substrate. |
| US09870920B2 |
Growing III-V compound semiconductors from trenches filled with intermediate layers
A method of forming an integrated circuit structure includes forming an insulation layer over at least a portion of a substrate; forming a plurality of semiconductor pillars over a top surface of the insulation layer. The plurality of semiconductor pillars is horizontally spaced apart by portions of the insulation layer. The plurality of semiconductor pillars is allocated in a periodic pattern. The method further includes epitaxially growing a III-V compound semiconductor film from top surfaces and sidewalls of the semiconductor pillars. |
| US09870919B2 |
Process chamber having separate process gas and purge gas regions
Embodiments of the present invention generally relate to chambers and methods of processing substrates therein. The chambers generally include separate process gas and purge gas regions. The process gas region and purge gas region each have a respective gas inlet and gas outlet. The methods generally include positioning a substrate on a substrate support within the chamber. The plane of the substrate support defines the boundary between a process gas region and purge gas region. Purge gas is introduced into the purge gas region through at least one purge gas inlet, and removed from the purge gas region using at least one purge gas outlet. The process gas is introduced into the process gas region through at least one process gas inlet, and removed from the process gas region through at least one process gas outlet. The process gas is thermally decomposed to deposit a material on the substrate. |
| US09870909B2 |
Compositions and methods for mass spectometry
The invention provides ionizing matrix compounds. These compounds are useful for mass spectrometry and ion mobility spectrometry as ionizing matrices facilitating transfer of diverse classes of analyte compounds from solid or solution states to gas-phase ions. |
| US09870908B2 |
Ambient ionisation with an impactor spray source
An ion source is disclosed comprising a nebulizer arranged and adapted to emit a liquid spray, a first target arranged downstream of the nebulizer, wherein the liquid spray is arranged to impact upon the first target, and a sample target arranged downstream of the first target, wherein a sample to be analyzed is provided at the sample target. |
| US09870905B2 |
Method of generating electric field for manipulating charged particles
A method of manufacturing a device for manipulating charged particles using an axial electric field as they travel along a longitudinal axis of the device is disclosed. The method comprises providing first electrodes of different lengths, supplying different voltages to these electrodes and arranging grounded electrodes between the first electrodes in order to form the desired axial potential profile. |
| US09870903B2 |
Adaptive and targeted control of ion populations to improve the effective dynamic range of mass analyser
A method of mass spectrometry is disclosed wherein one or more relatively abundant or intense species of ions in a first population of ions are selectively attenuated so as to form a second population of ions. The total ion current of the second population of ions is then adjusted so that the ion current corresponding to ions which are onwardly transmitted to a mass analyzer comprising an ion detector is within the dynamic range of the ion detector. |
| US09870902B2 |
Li-containing oxide target assembly
Provided is a target assembly which is manufactured by bonding a Li-containing oxide sputtering target and an Al-based or Cu-based backing plate through a bonding material. The Li-containing oxide target assembly does not undergo warping or cracking during the bonding. The Li-containing oxide target assembly according to the present invention is manufactured by bonding a Li-containing oxide sputtering target to a backing plate via a bonding material, and has bending strength of 20 MPa or larger. |
| US09870899B2 |
Cobalt etch back
Methods of etching cobalt on substrates are provided. Some methods involve exposing the substrate to a boron-containing halide gas and an additive, and exposing the substrate to an activation gas and a plasma. Additives improve selectively depositing a thicker layer of a boron-containing halide material on a surface of a mask than on a surface of a metal. Additives include H2, CH4, CF4, NF3, and Cl2. Boron-containing halide gases include BCl3, BBr3, BF3, and BI3. Exposures may be performed in two or more cycles, with variations in durations and/or bias power for each exposure in the two or more cycles. |
| US09870892B2 |
Periodic modulation of the X-ray intensity
In order to provide an increased, i.e. faster, periodic modulation of X-ray intensity, an anode disk (28) for a rotating anode in an X-ray tube includes a circumferential target area (34) with a target surface area (36), a focal track center line (38), and a beam-dump surface area (40). The target surface area when hit by an electron beam generates X-rays. The beam-dump surface area when hit by an electron beam generates no useful X-rays Target portions and beam-dump portions are arranged alternatingly along the focal track center line. A focal spot is centered on the focal track center line. Structures on both sides of the focal track center line are arranged such that same radiation intensities are provided by the both sides when being hit by a homogenous electron beam. |
| US09870891B1 |
High gradient permanent magnet elements for charged particle beamlines
The present invention provides a technique for constructing compact, high gradient magnetic lenses for charged particle beam focusing. Methods for adjusting the focusing strength of the lenses are provided, based on thermal control, mechanical motion of the magnetic chips within the yoke. The present invention is a method for designing and fabricating permanent magnet focusing elements that are compact, simple to construct, and having a large, adjustable focusing strength. Applications include beamlines for THz radiation sources, free electron lasers, wakefield accelerators and any other charged particle devices that require a compact beamline. |
| US09870882B2 |
Push button for motor vehicle key module
The invention relates to a button of the push-button type, comprising: a fixed part (3) forming a chassis, a mobile part (5) capable of translational movement between a rest position, adopted in the absence of actuation by a user, and an actuating position, adopted when the mobile part (5) is depressed with respect to the fixed part (3), a switch (7) toggling from a first state to a second when the mobile part (3) is brought into the actuating position, a flexible membrane (9) positioned between the mobile part (5) and the switch (7), connected by its edges to the fixed part (3) and returning the mobile part (5) to the rest position in the absence of actuation by the user, characterized in that: the membrane (9) has a thinning (15) of its thickness facing the switch (7). The invention also relates to the vehicle key module comprising at least one such button (1). |
| US09870879B2 |
Controlled switching devices and method of using the same
It is disclosed a technique in which Controlled Switching Devices (CSDs) are used to control medium and high voltage circuit breakers to mitigate switching transients. This invention describes a method for controlling the closing of a circuit breaker to mitigate and/or eliminate the inrush current in capacitive loads such as capacitor banks and filters by taking into account the residual DC voltage charges that may be present in the load. It is disclosed a method to perform fast switching operations on capacitive loads and therefore eliminate the load discharge period. |
| US09870872B2 |
Asymmetric electrical double-layer capacitor using electrochemical activated carbon
An asymmetric supercapacitor includes a negative electrode made of a first carbon, a positive electrode made of a soft carbon, a separator and an electrolyte. The separator is disposed in between the negative and positive electrodes. The soft carbon has an activation threshold (AT) larger than 1400, and the activation threshold (AT) is obtained from the following formula: AT=La*(Aa/Ac). La is an in-plane correlation length of the soft carbon, Aa is an area of amorphous peak of the soft carbon analysed by X-ray diffraction in Gaussian distribution graph, and Ac is an area of crystalline peak of the soft carbon analysed by X-ray diffraction in Gaussian distribution graph. |
| US09870870B2 |
Energy storage apparatus
Energy storage apparatus comprising: a porous conductor substrate, an insulator layer in contact with inner surfaces of the porous conductor substrate, and a conductor layer in contact with outer surfaces of the insulator layer. |
| US09870868B1 |
Wet electrolytic capacitor for use in a subcutaneous implantable cardioverter-defibrillator
A wet electrolytic capacitor that contains a casing that contains a cylindrical sidewall is provided. The cylindrical sidewall defines an inner surface that surrounds an interior. First and second outer anodes are positioned within the interior of the casing. The first outer anode has a radiused sidewall and an opposing planar sidewall and the second outer anode has a radiused sidewall and an opposing planar sidewall. A central anode is also positioned within the interior of the casing between the first and second outer anodes. The central anode contains opposing first and second outer sidewalls intersecting with opposing first and second inner sidewalls. The first and second inner sidewalls are planar, and the first planar inner sidewall of the central anode faces the planar sidewall of the first outer anode and the second planar inner sidewall of the central anode faces the planar sidewall of the second outer anode. |
| US09870867B2 |
Capacitor anode, solid electrolytic capacitor element, solid electrolytic capacitor, and method for producing capacitor anode
When forming a conductive polymer layer serving as a cathode of a solid electrolytic capacitor, in order to obtain a high capacitance even with a small number of times of polymerization treatments, a capacitor anode according to the present invention includes a tungsten sintered body (2) and is provided with a dielectric film (1), and in which vanadium oxide is deposited on the surface of the dielectric film (1). |
| US09870864B2 |
Ceramic electronic component
A ceramic electronic component includes a laminated body including ceramic layers and conductor layers stacked alternately; and first and second external electrodes provided on portions of the laminated body. Each of the first and second external electrodes includes a sintered metal layer provided on the laminated body, a conductive resin layer covering the sintered metal layer, and a plated layer covering the conductive resin layer. The maximum length of the sintered metal layer provided on the second principal surface is shorter than the maximum length of the sintered metal layer provided on each of the first and second side surfaces. |
| US09870858B2 |
Fluxgate device with low fluxgate noise
An integrated fluxgate device, which includes a magnetic core, an excitation coil, and a sense coil. The magnetic core has a longitudinal edge and a terminal edge. The excitation coil coils around the longitudinal edge of the magnetic core, and the excitation coil has a first number of excitation coil members within a proximity of the terminal edge. The sense coil coils around the longitudinal edge of the magnetic core, and the sense coil has a second number of sense coil members within the proximity of the terminal edge. For reducing fluxgate noise, the second number of sense coil members may be less than the first number of excitation coil members within the proximity of the terminal edge. |
| US09870857B2 |
Common-mode choke coil
A common-mode choke coil having: a core that extends in a predetermined direction; and first and second wires that are intertwined and wound together around the core. |
| US09870856B2 |
Magnetic component assembly with filled physical gap
Magnetic component assemblies for circuit boards include single, shaped magnetic core pieces formed with a physical gap and conductive windings assembled to the cores via the gaps. The physical gaps in the cores are filled with a magnetic material to enhance the magnetic performance. The magnetic component assemblies may define power inductors. |
| US09870848B2 |
Multiple stress control device for cable accessories and methods and systems including same
Provided are devices, methods and systems. A cover system may include a unitary cold shrinkable, tubular, elastomeric cover sleeve defining a cover sleeve through passage that is configured to receive the electrical cable. The cover sleeve may include a first type of stress control element and a second type of stress control element that is different from the first type of stress control element. A holdout maintains the cover sleeve in an expanded state in which the cover sleeve is elastically expanded and when removed, permits the cover sleeve to radially contract to a contracted state about the electrical cable. The first type of stress control element includes a geometric stress cone that includes an electrically conductive and/or semiconductive portion that is configured to conductively engage a semiconductor layer of the electrical cable. The second type of stress control element includes a high-K stress relief element. |
| US09870846B2 |
Telecommunications wire having a channeled dielectric insulator and methods for manufacturing the same
The present disclosure relates generally to a telecommunications wire including an electrical conductor and a dielectric insulator surrounding the electrical conductor. The dielectric insulator defines a plurality of channels defining void space containing a material having a low dielectric constant such as air. The channels each run along a length of the electrical conductor. The channels are configured to lower an overall dielectric constant of the dielectric insulator while maintaining desirable mechanical properties such as crush resistance. |
| US09870844B2 |
Methods of coating an electrically conductive substrate and related electrodepositable compositions
A method of producing an electrode for a lithium ion battery is disclosed in which an electrically conductive substrate is immersed into an electrodepositable composition, the substrate serving as the electrode in an electrical circuit comprising the electrode and a counter-electrode immersed in the composition, a coating being applied onto or over at least a portion of the substrate as electric current is passed between the electrodes. The electrodepositable composition comprises: (a) an aqueous medium; (b) an ionic (meth)acrylic polymer; and (c) solid particles comprising: (i) lithium-containing particles, and (ii) electrically conductive particles, wherein the composition has a weight ratio of solid particles to ionic (meth)acrylic polymer of at least 4:1. |
| US09870840B2 |
Metallic glass, conductive paste, and electronic device
According to example embodiments, a metallic glass includes aluminum (Al), a first element group, and a second element group. The first element group includes at least one of a transition metal and a rare earth element. The second element group includes at least one of an alkaline metal, an alkaline-earth metal, a semi-metal, and a non-metal. The second element group and aluminum have an electronegativity difference of greater than or equal to about 0.25. The second element group is included less than or equal to about 3 at % of the metallic glass, based on the total amount of the aluminum (Al), the first element group, and the second element group. A conductive paste and/or an electrode of an electronic device may be formed using the metallic glass. |
| US09870839B2 |
Frequency- and amplitude-modulated narrow-band infrared emitters
IR emission devices comprising an array of polaritonic IR emitters arranged on a substrate, where the emitters are coupled to a heater configured to provide heat to one or more of the emitters. When the emitters are heated, they produce an infrared emission that can be polarized and whose spectral emission range, emission wavelength, and/or emission linewidth can be tuned by the polaritonic material used to form the elements of the array and/or by the size and/or shape of the emitters. The IR emission can be modulated by the induction of a strain into a ferroelectric, a change in the crystalline phase of a phase change material and/or by quickly applying and dissipating heat applied to the polaritonic nanostructure. The IR emission can be designed to be hidden in the thermal background so that it can be observed only under the appropriate filtering and/or demodulation conditions. |
| US09870832B2 |
Control signal generation circuit and non-volatile memory device including the same
A control signal generation circuit may include: a counting unit suitable for generating counting information; a first signal generation unit suitable for activating/deactivating a first signal based on the counting information, first rising information, and first falling information; a second signal generation unit suitable for activating/deactivating a second signal based on the counting information, second rising information, second falling information, and the first falling information; and a control signal driving unit suitable for driving a control signal in response to the first and second signals. |
| US09870825B2 |
Nonvolatile memory device and method of programming the same
A nonvolatile memory device includes a memory cell array, an address decoder, a read & write circuit and control logic. The memory cell array includes a plurality of memory blocks including a plurality of cell strings, each cell string including a plurality of memory cells stacked in a direction perpendicular to a substrate. The control logic controls operations so that in a program operation, when the selected word line satisfies a precharge condition, a program voltage to be applied to the selected word line is applied before a pass voltage to be applied to an unselected word line. |
| US09870824B2 |
Iterator register for structured memory
Loading data from a computer memory system is disclosed. A memory system is provided, wherein some or all data stored in the memory system is organized as one or more pointer-linked data structures. One or more iterator registers are provided. A first pointer chain is loaded, having two or more pointers leading to a first element of a selected pointer-linked data structure to a selected iterator register. A second pointer chain is loaded, having two or more pointers leading to a second element of the selected pointer-linked data structure to the selected iterator register. The loading of the second pointer chain reuses portions of the first pointer chain that are common with the second pointer chain.Modifying data stored in a computer memory system is disclosed. A memory system is provided. One or more iterator registers are provided, wherein the iterator registers each include two or more pointer fields for storing two or more pointers that form a pointer chain leading to a data element. A local state associated with a selected iterator register is generated by performing one or more register operations relating to the selected iterator register and involving pointers in the pointer fields of the selected iterator register. A pointer-linked data structure is updated in the memory system according to the local state. |
| US09870822B2 |
Non-volatile memory element with thermal-assisted switching control
A non-volatile memory element with thermal-assisted switching control is disclosed. The non-volatile memory element is disposed on a thermal inkjet resistor. Methods for manufacturing the combination and methods of using the combination are also disclosed. |
| US09870820B2 |
Apparatuses and methods for current limitation in threshold switching memories
Apparatuses and methods for limiting current in threshold switching memories are disclosed. An example apparatus may include a plurality of first decoder circuits, a plurality of second decoder circuits, an array of memory cells, and a control circuit. Each memory cell of the array of memory cells may be cells coupled to a pair of first decoder circuits of the plurality of first decoder circuits, and further coupled to a pair of second decoder circuits of the plurality of second decoder circuits. The control circuit may be coupled to the plurality of first decoder circuits and the plurality of second decoder circuits, and the control circuit may be configured to activate a first one of the pair of first decoder circuits coupled to a memory cell of the array of memory cells before a second one of the pair of first decoder circuits, and further configured to activate a first one of the pair of second decoder circuits coupled to the memory cell of the array of memory cells before a second one of the pair of second decoder circuits to access the a memory cell. |
| US09870819B2 |
Semiconductor device and information reading method
A semiconductor device including a memory device configured to take a plurality of resistance states that are distinguishable from one another; a bias application section configured to apply, in a bias application period, a bias signal to the memory device; and a determination section configured to determine a resistance state of the memory device on the basis of a detection signal, in which the detection signal is generated in the memory device to which the bias signal is applied. The bias application section sets a length of the bias application period in accordance with a resistance value of the memory device, when the resistance state determined by the determination section is predetermined one of the resistance states. |
| US09870818B1 |
Separate read and write address decoding in a memory system to support simultaneous memory read and write operations
Memory systems that provide separate read and write address decoding to support simultaneous memory read and write operations are disclosed. Separating read and write address decoding can avoid circuit conflicts for a simultaneous memory read and write operation even if employing single port memory bit cells. The read and write addresses of respective read and write operations are separately decoded into read and write row and column selects driven to a memory array so that simultaneous read and write operations are not affected by each other. To avoid a circuit conflict for a simultaneous read and write operation, the memory system is configured to prioritize a write row select over a read row select to drive a row of memory bit cells in the memory array. In this manner, that write operation will always be successful regardless of whether the read and write row select are to the same row. |
| US09870816B2 |
Method for driving semiconductor device
A semiconductor device includes SRAM that stores data in an inverter loop including a CMOS inverter, transistors electrically connected to an input terminal or an output terminal of the CMOS inverter, and capacitors electrically connected to the corresponding transistors. The semiconductor device is configured to hold potentials corresponding to data at nodes between the transistors and the corresponding capacitors in a period during which supply of power to the CMOS inverter stops. In the period during which power supply stops, the potential of a wiring applying a low power supply potential is made equal to a high power supply potential to make the potentials of the input and output terminals of the CMOS inverter equal to the high power supply potential. The potentials corresponding to the data held at the nodes are applied to the input and output terminals of the CMOS inverter to restart power supply. |
| US09870814B2 |
Refreshing a group of memory cells in response to potential disturbance
A detection circuit is provided for a particular group of memory cells in a memory device, where the detection circuit is to be updated in response to at least one access of data and at least one neighboring group of memory cells. The particular group of memory cells is refreshed in response to an indication from the detection circuit, where the indication indicates presence of potential disturbance of the particular group of memory cells. |
| US09870811B2 |
Physically unclonable function based on comparison of MTJ resistances
In a particular aspect, an apparatus includes a magnetic random access memory (MRAM) cell including a pair of cross coupled inverters including a first inverter and a second inverter. The first inverter includes a first transistor coupled to a first node and a second transistor coupled to the first node. The second inverter includes a third transistor coupled to a second node and a fourth transistor coupled to the second node. The MRAM cell includes a first magnetic tunnel junction (MTJ) element coupled to the second transistor and a second MTJ element coupled to the fourth transistor. The apparatus further includes a voltage initialization circuit coupled to the MRAM cell. The voltage initialization circuit is configured to substantially equalize voltages of the first node and the second node in response to an initialization signal. |
| US09870806B2 |
Hermetic sealing with high-speed transmission for hard disk drive
Embodiments disclosed herein generally relate to hermetic electrical connectors used in hard disk drives. The hermetic electrical connector includes a barrier structure having a first plurality of connecting pads disposed on a first surface of the barrier structure and a second plurality of connecting pads disposed on a second surface of the barrier structure opposite the first surface. A plurality of conductors is disposed within the barrier structure, and each conductor is coupled to a connecting pad of the first plurality of connecting pads and a corresponding connecting pad of the second plurality of connecting pads. The barrier structure further includes a dielectric material between the first and second surfaces, and one or more layers embedded in the dielectric material. The addition of the layers helps choke the helium gas flow, thus improving sealing of the electrical connector while maintaining high-speed electrical transmission. |
| US09870800B2 |
Multi-source video input
A method of merging video files into a consolidated video file includes receiving, by a computer device, plural video files from plural video capture devices. The method also includes determining, by the computer device, an overlapping portion of the plural video files. The method additionally includes creating, by the computer device, a thumbnail image associated with the determined overlapping portion. The method further includes creating, by the computer device, a single video file from the plural video files. The method also includes displaying, by the computer device, the single video file and a thumbnail image. |
| US09870799B1 |
System and method for processing ancillary data associated with a video stream
Method and system for playing back ancillary data associated with a video stream. At playback, a video stream and an audio stream containing encoded non-audio ancillary data associated with the video stream are received. The audio stream is decoded on a basis of a predefined decoding scheme in order to extract therefrom the non-audio ancillary data associated with the video stream. The video stream and its associated non-audio ancillary data are then both output for playback. This method of playback enables a non-linear editing application that supports only video and audio data to receive, preserve, display to a user for editing purposes, and transmit unsupported non-audio ancillary data, since the latter is in the form of an audio stream. |
| US09870792B2 |
Disk drive suspension assembly having a partially flangeless load point dimple
Various embodiments concern a suspension assembly of a disk drive. The suspension assembly includes a load beam comprising a major planar area formed from a substrate. The load beam further comprises a window in the substrate, a dimple formed from the substrate, and a flange. The flange is a region of the major planar area that extends partially around the dimple but does not extend along an edge of the dimple. The edge of the dimple is adjacent to the window. The dimple is in contact with the flexure. A HAMR block or other element can extend through the window. The lack of a full flange can minimize the necessary clearance between the dimple and the HAMR block or other element and thereby allow the window to be enlarged to accommodate the HAMR block or other element. |
| US09870791B1 |
Stabilization of one or more upper sensors in multi-sensor readers
A multi-sensor reader that includes a first sensor that has a first sensor stack, which includes a sensing layer that has a magnetization that changes according to an external magnetic field. The first sensor also includes a first seed layer below the first sensor stack. The multi-sensor reader also includes a second sensor stacked over the first sensor. The second sensor includes a second sensor stack, which includes a sensing layer that has a magnetization that changes according to the external magnetic field. The second sensor also includes a second seed layer below the second sensor stack. A stabilization element is included to maintain a magnetization direction of the second seed layer and to stabilize the second seed layer. |
| US09870787B1 |
Bolometer with low scattering for a heat-assisted magnetic recording slider
A slider configured for heat-assisted magnetic recording has an upper surface, an opposing air bearing surface (ABS), and a body defined between the upper surface and the ABS. The slider comprises a write pole and a near-field transducer (NFT) at or near the ABS. An optical waveguide is configured to receive light from a laser source and comprises a first cladding layer, a second cladding layer, and a core between the first and second cladding layers. The core has a width, a length, and a longitudinal axis oriented along the length of the core. A bolometer is situated within the body of the slider at a location that receives at least some of the light communicated along the waveguide used during a writing operation. The bolometer is spaced apart from the core and comprises a longitudinal axis that is oriented substantially parallel to the longitudinal axis of the core. |
| US09870785B2 |
Determining features of harmonic signals
Features that may be computed from a harmonic signal include a fractional chirp rate, a pitch, and amplitudes of the harmonics. A fractional chirp rate may be estimated, for example, by computing scores corresponding to different fractional chirp rates and selecting a highest score. A first pitch may be computed from a frequency representation that is computed using the estimated fractional chirp rate, for example, by using peak-to-peak distances in the frequency distribution. A second pitch may be computed using the first pitch, and a frequency representation of the signal, for example, by using correlations of portions of the frequency representation. Amplitudes of harmonics of the signal may be determined using the estimated fractional chirp rate and second pitch. Any of the estimated fractional chirp rate, second pitch, and harmonic amplitudes may be used for further processing, such as speech recognition, speaker verification, speaker identification, or signal reconstruction. |
| US09870781B2 |
Device and method for reducing quantization noise in a time-domain decoder
The present disclosure relates to a device and method for reducing quantization noise in a sound signal contained in a time-domain excitation decoded by a time-domain decoder. A future frame time-domain excitation is evaluated based on the decoded time-domain excitation. A concatenated time-domain excitation is produced from the decoded time-domain excitation of the time-domain excitation of the future frame and is converted into a frequency-domain excitation. A weighting mask is produced for retrieving spectral information lost in the quantization noise. The frequency-domain excitation is modified to increase spectral dynamics by application of the weighting mask. The modified frequency-domain excitation is converted into a modified time-domain excitation. The latter conversion is delay-less. In an embodiment, the weighting mask may be produced using time averaging or frequency averaging or a combination of time and frequency averaging of the frequency-domain excitation. The method and device can be used for improving music content rendering of linear-prediction (LP) based codecs. |
| US09870780B2 |
Estimation of background noise in audio signals
Background noise estimators and methods are disclosed for estimating background noise in an audio signal. Some methods include obtaining at least one parameter associated with an audio signal segment, such as a frame or part of a frame, based on a first linear prediction gain, calculated as a quotient between a residual signal from a 0th-order linear prediction and a residual signal from a 2nd-order linear prediction for the audio signal segment. A second linear prediction gain is calculated as a quotient between a residual signal from a 2nd-order linear prediction and a residual signal from a 16th-order linear prediction for the audio signal segment. Whether the audio signal segment comprises a pause is determined based at least on the obtained at least one parameter; and a background noise estimate is updated based on the audio signal segment when the audio signal segment comprises a pause. |
| US09870779B2 |
Speech synthesizer, audio watermarking information detection apparatus, speech synthesizing method, audio watermarking information detection method, and computer program product
According to an embodiment, a speech synthesizer includes a source generator, a phase modulator, and a vocal tract filter unit. The source generator generates a source signal by using a fundamental frequency sequence and a pulse signal. The phase modulator modulates, with respect to the source signal generated by the source generator, a phase of the pulse signal at each pitch mark based on audio watermarking information. The vocal tract filter unit generates a speech signal by using a spectrum parameter sequence with respect to the source signal in which the phase of the pulse signal is modulated by the phase modulator. |
| US09870777B2 |
Lossless embedded additional data
Methods are disclosed for an encoder to embed a data stream into a quantized PCM digital audio signal and for a corresponding decoder to both retrieve the data stream and losslessly reconstruct the exact original audio. Some methods employ complimentary amplification and attenuation, while others employ gain redistribution. Pre-emphasis and soft clipping techniques are described as methods of losslessly reducing the peak excursion of the PCM audio signal. Also described is the lossless placing of data at predetermined positions within an audio stream. |
| US09870774B2 |
Vehicular apparatus and speech switchover control program
A vehicular apparatus is provided. In the vehicular apparatus, a first controller is disposed on a first board and a second controller is disposed on a second board which is exchangeable with respect to the first board. An AD converter performs A/D conversion of first and second speech data. A switch disposed on the first board is switchable between a first connection state in which the switch outputs the first speech data inputted from the A/D converter and a second connection state in which the switch outputs a sound data different from each of the first and second speech data. A switch controller controls the switch so that the switch is in the second connection state when the second controller performs speech recognition of the second speech data. |
| US09870772B2 |
Guiding device, guiding method, program, and information storage medium
A guiding device, a guiding method, a program, and an information storage medium are provided which can perform output control of a guidance related to a volume at which to input voice using the recognition ranking of a received voice. A voice receiving section (46) receives a voice. When given information is identified as a result of recognition of the voice, an output control section (58) performs control so as to output a guidance related to a volume at which to input voice in a mode corresponding to the recognition ranking of the information. |
| US09870767B2 |
Method for improving acoustic model, computer for improving acoustic model and computer program thereof
Embodiments include methods and systems for improving an acoustic model. Aspects include acquiring a first standard deviation value by calculating standard deviation of a feature from first training data and acquiring a second standard deviation value by calculating standard deviation of a feature from second training data acquired in a different environment from an environment of the first training data. Aspects also include creating a feature adapted to an environment where the first training data is recorded, by multiplying the feature acquired from the second training data by a ratio obtained by dividing the first standard deviation value by the second standard deviation value. Aspects further include reconstructing an acoustic model constructed using training data acquired in the same environment as the environment of the first training data using the feature adapted to the environment where the first training data is recorded. |
| US09870765B2 |
Detecting customers with low speech recognition accuracy by investigating consistency of conversation in call-center
Methods and a system are provided for estimating automatic speech recognition (ASR) accuracy. A method includes obtaining transcriptions of utterances in a conversation over two channels. The method further includes sorting the transcriptions along a time axis using a forced alignment. The method also includes training a language model with the sorted transcriptions. The method additionally includes performing ASR for utterances in a conversation between a first user and a second user. The second user is a target of ASR accuracy estimation. The method further includes determining whether an ASR result of the second user is consistent or inconsistent with an ASR result of the first user using the trained language model. The method also includes estimating the ASR result of the second user as poor responsive to the ASR result of the second user being as inconsistent with the ASR result of the first user. |
| US09870757B2 |
Low power digital driving of active matrix displays
Digital driving circuitry for driving an active matrix display comprising a plurality of pixels logically organized in a plurality of rows and a plurality of columns, each pixel comprising a light emitting element, comprises a current driver for each of the plurality of columns for driving a predetermined current through the corresponding column, the predetermined current being proportional to the number of pixels that are ON in that column. The digital driving circuitry further comprises digital select line driving circuitry for sequentially selecting the plurality of rows, and digital data line driving circuitry for writing digital image codes to the pixels in a selected row, synchronized with the digital select line driving circuitry. |
| US09870753B2 |
Light sensor having partially opaque optic
A rearview assembly for a vehicle is provided that includes: a housing configured for mounting to the vehicle; a rearview element disposed in the housing that displays images of a scene exterior of the vehicle; a light sensor assembly disposed in the housing; and a controller for receiving the electrical signal of the light sensor and for adjusting a brightness of the images displayed by the rearview element. The light sensor includes a light sensor for outputting an electrical signal representing intensity of light impinging upon a light-receiving surface of the light sensor, and a secondary optical element configured to receive light, wherein the light passes through the secondary optical element to the light sensor, the secondary optical element including a tint material that is substantially color neutral for attenuating light passing therethrough. |
| US09870737B2 |
Sensing circuit and organic light emitting diode display device having the same
A sensing circuit capable of simplifying a configuration of a data driver by reducing a size of a sensing circuit provided at each data driver, and an organic light emitting diode (OLED) display device having the same are provided. The sensing circuit includes N sampling and holding circuits, a scaler and an analog-digital converter. |
| US09870735B2 |
Display device including double-gate transistors with reduced deterioration
A display device includes: a plurality of pixels, wherein each of the plurality of pixels includes at least two double-gate transistors including a first gate electrode and a second gate electrode; conduction between source electrodes and drain electrodes of the at least two double-gate transistors is controlled by a voltage applied to the first gate electrode, and electrical connection between the second gate electrode and the first gate electrode of each of the at least two double-gate transistors is determined depending on a polarity of a voltage applied on average to each of the at least two double-gate transistors. |
| US09870730B2 |
Gate circuit, driving method for gate circuit and display device using the same
A gate circuit according to an exemplary embodiment of the present inventive concept comprises a plurality of stages, each receiving a clock signal and outputting a gate signal and a carry signal. One of the plurality of stages includes a first transistor of which a first terminal and a control terminal are connected to each other and a carry signal of a stage before previous stage is input to the first terminal and the control terminal and a second transistor of which a gate signal of the previous stage is input to a first terminal, a control terminal is connected with a second terminal of the first transistor, and an output terminal is connected to a first node. |
| US09870729B2 |
Control device and display device
A control device calculates output signal values to the respective pixels for each row based on pixel signal values. The control device includes a line integrating unit that calculates a line integrated value by totaling the pixel signal values for the respective pixels within a line pixel group, a frame integrating unit that calculates a frame integrated value by totaling the output signal values for the respective pixels of a former arranged pixel group for which the output signal values have already been calculated in the same display frame, a power consumption adjustment term determining unit that calculates a power consumption adjustment term based on a frame threshold that is a predetermined threshold for power consumption, a line integrated value, and a frame integrated value, and an output signal generating unit that calculates output signal values based on a pixel signal value and the power consumption adjustment term. |
| US09870727B2 |
Display device and driving method thereof
A display device includes: a display unit including pixels including a first color subpixel at a left upper end, a second color subpixel at a left lower end, and a third color subpixel at a right side; a data converter to convert first color, second color, and third color unit input data into first color, second color, and third color unit adapted data; and a driver to apply an image signal to the pixel based on the adapted data, the data converter generating unit adapted data using first unit input data of a target subpixel and second unit input data of another subpixel adjacent the target subpixel along a direction, the direction being: an up direction when the target subpixel is the first color subpixel; a down direction when the target subpixel is the second color subpixel; and a right direction when the target subpixel is the third color subpixel. |
| US09870726B2 |
Image display apparatus, image display method, storage medium, and monitoring system
A head-mounted display, a smart phone, a tablet terminal, an electronic book, or the like monitors conditions of the side of a power generation apparatus that charges a battery.An image display apparatus includes a power generation information acquisition means for obtaining power generation information on a power storage amount, a power generation amount, and the like of a secondary battery in each power generation apparatus, appropriately processes the obtained information, and displays it to a user via a display unit. The user can check the power generation amount of the power generation apparatus and the power storage amount of the secondary battery without stopping the use of the image display apparatus. When a power storage amount of a battery in use is lowered, the user can properly judge with which of the power generation apparatuses the user should replace the battery. |
| US09870724B1 |
Clean/biohazard transportation identification tag
A tag for positioning on containers for carrying item(s). The tag includes a base layer having a second status identifier that comprises a status identification symbol. The tag also includes a front layer having a top portion and a bottom portion and a removable tab connecting the top portion and the bottom portion. The bottom portion and the top portion are secured to the base layer. When the front layer is secured to the base layer, the front layer covers the second status identifier. The removable tab includes a first status identifier that is visible when the tab is retained to the front layer and, when the tab is removed, the second status identifier is visible. |
| US09870722B2 |
Dummy object with extremeties which utilise the mass inertia thereof to replicate a natural movement process
A dummy object is described which is particularly suitable for a functional testing of driver assistance systems for vehicles. The dummy object comprises a torso, at least one extremity representing an arm or a leg, wherein the extremity includes a proximal extremity portion mounted in an articulated manner at the torso and a distal extremity portion mounted in an articulated manner at the proximal extremity portion, and at least one drive which is arranged in the torso and is designed to move the proximal extremity portion relative to the torso. The proximal extremity portion can be moved in such a manner that a movement of the distal extremity portion, which is correlated with the movement of the proximal extremity portion, can be created by utilizing the mass inertia of the associated distal extremity portion. |
| US09870717B2 |
Assisting a visually impaired user to grip an object
The present disclosure relates to system(s) and device for assisting a visually impaired user to grip objects. The system may receive an image of an object in real-time and identify a reference image corresponding to the image by comparing the image with reference images. Further, the system may identify a reference tactile image corresponding to the reference image and generate a first set of audio instructions for assisting the visually impaired user to grip the object based on the reference tactile image. Further, the system may receive a tactile image from a tactile glove of the visually impaired user and compare the tactile image with the reference tactile image to identify pressure variation data. Furthermore, the system may generate a second set of audio instructions for guiding the visually impaired user to grip the object base on a second set of audio instructions generated using the pressure variation data. |
| US09870715B2 |
Context-aware cybersecurity training systems, apparatuses, and methods
A system assesses the susceptibility of an electronic device user to a cybersecurity threat by sensing a user action with respect to the electronic device. The system maps the sensed data to a training needs model to determine whether the sensed data corresponds to a pattern associated with a threat scenario in the training needs model. When the system determines that the sensed data corresponds to a pattern associated with a threat scenario in the training needs model, identify a cybersecurity threat scenario for which the user is at risk, and use the training needs model to estimate susceptibility of the user to the cybersecurity threat scenario. |
| US09870714B2 |
Tablet learning apparatus
A learning apparatus can electronically provide content to a user via a display on the learning apparatus. The content can include stationary image elements and removable image elements at a plurality of locations on the display. When a user shakes the learning apparatus, the removable image elements may move away from the plurality of locations. The user can then select one or more image elements, and place them at locations on the display. |
| US09870713B1 |
Detection of unauthorized information exchange between users
Detection and prevention of unauthorized exchange of information between users of user devices is disclosed. Monitoring data associated with respective information received by the user devices from respective users may be received. Position information indicating proximity or relative positions of the devices may also be received. The monitoring data and/or the position information may be analyzed to determining whether unauthorized information exchange between users may be occurring. One or more metrics indicating a likelihood that unauthorized information exchange is occurring may be generated based on the analysis of the monitoring data and/or the position information. A generated metric may be compared to an associated threshold and preventive measures for deterring unauthorized information exchange may be identified based on a result of the comparison. |
| US09870712B1 |
Time and spatial based flight selection system and method
A system and method may provide a real time alternative flight selection based on threat mitigation along a currently planned path at a specific time. The system and method may receive threat information associated with a specific path and compare the threat information to each leg of the path to determine if a threat may exist during that specific leg. Should a threat exist, the method may propose an alternate estimated time of departure (ETD) to mitigate the future threat. Should the alternate ETD be insufficient to mitigate the threat, the method may further propose an alternate lateral and vertical path at the original or modified ETD to successfully mitigate the threat. |
| US09870711B2 |
System and method for determining an alternative flight route based on sector geometry
A flight routing system for determining an alternative route for an aircraft based on an airspace partitioned into a plurality of sectors, and an original flight route having an initial point of takeoff and a destination point is disclosed. The flight routing system includes a processor and a memory storing instructions executable by the processor to perform operations including determining a plurality of points within each of the plurality of sectors. The plurality of points are each located along an edge of one of the plurality of sectors. The processor also performs operations including determining at least one connecting arc for each sector, where the connecting arc connects a first point with another point within each sector. The processor further performs operations for determining a complete time-based airspace network based on at least a forecast capacity. |
| US09870703B2 |
Pedestrian warning system providing adjustable acoustic indications
Systems and methods are disclosed for a pedestrian warning system. An example disclosed method to simulate noise for an electric or noise-dampened vehicle to warning pedestrians includes producing a first sound at a first frequency range from a first sound generator located at a front of the vehicle. The method also includes producing a second sound at a second frequency range from a second sound generator located under the vehicle. Additionally, the example method includes adjusting the acoustic characteristics of the first and second sounds based on vehicle motion data. |
| US09870702B2 |
Method for forwarding remote control signal and signal forwarding node using the same
A method for forwarding a remote control signal and a signal forwarding node using the same are disclosed. Herein, the signal forwarding node includes a laser light receiver configured to detect laser light, an Infra Red (IR) light receiver configured to receive a remote control signal, a wireless communication module configured to transmit and receive data to and from an external signal forwarding node, and a controller configured to control the wireless communication module, when laser light is detected through the laser light receiver, and when the remote control signal is received, so as to forward control information included in the received remote control signal to the external signal forwarding node. |
| US09870701B2 |
Apparatus and method for controlling opening and closing of vehicle door
An apparatus and method for controlling opening and closing of a vehicle door are provided. The apparatus includes a driving unit that opens and closes a door a controller that operates the driving unit. Additionally, an acoustic wave processing unit receives and analyzes an acoustic wave signal generated by force exerted onto the door to generate a control signal for opening or closing of the door. The controller receives the control signal to thus operate the driving unit. Further, the acoustic wave processing unit includes an acoustic wave sensor disposed inside of the door and receives the acoustic wave signal, and an MCU that analyzes a signal output from the acoustic wave sensor to generate the control signal. |
| US09870700B2 |
Method and device for avoiding false alarms in monitoring systems
A method is provided for avoiding false alarms on a self-service terminal, in particular an ATM. The ATM has at least one camera and at least one alarm unit that generates alarms when the ATM is attacked, and a network connection to a network to pass on the alarms to a customer. The method includes generating an alarm by the alarm unit and storing alarm images from the camera from which the alarm was derived; before passing on the alarm to an operator via a digital network, comparing the digital alarm images with templates stored on the ATM and that characterize a false alarm, and if a correlation with the templates is established, the alarm is ignored; otherwise the alarm is passed on to the consumer by the network. |
| US09870696B2 |
Smart device vehicle integration
A vehicle computing system includes at least one processor configured to communicate with a remote smoke detector device includes a smart device interface configured to provide access to the remote smoke detector device, a scripting application configured to utilize the smart device interface to execute scripting settings to manage the remote smoke detector, and a user interface of the scripting application configured to output one or more messages from the remote smoke detector. |
| US09870693B2 |
Method for preventing portable electronic device from being left in vehicle, the portable electronic device, and the vehicle
A method for preventing a portable electronic device from being left in a vehicle, and the electronic device and the vehicle using the same is provided. The method of the electronic device includes receiving, from the vehicle, a first signal including information regarding identification of an off state of an engine of the vehicle, receiving, from the vehicle, a second signal including information regarding identification of a change to an empty state of at least one seat of the vehicle, determining movement of the electronic device, and executing an alarm function, based on at least one of the first signal, the second signal, and the determined movement of the electronic device. |
| US09870692B2 |
Server computing device lighting for maintenance
A light source unit may be disposed at a first posterior side location of a server computing device. The light source unit may be configured to at least provide lighting to a posterior side of the server computing device via one or more light emitting diodes. The light emitting diodes may be coupled to at least a second posterior side location of the server computing device. The light source unit may include a first universal serial bus (USB) interface configured to receive a first end of a USB cable. The USB cable may be configured to connect to a power source at a second end. The power source may be for use in providing power to the light emitting diodes. |
| US09870687B1 |
System for interacting with a container and the related content placed near a conducting surface
Disclosed is a system for interacting with one or more containers placed near a conducting surface. The system sends the information of content inside the container in relation to an action caused by a user over the communication network. The system includes a controller; a frequency generator; a first electrode; an electronic circuitry including a convertor, an e-filed strength meter, an I/O interface and a bi-directional communication unit; a second electrode and a media unit. The controller generates a unique identification code for each container. The controller communicates through the communication network. The frequency generator provides a modulated alternating electric with variable frequency. The first electrode floats in the air inside the container and mirrors charges received from the frequency generator through the conducting surface and the content. The convertor converts alternating charges into DC energy received from the first electrode. The e-filed strength meter measures changes in the alternating charges on the container. The I/O interface generates input and output signals on receiving the change in the alternating charges from e-field strength meter and the bi-directional communication unit to communicate the changes in the electric field strength from the e-field strength meter to the controller. The second electrode is coupled to the converter and is attached to the cap of the container and further floats against the ground. The media unit stores and communicates media data related to the container over the communication network on receiving the field strength signal along with the unique ID number from the controller. |
| US09870682B2 |
Contact type tactile feedback apparatus and operating method of contact type tactile feedback apparatus
A contact type tactile feedback apparatus and operational method of the contact type tactile feedback apparatus is provided. The contact type tactile feedback apparatus may enable an object to be in close contact with a power feedback portion to transfer a power sensed by a sensor, using a fixing portion, thereby enabling the object to recognize the power, intuitively. |
| US09870681B2 |
Field installable light curtain status module
Apparatus and associated methods relate to a modular plug-in accessory including a connector for making pluggable electrical connection to a cascading electrical output port for providing cascading connection from an elongate light curtain, the accessory comprising an omni-directional light indicator to illuminate a light signal indicative of a status of the light curtain, wherein the accessory is configured to releasably make or break operative connection to the end cap containing the output port while the end cap is sealably connected to an end of the light curtain. In an illustrative example, the accessory may plug in directly to the terminal end of a light curtain. The receiving light curtain may be connected at the distal end of a string of light curtains. In some examples, the accessory may provide high visibility status indication information about any of the light curtain segments in the string of light curtains. |
| US09870678B2 |
Dynamic alarm system for reducing alarm fatigue
A dynamic alarm system that can assess the background noise in a clinical environment with sub-minute time sampling and change the alarm output to a desired signal-to-noise ratio (SNR) below ambient noise (negative SNR) to minimize clinician fatigue and ameliorate deleterious patient outcomes, while preserving clinician performance. |
| US09870677B1 |
Lightning video poker
A video poker game wherein an additional virtual bonus card, called a lightning bonus card, is added to a virtual deck of cards and is randomly dealt into the opening hand of a video poker game. Upon receiving a randomly dealt lightning bonus card in the opening deal of a video poker game, the player is awarded the opportunity to play as many virtual hands n of video poker during a specific amount of time t without wagering additional credits for each subsequent hand following the receiving of the lightning bonus card. |
| US09870675B2 |
Enriched game play environment
Systems and methods for a gaming system. A gaming system includes a game world engine connected to a real world engine and an entertainment software engine. The real world engine receives a trigger of execution of a gambling game, and determines a gambling outcome of the gambling game using a wager of real world credits. The entertainment software provides a skill based entertainment game to a player, and conveys, to the game world engine, a player action taken by the player during play of the of the entertainment game, the player action including use by the player of an enabling element. The game world engine receives the player action, correlates the wager of real world credit of the gambling game with the use of the enabling element by triggering execution of the gambling game, and accumulates game world credit for the player based on the player action. |
| US09870672B2 |
Wagering game and method having additional reel matrices sharing a common reel
Disclosed are a game, gaming device, system and method for play of a reel-based feature game including a base matrix of reel indicia, one or more additional matrices of reel indicia and an expanding reel which replaces a portion of the base matrix and each of the additional reel matrices to simultaneously produce outcomes in each of the matrices. |
| US09870671B1 |
Mechanical lift for delivery bins in vending machines
A mechanical lift for delivery bins and receptacles in vending and analogous machines includes a feature that partial opening of a delivery door allows at least partial access to the delivery bin or receptacle but that further opening of the door would lift the bin or receptacle floor. The assembly can be compact, relatively noncomplex and economical. It can come in basically a preassembled kit that can be retrofitted or original manufacture equipment. It can include additional features such as anti-cheat functions and dispense detect sensors. An additional feature can be a unique dispensing floor geometry. |
| US09870669B2 |
Security device for security document
A security device for verifying an authenticity of a security doc-ument comprises an at least partially transparent multilayer substrate with a first surface and a second surface. A first pattern is arranged on the first surface. This first pattern is derivable using a first seed pattern. A second pattern is arranged on the second surface. This second pattern is derivable using a second seed pattern. The security device furthermore comprises a third pattern arranged between a first and a second substrate layer. The third pattern is derivable using an inversion of the first pattern, an inversion of the second pattern, and a non-inverted third seed pattern. Transmit lances and reflectivities of the patterns are selected such that in a reflection viewing mode, only the first or second seed pattern is visible, respectively. In a transmission viewing mode, only the third seed pattern is visible. |
| US09870668B1 |
Systems, methods and devices for processing coins with linear array of coin imaging sensors
Currency processing systems, coin processing machines, and methods of imaging coins are presented herein. A currency processing system is disclosed which includes a housing with a coin input area for receiving coins and coin receptacles for stowing processed coins. A disk-type coin processing unit is coupled to the coin input area and coin receptacles. The disk-type coin processing unit includes a rotatable disk for imparting motion to the coins, and a sorting head having a lower surface adjacent the rotatable disk. The lower surface forms various shaped regions for guiding the coins, under the motion imparted by the rotatable disk, to exit channels through which the coins are discharged to the coin receptacles. A linear array of sensors is mounted to the sorting head and/or the rotatable disk. The sensors examine each coin on the rotatable disk and output a signal indicative of coin image information for processing the coin. |
| US09870665B2 |
Apparatus, system and method for vehicle access and function control utilizing a portable device
A system for providing dynamic access to a vehicle via a plurality of devices. A device and/or a server of an authentication network stored fob data relating to one or more key fobs linked to the vehicle, and device data that includes data relating to one or more devices that are authorized to access the vehicle. The vehicle receives an access request indicating that a new device is requesting access to the vehicle, whereupon a challenge may be transmitted to one or more of the authorized devices. The one or more devices may respond, granting access to vehicle functions. The vehicle and/or authentication network generate a secure fob key and access limitations based on the response and transmit the secure fob key to the new device. The new device may be authenticated to access vehicle functions subject to the limitation based at least in part on the fob key. |
| US09870664B2 |
Remote barrier operator command and status device and operation
The present disclosure provides a barrier operator system in which a remotely located transceiver type controller is in wireless communication with a transceiver type adapter connected to a barrier operator, and in electronic communication with the barrier operator's microcontroller. The controller is operable to wirelessly transmit door operator status inquiries to the adapter. This may be effected automatically in connection with the transmission and receipt by the adapter of door toggle commands or separate and apart from same. The status information is wirelessly transmitted by the adapter in broadcast form without source or destination address to the remote device in a signal that is non-addressed broadcast door operator (and, indirectly, door) status information by relying upon the receipt of the message by the remote within the specific time limit of the reception window of the remote. |
| US09870663B2 |
Authentication of a user provided with a mobile device by a vehicle
The invention relates to a method of pre-authenticating a user at a vehicle with a view to allowing the user to access the vehicle when a handle provided on a door of said vehicle is actuated, said user being provided with a mobile device, said vehicle and said mobile device each comprising a wireless communication interface operating according to the BLE protocol; each of said interfaces initially being in the “notification” state in which each of said interfaces transmits for a basic transmission time; said method comprising: —steps of connecting said interfaces according to the BLE protocol—steps of identifying and authenticating the mobile device, by the vehicle; a step in which the vehicle stores the identity data or the mobile device if the identification and authentication steps have been completed; —a subsequent step in which, when the handle of the vehicle door is actuated, the interface of the vehicle shifts from the “notification” state to the “scanning” state; —a tenth step in which the interface in the “scanning” state confirms the presence of the interface of the mobile device in the “notification” state. |
| US09870661B2 |
Access control system
An access control system provides authentication and notification. A visitor to a facility, for example, authenticates to the access control system. Once an identity of the visitor is confirmed, the access control system sends a notification to a host, such as an employee. The notification informs the host of the arrival of the visitor. |
| US09870659B2 |
Cryptographic key management via a computer server
Some embodiments include a computer server. The computer server can be configured to: add a security system associated with a user account; provision one or more communication devices associated with the security system; configure a cryptographic key to associate at least a communication device amongst the communication devices with the security system; configure an access control file that is cryptographically signed by the computer server and encrypted with the cryptographic key associated with the security system, wherein the access control file contains permissions of the communication devices to the security system; and provide a data payload including the access control file to a first communication device of the communication devices. |
| US09870658B1 |
Security badge
An identification device includes a radio-frequency identification (RFID) card, a base member, and a front panel. The RFID card is configured to transmit an identification number. The front panel includes a laser-markable layer. The base member and the front panel are joined to form an assembly in which the RFID card is enclosed. |
| US09870657B2 |
Apparatus and method for controlling damping of vehicle
The present invention relates to the control of a suspension system of vehicles, and more particularly, to a driver-customized damping control apparatus on the basis of the user's disposition information, and a method thereof. In particular, the present invention provides a damping control apparatus comprising: a mode determining unit that determines a damping mode of the vehicle according to a damping mode configuration signal; a receiving unit that receives a vehicle manipulation signal that is generated according to the vehicle manipulation of a driver; a driver-disposition analyzing unit that analyzes the vehicle manipulation signal and calculates a correction index for the correction of the damping force; and a damping force range determining unit that determines a final damping force range by correcting a damping force range predetermined for each damping mode on the basis of the correction index, and a method thereof. |
| US09870655B2 |
Apparatus and method for processing a plurality of logging policies
An apparatus for processing a plurality of logging policies includes: a logging policy input unit configured to receive the plurality of logging policies for vehicle data; a logging policy storage configured to store the logging policies received by the logging policy input unit; a logging policy analyzer configured to parse the logging policies stored in the logging policy storage and extract variables from the parsed logging policies; a rule maker configured to make a logging policy applying rule based on the variables extracted by the logging policy analyzer; and a logging policy processor configured to read and process the corresponding logging policy which is stored in the logging policy storage depending on the logging policy applying rule made by the rule maker. |
| US09870642B2 |
Method and apparatus for layout for augmented reality view
An approach is provided for providing an interactive perspective-based point of interest layout in an augmented reality view. The layout platform determines at least one zoom level for rendering of one or more representations of one or more items in a perspective-based display based, at least in part, on at least one push interaction or at least one pull interaction in the perspective-based display. The layout platform causes, at least in part, a rendering of the one or more representations based, at least in part, on the at least one zoom level. |
| US09870636B2 |
Method for sharing emotions through the creation of three dimensional avatars and their interaction
A two-dimensional image is transformed into at least one portion of a human or animal body into a three-dimensional model. An image is acquired that includes the at least one portion of the human or animal body. An identification is made of the at least one portion within the image. Searches are made for features indicative of the at least one portion of the human or animal body within the at least one portion. One or more identifications are made of a set of landmarks corresponding to the features. An alignment is a deformable mask including the set of landmarks. The deformable mask includes a number of meshes corresponding to the at least one portion of the human or animal body. The 3D model is animated by dividing it into concentric rings, quasi rings and applying different degrees of rotation to each ring. |
| US09870630B2 |
Methods and systems to generate graphical representations of relationships between persons based on transactions
In one example embodiment, a system and method is shown as including identifying a context set data defining a context within which a person resides. Next, an operation is executed so as to retrieve the context set data that includes person data and relationship between persons data, the relationship between persons data including certain characteristics that define the person in the context set. An operation may be executed so as to perform a set operation on the person in the context set so as to generate a graph set. Further, an operation may be executed to render a graphical representation of the context set. |
| US09870625B2 |
Method for estimating a quantity of a blood component in a fluid receiver and corresponding error
A method and system for communicating estimated blood loss parameters of a patient to a user, the method comprising: receiving data representative of an image, of a fluid receiver; automatically detecting a region within the image associated with a volume of fluid received at the fluid receiver, the volume of fluid including a blood component; calculating an estimated amount of the blood component present in the volume of fluid based upon a color parameter represented in the region, and determining a bias error associated with the estimated amount of the blood component; updating an analysis of an aggregate amount of the blood component and an aggregate bias error associated with blood loss of the patient, based upon the estimated amount of the blood component and the bias error; and providing information from the analysis of the aggregate amount of the blood component and the aggregate bias error, to the user. |
| US09870624B1 |
Three-dimensional mapping of an environment
A system for registering a three dimensional map of an environment includes a data collection device, such as a robotic device, one or more sensors installable on the device, such as a camera, a LiDAR sensor, an inertial measurement unit (IMU), and a global positioning system receiver. The system may be configured to use the sensor data to perform visual odometry, and/or LiDAR odometry. The system may use IMU measurements to determine an initial estimate, and use a modified generalized iterative closest point algorithm by examining only a portion of scan lines for each frame or combining multiple feature points across multiple frames. While performing the visual and LiDAR odometries, the system may simultaneously perform map registration through a global registration framework and optimize the registration over multiple frames. |
| US09870616B2 |
Information processing device, information processing method, and system
An information processing device includes an obtainer and a controller. The obtainer obtains a captured image obtained through imaging by an imaging device. The controller generates instruction information for instructing how a subject having plural feature points is to be held up. |
| US09870613B2 |
Detection of tooth condition using reflectance images with red and green fluorescence
A system and method for imaging a tooth. The method illuminates the tooth and acquires reflectance image data and illuminates the tooth and acquires fluorescence image data from the tooth. The acquired reflectance and fluorescence image data for the tooth are aligned to form aligned reflectance and fluorescence image data. For one or more pixels of the aligned reflectance and fluorescence image data, at least one feature vector is generated, having data derived from one or both of the aligned reflectance and fluorescence image data. The aligned reflectance and fluorescence image data and the at least one feature vector are processed using one or more trained classifiers obtained from a memory that is in signal communication with the computer. Processing results indicative of tooth condition are displayed. |
| US09870612B2 |
Method for repairing a mask
A method includes inspecting a mask to locate a defect region for a defect of the mask. A phase distribution of an aerial image of the defect region is acquired. A point spread function of an imaging system is determined. One or more repair regions of the mask are identified based on the phase distribution of the aerial image of the defect region and the point spread function. A repair process is performed to the one or more repair regions of the mask to form one or more repair features. |
| US09870610B2 |
Radiation imaging system and image processing device
A radiation imaging system includes a radiation imaging device, a reconstruction unit and a detection unit. The reconstruction unit generates at least two of a differential phase image, an absorption image and a small-angle scattering image based on periodic pattern images of a subject obtained by the imaging device. The detection unit performs regression analysis on at least two images of (a) the differential phase image, a differential absorption image of the absorption image and a differential small-angle scattering image of the small-angle scattering image or (b) a phase image of the differential phase image, the absorption image and the small-angle scattering image; calculates a value of an indicator indicating a relationship between the at least two images; and detects image quality deterioration due to change in relative position of the imaging device and the subject based on the value. |
| US09870608B2 |
Gamma camera, spect device, pet device, and method for generating measured gamma ray images
A unit (33) for generating count images for separate energy windows generates main measured count images and auxiliary measured count images on the basis of gamma ray (6) count information measured by a detector head (10). A main measurement window direct ray count rate estimation unit (42) estimates a count rate for direct gamma rays in a main measurement energy window, doing so by subtracting a scattered gamma ray count rate for an auxiliary measurement energy window, which has been estimated from an auxiliary measured count image and detector response data by an auxiliary measurement window scattered ray count rate estimation unit (41), from the main measured count image. |
| US09870607B1 |
System and method for digital image intensity correction
The present invention provides a method and apparatus to enhance the image contrast of a digital image device while simultaneously compensating for image intensity inhomogeneity, regardless of the source. The present invention corrects intensity inhomogeneities producing a more uniform image appearance. Also, the image is enhanced through increased contrast, e.g., tissue contrast in a medical image. The method makes no assumptions as to the source of the inhomogeneities, e.g., physical device characteristics or positioning of the object being imaged. In the method, the error between the histogram of the spatially-weighted original image and a specified histogram is minimized. The specified histogram may be selected to increase contrast generally or particularly for accentuation, e.g., on localized regions of interest. The weighting is preferably achieved by two-dimensional interpolation of a sparse grid of control points overlaying the image. A sparse grid is used rather than a dense one to compensate for slowly-varying image non-uniformity. Also, sparseness reduces the computational complexity, as the final weight set involves the solution of simultaneous linear equations whose number is the size of the chosen grid. |
| US09870606B2 |
Method and apparatus for compensating illumination variations in a sequence of images
In order to take into account the local illumination variations in a scene, the invention proposes a method of compensating illumination variations in which distributions are determined for each block of an image (or view) and, in order to avoid a loss of the video coding efficiency, a distribution-based mapping function is automatically computed by a remote apparatus, such a decoder, from only information available at that apparatus when decoding a current block of the sequence of images. The present invention relates also to a method and device of encoding and/or decoding a sequence of images which comprises means configured to implement the method of compensating illumination variations according to the invention. |
| US09870600B2 |
Raw sensor image and video de-hazing and atmospheric light analysis methods and systems
A method for processing image or video data receives color filtered mosaiced raw image or video data. The method, performed in an image processing pipeline, de-hazes the color filtered mosaiced raw image or video data, e.g. Bayer image data, to create de-hazed mosaiced image or video data and de-mosaicing the de-hazed mosaiced image or video data to crate de-hazed and de-mosaiced image or video data. |
| US09870598B2 |
Low complexity adaptive filtering for mobile captures
A method of noise filter parameter adaptation, the method comprising receiving a current video frame comprising a plurality of pixels. A table lookup is performed, using current statistical values associated with the current video frame. Noise filter parameters are adapted, based on current lighting conditions as determined from the performed table lookup. The current lighting conditions correspond to the current statistical values. The current video frame is noise filtered as defined by the adapted noise filter parameters. |
| US09870597B2 |
Systems and methods allowing multi-family property owners to consolidate retail electric provider charges with landlord provided utilities and services
Systems and methods for allowing landlords to combine information from a retail electric provider into landlord billed utilities and items, are described herein. In one aspect, residency information for a unit associated with a resident is received. Resource consumption or usage information associated with the unit is received from one retail electric provider. A consolidated data set is generated based on the resource consumption or usage information for the unit from both the retail electric provider and landlord provided services such as rent, water, trash and sewer. Under this process, a resident may choose to have the electric account remain in the landlord's name and then be billed for such retail electric charges on the same bill as the landlord provided utilities and services. In some implementations, the community will collect funds for the utility bills from each resident and will use such funds to pay the utility provider directly. |
| US09870596B2 |
Predicting community development trends
Community development is supported by a community rating. Community ratings for various communities are compared to identify a preferred community. Historical community ratings are determined for the preferred community. Community rating trends are identified for the community and these trends are used for predicting future community rating(s) to support development decisions. |
| US09870592B2 |
Process energy intensity monitoring and diagnostic system
A Process Energy Intensity Monitoring and Diagnostic System designed to evaluate the amount of energy input into a process and the resulting product output, and comparing the resulting energy intensity (energy per unit produced) calculation with a statistical average, or preferred value. Further, the system will isolate energy intensity data points that occur outside statistically derived upper or lower control limits. The system will collect information from specific equipment within a manufacturing or production process. This information will be transmitted to the central database that will store, calculate, and deliver real time and historical consumption, production, and energy intensity data to connected client devices. Client devices may include computers, smartphones, or web browsers. |
| US09870587B2 |
System and method for constructing and displaying active virtual reality cyber malls, show rooms, galleries, stores, museums, and objects within
A virtual reality scene corresponding to a physical scene is displayed. The virtual reality scene includes a plurality of objects. The plurality of objects is selectable by a user and is built from a plurality of images representing varied views of the plurality of objects in the physical scene. The user is enabled to navigate within the virtual reality scene to observe the virtual reality scene from at least two perspectives. The user is enabled to rotate at least one of the plurality of objects within the virtual reality scene about at least one axis. A selection received from the user corresponds to at least one of the plurality of objects within the virtual reality scene. In response to the selection, additional information about a selected at least one of the plurality of objects is displayed. The additional information includes at least one of a link to buy and a link to bid on the selected at least one of the plurality of objects. |
| US09870584B2 |
Method and system for web-based inventory control and automatic order calculator
A method and system for providing order placement and inventory control, integrating customers and suppliers and using both real-time and historical data to provide an automated process for the management of inventory. Various embodiments of this invention can include such features as automatic order placement, usage factor analysis, waste factor analysis, inventory analysis and reconciling of inventory data. |
| US09870580B2 |
Network-as-a-service architecture
A system may receive order information that may include information identifying a network service, associated with a service provider network, and a service location associated with the network service. The system may determine context information based on the order information that may include information associated with providing the network service to the service location via the service provider network. The system may generate a service order based on the context information. The system may create a virtual network function (VNF) based on the service request. The VNF may be created such that the VNF operates on a computing device associated with the system, and may be configured to provide the network service. The system may insert the VNF into the service provider network to cause the network service to be provided to the service location. The VNF may interact with a physical device of the service provider network. |
| US09870564B2 |
Systems and methods for risk based decisioning
A method and system for creating an assurance level based on authentication data attributes using a computer device coupled to a database are provided. The method includes receiving an authorization request associated with the financial transaction from the sender, the authorization request including a fraud risk assessment of the financial transaction determined by the sender using an authentication response received from the computer device by the sender, the authorization request including one or more reason codes associated with the sender fraud risk assessment. The method further includes transmitting the received authorization request to an issuer associated with the cardholder. |
| US09870562B2 |
Method and system for integration of market exchange and issuer processing for blockchain-based transactions
A method for authorization of a blockchain transaction includes: storing account profiles, each profile including an account identifier, fiat amount, and blockchain amount; receiving a transaction message, the transaction message being formatted based on transaction message standards and including a first data element that includes a specific account identifier and a second data element reserved for private use that includes a network identifier and transaction amount; identifying a specific account profile that includes the specific account identifier; identifying a risk value based on the transaction amount and at least one of: the fiat amount and blockchain amount; determining authorization of a transaction based on the identified risk value; modifying the transaction message based on the authorization determination; and transmitting the modified transaction message. |
| US09870561B2 |
Multi-use numbering system and method
A numbering system is provided having an identifier with hexadecimal, vigesimal, quadrivigesimal, or any other suitable alphanumeric characters includable on a card and an account identifiable using the identifier. The card can be a gift card, a customer loyalty card, or a customer incentive card. An interface may be connected to a communications network that is accessible to associate the identifier with an account and manage funds associable with the account. Funds data may be associable with the account and storable on the remote server, the funds data relating to the funds transferred by a user to a card issuer. The identifier may be storable on the card in an electronically readable format, and may be included on the card via printing and/or imprinting. A method is provided for using the numbering system. |
| US09870560B2 |
Online payment method and a network element, a system and a computer program product therefor
The invention concerns a payment arrangement in an online shopping. In the method a request for a transaction code containing at least predefined user-related identification information is received. The content of the request is compared to stored information and, in response to a positive outcome of the comparison, a transaction code is generated, stored and delivered to the requesting party. In the next phase an inserted transaction code is received for verification and it is compared to the generated transaction code stored. In response to a positive outcome of the comparison the payment information is confirmed to the requesting entity. The invention also relates to a network element, a system and a computer program product implementing the method. |
| US09870559B2 |
Establishing direct, secure transaction channels between a device and a plurality of service providers via personalized tokens
Methods and systems are provided for supporting electronic transactions, including transactions that are provided with per-user, per-device and per-domain security across domains of multiple service providers. |
| US09870557B2 |
Payment object reader device with multiple types of reader circuitry
Methods, systems, and apparatus, for a payment card reader comprising: a frame, where the frame includes a top surface, a bottom surface, a first side surface, and a second side surface, a second side surface of the side surfaces on an opposite side of the frame from the first side surface, the first side surface including a groove configured to receive a swipe of a magnetic stripe card, the second side surface including a slot configured to receive insertion of a chip card; a magnetic stripe reader interface; a chip card reader interface; circuitry configured to direct signals from the magnetic stripe reader interface and the chip card reader interface to a microcontroller in the card reader; and circuitry configured to communicate wirelessly between the card reader and a computing device. |
| US09870554B1 |
Managing documents based on a user's calendar
Disclosed is a system of managing documents based on the calendar of a user. When the user has a scheduled first event, one or more documents associated with a second occurrence of an event related to the first event can be identified and associated with the first event. In this way, a user may easily access documents related to the first event. The documents can be, for example, documents accessed during the second event or documents identified by the user with the second event. The events can be part of a recurring series of events. The events and their associated documents can be displayed in a folder format. |
| US09870550B2 |
Modifying existing recipes to incorporate additional or replace existing ingredients
Mechanisms are provided for implementing a recipe modification system. The recipe modification system receives a request to modify an existing recipe from a requestor. The request identifies the existing recipe and an ingredient to be added to the existing recipe. The recipe modification system identifies a cluster of recipe elements associated with the ingredient to be added to the existing recipe and selects a representative member recipe element of the cluster. The recipe modification system modifies the existing recipe based on the selected representative member recipe element and generates a natural language text for the modified recipe based on the existing recipe and the selected representative member recipe element. The recipe modification system outputs the natural language text for the modified recipe to the requestor. |
| US09870544B2 |
Determining an inventory target for a node of a supply chain
Determining an inventory target for a node of a supply chain includes calculating a demand stock for satisfying a demand over supply lead time at the node of the supply chain, and calculating a demand variability stock for satisfying a demand variability of the demand over supply lead time at the node. A demand bias of the demand at the node is established. An inventory target for the node is determined based on the demand stock and the demand variability stock in accordance with the demand bias. |
| US09870537B2 |
Distributed learning in a computer network
In one embodiment, a first data set is received by a network device that is indicative of the statuses of a plurality of network devices when a type of network attack is not present. A second data set is also received that is indicative of the statuses of the plurality of network devices when the type of network attack is present. At least one of the plurality simulates the type of network attack by operating as an attacking node. A machine learning model is trained using the first and second data set to identify the type of network attack. A real network attack is then identified using the trained machine learning model. |
| US09870535B2 |
Method and apparatus for determining probabilistic context awareness of a mobile device user using a single sensor and/or multi-sensor data fusion
An electronic device described herein includes a sensing unit having at least one sensor to acquire sensing data. An associated computing device extracts sensor specific features from the sensing data, and generates a motion activity vector, a voice activity vector, and a spatial environment vector as a function of the sensor specific features. The motion activity vector, voice activity vector, and spatial environment vector are processed to determine a base level context of the electronic device relative to its surroundings, with the base level context having aspects each based on the motion activity vector, voice activity vector, and spatial environment vector. Meta level context of the electronic device relative to its surroundings is determined as a function of the base level context, with the meta level context being at least one inference made from at least two aspects of the plurality of aspects of the base level context. |
| US09870534B1 |
Predicting network activities associated with a given site
A method predicting a network activity associated with a given network site is provided. The method can include receiving a request to predict a probability of network activity associated with the network site, analyzing historical data associated with the network site, and, based on the analysis, determining the probability of the network activity in future. The method can further include monitoring the network site, ascertaining evidence associated with the network activity, and, based on the evidence, adjusting treatment of the network site. Additionally, the method can include comparing the probability to a predetermined threshold probability and, based on the comparison, selectively taking an action concerning the network site. |
| US09870527B2 |
RFID disruption device and related methods
Devices and methods of disrupting data transfer between an RFID interrogation device (50, 50′) and an RFID data storage device (30, 30′) to be protected, are provided. An example of an embodiment of an RFID signal disruptor device includes a container (41, 141) and an RFID signal disruptor circuit (151, 161, 161′, 171, 171′, 271, 271′) configured to substantially disrupt the signal provided by the RFID interrogation device (50, 50′) when the RFID signal disruptor device is positioned to protect the RFID data storage device (30, 30′). The RFID signal disruptor device can also include an interrogation indicator (63, 296) configured to indicate to a user of the RFID data storage device (30, 30′) that an unauthorized RFID interrogation device (50, 50′) is attempting to interrogate the RFID data storage device (30, 30′) when the RFID signal disruptor device is positioned in close proximity to the RFID data storage device (30, 30′) to provide protection thereto and when the RFID interrogation device (50, 50′) is producing the interrogation signal. |
| US09870526B2 |
Barcode evaluation device, barcode image generation system, barcode evaluation method, barcode image generation method and barcode evaluation program
A barcode evaluation device is configured to conduct an evaluation, which involves determining whether or not a barcode image is displayable on an image display device and determining whether or not the barcode image is readable with a barcode reading device. The evaluation is conducted based on specifics of the barcode image, specifications of the image display device, and specifications of the barcode reading device without actually displaying and reading the barcode image. |
| US09870525B2 |
Semiconductor laser element and method of obtaining information from the semiconductor laser element
A semiconductor laser element includes a substrate having a first main surface and a second main surface; a semiconductor layered body including an active layer, the semiconductor layered body being disposed on the first main surface; and a plurality of sub-patterns that, when combined, form an integrated pattern that allows reading of predetermined information, the plurality of sub-patterns being disposed on either one or both a first main surface side and a second main surface side of the substrate. |
| US09870522B2 |
Label printer API using LUA program scripting language
A system and method are defined for modifying functionality of a printer that is provided with firmware for controlling printing operations. First programming code is developed that, when executed on a computer readable medium, interfaces with the printer's firmware and modifies the functionality of the printer. The first programming code is written in a first programming language, such as the LUA programming language, and the firmware is written in a second programming language other than the first programming language. Thereafter, the first programming code is executed on the computer readable, and the functionality of the printer is modified as a function of the executed first programming code interfacing with the firmware. The firmware is not modified by the interfacing. |
| US09870521B1 |
Systems and methods for identifying objects
Systems, methods and devices for automatically cropping images taken by an electronic device in order to determine the identity of a product contained in the image are described herein. A number of different techniques may be applied to perform the automatic cropping, including a focus sweep technique in which a first image is analyzed for the presence of a human being and then a second image is taken in a plane closer to the camera than the first image. The two frames are analyzed and a resultant image is provided that avoids the regions in which the human being is present to focus on the product. In other embodiments, a motion vector calculation is made between two images in which an individual is holding a product. The motion vectors related to the human are removed and a bounding box is calculated to reduce the size of the image to include a higher percentage of the product, such that the product can be more easily identified. |
| US09870512B2 |
Lidar-based classification of object movement
Within machine vision, object movement is often estimated by applying image evaluation techniques to visible light images, utilizing techniques such as perspective and parallax. However, the precision of such techniques may be limited due to visual distortions in the images, such as glare and shadows. Instead, lidar data may be available (e.g., for object avoidance in automated navigation), and may serve as a high-precision data source for such determinations. Respective lidar points of a lidar point cloud may be mapped to voxels of a three-dimensional voxel space, and voxel clusters may be identified as objects. The movement of the lidar points may be classified over time, and the respective objects may be classified as moving or stationary based on the classification of the lidar points associated with the object. This classification may yield precise results, because voxels in three-dimensional voxel space present clearly differentiable statuses when evaluated over time. |
| US09870511B2 |
Method and apparatus for providing image classification based on opacity
An approach is provided for automated classification of an image based on the fogging attributes associated with the image. The approach involves processing and/or facilitating a processing of image data associated with at least one image to cause, at least in part, an extraction of one or more fogging attributes from the image data. The approach also involves causing, at least in part, a mapping of the one or more fogging attributes to one or more features of at least one classifier, wherein the at least one classifier is trained based, at least in part, on a co-registration of the one or more features to one or more records of previously made image judgements. The approach further involves causing, at least in part, a classification of the at least one image as either in a fogging-afflicted state or a non-fogging-afflicted state based, at least in part, on the at least one classifier. |
| US09870508B1 |
Securely authenticating a recording file from initial collection through post-production and distribution
The technology disclosed relates to data captured in streams from sensors. Streams often are edited, especially video and audio data streams. In particular, the technology disclosed facilitates identification of segments of an originally captured stream that find their way into a finally edited stream and identification of changed segments in the finally edited stream. Summary analysis on self-aligned meta-blocks of stream data is described, along with pushing at least some self-aligned meta-hashes into a blockchain network, applying an alignment and hashing procedure described in a smart contract. |
| US09870506B2 |
Low-power always-on face detection, tracking, recognition and/or analysis using events-based vision sensor
Techniques disclosed herein utilize a vision sensor that integrates a special-purpose camera with dedicated computer vision (CV) computation hardware and a dedicated low-power microprocessor for the purposes of detecting, tracking, recognizing, and/or analyzing subjects, objects, and scenes in the view of the camera. The vision sensor processes the information retrieved from the camera using the included low-power microprocessor and sends “events” (or indications that one or more reference occurrences have occurred, and, possibly, associated data) for the main processor only when needed or as defined and configured by the application. This allows the general-purpose microprocessor (which is typically relatively high-speed and high-power to support a variety of applications) to stay in a low-power (e.g., sleep mode) most of the time as conventional, while becoming active only when events are received from the vision sensor. |
| US09870502B2 |
Apparatus for, a method of, and a network server for detecting data patterns in a data stream
An apparatus (30), method, network server (42, 43, 44, 46, 48) and system (40) for detecting data patterns in a data stream (37) comprising a plurality of data symbols representing characters of an alphabet, said apparatus (30) executing a deterministic finite automata. The apparatus comprises a state transition register (31) comprising a plurality of states (11, 12, 13, 14, 15) including a start state (11) and at least one accepting state (14), and state transitions (16a, 16b, 16c) from an initial state to a destination state triggered by a data symbol of the data stream (37). The apparatus (30) further comprises character position determining means (32) for determining for each data symbol of each state of the state transition register (31) a corresponding character position in the alphabet, it further comprises updating means (33) for updating the state transition register (31) to comprise data symbol ranges (18x, 18y) for data symbols with corresponding subsequent character positions (18b) in the alphabet triggering transitions to a same destination state. The apparatus (30) also comprises range determining means (34) for determining whether a data symbol of the data stream (37) is comprised in a data symbol range (18x, 18y) of the updated state transition register (37), and determining the corresponding destination state (18b) thereof, and triggering means (35) for triggering a state transition (16a, 16b, 16c) from the initial state to the determined destination state for detecting the data pattern. |
| US09870498B2 |
Dimensioning and barcode reading system
A system and method for calibrating a barcode scanning tunnel comprises providing a scanning tunnel having a moveable surface, a camera, and a dimensioning device. Orientations of the dimensioning device and camera are estimated. Instances of a calibration object on the moveable surface are acquired by the dimensioning device and the camera, and a relationship is defined between the two devices. A calibration object is moved along the moveable surface through the devices' fields of view, controlling the camera's focal distance according to the relationship, so that the dimensioning device and the camera acquire instances of the calibration object, and the relationship is revised. |
| US09870487B2 |
Automated manufacturing system with adapter security mechanism and method of manufacture thereof
A method of operation of an automated assembly system includes: detecting a socket adapter having an adapter identifier and an adapter cryptographic chip; calculating a primary key hash based on a primary key in a programming cryptographic chip; calculating an adapter hash based on the adapter identifier using the adapter cryptographic chip; matching the primary key hash to the adapter hash to update an authentication token with the adapter identifier for authenticating the socket adapter on the device programming system; and programming programmable devices in the socket adapter based on the authentication token. |
| US09870486B2 |
Methods and apparatus to assign demographic information to panelists
Methods and apparatus to assign demographic information to panelists are disclosed. Example disclosed methods include generating decoy database proprietor identifiers based on probability density functions. The example method also include querying a database proprietor using panelist database proprietor identifiers and the decoy database proprietor identifiers to obtain demographic information associated with the panelist database proprietor identifiers. The example method also include assigning the panelist database proprietor identifiers to panelists based on the demographic information obtained from the database proprietor. |
| US09870485B2 |
System and method for detecting sensitive user input leakages in software applications
A system and method for detecting sensitive user input leakages in software applications, such as applications created for smartphone platforms. The system and method are configured to parse user interface layout files of the software application to identify input fields and obtain information concerning the input fields. Input fields that contain sensitive information are identified and a list of sensitive input fields, such as contextual IDs, is generated. The sensitive information fields are identified by reviewing the attributes, hints and/or text labels of the user interface layout file. A taint analysis is performed using the list of sensitive input fields and a sink dataset in order to detect information leaks in the sensitive input fields. |
| US09870482B1 |
Method and system for managing and tracking content dissemination in an enterprise
A method and system for managing document dissemination, including obtaining a plurality of operation logs from a plurality of local agents, where each of the plurality of local agents is executing on one of a plurality of clients. The method further includes identifying a document stored on a client of the plurality of clients, determining, using at least one of the plurality of operation logs, a dissemination path of the document between the plurality of clients, and performing an action based on the dissemination path of the document. |
| US09870481B1 |
Associating a data encryption keystore backup with a computer system
The techniques presented herein provide for associating a data encryption lockbox backup with a data storage system. A first set of software system stable values (SSV) is derived from data storage system component values unique to the data storage system. A lockbox storing the first set of SSV and a set of encryption keys associated with a corresponding respective set of data storage system drives is created. Access to the lockbox requires providing a first minimum number of SSV that match corresponding SSV in the first set of SSV. A backup copy of the lockbox is created, wherein access to the backup copy requires providing a second minimum number of SSV that match corresponding SSV in the first set of SSV, wherein the minimum number of SSV is equal to a second match value. The backup copy of the lockbox is stored at a remote location. |
| US09870477B2 |
Security engine for a secure operating environment
The presenting invention relates to techniques for implementing a secure operating environment for the execution of applications on a computing devices (e.g., a mobile phone). In The secure operating environment may provide a trusted environment with dedicated computing resources to manage security and integrity of processing and data for the applications. The applications may be provided with a variety of security services and/or functions to meet different levels of security demanded by an application. The secure operating environment may include a security engine that enumerates and/or determines the security capabilities of the secure operating environment and the computing device, e.g., the hardware, the software, and/or the firmware of the computing device. The security engine may provide security services desired by applications by choosing from the security capabilities that are supported by the secure operating environment and the computing device. |
| US09870474B2 |
Detection of secure variable alteration in a computing device equipped with unified extensible firmware interface (UEFI)-compliant firmware
A firmware-based mechanism for protecting against physical attacks on ROM areas holding Authenticated Variables. A first hash of contents of at least one Authenticated Variable is created by a computing device's UEFI-compliant firmware and stored in a non-volatile storage location. Subsequently a second hash of contents of the at least one Authenticated Variable is created by the firmware and compared by the firmware to the stored hash to identify unauthorized modifications of the at least one Authenticated Variable occurring after the creation of the first hash. |
| US09870472B2 |
Detecting malign code in unused firmware memory
Systems and methods for preventing attachment of malign code to unused firmware memory are described. In some embodiments, an Information Handling System (IHS) may include a processor and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution by the processor, cause the IHS to: read contents of a non-volatile memory (NVM); and determine that the NVM does not include malign code stored thereon, at least in part, by determining that selected memory locations in the NVM where firmware is not stored contain pre-determined values. |
| US09870471B2 |
Computer-implemented method for distilling a malware program in a system
A computer-implemented method for distilling a malware program in a system is disclosed. The computer-implemented method includes steps of receiving a known malware program sample; providing a benign program containing a first instruction set associated with a security; extracting the instruction set; tracing a program segment associated with the instruction set from the benign program using a plurality of data flow pathways; slicing the program segment into a plurality of independent data flow elements; identifying a partial program having elements identical to the plurality of independent data flow elements from the known malware program sample; and removing the partial program from the known malware program sample to distill the malware program. |
| US09870467B2 |
Apparatus and method for implementing a forked system call in a system with a protected region
In an embodiment, at least one machine-readable storage medium includes instructions that when executed enable a system to receive, at a special library of a parent process located outside of a parent protected region of the parent process, from the parent protected region of the parent process, a call to create a child process and responsive to the call received at the special library, issue by the special library a first request and a second request. The first request is to execute, by a processor, a non-secure instruction to create the child process. The second request is to execute, by the processor, a first secure instruction to create a child protected region within the child process. Responsive to the first request the child process is to be created and responsive to the second request the child protected region is to be created. Other embodiments are described and claimed. |
| US09870466B2 |
Hardware-enforced code paths
There is disclosed in one example, a computing apparatus, including: first one or more logic elements providing a code module, the code module comprising a member having a branching policy designating either a public or private member; second one or more logic elements providing a policy engine, operable to: receive a first branch instruction to the member; determine that the branch instructions does not meet the policy; and take a security action. There is also disclosed a method of providing a policy engine, and a computer-readable medium having stored thereon executable instructions for providing a policy engine. |
| US09870461B2 |
CAPTCHA techniques utilizing traceable images
Techniques are disclosed for generating, utilizing, and validating traceable image CAPTCHAs. In certain embodiments, a traceable image is displayed, and a trace of the image is analyzed to determine whether a user providing the trace is human. In certain embodiments, a computing device receives a request for an image, and in response, creates a traceable image based upon a plurality of image elements. The computing device transmits data representing the traceable image to cause a second computing device to display the traceable image via a touch-enabled display. The computing device receives a user trace input data generated responsive to a trace made at the second computing device, and determines whether the trace is within an error tolerance range of the set of coordinates associated with the traceable image. The computing device then sends a result of the determination. |
| US09870458B2 |
Concealed data matching device, concealed data matching program, and concealed data matching method
A concealed data matching method for a computer including: registering a first concealed vector obtained by concealing registered data and key data based on a first random number and a linear combination of row vectors of a determination matrix; acquiring a second concealed vector; calculating a remainder vector indicating a remainder obtained by dividing the difference between the first concealed vector and the second concealed vector; determining the similarity between the registered data and the matching data based on the remainder vector; extracting the key data from the remainder vector if it is determined they are similar; calculating an inter-vector distance between the registered data and the matching data; and determining the similarity between the registered data and the matching data based on the magnitude of the inter-vector distance. |
| US09870445B2 |
Endoscope Inspection report creating apparatus, creating method of endoscope inspection report and storage medium
An endoscope inspection report creating apparatus includes a folder creating section creating a plurality of folders for storing a plurality of endoscopic images for each inspection target; a file name creating section that creates a file name of an endoscopic image file, the file name including inspection result information about an inspection result of an inspection target; an image storage section that stores the endoscopic image file with the file name including the inspection result information, in a specified folder; a report template format storage section storing a report template format for each inspection target; a report template format reading section that reads the report template format from the report template format storage section; a file name reading section that reads file names of endoscopic image files stored in the folder of the inspection target; an automatic report creating section that automatically creates an inspection report by writing the inspection result information and an endoscopic image to be associated with each other in the report template format read by the report template format reading section, the inspection result information being the inspection result information included in the file name of the endoscopic image file, the endoscopic image being the endoscopic image of the endoscopic image file the file name of which is read by the file name reading section, and the automatic report creating section automatically creating the inspection report for all endoscopic image files read by the file name reading section; and an outputting section outputting inspection reports created by the automatic report creating section. |
| US09870441B1 |
Snap-to valid pattern system and method
Described is a method for implementing a snap to capability that enables the manufactured of a valid pattern in a semiconductor device, based upon an originally invalid pattern. |
| US09870440B2 |
Method for automatically generating a netlist of an FPGA program
A method for generating a netlist of an FPGA program. The model of the FPGA program is composed of at least two components, each component being assigned a separate partition on the FPGA. An independent build is carried out for each component and an overall classification is generated from the components, wherein the build jobs are automatically started after a trigger event and the trigger event is a saving of a component, the exiting of a component of the design, or a time-controlled, automated initiation of a build. |
| US09870436B2 |
Creating a broken representation of a computer-aided design model
A computer-implemented method and system create computer-generated three-dimensional (3D) models in a broken state (broken view representation). To create a 3D model in a broken state, an area of the 3D model in an unbroken state is removed to create the 3D model in the broken state and a mapping between the 3D model in the unbroken state and the 3D model in a broken state is implemented to enable operations performed on the 3D model in the broken state to utilize data defining the 3D model in the unbroken state. The mapping maintains a relationship between data defining the 3D model in the unbroken state and data defining the 3D model in the broken state. |
| US09870434B1 |
Techniques for filtering workload and performance data
Described are techniques for processing collected workload and performance data. Components of a component category are selected, filtering criteria is specified, the filtering criteria is applied to the collected workload and performance data for the components selected and thereby generating filtered data results, and the filtered results are viewed. The filtering criteria may include a first operation and a first set of one or more metrics included in the collected workload and performance data for the components selected. The first operation may be applied to the first set of one or more metrics and may be selected from a plurality of operations. The plurality of operations may include at least one arithmetic operation, at least one logical operation and at least one relational operation. |
| US09870431B2 |
Method and device for controlling the access to knowledge networks
The invention relates to an efficient system for user rights in a semantic digital network, whereby users are arranged in the same semantic network as the information objects. The rights are thus derived from the semantic relations between users and information objects in a common semantic network. |
| US09870426B2 |
Managing information associated with network resources
Systems, methods, and interfaces for the selective management of information collected by a browser are provided. The browser obtains a network resource, such as a Web page, from a content provider, and collects information associated with the display and interaction with the content by a user. The browser presents, among other controls, a graphical icon that is representative of an integrated command to remove information collected while accessing a first network resource and to cause the browser application to access a second accessed network resource. Upon receipt of an input corresponding to the selection of the graphical icon, the browser deletes information collected while accessing the first network resource and accesses the second network resource. |
| US09870425B2 |
Localized selectable location and/or time for search queries and/or search query results
Briefly, embodiments of methods or systems providing a mobile device user with localized and/or time-selectable search query terms and/or search results are provided. |
| US09870423B1 |
Associating an entity with a search query
Methods and apparatus for associating an entity with at least one search query. Some implementations are directed to methods and apparatus for identifying multiple queries associated with an entity and identifying one or more of the queries as an entity search query that provides desired search results for the entity. Some implementations are directed to methods and apparatus for identifying a particular entity and, in response to identifying the particular entity, identifying an entity search query corresponding to the particular entity. |
| US09870421B2 |
Method for accurately searching for comprehensive information
The present invention provides a method for accurate search of comprehensive information. By providing coordinates of an alternative pragmatic keyword indicating a function and a utility scope of target search information for any search keyword, a general topic keyword, a pragmatic keyword, a common keyword, and a combination result thereof are obtained, and structured information, structured summary information, structured mapping information, semi-structured information, and unstructured information are concurrently searched for on the Internet, so that complete search and accurate search of various types of information on the Internet can be implemented in one search attempt, thereby achieving an objective of improving Internet information search efficiency substantially. |
| US09870414B2 |
Secure deletion operations in a wide area network
Methods, systems, and computer program products are provided for performing a secure delete operation in a wide area network (WAN) including a cache site and a home site. A method includes identifying a file for deletion at the cache site, determining whether the file has a copy stored at the home site, detecting a location of the copy at the home site prior to a disconnection event of the cache site from the home site, deleting the file from the cache site during the disconnection event, and in response to the secure deletion of the file not being complete during the disconnection event, indicating on a table a remote inode number assigned to the copy associated with the file at the home site, a name under which the copy is saved, and a list of data chunk tuples specifying selected data of the copy to undergo secure deletion. |
| US09870412B2 |
Automated integrated high availability of the in-memory database cache and the backend enterprise database
A cluster manager manages copies of a mid-tier database as a mid-tier database cluster. The cluster manager may concurrently manage a backend database system. The cluster manager is configured to monitor for and react to failures of mid-tier database nodes. The cluster manager may react to a mid-tier database failure by, for example, assigning a new active node, creating a new standby node, creating new copies of the mid-tier databases, implementing new replication or backup schemes, reassigning the node's virtual address to another node, or relocating applications that were directly linked to the mid-tier database to another host. Each node or an associated agent may configure the cluster manager during initialization, based on common cluster configuration information. Each copy of the mid-tier database may be, for example, a memory resident database. Thus, a node must reload the entire database into memory to recover a copy of the database. |
| US09870409B2 |
Entity display priority in a distributed geographic information system
A system for ranking geospatial entities is described. In one embodiment, the system comprises an interface for receiving ranking data about a plurality of geospatial entities and an entity ranking module. The module uses a ranking mechanism to generate place ranks for the geospatial entities based on the ranking data. Ranked entity data generated by the entity ranking module is stored in a database. The entity ranking module may be configured to evaluate a plurality of diverse attributes to determine a total score for a geospatial entity. The entity ranking module may be configured to organize ranked entity data into placemark layers. |
| US09870407B2 |
Automated and delegated model-based row level security
Business groups are created to secure business entities of a BI data model. In one aspect, a user to be secured is selected and a business group of the BI model is retrieved. Based on the business group, access to a business entity of the BI model is secured. The business group is associated with the business entity it secures. A value of the secured business entity is selected. A user is secured by assigning the user to the business group for the selected value. The value of the secured business entity is assigned to the user. In one aspect, requests from the user to access the secured business entity are filtered based on the assigned, to the user, value of the business entity. |
| US09870406B2 |
User recommendation method and system in SNS community, and computer storage medium
The present invention relates to a user recommendation method and system in SNS community and a computer storage medium. The method includes following steps: obtaining an interaction record between a first user and a second user in a first community; generating an interaction frequency of the first user and the second user according to the interaction record; calculating familiarity of the first user and the second user according to the interaction frequency; recommending the second user whose familiarity with the first user exceeds a threshold to the first user in a second community. The method and system and computer storage medium calculate familiarity between users in other community, recommend other users to the user in current community according to familiarity, expand information sources used for determining which users are persons user may possibly know, thereby obtaining more persons user may possibly know and improving efficiency of expanding user relationship circle. |
| US09870401B2 |
Database system with highly denormalized database structure
A database system converts a multi-table relational database into a wide table incorporating all of the information of the relational database tables and converts queries for the relational database system into a form applicable to the wide table. Dictionary compression and/or columnar store allow faster query processing despite a substantially larger size of the wide table. |
| US09870400B2 |
Managed runtime cache analysis
Analyzing a managed runtime cache is provided. A heap associated with a managed runtime environment, where the heap includes an N-generation cache or a plurality of objects associated with a program operating within a managed runtime environment is identified. A snapshot of the heap is produced, wherein the snapshot identifies a memory location for each object of the plurality of objects at which the object is stored. A generation of each of the plurality of objects based, at least in part, on the memory location of the object is determined. One or more suggestions based, at least in part, on the memory location of the plurality of objects is provided. |
| US09870396B2 |
Immediate join spilling scheme for a database
Embodiments relate to an immediate join spilling scheme for a database. An aspect includes receiving a command to perform a join of an inner table and an outer table in a database. Another aspect includes spilling a plurality of hash tables to a disk memory, each hash table corresponding to a respective inner table partition. Another aspect includes registering, by a first agent of a plurality of agents, a set of inner table partitions that require processing by the first agent to complete the join for a first stride of rows of the outer table. Another aspect includes, based on determining that a hash table corresponding to a registered inner table partition of the first agent has been loaded into the local memory by the second agent of the plurality of agents, performing the join of the loaded hash table and the first stride of rows of the outer table by the first agent. |
| US09870389B2 |
Interactive user interface for dynamic data analysis exploration and query processing
The systems and methods described herein provide highly dynamic and interactive data analysis user interfaces which enable data analysts to quickly and efficiently explore large volume data sources. In particular, a data analysis system, such as described herein, may provide features to enable the data analyst to investigate large volumes of data over many different paths of analysis while maintaining detailed and retraceable steps taken by the data analyst over the course of an investigation, as captured via the data analyst's queries and user interaction with the user interfaces provided by the data analysis system. Data analysis paths may involve exploration of high volume data sets, such as Internet proxy data, which may include trillions of rows of data. The data analyst may pursue a data analysis path that involves, among other things, applying filters, joining to other tables in a database, viewing interactive data visualizations, and so on. |
| US09870386B1 |
Reducing I/O operations for on-demand demand data page generation
A data store maintaining data may implement reducing input/output (I/O) operations for on-demand data page generation. Log records may be maintained for data pages of data describing changes to the data pages. A coalesce operation may be performed when log records for a data page exceed a coalesce threshold for the data page, applying the log records for the data page to a version of the data page and creating a new version that includes the changes indicated by the log records. An indication may be received to increase the coalesce threshold for a particular data page, delaying a coalesce operation for the data page according to the increased coalesce threshold. The indication may be received from a storage engine that identifies a delay for the particular data page. |
| US09870384B2 |
Database system transaction management
Systems, methods, and products for database system transaction management are provided herein. One aspect provides for annotating via a computing device at least one data object residing on the computing device utilizing at least one transaction tag, the at least one transaction tag being configured to indicate a status of an associated data object; processing at least one database transaction utilizing a transactional memory process, wherein access to the at least one data object is determined based on the status of the at least one data object; and updating the status of the at least one data object responsive to an attempted access of the at least one data object by the at least one database transaction. Other embodiments and aspects are also described herein. |
| US09870381B2 |
Detecting quasi-identifiers in datasets
Quasi-identifiers (QIDs) are detected in a dataset using a set of computing tasks. The dataset has a plurality of records and a set of attributes. An index is generated for the dataset. The index has an indicator for each attribute value of each record in the dataset. Each indicator specifies all the records in the dataset having the same value for the attribute. Each task is assigned an attribute combination and a subset of the plurality of records in the dataset and is passed to a thread for execution on computing resources. The executing task inspects the set of records specified by the index indicator for each attribute value in the attribute combination to produce a result. The result of at least one task identifies a unique record for the associated attribute combination. The attribute combination producing the unique record is a QID. |
| US09870380B2 |
Methods and arrangements for device profiles in wireless networks
Embodiments provide a device profile mechanism for wireless devices. Many embodiments comprise a medium access control (MAC) sublayer logic to build frames comprising a device profile index element for a first device. Embodiments may facilitate access by a second device to a device profile for the first device without communication of the entire device profile from the first device. In some embodiments, the second device may access a storage medium integrated with or accessible to the second device to determine the device profile. Some embodiments may store the device profile index element in memory, in logic, or in another manner that facilitates transmission of the device profile index element in frames. Some embodiments may receive and detect communications with the device profile index element. Further embodiments may generate and transmit a communication with the device profile index element. |
| US09870378B2 |
Read and delete input/output operation for database management
A computer-implemented method for improving database management includes selecting one or more database records that are requested based on a query statement. The one or more database records are read from a first database file. The one or more database records are copied from the first database file and stored to a memory. The one or more database records are deleted from the first database file at substantially the same time as the reading the one or more database records. The reading and the deleting occur through a single read and delete input/output (I/O) operation. |
| US09870377B2 |
Signal-to-noise ratio image validation
An image is compared to a validation image to obtain a signal-to-noise ratio. The signal-to-noise ratio is used to determine validity of the image. According to an embodiment, the image includes a barcode. According to another embodiment, a minimum threshold value for the signal-to-noise ratio is set and the validity of the image is determined based on the minimum threshold value and the signal-to-noise ratio. The minimum threshold value can be determined by using respective signal-to-noise ratios resulting from comparing a valid image to a validation image and an invalid image to a validation image. |
| US09870376B2 |
Method and system for concept summarization
A method and a system for summarizing a concept are provided. A query corresponding to a concept is received from a user. A plurality of images and corresponding descriptive information may be collected based on the query. The plurality of images and the descriptive information may be processed to form feature vectors and processed descriptive information respectively. Further, one or more topics may be identified for the plurality of images. Each of the plurality of images may be assigned with one or more topic distribution values corresponding to the one or more topics. The one or more topics correspond to the processed descriptive information. A sparse set of images may be determined based on the feature vectors and the assigned topic distribution values, to summarize the concept. Also, a target summary may be built from the summarized concept, by regularizing one or more distribution constraints. |
| US09870367B2 |
System and method of using data blocks to optimize file storage
A system and method is disclosed for using data blocks to optimize file storage in electronic data storage. An example method includes storing a data file in electronic memory, where the data file includes a main block and a plurality of secondary blocks, with the main block including metadata that indicates respective locations of the secondary blocks relative to the main block. The method further includes performing a sparse operation of a data file to determine regions of the data file that contains unused space, determining blocks that are overlapped by the regions of the data file that contains unused space, removing the overlapped blocks, and storing the updated data file in an electronic database. |
| US09870364B2 |
Intelligently categorizing data to delete specified amounts of data based on selected data characteristics
A method assigns stored documents within a distributed storage system (DSS) to various document categories to enable a target number of documents to be deleted. An intelligent storage management (ISM) utility identifies a data storage threshold value used to control data storage within the DSS. If a current storage usage exceeds the data storage threshold value, the ISM utility calculates, based on the current storage usage, a target number of documents that can be deleted from the DSS. The ISM utility utilizes a recursive process, which includes assigning stored documents to groups including a set of document categories based on data characteristics of the stored documents. The ISM utility further utilizes the recursive process to delete, based on an established ordering of the groups, all of the stored documents assigned to a subset of the groups in order to remove the target number of stored documents. |
| US09870362B2 |
Interactive data-driven presentations
The techniques and systems described herein efficiently and effectively enable an author to create an interactive, data-driven presentation during an authoring stage. Moreover, the techniques and systems enable a consumer to interact with the data-driven presentation during a consuming stage. For example, the techniques and systems generate and output graphical user interfaces that enable an author to define consumer interaction settings so a consumer of the presentation can: switch between alternative types of visual elements (e.g., charts), determine whether a visual element is presented with or without animation, determine a presentation timing of visual elements and/or textual elements, determine presentation styles (e.g., color scheme, font type, etc.), filter a set of data presented in a visual element so that a subset of the data can be viewed or distinguished, and/or adjust a scale associated with a visual element (e.g., change a scale for an axis of a chart). |
| US09870360B1 |
Shared metadata for media files
Methods, systems, and apparatus, including computer program products, for organizing music tracks based on shared metadata. In one aspect, a method includes identifying a set of common music tracks associated with a first user and a second user, wherein the set of common music tracks includes at least one music track present in both a first set of music tracks associated with the first user and a second set of music tracks associated with the second user. Metadata associated with at least one music track in the set of common music tracks is retrieved, the metadata being specific to the second user. A set of user music tracks associated with the first user is organized based on the retrieved metadata. |
| US09870359B2 |
System and method for dynamic document retention
A system for dynamic document retention, in a multi-owner environment that includes a document management system, registers, in a retention service, plural different document owners for a same document. The system receives a different owner-defined document retention policy for the document from each of the document owners, and registers, in a plug-in registry, the policies. In response to a scheduler or a document owner, the system triggers an update of a document retention policy, adds/deletes a document owner from the document, and/or deletes the document when there are no remaining document owners. The document management system includes a retention service that tracks the owners of the same document(s), the plug-in registry that tracks the different document retention policies of the different document owners, and an optional scheduler. The event-based retention policies can be responsive to events occurring internal to or external to the document management system. |
| US09870356B2 |
Techniques for inferring the unknown intents of linguistic items
Functionality is described herein for determining the intents of linguistic items (such as queries), to produce intent output information. For some linguistic items, the functionality deterministically assigns intents to the linguistic items based on known intent labels, which, in turn, may be obtained or derived from a knowledge graph or other type of knowledge resource. For other linguistic items, the functionality infers the intents of the linguistic items based on selection log data (such as click log data provided by a search system). In some instances, the intent output information may reveal new intents that are not represented by the known intent labels. In one implementation, the functionality can use the intent output information to train a language understanding model. |
| US09870354B2 |
Use of temporary optimized settings to reduce cycle time of automatically created spreadsheets
Aspects of the present invention provide a solution for reducing cycle time of automatically created spreadsheets. Specifically, an embodiment of the present invention provides a way to create a spreadsheet from data that is in a native format more quickly and/or efficiently. To do so, the invention accesses a control file using optimized settings to create the spreadsheet. Then, after creation of the spreadsheet, the invention uses a second control file having the final settings to modify the spreadsheet in preparation for output. The invention may use agents to perform all or a portion of these activities. |
| US09870349B2 |
Systems and methods for managing loading priority or sequencing of fragments of a web object
This disclosure is directed to methods and systems for delivering an item of web content requested by a client. An intermediary between a client and a server may intercept a request from the client to the server for an item of web content. The intermediary may split the item of web content into a plurality of fragments. The intermediary may identify, responsive to the request, a first fragment of the plurality of fragments to transmit to the client. The intermediary may inject executable code into the first fragment of the plurality of fragments. The executable code may be configured to conditionally incorporate additional fragments from the plurality of fragments into the first fragment at the client. |
| US09870346B2 |
Clickable links within live collaborative web meetings
An approach for creating a clickable link within a presentation during a live collaborative web meeting is provided. The approach identifies one or more uniform resource locators within the presentation. The approach retrieves metadata for each of the one or more uniform resource locators within the presentation. The approach presents the metadata for each of the one or more uniform resource locators with a corresponding image from the presentation. The approach creates the clickable link for each of the one or more uniform resource locators with the corresponding image. |
| US09870344B2 |
Reassigning ordinal positions of content item slots according to viewport information during resource navigation
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for adjusting ordinal positions for content item slots in response to determining that a content item slot with a highest slot ordinal position relative to the other content item slots in a resource is not within a viewport area. Adjusting the adjusting ordinal positions of either the content item slots or content items to be served in the content item slots ensures that a content item slot in the viewport displays a content item with a highest respective ordinal position in a ranking relative to other content items is rendered in the content item slot within the viewport area. |
| US09870339B2 |
Hardware processors and methods for tightly-coupled heterogeneous computing
Methods and apparatuses relating to tightly-coupled heterogeneous computing are described. In one embodiment, a hardware processor includes a plurality of execution units in parallel, a switch to connect inputs of the plurality of execution units to outputs of a first buffer and a plurality of memory banks and connect inputs of the plurality of memory banks and a plurality of second buffers in parallel to outputs of the first buffer, the plurality of memory banks, and the plurality of execution units, and an offload engine with inputs connected to outputs of the plurality of second buffers. |
| US09870334B2 |
Dense, nested arrangement of multiple peripheral component interconnect express (PCIe) cards within a thin server volume
An information handling system (IHS) server volume includes at least two pairs of flexible peripheral component interconnect express (PCIe) media for connecting data signals and power supply signals via riser cards mounted against respective PCIe devices in large adjacent physical slot locations. A first PCIe device corresponding to a first riser card and a second PCIe device corresponding to a second riser card are relatively positioned to enable the second riser card to be fitted within a specified space between the first PCIe device and the first riser card while a footprint of a first PCIe connector corresponding to the first PCIe device overlaps a footprint of a second PCIe connector corresponding to the second PCIe device. First and second PCIe cards provided by the first and second PCIe devices respectively are inserted into respective PCIe connectors via the first pair of riser cards having a dense nested arrangement. |
| US09870329B2 |
Techniques for escalating interrupts in a data processing system
A method of handling interrupts includes receiving an event notification message (ENM) that specifies a level, an event target number (ETN), and a number of bits to ignore. A group of virtual processor threads that may be potentially interrupted are determined based on the ETN, the number of bits to ignore, and a process identifier when the level specified in the ENM corresponds to a user level. The ETN identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore when determining a group of virtual processor threads that may be potentially interrupted. In response to no virtual processor thread within the group of virtual processor threads being dispatched and operating on an associated physical processor, an escalate message that includes an escalate event number is transmitted. The escalate event number is used to generate a subsequent ENM. |
| US09870328B2 |
Managing buffered communication between cores
Communicating among multiple sets of multiples cores includes: buffering messages in first buffer associated with a first set of multiple cores; buffering messages in a second buffer associated with a second set of multiple cores; and transferring messages over communication circuitry from cores not in the first set to the first buffer, and to transferring messages from cores not in the second set to the second buffer. A first core of the first set sends messages corresponding to multiple types of instructions to a second core of the second set through the communication circuitry. The second buffer is large enough to store a maximum number of instructions of a second type that are allowed to be outstanding from cores in the first set at the same time, and still have enough storage space for one or more instructions of a first type. |
| US09870321B2 |
Data storage device and flash memory control method
A flash memory control technology with high reliability. In a power recovery process, a microcontroller is configured to duplicate a last write page of a run-time write block of a flash memory and thereby generate a duplicated page in the run-time write block. The microcontroller is further configured use the mapping information accessed from the duplicated page in rebuilding a physical-to-logical address mapping table rather than the mapping information accessed from the last write page. The microcontroller is configured to maintain the physical-to-logical address mapping table on a random access memory for the run-time write block and is further configured to use the physical-to-logical address mapping table to update a logical-to-physical address mapping table maintained in the flash memory. |
| US09870320B2 |
Method for dynamically storing a flash translation layer of a solid state disk module
A shared memory is initially set in the solid state module. A command for accessing information is received. The translation time of the flash translation layer is measured. The translation time is compared to a predetermined time. Dynamic storing of the flash translation layer is initialized. And, the flash translation layer is moved to the shared memory to increase efficiency. |
| US09870308B2 |
Debugging of prefixed code
A debugging capability that enables the efficient debugging of code that has prefixes, referred to herein as prefixed code. To debug application code, in which the application code includes a prefixed instruction to be modified by a prefix, a trap is provided. The trap is configured to report a presence of the prefix, but to otherwise perform the trap functions absent the prefix; i.e., the prefix is otherwise ignored in the processing of the trap. |
| US09870307B2 |
Regression testing of software services
Techniques are provided for mocking downstream services while regression testing a service. In one technique a version of a service processes a request, during which one or more computers intercept downstream service calls made by the version of the service. For each downstream service call of the downstream calls, a computer provides, to the version of the service, a response of the downstream service call, which was previously recorded while processing the request in a production environment. Processing, by the version of the service, the request involves processing the request based on the response of at least one of the downstream service calls. |
| US09870304B2 |
System for verifying historical artifacts in disparate source control systems
A system for verifying historical artifacts in disparate source control systems. The system comprising a computer processor, a computer-readable hardware storage medium, and program code embodied with the computer-readable hardware storage medium for execution by the computer processor to implement a method for obtaining historical artifacts from a target repository; obtaining historical artifacts from a source repository; and verifying the historical artifacts in the target repository match the historical artifacts in the source repository. Verification further comprises comparing commit data in the historical artifacts in the target repository with commit data in the historical artifacts in the source repository; and evaluating whether each commit data event in the historical artifacts in the target repository is equivalent to the corresponding commit data event in the historical artifacts in the source repository. |
| US09870297B2 |
Optimization of power and computational density of a data center
Techniques for optimizing power and computational density of data centers are described. According to various embodiments, a benchmark test is performed by a computer data center system. Thereafter, transaction information and power consumption information associated with the performance of the benchmark test are accessed. A service efficiency metric value is then generated based on the transaction information and the power consumption information, the service efficiency metric value indicating a number of transactions executed via the computer data center system during a specific time period per unit of power consumed in executing the transactions during the specific time period. The generated service efficiency metric value is then compared to a target threshold value. Thereafter, a performance summary report indicating the generated service efficiency metric value, and indicating a result of the comparison of the generated service efficiency metric value to the target value, is generated. |
| US09870296B1 |
Evaluating system performance
A method and system for use in evaluating system performance is disclosed. In at least one embodiment, the method and system comprises collecting system performance, management operations, and system events data for a computer system; correlating the management operations and the system events data with the performance data; and based on the correlation, providing a graphical user interface for enabling performance evaluations of the computer system by graphically displaying the management operations and the system events data overlaying the performance data. |
| US09870291B2 |
Snapshotting shared disk resources for checkpointing a virtual machine cluster
Embodiments are directed to backing up a virtual machine cluster and to determining virtual machine node ownership prior to backing up a virtual machine cluster. In one scenario, a computer system determines which virtual machines nodes are part of the virtual machine cluster, determines which shared storage resources are part of the virtual machine cluster and determines which virtual machine nodes own the shared storage resources. The computer system then indicates to the virtual machine node owners that at least one specified application is to be quiesced over the nodes of the virtual machine cluster, such that a consistent, cluster-wide checkpoint can be created. The computer system further creates a cluster-wide checkpoint which includes a checkpoint for each virtual machine in the virtual machine cluster. |
| US09870289B2 |
Notifying a backup application of a backup key change
A notifying system to notify a backup application of a backup key change includes receiving, from a backup application, a request to associate with a backup key, replicating the backup key to create a replica backup key, associating the replica backup key with the backup application, monitoring the backup key for a change, the change indicating a backup event has occurred, and setting the replica backup key to indicate the backup key has changed. |
| US09870287B1 |
Volume duplication
A method, computer program product, and computing system for receiving a point-in-time copy command for a virtual volume exposed within a storage virtualization layer of a storage system. The point-in-time copy command is provided to one or more data arrays underlying the storage virtualization layer. The virtual volume is associated with physical storage within the one or more data arrays, thus defining associated physical storage. A level of high-availability is identified for the associated physical storage. A copy of the associated physical storage is generated that has the same level of high-availability, thus defining a high-availability copy. |
| US09870282B2 |
Systems and methods for providing service and support to computing devices with boot failure
Systems and methods for providing service and to computing devices. In some embodiments, an Information Handling System (IHS) includes a Basic I/O System (BIOS) and a memory coupled to the BIOS, the memory including program instructions stored thereon that, upon execution by the IHS, cause the IHS to: determine that the IHS is operating in a degraded state; and initiate one or more support, diagnostics, or remediation operations in response to the determination. |
| US09870280B2 |
Apparatuses and methods for comparing a current representative of a number of failing memory cells
Apparatuses and methods for comparing a sense current representative of a number of failing memory cells of a group of memory cells and a reference current representative of a reference number of failing memory cells is provided. One such apparatus includes a comparator configured to receive the sense current and to receive the reference current. The comparator includes a sense current buffer configured to buffer the sense current and the comparator is further configured to provide an output signal having a logic level indicative of a result of the comparison. |
| US09870279B2 |
Analysis apparatus and analysis method
An analysis apparatus is connectable to a terminal capable of displaying web pages by accessing a web server capable of executing a web application. The analysis apparatus comprises a processor, a memory and an interface. The processor is configured to perform the following processing of: receiving at least one log concerning the web application stored in the terminal from the terminal via the interface; acquiring a plurality of kinds of use condition feature values based on the log received, the plurality of kinds of use condition feature values being information characterizing conditions of use of the web application; analyzing whether a correlation exists between a first kind of use condition feature values and a second kind of use condition feature values in the plurality of kinds of use condition feature values acquired in the processing of acquiring; and outputting an analysis result obtained by the processing of the analyzing. |
| US09870278B2 |
Managing spaces in memory
A method of and system for managing spaces in memory of a storage facility is disclosed. The method and system includes storing first and second identifiers in first and second spaces in memory in response to allocating the second space for a set of data. The first identifier is stored in a first field within the first space. The first space has a pointer in a second field. The pointer in the second field indicates an address of the second space. The second identifier is stored within a portion of the second space. In response to an error event, the first and second identifiers may be captured. A determination is made as to whether the pointer is directed to the set of data. The determination is based on a comparison of the first identifier and the second identifier. |
| US09870276B2 |
User message queue method for inter-process communication
A computing device for a network of computer controlled devices that communicate with each other using a pre-determined protocol includes a computing module for sending a data message with a pre-determined message feature and a message queue module. The message queue module includes a message forwarding module and a message listening module. The message forwarding module receives data messages from its computing module and forwards the data messages to another computer controlled device of the same network. The message listening module receives data messages from another computer controlled device of the same network, checks for a match of the message features of the data messages with a pre-determined message interest feature, and if there is a match between the message feature and the pre-determined message interest feature, forwards the respective data message to the computing module. |
| US09870274B2 |
Method of executing a job in a computer system, a resource manager and a high performance computer system
A method of executing a job in a computer system having a plurality of different allowed configurations comprises: receiving the job; identifying one or more representative samples of the job; executing the one or more representative samples in an experimental phase, the or each representative sample being executed with each different allowed configuration of the computer cluster; collecting execution data including speed of execution and energy used in each configuration during execution of the one or more representative samples and selecting a suitable configuration for the job taking speed of execution and energy use into account; and executing the remainder of the job in a completion phase with the suitable configuration. |
| US09870273B2 |
Methods and systems for quantum ready and quantum enabled computations
The present disclosure provides methods, systems, and media for allowing access to quantum ready and/or quantum enabled computers in a distributed computing environment (e.g., the cloud). Such methods and systems may provide optimization and computational services on the cloud. Methods and systems of the present disclosure may enable quantum computing to be relatively and readily scaled across various types of quantum computers and users at various locations, in some cases without the need for users to have a deep understanding of the resources, implementation or the knowledge that may be required for solving optimization problems using a quantum computer. Systems provided herein may include user interfaces that enable users to perform data analysis in a distributed computing environment while taking advantage of quantum technology in the backend. |
| US09870271B1 |
System and method for deploying virtual servers in a hosting system
Some embodiments provide a method for creating an image of a virtual machine. The method identifies a particular computer system operating as a virtual machine with a particular configuration on a hardware resource of a hosting system that includes several hardware resources. The method captures data representing the particular computer system. Capturing the data includes copying a particular section of the data, computing a checksum for the particular section of the data, and streaming the particular section with the computed checksum to a storage. |
| US09870270B2 |
Realizing graph processing based on the mapreduce architecture
A method and device for realizing graph processing based on the MapReduce architecture is disclosed in the invention. The method includes the steps of: receiving an input file of a graph processing job; predicting a MapReduce task execution time distribution of the graph processing job using an obtained MapReduce task degree-execution time relationship distribution and a degree distribution of the graph processing job; and dividing the input file of the graph processing job into input data splits of MapReduce tasks according to the predicted MapReduce task execution time distribution of the graph processing job. |
| US09870267B2 |
Virtual vector processing
Methods and apparatus to provide virtualized vector processing are disclosed. In one embodiment, a processor includes a decode unit to decode a first instruction into a decoded first instruction and a second instruction into a decoded second instruction, and an execution unit to: execute the decoded first instruction to cause allocation of a first portion of one or more operations corresponding to a virtual vector request to a first processor core, and generation of a first signal corresponding to a second portion of the one or more operations to cause allocation of the second portion to a second processor core, and execute the decoded second instruction to cause a first computational result corresponding to the first portion of the one or more operations and a second computational result corresponding to the second portion of the one or more operations to be aggregated and stored to a memory location. |
| US09870260B2 |
Managing a set of assets for a user in a shared pool of configurable computing resources
Disclosed aspects include managing a set of assets for a user in a shared pool of configurable computing resources. The shared pool of configurable computing resources has a set of virtual machines. A set of usage data for the user is established. The set of usage data corresponds to usage of an asset by the user. Based on the set of usage data for the user, an asset action for the asset for the user on a virtual machine is determined. In response to determining the asset action for the asset, the asset action for the asset for the user on the virtual machine is selected. |
| US09870257B1 |
Automation optimization in a command line interface
A method of automation optimization in a command line interface is provided. The method includes receiving a configuration input that includes one or more commands and parsing the configuration input. The method also includes generating a command list that includes one or more tasks, based on the configuration input and populating a queue with the one or more tasks. The method includes executing each of the one or more tasks from the queue, on a command line interface and outputting a result, based on the executing. |
| US09870255B2 |
Hardware acceleration wait time awareness in central processing units with multi-thread architectures
Provided is a hardware accelerator, central processing unit, and computing device. A hardware accelerator includes a task accelerating unit configured to, in response to a request for a new task issued by a hardware thread, accelerate the processing of the new task and produce a processing result for the task; a task time prediction unit configured to predict the total waiting time of the new task for returning to a specified address associated with the hardware thread. One aspect of this disclosure makes the hardware thread aware of the time to be waited for before getting a processing result, facilitating its task planning accordingly. |
| US09870254B2 |
Multithreaded transactions
Embodiments relate to multithreaded transactions. An aspect includes assigning a same transaction identifier (ID) corresponding to the multithreaded transaction to a plurality of threads of the multithreaded transaction, wherein the plurality of threads execute the multithreaded transaction in parallel. Another aspect includes determining one or more memory areas that are owned by the multithreaded transaction. Another aspect includes receiving a memory access request from a requester that is directed to a memory area that is owned by the transaction. Yet another aspect includes based on determining that the requester has a transaction ID that matches the transaction ID of the multithreaded transaction, performing the memory access request without aborting the multithreaded transaction. |
| US09870252B2 |
Multi-threaded processing with reduced context switching
Multi-threaded processing with reduced context switching is disclosed. Context switches may be avoided through the use of pre-emption notification, a pre-emption wait time attribute and a no-context-save yield. |
| US09870248B2 |
Page table based dirty page tracking
A hypervisor identifies a set of pages associated with a guest operating system (OS) of a virtual machine (VM) that are shared with an application. The hypervisor maps each of the set of pages associated with the guest OS to a corresponding page associated with the application. The hypervisor modifies a write protection attribute for each corresponding page associated with the application to cause a protection page fault upon an application attempt to update the corresponding page. The hypervisor detects updated pages by detecting the protection page fault upon the application attempt to update one of the corresponding pages associated with the application. The hypervisor then logs a modification of each updated corresponding page. |
| US09870242B2 |
Parallel mapping of client partition memory to multiple physical adapters
Techniques are disclosed for performing input/output (I/O) requests to two or more physical adapters in parallel. One method for performing an input/output (I/O) request includes mapping an address for at least a first page associated with a virtual I/O request to an entry in a virtual TCE table and identifying a plurality of physical adapters required to service the virtual I/O request. For each of the identified physical adapters, the entry in the virtual TCE table is mapped to an entry in a physical TCE table corresponding to the physical adapter. This method may also include, in parallel, issuing physical I/O requests to the physical adapters. |
| US09870237B2 |
System and method for supporting distributed class loading in a virtual machine (VM)
A system and method can support distributed class loading in a computing environment, such as a virtual machine. A class loader can break a classpath into one or more subsets of a classpath, wherein the classpath is associated with a class. Furthermore, the class loader can use one or more threads to locate the class based on said one or more subsets of the classpath. Then, the class loader can load the class after a said thread locates the class. |
| US09870236B2 |
Control system for a wind turbine
A control system for a wind turbine is provided. The control system includes a plurality of controllers distributed in the wind turbine or the wind power plant; and a plurality of data storage units, each data storage unit being arranged at a respective predetermined position in the wind turbine or the wind power plant and being coupled to the controller arranged at the same position; wherein each data storage unit comprises operational information pertaining to the predetermined position in the wind turbine or the wind power plant; and wherein each controller is configured to read the operational information of the corresponding data storage unit and to determine its function from the operational information. |
| US09870232B2 |
Extensible method and system for storage metadata
According to an aspect of an embodiment, a system of using an extensible language to represent storage metadata includes a computer-readable storage medium and a processing device. The computer-readable storage medium may have stored thereon storage metadata. The processing device may be configured to write the storage metadata to the computer-readable storage medium in an extensible language format. The processing device may also be configured to manipulate the storage metadata in the extensible language format. The processing device may also be configured to transfer the storage metadata in the extensible language format. |
| US09870229B2 |
Independent mapping of threads
Embodiments of the present invention provide systems and methods for mapping the architected state of one or more threads to a set of distributed physical register files to enable independent execution of one or more threads in a multiple slice processor. In one embodiment, a system is disclosed including a plurality of dispatch queues which receive instructions from one or more threads and an even number of parallel execution slices, each parallel execution slice containing a register file. A routing network directs an output from the dispatch queues to the parallel execution slices and the parallel execution slices independently execute the one or more threads. |
| US09870227B2 |
Performing stencil computations
A method and apparatus for performing stencil computations efficiently are disclosed. In one embodiment, a processor receives an offset, and in response, retrieves a value from a memory via a single instruction, where the retrieving comprises: identifying, based on the offset, one of a plurality of registers of the processor; loading an address stored in the identified register; and retrieving from the memory the value at the address. |
| US09870225B2 |
Processor with virtualized instruction set architecture and methods
A processor comprises a decoder for decoding an instruction based both on an explicit opcode identifier and on metadata encoded in the instruction. For example, a relative order of source register names may be used to decode the instruction. As an example, an instruction set may have a Branch Equal (BEQ) specifying two registers (r1 and r2) that store values that are compared for equality. An instruction set can provide a single opcode identifier for BEQ and a processor can determine whether to decode a particular instance of that opcode identifier as BEQ or another instruction, in dependence on an order of appearance of the source registers in that instance. For example, the BEQ opcode can be interpreted as a branch not equal, if a higher numbered register appears before a lower numbered register. Additional forms of metadata can include interpreting a constant included in an instruction, as well as determining equality of source registers, among other forms of metadata. |
| US09870223B2 |
Efficient detection of architecture related issues during the porting process
Systems, methods, and computer program products to perform an operation comprising identifying a first commit of a plurality of commits for a software project, wherein a source code of the first commit is executable in a first system architecture, computing a score for each commit in a first set of the plurality of commits, wherein each score reflects a likelihood of success in porting the source code of the respective commit from the first system architecture to a second system architecture, wherein a version of each commit in the first set of commits is between a version of the first commit and a current version of the software project, identifying one or more of the first set of commits based on the scores for each commit, and building the source code of the one or more of the first set of commits for execution on the second system architecture. |
| US09870219B1 |
Mechanisms for performing switch upgrades using remote containers
Mechanisms for switch upgrades using remote containers. An example system can export, to a server, a state of software processes associated with a first software container at the system. The system can generate a lightweight software container configured to forward traffic associated with the first software container to a second software container at the server, generated based on the state. The system can perform a switchover between the first software container and lightweight software container. The switchover can enable the lightweight software container to forward, to the second container, traffic associated with the first software container. The system can generate a fourth software container based on a snapshot of the second software container, and perform another switchover between the lightweight software container and fourth software container. The switchover can include enabling the fourth software container to handle traffic associated with the first software container, and disabling the lightweight software container. |
| US09870216B2 |
Application providing method including extracting and converting packaged application
An application providing method includes steps of, after registering a packaged application in which files included in an application are packaged, extracting the packaged application such that the packaged application is separated from other packaged applications for each host, converting, in accordance with an execution platform of the packaged application, the extracted content to content for a web browser, and, when an application acquisition request including a host name is received from the web browser, providing content that belongs to the host indicated by the host name included in the application acquisition request. |
| US09870212B2 |
Data loading device and data loading method for loading software into aircraft systems
An embodiment relates to a data loading device and a corresponding data loading method for loading software into aircraft systems, the data loading device incorporating a portable computer and a data storage device. The data loading device incorporating a switching device, the switching device having an external data connection. The switching device can switch connections between the computer, the data storage device and the data connection, the switching device having a first switching state which includes a connection between the computer and the data storage device. Furthermore, the switching device has a second switching state which includes a connection between the data storage device and the data connection. |
| US09870205B1 |
Storing logical units of program code generated using a dynamic programming notebook user interface
The programming notebook system, methods, and user interfaces described herein provide software developers with enhanced tools by which a programming notebook workflow and session history associated with code cells in a programming notebook may be tracked and maintained. As a developer progresses through a development workflow, the developer can select an option to save a program code card representing some or all of the program code cell inputs. A card editor user interface may present an aggregated listing of all program code the developer has provided across multiple code cells during the current session which the developer can edit, refine, and/or comment. The card editor may also allow the developer to add associated user interface code to display a UI component associated with the program code card, and allow the developer to add a description and tags for the card so that the card can be searched for and reused. |
| US09870204B2 |
Algorithm to achieve optimal layout of instruction tables for programmable network devices
A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate values based on input source code that when programmed into the configuration registers of the LDEs cause the LDEs to implement the functionality defined by the input source code. |
| US09870200B2 |
Decimal and binary floating point rounding
Arithmetic logic circuitry is provided for performing a floating point arithmetic add/subtract operation on first and second floating point numbers. The method includes: generating a guard digit for the first or second number by transforming the first and second numbers by a compressing function; determining a result depending on the arithmetic operation, a sum of the transformed floating point numbers, and first and second differences of the transformed floating point numbers, and determining a corresponding result plus one by additionally adding a value of one to the result; generating injection values for rounding the final result; generating injection carry values based on the transformed first and second numbers and the injection values; and selecting the final result from the result, the result plus one, and a least significant digit, based on the injection carry values and the end around carry signals. |
| US09870197B2 |
Input information support apparatus, method for supporting input information, and computer-readable recording medium
A buffer receives input from a plurality of objects. A display controller performs control to cause a display unit to display received pieces of input content of the objects in divided frames in time-series order of reception and display received input content additionally in a frame that displays past input content when a specific condition is satisfied. |
| US09870193B2 |
Systems, methods, and devices for animation on tiled displays
A display system is disclosed for animation of media objects on tiled displays. The display system can include a plurality of discrete display nodes and a control module configured to determine a graphical representation of a current state of a media object. The control module can be configured to determine a graphical representation of a future state of the media object. The control module can also be configured to determine a path area on the display nodes comprising a plurality of graphical representations of the media object during a change from the current state to the future state. The control module also can be configured to cause the display nodes overlapping with at least a portion of the path area to prepare to display the media object. |
| US09870188B2 |
Content visibility management
One embodiment provides a method, including: outputting, to a display device, first content; receiving, using a processor, an instruction to output second content to the display device; positioning one or more of the first content and the second content within the display device according to positioning data based on the first content; and displaying both of the first content and the second content on the display device. Other embodiments are described and claimed herein. |
| US09870185B2 |
Print manager server, print management method, and storage medium for predictive print preview of print jobs
A disclosed print manager server includes one or more processors and a memory configured to store a print management program. The processors execute the print management program to perform a process including analyzing an attribute of print data introduced, predicting a page of a preview image to be generated based on the analyzed attribute, a preview history of previous print jobs, and a preview prediction condition, generating the preview image of the predicted page, and providing the generated preview image in response to a request to display a preview. |
| US09870180B2 |
Print interface technology agnostic data loss prevention through print operations
Print operations are monitored and a DLP policy is applied, independently of the print interface technology used by applications that initiate print operations. A DLP component monitors for and detects print drivers being loaded into the print spooler. When a print driver is loaded, the print spooler creates a corresponding driver object, which is intercepted. The instantiated driver object creates multiple device objects to carry out various print functions. The device object print functions of interest are intercepted. Attempts to send text to the printer at a print driver level by intercepted device object functions are monitored, and application level context information is identified, such as the associated 0user. The DLP policy is applied to monitored attempts to send text to the printer at the print driver level, taking into account application level context information and the specific text of the monitored attempt. |
| US09870177B2 |
System and method for reliably persisting storage writes at high speed
A method for operating a device adapted to store information with high reliability includes determining a storage address for a data payload portion of a write request in accordance with a configuration of a communications interface coupled to the device, where the data payload is to be stored in mirroring groups of cache storage partitions of a plurality of cache storage modules. The method also includes generating a payload read request in accordance with the storage address, and prompting the communications interface to initiate the storing of the data payload, in parallel, in the mirroring groups in accordance with the payload read request. |
| US09870174B2 |
Multi-stage programming at a storage device using multiple instructions from a host
An apparatus includes a memory storing a group of pages of data. An interface of the apparatus is configured to send, to a data storage device (DSD) from a first command queue, a first instruction of instructions to store the group of pages to the DSD using a logical address corresponding to the group of pages. The interface is further configured to send, to the DSD from a second command queue, a second instruction of the instructions to write the group of pages to the DSD using the logical address. Sending a first copy of the group of pages in association with the first instruction and sending a second copy of the group of pages in association with the second instruction enables a multi-stage programming operation to be performed at the DSD without storing the group of pages at the DSD between stages of the multi-stage programming operation. |
| US09870164B2 |
Restore of secondary data using thread pooling
A system according to certain aspects may include a secondary storage controller computer configured to: in response to a first instruction to obtain a first secondary copy of a first data set from a secondary storage device(s), the first instruction associated with a first restore operation: instantiate a first restore thread on a processor of the secondary storage controller computer; using the first restore thread, retrieve the first secondary copy from the secondary storage device(s); and forward the retrieved first secondary copy to a primary storage subsystem for storage; and in response to a second instruction to obtain a second secondary copy of a second data set from the secondary storage device(s), the second instruction associated with a second restore operation: using the first restore thread, retrieve the second secondary copy from the secondary storage device(s); and forward the retrieved second secondary copy to the primary storage subsystem for storage. |
| US09870163B2 |
Double bandwidth algorithmic memory array
The present disclosure relates to memory structures and, more particularly, to double bandwidth algorithmic memory array structures and methods of use. The memory array includes: a plurality of memory banks each of which includes addressable storage units; a redundant array of independent disks (RAID) bank which stores parity bits corresponding to data written into any of the plurality of memory banks at a same address; and a plurality of XOR gates in which data written into any of the plurality of memory banks is cascaded therethrough to refresh the parity bits in the RAID bank. |
| US09870162B2 |
Method to virtualize PCIe controllers to support boot/hibernation/crash-dump from a spanned virtual disk
An information handling system recognizes PCIe-based RAID volumes, including RAID virtual disks spanning two or more NVMe storage drives, while performing boot, hibernation, and crash-dump functions, rather than treating each storage device and its corresponding storage controller separately. The information handling system may perform a two-tiered discovery/initialization process during which a storage protocol function driver detects and initializes physical storage controllers, a storage controller bus driver virtualizes all physical storage controllers of a particular storage protocol and exposes a single virtualized storage controller for the protocol. A virtual miniport driver may then detect RAID volumes associated with the virtual storage controller and initialize the detected RAID stack(s). |
| US09870158B2 |
Rack mountable computer system that includes microarray storage systems
Data communications within a rack mountable microarray system includes: sending, from a microarray controller to a communication fabric, a request for data, where the microarray controller is one of the plurality of microarray controllers housed within a drive bay of an enclosure, where the enclosure includes a plurality of storage devices, and where the microarray controller controls one or more of the storage devices; determining, by the communication fabric, a destination microarray controller from among the plurality of microarray controllers, where the destination microarray controller controls another one or more of the storage devices; sending, from the destination microarray controller to the communication fabric, the data specified by the request for data; and receiving, at the microarray controller from the communication fabric, the data specified by the request for data. |
| US09870157B2 |
Command balancing and interleaving for write and reads between front end and back end of solid state drive
A data storage device includes a non-volatile semiconductor storage device and a controller that is configured to perform interleaving of small reads with large reads and small writes with large writes. In the example of reads, the controller receives a sequence of read commands including a first read command having a read size larger than a read threshold size and a second read command having a read size smaller than the read threshold size, and issue first and second read requests in succession to read data of a predetermined size less than the read threshold size, from the non-volatile semiconductor storage device. The interleaving is achieved by issuing the first read request to execute the first read command and the second read request to execute the second read command. As a result of this interleaving, the second read command will have a chance to complete earlier than the first read command even though it was received by the controller later in time. |
| US09870156B2 |
Memory system and method of controlling memory system
According to one embodiment, a memory system is provided wherein an interruption generating unit generates an interruption signal for one or more commands executed by a transfer executing unit when an end number counter is greater than or equal to a first threshold. A transfer type conjecturing unit determines whether the transfer type of a first command to be executed after transmitting the interruption signal is sequential transfer or random transfer and sets the first threshold at a value different between when determining being the sequential transfer and when determining being the random transfer. |
| US09870150B2 |
Simultaneous image distribution and archiving
The present specification discloses a storage system for enabling the substantially concurrent storage and access of data that has three dimensional images processed to identify a presence of a threat item. The system includes a source of data, a temporary storage memory for receiving and temporarily storing the data, a long term storage, and multiple workstations adapted to display three dimensional images. The temporary storage memory is adapted to support multiple file input/output operations executing substantially concurrently, including the receiving of data, transmitting of data to workstations, and transmitting of data to long term storage. |
| US09870148B2 |
Configuration control system and configuration control method
An FPGA can be started up without system failure when a soft error occurs. A configuration control system includes: a first semiconductor chip which is capable of programming a logic circuit inside an LSI; a semiconductor memory which stores a plurality of pieces of circuit information of the first semiconductor chip; and a second semiconductor chip which, when controlling a configuration of the semiconductor chip using the circuit information stored in the semiconductor memory, if the configuration using any one of the plurality of pieces of circuit information fails, performs a re-configuration using another piece of circuit information among the plurality of pieces of circuit information. |
| US09870146B2 |
Information processing apparatus, program, and operation control method
There is provided an information processing apparatus including: a detection unit for detecting pressure applied by user input performed on a touch screen; a determination unit for determining which of two or more input states the user input belongs to, in accordance with the pressure detected by the detection unit; and an operation control unit for enabling or disabling a limitation imposed on operation with a user interface displayed on the touch screen, in accordance with the state of the user input determined by the determination unit. |
| US09870143B2 |
Handwriting recognition method, system and electronic device
In a handwriting recognition method applied in an electronic device with touch screen and display screen, a handwriting input area and a handwriting display area are shown on a touch screen when a handwriting command is given. The handwriting of a complete or partial word in the handwriting input area is recognized and displayed and a new handwriting input area can be added when a preset slide operation is applied that the tracing of a handwritten character collides with a boundary of the input area. Handwriting in the new handwriting input area is recognized and displayed and the content of the original handwriting input area and of the new handwriting input area are combined to form a complete word when the handwriting input is finished. The complete word is then displayed. |
| US09870140B2 |
Electronic device and launcher screen position identifying method
A launcher screen position identifying method obtains a set of coordinates of a reference point of each launcher screen and a set of coordinates of a reference point of a touch screen. The method calculates a distance difference between each launcher screen and the touch screen according to the set of coordinates of the reference point of each launcher screen and the set of coordinates of the reference point of the touch screen, and the method converts the distance difference between each launcher screen and the touch screen to a scalar value of the corresponding launcher screen. The scalar value is between negative one and positive one. The method further identifies a position relationship between each launcher screen and the touch screen according to the scalar value of the corresponding launcher screen. A related electronic device and a related non-transitory storage medium are provided. |
| US09870136B2 |
Controlling visualization of data by a dashboard widget
Display data in a data graphical user interface (GUI) on a display device and display, by a processor, a control GUI on the display device representing the data. The control GUI includes a range defining visual element, corresponding to a data value, that is moveable via input received by the control GUI and defines two ranges of the data. The processor displays indicia associated with the range defining visual element indicating the corresponding data value. The processor receives input from the control GUI indicating the range defining visual element has been moved. In response, the processor visually emphasizes data in the data GUI having data values in a selected one of the defined data range. |
| US09870135B2 |
Time segment user interface
A method operates a device that includes a display device, a user interface device, and a processor connected to the display device and the user interface device. The processor connected to the display device receives a user input defining a line on the display device; detects one or more direction changes in the received user input of the defined line; and defines a line segment according to the detected direction changes, where a length of the line segment is a distance between a start of the defined line and a first detected direction change. One or more processors segment a time period into multiple time segments, where each time segment corresponds in length to the defined line segment. The display device then displays the segmented time period on the defined line segment. |
| US09870133B2 |
Graphical user interface layout
Exemplary methods, apparatuses, and systems receive user input to move, resize, or add a first user interface object to a first location in a user interface window. The user interface window includes a second user interface object in a second location. In response to the user input, constraints are generated based upon the first location and the second location. The constraints define a size or a position of the first user interface object relative to the second user interface object. The first user interface object is displayed within the user interface according to the determined constraints. |
| US09870132B2 |
Application reporting in an application-selectable user interface
This document describes techniques for application reporting in an application-selectable user interface. These techniques permit a user to view reports for applications in a user interface through which these applications may be selected. By so doing, a user may quickly and easily determine which applications to select based on their respective reports and then select them or their content through the user interface. |
| US09870131B2 |
Exploring information by topic
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for exploring information by topic. One of the methods includes determining, from a user input, a topic; selecting a first node from a plurality of nodes, wherein the first node is a collection of data about the topic; providing, for display in a user interface, a first threadlet, wherein the first threadlet includes an instance of the first node and a projection menu that includes a respective link to each of one or more projections, and wherein each of the one or more projections includes one or more threadlets that are instances of nodes that share a relationship to the topic; receiving a user input selecting a particular projection from the one or more projections; and providing, for display in the user interface, a set of threadlets from the particular projection. |
| US09870130B2 |
Pushing a user interface to a remote device
A graphical user interface (“GUI”) for a third-party application can be presented on accessory device that has user input and display devices. The GUI can be defined and managed by a portable media device. The portable media device can define one or more GUI image types for the third-party application. The accessory can choose one of the pre-defined GUI image types and receive a remote GUI image that conforms to the selected GUI image type from the portable media device. Alternatively, the accessory can specify the layout and contents of the GUI image that it needs, and the portable media device can generate and send a GUI image according to the accessory's specification. |
| US09870126B2 |
Imaging apparatus
An imaging apparatus includes a first housing which has a light incident section in a vicinity of one end and which has an imaging optical system to which light from the light incident section is incident, a second housing which has a display section and which functions as a grip section, and a linking section which supports the first housing and the second housing so as to be able to rotate centering on a first axis, in which the first axis is provided in a vicinity of the other end which is an opposite side to the one end of the first housing, and light which includes a component which is orthogonal to the first axis is incident to the light incident section. |
| US09870120B2 |
Applications presentation method and system of mobile terminal
An applications presentation method and system is provided, the method and system including displaying, a map on a display when a map application is executed, the map scaled to a location range, searching via a processor for installed applications having location information corresponding to the location range among a plurality of applications stored in the mobile terminal, transmitting information identifying at least the location range and the installed applications to an application provision server, receiving information on non-installed applications having the location information corresponding to the location range from the application provision server, and displaying icons including icons of the installed applications and icons of the non-installed applications on the map. |
| US09870119B2 |
Computing apparatus and method for providing three-dimensional (3D) interaction
A computing apparatus for providing a three-dimensional (3D) interactive user experience (UX) is provided. The computing apparatus may include an object position estimator configured to calculate first coordinates recognized by a user as a position of a first point of an object in a stereoscopic image. The computing apparatus may include a pointing determiner configured to determine whether the user points to the first point based on the first coordinates and second coordinates, the second coordinates representing a pointing position of the user. |
| US09870115B2 |
User interfaces for multiple displays
A set of user interfaces for a data processing system that operates with two or more display devices coupled to the system. In one embodiment, in response to moving a first window between two displays, the first window is displayed, as it straddles the two displays, differently on the two displays. For example, while a reference point (e.g. a cursor) on the window remains on a first display, a first portion of the window on the first display is displayed normally while a second portion on the second display is displayed with more translucence (more transparency) than the first portion; when the references point crosses to the second display, the first portion becomes more translucent than the second portion. |
| US09870108B2 |
Display device including relatively movable display panel and touch panel
A display device that includes a display panel to display an image; a touch panel on the display panel; a spacer layer between the display panel and the touch panel; and a window attached onto the touch panel, wherein the display panel and the touch panel are relatively movable. |
| US09870103B2 |
Controller and method for controlling a capacitive touch screen or the like
A controller for a capacitive touch screen or the like includes a touch resolve subsystem and a processor. The touch resolve subsystem, when activated, measures a plurality of capacitance values using a plurality of input pins. The processor uses the plurality of capacitance values at each of a plurality of values of a parameter to create an interference map. |
| US09870095B2 |
Touch analog front end and touch sensor controller having the same
A touch analog front-end (AFE) and a touch sensor controller (TSC) are provided. The touch AFE includes a transmitter configured to charge a touch panel and a receiver configured to sense the touch panel. The receiver includes a charge-to-voltage (C2V) converter configured to convert an amount of change of capacitance received from the touch panel into a voltage signal, a filter configured to filter a noise from the voltage signal, resulting in a filtered voltage signal, an integrator configured to accumulate the filtered voltage signal, and a polarity detection circuit configured to monitor the filtered voltage signal and to control the integrator to invert a polarity of the filtered voltage signal when it is negative. |
| US09870087B2 |
Display driving apparatus and method for driving touch display panel
A display driving apparatus configured to drive a touch display panel is provided. The touch display panel includes gate drivers and scan lines. The display driving apparatus includes a driving controller. The driving controller provides clock signals to the gate drivers during a display period. The display period includes scan operation periods. The gate drivers drive the scan lines according to the clock signals during the scan operation periods. The driving controller further provides a clear signal and a pre-charge signal to at least one of the gate drivers to insert at least one touch sensing period between the scan operation periods, so that the touch display panel performs a touch sensing operation during the at least one touch sensing period. Furthermore, a method for driving the touch display panel is also provided. |
| US09870082B2 |
Pixel driver circuit, pixel driving method, pixel circuit and display device
The present disclosure provides a pixel driver circuit, a pixel driving method, a pixel circuit and a display device. The pixel driver circuit includes a touch element connection unit connected between a touch element and a second end of a storage capacitor, a diving control unit connected between a gate electrode of a driving transistor and the second end of the storage capacitor, a first power voltage application unit connected between a second electrode of the driving transistor and a first power line, a touch detection unit connected between a touch detection line and a first electrode of the driving transistor, and a threshold compensation control unit configured to receive a reference voltage and connected to the gate electrode of the driving transistor and the second end of the storage capacitor. |
| US09870080B2 |
Method, system, and device for controlling a cursor or user interface action as a function of touch and force input
A method for controlling a user interface using an indirect input device includes determining a first touchdown location of an input object, determining a first subsequent location of the input object, calculating a first direction and a first distance between the first touchdown location and the first subsequent location, and moving a cursor representation on a display in a second direction and at a velocity. The method further includes detecting a touchdown event of at least two input objects, determining a second touchdown location of the at least two input objects, determining a second subsequent location of the at least two input objects, calculating a third direction and a second distance from the second touchdown location and the second subsequent location, and modulating a user interface action in a fourth direction at a magnitude. |
| US09870079B2 |
Touch screen display unit and method for manufacturing same
A touch screen display unit according to the present invention comprises: an adhesive layer having adhesive properties on both surfaces thereof; a decoration layer displaying, on one surface of the adhesive layer, one or more among letters, designs, patterns and a metallic texture; and a window attached on the other surface of the adhesive layer so as to allow the decoration layer to be seen therethrough and to form an outer appearance of the display unit. |
| US09870075B2 |
Touch screen device
Disclosed is a touch screen device for accurately detecting a touch by using a touch pen without having a separate sensor provided in a touch panel. The touch screen device includes a touch screen including a plurality of touch electrodes, a touch driving circuit applying a touch electrode driving signal to the plurality of touch electrodes, and a touch pen receiving the touch electrode driving signal applied to the plurality of touch electrodes and transmitting a pen output signal, synchronized with the received touch electrode driving signal, to the touch screen. |
| US09870074B2 |
Control panel for aircraft
A control unit is provided with a selector and a plurality of value indicators. One of the value indicators provides a coarse indication of an existing value of an adjustable control quantity. The other value indicators are in another state, distinguishable from the value indicating state. A rotary adjustor provides a manual adjustment facility for a user. Selection of the selector puts the adjustable control quantity in an adjustment mode. In this adjustment mode, rotary actuation of the rotary adjustor allows adjustment of the control quantity. A new value of the control quantity is indicated by a change in the display states of the value indicators. |
| US09870071B2 |
Method and apparatus for user authentication
An apparatus and a method for managing security of a terminal which increases reliability of an electronic signature. The apparatus includes a controller for detecting coordinate values of input positions of an electronic pen as interruption information when the interruption is received, and a memory for storing the detected input positions as additional electronic signature information. |
| US09870066B2 |
Method of manufacturing an input device
Input device manufacture techniques are described. In one or more implementations, a plurality of layers of a key assembly is positioned in a fixture such that one or more projections of the fixture are disposed through one or more openings in each of the one or more layers. The positioned plurality of layers is secured to each other. |
| US09870061B2 |
Input apparatus, input method and computer-executable program
One embodiment provides a method, including: capturing, using a camera, an image of an object in contact with a hand of a user; determining, using a processor, that the hand of the user contacts the object; thereafter capturing, using the camera, controlling gesture input; detecting, within the controlling gesture input, a gesture that emulates use of a pointing device; and controlling an application running on an information handling device based on the controlling gesture input. Other aspects are described and claimed. |
| US09870060B2 |
Systems and methods for gaze-based media selection and editing
Systems are presented herein, which may be implemented in a wearable device. The system is designed to allow a user to edit media images captured with the wearable device. The system employs eye tracking data to control various editing functions, whether prior to the time of capture, during the time of capture, or after the time of capture. Also presented are methods for determining which sections or regions of media images may be of greater interest to a user or viewer. The method employs eye tracking data to assign saliency to captured media. In both the system and the method, eye tracking data may be combined with data from additional sensors in order to enhance operation. |
| US09870057B1 |
Gesture detection using an array of short-range communication devices
In general, techniques and systems for defining a gesture with a computing device using short-range communication are described. In one example, a method includes obtaining position information from an array of position devices using near-field communication (NFC) during a movement of the computing device with respect to the array, wherein the position information identifies unique positions within the array for each position device from which position information was obtained. The method may also include determining sequence information associated with the position information, wherein the sequence information is representative of an order in which the position information was obtained from each position device, and performing, by the computing device, an action based at least in part on the position information and the sequence information, wherein the position information and the sequence information are representative of a gesture input associated with the movement of the computing device. |
| US09870052B2 |
Hand-held controller with pressure-sensing switch for virtual-reality systems
There is provided a hand-held controller for a virtual-reality system. The hand-held controller includes a grip extending from a proximal end to a distal end and a first user-input key mounted at least in part on the grip. The first user-input key includes a casing depressible by one or more fingers of a user, and a switch coupled to the casing. The switch includes a sensor configured to detect and distinguish between a range of pressures applied to the casing. |
| US09870044B2 |
Method and apparatus for a zero voltage processor sleep state
Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory. |
| US09870043B2 |
Memory device of adaptively calibrating timing margin and integrated circuit including the same
An integrated circuit, a method of controlling an operation timing of a memory device, an application processor, and a power manager are provided. The application processor includes: a power manager configured to determine a first operating power level, from among a plurality of operating power levels, to determine a first timing margin corresponding to the first operating power level, to generate a first gray code signal indicating the first timing margin, and to output the first gray code signal; and a first memory device configured to adjust an operation timing according to the first timing margin indicated by the first gray code signal, wherein the power manager is configured to provide the first operating power level to the first memory device. |
| US09870038B2 |
Status-sensitive power observing system
The present invention relates to a status-sensitive power observing system (1) which enables to observe power consumption of interconnected embedded systems under different operating conditions together with the said operating condition information and form real-like power consumption models thereof. |
| US09870031B2 |
Hinge device applicable to soft display screen
A hinge device applicable to soft display screen ensures that the total amount of motion is uniformly distributed to every motional shaft. The hinge device includes multiple joint units and motional shafts. Each joint unit has a shaft fixing section and a shaft guide section assembled with the motional shafts. Each joint unit has a top portion, a first side and a second side. A rotary shaft is formed on the first side along the top portion. A socket is formed on the second side along the top portion. A (soft) display screen is disposed on the top portions of the joint units. The shaft guide section is defined with a first position and a second position. When a user opens/closes the display screen, the rotary shafts serve as rotational fulcrums and the motional shafts are rotatably movable between the first and second positions of the shaft guide section. |
| US09870023B2 |
Display panel and method of manufacturing the same
A method of manufacturing a display panel, including providing a plurality of display substrates spaced apart from each other by a predetermined area disposed therebetween when viewed in a plan view, each of the display substrates including a display area, on which an image is displayed, and each of the display substrates being flexible; attaching a first film onto the display substrates to overlap with the display substrates; attaching a second film onto the first film; and substantially and simultaneously cutting the first and second films along a cutting line defined in an area overlapping with the predetermined area. |
| US09870021B2 |
Magnetic manual user interface devices
Various finger tip controlled manual interface devices that can be used as inputs to personal computers, electromechanical systems and video game consoles utilize concentrically arranged magnets. The polarities of the magnets are oriented to provide restoration forces on a one of the magnets to bias it toward a neutral position. A magnetic sensor including a plurality of sensing elements such as Hall effect devices generates output signals representative of direction and amount of movement of the magnet that is biased to the neutral position. |
| US09870019B2 |
Pedal cover assembly and methods of use and manufacture thereof
Some embodiments relate to a cover assembly for use with a vehicular plate member. The cover assembly includes a pad that is over-molded to a resilient member. The pad includes a primary contact member having an exterior surface with a relatively high coefficient of friction and disposed to be frictionally engagable with the vehicle operator's foot, the primary contact member being abradable through frictional engagement with the operator's foot. The pad can also include a connector member that is configured for attachment to the plate member. The cover assembly can also include a secondary contact member between the exterior surface of the primary contact member and the plate member. The secondary contact member is disposed completely below the primary contact member and thereby hidden from view prior to abrasion of the primary contact member, but disposed to frictionally engage the operator's foot subsequent to abrasion of the primary contact member. |
| US09870015B2 |
Energy control device and energy control system equipped with the energy control device
An energy control device adjusts an amount of energy consumed by mechanical equipment placed at a property. The energy control device includes a first control unit and a second control unit. The first control unit executes a first adjustment control during a prescribed adjustment period. The first adjustment control adjusts an amount of energy consumed by the mechanical equipment in order to respond to a prescribed event. The second control unit executes a second adjustment control separate from the first adjustment control during a non-adjustment period after the adjustment period. |
| US09870012B2 |
Digitally phase locked low dropout regulator apparatus and system using ring oscillators
Described is an apparatus which comprises: a first oscillator to generate a first clock signal a second oscillator to generate a second clock signal; a phase frequency detector to detect phase difference between the first and second clock signals, and to generate a phase difference; and an output stage, coupled to a load, to generate a power supply for the load according to the phase difference. |
| US09870004B2 |
High authority stability and control augmentation system
A method of increasing the control authority of redundant stability and control augmentation system (SCAS) actuators by utilizing feedback between systems such that one system may compensate for the position of a failed actuator of the other system. Each system uses an appropriate combination of reliable and unreliable inputs such that unreliable inputs cannot inappropriately utilize the increased authority. Each system may reconfigure itself when the other system actuator fails at certain positions so that the pilot or other upstream input maintains sufficient control authority of the aircraft. |
| US09869999B2 |
Robotic golf caddy
A autonomous robotic golf caddy which is capable of following a portable receiver at a pre-determined distance, and which is capable of sensing a potential impending collision with an object in its path and stop prior to said potential impending collision. |
| US09869993B2 |
System and method for monitoring and/or diagnosing operation of a production line of an industrial plant
A system and method monitor and/or diagnose the operation of a production line of an industrial plant which is controlled by an automation system. The system includes a remote data processing server, which is installed outside of the industrial plant. The remote data processing server is configured to receive a digital input signal reflecting at least one control input signal and a digital output signal reflecting a second operational state, to determine at least first and second modeled states corresponding to the at least first and second operational states, respectively, by inputting the digital input and the digital output signals to a digital observer model of the production line and the automation system and by processing the digital observer model, and to forward the first and second modeled states to an output interface from where they can be accessed by modeling and/or diagnosing modules. |
| US09869989B2 |
Numerical controller
A numerical controller is configured to move a tool in synchronism with rotation of a workpiece, thereby controlling a machine tool configured to perform thread cutting, and comprises a cutting amount variation setting unit for previously setting the size of a variation of a cutting amount during the thread cutting. The cutting amount variation setting unit periodically changes the cutting amount based on a preset variation during the thread cutting. |