| Document | Document Title |
|---|---|
| US09787667B2 |
Attested sensor data reporting
A apparatus and a method for attested sensor data reporting, wherein a challenge is received from an online service; sensor data is read; and a sensor data signature based on the sensor data is created and sent to the online service. |
| US09787666B2 |
Single sign-on processing for associated mobile applications
Systems, methods and computer-readable media are disclosed for performing single sign-on processing between associated mobile applications. The single sign-on processing may include processing to generate an interaction session between a user and a back-end server associated with a mobile application based at least in part on one or more existing interaction sessions between the user and one or more back-end servers associated with one or more other mobile applications. In order to establish an interaction session with an associated back-end server, a mobile application may leverage existing interaction sessions that have already been established in connection with the launching of other associated mobile applications. |
| US09787660B2 |
Method, apparatus, and system for providing a security check
Embodiments of the present application relate to a method, apparatus, and system for providing a security check. The method includes receiving a security verification request sent from a terminal, obtaining first verification element information based at least in part on the security verification request, generating a digital object unique identifier based at least in part on the first verification element information, sending the digital object unique identifier to the terminal, receiving second verification element information from the terminal, and in the event that the first verification element information and the second verification element information are consistent, sending security check pass information to the terminal. |
| US09787658B2 |
Login system based on server, login server, and verification method thereof
A method performed by a login server with memory and one or more processors are described. The method includes receiving a login request from a computer system; determining whether an identity of the computer system matches a preset standard; and, in accordance with a determination that the identity of the computer system does not match the preset standard, denying the login request. The login server and its components, and a computer readable storage medium storing one or more programs for execution by one or more processors of the login server are also described. |
| US09787654B2 |
Resolving authenticating issues with a second device
Authenticating issues involving the re-authenticating of a first device that was previously authenticated are resolved by use of a second device which receives a notification of the failed authentication. The second device sends a response to the notification which is operable to facilitate re-authentication of the primary device and without requiring the user to provide credentials at the first device prior to obtaining the re-authentication at the primary device and/or without requiring the primary device to obtain a code to be entered into the secondary device and/or prior to the primary device being notified of a failure condition associated with the primary device. |
| US09787650B2 |
System and method for multiparty billing of network services
A scalable, distributed system and method for communicating originating network information for multiparty billing of network services, with authentication of originating network attributes, having particular application when value added services are provided to subscribers of other networks, for which price is determined at the terminating end. An originating network attribute, e.g. an originating network identification, is associated with a private-public key pair of the originating network operator, a service request is generated comprising an network attribute pair containing a clear text attribute and an encrypted attribute, encrypted with the private-key of the originating network operator. Authorized parties having a billing relationship with the originating network operator have access to public keys for decryption and verification the originating network identification prior to forwarding of the service request for completion and billing. An attribute pair may be provided as an extension of known service request protocols, and the network attribute may optionally include originating network identification, subscriber information, and other information associated with the service request. |
| US09787643B2 |
Transport layer security latency mitigation
Some embodiments include a method of utilizing a proxy device to mitigate latency related to a transport layer security (TLS) handshake protocol. The proxy device can be an untrusted proxy of a server or a client. The proxy device can negotiate cipher suites on behalf of its principal (e.g., the server or the server) without storing private keys of its principal. The use of the proxy device can reduce a typical two round-trips taken between the server and the client into a single round-trip. |
| US09787640B1 |
Using hypergraphs to determine suspicious user activities
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for detecting suspicious user activities. One of the methods includes generating hypergraphs, wherein the hypergraphs include nodes corresponding to feature profiles and edges between particular nodes representing a measure of similarity between nodes; using the generated hypergraphs to detect suspicious graph nodes; and using the suspicious graph nodes to detect malicious user communities. |
| US09787638B1 |
Filtering data using malicious reference information
A device may receive data from a first endpoint device. The device may identify a network protocol. The network protocol may be associated with receiving the data. The device may identify a format. The format may be associated with encoding textual information in the data. The device may determine, based on the format and the network protocol, text in the data. The device may determine whether the text includes a reference from a plurality of references. The plurality of references may identify addresses associated with malicious devices. The device may selectively forward the data to a second endpoint device based on determining whether the text includes the reference. |
| US09787637B2 |
Secure analysis application for accessing web resources
Embodiments described herein may be directed to systems, methods, apparatuses, devices, computer program products, computer-executable instructions, and/or applications for securely and anonymously accessing web resources and customizable attribution of identity. In accordance with the present disclosure, a user may inspect and analyze a webpage as well as the underlying source code from an “arm's length” using a secure analysis application to prevent exposure on the user's local machine. The secure analysis application may provide increased flexibility in masking and/or modifying the user's digital persona to external websites. Additionally, the secure analysis application may be integrated with a translation service to translate textual web content without the web content provider being alerted that a translation is taking place. |
| US09787631B2 |
Unified and consistent multimodal communication framework
A unified communication framework in which multiple users communicate using multiple modes. Conversations are kept consistent across users' devices. A backend maintains the true and authoritative version of the conversation within the communication framework. |
| US09787629B2 |
Tagging posted content in a social networking system with media information
A social networking system allows a user to insert media information into content posted by the user, where the media information identifies a media item that the user is consuming while composing the posted content. When a user of a social networking system composes content via a composer interface, the user may select an option on the composer interface to record audio using a microphone on the user's device. A media item is identified from the recorded audio and information about the identified media item is added to the user's posted content. The system may also update information about the identified media item and the composing user. |
| US09787625B2 |
Method and apparatus for managing communication exchanges
A system that incorporates teachings of the present disclosure may include, for example, obtaining a message and an importance rating for the message where the importance rating is determined by a second communications management agent of a server based on an analysis of content of the message. The system can access rating feedback information associated with the second communications management agent. A rating accuracy for the importance rating of the particular message can be determined based on the rating feedback information, and the method of providing the message to the intended recipient can be adjusted based on the determined accuracy. Other embodiments are disclosed. |
| US09787623B2 |
Automatically providing a communication based on location information for a user of a social networking system
Systems and methods for automatically locating web-based social network members are provided. According to one embodiment, contact content including an associated GPS identifier and status for web-based social network members located at or near the same location automatically appears on a GPS-enabled device. A further exemplary system includes a GPS-enabled device configured to receive a GPS identifier and a status representing a location and a current state for a web-based social network member, a processing module that associates the received GPS-identifier and the received status, and a communications module that sends the associated GPS-identifier and status to a server comprising a web-based social network database. Contact content in a web-based social network database record in the web-based social network database is updated to include the associated GPS identifier and status for the web-based social network member. |
| US09787622B2 |
System and method providing proximity based notifications to electronic devices
System, method and electronic device providing proximity based communication and notification are disclosed. Presence of the electronic device is detected in a pre-defined area according to a detection methodology. The electronic device is then engaged according to an availability of identification details of the electronic device. The electronic device receives one time authentication request to collect the business identity and map it with the network identity. The business identity of the electronic device is verified and contact details of the electronic device are obtained. Subsequently when the electronic device enters the proximity range of a WiFi network, the system identifies its presence. The system identifies the contact details of the device based on the mapping of the network identity and business identity of the electronic device. The system sends multi-mode message communications to the electronic device based on defined proximity rules. The proximity rules can also be defined in such a way that the system sends multi-mode message communications to the electronic devices of the business. |
| US09787615B2 |
Apparatus, systems, and methods for network interactions
A network interaction system may comprise a terminal device, an instant messaging server, and a public account server. The terminal device may be configured to receive information from the public account server via the instant messaging server. The instant messaging server may be configured to receive from the terminal device an information operation request associated with information from the public account server. Then the instant messaging server may send a notification associated with the information operation request to the public account server and send a response to the information operation request to the terminal device. The public account server may be configured to receive from the instant messaging server the notification and determine an information transmission strategy for the terminal device in accordance with the information operation request. |
| US09787611B2 |
Establishing and managing alternative networks for high quality of service communications
Methods and systems are provided. Exemplary methods may include: providing a first data packet to a first interface, the first data packet including a first address and being received from a computing device, the computing device being at a premises and coupled to a third interface, the first interface coupled to a first broadband connection received at the premises, the first broadband connection being coupled to a service using a first data network; determining at least one second data packet to be received at the first interface from the service is lost or delayed; supplying a second address to the computing device for communications with the service, in response to the determining; receiving from the computing device a third data packet including the second address; modifying the third data packet including replacing the second address with the first address; and giving the modified third data packet to a second interface. |
| US09787610B2 |
Active multi-path network redundancy with performance monitoring
A receiving network node (210) configured to select from received packets differing by time of initial transmission from a sending network node (230), and accepting for transmission, based on initial transmission time, the selected packets to an application layer (740). An internetworked processor node configured to: (a) read a sequence number and an originator identifier of a received packet message (810); (b) compare a stored highest sequence number associated with the originator identifier with the received packet sequence number (820); (c) if the received packet sequence number is less than or equal to the stored highest sequence number associated with the originator identifier, then discard (840) the received packet; and (d) if the received packet sequence number is greater than the stored highest sequence number associated with the originator identifier, then deliver (860) the message of the received packet to an application based on an upper layer protocol. |
| US09787607B2 |
End-to-end provisioning of Ethernet Virtual Circuits
Methods and systems are disclosed for providing a signaling protocol to enable a bi-directional point-to-point Ethernet Virtual Circuits (EVC) to be configured between any two network elements, as part of a network infrastructure. The bi-directional EVC is established by configuration of a source network element and a destination network element, and defines a bi-directional data path across the network infrastructure therebetween. The EVC may include one or more network elements over which the data path may traverse. The methods and systems disclosed may be applied to linear, ring and mesh network topologies. |
| US09787606B2 |
Inline network switch having serial ports for out-of-band serial console access
Systems, methods and apparatus regarding network configuration and network switches including an in-line Network Console Access (NETCONA) Device having a NETCONA Management Module, a NETCONA WAN-side Port, a NETCONA LAN-side Port, and at least one NETCONA Serial Console Access Port. The NETCONA Device may share a single IP address for “out-of-band” access to network appliances at a network edge point. The NETCONA Device uses packet forwarding to transparently transfer data between a WAN and a LAN. Data packets having console access information are forwarded to the NETCONA Management Module for processing. An exemplary network system includes an in-line NETCONA Device and at least one Network Appliance; wherein the Network Appliance includes a Network Appliance Serial Console Access Port; and wherein the NETCONA Serial Console Access Port is coupled with the Network Appliance Serial Console Access Port to enable Serial Console Access. Numerous other aspects are provided. |
| US09787604B2 |
Cloud computing infrastructure, method and application
The present invention discloses a cloud computing infrastructure having a rights management device, which is designed to manage operating rights for at least one application which can be executed in the cloud computing infrastructure for the purpose of controlling the operation of the at least one application in the cloud computing infrastructure, to evaluate the managed operating rights with respect to execution of the at least one application and to output an execution enable on the basis of the evaluation of the operating rights, and having an execution device which is designed to execute the at least one application in the cloud computing infrastructure on the basis of the output execution enable. The present invention also discloses a method for operating at least one application in a cloud computing infrastructure and an application for execution in a cloud computing infrastructure. |
| US09787595B2 |
Evolved node-B and mobility management entity and user equipment and methods for supporting attended and unattended services
Embodiments of an Evolved Node-B (eNB) to support packet-switched (PS) services according to EPS bearers are disclosed herein. The eNB may receive an EPS bearer setup message from an MME for an establishment of an EPS bearer for a PS service between a User Equipment (UE) and a PGW. The EPS bearer setup message may include an attention indicator for the PS service that indicates whether traffic for the PS service is attended or unattended at the UE. The eNB may further transmit traffic packets to and receive traffic packets from the UE 102 as part of the PS service. In addition, the eNB may use the attention indicator as part of congestion control in the network. |
| US09787593B2 |
Performing path-oriented systems management
A method is disclosed for transmitting system management requests to computer systems along a network path using a network control protocol, such as RSVP. For example, an originating node may send a single system management request along a path to a destination node using a network control protocol. Each computer system along the network path may analyze the network control protocol message to determine whether the message contains a system management request. If a system management request is found in the message, the computer system may perform the system management function identified in the request, and respond to it. |
| US09787589B2 |
Filtering of unsolicited incoming packets to electronic devices
The disclosed embodiments provide a system that processes incoming network packets to an electronic device. The system includes an analysis apparatus that maintains a list of accepted incoming packet attributes for the electronic device based on outgoing packets from the electronic device. The system also includes a filtering apparatus that compares a first set of header information for an incoming packet to the list. If the first set of header information is not included in the list, the filtering apparatus discards the incoming packet. If the first set of header information is included in the list, the filtering apparatus enables subsequent processing of the incoming packet on the electronic device by, for example, providing the incoming packet to a transport-layer mechanism on the electronic device for subsequent processing of the incoming packet by the transport-layer mechanism. |
| US09787587B2 |
Method and apparatus for bidirectional message routing between services running on different network nodes
Methods and systems are disclosed for secure bi-directional message routing between services running on a different nodes in a computer cluster. According to some embodiments, a multi-tenant computer cluster is accessed online via a controller. The controller, acting as central management system, may establish secure independent connections with each of the many nodes. Messages from the controller to any given node, and vice versa, are wrapped in a routing envelope and transferred over an independent and secure virtual private network tunnel. This allows the plurality of nodes to be centrally managed and utilized as a cluster while not being allowed to communicate with each other. |
| US09787585B2 |
Distributed storage system, control apparatus, client terminal, load balancing method and program
A distributed storage system includes: a plurality of servers that store data that is associated with key information, respectively; a packet forwarding apparatus that, on receipt of a new packet that contains the key information and is addressed to one of the plurality of servers, requests a control apparatus to decide a forwarding destination from among the plurality of servers; and the control apparatus. The control apparatus includes: a forwarding destination selection section that decides a forwarding destination of the packet based on key information in a header part of the packet; and an entry setting section that sets, in a packet forwarding apparatus(es) on a path to the forwarding destination, a flow entry for forwarding a subsequent packet(s) with same key information to the forwarding destination. The packet forwarding apparatus(es) forwards a packet(s) with the same key information to the forwarding destination using the set flow entry. |
| US09787584B2 |
Data transmission reservation method and apparatus, data reception method and apparatus, and data transmission and reception system in receiver-initiated asynchronous medium access control protocol
According to the present invention, there is disclosed a method for reserving data transmission from a transmitting node to a receiving node in a receiver-initiated asynchronous MAC (Medium Access Control) protocol. The method includes receiving a base beacon frame from the receiving node and when transmitting a data frame to the receiving node, transmitting the data frame, with a reserved field value set in a portion of a header of the data frame. |
| US09787579B2 |
Application controlled path selection based on type-of-service
Some embodiments override network or router level path selection with application or server controlled path selection by repurposing the type-of-service (ToS) or differentiated services header field. A mapping table maps different ToS values to different available transit provider paths to a particular destination. A server generating a packet to the destination selects one of the available paths according to any of load balanced, failover, or performance optimization criteria. The server sets the packet header ToS field with the value assigned to the selected path. A router operating in the same network as the server is configured with policy based routing rules that similarly map the ToS values to different transit provider paths to the particular destination network. Upon receiving the server generated packet, the router routes the packet to the destination network through the transit provider path identified in the packet header by the server set ToS value. |
| US09787577B2 |
Method and apparatus for optimal, scale independent failover redundancy infrastructure
Exemplary methods performed by a first network device (ND) include generating first and second prefix entries associating incoming Internet Protocol (IP) traffic to first and second data structures (DSs), respectively. Generating the first DS includes generating a first proxy including forwarding information causing incoming IP traffic to be forwarded to a second ND, and generating a second proxy referencing a third DS. Generating the second DS includes generating a first proxy including forwarding information causing incoming IP traffic to be forwarded to the second ND, and generating a second proxy referencing the third DS. The methods include generating the third DS including forwarding information causing the incoming IP traffic to be forwarded to a third ND, the third DS further including first state information indicating whether the forwarding information included in the first proxies of the first and second DSs should be used for forwarding the incoming IP traffic. |
| US09787573B2 |
Fast convergence on link failure in multi-homed Ethernet virtual private networks
Techniques are described for providing fast convergence in the event of a link failure in an all-active multi-homed Ethernet virtual private network. A provide edge (PE) network device may pre-configure an interface next hop and secondary next hops. The secondary next hops may be logical links to other PE network devices in the same Ethernet segment. In the event of a link failure in the interface next hop between the PE network device and a customer edge (CE) network device, the PE network device may be configured to forward data traffic to the CE network device using the secondary next hops. In the event of a link failure between the PE network device and a core network, the PE network device may be configured to send an out-of-service message to the CE network device that instructs the CE network device to stop sending traffic to the PE network device. |
| US09787572B2 |
Conflict avoidant traffic routing in a network environment
An example method for facilitating conflict avoidant traffic routing in a network environment is provided and includes detecting, at a network element, an intent conflict at a peer network element in a network, and changing a forwarding decision at the network element to steer traffic around the conflicted peer network element. The intent conflict refers to an incompatibility between an asserted intent associated with the traffic and an implemented intent associated with the traffic. In specific embodiments, the detecting includes mounting rules from the peer network element into the network element, and analyzing the mounted rules to determine intent conflict. In some embodiments, a central controller in the network deploys one or more intentlets on a plurality of network elements in the network according to corresponding intent deployment parameters. |
| US09787570B2 |
Dynamic feature peer network for application flows
A device receives packets of a traffic flow, and inspects one or more of the packets of the traffic flow. The device determines, based on the inspection of the one or more packets, a service graph of feature peers for the packets of the traffic flow. The feature peers are associated with a network, and the service graph includes an ordered set of the feature peers. The device configures network devices of the network with the service graph, and the network devices forward the packets of the traffic flow to the feature peers based on the service graph and without changing the traffic flow. |
| US09787568B2 |
Physiological test credit method
A physiological test credit method determines if test credits are available to the monitor and checks if a Wi-Fi connection is available. If test credits are less than a test credit threshold, the monitor connects to a test credit server, processes server commands so as to download test credits and disconnects from the server. In various embodiments, the monitor is challenged to break a server code, the server is challenged to break a monitor code. The server validates monitor serial codes, and saves monitor configuration parameters. |
| US09787567B1 |
Systems and methods for network traffic monitoring
A packet forwarding network may include switches that forward network traffic between end hosts and network tap devices that forward copied network traffic to an analysis network formed from client switches that are controlled by a controller. Network analysis devices and network service devices may be coupled to the client switches at interfaces of the analysis network. The controller may receive one or more network policies from a network administrator. A network policy may identify ingress interfaces, egress interfaces, matching rules, packet manipulation services to be performed. The controller may control the client switches to generate network paths that forward network packets that match the matching rules from the ingress interfaces to the egress interfaces through service devices that perform the services of the list. The controller may generate network paths for network policies based on network topology information and/or current network conditions maintained at the controller. |
| US09787563B2 |
Network interface and detection module to enable network communication within information handling systems
A network interface module can include a housing including a first cavity configured to receive a first network plug having a first dimension. The housing also includes a second cavity within the first cavity, and configured to receive a second network plug having a second dimension that is less than the first dimension. The network interface module can also include a network detection circuit operatively connected to a first terminal within the housing. |
| US09787556B2 |
Apparatus, system, and method for enhanced monitoring, searching, and visualization of network data
A system for monitoring and visualization of network data includes a plurality of first devices and a second device coupled to the plurality of first devices over a network. Each first device is associated with corresponding ones of a plurality of ports. Each first device is configured to determine network traffic analysis information associated with a characteristic of network data traversing each of the ports, and to push the network traffic analysis information across a network independent of a solicitation from the network. The second device is configured to generate a map of the network including a visual indicator based on the network traffic analysis information, to receive an update of the network traffic analysis information from at least one of the first devices, and to refresh the visual indicator in real time to reflect the update of the network traffic analysis information. |
| US09787555B2 |
Apparatus, system, and method of activation control, and medium storing activation control program
An activation control apparatus stores, in a memory, first association information that associates, for each one of a plurality of applications, application identification information for identifying an application with terminal identification information for identifying a communication terminal permitted to debug the application. In response to an activation request for activating a first application from a first communication terminal, the activation control apparatus determines whether the first communication terminal is provided with a debugger. When the first communication terminal is provided with a debugger, the activation control apparatus further determines whether the first communication terminal is permitted to debug the first application using the first association information, and rejects the activation request when the first communication terminal is not permitted to debug the application. When the first communication terminal is not provided with a debugger, the activation control apparatus accepts the activation request. |
| US09787554B2 |
Information-processing apparatus and output adjustment method
The present invention accumulates received information in a buffer, monitors a buffer accumulation amount, which is an amount of information accumulated in the buffer, adjusts a clock frequency used to output the information from the buffer based on the monitored buffer accumulation amount, and outputs the information from the buffer in accordance with the adjusted clock frequency. |
| US09787552B2 |
Operation process creation program, operation process creation method, and information processing device
A non-transitory computer-readable recording medium stores an operation process creation program that causes a computer to execute a process, the process including extracting a candidate operation manipulation component to be combined with an operation process following an operation manipulation component that has been determined to be arranged, when creating the operation process by arranging a plurality of the operation manipulation components on a screen, the candidate being extracted based on previously set relevance information indicating relevance between operation manipulation components and usage frequency information indicating usage frequencies of operation manipulation components in past instances of creating the operation processes; and displaying the extracted candidate operation manipulation component on the screen, by combining the extracted candidate operation manipulation component with the operation manipulation component that has been determined to be arranged. |
| US09787551B2 |
Responsibility-based request processing
A method is operable in a network comprising multiple service endpoints, the service endpoints running on a plurality of devices, wherein the multiple service endpoints form one or more sub-clusters. The method includes defining a group from an arbitrary set of nodes comprising service instances across the machines of the one or more sub-clusters, wherein each node in the group assumes one or more discrete responsibilities involved in processing of a request across the group. In response to a request made at a node the group, the service type of the request is dynamically determined; and, based on the type of the request, one or more nodes in the group are selected to be responsible for processing the request. |
| US09787543B2 |
Communication apparatus and communication method
A communication apparatus includes a physical layer circuit that functions as a physical layer for communication with a communication destination and can perform an automatic negotiation with the communication destination for determining communication setting information representing physical setting of communication with the communication destination, a nonvolatile storage unit, and a control unit that controls the physical layer circuit. In one operating mode, the control unit controls the physical layer circuit such that an automatic negotiation with the communication destination is performed and communication setting information determined by the automatic negotiation in the storage unit is written. In another operating mode, the control unit writes the communication setting information stored in the storage unit in the physical layer circuit. |
| US09787534B1 |
System, method, and computer program for generating event tests associated with a testing project
A system, method, and computer program product are provided for generating event tests associated with a testing project. In use, an indication of one or more event types is received for creating one or more events on which to perform event testing associated with at least one testing project. Additionally, an indication of one or more parameters associated with the one or more events on which to perform the event testing is received. Further, one or more event files are generated for testing the one or more events based on the one or more event types and the one or more parameters. In addition, the one or more event files are sent to one or more event processing systems for testing the one or more events, the testing of the one or more events including storing information associated with all faults resulting from the testing of the one or more events in a risky events repository that is capable of being utilized to generate testing rules for additional testing projects. Moreover, at least one report including information associated with a result of testing the one or more events is generated. |
| US09787533B2 |
Obstruction determination device
A obstruction determination process by a program stored in a recording medium comprises (i) in cases in which a connection data has been received from a plurality of transfer devices connected to a non-transmitting transfer device which is not transmitting the connection data, identifying a non-transmitting transfer device transfer path on which the non-transmitting transfer device is positioned; and (ii) determining for each of the identified transfer paths whether or not an obstruction has occurred on the identified transfer path, and in cases in which the identified transfer path is the non-transmitting transfer device transfer path identified, employing the transfer volume data that has been received from another transfer device positioned on the non-transmitting transfer device transfer path as the transfer volume data of the non-transmitting transfer device to determine whether or not an obstruction has occurred on the identified transfer path. |
| US09787528B2 |
Instantiating resources of an IT-service
Instantiating a resource of an IT-service includes analyzing a service model of the IT-service where the service model includes a node representing a resource for providing the IT-service. A resource type of the resource being indicated by the node is determined, and a service provider catalog is evaluated to determine a resource manager operable to instantiate the resource and an address of the resource manager. A request is sent to the address of the resource manager for a description of a resource-manager-specific API of the resource manager. Upon receipt of the requested description, at least one abstract method for instantiating the resource is overridden with a resource-manager specific method of the resource-manager-specific API, and the resource-manager specific method for instantiating the resource represented by the node is executed. |
| US09787524B1 |
Fibre channel virtual host bus adapter
Methods and devices to allow multiple operating system images to simultaneously access a Fiber Channel fabric through a common host bus adapter port are described. For each requesting operating system image, a fabric switch maintains a unique port identifier value and a unique fabric channel address so that each operating system image may be uniquely identified across the fabric. |
| US09787523B2 |
Managing data in a data queue including synchronization of media on multiple devices
A method of managing data in a data queue includes analyzing media currently being played, or to be played by a first computing device functioning as a leader to identify an offset into the media and a timestamp corresponding to the offset. A buffer duration is calculated that corresponds to an amount of time that the data queue takes to output data currently in the data queue. The media is played at the leader and a second computing device functioning as a follower, in a substantially synchronized manner, by inputting data to the data queue at a specified time based on the calculated buffer duration, the offset, and the timestamp. |
| US09787521B1 |
Concurrent loading of session-based information
Techniques are described for determining non-session-related content of a web page through operations that are performed at least partly concurrently with operations for determining session-related content for the page. Session data may be stored on, or accessed through, a centralized session data service that is in communication with a plurality of content servers configured to serve web pages. To mitigate latency incurred through network communications between the content server(s) and the session data service, the generation or retrieval of non-session-related content may begin after the receipt of a page request in a session, and may proceed at least partly in parallel with operations to validate the session identifier, retrieve session data associated with the session identifier, or determine session-related content for the page based on the session data. |
| US09787517B2 |
Coarse timing
A coarse timing method for a communication system is provided. The coarse timing method may include: calculating timing metric values for received signal samples using a self-correlation based timing metric function; calculating average timing metric values based on previous timing metric values; and determining whether there is a data frame based on the timing metric values and the average timing metric values. |
| US09787516B2 |
Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals
A method and an apparatus for receiving broadcast signals thereof are disclosed. The apparatus for receiving broadcast signals, the apparatus comprises a receiver to receive the broadcast signals, a demodulator to perform demodulation on the received broadcast signals by an OFDM (Orthogonal Frequency Division Multiplex) scheme, a frequency de-interleaver to frequency de-interleave the demodulated broadcast signals by using a different interleaving sequence, wherein the different interleaving sequence is used for data corresponding to an OFDM symbol pair or data corresponding to an OFDM symbol according to an FFT size of the demodulation, a frame parser to parse at least one signal frame from the frequency de-interleaved broadcast signals and a decoder to decode service data in the parsed at least one signal frame. |
| US09787511B2 |
Methods, devices and systems for receiving and decoding a signal in the presence of noise using slices and warping
A method may comprise receiving and sampling a signal. The signal may encode a data packet. A slice may be generated and stored comprising a pair of values for each of a selected number of samples of the signal representing a correlation of the signal to reference functions in the receiver. The presence of the data packet may then be detected and the detected packet decoded from the stored slices. The generating and storing slices may be carried out as the received signal is sampled. The sampled values of the signal may be discarded as the slices are generated and stored. The slice representation of the signal can be manipulated to generate filters with flexible bandwidth and center frequency. |
| US09787505B2 |
Tap embedded data receiver and data transmission system having the same
A data receiver includes a plurality of samplers, each of the samplers amplifies a difference between a first reference voltage and an input voltage and amplifies a difference between a second reference voltage and the input voltage. Operational paths of the samplers are differently controlled according to a level of second data corresponding to the second reference voltage, and first data corresponding to the first reference voltage is past data preceding current data and the second data is past data preceding the first data in the sampler. |
| US09787504B2 |
Channel estimation method and apparatus for cooperative communication in a cellular mobile communication system
A channel estimation method and apparatus are provided for a terminal in a cellular mobile communication system including a plurality of base stations. The method includes maintaining a maximum number of CSI processes supported by the UE; receiving CSI process report information; determining a number of CSI to be updated based on the maximum number of CSI processes supported by the UE; generating at least one CSI report based on the determined number of CSI to be updated; and transmitting the at least one CIS report to an evolved Node B (eNB). |
| US09787499B2 |
Private alias endpoints for isolated virtual networks
In accordance with a designation of a private alias endpoint as a routing target for traffic directed to a service from within an isolated virtual network of a provider network, a tunneling intermediary receives a baseline packet generated at a compute instance. The baseline packet indicates a public IP (Internet Protocol) address of the service as the destination, and a private IP address of the compute instance as the source. In accordance with a tunneling protocol, the tunneling intermediary generates an encapsulation packet comprising at least a portion of the baseline packet and a header indicating the isolated virtual network. The encapsulation packet is transmitted to a node of the service. |
| US09787497B2 |
Network apparatus and method using link layer routing
A next-generation mobile communication network apparatus and method using link layer routing. The network apparatus uses an existing IP address as an identifier while using a link layer address as a locator, and utilizers a location server that manages mapping between the IP address and the link layer address, thereby providing mobility. |
| US09787486B2 |
Enabling chat sessions
Methods, systems, computer readable media, and apparatuses for enabling chat sessions are presented. In response to detecting that a first user is viewing a first program, a chat invitation may be automatically transmitted to a second user. The chat invitation may identify the first user and the first program, and further may invite the second user to initiate a chat session with the first user. An updated chat invitation may be automatically transmitted in response to detecting that the first user has changed to viewing a second program, and a chat session that has been initiated may subsequently be transferred to another device. Content prioritization settings may be accounted for in transmitting one or more chat invitations, and before a chat invitation is transmitted, it may be determined that a sufficient amount of time has elapsed to suggest that the user will continue viewing the first program. |
| US09787484B2 |
Adapting PCC rules to user experience
A method for policy management in a network comprises collecting data relating to one or more active user equipment in the network, processing said data, and responsive to said processing determining if policy management provided by a policy function of the network with respect to a respective user equipment is to be changed. |
| US09787483B2 |
Method, system, and controller for routing forwarding
A method for routing forwarding is provided. The method includes: a controller sends pre-generated routing flow tables to an Evolved Universal Terrestrial Radio Access Network (UTRAN) NodeB (eNB) and an Access Gateway (AGW) respectively; and the eNB and the AGW distribute data according to the received routing flow tables respectively. The controller sends the routing flow tables to the eNB and the AGW, so that the extended OpenFlow protocol can be applied to an Evolved Packet System (EPS), network upgrading cost is lowered, network upgrading can be simplified, and a network upgrading period can be shortened. |
| US09787477B1 |
Validating certificate chains for both internal and public facing server using unified interface
Embodiments presented herein provide a validation service used to validate a certificate chain for both public facing servers as well as internal, non-public facing servers. To validate a certificate chain, the client generates a request with the network address and sends it to the validation service. In response, the validation service attempts to establish a connection with the server at the network address. If successful, the validation service receives a certificate chain from the server and can verify that the certificate chain is complete, valid, and chains to a trusted root. If the validation service cannot connect to the network address identified in the request, then the validation service sends a local validation component to the requesting client. The local validation component executes from the client and validates the certificate chain presented by the network server. |
| US09787473B2 |
Carbon nanotube array for cryptographic key generation and protection
Techniques for use of carbon nanotubes as an anti-tampering feature and for use of randomly metallic or semiconducting carbon nanotubes in the generation of a physically unclonable cryptographic key generation are provided. In one aspect, a cryptographic key having an anti-tampering feature is provided which includes: an array of memory bits oriented along at least one bit line and at least one word line, wherein each of the memory bits comprises a memory cell, wherein the cryptographic key is stored in the memory cell, and wherein the memory cell is connected to the at least one bit line; and a metallic carbon nanotube interconnect which connects the memory cell to the at least one word line. A cryptographic key and method for processing the cryptographic key are also provided. |
| US09787470B2 |
Method and apparatus of joint security advanced LDPC cryptcoding
A JSALE encoder includes a first encryption layer to apply a first encryption key to a plaintext input data. The JSALE encoder includes a row encoding module to: generate parity bits of a current layer of an H-matrix by applying a LDPC encoding process to the encrypted input data, and generate a cryptcoded data appending the parity bits to the encrypted input data. The JSALE encoder includes a second encryption layer to initiate each subsequent round of the JSALE process through round Nr and to output a ciphertext after the Nr round. |
| US09787469B2 |
Method and system for encrypting data
A method for encrypting data based on all-or-nothing encryption. Data to be encrypted and an encryption key are provided. The data is divided into an odd number of blocks, wherein each of the odd number of blocks has the same size. The blocks are encrypted with the encryption key to obtain an intermediate ciphertext that includes the encrypted blocks. The intermediate ciphertext is linearly transformed based on additive contravalence operations to obtain a final ciphertext. |
| US09787468B2 |
LVDS data recovery method and circuit
An LVDS data recovery method includes adopting three clocks to sample a received signal clock at the same time, wherein the first clock, the second clock and the third clock have the same frequency and different phases; determining whether the first clock is in the rising-falling edges of the received signal clock, in accordance with sampled levels of the received signal clock sampled by the three clocks at the same time; after determining the first clock is in the rising-falling edges of the received signal clock, adjusting phase of the first clock, and sampling the received data signal in accordance with adjusted phase of the first clock. The LVDS data recovery method ensures that the sampling clock edge is aligned with at the center of the data to be sampled. In case of high speed, the accuracy of the data sampling is guaranteed. |
| US09787466B2 |
High order hybrid phase locked loop with digital scheme for jitter suppression
A method for filtering noise. The method may include obtaining an output signal from a phase locked loop (PLL) device. The method may include determining, using a digital phase detector and the output signal, an amount of PLL error produced by the PLL device. The method may include filtering, using a delay element and a digital filter, a portion of the amount of PLL error from the output signal to produce a filtered signal in response to determining the amount of PLL error produced by the PLL device. |
| US09787460B2 |
Self-interference channel estimation system and method
The present application describes a method for characterizing a self-interference channel of a frequency division duplex transceiver including a transmitter and a receiver. The method includes transmitting, from a transmitter of a frequency division duplex transceiver in a transmission band, a transmission signal including a message signal and a swept tone that changes frequency from below an upper edge to above a lower edge of a reception band of a receiver, the self-interference channel being defined between the transmitter and the receiver of the frequency division duplex transceiver, such that at least a portion of the message signal leaks into a signal received the receiver, determining, at an infinite impulse response (IIR) filter of the receiver, an infinite impulse response of the self-interference channel based upon a reception of the swept tone swept at each frequency in the reception band, and estimating the self-interference channel, based upon the infinite impulse response. |
| US09787458B2 |
Methods and apparatus relating to LTE FDD-TDD inter-system carrier aggregation in advanced wireless communication systems
A signalling method is disclosed for use in an advanced wireless communication network that supports FDD-TDD carrier aggregation (CA). The signalling method comprises configuring the UE (by establishing radio resource control (RRC) connection with the network through the first access node) for data transmission between the UE and the network through the first access node on the first duplex mode carrier as a primary component carrier (PCell), configuring the UE (via dedicated RRC signalling on the PCell) for data transmission between the UE and the network through the second access node on the second duplex mode carrier as a secondary component carrier (SCell), and performing scheduling for data transmission on the aggregated SCell using either self-scheduling or cross-carrier scheduling. |
| US09787456B2 |
Wireless terminals, nodes of wireless communication networks, and methods of operating the same
According to one embodiment, a method of operating a wireless terminal may include configuring a first group of component carriers, and while configured with the first group of component carriers, communicating a first MAC CE including a first bit map having a first bit map size with bits of the first bit map corresponding to respective component carriers of the first group of component carriers. The method may also include configuring a second group of component carriers wherein the first and second groups of component carriers are different. While configured with the second group of component carriers, a second MAC CE may be communicated, wherein the second MAC CE includes a second bit map having a second bit map size with bits of the second bit map corresponding to respective component carriers of the second group of component carriers. Moreover, the first and second bit map sizes may be different. |
| US09787450B2 |
Method and apparatus for estimating channel in wireless communication system
The present invention relates to a wireless communication system. A method for estimating a channel by a user equipment (UE) in a wireless communication system includes receiving information about at least one channel station information (CSI) configuration for reporting CSI of one of a plurality of serving cells, determining that the same precoding matrix is applied to a plurality of resource blocks when all of the at least one CSI configuration is configured to report a precoding matrix indicator (PMI) and a rank indicator (RI), and determining that the precoding matrix is applied to one resource block when CSI configuration configured not to report the PMI and the RI is present among the at least one CSI configuration, and estimating a channel based on a result of the determination. |
| US09787441B2 |
Video conference bridge setting, sharing, pushing, and rationalization
A conference system is provided with enhanced settings capabilities. A controller can poll for settings at each endpoint in a conference system and be able via the video stream to selectively display and compare settings among the endpoints. One location can push its settings to one or more locations to overcome failures or degradation in the conference. The settings between different controllers may be rationalized via a common denominator method or tabular method to build a knowledge of how to configure conferences and to automate responses to problems. |
| US09787437B2 |
Uplink ACK/NACK bundling enhancement for LTE TDD enhanced interference management and traffic adaptation
A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus groups subframes of a time division duplex (TDD) configuration of a serving cell into a set of anchor subframes and a set of non-anchor subframes. The apparatus also separately bundles positive acknowledgements (ACKs) and/or negative acknowledgements (NACKs) of the anchor subframes, and ACKs and/or NACKs of the non-anchor subframes. |
| US09787428B2 |
Smart dynamic line management
The invention describes a method of performing re-synchronizations on a DSL line to optimize the synchronization rate of the line. The line is monitored over a period of time, and a stable SNR margin is determined, below which the line is observed to lose synchronization. Historical synchronization rates and associated SNR margins for the line are recorded, and the highest stable synchronization rate is determined as the historical synchronization rate that does not have any associated SNR margins below the stable SNR margin. The method attempts to optimize the synchronization rate of the line towards this highest stable synchronization rate. To do this, the current target SNR margin imposed by DLM is identified, for example, by interrogating the DLM system or by noting the SNR margin on the line immediately after the most recent synchronizations. Assuming the current synchronization rate on the line is less than the highest stable rate, then the synchronization rate is optimized by triggering a synchronization of the line when the SNR margin is greater than the target SNR margin plus an additional predetermined amount. The result should be an increase in the synchronization rate, and can be repeated until the synchronization rate reaches the highest stable synchronization rate. |
| US09787425B1 |
Device and method for jamming over the air signals in a geographical delimited area
The present invention is generally related to a device for providing wireless jamming signals in a delimited geographic area. The device is comprised of an on/off initiation module that allows the user to turn-on or turn-off the device, and initialize the jamming wireless signals device, a central controller module to distribute and analyze the information of the system, a signal transmitter device to transmit the jamming signals, a device to calculate distances to obtain the distances between the said signal transmitter and the objects in the delimited geographic area. The jamming device once is turned on calculates the distances and the power where to transmit the jamming signals to cover the required geographic area. This device will be capable of jamming one or more types of wireless signals at the same time such as Wi-Fi, cell phones and other wireless signals. |
| US09787423B2 |
Optical module
An integrated apparatus with optical/electrical interfaces and protocol converter on a single silicon substrate. The apparatus includes an optical module comprising one or more modulators respectively coupled with one or more laser devices for producing a first optical signal to an optical interface and one or more photodetectors for detecting a second optical signal from the optical interface to generate a current signal. Additionally, the apparatus includes a transmit lane module coupled between the optical module and an electrical interface to receive a first electric signal from the electrical interface and provide a framing protocol for driving the one or more modulators. Furthermore, the apparatus includes a receive lane module coupled between the optical module and the electrical interface to process the current signal to send a second electric signal to the electrical interface. |
| US09787422B2 |
Transmitting apparatus and mapping method thereof
A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme. |
| US09787412B2 |
Methods and apparatus for inducing a fundamental wave mode on a transmission medium
Aspects of the subject disclosure may include, for example, a system for generating electromagnetic waves having a fundamental wave mode, and directing the electromagnetic waves to an interface of a transmission medium for guiding propagation of the electromagnetic waves. Other embodiments are disclosed. |
| US09787408B2 |
Apparatus and method for unified mitigation of correlative additive and multiplicative noise
A digital signal processing method and apparatus is described. The digital processing apparatus comprises a coarse carrier recovery module for performing a coarse carrier compensation of a received modulated signal; and a trellis-based equalization module selectable between a first mode for performing a trellis-based equalization to compensate a residual inter-symbol interference of the received modulated signal and a second mode for performing a trellis-based equalization to compensate a residual phase noise of the received modulated signal. |
| US09787407B1 |
Fading mitigation of the turbulent channel based on polarization diversity in coherent optical receivers
A method includes receiving a first data packet on a first polarization portion of an optical signal from a second communication terminal through a free space optical link during a first time period and receiving a first data packet replica on the first polarization portion of the optical signal during a second time period. The second time period is delayed in time relative to the first time period. The method also includes determining receiving powers for the optical link during both the first time period and the second time period based on at least one of the received first data packet and the received first data packet replica. The method also includes selecting the one of the first data packet or the first data packet replica that is associated with the highest receiving power for the optical link as surviving data for maintaining the optical link. |
| US09787406B2 |
Power management implementation in an optical link
An optical link power management scheme takes the best advantage of a dynamic connection environment, where ports may be connected and disconnected at any time, and where data flows may start and stop as needed by the applications using the high speed data links. Power consumption is optimized, eye safety standards are met, and robust connection detection is preserved. |
| US09787403B2 |
Digital optical transmitter, optical communication system using the same, and digital optical transmission method
A digital optical transmitter of the present invention comprises an optical modulator, pre-equalization factor computation means for generating transform functions for compensating waveform distortion to occur in the optical modulator, and pre-equalization signal generation means for outputting third data and fourth data after creating them by performing a pre-equalization process on first data and second data. Here, through the transform functions, the first data is added to the fourth data, in a manner depending on a characteristic of the optical modulator, and the second data is added to the third data, in a manner depending on a characteristic of the optical modulator. |
| US09787401B2 |
Mode division multiplexed passive optical network (MDM-PON) apparatus, and transmission and reception method using the same
A Mode Division Multiplexed Passive Optical Network (MDM-PON) apparatus includes: a non-mode selective multiplexer which includes a first end where three or more single-mode optical fibers are spaced apart from each other by a predetermined distance, and a second end where cores of the three or more single-mode optical fibers are tapered such that a gap between the three or more single-mode optical fibers is narrower than the predetermined distance while the three or more single-mode optical fibers are spaced apart from each other by an equal distance; an optical line terminal (OLT) which is connected to the second end through a few-mode fiber, and transmits a downstream optical signal; and three or more optical network units (ONUs) which is connected to the first end through the three or more single-mode optical fibers, and transmits upstream optical signals. |
| US09787397B2 |
Self identifying modulated light source
In one aspect, the present disclosure relates to a self identifying light source including an emitter that produces visible light; and an autonomous modulator in electrical communication with the emitter that automatically and continually modulates the visible light produced by the emitter, wherein the modulated visible light represents an identification code of the light source. In some embodiments, the emitter is a light emitting diode (LED) and further comprises an LED driver that provides a specified voltage and current to each LED in the light source. |
| US09787396B2 |
Optical transmission device, transmission system, and transmission method
There is provided an optical transmission device including: a generator configured to convert an electric signal into a plurality of parallel signals, modulate the plurality of parallel signals, shift center frequencies of spectra of the plurality of modulated parallel signals into different frequencies, so as to generate signals accommodated in a plurality of sub-channels each having different center frequencies, and generate a multiplexed signal by multiplexing the signals accommodated in the plurality of sub-channels; a transmitter configured to optical-modulate the multiplexed signal and transmit the optical-modulated signal to an optical reception device; and a controller configured to control a frequency spacing between adjacent sub-channels of the plurality of sub-channels, based on a monitoring result of reception characteristics of the signals accommodated in the plurality of sub-channels within the multiplexed signal in the optical reception device. |
| US09787388B1 |
Fully flexible multi-tuner front end architecture for a receiver
In an example, a method includes: in a first mode, causing a first tuner of an entertainment system to receive and process a first RF signal from a first antenna configured for a first band to output a first audio signal of a first radio station and causing a second tuner of the entertainment system to receive a second RF signal from a second antenna configured for the first band to determine signal quality metrics for one or more radio stations of the first band; in a second mode, causing the first tuner to output a first signal representation of the first RF signal and causing the second tuner to receive and process the second RF signal to output a second signal representation of the second RF signal; and causing a phase diversity combining circuit to process the first and second signal representations to output an audio signal of the first radio station, without disruption of output from the entertainment system of a broadcast of the first radio station. |
| US09787387B2 |
Method and apparatus for virtualizing antenna in multi-antenna system, and method and apparatus for transmitting and receiving signal using the same
The transmitter maps an antenna port to a logical antenna port through a first virtualization. The transmitter maps the logical antenna port to a transceiver unit (TXRU) through a first operation. The transmitter maps the TXRU to a logical TXRU through a second operation. The transmitter maps the logical TXRU to a physical antenna element through a second virtualization. |
| US09787382B2 |
Joint beamforming in point-to-point wireless communication networks
A system for transmitting information between nodes in a point-to-point wireless communication system. The system includes a node with an antenna array and a beamformer that is controllable to orient a main lobe of the antenna array in a desired direction. A spacing of the plurality of antenna elements in the array is adjustable to control a direction of a grating lobe of the antenna array to complete a communication link with a node in the network. Signals are simultaneously transmitted in the direction of the main lobe and the grating lobe to different nodes in the network. |
| US09787377B2 |
Mutual WLAN and WAN interference mitigation in unlicensed spectrum
The disclosure provides for interference mitigation for wireless signals in unlicensed spectrum. A wireless device may receive a combined signal including a first radio access technology (RAT) signal and a second RAT signal. The wireless device may generate, using a first RAT receiver in a first processing path, a channel estimate for the first RAT signal based on a previously decoded signal of the first RAT. The wireless device may reduce interference to the second RAT signal caused by the first RAT signal, in a second processing path, using the channel estimate. The wireless device may further decode the second RAT signal. The wireless device may remodulate the decoded signal using a transmitter to generate a remodulated second RAT signal. The remodulated second RAT signal may be canceled from the combined signal. The wireless device may decode a remaining portion of the combined signal including the first RAT signal. |
| US09787375B2 |
Spatial spreading in a multi-antenna communication system
Spatial spreading is performed in a multi-antenna system to randomize an “effective” channel observed by a receiving entity for each transmitted data symbol block. For a MIMO system, at a transmitting entity, data is processed (e.g., encoded, interleaved, and modulated) to obtain ND data symbol blocks to be transmitted in NM transmission spans, where ND≧1 and NM>1. The ND blocks are partitioned into NM data symbol subblocks, one subblock for each transmission span. A steering matrix is selected (e.g., in a deterministic or pseudo-random manner from among a set of L steering matrices, where L>1) for each subblock. Each data symbol subblock is spatially processed with the steering matrix selected for that subblock to obtain transmit symbols, which are further processed and transmitted via NT transmit antennas in one transmission span. The ND data symbol blocks are thus spatially processed with NM steering matrices and observe an ensemble of channels. |
| US09787374B1 |
Systems and methods for high-rate RF communications employing spatial multiplexing in line of sight environments
A system and method to optimize a multiple-input multiple-output signal processing RF communication system that includes obtaining, by a processor, at the receiver, during spatial processing, metrics from the channel stream. The metrics include a spatial correlation metric representing spatial coupling between multiplexed streams in the channel stream, a signal-to-noise power ratio metric representing propagation losses encountered by the signal, and a cross polarization discrimination metric representing whether polarization modes can be processed as independent groups. The processor obtains these metrics based on obtaining geometric information related to the receiver and the transmitter. Predictive methods may be employed to determine expectations for some metrics in advance. The method includes applying a policy with at least one objective of the system, and based on at least one metric and the policy, applying at least one adaptation to at least one of: the receiver or, the transmitter. |
| US09787373B1 |
Hybrid node
Apparatuses, methods, and systems of a hybrid node are disclosed. One embodiment of the hybrid node includes a first sector and a second sector. The first sector is operative to transmit a signal through a predetermined transmission channel at each of a first plurality of transmit beam forming settings. The second sector is operative to receive the signal through the predetermined channel at a second plurality of receive beam forming settings for each of more than one of the first plurality of transmit beam forming settings. Further, the node is operative to measure a received signal quality of the received signal at each of the second plurality of receive beam forming settings of the second plurality of antenna elements, for each of the more than one of the first plurality of transmit beam forming settings of the first plurality of antenna elements. |
| US09787372B2 |
Single frequency data network
A Next Generation Data Network is described. It leverages the “cloud” for data management, frequency data computation and analytics. Packets are transmitted at times and in directions to minimize interference between nodes in the network. The wireless network is a single frequency network that permits limited non-line-of-sight operation. |
| US09787370B2 |
Dynamic clustering for radio coordination in a virtual network
An apparatus for adaptively defining clusters transmit points for coordination in a communication network includes a circuit that receives radio frequency channel information corresponding to the transmit points and defines a subset of the transmit points based at least in part on the radio frequency communication channel information. The subset is interrelated by a contiguous chain of dominant interference relationships between pairs of the transmit points. The apparatus further includes a processor that independently coordinates radio communications among the subset of transmit points. |
| US09787361B2 |
Multi-length cyclic prefix for OFDM transmission in PLC channels
Embodiments of the invention provide multiple cyclic prefix lengths for either both the data-payload and frame control header or only the data payload. Frame control header (FCH) and data symbols have an associated cyclic prefix. A table is transmitted in the FCH symbols, which includes a cyclic prefix field to identify the cyclic prefix length used in the data payload. A receiver may know the cyclic prefix length used in the FCH symbols in one embodiment. In other embodiments, the receiver does not know the FCH cyclic prefix length and, therefore, attempts to decode the FCH symbols using different possible cyclic prefix lengths until the FCH symbols are successfully decoded. |
| US09787359B2 |
Method and apparatus for providing security using network traffic adjustments
Aspects of the subject disclosure may include, for example, generating first traffic for transmitting along a network path toward a recipient device, determining a schedule for transmitting the first traffic, and facilitating transmission of the first traffic along the network path using a first waveguide system. The first waveguide system has a dielectric coupler, and operates by communicating electromagnetic waves via the dielectric coupler at a physical interface of a transmission medium that propagate without utilizing an electrical return path. The electromagnetic waves are guided by the transmission medium, wherein the electromagnetic waves at least partially surround an outer surface of the transmission medium, and wherein the electromagnetic waves have a non-optical frequency range. Other embodiments are disclosed. |
| US09787356B2 |
System and method for large dimension equalization using small dimension equalizers
An equalizer includes an equalizer circuit including a signal input to receive a first frequency-domain signal, another signal input to receive a second frequency-domain signal, and an equalized signal output to provide a first equalized signal based upon the first and second frequency-domain signals. Another equalizer circuit includes a signal input to receive a third frequency-domain signal, another signal input to receive a fourth frequency-domain signal, and an equalized signal output to provide a second equalized signal based upon the third and fourth frequency-domain signals. A third equalizer circuit includes a signal input coupled to the equalized signal output of the first equalizer circuit to receive the first equalized signal, another signal input coupled to the equalized signal output of the second equalizer circuit to receive the second equalized signal, and an equalized signal output to provide a third equalized signal based upon the first and second equalized signals. |
| US09787353B2 |
Radio frequency (RF) front-end without signal switches
Disclosed is an RF front-end with improved insertion loss having at least a first resonator with a first port and a second port and at least a second resonator having a third port and a fourth port, wherein the first resonator and the second resonator are magnetically coupled by no more than 5%. Also included is at least one coupling structure coupled between the second port of the first resonator and the third port of the second resonator, wherein the coupling structure has a coupling control input for varying a coupling coefficient between the first resonator and the second resonator such that an RF signal transfer between the first port of the first resonator and the fourth port of the second resonator is controllably variable between 5% and 95%. |
| US09787352B2 |
Radio frequency front end system with an integrated transmit/receive switch
A Radio Frequency (RF) front end system and method are disclosed. The RF front end system comprises an antenna, a matching network coupled to the antenna, a power amplifier (PA) coupled to the matching network via a port on a transmit path, a low noise amplifier (LNA) coupled to the matching network via the port on a receive path and at least one transmit/receive switch (T/R SW) coupled between the port and at least one of the PA and LNA. |
| US09787351B2 |
Radiofrequency receiver device, method for adjusting such a device and corresponding computer program
A radiofrequency receiver device including: a local oscillator oscillating at an adjustable local frequency; a mixer receiving radiofrequency signals and the output of the local oscillator for the supply of intermediate-frequency signals; a filtering system configured and positioned to filter the signals according to a bandpath with an adjustable frequency bandwidth; and a data detector in the intermediate-frequency signals. It further includes means for adjusting the local frequency of the local oscillator, between minimum and maximum oscillation frequencies, and for adjusting the bandpath of the filtering system, between minimum and maximum frequency bandwidths, wherein the adjusting means are suitable for adjusting the local frequency and the bandpath until the detector detects a predetermined identification code in one of the intermediate-frequency signals. |
| US09787348B2 |
Collapsible and expandable spring-loaded discs
Two circular rings or discs which are somewhat rotatable with respect to one another. They are connected by a foldable cover which houses a spring inside. The spring, when collapsed, pushes the discs away from each other while the foldable cover is semi-flexible. When the accessory is collapsed, the foldable cover folds over itself, whereas when the accessory is expanded, the foldable cover becomes unfolded with a smaller-circumference center ridge which is less flexible or non-flexible, and situated between two larger circumference areas. Flanges on the inner and outer rings abut each other, keeping the spring collapsed and discs locked into each other in some embodiments. When the rings are rotated with respect to one another, the flanges become unlocked and the spring separates the discs such that one or both of the foldable cover or spring become the limiting factor in how far apart the discs spread from another. |
| US09787346B2 |
Configurable wearable electronic device
An electronic device includes a pliable casing that enables the electronic device to be configured in at least two different shapes. The two different shapes include a first shape that aligns the electronic device to a second electronic device having a set physical shape and a second shape that has at least one different physical configuration of the casing relative to the first shape. Electronic circuitry is located within the pliable casing that operates to provide at least one functional feature associated with the electronic device. A display screen is embedded in the pliable casing and displays data or images corresponding to the functional feature. A communication mechanism enables information exchange with the host device when the electronic device is brought in communication range of the host device. |
| US09787342B2 |
Subscriber identity module (SIM) ejector
Several embodiments for ejecting a SIM tray from an electronic device are disclosed. In some embodiments, a lever positioned behind the tray can be actuated to eject the tray. In some embodiments, a pivot mechanism can be actuated to eject the tray. In other embodiments, a gear mechanism can be actuated to eject the tray. In other embodiments, a spring element can be actuated to eject the tray. In some embodiments, the electronic device may include a key feature that allows the tray to eject only when a tool is used having a mating key feature with the key feature of the electronic device. |
| US09787341B2 |
Density function centric signal processing
A circuit for direct current (DC) offset estimation comprises a quantile value circuit and a signal processor. The quantile value circuit determines a plurality of quantile values of an input signal and includes a plurality of quantile filters. Each quantile filter includes a comparator, a level shifter, a monotonic transfer function component, and a latched integrator. The comparator compares the input signal and a quantile value. The level shifter shifts the output of the comparator. The monotonic transfer function component determines the magnitude of the shifted signal and provide a transfer function signal. The latched integrator suppresses transient characteristics of the transfer function signal and provide the quantile value. The signal processor is configured to calculate a weighted average of the quantile values to yield a DC offset estimate. |
| US09787336B1 |
Device and method of pre-distortion of power amplifier input signals
Embodiments of a mobile communication device and method for digital pre-distortion (DPD) are disclosed herein. The mobile communication device may scale a sequence of input samples by per-sample scale factors to generate a sequence of output samples for input to a power amplifier (PA), the input samples scaled to compensate for distortion of the PA. The mobile communication device may generate the scale factors based on per-sample inner products between a common weight vector and a per-sample distortion compensation vectors. The mobile communication device may generate the distortion compensation vectors based on vector outputs of predetermined distortion compensation functions. The mobile communication device may update the common weight vector based on a distortion error sequence between the sequence of output samples and a sequence of feedback samples. |
| US09787335B1 |
Method and apparatus for determining validity of samples for digital pre-distortion apparatus
A method and an apparatus for determining validity of samples for a digital pre-distortion apparatus is disclosed. It is an object of at least one embodiment to provide a method and an apparatus for determining validity of samples for a digital pre-distortion apparatus that is configured to compensate for nonlinearity of a power amplifier in an efficient manner by accurately estimating a pre-distortion coefficient with a low-capacity memory. |
| US09787334B2 |
High frequency power amplifier, high frequency front-end circuit, and radio communication device
A high frequency power amplifier includes a first high frequency amplifier, a final high frequency amplifier, and a tunable filter. The tunable filter is connected between the first high frequency amplifier and the final high frequency amplifier. The first high frequency amplifier and the final high frequency amplifier are each a multimode/multiband power amplifier. The tunable filter is regulated such that its pass band includes the frequency band of a transmission signal and its attenuation band includes the frequency band of a reception signal in a communication band used in transmission and reception. The pass band and the attenuation band are switched by the tunable filter in accordance with the communication band used in transmission and reception. |
| US09787320B1 |
Methods and apparatus for an analog-to-digital converter
Various embodiments of the present technology may comprise a method and apparatus for an analog-to digital converter (ADC). Methods and apparatus for an ADC according to various aspects of the present invention may operate in conjunction with a reference voltage that varies according to the frequency of a timing signal. By varying the reference voltage according to the frequency of the timing signal, the ADC generates a digital output having a substantially fixed voltage regardless of the frequency of the timing signal. |
| US09787314B2 |
System and method for fast-capture multi-gain phase lock loop
A phase locked loop system has a voltage-controlled variable-load ring oscillator (VLCO) that operates in a frequency band determined by a selected load on each stage of the ring oscillator. Each stage of the VLCO has multiple load selection transistors, each coupled to a load capacitor. Apparatus is provided for driving the load selection transistors according to a load configuration; and apparatus is provided for determining an operating load configuration such that a period of a divided reference signal approximately matches a period of a divided VLCO signal with the VLCO control voltage input clamped to a reference voltage. Once the load configuration is set, the loop is allowed to lock. In a particular embodiment, devices are provided for slowly tweaking the VLCO load to help keep the VLCO operating near an optimum control voltage despite drift of circuit parameters with temperature or time. |
| US09787312B2 |
Systems and methods for applying flux to a quantum-coherent superconducting circuit
Systems and methods are provided for applying flux to a quantum-coherent superconducting circuit. In one example, a system includes a long-Josephson junction (LJJ), an inductive loop coupled to the LJJ and inductively coupled to the quantum-coherent superconducting circuit, and a single flux quantum (SFQ) controller configured to apply a SFQ pulse to a first end of the LJJ that propagates the SFQ pulse to a second end of the LJJ, while also applying a flux quantum to the inductive loop resulting in a first value of control flux being applied to the quantum-coherent superconducting circuit. |
| US09787309B2 |
Methods for preventing reverse conduction
In one embodiment, a circuit includes a resistance including first and second terminals. The first terminal of the resistance is coupled to ground. The circuit also includes a first switching element including first, second, and third terminals. The first terminal of the first switching element is coupled to an output of an integrated circuit and the second terminal of the first switching element is coupled to a voltage supply of the integrated circuit. Additionally, the circuit includes a second switching element including first, second, and third terminals. The first terminal of the second switching element is coupled to an enable input of the integrated circuit. Furthermore, the second terminal of the second switching element is coupled to the third terminal of the first switching element and to the second terminal of the resistance. Moreover, the third terminal of the second switching element is coupled to the ground. |
| US09787307B2 |
Hybrid touch button and module using the same
A hybrid touch button, including: a touch display unit having a touch display area; a mechanical switch having a plurality of conductive contacts; and a control unit, having a power interface for coupling with a power source, a first interface coupled with the touch display area, a second interface coupled with the plurality of conductive contacts, and an output interface, wherein the control unit derives first input information from the first interface and second input information from the second interface, and determines an output configuration of the output interface according to the first input information and the second input information. |
| US09787300B2 |
Control circuit and control method for turning on a power semiconductor switch
A control circuit for turning on a power semiconductor switch comprises an input which is configured to receive a signal that characterizes the switch-on behavior of the power semiconductor switch, a variable current source which is configured to supply a current with a variable level to a control input of the power semiconductor switch in order to switch on the power semiconductor switch, wherein the control circuit is configured to control the variable current source in a closed control loop in response to the signal that characterizes the switch-on behavior of the power semiconductor switch. |
| US09787298B2 |
Operation of double-base bipolar transistors with additional timing phases at switching transitions
Methods and systems for operating a double-base bidirectional power bipolar transistor. Two timing phases are used to transition into turn-off: one where each base is shorted to its nearest emitter/collector region, and a second one where negative drive is applied to the emitter-side base to reduce the minority carrier population in the bulk substrate. A diode prevents reverse turn-on while negative base drive is being applied. |
| US09787295B2 |
Power supply circuit for gate driver and gate driver circuit of floating switch having the same
Disclosed herein is a power supply circuit for a gate driver. The power supply circuit for the gate driver includes a negative voltage generator configured to generate a negative voltage by receiving an input voltage, wherein the negative voltage generator includes a tank capacitor configured to be charged by receiving the input voltage through a charge path, a discharge switch configured to form a discharge path when the tank capacitor is discharged, and a negative voltage generation capacitor arranged on the discharge path and configured to generate the negative voltage by storing electric charges discharged from the tank capacitor when the tank capacitor is discharged. |
| US09787293B2 |
Current-mode clock distribution
Current-mode signaling for a one-to-many clock signal distribution providing significantly less dynamic power use and improved noise immunity compared to traditional VM signaling schemes. |
| US09787290B2 |
Resource-saving circuit structures for deeply pipelined systolic finite impulse response filters
Circuitry that accepts a data input and an enable input, and generates an output sum based on the data input includes an input stage circuit that includes an input register. The input register accepts the enable input. The circuitry further includes a systolic register operatively connected to the input stage circuit, and the systolic register is operated without any enable connection. The circuitry further includes a multiplier connected to the systolic register, which is configured to generate a product value. The circuitry further includes an output stage circuit that includes an adder that calculates the output sum based least in part on the product value. |
| US09787289B2 |
M-path filter with outer and inner channelizers for passband bandwidth adjustment
Disclosed is apparatus and method to filter a signal. In such an apparatus, an outer polyphase filter is configured for receiving an input signal and for channelizing the input signal into outer filtered samples. An outer Inverse Fourier Transform block is coupled to the outer polyphase filter and configured for transforming the outer filtered samples into a coarse multi-path output. An inner polyphase filter is coupled to a path of the coarse multi-path output for receiving information therefrom and configured for generating inner filtered samples of the information obtained from the path. The inner filtered samples are for moving an edge of a passband associated with the outer filtered samples toward a center of the passband. |
| US09787288B2 |
Optimal factoring of FIR filters
A method and system for the design and implementation of an optimally factored filter is presented. Pairs of angle values are organized in pairing candidates and a threshold is defined to indicate an upper bound on the number of pairing candidates. A first pairing candidate is exchanged above the threshold with a second pairing candidate below the threshold and a matrix is generated based on the pairing candidates below the threshold. A lowest predicted total quantization cost between all pairing candidates represented within the matrix is determined and the pairing candidates that result in the lowest predicted total quantization cost are used to determine the coefficients of the filter. |
| US09787287B2 |
Impedance calibration circuit
An impedance calibration circuit is disclosed, which relates to a technology for improving precision of pad resistance. The impedance calibration circuit includes: a first On Die Termination (ODT) circuit selected by a first selection signal, configured to tune its own resistance using a first code signal, and output a first resistance value to an output terminal; and a second ODT circuit selected by a second selection signal, configured to tune its own resistance using a second code signal, and output a second resistance value to the output terminal. |
| US09787286B2 |
Low phase shift, high frequency attenuator
A wideband RF attenuator circuit that has a reduced impact on the phase of an applied signal when switched between an attenuation state and a non-attenuating reference or bypass state. A low phase shift attenuation at high RF frequencies can be achieved by utilizing a switched signal path attenuator topology with multiple distributed transmission line elements per signal path to provide broadband operation, distribute parasitic influences, and improve isolation to achieve higher attenuation at higher frequencies while still maintaining low phase shift operational characteristics. In an alternative embodiment, extension to even higher frequencies can be achieved by utilizing a quarter-wave transmission line element at the signal interfaces of each signal path, thereby improving insertion loss and power handling. |
| US09787285B2 |
Apparatus and methods for digital step attenuators with small output glitch
Apparatus and methods for digital step attenuators are provided herein. In certain configurations, a DSA includes a plurality of DSA stages that can be set in an attenuation mode or in a bypass mode using a plurality of switching circuits. A first switching circuit of the plurality of switching circuits includes a field effect transistor (FET) switch, a gate resistor, one or more gate resistor bypass switches, and a pulse generation circuit. The gate resistor is electrically connected between a switch control input and a gate of the FET switch, and a switch control signal can be provided to the switch control input to turn on or off the FET switch. In response to detecting a rising and/or falling edge of the switch control signal, the pulse generation circuit can control the one or more gate resistor bypass switches to bypass the gate resistor. |
| US09787284B2 |
Waveform shaping filter and radiation detection device
A waveform shaping filter according to one embodiment includes a first resistor, a first transistor, a first capacitor, and a first amplifier. The first resistor includes one end to which a signal current is input and the other end. The first transistor includes a first terminal connected to the other end of the first resistor, a second terminal, and a control terminal. The first capacitor includes one end connected to the other end of the first resistor and the other end. The first amplifier includes an input terminal connected to the one end of the first resistor and an output terminal connected to the control terminal of the first transistor. |
| US09787280B2 |
Acoustic resonator and method of manufacturing the same
There is provided an acoustic resonator including: a resonance part including a first electrode, a second electrode, and a piezoelectric layer interposed between the first and second electrodes; and a substrate provided below the resonance part, wherein the substrate includes at least one via hole penetrating through the substrate and a connective conductor formed in the via hole and connected to at least one of the first and second electrodes. Therefore, reliability of the connective conductor formed in the substrate may be secured. |
| US09787275B2 |
Low voltage electromagnetic interference filter of electric vehicle
A low voltage electromagnetic interference (EMI) filter of an electric vehicle is provided. In the low voltage EMI filter, a pair of Y capacitor units are respectively installed in input and output ends of the low voltage EMI filter. A normal mode (DM) filter and a common mode (CM) filter are installed between the pair of Y capacitor units. The pair of Y capacitor units, the DM and CM filters discharge CM and DM noises generated in a low voltage battery connection unit to a sash GND (earth) step by step and reduce noises of the low voltage battery connection unit. |
| US09787274B2 |
Automatic sound equalization device
A technique for determining one or more equalization parameters includes acquiring, via one or more electrodes, auditory brainstem response (ABR) data associated with a first audio sample and determining, via a processor, one or more equalization parameters based on the ABR data. The technique further includes reproducing a second audio sample based on the one or more equalization parameters, acquiring, via the one or more electrodes, complex auditory brainstem response (cABR) data associated with the second audio sample, and comparing, via the processor, the cABR data to at least one representation of the second audio sample to determine at least one measure of similarity. The technique further includes modifying the one or more equalization parameters based on the at least one measure of similarity. |
| US09787272B2 |
Linearizing and reducing peaking simultaneously in single-to-differential wideband radio frequency variable gain trans-impedance amplifier (TIA) for optical communication
An amplifier, a circuit, and an optical communication system are provided. The disclosed amplifier may include a first transistor receiving a first portion of an input signal received at the amplifier, a second transistor receiving a second portion of the input signal, an automatic gain control signal that is dynamically adjustable in response to variations in an output of the amplifier, and a varactor that has its capacitance adjusted by changes in the automatic gain control signal and, as a result, adjusts a position of a pole in a transfer function of the amplifier. |
| US09787269B2 |
Audio control using auditory event detection
In some embodiments, a method for processing an audio signal in an audio processing apparatus is disclosed. The method includes receiving an audio signal and a parameter, the parameter indicating a location of an auditory event boundary. An audio portion between consecutive auditory event boundaries constitutes an auditory event. The method further includes applying a modification to the audio signal based in part on an occurrence of the auditory event. The parameter may be generated by monitoring a characteristic of the audio signal and identifying a change in the characteristic. |
| US09787267B2 |
Integrated audio amplification circuit with multi-functional external terminals
The present invention relates in one aspect to an audio amplification circuit comprising an input terminal for receipt of an input signal from a transducer. A signal processor is operatively coupled to the input terminal for receipt and processing of the input signal to generate a processed digital audio signal in accordance with a programmable configuration setting of the signal processor. A serial data transmission interface is configured for receipt of the processed digital audio signal and supply of a corresponding digital audio stream at an output terminal of the integrated audio amplification circuit. A serial data receipt interface is operatively coupled to an externally accessible configuration terminal of the integrated audio amplification circuit and a controller is configured to adjust one of the programmable configuration setting of the signal processor and a format of a digital audio stream in accordance with first configuration data received through the serial data receipt interface. The controller is in a first state is responsive to a logic state of the externally accessible configuration terminal to control the format of the digital audio stream or the programmable configuration setting. In a second state, the controller is configured for receipt and reading of the first configuration data through the externally accessible configuration terminal and the serial data receipt interface. |
| US09787263B2 |
Mismatch correction in differential amplifiers using analog floating gate transistors
An analog differential amplifier circuit, such as an operational transconductance amplifier (OTA), with input offset correction capability. First and second analog floating gate (AFG) devices each include a trim transistor connected in parallel with a series transistor in first and second input legs, respectively, of the amplifier. Floating gate electrodes in the AFG devices are differentially programmed to correct for error in the output signal in response to zero input differential voltage at its inputs. Temperature stability is attained by programming the floating gate electrodes to gate voltages above the floating gate transistors. In one embodiment, the AFG devices each include a second trim transistor sharing the same floating gate electrode; the sum of the currents conducted by the second trim transistors is added, by way of a current mirror, to the tail current applied to the first and second input legs. |
| US09787262B2 |
Doherty amplifier with additional delay element
An amplifier includes two amplifier circuits and a power splitter. The power splitter splits a signal to be amplified and generates a phase displacement of 90° in the case of a rated frequency between resulting partial signals. In this context, the amplifier circuits each amplify one of the partial signals or respectively a signal derived from one of the partial signals. The amplifier additionally contains a first delay element, which is arranged between the power splitter and one of the amplifier circuits. |
| US09787256B1 |
Coupled coils inter-stage matching network
An amplifier circuit having an improved inter-stage matching network and improved performance. In one embodiment, an RF signal source having an output impedance ZSOURCE is approximately impedance matched through an inductive tuning circuit to a power amplifier having an input impedance ZPA. The inductive tuning circuit includes a tunable capacitor element C1 and inductive elements L1, L2, which may be fabricated as stacked conductor coils. Since the capacitance of C1 is tunable, impedance matching is available over a broad range of RF frequencies. Also provided are DC isolation between the RF signal source and the power amplifier, coupling of a voltage source to the output of the RF signal source through L1, and coupling of a bias voltage to the input of the power amplifier through L2. |
| US09787255B2 |
Sequential broadband doherty power amplifier with adjustable output power back-off
The invention relates to a sequential broadband Doherty power amplifier with adjustable output power back-off The sequential broadband Doherty power amplifier has at least one input (I1, I2; RFin) for receiving at least one broadband HF signal, wherein the broadband HF signal or broadband HF signals (RFin) have at least an average power level (carrier/average) and a peak envelope power level (peak), with the average power level and the peak envelope power level defining a crest factor, and a first amplifier branch for amplifying the input signal, with the first amplifier branch providing the amplification substantially for the low and at least the average power level, at least one second amplifier branch for amplifying the input signal, wherein the second amplifier branch substantially provides the amplification for the peak envelope power level, wherein the output of the first amplifier branch is connected via an impedance inverter (ZT) to the output of the second amplifier branch, the junction (CN) being connected to the load (Z0) in a substantially directly impedance-matched manner, wherein the first and the second amplifier branch each have a supply voltage, with at least one of the supply voltages being variable as a function of the crest factor of the signal to be amplified, and wherein the signal propagation delay through the at least two amplifier branches is substantially identical in the operating range. |
| US09787253B2 |
Doherty amplifier and transmission apparatus
A Doherty amplifier (10) according to the present invention includes: a distribution unit (11) that distributes input signals; a main amplifier (12) that amplifies a first distributed signal output from the distribution unit (11); a transmission line unit (13) that transmits the first distributed signal amplified by the main amplifier (12); a peak amplifier (14) that amplifies a second distributed signal output from the distribution unit (11); a transmission line unit (15) that transmits the second distributed signal amplified by the peak amplifier (14); a synthesizing unit (16) that synthesizes the first distributed signal and the second distributed signal, and outputs a synthesized signal; and an impedance transformation unit (17) that performs an impedance transformation of the synthesized signal output from the synthesizing unit (16). The impedance transformation unit (17) includes a plurality of λ/4 transmission lines connected in series. |
| US09787250B2 |
Semiconductor device and measurement device
A semiconductor device includes an electronic component that includes an oscillator and has terminals on one face. A semiconductor chip is electrically connected to the electronic component and also includes terminals on one face thereof. The electronic component and the semiconductor chip are mounted to a mounting base such that the terminals of the electronic component and the terminals of the semiconductor chip face in the same direction. First bonding wires are connected to the terminals of the semiconductor chip, and second bonding wires having an apex height smaller than that of the first bonding wires connect the terminals of the electronic component to the terminals of the semiconductor chip. A sealing member completely seals within at least the electronic component. |
| US09787248B2 |
Power measurement system and load power monitoring system using the same and operating method thereof
A load power monitoring system includes: an external power supply source; a renewable energy source configured to generate power or store a power applied from the external power supply source, and discharge the generated or stored power; a distribution board configured to distribute a power applied from the external power supply source or the renewable energy source to an electronic device; a power measurement device configured to detect power amount data of at least one of the external power supply source and the renewable energy source; a second power measurement device configured to detect power amount data distributed to the electronic device; and a monitoring server configured to collect power amount data detected by each of the power measurement devices and monitor a power of a load on the basis of the collected power amount data. |
| US09787247B2 |
Solar concentrator with asymmetric tracking-integrated optics
A method is provided for using asymmetrically focused photovoltaic conversion in a hybrid parabolic trough solar power system. Light rays received in a plurality of transverse planes are concentrated towards a primary linear focus in an axial plane, orthogonal to the transverse planes. T band wavelengths of light are transmitted to the primary linear focus, while R band wavelengths of light are reflected towards a secondary linear focus in the axial plane. The light received at the primary linear focus is translated into thermal energy. The light received at the secondary linear focus is asymmetrically focused along a plurality of tertiary linear foci, orthogonal to the axial plane. The focused light in each tertiary linear focus is concentrated into a plurality of receiving areas and translated into electrical energy. Asymmetrical optical elements are used having an optical input interfaces elongated along rotatable axes, orthogonal to the axial plane. |
| US09787245B2 |
Motor control apparatus having protection operation unit, and machine learning apparatus and method thereof
A machine learning apparatus learns conditions associated with power failure on the side of an AC power supply in a motor control apparatus which converts AC power into DC power, outputs the DC power to a DC link, further converts the DC power into AC power for driving a motor, and supplies the AC power to the motor, includes a state observation unit which observes a state variable including at least one of data associated with the value of a power supply voltage on the AC power supply side, data associated with the amount of energy stored in a DC link capacitor provided in the DC link, and data indicating whether a protective operation for the motor control apparatus is successful, and a learning unit which learns conditions associated with power failure on the AC power supply side in accordance with a training data set defined by the state variable. |
| US09787242B2 |
Motor control device for controlling motor in dependence on motor's temperature and sheet conveying device
Temperature-dependent motor control device, including: a motor controller configured to switch a motor control state among an activated state in which the motor is activated by a first current, an activation stopped state in which activation of the motor is stopped by stopping current supply, and an activation suspended state in which activation of the motor is suspended with a second current smaller than the first current kept supplied; and a temperature estimator configured to calculate an estimated motor temperature value and to perform a first calculation for gradually increasing the estimated value when the motor is in the activated state, a second calculation for gradually decreasing the estimated value when the motor is in the activation stopped state, and a third calculation for gradually decreasing the estimated value at a rate of decrease lower than that in the second calculation when the motor is in the activation suspended state. |
| US09787238B2 |
Four-phase switched reluctance motor torque ripple three-level suppression method
A four-phase switched reluctance motor torque ripple three-level suppression method. A first set of torque thresholds is set in rotor position interval [0°, θr/4]. A second set of torque thresholds is set in rotor position interval [θr/4, θr/2]. Power is supplied to adjacent phase A and phase B for excitation. The power supplied for excitation to phase A leads the power supplied for excitation to phase B by θr/4. An entire commutation process from phase A to phase B is divided into two intervals. In rotor position interval [0°, θ1], phase A uses the second set of torque thresholds while phase B uses the first set of torque thresholds. Critical position θ1 automatically appears in the commutation process, thus obviating the need for additional calculations. Total torque is controlled between [Te+th2low and Te+th2up]. In rotor position interval [θ1, θr/4], phase A continues to use the second set of torque thresholds, phase B continues to use the first set of torque thresholds, and the total torque is controlled between [Te+th1low and Te+th1up]. This suppresses torque ripples of a four-phase switched reluctance motor and provides great engineering application values. |
| US09787236B2 |
System and method for optimizing flux regulation in electric motors
A system and method for dynamically optimizing flux levels in electric motors based on estimated torque. Motor parameters and motor equations are used to estimate operating characteristics and to set current and voltage limits which define an optimal flux operating range for a given speed and torque of the motor. A slope of a linear flux gain is determined within the defined operating range at different speeds of the motor. The determined slopes for the different speeds are saved in a memory element. A control element determines and achieves an optimal flux level for the motor by accessing the table to identify a specific slope which corresponds to an actual speed of the motor, multiplying the slope by the estimated torque and adding an offset value to determine a phase current component value associated with the optimal flux level, and applying the determined phase current component value to the motor. |
| US09787234B2 |
Drive controller of instrument
A drive controller of an instrument controls a stepping motor to rotate a pointer of the instrument attached to a rotation shaft of the stepping motor, the pointer rotatable between a zero scale position and a maximum scale position. The drive controller controls the stepping motor to perform a sweeping operation in which the pointer is swung from the zero scale position to the maximum scale position and returned back to the zero scale position, wherein the drive controller controls the stepping motor, during the sweeping operation, to accelerate to a predetermined speed by outputting a rated torque signal to the stepping motor and controls the stepping motor to rotate at the predetermined speed by outputting a decreased torque signal to the stepping motor, the decreased torque signal being lower than the rated torque signal. |
| US09787225B2 |
Hybrid electric device
A device includes a housing configured with a working element and a motor configured for urging motion of the working element. The device further includes a power control module. The power control module is configurable for being in electrical connection with at least one of the motor, a first power source configuration and a second power source configuration. The first power source configuration is configurable for being electrically connected to a battery assembly having a DC power output. The second power source configuration is configurable for being electrically connected to a power inverter, the power inverter configured for receiving an AC power and further configured for outputting a DC power to the second power source configuration. The power control module includes an automatic power selection configuration for automatically selecting the second power source configuration when the second power source configuration receives DC power from the power inverter. |
| US09787224B2 |
Motor control apparatus equipped with protection operation command unit
A motor control apparatus includes a rectifier which converts AC of a power source to DC, an inverter which converts DC to AC for a motor, a voltage amplitude calculation unit which calculates a power source voltage amplitude value, a power failure recovery detection unit which determines whether or not the AC input side has transitioned to a power failure state or a power recovery state on the basis of the power source voltage amplitude value, a protection operation command unit which outputs a protection operation command when a reference time has elapsed from a time point at which the AC input side transitioned to the power failure state, a time measurement unit which measures an elapsed time from when the AC input side transitioned to the power recovery state, and a condition change unit which changes the power failure reference voltage value and/or the reference time. |
| US09787222B2 |
Electrostatic attraction apparatus, electrostatic chuck and cooling treatment apparatus
Provided is an electrostatic attraction apparatus in which a first insulating layer is formed on a base in an electrostatic chuck. A first portion of the first insulating layer extends on a first face of the base and a second portion of the first insulating layer extends on at least a portion of a second face of the base. An attraction electrode is formed on the first portion of the first insulating layer. A second insulating layer is formed on the first portion of the first insulating layer and the attraction electrode. A conductor pattern extends from the attraction electrode and provides a power supply terminal on the second portion of the first insulating layer. A contact part of a terminal member urged by an urging unit is in contact with the power supply terminal. The terminal member is connected with a wiring line connected to a supply power. |
| US09787219B2 |
Modulation policy for modular multi-level converter
A modulation policy for a modular multi-level convertor, determining a switching state of each submodule by combining the current direction of each bridge arm and the capacitor voltage order of the submodules based on a carrier stacking method. The beneficial effects of the modulation policy are that: each phase only needs a modulation wave and N carriers, given N submodules of each upper bridge arm or lower bridge arm of the modular multi-level convertor; the modular multi-level convertor can output N+1 levels without carrier phase shift; N devoted submodules of each phase are guaranteed at any time; and the submodules' capacitor voltage balancing can be controlled without a closed-loop control policy. The modulation policy facilitates adjustment of the modular multi-level convertor voltage and power class, has unlimited number of levels, has a high precision control algorithm, is easy to realize in engineering and saves software and hardware resources. |
| US09787216B2 |
Full-wave rectifier
A full-wave rectifier is disclosed. In one embodiment the full-wave rectifier includes two input paths configured to receive an alternating input voltage, two output paths configured to provide a direct output voltage, and four switched-mode rectifying paths that are connected between each of the input paths and each of the output paths, wherein the switched mode rectifying paths are configured to connect a first input path to a first output path and a second input path to a second output path during a first half wave of the input voltage, and to connect the first input path to the second output path and the second input path to the first output path during a second half wave of the input voltage, and wherein the switched-mode rectifying paths include cascode circuits. |
| US09787213B2 |
Power cell bypass method and apparatus for multilevel inverter
Multilevel inverters, power cells and bypass methods are presented in which a power cell switching circuit is selectively disconnected from the power cell output, and a bypass which is closed to connect first and second cell output terminals to selectively bypass a power stage of a multilevel inverter, with an optional AC input switch to selectively disconnect the AC input from the power cell switching circuit during bypass. |
| US09787212B2 |
Motor drive with silicon carbide MOSFET switches
Motor drive power conversion systems are provided including a rectifier and a switching inverter, wherein the switching devices of the rectifier, the inverter and/or of a DC/DC converter are silicon carbide switches, such as silicon carbide MOSFETs. Driver circuits are provided for providing bipolar gate drive signals to the silicon carbide MOSFETs, including providing negative gate-source voltage for controlling the off state of enhancement mode low side drivers and positive gate-source voltage for controlling the off state of enhancement mode high side drivers. |
| US09787211B1 |
Power converter for AC mains
An AC power converter converts power from an AC power source to an AC load. A DC power holding source is coupled to an input half-bridge switch, a common half-bridge switch and an output half-bridge switch. A controller is coupled to at least two of the input half-bridge switch, the common half-bridge switch, and an output half-bridge switch. The controller switches the input half bridge at the first switching frequency in boost mode and at the line frequency in buck mode. The controller also switches the output half bridge switch at the first switching frequency in buck mode and at the line frequency in boost mode. Input and output low pass filters can eliminate switching frequency energy from entering the AC source and load. The converter maintains a DC power holding source voltage slightly above peak AC input voltage and significantly less than twice the peak AC input voltage. |
| US09787210B2 |
Precharging apparatus and power converter
Precharging systems and methods are presented for precharging a DC bus circuit in a power conversion system, in which precharging current is connected through a precharging resistance coupled between only a single AC input line and the DC bus circuit when the DC bus voltage is less than a non-zero threshold, and a controller individually activates controllable rectifier switching devices when the DC bus voltages greater than or equal to the threshold using DC gating or pulse width modulation to selectively provide a bypass path around the precharging resistance for normal load currents in the power conversion system. |
| US09787209B2 |
Modular three phase on-line ups
An uninterruptible power supply system (UPS) includes an interconnect circuit configured to receive three-phase AC input power from an AC power source and a plurality of UPS subsystems each coupled to the interconnect circuit. A first UPS subsystem includes first and second single-phase AC-to-DC converters. At least one second UPS subsystem includes third and fourth single-phase AC-to-DC converters. In a first mode of operation, the interconnect circuit is configured to conduct at least one phase of the AC input power to the first UPS subsystem and at least one phase of the AC input power to the second UPS subsystem, and, in a second mode of operation, to disconnect the AC input power from the first UPS subsystem and to conduct at least one phase of the AC input power to the second UPS subsystem. |
| US09787208B2 |
Single phase AC chopper for high current control of complex and simple loads
A testing device is provided. The testing device comprises a processor and a switching AC to AC power converter that has no DC link. The processor is configured to set a plurality of bi-directional switches in the power converter in a configuration of on/off states that cause a substantially set electric current to flow through a component being tested by the testing device. |
| US09787207B2 |
Electric machine and use thereof
An electric machine is selectively operated as a transformer for AC voltage operation or as a throttle system for DC voltage operation. A transformer core has two limbs. An additional winding with a first additional partial winding is wound around a first limb and a second additional winding is wound around the second limb. A higher-voltage winding with a first higher-voltage partial winding is wound around the first additional partial winding and a second higher-voltage partial winding is wound around the second additional partial winding. A first traction winding is wound around the first higher-voltage partial winding and a second traction winding is wound around the second higher-voltage partial winding. A first DC voltage winding may be wound around the first traction winding and a second DC voltage winding may be wound around the second traction winding. |
| US09787205B2 |
Power source device and image forming apparatus
A power source device includes a transformer, a first switching element and a second switching element, a resonance capacitor, and a switch. One end of the second switching element is connected with one end portion of a primary winding. The other end of the second switching element is connected with one end portion of the resonance capacitor. The primary winding and the resonance capacitor are resonated with each other by alternately operating the first and second switching elements to supply electric power to a load connected with a secondary winding of the transformer. The primary winding includes a first primary winding and a second primary winding. Depending on the load, the switch connects or disconnects between the first primary winding and the resonance capacitor, or connects or disconnects between the second primary winding and said resonance capacitor. |
| US09787204B2 |
Switching power supply device
A drive control circuit for a switching power supply device. The drive control circuit includes an output control circuit configured to generate an output control signal with a pulse width corresponding to an output voltage of the switching power supply device, a threshold setting circuit configured to determine a winding threshold voltage according to a direct current input voltage applied to the series resonant circuit formed of the leakage inductance of an isolation transformer and a capacitor of the switching power supply device, a winding detection circuit configured to compare a voltage generated in a tertiary winding of the isolation transformer with the winding threshold voltage and to accordingly output a winding detection signal, and a drive circuit configured to receive the winding detection signal and the output control signal, and to generate a pulse-width controlled drive signal for driving a first switching element of the switching power supply device. |
| US09787198B1 |
Systems and methods with prediction mechanisms for synchronization rectifier controllers
System controller and method for regulating a power converter. For example, the system controller includes a first controller terminal and a second controller terminal. The system controller is configured to receive, at the first controller terminal, an input signal, generate a drive signal based at least in part on the input signal, and output, at the second controller terminal, the drive signal to a switch to affect a current associated with a secondary winding of the power converter. The system controller is further configured to detect a first duration of a demagnetization period associated with the secondary winding based at least in part on the input signal, determine a second duration of a time period for the drive signal based at least in part on the first duration, and keep the drive signal at a first logic level during the entire time period. |
| US09787197B2 |
Switching power supply unit
A switching power supply unit includes input terminals, output terminals, first to third primary windings and first to third secondary windings, a switching circuit, a rectifying smoothing circuit, and a driver. In the switching circuit, first and second switching devices, third and fourth switching devices, and first and second capacitors, coupled in series to one another, are disposed in parallel between the input terminals. In the rectifying smoothing circuit, first to third arms, each having two of rectifying devices disposed in series, are disposed in parallel between the output terminals, the first secondary winding is coupled between the first and the second arms to form an H-bridge coupling, the second and the third secondary windings are coupled between the second and the third arms to form an H-bridge coupling, and a choke coil is disposed between the first to the third arms and an output capacitor. |
| US09787194B2 |
Primary side regulated isolation voltage converter
A primary side regulated isolation voltage converter. The primary side regulated isolation voltage converter comprises a control module and a ripple control circuit. The control module receives the voltage feedback signal and determines whether the isolation voltage converter operates in a light load state. When the isolation voltage converter operates in a light load state, the ripple control circuit senses the ripple of an output voltage signal to generate a ripple signal, and compare the ripple signal with a ripple threshold. When the ripple signal is larger than the ripple threshold, the isolation voltage converter jumps out the light load state. |
| US09787192B2 |
Power-supply circuit, related transmission circuit, integrated circuit, and method of transmitting a signal
A power-supply circuit includes a transformer with primary and secondary windings, and an energy accumulator on the secondary winding. A circuit monitors the secondary winding and generates a feedback signal that is transferred by a transmission circuit through the secondary winding by selectively transferring energy from the energy accumulator. The transmission circuit includes: a) an electronic switch having a control terminal; and b) a driver circuit for driving the electronic switch. The driver circuit includes a charge-accumulation capacitor connected to the control terminal, and a charge circuit configured to draw energy from the secondary winding and charge the charge-accumulation capacitor. |
| US09787189B1 |
Multiphase DC power supply with high switching frequency
A multiphase DC power supply with high switching frequency of 1 MHz comprising three parallel connected three phase DC power supply. Each of the d parallel connected three phase DC power supply comprises a boost power factor corrector to convert an AC power source to a rectified and filtered DC voltage, an isolation transformer connected to the boost power factor corrector to generate a full wave rectified DC voltage having stable voltage level, a duck switching circuit consisting a first, a second and a third semiconductor switches to regulate the voltage level of the output of said isolation transformer and a phase controller to manage an interleaved phase of the output of said three semiconductor switches. The multiphase DC power supply uses interleaved power factor correction technology to successfully provide a DC power supply with high switching frequency, low ripple noise and not subject to EMI. |
| US09787186B2 |
Area-friendly method for providing duty cycle inverse to supply voltage
An illustrative converter embodiment employs an oscillator comprising a capacitor and a comparator. The capacitor is alternately coupled to a charging current source and a discharging current source, the charging current source operating to charge the capacitor at a first rate and the discharging source operating to discharge the capacitor at a second rate. The comparator asserts an output signal when the capacitor charges to a first threshold voltage and deasserts the output signal when the capacitor discharges to a second threshold voltage. The first rate may be proportional to the input voltage and the second rate may be fixed. The output signal may be applied to the gate of a transistor to alternately apply the input voltage across an inductor and to apply current from the inductor to a capacitance. The duty cycle of the output signal is inversely proportional to the input voltage, or at least approximately so. |
| US09787183B2 |
Driver and driving control method for power converter
A driver and a driving control method for a power converter are provided. The driver includes a level shift circuit, a negative voltage generator and a first PMOS transistor. The level shift circuit provides an output signal, wherein the output signal has a first operation voltage and a second operation voltage. When the output signal received by the negative voltage generator is the first operation voltage, the negative voltage generator outputs the first operation voltage. When the output signal received by the negative voltage generator is the second operation voltage, the negative voltage generator generates and outputs a third operation voltage, and the third operation voltage is lower than the second operation voltage. A control terminal of the first PMOS transistor is coupled to an output terminal of the negative voltage generator. An output terminal of the first PMOS transistor provides a driving voltage. |
| US09787182B2 |
Self-adaption current control circuit
A self-adaption current control circuit includes: a regulating transistor, a first sampling comparison circuit, a proportion control circuit, a variable sampling resistor, and a second sampling comparison circuit. The self-adaption current control circuit adjusts the resistance value of the variable sampling resistor and the coefficient of the proportion circuit simultaneously through the proportion control circuit. Meanwhile, the resistance value of the variable sampling resistor and the coefficient of the proportion circuit can be increased or decreased in the same proportion so that the input voltage of a second sampling comparison circuit can be in an appropriate input range. |
| US09787176B2 |
Charge pump
In a charge pump circuit, a first circuit is configured to provide a first node with a first first-voltage level or a first second-voltage level. A second circuit is configured to provide a second node with a second first-voltage level or a second second-voltage level. The first node is coupled with a first end of the first capacitive element. The second node is coupled with a first end of the second capacitive device. A first end of the first voltage transfer circuit is configured to receive an input voltage. A second end of the first voltage transfer circuit is coupled with a second end of the first capacitive device and a first end of the second voltage transfer circuit. A second end of the second voltage transfer circuit is coupled with a second end of the second capacitive element. |
| US09787172B2 |
Methods and systems for implementing adaptive FET drive voltage optimization for power stages of multi-phase voltage regulator circuits
Methods and systems are disclosed that may be employed to implement adaptive FET drive voltage optimization for voltage regulator (VR) integrated power stages (IPstages) that have different MOSFET RDS(on) characteristics to improve VR efficiency and current-sense accuracy. |
| US09787169B2 |
Electromagnetic actuators and component designs therefor
An embodiment of an electromagnetic actuator, such as a moving magnet actuator (MMA), includes a back iron, a first coil winding, a second coil winding, a mover, and a permanent magnet. The first and second coil windings are connected to the back iron, and have generally annular shapes. The mover moves relative to the back iron during use of the MMA. The permanent magnet is connected to the mover and moves with the mover during use of the MMA. The permanent magnet has a generally annular shape. |
| US09787167B2 |
Oscillating motor for a personal care appliance
An oscillating motor suitable for use with a personal care appliance is provided. The oscillating motor is configured with a reduced motor envelope as compared to conventional motors in order to be suitable for personal care appliances with smaller handles. |
| US09787164B2 |
Electrical machine having a rotor for cooling the electrical machine
The invention relates to an electrical machine (1, 51), in particular an asynchronous machine, comprising a stator (2), a rotor (4) which is rotatably mounted about a rotation axis (3) and magnetically interacts with the stator (2) during operation of the electrical machine (1, 51), a shaft (5) on which the rotor (4) is fixed and which has an axial hole (6), and an inflow element (7, 47) which extends into the axial hole (6) such that a coolant (15), in particular a cooling liquid (15), can flow into the axial hole (6) from the inflow element (7, 47). The invention also relates to a cooling system (50) comprising an electrical machine (1, 51) and a coolant circuit (55) for transporting the coolant (15), in particular the cooling liquid (15), through the axial hole (6), and to a vehicle (61) comprising a cooling system (50). |
| US09787163B2 |
Rotor of an electrical machine and electrical machine
A rotor (2) of an electrical machine (60) has a laminated rotor core (4). A fan (18), which is arranged at the end face in the laminated rotor core (4) is provided for cooling purposes. The fan has a fan blade (21) and a supporting element (20) for the fan blade (21), wherein the fan blade (21) extends by way of a first section (31) beyond the supporting element (20) in a first axial direction and extends by way of a second section (33) beyond the supporting element (20) in a second axial direction (34) which is opposite the first axial direction (32). |
| US09787162B2 |
Vibration power generator
The vibration power generator includes: a plurality of permanent magnets (1, 2) integrated together to have given inter-magnet gaps under a state in which the same poles of the permanent magnets are opposed to each other; and a plurality of coils (3, 4) arranged on respective outer peripheries of the plurality of permanent magnets so as to have a distance from the plurality of permanent magnets, and is configured to generate an electric power through relative movement of the plurality of permanent magnets and the plurality of coils. A relationship between a length of the opposed coils and a length of the permanent magnet is set so that the length of the coils is larger than the length of the permanent magnet and equal to or smaller than a sum of the length of the permanent magnet and a length of the inter-magnet gap. |
| US09787157B2 |
Actuator device and method of converting rotational input to axial output with rotary flexure mechanism
An actuator device includes a motor and a reduction device operatively coupled to the motor and oriented about a central axis, the reduction device configured to modify an input angle of rotation provided by the motor to an output angle of rotation. Further included is a rotary flexure mechanism that includes a rotary flexure operatively coupled to an output portion of the reduction device. The rotary flexure mechanism also includes a plurality of flexure blades coupled to the rotary flexure, each of the flexure blades angularly oriented from the central axis. The rotary flexure mechanism further includes a diaphragm flexure pair operatively coupled to the flexure blades, wherein the diaphragm flexure comprises a rotational and in-plane stiffness greater than an axial stiffness resulting in the rotary flexure mechanism being configured to convert a rotational input to an axial translation. |
| US09787156B1 |
Energy storage apparatus for storing electrical energy generated by an energy source
A system for storing electrical energy generated by an external energy source that includes a ring for storing kinetic energy of rotation, an assembly a control system, and at least two motors/generators. The assembly includes a plurality of independent supports, each releasably attachable to a levitation electromagnet such that pole faces of the levitation electromagnet oppose a top protruding surface of a levitation rail of the ring and each releasably attachable to a centering electromagnet such that pole faces of the centering electromagnet oppose a surface of the centering rail of the ring. The control system supplies current to each levitation electromagnet to generate vertical forces to levitate and vertically stabilize the ring and to each centering electromagnet to generate radial forces to center and horizontally stabilize the ring. At least two of motor/generators electromagnetically engage a reaction rail of the ring and impose a reversible torque on the ring to enable bi-directional transfer of electrical energy from the energy source to the ring in the form of kinetic energy of rotation of the ring, and subsequent recovery of electrical energy from the kinetic energy of rotation of the ring. |
| US09787155B2 |
Stator system for an electric motor
A stator system for an electric motor has multiple coil formers and stator windings that are wound on the coil formers. The stator windings are distributed over the circumference of the stator system and are arranged to form a substantially circular stator star. A number of the stator windings are electrically insulated in the axial direction in each case by way of a phase separator. The stator windings in each case of two coil formers are electrically connected as a coil pair in an electrically conductive manner by a conductor track. The conductor track is retained by a separating web that is arranged in the axial direction above the allocated phase separator and that extends in a radial direction. |
| US09787154B2 |
Electric motor with Halbach array and ferrofluid core
An electric motor apparatus is described that utilizes a Halbach array and a ferrofluid core. The electric motor comprises a rotor assembly and a stator assembly, each of which utilizes a Halbach array. A ferrofluid core is utilized in the stator, which results in a motor that is less susceptible to core loss and operates with increased efficiency. |
| US09787148B2 |
Motor
A rotor of a motor includes first and second rotor cores, a field magnet, and a commutator magnet. The first and second rotor cores each include a core base and a plurality of claw poles. The claw poles of the first rotor core and the claw poles of the second rotor core are alternately arranged in a circumferential direction. The field magnet is located between the core bases. The field magnet is magnetized in an axial direction so that the claw poles of the first rotor core and the claw poles of the second rotor core function as different magnetic poles in the circumferential direction. The commutator magnet is located on an outer circumference of the field magnet around the claw poles. The commutator magnet is magnetized so that surfaces having the same polarity face each other between the claw poles and the commutator magnet. |
| US09787129B2 |
System for displaying products
A display system for displaying an electronic device is disclosed. The display system includes a cup disposed in an aperture of a tray with a charging fixture disposed therein. The charging fixture includes a charging element for magnetically attaching to an electronic device and providing power to the electronic device. |
| US09787128B2 |
Wireless charger and wireless charging method
A wireless charger includes a wireless charging transmitter. The wireless charging transmitter includes a transmission antenna, a driving circuit, a transmission temperature sensor, and a controller. The driving circuit can output a charging signal in a fast charging mode initially. The transmission temperature sensor can detect a transmission temperature value of the transmission antenna. The controller can receive the transmission temperature value from the transmission temperature sensor. The driving circuit is can output the charging signal in a fast charging mode initially. When the transmission temperature value is greater than an overheat value, the controller can control the driving circuit to output in a slow charging mode. |
| US09787127B2 |
Door lock with a wireless charging device
A door lock mounted to a door includes a latch head. A receiver includes a charging circuit and is mounted to the door. A battery provides electricity required for moving the latch head between a latching position and an unlatching position or providing electricity required for permitting or not permitting movement of the latch head from the latching position to the unlatching position. A transmitter includes a wireless transmitting circuit and is mounted to a door frame to which the door is pivotably mounted. The transmitter is connected to a power supply. When the door is in an open position, the receiver is not aligned with the transmitter. When the door is in a closed position, the receiver is aligned with the transmitter, the receiver receives a radio wave from the transmitter, converts the radio wave into electricity, and stores the electricity in the battery. |
| US09787125B2 |
Battery management system and method of driving the same
A battery management system and a method of driving the same are provided. When the output signal of a charger is higher than a first voltage, a battery cell is charged with a first current by a first charge circuit. When the output signal of the charger is higher than a second voltage, a battery cell is charged with a second current by a second charge circuit. The second voltage is higher than the first voltage and second current is higher than the first current. |
| US09787120B2 |
Usb charger, mobile terminal and charging method thereof
A USB charger, a mobile terminal, and a charging method are provided. The USB charger for charging a mobile terminal, includes a first logic control unit through which bidirectional communication is established between the USB charger and the mobile terminal, wherein the first logic control unit is configured to: send, to the mobile terminal, a first signal which includes a maximum output capability of the USB charger; receive, from the mobile terminal, a second signal which indicates magnitude of a voltage requested by the mobile terminal; and adjust a voltage output from the USB charger to be consistent with the voltage requested by the mobile terminal. Accordingly, the USB charger and the mobile terminal can communicate with each other through a single signal wire. Thus, the voltage output from the USB charger can be intelligently controlled, so as to charge the mobile terminal in a fast, safe, and simply way. |
| US09787118B2 |
Simple and high efficiency balancing circuits and methods for hybrid batteries
A balancing circuits and methods for hybrid batteries having two different rechargeable batteries that are coupled in series includes coupling a fuel gauge to each battery to determine the state of charge of each battery, comparing the state of charge of the two batteries, and if the state of charge of the two batteries is more than a predetermined difference, then enabling a switching converter to source current to a node between the batteries or to sink current from the node between the batteries, as required to tend to equalize the state of charge of the two batteries. Otherwise, if the state of charge of the two batteries is equal within a predetermined allowance, then disabling the switching converter. |
| US09787115B2 |
Universal serial bus adaptor and universal serial bus cable
A universal serial bus (USB) adaptor supplies a large charging current to charge a device. The USB adaptor includes a voltage conversion circuit, a USB interface, a current detection circuit, a first switch, a second switch, and a third switch. The USB interface includes a power pin, a first data pin, a second data pin, and a ground pin. The current detection circuit detects a charging current of the device, and converts the charging current into a voltage to compare the charging current with a reference voltage to output a comparison signal. The first switch, the second switch, and the third switch control connection relationships between the power pin and the first data pin, the first data pin and the second data pin, and the second data pin and the ground pin according to the comparison signal, respectively. A USB cable is also provided. |
| US09787113B2 |
Charging apparatus for mobile device and multi-station charging apparatus using the same
Charging apparatuses are provided for charging mobile devices while sterilizing the mobile devices via UV illumination. Such a charging device can include a charging apparatus case having a slot structured to receive a mobile device. The front and rear surfaces of the mobile device are exposed to inner walls of the slot; and at least one UV light source can irradiate UV light onto the front and rear surfaces of the mobile device, which are exposed to the inner walls of the slot. |
| US09787112B2 |
Inter-protocol charging adapter
An inter-protocol charging adapter for equipment to be charged via a bus includes: first connectors corresponding to a first charging protocol that requires the bus to be energized before the equipment closes onto the bus; second connectors corresponding to a second charging protocol that does not energize the bus before the equipment closes onto the bus; and a boost converter coupled to the bus and to at least one of the second connectors, wherein the boost converter uses energy from the second connector to energize the bus before the equipment closes onto the bus. |
| US09787110B2 |
USB power supply
A power supply system effective to provide power to a plurality of different personal electronic devices includes a source of AC or DC power, a power converter effective to convert the AC or DC power to a useable voltage and amperage, a remote power outlet or a plurality of remote power outlets each configured to receive one or more connectors and a signal decoder. The signal decoder determines the requirements of a connected one of the personal entertainment devices and personal computing devices and apply the requirements to the power outlet for powering the device. |
| US09787109B2 |
Battery pack
A battery pack includes a battery pack housing defining an interior region with first and second interior spaces and an intermediate space. The battery pack housing includes inlet and outlet apertures communicating with the first and second interior spaces, respectively. The battery pack has a battery module disposed in the first interior space having a first battery cell and a heat exchanger. The heat exchanger defines a first flow path portion therethrough. The battery pack has a fan assembly disposed in the intermediate space having a first electric fan, and a thermally conductive housing disposed in the second interior space that defines a second flow path portion. The first electric fan urges air to flow through the inlet aperture, the first flow path portion, a portion of the first electric fan, the second flow path portion, and the outlet aperture. |
| US09787108B2 |
Enhanced battery management system
A battery management system and a method for enhanced battery management of a battery containing a number of cells. The method and system measures the cell capacity of two or more of said cells, ranks the cells in order of their cell capacity values and calculates a value for a cell specific supporting current for the measured cell, for a given load, based upon the ranked cell capacity values. Calculated cell specific currents are then provided to the cells. |
| US09787101B2 |
Bidirectional conversion architecture with energy storage
An electrical system for an aircraft with an electric taxi system (ETS), the electrical system may include at least one traction motor, a DC link and at least one traction-motor bidirectional DC-AC converter interposed between the at least one traction motor and the DC link. An engine-driven power source may be configured to provide DC power to the DC link or extract DC power from the DC link. A battery unit may be configured to provide DC power to the DC link or extract DC power from the DC link. An adaptive power controller may be interconnected with the power source, the battery unit and the at least one traction-motor bidirectional DC-AC converter and configured to regulate voltage of DC power delivered to the DC link. |
| US09787097B2 |
Electric power supply network linked to a transport system
An electric power supply network includes at least one connection point with an upstream electrical network delivering useful power to at least one input of a first electric power supply network of an electrically powered transport system, such as trolley buses, trams, metro, train, or other transport, the first electrical network presenting peak power fluctuations as a function of variable energy needs depending on traffic associated with the transport system. The first electrical network includes at least one power output capable of distributing energy, in particular recovered from the transport system and from the upstream electrical network, to at least a second electrical network, enabling energy to be supplied to electrical consumption points. At least one supervision unit monitors distribution of energy from the power output whenever at least the peak power required by the first transport system is below the useful power available upstream. |
| US09787092B2 |
Aircraft power management system and method for managing power supply in an aircraft
An aircraft power management system includes an electrical power supply input configured to be coupled to an electrical power supply, a first power supply bus bar coupled to the power supply input, at least one primary electrical equipment including a primary load coupled in parallel to the first power supply bus bar, a bus bar switch configured to selectively deactivate the first power supply bus bar downstream of the at least one primary electrical equipment, a load monitoring device configured to monitor the power demand of the primary load and to output a deactivation signal to the bus bar switch for selectively deactivating the first power supply bus bar, if the monitored power demand of the primary load exceeds a primary threshold, and at least one tertiary electrical equipment including a tertiary load coupled to the first power supply bus bar downstream of the at least one primary electrical equipment. |
| US09787091B2 |
Systems and methods for controlling a power conversion system
Systems and methods for controlling a power conversion system are provided. The power conversion system includes a power converter comprising a primary stage coupled to a secondary stage to generate an output direct current (DC) voltage from an input voltage received from an input voltage source. The power conversion system also includes a control circuit coupled to the power converter. The control circuit is configured to implement a self-adjusting set-point control algorithm to generate the output DC voltage without using an input voltage measurement, wherein the output DC voltage follows the input voltage over at least a portion of an input voltage range. |
| US09787087B2 |
Systems and methods for discharging an input capacitance
An electronic device including first and second line inputs, first and second device inputs, a filter circuit, and a switching circuit. The filter circuit has a first input electrically coupled to the first line input, a second input electrically coupled to the second line input, a first output electrically coupled to the first device input, a second output, and at least one capacitor electrically coupling at least one of the first input to the second input or the first output to the second output. The switching circuit has a control input to receive a control signal, and electrically couples the second output to the second device input in response to the control signal having the first state and electrically couples the second output to one of the first input and the first output through a resistor in response to the control signal having the second state. |
| US09787081B2 |
Overvoltage notching of electrical swells
To protect a connected electrical load from anomalous electricity, an apparatus has a condition sensing unit configured to distinguish a power event type from among power event types from characteristics of an input electricity waveform accepted through an input port. The condition sensing unit indicates the power event type when a corresponding overvoltage criterion is met by characteristics of the input electricity waveform. A power control unit generates, responsive to a power event, a modulation signal that defines at least one amplitude notch in the input electricity waveform in accordance with the power event type. A switching mechanism electrically interposed between the input port and the output port transitions into conducting and non-conducting states in accordance with the modulation signal to superimpose the notch on the input electricity waveform. |
| US09787076B2 |
Telescopic device having carrier member, carrier member, and cable thereof
A carrier member includes a first section, a second section, and a third section. The first section has a first length. The second section has a second length. The first section, the third section, and the second section connect sequentially and form a U-shaped structure. The first section and the second section have curved sections. The third section has a flat section. When the second section moves relative to the first section, the first section or the second section having the curved section transform into the third section having the flat section and store a resilient recovering force, and the third section having the flat section transforms into the first section or the second section having the curved section for adjusting lengths of the first section and the second section, which prevents a cable disposed on the carrier member from interfering with other mechanism or getting knotted. |
| US09787074B1 |
Electric junction box assemblies with access hood
Electric junction box assemblies with an access hood for providing access to an eyelet terminal is provided. The electric junction box assembly includes a junction box configured to store electric components. The junction box includes an eyelet terminal support configured to support an eyelet terminal connection. A top cover is mounted onto the junction box. The top cover includes a first cut-out and a hood mounting structure. A hood is shaped so as to both engage and disengage the hood mounting structure and cover the eyelet terminal opening. In one instance the closing member of the hood is configured to engage the hood mounting structure so as to cover the eyelet terminal connection. In another instance, the hood may be disengaged so as to expose the eyelet terminal connection without having to remove the cover from the junction box. |
| US09787067B2 |
Vacuum circuit breaker
Disclosed herein is a vacuum circuit breaker. In some embodiments, a vacuum circuit breaker includes a cradle having a rail which forms a travel route; a main body being movably mounted to the cradle and configured to be in a test position or in an operation position; a wheel traveling along the travel route and configured to move the main body to the test position or the operation position; an interlock plate provided in the main body so as to move together with the main body; and a ground interlock device restraining the movement of the main body by restraining the movement of the interlock plate when grounded. |
| US09787065B2 |
Ionizer for adding negative ions to air, for example to air inside a motor vehicle, and method of operating same
An ionizer for charging air in a motor vehicle with negative ions. The ionizer has an emitter with a pair of spaced electrodes, a high-voltage power supply, means connecting the power supply to the electrodes to apply a voltage differential across them and thereby ionize gas molecules adjacent the electrodes, and a sensor between the power supply and the electrodes for measuring current passing between the electrodes. |
| US09787064B2 |
Corona ignition with hermetic combustion seal
A corona igniter (20) comprises a central electrode (22) surrounded by an insulator (24), which is surrounded by a metal shell (26). A ceramic combustion seal (30) is disposed along the gap (32) between a shell lower end shell (52) and the insulator nose region (48) to provide a hermetic seal therebetween. The ceramic combustion seal (30) is typically a bushing, cylinder, or ring formed of sintered alumina. A glass material or glass/ceramic mixture (60) typically adheres the ceramic combustion seal (30) to the shell (26) and the insulator (24). Alternatively, the ceramic combustion seal (30) is brazed to the shell (26), and the glass material or glass/ceramic mixture (60) adheres the ceramic combustion seal (30) to the insulator (24). |
| US09787056B2 |
Method, apparatus, optical component and optical network system for controlling operating temperature of optical component
The present invention discloses a method, an apparatus, an optical component and an optical network system for controlling an operating temperature of an optical component. The method includes: acquiring an external ambient temperature of the optical component; setting a target control temperature of a temperature controller according to the external ambient temperature, where the target control temperature is a function value of the external ambient temperature, and the target control temperature is within a range from an operating temperature lower limit of a laser to an operating temperature upper limit of the laser; and controlling, according to the target control temperature, an operating temperature of the optical component by means of heating or cooling by using the temperature controller. |
| US09787045B2 |
Disconnect device
A method for installing a wedge connector positioned between two conductive cables includes connecting a head coupler portion of a disconnect assembly to a wedge frame, wherein the head coupler portion includes an extension rod within a longitudinal bore; positioning the wedge frame and a first end of the extension rod against the wedge connector; connecting the head coupler portion to a tool coupler portion of the disconnect assembly, wherein the tool coupler portion is connected to a hydraulic drive tool that includes a ram; causing the hydraulic drive tool to apply force to a second end of the extension rod, wherein applying the force to the second end causes the first end to apply force to the wedge connector; and disconnecting the head coupler portion from the tool coupler portion. |
| US09787035B1 |
Electrical plug connector for vehicle
The present disclosure relates to an electrical plug connector, such as a high-voltage plug connector, for a vehicle. The plug connector comprises a plug with a plug casing, one or more electrical contact parts accommodated in the plug casing, a socket with a socket casing, and a protective housing at least partly encasing the plug casing and the socket casing. The protective housing comprises an attachment flange in a connection area reaching up to a counterpart connectable thereto. An engagement ridge of the protective housing is spaced apart from the attachment flange in the longitudinal direction L of the plug connector and at least positively engages in an engagement channel of the plug casing. |
| US09787031B2 |
Electrical connector with adjusted impedance
An electrical connector system with adjusted impedance is described herein. The electrical connector system includes a cable having at least two conductors and a shell element provided at least partially around the cable. Further, the electrical connector system includes a connector housing assembly that is separate from the shell element and is configured to at least partially receive the two conductors and the shell element. |
| US09787028B2 |
Improving signaling performance in connector design
Apparatus and methods of arranging ground pins and signal pins in a card connector includes arranging a signal pins and ground pins in a card connector into at least six (6) columns divided between a primary side and a secondary side of the connector. |
| US09787027B2 |
Power plug connector can be plugged in both normal and reverse way
A power plug connector capable of being plugged in both normal and reverse way, comprising an insulator, a soft tongue plate, a plurality of first terminals and second terminals, and a shielding case; by fixing the soft tongue upon the insulator, the front end of the soft tongue being suspended inside the insertion slot; every rear end of the second terminals respectively connected with the corresponding rear ends of the first terminals; When plug normally, the power plug connector can be smoothly plugged-in, and the first terminals contacts the power socket connector; When plug reversely, the soft tongue plate will bend which allows the product to continue inserting, so the multiple terminals can connect the power socket connector and conducts, thereby realizing normal and reverse plug and avoiding wear and damage to the power plug connector. |
| US09787025B2 |
Active cover plates
In one example, a cover plate for an electrical receptacle may include a face plate, an engaging feature disposed on the face plate, and a spring clip, wherein the engaging feature disposed on the face plate engages with the spring clip and secures the spring clip in at least two different positions with respect to the face plate. |
| US09787024B2 |
Lever-type connector
A lever (40) is formed with resilient arms (48) cantilevered in a direction substantially perpendicular to rotary shafts (15) of the lever (40) and intersecting with a circumferential direction about the rotary shafts (15), and locking projections (49) projecting from extending end parts of the resilient arm pieces (48) and configured to hold the lever (40) at an initial position by entering locking holes (20) and being locked. The locking hole (20) is formed with a locking edge part (21) located on a surface of a housing (10) facing the lever (40) and configured to lock the locking projection (49) and a recess (23) formed by recessing an inner surface part on a deeper side than the locking edge part (21), and the locking projection (49) is formed with a hooking portion (53) configured to enter the recess (23) while being locked to the locking edge part (21). |
| US09787019B2 |
Electrical connector with a mobile skirt
An element making up the body of an assembly providing a connection, consisting of a first element making up the connection module (1) and a second element making up the body (2); the module comprising a lower housing (4) destined to be received in a lower housing or at the body base (5) to make the connection; an elastomeric inter-housing gasket intended to form a seal between the lower housing and the base set on the module's lower housing upper edge rim, and a ring (9) making up a skirt that is set to be removable in the direction of insertion of the module into the base around the module; the skirt, which can be placed in such a way as to cover the gasket, and in such a way as to leave the gasket exposed, wherein the body comprises the translation means intended to allow the ring making up the skirt to move into the position where it will not cover the gasket when the module is inserted into the body. |
| US09787016B2 |
Electrical connector system comprising a housing and a selector outlet
The invention regards a plug comprising a housing, a number of connectors and a selector outlet having a movable selector part whereby the configuration of the connectors may be changed when the selector part is moved. The housing may have a triangular cross section defined by a first side A, a second side B and a third side C and where the number of connectors allows for connection of two or more electrical circuits. The invention also relates to a system of plugs and a method of producing the same. |
| US09787015B2 |
Electrical connector with separable contacts
A contact sub-assembly is provided for an electrical connector. The contact sub-assembly includes a printed circuit and an array of mating contacts. Each mating contact includes a terminating end portion and a mating interface. The contact sub-assembly also includes an array of circuit contacts that is discrete from the array of mating contacts. Each circuit contact is engaged with and electrically connected to the printed circuit. Each circuit contact is separably engaged with and electrically connected to the terminating end portion of a corresponding one of the mating contacts such that the array of circuit contacts electrically connects the array of mating contacts to the printed circuit. |
| US09787013B2 |
Connector having a moving plate
A connector comprises a housing, a plurality of contacts, a slide plate, and a moving plate. The contacts are configured to make contact with a plurality of contact pads of a mating connector. The slide plate has a cam face composed of a pattern of projections and recesses and expanding in a direction intersecting with the mating direction. The moving plate expands in an overlapping manner with the slide plate and receives an action of the cam face caused by the sliding of the slide plate. The moving plate moves toward the mating connector and pushes the contacts onto the contact pads of the mating connector. |
| US09787009B2 |
Receptacle connector having an insulating tongue with a combining area for accommodating combining portions of a plurality of contacts
An electrical receptacle connector includes a shell, a first insulator, a second insulator and a blanking contact. The first insulator is disposed in the shell. The first insulator has a first insulator front end and a first insulator rear end. The second insulator is disposed in the shell and installed on the first insulator. The second insulator has a combining area. The blanking contact includes a fixing portion, a soldering portion, a contact portion and a combining portion. The fixing portion is combined with the first insulator. The soldering portion protrudes from the fixing portion toward the first insulator rear end and stretches out of the first insulator rear end. The contact portion protrudes from the fixing portion toward the first insulator front end and stretches out of the first insulator rear end. The combining portion protrudes from the contacting portion and inserts into the combining area. |
| US09787008B2 |
Cable end connector and method making the same
A USB cable end connector and the method of making the same are disclosed. The cable end connector includes a first contact module, a second contact module, a central grounding unit sandwiched between the two contact modules, a shielding shell enclosing the first and the second contact modules; and a grounding means attached to the first and the second contact modules along a height direction of the connector. The grounding means includes an upper grounding pad and a lower grounding pad. The upper grounding pad and the lower grounding pad are assembled to a first and a second insulators of the contact modules along a height direction, respectively. The upper grounding pad is sandwiched between the first contact module and the shielding shell. The lower grounding pad is sandwiched between the second contact module and the shielding shell. |
| US09787006B2 |
Cable termination for connecting a switchgear assembly to a high-voltage cable
A cable termination comprises, amongst other things, three insulated cable connection elements which project into a housing and have an internal conductor, and also three phase connection parts which are designed as hollow bodies and likewise project into the housing from a side which is situated opposite the cable connection elements and into each of which one of three cable end reinforcements can be inserted. The cable connection elements and the phase connection parts each form the corners of a triangle. These triangles are rotated in relation to one another in their respective plane, so that an offset is created. In order to bridge the offset, a connecting element is arranged between in each case one cable connection element and the associated phase connection part, the said connecting element being designed such that it can be partially or entirely removed in order to establish an isolating gap. |
| US09787001B2 |
Terminal fitting and wire with terminal fitting
A terminal fitting includes a soldering portion (11) to which a conductor (91) of a wire (90) is to be soldered, solid solder (60) for soldering the conductor (91) to the soldering portion (11) in a solid state, and a holding portion (20) that holds the solid solder (60) until the solid solder (60) is melted and the conductor (91) is soldered. The conductor (91) is connected to the soldering portion (11) by melting the solid solder (60) held in the holding portion (20). |
| US09787000B2 |
Beamforming array antenna control system and method for beamforming using the same
A control system connected to a plurality of array antenna performs beamforming. The control system comprises a beam radiation controller for requesting a predetermined first antenna group to radiate beams and requesting a second antenna group including the first antenna group to radiate beams to an optimized sector, a beam receiver for receiving response beams from the first antenna group and the second antenna group, and a sector selector for setting up an optimized sector based on the received beams for the first antenna group, and transmitting information on the optimized sector to the beam radiation controller in order to control the second antenna group to radiate beams to the optimized sector. |
| US09786999B2 |
Over-the-air test
A testing system optimizes a cost function of a theoretical spatial cross correlation and a spatial correlation obtained with antenna elements for determining weights of the antenna elements, and forms a beam of a signal of at least one path of a simulated radio channel with at least two antenna elements of a plurality of antenna elements coupled to an emulator in an anechoic chamber. The at least two antenna elements are capable of polarizing the beam in a known manner. |
| US09786997B2 |
Wireless access point in pedestal or hand hole
Novel tools and techniques are provided for implementing antenna structures to optimize transmission and reception of wireless signals from ground-based signal distribution devices, which include, but are not limited to, pedestals, hand holes, and/or network access point platforms. Wireless applications with such devices and systems might include, without limitation, wireless signal transmission and reception in accordance with IEEE 802.11a/b/g/n/ac/ad/af standards, UMTS, CDMA, LTE, PCS, AWS, EAS, BRS, and/or the like. In some embodiments, an antenna might be provided within a signal distribution device, which might include a container disposed in a ground surface. A top portion of the container might be substantially level with a top portion of the ground surface. The antenna might be communicatively coupled to one or more of at least one conduit, at least one optical fiber, at least one conductive signal line, or at least one power line via the container. |
| US09786995B2 |
Slot array antenna
A slot array antenna includes: an electrically conductive member having an electrically conductive surface and slots therein, the slots being arrayed in a first direction which extends along the conductive surface; a waveguide member having an electrically conductive waveguide face which opposes the slots and extends along the first direction; and an artificial magnetic conductor extending on both sides of the waveguide member. At least one of the conductive member and the waveguide member includes dents on the conductive surface and/or the waveguide face, the dents each serving to broaden a spacing between the conductive surface and the waveguide face relative to any adjacent site. The dents include a first, second, and third dents which are adjacent to one another and consecutively follow along the first direction. A distance between centers of the first and second dents is different from a distance between centers of the second and third dents. |
| US09786992B2 |
System and method for cavity-backed antenna
A system includes a housing, a radio module, and an antenna coupled to the radio module. The housing includes a first wall having one or more openings, and the housing defines a cavity. The radio module and the antenna are disposed at least partially within the cavity of the housing. The radio module is configured to transmit or to receive a radio signal in a desired frequency spectrum via the antenna. The one or more openings are configured to contribute to the housing having a resonant frequency within the desired frequency spectrum. |
| US09786990B2 |
Integrated multiband antenna
An end fed dipole antenna on a circuit board configured to be a multiband, portable radio antenna has, among other features, an integrated diplexer for operating the antenna in multiple frequency bands. |
| US09786988B2 |
Multiband source with coaxial horn having monopulse tracking systems for a reflector antenna
The invention relates to a source for a reflector antenna, comprising: a pseudo-cavity, a first sigma excitation device for exciting the pseudo-cavity in such a way as to generate a sum channel signal via a coaxial waveguide, a second excitation device for exciting the pseudo-cavity in such a way as to generate a difference channel signal, the second device comprising eight probes angularly distributed around a principal emission axis of the source, and a difference supply circuit for supplying the eight excitation probes according to the two modes TE21. |
| US09786984B2 |
Portable antenna
An antenna having an elongated housing open at one end and defining an interior chamber. A telescoping mast has a carrier attached at a first end and a flexible antenna attached at its other end. The carrier with the attached mast and antenna is movable between a storage position in which the carrier, mast, and antenna are contained within the interior chamber of the housing, and a deployed position in which the mast and attached antenna protrude outwardly from the housing. A spring is positioned between the carrier and the housing which urges the carrier towards its deployed position. A catch mechanism selectively holds the carrier in its stored position and, when released, releases the spring to move the antenna to its deployed position. |
| US09786981B2 |
Antenna for electronic device
Embodiments are disclosed for an antenna system comprising an over-resonant antenna conductor and a radio receiver electrically coupled to the over-resonant antenna conductor. The antenna system further comprises a capacitor electrically coupled to the over-resonant antenna conductor and sized to match the antenna conductor to a selected frequency. |
| US09786980B2 |
Antenna system
An antenna system includes a ground metal element, a first signal source, a first antenna, a second signal source, a second antenna, an isolation metal element, and a matching circuit. The first signal source is connected to the ground metal element. The first antenna is connected to the first signal source. The first signal source is configured to excite the first antenna. The second signal source is connected to the ground metal element. The second antenna is connected to the second signal source. The second signal source is configured to excite the second antenna. The isolation metal element is disposed between the first antenna and the second antenna, and is configured to improve the isolation between the first antenna and the second antenna. The matching circuit is connected between the isolation metal element and the ground metal element. |
| US09786977B2 |
Pocketed circuit board
An example circuit board structure includes: a substrate; and vias that are electrically conductive and that pass through the substrate to enable electrical connection through the circuit board structure. The substrate is thinner, and lengths of the vias are shorter, in first areas of the circuit board structure that deliver first speed signals than in second areas of the circuit board structure that deliver second speed signals and power. The first speed signals have a shorter rise time than the second speed signals. |
| US09786972B2 |
Millimeter waveband filter
In an end surface 32b of the second transmission line forming body 32 forming a second waveguide 30, the height of a central region 33 which includes an opening of the second transmission line 30b is a reference plane. A depressed portion 32e that is depressed to a depth greater than the length of a thread portion of a screw 205 from the reference plane is provided in a region outside the central region 33 and includes a screw hole forming position. A screw hole 32d for fixing an external circuit 200 to be connected is provided at the screw hole forming position in the depressed portion 32e. The height of a region, which is excluding the depressed portion 32e and is further away from the central region 33 than the screw hole forming position, is equal to the reference plane. |
| US09786968B2 |
Battery module assembly having coolant flow channel
Disclosed herein is a battery module assembly including unit modules, each of which includes unit cells mounted to a cartridge in a state of being electrically connected to each other via bus bars, the battery module assembly including two or more sub-modules, each of which includes two or more unit modules vertically stacked from a ground to form a coolant flow channel at an interface therebetween, the sub-modules being arranged in a lateral direction in a state of being spaced apart from each other to provide the coolant flow channel, a base plate, on which the sub-modules are loaded, side cover plates mounted at sides of the sub-modules, each of the side cover plates having at least one coolant inlet port, through which a coolant is introduced, and a bracket for fixing ends of the sub-modules, the bracket having a coolant outlet port communicating with the coolant flow channel. |
| US09786962B2 |
Battery pack
A battery pack includes a plurality of battery cells, a protective circuit module (PCM), a temperature sensor and a case. Each battery cell has a terrace portion sealed so that an electrode tab of an electrode assembly is extracted to an outside. The PCM is electrically connected to the plurality of battery cells. The temperature sensor is connected to the PCM to measure a temperature of the battery cells. The case accommodates the plurality of battery cells, the PCM and the temperature sensor. The case includes a mounting portion on which the PCM is mounted, and a temperature sensor support portion protruded to be spaced apart from the mounting portion at a predetermined height is formed in one area of the mounting portion. |
| US09786959B2 |
Smart battery provided with a power supply voltage management circuit
The smart battery includes an electronic circuit for managing the supply voltage connected to a battery. The electronic circuit includes a battery end-of-life detector, a management unit, an oscillator stage, a DC-DC converter powered on when the supply voltage of the battery is close or equal to a battery end-of-life threshold, and a data or command communication interface. The data or command communication interface is a 1-wire interface which is connected to a positive supply voltage terminal of the smart battery for transmitting a modulated data or command signal through one of the supply voltage terminals. The modulated signal transmitted by the interface may include battery end-of-life information. |
| US09786954B2 |
Electrolyte including silane for use in electrochemical devices
The electrolyte includes one or more salts and a silane. The silane has a silicon linked to one or more first substituents that each include a poly(alkylene oxide) moiety or a cyclic carbonate moiety. The silane can be linked to four of the first substituents. Alternately, the silane can be linked to the one or more first substituents and one or more second substituents that each exclude both a poly(alkylene oxide) moiety and a cyclic carbonate moiety. |
| US09786940B2 |
Chlorination of processing residues as a variable load for grid scale electrical load following and storage
Disclosed are systems and methods having inherent carbon capture and conversion capabilities offering maximum flexibility, efficiency, and economics while simultaneously enabling environmentally and sustainably sound practices. A hybrid thermochemical cycle couples staged reforming with hydrogen production and residue chlorination. The residues of the upgrading are chlorinated, metals of interest are removed and bulk material is re-mineralized. Through the residue chlorination process, various metals including rare earths are concentrated and extracted. Energy is retained through chemical synthesis such as hydrocarbon and metal and non-metal chloride production. Produced chemicals are later exploited by redox reactions in the operation of an integrated gasification flow battery. |
| US09786939B2 |
Integrated power generation and chemical production using fuel cells
In various aspects, systems and methods are provided for operating a molten carbonate fuel cell assembly at increased power density. This can be accomplished in part by performing an effective amount of an endothermic reaction within the fuel cell stack in an integrated manner. This can allow for increased power density while still maintaining a desired temperature differential within the fuel cell assembly. |
| US09786938B2 |
Fuel cell system
A fuel cell system according to the present invention comprises: a fuel cell including a membrane-electrode assembly in which electrodes, each having a catalyst layer, are arranged on both surfaces of a polymer electrolyte membrane; and a control apparatus that performs performance recovery processing for the catalyst layer by decreasing an output voltage of the fuel cell to a predetermined voltage, wherein the control apparatus predicts a timing of an output increase request being made to the fuel cell and determines the necessity and content of the performance recovery processing based on a result of the prediction. |
| US09786932B2 |
Metal-air battery
A metal-air battery includes first and second cells, each cell including a negative electrode metal layer, a negative electrode electrolytic film, a positive electrode layer configured to use oxygen as an active material, and a gas diffusion layer, wherein the negative electrode metal layer, the negative electrode electrolytic film, the positive electrode layer, and the gas diffusion layer are sequentially disposed, wherein each cell has an open surface through which at least a portion of the gas diffusion layer is in fluid communication with, outside air, wherein the first and second cells contact each other, and wherein a direction of a first open surface of the first cell is different from a direction of a second open surface of the second cell. |
| US09786930B2 |
Fuel cell system and method for controlling the same
A fuel cell system and a method for controlling the same are provided. The method includes rapidly increasing an angular speed of a rotating magnetic field of an induction motor to maximize iron loss of the induction motor, thereby resulting in an increase in the temperature of a rise cell stack. The method further includes eliminating torque of a driving motor generated by an increase in the angular speed of the rotating magnetic field, using a torque eliminator. The torque eliminator includes a P-stage reducer or a hydraulic break. |
| US09786928B2 |
Proton exchange membrane fuel cell with stepped channel bipolar plate
A fuel cell stack includes a membrane electrode assembly and a bipolar plate. The bipolar plate has a corrugated portion defined by an adjacent pair of proximal and distal peak portions and a sidewall segment connecting the peak portions. The sidewall segment and membrane electrode assembly at least partially define a flow channel. The sidewall segment includes a shoulder portion defining a step spaced away from the peak portions. |
| US09786927B2 |
Conductive member, cell stack, electrochemical module, and electrochemical device
To provide a conductive member and a cell stack, where a concave groove of a conductive base substrate can be covered with a cover layer, as well as an electrochemical module and an electrochemical device. |
| US09786925B2 |
Fuel cell and fuel cell use gas diffusion electrode
A fuel cell comprised of a proton conductive electrolyte film sandwiched between a pair of catalyst layers, wherein the catalyst layer of at least the cathode is comprised of a mixture including a catalyst ingredient, an electrolytic material, and a carbon material, the carbon material is comprised of a catalyst-carrying carbon material carrying the catalyst ingredient and a gas-diffusing carbon material not carrying the catalyst ingredient, and the catalyst-carrying carbon material has an amount of adsorption of water vapor at 25° C. and a relative humidity of 90% of 50 ml/g or more. |
| US09786921B2 |
Secondary battery, manufacturing method of secondary battery, electrode for secondary battery, and electronic device
There is provided a secondary battery including a positive electrode, a negative electrode, and a solid electrolyte layer disposed between the positive electrode and the negative electrode, wherein at least one of the positive electrode and the negative electrode contains a granular solid electrolyte and a granular conduction aid both bonded to a surface of a granular electrode active substance. |
| US09786916B2 |
Electrode and secondary battery including the same
Disclosed is an electrode for secondary batteries including an electrode mixture including an electrode active material, binder and conductive material coated on a current collector wherein a conductive material is coated to a thickness of 1 to 80 μm on the current collector and the electrode mixture is coated on a coating layer of the conductive material so as to improve electrical conductivity. |
| US09786915B2 |
All-solid state lithium carbon monofluoride batteries
A solid state lithium carbon monofluoride battery includes an anode comprising Li, a solid electrolyte, and a cathode including CFx and LPS. The cathode can also include a carbon compound. The solid electrolyte can include LPS. The LPS can include β-Li3PS4. The cathode LPS can include β-Li3PS4. A method of making a battery is also disclosed. |
| US09786914B2 |
Spinel-type lithium cobalt manganese-containing complex oxide
There is provided a Co-based 5-V spinel-type lithium manganese-containing complex oxide not only having an operating potential of 4.5 V or higher but also being capable of extending its capacity region of a 5.5 to 5.5 V region and being capable of enhancing its energy density as well. There is proposed a spinel-type lithium cobalt manganese-containing complex oxide having a crystal structure classified as a space group Fd-3m and being represented by the general formula [Lix(CoyMn3−x−y)O4−δ] (wherein 0.90≦x≦1.15 and 0.75≦y≦1.25), wherein the oxide has a crystallite size measured by a Rietveld method using the fundamental method of 100 nm to 200 nm, an interatomic distance of Li—O of 1.80 Å to 2.00 Å, and a strain of 0.20 to 0.50. |
| US09786912B2 |
Titanium raw material for lithium titanate production and method for producing lithium titanate using same
The invention provides a low-cost, efficient method for producing lithium titanate that is useful for applications in electric storage devices. The desired lithium titanate can be obtained by heating at least (1) titanium oxide having a BET single point specific surface area of 50 to 450 m2/g based on nitrogen adsorption and (2) a lithium compound. Preferably the titanium oxide and lithium compound are heated together with (3) a lithium titanate compound having the same crystal structure as the desired lithium titanate. Preferably these ingredients are dry-mixed before heating. |
| US09786911B2 |
Cathode active material and lithium secondary battery comprising the same
Disclosed is a cathode active material for secondary batteries comprising at least one compound selected from the following formula 1: (1−s−t)[Li(LiaMn(1−a−x−y)NixCoy)O2]*s[Li2CO3]*t[LiOH] (1) wherein 0 |
| US09786907B2 |
Positive electrode active material for lithium secondary battery, positive electrode for lithium secondary battery, and lithium secondary battery
A positive electrode active material for a lithium secondary battery includes a primary particle containing a spinel phase and a layered rock-salt phase. The spinel phase is formed of a nickel-and-manganese-containing composite oxide having a spinel crystal structure that includes lithium, nickel, and manganese. The layered rock-salt phase is formed of a transition metal composite oxide having a layered rock-salt crystal structure that includes lithium and at least one transition metal element. The nickel-and-manganese-containing composite oxide contains oxygen and fluorine. The transition metal composite oxide includes oxygen and fluorine. |
| US09786903B2 |
Positive electrode active material for lithium secondary battery, method of preparing the same and lithium secondary battery including the same
The present invention provides a positive electrode active material for a lithium secondary battery including a core including first lithium cobalt oxide, and a surface modifying layer positioned on a surface of the core. The surface modifying layer includes a lithium compound discontinuously distributed on the surface of the core, and second lithium cobalt oxide distributed while making a contact with or adjacent to the lithium compound, with a Li/Co molar ratio of less than 1. The positive electrode active material according to the present invention forms a lithium deficient structure in the positive electrode active material of lithium cobalt oxide and changes two-dimensional lithium transport path into three-dimensional path. The transport rate of lithium ions may increase when applied to a battery, thereby illustrating improved capacity and rate characteristic without decreasing initial capacity. |
| US09786902B2 |
Electrode for non-aqueous electrolytic battery, non-aqueous electrolytic secondary battery, and battery pack
An electrode for battery has an electrode mixture containing a binder and an active material particle selected from at least one of a carbonaceous material, a metal particle and a metal oxide particle formed on a current collector. When cutting strength of an interface between the current collector and the electrode mixture is represented by “a” and cutting strength in a horizontal direction within the electrode mixture is represented by “b”, the “a” and “b” satisfy a relation of a/b<1. |
| US09786901B2 |
Electrode and method for manufacturing an electrode
A method for manufacturing an electrode. To provide a particularly cost-effective method, which is able to provide a current collector layer that adheres well and is electrically well-connected, the method including: a) providing a layer having an active material; b) one-sided electrochemical deposition of a metallic material on the layer having the active material, thus forming a current collector layer having the metallic material; c) joining the product obtained in b) to another layer having an active material and to a contact element so that the current collector layer having the deposited metallic material is situated between two layers having an active material, and that the contact element for establishing contact is at least partially exposed and is in contact with the current collector layer having the deposited metallic material. |
| US09786900B2 |
Method for producing a battery filled with a liquid electrolyte, filling vessel therefor, machine and battery
The invention relates to a method for producing a battery (10) filled with a liquid electrolyte (2, 11), wherein the battery (10) comprises a housing (1) having a top side (3) lying at the top in the normal operation of the battery (10) and a bottom side (4) opposite the top side (3), wherein battery electrodes (6) are arranged in the housing (1) and the housing (1) has at least one filling opening (5) for the liquid electrolyte (2, 11), which filling opening is arranged on the top side (3) of the housing (1) or at least above the center of the housing (1), characterized in that liquid electrolyte (2, 11) is fed through the at least one filling opening (5) in such a way that the topmost point (16) of the battery electrodes (6) with respect to the direction of action of gravity is not completely covered with the liquid electrolyte (2, 11) at any time during the process of filling the battery with liquid electrolyte (2, 11). The invention further relates to a filling vessel designed for performing the method, to a machine, and to a battery. |
| US09786899B2 |
Terminal component and method of manufacturing terminal component
A terminal component includes an external terminal that is provided above a cover covering an electrode body; and an internal terminal that is provided below the cover and extends through a through-hole of the external terminal. A part of the internal terminal protrudes above the external terminal. A dimension of the part of the internal terminal in a radial direction of the through-hole is larger than a diameter of the through-hole. The external terminal has a joint surface that is a first part of an upper surface of the external terminal and that is joined to the internal terminal, and a non-joint surface that is a second part of the upper surface of the external terminal and that is located outside the joint surface. The joint surface is located higher than at least part of the non-joint surface. |
| US09786895B2 |
Energy storage module with reduced damage to electrode terminals
An energy storage module includes an energy storage cell group containing a plurality of energy storage cells stacked in a stacking direction, and a pair of end plates provided at both ends of the energy storage cell group in the stacking direction. A terminal frame is provided at the end plate in order to electrically connect an electrode terminal of the energy storage cell provided at an end in the stacking direction and an output line. The terminal frame is fixed to the end plate by fixing points. |
| US09786894B2 |
Battery pack
A battery pack includes a first battery module having first and second battery frame assemblies and first and second battery cells. The first battery frame assembly has a plastic frame member, a thermally conductive plate, a busbar, and a voltage sensing member. The plastic frame member has a rectangular ring-shaped body. The thermally conductive plate is coupled to rectangular ring-shaped body. The busbar has a first post and a first conductive body coupled to the first post. The first post extends outwardly from the plastic frame member, and the first conductive body extends through the rectangular ring-shaped body. The voltage sensing member has a first sensing post and a first sensing body. The first sensing post extends outwardly from the rectangular ring-shaped body. |
| US09786893B2 |
Flexible electrochemical device including electrically connected electrode assemblies
A flexible electrochemical device in which a plurality of electrode assemblies is electrically connected to each other so that the flexible electrochemical device may be repeatedly bent, includes at least two electrode assemblies that are arranged separate from each other and a casing member that packs the at least two electrode assemblies and includes at least two accommodation portions in which electrode assemblies are individually received, and a connecting portion that connects the at least two adjacent accommodation portions where a path between a conductive line that electrically connects at least two electrode assemblies together and an electrolyte is defined in the connecting portion. |
| US09786889B2 |
Electrode assembly of secondary battery
Provided is an electrode assembly of a secondary battery, including: a first electrode unit and a second electrode unit; a separation membrane interposed between the first electrode unit and the second electrode unit; and a first coating unit having an insulating member which is made of a metal oxide material and is coated along front and rear edge portions of the first electrode unit. |
| US09786881B2 |
Battery pack and power supply unit
A battery pack comprises a battery unit containing a plurality of batteries connected in series or in parallel; a lower frame housing a portion of a side of a bottom of the battery unit and mounted on an shelf plate top surface; a upper frame housing a portion on the side of a top surface of the battery unit as a surface opposed to the bottom and holding the battery unit by being connected to the lower frame; and a bracket mounted on the lower frame and fixed to the shelf plate top surface. |
| US09786877B2 |
Battery pack of electric power tool
A battery pack of an electric power tool comprises ten lithium-ion cells. The ten lithium-ion cells are connected in series. Each lithium-ion cell has a diameter equal to or less than 18 millimeters, a length equal to or less than 65 millimeters, and an internal resistance equal to or less than 30 milliohms. Because the battery pack has a high voltage in operation and is therefore able to supply large current, the battery pack is preferably configured incapable of being used in a conventional electric power tool that cannot operate under such a large current. |
| US09786869B2 |
Organic light emitting device and display unit
An organic light emitting device capable of improving the light extraction characteristics while suppressing the driving voltage and improving the luminescent performance, and a display unit using it are provided. The organic light emitting device includes: a lamination structure that includes a cathode, a plurality of layers including a light emitting layer made of an organic material, and an anode including a metal thin film in this order, in which the cathode is reflective and the anode is semi-transparent to light generated in the light emitting layer; and a resonator structure that resonates the light generated in the light emitting layer between the cathode and the anode. |
| US09786868B2 |
Electronic structure having at least one metal growth layer and method for producing an electronic structure
Various embodiments may relate to an electronic structure, including at least one organic layer, at least one metal growth layer grown onto the organic layer, and at least one metal layer grown on the metal growth layer. The at least one metal growth layer contains germanium. Various embodiments further relate to a method for producing the electronic structure. |
| US09786863B2 |
White organic light emitting device
Provided is a white organic light emitting device which can improve abnormal light emission and efficiency and reliability of the device.A white organic light emitting device according to an exemplary embodiment of the present invention includes: a first light emitting unit including a first emitting layer between a first electrode and a second electrode; a second light emitting unit including a second emitting layer on the first light emitting unit; and a charge generation layer between the first light emitting unit and the second light emitting unit, and a volume of a metal in the charge generation layer is 1.0% or less of the total volume of the charge generation layer. |
| US09786862B2 |
Organic light emitting device including a multi-layer light emitting structure and an organic light emitting display including the organic light emitting device
An organic light emitting device including a first electrode connected to a thin film transistor formed on a substrate, a second electrode opposite to the first electrode, and an organic laminate formed between the first electrode and the second electrode and including a hole transport layer, a multilayer-light emitting structure, and an electron transport layer. The multilayer-light emitting structure includes at least two light emitting layers emitting light of different colors through recombination of electrons and holes injected through the first and second electrodes, and a charge transport control layer formed of a bipolar material transporting both electrons and holes at boundaries between the at least two light emitting layers and controlling the amount of charges transported between the at least two light emitting layers. |
| US09786860B2 |
Light-emitting element, light-emitting device, display device, electronic device, and lighting device
An object is to provide a light-emitting element which uses a plurality of kinds of light-emitting dopants and has high emission efficiency. In one embodiment of the present invention, a light-emitting device, a light-emitting module, a light-emitting display device, an electronic device, and a lighting device each having reduced power consumption by using the above light-emitting element are provided. Attention is paid to Förster mechanism, which is one of mechanisms of intermolecular energy transfer. Efficient energy transfer by Förster mechanism is achieved by making an emission wavelength of a molecule which donates energy overlap with a local maximum peak on the longest wavelength side of a graph obtained by multiplying an absorption spectrum of a molecule which receives energy by a wavelength raised to the fourth power. |
| US09786854B2 |
N-type thin film transistor
An N-type thin film transistor includes an insulating substrate, a gate electrode, an insulating layer, a first MgO layer, a semiconductor carbon nanotube layer, a second MgO layer, a functional dielectric layer, a source electrode and a drain electrode. The gate electrode is located on a surface of the insulating substrate. The insulating layer is located on the gate electrode. The first MgO layer is located on the insulating layer. The semiconductor carbon nanotube layer is located on the first MgO layer. The source electrode and the drain electrode are electrically connected to the semiconductor carbon nanotube layer, wherein the source electrode and the drain electrode are spaced from each other. The second MgO layer is located on the semiconductor carbon nanotube layer. The functional dielectric layer is located on the second MgO layer. |
| US09786848B2 |
Nanofiber-based heterojunction approach for high photoconductivity on organic materials
The present disclosure provides methods and compositions for an organic nanofiber-based heterojunction material, comprising nano fibers of an acceptor molecule, the nano fibers coated with a donor molecule, where the acceptor molecule contains a group and the donor molecule contains a companion group, wherein the group and companion group enables strong binding between the acceptor molecule and donor molecule, the strong binding providing for efficient forward electron transfer between the acceptor molecule and donor molecule, and wherein the group and companion group minimize charge carrier recombination between the acceptor molecule and the donor molecule. |
| US09786847B2 |
Compound for organic photoelectric device, and organic photoelectric device and image sensor including the same
A compound for an organic photoelectric device is represented by Chemical Formula 1, and an organic photoelectric device, an image sensor, and an electronic device include the same. |
| US09786845B1 |
Optical discs as low-cost, quasi-random nanoimprinting templates for photon management
Methods of patterning a layer of a photonic device are provided using stamps or masks derived from pre-written optical media discs. One method comprises pressing a stamp on a surface of a layer of a photonic device, the stamp comprising a stamping surface which defines a negative replica of a quasi-random pattern of nanostructures defined in a recording layer of a pre-written optical media disc, for a period of time sufficient to imprint the quasi-random pattern of nanostructures defined in the recording layer of the pre-written optical media disc onto the surface of the layer of the photonic device; and removing the stamp. The stamps, the masks, and the photonic devices comprising the patterned layers are also provided. |
| US09786840B2 |
Electronic device and method for fabricating the same
An electronic device including a semiconductor memory is provided. The semiconductor memory includes an interlayer dielectric layer disposed over a substrate, and having a recess which exposes a portion of the substrate; a bottom contact partially filling the recess; and a resistance variable element including a bottom layer which fills at least a remaining space of the recess over the bottom contact, and a remaining layer which is disposed over the bottom layer and protrudes out of the interlayer dielectric layer. |
| US09786838B2 |
Packages for integrated circuits and methods of packaging integrated circuits
An integrated circuit package including an integrated circuit die including a first side and a second side opposite the first side, the first side including at least one magnetoresistive device formed thereon. The integrated circuit package also may include a first magnetic shield disposed on or adjacent the first side of the integrated circuit die, wherein the first magnetic shield is formed of a composite material. |
| US09786837B2 |
Multibit self-reference thermally assisted MRAM
A mechanism is provided for a thermally assisted magnetoresistive random access memory device (TAS-MRAM). A storage layer has an anisotropic axis, in which the storage layer is configured to store a state in off axis positions and on axis positions. The off axis positions are not aligned with the anisotropic axis. A tunnel barrier is disposed on top of the storage layer. A ferromagnetic sense layer is disposed on top of the tunnel barrier. |
| US09786836B2 |
Multibit self-reference thermally assisted MRAM
A mechanism is provided for a thermally assisted magnetoresistive random access memory device (TAS-MRAM). A storage layer has an anisotropic axis, in which the storage layer is configured to store a state in off axis positions and on axis positions. The off axis positions are not aligned with the anisotropic axis. A tunnel barrier is disposed on top of the storage layer. A ferromagnetic sense layer is disposed on top of the tunnel barrier. |
| US09786835B2 |
Backside integration of RF filters for RF front end modules and design structure
A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device. |
| US09786828B2 |
Method of producing a thermocouple having a tailored thermoelectric response
A method is disclosed for tailoring the thermoelectric response of a thermocouple to that desired by a user. The method comprises the steps of; (a) selecting a first thermoelectric material, (b) selecting a second thermoelectric material having dissimilar thermoelectric properties to the first thermoelectric material, a thermocouple formed from the first thermoelectric material and the second thermoelectric material having a known thermoelectric response, and (c) modifying the chemical composition of at least one of the first thermoelectric material and the second thermoelectric material to produce a thermocouple having a tailored thermoelectric response. In specific embodiments, the chemical composition may be modified by selectively depleting one or more chemical elements from the thermoelectric material or by selectively adding, or increasing the proportion of, one or more elements to the thermoelectric material. |
| US09786827B2 |
Light emitting diode package
A light-emitting diode package includes a package body. The package body includes an upper insulation substrate including upper conductive patterns, a lower insulation substrate including lower conductive patterns, and middle conductive patterns disposed between the upper insulation substrate and the lower insulation substrate. The package body also includes an upper via disposed in the upper insulation substrate, a lower via disposed in the lower insulation substrate, the upper via and the lower via not overlaid with each other. |
| US09786825B2 |
Ceramic-based light emitting diode (LED) devices, components, and methods
Devices, components and methods containing one or more light emitter devices, such as light emitting diodes (LEDs) or LED chips, are disclosed. In one aspect, a light emitter device component can include a ceramic body having a top surface, one or more light emitter devices mounted directly or indirectly on the top surface, and one or more electrical components mounted on the top surface and electrically coupled to the one or more light emitter devices, wherein the one or more electrical components can be spaced from the ceramic body by one or more non-metallic layers. Components disclosed herein can result in improved light extraction and thermal management. |
| US09786823B2 |
Light-emitting device with sealing member comprising zinc sulfide particles
An LED light emitting device 5 as an example of a light emitting device utilizing a semiconductor to which the present invention is applied includes a package 10, a semiconductor light emitting element 200, a first sealing layer 50, and a second sealing layer 60. The semiconductor light emitting element 200 includes a p-n functioned semiconductor layer, and serves as a light source that emits light in accordance with application of a voltage to the semiconductor layer. The semiconductor light emitting element 200 is connected to power supply terminals 201 that supply a current. |
| US09786822B2 |
Light emitting diode package and method of manufacture
A light emitting diode (LED) device and packaging for same is disclosed. In some aspects, the LED is manufactured using a vertical configuration including a plurality of layers. Certain layers act to promote mechanical, electrical, thermal, or optical characteristics of the device. The device avoids design problems, including manufacturing complexities, costs and heat dissipation problems found in conventional LED devices. Some embodiments include a plurality of optically permissive layers, including an optically permissive cover substrate or wafer stacked over a semiconductor LED and positioned using one or more alignment markers. |
| US09786821B2 |
Method for manufacturing light emitting device
A method for manufacturing a light emitting device includes: mounting a light emitting element on the support body upper surface such that a light emitting element lower surface of light emitting element is opposite to the support body upper surface in a height direction, a frame and the light emitting element being mounted such that the light emitting element is located in an opening of the frame; injecting a resin into an inner space provided between the frame and the light emitting element through an inlet to form a covering member which covers the light emitting element such that at least a part of a light emitting element upper surface is exposed, the inlet connecting the inner space and an outer space opposite to the inner space with respect to the frame wall; and providing a light-transmissive member on the light emitting element. |
| US09786813B2 |
Thin-film flip-chip light emitting diode having roughening surface and method for manufacturing the same
A thin-film flip-chip light emitting diode (LED) having a roughened surface and a method for manufacturing the same are provided. First, a substrate having a patterned structure on a surface of the substrate is provided, and the surface is roughened. A first semiconductor layer is then formed on the surface; a light emitting structure layer is then formed on the first semiconductor layer; a second semiconductor layer is then formed on the light emitting structure layer. The first and second semiconductor layers possess opposite electrical characteristics. A first contact electrode and a second contact electrode are then formed on the first semiconductor layer and the second semiconductor layer, respectively. Finally, a sub-mount is formed on the first and second contact electrodes, and the substrate is removed to form the thin-film flip-chip LED having the roughened surface. Here, the light emitting efficiency of the thin-film flip-chip LED is improved. |
| US09786811B2 |
Tilted emission LED array
The present disclosure is directed to LED components, and systems using such components, having a light emission profile that may be controlled independently of the lens shape by varying the position and/or orientation of LED chips with respect to one or both of an overlying lens and the surface of the component. For example, the optical centers of the LED emitting surface and the lens, which are normally aligned, may be offset from each other to generate a controlled and predictable emission profile. The LED chips may be positioned to provide a peak emission shifted from a perpendicular centerline of the lens base. The use of offset emitters allows for LED components with shifted or tilted emission patterns, without causing output at high angles of the components. This is beneficial as it allows a lighting system to have tilted emission from the LED component and primary optics. |
| US09786809B2 |
Method of forming electrode pattern and method of manufacturing solar cell
A method of forming an electrode pattern includes: forming, on a base material, a seed layer having a pattern corresponding to the electrode pattern; forming an organic material layer on the seed layer; producing an electrode layer transfer sheet by forming an electrode layer on the organic material layer via an electroplating process using the seed layer as a seed; disposing the electrode layer transfer sheet on a substrate on which the electrode pattern is to be formed such that the electrode layer is in contact with the substrate and pressure bonding the electrode layer to the substrate; and in a state in which the electrode layer is pressure bonded to the substrate, removing the base material along with the organic material layer and the seed layer to transfer the electrode layer to the substrate. |
| US09786808B2 |
Method of anodising a surface of a semiconductor device
The present disclosure provides a method of anodizing a surface of a semiconductor device comprising a p-n junction. The method comprises exposing a first surface portion of the semiconductor device to an electrolytic solution that is suitable for anodizing the first surface portion when an electrical current is directed through a region at the first surface portion. Further, the method comprises exposing a portion of the semiconductor device to electromagnetic radiation in a manner such that the electromagnetic radiation induces the electrical current and the first surface portion anodizes. |
| US09786807B2 |
Thin-film photovoltaic device and fabrication method
A method to fabricate thin-film photovoltaic devices including a photovoltaic Cu(In,Ga)Se2 or equivalent ABC absorber layer, such as an ABC2 layer, deposited onto a back-contact layer characterized in that the method includes at least five deposition steps, during which the pair of third and fourth steps are sequentially repeatable, in the presence of at least one C element over one or more steps. In the first step at least one B element is deposited, followed in the second by deposition of A and B elements at a deposition rate ratio Ar/Br, in the third at a ratio Ar/Br lower than the previous, in the fourth at a ratio Ar/Br higher than the previous, and in the fifth depositing only B elements to achieve a final ratio A/B of total deposited elements. |
| US09786799B2 |
Process for the production of an optically selective coating of a substrate for high temperature receiver solar devices and relative material obtained
A process for the production of an optically selective coating of a receiver substrate of a suitable material for solar receiver devices particularly suitable for operating at high temperatures, more specifically for receiver tubes of linear parabolic trough, which comprises: deposition of a layer reflecting infrared radiation consisting of a high-melting metal on a heated receiver substrate of a suitable material; annealing under the same temperature and pressure conditions as the deposition of the reflecting layer; deposition on the high-melting metal of one or more layers of metal-ceramic composite materials (CERMET), wherein the metal is W and the ceramic matrix is YPSZ (“Yttria-Partially Stabilized Zirconia”); deposition on the cermet of an antireflection layer; annealing under the same temperature and pressure conditions as the depositions of the cermet and antireflection layers. |
| US09786793B2 |
Semiconductor device comprising oxide semiconductor layer including regions with different concentrations of resistance-reducing elements
To increase the on-state current of a transistor whose channel is formed in an oxide semiconductor layer. To provide a transistor where a resistance-reducing element is introduced into a region of an oxide semiconductor layer which overlaps with part of a source or drain or part of a gate. For example, the thickness of a region of a conductive layer serving as a source or drain or a gate (at least part of a region overlapping with an oxide semiconductor layer) is made smaller than that of the other region of the conductive layer. A resistance-reducing element is introduced into the oxide semiconductor layer through the conductive layer thinned partly, thereby obtaining the oxide semiconductor layer where the resistance-reducing element is introduced into the region overlapping with part of the source or drain or part of the gate. Thus, the on-state current of the transistor can be increased. |
| US09786790B2 |
Flexible device
In one embodiment, a flexible device is provided. The flexible device may include a flexible substrate, a buffer layer, a light reflective layer, and a device layer. The buffer layer is located on the flexible substrate. The light reflective layer is located on the flexible substrate, wherein the light reflective layer has a reflection wavelength of 200 nm˜1100 nm, a reflection ratio of greater than 80%, and a stress direction of the light reflective layer is the same as a stress direction of the flexible substrate. The device layer is located on the light reflective layer and the buffer layer. |
| US09786787B2 |
Semiconductor device and fabrication method thereof
A p channel TFT of a driving circuit has a single drain structure and its n channel TFT, an LDD structure. A pixel TFT has the LDD structure. A pixel electrode disposed in a pixel unit is connected to the pixel TFT through a hole bored in at least a protective insulation film formed of an inorganic insulating material and formed above a gate electrode of the pixel TFT, and in an inter-layer insulation film disposed on the insulation film in close contact therewith. These process steps use 6 to 8 photo-masks. |
| US09786786B2 |
Non-planar quantum well device having interfacial layer and method of forming same
Techniques are disclosed for forming a non-planar quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), and a quantum well layer. A fin structure is formed in the quantum well structure, and an interfacial layer provided over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure. |
| US09786785B2 |
Semiconductor device, method for fabricating the same, and memory system including the semiconductor device
Semiconductor device, method for fabricating the same and electronic devices including the semiconductor device are provided. The semiconductor device comprises an interlayer insulating layer formed on a substrate and including a trench, a gate electrode formed in the trench, a first gate spacer formed on a side wall of the gate electrode to have an L shape, a second gate spacer formed on the first gate spacer to have an L shape and having a dielectric constant lower than that of silicon nitride, and a third spacer formed on the second gate spacer. |
| US09786783B2 |
Transistor architecture having extended recessed spacer and source/drain regions and method of making same
Techniques are disclosed for forming transistor architectures having extended recessed spacer and source/drain (S/D) regions. In some embodiments, a recess can be formed, for example, in the top of a fin of a fin-based field-effect transistor (finFET), such that the recess allows for forming extended recessed spacers and S/D regions in the finFET that are adjacent to the gate stack. In some instances, this configuration provides a higher resistance path in the top of the fin, which can reduce gate-induced drain leakage (GIDL) in the finFET. In some embodiments, precise tuning of the onset of GIDL can be provided. Some embodiments may provide a reduction in junction leakage (Lb) and a simultaneous increase in threshold voltage (VT). The disclosed techniques can be implemented with planar and non-planar fin-based architectures and can be used in standard metal-oxide-semiconductor (MOS) and complementary MOS (CMOS) process flows, in some embodiments. |
| US09786782B2 |
Source/drain FinFET channel stressor structure
A semiconductor structure includes a material stack of, from bottom to top, an insulator structure and a semiconductor fin portion located on a pedestal portion of a semiconductor substrate portion, wherein a doped epitaxial semiconductor material structure extends from each sidewall surface of the semiconductor fin portion, each doped epitaxial semiconductor material structure introduces a stress on the semiconductor fin portion. A gate structure straddles the semiconductor fin portion. A source-side stressor structure having a bottommost surface contacting a first subsurface of the semiconductor substrate portion and covering one of the doped epitaxial semiconductor material structure is located on a source-side of the gate structure. A drain-side stressor structure having a bottommost surface contacting a second subsurface of the semiconductor substrate portion and covering another of the doped epitaxial semiconductor material structure is located on a drain-side of the gate structure. |
| US09786781B2 |
Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction
A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink. |
| US09786780B2 |
Integrated circuits having source/drain structure
An integrated circuit includes a gate structure over a substrate. A silicon-containing material structure is in each of recesses that are adjacent to the gate structure. The silicon-containing material structure has a first region and a second region, the second region is closer to the gate structure than the first region, and the first region is thicker than the second region. |
| US09786774B2 |
Metal gate of gate-all-around transistor
The disclosure relates to a semiconductor device. An exemplary structure for a semiconductor device comprises a nanowire structure comprising a channel region between a source region and a drain region; and a metal gate surrounding a portion the channel region, wherein the metal gate comprising a first gate portion adjacent to the source region having a first thickness and a second gate portion adjacent to the drain region having a second thickness less than the first thickness. |
| US09786772B2 |
Semiconductor device and method for manufacturing the same
A semiconductor device according to the present invention includes a semiconductor substrate, having an emitter layer of a first conductivity type, a collector layer of a second conductivity type and a drift layer of the first conductivity type sandwiched therebetween, the emitter layer disposed at a front surface side of the semiconductor substrate and the collector layer disposed at a rear surface side of the semiconductor substrate, a base layer of the second conductivity type between the drift layer and the emitter layer, a buffer layer of the first conductivity type between the collector layer and the drift layer, the buffer layer having an impurity concentration higher than that of the drift layer, and having an impurity concentration profile with two peaks in regard to a depth direction from the rear surface of the semiconductor substrate, and a defect layer, formed in the drift layer and having an impurity concentration profile with a half-value width of not more than 2 μm in regard to the depth direction from the rear surface of the semiconductor substrate. |
| US09786770B1 |
Semiconductor device structure with non planar slide wall
A semiconductor device that includes a semiconductor structure having a side wall that is non planar and that extends farther outward at an upper portion than at a lower portion of the side wall. The semiconductor structure extends underneath a semiconductor layer wherein a top portion of the structure contacts the semiconductor layer. |
| US09786768B1 |
III-V vertical field effect transistors with tunable bandgap source/drain regions
Vertical field effect transistor (FET) device with tunable bandgap source/drain regions are provided, as well as methods for fabricating such vertical FET devices. For example, a vertical FET device includes a lower source/drain region formed on a substrate, a vertical semiconductor fin formed on the lower source/drain region, and an upper source/drain region formed on an upper region of the vertical semiconductor fin. The lower source/drain region and vertical semiconductor fin are formed of a first type of III-V semiconductor material. The upper source/drain region is formed of a second type of III-V semiconductor material which comprises the first type of III-V semiconductor material and at least one additional element that increases a bandgap of the second type of III-V semiconductor material of the upper source/drain region relative to a bandgap of the first type of III-V compound semiconductor material of the lower source/drain region and the vertical semiconductor fin. |
| US09786763B2 |
Semiconductor device and manufacturing method thereof
A method of manufacturing a semiconductor device includes: forming a lattice defect layer in a substrate having a front surface region where a bipolar element of a pn junction type is formed and a rear surface region opposing the front surface region, the lattice defect layer being formed by injecting a charged particle to a first region in the rear surface region of the substrate; forming a laminated region, in which a first conductivity type impurity region and a second conductivity type impurity region are sequentially laminated from a rear surface side of the substrate toward the first region, in a second region in the rear surface region of the substrate, the first region being positioned deeper than the second region from a rear surface of the substrate; and selectively activating the laminated region by laser annealing after the formation of the laminated region and the lattice defect layer. |
| US09786761B2 |
Integrated circuit device having an interfacial layer and method of manufacturing the same
An integrated circuit device includes a substrate including an active region, an interfacial layer including a lower insulating layer on the active region, the lower insulating layer doped with a chalcogen element having an atomic weight equal to or greater than 16, a gate insulation layer on the interfacial layer, and a gate electrode on the gate insulation layer. |
| US09786760B1 |
Air gap and air spacer pinch off
Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact. |
| US09786756B2 |
Self-aligned source and drain regions for semiconductor devices
A method for forming a semiconductor device includes patterning a gate conductor, formed on a substrate, and a two-dimensional material formed on the gate conductor. Recesses are formed adjacent to the gate conductor in the substrate, and a doped layer is deposited in the recesses and over a top of the two-dimensional material. Tape is adhered to the doped layer on top of the two-dimensional material. The tape is removed to exfoliate the doped layer from the top of the two-dimensional material to form source and drain regions in the recesses. |
| US09786755B2 |
Process for producing, from an SOI and in particular an FDSOI type substrate, transistors having gate oxides of different thicknesses, and corresponding integrated circuit
An integrated circuit includes a first zone for a first transistor and a second zone for a second transistor. The transistors are supported by a substrate of the silicon-on-insulator type that includes a semiconductor film on a buried insulating layer on a carrier substrate. In the second zone, the semiconductor film has been removed. The second transistor in the second zone includes a gate-dielectric region resting on the carrier substrate that is formed by a portion of the buried insulating layer). The first transistor in the first zone includes a gate-dielectric region formed by a dielectric layer on the semiconductor film. |
| US09786747B2 |
Wiring substrate, manufacturing method of wiring substrate and electronic component device
A wiring substrate includes an insulation layer having an electronic component mounting area, and a wiring layer embedded in the insulation layer, the wiring layer having a first surface exposed from the insulation layer, to which a terminal of an electronic component is to be connected, a second surface opposite to the first surface, which is covered by the insulation layer, and a side surface. The second surface has a roughened surface and the side surface has a roughened surface, and a surface roughness of the second surface of the wiring layer is greater than a surface roughness of the side surface. |
| US09786746B2 |
Semiconductor device with improved reverse recovery characteristics
A semiconductor device includes a diode and a semiconductor substrate. The diode includes a p-type anode region and an n-type cathode region. A lifetime control layer is provided in an area within the cathode region. The area is located on a back side than a middle portion of the semiconductor substrate in a thickness direction of the semiconductor substrate. The lifetime control layer has crystal defects which are distributed along a planar direction of the semiconductor substrate. A peak value of a crystal defect density in the lifetime control layer is higher than a crystal defect density of a front side region adjacent to the lifetime control layer on a front side of the lifetime control layer and a crystal defect density of a back side region adjacent to the lifetime control layer on a back side of the lifetime control layer. |
| US09786743B2 |
Semiconductor device with electron supply layer
A semiconductor device includes a semiconductor stacked structure including at least an electron transit layer and an electron supply layer over a substrate. The electron supply layer includes a first portion and second portions sandwiching the first portion, and the first portion has a higher energy of a conduction band than that of the second portion, and includes a doped portion doped with an n-type impurity and undoped portions that sandwich the doped portion and are not doped with an impurity. |
| US09786742B2 |
Semiconductor device
A semiconductor device according to an embodiment includes a SiC layer having a first plane and a second plane, a gate insulating film provided on the first plane, a gate electrode provided on the gate insulating film, a first SiC region of a first conductivity type provided in the SiC layer, a second SiC region of a second conductivity type provided in the first SiC region, a third SiC region of the first conductivity type provided in the second SiC region, and a fourth SiC region of the first conductivity type provided between the second SiC region and the gate insulating film, the fourth SiC region interposed between the second SiC regions, and the fourth SiC region provided between the first SiC region and the third SiC region. |
| US09786741B2 |
Silicon carbide semiconductor device and method for manufacturing the same
A silicon carbide semiconductor device includes a silicon carbide layer and a gate insulating layer. The silicon carbide layer has a main surface. The gate insulating layer is arranged as being in contact with the main surface of the silicon carbide layer. The silicon carbide layer includes a drift region having a first conductivity type, a body region having a second conductivity type different from the first conductivity type and being in contact with the drift region, a source region having the first conductivity type and arranged as being spaced apart from the drift region by the body region, and a protruding region arranged to protrude from at least one side of the source region and the drift region into the body region, being in contact with the gate insulating layer, and having the first conductivity type. |
| US09786738B2 |
Semiconductor device with well resistor and alternated insulating and active regions between input and output terminals
A semiconductor device including a well resistance element of high accuracy and high withstand voltage and a method of manufacturing the semiconductor device are provided.The semiconductor device includes a semiconductor substrate, a well region, an input terminal, an output terminal, a separation insulating film, and an active region. The input terminal and the output terminal are electrically coupled to the well region. The separation insulating film is arranged to be in contact with the upper surface of the well region in an intermediate region between the input terminal and the output terminal. The active region is arranged to be in contact with the upper surface of the well region. The separation insulating film and the active region in the intermediate region have an elongated shape in plan view. In the intermediate region, a plurality of separation insulating films and a plurality of active regions are alternately and repeatedly arranged. |
| US09786737B2 |
FinFET with reduced parasitic capacitance
A semiconductor device including at least one fin extending upward from a substrate and a gate on the substrate, wherein the gate includes outer sidewalls, wherein the fin extend through a width of the gate. A spacer material can be adjacent to the outer sidewalls of the gate, wherein a top surface of the spacer material is below the top surface of the gate and above the top surface of the fin. The semiconductor device can also include an epitaxial semiconductor layer over the fins on each side of the spacer material. A low-k dielectric material can be deposited above each epitaxial semiconductor layer. The semiconductor device also includes a dielectric top layer forming a top surface of the transistor, wherein the dielectric top layer seals an air gap between the top surface of the fins and the dielectric top layer. |
| US09786736B2 |
Power semiconductor device
A problem associated with n-channel power MOSFETs and the like that the following is caused even by relatively slight fluctuation in various process parameters is solved: source-drain breakdown voltage is reduced by breakdown at an end of a p-type body region in proximity to a portion in the vicinity of an annular intermediate region between an active cell region and a chip peripheral portion, arising from electric field concentration in that area. To solve this problem, the following measure is taken in a power semiconductor device having a superjunction structure in the respective drift regions of a first conductivity type of an active cell region, a chip peripheral region, and an intermediate region located therebetween: the width of at least one of column regions of a second conductivity type comprising the superjunction structure in the intermediate region is made larger than the width of the other regions. |
| US09786731B2 |
Display device and method for manufacturing same
A display device includes a substrate. A pixel electrode is disposed on the substrate. An auxiliary electrode is disposed on the substrate. A first auxiliary line is connected to the auxiliary electrode. A second auxiliary line is spaced apart from the auxiliary electrode. A top electrode contacts at least one of the auxiliary electrode, the first auxiliary line, or the second auxiliary line. An organic light emitting layer is disposed between the top electrode and the pixel electrode, and is disposed between the top electrode and the first and second auxiliary lines. |
| US09786728B2 |
Organic light emitting display device
Discussed is an organic light emitting display device that may include a first pixel on a substrate; a switching transistor with a first active layer provided inside the first pixel; a driving transistor with a second active layer provided inside the first pixel; a first light shielding layer overlapping the second active layer; and a second light shielding layer overlapping the first active layer, wherein the first light shielding layer is connected with the driving transistor, and the second light shielding layer is electrically insulated from the first light shielding layer. |
| US09786724B2 |
Organic light emitting diode display, optical unit, and method for manufacturing optical unit
An organic light emitting diode display includes: a display module including a first organic light emitting diode to emit light with a first wavelength, a second organic light emitting diode to emit light with a second wavelength, and a third organic light emitting diode to emit light with a third wavelength; a phase difference layer including a first liquid crystal pattern on the first organic light emitting diode, and a second liquid crystal pattern on the second organic light emitting diode and the third organic light emitting diode; and a linear polarization layer on the phase difference layer. |
| US09786723B2 |
Pixel circuit, driving method thereof and display apparatus
A pixel circuit includes a display unit and a touch control unit. The display unit includes a light-emitting element, a storage capacitor, a driving transistor for using the data signal stored in the storage capacitor to drive a light-emitting element (11) to emit light, a power switch module for inputting an operating voltage into the driving transistor, a precharging module for charging a control terminal of the driving transistor, and a compensation module for compensating a data signal and write the compensated data signal into the storage capacitor. The touch control unit includes an initialization module for initializing the touch control module while the precharging module is operating, a touch control module for collecting touch control signals in corresponding regions, and an output control module for closing an output path to output the touch control signals collected by the touch control module which the compensation module is operating. |
| US09786717B2 |
Method of manufacturing photoelectric conversion device
A method of manufacturing a photoelectric conversion device includes forming a wiring structure above a semiconductor substrate including a photoelectric converter, forming, by a plasma CVD method, a first insulating film which contains hydrogen, above an uppermost wiring layer in the wiring structure, performing, after formation of the first insulating film, first annealing in a hydrogen containing atmosphere on a structure including the semiconductor substrate, the wiring structure, and the first insulating film, forming a second insulating film above the first insulating film after the first annealing, and performing, after formation of the second insulating film, second annealing in the hydrogen containing atmosphere on a structure including the semiconductor substrate, the wiring structure, the first insulating film, and the second insulating film. |
| US09786715B2 |
High efficiency wide spectrum sensor
An optical sensor including a first material layer comprising at least a first material; a second material layer comprising at least a second material that is different from the first material, where a material bandgap of the first material is larger than a material bandgap of the second material; and a graded material layer arranged between the first material layer and the second material layer, the graded material layer comprising an alloy of at least the first material and the second material having compositions of the second material that vary along a direction that is from the first material to the second material. |
| US09786713B2 |
Solid-state image pickup apparatus, method of manufacturing the same, and electronic apparatus
A solid-state image pickup apparatus includes an image pickup pixel and a focus detection pixel. The image pickup pixel includes a micro lens and a photoelectric conversion unit that receives light incident from the micro lens. The focus detection pixel includes the micro lens, the photoelectric conversion unit, and a light shielding unit that shields part of light incident on the photoelectric conversion unit. In the solid-state image pickup apparatus, the micro lens is uniformly formed in the image pickup pixel and the focus detection pixel, and the focus detection pixel further includes a high refractive index film formed under the micro lens. |
| US09786712B2 |
Radiation image pickup unit and radiation image pickup display system
There is provided a radiation image pickup unit including: a plurality of pixels each configured to generate a signal charge based on a radiation; a device substrate including a photoelectric conversion element for each pixel; a wavelength conversion layer provided on a light incident side of the device substrate, and configured to convert a wavelength of the radiation into other wavelength; and a partition wall separating the wavelength conversion layer for each pixel. The radiation image pickup unit is configured to allow a gap between the wavelength conversion layer and the device substrate to be equal to or larger than a threshold or equal to or smaller than the threshold, the threshold being preset based on a spatial frequency of an image pickup target. |
| US09786711B2 |
Array substrate of X-ray sensor and method for manufacturing the same
An array substrate of an X-ray sensor and a method for manufacturing the same are provided, the method comprising a step of forming a thin-film transistor element and a photodiode sensor element, wherein the step of forming the thin-film transistor element comprises: forming a gate electrode on an base substrate by a mask process; depositing a gate insulating layer on the base substrate on which the gate electrode is formed; the step of forming the photodiode sensor element comprises: forming an ohmic contact layer on the base substrate through the same mask process while forming the gate electrode; forming a semiconductor layer and a transparent electrode through a mask process on the substrate on which the ohmic contact layer is formed; depositing the gate insulating layer on the base substrate on which the semiconductor layer and the transparent electrode are formed while depositing the gate insulating layer on the base substrate on which the gate electrode is formed. A gate pattern and an ohmic contact layer are formed through the same mask process, and a passivation layer substitutes a channel blocking layer to reduce the number of the mask processes and simplify the manufacturing process and improve throughput and yield of the product. |
| US09786708B2 |
Unit pixel having an insulated contact penetrating a charge accumulation region, solid-state image pickup unit including the same, and method of manufacturing the unit pixel
A solid-state image pickup unit including a pixel section having a plurality of unit pixels two-dimensionally arranged in a matrix formation, wherein a unit pixel includes a conductive region of a first conductivity type having a surface adjacent to a multilayer wiring layer, a charge accumulation region of a second conductivity type formed within the first conductive region, wherein the charge accumulation region is separated from the surface of the conductive region adjacent to the multilayer wiring layer by a separation section, and a contact disposed in the conductive region, the contact electrically connecting the charge accumulation region and an external wire of the multilayer wiring layer. |
| US09786703B2 |
Buried channel deeply depleted channel transistor
Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region. |
| US09786702B2 |
Backside illuminated image sensors having buried light shields with absorptive antireflective coating
An image sensor with an array of image sensor pixels is provided. Each image pixel may include a photodiode and associated pixel circuits formed in the front surface of a semiconductor substrate. Buried light shielding structures may be formed on the back surface of the substrate to prevent pixel circuitry that is formed in the substrate between two adjacent photodiodes from being exposed to incoming light. The buried light shielding structures may be lined with absorptive antireflective coating material to prevent light from being reflected off the surface of the buried light shielding structures. Forming buried light shielding structures with absorptive antireflective coating material can help reduce optical pixel crosstalk and enhance signal to noise ratio. |
| US09786698B2 |
Liquid crystal display device and manufacturing method thereof
A liquid crystal display device is disclosed. The liquid crystal display device includes a first substrate, a second substrate opposite of the first substrate, and a TFT layer on the first substrate. The TFT layer includes a gate electrode metal layer, and a source/drain electrode metal layer, where the source/drain electrode metal layer overlaps the gate electrode metal layer. The display device also includes an alignment film layer on a side of the first substrate that faces the second substrate, and on a side of the second substrate that faces the first substrate. The display device also includes at least one protrusion on at least a part of a side of at least one of the gate electrode metal layer and the source/drain electrode metal layer that faces the first substrate, where the protrusion is configured to reflect incident light from a side of the first substrate. |
| US09786694B2 |
Display device and manufacturing method thereof
A display device and a method of manufacturing the display device are provided. According to an exemplary embodiment, a display device includes: a substrate; a gate electrode disposed on the substrate; a semiconductor pattern disposed on the gate electrode; data wiring disposed on the semiconductor pattern and having a data line, a source electrode, and a drain electrode; a first barrier layer disposed between the data wiring and the semiconductor pattern; and undercuts disposed on at least one side of each segment of the first barrier layer. |
| US09786693B2 |
Thin film transistor substrate
A display panel is disclosed, which comprises: a first substrate; a scan line disposing on the first substrate; a data line disposing on the first substrate and overlapping with the scan line to form a first overlapping region; and an active layer disposing between the scan line and the data line and overlapping with the scan line and the data line to form a second overlapping region, wherein the second overlapping region locates in the first overlapping region and has a via, wherein an edge of the scan line has a first length along a substantial extension direction of the scan line in the first overlapping region, the active layer has a second length along a substantial extension direction of the scan line in the second overlapping region, and the second length is greater than the first length. |
| US09786691B2 |
TFT substrate structure
The present invention provides a TFT substrate structure, comprising a Switching TFT and a Driving TFT, and the Switching TFT comprises a first active layer, and the Driving TFT comprises a second active layer, and the first active layer and the second active layer are made by the same or different materials and the electrical properties of the Switching TFT and the Driving TFT are different. According to the different functions of the different TFTs, the present invention employs different working structures for the Switching TFT and the Driving TFT to respectively implement deposition and photolithography, and employs different materials for the active layers of the Switching TFT and the Driving TFT to differentiate the electrical properties of different TFTs in the TFT substrate. Accordingly, the accurate control to the OLED with lowest cost can be realized. |
| US09786684B2 |
Apparatuses having a ferroelectric field-effect transistor memory array and related method
An apparatus comprises field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates extending vertically and spaced horizontally between the plurality of FET structures, and a ferroelectric material separating the FET structures and the gates. Individual ferroelectric FETs (FeFETs) are formed at intersections of the FET structures, the gates, and the ferroelectric material. Another apparatus comprises a plurality of bit lines and word lines. Each bit line has at least two sides that are coupled with a ferroelectric material such that each bit line is shared by neighboring gates to form a plurality of FeFETs. A method of operating a memory array comprises applying a combination of voltages to a plurality of word lines and digit lines for a desired operation for a plurality of FeFET memory cells, at least one digit line having the plurality of FeFET memory cells accessible by neighboring gates. |
| US09786682B1 |
Manufacturing method of semiconductor device including barrier pattern
The invention is related to a method for manufacturing a semiconductor device having a barrier pattern. The method includes alternately forming first sacrificial layers and insulating layers forming channel patterns penetrating the first sacrificial layers and the insulating layers, and forming a slit penetrating the first sacrificial layers and the insulating layers. In order to form the barrier pattern, the method also includes forming openings by removing the first sacrificial layers through the slit, and respectively forming conductive layers in the openings. The conductive layers include first barrier patterns having inclined inner surfaces and metal patterns in the first barrier patterns. |
| US09786677B1 |
Memory device having memory cells connected in parallel to common source and drain and method of fabrication
A memory device may include a memory unit having multiple channel structures connected to a common source and drain in parallel. The memory unit can include floating gate structures including control gates connected to word lines and charge trap layers to store charge to form tiered floating gate memory cells. In some embodiments, rows and columns of memory units can be connected to form a three dimensional memory device. A method of fabricating a memory unit having tiered channel structures utilizing common source and drain elements and 3D memory device utilizing rows and columns of memory units having multiple channel structures connected to the common source and drain elements in parallel is disclosed. |
| US09786675B2 |
Non-volatile memory devices including charge storage layers
A non-volatile memory device includes gate electrodes stacked on a substrate, a semiconductor pattern penetrating the gate electrodes and connected to the substrate, and a charge storage layer between the semiconductor pattern and the gate electrodes. The charge storage layer includes a first charge storage layer between the semiconductor pattern and the gate electrodes, a second charge storage layer between the first charge storage layer and the semiconductor pattern, and a third charge storage layer between the first charge storage layer and the gate electrodes. An energy band gap of the first charge storage layer is smaller than those of the second and third charge storage layers. The first charge storage layer is thicker than the second and third charge storage layers. |
| US09786674B2 |
Discrete storage element formation for thin-film storage device
Provided is a method of forming a decoupling capacitor device and the device thereof. The decoupling capacitor device includes a first dielectric layer portion that is deposited in a deposition process that also deposits a second dielectric layer portion for a non-volatile memory cell. Both portions are patterned using a single mask. A system-on-chip (SOC) device is also provided, the SOC include an RRAM cell and a decoupling capacitor situated in a single inter-metal dielectric layer. Also a method for forming a process-compatible decoupling capacitor is provided. The method includes patterning a top electrode layer, an insulating layer, and a bottom electrode layer to form a non-volatile memory element and a decoupling capacitor. |
| US09786669B2 |
Memory device and manufacturing method the same
A semiconductor device that can transmit and receive data without contact is popular partly as some railway passes, electronic money cards, and the like; however, it has been a prime task to provide an inexpensive semiconductor device for further popularization. In view of the above current conditions, a semiconductor device of the present invention includes a memory with a simple structure for providing an inexpensive semiconductor device and a manufacturing method thereof. A memory element included in the memory includes a layer containing an organic compound, and a source electrode or a drain electrode of a TFT provided in the memory element portion is used as a conductive layer which forms a bit line of the memory element. |
| US09786667B2 |
Floating body memory cell having gates favoring different conductivity type regions
A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described. |
| US09786666B2 |
Method to form dual channel semiconductor material fins
A silicon fin precursor is formed in an nFET device region and a fin stack comprising alternating material portions, and from bottom to top, of silicon and a silicon germanium alloy is formed in a pFET device region. A thermal anneal is then used to convert the fin stack into a silicon germanium alloy fin precursor. A thermal oxidation process follows that converts the silicon fin precursor into a silicon fin and the silicon germanium alloy fin precursor into a silicon germanium alloy fin. Functional gate structures can be formed straddling over each of the various fins. |
| US09786662B1 |
Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a first gate pattern is formed on the substrate, a first spacer is formed around the first gate pattern, part of the first gate pattern is removed to form a first slot, a first dielectric layer is formed into the first slot, and a replacement metal gate (RMG) process is performed to transform part of the first gate pattern into a metal gate. |
| US09786658B2 |
Fabrication method of a stack of electronic devices
This method comprises the following steps: a) providing a first structure successively comprising a first substrate, a first electronic device, and a first dielectric layer; a second structure successively comprising a second substrate, an active layer, a second dielectric layer, and a polycrystalline semiconductor layer, the active layer being designed to form a second electronic device; b) bombarding the polycrystalline semiconductor layer by a beam of species configured to form an amorphous part and to preserve a superficial polycrystalline part; c) bonding the first and second structures; d) removing the second substrate of the second structure; e) introducing dopants into the amorphous part, through the exposed active layer; f) thermally activating the dopants by recrystallization of the amorphous part. |
| US09786656B1 |
Integration of bipolar transistor into complimentary metal-oxide-semiconductor process
A fin heterojunction bipolar transistor (fin HBT) and a method of fabricating the fin HBT for integration with a fin complimentary metal-oxide-semiconductor (fin CMOS) into a BiCMOS fin device include forming a sub-collector layer on a substrate. The sub-collector layer includes silicon doped with arsenic (As+). A collector layer and base are patterned as fins along a first direction. An emitter layer is formed on the fins. The emitter layer is a continuous layer of epitaxially grown silicon. An oxide is deposited above the sub-collector layer, the base, and the emitter layer, and at least one contact is formed through the oxide to each of the sub-collector layer, the base, and the emitter layer. |
| US09786654B1 |
Electrostatic discharge protection semiconductor device
An ESD protection semiconductor device includes a substrate, a first isolation structure disposed in the substrate, a gate disposed on the substrate and overlapping a portion of the first isolation structure, a source region formed in the substrate at a first side of the gate, and a drain region formed in the substrate at a second side of the gate opposite to the first side. The substrate and the drain region include a first conductivity type, the source region includes a second conductivity type, and the first conductivity and the second conductivity type are complementary to each other. |
| US09786653B1 |
Self-balanced diode device
A self-balanced diode device includes a substrate, a doped well, at least one first conductivity type heavily doped fin and at least two second conductivity type heavily doped fins. The doped well is arranged in the substrate. The first conductivity type heavily doped fin is arranged in the doped well, arranged in a line along a first direction, and protruded up from a surface of the substrate. The second conductivity type heavily doped fins is arranged in the doped well, arranged in a line along a second direction intersecting the first direction, respectively arranged at two opposite sides of the first conductivity type heavily doped fin, and protruded up from the surface of the substrate. Each second conductivity type heavily doped fin and the first conductivity type heavily doped fin are spaced at a fixed interval. |
| US09786650B1 |
Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including snake open configured fill cells, and the second DOE including metal island open configured fill cells
A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOES), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of snake opens, and the second DOE contains fill cells configured to enable NC detection of metal island opens. The process may further include obtaining NC measurements from the first and/or second DOE(s) and using such measurements, at least in part, to selectively perform additional processing, metrology or inspection steps on the wafer, and/or on other wafer(s) currently being manufactured. |
| US09786649B1 |
Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including stitch open configured fill cells
A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOES), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of via opens, and the second DOE contains fill cells configured to enable NC detection of stitch opens. The process may further include obtaining NC measurements from the first and/or second DOE(s) and using such measurements, at least in part, to selectively perform additional processing, metrology or inspection steps on the wafer, and/or on other wafer(s) currently being manufactured. |
| US09786647B1 |
Semiconductor layout structure
A semiconductor layout structure includes a substrate comprising a cell edge region and a dummy region abutting thereto, a plurality of dummy contact patterns disposed in the dummy region and arranged along a first direction, and a plurality of dummy gate patterns disposed in the dummy region and arranged along the first direction. The dummy contact patterns and the dummy gate patterns are alternately arranged. Each dummy contact pattern includes an inner dummy contact proximal to the cell edge region and an outer dummy contact distal to the cell edge region, and the inner dummy contact and the outer dummy contact are arranged along a second direction perpendicular to the first direction and spaced apart from each other by a first gap. |
| US09786641B2 |
Packaging optoelectronic components and CMOS circuitry using silicon-on-insulator substrates for photonics applications
Package structures and methods are provided to integrate optoelectronic and CMOS devices using SOI semiconductor substrates for photonics applications. For example, a package structure includes an integrated circuit (IC) chip, and an optoelectronics device and interposer mounted to the IC chip. The IC chip includes a SOI substrate having a buried oxide layer, an active silicon layer disposed adjacent to the buried oxide layer, and a BEOL structure formed over the active silicon layer. An optical waveguide structure is patterned from the active silicon layer of the IC chip. The optoelectronics device is mounted on the buried oxide layer in alignment with a portion of the optical waveguide structure to enable direct or adiabatic coupling between the optoelectronics device and the optical waveguide structure. The interposer is bonded to the BEOL structure, and includes at least one substrate having conductive vias and wiring to provide electrical connections to the BEOL structure. |
| US09786636B2 |
Semiconductor device and structure
An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; a first wire structure constructed to provide power to a portion of the first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second single crystal transistors, the second layer overlying the at least one metal layer; and a second wire structure constructed to provide power to a portion of the second transistors, where the second wire structure is isolated from the first wire structure to provide a different power voltage to the portion of the second transistors. |
| US09786635B2 |
Integrated circuit package assembly
An integrated circuit package assembly includes a substrate and a first integrated circuit package over the substrate. The integrated circuit package assembly also includes a second integrated circuit package between the first integrated circuit package and the substrate. The integrated circuit package further includes solder bumps between the first integrated circuit package and the second integrated circuit package. The solder bumps are configured to electrically connect the first integrated circuit package and the second integrated circuit package. The integrated circuit package assembly further includes at least two support structures between and in direct contact with the second integrated circuit package and the substrate. The at least two support structures are configured to facilitate thermal conduction between the second integrated circuit package and the substrate without providing electrical connections. |
| US09786631B2 |
Device package with reduced thickness and method for forming same
A device package includes a die and a molding compound around the die. The molding compound has a non-planar surface recessed from a top surface of the die. The device package also includes an interconnect structure over the die. The interconnect structure includes a redistribution layer extending onto the molding compound and conformal to the non-planar surface of the molding compound. The device package further includes a first connector disposed over the die and bonded to the interconnect structure. |
| US09786630B2 |
Semiconductor device manufacturing method and semiconductor wafer
A semiconductor device manufacturing method improves the yield of manufacturing semiconductor devices. There are provided an insulating film for covering multiple bonding pads, a first protective film over the insulating film, and a second protective film over the first protective film. In semiconductor chips, multiple electrode layers are coupled electrically to each of the bonding pads via first openings formed in the insulating film and second openings formed in the first protective film. Multiple bump electrodes are coupled electrically to each of the electrode layers via third openings formed in the second protective film. In pseudo chips, the second openings are formed in the first protective film and the third openings are formed in the second protective film. The insulating film is exposed at the bottom of the second openings coinciding with the third openings. A protective tape is applied to a principal plane to cover the bump electrodes. |
| US09786627B2 |
Method for creating a connection between metallic moulded bodies and a power semiconductor which is used to bond to thick wires or strips
The invention relates to a method for connecting a power semi-conductor chip having upper-sided potential surfaces to thick wires or strips, consisting of the following steps: Providing a metal molded body corresponding to the shape of the upper-sided potential surfaces, applying a connecting layer to the upper-sided potential surfaces or to the metal molded bodies, and applying the metal molded bodies and adding a material fit, electrically conductive compound to the potential surfaces prior to the joining of the thick wire bonds to the non-added upper side of the molded body. |
| US09786621B2 |
Elongated bump structures in package structure
A package structure includes a chip attached to a substrate. The chip includes a bump structure including a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar. The substrate includes a pad region and a mask layer overlying the pad region, wherein the mask layer has an opening exposing a portion of the pad region. The chip is attached to the substrate to form an interconnection between the conductive pillar and the pad region. The opening has a first dimension (d1) measured along the long axis and a second dimension (d2) measured along the short axis. In an embodiment, L is greater than d1, and W is less than d2. |
| US09786617B2 |
Chip packages and methods of manufacture thereof
A chip package may include a die and a redistribution structure over the die. The redistribution structure may include a die, a redistribution structure over the die, and an under-bump metallurgy (UBM) structure over the redistribution structure. The UBM structure may include a central portion, a peripheral portion physically separated from and surrounding a perimeter of the central portion, and a bridging portion having a first end and a second end opposite the first end. The first end of the bridging portion may be coupled to the central portion of the UBM structure, while the second end of the bridging portion may be coupled to the peripheral portion of the UBM structure. |
| US09786613B2 |
EMI shield for high frequency layer transferred devices
Various methods and devices that involve EMI shields for radio frequency layer transferred devices are disclosed. One method comprises forming a radio frequency field effect transistor in an active layer of a semiconductor on insulator wafer. The semiconductor on insulator wafer has a buried insulator side and an active layer side. The method further comprises bonding a second wafer to the active layer side of the semiconductor on insulator wafer. The method further comprises forming a shield layer for the semiconductor device. The shield layer comprises an electrically conductive material. The method further comprises coupling the radio frequency field effect transistor to a circuit comprising a radio frequency component. The method further comprises singulating the radio frequency field effect transistor, radio frequency component, and the shield layer into a die. The shield layer is located between a substrate of the radio frequency component and the radio frequency field effect transistor. |
| US09786606B2 |
Semiconductor structures with isolated ohmic trenches and stand-alone isolation trenches and related method
A method of forming a semiconductor structure in a semiconductor-on-insulator (SOI) substrate and semiconductor structure so formed are provided. The SOI substrate includes a semiconductor layer; a bulk semiconductor region underlying the semiconductor layer; and an insulation layer between the two. The structure includes first and second openings each having sidewalls, each of the first opening and the second opening formed substantially simultaneously and extending from a top surface of the semiconductor layer through the semiconductor layer and through the insulation layer to the conductive region; an insulating material adapted to provide electrical insulation to at least a portion of the side walls of the first opening; a semiconductor material at least partially filling the first opening, the semiconductor material defining an ohmic contact trench providing electrical contact with the semiconductor region; and an insulating material disposed in the second opening and defining a device isolation trench. |
| US09786604B2 |
Metal cap apparatus and method
A method of forming a metal layer may include forming an opening in a substrate; forming a liner over sidewalls of the opening; filling the opening with a first metal; etching a top surface of the first metal to form a recessed top surface below a top surface of the substrate; and exposing the recessed top surface of the first metal to a solution, the solution containing a second metal different from the first metal, the exposing causing the recessed top surface of the first metal to attract the second metal to form a cap layer over the recessed top surface of the first metal. |
| US09786600B2 |
Semiconductor devices including bit line contact plug and peripheral transistor
A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode. |
| US09786593B1 |
Semiconductor device and method for forming the same
A semiconductor device with a ring structure surrounding a through silicon via (TSV) electrode and a method for forming the same are disclosed. The method includes receiving a substrate including a back side and a front side having a conductor thereon, forming a via hole in the substrate and exposing the conductor, forming a groove extending from the back side into the substrate and surrounding the via hole, forming a first material layer in the via hole, and forming a second material layer in the groove. The groove filled with the second material layer forms the ring structure, while the via hole filled with the first material layer forms the TSV electrode. |
| US09786589B2 |
Method for manufacturing package structure
A method for manufacturing a package structure carries out in following way. A flexible circuit board is provided. The flexible circuit board defines a bent area and a laminated area. The flexible circuit board includes a first dielectric layer, a first conductive pattern and a bearing layer located at opposite sides. The bearing layer corresponds to the laminated area. A second dielectric layer and a second conductive pattern are formed on the first conductive pattern. A third dielectric layer and a third conductive pattern are formed on the bearing layer. All of the second and third dielectric layers, and the second and third conductive pattern corresponds to the laminated area. A first solder resist layer is formed on the second conductive layer. The first solder resist layer defines a plurality of openings, a portion of the second conductive pattern is exposed from the openings defining a plurality of first pads. |
| US09786588B2 |
Circuit substrate and package structure
The invention provides a circuit substrate and a package structure. The circuit substrate includes a molding compound having a chip-side surface and a solder ball-side surface opposite from the chip side surface. A first conductive bulk is formed embedded in the molding compound. The first conductive bulk has a first number of first chip-side bond pad surfaces and a second number of first solder ball-side surfaces exposed from the chip side surface and the ball-side surface, respectively. The width of the first conductive bulk is greater than the first width of the first chip-side bond pad surfaces and the second width of the first solder ball-side surfaces. |
| US09786587B2 |
Semiconductor device and method for manufacturing the semiconductor device
A semiconductor device is disclosed in which an implant board and a semiconductor element of a semiconductor mounting board are bonded and electrically connected through implant pins and which can be manufactured with high productivity. Implant pins are bonded to a semiconductor element and/or a circuit pattern of a semiconductor mounting board through cylindrical terminals press-fitted into the other ends of the implant pins. Press-fitting depth L2 of each of the implant pins into corresponding cylindrical terminals is adjustable, so that total length of the implant pin and cylindrical terminal which are press-fitted to each other matches up with the distance between the semiconductor element and/or the circuit pattern on the semiconductor mounting board and an implant board. |
| US09786575B2 |
Printed circuit module having semiconductor device with a polymer substrate and methods of manufacturing the same
A printed circuit module and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned die attached to the printed circuit substrate. The thinned die includes at least one device layer over the printed circuit substrate and a buried oxide (BOX) layer over the at least one device layer. A polymer layer is disposed over the BOX layer, wherein the polymer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 103 Ohm-cm. |
| US09786574B2 |
Thin film based fan out and multi die package platform
Thin film based fan out wafer level packaging and a method of manufacturing the same are disclosed. Embodiments include a method including forming tapered via holes in a first surface of a polymer film; forming a conductive pillar on the first surface of a semiconductor device; bonding a solderable surface of the conductive copper pillars to metallization on the second side of the polymer film; bonding the semiconductor device to the first surface of the polymer film over the conductive pillars with an underfill material; and depositing an encapsulant material over the semiconductor device and polymer film. |
| US09786573B2 |
Electronic component package
An electronic component package includes: a core including a cavity, a first resin layer, a second resin layer and a reinforcing layer disposed between the first resin layer and the second resin layer; and an electronic component disposed in the cavity, wherein a thickness of the first resin layer is different from a thickness of the second resin layer. |
| US09786570B2 |
Methods for depositing films on sensitive substrates
Methods and apparatus to form films on sensitive substrates while preventing damage to the sensitive substrate are provided herein. In certain embodiments, methods involve forming a bilayer film on a sensitive substrate that both protects the underlying substrate from damage and possesses desired electrical properties. Also provided are methods and apparatus for evaluating and optimizing the films, including methods to evaluate the amount of substrate damage resulting from a particular deposition process and methods to determine the minimum thickness of a protective layer. The methods and apparatus described herein may be used to deposit films on a variety of sensitive materials such as silicon, cobalt, germanium-antimony-tellerium, silicon-germanium, silicon nitride, silicon carbide, tungsten, titanium, tantalum, chromium, nickel, palladium, ruthenium, or silicon oxide. |
| US09786569B1 |
Overlay measurement and compensation in semiconductor fabrication
A method includes receiving a device having a first layer and a second layer over the first layer, the first layer having a first overlay mark. The method further includes forming a first resist pattern over the second layer, the first resist pattern having a second overlay mark. The method further includes performing a first overlay measurement using the second overlay mark in the first resist pattern and the first overlay mark; and performing one or more first manufacturing processes, thereby transferring the second overlay mark into the second layer and removing the first resist pattern. The method further includes performing one or more second manufacturing processes that include forming a third layer over the second layer. After the performing of the one or more second manufacturing processes, the method includes performing a second overlay measurement using the second overlay mark in the second layer and the first overlay mark. |
| US09786568B2 |
Method of manufacturing an integrated circuit substrate
A method of manufacturing a wafer. The method includes providing a wafer that includes a plurality of semiconductor device structures, and testing at least one of the plurality of semiconductor device structures. Based on a test result, a substance is provided on a selected portion of the wafer to selectively configure a circuit element within the at least one of the plurality of semiconductor device structures. |
| US09786567B2 |
Chip-on-wafer process control monitoring for chip-on-wafer-on-substrate packages
An embodiment method includes providing a standardized testing structure design for a chip-on-wafer (CoW) structure, wherein the standardized testing structure design comprises placing a testing structure in a pre-selected area a top die in the CoW structure, and electrically testing a plurality of microbumps in the CoW structure by applying a universal testing probe card to the testing structure. |
| US09786564B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device includes a substrate, a first gate, a second gate, and an insulating structure. The substrate includes a first fin and a second fin. The first gate is disposed over the first fin. The second gate is disposed over the second fin. A gap is formed between the first gate and the second gate, and the gap gets wider toward the substrate. The insulating structure is disposed in the gap. The insulating structure has a top surface and a bottom surface opposite to each other. The bottom surface faces the substrate. An edge of the top surface facing the first gate is curved inward the top surface. |
| US09786558B2 |
Semiconductor devices including a bit line structure and a contact plug
Semiconductor devices are provided. A semiconductor device includes a bit line structure and a contact plug. The contact plug is adjacent a sidewall of the bit line structure and is on a sloped surface of the bit line structure. Moreover, in some embodiments, a level of the sloped surface of the bit line structure becomes lower as the sloped surface approaches the sidewall of the bit line structure. |
| US09786555B1 |
Method for reducing contact resistance
Disclosed is a method for reducing contact resistance, including depositing a GST layer on an InGaAs substrate, generating an InGaAs/GST/Ni stacked structure by depositing a Ni layer on the GST layer, and thermally treating the stacked structure to rearrange components of the GST layer and to generate a Ni—InGaAs alloy. |
| US09786551B2 |
Trench structure for high performance interconnection lines of different resistivity and method of making same
An integrated circuit includes a substrate with an interlevel dielectric layer positioned above the substrate. First trenches having a first depth are formed in the interlevel dielectric layer and a metal material fills the first trenches to form first interconnection lines. Second trenches having a second depth are also formed in the interlevel dielectric layer and filled with a metal material to form second interconnection lines. The first and second interconnection lines have a substantially equal pitch, which in a preferred implementation is a sub-lithographic pitch, and different resistivities due to the difference in trench depth. The first and second trenches are formed with an etching process through a hard mask having corresponding first and second openings of different depths. A sidewall image transfer process is used to define sub-lithographic structures for forming the first and second openings in the hard mask. |
| US09786550B2 |
Low resistance metal contacts to interconnects
A semiconductor device and a method of fabricating a contact to interface with an interconnect in a semiconductor device are described. The device includes a dielectric layer formed on a semiconductor layer, and a contact fabricated in a via formed within the dielectric layer. An interconnect formed above the contact interfaces with an exposed surface of the contact opposite a surface closest to the semiconductor layer. The contact includes a contact material in a first portion of the contact and an interface metal in a second portion of the contact. |
| US09786545B1 |
Method of forming ANA regions in an integrated circuit
A method includes providing a structure having a first hardmask layer, interposer layer, second hardmask layer and mandrel layer disposed respectively over a dielectric stack. An array of mandrels is patterned into the mandrel layer with a mandrel mask. An ANA trench is patterned into the mandrel layer with a first cut mask. The ANA trench is patterned into the interposer layer with a second cut mask. An organic planarization layer (OPL) is disposed over the structure. The OPL is etched to dispose it only in the ANA trench such that a top surface of the OPL is lower than the second hardmask layer. The structure is etched to form a pattern in a dielectric layer of the dielectric stack to form an array of metal lines in the dielectric layer, a portion of the pattern formed by the ANA trench forms an ANA region within the dielectric layer. |
| US09786544B2 |
Floating body memory cell apparatus and methods
Some embodiments include apparatus and methods having a base; a memory cell including a body, a source, and a drain; and an insulation material electrically isolating the body, the source, and the drain from the base, where the body is configured to store information. The base and the body include bulk semiconductor material. Additional apparatus and methods are described. |
| US09786543B2 |
Isolation structure of semiconductor device
The invention relates to an isolation structure of a semiconductor device and a method of forming. An exemplary isolation structure for a semiconductor device comprises a substrate comprising a trench; a strained material in the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an oxide layer of the strained material over the strained material; a high-k dielectric layer over the oxide layer; and a dielectric layer over the high-k dielectric layer filling the trench. |
| US09786536B2 |
Reticle rack system
The present disclosure relates to semiconductor manufacturing, in particular to reticle rack systems. The teachings of the present disclosure may be embodied in a reticle rack unit including a frame with four uprights and multiple crossbars and four turnstiles. The frame may have a longest dimension defining a front side and a back side. The four turnstiles may be mounted to the frame to pivot around a respective rotational axis parallel to the four uprights. Each turnstile may define a plurality of reticle nests sized to hold reticles. |
| US09786530B2 |
Wafer transfer method and system
A wafer transfer method includes the following steps. An initial position of a first wafer in a wafer cassette is detected. A picking entry position in the wafer cassette is determined based on the initial position of the first wafer, in which the picking entry position is spaced apart from the initial position of the first wafer. A wafer transfer blade is moved to the picking entry position. |
| US09786527B2 |
Substrate processing device and substrate processing method for carrying out chemical treatment for substrate
It is an object to reduce a chemical treating width in a peripheral edge part of a substrate while suppressing deterioration in each of uniformity of the chemical treating width and processing efficiency. In order to achieve the object, a substrate processing device for carrying out a chemical treatment for a substrate using a processing liquid having a reaction rate increased with a rise in temperature includes a substrate holding portion, a rotating portion for rotating the substrate held in the substrate holding portion in a substantially horizontal plane, a heating portion for injecting heating steam to a central part of a lower surface of the substrate to entirely heat the substrate, and a peripheral edge processing portion for supplying the processing liquid from above to a peripheral edge part of the substrate heated by the heating portion, thereby carrying out a chemical treatment for the peripheral edge part. |
| US09786525B2 |
Apparatus for processing semiconductor wafers, in particular for carrying out a polymers removal process step
An apparatus for processing semiconductor wafers includes at least a wet bench and an automatic handling system of a wafer carrier removably connected thereto. The wet bench includes a first processing tank, a second processing tank and a third processing tank, separated from one another, each processing tank being dedicated to a different chemical, as well as a special cleaning and drying tank for processing the automatic handling system when the wafer carrier has been removed. |
| US09786524B2 |
Developing unit with multi-switch exhaust control for defect reduction
The present disclosure provides a developing unit that includes a wafer stage designed to secure a semiconductor wafer; an exhaust mechanism configured around the wafer stage and designed to exhaust a fluid from the semiconductor wafer; and a multi-switch integrated with the exhaust mechanism and designed to control the exhaust mechanism at various open states. |
| US09786517B2 |
Ablation method and recipe for wafer level underfill material patterning and removal
Introducing an underfill material over contact pads on a surface of an integrated circuit substrate; and ablating the introduced underfill material to expose an area of the contact pads using temporally coherent electromagnetic radiation. A method including first ablating an underfill material to expose an area of contact pads on a substrate using temporally coherent electromagnetic radiation; introducing a solder to the exposed area of the contact pads; and second ablating the underfill material using temporally coherent electromagnetic radiation. A method including introducing an underfill material over contact pads on a surface of an integrated circuit substrate; defining an opening in the underfill material to expose an area of the contact pads using temporally coherent electromagnetic radiation; introducing a solder material to the exposed area of the contact pads; and after introducing the solder, removing the sacrificial material. |
| US09786511B2 |
Sequential infiltration synthesis for advanced lithography
A plasma etch resist material modified by an inorganic protective component via sequential infiltration synthesis (SIS) and methods of preparing the modified resist material. The modified resist material is characterized by an improved resistance to a plasma etching or related process relative to the unmodified resist material, thereby allowing formation of patterned features into a substrate material, which may be high-aspect ratio features. The SIS process forms the protective component within the bulk resist material through a plurality of alternating exposures to gas phase precursors which infiltrate the resist material. The plasma etch resist material may be initially patterned using photolithography, electron-beam lithography or a block copolymer self-assembly process. |
| US09786510B2 |
Fin-shaped structure and manufacturing method thereof
A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In one case, a substrate having a first fin-shaped structure and a second fin-shaped structure is provided. A treatment process is performed to modify an external surface of the top of the second fin-shaped structure, thereby forming a modified part. A removing process is performed to remove the modified part through a high removing selectivity to the first fin-shaped structure and the second fin-shaped structure, and the modified part, thereby the second fin-shaped structure having a ladder-shaped cross-sectional profile part is formed. |
| US09786507B2 |
Methods of forming field effect transistors using a gate cut process following final gate formation
Disclosed are field effect transistor (FET) formation methods using a final gate cut process and the resulting structures. One method forms an elongated gate across first and second semiconductor bodies for first and second FETs, respectively. An opening is formed in a portion of the elongated gate between the semiconductor bodies, cutting at least the gate conductor layer. The opening is filled with an isolation layer, thereby forming an isolation region that segments the elongated gate into first and second gates for the first and second FETs, respectively. Another method forms at least three gates across an elongated semiconductor body. An isolation region is formed that extends, not only through a portion of a center one of the gates, but also through a corresponding portion of the elongated semiconductor body adjacent to that gate, thereby segmenting the elongated semiconductor body into discrete semiconductor bodies for first and second FETs. |
| US09786506B2 |
Array substrate, manufacturing method therefor and display device
Provided is a manufacturing method for an array substrate, which relates to the technical field of displaying and comprises the steps of: S1: forming a pattern which comprises a first gate electrode (2) on a substrate (1); S2: forming a second gate electrode (4) above the first gate electrode (2) on the substrate (1) after step S1, and conducting oxidation treatment on the surface of the second gate electrode (4) to form a gate-insulating layer, the first gate electrode (2) and the second gate electrode (4) forming a gate electrode together; and S3: forming a layer-level structure of a pattern which comprises an active layer, source and drain electrodes, a data line, a passivation layer and a pixel electrode on the substrate after step S2. Also provided are an array substrate and a display device. |
| US09786503B2 |
Method for increasing pattern density in self-aligned patterning schemes without using hard masks
Provided is a method for increasing pattern density of a structure using an integration scheme and perform pitch splitting at the resist level without the use of hard mandrels, the method comprising: providing a substrate having a patterned resist layer and an underlying layer comprising a silicon anti-reflective coating layer, an amorphous layer, and a target layer; performing a resist hardening process; performing a first conformal spacer deposition using an atomic layer deposition technique with an oxide, performing a spacer first reactive ion etch process and a first pull process on the first conformal layer, performing a second conformal spacer deposition using titanium oxide; performing a second spacer RIE process and a second pull process, generating a second spacer pattern; and transferring the second spacer pattern into the target layer, wherein targets include patterning uniformity, pulldown of structures, slimming of structures, aspect ratio of structures, and line width roughness. |
| US09786494B2 |
Film formation method and film formation apparatus
Disclosed is a film formation method, including vaporizing a plurality of raw material monomers in respective corresponding vaporizers, supplying the plurality of raw material monomers into a film formation apparatus, causing vapor deposition polymerization of the plurality of raw material monomers in the film formation apparatus to form an organic film on a substrate, and removing an impurity contained in at least one raw material monomer among the plurality of raw material monomers before the vapor deposition polymerization. |
| US09786492B2 |
Formation of SiOCN thin films
Methods for depositing silicon oxycarbonitride (SiOCN) thin films on a substrate in a reaction space are provided. The methods can include at least one plasma enhanced atomic layer deposition (PEALD) cycle including alternately and sequentially contacting the substrate with a silicon precursor and a second reactant that does not include oxygen. In some embodiments the methods allow for the deposition of SiOCN films having improved acid-based wet etch resistance. |
| US09786486B2 |
Parallel multi wafer axial spin clean processing using spin cassette inside movable process chamber
A system and method concurrently processes multiple wafers. A cassette structure includes multiple chucks and a drive spool for supporting and rotating the chucks. Each chuck holds a wafer in position while rotating. The cassette structure is loaded into a process chamber. Each chuck includes a self-locking mechanism that is activated by the centrifugal force generated from the rotation of the chuck. The self-locking mechanism centers and holds a wafer in position with respect to the chuck. A drive motor drives the drive spool, which causes the chucks to rotate. As the chucks are being rotated, a dispensing assembly delivers a processing chemical to the wafers. |
| US09786485B2 |
Mass analyser
A mass analyser comprises a pair of electrode arrays. Each array has a set of focusing electrodes which are supplied, in use, with voltage to create an electrostatic field in a space between the electrode arrays causing ions to undergo periodic, oscillatory motion in the space, ions passing between electrodes of the sets of focusing electrodes and being repeatedly focused at a center plane, mid-way between the electrode arrays. At least one electrode of each set of focusing electrodes has an electrode surface closer to the center plane than the electrode surfaces of other electrodes of the same set. The analyzer may be an ion trap mass analyser or a multi-turn ToF mass analyzer. |
| US09786481B2 |
Automated cleanliness diagnostic for mass spectrometer
A mass spectrometer or ion mobility spectrometer is disclosed comprising means for detecting a blockage in an inlet orifice arranged between an ion source and a vacuum chamber. The blockage is detected as a result of a reduction in pressure within the vacuum chamber. This change in pressure is detected indirectly by monitoring the amount of power that a vacuum pump is using, the amount of current that a vacuum pump is drawing, the temperature of a vacuum pump or a region in proximity to the vacuum pump, or the flow rate of gas out of a vacuum pump. |
| US09786480B2 |
Analytical apparatus utilizing electron impact ionization
An analytical apparatus for mass spectrometry comprises an electron impact ionizer including an electron emitter and an ionization target zone. The target zone is arranged to be populated with matter to be ionized for analysis. An electron extracting element is aligned with an electron pathway defined between the electron emitter and the ionization target zone. The electron extracting element is configured to accelerate electrons away from the emitter along the electron pathway between the emitter and the extracting element and to decelerate the electrons along the electron pathway between the extracting element and the ionization target zone to enable soft ionization while avoiding the effects of Coulombic repulsion at the electron source. |
| US09786468B2 |
Charged particle beam device
An object of the invention is to provide a charged particle beam apparatus capable of performing high-precision measurement even on a pattern in which a width of edges is narrow and inherent peaks of the edges cannot be easily detected. In order to achieve the above object, there is proposed a charged particle beam apparatus including an opening portion forming member having a passage opening of a charged particle beam and a detector for detecting charged particles emitted from a sample or charged particles generated by causing the charged particles to collide with the opening portion forming member, the charged particle beam apparatus including: a deflector for deflecting the charged particles emitted from the sample; and a control device for controlling the deflector, the control device performing pattern measurement with the use of a first detected signal in which a signal of one edge is emphasized relatively more than a signal of another edge among a plurality of edges on the sample and a second detected signal in which the signal of the another edge is emphasized relatively more than the signal of the one edge among the plurality of edges. |
| US09786461B2 |
Component unit, fusible link unit, and affixing structure for the component
Provided is a fusible link unit in which a case includes case-side locking portions to be locked in a fusible link so as to affix the fusible link, the fusible link includes fusible link-side locking portions locked in the case-side locking portions, the fusible link-side locking portion on one side in a longitudinal direction is provided closer to a connected position of a bus bar than the fusible link-side locking portion on the other side in the longitudinal direction, and a gap size between the fusible link-side locking portion on the one side and the case-side locking portion in a vertical direction is made greater than a gap size between the fusible link-side locking portion on the other side and the case-side locking portion in the vertical direction. |
| US09786460B2 |
Ground fault circuit interrupter (GFCI) system and method
A wiring device including a face contact; one or more line contact arms; one or more load contact arms; and a fault detection circuit. The one or more line contact arms having an upper line contact located on a bent portion of the line contact arm, and a lower line contact located on a substantially straight portion of the line contact arm. The one or more load contact arms having a load contact located on a bent portion of the load contact arm. The fault detection circuit that detects a fault condition in said wiring device and generates a fault detection signal when said fault condition is detected, wherein said fault detection signal electrically disconnects the face contact from the upper line contact and the lower line contact from the load contact. |
| US09786459B2 |
Normally closed microelectromechanical switches (MEMS), methods of manufacture and design structures
Normally closed (shut) micro-electro-mechanical switches (MEMS), methods of manufacture and design structures are provided. A structure includes a beam structure that includes a first end hinged on a first electrode and in electrical contact with a second electrode, in its natural state when not actuated. |
| US09786450B2 |
Membrane switch and object employing same
A membrane switch in which a first conductive part is formed on a first substrate, a second conductive part is formed on a second substrate, and the substrates are layered via a spacer such that the conductive parts face each other with a space therebetween, and an organic material showing piezoelectricity is filled, or disposed in the space such that an air gap is present, are useful for obtaining an output signal corresponding to an applied pressure. |
| US09786446B2 |
Switch
A switch includes a first arm that is rotatably supported, a first contact member that is provided at a free end of the first arm, a second arm that is rotatably supported, and a second contact member that is provided at a free end of the second arm and is to come into contact with the first contact member. After the first contact member and the second contact member have come into contact with each other, a point of contact between the first contact member and the second contact member is displaced with rotational motions of the first arm and the second arm. |
| US09786445B2 |
Supercapacitor configurations with graphene-based electrodes and/or peptide
One embodiment is an EDLC with a capacitor cell that includes two electrodes of opposite polarity aligned in parallel, and a peptide separator disposed between the electrodes. The separator may be a peptide coating on an electrode surface. Another embodiment is an electrode for an electrochemical energy storage device, such as an EDLC, the electrode including graphene and coated with peptide. The peptide may act as a separator for the EDLC. A further embodiment is an electrode for an electrochemical energy storage device, the electrode-unit including: two graphene layers, CNTs, and electrolyte. The graphene layers are arranged separated along a first axis and aligned with parallel surfaces, where at least one graphene layer is coated with peptide. The CNTs are arranged along a second axis orthogonal to the first axis and disposed between the graphene layers. The electrolyte is impregnated within the volume defined between the graphene layers and CNTs. |
| US09786444B2 |
Nano-structured flexible electrodes, and energy storage devices using the same
An electrical energy storage device structure comprises a first conductive sheet, a second conductive sheet and an electrolyte sheet placed between the first conductive sheet and the second conductive sheet. In the device, at least one of the first conductive sheet and the second conductive sheet comprises a layer of carbon nanoparticles. The carbon nanoparticle layer is arranged to be adjacent to the electrolyte sheet. The carbon nanoparticles may include both high aspect ratio carbon nanoparticles and low aspect ratio carbon nanoparticles. The device is flexible and at least partially transparent. |
| US09786438B2 |
Capacitor for multiple replacement applications
An apparatus suitable for use in an air-conditioning system and configured to provide a plurality of selectable capacitance values includes a plurality of capacitive devices and a pressure interrupter cover assembly. Each of the capacitive devices has a first capacitor terminal and a second capacitor terminal. The pressure interrupter cover assembly includes a deformable cover, a set of capacitor cover terminals, a common cover terminal, and a set of insulation structures. The apparatus also includes a conductor configured to electrically connect the second capacitor terminal of at least one of the capacitive devices to the common cover terminal. |
| US09786433B2 |
Reactor and manufacturing method thereof
First and second divisional cores each including right and left leg portions and a yoke interconnecting those together are formed by molding respective yoke-side core members in a resin. Cylindrical core mounting portions extending from the outer circumference of the surface of the yoke-side core member are formed integrally with the respective right and left leg portions of the first divisional core. I-shaped leg-portion-side core members and spacers are attached in the cylindrical core mounting portion formed in each of the right and left leg portions. The surface of the yoke-side core member molded in the resin and the surface of the leg-portion-side core member are disposed so as to have a spacer therebetween. The two divisional cores are joined together by butting respective leg portions of the two divisional cores with each other to form an annular mold core, and a coil is wound around the mold core. |
| US09786432B2 |
Coplanar energy transfer
An external transmitter inductive coil can be provided in, on, or with a belt designed to be placed externally around a part of a body of a patient. An implantable device (such as a VAD or other medical device) that is implanted within the patient's body has associated with a receiver inductive coil that gets implanted within that part of the patient's body along with the device. The externally-located transmitter inductive coil inductively transfers electromagnetic power into that part of the body and thus to the receiver inductive coil. The implanted receiver inductive coil thus wirelessly receives the inductively-transferred electromagnetic power, and operates the implant. |
| US09786431B2 |
Electrical power and/or electrical signal transmission
An electrical power and/or electrical signal transmission system for transmitting electrical power and/or electrical signals from a location on a first side of a metallic wall to a location on a second side of the metallic wall includes a transmitting apparatus having an electrical source and a first transformer. A receiving apparatus has a receiving module for receiving electrical power and/or electrical signals and a second transformer. First and second ends of a primary winding of the second transformer are electrically connected to respective spaced locations on the second, opposite, side of the metallic wall for picking up electrical power and/or electrical signals from the metallic wall. The receiving module is electrically connected to a secondary winding of the second transformer to enable electrical power and/or electrical signals to be transmitted from the electrical source to the receiving module. |
| US09786422B2 |
Independent control of two solenoid operated valves over two wires in an irrigation system
Apparatus 11 and 13 for interfacing two AC sources with two AC loads 17a 17b in the form of solenoid operated valves over a single conductor 25, with a return conductor 19 in an irrigation system is disclosed. The apparatus has an encoder circuit 11 with two inputs 21a 21b for connection to the two AC sources, and an output 23 for connection to the single conductor 25, and a decoder circuit 13 having an input 27 for connection to the conductor 25, and two outputs 29a 29b for connection to loads 17a 17b respectively. When the first input 21 a is powered, the first load 17a will be switched on, and when the second input 21b is powered, the second load 17b will be switched on. The decoder portion 13 incorporates switching circuits 43a 43b, interfaced with turn on delay timers 45a 45b respectively, to delay operating the loads at switch on, and turn-off delay timers 47a 47b to hold the loads on after switch off. |
| US09786419B2 |
Grain boundary diffusion process for rare-earth magnets
In at least one embodiment, a single sintered magnet is provided having a concentration profile of heavy rare-earth (HRE) elements within a continuously sintered rare-earth (RE) magnet bulk. The concentration profile may include at least one local maximum of HRE element concentration within the bulk such that a coercivity profile of the magnet has at least one local maximum within the bulk. The magnet may be formed by introducing alternating layers of an HRE containing material and a magnetic powder into a mold, pressing the layers into a green compact, and sintering the green compact to form a single, unitary magnet. |
| US09786414B2 |
Cable
A cable including a first insulating layer, a twisted pair, a ground structure, and at least one conducting element is provided. The twisted pair is disposed in the first insulating layer and includes two signal wires, wherein the two signal wires are intertwisted to each other. The ground structure is disposed at the first insulating layer. The conducting element includes a main body portion and at least one extending portion. The main body portion is disposed in the twisted pair to be surrounded by the two signal wires. The extending portion is connected to the main body portion and grounded to the ground structure. |
| US09786412B2 |
Cable moisture seal assemblies, systems and methods
A sealed cabled assembly includes a cable and a cable moisture seal assembly. The cable includes a cable subcore, a metal shield layer surrounding the cable subcore, and a jacket surrounding the metal shield layer. The cable subcore includes an electrical conductor surrounded by an electrical insulation layer. The cable moisture seal assembly includes a sealant, a electrically conductive jumper member, and an outer sleeve. The cable includes a sealing region section extending from a first axial end to a second axial end, and in which a section of the jacket and a section of the metal shield layer are removed to expose a section of the cable subcore. The insulation layer and the conductor extend through the sealing region section. First and second sections of the jacket extend away from the sealing region section in first and second opposed directions, respectively. First and second sections of the metal shield layer extend away from the sealing region section in the first and second opposed directions, respectively. The outer sleeve surrounds the sealing region section. The sealant is disposed radially between the cable subcore and the outer sleeve, and engages the cable subcore to form a moisture barrier in the sealing region section between the first and second sections of the jacket. The jumper member electrically connects the first and second sections of the metal shield layer. |
| US09786409B2 |
Metathesis polymers as dielectrics
Oxacycloolefinic polymers as typically obtained by metathesis polymerization using Ru-catalysts, show good solubility and are well suitable as dielectric material in electronic devices such as capacitors and organic field effect transistors. |
| US09786408B2 |
Renewable hydrocarbon based insulating fluid
Electrical equipment including insulating fluid and having isoparaffins derived from a renewable carbon source, the fluid having a flash point of at least 210° C. and comprising at least 70 wt % of the isoparaffins. The electrical equipment can be installed and operated subsea. |
| US09786406B2 |
Cellulose capsules
The present invention provides a composition having an interior hydrophobic space encapsulated by at least one non-derivatized cellulose molecular layer surrounded by a hydrophilic medium. The invention also provides methods for making an oil-in-water dispersion or water-in-oil dispersion by mixing a hydrophilic medium, a hydrophobic composition and non-derivatized cellulose solution in an ionic liquid or pure non-derivatized cellulose hydrogel. |
| US09786405B2 |
Forming patterned graphene layers
Structures and methods for forming a patterned graphene layer on a substrate. One such method includes forming at least one patterned structure of a carbide-forming metal or metal-containing alloy on a substrate, applying a layer of graphene on top of the at least one patterned structure of a carbide-forming metal or metal-containing alloy on the substrate, heating the layer of graphene on top of the at least one patterned structure of a carbide-forming metal or metal-containing alloy in an environment to remove graphene regions proximate to the at least one patterned structure of a carbide-forming metal or metal-containing alloy, and removing the at least one patterned structure of a carbide-forming metal or metal-containing alloy to produce a patterned graphene layer on the substrate, wherein the patterned graphene layer on the substrate provides carrier mobility for electronic devices. |
| US09786396B2 |
Decay heat conversion to electricity and related methods
Various embodiments of a decay heat conversion to electricity system and related methods are disclosed. According to one exemplary embodiment, a decay heat conversion to electricity system may include a spent fuel rack configured to pressurize spent fuel bundles to obtain superheated vapor to drive a turbine-driven pump and fast alternator all submerged with the spent fuel rack and positioned at the bottom of the spent fuel pool for conversion of electricity distributed outside of the spent fuel pool via cables without impairing spent fuel pool operations. |
| US09786392B2 |
Methods and systems for migrating fuel assemblies in a nuclear fission reactor
Illustrative embodiments provide methods and systems for migrating fuel assemblies in a nuclear fission reactor, methods of operating a nuclear fission traveling wave reactor, methods of controlling a nuclear fission traveling wave reactor, systems for controlling a nuclear fission traveling wave reactor, computer software program products for controlling a nuclear fission traveling wave reactor, and nuclear fission traveling wave reactors with systems for migrating fuel assemblies. |
| US09786391B2 |
Nuclear fuel pebble and method of manufacturing the same
A method of manufacturing nuclear fuel elements may include: forming a graphite base portion of the fuel element; depositing a first layer of graphite spheres on the base portion; depositing a first layer of fuel, burnable poison and/or breeder particles on the first layer of graphite spheres; forming a second layer of graphite spheres on the first layer of particles; depositing a second layer of fuel, burnable poison and/or breeder particles on the second layer of graphite spheres; and forming a graphite cap portion of the fuel element. Fuel, burnable poison and/or breeder particles of the first layer may be are spaced apart by substantially the same distance, and fuel, burnable poison and/or breeder particles of the second layer may be spaced apart by substantially the same distance. The fuel element may be a spherical fuel pebble. The fuel particles may be tri-structural-isotropic (TRISO) particles without an overcoat. |
| US09786388B1 |
Detecting and managing bad columns
A system, computer readable medium and a method. The method may include sending input data to a NAND flash memory unit that comprises the NAND flash memory array and instructing the NAND flash memory unit to write input data to the NAND flash memory array to provide programmed data; reading from the NAND flash memory array the programmed data to provide read data; comparing the input data and the read data to provide column errors statistics at a column resolution; and defining, by a flash memory controller, bad columns of the NAND flash memory array in response to the column error statistics. |
| US09786387B2 |
Semiconductor memory devices, memory systems including the same and method of correcting errors in the same
A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged. The semiconductor memory device includes an error correcting code (ECC) circuit configured to generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors in the read codeword on a per symbol basis based on the syndromes. The main data includes first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row. The first data and the second data are assigned to one symbol of a plurality of symbols, and the first memory cell and the second memory cell are adjacent to each other in the memory cell array. |
| US09786384B2 |
Display device
Disclosed is a display device including a light emission driver configured to sequentially generate a plurality of light emission signals having a disable level during a first period; and a scan driver configured to generate a plurality of shift outputs each having two enable pulses, and each outputting two scan signals, in response to two light emission signals among the plurality of light emission signals, by dividing the two enable pulses of a first shift output among the plurality of shift outputs, which correspond to the two light emission signals among the plurality of light emission signals, from each other. |
| US09786379B2 |
Data storage device and data maintenance method
A data storage device including a flash memory and a controller. The flash memory includes a plurality of pages and a plurality of word lines, wherein each of the word lines controls at least two of the pages. The controller reads a first page of the pages in response to a read command, wherein the first page is controlled by a first word line of the word lines, and the controller further writes dummy data into the pages controlled by the first word line other than the first page when a predetermined condition is satisfied, wherein the predetermined condition includes that the first word line is not close. |
| US09786378B1 |
Equalizing erase depth in different blocks of memory cells
A memory device and associated techniques provide a uniform erase depth for different blocks of memory cells which are at different distances from pass gates of a voltage source. In one approach, a voltage of a source side select gate transistor of a memory string is a decreasing function of the distance. In another approach, a magnitude or duration of an erase voltage at a source end of a memory string is an increasing function of the distance. Adjacent blocks can be arranged in subsets and treated as being at a common distance. In another approach, an additional erase pulse can be applied when the distance of the block exceeds a threshold. Other variables such as initial erase voltage and step size can also be adjusted as a function of distance. |
| US09786375B2 |
Multiple blocks per string in 3D NAND memory
Embodiments describe techniques and configurations for an apparatus including a three-dimensional (3D) memory array having a plurality of strings of memory cells, where individual strings may have memory cells that correspond to different memory blocks (e.g., multiple memory blocks per string). For example, a first set of memory cells of a string may be included in a first memory block, and a second set of memory cells of the string may be included in a second memory block. The memory device may include separator wordlines disposed between wordlines associated with the first memory block and wordlines associated with the second memory block. The separator wordlines may receive different bias voltages during various operations of the memory device. Additionally, a wordline biasing scheme may be selected to program the first memory block based on whether the second memory block is programmed. Other embodiments may be described and/or claimed. |
| US09786374B2 |
Nonvolatile memory device, operating method thereof, and test system for optimizing erase loop operations
A nonvolatile memory device includes a plurality of memory blocks. The nonvolatile memory device includes a controller configured to perform an erase operation by repeating an erase loop, and generates and stores a test result based on a pass erase loop count of the erase operation in response to a result processing command. The erase loop includes applying an erase voltage to a target memory block among the memory blocks in response to an erase command. |
| US09786371B1 |
Power-on reset circuit with variable detection reference and semiconductor memory device including the same
Provided herein are a power-on reset circuit and a semiconductor memory device including the same. The power-on reset circuit may include: a voltage dividing circuit suitable for dividing an external power supply voltage to output a reference voltage, an output node control circuit suitable for controlling a potential level of an output node to an external power supply voltage level or a ground power supply voltage level in response to the reference voltage, and a buffer circuit suitable for buffering the potential level of the output node to output a power-on reset signal. In the voltage dividing circuit, a potential level of the reference voltage in a power up period is different from a potential level of the reference voltage in a power down period. |
| US09786368B2 |
Two stage forming of resistive random access memory cells
Provided are memory cells, such as resistive random access memory (ReRAM) cells, each cell having multiple metal oxide layers formed from different oxides, and methods of manipulating and fabricating these cells. Two metal oxides used in the same cell have different dielectric constants, such as silicon oxide and hafnium oxide. The memory cell may include electrodes having different metals. Diffusivity of these metals into interfacing metal oxide layers may be different. Specifically, the lower-k oxide may be less prone to diffusion of the metal from the interfacing electrode than the higher-k oxide. The memory cell may be formed to different stable resistive levels and then resistively switched at these levels. Each level may use a different switching power. The switching level may be selected a user after fabrication of the cell and in, some embodiments, may be changed, for example, after switching the cell at a particular level. |
| US09786361B1 |
Programmable decoupling capacitance of configurable logic circuitry and method of operating same
An integrated circuit comprising at least one logic tile including a plurality of multiplexers interconnected into a network configuration, wherein each multiplexer includes a plurality of inputs, an output and a plurality of selection inputs to receive selection signals to determine whether an input of the plurality of inputs is connected to the output. The logic tile further includes (i) at least one inactive multiplexer having an output that is inactive in the network configuration and/or (ii) at least one static multiplexer receiving static selection signals, wherein during operation of the integrated circuit, the selection inputs of the inactive and/or the static multiplexer receive selection signals responsively connect (whether directly or indirectly) two or more inputs of the inactive and/or the static multiplexer to the output of the inactive multiplexer. |
| US09786360B2 |
Static semiconductor memory device using a single global data line
A memory bank of a semiconductor memory device includes: a plurality of memory cells; first and second local bit lines; a differential amplifier configured to amplify a potential difference between the first and second local bit lines; a connector to which a global data line is connected; a first output circuit configured to selectively output, according to a potential level of the first local bit line, a first potential to the connector; and a second output circuit configured to selectively prevent, according to a potential level of the second local bit line, a potential of the connector from being affected by an output of the first output circuit and being equal to the first potential. |
| US09786357B2 |
Bit-cell voltage distribution system
In some embodiments, a method includes receiving, at a voltage distribution circuit, a power enable signal. In response to the power enable signal, the voltage distribution circuit may connect a word line driver circuit to a bit-cell voltage circuit such that an operating voltage is received at a bit-cell circuit before a word line signal form the word line driver circuit is received at the bit-cell circuit, where the operating voltage is provided by the bit-cell voltage circuit. The method may further include the bit-cell circuit providing the operating voltage along a bit line based on a data stored at the bit-cell circuit and based on the word line signal. In some embodiments, a static noise margin of one or more portions of the bit-cell circuit may be improved. Additionally, in some cases, a wakeup time of the bit-cell circuit may be ignored, resulting in a faster read operation. |
| US09786349B1 |
Cell performance recovery using cycling techniques
Methods, systems, and devices for memory array operation are described. A series of pulses may be applied to a fatigued memory cell to improve performance of memory cell. For example, a ferroelectric memory cell may enter a fatigue state after a number of access operations are performed at an access rate. After the number of access operations have been performed at the access rate, a fatigue state of the ferroelectric memory cell may be identified and the series of pulses may be applied to the ferroelectric capacitor at a different (e.g., higher) rate. For instance, a delay between pulses of the series of pulses may be shorter than the delay between access operations of the ferroelectric memory cell. |
| US09786347B1 |
Cell-specific reference generation and sensing
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A portion of charge of a memory cell may be captured and, for example, stored using a capacitor or intrinsic capacitance of the memory array that includes the memory cell. The memory cell may be recharged (e.g., re-written). The memory cell may then be read, and a voltage of the memory cell may be compared to a voltage resulting from the captured charge. A logic state of the memory cell may be determined based at least in part on the voltage comparison. |
| US09786345B1 |
Compensation for threshold voltage variation of memory cell components
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Before reading a memory cell, the voltage on an access line of the memory cell may be initialized to a value associated with the threshold voltage of a switching component in electronic communication with the memory cell. The voltage may be initialized by reducing the existing voltage on the access line to the value. The switching component or an additional pull down device, or both, may be used to reduce the voltage of the access line. After the access line has been initialized to the value, the read operation may be triggered. |
| US09786332B2 |
Semiconductor device package with mirror mode
Semiconductor device assemblies with semiconductor device packages configured to operate in mirror mode are disclosed herein. In one embodiment a semiconductor device assembly includes a first semiconductor device package attached to a front side of a support substrate, and a second semiconductor device package attached to a back side of the support substrate. The first device package includes a plurality of first package contacts having a first arrangement of corresponding pin assignments, and the second device package includes a plurality of second package contacts and a switch circuit operably coupled to the second package contacts. The switch circuit is configured to receive a switch signal via the support substrate, and to assign the second package contacts to either the first arrangement of corresponding pin assignments or a second arrangement of corresponding pin assignments based on the switch signal. |
| US09786330B1 |
Shield for external welds of hermetically sealed electronics devices
Described herein is a system that includes a hard disk drive. The hard disk drive includes a base and a cover welded to the base by a weld bead. The base and the cover form a hermetically sealed housing. The system further includes a shield, coupled to an exterior of the hermetically sealed housing over the weld bead. The shield also is spaced-apart from the weld bead. |
| US09786327B2 |
Utilizing audio digital impact to create digital media presentations
Systems and methods disclosed create one or more digital media presentations based on impact values. In particular, in one or more embodiments, systems and methods generate impact values based on a change in a measure of energy associated with digital audio content over time. For instance, systems and methods generate impact values by calculating a difference in a measure of energy over time in relation to the amount of energy at a particular time period. Based on the generated impact values, systems and methods identify transition points in the digital audio content. Specifically, systems and methods utilize a decaying masking threshold to identify transition points from generated impact values. Moreover, systems and method utilize identified transition points to modify digital visual content displayed in conjunction with the digital audio content. |
| US09786324B2 |
Media clip creation and distribution systems, apparatus, and methods
Various embodiments for creating media clips are disclosed. In one example, a method is performed by a server for managing the creation and distribution of media clips, where the server associates a content capture device with an event, the content capture device for recording at least a portion of the event, receives a tag notification from a content tagging device via a network interface, generates a media clip creation command to the content capture device via the network interface, sends the media clip creation command to the content capture device, and receives a media clip created by the content capture device in response to receiving the media clip creation command. |
| US09786321B2 |
Electronic device and method for controlling navigation in a video
An electronic device comprises a display to output a video, a user interface for controlling a navigation in the video along a time axis, and a processing device. The processing device is configured, when operating in an operating mode in which an object shown in a plurality of frames of the video is selected by a user input, to determine a magnitude of a speed vector of the object, and to apply a time scaling factor which depends on the determined magnitude of the speed vector of the object to the navigation along the time axis. |
| US09786319B1 |
Codes and techniques for magnetic recording
This disclosure describes codes and techniques for magnetic recording. The coding schemes decrease bit error rates by decreasing total transitions in the encoded binary data compared to conventional codes. Additionally, instead of relying on a single coding scheme, an encoder and decoder are configured to switch between different coding schemes. By so doing, a variety of the coding schemes allows the encoded binary data to have a smaller bit error rate than a single coding scheme and have a maximum run-length less than or equal to a maximum run-length limitation of a magnetic disk. |
| US09786316B2 |
Multi-track data readers with iterative inter-track interference cancellation
An apparatus for two-dimensional magnetic recording includes an array reader comprising a number of read sensors configured to read data from at least one track on a storage medium, a number of two-dimensional equalizer circuits each comprising inputs for receiving signals derived from each of the read sensors, each comprising an equalized output, and a number of iterative inter-track interference cancellation circuits, each operable to cancel inter-track interference in a different one of the equalized outputs from the two-dimensional equalizer circuits. |
| US09786315B1 |
Disc device
A disc device includes a first traverse chassis holding a first optical pickup unit which performs recording/reproduction of information on a first surface of a disc, a second traverse chassis holding a second optical pickup unit which performs recording/reproduction of information on a second surface of the disc, and first and second biasing members which bias the first and second traverse chassis, respectively, in directions of coming closer to each other. The first and second traverse chassis are coupled to each other so as to turn around a turning axis at a rear side of a housing and extending in a width direction of the housing. At least one of the first and the second biasing members is attached while being inclined with respect to each of a conveying direction of the disc, and a thickness and the width directions of the housing. |
| US09786311B2 |
Near-field transducer with tapered peg
An apparatus includes a waveguide that delivers energy from an energy source, a write pole located proximate the waveguide at a media-facing surface, and a near-field transducer located proximate the write pole in a down track direction. The near-field transducer includes an enlarged portion and a peg extending from the enlarged portion towards the media-facing surface. The peg comprises a taper facing away from the write pole, and the taper causes a reduced down track dimension of the peg near the media-facing surface. |
| US09786309B1 |
Data storage device detecting minimum stable fly height of a head over a disk
A data storage device is disclosed comprising a head actuated over a disk, wherein the head comprises a fly height actuator (FHA). A FHA control signal is applied to the FHA, wherein the FHA control signal comprises a DC component and an AC component. A fly height metric is measured representing a fly height of the head over the disk for different levels of the DC component. A modulation amplitude of the fly height metric is detected, and a minimum in the modulation amplitude of the fly height metric is detected. |
| US09786306B2 |
Failure prognosis device, method, and storage system
According to one embodiment, a failure prognosis device includes circuitry configured to determine whether a sign of failure exists in a head, based on a signal quality value and a floating quantity of the head, the signal quality value being based on an error between a reproducing signal acquired from the head when reading data stored on a storage surface of a disk and a predetermined target signal, and output a determination result. |
| US09786305B1 |
Magnetic read apparatus having multiple read sensors with reduced sensor spacing usable in two-dimensional magnetic recording applications
A magnetic read apparatus includes a first sensor, a shield layer, an insulating layer, a shield structure and a second sensor. The shield layer is between the first sensor and the insulating layer. The shield structure is in the down track direction from the insulating layer. The shield structure includes a magnetic seed structure, a shield pinning structure and a shield reference structure. The magnetic seed structure adjoins the shield pinning structure. The shield pinning structure is between the shield reference structure and the magnetic seed structure. The second sensor includes a free layer and a nonmagnetic spacer layer between the shield reference structure and the free layer. The shield reference structure is between the shield pinning structure and the nonmagnetic spacer layer. The shield pinning structure includes a pinned magnetic moment. The shield reference structure includes another magnetic moment weakly coupled with the pinned magnetic moment. |
| US09786302B1 |
Flux-guided tunneling magnetoresistive (TMR) sensor for magnetic tape with reduced likelihood of electrical shorting
A tunneling magnetoresistive (TMR) read head for magnetic tape has a tape-bearing surface (TBS) and includes a first magnetic shield, a first gap layer on the first shield, a TMR sensor on the first gap layer and recessed from the TBS, a second gap layer on the TMR sensor, a second magnetic shield on the second gap layer, and a magnetic flux guide between the first and second gap layers between the TBS and the recessed TMR sensor. The first gap layer has an insulating portion with an edge at the TBS and a non-magnetic electrically-conducting portion recessed from the TBS, with the TMR sensor located on the conductive portion. The sense current is between the two shields. An insulating isolation layer may be located between the first gap layer and the first shield layer with the sense current being between the second shield and the first gap layer. |
| US09786295B2 |
Voice processing apparatus and voice processing method
A voice processing apparatus includes: a feature amount acquisition unit configured to acquire a spectrum of an audio signal for each frame; an utterance state determination unit configured to determine an utterance state for each frame on the basis of the audio signal; and a spectrum normalization unit configured to calculate a normalized spectrum in a current utterance by normalizing a spectrum for each frame in the current utterance using at least an average spectrum acquired until the present time. |
| US09786287B2 |
Low-frequency effects haptic conversion system
A system is provided that produces haptic effects. The system receives an audio signal that includes a low-frequency effects audio signal. The system further extracts the low-frequency effects audio signal from the audio signal. The system further converts the low-frequency effects audio signal into a haptic signal by shifting frequencies of the low-frequency effects audio signal to frequencies within a target frequency range of a haptic output device. The system further sends the haptic signal to the haptic output device, where the haptic signal causes the haptic output device to output one or more haptic effects. |
| US09786282B2 |
Mobile thought catcher system
A voice capture device helps users capture and act upon fleeting thoughts. In response to user activation a processor stores an audio file corresponding to a finite amount of audio captured by a microphone of the voice capture device. The processor automatically transfers the audio file to one or more servers either directly via the Internet or via an intermediate device at a later time when such transfer is possible. The one or more servers automatically convert the audio file to a corresponding text record, automatically add the text record to a history of text records for the user, and send a copy of the history of text records for the user to a computing device associated with the user. The user can thereby utilize the computing device to review the history of text records and be reminded of actions that need to be taken. |
| US09786280B2 |
Methods and apparatus for voice-controlled access and display of electronic charts onboard an aircraft
A method for accessing electronic charts stored on an aircraft is provided. The method receives, via an onboard avionics system, location data for the aircraft; receives a set of speech data via a user interface of the aircraft; identifies one or more applicable electronic charts, based on the received location data and the received set of speech data, wherein the electronic charts stored on the aircraft comprise at least the one or more applicable electronic charts; and presents, via an aircraft display, a first one of the one or more applicable electronic charts. |
| US09786279B2 |
Answering questions using environmental context
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for receiving audio data encoding an utterance and environmental data, obtaining a transcription of the utterance, identifying an entity using the environmental data, submitting a query to a natural language query processing engine, wherein the query includes at least a portion of the transcription and data that identifies the entity, and obtaining one or more results of the query. |
| US09786278B2 |
Image display apparatus and method of controlling the same
Provided are an image display apparatus and a method of controlling the same. The image display apparatus enabling voice recognition includes: a first voice inputter which receives a user-side audio signal; an audio outputter which outputs an audio signal processed by the image display apparatus; a first voice recognizer which recognizes the user-side audio signal received through the first voice inputter; and a controller which decreases a volume of the audio signal output through the audio outputter to a predetermined level if a voice recognition start command is received. |
| US09786274B2 |
Analysis of professional-client interactions
One or more processors receive recording data of a meeting between a first individual and a second individual. One or more processors analyze the recording data to identify one or more characteristics of the first individual. One or more processors match the one or more characteristics of the first individual to one or more preferences of a third individual. |
| US09786273B2 |
Multimodal disambiguation of speech recognition
The present invention provides a speech recognition system combined with one or more alternate input modalities to ensure efficient and accurate text input. The speech recognition system achieves less than perfect accuracy due to limited processing power, environmental noise, and/or natural variations in speaking style. The alternate input modalities use disambiguation or recognition engines to compensate for reduced keyboards, sloppy input, and/or natural variations in writing style. The ambiguity remaining in the speech recognition process is mostly orthogonal to the ambiguity inherent in the alternate input modality, such that the combination of the two modalities resolves the recognition errors efficiently and accurately. The invention is especially well suited for mobile devices with limited space for keyboards or touch-screen input. |
| US09786271B1 |
Voice pattern coding sequence and cataloging voice matching system
A method for voice pattern coding and catalog matching. The method includes identifying a set of vocal variables for a user, by a voice recognition system, based, at least in part, on a user interaction with the voice recognition system. The method further includes generating a voice model of speech patterns that represent the speaking of a particular language using the identified set of vocal variables, wherein the voice model is adapted to improve recognition of the user's voice by the voice recognition system. The method further includes matching the generated voice model to a catalog of speech patterns, and identifying a voice model code that represents speech patterns in the catalog that match the generated voice model. The method further includes providing the identified voice model code to the user. |
| US09786269B2 |
Language modeling of complete language sequences
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for language modeling of complete language sequences. Training data indicating language sequences is accessed, and counts for a number of times each language sequence occurs in the training data are determined. A proper subset of the language sequences is selected, and a first component of a language model is trained. The first component includes first probability data for assigning scores to the selected language sequences. A second component of the language model is trained based on the training data, where the second component includes second probability data for assigning scores to language sequences that are not included in the selected language sequences. Adjustment data that normalizes the second probability data with respect to the first probability data is generated, and the first component, the second component, and the adjustment data are stored. |
| US09786266B2 |
Method and system for acoustically treating material
Methods and systems for acoustically treating material are described. Acoustic energy is emitted into a waveguide having a wall with a shape that tapers away from the acoustic source. The wall may have a substantially conical or parabolic shape. When emitted therein, the waveguide causes convergence of the acoustic energy so as to form an acoustic focal zone at a vessel. In some embodiments, a substantial portion of the acoustic focal zone is located outside of the internal volume defined by the waveguide. |
| US09786261B2 |
Active noise reduction earcup with speaker array
Embodiments relate generally to devices and methods for improved active noise cancellation hearing protection. For example, multiple speakers might be used in each earcup, with each speaker providing active noise cancellation for a narrow frequency range which is a portion of the total frequency range of the entire array of speakers. By dividing the active noise cancellation up across an array of speakers, each speaker can better target its specific narrow frequency range, resulting in improved active noise cancellation. |
| US09786260B2 |
Method and device for rechargeable, retrofittable power source
A power system on an electric guitar may include a cover plate covering a standard cavity in the electric guitar. A rechargeable power source may be contained within the standard cavity and may not extend beyond an external surface of the cover plate. Other instruments or configurations may be used. |
| US09786257B2 |
Capo with attachment mechanism and fretting action in separate offset planes
Embodiments of a capo and fretting component are described. In certain embodiments, the fretting component is threaded onto a crossbar configured to overlie the instrument strings when in use and to pivot with respect to the crossbar so as to contact and press the strings against a fret on the instrument neck. The fretting component is offset with respect to the attachment mechanism of the capo, allowing the attachment mechanism to be offset on the neck of the instrument from where it would normally be positioned to achieve a comparable fretting effect. |
| US09786256B2 |
Method and device for generating graphical user interface (GUI) for displaying
Methods and devices for generating Graphical User Interface (GUI) for displaying are provided, wherein the GUI is generated based on a plurality of windows. The method for generating GUI includes the step of: separately drawing a plurality of pictures into the plurality of windows by a first graphical processing unit; and selecting the first graphical processing unit or a second graphical processing unit according to a predefined rule to compose the plurality of windows with pictures into a frame buffer, such that the GUI is obtained; wherein the first graphical processing unit and the second graphical processing unit are different. |
| US09786255B2 |
Dynamic frame repetition in a variable refresh rate system
A method, computer program product, and system for adjusting a dynamic refresh frequency of a display device are disclosed. The method includes the steps of obtaining a current frame duration associated with a first image, computing, based on the current frame duration, a repetition value for a second image, and repeating presentation of the second image on a display device based on the repetition value. The logic for implementing the method may be included in a graphics processing unit or within the display device itself. |
| US09786251B1 |
Apparatus, method, and system for visually indicating perceived glare thresholds
Discussed herein is the adequate lighting of a target area as viewed from one or more vantage points to one or more specifications for one or more situations, and in a manner that addresses glare; in particular, glare perception. Various apparatuses, methods, and systems are presented herein whereby glare thresholds are visually indicated. Said glare-indicating apparatus, methods, and/or systems are readily implemented using existing lighting design tools, adaptable in accordance with advances in glare science, and either avoid or overcome limitations of existing glare models. Said apparatuses, methods, and systems can be adapted for real-time evaluation of glare so to, for example, aid a lighting designer in vetting generated (i.e., virtual) lighting designs and identify retrofit options for existing lighting systems. |
| US09786250B2 |
Control apparatus, image processing apparatus, control method, and non-transitory computer-readable storage medium
A control apparatus causes, to execute image processing of single-color image data, a processing apparatus configured to accept an image processing command including a plurality of fields, each capable of storing a respective one of a plurality of color components in a dot sequential format, and execute image processing by using pixel values included in the command. The control apparatus extracts, from single-color image data, a plurality of partial images by a number corresponding to the number of color components. The control apparatus acquires single-color pixel values from the respective partial images, and stores the single-color pixel values in the respective fields of the image processing command. A generated image processing command is input to the processing apparatus, and the processing apparatus executes image processing using the pixel values included in the command. |
| US09786247B2 |
Wearable display device
A wearable display device of the present invention includes: a wearable part configured for placement on a portion of a human body; a flexible display unit connected to the wearable part through a coupling part; at least one curvature changer configured to alter a curvature of at least a portion of the flexible display unit; and a curvature holder configured to maintain the curvature of the at least a portion of the flexible display unit once the curvature is altered by the at least one curvature changer. |
| US09786243B2 |
Gate driving circuit and display apparatus including the same
A gate driving circuit includes a plurality of stages for providing gate signals, wherein a k-th stage (k is a natural number greater than 3) includes a first output transistor including a control electrode connected to a first node, an input electrode for receiving a clock signal, and an output electrode for outputting a k-th gate signal, a second output transistor including a control electrode connected to the first node, an input electrode for receiving the clock signal, and an output electrode for outputting a k-th carry signal, a pull-down unit connected to a discharge node to pull down the output electrode of the first output transistor in response to a signal of the discharge node, and a discharge unit configured to output a (k−1)-th carry signal output from a (k−1)-th stage to the discharge node in response to a (k+1)-th carry signal output from a (k+1)-th stage. |
| US09786242B2 |
Gate driver on array circuit and display using the same
A GOA circuit includes GOA circuit units. The GOA circuit units at every two stages share a pull-down circuit. The pull-down circuit includes a first transistor, a second transistor and a third transistor. The present invention uses fewer transistors for the GOA circuit and lower the frequency of the first and second clock signals. The decrease in the frequency of the first and second clock signals helps a decrease in the frequency of charge and discharge to the parasitic capacitance and further a reduction in overall power consumption of the GOA circuit. |
| US09786241B2 |
Liquid crystal display and gate driver on array circuit
A GOA circuit for an LCD includes GOA units connected in cascade and the plurality of GOA units at stages formed. The GOA unit at an nth stage corresponds to a scan line. The scan line includes a nth scan line, a (n+1)th scan line, and a (n+2)th scan line. The GOA unit at the an nth stage includes a first pull-down holding circuit, a pull-up circuit, a bootstrap capacitance circuit, a pull-down circuit, and a clock circuit. The improved GOA circuit at one stage corresponds to the output of three gate lines. So a number of the stages of the GOA circuit is reduced. Only ⅓ stage of the conventional GOA circuit is needed. Because of the decrease in the number of the stages, more flexibility of design is given to the GOA circuit at each stage. It is beneficiary for the design in narrow bezels. |
| US09786238B2 |
Array substrate, display device, and method for driving display device
According to the array substrate provided by this disclosure, in a row of sub-pixels, sub-pixels in the odd columns and even columns are separately coupled to different gate lines, i.e., making the sub-pixels coupled to the same gate line are not adjacent to each other. In this way, during row scanning drive, an up-down twist charging may be implemented, and the sub-pixels cause no interference to each other. |
| US09786234B2 |
Driving module having low charging/discharging power consumption and driving device thereof
A driving module for a driving device of a display system includes a control unit, for generating a control signal according to a polarity signal indicating whether the driving device performs a polarity inversion; a first driving unit, coupled to the control unit, a first voltage source and a second voltage source, for generating a positive output voltage at a first output end according to a first display voltage and charging the first output end via the second voltage source according to the control signal; and a second driving unit, coupled to the control unit, the second voltage source and a third voltage source, for generating a negative output voltage at a second output end according to a second display voltage and discharging the second output end via the second voltage source according to the control signal. |
| US09786233B2 |
Electronic label system
An electronic label system including a control unit and a plurality of electronic label units is provided. The control unit transmits wireless power. The electronic label units are coupled to the control unit. The electronic label units respectively output a plurality of state information to the control unit, so that the control unit monitors operation states of the electronic label units according to the state information. The state information is transmitted to the control unit when a state of the electronic label units is varied. The control unit transmits the wireless power to the electronic label units by using wireless communications, and the electronic label units are charged with the wireless power. Furthermore, a wired communication interface is used as the communication interface between the net unit and the electronic label units in the electronic label system, so that the cost of the electronic label system is reduced. |
| US09786220B2 |
Display device and method of driving display device
A display device and method of driving the display device are disclosed. In one aspect, the display device includes a display panel including a plurality of pixels and a scan driver configured to apply a scan signal having activation and deactivation levels to the pixels. Each of the pixels includes a storage capacitor, a switching transistor, a driving transistor and an emitting element configured to emit light based on an emission current received from the driving transistor. The scan driver is configured to selectively control the activation level of the scan signal so as to control the amount of charge stored in the storage capacitor. The driving transistor is configured to control the emission current based on the amount of charge stored in the storage capacitor. |
| US09786217B2 |
Organic light emitting display device and driving method thereof
An organic light emitting display device includes a scan driving unit that supplies scan signals to scan lines, a data conversion unit that receives a first data signal for displaying an image and converts the first data signal to create a second data signal; a data driving unit that supplies the first data signal and the second data signal to data lines; a pixel unit including pixels positioned at intersections of the scan lines with the data lines, the pixels emitting light having a luminance corresponding to the first data signal during an image display subperiod and having a luminance corresponding to the second data signal during a compensation subperiod; and an image selection unit that transmits an image corresponding to the first data signal and blocking an image corresponding to the second data signal. |
| US09786215B2 |
Display panel and driving method thereof
A display panel and a driving method thereof are provided. The display panel has a clock signal generating module, a scanning signal generating module, a data signal generating module, first and second data lines, and first and second pixel columns. The first data line connects to second and third sets of pixels in the first pixel columns, and the second data line connects to fourth set of pixels in the second pixel columns and the next first set of pixels adjacent thereto. The present invention can reduce the power consumption of the display panel. |
| US09786213B2 |
Display device with basic control mode and low frequency control mode
A display device including a display portion, a source driver, a gate driver and a controller, wherein the controller is configured to control the source driver and the gate driver based on a control mode for displaying the frame image on the display portion, in a basic control mode, the controller is configured to display a frame image on the display portion by causing the gate driver to progressively scan gate signal lines, in a low frequency control mode, the controller is configured to determine whether a regional signal is on in a specific region corresponding to specific gate signal lines, when it is determined that the regional signal is off, the controller is configured to display a sub-frame image on the display portion by causing the gate driver to perform interlaced scanning of the gate signal lines every K lines in the first frame frequency F1. |
| US09786211B2 |
Display panel, driving method and display apparatus
The present disclosure provides a display panel, a driving method and a display apparatus. The data signals are outputted by different operational amplifiers to the subpixels of different colors connected to the same data line, and the data signals are outputted by the same operational amplifier to the subpixels of the same color on the same data line. |
| US09786210B2 |
Pixel array composed of pixel units, display and method for rendering image on a display
A pixel array composes of a plurality of basic pixel units arranged in row and column directions. Each of the basic pixel units consists of a first sub-pixel group composed of two adjacent first sub-pixel having a first color, a second sub-pixel group composed of two adjacent second sub-pixels having a second color, and two third sub-pixel groups, each of which is composed of two adjacent third sub-pixels having a third color. The distance between the two adjacent first, second, third sub-pixels, in row or column direction is smaller than a first predetermined value. The two adjacent third sub-pixel groups are arranged at a first row, and located at a first, third columns respectively, and the first, second sub-pixel group are arranged at a second row, wherein, the first sub-pixel group is located at a second column, and the other is located at a fourth column. |
| US09786206B2 |
Water resistant and stretchable sticker
A water-resistant and stretchable sticker comprises a printable layer and a neoprene layer, the neoprene layer may be fused or melted to a printable layer. A water-resistant and stretchable sticker may also include a nylon fabric layer, the nylon fabric layer being attached to the neoprene-based layer. The printable layer comprises a nylon-based layer. The printable layer may comprise a polyester, double-knit jersey fabric layer. In embodiments, the water-resistant and stretchable layer further comprises an adhesive layer, the adhesive layer being adhered to the nylon fabric layer. In embodiments, the water-resistant and stretchable layer further comprises a peel-away layer being adhered to the adhesive layer. |
| US09786200B2 |
Acoustic representations of environments
Concepts and technologies are disclosed herein for acoustic representations of environments. A processor can execute an acoustic representation service. The processor can receive a request to provide acoustic representation data to a device. The processor can obtain input data from the device. The input data can include captured data. The processor can analyze the input data to recognize an object represented in or by the input data and a path associated with the object. The processor can generate acoustic representation data representing the object and the path, and provide the acoustic representation data to the device. |
| US09786195B2 |
System and method for evaluating reading fluency using underlining
A system of evaluating reading fluency by monitoring the underlining of text as it is being read on a tablet or other computing device. The text or passage is presented on the screen of the tablet computing device with a touchscreen, such as, but not limited to, an iPad. The reader uses a stylus, finger, or other device to underline each word as it is read, and may go back and re-underline any words to regress within the passage. Alternatively, a mouse can be used to indicate words as they are read. Computer software tracks the reader's underlining, providing detailed information about reading rate, pauses, regressions, and other word and word combination features. |
| US09786193B2 |
Adaptive training system, method and apparatus
A system and method for training a student employ a simulation station that displays output to the student and receives input. The computer system has a rules engine operating on it and computer accessible data storage storing (i) learning object data including learning objects configured to provide interaction with the student at the simulation system and (ii) rule data defining a plurality of rules accessed by the rules engine. The rules data includes, for each rule, respective (a) if-portion data defining a condition of data and (b) then-portion data defining an action to be performed at the simulation station. The rules engine causes the computer system to perform the action when the condition of data is present in the data storage. For at least some of the rules, the action comprises output of one of the learning objects so as to interact with the student. The system may be networked with middleware and adapters that map data received over the network to rules engine memory. |
| US09786186B2 |
System and method for confirming received taxi instructions
A method and system are described for enhancing ground situational awareness to an aircrew via an alphanumeric display of an air traffic control ground clearance, including displaying a symbol for each stage of the clearance. A crewmember may accept or change each stage via a graphical user interface within the alphanumeric display. |
| US09786185B2 |
Collaborative aviation information collection and distribution system
A collaborative aviation information collection and distribution system includes a plurality of aircraft data transmitters and an aircraft data processing system. Each aircraft data transmitter is configured to selectively transmit aircraft data associated with a subscribing aircraft. The aircraft data processing system is in operable communication with each of the aircraft data transmitters and includes a data receiver, a data transmitter, and a data processor. The data receiver receives aircraft data transmitted from each of the aircraft transmitters. The data transmitter selectively transmits actionable aircraft data to one or more of the subscribing aircraft or subscribing ground-based users. The data processor determines which of, and when, the one or more subscribing aircraft or subscribing ground-based users should receive actionable aircraft data, generates actionable aircraft data from at least a portion of the received aircraft data, and supplies the generated actionable aircraft data to the data transmitter for transmission. |
| US09786183B2 |
Systems and methods for vessel position reporting and monitoring
Systems and methods for vessel position reporting and monitoring. Methods and systems for augmenting e-Navigation messages to provide ancillary information, such as a history of previous vessel positions. A compact representation is provided, in which transmitters may select among a plurality of possible position layouts to provide a compact representation. Transmitted messages are received by a satellite or other surveillance platform employing a compatible radio frequency receiver to collect message signals over a large area or great distance. |
| US09786177B2 |
Pedestrian path predictions
Systems and techniques for pedestrian path predictions are disclosed herein. For example, an environment, features of the environment, and pedestrians within the environment may be identified. Models for the pedestrians may be generated based on features of the environment. A model may be indicative of goals of a corresponding pedestrian and predicted paths for the corresponding pedestrian. Pedestrian path predictions for the pedestrians may be determined based on corresponding predicted paths. A pedestrian path prediction may be indicative of a probability that the corresponding pedestrian will travel a corresponding predicted path. Pedestrian path predictions may be rendered for the predicted paths, such as using different colors or different display aspects, thereby enabling a driver of a vehicle to be presented with information indicative of where a pedestrian is likely to travel. |
| US09786175B1 |
Availability estimation method for parking lots based on incomplete data
Methods and systems for monitoring parking areas and/or recommending a parking spot or a parking area to a driver are provided. The methods and systems can operate using incomplete camera or sensor coverage and minimal additional overhead. A method for assigning parking locations can include providing a first parking area and a second parking area, providing a means for determining a first parking area density and a means for determining a second parking area density, calculating a first parking index for the first parking area and a second parking index for the second parking area, providing a user interface suitable for assigning parking areas to drivers, and providing an assigned parking area based on the means for determining the first parking area density, the means for determining the second parking area density, the first parking index, and the second parking index. |
| US09786172B2 |
Warning guidance system, method, and program that provide information to vehicle navigation systems
Warning guidance systems, methods, and programs communicate with a vehicle navigation system to provide guidance on a warning event that may occur on the vehicle. The systems, methods, and programs acquire warning event information indicating the warning event and an event vehicle on which the warning event has occurred. The systems methods and programs transmit the guidance to the vehicle traveling in a predetermined section in a case in which the warning event that has occurred a plurality of times in the predetermined section has occurred on a plurality of event vehicles, but do not transmit the guidance at another vehicle traveling in the predetermined section in a case in which the warning event that has occurred a plurality of times in the predetermined section has occurred on a single event vehicle for all of the plurality of times. |
| US09786167B2 |
Method and device for validating an information item regarding a wrong-way driver
A method for validating an information item regarding a wrong-way driver, which indicates an instance of detected wrong-way travel of a vehicle driving the wrong way. The method includes checking plausibility, in which the information item regarding a wrong-way driver is checked for plausibility, using an additional information item, before the information item regarding a wrong-way driver is made available as a warning message for affected road users. In this context, the warning message is suppressed, if the additional information item characterizes the information item regarding a wrong-way driver as irrelevant. |
| US09786166B2 |
Method and control and detection unit for checking the plausibility of a wrong-way driving incident of a motor vehicle
In a method for checking the plausibility of a wrong-way driving of a motor vehicle when entering a unidirectional roadway, a traversing of a stop line or a solid line of a junction of the unidirectional roadway is detected and/or at least one item of directional information of a roadway of the junction, which is located ahead of the motor vehicle, is collected, and a probability of a wrong-way driving is ascertained based on the detection. The method is performed by a control and detection unit for checking the plausibility of a wrong-way driving. |
| US09786154B1 |
Methods of facilitating emergency assistance
In system and methods for loss mitigation, accident data associated with a vehicle accident involving a driver may be collected. The accident data may be analyzed, and a likely severity of the vehicle accident may be determined based upon the analysis of the accident data. A communication related to emergency assistance or an emergency assistance recommendation may be generated based upon the determined likely severity of the vehicle accident, and transmitted, via wireless communication, from one or more remote servers to a mobile device associated with the driver. A wireless communication from the driver indicating approval or modification of the emergency assistance or emergency assistance recommendation may be received. A third party may be notified, via a communication sent from the remote server(s), of requested emergency assistance as approved or modified by the driver. An estimated insurance claim may also be generated based upon vehicle accident likely severity. |
| US09786152B1 |
Septic overflow warning system
The septic overflow warning system includes a sensor unit that is adapted to secure itself to a tank lip of a septic tank. The sensor unit includes a float that is adapted to be moved up or down depending upon the waste level inside of the septic tank. Moreover, the float is slideably positioned on a sensor rod that is in wired connection with an alarm module. The alarm module includes a plurality of lights thereon. The plurality of lights collectively indicates the status of the volume of the septic tank via the float. The alarm module is powered via at least one solar cell. |
| US09786145B2 |
System and method for item self-assessment as being extant or displaced
A portable item reporting device (200) is configured to be attached to and in substantial collocation with a portable item (100), or to be integrated into a portable item (100). The device (200) includes environmental sensors (210) to monitor item location, movement, ambient light, sounds, temperature, etc. The device (200) is configured to store usage expectation data (600) indicative of historical and/or expected item usage and environments when the item (100) is in normal use/storage associated with an authorized user (AU). The device (200) monitors current environmental conditions (104) surrounding and pertaining to the item. If the current environment (104) is inconsistent with expected conditions (600), the device (200) assesses that the item (100) is displaced (503.0), meaning either that the item (100) is in abnormal use or abnormal storage, or is under the control of an unauthorized user (UU) who is other than the authorized user (AU). Based on the assessment the device initiates a signal (372) or message (374) to an authorized user (AU) of the item (100), indicating that the item (100) usage/storage is displaced (503.0) or otherwise anomalous (503.2). |
| US09786135B1 |
Radio apparatus
A radio apparatus includes a control unit, a power unit, a distress key and a transmission unit. When the distress key is manipulated, a distress key manipulation signal is output to the control unit and the power unit. When the power unit receives the distress key manipulation signal during a power supply is stopped, the power unit supplies power to the control unit and the transmission unit. When the control unit receives power from the power unit, the control unit starts setting up the radio apparatus and counts a time that the control unit continuously receives the distress key manipulation signal. When the control unit continuously receives the distress key manipulation signal for a preset time or longer, the control unit outputs a power supply maintenance signal to the power unit, generates the distress signal, and causes the transmission unit to send the distress signal. |
| US09786125B2 |
Determining appearances of objects in a virtual world based on sponsorship of object appearances
An online system provides objects for presentation to a user via a virtual world, each object having an organic appearance for display. The online system receives sponsorship requests for sponsoring appearances of one or more objects in the virtual world. A sponsorship request includes information describing a sponsored appearance of an object and a bid amount identifying compensation to the online system for using the sponsored appearance. When presenting an object to a user via the virtual world, the online system selects an appearance for the object from the object's organic appearance and one or more sponsored appearances based on characteristics of the user and bid amounts in the sponsorship requests including the sponsored appearances. The online system then presents the object to a user via the virtual world using the selected appearance. |
| US09786124B2 |
Gaming device and method for providing player selection of modifiers to game components
In one embodiment, the gaming device and method disclosed herein provides a player one or more modifiers to apply to different components or characteristics of a game. In one such embodiment, the gaming device enables a player to selectively apply or associate a plurality of modifiers to a single game component or apply the plurality of modifiers across the plurality of game components. For each game component with at least one applied modifier, the gaming device disclosed herein modifies said game component based on each applied modifier. The gaming device generates any awards based on any modified game components and any unmodified game components and provides any generated awards to the player. |
| US09786122B2 |
Method and apparatus for electronic gaming
A system and method for controlling a player's rate of play is provided. In an embodiment, a rate of play is defined that influences when a player is transferred to a new hand, such as upon folding or when play in a current hand is completed. Rate of play may be expressed, for example, as a percentage of hands to transfer upon which the player is to be moved upon folding. In another embodiment, a player may select, for example, a “Fold and Transfer” option or a “Fold and Observe” option, thereby allowing the player to better control the rate of play. In yet another embodiment, a player may designate a rate of play and be presented with a “Fold and Transfer” option and/or a “Fold and Observe” option, wherein the “Fold and Transfer” option and/or the “Fold and Observe” option may override the designated rate of play. |
| US09786116B2 |
Gaming system and method for providing a symbol game
In various embodiments, the gaming system disclosed herein includes a cascading symbol or tumbling reel game which retains, saves or stores zero, one or more of any symbols removed during the play of a primary cascading symbols game. In various embodiments, the gaming system disclosed herein includes a cascading symbol or tumbling reel game which sequentially layers a plurality of adjacent symbol display position grids at different depths. |
| US09786112B2 |
Paper sheet handling machine
A paper sheet handling machine 100 comprises an upper unit 10 having a paper sheet take-in apparatus 120 adapted for taking therein paper sheets, one by one, from the exterior, an upper transport mechanism 201a adapted for transporting the paper sheets taken in by the paper sheet take-in apparatus 120, one by one, and a recognition unit 220 adapted for recognizing each paper sheet transported by the upper transport mechanism 201a; a lower unit 20 located below the upper unit 10 and having a lower transport mechanism 201b provided to receive the paper sheets transferred from the upper transport mechanism 201a, one by one, and then further transport the transferred paper sheets, and a plurality of stacking units 106, each adapted for stacking therein the paper sheets transported by the lower transport mechanism 201b and sorted based on results obtained by the recognition unit 220. In this case, at least a part of a bottom portion of the upper unit 10 is opened. Additionally, a partition member 30 is provided between the upper unit 10 and the lower unit 20. |
| US09786110B2 |
On-vehicle apparatus control system and on-vehicle control device
An on-vehicle control device mounted on a vehicle includes: an on-vehicle transmission unit that transmits a response request signal to a portable machine carried by a user; and an on-vehicle reception unit that receives a response signal transmitted from the portable machine in response to reception of the response request signal, and a remote control signal transmitted from the portable machine in response to an operation on an operation switch disposed in the portable machine. The on-vehicle reception unit performs: reception processing on the remote control signal on a basis of a first reception sensitivity when receiving the remote control signal transmitted from the portable machine; and reception processing on the response signal on a basis of a second reception sensitivity lower than the first reception sensitivity when receiving the response signal transmitted from the portable machine. |
| US09786108B2 |
NFC based secure car key
A device is disclosed. The device includes a processor and a memory. The memory is coupled to the processor and having programming instructions to operate a vehicle via Near Field Communication (NFC). The device also includes a NFC controller coupled to a short range antenna, a passive NFC tag and a secure memory coupled to the NFC controller for storing a security code. |
| US09786106B2 |
Security control system for granting access and security control method thereof
The present invention provides a method for granting a visitor access into a premise. The security control method includes determining an identification tag, transmitting the identification tag to the visitor, scanning the identification tag of the visitor, authenticating the identification tag, generating an approving signal upon positive authentication of the identification tag, dispensing an identification token to the visitor upon receiving the approving signal, scanning the identification token of the visitor, and authenticating the identification token to grant the visitor access into the premise. The present invention further provides a security control system for the security control method. |
| US09786105B2 |
Gathering data from machine operating at worksite
A data gathering system associated with a machine operating at a worksite is provided. The data gathering system includes a base station located at the worksite and an unmanned aerial device (UAD) in communication with the base station and the machine. The UAD includes an image capturing unit for capturing images of an area around the machine and a controller in communication with the image capturing unit. The controller receives a first input from the machine indicative of one or more machine parameters, and receives a second input from the image capturing unit indicative of the images of the area around the machine. The controller further determines multiple operational parameters associated with an operation of the machine based on the first input and the second input, and transmits the determined multiple operational parameters to at least one of the machine and the base station. |
| US09786102B2 |
System and method for wireless vehicle content determination
A fleet management system providing a manager with a tailored user interface based on the enabled features recognized in a vehicle. The fleet management system may monitor two or more vehicles, wherein each vehicle may have one or more processors. The one or more processors may receive an initialization signal from the fleet management system. The one or more processors may perform a query of one or more vehicle modules for enabled features in response to the initialization signal received from the fleet management system. The query of enabled vehicle features may be based on one or more criteria. The system may transmit to a server a signal indicating the enabled vehicle features installed in the vehicle. The system may output the enabled vehicle features to a user while tailoring the user screen data based on the enabled features. |
| US09786101B2 |
Evaluating image values
Images of items are evaluated. A first image of the item, having a view of two or more of its surfaces, is captured at a first time. A measurement of at least one dimension of one or more of the surfaces is computed and stored. A second image of the item, having a view of at least one of the two or more surfaces, is captured at a second time, subsequent to the first time. A measurement of the dimension is then computed and compared to the stored first measurement. The computed measurement is evaluated based on the comparison. |
| US09786099B2 |
Coinage identification device
Provided is a coinage identification device (6), comprising: a coinage sorting device (6A), which is configured to further comprise a first coinage guidance unit (9), and a second coinage guidance unit (10) which moves between a narrowing location which is close to the first coinage guidance unit (9) and a widening location which is separated from the first coinage guidance unit (9), and to cause a plurality of coins to fall in batches of a defined number from between the first coinage guidance unit (9) and the second coinage guidance unit (10); and a coinage intake (28a) which is disposed below the first coinage guidance unit (9) and the second coinage guidance unit (10), and which accepts the coins which fall from between the first coinage guidance unit (9) and the second coinage guidance unit (10). When a coin is jammed between the first coinage guidance unit (9) and the second coinage guidance unit (10), the coinage sorting device (6A) moves the second coinage guidance unit (10) from the narrowing location to the widening location, thereby widening the space between the first coinage guidance unit (9) and the second coinage guidance unit (10) and causing the jammed coin to fall. The coinage identification device further comprises a shutter unit (31) which covers the coinage intake (28a) when the second coinage guidance unit (10) is positioned in the widening location. |
| US09786098B2 |
Apparatus for performing tessellation operation and methods utilizing the same
A rendering method executed by a graphics processing unit includes: loading a vertex shading command from a first command queue to a shader module; executing the vertex shading command for computing the varying of the vertices to perform a vertex shading operation by taking the vertices as first input data; storing first tessellation stage commands into a second command queue; loading the first tessellation stage commands to the shader module; and executing the first tessellation commands for computing first tessellation stage outputs to perform a first tessellation stage of the one or more tessellation stages by taking the varying of the vertices as second input data. The vertex shading command is stored into the first command queue by a first processing unit. The varying of the vertices and the first tessellation stage outputs are stored in a cache of the graphics processing unit. |
| US09786097B2 |
Multi-modal method for interacting with 3D models
The present disclosure concerns a methodology that allows a user to “orbit” around a model on a specific axis of rotation and view an orthographic floor plan of the model. A user may view and “walk through” the model while staying at a specific height above the ground with smooth transitions between orbiting, floor plan, and walking modes. |
| US09786096B2 |
Systems for parametric modeling of three dimensional objects
A system for parametric modeling of a three-dimensional object has a processor running a software program operable to configure the object by defining a zone comprising a root of a tree hierarchy, the zone having a three-dimensional region defining an outer dimension of the object to be modeled; a part comprising a child of the zone, the part also having a component object to be modeled, wherein the component object is an element of the object; and a variable comprising a child of the part, wherein variable has data defining characteristics of the zone or part. A user interface can display a representation of the three-dimensional object. |
| US09786095B2 |
Shadow rendering apparatus and control method thereof
A shadow rendering method is provided. The shadow rendering method includes emitting radial light to an object so that a shadow area for the object generated by a three-dimensional modeling is projected; determining a portion of the shadow area as a penumbra area for the object; and rendering a penumbra for the object to the penumbra area. |
| US09786093B2 |
Radiotherapy method, computer program and computer system
A method of obtaining a 3D image of a part of a patient's body is disclosed, based on a fraction image having a limited field-of-view and complementing this with information from a planning image having a greater field-of-view. In the area outside of the fraction image field-of-view, contour and anatomical data from the planning image are used to complement the fraction image, by means of a contour-guided deformable registration between the planning image and the fraction image. |