| Document | Document Title |
|---|---|
| US09628624B2 |
System and method for a work distribution service
Systems and methods for a work distribution service. At a multi-tenant platform that provides a work distribution service for a plurality of external systems, a priority is assigned to a first work item of a first external system. The work item is received via a RESTful work item API call request. The priority is assigned based on work item attributes of the work item and a workflow instruction corresponding to workflow information specified by the work item. The workflow instruction is provided by the external system via a RESTful Workflow API. A worker is assigned to the work item based on: the priority of the work item, the workflow information, and worker state managed by the first external system via a RESTful Worker API. The worker state includes worker attributes. The work item is generated by the external system, and the workflow instruction is managed by the external system. |
| US09628618B1 |
System, method and computer readable medium for call center management
A call center system is configured to record call data into call records. A transfer center within the call center transfers the call records to a database. A query engine, controlled from an interactive user interface, executes queries on the call data records in the database, allowing real-time analysis of the call data. |
| US09628617B2 |
Method and apparatus for controlling outgoing call in vehicle equipped with voice recognition function
An outgoing call control method for an in-vehicle head unit equipped with a voice recognition function includes connecting Bluetooth communication with a user device when a vehicle is powered on. Whether or not an existing voice recognition database is present is checked. Phone book information is downloaded from the user device through the connected Bluetooth communication. Voice recognition for an outgoing call is performed using the existing voice recognition database during download of the phone book information if the existing voice recognition database is present. |
| US09628616B2 |
Systems and methods for transmitting subject line messages
A method includes receiving a call setup signaling message at a subject line messaging application server. The call setup signaling message includes a subject header. The subject header includes a message identifier that corresponds to a subject line message selected by a caller device. The method includes replacing the message identifier with the subject line message to form a modified call setup signaling message when a removal determination indicates that the subject header should remain. The method also includes sending the modified call setup signaling message to a called party device via a server. |
| US09628615B2 |
System and method of presenting caller identification information at a voice over internet protocol communication device
A method includes receiving a call from communication device associated with a caller. The call is directed to a second communication device associated with a callee. The method includes determining whether a caller profile associated with the caller is available. The method includes searching at least two networks in response to determining that the caller profile is not available. The method includes creating the caller profile based on the search of the at least two networks and populating a caller identification portal with at least one of a plurality identification characteristics included in the caller profile. |
| US09628604B2 |
Mobile terminal and controlling method thereof
A mobile terminal and controlling method thereof are disclosed, by which a prescribed function can be performed using a more intuitive gesture and voice input. The present invention includes a display unit, a microphone, a sensing unit configured to detect a gesture, and a controller configured to convert voice data, received based on the microphone, to a text in a first language, detect, using the sensing unit, a first gesture, and in response to detecting the first gesture, translate the text in the first language to text in a second language. |
| US09628599B2 |
Flexible telematics system and method for providing telematics to a vehicle
With a telematics system comprising a telematics unit, a mobile device of the user, and an integrated communication device of a vehicle, a method for providing information to a user of a telematics system includes receiving an event call at the telematics unit and, in response to the event call, sending a first message from the telematics unit to at least one of the mobile device of the user and the integrated communication device of the vehicle and sending a second message from the telematics unit to a telematics provider over a communications channel, the second message causing the telematics provider to communicate with at least one of the mobile device of the user and a mobile device of a third party. |
| US09628596B1 |
Electronic device including a directional microphone
An electronic device may include a housing and a directional microphone. The housing may include a front surface, a rear surface positioned opposite the front surface, and a hollow cavity positioned between the front surface and the rear surface. The hollow cavity may include a front opening defined in the front surface and a rear opening defined in the rear surface. The directional microphone may include a front port and a rear port. The directional microphone may be mounted in the hollow cavity of the housing with the front port oriented toward the front opening and with the rear port oriented toward the rear opening. |
| US09628593B2 |
Card tray for electronic device and tray carrier assembly using the same
A card tray for use in electronic devices is disclosed that can improve tray durability, eliminate the occurrence of resin flash during insert molding, and simplify the tray mold structure. The card tray for electronic devices according to a preferred embodiment may be a card tray for electronic device use for insertion into and withdrawal from a card socket of an electronic device with a card loaded thereon, comprising a tray body made of a nonmetallic material whereon is formed a card mounting hole or mounting recess for mounting the card, and a metal frame part that is coupled to the tray body so that the cross section protrudes from the front of the tray body. |
| US09628591B2 |
Packet transport protocol processing
A method of implementing a packet transport protocol between a source and a receiver may include receiving input from a source system including data fields indicating whether the source system will allow packet transport to be handled by the receiver. The method may also include receiving input indicating that a packet from the source is required by the receiver. The input can include a first timing requirement indicating at time when the packet is required at the receiver, and a selection between first and second protocols that mandate, respectively, that packet transport is handled by the receiver in the first protocol and by the source in the second protocol. The method may also include determining, based on the data fields, whether the source will allow use of the selected protocol. The method may also include transmitting a request for the packet, in which the request includes a second timing requirement. |
| US09628582B2 |
Social-driven precaching of accessible objects
A precaching system identifies an object, such as a media file, that a user accesses and then analyzes a social graph of the user to identify social graph contacts that may be interested in the object. Based on the content of the object—and the interests and connections of contacts in the social graph—the precaching system determines whether a particular contact in the user's social graph is likely also to access the object. For example, the precaching system may determine a hit score corresponding to the object and a likelihood that the particular contact in the social graph will access the object. If the precaching system determines that the likelihood that the particular contact will access the object meets or exceeds a threshold probability level for precaching the object, the precaching system precaches the object near the contact in anticipation that the contact will access the object. |
| US09628576B1 |
Application and sharer specific recipient suggestions
A system and method for suggesting to a first user about a second user who is available to have social interactions with the first user at a specific time based at least in part on user context for activities associated with habits of users. A habit engine determines habits of the first user and the second user to identify when each user is available for the social interactions. A context engine determines user context for a group of activities performed by the first user and the second user. A suggestion module identifies a time when the first user and the second user are available for the social interactions associated with a first activity having a matching context. The suggestion module provides a first suggestion that the first user join the second user in the first activity in a social network. |
| US09628575B1 |
Promoting social network sharing of a content item on a content sharing platform
A method for promoting social network sharing of a content item on a content sharing platform is disclosed. The method includes determining whether actions of a user and statistics associated with a content item of a content sharing platform satisfy criteria to present a promotion to the user to share the content item on one or more social networks. The method further includes identifying, based on the actions and the statistics, presentation characteristics to display the promotion to the user to share the content item. The method also includes selecting, based on a history of the user with each of the one or more social networks, at least one of the one or more social networks to include in the promotion for the user to select from for sharing the content item. |
| US09628574B2 |
Systems and methods for streamlined content download
Systems and methods in accordance with embodiments of the invention enable streamlined content download that minimizes user input during the download process. One embodiment includes a system for streamlined downloading of content to a user computing device, including: an application server system configured to locate an intermediary application in response to a request received from a user computing device; where the intermediary application includes a content ID and configures a user computing device to initialize a download manager on a user computing device, and to pass the content ID to the download manager; and where the download manager configures the user computing device to utilize the content ID to retrieve content access information, and download content from a content server system utilizing the content access information. |
| US09628573B1 |
Location-based interaction with digital works
In some implementations, a service provider may enable location-based interaction of a user of a device with at least one of a digital work or another user. For instance, when the service provider determines that the device of the user is at a particular physical location, the service provider may send a communication to notify the user that one or more digital works are available to be accessed at the current physical location of the device. As one example, a digital work may have been virtually left at the location by another user, and the digital work may be available to be accessed by the user currently at the location. As another example, the user may be attending an event and the service provider may offer a digital work related to the event when the user is determined to be at the location of the event. |
| US09628567B2 |
Methods and systems for efficient discovery of devices in a peer-to-peer network
When attempting to establish a peer-to-peer connection, a computing device can quickly discover compatible devices, which are capable of exchanging content, and remember them. When a neighboring device is discovered during a scan, the computing device can determine whether the neighboring device is capable of sharing content. Once it is determine that the neighboring device can share content, the computing device can determine a history of previous connections with the neighboring device. The computing device can determine a priority for sharing content with neighboring device relative to other devices. The computing device can determine the priority based on the history of the neighboring device and the history of other devices so that the devices with a likelihood of new content receive a higher priority. |
| US09628565B2 |
Highly assisted driving platform
Methods for providing a highly assisted driving (HAD) service include: (a) transmitting telematics sensor data from a vehicle to a remote first server; (b) transmitting at least a portion of the telematics sensor data from the remote first server to a remote second server, wherein the remote second server is configured to execute a HAD application using received telematics sensor data, and wherein the HAD application is configured to output a HAD service result; and (c) transmitting the HAD service result from the remote second server to a client. Apparatuses for providing a HAD service are described. |
| US09628563B2 |
Sharing and synchronizing data across users of cloud computing systems
The disclosed embodiments provide a system that processes data from a user. During operation, the system obtains, at a cloud computing system, a set of data-sharing preferences for the user. Next, the system creates a set of virtual storage partitions for the user with the cloud computing system based on the data-sharing preferences. Upon receiving data from the user to the cloud computing system, the system associates the data with a virtual storage partition from the set of virtual storage partitions based on the data-sharing preferences and a set of data attributes for the data. Finally, the system manages access to the virtual storage partition by one or more other users based on the data-sharing preferences. |
| US09628562B2 |
Data and event gap reconciliation across networks using different communication technologies
Systems and methods automatically detect missing data and attempt to collect the missing data. The missing data may be related to a data reading or may be related to an event. The missing data is detected by comparing a communication received from an endpoint with previously received communications from the endpoint. The communication technology used by the endpoint may be considered in determining how to detect missing data and how to request the missing data from the endpoint. A single headend system may communicate with endpoints that use different communication technologies by adjusting the speed, batch size and the retry process used. |
| US09628561B1 |
System and method for smart throttling mechanisms for virtual backup appliances
A method for managing resources of virtual backup appliances is described. The method includes receiving, by a backup management server (BMS), a request to back up a plurality of virtual machines (VMs), determining, at the BMS, a set of VMs to be backed up from the plurality of VMs that yields a maximum performance for the backup request without causing the set of VM servers to become bottlenecked, wherein the determination is performed based on at least one of a concurrency limit of the virtual backup appliance (VBA) and any VBA proxies corresponding to the set of VMs, and a set of one or more data performance metrics of one or more storage devices in the set of VM storage arrays, and sending one or more backup jobs to the VBA to back up the determined set of VMs to be backed up to a backup storage system. |
| US09628557B2 |
Peer-to-peer exchange of data resources in a control system
System(s) and method(s) are provided for peer-to-peer exchange of data in a control system. Decentralized storage and multi-access paths provide complete sets of data without dependence on a specific or pre-defined data source or access paths. Data is characterized as data resources with disparate granularity. The control system includes a plurality of layers that act as logic units communicatively coupled through access network(s). Server(s) resides in a service layer, whereas client(s) associated with respective visualization terminal(s) are part of a visualization layer. Peer-to-peer distribution of data resource(s) can be based on available access network(s) resources and optimization of response time(s) in the control system. When client requests a data resource, all the locations of the data resource and the quickest source to retrieve it are automatically determined. The client stores copy of data resource. Peer-to-peer distribution of data resource(s) can be implemented within the service layer or the visualization layer. |
| US09628551B2 |
Enabling digital asset reuse through dynamically curated shared personal collections with eminence propagation
A method and associated systems for reusing digital assets and automatically updating user and asset eminence values associated with each asset reuse. Users each control a collection of digital assets and each user and each asset is assigned an eminence value that represents a relative importance of a user or asset. When a first user accesses an asset, that asset is copied to the first user's collection. When a second user accesses the first user's copy, the asset is copied to the second user's collection, and the eminence of the first user and of the asset are increased. When a third user accesses the second user's copy, the asset is copied to the third user's collection and first-user's, second-user's, and asset's eminence values increase. The second user may automatically locate an asset in the first user's collection by “following” the first user. |
| US09628547B2 |
Media file receiving and media file sending methods, apparatuses, and systems
Embodiments of the present invention provide media file receiving and media file sending methods, apparatuses, and systems. A media file receiving method includes: obtaining, by a client, an MPD fragment address of a first MPD fragment from a media presentation description MPD fragment index file according to a start-to-play time point requested by a user; sending, by the client, a first MPD fragment obtaining request including the MPD fragment address of the first MPD fragment to a server; receiving, by the client, the first MPD fragment fed back by the server, and sending a media segment obtaining request to the server according to media description information in the first MPD fragment; and receiving, by the client, a media segment fed back by the server. With the media receiving method according to the embodiments of the present invention, an objective of rapidly starting playing a media file can be achieved. |
| US09628544B2 |
Distributed build and compile statistics
The present technology adds code to a top level build configuration file of a configuration program that will gather metrics for each invocation of a build. These metrics are sent to a commonly accessible metric server for future analysis. The metrics are collected for a distributed engineering team over several machines. Compilation time metrics may then be collected for each compilation event and those metrics are analyzed by a common aggregator. |
| US09628543B2 |
Initially establishing and periodically prefetching digital content
Content playback that includes maintaining a connection between an electronic device and a content source. Content is prefetched prior to attempting to play one or more stations on the electronic device. Scanning a multiple stations and listening to a particular one station is distinguishable. |
| US09628542B2 |
Hybrid HTTP and UDP content delivery
A hybrid HTTP/UDP delivery protocol provides significant improvements for delivery of video and other content over a network, such as an overlay. The approach is especially useful to address problems (e.g., slow startup times, rebuffering, and low bitrates) for HTTP-based streaming. In general, the protocol has two phases: an HTTP phase, and a UDP phase. In the HTTP phase, the client sends an HTTP GET request to a server. The GET request contains a transport header informing the server that the client would like to use UDP-based transfer over the protocol. The server may refuse this mode and continue in ordinary HTTP mode, or the server may respond by sending an empty response with header information informing the client how to make the connection to enter the UDP phase. In the UDP phase, the client initiates a connection and receives the originally-requested content over UDP. |
| US09628540B2 |
Systems and methods for handling multiple concurrent session initiation protocol transactions
Systems and methods for handling the processing of multiple SIP transactions that have been requested at substantially the same time can involve establishing a priority order for processing the SIP transactions, and then individually processing the SIP transactions based on the established priority order. One or more SIP transactions having a lower priority can be held in a SIP processing queue of a software application until the processing of SIP transactions having a higher priority has been completed. Each time that the processing of a higher priority SIP transaction is completed, the next-highest priority SIP transaction in the queue is submitted for processing. Also, where possible, two or more SIP transactions in the queue may be consolidated into a single SIP transaction. |
| US09628533B2 |
Method and device for generating a description file, and corresponding streaming method
The present invention relates to a method and device for generating a description file about a video sequence at a server device for a client device, to retrieve a video segment and containing a region of interest. The method comprising for each video segment, determining a time interval during which the detected region of interest is spatially included in a same frame region in the video sequence; and generating a description file comprising spatial information describing the frame region and temporal information describing a duration at least equal to the determined time interval. |
| US09628529B2 |
Region on interest selection
In one implementation, a presentation includes multiple regions of interest or multiple views. The presentation is viewed by local users at the same location as the presentation and remote users at locations different from the presentation. A device receives orientation data from one or more local users that indicates the viewing angle of the one or more local users. The device selects a view including one of plurality of regions of interest based on the orientation data and sends a media stream including the view to the one or more remote users. |
| US09628527B2 |
System and method for delivering content in a unicast/multicast manner
The present invention is a system and method for enabling multicast synchronization of initially unicasted content. Multiple unicast streams are synchronized in order to convert the unicast streams into a multicast stream. Each unicast stream may be accelerated or slowed down in relation to a reference stream to a common point within each stream upon which the unicast streams are replaced by a multicast stream of the same content. |
| US09628525B2 |
Determining user perceived delays in voice conferencing systems and video conferencing systems
The determination of user perceived delay in audio and video conferencing systems/services is described. Example embodiments consistent with the present invention measure delays in audio and/or video conferencing systems and services, by treating such systems and services as black boxes, thereby providing end-to-end delays as they would be perceived by users. For example, the user perceived round-trip delay in a video conference system/service may include time delays from each of video capture, video encoding, video transmission, video decoding and video rendering. |
| US09628522B2 |
Enhanced content consumption
Enhanced content consumption is provided by establishing a pairing between two computing devices, wherein at least one of the two computing devices provides a primary consumption experience of a digital content item, so that a secondary consumption experience can be provided via operation of at least one of the two computing devices. The method further comprises presenting, using at least one of the two computing devices, the digital content item for consumption by a user. The method further comprises performing one or more supplemental consumption functions with the other of the two computing devices. |
| US09628521B2 |
Hybrid location
A location application can be configured to detect a call to a particular telephone number. The location application can also be configured to receive a plurality of radio frequency (RF) signals provided through a plurality of different RF interfaces. Each of the RF interfaces can be configured to receive RF signals of different protocols. The location application can also be configured to determine an identifier (ID) for a source of each of the RF signals. At least two of the RF signals can be of different protocols. The location application can also be configured to insert the ID for the sources of each of the RF signals into call signaling for the call. |
| US09628509B2 |
Identifying a denial-of-service attack in a cloud-based proxy service
A cloud-based proxy service identifies a denial-of-service (DoS) attack including determining that there is a potential DoS attack being directed to an IP address of the cloud-based proxy service; and responsive to determining that there are a plurality of domains that resolve to that IP address, identifying the one of the plurality of domains that is the target of the DoS attack. The domain that is under attack is identified by scattering the plurality of domains to resolve to different IP addresses, where a result of the scattering is that each of those domains resolves to a different IP address, and identifying one of those plurality of domains as the target of the DoS attack by determining that there is an abnormally high amount of traffic being directed to the IP address in which that domain resolves. |
| US09628508B2 |
Discovery of suspect IP addresses
A method of discovering suspect IP addresses, the method including, at a client computer: monitoring the computer for malware; on detection of malware, obtaining a list of IP addresses with which a connection has been made or attempted at the client computer within a preceding time frame; sending the list of IP addresses to a central server; and receiving from the central server a blacklist of suspect IP addresses to allow the client computer to block connections with IP addresses within said blacklist. |
| US09628505B2 |
Deploying a security appliance system in a high availability environment without extra network burden
A security appliance system routing strings of data packets in a high availability environment. The security appliance system contains a plurality of intrusion prevention systems connected to a load balancer and a computing device. Each intrusion prevention system contains stored session state information in a local session state data store, the load balancer contains a shared hash algorithm, and the computing device contains a connection state manager containing a network session state data store. The computing device includes a topology manager recording connectivity changes of the intrusion prevention systems and accordingly adjusting the shared hash algorithm for the recorded connectivity changes. Using the shared hash algorithm and routing information, a hash value is assigned to received strings. Strings are forwarded an intrusion prevention system based on assigned hash value and processed using stored session state information within the local session state data store and the network session state data store. |
| US09628500B1 |
Network anomaly detection
A security system detects anomalous activity in a network. The system logs user activity, which can include ports used, compares users to find similar users, sorts similar users into cohorts, and compares new user activity to logged behavior of the cohort. The comparison can include a divergence calculation. Origins of user activity can also be used to determine anomalous network activity. The hostname, username, IP address, and timestamp can be used to calculate aggregate scores and convoluted scores. |
| US09628499B1 |
Statistics-based anomaly detection
Systems and methods are described herein for detecting an anomaly in a discrete signal, where samples in the signal correspond to amounts of data flow in a network within a time interval. The discrete signal is received, and a sequence of likelihoods corresponding to the sample values in the signal is generated. The likelihoods are based at least in part on a historical probability distribution of previously received sample values, and a likelihood is a probability of occurrence of a corresponding sample value in the signal. Likelihood change points are identified in the likelihood sequence, and the discrete signal is segmented into a plurality of segments at samples corresponding to the identified change points. A segment is identified as an anomaly based on a comparison between a statistic of the segment and a statistic of the historical probability distribution. |
| US09628493B2 |
Computer implemented methods and apparatus for managing permission sets and validating user assignments
Disclosed are methods, apparatus, systems, and computer-readable storage media for modifying permission sets and validating permission set assignments to users. In some implementations, a computing device receives a request to create a permission set containing one or more permissions and assign the permission set to a first user. The first user is associated with a first user constraint that defines a first group of permissions available to the first user. The computing device may determine that the permission set to be assigned to the first user does not violate the first user constraint, and may assign the permission set to the first user. |
| US09628492B2 |
Method and system for restricting access rights on user profile information using a new notion of peer
The present invention relates to the field of Network portals and in particular to a method and system for restricting access rights on user profile information using a new notion of peer groups, wherein a given user's peer group is defined to be the set of users containing all the members of all the user's communities, wherein the individual communities are defined within the web portal wherein on said web portal a plurality of composite applications are implemented, wherein each composite application (19; 50) has a predetermined number of users working with said composite application building a community for that composite application,characterized by the steps of: a) building a filter based on the peer group of the requesting user by collecting the communities of all composite applications which said user is member of (650, 660, 670) b) using said filter as an additional constraint when selecting (680) user information from the user registry in order to limit all query results to user profile information associated to members of the given user's peer group and, c) displaying the result to the user (690). |
| US09628491B1 |
Secure assertion attribute for a federated log in
Embodiments of the present invention disclose a method, computer program product, and system for authenticating a user. The application server receives a user log in request and determines if a unique identification accompanies the received user log in request. The application server uses the unique identification to authenticate the identity of the user. The application server determines if the unique identification has been previously received by searching a first database to see if the unique identification was already stored in the first database. If the unique identification is not in the first database then the application server stores the unique identification and grants the user access to the one or more applications hosted on the application server. |
| US09628484B2 |
Leveraging online identities to grant access to private networks
An authentication service running on a processing device receives a request from a local area network (LAN) to authenticate a computing device (and/or a user of the computing device) that has attempted to access the LAN, the request comprising a first identifier (ID) that uniquely identifies the computing device. The authentication service determines whether to authenticate the computing device based on the first ID, information from a third party data set, and an authentication criterion of the LAN. Responsive to determining that the information from the third party data set satisfies the authentication criterion, the authentication service notifies the LAN that the computing device is authenticated. |
| US09628483B1 |
Auditable retrieval of privileged credentials
In an approach for providing auditable retrieval of privileged credentials in a privilege identity management (PIM) system, a processor invokes a checkout of a PIM credential, based on, at least, a determination that a PIM server cannot be accessed. A processor receives a request to access the PIM credential by a user. A processor receives validation of the request to access the PIM credential and an identity of the user. A processor retrieves the PIM credential from a database, wherein the database stores a plurality of PIM credentials owned by a system owner. |
| US09628482B2 |
Mobile based login via wireless credential transfer
Systems and methods for mobile-based login via wireless credential transfer are disclosed. In some implementations, a proxy server receives a registration request for a receiver device for accessing a secure resource. The proxy server registers the receiver device in response to the registration request. The proxy server receives, from a transmitter device, information identifying the transmitter device along with authentication credentials for authenticating the receiver device to access the secure resource. The proxy server identifies the receiver device based on the information identifying the transmitter device. The proxy server forwards, to the receiver device, the authentication credentials for authenticating access of the receiver device to the secure resource. |
| US09628477B2 |
User profile selection using contextual authentication
In embodiments, apparatuses, methods and storage media (transitory and non-transitory) are described that are associated with user profile selection using contextual authentication. In various embodiments, a first user of a computing device may be authenticated and have an access control state corresponding to a first user profile established, the computing device may select a second user profile based at least in part a changed user characteristic, and the computing device may present a resource based at least in part on the second user profile. In various embodiments, the computing device may include a sensor and a user profile may be selected based at least in part on an output of the sensor and a previously stored template generated by a machine learning classifier. |
| US09628475B2 |
User authentication of applications on third-party devices via user devices
In one embodiment, a first computing device receives an access token from a second computing device, the access token being generated by the second computing device for a specific software application executing on a specific computing device; stores the access token; receives a request for the access token from a software application executing on a third computing device; verifies whether the software application is the same as the specific software application and the third computing device is the same as the specific computing device for which the access token is generated; and sends the access token to the third computing device only when the software application is the same as the specific software application and the third computing device is the same as the specific computing device for which the access token is generated. |
| US09628473B1 |
System, method, and device for delivering communications and storing and delivering data
A system, method, and device includes a platform data storage that stores a wrap that secures an executable controller and executable sensors. The wrap is verified, optionally through a downloaded authentication driver. After verifying the wrap, the wrap is opened and a sister of the executable controller is installed into the platform memory to cooperate with the executable controller. Additionally or alternatively, the authentication driver may cooperate with the executable controller. The executable controller allows the platform processor to access data secured in a vault and/or verify the platform to create a connection to an application server. |
| US09628470B2 |
Client device, non-transitory storage medium storing instructions executable by the client device, and service performing system
A client device communicates with a server and a relay device and includes a controller and a storage. The controller is configured to: receive service use information from the relay device; use the received service use information to transmit connection request information to the server; receive the server certificate data which is transmitted from the server as a response to the connection request information; determine whether certificate-authority certificate data for verification of server certificate data is stored in the storage; when the certificate-authority certificate data is stored in the storage, verify the server certificate data using the certificate-authority certificate data; when the certificate-authority certificate data is not stored in the storage, receive the certificate-authority certificate data from the relay device; verify the server certificate data using the received certificate-authority certificate data; and store the received certificate-authority certificate data into the storage. |
| US09628469B2 |
Single sign on for a remote user session
A user accesses a remote session, the connection to which is managed by a connection broker, according to a single sign-on (SSO) process. The SSO process includes the user entering his or her credentials and being authenticated to the connection broker. In addition to user authentication, the SSO process includes connection broker authentication to confirm that the connection broker is trustworthy. When the connection broker is authenticated, the user credentials are transmitted to the connection broker in a secure manner and the connection broker forwards them onto a machine hosting the remote session so that the user can be logged into the remote session without entering his or her credentials again. |
| US09628468B2 |
Web-based single sign-on with form-fill proxy application
Web-based single sign-on can enable a user to log in to a single interface (such as through a web browser or thin client) and then provide SSO services to the user for one or more web applications. The web-based SSO system can be extended to support one or more different access control methods, such as form-fill, Federated (OIF), SSO Protected (OAM), and other policies. The web-based SSO system can include a user interface through which the user can access different web applications, systems, etc. and manage their credentials. Each SSO service can be associated with a web interface allowing the SSO services to be accessed over the web. The web interfaces can provide CRUD (create, read, update, delete) functionality for each SSO service. To support different access policy types, the web-based SSO system can include an extensible data manager that can manage data access to different types of repositories transparently. |
| US09628467B2 |
Wireless device authentication and service access
Authenticating a client device coupled to an authenticator network device for a network. A service request is received from the client device at the authenticator network device. User credentials, including a user ID, a user key, and a nonce for a user are received at the authenticator network device. A token is generated using the received user credentials. The service request is modified to include the token and a user ID parameter that is the user ID to generate a modified service request. The modified service request is used to provide single sign-on access to a service that is the subject of the service request. |
| US09628459B2 |
Secure data transmission using multi-channel communication
A method includes receiving a request to initiate secure communications from a first client and authenticating the first client. The authenticating includes communicating with a second client using a second communication channel, and receiving a response from the first client, the response being transmitted over a first communication channel. The method also includes receiving a first set of message data from the first client, the first set of message data being transmitted over the first communication channel, and receiving a second set of message data from the second client, the second set of message data being transmitted over the second communication channel. The method additionally includes constructing the message using the first set of message data and the second set of message data. |
| US09628458B2 |
Access management for controlling access to computer resources
A computer system to control access to computer resources of a computer data center. The computer system includes processors and program instructions stored on one or more computer-readable storage devices of the computer system. The stored program instructions include: (i) program instructions to determine that a request to access one of the computer resources is in response to a service request pertaining to the one computer resource targeted by the service request; and (ii) program instructions, responsive to the determination, to map the service request to one or more standard operating procedures to enable information embedded in the one or more standard operating procedures to be used to process the service request, assign a user to execute the service request, and grant the user the requested access of the one computer resource to enable the user to execute the service request. |
| US09628456B2 |
User authentication relying on recurring public events for shared secrets
An access manager manages access to a resource. At a first time, the access manager designates a variable attribute associated with a recurring public event as a shared secret between the access manager and a user. At a second time occurring after the first time, the access manager receives a shared key from the user. As received, the shared key is based on a value of the variable attribute associated with the recurring public event at a most recent recurrence of the recurring public event relative to the second time. The access manager evaluates the shared key. In response to the evaluation, the access manager grants or denies the user access to the resource. |
| US09628454B2 |
Signalling delegation in a moving network
In order to delegate location update signaling responsibility from a Mobile Node to a Mobile Router, the Mobile Router is provided with a second symmetric key generated by a Mobile Node using a first symmetric key shared between the Mobile Node and a Peer Node. The Mobile Router is additionally provided with a “certificate” authenticating the second symmetric key using the first symmetric key. In this way, the mobile router can sign location update related messages sent to the Peer Node with the second symmetric key, and can provide the Peer Node with the certificate in order to allow the Peer Node to authenticate the right of the Mobile Router to act on behalf of the Mobile Node. |
| US09628451B2 |
Power and cost efficient peripheral input
Systems and methods may provide for receiving, at a controller of a first device having a host processor, user input data and converting the user input data into one or more packets. Additionally, the one or more packets may be sent to a wireless communication component of the first device. In one example, the one or more packets are sent to the wireless communication component while the host processor is in one or more of a sleep state or a low power state. |
| US09628441B2 |
Attack defense method and device
An attack defense method and device, which relate to the communications field and effectively defend against a Secure Socket Layer (SSL) denial of service (DoS) attack behavior. The method includes after a Transmission Control Protocol (TCP) connection to a client is established, the attack defense device receives a key negotiation request message sent by the client; when a session monitoring table of the client exists, the attack defense device determines whether a session identity exists in the session monitoring table of the client; when the session identity does not exist, the attack defense device records the session identity into the session monitoring table, and determines whether a quantity of session identities of the client is greater than a first preset value; and when the quantity of session identities of the client is greater than the first preset value, disconnects the TCP connection. |
| US09628439B2 |
Systems and methods for managing network address information
Systems, methods and apparatus for managing network address information. In some embodiments, an appropriate address authority is queried to obtain information useful for address mapping. For example, the address authority may be selected by determining whether an address to be mapped is within one or more blocks of addresses for which the address authority is authoritative. In some further embodiments, address mapping information may be distributed from an address authority to a network device, so that the network device may perform address mapping using locally available information. |
| US09628436B1 |
User-configurable dynamic DNS mapping for virtual services
Various example implementations are directed to circuits, apparatuses, and methods for providing virtual computing services. According to an example embodiment, an apparatus includes a computing server configured to provide a respective group of virtual servers for each of a plurality of accounts. Each of the accounts has a respective set of domain names and a respective settings file. The apparatus also includes a domain name server (DNS). The DNS is configured and arranged to dynamically map a respective set of domain names for each account to network addresses of the respective group of virtual servers, provided for the account. The DNS performs the mapping according to a mapping function indicated in the respective settings file of the account. The respective settings file of a first account accounts includes a mapping function that is different from a mapping function included in the respective settings file of a second account. |
| US09628435B2 |
Duplicate address detection based on distributed bloom filter
In one embodiment, a method comprises: generating, by a first network device in a network, a Bloom filter bit vector representing device addresses of devices having attached to at least one of the first network device or a second network device in the network; and determining whether a new device address is not a duplicate of any of the device addresses in the network based on the Bloom filter bit vector. |
| US09628430B2 |
Notifications based on social network service activity and profile triggers
An embodiment searches a social network for at least one trigger event, detects one or more trigger events, and communicates the detected one or more trigger events as an alert. Searching the social network comprises searching member profiles and searching member activities. Detected one or more trigger events are centralized into a sortable list and prioritized based on business entities and the importance of the trigger events to persons related to the business entities. The centralized sortable list is fed into a customer relations management system which presents the alerts on a user interface. A plurality of types of triggers includes people updates, company updates, product purchases, and product usage. |
| US09628426B2 |
Instant messaging system
An instant messaging system is disclosed that provides a means for presenting information to a user about current conversants and for managing the handling of multiple messages from different parties. A priority hierarchy is established and set by a user with respect to each conversant. Messages from high priority conversants are delivered and displayed prior to messages from lower priority conversants. In a business setting, messages may be routed to particular individuals or with a particular priority based on characteristics or attributes of the message sender. |
| US09628422B2 |
Acknowledgement as a propagation of messages in a simulcast mesh network
The presently described apparatus and method extends the capabilities of an Insteon network of devices. The method includes transmitting a group command message from a first device to a selected group of devices having a common group number, and receiving the group command message by a second device of the group or receiving a clean-up message transmitted by the first device, and resetting the state of the second one of the devices, and transmitting an acknowledgement message to the first devices from the second device, and receiving the first acknowledgement message by a third one of the devices that had not received the group command message or a clean-up message previously, and restoring the state of the third one of the devices. |
| US09628421B2 |
System and method for breaking up a message thread when replying or forwarding a message
Disclosed is a method of communicating a message thread, comprising: receiving a message thread at a first device, the message thread comprising existing sub-messages; receiving input of a newly composed sub-message associated with the message thread; delineating each of the respective existing sub-messages from one another within the message thread; receiving selection of at least one delineated existing sub-message from the message thread through a selection interface for one of inclusion in and exclusion from a modified message thread; creating a modified message thread in accordance with the selection of at least one delineated existing sub-message, the modified message thread further comprising the new sub-message; and initiating communication of the modified message thread to a second device. |
| US09628417B2 |
Time conversion in an instant message
Embodiments of the present invention provide methods, program products and systems for displaying a corrected time included in the text of an instant message. One or more processors determine that an instant message sent from a first user to a second user includes a first time and a first time zone corresponding to the first time and determine that the first time zone corresponding to the first time does not match a second time zone. The one or more processors convert the first time to a second time, wherein the second time is determined based, at least in part, on the first time, the first time zone, and the second time zone. The one or more processors cause the second time to be displayed to the second user. |
| US09628415B2 |
Destination-configured topic information updates
A target travel destination is configured with a topic of conversation planned by a user to occur with at least one person at the target travel destination. A selection by the user of the target travel destination is detected within a user interface. Updated information about the topic of conversation configured with the target travel destination is obtained. The updated information about the topic of conversation configured with the target travel destination is provided to the user during the user's travel to the target travel destination. |
| US09628414B1 |
User state based engagement
The subject technology discloses configurations, for a set of unique users, processing application usage logs to determine a set of features of an application accessed by each user. A respective profile of each user is then updated based on the determined set of features accessed by the set of unique users. The subject technology determines a set of users that have lapsed in usage of an application based on a respective profile of each user. One or more previous engagement messages sent to the determined set of users are determined. The subject technology ranks a set of engagement types for each user of the determined set of users based on a set of criteria including the determined previous engagement messages. A new engagement message is generated based on a selected engagement type and then transmitted to each user of the determined set of users. |
| US09628410B2 |
Switch and switch system for enabling paths between domains
A disclosed switch includes: ports that include a first port to be connected to another switch included in a first domain that includes plural switches to be virtually integrated, and a second port that is other than the first port; a first processing unit configured to obtain data of a switch included in the first domain through the first port; and a second processing unit configured to obtain data of switches included in a second domain that is adjacent to the first domain through the second port and obtain data of switches included in the second domain from the another switch included in the first domain to identify, from among the ports, plural ports that are connected to the second domain, perform a setting for the identified plural ports, and perform a first processing to make plural domains that include the first and second domains a tree structure. |
| US09628408B2 |
Dissimilar switch stacking system
A switch IHS stacking system includes a plurality of switch IHSs. A least one first switch IHS includes a first processing system and at least one second switch IHS includes a second processing system that is different from the first processing system. A stacking engine is located on each of the plurality of switch IHSs. Following the coupling of the plurality of switch IHSs into a stack and in response to the startup of the plurality of switch IHSs, the each of the stacking engines may exchange capability information with each of the plurality of switch IHSs and determine a control plane processing system affinity and a data plane processing system affinity for each of the plurality of switch IHSs. The stacking engines may then determine a master switch IHS for the stack that has the highest control plane processing system affinity and data plane processing system affinity. |
| US09628403B2 |
Managing network data display
Systems and methods for monitoring performance associated with fulfilling resource requests and determining optimizations for improving such performance are provided. A processing device obtains and processes performance metric information associated with processing a request corresponding to a set of resources. The processing device uses the performance metric information to identify a subset of the resources corresponding to a display location associated with a visible portion of a display and to assess performance related to processing of the identified subset of the resources. In some embodiments, the processed performance data may be used to identify timing information associated with the subset of the embedded resources. Aspects of systems and methods for identifying and testing alternative resource configurations corresponding to the content associated with the original set of resources and for determining whether to recommend a resource configuration for improving performance of subsequent client requests for the content are also provided. |
| US09628402B2 |
Provisioning of resources
Reservation of resources for a service includes receiving a request for resources for a project duration with a start time and an end time; determining if the requested resources are available for the project duration; determining a utilization level of one or more resource provisioning components during a provisioning time prior to the start time of the project; and determining if the one or more resource provisioning components have capacity to handle the provisioning of resources for the request prior to the start time of the project. The one or more resource provisioning components can be reserved for a provisioning time prior to the start time of the project. |
| US09628399B2 |
Software product instance placement
A system, method and computer program product for detecting data omissions between intermittently-connected devices. An example system includes physical computing resources available for utilization. A placement server communicates with a client. The client seeks to use a portion of the computer resources to execute the software product instances. The placement server receives resource utilization parameters from the client and assigns the portion of the computer resources to the software product instances based on the resource utilization parameters and the physical computing resources available for utilization. The resource utilization parameters include specification of a hierarchal arrangement of the software product instances. |
| US09628398B1 |
Queuing methods and apparatus in a network device
In a method for queuing data units in a network device, a plurality of physical queues corresponding to a port of the network device are defined in a memory of the network device. Respective subsets of the plurality of physical queues are logically coupled to define a plurality of logical queues that are respectively formed of logically coupled physical queues. The logical queues correspond to respective data flows of the port. A data unit belonging to a data flow is received. A logical queue for storing the data unit is selected, based on the data flow of the data unit, from the plurality of logical queues The A physical queue for storing the data unit is then selected from the subset of physical queues that corresponds to the selected logical queue. The data unit is stored in the selected physical queue. |
| US09628390B2 |
Load balancing pseudowire encapsulated IPTV channels over aggregated links
A method for load balancing IPTV channels is described. In one embodiment of the invention, a first Provider Edge (PE) network element of a label switched network, coupled with a second PE network element over multiple member links of an aggregate link, receives IPTV packets. For each IPTV packet received, the first PE network determines layer 3 information of the IPTV packet, and generates one or more channel load balancing keys based on the layer 3 information. The PE network element generates a hash value from the channel load balancing keys and determines which one of multiple member links to transmit the IPTV packet on based on the hash value, and transmits the IPTV packet to the second PE network element on the determined member link. Other methods and apparatuses are also described. |
| US09628389B2 |
Dynamic, asymmetric rings
Dynamic, asymmetric rings and related communication equipment and methods are disclosed. Various features may be implemented to provide any or all of several degrees of freedom for managing resources in a communication network. Communication rates may be optimized on a node-to-node basis or overall on a network level. Different rates may be configured and possibly dynamically adjusted between different nodes, and/or for different directions of traffic transfer. Bandwidth can be dynamically allocated along a string of the communication nodes in a ring or linear topology in some embodiments. Direction of traffic transfer represents an additional possible degree of freedom in a ring topology, in that traffic can be transferred in either direction in a ring, such as the direction of least delay. |
| US09628386B2 |
Method of dispatching application messages
A method for dispatching a plurality of messages incoming into a dispatching server, each incoming message being issued by a source application and targeted to at least a destination application, the source application, the destination application and the dispatching server residing within a server-client network. The method includes the steps of defining a maximum rate of incoming messages per second, choosing an appropriate message rate reduction policy out of a first and of a second message rate reduction policy, starting a process which periodically determines a current rate of incoming messages per second, dispatching the message in case the current rate is smaller than the maximum rate, activating the appropriate message rate reduction policy in case the current rate of incoming messages is higher than the maximum rate, monitoring a result of the process and adapting a totality of parameters for the appropriate message rate reduction in case the current rate of incoming messages has dropped below the maximum rate. |
| US09628379B2 |
Large scale residential cloud based application centric infrastructures
A first customer edge network device receives an encapsulated packet that includes inner headers comprising source address information for a first service running on a first computing apparatus in a first home cloud and destination address information for a second service running on a second computing apparatus in a second home cloud. The customer edge network device inserts a predetermined portion of bits of a virtual domain identifier of the encapsulated packet into a label to form a virtual domain label for label-based routing. The virtual domain label is appended to the encapsulated packet. The encapsulated packet is sent to a first provider edge network device of a provider network. The first provider edge network device appends an virtual private network label to the encapsulated packet, and sends the encapsulated packet to a provider network device for label-based routing in the provider network. |
| US09628376B2 |
Communication system, switch, controller, method for constructing a control channel and program
The controller sets control information in a switch over a control channel to control the switch. The switch includes a packet processing unit that processes a packet received based on control information as set from the controller, and a Layer-2 forwarding unit that learns an input port of a control packet between the controller and a neighboring switch or switches and that forwards the control packet on the basis of learned results. The switch also includes an alternative control channel construction unit that, on detecting a disconnection of the control channel, sends a packet requesting a resolution of a Layer-2 address of the controller to the neighboring switch or switches. The alternative control channel construction unit acquires the Layer-2 address from the controller via the neighboring switch or switches and transmits the control packet to the controller using the Layer-2 address acquired to construct a second control channel between the switch and the controller. |
| US09628375B2 |
N-node link aggregation group (LAG) systems that can support various topologies
Aspects of the present invention include an arbitrary N-Node virtual link trunking (VLT) system comprising a set of N nodes collectively provide a logical fabric-level view that is consistent across the set of N nodes. Embodiments of the arbitrary N-Node VLT system comprise a control plane mechanism to provide Layer 2 multipathing between access network devices (switches or servers) and the core network. The N-Node VLT system provides a loop-free topology with active-active load-sharing of uplinks from access to the core. Accordingly, the N-Node VLT system eliminates the disadvantage of Spanning Tree Protocol (STP) (active-standby links) by allowing link aggregation group (LAG) terminations on multiple separate distribution or core switches and also supporting a loop-free topology. Additional benefits of an N-Node VLT system include, but are not limited to, higher resiliency, improved link utilization, and improved manageability of the network. |
| US09628369B2 |
Distributing non-unicast routes information in a trill network
The present invention discloses a method for processing non-unicast routes information in a TRILL network and a corresponding RBridge, wherein the RBridge has a neighbor relation with a plurality of other RBridges in the TRILL network, and the RBridge is the RBridge which computes non-unicast routes information in the neighbor relation, and in the method, the RBridge executes steps of: sending an acknowledgement message to the plurality of other RBridges, wherein the acknowledgement message acknowledges that the RBridge is the RBridge which computes the non-unicast routes information; obtaining a network topology related to the non-unicast routes information in the TRILL network; computing the non-unicast routes information based on the network topology; and distributing the computed non-unicast routes information to the plurality of other RBridges. The method and the corresponding RBridge are capable of reducing consumption of CPU resource of RBridges in the TRILL network. |
| US09628365B2 |
Apparatus for internetworked wireless integrated network sensors (WINS)
The Wireless Integrated Network Sensor Next Generation (WINS NG) nodes provide distributed network and Internet access to sensors, controls, and processors that are deeply embedded in equipment, facilities, and the environment. The WINS NG network is a new monitoring and control capability for applications in transportation, manufacturing, health care, environmental monitoring, and safety and security. The WINS NG nodes combine microsensor technology, low power distributed signal processing, low power computation, and low power, low cost wireless and/or wired networking capability in a compact system. The WINS NG networks provide sensing, local control, remote reconfigurability, and embedded intelligent systems in structures, materials, and environments. |
| US09628363B2 |
Network usage monitoring and analytics for differentiated data services
A system for discovery and analysis of network data usage of users of a communication network may collect information related to data usage over a network. The system may determine network data usage patterns for users from the data usage information. The network usage data, usage patterns and additional information may be analyzed to create user segments, and to analyze network data usage for the user segments. Differentiated data services may be created and implemented based on the network data usage for the user segments. |
| US09628360B2 |
Computer management system based on meta-rules
A computer management system that manages a plurality of types of managed objects according to one or more meta-rules. In the system, the one or more meta-rules are established by dividing a plurality of relationships among the managed objects into one or more groups based on a change frequency of the relations among the managed objects. |
| US09628356B2 |
Methods, systems, and computer readable media for providing user interfaces for specification of system under test (SUT) and network tap topology and for presenting topology specific test results
A network equipment test device provides a user interface for user specification of a test traffic source, a test traffic destination, SUT and waypoint topology and one or more test cases. In response to receiving the specified input from the user via the interface, the test traffic source is automatically configured to send the test traffic to the destination via the SUT. The waypoint is automatically configured to measure the test traffic. When the test is initiated, test traffic is sent from the test traffic source to the test traffic destination via the SUT and the at least one waypoint. Test traffic is measured at the waypoint, and traffic measurement results are displayed on a visual map of SUT topology. |
| US09628347B2 |
Layered request processing in a content delivery network (CDN)
In a content delivery network (CDN a method includes: receiving a request for a CDN service of a particular type, wherein a CDN service of said particular type defines a fixed number of configurable layers of request processing, sequentially from a first layer to a last layer; and processing said request, starting at said first layer, said processing being based on a modifiable runtime environment, said processing continuing conditionally through each of said layers in turn until either said request is terminated by one of said layers or said last layer processes said request. The CDN service may be selected from: delivery services, collector services, reducer services, rendezvous services, configuration services, and control services. |
| US09628344B2 |
Framework supporting content delivery with reducer services network
A framework includes a plurality of devices, each device configured to run at least one content delivery (CD) service of a plurality of CD services. The plurality of CD services include reducer services forming one or more reducer service networks. |
| US09628340B2 |
Proactive operations, administration, and maintenance systems and methods in networks using data analytics
A computer-implemented method, a system, and a network include receiving network data from a network and non-network sourced data from one or more external sources relative to the network; performing data mining on the network data and the non-network sourced data; developing a predictive analytics model based on the data mining; and performing predictive analytics on the network data and the non-network sourced data using the predictive analytics model to detect likely future failures in the network. The network can include a Software Defined Network (SDN) operating at any of Layers 0, 1, 2 and/or 3. |
| US09628338B2 |
Mesh network commissioning
In embodiments of mesh network commissioning, a node device in a mesh network receives a commissioning dataset, and compares a timestamp in the received commissioning dataset with a stored timestamp in a commissioning dataset that is stored in the node. The node device can determine from the comparison that the stored timestamp is more recent than the received timestamp, and in response, transmit a message to a leader device of the mesh network, where the message includes the stored commissioning dataset. The leader device accepts the stored commissioning dataset as the most recent commissioning dataset for the mesh network, and propagates the stored commissioning dataset to the mesh network. Alternatively, the node device can determine that the received timestamp is more recent than the stored timestamp, and in response to the determination, update the stored commissioning dataset to match the received commissioning dataset. |
| US09628330B2 |
Information providing device, information providing method, and information providing system
An information providing device which communicates with a communication terminal and an information processing device accepting a request of information processing from the communication terminal includes an obtaining unit obtaining positional information about the communication terminal; a determining unit determining that the information processing device is using the positional information; and a transmitting unit transmitting to the communication terminal configuration information required for the communication terminal to allow the information processing device to perform the information processing. |
| US09628329B2 |
Ubiquitous collaboration in managed applications
Methods and systems for an ubiquitous collaboration feature in a managed application environment are described herein. The collaboration service and/or server may store session information and one or more configuration files for use in rendering the collaboration features in combination with managed applications executing on a user's computing device. |
| US09628323B1 |
Selective routing of asynchronous event notifications
A processor enables simultaneous use of a single facility by an application, and privileged operators, such as an operating system or a hypervisor. The processor includes a routing register, which may be initialized by an operating system (or hypervisor), to indicate which subsets of a facility are used by which entity. The processor is configured to determine the entity assigned to a given subset of the facility in response to an event notification, and selectively route the event notification to the appropriate entity. |
| US09628319B2 |
Time-alignment of signals suffering from quadrature errors
Data is received characterizing a first signal and a second signal. The first signal and a function of the second signal is compared at a plurality of time-shifts to estimate a time-difference between the first signal and the second signal. The function of the second signal includes the second signal, a complex conjugate of the second signal, and a constant. The comparison is provided. At least one of receiving, comparing, and providing is performed by at least one processor of at least one computing system. |
| US09628318B1 |
Transpositional modulation communications
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium for receiving, by a first device, a first signal from a second device, the first signal including a carrier signal modulated with a first modulation signal. Detecting a frequency of the carrier signal by performing a carrier extraction (CAREX) process on the first signal. Adding a second modulation signal to the carrier signal of the first signal to produce a combined signal, wherein the second modulation signal is a transpositional modulation (TM) signal and the first modulation signal is a non-TM signal. Transmitting the combined signal. |
| US09628314B1 |
Digital I/Q reprocessing demodulator (DIRD)
A digital I/Q reprocessing demodulator and a process for significantly reducing arctangent computational loads. This is done by ensuring that all calculations are carried out in the linear part of the curve. The architecture of the demodulator is such that the demodulator 100 utilizes two I/Q stages. The first stage is utilized to determine a phase offset with regards to the free-running I/Q clocks. In the second processing stage, the phase of the I/Q reference signals are phase shifted based on the initial estimate such that the incoming carrier signal is nearly in-phase. |
| US09628310B2 |
Long training field sequence construction
In wireless communications, a first device may determine a channel bandwidth and a high efficiency long training field (HE-LTF) mode. The first device may generate an HE-LTF symbol by using an HE-LTF sequence corresponding to the determined channel bandwidth and HE-LTF mode. The first device may transmit, in the determined channel bandwidth, a high efficiency physical layer convergence procedure (PLCP) protocol data unit (HE PPDU) that includes the HE-LTF symbol. A second device may receive, in a channel bandwidth, a downlink HE PPDU that includes an HE-LTF symbol. The second device may obtain, from the HE-LTF symbol, an HE-LTF sequence corresponding to the channel bandwidth and an HE-LTF mode of the HE-LTF symbol. The downlink HE PPDU may be the HE PPDU from the first device. Other methods, apparatus, and computer-readable media are also disclosed. |
| US09628307B2 |
Method and system for optimizing asset allocation in a cognitive radio configuration
A method and system are provided for optimizing asset allocation in a cognitive radio configuration, the method comprising obtaining, in a digital computer, an indication of the cognitive radio configuration; converting the indication of the cognitive radio configuration into a degree 2 polynomial; providing the degree 2 polynomial to a quadratic programming machine; solving the degree 2 polynomial using the quadratic programming machine to generate binary solutions; the digital computer receiving the generated binary solutions and generating an asset allocation for the cognitive radio configuration and providing the generated asset allocation for the cognitive radio configuration. |
| US09628305B2 |
Systems and methods to compensate for memory effects using enhanced memory polynomials
A system for mitigating non-linearity distortions from a memory effect is disclosed. The system includes an enhanced predistortion component, a power amplifier, and a lookup table. The enhanced predistortion component is configured to receive an input signal, to obtain a plurality of enhanced memory polynomials based on a plurality of samples of the input signal and to generate a pre-distorted signal from the input signal according to the enhanced memory polynomials and the plurality of samples of the input signal. The power amplifier is configured to receive the pre-distorted signal and to generate an output signal. |
| US09628301B2 |
Interference estimation for LTE receiver
A method of estimating interference in a received signal is disclosed. The method includes receiving a plurality of subcarriers from a remote transmitter. Each of the subcarriers is multiplied by a control signal. At least two of the subcarriers are compared to produce a differential signal. Interference is estimated in response to the differential signal. |
| US09628298B2 |
Routing technique
A first communication device sends a call request to a second communication device. The call request comprises a source address associated with the first device and a destination address associated with the second communication device. A communication system modifies the call request by replacing or augmenting the source address with a dynamic address and adding a key associated with the source address. The modified request is sent to the second device.If a user at the second device wants to make a return call, a call request is sent using the dynamic address as the destination address along with the key. The call request is routed to the first communication address by determining the source address of the first communication device from the key. |
| US09628295B2 |
Method, device, and routing system for data transmission of network virtualization
A method resolves connectivity of services inside a network virtualization system when a virtual cluster system supports unicast IP, L2VPN, and L3VPN services, so that the software network virtualization system can support various types of services efficiently and with high quality. The method includes: creating, on a control device, a virtualized remote logical interface for an external interface of a remote access node; identifying, by the control device according to a service configured on the virtualized remote logical interface, a service type of the service, and generating virtual link forwarding entries of the remote access node and a core aggregation node; and sending, by the control device, the virtual link forwarding entry to the remote access node and the core aggregation node, so as to set up a virtual link between the core aggregation node and the remote access node. |
| US09628293B2 |
Network layer multicasting in trill networks
Systems and techniques for performing network layer multicasting in a TRILL network are described. Some embodiments provide a system that receives multicast packet that includes a network-layer multicast-address. The multicast packet can be received on a first multicast tree associated with a first virtual network. Next, the system can determine, based on the network-layer multicast-address, a second multicast tree associated with a second virtual network over which the multicast packet is to be forwarded. The system can then forward the multicast packet on the first multicast tree associated with the first virtual network, and forward a copy of the multicast packet on the second multicast tree associated with the second virtual network. |
| US09628292B2 |
Intelligent bridging of Wi-Fi flows in a software-defined network (SDN)
Wi-Fi flows are intelligently bridged in a software-defined network (SDN) controller of a wireless communication network that centrally coordinates data plane behavior. A default mode tunnels packets received at an access point to the SDN controller for layer 2 routing decisions. A bridging policy concerning bridging of specific types of traffic flows for the wireless communication network is received at the SDN. Data plane traffic flow for each of a plurality of access points distributed around the wireless communication network is centrally monitored. New data streams tunneled to the SDN controller are matched to bridging policies with deep packet inspection. Responsive to matching, the tunnel mode is converted to a bridge mode by sending a rule concerning the new data stream to the access point. As a result, subsequent packets of the new data stream are transferred at the access point without tunneling additional packets to the SDN controller). |
| US09628288B2 |
Apparatus for controlling network traffic
An apparatus for controlling network traffic is provided. The apparatus includes: a data object service providing module generating a data check service frame; a message service providing module generating a data transmission service frame; a frame delay module adjusting a generation period of the data check service frame generated by the data object service providing module; a traffic analysis module comparing a data transmission amount of the data transmission service frame generated by the message service providing module with a reference data transmission amount, wherein the traffic analysis module determines a generation period of the data check service frame according to a comparison result, and controls the operation of the frame delay module according to a determined generation period; and a transmit queue transmitting a service frame transmitted from the traffic analysis module to a control area network open (CANopen) network. |
| US09628283B2 |
Reverse powering system for telecommunications node
To initiate the transmission of electrical power over a telecommunications connection from a power-collecting telecommunications interface unit such as a customer premises equipment, connectable to a power supply, to a power-receiving unit such as a curbside electrical/optical interface, when a connection is first established, or the collecting unit is first powered up, or in order to re-establish connection after a power outage, control signals are transmitted between low-power modems in the interface units using a low-power communications protocol. This allows the controlled initiation of a larger power output and a higher speed exchange of data once the full telecommunications connection has been established. A low-powered beacon signal is transmitted over the telecommunications connection by the power-collecting telecommunications interface unit on connection to a power supply, for detection by the power-receiving telecommunications interface unit. In the event of a loss of power at the input, the low power modem initiates power management control signals to cause the power-receiving telecommunications interface to shut down certain functions in order to preserve backup power for essential “lifeline” services. |
| US09628279B2 |
Protecting application secrets from operating system attacks
Various embodiments provide techniques and devices for protecting application secrets from operating system attacks. In some examples, applications execute with an isolated user mode of a secure execution environment, while relying on an operating system executing within a separate execution environment for resource management and system services. A proxy kernel can control access by the operating system to data associated with the secure execution environment. Further, the proxy kernel can act as a transparent interface between isolated user mode applications and the operating system during the provision of resource management and system services. |
| US09628269B2 |
System and method for secure message key caching in a mobile communication device
A method and system are provided for processing encrypted messages at a mobile device. A mobile device receives an encrypted message that comprises encrypted content as well as encryption information for accessing the encrypted content. At the mobile device, the encryption accessing information is obtained and stored to memory. The encryption accessing information is retrieved from memory in order to decrypt the encrypted content when the encrypted message is subsequently accessed. |
| US09628267B2 |
Industrial control system with internal generation for secure network communications
Security for network communications is internally generated by an industrial control system (ICS). The ICS is assembled in a known-good environment prior to connecting to another network. While in the known-good environment, one or more components of the ICS auto-negotiate (40) with other components, assigning (42) security tokens. These certificates are used to internally secure communications between the components prior to any connection to other devices and without relying on external provisioning of the security tokens during commissioning (30) of the ICS. |
| US09628249B2 |
Radio communication device, method for controlling radio communication, and radio communication system
A radio communication device includes: a receiver configured to receive a radio signal; and a processor coupled to the receiver, configured to switch between a first communication mode and a second communication mode in accordance with scheduling of allocation of a time slot to another radio communication device based on the radio signal, communication between the radio communication device and the another radio communication device being executed using time division multiplexing in the first communication mode, and communication between the radio communication device and the another radio communication device being executed using a competitive access method in the second communication mode. |
| US09628247B2 |
Radio access network node and mobile station with increased Ack/Nack space for packet downlink Ack/Nack message
A radio access network node (e.g., base station system), a mobile station, and various methods are described herein that increase the size and/or efficiency of an ack/nack bitmap in one or more control messages (e.g., Packet Downlink Ack/Nack message(s)). The mobile station when operating in a Downlink Multi Carrier mode sends the one or more control messages to the radio access network node. |
| US09628244B2 |
Communications system, on-vehicle electronic device and communication method
An on-vehicle electronic device creates a first signal and a second signal, and designates the number of times of transmitting the second signal. When noise is generated, the first signal includes information indicating a period of time to receive a signal by the portable device longer than that when noise is not generated. When noise is generated, the number of times of transmitting the second signal to a portable device by the on-vehicle electronic device to be designated is larger than that when noise is not generated. For the period of time to receive a signal indicated by the first signal, the portable device receives a signal. |
| US09628242B2 |
Method and apparatus for transmitting a signal in a wireless communication system
An embodiment of the present invention relates to a method in which a base station transmits a signal in a wireless communication system, comprising: a step of generating a reception acknowledgement response to the uplink data received from a terminal; and a step of mapping the reception acknowledgement response to a downlink time-frequency resource and transmitting the mapped result. The downlink time-frequency resource is located on a resource region excluding the control region indicated by a physical control format indicator channel, and associated with the index of the resource block with which the uplink data is transmitted. |
| US09628241B2 |
Method and apparatus of transmitting uplink signal
A method for transmitting an uplink signal by a communication apparatus in a wireless communication system is discussed. The method includes multiplexing control information with at least one of a plurality of data blocks to generate a bit sequence; and transmitting the uplink signal including the bit sequence. When the control information includes a first type of control data, the control information is multiplexed with all of the plurality of data blocks. When the control information includes a second type of control data, the control information is multiplexed only with a specific data block among the plurality of data blocks. The first type of control data includes acknowledgement/negative acknowledgement (ACK/NACK) information, and the second type of control data includes channel quality information. |
| US09628235B2 |
Communication system, base station apparatus, terminal apparatus, and communication method
The present invention is designed to provide a communication system, a base station apparatus, a terminal apparatus and a communication method that can support the diversification of communication. In the communication system of the present invention, in which a terminal apparatus receives a downlink data signal transmitted from a base station apparatus (eNB) in a radio resource region for a downlink data signal, the base station apparatus transmits a terminal-specific reference signal in the radio resource region for the downlink data signal to the terminal apparatus (UE), and the terminal apparatus measures channel quality information based on the terminal-specific reference signal and transmits the measured channel quality information to the base station apparatus. |
| US09628233B2 |
Method of reference signal allocation in wireless communication systems
A method is provided for determining reference signal positions in a frequency-time domain in an Orthogonal Frequency Division Multiple Access (OFDMA) system. A plurality of sub-carriers are selected in one resource block according to a predetermined mother pattern for reference signal allocation. When a single resource block is assigned for transmission to a user, the reference signal positions are determined corresponding to the plurality of selected sub-carriers in the single resource block. When multiple resource blocks are assigned for transmission to a user, the reference signal positions are determined in the multiple resource blocks by reducing a number of the plurality of selected sub-carriers in the mother pattern for at least one of the multiple resource blocks. |
| US09628225B2 |
Apparatus and method for transmitting data based on cooperation of member nodes belonging to multicast group
Methods and apparatuses for transmitting data based on cooperation of member nodes belonging to a multicast group is provided. The method may include transmitting multicast packets through a first communication network to member nodes belonging to a multicast group and the member nodes receiving the same multicast packets; and retransmitting the multicast packets upon determination that no member node has completed reception of the multicast packets. |
| US09628223B2 |
Bundling of ack information in a wireless communication system
Techniques for bundling acknowledgement (ACK) information in a wireless communication system are described. In one design, a user equipment (UE) may receive multiple codewords in at least one downlink subframe. The UE may decode the multiple codewords and determine an ACK or a negative acknowledgement (NACK) for each codeword based on decoding result. The UE may bundle the ACKs and NACKs for the multiple codewords to obtain bundled ACK information. In one design, the UE may generate (i) a bundled ACK if ACKs are obtained for all codewords or (ii) a bundled NACK if a NACK is obtained for any codeword. The UE may send the bundled ACK information as feedback for the multiple codewords. The UE may receive retransmissions of the multiple codewords if a bundled NACK is sent and may receive new codewords if a bundled ACK is sent. |
| US09628221B2 |
Broadcast-signal transmitter/receiver and method for transmitting/receiving broadcast signals
The broadcast-signal transmitter according to one embodiment of the present invention includes: an encoder for encoding physical layer pipe (PLP) data, including a base layer and an enhancement layer of a broadcasting service, and signaling information through a SISO, and/or MIMO technique; a frame builder for generating a transmission frame, which includes a preamble having the encoded signaling information and the PLP data and an OFDM generator for modulating and transmitting a broadcast signal including the transmission frame. |
| US09628220B2 |
Remote TX training with a re-timer
A device for transmit (TX) training a remote link partner (LP) includes a TX retimer module adjacent to a TX port of the device, and a receive (RX) retimer module adjacent to the TX retimer module. The RX retimer module copies first control and status data to the TX retimer module, and the TX retimer module provides second control and status data for TX training of the remote LP. |
| US09628219B2 |
Apparatus and method for transmitting and receiving polarized signals
Provided is an apparatus and method for transmitting and receiving polarized signals. Wireless communication with multiple polarized signals may experience greater attenuation on one polarized signal than another polarized signal. The polarized signal that is more attenuated limits overall throughput for the wireless communication. According to an embodiment of the invention, signals undergo rotation processing with a transformation involving a rotation matrix prior to transmission. Each polarized signal that is transmitted is based on a different weighted combination of the signals. The rotation processing can be performed with an objective that signals recovered at a receiver have comparable signal quality, which can increase overall throughput. In some implementations, the rotation processing is performed based on feedback to dynamically adjust the rotation processing. |
| US09628218B2 |
Apparatus and method for sending and receiving channel state information in communication system
The present invention relates to a channel status information transmission/reception method and apparatus in a wireless communication system in which the transmission apparatus generates channel status informations for at least two transmission schemes by combining rank informations corresponding to the transmission schemes into combined rank information through analyzing an uplink channel, and transmits the channel status informations for the respective transmission schemes on uplink channel, the channel status information for one of the transmission schemes containing the combined rank information; the reception apparatus receives the channel status informations corresponding to at least two transmission schemes, the channel status information for one of the transmission schemes including combined rank information for the transmission schemes, schedules downlink channel according to the channel status information, and transmits signals on the downlink channel. According to the present invention, the transmission apparatus combines rank informations of a plurality of transmission schemes and feeds back the combined rank information so as to reduce overhead at a reception apparatus. |
| US09628215B2 |
Cell-specific reference signal interference cancellation improvement
A method includes receiving, at a user equipment, a signal including cell-specific reference signals from a number of cells. Cell-specific reference signal(s) are measured from one of the cells to determine measured result(s). The user equipment, based on the measured result(s) meeting first criteria, performs interference cancelation to cancel the cell-specific reference signal(s) corresponding to the one cell from the signal. The user equipment performs the measuring and the performing the interference cancelation for additional ones of the cells until second criteria are met. The user equipment uses measured cell-specific reference signals having their interference canceled to reduce an effect of interference from corresponding cells on communications between the user equipment and a base station. A base station may store cell search information that can be sent to the user equipment to help the user equipment perform the previous method. Apparatus, systems, computer programs, and program products are also disclosed. |
| US09628214B2 |
Handling mismatch of control spans between serving cell and interfering cells for control and data channel interference cancellation
The following is directed to control and data channel interference cancellation between a serving cell and interfering cell. A first symbol of a subframe is processed to determine a control span of a serving cell and a control span of an interfering cell. The interference is then cancelled based on the determined control spans. |
| US09628213B2 |
Access system, communication method and device for optical fiber network
Embodiments of the present invention provide an access system and a communication method for an optical fiber network. A virtual ONU located on a user side is established, and an ONU control plane function, a PON MAC function, and a QoS function on an existing ONU is moved downwards to a virtual ONU. After the forgoing function modules are removed from the existing ONU, the existing ONU becomes an ONU physical converter and only has a function of converting the PON physical layer frame and the first user side physical layer frame. |
| US09628211B1 |
Clock generation with non-integer clock dividing ratio
A clock generator for generating a clock equivalent to a target clock which is an input clock divided by a non-integer ratio is disclosed. The clock generator comprises a clock divider configured to receive the input clock and divide the input clock with a reconfigurable dividing ratio; and a control circuit controlling operations of the clock divider to divide the input clock by a first dividing ratio to generate a first number of cycles of a first clock in a frame, and divide the input clock by a second dividing ratio to generate a second number of cycles of a second clock in the frame, wherein a difference between a period of the frame and a cumulative time of the first number of cycles of the first clock and the second number of cycles of the second clock is less than a threshold value. |
| US09628210B1 |
Universal asymmetry correction for packet timing protocols
The notion of a “PTP aware” path is one current proposed approach to reduce asymmetry effects. In a fully PTP aware path there is the notion of on-path support mechanisms such as boundary clocks and transparent clocks at every switching or routing node. However, on-path support methods only address time-transfer errors introduced inside network elements and any asymmetry in the transmission medium, such as, for example, the fiber strands for the two directions of transmission, cannot be compensated for by on-path support mechanisms. Furthermore, in a real operational network, which may traverse different operational domains administered by different entities, full on-path support is a difficult challenge. In certain managed network scenarios full on-path support can be contemplated. Nevertheless, the universal asymmetry compensation method described herein mitigates the asymmetry in a network path, without requiring on-path support mechanisms such as transparent clocks and boundary clocks. |
| US09628206B2 |
Endpoint parameter management architecture for audio mixers
The present disclosure describes a system using an audio mixer for managing endpoint parameters of an input audio device and an output audio device. The system includes a data terminal, multiple endpoints, and the audio mixer, where the data terminal provides multiple data files including configuration parameters of endpoints. The endpoints include a first endpoint and a second endpoint. The audio mixer is configured to receive the data files from the data terminal, process the data files to obtain a first set of configuration parameters corresponding to the first endpoint and a second set of configuration parameters corresponding to the second endpoint, convert the first set and the second set of configuration parameters into a predefined common data format, and organize the predefined common data structure into a generic data structure. |
| US09628202B2 |
Testing front end modules, testing methods and modular testing systems for testing electronic equipment
A testing front end module for testing a plurality of devices under test (DUT) includes a testing signal interface, a vector signal generator (VSG) coupled to the testing signal interface and configured to generate testing signals upon reception of testing routine signals from a remote controller via the testing signal interface, a vector signal analyzer (VSA) coupled to the testing signal interface and configured to receive testing response signals from a plurality of DUTs and to transmit the received testing response signals to the remote controller via the testing signal interface, a multiplexer/demultiplexer (MUX/DEMUX) coupled to the VSG and the VSA, the MUX/DEMUX being configured to multiplex the received testing response signals and to demultiplex the generated testing signals, and a test device interface coupled to the MUX/DEMUX and configured to couple the testing front end module to the plurality of DUTs. |
| US09628196B2 |
Interconnect signal transmission system
Systems and methods for transmitting interconnect signals include a source device having a first source device input connector of a first interconnect technology, a second source device input connector of a second interconnect technology, and a source device output connector. A cable includes a first connector that is coupled to the source device output connector, a second connector, and a transmission line extending between the first connector and the second connector. A receive device is coupled to the second connector. The transmission line is configured to pass a first signal of the first interconnect technology and a second signal of the second interconnect technology, received through the source device output connector by the first connector, to the second connector. The first and second signal may be multiplexed into a single stream before being passed over the transmission line, and then demultiplexed for use by the receive device. |
| US09628195B2 |
Transimpedance amplifier (TIA) having an enlarged dynamic range and optical devices using the same
A gain-variable trans-impedance amplifier (TIA) in optical device is disclosed. The TIA has an improved dynamic range for receiving electrical signals and is configured to convert current signals from an avalanche photodiode (APD) to voltage signals. A resistor element is between the input and output terminals of the TIA, wherein the resistance of the resistor element can regulate the resistance and/or impedance value of the TIA, and a switch determines or controls the resistance of the resistor element. When the power of an optical signal received by the APD is higher than a predetermined value, the resistance becomes smaller and the gain of the TIA becomes greater. When the power of the optical signal is lower than the predetermined value, the resistance becomes greater. The gain of the TIA is automatically adjusted on the basis of the intensity of received optical signals to obtain a greater dynamic operational range. |
| US09628190B2 |
Optical transmitter and optical communication device
At least two light-emitting elements emit light to a branching device, and the branching device divides the light that entered into an input port into at least two and emits the light from M number of output ports. An optical modulator individually modulates the M number of light beams that were emitted. When a first light-emitting element driven normally fails, the first light-emitting element is stopped and a second light-emitting element that was stopped is driven, thereby maintaining the emission of the modulated M number of light beams. |
| US09628188B2 |
Apparatus and methods for generating and receiving optical signals having standard and shifted wavelengths
An optical communication technique transmits an optical signal at a higher bit rate using an optical transceiver interface couplable to a set of optical transmitters, each operating at a lower bit rate over a plurality of channels, by demultiplexing the optical signals from the transmitters such that some of the resulting optical signals have wavelengths that are specified as center wavelengths by an optical communication standard for the lower bit rate optical transmission and the rest of the resulting optical signals have wavelengths offset from the specified center wavelengths, then multiplexing the resulting optical signals into the higher bit rate optical signal. Related optical communication techniques involve using the reciprocal method to receive the higher bit rate optical signal and to produce multiplexed optical signals at the lower bit rate. |
| US09628187B1 |
Isolating light paths
Optical waveguides can extend alongside one another in sufficient proximity such that light couples between or among them as crosstalk. The electromagnetic field associated with light flowing in one optical waveguide can extend to an adjacent optical waveguide and induce unwanted light flow. The optical waveguide receiving the crosstalk can comprise a phase shifting capability, such as a longitudinal variation in refractive index, situated between two waveguide lengths. Crosstalk coupled onto the first waveguide length can flow through the refractive index variation, be phase shifted, and then flow onto the second waveguide length. The phase shifted crosstalk flowing on the second waveguide can meet other crosstalk that has coupled directly onto the second waveguide segment. The phase difference between the two crosstalks can suppress crosstalk via destructive interference. Destructive interference can also result from disposing a phase shifting provision in a crosstalk coupling path located between two optical waveguides. |
| US09628184B2 |
Efficient optical communication device
In one embodiment, an apparatus for optical communication is disclosed. An optical sub-assembly and optical platform may form the apparatus. Lasers contained in the hermetically sealed optical sub-assembly can be coupled to a modulator on the optical platform. The optical modulator can access an optical network using beams of light sent from the laser. |
| US09628182B2 |
Repeater, feedthrough, and repeater manufacturing method
A repeater includes: a pressure-tight casing to be arranged on seabed or in sea; and a feedthrough having a plurality of lead sections each configured to connect a circuit housed in the pressure-tight casing with a cable outside the pressure-tight casing, wherein the plurality of lead sections include at least a power wire and an electric signal wire, and at least two of the plurality of lead sections have a difference in length from each other. |
| US09628177B1 |
Adaptive baud rate in light-based communication
Light-based communication (LCom) techniques are disclosed for adaptively adjusting the baud rate of a luminaire to optimize the LCom signal transmitted for an intended receiver device. The adaptive baud rate can be adjusted by a process that includes, for example: determining decoding parameters of the receiver device, the device including a camera for receiving LCom signals, and a display. The process further includes calculating a baud rate suitable for the receiver device based on the decoding parameters, and causing the baud rate to be set at the luminaire. The process may further include at least one of: verifying the baud rate at the receiver device; adjusting the decoding parameters of the receiver device if baud rate cannot be adjusted to meet a current configuration of decoding parameters; and prompting a user to rotate receiver device to improve orientation of the luminaire with respect to a raster direction of the camera. |
| US09628172B2 |
Optimization of photonic services with colorless and directionless architecture
A method, in a node operating in a network with a control plane, to optimize wavelength retuning on service redials, includes detecting a failure on a link associated with the node; and, for each affected connections on the link, sending a respective release message to an associated originating node via the control plane, the release message including a protect path and a wavelength, wherein the release message is utilized by the associated originating node to redial the affected connections with the protect path and the wavelength determined by the node, to minimize wavelength retuning on the affected connections. |
| US09628171B2 |
Systems and methods for timeslot assignment in a wireless network
A mobile station in a communications system includes hardware and software stored on a tangible computer readable medium that, during operation, cause the mobile station to receive a timeslot assignment from a wireless network and operate based on the received timeslot assignment. The timeslot assignment may be based on whether a timing advance offset is used by the wireless network. The mobile station may also receive an indication from the wireless network, indicating whether a timing advance offset is used by the wireless network. The mobile station may subsequently operate based on the received indication. |
| US09628170B1 |
Devices and methods for a rotary joint with multiple wireless links
A device is provided that includes a first platform having a first side, and a second platform having a second side positioned within a predetermined distance to the first side. The device also includes an actuator configured to cause a relative rotation between the first platform and the second platform such that the first side of the first platform remains within the predetermined distance to the second side of the second platform. The device also includes a probe mounted to the first platform, and a plurality of probes mounted to the second platform. The device also includes a signal conditioner coupled to the plurality of probes. The signal conditioner may select one of the plurality of probes based on an orientation of the first platform relative to the second platform. The signal conditioner may then to use the selected probe for wireless communication with the probe on the first platform. |
| US09628163B2 |
Low-complexity communication terminal with enhanced receive diversity
A method includes, in a receiver, receiving a signal carrying data using multiple antennas, so as to produce multiple respective input signals. The input signals are divided into two or more subsets. The input signals within each of the subsets are combined in a first diversity-combining stage, to produce respective intermediate signals. In a second diversity-combining stage, the intermediate signals are combined to produce an output signal. The output signal is decoded so as to reconstruct the data carried by the received signal. |
| US09628159B2 |
Transmission device and transmission method
A transmission device comprising: a weighting circuity which, in operation, generates transmission signals of n streams (n is an integer of 3 or more) by weighting modulated signals of the n streams using a predetermined fixed precoding matrix; a phase changing circuity which, in operation, regularly changes each phase of a symbol series included in each of the transmission signals of the n streams; and a transmitter which, in operation, transmits the transmission signals of the n streams from different antennas, the phases of each of the transmission signals of the n streams being changed in each symbol, wherein the transmission signal of an i-th stream has an mi kind of phase change value yi(t) (i is an integer between 1 and n (inclusive), 0≦yi<2π, and mi is set in each stream, t is an integer of 0 or more, and indicates a symbol slot), and the phase changing circuity changes the phase in one or more u (u=m1×m2× . . . ×mn) symbol periods using all patterns of a set of phase change values yi(t) different from each other in each symbol. |
| US09628153B2 |
Closed loop MIMO systems and methods
Systems and methods for closed loop MIMO (multiple input and multiple output) wireless communication are provided. Various transmit formats including spatial multiplexing and STTD are defined in which vector or matrix weighting is employed using information fed back from receivers. The feedback information may include channel matrix or SVD-based feedback. |
| US09628151B2 |
Selection of access points for coordinated multipoint uplink reception
The proposed technology involves a mechanism for selecting, for a user, access points for coordinated multipoint (COMP) uplink reception. The method comprises obtaining, for each of a number of candidate access points, at least one uplink measurement result. The method also involves combining candidate access points to form at least two different sets of access points from the candidate access points. The method comprises estimating, for each one of the at least two different sets of access points, an uplink quality measure based on the uplink measurement results of the considered set of access points, and determining, for each one of the at least two different sets of access points, a measure representative of the number of transmission opportunities available to the user for the considered set of access points over a given period of time. The method also comprises selecting which one of the at least two different sets of access points to use for COMP uplink reception based on the uplink quality measure and the measure representative of the number of transmission opportunities available to the user over the given period of time. |
| US09628144B2 |
Method for estimating a time invariant transmission channel, and corresponding receiver
A method is for processing an analog channel signal from a transmission channel. The method may include converting of the analog channel signal to a digital channel signal, and performing a channel estimation digital processing of the digital channel signal. The channel estimation digital processing may include for at least one frame, generating transfer functions of the transmission channel, the transfer functions respectively associated with reference symbols of the frame, and averaging processing of the transfer functions to generate an average transfer function. The method may include decoding of symbols of the frame following the reference symbols using the average transfer function. |
| US09628141B2 |
System and method for acoustic echo cancellation
A system and method are presented for acoustic echo cancellation. The echo canceller performs reduction of acoustic and hybrid echoes which may arise in a situation such as a long-distance conference call with multiple speakers in varying environments, for example. Echo cancellation, in at least one embodiment, may be based on similarity measurement, statistical determination of echo cancellation parameters from historical values, frequency domain operation, double talk detection, packet loss detection, signal detection, and noise subtraction. |
| US09628136B2 |
Methods and apparatus for controlling multiple-input and multiple-output operation in a communication device based on a position sensor input
A method for disabling multiple-input and multiple-output operation in a communication device includes communicating data using multiple-input and multiple-output operation, wherein the data is communicated using multiple transceiver paths. Further, the method includes receiving position sensor input and disabling at least a portion of one or more transceiver paths, of the multiple transceiver paths, based on the position sensor input. |
| US09628135B1 |
Method for automatically adjusting a tunable matching circuit, and automatic tuning system using this method
The invention relates to a method for automatically adjusting a single-input-port and single-output-port tunable matching circuit, for instance a single-input-port and single-output-port tunable matching circuit coupled to an antenna of a radio transceiver. The invention also relates to an automatic tuning system using this method. An automatic tuning system comprises: one user port; one target port; a sensing unit; a single-input-port and single-output-port tunable matching circuit comprising one or more adjustable impedance devices; a signal processing unit which delivers a tuning instruction as a function of one or more temperature signals and as a function of two or more real quantities depending on an impedance seen by the target port; and a tuning control unit which delivers tuning control signals, the reactance of each adjustable impedance device of the tunable matching circuit being determined by at least one of the tuning control signals. |
| US09628133B2 |
Case having protective film for electronic device
A case having a protective film for an electronic device includes a soft protective shell having a bottom and a side wall, a hard protective frame configured to removably mount over the bottom and side wall of the protective shell, and a protective film for covering the front portion of the electronic device. The soft protective shell significantly covers hack and side portions of the electronic device, but does not significantly covers a front portion of the electronic device. The protective shell further includes an inverted “L”-shaped recess for receiving and holding in place edges of the protective film. The case may further include a film frame for covering the protective film. |
| US09628119B2 |
Adaptive high-order nonlinear function approximation using time-domain volterra series to provide flexible high performance digital pre-distortion
A method is described for predistorting an input signal to compensate for non-linearities caused to the input signal in producing an output signal. The method comprises: providing an input for receiving a first input signal as a plurality of signal samples, x[n], to be transmitted over a non-linear element; providing at least one digital predistortion block comprising, a plurality of IQ predistorter cells coupled to the input, each comprising a lookup table (LUT) for generating an LUT output. The at least one digital predistortion block block is configured to apply interpolation between LUT entries for the plurality of LUTs; and generate an output signal, y[n], by each of the plurality of IQ predistorter cells by adaptively modifying the first input signal using interpolated LUT entries to compensate for distortion effects in the non-linear element. A combiner may be provided configured to combine the output signal samples, yQ, from the plurality of IQ predistorter cells into a combined signal to generate the output signal, y[n], for transmission to the non-linear element. An error calculation block may be coupled to a digital predistortion adaptation block to determine and modify a predistortion performance. |
| US09628117B2 |
Amplifier
Mobile devices such as mobile phones include amplifiers for example audio and RF amplifiers which may consume a significant amount of the available power supplied by a battery. An amplifying system 100 for a mobile device is described the amplifying system comprising a current monitor 12 arranged between a first supply node and a second supply node and operable to monitor a current flow between the first and second supply nodes and to output a monitored current value; a peak current limiter 14 configured to limit an amplifier current to an amplifier to not exceed a maximum peak current value and coupled to a one of the first supply node and the second supply node; a controller coupled to the current monitor output and configured to control the peak current limiter. The amplifying system can dynamically manage the peak current available to the amplifier dependent on the load current being supplied by a battery. |
| US09628115B1 |
Wireless communication device
A wireless communication device that has a circuit board, an RF signal module, a capacitive touch-sensing component and an antenna component is provided. The touch-sensing signal module is disposed on the circuit board. The capacitive touch-sensing component includes a sensing layer and a ground layer. The sensing layer is electrically connected to the touch-sensing signal module. The antenna component includes a feed point and a radiating body. The feed point is disposed on the ground layer and is electrically connected to the RF single module. The radiating body incorporates at least parts of the ground layer. Alternatively, the feed point is disposed on the sensing layer, and the radiating body incorporates at least parts of the sensing layer. Therefore, the radiating body is incorporated into the sensing layer or ground layer of the capacitive touch-sensing component and can save accommodating space. |
| US09628114B2 |
Length-compatible extended polar codes
A method for increasing coding reliability includes generating a generator matrix for an extended polar code including a standard polar code part and an additional frozen part. The standard polar code part has N bit-channels, including K information bit-channels and N−K frozen bit-channels. The additional frozen part has q additional frozen bit-channels. Among the K information bit-channels, q information bit-channels are re-polarized using the q additional frozen bit-channels. The method further includes receiving an input vector including K information bits and N+q−K frozen bits, and transforming, using the generator matrix, the input vector to an output vector including N+q encoded bits. The K information bits are allocated to the K information bit-channels, and the N+q−K frozen bits are allocated to the N−K frozen bit-channels and the q additional frozen bit-channels. |
| US09628112B2 |
Apparatus and method for length and rate variable LDPC encoder and decoder using shortening set allocator
A method and apparatus for encoding data and for decoding data using LDPC (low density parity check) codes includes providing a mother LDPC matrix of a particular size. A data payload of a smaller size is encoded by shortening the mother matrix to a smaller daughter matrix corresponding in size to the data payload and using the smaller daughter matrix for the encoding. The portions of the mother matrix to be removed in the shortening are derived from a control signal. The encoded data is transmitted with the control signal so that the receiver can derive the portions of the mother matrix to be removed to obtain the daughter matrix. At the receiver, a mother matrix is shortened to a daughter matrix and is then used to decode the data. The data at the encoder may be further reduced by puncturing to remove selected information bits and selected parity bits. The decoder inserts the selected information bits and parity bits when decoding the data. |
| US09628109B1 |
Operation of a multi-slice processor implementing priority encoding of data pattern matches
Operation of a multi-slice computer processor that includes a plurality of execution slices. Operation of such a computer processor includes: matching one or more sub strings of a data string to one or more substrings of a data set; determining that a particular substring of the one or more substrings of the data string corresponds to a highest priority value among one or more priority values mapped to one or more encodings for the one or more substrings of the data string; and encoding, in dependence upon the particular substring of the data string corresponding to the highest priority value, the data string into an encoding that encodes the particular substring of the one or more substrings of the data string. |
| US09628108B2 |
Method and apparatus for dense hyper IO digital retention
System and method to encode and decode raw data. The method to encode includes receiving a block of uncoded data, decomposing the block of uncoded data into a plurality of data vectors, mapping each of the plurality of data vectors to a respective bit marker, wherein the respective bit marker is shorter than said respective mapped data vector, and storing the bit marker in a memory to produce an encoded representation of the uncoded data. Encoding may further include decomposing the block of uncoded data into default data and non-default data, and mapping only the non-default data. In some embodiments, bit markers may include a seed value and replication rule, or a fractalized pattern. |
| US09628102B2 |
Integrated circuits, liquid crystal display (LCD) drivers, and systems
An integrated circuit includes a digital-to-analog converter (DAC) circuit including at least one first channel type digital-to-analog converter (DAC) and at least one second channel type DAC. The integrated circuit further includes a plurality of sample and hold (S/H) circuits, each of the plurality of S/H circuits being coupled with a single DAC of the DAC circuit. A number of the at least one first channel type DAC is different than a number of the at least one second channel type DAC. |
| US09628098B2 |
Multichannel transducer devices and methods of operation thereof
The present disclosure is directed to multichannel transducer devices and methods of operation thereof. One example device includes at least two acquisition modules that have different sensitives and a signal processing stage that generates a blended signal representative of a lower gain signal mapped onto a higher gain signal. One example method of operation includes receiving a first signal from a first sensor having a first sensitivity, receiving a second signal from a second sensor having a second sensitivity that is different from the first sensitivity, generating a blended signal by mapping the second signal to the first signal, outputting the first signal while the first signal is below a first threshold and above a second threshold, and outputting the blended signal when the first signal is above the first threshold and when the first signal is below the second threshold. |
| US09628095B1 |
Parameterizable method for simulating PLL behavior
Methods for designing and developing models for simulating the behavior of clock signals and in particular those generated by phase-locked loop (PLL) circuits are provided. The clock period of a phase-locked loop circuit's variable frequency oscillator signal may be modeled by combining the inverse of the oscillator frequency rounded up to the simulation time scale with the inverse rounded down to the simulation time scale. The variable frequency oscillator signal may further be synchronized with a reference clock signal at a rate determined by the relationship between the reference clock signal and the variable frequency oscillator signal. A parameter may indicate a target range for the deviation between the two signals and a runtime monitor may be used together with the parameter setting to decide whether synchronization is required and make the appropriate adjustments. |
| US09628094B2 |
Apparatus and method for fast phase locking for digital phase locked loop
Described is an integrated circuit (IC) with a phase locked loop with capability of fast locking. The IC comprises: a node to provide a reference clock; a digitally controlled oscillator (DCO) to generate an output clock; a divider coupled to the DCO, the divider to divide the output clock and to generate a feedback clock; and control logic operable to reset the DCO and the divider, and operable to release reset in synchronization with the reference clock. An apparatus for zeroing phase error is provided which comprises a first node to provide a reference clock; a second node to provide a feedback clock; a time-to-digital converter, coupled to the first and second nodes, to measure phase error between the reference and feedback clocks; a digital loop filter; and a control unit to adjust the measured phase error, and to provide the adjusted phase error to the digital loop filter. |
| US09628088B2 |
Multi-mode crystal oscillators
Digital control of a crystal oscillator is implemented in a manner that allows frequency accuracy to be traded off dynamically with power consumption. The oscillator transitions between a less accurate/lower power mode and a high accuracy/higher power mode smoothly without requiring any external clock source during the transition. Power consumption is optimized because the crystal oscillator provides the clock source during transitions between the power modes and no other clock source is needed for these transitions. The system can also optimize the startup time and steady state power consumption independently. |
| US09628087B2 |
Radio transmission apparatus
A radio transmission apparatus includes a radio transmission IC including a vibration element and a fractional N-PLL circuit and a power amplifier generating a radio transmission signal and a control device that controls the radio transmission IC, and a temperature detection element. The control device controls the fractional N-PLL circuit based on temperature information obtained from the temperature detection element such that a frequency of the radio transmission signal is temperature-compensated. |
| US09628080B2 |
Voltage generating circuits based on a power-on control signal
A voltage generating circuit includes a first supply voltage node, a first switching device, a sub voltage generating circuit, and a second switching device. The first supply voltage node is configured to have a first supply voltage value, and is coupled with the first switching device. The sub voltage generating circuit is coupled in between the first switching device and the second switching device. The first switching circuit and the second switching circuit are configured to receive a control signal behaving based on the first supply voltage value and a second supply voltage value different from the first supply voltage value. |
| US09628078B2 |
Electronic device
An electronic device including an inverter includes a pull-up driving unit configured to drive an output node with a high voltage in response to an input signal; a path switching unit coupled in a path between the pull-up driving unit and the output node according to a direction of a first current flowing between the pull-up driving unit and the output node and operable to selectively switch on or off the path; a pull-down driving unit coupled to the output node to supply a low voltage in response to the input signal; a path blocking unit coupled in a path between the pull-down driving unit and the output node to block the path; and a bypass unit coupled to form a bypass path between the pull-down driving unit and the output node. |
| US09628077B2 |
Dual power swing pipeline design with separation of combinational and sequential logics
A three-dimensional integrated circuit having a dual or multiple power domain is capable of less energy consumption operation under a given clock rate, which results in an enhanced power-performance-area (PPA) envelope. Sequential logic operates under a system clock that determines the system throughput, whereas combinational logic operates in a different power domain to control overall system power including dynamic and static power. The sequential logic and clock network may be implemented in one tier of the three-dimensional integrated circuit supplied with a relatively high power supply voltage, whereas the combinational logic may be implemented in another tier of the three-dimensional integrated circuit supplied with a relatively low power supply voltage. Further pipeline reorganization may be implemented to leverage the system energy consumption and performance to an optimal point. |
| US09628076B2 |
Transmission circuit and semiconductor integrated circuit
A transmission circuit includes a driver circuit that includes: a transistor to regulate output impedance, and a switching circuit that is connected to the transistor to regulate output impedance and switches an output polarity for differential output; and a bias circuit that includes: a first replica circuit including another transistor corresponding to the transistor to regulate output impedance, the bias circuit generating a gate voltage so as to make a current-voltage characteristic of the transistor to regulate output impedance correspond to a first output impedance value, and supply the gate voltage to a gate of the transistor to regulate output impedance. |
| US09628074B2 |
Bypass switch for in-line power steal
A power supply unit for use with thermostats or other like devices. The power supply unit may keep electromagnetic interference emissions and harmonics at a minimum. A unit may have enough power for triggering a switch at about a cross over point of a waveform of input power to the unit. Power for triggering may come from a storage source. Power for the storage source may be provided with power stealing which require switching transistors which can generate emissions. In-line thermostats using MOSFETS power steal may do the power steal during an ON state (triac, relay or silicon controlled rectifier activated). Gate signals to the transistors may be especially shaped to keep emissions from transistor switching at a minimum. All that may be needed, during an OFF state as a bypass, is a high voltage controllable switch. The need may be achieved using high voltage MOSFETS. |
| US09628073B2 |
Current control circuit
A current control circuit includes a first drive switching device, a gate power source, a control switching device, a first resistor, an operational amplifier, and a switching circuit. The operational amplifier includes: an output terminal connected to the control switching device; a non-inverting input terminal; and an inverting input terminal configured to receive a reference potential. The switching circuit is configured to: input a value based on a potential difference between both ends of the first resistor to the non-inverting input terminal when a current flowing through the first drive switching device is equal to or smaller than a threshold level; and input a value based on a potential on a current pathway between the control switching device and the first drive switching device to the non-inverting input terminal when the current flowing through the first drive switching device is greater than the threshold level. |
| US09628072B2 |
Driving device and switching circuit control method
A driving device includes a switching circuit configured to have switching elements disposed on a high side and a low side, the switching element including a first electrode, a second electrode, and a reverse conducting element disposed between the first electrode and the second electrode; and a determination part configured to determine whether to permit the switching element to turn on, based on a result obtained by detecting a voltage between the first electrode and the second electrode, in a period during which the switching elements on both sides are off. |
| US09628071B2 |
Power-on reset circuit and display device using power-on reset circuit
A power-on reset circuit includes a voltage detector unit to output an electrical signal in response to a power supply voltage received from a power supply terminal, an inverter to output a reset signal according to a level of the electrical signal from the voltage detector unit, a first switch unit to be turned on or off in response to the reset signal from the inverter; a first discharge unit to discharge the electrical signal in response to the power supply voltage from the first switch unit, a second switch unit to be turned on according to a start pulse signal from an external device and to receive the power supply voltage from the power supply terminal, and a second discharge unit to discharge the electrical signal in response to the power supply voltage from the second switch. |
| US09628070B2 |
Radio frequency switch circuit and control method thereof
A radio frequency switch circuit may include a first switch circuit unit connected between a signal port and an antenna port, a second switch circuit unit connected between the signal port and a ground, and a third switch circuit unit connected between the antenna port and the ground. An operation reference voltage of the third switch circuit unit is lower than an operation reference voltage of the first switch circuit unit. |
| US09628069B2 |
Transmission circuit with leakage prevention circuit
A transmission circuit includes: a first transistor, having a source terminal coupled to a first reference voltage terminal of the transmission circuit and a drain terminal coupled to a first output terminal of the transmission circuit; a second transistor, having a source terminal coupled to a gate of the first transistor, and a drain terminal coupled to the first output terminal of the transmission circuit; and a third transistor, having a drain terminal coupled to the first output terminal of the transmission, a source terminal coupled to a second reference voltage terminal of the transmission, and a gate terminal for receiving a first input signal; wherein the first and second transistors are of a first conducting type, and the third transistor is of a second conducting type different from the first conducting type. |
| US09628068B2 |
High power FET switch
Described are embodiments of stacked field effect transistor (FET) switch having a plurality of FET devices coupled in series to form an FET device stack. To prevent the FET device stack from being turned on during large signal conditions, one or more decoupling paths are provided and are configured to pass the time-variant input signal during the open state of the FET device stack. The first decoupling path may include a capacitor, a transistor, or the like, that passes the time-variant input signal by, for example, presenting a low impedance to the time-variant input signal during the open state. The decoupling paths may be connected so that the time-variant input signal bypasses a portion of the FET device stack during the open state. |
| US09628065B2 |
Safety instrumented process control apparatus and methods
Example apparatus and methods to remove power from a field device are disclosed. An example apparatus includes a first switch to control power to the field device, and a second switch comprising a first gate and a second gate. The second gate is electrically coupled in parallel to the first gate, and the second switch is electrically coupled in series to the first switch. The example apparatus also includes a first diagnostics controller to control the first and second gates, a first processor to control the first switch, a third switch to control power to the field device, and a fourth switch comprising a third gate and a fourth gate. The fourth gate is electrically coupled in parallel to the third gate, and the fourth switch is electrically coupled in series to the third switch. The example apparatus also includes a second processor to control the third switch, and a second diagnostics controller to control the third and fourth gates. |
| US09628063B2 |
Asymmetrically-switched modulation scheme
An asymmetric modulation scheme may be used to drive two output nodes coupled to a load. The asymmetric modulation scheme may be one-sided such that the switching rate of a first output node is lower than the switching rate of a second output node. The first output node may be switched only to change a direction of current between the first output node and the second output node, while the second output node is switched to convey the information of an input signal. The asymmetric modulation scheme may be used to drive a speaker to reduce noise at the first output node to improve accuracy of current monitoring through the speaker by a current monitor coupled at the first output node. |
| US09628061B2 |
Power drop detector circuit and operating method of same
A power drop detector circuit includes a detect element, for coupling to a first source voltage, for detecting a voltage level of the first source voltage, and a memory element coupled to the detect element and switchable between a first memory state and a second memory state based on the voltage level of the first source voltage. |
| US09628059B2 |
Fine delay structure with programmable delay ranges
A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node. |
| US09628054B1 |
Current-mode logic latch circuit
A latch circuit including a symmetric circuit, a clock receiving circuit, a current generating circuit, a sampling circuit and a holding circuit is provided. The clock receiving circuit receives a first clock signal and a second clock signal. A phase difference between the first clock signal and the second clock signal is 180 degrees. The current generating circuit is electrically connected with the symmetric circuit and the clock receiving circuit, for providing a discharge current. The sampling circuit is electrically connected with the current generating circuit. According to the first clock signal, the sampling circuit receives a differential input signal, and the discharge current flows through the sampling circuit. The holding circuit is electrically connected with the current generating circuit. According to the second clock signal, the discharge current flows through the holding circuit, and the holding circuit generates a differential output signal. |
| US09628052B2 |
Embedded multi-terminal capacitor
An embedded multi-terminal capacitor embedded in a substrate cavity includes at least one metal layer patterned into a plurality of power rails and a plurality of ground rails. The substrate includes an external power network. |
| US09628050B2 |
Scan driving circuit
A scan driving circuit configured for driving cascaded scan lines is provided, which includes an input control module, a latch module, a driving-signal generation module, an output control module, a constant high voltage source and a constant low voltage source. The scan driving circuit of the present invention drives the input control module through cascade signals of a preceding stage and cascade signals of a succeeding stage, so as to reduce interference and the driving power consumption of the scan driving circuit. |
| US09628047B2 |
Acoustic wave devices, and antenna duplexers, modules, and communication devices using same
An elastic wave device including a substrate, an interdigital transducer (IDT) electrode provided on an upper surface of the substrate, a first wiring electrode provided on the upper surface of the substrate and connected to the IDT electrode, a dielectric film that does not cover a first region of the first wiring electrode but covers a second region of the first wiring electrode above the substrate, the first wiring electrode including a cutout in the second region, and a second wiring electrode that covers an upper surface of the first wiring electrode in the first region and an upper surface of the dielectric film in the second region above the substrate. |
| US09628046B2 |
Resonator element, resonator, oscillator, electronic apparatus, and mobile object
A resonator element includes a resonator blank having a base portion, a vibrating arm, a linking portion, and a connecting portion connects the base portion and the linking portion to each other, in which, when a thickness of the resonator blank is set to T, a width of the base portion is set to W1, and a width of the connecting portion is set to W2, a relationship of 50 μm≦T≦210 μm is satisfied, and a relationship of 0.067≦W2/W1≦0.335 is satisfied, and in which, when a width of the arm section of the vibrating arm is set to W3, and a width of the hammer head is set to W4, a relationship of W4≧2.8×W3 is satisfied. |
| US09628044B2 |
Parameter scanned tunable antenna
Generally discussed herein are techniques, software, apparatuses, and systems configured for tuning an antenna. In one or more embodiments, a method can include sending, by processing circuitry, one or more signals to an antenna tuner to sweep the tuner through a plurality of tuner states, determining a plurality of power values, each power value corresponding to a signal received from an antenna and each power value corresponding to the tuner being in a state of the plurality of tuner states, and sending one or more signals to the tuner to set the tuner to a tuner state of the plurality of tuner states, the tuner state determined using the determined powers. |
| US09628041B2 |
Device for blocking high frequency signal and passing low frequency signal
A device is disclosed that includes a transmission plate, a conductive plate, and a capacitive unit. The transmission plate includes a winding structure and is configured to be electrically coupled between an input source and a load. The conductive plate is configured to be electrically coupled to ground. The capacitive unit is electrically coupled between the conductive plate and the transmission plate. |
| US09628036B2 |
Sensor signal processing using translinear mesh
Apparatuses and methods are described where input signals are supplied to a translinear mesh. In some embodiments an output of the translinear mesh is regulated to a desired value. |
| US09628034B2 |
Operational amplifying circuit and semiconductor device comprising the same
An operational amplifying circuit are provided. The operational amplifying circuit includes a control circuit, pull-up and pull-down transistors, first and second bias circuits, and a bias voltage generating circuit. The control circuit includes first and second input terminals, and is configured to change, when an input voltage transitions to a first level, a voltage level of a pull-up node and a pull-down node to a second level different from the first level. The pull-up transistor provides a power supply voltage to the output terminal. The pull-down transistor connects the output terminal to a ground voltage. The first bias circuit provides a first bias current to the control circuit. The bias voltage generating circuit generates a bias voltage when the voltage level of at least one of the pull-up and pull-down nodes reaches a threshold voltage level, and the second bias circuit provides a second bias current to the control circuit. |
| US09628033B2 |
Power stage with switched mode amplifier and linear amplifier
A method for producing an output voltage to a load may include, in a power stage comprising power converter having a power inductor, a plurality of switches arranged to sequentially operate in a plurality of switch configurations, and an output for producing the output voltage comprising a first output terminal and a second output terminal, controlling the linear amplifier to transfer electrical energy from the input source of the power stage to the load in accordance with one or more least significant bits of a digital input signal, and controlling the power converter in accordance with bits of the digital input signal other than the one or more least significant bits to sequentially apply switch configurations from the plurality of switch configurations to selectively activate or deactivate each of the plurality of switches in order to transfer electrical energy from the input source of the power stage to the load. |
| US09628031B2 |
Transformer feedback amplifier
An apparatus includes: first and second transistors, each of the first and second transistors includes a gate terminal, a source terminal, and a drain terminal; and a transformer including a primary winding and first and second secondary windings, the primary winding is coupled to a first input node configured to receive an input signal and a second input node configured to receive a potential, the first and second secondary windings are coupled to gate terminals of the first and second transistors and cross-coupled to source terminals of the first and second transistors. |
| US09628029B2 |
Systems, circuits and methods related to dynamic error vector magnitude corrections
Systems, circuits and methods related to dynamic error vector magnitude (DEVM) corrections. In some embodiments, a power amplifier (PA) system can include a PA circuit having a plurality of amplification stages, and a bias system in communication with the PA circuit and configured to provide bias signals to the amplification stages. The PA system can further include a first correction circuit configured to generate a correction current that results in an adjusted bias signal for a selected amplification stage, with the adjusted bias signal being configured to compensate for an error vector magnitude (EVM) during a dynamic mode of operation. The PA system can further include a second correction circuit configured to change the correction current based on an operating condition associated with the PA circuit. |
| US09628027B2 |
Multi-path devices with mutual inductance compensation networks and methods thereof
The embodiments described herein provide compensation for mutual inductance in a multi-path device. In one embodiment, a device includes a multi-path integrated device. The multi-path integrated device includes a first output and a second output. The first output is configured to be coupled to a first output lead through a first bonding wire, and the second output is configured to be coupled to a second output lead through a second bonding wire. Due to their proximity, the second bonding wire has a first mutual inductance with the first bonding wire. A first compensation network is coupled to the first output, and a second compensation network is coupled to the second output. The second compensation network is configured to have a second mutual inductance with the first compensation network. The second mutual inductance at least partially cancels the effects of the first mutual inductance. |
| US09628023B2 |
Apparatus and methods for multi-mode low noise amplifiers
Apparatus and methods for multi-mode low noise amplifiers (LNAs) are provided herein. In certain configurations, a radio frequency (RF) system includes a multi-mode LNA including at least a first amplification stage and a second amplification stage electrically connected in a cascade. The RF system further includes a mode control circuit, which receives a mode selection signal and controls the biasing of the first and second amplification stages based on the mode selection signal. The mode control circuit operates the multi-mode LNA in one of a plurality of modes including both a first mode in which the LNA operates with higher gain and better noise figure and a second mode in which the LNA operates with lower gain and higher linearity. Controlling the mode of the multi-mode LNA using the mode selection signal allows the multi-mode LNA to advantageously achieve both the benefits of low noise figure and high linearity. |
| US09628021B2 |
Crystal oscillation device and semiconductor device
A wiring pattern for oscillation input signal and a wiring pattern for oscillation output signal are provided on a printed circuit board, and a wiring pattern for ground power source voltage is arranged in a region therebetween. A quartz crystal unit is connected between the wiring pattern for oscillation input signal and the wiring pattern for oscillation output signal and one ends of capacitors serving as load capacitors thereof are connected to the wiring pattern for ground power source voltage. Further, a wiring pattern for VSS is arranged so as to enclose these wiring patterns, and a wiring pattern for VSS is arranged also in a lower layer in addition thereto. By this means, reduction of a parasitic capacitance between an XIN node and an XOUT node, improvement in noise tolerance of these nodes and others can be achieved. |
| US09628016B2 |
Electrical apparatus and control system
In a system that receives power from an electric power grid, a variable frequency AC drive has an output connected to an AC electric motor, and an input connected to the power grid. The motor is in 1 connection with a load, and the AC drive includes an active converter having a predetermined maximum apparent power capacity. The converter is coupled to a controller programmed to regulate reactive power generation and consumption of the variable frequency AC drive so that the drive produces reactive power when the converter is utilizing less than its maximum apparent power capacity. This reactive power is fed to the power grid. A device monitors current and voltage in the power grid and calculates power factor, which is then used as a feedback to an external controller that generates a reactive power reference signal intended to control the system's power factor. The controller is programmed to respond to the signal, controlling power generation and consumption so that the combination of reactive power and real power does not result in apparent power exceeding the maximum capacity of the active converter and avoids generating reactive power that would result in a leading power factor for the system. |
| US09628011B2 |
Engine speed control via alternator load shedding
Method and systems are provided for adjusting an engine load exerted on a vehicle engine by an alternator mechanically coupled to said engine. In one example, a method may include when decelerating a vehicle driven by an engine, recharging a battery by an alternator driven by said engine, and during engine idle speed control, when engine speed is less than desired, in a first mode reducing electrical power to selected devices, and in a second mode offsetting a set point of desired engine ignition timing to a new set point when engine speed is higher than desired. |
| US09628010B2 |
Power distribution systems comprising variable frequency AC generator
A power distribution system is described that does not rely on a fixed frequency and which therefore allows prime movers to run at different speeds in response to load demand, typically so that fuel consumption and/or harmful exhaust emissions is/are minimised. A marine power distribution and propulsion system can include an ac busbar adapted to carry a variable-frequency ac distribution voltage. A plurality of ac generators are connected to the busbar, each having an associated prime mover such as a diesel engine, turbine etc. A power management controller is adapted to vary the rotational speed of the prime movers with reference to the electrical load on the ac busbar such that the generators provide a variable frequency output during normal operation of the power distribution system. Such operation is to be contrasted with conventional distribution systems which have a fixed frequency. |
| US09628001B2 |
Method and apparatus for measurement and control of linear actuator
An apparatus for controlling force of a magnetic lead screw actuator includes a magnetic lead screw actuator, an external control module and at least one sensor device integrated within the magnetic lead screw actuator. The magnetic lead screw actuator includes an electric machine, a rotor, and a translator. The rotor includes a rotor magnet assembly forming first helical magnetic threads along the rotor and the translator includes a translator magnet assembly forming second helical magnetic threads along the translator. Rotation of the rotor by the electric machine effects linear translation of the translator by interaction of the first and second helical magnetic threads. The external control module is electrically operatively coupled to an electric machine controller of the magnetic lead screw actuator. The at least one sensor device integrated within the magnetic lead screw actuator is configured to measure a parameter indicative of a relative displacement between the rotor and the translator and this parameter is provided as feedback to the electric machine controller. |
| US09627999B2 |
Power supply device
A power supply device for supplying power to a load by combining a secondary battery and a capacitor includes a bypass switch which enables power to be directly supplied to the load from the capacitor by being switched to a connected state when a voltage of the capacitor is a voltage capable of driving the load, and a first DC-DC converter which enables the voltage of the capacitor to be stepped up and supplied to the load when the voltage of the capacitor drops below a minimum voltage capable of driving the load. |
| US09627995B2 |
Inverter device with a control unit
An inverter device includes: a step-up circuit; an inverter circuit; a control unit for controlling the step-up circuit and the inverter circuit; and a reactor provided on an electric path for outputting the converted AC power to an AC system. An output current target value is calculated based on an input power value of DC power and a voltage value of the AC system, and a current target value and a voltage target value for the inverter circuit are calculated based on the output current target value, to control the inverter circuit. A current target value for the step-up circuit is calculated based on a current target value and a voltage target value that are common with the inverter circuit, and on a DC input voltage value, to control the step-up circuit. Thereby, output of the AC power is controlled. |
| US09627991B2 |
Rectifier with indicator switch
This relates to a rectifier with indicator switch circuit that may be used in a power conversion system. The rectifier with indicator switch circuit may be configured to rectify an ac line voltage and output an indicator signal that is representative of a fault condition in the ac line voltage. The rectifier with indicator switch circuit may include a storage capacitor configured to be charged by the ac line voltage during a first half-cycle of the ac line voltage and a detection capacitor configured to be charged by the storage capacitor during a second half-cycle of the ac line voltage. A switch coupled to the detection capacitor may be configured to generate the indicator signal based on a voltage across the detection capacitor. The indicator signal may be provided to a controller to disable operation of the power conversion system in response to the detection of a fault condition. |
| US09627990B2 |
Non-isolated symmetric self-coupling 18-pulse rectifier power supply system
A non-isolated symmetric self-coupling 18-pulse rectifier power supply system comprises a phase-shifting autotransformer, three circuits of output devices, a time sequence controller and a power output end. The phase-shifting autotransformer is provided with three groups of output ends and one group of input ends, and the output device in each circuit comprises a zero-sequence suppression reversing inductor, a three-phase uncontrolled rectifier bridge and a bidirectional switch BUCK converter, which are connected to each other in turn. The time sequence controller is provided with three groups of control ends which are respectively connected to the control end of the bidirectional switch BUCK converter in each circuit. The output end of the bidirectional switch buck converter in each circuit is connected to the power output end. |
| US09627985B2 |
Power converter output voltage clamp and supply terminal
A secondary control circuit includes a voltage regulator circuit coupled to an output of the power converter to provide a regulated power supply. One or more switched loads are coupled between a first terminal and an output ground terminal. The first terminal is coupled to the output of the power converter. Each switched load is coupled to draw a respective current from a load current to clamp the output of a power converter. One or more comparator circuits are coupled to a second terminal. The second terminal is coupled to receive an output sense signal. Each comparator circuit is coupled to receive a reference signal that is a scaled representation of a first reference signal. Each switched load is switched in response to a respective comparator circuit to draw a respective current from the load current of the power converter to clamp the output of the power converter. |
| US09627971B2 |
Gate driver initiated zero voltage switch turn on
Devices, systems, and methods for monitoring overcurrent and zero voltage are disclosed. These devices, systems, and methods monitor an input/output pin of an electronic device to determine a period of time when monitoring for an overcurrent of the input/output pin of the electronic device is not performed and compare a first input voltage to a first reference voltage during the period of time when monitoring for the overcurrent of the input/output pin of the electronic device is not performed so as to determine when a diode is conducting current, the diode being located across a switch being monitored for a zero voltage state, wherein the diode conducting current indicates that the switch is at the zero voltage state. |
| US09627968B2 |
Step-down chopper type switching power-supply device
A step-down chopper type switching power-supply device includes a step-down chopper circuit including an inductor connected to a switching element connected to a DC power source, a regenerative-voltage detecting circuit, a control circuit controlling the switching element such that regenerative voltage becomes a reference voltage, an auxiliary power supply circuit charging a capacitor by using the regenerative voltage and supplying the voltage of the capacitor as power-supply voltage to the control circuit, and a activation circuit stopping supply of current to the capacitor after activation of the auxiliary power supply circuit, wherein, after activation of the auxiliary power supply circuit, in a case where voltage supplied from the DC power source is equal to or less than a first threshold value, the activation circuit performs control by the voltage supplied from the DC power source, such that current is supplied to the capacitor. |
| US09627964B1 |
Systems and methods for recovering voltage beyond device limits
A voltage recovery circuit in an integrated circuit is provided. The voltage recovery circuit includes a bootstrap circuit coupled to a cascode switch circuit. The bootstrap circuit includes a first transistor coupled in series to a second transistor, a resistive element is coupled between the second transistor and an output of the voltage recovery circuit, and a capacitive element is coupled between control electrodes of the first and second transistors and the output. The cascode switch circuit includes a third and fourth transistor coupled in series. The third transistor includes a current electrode coupled to receive a first input voltage, and a control electrode coupled to the control electrodes of the first and second transistors. The fourth transistor includes a current electrode coupled to the output, and a control electrode coupled to a current electrode of the second transistor and a terminal of the resistive element. |
| US09627962B2 |
Fast blocking switch
A fast blocking switch includes, for example, an energy storage device, a first power switch and a second power switch. The energy storage device stores a charge for fast activation of the switches. The first switch is operable for coupling input current to an output terminal in response to the coupling of a potential supplied by the stored charge to a control terminal of the first switch. The second switch is operable for coupling a limited amount of the input current to the output terminal in response to the coupling of a potential supplied by the stored charge to a control terminal of the second switch. |
| US09627959B2 |
Switch power converter and frequency response characteristic testing and adjusting method thereof
A switch power converter and method of testing and adjusting is provided. A switch power unit comprises at least a power switch for transform of the power. A controller is configured to generate a control signal for the power switch. A detector is configured to detect an output voltage signal and/or an output current signal of the switch power unit and output a sampling signal. A testing and adjusting unit is configured to receive the sampling signal and output a testing signal to the controller. The testing and adjusting unit comprises a compensator. The compensator attends the testing and adjusting of the switch power converter. An AC disturbing signal various in frequency causes the difference in the sampling signal and the testing signal so as to test open-loop transfer function of the switch power converter, the compensator compensates frequency response characteristic of the switch power converter, when the frequency response characteristic of the switch power converter doesn't match a target frequency response characteristic. |
| US09627952B2 |
Pendulum apparatus having a sustained swing
An apparatus (100), including: a pendulum (102) having a pendulum magnet arrangement; a stationary magnet (118, 122) positioned such that a magnetic field of the stationary magnet repels the pendulum magnet as it approaches the stationary magnet; a magnetic shielding apparatus (126, 128) configured to intermittently shield the stationary magnet from the pendulum magnet; and a power source configured to supply power to the magnetic shielding apparatus. The magnetic shielding apparatus is configured to shield the stationary magnet from the pendulum magnet as the pendulum magnet approaches an apex position (16, 42) of a cycle. As the pendulum, magnet arrangement recedes from the apex position a repulsion associated with an interaction of a fully unshielded magnetic field of the stationary magnet and a magnetic field of the pendulum magnet arrangement is effective to accelerate the pendulum. |
| US09627944B2 |
Electric drive apparatus
Provided is an electric drive apparatus in which a detected portion (10) of a rotation angle sensor is disposed at an end of a shaft (7) of a motor, and a sensor portion (300) as a detection portion of the rotation angle sensor is disposed coaxially with the rotating axis of the shaft. In a control unit (200), an inverter circuit portion with a drive element (SW) for driving the motor, and a control substrate (17) which is separate from the sensor portion and controls the output of the inverter circuit portion are disposed. The sensor portion and the control substrate are electrically connected, with the control substrate disposed along a plane perpendicular to the rotating axis of the shaft. |
| US09627943B2 |
Motor cooling structure and motor
A motor cooling structure for cooling a motor, which includes a shaft transmitting power and a rotor core attached to an outside of the shaft, by a cooling medium, includes: a cooling medium supply passage that extends to an inside of the shaft in an axial direction of the shaft and passes the cooling medium through the cooling medium supply passage; and a plurality of cooling medium passages that are branched from the cooling medium supply passage to cool the rotor core while flowing the cooling medium without branching the cooling medium in the axial direction and then eject the cooling medium from a plurality of ejection holes opened to a surface of the rotor core, wherein distances from a cooling medium inlet, through which the cooling medium flows into the cooling medium supply passage, to the respective ejection holes are equal between the plurality of cooling medium passages. |
| US09627934B2 |
Rotor windings for DC motor
A commutated DC motor (10) includes a stator (12) and a rotor (14) mounted in the stator (12). The stator (12) has 2P magnetic poles, wherein P is an integer greater than 1. The rotor (14) includes a rotor shaft (81) with a rotor core (85), and a commutator (83) fixed thereto. The rotor core (85) has multiple teeth defining m×P slots therebetween, wherein m is an odd integer greater than 1. The commutator (83) has k×m×P segments, wherein k is 1 or 2. A rotor winding (87) formed by winding a single continuous wire is received in the slots of the rotor core (85) and connected to the segments of the commutator (83), and has k×m winding units. Each winding unit includes P coils in series connection and is directly connected to only two segments. |
| US09627933B2 |
Brushless motor
A brushless motor includes a stator comprising a stator core with teeth protruding inwardly and windings wound on the teeth, and a rotor comprising a shaft, a rotor core fixed to the shaft, and a ring magnet fixed to the circumferential outer surface of the rotor core. The ring magnet includes a plurality of magnetic poles radially magnetized so that north poles and south poles are arranged alternately in the circumferential direction, boundary lines between adjacent magnetic poles being skewed by an angle α relative to an axis of the shaft. A plurality of grooves are formed in a circumferential outer surface of the rotor core. Each groove extends from one axial end to the other axial end of the rotor core, has a circumferential width smaller than each of the magnetic poles, and is covered by the ring magnet with a void formed between the groove and the ring magnet. |
| US09627932B2 |
Stator assembly with magmate holder
Disclosed therein is a stator assembly, which includes a circular base part and a stator core having a plurality of teeth radially formed on an outer face of the base part and respectively having a tooth end portion. The stator assembly further includes: a magmate holder including a base plate, at least one inner leg and at least one outer leg formed at a lower portion of the base plate, and a power connector part formed on an upper portion of the base plate and having a joining projection formed at one side thereof; and a sensor cover including a body part and a hook formed on a lower portion of the body part and being joined with the joining projection. |
| US09627931B2 |
Power feeding apparatus and power feeding system
According to the present embodiment, the power feeding apparatus configured to feed power by electric field coupling to a power receiving apparatus having a first and a second electrodes for receiving power arranged along a mounting surface and a protrusion arranged on the mounting surface side includes a power feeder divided into a plurality of small regions having a small electrode respectively, the power receiving apparatus being mounted on the small regions, and a control module configured to supply power to the small electrodes corresponding to the first and second electrodes, wherein the small region in contact with the protrusion sinks when the power receiving apparatus is mounted, and the small region returns to an original position when the power receiving apparatus is removed. |
| US09627928B2 |
Electrical outlet having wireless control capabilities
A line-in power is connectable to the disclosed outlet housing similar to any known power outlet. This provided power is used to drive an AC/DC converter to create a DC bus internal to the outlet housing. This DC bus powers the electronics, including, for example, a wireless transceiver incorporated within the outlet housing. In at least one instance, the wireless transceiver will receive a command from another wireless device to turn power ON or OFF to the local outlet and the downstream (e.g. daisychained, etc.) outlets. These outlets can be wired to the output terminations (push-in and/or other) on the back of the local outlet and/or outlet housing, or may be connected through any other suitable electrical connection. |
| US09627922B2 |
Active load circuit
An active load circuit applicable to a power supply. The active load circuit includes a control circuit, a dummy load and an active switching circuit. The control circuit is coupled to a ground terminal, an output terminal of a power supply and the detection circuit. The dummy load is coupled to the output terminal The active switching circuit is coupled to the control circuit, the dummy load and the ground terminal. The control circuit receives an output voltage via the output terminal and receives a power-good input signal via the detection circuit. When a voltage level of the power-good input signal is lower than a threshold value, the control circuit controls the active switching circuit to enter a load-on mode so that the dummy load is connected to the ground terminal and that the output terminal is connected to the dummy load. |
| US09627920B2 |
Battery pack and charging method thereof
A charging method of a battery and a battery pack thereof are described. A fully charged amount of the battery cell is changed upon comparing the charge amount of the battery to a reference capacity. If the battery cell is fully charged, charging of the battery cell may be interrupted and a counter incremented. The charged amount of the battery cell is compared to a reference capacity, and if the charged amount of the battery cell is equal to the first reference capacity, the fully charged amount of the battery cell may be set to another reference capacity, and the battery discharged the battery cell down to the new reference capacity. |
| US09627916B2 |
Electronic card with a charging mechanism
An electronic card including an antenna, a chip, a charging circuit and a battery is provided. The antenna receives an external electric signal, and the chip is coupled to the antenna, so as to receive the external electric signal and provide a demodulated electric signal. The charging circuit is coupled to the chip, receives the demodulated electric signal and converts the demodulated electric signal to generate a charging power. The battery is coupled to the charging circuit, wherein, the charging circuit provides the charging power to the battery according to a residual electricity of the battery, so as to charge the battery. |
| US09627910B2 |
Peak-cut control device
A peak-cut control device is provided with a storage battery having a power generation device and a storage battery for charging/discharging a part of power generated by the power generation device. The peak-cut control device includes a difference power calculating section that calculates differential power between a planned power generation amount in the power generation device determined based on a temporary peak cut amount and a demand prediction power amount that predicts a power demand for each predetermined time, and also includes a peak-cut amount calculating section that compares the calculated differential power with chargeable power or dischargeable power per unit time of the storage battery every predetermined time and simulating charge/discharge of the difference power to/from the storage battery and an increase/decrease in the temporary peak-cut amount. |
| US09627908B2 |
Ultracapacitor and battery combination with electronic management system
This disclosure provides systems, methods and apparatus for a combined battery/capacitor energy storage device. The device includes a first device terminal, a second device terminal, a battery connected between the first terminal and the second terminal, and a capacitor connected in parallel with the battery. In one aspect, a rectifier is connected between the first terminal and the capacitor, the rectifier configured to allow substantially unidirectional current flow from the first terminal to the capacitor. In another aspect, a switch is between the capacitor and the first terminal. In another aspect, a current limiter extends between the first terminal and the capacitor. |
| US09627907B2 |
Storage battery control device, storage battery control method, program, electricity storage system, and power supply system
The present disclosure relates to a storage battery control device that can exert better performance in a configuration in which a plurality of storage batteries are connected, a storage battery control method, a program, an electricity storage system, and a power supply system. A charge order table previously set according to a state of charge and a charge/discharge frequency of a storage battery that stores power is referred to, and based on the states of charge and the charge/discharge frequencies acquired from the storage battery provided in plural, a discharge order based on which discharge is preferentially performed with respect to the plurality of storage batteries is decided. In order to supply necessary power necessary to be output upon a request from a load, discharge power output from each of the plurality of storage batteries is set based on the decided discharge order. |
| US09627898B2 |
Device and method for transmitting energy and data between a control unit and a position-measuring device
In a device and a method for transmitting energy and data between a control unit and a position-measuring device via a line pair, the energy transmission takes place in a charge mode and the data transmission takes place in a communication mode, and an energy storage device is provided in the position-measuring device, which is able to be charged in the charge mode via the line pair, and which is able to supply energy to the position-measuring device in the communication mode, and a charge unit and a switching device are provided in the control unit. The switching unit is adapted to the charge unit to the line pair in two-pole manner. |
| US09627896B2 |
Battery system including a voltage detecting circuit for detecting voltages of plural battery cells through voltage detecting lines having different lengths
A battery system comprises plural battery cells, a voltage detecting circuit detecting voltage of each of the battery cells, and plural voltage detecting lines connecting an electrode terminal of each of the battery cells to input side of the voltage detecting circuit, and the voltage detecting circuit detects the voltage of each of the battery cells through the voltage detecting lines. The voltage detecting lines have different lengths, and at least one of the voltage detecting lines has a resistance adjusting portion which equalizes electrical resistances of the long voltage detecting line and the short voltage detecting line, and through the plural voltage detecting lines of which electrical resistances are equalized by the resistance adjusting portion, the voltage detecting circuit detects the voltage of each of the battery cells. |
| US09627891B2 |
Power supply system
There is provided a power supply system in which a user can easily determine an optimum method of consuming power obtained by discharging a power storage portion. The power supply system (1) includes: a power storage portion (11) that supplies a power by discharge; a dischargeable time prediction portion (55) that predicts, when a power is supplied to a predetermined load among a plurality of loads included in the load portion (31), a dischargeable time that is a time period in which the power storage portion (11) can perform discharge; and a notification portion (70) that notifies a user of the dischargeable time predicted by the dischargeable time prediction portion (55). The dischargeable time prediction portion (55) predicts a plurality of dischargeable times in which combinations of loads receiving power supply are different and the notification portion (70) notifies the dischargeable times. |
| US09627889B2 |
High voltage energy harvesting and conversion renewable energy utility size electric power systems and visual monitoring and control systems
A renewable energy, utility-size electric power system is provided with a high voltage, renewable energy harvesting network connected by a direct current link to a centralized grid synchronized multiphase regulated current source inverter system. The harvesting network includes distributed renewable energy power optimizers and transmitters that control delivery of renewable energy to the grid synchronized multiphase regulated current source inverter system. A visual immersion monitoring and control system can be provided for a three dimensional, visually oriented, virtual reality display, and command and control environment. |
| US09627888B2 |
Electrical power distribution device having a current display
An electrical power distribution unit can include a power distribution unit enclosure, a power input associated with the power distribution unit enclosure, and a plurality of power outputs associated with the power distribution unit enclosure. At least certain power outputs can be connectable to one or more electrical loads external to the power distribution unit enclosure and to the power input. In some embodiments, an intelligent power section can communicate with at least one of the power outputs and can connect to a communications network external to the power distribution unit enclosure. |
| US09627886B2 |
State estimation for power system using hybrid measurements
A method determines voltages of buses of a power system. Values the voltages include a magnitude and a phase angle. The buses of the power system are grouped in a first area and a second area based on a type of measurement associated with each bus. The first area and the second area have at least one common bus, and wherein at least one bus in the first area is associated with a first type of measurement, and at least one bus in the second area is associated with a second type of measurement. Next, the method determines sequentially voltages of the buses of the first and the second areas. |
| US09627882B2 |
Serial capacitance tuner
An impedance matching network comprises a first signal terminal configured to receive a signal from a source circuit and a second signal terminal configured to provide the signal to a load circuit. The network further comprises a series branch comprising a variable capacitive component between the first signal terminal and the second signal terminal. The variable capacitive component comprises a plurality of capacitive portions connected in series, wherein at least one of the capacitive portions comprises a switching element comprising a stack of series connected transistors. The impedance matching network also comprises a control component configured to control a capacitance of the variable capacitive component by controlling the at least one of the capacitive portions based on a predetermined algorithm. |
| US09627877B2 |
Control system and method for nuclear power facility
A nuclear power control system includes: a safety protection apparatus which outputs a first safety mode operating signal while outputting a first unsafety mode operating signal; a CCF apparatus that outputs a second safety mode operating signal; and a signal input/output circuit that is connected to the safety protection apparatus and the CCF apparatus. The signal input/output circuit includes an OR circuit that outputs a third safety mode operating signal based on the presence or absence of an input of the first safety mode operating signal and the second safety mode operating signal; a NOT circuit that is connected to the output side of the OR circuit; and an AND circuit that outputs a third unsafety mode operating signal, and the presence and absence of an input of a first unsafety mode operating signal. |
| US09627874B2 |
Mounting device and method of assembling the same
A method and a system for a mounting device are provided. The mounting device includes at least two shells, each shell having an inner surface and an outer surface wherein the outer surface includes a first banding zone, a second banding zone, and a clamping zone extending between the first banding zone and the second banding zone and a pair of shoulders bounding each of the first banding zone and second banding zone. The mounting device also includes an intermediary material circumscribing the wire bundle including at least one of a substantially non-porous material, a vulcanizing tape, and a silicone material. The mounting device further includes at least one fastener configured to engage the first banding zone or second banding zone to couple the first shell and the second shell to the wire bundle and the intermediary material. |
| US09627868B2 |
Backless electrical box and method of making
A backless electrical box is formed out of a single piece of material, with a front and sides of the box being parts of the same single piece of material. The front of the box has an integrally-formed mud ring that extends forward from a front base of the front. The sides are made out of material bent back from two opposite edges of the front base, bent around to form the four sides. Some or all of the sides may have seams in them, which may be secured by portions of material overlapping along some or all of the height of the sides, riveted or otherwise attached together. Mounting flanges may extend from the other two opposite edges of the front base. Tabs bent downward from the mounting flanges may be used to cover holes in the sides that extend rearward from these two other opposite edges. |
| US09627867B2 |
Mounting brace assembly for mounting an electrical box
A brace assembly is provided having a brace for mounting to a support and a hanger member. The hanger member is coupled to the brace by a bar positioned in a longitudinal slot in the bottom side of the brace. The bar enables the hanger member to slide along the length of the brace. The hanger member has a bottom wall and side walls with a top end for coupling to a support. A mounting bracket is removably coupled to the hanger member for supporting the brace. |
| US09627866B2 |
Door mounted vent flap structure for arc-resistant compartment
A door for an arc-resistant compartment includes an opening there-through. Flap structure includes a flap member coupled to the door and movable between an opened position permitting air to pass through the opening, and a closed position covering the opening. Spring structure is engaged with the flap member to bias the flap member to the closed position. Handle structure is coupled to the flap member and extends through the door for moving the flap member to the opened position against the bias of the spring structure. Retaining structure provides a retaining force on the flap member to retain the flap member in the open position, against the bias of the spring structure. During an arcing event in the compartment, pressure within the compartment together with the bias of the spring structure overcomes the retaining force to automatically move the flap member to the closed position. |
| US09627863B1 |
Electrical panel barricade
The electrical panel barricade is a three sided cabinet that prevents unauthorized access to electrical panels that are uncovered for maintenance purposes. The electrical panel barricade is attached directly to the uncovered electrical panel using two adjustable clamping bars. The electrical panel barricade can be installed to protect an uncovered electrical panel that needs to be left unattended. The electrical panel barricade can be installed as a temporary closure to accommodate electrical testing equipment that may not fit into the original electrical panel. The electrical panel barricade comprises a door, a left panel, a right panel, a left locking wing, a right locking wing, a top member, and a bottom member. |
| US09627862B2 |
Methods and systems for subsea direct current power distribution
A submersible power system includes at least one DC power source and at least one submersible power distribution system electrically coupled to the at least one DC power source. The at least one submersible power distribution system includes at least one receptacle configured to be exposed to an underwater environment. The at least one submersible power distribution system also includes a plurality of power conversion modules removably positioned within the at least one receptacle. Each power conversion module of the plurality of power conversion modules includes an enclosure configured to be exposed to the underwater environment. The at least one submersible power distribution system further includes at least one switchyard module selectably coupled to and uncoupled from the plurality of power conversion modules. The at least one switchyard module includes a plurality of switches configured to electrically bypass and isolate each power conversion module from the DC power source. |
| US09627858B2 |
Observation plug and spark observation system
An observation plug 102 includes a spark plug body 50, an objective optical system 10, and a set of light conduction paths 16. The spark plug body 50 ignites gas in a combustion chamber by an electric discharge in a discharge gap 60, and has an observation hole 4 penetrating in an axial direction at a location dislocated from the discharge gap 60. The objective optical system 10, which is provided in the observation hole 4 to be exposed into the combustion chamber, bends a course of light received from an incident surface 10a facing toward the discharge gap included in an observation area, and forms an image of the observation area within the observation hole 4. The set of light conduction paths 16 is provided in the observation hole 4, and divides the image of the observation area into a plurality of portions to be transmitted therethrough. |
| US09627850B2 |
Two-dimensional photonic crystal surface-emitting laser
A two-dimensional photonic crystal surface emitting laser has a laminated structure including: a two-dimensional photonic crystal (2DPC) layer in which refractive index distribution is formed by two-dimensionally arranging air holes in a plate-shaped base member; and an active layer for generating light with wavelength λL by receiving an injection of electric current. The two-dimensional photonic crystal surface emitting laser emits a laser beam in the direction of an inclination angle θ from normal to the 2DPC layer. |
| US09627847B2 |
Wavelength-tunable laser
The present invention relates to a wavelength-tunable laser, which can tune an oscillating laser wavelength and can be manufactured in a small size, comprising: a laser diode chip (100) for emitting a laser beam; a partial reflection mirror (500) for optical feedback, which partially reflects the beam emitted from the laser diode chip (100) so as to enable the reflected beam to be fed back to the laser diode chip (100); a collimation lens (200) provided on an optical path between the laser diode chip (100) and the partial reflection mirror (500) for optical feedback so as to collimate the beam emitted from the laser diode chip (100); a wavelength-tunable selective filter (300) for converting the wavelength transmitted according to the temperature; a phase compensator (350) of which a refractive index is changed according to the temperature and which offsets a change in the refractive index according to the temperature of the semiconductor laser diode chip (100) or the wavelength-tunable selective filter (300); and a 45 degree reflection mirror (400) for switching the direction of the laser beam from the laser beam traveling in the horizontal direction with respect to a bottom surface of a package, to the laser beam traveling in the vertical direction with respect to the bottom surface of the package, wherein the laser diode chip (100), the wavelength-tunable selective filter (300), and the phase compensator (350) are disposed at an upper part of a thermoelectric element (900) so as to change the wavelength oscillating according to a change in the temperature of the thermoelectric element (900). |
| US09627846B2 |
Light-emitting element module, quantum interference apparatus, atomic oscillator, electronic apparatus and moving object
A light-emitting element module includes a temperature adjustment element, a light-emitting element arranged on a temperature adjustment surface of the temperature adjustment element, a metal layer arranged on the temperature adjustment surface, a relay member arranged on the temperature adjustment surface through the metal layer, a wiring layer arranged on a surface of the relay member at an opposite side to the temperature adjustment surface, a wiring to electrically connect the light-emitting element and the wiring layer, and a wiring to electrically connect a connection electrode and the wiring layer. The wiring layer has an area smaller than an area of a region where the metal layer overlaps the relay member in a plan view. |
| US09627843B2 |
Method and laser pulse source apparatus for generating fs laser pulses
A method of generating fs laser pulses (1), includes steps of creating a circulating light field in a resonator cavity (10) with multiple resonator mirrors (11-18) by pumping at least one gain medium (21, 22) included in the resonator cavity (10), and passing the circulating light field through a first Kerr medium (31) included in the resonator cavity (10), so that the fs laser pulses (1) are formed by self-amplitude modulation of the circulating light field, wherein the resonator cavity (10) includes at least one supplementary Kerr medium (32-36) enhancing the self-amplitude modulation of the circulating light field, and each of the first Kerr medium (31) and the at least one supplementary Kerr medium (32-36) provide different non-linear Kerr lens contributions to the self-amplitude modulation of the circulating light field. Laser pulse source apparatus (100) for generating fs laser pulses (1) is also described. |
| US09627842B2 |
Optical amplifier arrangement
The present invention relates to an optical amplifier arrangement and a method of amplifying an optical signal. The optical amplifier arrangement (20) comprises an optical dividing device (21) arranged to divide an optical input pulse into a plurality of non-overlapping pulses forming a pulse train, an optical amplifier (22) arranged to amplify the pulse train, and an optical aligning display (23) arranged to temporally align the plurality of amplified pulses in the amplified pulse train into a single output pulse having the same temporal width as the input pulse. |
| US09627833B2 |
Electrical leads for a feedthrough
A lead frame for attaching leads to a hermetic feedthrough includes a cross-member and a plurality of leads. Each of the leads has an elongate body extending from the cross-member in a direction substantially parallel with one another, and each lead includes at least one of a notch on an end thereof opposite to the cross-member or a hole proximate to the end. |
| US09627832B2 |
Lock member for a rotary connector device
A lock member for a rotary connector device includes a ring portion defining an aperture. Also included is a first leg. Further included is a second leg, wherein the lock member is moveable between a first configuration and a second configuration, the first configuration comprising the first leg disposed within a slot of a rotating member of the rotary connector device and the second leg disposed within a pocket of a fixed member of the rotary connector device, the second configuration comprising the second leg disposed within the slot of the rotating member and the first leg disposed within the pocket of the fixed member. |
| US09627830B1 |
Receptacle compatible with multiple types of lamp sockets
A lighting system can comprise a receptacle for mounting and supplying electricity to a lamp. The receptacle can be compatible with multiple types of lamp sockets. For example, the receptacle can be compatible with two types of lamp sockets that utilize spring force for socket retention in the receptacle. In one such lamp socket type, a spring clip retains the lamp socket in the receptacle utilizing outward spring force. In another such lamp socket type, a spring clip retains the lamp socket in the receptacle utilizing inward spring force. |
| US09627828B2 |
High outlet density power distribution unit
A power distribution unit including a housing having a front face and at least one housing aperture formed therethrough. A power input is coupled with the housing and connectable to an external power source. At least one molded multi receptacle module is located at least partially within the housing. The molded multi receptacle module includes a recessed surface and a plurality of outlet cores extending from the recessed surface toward the housing aperture. The outlet cores include an unobstructed space between adjacent pairs of the outlet cores and each outlet core includes at least two aligned power-connection elements. |
| US09627827B2 |
Communication outlet with shutter mechanism and wire manager
A communication connector with a housing door pivotably coupled to a housing. The housing door is rotatable with respect to the housing between open and closed positions. The housing door is configured to be electrically connected to at least one grounding component of a cable. The housing has a door gripping portion. One of the housing door and the door gripping portion has a projection configured to engage another one of the housing door and the door gripping portion when the housing door is in the closed position. When so engaged, the projection is configured to electrically connect the housing door with the housing to thereby electrically connect the at least one grounding component with the housing. |
| US09627825B2 |
Large current female connector for high-speed transmission
Provided is a large current female connector for high-speed transmission, comprising a case, an insulating body, and an upper terminal group and a lower terminal group disposed in the insulating body. The insulating body is disposed in the case. A power terminal in the upper terminal group and a corresponding power terminal in the lower terminal group are connected to form a big power terminal. An insulating body trench for accommodating the big power terminal is disposed on the insulating body. The present invention has advantages in that the fabrication process is simple and cost effective, and a large current transport is possible. |
| US09627824B2 |
Electrical connector and retaining device
An electrical connector has a body, with an input part forming passages for corresponding electrical cables, and a base from which two stems project. The connector is associated with a retaining device including a base plate from which two facing sprung retaining elements extend. A retaining region adapted to receive the input part of the connector is formed between these elements. The retaining elements have retaining formations capable of being spread apart by the input part of the connector when it is inserted into the retaining region, and of retaining the input part in the retaining region thereafter. A pair of openings is formed in the base plate between the sprung elements, into which the stems of the base of the connector are insertable. |
| US09627821B1 |
Power connector having a transparent observation portion to view the status of a contact limiting member
A power connector having an observation portion includes a housing, a live wire conductive member, a live wire contact plate and a neutral wire conductive member. The live wire contact plate has an elastic force to move away from the live wire conductive member. The live wire conductive member and the live wire contact plate contact with each other by a first limiting element damaged at a temperature of 80°˜299° C., separating the live wire contact plate from the live wire conductive member by that elastic force. The housing includes a transparent observation portion, allowing a user to see through partial or whole part of the first limiting element, of the live wire conductive member and of the live wire contact plate, enabling the observation of whether the live wire conductive member and the live wire contact plate are limited by the first limiting element to remain contacted. |
| US09627812B2 |
USB plug capable of being inserted face up and face down
An USB plug capable of being inserted face up and face down includes a metal shell, an insulating body and conductive terminals arranged in the metal shell. The front end of the insulating body protrudes and is provided with an insertion core. The upper face and the lower face of the insertion core are respectively provided with a set of conductive terminals. Each of the conductive terminals on the upper face of the insertion core in a sequence from left to right is connected with the corresponding one of the conductive terminals on the down side of the insertion core in a sequence from right to left one by one. Both the up side and the down side of the insertion core of the USB plug can be electrically connected, so that the plug can be electrically connected effectively when being inserted in a socket either face up or face down. |
| US09627811B2 |
Locking mechanism for cables and connectors in hazardous locations
This technology includes a device designed to retain a cable or cable connector when connected to a receptacle. The device is composed of a base bracket that interfaces with a receptacle or receptacle housing and cable bracket that interfaces with a cable or cable connector. A tool may be required to disconnect the brackets or free the cable from the receptacle. |
| US09627807B2 |
Remote radio unit, and cable connector assembly and housing of the same
A cable connector assembly includes a connecting frame, wherein an opening through which a cable penetrates is formed at an end of the connecting frame, a cable support connected to another end of the connecting frame and supporting the cable, a first locking part including a fixed end fixed to a first side of the connecting frame and a free end that is movable about the fixed end, a second locking part including a fixed end fixed to a second side of the connecting frame opposite to the first side of the connecting frame, and a free end that is movable about the fixed end, and a sealing portion surrounding the connecting frame and being elastic deformable. |
| US09627806B2 |
Insulative housing of a cable connector assembly having a one piece structure latch
A cable connector assembly includes an insulative housing, a spacer mounted at a rear of the insulative housing, and an outer boot enclosing the spacer and a part of the insulative housing. The insulative housing includes a top wall, a bottom wall, and a pair of side walls connecting the top wall and the bottom wall. The insulative housing includes a pair of latches extending rearwardly from the side walls respectively. Each of the latches has a one piece flat structure and comprises a lock part projecting outwardly from a free end thereof, and the spacer defines a pair of holes corresponding to the latches, the latches passing through the holes to fix the spacer on the insulative housing. |
| US09627797B2 |
Ejection assembly with plug feature
Disclosed herein is a plug feature for an electronic device. More specifically, the plug feature described herein is used to plug, fill or otherwise seal an aperture associated with a SIM tray of an electronic device. The plug feature may be coupled to an ejection mechanism and may extend at least partially into an aperture defined by the SIM tray and/or an aperture defined by the housing of the electronic device. |
| US09627795B2 |
Electrical connecting assemblies, and related methods
An assembly for electrically connecting at least two wires is provided. The assembly includes a body configured to receive a connector therein for electrically connecting at least two wires, and a retainer configured to releasably couple to the body. The retainer has at least one arm configured to extend into the body, when the retainer is coupled to the body, and inhibit movement of the connector out of the body after the connector is received in the body. Methods of making an electrical connection using an electrical connecting assembly are also disclosed. |
| US09627791B2 |
Connector apparatus
A connector apparatus which can keep an electrical connection between signal pins in good condition; when a male member and female member are coupled together, first bumps of a first contact portion and second bumps of a second contact portion are brought into contact with each other, electrically connecting the first signal pins and second signal pins with each other. Measures are taken to bring tops and ridge lines of the second bumps into contact with lateral faces of the first bumps. Also, the first signal pins and second signal pins are configured to be pivotable. During connection, contact area is increased by contact between the lateral faces of the first bumps and the tops and ridge lines of the second bumps, causing rubbing between the lateral faces and the tops and ridge lines, and thereby pushing aside and rubbing off sticking spatter, oxide films, contamination, and the like. |
| US09627790B2 |
Electrical contact including corrosion-resistant coating
In accordance with one embodiment, an electrical contact has a mating end and a mounting end. The electrical contact includes an electrically conductive base, and a multi-layered coating disposed on an outer surface of the base at the mating end. The multi-layered coating can include a metallic layer of a noble metal or alloy thereof, a layer of anti-tarnish material disposed on the metallic layer, and a lubricant layer disposed on the layer of anti-tarnish material, the lubricant effective to seal at least some wear regions created in the layer of anti-tarnish material due to micromotion of the mating end in use. |
| US09627788B2 |
Electrical harness connector
An electrical assembly is disclosed in which two flexible printed circuits are electrically joined. This allows greater lengths of flexible printed circuits to be provided, for example for gas turbine engine harnesses. Each flexible printed circuit has a terminating region having electrically conductive through holes that are connected to respective electrical tracks of the flexible printed circuit. The terminating regions are adjacent each other in the electrical assembly, and an electrically conductive pin is passed through the aligned through holes, then permanently bonded in position, for example by welding. This results in a robust, reliable connection of two flexible printed circuits. |
| US09627787B2 |
DIMM connector region vias and routing
A dual in-line memory module (DIMM) connector system is provided. The DIMM connector system includes a motherboard, a DIMM card and a connector by which the DIMM card is coupled with the motherboard. The motherboard includes a printed circuit board (PCB) formed of a mid-loss dielectric constant material, signal pads that are thinner than ground pads, ground pads disposed proximate to signal pads, signal vias connected to distal edges of signal pads and shared antipads. The DIMM card includes a printed circuit board (PCB) formed of a mid-loss dielectric constant material, signal pads that are thinner than ground pads, signal vias connected to distal edges of signal pads and shared antipads for respective pairs of signal vias. |
| US09627784B1 |
Method and apparatus for strain relieving surface mount attached connectors
An interconnect structure that includes a component circuit board containing a plurality of electrical components, and a wafer connector assembly. The wafer connector assembly includes a plurality of interconnect circuit boards that are in electrical connection with the components circuit board through a plurality of rows of solder joints, the plurality of interconnect circuit boards having a connection end including at least one contact. An adhesive is present structurally reinforcing at least a row of the solder joints that is proximate to the connection end of the plurality of interconnect circuit boards of the wafer assembly. |
| US09627781B2 |
Contact element and method for manufacturing same
A contact element for contacting a contact point formed on a body includes: an element section on the contact point side for a force-locking connection to the contact point, an element section on the connection side for connection to an electrical connection conductor, and an intermediate section which connects the two element sections to one another for compensating for thermal expansions. At least the element sections on the contact point side and on the connection side are made of different integrally bonded materials having material properties which are adapted to the functionality of the corresponding element section. |
| US09627769B2 |
Slot antenna and information terminal apparatus using the same
A slot antenna and an information terminal apparatus using the same are provided. The slot antenna comprises: a conductive housing; and at least one slot formed on the corner and edge of the conductive housing. |
| US09627765B2 |
Optically transparent antenna for wireless communication and energy transfer
Embodiments of an optically transparent antenna are generally described herein. In some embodiments, the optically transparent antenna may comprise a plurality of electrically-isolated conductive patches arranged on a non-conductive surface. A combination of a size of the conductive patches and a spacing between the conductive patches is less than a human visual acuity for a predetermined viewing distance so that the patches are not be visible or perceptible to a human. In some embodiments, optically transparent antenna may serve as one or more antennas on a mobile platform. |
| US09627764B2 |
Antenna device and communication terminal apparatus
An antenna device includes a first coil wound in one direction and a second coil disposed adjacent to the first coil and wound in a direction opposite to the winding direction of the first coil and having conductor openings at the centers of wound coils, and a magnetic core. The magnetic core is inserted into the conductor opening of the first coil and the conductor opening of the second coil. A portion of a conductor line forming the first coil positioned farther away from the second coil than a portion of the conductor line forming the first coil positioned closer to the second coil, and a portion of a conductor line forming the second coil positioned farther away from the first coil than a portion of the conductor line forming the second coil positioned closer to the first coil, are disposed along the first main surface of the magnetic core. |
| US09627755B2 |
Multiband antenna and wireless communication device
A multiband antenna includes main antenna, a switch circuit, and a parasitic antenna. The main antenna includes a radiating portion, a feeding portion, a grounding portion, and an extending portion coupled to the feeding portion and the grounding portion. The radiating portion is configured to generate a low frequency resonate mode. The switch circuit is configured to regulate an impedance matching characteristic of the multiband antenna, thereby regulating an operating frequency of the low frequency resonate mode. The parasitic antenna is positioned apart from and electromagnetically coupled to the main antenna, and configured to generate a high frequency resonate mode. |
| US09627749B2 |
Radio-frequency transparent window
A patch for a device in an electronic housing including an aluminum layer having a threshold thickness, a non-conductive layer on a first side of the aluminum layer, and a radio-frequency (RF) transparent layer on a second side of the aluminum layer is provided. A method for manufacturing an antenna window including a patch as above is also provided, the method including determining a thickness of the aluminum layer adjacent to an anodized aluminum layer. A method for manufacturing an antenna window including coating an aluminum layer having a threshold thickness on a radio-frequency (RF) transparent layer to form an RF transparent laminate is also provided. A method for manufacturing an antenna window including removing a thickness of aluminum is also provided. A method for manufacturing an antenna window including disposing a mask on an aluminum substrate and anodizing the aluminum substrate to a selected thickness is also provided. |
| US09627746B2 |
Wireless communication apparatus and antenna system thereof
A wireless communication apparatus and an antenna system therein are provided. The antenna system includes a grounding portion and an antenna body. The grounding portion includes a ground plane and a conducting element. The conducting element is perpendicular to the ground plane and is connected to the ground plane to provide a first current path. The antenna body includes a main radiating portion and a short circuit portion. The main radiating portion is parallel to the ground plane and provides a second current path. An end of the main radiating portion is electrically connected to a signal source. The short circuit portion is electrically connected between the main radiating portion and the conducting element and provides a third current path. The directions of the first current path, the second current path and the third current path are perpendicular mutually. |
| US09627745B2 |
Antenna device attached to vehicle
An antenna device attached to a vehicle includes a base to which an antenna is fixed, a cover that is attached to the base, and a flexible pad that covers and supports an edge of the base, contacts an edge of the cover, and is located between the vehicle and the cover. A protrusion is provided on a surface of the pad on the cover side, and includes a body portion formed along the edge of the base, and a plurality of rib-like portions extending from the body portion to an edge of the pad. |
| US09627744B2 |
Method of making arbitrarily-shaped multifunctional structure
Multifunctional structures and methods of manufacturing multifunctional structures which function as both electronic devices and load-bearing elements are disclosed. The load-bearing elements are designed to have electronic functionality using electronics designed to be load-bearing. The method of manufacturing the multifunctional structure comprises forming an electronic element directly on at least one ply of arbitrarily shaped load-bearing material using conventional lithographic techniques and/or direct write fabrication techniques, and assembling at least two plies of arbitrarily shaped load-bearing material into a multifunctional structure. The multifunctional structure may be part of an aerospace structure, part of a land vehicle, pan of a watercraft or part of a spacecraft. |
| US09627740B2 |
RF notch filters and related methods
A radio-frequency (RF), base station notch filter includes an integral, conductive RF notch filter structure having one or more notch filter elements, where the notch filter elements may be circular in shape. The integral notch filter reduces insertion losses and passive intermodulation distortion. |
| US09627733B2 |
Millimeter waveband filter
To provide a millimeter waveband filter which can vary a resonance frequency in a wider band without causing deterioration of resonance characteristics due to leakage of electromagnetic waves. In a millimeter waveband filter 20, a first waveguides 22 and a second waveguide 24 are relatively moved to vary the interval between the electric wave half mirrors 30A and 30B, and the resonance frequency of a resonator formed between the mirrors varies to selectively transmit resonance frequency components. A groove 60 which has a length p along a longitudinal direction of the transmission line corresponding to a ¼ wavelength of electromagnetic waves to be a leakage prevention target is provided on the outside of the second waveguide 24 facing the inside of the first waveguide 22, thereby preventing leakage of electromagnetic waves from the gap between the first waveguide 22 and the second waveguide 24. |
| US09627732B2 |
Connector for cavity filter
A connector adapted for a cavity filter of the present invention includes a contact pin, a first insulator, a housing and a transmission line, the first insulator is provided with a first locating hole, the housing shaped as a cylinder is provided with a second locating hole. During the assembly, no additional mounting slot is required. Less space is taken up by the cylindrical housing, which provides more space for the transmission line and makes the line connections easier therefore. Moreover, the assembly of the connector is simple and efficient, and the connector is in an integrated structure, and the components of the connector are connected by inserting or plugging, which reduces the welding points, thus the vibrations among the components are reduced and the accumulated assembly tolerances are reduced accordingly, thereby the communication quality is improved and the cost is decreased. |
| US09627724B2 |
Battery pack having a cooling plate assembly
A battery pack having a cooling plate assembly and a battery module is provided. The cooling plate assembly has a pan member, first and second corrugated support members, a cover plate, and a thermally conductive layer. The pan member has first and second depressed plate portions. The first and second corrugated support members are disposed on the first and second depressed plate portions, respectively. The cover plate is coupled to the pan member such that the first and second corrugated support members are held between the cover plate and the pan member in first and second internal regions, respectively, defined by the cover plate and the pan member. The thermally conductive layer is disposed on the cover plate. The battery module is disposed on the thermally conductive layer. |
| US09627721B2 |
Electricity storage device and vehicle
An electricity storage device includes: a first battery stack (15) including a plurality of cells that are aligned in a first direction; a second battery stack (11 to 14) including a plurality of cells that are aligned in a second direction different from the first direction, the second battery stack being placed under the first battery stack; and a duct for coolant. The duct is disposed along the first battery stack and is positioned between the first battery stack and the second battery stack. |
| US09627720B2 |
Battery pack, apparatus including battery pack, and method of managing battery pack
A battery pack includes a battery module, a plurality of temperature sensors, a temperature data generating unit, and a control unit. The battery module has a plurality of battery cells. The temperature data generating unit detects battery temperatures from the temperature sensors and generates battery temperature data including temperature values corresponding to the battery temperatures. The control unit determines whether or not the temperature sensors are defective based on the battery temperature data, and controls the battery module based on temperature values corresponding to temperature sensors determined not to be defective. |
| US09627719B2 |
Charging method of battery and battery charging system
A method of charging a battery and a battery charging system, which has a relatively high charging speed while having a relatively low level of battery deterioration. The charging method includes charging a battery cell with a first current in a first constant current mode; charging the battery cell with a first voltage in a first constant voltage mode; idling the charging of the battery cell for a first idle period (t); charging the battery cell with a second current different from the first current in a second constant current mode; and charging the battery cell with a second voltage different from the first voltage in a second constant voltage mode. |
| US09627716B2 |
Electrolyte and lithium based batteries
An example electrolyte includes a solvent mixture, a lithium salt, a non-polymerizing solid electrolyte interface (SEI) precursor additive, and a solvent additive. The solvent mixture includes dimethyl carbonate (DMC) and fluoroethylene carbonate (FEC) present in a volume to volume ratio ranging from 20 to 1 to 1 to 20. The non-polymerizing SEI precursor additive is present in an amount ranging from greater than 0 wt % to about 10 wt % of a total wt % of the electrolyte, and the solvent additive is present in an amount ranging from greater than 0 wt % to about 10 wt % of the total wt % of the electrolyte. |
| US09627714B2 |
Non-aqueous electrolyte and battery
A non-aqueous electrolyte including (i) a compound represented by the general formula (1): X—R—SO2F (1) where R is a C1-12 linear or branched alkylene group optionally containing an ether bond and optionally hydrogen atoms of the alkylene group are partly substituted by a fluorine atom(s); and X is a carboxylic acid derivative group), (ii) a non-aqueous solvent and (iii) an electrolyte salt. |
| US09627710B2 |
Battery
A battery includes: an electricity-generating element that is formed by winding an electrode plate and a separator and has a space at a winding axial portion; and a spacer having an inclined portion having a width that is gradually reduced toward the center of the electricity-generating element. At least a part of the spacer is disposed in the space at the winding axial portion of the electricity-generating element, the inclined portion of the spacer abutting against an end of an inner wall of the electricity-generating element. |
| US09627699B2 |
Gaseous fuel CPOX reformers and methods of CPOX reforming
A gaseous fuel catalytic partial oxidation (CPOX) reformer can include a plurality or an array of spaced-apart CPOX reactor units, each reactor unit including an elongate tube having a wall with internal and external surfaces, the wall enclosing an open gaseous flow passageway with at least a portion of the wall having CPOX catalyst disposed therein and/or comprising its structure. The catalyst-containing wall structure and open gaseous flow passageway enclosed thereby define a gaseous phase CPOX reaction zone, the catalyst-containing wall section being gas-permeable to allow gaseous CPOX reaction mixture to diffuse therein and hydrogen-rich product reformate to diffuse therefrom. At least the exterior surface of a CPOX reaction zone of a CPOX reactor unit can include a hydrogen barrier. The gaseous fuel CPOX reformer also can include one or more igniters, and a source of gaseous reformable fuel. |
| US09627694B2 |
Zinc-water battery and system
Systems for batteries or galvanic cells are disclosed. The system comprises a mixing chamber. The system further comprises a first reservoir, in fluid communication with a mixing chamber, the first reservoir configured to store a concentrated electrolyte. Additionally the system comprises a pump configured to pump a fluid into the mixing chamber. The system further comprises an electrochemical energy cell in fluid communication with the mixing chamber wherein the mixing chamber is configured to receive the fluid and concentrated electrolyte and mix the fluid and the concentrated electrolyte to produce a diluted electrolyte. Finally the system comprises the electrochemical energy cell configured to receive the diluted electrolyte, use the received diluted electrolyte for an electrochemical reaction and remove the used electrolyte solution from the cell. |
| US09627693B2 |
Energy storage and generation systems
This disclosure relates to energy storage and generation systems, e.g., combination of flow battery and hydrogen fuel cell, that exhibit operational stability in harsh environments, e.g., both charging and discharging reactions in a regenerative fuel cell in the presence of a halogen ion or a mixture of halogen ions. This disclosure also relates to energy storage and generation systems that are capable of conducting both hydrogen evolution reactions (HERs) and hydrogen oxidation reactions (HORs) in the same system. This disclosure further relates to energy storage and generation systems having low cost, fast response time, and acceptable life and performance. |
| US09627691B2 |
Metalized, three-dimensional structured oxygen cathode materials for lithium/air batteries and method for making and using the same
This disclosure relates generally to cathode materials for electrochemical energy cells, more particularly to metal/air electrochemical energy cell cathode materials containing silver vanadium oxide and methods of making and using the same. The metal/air electrochemical energy cell can be a lithium/air electrochemical energy cell. Moreover the silver vanadium oxide can be a catalyst for one or more of oxidation and reduction processes of the electrochemical energy cell. |
| US09627687B2 |
Secondary battery
An exemplary embodiment provides a lithium ion secondary battery using a high energy type anode, which enables long-life operation thereof. A secondary battery according to an exemplary embodiment comprises an electrode element in which a cathode and an anode are oppositely disposed, an electrolytic solution, and an outer packaging body which encloses the electrode element and the electrolytic solution inside; wherein the anode is formed by binding an anode active material, which comprises carbon material (a) that can absorb and desorb a lithium ion, metal (b) that can be alloyed with lithium, and metal oxide (c) that can absorb and desorb a lithium ion, to an anode collector with an anode binder; and wherein the electrolytic solution comprises a liquid medium which is hard to generate carbon dioxide at a concentration of 10 to 80 vol %. |
| US09627686B2 |
Method for manufacturing lithium-containing composite oxide
To simply manufacture a lithium-containing oxide at lower manufacturing cost. A method for manufacturing a lithium-containing composite oxide expressed by a general formula LiMPO4 (M is one or more of Fe (II), Mn (II), Co (II), and Ni (II)). A solution containing Li and P is formed and then is dripped in a solution containing M (M is one or more of Fe (II), Mn (II), Co (II), and Ni (II)) to form a mixed solution. By a hydrothermal method using the mixed solution, a single crystal particle of a lithium-containing composite oxide expressed by the general formula LiMPO4 (M is one or more of Fe (II), Mn (II), Co (II), and Ni (II)) is manufactured. |
| US09627685B2 |
Method for preparing lithium iron phosphate nanopowder
The present invention relates to a method for preparing a lithium iron phosphate nanopowder, including the steps of (a) preparing a mixture solution by adding a lithium precursor, an iron precursor and a phosphorus precursor in a reaction solvent, and (b) putting the mixture solution into a reactor and heating to prepare the lithium iron phosphate nanopowder under pressure conditions of 10 to 100 bar, and a lithium iron phosphate nanopowder prepared by the method. When compared to a common hydrothermal synthesis method and a supercritical hydrothermal synthesis method, a reaction may be performed under a relatively lower pressure. When compared to a common glycothermal synthesis method, a lithium iron phosphate nanopowder having effectively controlled particle size and particle size distribution may be easily prepared. |
| US09627684B2 |
High capacity, dimensionally stable anode from low-bulk density amorphous silicon for lithium-ion batteries
An anode active material for a lithium-ion battery cell comprises low density silicon. The anode active material is provided in an anode for a lithium-ion battery. Also disclosed are methods of making the anode active material. |
| US09627681B2 |
Silicon-based composite and production method thereof
The present invention relates to a silicon-based composite including a silicon oxide which is coated thereon with carbon and bonded therein to lithium. The present invention also relates to a method of producing a silicon-based composite, comprising coating a surface of silicon oxide with carbon, mixing the silicon oxide coated with carbon with lithium oxide, and heat-treating a mixture of the silicon oxide coated with carbon and the lithium oxide in an inert atmosphere. |
| US09627674B2 |
Battery module
A battery module includes a plurality of battery cells, each including terminal portions on a first surface thereof, the plurality of battery cells being aligned in a first direction; and a terminal connecting member configured to connect terminal portions of first and second battery cells of the plurality of battery cells that are adjacent to each other, and the terminal connecting member includes first and second contact portions spaced apart from each other to respectively come in surface contact with the terminal portions of the first and second battery cells, and a body portion connecting the first and second contact portions to each other. |
| US09627670B2 |
Battery cell and method for making battery cell
Embodiments provide a battery cell including a porous membrane, the porous membrane including transformed semiconductor material. The porous membrane separates a first half-cell from a second half-cell of the battery cell. The porous membrane comprises channels allowing ions and/or an electrolyte to move between the first half-cell and the second half-cell. |
| US09627667B2 |
Lid including rib adjacent safety valve for a battery case
In a lid for a battery case where an annular thin portion is formed integrally with a lid main body by coining, a pair of ribs formed integrally with the lid main body so as to bulge from the lid main body and extending in a short direction of the lid main body are disposed on both sides of the annular thin portion in a long direction of the lid main body. |
| US09627665B1 |
Battery module and manufacturing method thereof
A manufacturing method of a battery module is firstly to produce two integrated electrodes. An electrode plate has a plurality of electrode openings, and two electrode side plates have individual side-plate screw contact openings. The side walls of the two electrode side plates have individually inner-wall surfaces facing to each other. Two screw members are then bonded to the inner-wall surfaces of the two electrode plates. Two holder frames cover the electrode plate and the two screw members to form an integrated holder frame. Two holder frame side openings of the two holder frames are located respective to the side openings. A plurality of battery cells, each of which has a first and a second electrode, is combined to the two integration-battery-holder frames. The second electrode electrically connect one of the integrated electrodes, and a plurality of wires connects the first electrode to a plate bonding portion, such that a battery module can be produced. |
| US09627664B2 |
Battery module of excellent structural stability
Disclosed is a battery module including a base plate on which unit modules, each with two or more secondary batteries therein, are stacked in a vertically erected state, a pair of end plates disposed in tight contact with outer surfaces of outermost unit modules while bottoms of the end plates are fixed to the base plate, and supporting bars connected between opposite sides of upper or side parts of the end plates so as to support the end plates, wherein each of the end plates includes a main body contacting a corresponding one of the unit modules, and a top wall, a bottom wall, and a pair of side walls protruding outward from the perimeter of the main body, the thickness of each of the side walls being increased from the top to the bottom wall, thereby dispersing pressure (bending load) from the unit modules and the supporting bars. |
| US09627662B2 |
Secondary battery
A secondary battery includes an electrode assembly, a case that accommodates the electrode assembly, a cap plate that seals the case, an electrode terminal assembled to penetrate through the cap plate, and a short-circuit inducing member that is fixed to a top surface of the cap plate, the short-circuit inducing member being displaceable according to a deformation of the cap plate to induce a short-circuit by contact with the electrode terminal. |
| US09627654B2 |
Organic light emitting diode device
An OLED display includes a first substrate, a first electrode on the first substrate, a pixel defining layer having a first aperture exposing the first electrode, an organic light emitting layer on the first electrode, a second electrode on the organic light emitting layer, a second substrate disposed to face the first substrate, a black matrix disposed on the second substrate and having a second aperture, and a lens disposed to cover at least a part of the second aperture and protruding toward the first substrate. |
| US09627653B2 |
Organic electroluminescence element and planar light-emitting body each having light extraction sheet
Provided is an organic EL element having both excellent light extraction efficiency and excellent weather resistance. The organic EL element (10) has a configuration comprising: an organic EL element main body (1) including an organic compound layer (13) including a light-emitting layer; and a light extraction sheet (2) provided on the light-extraction side of the organic EL element main body (1). In addition, the organic EL element (10) is characterized by: the light extraction sheet (2) including a silicon compound; the haze value of the light extraction sheet (2) being at least 90; and the total light transmittance of the light extraction sheet (2) being at least 80%. |
| US09627650B2 |
Multiple light-emitting element device each with varying wavelength
To provide a novel light-emitting device, a light-emitting device that emits light of a plurality of colors includes a first light-emitting element and a second light-emitting element. The first light-emitting element includes a first lower electrode, a first light-emitting layer over the first lower electrode, a second light-emitting layer over the first light-emitting layer, and an upper electrode over the second light-emitting layer. The second light-emitting element includes a second lower electrode, the first light-emitting layer over the second lower electrode, the second light-emitting layer over the first light-emitting layer, and the upper electrode over the second light-emitting layer. An emission spectrum of the first light-emitting layer peaks at a longer wavelength than an emission spectrum of the second light-emitting layer. A distance between the first lower electrode and the first light-emitting layer is shorter than a distance between the second lower electrode and the first light-emitting layer. |
| US09627649B2 |
Organic light emitting display device
Discussed is an organic light emitting display device. An OLED including a transparent anode formed of one conductive transparent material and an organic light emitting diode (OLED) including a cavity anode formed of a plurality of conductive materials are provided in one panel. |
| US09627645B2 |
Mask plate, organic light-emitting diode (OLED) transparent display panel and manufacturing method thereof
A mask plate for manufacturing an organic light-emitting diode (OLED) transparent display panel, the OLED transparent display panel and a manufacturing method thereof are disclosed. The mask plate includes a substrate and a plurality of hollowed-out areas and a plurality of opaque areas disposed on the substrate, and a pattern of the hollowed-out areas correspond to a pattern of a cathode of the OLED transparent display panel to be manufactured; and all the hollowed-out areas are communicated with each other. |
| US09627644B2 |
Organic light emitting diode device
In an aspect, an organic light emitting diode device including a first electrode, a second electrode facing the first electrode, and an emission layer positioned between the first electrode and second electrode, wherein the first electrode includes samarium (Sm) is provided. |
| US09627631B2 |
Organic electroluminescent materials and devices
Boron-nitrogen polyaromatic compounds having a fused aromatic ring system are provided, where the compounds include a [1,2]azaborino[1,2-a][1,2]azaborine which is optionally fused to one or more aromatic rings or fused aromatic rings; wherein the fused aromatic ring system is substituted by one or more substituents, R, that are not fused to the aromatic ring system, selected from the group consisting of deuterium, halide, alkyl, cycloalkyl, heteroalkyl, arylalkyl, alkoxy, aryloxy, amino, silyl, alkenyl, cycloalkenyl, heteroalkenyl, alkynyl, aryl, heteroaryl, acyl, carbonyl, carboxylic acids, ester, nitrile, isonitrile, sulfanyl, sulfinyl, sulfonyl, phosphino, and combinations thereof; and wherein any two adjacent substituents, R, are optionally joined to form one or more non-aromatic rings. Devices, such as organic light emitting devices (OLEDs) that comprise light emitting materials are also provided. |
| US09627630B2 |
Organic electroluminescent element, display device and lighting device
Disclosed is an organic electroluminescent device having long life, while exhibiting high luminous efficiency. Also disclosed are an illuminating device and a display, each using such an organic electroluminescent device. In the organic electroluminescent device, a compound represented by the general formula (A) which is suitable as a host material for a phosphorescent metal complex is used at least in one sublayer of a light-emitting layer. |
| US09627623B2 |
Organic electroluminescent element, compound, and light emitting device, display device and lighting device each using organic electroluminescent element
An organic electroluminescent element including a substrate, a pair of electrodes including an anode and a cathode, disposed on the substrate, and at least one organic layer including a light emitting layer, disposed between the electrodes. At least one kind of a compound represented by the following general formula (I) is contained in any layer of the at least one organic layer. The organic electroluminescent element has good luminous efficiency, driving voltage, and driving durability, and has low dependence of such performance on a deposition rate. Wherein: L1 to L4, n1 to n4, A1, A5, A6, A10 and, R are as defined in the application. |
| US09627618B2 |
Substrate for use in manufacturing display device and method for forming element on substrate
A substrate is for use in manufacturing a display device. The substrate includes a first area that corresponds to pixel positions. The substrate further includes a second area adjacent to the first area. The substrate further includes a first mark disposed in the second area, wherein a first virtual line corresponds to the first mark. The substrate further includes a second mark disposed in the second area and spaced from the first mark, wherein a second virtual line corresponds to the second mark and intersects the first virtual line at a virtual reference point. The substrate further includes an indicator disposed in the second area, spaced from the first mark and the second mark, and corresponding to an opening of a mask, wherein a positional relation between the virtual reference point and a point of the indicator represents a positional relation between the substrate and the mask. |
| US09627617B2 |
Method for manufacturing organic EL panel
A method for manufacturing an organic EL panel includes: applying sealing resin for forming a sealing resin layer to a plurality of spots on an application target surface of one of an EL substrate and a CF substrate, the application target surface being a surface to which the sealing resin is to be applied, and stacking the EL substrate and the CF substrate one on top of the other after the sealing resin is applied, and when the sealing resin is applied, the amount of the sealing resin applied to a spot near an edge of the application target surface is less than the amount of the sealing resin applied to a spot further inward than the spot near the edge. |
| US09627614B2 |
Resistive switching for non volatile memory device using an integrated breakdown element
A method of suppressing propagation of leakage current in an array of switching devices. The method includes providing a dielectric breakdown element integrally and serially connected to a switching element within each of the switching device. A read voltage (for example) is applied to a selected cell. The propagation of leakage current is suppressed by each of the dielectric breakdown element in unselected cells in the array. The read voltage is sufficient to cause breakdown in the selected cells but insufficient to cause breakdown in the serially connected, unselected cells in a specific embodiment. Methods to fabricate of such devices and to program, to erase and to read the device are provided. |
| US09627604B2 |
Tubular spring for receiving and pretensioning an actuator
A tubular spring is provided for receiving and pretensioning a piezoelectric or magnetostrictive actuator of an actuator unit, e.g., for actuating a fuel injector valve in internal combustion engines, wherein the tubular spring comprises at least two types of recesses, each comprising different maximum lateral extensions in the longitudinal direction of the tubular spring. The tubular spring is designed to comprise a uniform load distribution about the circumference of the tubular spring even without welding the longitudinal sides thereof abutting one another. |
| US09627600B2 |
Mg—Si system thermoelectric conversion material, method for producing same, sintered body for thermoelectric conversion, thermoelectric conversion element, and thermoelectric conversion module
Provided are: an Mg—Si system thermoelectric conversion material which exhibits stably high thermoelectric conversion performance; a sintered body for thermoelectric conversion, which uses this Mg—Si system thermoelectric conversion material; a thermoelectric conversion element having excellent durability; and a thermoelectric conversion module. A method for producing an Mg—Si system thermoelectric conversion material according to the present invention comprises a step for heating and melting a starting material composition that contains Mg, Si, Sb and Zn. It is preferable that the contents of Sb and Zn in the starting material composition are respectively 0.1-3.0 at % in terms of atomic weight ratio. |
| US09627599B2 |
LED lighting apparatus and heat dissipation module
Provided is an LED light which may include a base plate, an LED module disposed under the base plate, a plurality of heat pipes provided over the base plate, and a plurality of heat dissipation fins provided over the base plate. The plurality of heat pipes may include a first portion thermally coupled to the base plate and a second portion that extends from the first portion. The plurality of heat dissipation fins may be spaced apart from each other and thermally coupled to the second portion of the heat pipes to dissipate heat from the LED module. The LED light may include an upper bracket provided over the plurality of heat dissipation fins and fastened to a hanger, and a plurality of studs that connect the base plate to the upper bracket. |
| US09627598B2 |
Light emitting device
A light emitting device has: a plurality of light emitting elements, a base having a first main surface and a second main surface on the opposite side from the first main surface, the base having conductive patterns disposed on the first main surface on which the light emitting elements are mounted, conductive patterns disposed on the second main surface, and a groove provided on the second main surface of the base corresponding to a space between the light emitting elements, and a light reflecting member that integrally covers side surfaces of the plurality of light emitting elements. |
| US09627586B2 |
Electroluminescent element and lighting apparatus comprising the same
An electroluminescent element includes a first transparent electrode, a second transparent electrode, a light emitting layer sandwiched between the first transparent electrode and the second transparent electrode, a first transparent member formed on a surface of the first transparent electrode opposite to the light emitting layer, and a second transparent member formed on a surface of the second transparent electrode opposite to the light emitting layer, wherein refractive indices of the first transparent electrode and the second transparent electrode are selected such that as seen from the light emitting layer, a reflectance of an interface between the light emitting layer and the first transparent electrode becomes higher than a reflectance of an interface between the light emitting layer and the second transparent electrode, and wherein a refractive index of the first transparent member is set to be higher than a refractive index of the second transparent member. |
| US09627585B2 |
Wiring structure, thin film transistor array substrate including the same, and display device
In a wiring conversion part which connects a lower conductive film to a first conductive film each functioning as a wiring, a first transparent conductive film is formed into a pattern in which it covers an end surface of the first conductive film, and an angle formed at a corner part in a portion of the first transparent conductive film making contact with a lower first insulating film (outside a width of the first conductive film) is larger than 90 degrees and smaller than 270 degrees or the corner part has an arc shape. A second transparent conductive film is connected to the lower conductive film and the first transparent conductive film, and the first transparent conductive film is connected to the first conductive film, so that the lower conductive film and the first conductive film are electrically connected to each other. |
| US09627584B2 |
Light emitting device and light emitting device package
A light emitting device includes a light emitting structure including a plurality of compound semiconductor layers. A current spreading layer is provided under the light emitting structure, and a plurality of wavelength conversion structures is provided in the current spreading layer. An electrode layer is provided under the current spreading layer, and an electrode is provided on the light emitting structure. |
| US09627583B2 |
Light-emitting device and method for manufacturing the same
There is provided a light-emitting device comprising a light-emitting element. The light-emitting device of the present invention comprises an electrode part for the light-emitting element; a reflective layer provided on the electrode part; and the light-emitting element provided on the reflective layer such that the light-emitting element is in contact with at least a part of the reflective layer, wherein the light-emitting element and the electrode part are in an electrical connection with each other by mutual surface contact via the at least a part of the reflective layer, wherein the electrode part serves as a supporting layer for supporting the light-emitting element, and wherein the electrode part extends toward the outside of the light-emitting element and beyond the light-emitting element. |
| US09627581B2 |
Nitride semiconductor structure, electronic device including the nitride semiconductor structure, light-emitting device including the nitride semiconductor structure, and method for producing the nitride semiconductor structure
A nitride semiconductor structure includes a nitride semiconductor layer having a principal plane and including a nitride semiconductor. The normal to the principal plane of the nitride semiconductor layer is inclined at 5 degrees or more and 17 degrees or less with respect to the [11-22] axis of the nitride semiconductor constituting the nitride semiconductor layer in the direction of the +c-axis of the nitride semiconductor. The nitride semiconductor structure may further include a substrate having a principal plane which supports the nitride semiconductor layer on the principal plane. The substrate may include any one selected from the group consisting of a nitride semiconductor, sapphire, and Si. |
| US09627572B2 |
Light receiving and emitting element module and sensor device using same
A light receiving and emitting element module includes a substrate; a light emitting element and a light receiving element on an upper surface of the substrate; a frame-shaped outer wall that on the upper surface of the substrate; and a light shielding wall that is positioned inside the outer wall and partitions an internal space of the outer wall into spaces respectively corresponding to the light emitting element and the light receiving element. The light shielding wall includes a light emitting element-side shading surface on the light emitting element side, a light receiving element-side shading surface on the light receiving element side, and a lower surface that is connected to each of the light emitting element-side shading surface and the light receiving element-side shading surface, and that faces the substrate. The lower surface has an inclined surface inclined with respect to the upper surface of the substrate. |
| US09627571B2 |
Semiconductor device
An optical fiber is provided between a photodiode and a semiconductor active portion of a wide gap semiconductor element forming portion such that emitted light at the time of light emission of the semiconductor active portion of the wide gap semiconductor element forming portion is incident from an incident surface of the optical fiber, and is received from an emitting surface to the photodiode through the optical fiber. Specifically, the incident surface of the optical fiber is arranged so as to be opposed to a side surface portion of the wide gap semiconductor element forming portion, so that the emitted light at the time of light emission of the wide gap semiconductor element is incident on the incident surface. |
| US09627564B2 |
Optoelectronic device comprising nanostructures of hexagonal type crystals
An optoelectronic device comprising: a first conductive layer, a second conductive layer, an active layer between the first conductive layer and the second conductive layer, wherein the active layer comprises a submicrometer size structure of hexagonal type crystals of an element or alloy of elements selected from the carbon group. |
| US09627562B2 |
Method of manufacturing a monolayer graphene photodetector and monolayer graphene photodetector
In various embodiments of the present disclosure, there is provided a method of manufacturing a monolayer graphene photodetector, the method including forming a graphene quantum dot array in a graphene monolayer, and forming an electron trapping center in the graphene quantum dot array. Accordingly, a monolayer graphene photodetector is also provided. |
| US09627561B2 |
Method for etching multi-layer epitaxial material
A single-step wet etch process is provided to isolate multijunction solar cells on semiconductor substrates, wherein the wet etch chemistry removes semiconductor materials nonselectively without a major difference in etch rate between different heteroepitaxial layers. The solar cells thus formed comprise multiple heterogeneous semiconductor layers epitaxially grown on the semiconductor substrate. |
| US09627560B2 |
Radiographic image detector
A radiographic image detector includes a phosphor layer, a heat shield layer, and a photoelectric converter in this order, wherein the heat shield layer has a thickness T (μm) and a thermal conductivity C (W/m·K) satisfying that C/T is from 0.004 to 5. |
| US09627551B2 |
Ultrahigh-voltage semiconductor structure and method for manufacturing the same
The disclosure provides an ultrahigh-voltage (UHV) semiconductor structure including a first electrical portion, a second electrical portion and a bridged conductive layer. In which, the first electrical portion and the second electrical portion are isolated, and directly connected to each other through the bridged conductive layer. Thus, there is no current leakage occurring in the UHV semiconductor structure disclosed in this disclosure. And a method for manufacturing the UHV semiconductor structure also provides herein. |
| US09627549B1 |
Semiconductor transistor device and method for fabricating the same
A semiconductor transistor device includes an oxide semiconductor layer having an active surface, a source electrode, a drain electrode, a gate electrode and a control capacitor. The gate electrode, the source electrode and the drain electrode are directly in contact with the active surface. The gate electrode is disposed between the drain electrode and the source electrode. The gate electrode, the source electrode and the drain electrode are separated from each other. The control capacitor is electrically connected to the gate electrode through a connection. |
| US09627547B2 |
Semiconductor structure
A semiconductor structure includes a substrate and a first element disposed in the substrate and arranged along a first direction. The first element is made of a semiconductor oxide material. The semiconductor structure also includes a dielectric layer disposed on the first element, and a second element, disposed on the dielectric layer and arranged along the first direction. The second element is used as a gate of a transistor structure. |
| US09627541B2 |
Non-planar transistor and method of forming the same
A non-planar transistor is provided. It includes a substrate, a fin structure, a gate structure, a spacer structure and a source/drain region. The fin structure is disposed on the substrate, the gate structure is disposed on the fin structure. The spacer structure is disposed on a sidewall of the gate structure. The spacer structure includes a first spacer with a first height and a second spacer with a second height, wherein the first spacer is disposed between the second spacer, and the first height is different from the second height. The source/drain region is disposed in a semiconductor layer at two sides of the spacer structure. The present invention further provides a method of forming the same. |
| US09627534B1 |
Semiconductor MOS device having a dense oxide film on a spacer
A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, an ILD layer on the semiconductor substrate, a gate in the ILD layer, an offset liner on a sidewall of the gate, a spacer on the offset liner, a dense oxide film on the spacer, a contact etch stop layer on the dense oxide film, and a contact plug adjacent to the contact etch stop layer. The semiconductor device further includes a source region in the semiconductor substrate and a drain region spaced apart from the source region. A channel is located between the source region and the drain region. |
| US09627533B2 |
High selectivity nitride removal process based on selective polymer deposition
A silicon nitride cap on a gate stack is removed by etching with a fluorohydrocarbon-containing plasma subsequent to formation of source/drain regions without causing unacceptable damage to the gate stack or source/drain regions. A fluorohydrocarbon-containing polymer protection layer is selectively deposited on the regions that are not to be etched during the removal of the nitride cap. The ability to remove the silicon nitride material using gas chemistry, causing formation of a volatile etch product and protection layer, enables reduction of the ion energy to the etching threshold. |
| US09627532B2 |
Methods and apparatus for training an artificial neural network for use in speech recognition
Methods and apparatus for training a multi-layer artificial neural network for use in speech recognition. The method comprises determining for a first speech pattern of the plurality of speech patterns, using a first processing pipeline, network activations for a plurality of nodes of the artificial neural network in response to providing the first speech pattern as input to the artificial neural network, determining based, at least in part, on the network activations and a selection criterion, whether the artificial neural network should be trained on the first speech pattern, and updating, using a second processing pipeline, network weights between nodes of the artificial neural network based, at least in part, on the network activations when it is determined that the artificial neural network should be trained on the first speech pattern. |
| US09627523B2 |
High electron mobility transistor
A high electron mobility transistor comprises a substrate, an epitaxial stack arranged above the substrate and having a first region and a second region surrounding the first region, a matrix electrode structure arranged in the first region. The matrix electrode comprises a plurality of first electrodes arranged on the epitaxial stack, a plurality of second electrodes arranged on the epitaxial stack and adjacent to the plurality of first electrodes, a plurality of third electrodes arranged adjacent to the plurality of first electrodes and second electrodes. One of the plurality of first electrodes comprises a first side, a second side, a third side and a fourth side. The first side and the third side are opposite sides, and the second side and the fourth side are opposite sides. Two of the plurality of second electrodes are arranged on the first side and the third side, and two of the plurality of third electrodes are arranged on the second side and the fourth side. |
| US09627518B2 |
Power integrated devices, electronic devices including the same and electronic systems including the same
A power integrated device includes a gate electrode on a substrate, a source region and a drain region disposed in the substrate at two opposite sides of the gate electrode, a drift region disposed in the substrate between the gate electrode and the drain region to be spaced apart from the source region, and a plurality of insulating stripes disposed in an upper region of the drift region to define at least one active stripe therebetween. Related electronic devices and related electronic systems are also provided. |
| US09627514B1 |
Semiconductor device and method of fabricating the same
A method of fabricating a semiconductor device is provided as follows. Epitaxial layers is formed on an active fin structure of a substrate. First metal gate electrodes are formed on the active fin structure. Each first metal gate electrode and each epitaxial layer are alternately disposed in a first direction on the active fin structure. ILD patterns are formed on the epitaxial layers, extending in a second direction crossing the first direction. Sacrificial spacer patterns are formed on the first metal gate electrodes. Each of the plurality of sacrificial spacer patterns covers a corresponding first metal gate electrode of the first metal gate electrodes. Self-aligned contact holes and sacrificial spacers are formed by removing the ILD patterns. Each self-aligned contact hole exposes a corresponding epitaxial layer disposed under each ILD pattern. Source/drain electrodes are formed in the self-aligned contact holes. The sacrificial spacers are replaced with air spacers. |
| US09627513B2 |
Method for manufacturing lateral double-diffused metal oxide semiconductor transistor
The present disclosure relates to a lateral double-diffused metal oxide semiconductor transistor and a method for manufacturing the same. In the method, a high-voltage gate dielectric is formed at a surface of a semiconductor layer. A thin gate dielectric is formed above the substrate and has at least a portion adjacent to the high-voltage gate dielectric. A gate conductor is formed above the thin gate dielectric and the high-voltage gate dielectric. A first mask is used for patterning the gate conductor to define a first sidewall of the gate conductor above the thin gate dielectric. A second mask is used for patterning the gate conductor to define a second sidewall of the gate conductor at least partially above the high-voltage gate dielectric. Source and drain regions are formed to have a first doping type. The method further comprises doping through the first mask to form a body region of a second doping type. The second doping type is opposite to the first doping type. The method simplifies a manufacturer process and improves reliability of the resultant devices. |
| US09627510B1 |
Structure and method for replacement gate integration with self-aligned contacts
A method for fabricating a semiconductor device comprises forming a dummy gate on a substrate; forming spacers at opposing sides of the dummy gate; depositing a sacrificial interlayer dielectric over the dummy gate; planarizing the interlayer dielectric to expose the dummy gate; removing the dummy gate; forming a replacement metal gate with a protective cap between the spacers and on the substrate to replace the removed dummy gate; removing the sacrificial interlayer dielectric; siliciding exposed areas of the substrate adjacent to the replacement metal gate; depositing a final interlayer dielectric over the replacement metal gate and the exposed silicided areas; and forming vias through the final interlayer dielectric to the silicided areas. |
| US09627508B2 |
Replacement channel TFET
A semiconductor structure includes a substrate and an intrinsic replacement channel. A tunneling field effect transistor (TFET) fin may be formed by the intrinsic replacement channel, a p-fin and an n-fin formed upon the substrate. The p-fin may serve as the source of the TFET and the n-fin may serve as the drain of the TFET. The replacement channel may be formed in place of a sacrificial channel of a diode fin that includes the p-fin, the n-fin, and the sacrificial channel at the p-fin and n-fin junction. |
| US09627506B2 |
Method of manufacturing semiconductor device
A semiconductor device includes a semiconductor layer formed on a substrate, an electrode contact window that includes a recess formed on a surface of the semiconductor layer, an inner wall having a slope, and a source electrode, a drain electrode, and a gate electrode formed on the semiconductor layer, in which the drain electrode is in contact with the slope of the inner wall. |
| US09627503B2 |
Bipolar transistor, semiconductor device, and bipolar transistor manufacturing method
Disconnection of a base line is suppressed even when a short-side direction of a collector layer is parallel to crystal orientation [011]. A bipolar transistor includes: a collector layer that has a long-side direction and a short-side direction in a plan view, in which the short-side direction is parallel to crystal orientation [011], a cross-section perpendicular to the short-side direction has an inverted mesa shape, and a cross-section perpendicular to the long-side direction has a forward mesa shape; a base layer that is formed on the collector layer; a base electrode that is formed on the base layer; and a base line that is connected to the base electrode and that is drawn out from an end in the short-side direction of the collector layer to the outside of the collector layer in a plan view. |
| US09627499B2 |
Electrical conduction element, electronic device, and method for operating electrical conduction element
A nonvolatile three-terminal element is provided that operates by controlling a bandgap in an electron state of a graphene-based material. An ion conductor (5) having hydrogen ion or oxygen ion conductivity is provided between graphene oxide or graphene (hereinafter, referred to as GO) (6), and a gate electrode (1). In addition, a drain electrode (2) and a source electrode (3) are provided on a GO (6) side. |
| US09627498B2 |
Contact structure for thin film semiconductor
A method is described for forming a circuit that comprises forming a layer of semiconductor material on the substrate and an interlayer conductor contacting the layer. The layer can be a thin film layer. An opening is etched in an interlayer insulator over a layer of semiconductor material, to expose a landing area on the layer of semiconductor material. The semiconductor material exposed by the opening is thickened by adding some of the semiconductor material within the opening. The process for adding the semiconductor material can include a blanket deposition, or a selective growth only within the landing area. A reaction precursor, such as a silicide precursor is deposited on the landing area in the opening. A reaction of the precursor with the semiconductor material in the opening is induced. An interlayer conductor is formed within the opening. |
| US09627497B1 |
Semiconductor device with trench epitaxy and contact
A semiconductor device comprises a semiconductor fin arranged on a substrate, a gate stack arranged over a channel region of the fin, a spacer arranged in contact with sidewalls of the gate stack, a trench partially defined by the spacer, the fin, and a flowable oxide material, an epitaxially grown source/drain region formed on the fin in the trench, and a contact metal arranged on the source/drain region in the trench, the contact metal substantially filling the trench. |
| US09627495B2 |
Method for manufacturing semiconductor device
A method of fabricating a semiconductor device includes forming fin-shaped semiconductor layers on a semiconductor substrate. First and second pillar-shaped semiconductor layers are formed, and first and second control gates are formed around the first and second pillar-shaped semiconductor layers, respectively. First and second selection gates are formed around the first and second pillar-shaped semiconductor layers, respectively. First and second contact electrodes are formed around upper portions of the first and second pillar-shaped semiconductor layers, respectively. |
| US09627478B1 |
Integrated vertical nanowire memory
A nanowire structure includes successive crystalline nanowire segments formed over a semiconductor substrate. A first crystalline segment formed directly on the semiconductor substrate provides electrical isolation between the substrate and the second crystalline segment. Second and fourth crystalline segments are each formed from a p-type or an n-type semiconductor material, while the third crystalline segment is formed from a semiconductor material that is oppositely doped with respect to the second and fourth crystalline segments. |
| US09627477B2 |
Trench isolation structure having isolating trench elements
A semiconductor device includes a semiconductor substrate, an element isolating trench structure that includes an element isolating trench formed in one main surface of the semiconductor substrate, an insulating material that is formed within the element isolating trench, element formation regions that are surrounded by the element isolating trench, and semiconductor elements that are respectively formed in the element formation regions. The element isolating trench includes first element isolating trenches extending in a first direction, second element isolating trenches extending in a second direction that are at a right angle to the first direction, and third element isolating trenches extending in a third direction inclined at an angle θ (0°<θ<90°) from the first direction. |
| US09627472B2 |
Semiconductor structure with varying doping profile and related ICS and devices
An embodiment of a structure for a high voltage device of the type which comprises at least a semiconductor substrate being covered by an epitaxial layer of a first type of conductivity, wherein a plurality of column structures are realized, which column structures comprises high aspect ratio deep trenches, said epitaxial layer being in turn covered by an active surface area wherein said high voltage device is realized, each of the column structures comprising at least an external portion being in turn realized by a silicon epitaxial layer of a second type of conductivity, opposed than said first type of conductivity and having a dopant charge which counterbalances the dopant charge being in said epitaxial layer outside said column structures, as well as a dielectric filling portion which is realized inside said external portion in order to completely fill said deep trench. |
| US09627471B2 |
Super junction semiconductor device having strip structures in a cell area
A super junction semiconductor device includes a semiconductor portion having strip structures in a cell area. Each strip structure has a compensation structure with first and second sections inversely provided on opposite sides of a fill structure. Each section has first and second compensation layers of complementary conductivity types. The strip structures are linear stripes extending through the cell area in a first lateral direction and into an edge area surrounding the cell area in lateral directions. Each strip structure has an end section with a termination portion in the edge area in which the first compensation layer of the first section is connected with the first compensation layer of the second section via a first conductivity layer, and the second compensation layer of the first section is connected with the second compensation layer of the second section via a second conductivity layer. |
| US09627457B2 |
Organic light emitting display device and method of manufacturing the same
An organic light emitting display device includes a spacer on a pixel defining layer. The pixel defining layer includes openings corresponding to pixels. The device further includes first pixels to third pixels emitting light having different colors. The first pixels and the second pixels are alternately disposed in a row direction, and the third pixels are continuously disposed in a row direction. The row in which the first pixels and the second pixels are alternately disposed and the row in which the third pixels are continuously disposed are adjacent to each other in a column direction The spacer is disposed between two of the third pixels. |
| US09627456B2 |
Organic light-emitting display apparatus
An organic light-emitting display apparatus includes: a display substrate; at least one thin film transistor (TFT) on the display substrate; an organic light-emitting diode (OLED) electrically connected to the TFT, the OLED including: a first electrode on each sub-pixel on the display substrate; an intermediate layer on the first electrode; and a second electrode on the intermediate layer; an encapsulation substrate covering the OLED; a filler filling a space between the display substrate and the encapsulation substrate, the filler including scatterers having optical anisotropy; and a color filter between the encapsulation substrate and the filler, the color filter including a color filter electrode at a surface of the color filter. |
| US09627453B2 |
Display unit
A display unit includes a plurality of light emitting devices, each of the light emitting devices including a function layer including at least an organic layer is sandwiched between a first electrode and a second electrode, and which have a resonator structure for resonating light by using a space between the first electrode and the second electrode as a resonant section and extracting the light through the second electrode are arranged on a substrate, wherein in the respective light emitting devices, the organic layer is made of an identical layer, and a distance of the resonant section between the first electrode and the second electrode is set to a plurality of different values. |
| US09627452B2 |
Organic light emitting display apparatus
An organic light emitting display apparatus wherein a shift of white light caused by a viewing angle is reduced by adjusting an offset distance between one end of a corresponding emission region and one end of the black matrix adjacent to the one end of the corresponding emission region, thereby preventing a white color shift phenomenon at various viewing angles. Accordingly, a certain image is produced regardless of a use environment of a user's viewing angle. |
| US09627450B2 |
Organic light emitting display device
An organic light emitting display device includes a plurality of first sub-pixels arranged adjacent to each other along a first direction, each of the first sub-pixels includes a first emission region configured to emit light of a first color and a first transmission region configured to transmit external light, the first emission regions of at least two of the first sub-pixels are adjacent to each other; and a plurality of second sub-pixels arranged adjacent to each other along the first direction and adjacent to corresponding ones of the plurality of first sub-pixels along a second direction crossing the first direction, each of the plurality of second sub-pixels includes a second emission region configured to emit light of a second color and a second transmission region configured to transmit external light, the second emission regions of at least two of the sub-pixels are adjacent to each other. |
| US09627444B2 |
Fine metal mask and method of manufacturing the same
A method of manufacturing a fine metal mask is provided. The method of manufacturing a fine metal mask includes: forming a first recessed portion in a first surface of a base member; forming an edge portion of the first recessed portion in a uniform depth; forming a second recessed portion in a second surface of the base member, the second surface being opposite to the first surface; and communicating the first recessed portion and the second recessed portion of the base member. A fine metal mask produced by the inventive method is also described and may be used to fabricate OLEDs having better resolution and an increased aperture ratio in comparison with OLEDs prepared using the fine metal masks of the conventional art. |
| US09627442B2 |
Horizontally oriented and vertically stacked memory cells
Horizontally oriented and vertically stacked memory cells are described herein. One or more method embodiments include forming a vertical stack having a first insulator material, a first memory cell material on the first insulator material, a second insulator material on the first memory cell material, a second memory cell material on the second insulator material, and a third insulator material on the second memory cell material, forming an electrode adjacent a first side of the first memory cell material and a first side of the second memory cell material, and forming an electrode adjacent a second side of the first memory cell material and a second side of the second memory cell material. |
| US09627439B2 |
ZnO-based system on glass (SOG) for advanced displays
A ZnO based display pixel structure that includes system-on-glass (SOG) substrates with embedded non-volatile resistive random access memory iNV-RRAM) is provided. Such pixels feature high frame rates and low power consumption. The entire SOG is based on ZnO devices. Different devices including TFT, TCO, RRAM, inverters, and shift registers are obtained through doping of different elements into selected ZnO active regions. This reduces the cost to package control circuitry onto a backplane of a display system, resulting in a low cost, light weight and uUra-thin display. |
| US09627438B1 |
Three dimensional memory arrays and stitching thereof
The present invention is directed to a memory device including a first layer of memory cells with each cell of the first layer of memory cells including a two-terminal selection element coupled to a memory element in series; a plurality of first local wiring lines connected to one ends of the first layer of memory cells along a first direction with each of the first local wiring lines being electrically connected to two first line selection transistors at two ends thereof; and a plurality of second local wiring lines connected to other ends of the first layer of memory cells along a second direction substantially orthogonal to the first direction with each of the second local wiring lines being electrically connected to two second line selection transistors at two ends thereof. |
| US09627436B2 |
Substrate free LED package
A method of fabricating a substrate free light emitting diode (LED), includes arranging LED dies on a tape to form an LED wafer assembly, molding an encapsulation structure over at least one of the LED dies on a first side of the LED wafer assembly, removing the tape, forming a dielectric layer on a second side of the LED wafer assembly, forming an oversized contact region on the dielectric layer to form a virtual LED wafer assembly, and singulating the virtual LED wafer assembly into predetermined regions including at least one LED. The tape can be a carrier tape or a saw tape. Several LED dies can also be electrically coupled before the virtual LED wafer assembly is singulated into predetermined regions including at the electrically coupled LED dies. |
| US09627431B2 |
Solid-state imaging device
A solid-state imaging device according to the present disclosure includes: a charge storage region that stores a signal charge obtained through photoelectric conversion in a photoelectric conversion film; an amplification transistor that amplifies the signal charge stored in the charge storage region in a corresponding pixel; a contact plug that is electrically connected to the charge storage region and contains a semiconductor material; and a line that is disposed above the contact plug and contains a semiconductor material. The contact plug and the charge storage region are electrically connected, and the contact plug and a gate electrode of the amplification transistor are electrically connected via the line. |
| US09627424B2 |
Photodiodes for ambient light sensing and proximity sensing
Ambient light sensing and proximity sensing is accomplished using pairs of stacked photodiodes. Each pair includes a shallow diode with a shallow junction depth that is more sensitive to light having a shorter wavelength and a deeper diode with a deeper junction depth more sensitive to light with longer wavelengths. Photodiodes receiving light passed through cyan, yellow, and magenta filters and light passed without a color filter are used to generate red, green, and blue information through a subtractive approach. The shallow diodes are used to generate lux values for ambient light and the deeper diodes are used for proximity sensing. One or more of the deep diodes may be used in correction to lux determinations of ambient light. |
| US09627418B2 |
Semiconductor device
Disclosed is a semiconductor device having a first transistor and a second transistor over the first transistor. The first transistor includes a first semiconductor, and the second transistor includes an oxide semiconductor that is different from the first semiconductor. A gate of the first transistor is electrically connected to a source or drain electrode of the second transistor. The second transistor has a semiconductor layer including the oxide semiconductor over the source and drain electrodes and a gate electrode over the semiconductor layer with an insulating layer therebetween. |
| US09627416B2 |
Array substrate and method for manufacturing the same, display device
An array substrate is disclosed. The array substrate includes gate lines and data lines, and first and second signal lines. A first data line is between first and second pixel units, respectively including first and second film transistors. A first gate line is electrically connected to the gate electrodes of the first and second film transistors. The second electrode of the second film transistor is electrically connected to the first data line, and the second electrode of the first film transistor is electrically connected to the first signal line. The array substrate also includes a common electrode layer partially located between a third pixel unit and the first pixel unit, which is electrically insulated. In addition, a portion of the common electrode layer between the first pixel unit and the second pixel unit overlaps the first data line. |
| US09627409B2 |
Semiconductor device with thin-film resistor
A semiconductor device with a metal-containing layer, a first semiconductor layer, that is formed on top of the metal-containing layer, and a resistor that is formed in the metal-containing layer and that is contacted through the first semiconductor layer is provided. Furthermore, a method of manufacturing a semiconductor device is provided, wherein the method comprises manufacturing of a resistor with the following steps: formation of a metal-containing layer over a wafer, particularly a SOI wafer, formation of a first semiconductor layer on top of the metal-containing layer and formation of a contact through the semiconductor layer to the metal-containing layer. |
| US09627408B1 |
D flip-flop cells, with DFM-optimized M0 cuts and V0 adjacencies
A library of a DFM-improved standard logic cells (including D flip-flop cells) that avoid pattern-degrading configurations in the M0 and/or V0 layer(s) is disclosed, along with wafers, chips and systems constructed from such cells. |
| US09627405B1 |
Semiconductor device and manufacturing method thereof
A semiconductor device may include a multi-layered source layer, conductive patterns, interlayer insulating layers, and a channel pillar. The multi-layered source layer may include a lower source layer, an interlayer source layer, and an upper source layer. The conductive patterns and interlayer insulating layers may be alternately disposed on the multi-layered source layer. The channel pillar may penetrate the conductive patterns. The interlayer insulating layers, the upper source layer, and the interlayer source layer, the channel pillar may extend into the lower source layer. The channel pillar may be in contact with the interlayer source layer. Doped regions having various structures can be formed at a lower portion of the channel pillar, thereby improving the operational reliability of the semiconductor device. |
| US09627403B2 |
Multilevel memory stack structure employing support pillar structures
A first stack of alternating layers including first electrically insulating layers and first sacrificial material layers is formed with first stepped surfaces. First memory openings can be formed in a device region outside of the first stepped surfaces, and first support openings can be formed through the first stepped surfaces. The first memory openings and the first support openings can be filled with a sacrificial fill material. A second stack of alternating layers including second electrically insulating layers and second sacrificial material layers can be formed over the first stack. Inter-stack memory openings including the first memory openings can be formed in the device region, and inter-stack support openings including the first support openings can be formed in a steppes surface region. Memory stack structures and support pillar structure are simultaneously formed in the inter-stack memory openings and the inter-stack support openings, respectively. |
| US09627400B2 |
Nonvolatile semiconductor memory device and method for manufacturing same
According to one embodiment, a nonvolatile semiconductor memory device includes an interconnect layer, a stacked body, an insulating layer, a semiconductor pillar, a charge storage layer and a first conductive unit. The stacked body is separated from the interconnect layer in a first direction. The stacked body includes a memory unit and a selection gate provided between the memory unit and the interconnect layer. The insulating layer is provided between the interconnect layer and the stacked body. The semiconductor pillar pierces the stacked body in the first direction. The charge storage layer is provided between the semiconductor pillar and the memory unit. The first conductive unit connects the semiconductor pillar and the interconnect layer. A width of the first conductive unit along a second direction perpendicular to the first direction is wider than a width of the semiconductor pillar along the second direction. |
| US09627398B2 |
Method of manufacturing semiconductor device
A performance of a semiconductor device is improved. A film, which is made of silicon, is formed in a resistance element formation region on a semiconductor substrate, and an impurity, which is at least one type of elements selected from a group including a group 14 element and a group 18 element, is ion-implanted into the film, and a film portion which is formed of the film of a portion into which the impurity is ion-implanted is formed. Next, an insulating film with a charge storage portion therein is formed in a memory formation region on the semiconductor substrate, and a conductive film is formed on the insulating film. |
| US09627397B2 |
Memory device and method for fabricating the same
A memory device includes a semiconductor substrate, an isolation layer disposed on the semiconductor substrate, a first conductive layer disposed on the isolation layer, at least one contact plug passing through the isolation layer and electrically contacting the semiconductor substrate with the first conductive layer, a plurality of insulating layers disposed on the first conductive layer, a plurality of second conductive layers alternatively stacked with the insulating layers and insulated from the first conductive layer, a channel layer disposed on at least one sidewall of a first through opening and electrically contacting to the contact plug, wherein the first through opening passes through the insulating layers and the second conductive layers to expose the contact plug, and a memory layer disposed between the channel layer and the second conductive layers. |
| US09627396B2 |
Semiconductor device including a stack having a sidewall with recessed and protruding portions
A semiconductor device includes a substrate, a stack, and channel structures penetrating the stack. The stack includes gate electrodes and insulating layers alternately and repeatedly stacked on the substrate, and extending in a first direction. The channel structures in a first row are spaced apart from each other in the first direction. The stack includes a first sidewall that includes first recessed portions and first protruding portions. Each of first recessed portions is defined by an adjacent pair of the first recessed portions. Each of the first recessed portions has a shape recessed toward a first region of the stack between an adjacent pair of the channel structures of the first row. Each of the first recessed portions has a width that decreases in a direction toward the first region when measured along the first direction. |
| US09627393B2 |
Height reduction in memory periphery
A NAND flash memory has word lines in a memory array area and contact pads and lead lines in a word line hookup area, each of the word lines connected to a corresponding contact pad by a lead line. The word lines in the memory array area have a first height and low-profile areas of lead lines in the word line hookup area have a second height that is less than the first height. |
| US09627391B2 |
Non-volatile memory device
According to one embodiment, a non-volatile memory device includes electrodes, an interlayer insulating film, at least one semiconductor layer, conductive layers, first and second insulating films. The electrodes are arranged in a first direction. The interlayer insulating film is provided between the electrodes. The semiconductor layer extends in the first direction in the electrodes and the interlayer insulating film. The conductive layers are provided between each of the electrodes and the semiconductor layer, and separated from each other in the first direction. The first insulating film is provided between the conductive layers and the semiconductor layer. The second insulating film is provided between each of the electrodes and the conductive layers, and extends between each of the electrodes and the interlayer insulating film adjacent to the each of the electrodes. A width of the conductive layers in the first direction is narrower than that of the second insulating film. |
| US09627380B2 |
Semiconductor devices having work function adjusting films with chamfered top surfaces
A semiconductor device includes an interlayer insulating film formed on a substrate and including a trench, a gate insulating film formed in the trench, a work function adjusting film formed on the gate insulating film in the trench along sidewalls and a bottom surface of the trench, and including an inclined surface having an acute angle with respect to the sidewalls of the trench, and a metal gate pattern formed on the work function adjusting film in the trench to fill up the trench. |
| US09627378B2 |
Methods of forming FINFETs with locally thinned channels from fins having in-situ doped epitaxial cladding
In one aspect, a method of forming finFET devices is provided which includes patterning fins in a wafer; forming dummy gates over the fins; forming spacers on opposite sides of the dummy gates; depositing a gap fill oxide on the wafer, filling any gaps between the spacers; removing the dummy gates forming gate trenches; trimming the fins within the gate trenches such that a width of the fins within the gate trenches is less than the width of the fins under the spacers adjacent to the gate trenches, wherein u-shaped grooves are formed in sides of the fins within the gate trenches; and forming replacement gate stacks in the gate trenches, wherein portions of the fins adjacent to the replacement gate stacks serve as source and drain regions of the finFET devices. |
| US09627375B2 |
Indented gate end of non-planar transistor
In some embodiments, a semiconductor structure includes a substrate, a dielectric region, a non-planar structure and a gate stack. The dielectric region is formed on the substrate, and has a top surface. The non-planar structure protrudes from the top surface, and includes a channel region, and source and drain regions formed on opposite sides of the channel region. The gate stack is formed on the top surface, wraps around the channel region, and includes a gate top surface, and a gate side wall that does not intersect the non-planar structure. The gate side wall has a first distance from a vertical plane at a level of the top surface, and a second distance from the vertical plane at a level of the gate top surface. The vertical plane is vertical with respect to the top surface, and intersects the non-planar structure. The first distance is shorter than the second distance. |
| US09627374B2 |
Electronic circuits including a MOSFET and a dual-gate JFET
Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths. |
| US09627373B2 |
CMOS compatible fuse or resistor using self-aligned contacts
A semiconductor device includes dummy gate structures formed on a dielectric layer over a substrate and forming a gap therebetween. A trench silicide structure is formed in the gap on the dielectric layer and extends longitudinally beyond the gap on end portions. The trench silicide structure forms a resistive element. Self-aligned contacts are formed through an interlevel dielectric layer and land on the trench silicide structure beyond the gap on the end portions. |
| US09627371B1 |
Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and AA-short-configured, NCEM-enabled fill cells
An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of open-circuit and short-circuit failure modes, including at least one via-open-related failure mode, one GATE-short-related failure mode, one GATECNT-short-related failure mode, and one AA-short-related failure mode. |
| US09627359B2 |
Semiconductor device and manufacturing method of the same
Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers. |
| US09627358B2 |
Method for interconnecting stacked semiconductor devices
A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the corresponding rims. The one or more vias extend through the corresponding rims, and the one or more vias are in communication with the first and second dice through the rims. |
| US09627355B2 |
Package-on-package structure having polymer-based material for warpage control
A package on package structure providing mechanical strength and warpage control includes a first package component coupled to a second package component by a first set of conductive elements. A first polymer-comprising material is arranged between the first package component and the second package component. The first polymer-comprising material surrounds the first set of conductive elements and the second package component. A third package component is coupled to the second package component by a second set of conductive elements. An underfill is arranged on the second package component and surrounds the second set of conductive elements. The first polymer-comprising material extends past sidewalls of the underfill. |
| US09627352B2 |
Devices and methods for processing singulated radio-frequency units
Devices and methods for processing singulated radio-frequency (RF) units. In some embodiments, a device for processing singulated RF packages can include a plate having a plurality of apertures. Each aperture can be dimensioned to receive and position a singulated RF package to thereby facilitate processing of the singulated RF packages positioned in their respective apertures. In some embodiments, such a device can be utilized to batch process high volume of RF packages as if the RF packages are still in a panel format. |
| US09627350B2 |
Method for manufacturing semiconductor device
A method for manufacturing a semiconductor device according to the present invention includes: (a) disposing, on a substrate (insulating substrate), a bonding material having a sheet shape and having sinterability; (b) disposing a semiconductor element on the bonding material after the (a); and (c) sintering the bonding material while applying pressure to the bonding material between the substrate and the semiconductor element. The bonding material includes particles of Ag or Cu, and the particles are coated with an organic film. |
| US09627343B2 |
Power semiconductor module with switching device and assembly
A power semiconductor module and an arrangement including it. The module includes a housing, a switching device having a substrate connected to the housing, a connecting device, load connection devices and a pressure device movable relative to the housing. The substrate has a first central passage and conductor tracks which are electrically insulated from one another. A power semiconductor component sits on a conductor track. The connecting device has two main surfaces and an electrically conductive film. The pressure device has a pressure body with a second passage, in alignment with the first passage and a first recess. A pressure element projects out of the recess, and presses onto a section of the second main surface. This section is within the surface of the component projects normal to the substrate. The first and second passages receive a fastener which force-fittingly fastens the module to the cooling device. |
| US09627342B2 |
Electronic component and method of manufacturing electronic component
Plating pre-processing is carried out before carrying out a plating process on the surface of a conducting section provided on a semiconductor wafer. A first metal film is formed on the surface of the conducting section by NiP alloy plating process. A second metal film is formed on the surface of the first metal film by immersion Ag plating process. The semiconductor wafer is diced and cut into semiconductor chips. A conductive composition containing Ag particles is applied to the surface of the second metal film which is on the front surface of the semiconductor chip. A bonding layer containing Ag particles is formed by sintering the conductive composition through heating. A metal plate is then bonded to the surface of the second metal film via the bonding layer containing Ag particles. The electronic component has high bonding strength, excellent thermal resistance and heat radiation properties. |
| US09627340B2 |
Semiconductor device
According to one embodiment, a semiconductor device includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip outputs a first signal by a first bus width and includes a first via which transfers the first signal. The second semiconductor chip receives, by the first bus width, the first signal transferred through the first via. |
| US09627339B2 |
Method of forming an integrated circuit device including a pillar capped by barrier layer
A method of forming an integrated circuit device includes forming a mask layer overlying an under bump metallurgy (UBM) layer, wherein the mask layer comprises a first portion adjacent to the UBM layer, and a second portion overlying the first portion. The method further includes forming an opening in the mask layer to expose a portion of the UBM layer. The method further includes forming a conductive layer in the opening of the mask layer, electrically connected to the exposed portion of the UBM layer. The method further includes removing the second portion of the mask layer to expose an upper portion of the conductive layer. The method further includes forming a barrier layer on the exposed upper portion of the conductive layer. |
| US09627337B2 |
Integrated circuit device
An integrated circuit device including a semiconductor substrate, a first bonding pad structure, a second bonding pad structure, and an internal bonding wire is provided. The first bonding pad structure is disposed on a surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The second bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The first bonding pad structure is electrically coupled to the second bonding pad structure via the internal bonding wire. The integrated circuit device having a better electrical performance is provided by eliminating internal resistance drop in power supply trails or ground trails, and improving signal integrity of the integrated circuit device. |
| US09627334B2 |
Self-aligned under bump metal
An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with a solder ball formed on the self-aligned under bump metal pad. Processes of forming integrated circuits including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, by a process of forming one or more metal layers on the interconnect level and the dielectric layer, selectively removing the metal from over the dielectric layer, and subsequently forming a solder ball on the self-aligned under bump metal pad. Some examples include additional metal layers formed after the selective removal process, and may include an additional selective removal process on the additional metal layers. |
| US09627326B2 |
Method for forming alignment marks and structure of same
A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks. |
| US09627324B2 |
Apparatus and method for processing a substrate
A method of processing a substrate that displays out-gassing when placed in a vacuum comprises placing the substrate in a vacuum and performing an out-gassing treatment by heating the substrate to a temperature T1 and removing gaseous contamination emitted from the substrate until the out-gassing rate is determined by the diffusion of the substrate's contamination and thus essentially a steady state has been established. Afterwards, the temperature is lowered to a temperature T2 at which the diffusion rate of the substrate's contamination is lower than at T1. The substrate is further processed at said temperature T2 until the substrate has been covered with a film comprising a metal. |
| US09627320B2 |
Nanowires coated on traces in electronic devices
Methods and devices including the formation of a layer of nanowires on wiring line traces are described. One device comprises a first dielectric layer and a plurality of traces on the first dielectric layer, the traces comprising Cu. The traces include a layer of ZnO nanowires positioned thereon. A second dielectric layer is positioned on the first dielectric layer and on the traces, wherein the second dielectric layer is in direct contact with the ZnO nanowires. Other embodiments are described and claimed. |
| US09627314B2 |
Fuse structure and method of blowing the same
A fuse structure and a method of blowing the same are provided. The fuse structure includes a conductive line on a substrate, first and second vias on the conductive line that are spaced apart from each other, a cathode electrode line that is electrically connected to the first via, an anode electrode line that is electrically connected to the second via, and a dummy pattern that is adjacent at least one of the cathode and anode electrode lines and electrically isolated from the conductive line. |
| US09627312B2 |
On-chip capacitors and methods of assembling same
An on-chip capacitor a semiconductive substrate is fabricated in a passivation layer that is above the back-end metallization. At least three electrodes are configured in the on-chip capacitor and power and ground vias couple at least two of the at least three electrodes. The first via has a first-coupled configuration to at least one of the first- second- and third electrodes and the second via has a second-coupled configuration to at least one of the first- second- and third electrodes. |
| US09627311B2 |
Chip package, package substrate and manufacturing method thereof
A package substrate is provided. The package substrate includes: a dielectric layer; a passive component embedded in the dielectric layer and contacting the dielectric layer; and a circuit layer embedded in the dielectric layer and having a first surface aligned with a second surface of the dielectric layer. |
| US09627305B2 |
Semiconductor module with interlocked connection
A semiconductor package includes a support substrate having opposing first and second main surfaces and sides between the first and second main surfaces, a semiconductor die attached to one of the main surfaces of the support substrate, and an encapsulation material at least partly covering the support substrate and the semiconductor die. A protrusion extends outward from a side of the support substrate and terminates in the encapsulation material. The protrusion forms an interlocked connection with the encapsulation material. The interlocked connection increases the tensile strength of the interface between the encapsulation material and the side of the support substrate with the protrusion. |
| US09627304B2 |
Method of producing a large number of support apparatus which can be surface-mounted, arrangement of a large number of support apparatus which can be surface-mounted, and support apparatus which can be surface-mounted
A method of producing a multiplicity of surface-mountable carrier devices includes: A) providing a carrier plate having a first main face and a second main face located opposite the first main face, B) applying an electrically conductive layer to the first main face, C) applying a solder resist mask to a side of the electrically conductive layer remote from the carrier plate, wherein a multiplicity of adjoining regions are formed on the electrically conductive layer by the solder resist mask, D) applying a solder material to the solder resist mask and the electrically conductive layer, wherein the solder resist mask and the electrically conductive layer are at least partially covered by the solder material, and E) singulating the carrier plate and the electrically conductive layer along and through the solder resist mask and the solder material, wherein the solder material remains at least partially on the solder resist mask. |
| US09627302B2 |
Power semiconductor device
An object is to provide a technique in which a cost reduction in a power semiconductor device can be achieved while maintaining heat dissipation performance as much as possible. A power semiconductor device includes a leadframe, a power semiconductor element disposed on an upper surface of the leadframe, and an insulating layer disposed on a lower surface of the leadframe. At least a partial line of a peripheral line of a region where the insulating layer is disposed, on the lower surface, is aligned, in top view, with at least a partial line of an expanded peripheral line obtained by shifting outwardly, by the amount corresponding to the thickness of the leadframe, the peripheral line of the region where the power semiconductor element is disposed, on the upper surface. |
| US09627301B2 |
Integrated circuit arrangement
An integrated circuit arrangement includes a flange, a transistor die, and a first conducting element defining a lead. The flange includes a conducting material and the transistor die is disposed on a surface of the flange. The first conducting element is electrically connected to the transistor die via connecting elements to allow current flow from the transistor die. The flange defines return current paths allowing the current flow via the connecting elements and the lead to return to the transistor die. The flange includes one or more reduced thickness portions that are configured to limit the return current paths and control current flow passing through the flange to the transistor die. |
| US09627300B2 |
Amplifier package with multiple drain bonding wires
An amplifier includes a package, a transistor chip having a gate pad and a drain pad formed elongately, the transistor chip being provided in the package, and a plurality of drain bonding wires connected to the drain pad, wherein the plurality of drain bonding wires include a first outer-most bonding wire connected to one of two end portions of the drain pad, a second outer-most bonding wire connected to the other of the two end portions of the drain pad, and an intermediate bonding wire interposed between the first outer-most bonding wire and the second outer-most bonding wire, each of the plurality of drain bonding wires is longer than 1 mm, and the first outer-most bonding wire and the second outer-most bonding wire have loop heights larger than a loop height that the intermediate bonding wire has. |
| US09627297B2 |
Solder flow-impeding plug on a lead frame
Embodiments described herein relate to a packaged component including a lead frame and a non-conductive plug disposed between two or more adjacent sections of the lead frame. The plug is composed of a non-conductive material functions to impede the flow of solder along edges of the two or more adjacent sections during second level solder reflow events that occur after encapsulation of the packaged component. The plug includes a main portion disposed within a space between the two or more adjacent sections, and one or more overlap portions extending from the main portion. The one or more overlap portions are disposed on an internal surface of at least one of the two or more adjacent sections. At least one component is mounted on one of the plurality of sections of the lead frame. |
| US09627295B2 |
Devices, systems and methods for manufacturing through-substrate vias and front-side structures
Methods of manufacturing semiconductor devices and semiconductor devices with through-substrate vias (TSVs). One embodiment of a method of manufacturing a semiconductor device includes forming an opening through a dielectric structure and at least a portion of a semiconductor substrate, and forming a dielectric liner material having a first portion lining the opening and a second portion on an outer surface of the dielectric structure laterally outside of the opening. The method further includes removing the conductive material such that the second portion of the dielectric liner material is exposed, and forming a damascene conductive line in the second portion of the dielectric liner material that is electrically coupled to the TSV. |
| US09627288B2 |
Package structures and methods of forming the same
Package structures and methods of forming the same are disclosed. A package structure includes a die, a dielectric layer, an encapsulant and a plurality of supports. The die includes, over a first side thereof, a plurality of connectors. The dielectric layer is formed over the first side of the die aside the connectors. The encapsulant is aside the die. The supports penetrate through the dielectric layer. The grinding rate of the supports is substantially the same as that of the encapsulant but different from that of the dielectric layer. |
| US09627287B2 |
Thinning in package using separation structure as stop
A method of forming a thinned encapsulated chip structure, wherein the method comprises providing a separation structure arranged within an electronic chip, encapsulating part of the electronic chip by an encapsulating structure, and thinning selectively the electronic chip partially encapsulated by the encapsulating structure so that the encapsulating structure remains with a larger thickness than the thinned electronic chip, wherein the separation structure functions as a thinning stop. |
| US09627285B2 |
Package substrate
A package substrate is disclosed. The package substrate includes a molding layer, a redistribution structure, and a build-up structure. The redistribution structure is embedded in the molding layer with a surface exposed by the molding layer. The build-up structure is formed on the bottom surface of the molding layer. An inner stress caused by a CTE difference between different materials in the package substrate is reduced by forming at least one groove which is arranged around the periphery of the redistribution structure onto the top surface of the molding layer, thereby improving the problem of the redistribution structure cracking in the prior art. |
| US09627283B2 |
Display device
In a liquid crystal display device it is desirable to test in the state of TFT substrates, without reducing the number of TFT substrates to be obtained from one mother TFT substrate, and without increasing the overall size of the TFT substrates. Test terminals are formed on the outside of terminals for driving the liquid crystal display device. The test terminals of the specific TFT substrate are formed in another TFT substrate just below the specific TFT substrate. The area in which the test lines are formed is a space in which a sealing material is formed, between the display area and an end of the lower TFT substrate. Thus, the size of the TFT substrates is not actually increased. A test line area is not separately formed and not discarded, so that the number of TFT substrates to be obtained from one mother TFT substrate is not reduced. |
| US09627282B2 |
Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device includes: forming lower-layer wirings for a transistor, a circuit element and a plurality of contact pads on a substrate independently of each other; forming a first feed layer over an entire surface of the substrate on which the lower-layer wirings are formed; patterning the first feed layer to form a test pattern connecting terminals of the transistor to the separate contact pads independently of the circuit element; making a test on the transistor in a stand-alone state by using the contact pad and the test pattern; and after the test, connecting the transistor and the circuit element to form a circuit. |
| US09627281B2 |
Semiconductor chip with thermal interface tape
A method of manufacturing is provided that includes applying a thermal interface tape to a side of a semiconductor wafer that includes at least one semiconductor chip. The thermal interface material tape is positioned on the at least one semiconductor chip. The at least one semiconductor chip is singulated from the semiconductor wafer with at least a portion of the thermal interface tape still attached to the semiconductor chip. |
| US09627277B2 |
Method and structure for enabling controlled spacer RIE
A method and structure to enable reliable dielectric spacer endpoint detection by utilizing a sacrificial spacer fin are provided. The sacrificial spacer fin that is employed has a same pitch as the pitch of each semiconductor fin and the same height as the dielectric spacers on the sidewalls of each semiconductor fin. Exposed portions of the sacrificial spacer fin are removed simultaneously during a dielectric spacer reactive ion etch (RIE). The presence of the sacrificial spacer fin improves the endpoint detection of the spacer RIE and increases the endpoint signal intensity. |
| US09627276B2 |
Self-aligned low defect segmented III-V finFET
A method includes forming one or more fin structures on a substrate, the one or more fin structures comprising a first material comprising a first lattice structure and the substrate comprising a second material comprising a second lattice structure. Forming the one or more fin structures on the substrate includes forming one or more trenches in the substrate, and growing the first material in the one or more trenches. The first lattice structure is different from the second lattice structure. The one or more fin structures are self-aligned by the one or more trenches. |
| US09627272B2 |
Patterning scheme to minimize dry/wets strip induced device degradation
A patterning scheme to minimize dry/wet strip induced device degradation and resultant devices are provided. The method includes removing a workfunction material over a first device area of a structure, while protecting the workfunction material over a second device area of the structure with a first masking material. The method further includes applying a second masking material over the first device area and the first masking material. The method further includes removing the first masking material and the second masking material until the workfunction material is exposed over the second device area. |
| US09627270B2 |
Dual work function integration for stacked FinFET
A three-dimensional stacked fin complementary metal oxide semiconductor (CMOS) device having dual work function metal gate structures is provided. The stacked fin CMOS device includes a fin stack having a first semiconductor fin over a substrate, a dielectric fin atop the first semiconductor fin and a second semiconductor fin atop the dielectric fin, and a gate sack straddling the fin stack. The gate stack includes a first metal gate portion surrounding a channel portion of the first semiconductor fin and a second metal gate portion surrounding a channel portion of the second semiconductor fin. The first metal gate portion has a first work function suitable to reduce a threshold voltage of a field effect transistor (FET) of a first conductivity type, while the second gate portion has a second work function suitable to reduce a threshold voltage of a FET of a second conductivity type opposite the first conductivity type. |
| US09627268B2 |
Method for fabricating semiconductor device
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon and a shallow trench isolation (STI) around the fin-shaped structure, in which the fin-shaped structure has a top portion and a bottom portion; forming a first doped layer on the STI and the top portion; and performing a first anneal process. |
| US09627264B2 |
Semiconductor device and formation thereof
A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a doped region, in some embodiments. The semiconductor device includes a gate over a channel portion of the fin. The gate including a gate electrode over a gate dielectric between a first sidewall spacer and a second sidewall spacer. The first sidewall spacer includes an initial first sidewall spacer over a first portion of a dielectric material. The second sidewall spacer includes an initial second sidewall spacer over a second portion of the dielectric material. |
| US09627255B1 |
Semiconductor device package substrate having a fiducial mark
A method for forming a semiconductor device package substrate including a fiducial mark is provided. The method of forming the package substrate includes forming a dielectric layer over a lower portion of the package substrate. A metal layer is formed over a fiducial region of the package substrate. The metal layer is etched to form a first signal line in the fiducial region. A passivation layer is formed over the first signal line. The passivation layer is etched over the first signal line to form a fiducial mark. |
| US09627253B2 |
Semiconductor device including air gaps and method of fabricating the same
A semiconductor device including air gaps and a method of fabricating the same. The semiconductor device in accordance with an embodiment may include a bit line structure having a bit line formed over a first contact plug, a second contact plug formed adjacent to the first contact plug and the bit line structure, an air gap structure comprising two or more air gaps to surround the second contact plug and have an outer sidewall in contact with the bit line structure, and one or more capping support layers separating the air gaps, a third contact plug capping a part of the air gap structure and being formed over the second contact plug, and a capping layer for capping a remainder of the air gap structure. |
| US09627251B2 |
Forming array contacts in semiconductor memories
Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts. |
| US09627250B2 |
Method and apparatus for back end of line semiconductor device processing
A via opening comprising an etch stop layer (ESL) opening and methods of forming the same are provided which can be used in the back end of line (BEOL) process of IC fabrication. A metal feature is provided with a first part within a dielectric layer and with a top surface. An ESL is formed with a bottom surface of the ESL above and in contact with the dielectric layer, and a top surface of the ESL above the bottom surface of the ESL. An opening at the ESL is formed exposing the top surface of the metal feature; wherein the opening at the ESL has a bottom edge of the opening above the bottom surface of the ESL, a first sidewall of the opening at a first side of the metal feature, and a second sidewall of the opening at a second side of the metal feature. |
| US09627245B2 |
Methods of forming alternative channel materials on a non-planar semiconductor device and the resulting device
One illustrative method disclosed herein involves, among other things, forming trenches to form an initial fin structure having an initial exposed height and sidewalls, forming a protection layer on at least the sidewalls of the initial fin structure, extending the depth of the trenches to thereby define an increased-height fin structure, with a layer of insulating material over-filling the final trenches and with the protection layer in position, performing a fin oxidation thermal anneal process to convert at least a portion of the increased-height fin structure into an isolation material, removing the protection layer, and performing an epitaxial deposition process to form a layer of semiconductor material on at least portions of the initial fin structure. |
| US09627241B2 |
Resin sheet attaching method
A resin sheet attaching method of attaching a resin sheet to a workpiece. The resin sheet attaching method includes a molecular weight reducing step of applying vacuum ultraviolet radiation to the front side of the resin sheet, thereby cutting an intermolecular bond in a surface region having a depth of tens of nanometers from the front side of the resin sheet to thereby reduce the molecular weight of the surface region and produce an adhesive force, and a resin sheet attaching step of attaching the front side of the resin sheet to the workpiece after performing the molecular weight reducing step. |
| US09627239B2 |
Wafer surface 3-D topography mapping based on in-situ tilt measurements in chemical vapor deposition systems
The surface topography of at least one wafer can be determined in-situ based on deflectometer measurements of surface tilt. The deflectometer is re-positioned by a scanning positioner to facilitate tilt mapping of the wafer surface for each of the at least one wafer. A surface height mapping engine is configured to generate a three-dimensional topographic mapping of the surface of each of the at least one wafer based on the mapping of the tilt. |
| US09627237B2 |
Apparatus, method and non-transitory storage medium for accommodating and processing a substrate
A substrate accommodating and processing apparatus is provided with a cassette mounting table, a processing part, a substrate transfer mechanism, a partition wall, a cassette stage, and a lid attaching/detaching mechanism. The lid attaching/detaching mechanism is provided with a key configured to be engaged with a key hole installed in the lid, and configured to switch a latch between locking and unlocking positions. The mechanism is also provided with a lid abnormality detecting sensor, a lid attaching/detaching mechanism closing sensor, a lid attaching/detaching mechanism opening sensor, a pressure sensor and a control part. |
| US09627236B2 |
Substrate treating apparatus
A substrate treating apparatus is provided which includes housing and a door assembly. The housing provides a process space for treating a substrate therein and has an opening formed at a sidewall thereof. The door assembly opens and closes the opening. The door assembly includes a shutter, a driving member, and a gap maintaining unit. The driving member transfers the shutter to an open position where the shutter faces to the opening and to a blocking position where the shutter gets out of the open position. The gap maintaining unit maintains a constant gap between the shutter and the sidewall. |
| US09627226B2 |
Fabrication method of semiconductor package
A fabrication method of a semiconductor package is disclosed, which includes the steps of: disposing a plurality of first semiconductor elements on an interposer; forming a first encapsulant on the interposer for encapsulating the first semiconductor elements; disposing a plurality of second semiconductor elements on the first semiconductor elements; forming a second encapsulant on the first semiconductor elements and the first encapsulant for encapsulating the second semiconductor elements; and thinning the interposer, thereby reducing the overall stack thickness and preventing warpage of the interposer. |
| US09627224B2 |
Semiconductor device with sloped sidewall and related methods
A semiconductor device may include a multi-layer interconnect board having in stacked relation a lower conductive layer, a dielectric layer, and an upper conductive layer. The dielectric layer may have a recess formed with a bottom and sloping sidewall extending upwardly from the bottom. The upper conductive layer may include upper conductive traces extending across the sloping sidewall, and the lower conductive layer may include lower conductive traces. The semiconductor device may include vias extending between the lower and upper conductive layers, an IC carried by the multi-layer interconnect board in the recess, bond wires coupling upper conductive traces to the IC, and encapsulation material adjacent the IC and adjacent portions of the multi-layer interconnect board. |
| US09627223B2 |
Methods and apparatus of packaging with interposers
Methods and apparatus for forming a semiconductor device package on an interposer using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, where a micro-bump is used as a vertical connection between a die and the interposer, and a micro-bump line is used as a horizontal connection for signal transmission between different dies above the interposer. The micro-bump lines may be formed at the same time as the formation of the micro-bumps with little or no additional cost. |
| US09627222B2 |
Method for fabricating nitride semiconductor device with silicon layer
A method for fabricating a semiconductor device including: forming a silicon layer on an upper face of a nitride semiconductor layer including a channel layer of a FET; thermally treating the nitride semiconductor layer in the process of forming the silicon layer or after the process of forming the silicon layer; and forming an insulating layer on an upper face of the silicon layer after the process of forming the silicon layer. |
| US09627221B1 |
Continuous process incorporating atomic layer etching
A method of continuous fabrication of a layered structure on a substrate having a patterned recess, includes: (i) forming a dielectric layer on a substrate having a patterned recess in a reaction chamber by PEALD using a first RF power; (ii) continuously after completion of step (i) without breaking vacuum, etching the dielectric layer on the substrate in the reaction chamber by PEALE using a second RF power, wherein a pressure of the reaction chamber is controlled at 30 Pa to 1,333 Pa throughout steps (i) and (ii); a noble gas is supplied to the reaction chamber continuously throughout steps (i) and (ii); and the second RF power is higher than the first RF power. |
| US09627209B2 |
Method for producing a semiconductor
A method for producing a semiconductor is disclosed, the method having: providing a semiconductor body having a first side and a second side; forming an n-doped zone in the semiconductor body by a first implantation into the semiconductor body via the first side to a first depth location of the semiconductor body; and forming a p-doped zone in the semiconductor body by a second implantation into the semiconductor body via the second side to a second depth location of the semiconductor body, a pn-junction forming between said n-doped zone and said p-doped zone in the semiconductor body. |
| US09627208B2 |
Semiconductor switch
According to an embodiment, a semiconductor switch includes a first insulating film on a semiconductor substrate, a first semiconductor layer on the first insulating film, a semiconductor switch circuit on the first semiconductor layer, and a wiring on the first insulating film. The first insulating film being between the wiring and the substrate. The wiring connects the semiconductor switch circuit and a terminal. A polycrystalline semiconductor layer is between the wiring and the first insulating film. |
| US09627207B2 |
Methods of forming semiconductor device having gate electrode
Methods of forming a semiconductor device are provided. An active region is formed on a substrate. A temporary gate crossing the active region and a capping pattern covering the temporary gate are formed. Spacers are formed on sidewalls of the temporary gate. A growth-blocking layer is locally formed in an upper edge of the temporary gate. A source/drain region is formed on the active region adjacent to the temporary gate. The capping pattern, the first growth-blocking layer, and the temporary gate are removed to expose the active region. A gate electrode is formed on the exposed active region. |
| US09627205B2 |
Method of manufacturing a semiconductor device using purified block copolymers and semiconductor devices
In a method of manufacturing a semiconductor device, a blend solution that includes a block copolymer and an adsorbent is prepared. The block copolymer is synthesized by a copolymerization between a first polymer unit and a second polymer unit having a hydrophilicity greater than that of the first polymer unit. The adsorbent on which the block copolymer is adsorbed is extracted. The block copolymer is separated from the adsorbent. The block copolymer is collected. The block copolymer may be used to form a mask on an object layer on a substrate and the mask used to etch the object layer. |
| US09627204B2 |
Composition for forming a coating type BPSG film, substrate formed a film by said composition, and patterning process using said composition
The present invention provides a composition for forming a coating type BPSG film, which comprises: one or more structures comprising a silicic acid represented by the following general formula (1) as a skeletal structure, one or more structures comprising a phosphoric acid represented by the following general formula (2) as a skeletal structure and one or more structures comprising a boric acid represented by the following general formula (3) as a skeletal structure. There can be provided a composition for forming a coating type BPSG film which is excellent in adhesiveness in fine pattern, can be easily wet etched by a peeling solution which does not cause any damage to the semiconductor apparatus substrate, the coating type organic film or the CVD film mainly comprising carbon which are necessary in the patterning process, and can suppress generation of particles by forming it in the coating process. |
| US09627199B2 |
Methods of fabricating micro- and nanostructure arrays and structures formed therefrom
Methods of fabricating micro- and nanostructures comprise top-down etching of lithographically patterned GaN layer to form an array of micro- or nanopillar structures, followed by selective growth of GaN shells over the pillar structures via selective epitaxy. Also provided are methods of forming micro- and nanodisk structures and microstructures formed from thereby. |
| US09627196B2 |
Method for processing a carrier
According to various embodiments, a method for processing a carrier may include: co-depositing at least one metal from a first source and carbon from a second source over a surface of the carrier to form a first layer; forming a second layer over the first layer, the second layer including a diffusion barrier material, wherein the solubility of carbon in the diffusion barrier material is less than in the at least one metal; and forming a graphene layer at the surface of the carrier from the first layer by a temperature treatment. |
| US09627190B2 |
Energy resolved time-of-flight mass spectrometry
A time-of-flight mass spectrometer (TOF-MS) utilizes an ion dispersion device and a position-sensitive ion detector or an energy-sensitive ion detector to enable measurement of time of flight and kinetic energy of ions arriving at the detector. The measurements may be utilized to improve accuracy in calculating ion masses. |
| US09627189B2 |
Vacuum system
The invention concerns a vacuum system, comprising a first vacuum chamber and a second vacuum chamber, the first vacuum chamber being evacuated by a first vacuum pump, in particular a turbomolecular pump, the first and the second vacuum chamber being connected by a passage, wherein the passage is surrounded by a sealing arrangement comprising an inner seal and an outer seal with a plenum positioned between the inner seal and the outer seal, the plenum being evacuated by a support vacuum pump, and wherein at least one sealing face of the inner seal consists of the wall material of the first or the second vacuum chamber, in particular the inner seal being formed by direct contact between the wall material of the first vacuum chamber and the wall material of the second vacuum chamber. Additionally, the invention concerns a mass spectrometry system. |
| US09627188B2 |
Method and system for the quantitative chemical speciation of heavy metals and other toxic pollutants
This invention relates to systems and methods for measuring quantitatively multiple species or heavy metals, including mercury, and other toxic pollutants. More specifically, the systems and methods of the invention allows for determination of the analytes even at very low concentration, through concentration on a collection interface, desorption and analysis by mass spectrometry. The invention also provides for a portable device or kit for modifying an existing mass spectrometer. |
| US09627186B2 |
System, method and apparatus for using optical data to monitor RF generator operations
A system and method monitoring a plasma with an optical sensor to determine the operations of a pulsed RF signal for plasma processing including a plasma chamber with an optical sensor directed toward a plasma region. An RF generator coupled to the plasma chamber through a match circuit. An RF timing system coupled to the RF generator. A system controller is coupled to the plasma chamber, the RF generator, the optical sensor, the RF timing system and the match circuit. The system controller includes a central processing unit, a memory system, a set of RF generator settings and an optical pulsed plasma analyzer coupled to the optical sensor and being capable to determine a timing of a change in state of an optical emission received in the optical sensor and/or a set of amplitude statistics corresponding to an amplitude of the optical emission received in the optical sensor. |
| US09627185B2 |
Methods and apparatus for in-situ cleaning of a process chamber
Methods and apparatus for in-situ cleaning of substrate processing chambers are provided herein. A substrate processing chamber may include a chamber body enclosing an inner volume; a chamber lid removably coupled to the chamber body and including a first flow channel fluidly coupled to the inner volume to selectively open or seal the inner volume to or from a first outlet; a chamber floor including a second flow channel fluidly coupled to the inner volume to selectively open or seal the inner volume to or from a first inlet; and a pump ring disposed in and in fluid communication with the inner volume, the pump ring comprising an upper chamber fluidly coupled to a lower chamber, and a second outlet fluidly coupled to the lower chamber to selectively open or seal the inner volume to or from the second outlet. |
| US09627178B2 |
Charged particle beam drawing apparatus, information processing apparatus and pattern inspection apparatus
A charged particle beam drawing apparatus of an embodiment includes: a graphic information file for storing graphic information for each of elements (for example, patterns) at a level underlying an element (for example, a cell) at a particular level in hierarchically-structured drawing data which has elements at each level; and an attribute information file for storing attribute information to be given to each of the elements at the underlying level in association with information (for example, an index number) on the element at the particular level. |
| US09627173B2 |
Stage device and charged particle beam apparatus using the stage device
To attain the above object, in the present invention, proposed are a stage apparatus including a sample stage that mounts a sample, a first position detection device that detects a position of the sample stage, a second position detection device that detects a position of the sample stage when the sample stage is positioned in a part of a stage movement range that the first position detection device is capable of detecting, and a control device that adjusts an offset amount of the first position detection device on the basis of a position detection result obtained by the second position detection device, and a charged particle beam apparatus using the stage apparatus. |
| US09627170B2 |
Electrode for use in ion implantation apparatus and ion implantation apparatus
An electrode for use in an ion implantation system includes a body portion and a penetration portion. The penetration portion includes penetration holes which are closely and regularly arranged. The penetration holes have the shape of a circle or a regular polygon with at least four sides. The electrode has an increased aperture ratio which, in turn, increases the density of the ion beam, thereby improving the efficiency of the ion implantation process. |
| US09627167B2 |
Apparatus for generating plasma
Provided herein an apparatus for generating plasma, the apparatus including a nozzle array, first electrode, and housing. The nozzle discharges plasma. The first electrode is disposed to surround the nozzle array. The housing is disposed to surround the nozzle array and first electrode. The nozzle includes a plurality of nozzles disposed adjacent to one another and in the form of an array, each nozzle configured to discharge plasma. Therefore, it is possible to generate a large size plasma evenly and stably. |
| US09627165B2 |
Circuit breaker tripping shaft with over-molded levers
A tripping shaft apparatus for a circuit breaker. Tripping shaft apparatus includes a rigid shaft portion and a polymer shaft portion molded onto the rigid shaft portion, wherein the polymer shaft portion includes a first molded lever. At least one other lever is a part of the tripping shaft apparatus. A torsion spring is received over the shaft between the first molded lever and the second lever providing an integral torsion spring positioned between the levers. Circuit breaker tripping assemblies and methods of assembling a circuit breaker tripping assembly are provided, as are other aspects. |
| US09627162B1 |
Finger activated mouse device/switching device
The embodiments herein show a switching device/mouse device activated by proximal phalanx of a finger(s). The switching device/mouse is ergonomically designed to prevent carpal-tunnel effect and bending of fingers. The switching device/mouse includes an enclosure having a top wall, a bottom wall, and sidewalls. The switching device/mouse includes an upper levers/elongated buttons pivotally supported by the top wall. The upper levers/elongated buttons are elevated surfaces to better support a user's fingers in a rest position. The mouse is operated by pressing down on the elevated surfaces of the upper levers with the proximal phalanx of the fingers without bending the fingers. |
| US09627160B1 |
Systems and methods for rotary knob friction adjustment control
A circuit breaker including a trip unit having an internal support and a friction adjustment control system for knob control is provided. The internal support includes a first opening to receive a first rotary knob having one or more first smooth rings and a second opening to receive a second rotary knob having one or more second smooth rings. The trip unit includes a first knob control of the first rotary knob. The first knob control includes a first structural support, a first housing and a first spring installed in the first housing against the first structural support. The trip unit further includes a second knob control of the second rotary knob. The second knob control includes a second structural support, a second housing and a second spring installed in the second housing against the second structural support. |
| US09627158B2 |
Keyboard key using an asymmetric scissor-type connecting element
A keyboard module includes a first key and a second key. The first key includes a first keycap and a first scissors-type connecting element. The first scissors-type connecting element includes a first outer frame and a first inner frame. The second key includes a second keycap and a second scissors-type connecting element. The second scissors-type connecting element includes a second outer frame and a second inner frame. The first outer frame, the first inner frame and the second inner frame have symmetrical structures. The second outer frame has an asymmetrical structure. |
| US09627156B2 |
Snap-action switch
A snap-action switch has at least two switching contacts, at least one flexible circuit carrier carrying conductor tracks and at least one multifunction component receiving the flexible circuit carrier. The switching contacts and the conductor tracks are connected with each other via a non-detachable connection. The region of the flexible circuit carrier between the switching contacts is configured as a bending tab. |
| US09627153B2 |
Electrical medium or high voltage switching device
An electrical switching device for medium or high voltage circuits having at least a nominal contact arrangement, wherein the nominal contact arrangement includes at least a first nominal contact including a plurality of contact fingers forming a finger cage concentric with respect to a longitudinal axis, wherein the contact fingers are separated from one another by empty slots extending up to a free end of the contact fingers. The empty slots include first and second empty slots, wherein the second empty slots are shorter than the first empty slots, and wherein the contact fingers are grouped in groups, with the contact fingers of each group being separated by second empty slots and the contact fingers of adjacent groups being separated by first empty slots. |
| US09627152B2 |
Low resistance electrode for electric dual layer capacitor and method of manufacturing the same
A low resistance electrode includes a through type aluminum sheet, a plurality of first hollow protrusion members protruded to one side of the through type aluminum sheet, a plurality of second hollow protrusion members protruded to the other side of the through type aluminum sheet, a conductive adhesive layer coated on a first surface and second surface of the through type aluminum sheet, a first active material sheet bonded to the first surface of the through type aluminum sheet, and a second active material sheet bonded to the second surface of the second surface of the through type aluminum sheet. |
| US09627151B2 |
Electrical storage module
An electrical storage module in which a plurality of electricity storage elements are electrically connected by conductive member, includes: a voltage detection board having voltage detection conductor that detects terminal voltage of the electricity storage element; a first external threaded component that connects the voltage detection conductor of the voltage detection board to the conductive member; and a cover that covers the voltage detection board; wherein: the cover is made from an insulating material; the conductive member has a first internal threaded portion into which the first external threaded component is to be screwingly engaged; and the distance between the inside surface of the cover that faces a head portion of the first external threaded component and an upper surface of the head portion of the first external threaded component is shorter than the distance between an end portion of the first internal threaded portion towards the cover side and an end of shaft portion of the first external threaded component. |
| US09627147B2 |
Composition and method for forming electroactive coating comprising conjugated heteroaromatic polymer, capacitor and antistatic object comprising the electroactive coating, and solid electrolytic capacitor and method for fabricating the same
A composition for forming an electroactive coating is described, including an acid as a polymerization catalyst, at least one functional component, and at least one compound of formula (1) as a monomer: wherein X is selected from S, O, Se, Te, PR2 and NR2, Y is hydrogen (H) or a precursor of a good leaving group Y− whose conjugate acid (HY) has a pKa of less than 30, Z is hydrogen (H), silyl, or a good leaving group whose conjugate acid (HY) has a pKa of less than 30, b is 0, 1 or 2, each R1 is a substituent, and the at least one compound of formula (1) includes at least one compound of formula (1) with Z═H and Y≠H. |
| US09627145B2 |
Electrolytic capacitor for use in a charge/discharge circuit with shorter period and greater voltage difference
An electrolytic capacitor according to the present invention employs a capacitor element wherein an anode foil having an anode internal terminal and a cathode foil having a cathode internal terminal are wound or laminated through a separator. The end of the anode foil faces with the cathode foil through the separator and the surface area of the cathode internal terminal is provided with an enlargement treatment, whereby the small area portion of the cathode foil that faces with the anode foil is eliminated, and the charge/discharge characteristics are thus improved. Furthermore, in the electrolytic capacitor provided with the capacitor element wherein the anode foil having the anode internal terminal and the cathode foil having the cathode internal terminal are wound or laminated through the separator, the capacitor element being impregnated with an electrolyte, the cathode internal terminal is composed of an aluminum material, the surface of the cathode internal terminal is etched and the concentration of iron in the etching layer is less than 300 ppm. |
| US09627141B2 |
Ceramic multi-layered capacitor
A ceramic multi-layer capacitor includes a main body, which has ceramic layers arranged along a layer stacking direction to form a stack, and first and second electrode layers arranged between the ceramic layers. The multi-layer capacitor also includes a first external contact-connection arranged on a first side surface of the main body and electrically conductively connected to the first electrode layers, and a second external contact-connection arranged on a second side surface (62) of the main body (2). The second side surface is situated opposite the first side surface and is electrically conductively connected to the second electrode layers. |
| US09627139B2 |
Multilayered ceramic capacitor and board for mounting the same
There is provided a multilayered ceramic capacitor including: a ceramic body in which a plurality of dielectric layers are stacked; an active layer including a plurality of first and second internal electrodes formed to be alternately exposed to both end surfaces of the ceramic body, having the dielectric layer interposed therebetween, to form capacitance; an upper cover layer formed above the active layer, a lower cover layer formed below the active layer and being thicker than the upper cover layer; and first and second external electrodes formed to cover both end surfaces of the ceramic body, wherein a ratio of an area Y of a region overlapped between the first and second internal electrodes to a total area X of the active layer and the upper cover layer on a cross section of the ceramic body in length-thickness (L-T) directions is in a range of 0.5 to 0.9. |
| US09627138B1 |
Apparatus and associated methods for capacitors with improved density and matching
Apparatus for integrated capacitors and associated methods are disclosed. In one embodiment, an integrated capacitor includes a first plurality of metal members that are fabricated using a first plurality of metal layers, and are oriented in a first orientation. The integrated capacitor also includes a second plurality of metal members that are fabricated using a second plurality of metal layers. The second plurality of metal members are oriented transverse to the first orientation. The integrated capacitor further includes a third plurality of metal members, which are fabricated using a third plurality of metal layers, and are oriented in the first orientation. |
| US09627135B2 |
Laminated ceramic capacitor
A ceramic capacitor having dielectric ceramic layers that include Ba, Re (Re is at least one of La, Ce, Pr, Nd, and Sm), Ti, Zr, M (M is at least one of Mg, Al, Mn, and V), Si, and optionally Sr, where at least some of the Ba, Re, Ti, and Zr and optionally Sr are in the form of a perovskite compound. Respective amounts, expressed as parts by mol, of the elements of the dielectric ceramic layers satisfy, with respect to a total of 100 of the Ti amount and the Zr amount, 0≦a≦20.0 where a is the Sr amount; 0.5≦b≦10.0 where b is the Re amount; 46≦c≦90 where c is the Zr amount; 0.5≦d≦10.0 where d is the M amount; 0.5≦e≦5.0 where e is the Si amount; and 0.990≦m≦1.050 where m is a ratio of a total of the Ba amount, the Sr amount, and the Re amount, to the total of the Ti amount and the Zr amount. |
| US09627131B2 |
Multilayer ceramic capacitor having an intermitting part
A multilayer ceramic capacitor includes: a ceramic body; first and second internal electrodes disposed so as to be alternately exposed to both end surfaces of the ceramic body with each of dielectric layers; first and second external electrodes formed so as to be extended onto portions of one main surface of the ceramic body, respectively; third and fourth external electrodes formed on both side surfaces of the ceramic body, respectively, so as to be extended onto portions of both main surfaces of the ceramic body, respectively; an intermitting part connecting the third and fourth external electrodes to one another; first and second land patterns formed so as to be connected to the first and third external electrodes, respectively; and a third land pattern formed so as to be connected to both of the second and fourth external electrodes. |
| US09627130B2 |
Magnetic connection and alignment of connectible devices
A first and second electronic device each including a connection surface and a magnetic element. The first and second devices may be in contact along the respective connection surfaces. The magnetic elements may be configured to align the first and second devices by moving either or both of the first and second devices relative to each other to achieve an aligned position. The magnetic element may also be operative to resist disconnection of first and second electronic devices when in the aligned position. |
| US09627127B2 |
High-efficiency, energy-saving device for inserting between a power source and a motive and/or lighting power load
An energy-saving device (1) inserted between a three-phase power supply (A) and a three-phase load (L), includes a three-phase electrical transformer (10), each phase of which includes a transformation assembly (11) with a primary winding (2) connected at a first end (5) to one phase of the power supply (A) and electromagnetically coupled to a secondary winding (3) connected at its second end (S1) to one phase of the load (L). The device (1) involves the second ends (6) of the primary windings (2) in each of the transformation assemblies (11), lying opposite the first ends (5), being electrically connected to one another by a first switch (4). The device (1) also involves each of the secondary windings (3) being connected in parallel to a second switch (7) for enabling or disabling the operation of the energy-saving device (1) between the power source (A) and the load (L). |
| US09627126B2 |
Printed circuit board including inductor
A printed circuit board (PCB) includes an insulating substrate, a plurality of copper foil pattern layers and a plurality of insulating adhesive sheets sequentially stacked on an upper side of the insulating substrate and a lower side of the insulating substrate, an inductor included in the copper foil pattern layer disposed on the upper side of the insulating substrate, a grounding element included in the copper foil pattern layer disposed on the lower side of the insulating substrate, and a single through hole penetrating the insulating substrate and the insulating adhesive sheets. The single through hole is disposed between the inductor and the grounding element. |
| US09627124B2 |
Ignition coil with molding mark
In an ignition coil, a housing has an inner chamber, and a transformer is installed in the inner chamber of the housing. A molded side-core assembly of a transformer includes an arched side core magnetically coupled to first and second ends of a longitudinal center core and located outside a circumferential part of primary and secondary windings. The molded side-core assembly includes an insulation cover molded to cover at least part of the arched side core. The insulation cover has a surface and at least one molding mark formed on the surface thereof. An insulation filler is filled in the inner chamber of the housing while the at least part of the arched side core is exposed from the insulation filler and the at least one molding mark is hermetically sealed in the insulation filler. |
| US09627119B2 |
Persistent-mode MRI magnet fabricated from reacted, monofilamentary MgB2 wires and joints
A superconducting magnet and method for making a superconducting magnet, are presented. The superconducting magnet is made by forming a coil from windings of a first wire comprising a reacted MgB2 monofilament, filling a cavity of a stainless steel billet with a Mg+B powder. Monofilament ends of the first wire and a similar second wire are sheared at an acute angle and inserted into the billet. A copper plug configured to partially fill the billet cavity is inserted into the billet cavity. A portion of the billet adjacent to the plug and the wires is sealed with a ceramic paste. |
| US09627118B2 |
Gapped magnet core
A gapped core leg for a shunt reactor, comprising magnetic core elements separated by spacers cast directly between the core elements. Accordingly, a rigid core leg construction is achieved. |
| US09627117B2 |
Thin film ferrite lamination
Forming a ferrite thin film laminate includes heating a layered assembly to form a laminate. The layered assembly includes a first coated substrate having a first ferrite layer opposite a first thermoplastic surface and a second coated substrate having a second ferrite layer opposite a second thermoplastic surface to form a laminate. Each coated substrate is formed by forming a ferrite layer on a surface of a thermoplastic substrate. The coated substrates are arranged such that the first ferrite layer contacts the second thermoplastic surface. Heating the layered assembly includes bonding the first coated substrate to the second coated substrate such that the first ferrite layer is sandwiched between a first thermoplastic substrate and a second thermoplastic substrate. The ferrite thin film laminate may include a multiplicity of coated substrates. |
| US09627114B2 |
Magnetic plasmonic nanoparticle positioned on a magnetic plasmonic substrate
Described embodiments include a system, method, and apparatus. The apparatus includes a magnetic substrate at least partially covered by a first negative-permittivity layer comprising a first plasmonic outer surface. The apparatus includes a plasmonic nanoparticle having a magnetic element at least partially covered by a second negative-permittivity layer comprising a second plasmonic outer surface. The apparatus includes a dielectric-filled gap between the first plasmonic outer surface and the second outer surface. The first plasmonic outer surface, the dielectric-filled gap, and the second plasmonic outer surface are configured to support one or more mutually coupled plasmonic excitations. |
| US09627106B2 |
High density shielded electrical cable and other shielded cables, systems, and methods
A shielded cable includes adjacent first and second conductor sets. Each conductor set includes two or more insulated conductors. The first conductor set also includes a ground conductor that generally lies in the plane of the insulated conductors of the first conductor set. At least 90% of the periphery of each conductor set is encompassed by a shielding film. First and second non-conductive polymeric films are disposed on opposite sides of the cable and form cover portions substantially surrounding each conductor set, and pinched portions on each side of the cable. When the cable is laid flat, the distance between the center of the ground conductor of the first conductor set and the center of the nearest insulated conductor of the second conductor set is σ1, the center-to-center spacing of the insulated conductors of the second conductor set is σ2, and σ1/σ2 is greater than 0.7. |
| US09627104B2 |
Harness exterior protection member and wire harness using the same
A harness exterior protection member with an electric wire bundle inserted therein includes a bent portion and a straight portion which are formed in a cylindrical shape in an integrated manner formed of a flame-retardant polyamide resin composition. A thickness of the straight portion is set to be twice to four times of a thickness of the bent portion. A bending radius of the bent portion is 10 mm or larger, and a bending strength of the straight portion is 15 to 25 N. |
| US09627102B2 |
Wire harness
An outer cover includes a flexible tube portion having flexibility and an inflexible tube portion. The flexible tube portion has a corrugated tubular shape in which concave portions and convex portions both extending in a circumferential direction are alternately formed side by side in an axial direction and in which intervals of the adjacent concave portions or intervals between the adjacent convex portions are partially changed. |
| US09627098B2 |
Real-time moving collimators made with X-ray filtering material
An apparatus includes an x-ray source operable to generate x-ray beams, a collimator comprising one or more leaves configured to modify the x-ray beams, a motorized system operable to move the one or more leaves of the collimator independently in or out of the x-ray beams, and a controller configured to synchronize operation of the x-ray source and the motorized system, allowing modification of the x-ray beams substantially in real time with generation of the x-ray beams. At least one leaf or each of the leaves of the collimator may be configured to modulate a beam quality of the x-ray beams. |
| US09627097B2 |
Systems, methods and apparatus for infusion of radiopharmaceuticals
Systems, apparatus and methods are provided through which an injector system automates a process of injecting an individual dose from a multiple dose of a radiotracer material. In some embodiments, the injector system includes a first dose calibrator system that receives a multidose vial of a radiotracer, a second dose calibrator system, an injection pump and an intravenous needle. In some embodiments, the first dose calibrator system and the multidose vial have an integrated shape. In some embodiments, the first dose calibrator system includes a pneumatic arm that receives the multidose vial. |
| US09627096B2 |
Semiconductor memory device
A semiconductor memory device may include a memory bank having a plurality of word lines arranged at a predetermined address interval, an address latching unit suitable for storing a target address corresponding to a target word line of the plurality of word lines, and a refresh control unit suitable for performing a refresh operation on first to Nth word lines having different address intervals from the target word line based on the target address in response to a smart refresh command, wherein N is a natural number. |
| US09627089B2 |
Shift register, gate driving circuit, and display device
The present invention provides a shift register, a gate driving circuit and a display device. The shift register comprises a precharge and reset module, a pull-up module, a pull-down module and a cut-off module, the cut-off module, the pull-up module and the pull-down module are connected at a first node, and the cut-off module is connected between the first node and the precharge and reset module. In the present invention, the cut-off module is provided to disconnect electric connection between the precharge and reset module and the pull-up module, such that the first node cannot discharge through the precharge and reset module, which effectively avoids internal discharge of the shift register, and further ensures normal output of the signal output from the output terminal of the shift register, and improves stability of the shift register. |
| US09627088B2 |
One time programmable non-volatile memory and read sensing method thereof
A read sensing method for an OTP non-volatile memory is provided. The memory array is connected with plural bit lines. The read sensing method includes following steps. Firstly, the plural bit lines are precharged to a precharge voltage. Then, a selected memory cell of the memory array is determined, wherein the selected memory cell is connected with a first bit line of the plural bit lines. Then, the bit line corresponding to the selected memory cell is connected with the data line, and the data line is discharged to a reset voltage. After a cell current from the selected memory cell is received, a voltage level of the data line is gradually changed from the reset voltage. According to a result of comparing a voltage level of the data line with a comparing voltage, an output signal is generated. |
| US09627086B2 |
Nonvolatile memory device, operating method thereof and memory system including the same
A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL. |
| US09627085B2 |
Refresh method for flash memory and related memory controller thereof
A refresh method for a flash memory includes at least the following steps: performing a write operation to store an input data into a storage space in the flash memory; checking reliability of the storage space with the input data already stored therein; and when the reliability of the storage space meets a predetermined criterion, performing a refresh operation upon the storage space based on the input data. For example, the write operation stores the input data into the storage space through an initial program operation and at least one reprogram operation following the initial program operation; and the refresh operation is an additional reprogram operation applied to the storage space for programming the input data recovered from the storage space into original storage locations in the storage space. |
| US09627082B2 |
NAND flash memory device
Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR (“HPSF-NOR”) memory read commands so that the serial NAND flash memory may be used with controllers designed for HPSF-NOR memory. Serial NAND flash memory having these compatibilities is referred to herein as high-performance serial flash NAND (“SPSF-NAND”) memory. Since devices and systems which use HPSF-NOR memories and controllers often have extreme space limitations, HPSF-NAND may also be provided with the same physical attributes of low pin count and small package size of HPSF-NOR memory for further compatibility. HPSF-NAND memory is particularly suitable for code shadow applications, even while enjoying the low “cost per bit” and low per bit power consumption of a NAND memory array at higher densities. |
| US09627080B2 |
Semiconductor memory device
A semiconductor memory device has a memory block including memory strings with first and second selection transistors at opposite ends of the memory strings. A bit line is connected to the first selection transistor of each memory string and a sense amplifier is connected to the bit line. The memory block includes word lines connected to each memory cell transistor in the memory strings. The memory device also includes a controller to control an erase operation that includes applying an erase voltage to the word lines, addressing a first memory string by applying a selection voltage to a gate electrode of first and second selection transistors of the first memory string, then applying an erase verify voltage to the word lines and using the sense amplifier to read data of memory cell transistors in the first memory string, then addressing a second memory string without first discharging the word lines. |
| US09627074B2 |
Method for determining an optimal voltage pulse for programming a flash memory cell
A method for determining an optimal voltage pulse for programming a flash memory cell, the optimal voltage pulse being defined by a voltage ramp from a non-zero initial voltage level during a programming duration, wherein the method takes into account a set of parameters including a programming window target value and a drain current target value of the memory cell. |
| US09627069B1 |
Semiconductor memory device and operating method thereof
A semiconductor memory device includes a memory cell array including a plurality of memory cells, connecting circuits including pass transistors coupled between global word lines and the plurality of memory cells, an address decoder coupled to block word lines coupled to gates of the pass transistors and the global word lines, and a control logic controlling the address decoder and applying a voltage pulse to the global word lines and the block word lines according to an operation state of the semiconductor memory device. |
| US09627065B2 |
Memory equipped with information retrieval function, method for using same, device, and information processing method
CPUs are not effective for search processing for information on a memory. Content-addressable memories (CAMs) are effective for information searches, but it is difficult to build a large-capacity memory usable for big data using the CAMs. A large-capacity memory may be turned into an active memory having an information search capability comparable to that of a content-addressable memory (CAM) by incorporating an extremely small, single-bit-based parallel logical operation unit into a common memory. With this memory, a super fast in-memory database capable of fully parallel searches may be realized. |
| US09627064B2 |
Dynamic tag compare circuits employing P-type field-effect transistor (PFET)-dominant evaluation circuits for reduced evaluation time, and related systems and methods
Dynamic tag compare circuits employing P-type Field-Effect Transistor (PFET)-dominant evaluation circuits for reduced evaluation time, and thus increased circuit performance, are provided. A dynamic tag compare circuit may be used or provided as part of searchable memory, such as a register file or content-addressable memory (CAM), as non-limiting examples. The dynamic tag compare circuit includes one or more PFET-dominant evaluation circuits comprised of one or more PFETs used as logic to perform a compare logic function. The PFET-dominant evaluation circuits are configured to receive and compare input search data to a tag(s) (e.g., addresses or data) contained in a searchable memory to determine if the input search data is contained in the memory. The PFET-dominant evaluation circuits are configured to control the voltage/value on a dynamic node in the dynamic tag compare circuit based on the evaluation of whether the received input search data is contained in the searchable memory. |
| US09627061B2 |
Electronic device having resistance element
An electronic device includes a first electrode, a second electrode spaced apart from the first electrode, a resistance variable element interposed between the first electrode and the second electrode, and a conductor arranged at least one of a first side and a second side of the resistance variable element to apply an electric field to the resistance variable element while being spaced apart from the resistance variable element, the first side facing the second side. |
| US09627058B2 |
Resistance random access memory with accurate forming procedure, operating method thereof and operating system thereof
An operating method, an operating system and a resistance random access memory (ReRAM) are provided. The operating method includes the following steps. A write voltage and a write current are set at a first predetermined voltage value and a first predetermined current value respectively. The write voltage and the write current are applied to a memory cell of the ReRAM for writing. Whether the write current reaches a second predetermined current value is verified, if a read current of the memory cell is not within a predetermined current range. The write current is increased, if the write current does not reach the second predetermined current value. Whether the write voltage reaches a second predetermined voltage value is verified, if the write current reaches the second predetermined current value. The write voltage is increased, if the write voltage does not reach the second predetermined voltage value. |
| US09627050B2 |
Memory access module for performing memory access management
A memory access module for performing memory access management of a storage device including a plurality of storage cells includes: sensing means for performing a plurality of sensing operations respectively corresponding to a plurality of different sensing voltages in order to generate at least a first digital value of a storage cell, wherein each subsequent sensing operation corresponds to a sensing voltage which is determined according to a result of the previous sensing operation; processing means for using the first digital value to obtain soft information of a bit stored in the storage cell; and decoding means for using the soft information to perform soft decoding. |
| US09627048B2 |
Semiconductor memory device which stores plural data in a cell
A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage. |
| US09627045B1 |
Superconducting devices with ferromagnetic barrier junctions
A superconducting memory cell includes a magnetic Josephson junction (MJJ) with a ferromagnetic material, having at least two switchable states of magnetization. The binary state of the MJJ manifests itself as a pulse appearing, or not appearing, on the output. A superconducting memory includes an array of memory cells. Each memory cell includes a comparator with at least one MJJ. Selected X and Y-directional write lines in their combination are capable of switching the magnetization of the MJJ. A superconducting device includes a first and a second junction in a stacked configuration. The first junction has an insulating layer barrier, and the second junction has an insulating layer sandwiched in-between two ferromagnetic layers as barrier. An electrical signal inputted across the first junction is amplified across the second junction. |
| US09627044B2 |
Offset detection
There is provided a method of detecting offset in a sense amplifier of an SRAM memory unit. The method comprises using a sense amplifier of the SRAM memory unit to implement a read of a first data value stored in a memory cell of the SRAM memory unit, and measuring a first time for the sense amplifier to read the first data value. The method further comprises using the sense amplifier to implement a read of a second data value stored in a memory cell of the SRAM memory unit, and measuring a second time for the sense amplifier to read the second data value. The method then comprises calculating a difference between the first time and the second time, and determining whether an offset adjustment should be applied to the sense amplifier in dependence upon the difference between the first time and the second time. |
| US09627040B1 |
6T static random access memory cell, array and memory thereof
A 6T static random access memory cell, array, and memory thereof are provided, in which the memory cell includes a first inverter, a second inverter, a first NMOS transistor, and a second NMOS transistor. A first high supply voltage and a low supply voltage are coupled to the first inverter. A second high supply voltage and the low supply voltage are coupled to the second inverter. The first NMOS transistor has a gate terminal coupled to a first word line. The first NMOS transistor has a source terminal coupled to the first node. The second NMOS transistor has a gate terminal coupled to a second word line, and the second NMOS transistor has a source terminal coupled to the second node. The first word line provides ON signals to turn on the first NMOS transistor, and the second high supply voltage provides a first boost voltage simultaneously. |
| US09627039B2 |
Apparatus for reducing write minimum supply voltage for memory
Described is an apparatus for self-induced reduction in write minimum supply voltage for a memory element. The apparatus comprises: a memory element having cross-coupled inverters coupled to a first supply node; a power device coupled to the first supply node and a second supply node, the second supply node coupled to power supply; and an access device having a gate terminal coupled to a word-line, a first terminal coupled to the memory element, and a second terminal coupled to a bit-line which is operable to be pre-discharged to a logical low level prior to write operation. |
| US09627038B2 |
Multiport memory cell having improved density area
A mutltiport memory cell having improved density area is disclosed. The memory cell includes a data storing component, a first memory access component coupled to a first side of the data storing component, a second memory access component coupled to a second side of the data storing component, first and second bit lines coupled to the first memory access component, first and second bit lines coupled to the second memory access component, first and second write lines coupled to the first memory access component and first and second write lines coupled to the second memory access component. The multiport memory cell also includes a read/write assist transistor, coupled to load transistors of the data storing component, that during read operations is activated for the duration of the read operation and during write operations is activated to impress the desired voltage level before or after one or more memory access components activated as a part of the write operation are deactivated. |
| US09627034B2 |
Electronic device
Provided is an electronic device including a circuit for reading data from a memory cell that can store multilevel data. The electronic device includes a memory cell array region, N sense amplifier regions, and switching elements. The memory cell array region includes memory cells that store, when (N+1)-level data is stored, the (N+1)-level data as different potentials. Each of the N sense amplifier regions compares a read potential, which depends on a charge released to a bit line and a wiring or the like connected thereto, with a reference potential and performs amplification. Each of the switching elements electrically isolates a sense amplifier region from the other sense amplifier regions after all of the N sense amplifier regions are electrically connected to the bit line. Each of the sense amplifier regions can output a write potential to the bit line. |
| US09627033B2 |
Sense amplifier and semiconductor device for securing operation margin of sense amplifier
A sense amplifier includes an equalization unit configured to precharge a pair of bit lines to a level of a bit line precharge voltage in response to a bit line equalizing signal; and an amplification unit configured to sense and amplify voltages of the pair of bit lines, supply, during an active operation, a ground voltage to a pull-down node of a latch section, and supply, when a precharge signal is enabled, a first voltage lower than the ground voltage to the pull-down node of the latch section for a predetermined time. |
| US09627031B1 |
Control methods and memory systems using the same
A control method for a memory system is provided. A memory controller of the memory system is configured to control the memory device. After a condition is met, the memory controller performs a retry operation to compensate for shifting of a data strobe signal sent from the memory device until the memory system enters a normal operation mode. When the shifting of the data strobe signal is compensated for, the number of pulses of the data strobe signal in the gating window is equal to the first predetermined number. |
| US09627021B2 |
8-transistor dual-ported static random access memory
An 8-transistor SRAM (static random access memory) storage cell provides differential read bit lines that are precharged to a low voltage level for read operations. The 8-transistor storage cell provides separate ports for read and write operations, including differential read bit lines. Prior to each read operation, the differential read bit lines are precharged to the low voltage level. During read operations, one of the two differential read bit lines is pulled high towards a high voltage level while the complementary bit line remains at the low voltage level resulting from the precharge. The difference in voltage between the differential read bit lines is sensed to determine the value stored in each 8-transistor SRAM storage cell and complete the read operation. |
| US09627020B1 |
Semiconductor device
A semiconductor device may be provided. The semiconductor device may include a reference mat including a reference bit line and a reference word line, the reference mat, located adjacent to a normal mat, and the reference mat configured such that a capacitance of the reference bit line is adjusted based on a signal of the reference word line. The semiconductor device may include a drive controller configured to drive the signal of the reference word line with a drive voltage based on a boosting voltage, the drive voltage having a lower voltage level than the boosting voltage. |
| US09627017B1 |
RAM at speed flexible timing and setup control
Embodiments of the present invention provide systems and methods for a RAM at speed flexible timing and setup control. The memory module includes: a module connected to a functional logic circuitry; first timing control latches of a first scan-in chain; a timing configuration circuitry controllable by timing and control configuration signals; selection circuits connected to each output line of the first timing control latches; and an output signal of the timing configuration circuitry is connected to input lines of the selection circuits, such that two sets of control data are operatively connected to the control input lines of the memory cells under test, without a reloading of the respective timing control latches. |
| US09627009B2 |
Interleaved grouped word lines for three dimensional non-volatile storage
A three dimensional non-volatile storage system includes a substrate and a plurality of memory cells arranged in a monolithic three dimensional memory array (or other 3D structure) positioned above and not in the substrate. The system includes a plurality of vertical bit lines and a plurality of word lines. Each group of three neighboring word lines on a common level of the three dimensional memory array are electrically isolated from each other and at least a subset of the three neighboring word lines of each group are connected to other word lines. |
| US09627004B1 |
Video frame annotation
A system and methodology provide for annotating videos with entities and associated probabilities of existence of the entities within video frames. A computer-implemented method selects an entity from a plurality of entities identifying characteristics of a video item, where the video item has associated metadata. The computer-implemented method receives probabilities of existence of the entity in video frames of the video item, and selects a video frame determined to comprise the entity responsive to determining the video frame having a probability of existence of the entity greater than zero. The computer-implemented method determines a scaling factor for the probability of existence of the entity using the metadata of the video item, and determines an adjusted probability of existence of the entity by using the scaling factor to adjust the probability of existence of the entity. The computer-implemented method labels the video frame with the adjusted probability of existence. |
| US09627000B1 |
Canary testing for storage devices
Embodiments are disclosed for analyzing data storage devices. The present disclosure employs a “canary” test that selects multiple storage devices and tests the same for a predetermined period of time. By analyzing the statuses of the storage devices monitored and recorded during the applicable tests, the present disclosure can generate an analytical result regarding the characteristics of the storage devices. The analytical result can be presented to an operator in a meaningful way so as to enable him or her to make an informed decision when utilizing a storage device with characteristics similar to the tested storage devices. |
| US09626998B2 |
Write interference reduction when reading while writing to a hard disk drive media
A hard disk drive device and a method and apparatus for control of the hard disk drive is provided. The hard disk drive includes disk media, a slider head, a head gimbal assembly and a control means. The disk media includes at least two layers for data storage. The slider head flies above the disk media and includes a writer and a reader, and a head gimbal assembly supports the slider head above the disk media. The control means is physically coupled to the head gimbal assembly and electrically coupled to the writer and the reader for reducing write interference from the writer when the writer is writing to the disk media while the reader is reading from the disk media, wherein write interference is reduced in one or more of a time domain and a frequency domain. |
| US09626997B1 |
Variable spinning rates for hard disk drives
Systems and techniques for varying the spindle speed of a hard disk drive are disclosed. In some embodiments, the systems and techniques involve a hard disk drive (HDD) that is accessible to a storage controller. A spin speed of the HDD is set to a full spinning speed, and an amount of time that the HDD is unassigned is compared to a threshold. After detecting that the threshold is exceeded, the spin speed of the HDD is decreased to a reduced spinning speed. Likewise, upon determining that the HDD is assigned, the spin speed of the HDD is increased to the full spinning speed. In various such embodiments, assigning the HDD may include assigning the HDD to a volume group or assigning the HDD operate as an in-use hot spare. |
| US09626995B2 |
Disk apparatus, controller, and control method
According to one embodiment, there is provided a disk apparatus including a disk medium and a controller. The disk medium has a data area and a servo area. The controller obtains offset amount of a head from a target position along an cross-track direction based on a signal read from the data area by the head and performs first control to cause the head to approach the target position based on the offset amount. |
| US09626994B2 |
Usage of state information from state-space based track-follow controller
A method according to one embodiment includes generating track following controller state information based on a positional signal of a head relative to a medium. One or more portions of the state information corresponding to particular frequencies are used to determine at least one of: lateral tape movement, tape skew, vibration operation conditions, and roller performance. |
| US09626990B2 |
Perpendicular magnetic recording (PMR) writer with hybrid shield layers
A perpendicular magnetic recording writer with an all wrap around (AWA) shield design wherein one or more of the leading shield, trailing shield, and side shields comprises a magnetic hot seed layer made of a >19 kG to 24 kG material that adjoins a gap layer, and a side of the hot seed layer opposite the gap layer adjoins a high damping magnetic layer made of a 10-16 kG material (or a 16-19 kG material in the trailing shield) having a Gilbert damping parameter a >0.04. In one embodiment, the high damping magnetic layer is FeNiRe with a Re content of 3 to 15 atomic %. The main pole leading and trailing sides may be tapered. Side shields may have a single taper or dual taper structure. Higher writer speed with greater areal density capability is achieved. |
| US09626985B2 |
Audio processing method and apparatus
Audio processing methods and apparatus are provided. An audio processing method may include: receiving audio data packets; buffering the audio data packets to a buffer; reading the audio data packets from the buffer and playing the audio data packets; accumulating an actual total playing time length and a total sampling time length of the audio data packets that currently have been read from the buffer and have been played; and suspending reading and playing, when a sum of sampling time lengths of audio data packets that are buffered and unread in the buffer is less than or equal to a first threshold, until a sum of sampling time lengths of the audio data packets in the buffer that are unread is greater than or equal to a current network jitter estimated value. |