| Document | Document Title |
|---|---|
| US09602382B2 |
Dynamic reaction to diameter routing failures
A method for dynamic reaction to DIAMETER routing failures is disclosed. The method for dynamic reaction to DIAMETER routing failures includes receiving a DIAMETER message, calculating a statistic associated with the route of the message, testing if the message is an unable_to_deliver message type, and if it is, testing the calculated statistic against a criterion. In the event the statistic exceeds the criterion, an action pertinent to the route which had a delivery failure is taken. The method for dynamic reaction to DIAMETER routing failures provides for dynamic management of routes at the node level in response to delivery failures. The method for dynamic reaction to DIAMETER routing failures is particularly useful for overcoming bandwidth usage in terms of delivery failures known in the art. |
| US09602376B2 |
Detection of periodic impairments in media streams
The invention relates to methods and systems for detecting periodic impairments of media streams of real-time communication sessions within a packet-switched network. The invention is performed in a passive monitoring system monitoring a plurality of media streams providing quality data records for each monitored media stream and for predefined time intervals. For each media stream a frequency distribution is generated, which is indicative of the number of good quality data records between two quality data records indicative of impairment. If a maximum exists in the media stream's frequency distribution for a given number of consecutive good quality data records, the stream is determined to be periodically impaired and said given number of consecutive good quality data records for which the maximum exists indicates the periodicity in the impairment of the media stream. |
| US09602373B2 |
Method, apparatus and system for dual-homing protection switching
The invention discloses a method for dual-homing protection switching. The method includes: when the bidirectional forwarding detection (BFD) state of a Pseudo Wire (PW) is DOWN, the Provider Edge (PE) disenabling the Ethernet Operation, Administration and Maintenance (OAM) function of a port connected with a Customer Edge (CE); and the CE which has started a master and standby link switching function switching the service traffic to a standby link. The invention also provides corresponding apparatus and system. The invention reduces the influence of network failure on the service, decreases service unavailable probability and improves the service reliability. |
| US09602371B2 |
Methods and apparatus for nonintrusive monitoring of web browser usage
Example methods disclosed herein for monitoring web browsing include processing a video image obtained from a video signal of a device implementing a web browser to identify a first image region less than the entire video image, the first image region having a first shape corresponding to an address bar of the web browser. Disclosed example methods also include tagging first textual information identified in the first image region as corresponding to an address of a web page displayed by the web browser in response to determining that the first textual information includes a first string of text matching a reference string of text. Disclosed example methods further include reporting the tagged first textual information to determine usage of the web browser. |
| US09602366B1 |
System and method for correcting clock discrepancy in simultaneous network traffic captures
A system and method for correcting clock discrepancy in simultaneous network traffic data captures in a multi-tiered, multi-session environment. The invention uses intrinsic constraints imposed by the nature of the traffic onto the possible temporal sequence of the packets, The invention uses the intrinsic restraints of the network architecture and the protocols used at each segment along with the time stamps in the various segments to determine both an offset and scale correction to the clock readings (timestamps) in the traces in order to obtain a correct temporal sequence of packets when using multiple capture agents/engines/network monitors. |
| US09602363B2 |
System and method for implementing network service level agreements (SLAs)
Some implementations provide a method including: storing, at a Network Credit Server (NCS), a service level agreement of a customer; maintaining a database of topology information of the network; receiving a request from a network device where a first plurality of packets associated with the customer have been received en-route to a destination and when the number of the first plurality of packets surpasses a pre-configured threshold number; generating, by the NCS, a reply based on the service level agreement of the customer and the topology information of the network; and sending the reply to the network device for the network device to process a second plurality of packets associated with the customer, the second plurality of packets being received at the network device subsequent to the first plurality of packets and en-route to the destination. |
| US09602360B1 |
Dynamic resource zone mapping
Techniques, including systems and methods, for organizing access to computing resources include dynamically mapping identifiers of data zones to data zones. A request for initiation of one or more computing resources is received. The request specifies an identifier of a data zone. Responsive to the request, the specified identifier is mapped to a data zone. The requested computing resources are initiated in the data zone to which the identifier was mapped. |
| US09602357B2 |
Network visualization systems and methods
Example network visualization systems and methods are described. In one implementation, a method displays a network environment as a network graph using a first zoom level. The method receives a request to provide a second zoom level in a particular portion of the network environment. Network components are identified to display at the second zoom level in the particular portion of the network environment. The method further determines which network connections to display at the second zoom level in the particular portion of the network environment and generates a revised network graph containing the identified network components and the determined network connections. |
| US09602354B1 |
Applications-aware targeted LDP sessions
In general, the disclosure relates to techniques for initiating a targeted LDP session in a manner that includes information specifying one or more application for which a targeted LDP session is being initiated. In one example, a method includes receiving, by a network device, a LDP initialization message to initiate an Label Distribution Protocol (LDP) session with a peer network device, the LDP initialization message including a Targeted Applications Capability (TAC) field specifying one or more applications for which the LDP session is to be used for advertising forwarding equivalence class (FEC)-label bindings between the network device and the peer network device, and determining, by the network device, whether to allow the LDP session to be established based on the one or more applications specified in the TAC field. |
| US09602351B2 |
Proactive handling of network faults
The techniques and/or systems described herein implement a fault handling service that is able to ensure that at least part of a network can avoid congestion (e.g., a link exceeding capacity) as long as a predetermined maximum number of faults is not exceeded. The fault handling service models different combinations of possible faults based on network topology and then computes an amount of traffic to be communicated via individual paths such that congestion is avoided as long as a number of actual faults that occur is less than or equal to the predetermined maximum number of faults. |
| US09602350B2 |
Expandable distributed core architectures having reserved interconnect bandwidths
A network system for an expandable distributed core architecture (“DCA”) includes multiple spine switches, multiple leaf switches coupled thereto, and a plurality of interconnections coupling each of the spine switches to each of the leaf switches. Servers, storage, and other system items and resources can be coupled to the leafs via downlinks and uplinks. Each of the plurality of spine switches includes at least one unused spine port that is reserved for a future expansion of the DCA in order to accommodate the addition of at least one other separate leaf switch to the at least one unused spine port. Additional ports can be unused and reserved for future expansion additions of more leafs and/or more spines. Also, a computing system assists in the design of the specific number and configuration of spines, leafs and interconnections based upon user inputs regarding current and future system needs. |
| US09602349B2 |
Multi-device sensor subsystem joint optimization
A system and method for reducing sensor redundancy in sensor-equipped devices includes identifying, via a master device, at least one device within an area. The at least one device is queried to determine at least one of a device status or application status for the at least one device. A configuration of one or more sensors within the at least one device based at least in part on the querying is determined. The one or more sensors within the at least one device is configured to balance quality of service across the master device and the at least one device, based at least in part on the determining. |
| US09602342B2 |
Method of provisioning network elements
A system and method for provisioning network elements, such as but not limited to the type of network elements used in cable television system to facilitate subscriber access to services. The provisioning may be accomplished without communications between multiple provisioning servers. This allows the provisioning to be conducted in a stateless manner. |
| US09602339B2 |
System and method for supporting a server-side event model in a distributed data grid
A server-side event model provides a general-purpose event framework which simplifies the server-side programming model in a distributed data grid storing data partitions distributed throughout a cluster of nodes. A system provides event interceptors which handle events associated with operations and maps the event interceptors to event dispatchers placed in the cluster. Advantageously, the system supports handling critical path events without the need for interactions from the client-side thereby avoiding unnecessary delays waiting for client responses. Additionally, the system can defer completion of an operation in the distributed data grid pending completion of event handling by an event interceptor. The system enables the data grid to employ more types of events and define different event interceptors for handling the events while avoiding client interaction overhead. |
| US09602335B2 |
Independent network interfaces for virtual network environments
Embodiments of the invention relate to providing network independent network interfaces. One embodiment includes creating a root interface in a first device in a network system. Virtual network interface cards (vNICs) are added to the root interface. The first device executes network services on the root interface. The root interface is a single access point for accessing a plurality of underlying networks. |
| US09602334B2 |
Independent network interfaces for virtual network environments
Embodiments of the invention relate to providing network independent network interfaces. One embodiment includes a networking system. The networking system includes a physical networking device connected to one or more underlying networks. A primary switch and a secondary switch are each connected to the physical networking device. A connectivity module creates a root interface for a first device. Virtual network interface cards (vNICs) are added to the root interface by the connectivity module. The root interface is a single access point for accessing the underlying networks. The first device is a virtual machine (VM) or a server with more than one network interface. |
| US09602333B2 |
DNS server, gateways and methods for managing an identifier of a port range in the transmission of data
A DNS server (110) and to a method of managing a DNS request, the method comprising receiving (E2) a DNS request for accessing a remote application (104B) accessible via a gateway (106B) and sending (E3) a DNS response including the IP address of the gateway (106B), the method further comprising a verification for determining whether a port range identifier is stored in the DNS server (110) in association with the IP address of the gateway (106B), and if so, the identifier is inserted in the DNS response before sending the DNS response. The invention also provides a method of transmitting data from a first gateway (106A) to a second gateway (106B), a method of transmitting data from a gateway (106B) to a server (102B) of a local network (LAN_B), and the gateways (106A, 106B) for performing such methods. |
| US09602332B2 |
Method and apparatus for DNS update triggered IPv6 neighbor advertisement
In a 3GPP2 Converged Access Network (CAN), IPv6 stateless auto configuration can be used to configure an IPv6 address of an access terminal (AT) for Simple IPv6 operation. A domain name system (DNS) update is triggered by IPv6 Neighbor Advertisement addresses a need for a DNS update when the full IPv6 address (128 bits) has not yet been sent in IPv6 packets from the AT. Upon receipt of the full address in response to the IPv6 Neighbor Advertisement, provision is made for prompting this DNS update even when the requesting network entity (e.g., access gateway (AGW) or home agent (HA)) does not have security authentication with a responsible home DNS server by utilizing access to an authentication, authorization, and accounting (AAA) function, perhaps via a local visited AAA, to submit an Accounting Request (Start) message that prompts the home DNS server to perform the DNS update. |
| US09602325B2 |
Transmitter and method of transmitting
At least one tone is generated. An output signal is generated in response to an input signal and the at least one tone. The output signal is modulated. The input signal and the at least one tone are represented in the modulated output signal. The at least one tone is outside a bandwidth of the input signal as represented in the modulated output signal. The modulated output signal is amplified. The at least one tone in the amplified signal is attenuated after the amplifying. |
| US09602324B2 |
Telecommunication signaling using nonlinear functions
One exemplary embodiment can describe a method for communicating. The method for communicating can include a step for identifying characteristics of a communications channel, a step for identifying a set of nonlinear functions used to generate waveforms, a step for assigning a unique numeric code to each waveform, a step for transmitting a numeric sequence as a series of waveforms, a step for receiving the series of waveforms, and a step for decoding the series of waveforms. |
| US09602323B2 |
Method for increasing coverage and robustness against frequency offsets in wireless networks, user device and computer programs thereof
A Method for increasing coverage and robustness against frequency offsets in wireless networks, user device and computer program productsIn the method, a user device (171) that wirelessly communicates with a base station (172) through a wireless network employing a Single Carrier-Frequency Division Multiple Access, SC-FDMA, comprises: applying a number of calculated repetitions of a block of complex information symbols prior to a SC-FDMA modulator (176), said number of repetitions being an integer submultiple of a number of subcarriers scheduled for uplink transmission according to the expression: NscUL=L×M with L and M integers; and applying, when mapping to scheduled resources in the SC-FDMA modulator (176), a frequency shift equal to a subcarrier width multiplied by one half of said number of repetitions. |
| US09602319B2 |
Apparatus, method, and computer readable medium for high-efficiency wireless local-area network (HEW) signal field detection
Apparatuses, methods, and computer readable media are disclosed. A STA to detect a HE SIG may be configured to detect the HE SIG based on at least one from the following group: a flipped reserved bit, a scrambled portion of the HE SIG, and a rotation of a signal constellation of the HE SIG different than legacy rotations of: a rotation of a first signal constellation and no rotation of a second signal constellation, and no rotation of the first signal constellation and a rotation of the second signal constellation. The STA may determine that a reserved bit is the flipped reserved bit based on a bit being reversed from a legacy standard. The STA may unscramble a received signal field, determine whether a CRC indicates the HE-SIG contains errors, and if the CRC indicates there are no errors, then determine that the signal field is the HE SIG. |
| US09602318B2 |
Closed-loop high-speed channel equalizer adaptation
A serial communication circuit (FIG. 3) is disclosed. The circuit includes an equalizer circuit (306) arranged to receive a data signal (CH 1) and produce an equalized data signal. A log detector circuit (300) receives the data signal and produces a power signal indicating a power level of the data signal. A decision circuit (332) receives the power signal and produces a select signal. A first selection circuit (336) receives a plurality of first correction signals and applies one of the first correction signals to the equalizer circuit in response to the select signal. |
| US09602316B2 |
Multiple symbol noncoherent soft output detector
Multiple symbol noncoherent soft output detectors in accordance with embodiments of the invention are disclosed. In a number of embodiments, the multiple symbol noncoherent soft output detector uses soft metrics based on the Log Likelihood Ratio (LLR) of each symbol to provide information concerning the reliability of each detected symbol. One embodiment of the invention includes a receiver configured to receive and sample a phase modulated input signal, and a multiple symbol noncoherent soft output detector configured to receive the sampled input signal and to generate a soft metric indicative of the reliability of a detected symbol based upon observations over multiple symbols. |
| US09602313B1 |
Time-controlled spatial interference rejection
A dual-modem device opportunistically switches between spatial filtering techniques to enhance the received symbol estimates based at least in part on identifying, at a first modem, an interfering communication from a second modem. A WLAN modem can determine the timing of a WWAN transmission from a coexisting WWAN modem that interferes with a WLAN transmission and toggle between MRC and IRC receive techniques based at least in part on the determined timing. |
| US09602312B2 |
Storing network state at a network controller
Some embodiments provide a network controller for managing a logical network that spans several physical domains. The network controller is located at a particular one of the several physical domains. The network controller includes a first storage for storing network state information that is local to the particular physical domain. The network controller includes a second storage for storing a first type of global network state information for the logical network. The network controller includes a third storage for storing a second type of global network state information for the logical network. The network controller includes an interface for communicating with other network controllers located at the other physical domains in the several physical domains spanned by the logical network. The interface is for sharing the first and second types of global network state information. |
| US09602311B2 |
Dual-mode network
Aspects of the present disclosure are directed toward apparatuses, systems, and methods that include a first gateway circuit in an optical access network connecting a plurality of end-of-network users to a central node, the first gateway circuit connecting one of the plurality of end-of-network users to the central node via fiber optic data lines. Further, the first gateway circuit is configured and arranged to: relay a first set of data between the end-of-network user and the central node using a packet-switching communication protocol, and relay a second set of data between the end-of-network user and the central node using an optical flow switching communication protocol. |
| US09602309B2 |
Alert message portal to securely notify subscribers of events
The present invention provides a method of operating a communication portal. One embodiment of the method includes accessing, at the communication portal, an alert message addressed to a group registered to receive an alert service. The method also includes generating user identifiers corresponding to users that are registered to the group. The user identifiers are assigned to the users for use within the communication portal. The method further includes transmitting the alert message from the communication portal to the users indicated by the user identifiers. |
| US09602307B2 |
Tagging virtual overlay packets in a virtual networking system
Embodiments of the invention provide a method for packet distribution in a virtual networking system comprising multiple virtual networks interconnected over an underlying layer network, wherein each virtual network comprises one or more computing nodes. The method comprises, for each virtual network, sending at least one outgoing packet targeting a computing node at a different virtual network, and receiving at least one incoming packet targeting a computing node of the virtual network. Each packet has a corresponding virtual networking tag that includes routing information identifying a destination virtual network for the packet. |
| US09602305B2 |
Method and system for virtual and physical network integration
The disclosure herein describes a virtual extensible local area network (VXLAN) gateway. During operation, the VXLAN gateway receives, from a physical host, an Ethernet packet destined for a virtual machine residing in a remote layer-2 network broadcast domain that is different from a local layer-2 network broadcast domain where the physical host resides. The VXLAN gateway then determines a VXLAN identifier for the received Ethernet packet. The VXLAN gateway further encapsulates the Ethernet packet with the virtual extensible local area network identifier and an Internet Protocol (IP) header, and forwards the encapsulated packet to an IP network, thereby allowing the packet to be transported to the virtual machine via the IP network and allowing the remote layer-2 network broadcast domain and the local layer-2 network broadcast domain to be part of a common layer-2 broadcast domain. |
| US09602302B1 |
Method for disabling a legacy loop detect circuit in a Beta node
A method for disabling or removing a Legacy loop detect circuit to eliminate the circuit erroneously detecting a legacy loop during a IEEE-1394 serial bus initialization. The method includes providing a programmable code to the Legacy loop detect circuit for increasing a reset count to a value greater than three (3) to the Legacy loop circuit thus reducing the probability of an erroneous disconnect of a Beta node connection. This method provides for more robust Beta loop node operation during high frequency bus resets. |
| US09602299B1 |
Detection of device compliance with an operational policy
A detection device may monitor emissions from a computing device, which may include radiation and/or radio waves from a computing device. The emissions may be electromagnetic (EM) radiation indicative of operation of components of the computing device. When the emissions reach or exceed an emissions threshold, the detection device may output an indicator. The indicator may indicate a violation of an operational policy that is associated with the emissions threshold. The indicator may additionally or alternatively indicate compliance with the operation policy. In some embodiments, the detection device may be implemented as an accessory such as a case, a cover, a light, or another type of accessory for the computing device. |
| US09602296B2 |
Adaptive multicast network communications
This disclosure is directed to techniques for internet group management protocol tunneling. This may be done by electing, by each of a plurality of multicast gateways in a subnet, a designated router in the subnet. The designated router sends internet group management protocol queries to at least one router in the subnet. The designated router further tunnels internet group management protocol reports. |
| US09602292B2 |
Device-level authentication with unique device identifiers
An embodiment may include transmitting a manufacturer security certificate to a provisioning server device, and establishing, with the provisioning server device, a secure connection based on the manufacturer security certificate. The embodiment may also involve transmitting, over the secure connection, device data that characterizes the client device, and receiving, over the secure connection, a server security certificate. The embodiment may further include obtaining a unique client device identifier, where the unique client device identifier is stored in a secure memory element of the client device. The embodiment may additionally include, possibly based on the server security certificate and the unique client device identifier, accessing protected information available to a particular pre-validated server device. |
| US09602291B2 |
Secure connection certificate verification
One or more computer processors identify a first certificate that is used to establish a secure Internet connection. One or more computer processors identify a stored second certificate that shares at least one attribute with the first certificate. One or more computer processors determine a policy action based, at least in part, on a result of a comparison between an attribute of the first certificate and an attribute of the second certificate. |
| US09602288B1 |
Enhanced data security through uniqueness checking
A system records use of values used in cryptographic algorithms where the values are subject to uniqueness constraints. As new values are received, the system checks whether violations of a unique constraint has occurred. If a violation occurs, the system performs actions to mitigate potential compromise caused by exploitation of a vulnerability caused by violation of the uniqueness constraint. |
| US09602283B1 |
Data encryption in a de-duplicating storage in a multi-tenant environment
The present invention addresses encryption systems and methods in the de-duplication of data in a multi-tenant environment. The system provides isolation between tenants' stored data and the storage system. Tenant keys are assigned to tenants. The storage system stores raw data objects backed up for the tenants and fingerprints, corresponding to the data objects, in a single use key encrypted format. Fingerprints are wrapped with a storage system key held by the storage system. A request is received to retrieve data backed up for a tenant. The request includes fingerprints corresponding to the data objects to retrieve, and a tenant key, the fingerprints being in the single use key encrypted format and wrapped with the tenant key. The received fingerprints are unwrapped using the tenant key to retrieve data objects corresponding to the received fingerprints. The data objects are transmitted to the tenant and the tenant key is removed. |
| US09602279B1 |
Configuring devices for use on a network using a fast packet exchange with authentication
Aspects of this disclosure related to a computer-implemented method for using a first device to configure a second device to access a network. The method includes transmitting a request on a channel, the request containing information sufficient to inform a device that the system can configure the device to access a network through an access point. The method further includes receiving a response on the channel, the response sent by the device after the request and transmitting a request for security information from a server. The method further includes receiving security information from the server, using the security information to verify an identity of the device, and transmitting a security profile to the device, the security profile containing information sufficient to allow the device to connect to the access point to access the network. |
| US09602274B2 |
Secure password generation
A secure password generation method and system is provided. The method includes enabling by a processor of a computing system, password translation software. The computer processor generates and stores the random translation key. A first password is received and a second associated password is generated. The computer processor associates the second password with a secure application. The computer processor stores the random translation key within an external memory device and disables a connection between the computing system and the external memory device. |
| US09602271B2 |
Sub-nanosecond distributed clock synchronization using alignment marker in ethernet IEEE 1588 protocol
A method for determining a slave clock to master clock time difference with an alignment marker. The method selects and transmits a first alignment marker at a first time by a transmitter that has a master clock in a first message to a receiver that has a slave clock. Subsequent to transmitting the first message, the method further transmits a second message that contains the first time and an identity of the first alignment marker. The method further receives the first message and records a second time that the first message is received. The method further receives the second message and the first time and the identity of the first alignment marker. The method further determines a transmission delay and generates a time difference from the slave clock to the master clock. |
| US09602270B2 |
Clock drift compensation in a time synchronous channel hopping network
Disclosed are various embodiments for compensating for clock drift between nodes in a time synchronous network. A node receives time synchronization information from a parent node in the network. A drift between a clock of the node and a clock of the parent node is determined based upon the time synchronization information. The node identifies a number of time slots of the network since making a last time synchronization based on previous time synchronization information transmitted from the parent node. A compensation interval is calculated that represents a number of the time slots over which the clock of the node deviated, with respect to the parent node, by a predefined compensation value. The node compensates, by the compensation value, one of the time slots according to the compensation interval. |
| US09602269B2 |
Dynamic time division duplexing method and apparatuses using the same
The present disclosure proposes a dynamic time division duplexing (TDD) method applicable to a user equipment and a control node, and apparatuses using the same method. Accordingly, the present disclosure proposes a base station (BS) which transmits to a least one user equipment (UE) a system information block (SIB) having a first modification period, and the base station may transmit a TDD uplink-downlink subframe configuration during the first modification period. The BS also configures for at least one UE a second modification period which is in an integer divisor of the first modification period and could be within the first modification period so that the BS may transmit a second TDD uplink-downlink subframe configuration in the second modification period. As the second modification period is shorter than the first modification period and is periodically scheduled, the BS may alter the current TDD uplink-downlink subframe configuration dynamically at a faster rate. |
| US09602267B2 |
Communication apparatus and communication method
A communication apparatus comprises a generator that generates frequency resource position information corresponding to a first information which is based on the communication quality information received from user equipments, the frequency resource position information indicating validity or invalidity of the first information for each frequency resource, anda transmitter that transmits the first information, the frequency resource position information and a cell ID which the frequency resource position is applied, to another communication apparatus via a backhaul. |
| US09602266B2 |
Method and apparatus for scheduling use of radio resources in a wireless network
The present disclosure describes techniques and apparatuses for scheduling use of radio resources in a wireless network. In some aspects a method is described that includes receiving an indication from a mobile device of an in-device coexistence problem, and determining, from the parameters in the received indication, one or more component carriers of the carrier aggregation affected by the in-device coexistence problem. The method also includes applying a time-domain solution and/or a frequency domain solution to at least one of the one or more affected component carriers to solve the in-device coexistence problem. |
| US09602262B2 |
Method for setting search regions for downlink control channels in wireless communication systems and apparatus for same
The present invention relates to a method for transmitting an Enhanced Physical Downlink Control Channel (EPDCCH) from a based station to a terminal in a wireless communication system. In particular, the method includes the steps of: setting resource blocks for the EPDCCH; re-indexing by permutation indexes of the resource blocks; defining an Enhanced Control Channel Element (ECCE) for each of the re-indexed resource blocks; selecting the ECCEs in a number corresponding to the aggregation level of the EPDCCH; and transmitting the EPDCCH to the terminal using the selected ECCEs. |
| US09602261B2 |
Method of indicating physical uplink control channel resource in enhanced multiple-input multiple-output technology and related communication device
A method of indicating a physical uplink control channel (PUCCH) resource for a user equipment (UE) of a wireless communication system includes receiving a resource index denoting PUCCH format 2 resources and PUCCH format 3 resources, instead of merely denoting PUCCH format 2 resources, from a network of the wireless communication system; and determining resources for a transmission of control information over PUCCH format 2 or PUCCH format 3 based on an operation of the received resource index. |
| US09602258B2 |
Method and apparatus for transmitting reference signal
Disclosed are a method and an apparatus for transmitting a reference signal. The method for transmitting the reference signal comprises the step of: transmitting a secondary synchronization signal (SSS) and a primary synchronization signal (PSS) from a subframe including an N (natural number wherein N>1) number of resource blocks (RB) and a plurality of orthogonal frequency division multiplexing (OFDM) symbols; and transmitting from the subframe the reference signal which is generated on the basis of a cell identifier, wherein the reference signal can be transmitted from an M (natural number wherein K<=M |
| US09602250B2 |
Method for retransmitting data in wireless communication system
A method for retransmitting data in wireless communication system is disclosed. MS can receive a NACK (Not-Acknowledge) signal from a base station (BS) through a specific downlink subframe of a specific frame in a first superframe, and the MS can retransmits the data using a second uplink subframe in a first frame in a second superframe subsequent to a first superframe. In this case, a index of the second uplink subframe may be 1. The wireless communication system can support the Half-Frequency Division Duplex (H-FDD) scheme. A first uplink subframe in the first frame of the second superframe can be punctured. |
| US09602249B2 |
Method and device for setting backhaul link subframe in wireless communication system having carrier aggregation technique applied thereto
Disclosed in the present invention is a method for a base station to set a backhaul link subframe for a relay node in a wireless communication system, to which a carrier aggregation technique is applied. More particularly, the present invention comprises the steps of: determining one of the plurality of subframe settings as a first subframe setting for a main component carrier allocated to the relay node; composing subframe setting candidates for one or more subcomponent carriers allocated to the relay node, one the basis of the determined first subframe setting; and determining a second subframe setting for each of the one or more subcomponent carriers, using the composed subframe setting candidates, wherein a subframe aggregation according to the first subframe setting and subframe aggregations according to each of the subframe setting candidates do not overlap when downlink subframes and uplink subframes of the different component carriers are identical, and a downlink subframe aggregation according to the second subframe setting is included in a downlink subframe aggregation according to the first subframe setting. |
| US09602241B2 |
Computing system with polar processing mechanism and method of operation thereof
A computing system includes: an inter-device interface configured to communicate content; and a communication unit, coupled to the inter-device interface, configured to process the content based on a polar communication mechanism utilizing multiple processing dimensions for communicating the content, including: generating a node result with a first orthogonal mechanism, and processing the node result from the first orthogonal mechanism with a second orthogonal mechanism. |
| US09602234B2 |
Data transmission control methods and devices
A method of controlling a receiver of a data unit communication from a data source is described, said receiver being associated with a first terminal of a data unit communication network providing said first terminal with a transport service characterized by a set of values associated with respective service quality parameters, said service quality parameters comprising a Guaranteed Bit Rate (GBR), said data source being associated with a second terminal. The method comprises determining, by the receiver, whether a received data unit contains an Explicit Congestion Notification (ECN). If said ECN is detected, the method further comprises sending, from the receiver, to said data source a message for adjusting a data transmission rate of said data source, said message indicating as an upper bound for said data transmission rate a value corresponding to a value associated with the GBR for said first transport service. |
| US09602230B2 |
Estimating channel information
Disclosed is a method of providing channel state information for a desired downlink channel of a wireless communication system. In a configuration phase, the method comprises receiving on a signaling channel configuration information comprising an identifier of an interference source and an association which associates the identifier with at least one resource element not used for transmission on the desired downlink channel. In an estimation phase, the method comprises estimating channel state information for an expected transmission on the desired downlink channel accounting for an incoming interference transmission from the identified interference source as observed from the at least one resource element. In a reporting phase, the method comprises reporting the channel state information. |
| US09602228B1 |
Method and apparatus for transmission and reception of a signal over multiple frequencies with time offset encoding at each frequency
A method of processing a signal including the steps of: (a) modulating the signal using a modulator corresponding to a modulation, (b) sending the modulated signal over multiple frequencies where the signal is offset in time in each frequency, (c) receiving the signal over the multiple frequencies, (d) reconstructing the sent signal by reversing the time delay and combining the received signal from each frequency, and (e) demodulating the received combined signal using a demodulator corresponding to the modulation used in (a). |
| US09602227B2 |
Distribution of broadcast traffic through a mesh network
Systems, methods and apparatuses for supporting broadcast traffic through a wireless mesh network are disclosed. One method includes obtaining broadcast listening information of a broadcast listening access node, wherein the broadcast listening information includes an identifier of the broadcast listening access node, and a broadcast identifier of the broadcast listening device. The method further includes obtaining broadcast sourcing information of a broadcast sourcing access node, wherein the broadcast sourcing information includes an identifier of the broadcast sourcing access node, and a broadcast identifier of the broadcast sourcing device. The method further includes providing broadcast listening information of the broadcast listening access node to the broadcast sourcing access node upon determining the broadcast identifier of the broadcast sourcing device matches the broadcast identifier of the broadcast listening device. |
| US09602224B1 |
Antenna placement based on LIDAR data analysis
In an embodiment, a computer-implemented method for optimizing service quality for a line of sight (LOS) radio service is provided. The method includes identifying an antenna on a rooftop and determining a transmitter to provide LOS radio service to the antenna. A residential units data set for the service area is created. In an embodiment, the residential units data set is based on a light detection and ranging (LIDAR) data set. The residential units data set is accessed and a cross section analysis of a line of sight from the transmitter with the rooftop data is conducted to identify regions that have line of sight. A service quality ranking is generated based on the level of visibility between the residential unit and the transmitter for each of the identified regions on the rooftop. A region is selected for antenna placement that has the highest service quality ranking. |
| US09602222B2 |
Techniques for securing body-based communications
Various embodiments are generally directed to techniques to form and maintain secure communications among two or more body-carried devices disposed in close proximity to the body of a person to form a body area network (BAN). An apparatus to establish secure communications includes a processor component; a signal component for execution by the processor component to compare a signal characteristic of a security test signal to a known signal characteristic of the security test signal to derive a bioelectric characteristic, the security test signal received via a tissue; and a bioelectric component for execution by the processor component to determine whether to allow transmission of data through the tissue based on the bioelectric characteristic. Other embodiments are described and claimed. |
| US09602219B2 |
Efficient processing of high data rate signals with a configurable frequency domain equalizer
An optical system includes an optical transmitter configured to modulate an optical signal to carry data, associated with an optical channel, via multiple sub-carriers in a quantity greater than four. The optical system further includes an optical receiver configured to demodulate the optical signal to recover the data from the multiple sub-carriers. |
| US09602213B2 |
System and method of extending time division passive optical network services to plastic optical fiber in the home
A system (87; FIG. 2) is disclosed to provide a Time Division Multiple Access Passive Optical Network to a Plastic Optical Fiber to be used in both single-family home networks and in multiple dwelling units. The system (87) extends the fiber to the home fiber network infrastructure from existing fiber access networks to fiber in the home for home networking. A plastic optical fiber converter (48; FIG. 4) associated with an optical network terminal (56; FIG. 6) receives a downstream optical signal (15; FIG. 3) that is converted into an electrical signal (61; FIG. 6). The converter (48) within the optical network terminal (56) modulates Ethernet frames contained within the electrical signal and converts the frames into optical signals (71,72; FIG. 6) with advanced modulations that are then transmitted via the plastic optical fiber within the home network (124; FIG. 2). |
| US09602209B2 |
Extremely high frequency (EHF) distributed antenna systems, and related components and methods
Extremely High Frequency (EHF) distributed antenna systems and related components and methods are disclosed. In one embodiment, a base unit for distributing EHF modulated data signals to a RAU(s) is provided. The base unit includes a downlink data source input configured to receive downlink electrical data signal(s) from a data source. The base unit also includes an E-O converter configured to convert downlink electrical data signal(s) into downlink optical data signal(s). The base unit also includes an oscillator configured to generate an electrical carrier signal at a center frequency in the EHF band. The base unit also includes a modulator configured to combine the downlink optical data signal(s) with the electrical carrier signal to form downlink modulated optical signal(s) comprising a downlink optical data signal(s) modulated at the center frequency of the electrical carrier signal. The modulator is further configured to send the downlink modulated optical signal to the RAU(s). |
| US09602207B2 |
Soft decoding of data in a coherent optical receiver
In a coherent optical receiver receiving a polarization multiplexed optical signal through an optical communications network, a method of compensating noise due to polarization dependent loss (PDL). A Least Mean Squares (LMS) compensation block processes sample streams of the received optical signal to generate symbol estimates of symbols modulated onto each transmitted polarization of the optical signal. A decorrelation block de-correlates noise in the respective symbol estimates of each transmitted polarization and generating a set of decorrelated coordinate signals. A maximum likelihood estimator soft decodes the de-correlated coordinate signals generated by the decorrelation block. |
| US09602204B2 |
Light module, illumination system and method incorporating data in light emitted
Proposed is a light module (110) comprising at least two primary light sources (111,112,113) capable of emitting a primary color light. This allows the light module to emit light having intensity (Y) and color coordinates (x,y) through additive color mixing of the constituent primary colors. The light module further comprises an modulator (115) capable of modulating the primary light sources enabling embedment of data in the light emitted. The modulator (115) is arranged to modulate the color coordinates of the light emitted for embedding the data. This is especially advantageous as the sensitivity of the human eye to changes in color is lower than to changes in intensity. The invention thus advantageously allows embedding the data into the light emitted from the light modules (110) of an illumination system (100) without reducing the performance of its primary function as an aid to human vision. |
| US09602199B2 |
Method of measuring optical fiber link chromatic dispersion by fractional Fourier transformation (FRFT)
The present invention relates to a method of measuring optical fiber link chromatic dispersion by fractional Fourier transformation (FRFT), belonging to the technical field of optical communication. The method of the present invention performs coherent demodulation for an optical pulse signal output from the optical fiber link to obtain a complex field of the optical pulse signal, then performs FRFT on the complex field; according to the energy focusing effect of the chirp signal in the fractional spectrum, calculates an optimal fractional order of the FRFT, and then calculates chromatic dispersion of the optical fiber link according to the optimal fractional order. The method can be applied to an optical fiber communication system consisting of different types of optical fibers, to perform monitoring of optical fiber link chromatic dispersion. |
| US09602197B2 |
Non-intrusive diagnostic port for inter-switch and node link testing
A diagnostic testing utility is used to perform single link diagnostics tests including an electrical loopback test, an optical loopback test, a link traffic test, and a link distance measurement test. These diagnostics tests can be performed on trunked links and virtual channels and can be performed while QoS is enabled. Additionally the tests can be performed non-intrusively by using a dedicated VC such that regular traffic is not affected by the diagnostics testing. |
| US09602196B2 |
Devices and methods for flow control of messages in a passive optical network (PON) and methods therein
A method in an Optical Line Terminal (OLT) device for transmitting a flow control message to an Optical Network Unit/Terminal (ONU/T) device in a Passive Optical Network (PON) access network is provided. The OLT device is configured to receive alarm and/or Attribute Value Change (AVC) messages from the ONU/T device. The OLT device is also configured to temporarily store the alarm and/or AVC messages in a message queue. The OLT device generates a flow control message indicating that the ONU/T device is to stop transmitting alarm and/or AVC messages to the OLT device, when the number of alarm and/or AVC messages in the message queue exceeds a first threshold. Then, the OLT device transmits the flow control message to the ONU/T device(s). An OLT device for transmitting a flow control message to an ONU/T device, and an ONU/T device and related method for receiving a flow control message are also provided. |
| US09602194B2 |
Transmission device, network designing device, activation method, and network designing method
A transmission device is used for a network that includes a plurality of working paths and a plurality of protection paths bypassing a relevant working path for each working paths. The transmission device includes a data plane unit that transmits and receives data to and from other transmission devices; and a signaling processing unit that performs switching, when a signaling message requesting activation to switch to a first protection path corresponding to a first working path is received, from the first working path to the first protection path, wherein, when the first working path is configured as a subset of a second working path and a second protection path corresponding to the second working path is provided, the signaling processing unit performs switching from the first working path to the first protection path and performs switching from the second working path to the second protection path. |
| US09602193B1 |
Transportation support network utilized fixed and/or dynamically deployed wireless transceivers
An application that creates a dynamic ad hoc network by wirelessly linking a plurality of mobile Bluetooth transceivers. The dynamic ad hoc network enables communication between a transmitting Bluetooth transceiver and a receiving Bluetooth transceiver through at least one intermediary Bluetooth transceiver exclusive of other higher power consuming and expensive communication protocols, such as cellular networks. The network provides a number of solutions, including transportation management, traffic alerts, traffic telematics, information associated with road signs, warnings of speed limit changes, navigation, emergency scenarios (more specifically in a condition where a cellular network is inoperable or unavailable), etc. Navigation can utilize GPS, motion sensors, references from RF beacons signals, and the like to determine a user's location and routing. |
| US09602186B1 |
Extending mobile network presence
Embodiments of the present invention may relate to extending a network's presence. A first device may compile an accepted device list including a second device. The first device may determine a network connection status, such as, for example, connected, weak connection, and disconnected. In response to determining the network connection status is disconnected, the first device may search for the second device. In response to determining the network connection status is connected, the first device may discontinue searching for the second device. In response to determining the network connection status is weak connection, the first device may search for the second device. The first device may evaluate connectivity information of the second device. The first device may communicate with at least one network via the second device. |
| US09602184B2 |
Wireless communication device, control method of wireless communication device and phase shifter
A wireless communication device includes a delay circuit to generate four or more delay signals, an amplifier circuit amplifying the four or more delay signals to generate four or more amplified delay signals, and a combiner circuit combining at least two amplified delay signals to generate an output signal, a second phase of a second amplified delay signal is between a first phase of a first amplified delay signal and a third phase of a third amplified delay signal, gains of the amplifier circuit for the four or more delay signals are controlled such that the output signal is generated by combining the first amplified delay signal and the third amplified delay signal, and a phase of the output signal is between the first phase of the first amplified delay signal and the third phase of the third amplified delay signal. |
| US09602176B2 |
Distributed antenna system for MIMO signals
A distributed antenna system includes a master unit configured to receive at least one set of multiple input multiple output (MIMO) channel signals from at least one signal source. The master unit is configured to frequency convert at least one of the MIMO channel signals to a different frequency from an original frequency, and combine the MIMO channel signals for transmission. An optical link couples the master unit with a unit remote from the master unit for transceiving the MIMO channel signals. Conversion circuitry is configured to frequency convert at least one of the first and second MIMO channel signals from the different frequency back to an original frequency for transmission over an antenna. |
| US09602175B2 |
Radio base station, master station apparatus, slave station apparatus, and control method
A master station apparatus modulates downlink digital control data that includes at least a synchronization signal and a control signal, adds resource element information to the modulated control data, and composites downlink digital frequency-domain user data that has not been modulated and data originating from the modulated control data to which the resource element information has been added. A slave station apparatus converts a received optical signal into an electrical signal, separates, from the electrical signal, the frequency-domain user data and the data originating from the modulated control data, modulates the frequency-domain user data, adds resource element information to the modulated user data, and transmits time-domain composite data including a component originating from the modulated user data and a component originating from the modulated control data by radio waves. |
| US09602171B2 |
Near field communication device
A near field communication device is disclosed herein. An example of such a device includes a user interface and an application that displays information on the user interface. The device also includes a non-transitory storage medium including a list of data elements that may appear within the information displayed in the user interface and a near field communication filter module to automatically extract any of the data elements from the information displayed on the user interface via the application. The example additionally includes a near field communication write module to automatically record any of the extracted data elements transferred by the near field communication filter module to a near field communication data tag. Examples of a method for use in a near field communication device and a non-transitory storage medium are also disclosed herein. |
| US09602170B2 |
Electrical instrument
An electrical instrument of the present invention includes: a main function section; a communication section that receives an aspect of a main function to be executed by the main function section from an external information terminal by near field communication; an input section for allowing a user to input an aspect of the main function to be executed by the main function section; a notification section for issuing a notice on information regarding the near field communication; a main function section control unit that controls the main function section based on the aspect of the main function, which is inputted to the input section, and based on the aspect of the main function, which is received by the communication section; a history recording unit that records a near field communication control history that is a history that the main function section control unit has controlled the main function section based on the aspect of the main function, which is received by the communication section; and a notification content decision unit that decides whether or not to issue the notice on the information regarding the near field communication in accordance with whether or not the near field communication control history is recorded in the history recording unit. |
| US09602167B2 |
Remote energy transfer system
A remote energy transfer system is provided that is capable of wirelessly transmitting data and power through barriers. Generally, the remote energy transfer system comprises at least one power antenna, at least one data antenna, and at least one link controller operatively coupled to the power antenna and the data antenna. The link controller can be configured to at least partially control the energy transfer from the power antenna and the data transfer of the data antenna. |
| US09602164B1 |
Methods and systems for making a pre-payment
Methods and systems are provided for making a pre-payment from a vehicle. In some embodiments, a user is provided with a mobile wallet; information populating at least one payment instrument to the mobile wallet is received; information that the mobile wallet is usable with respect to the vehicle is received; information that the mobile wallet has been presented by the vehicle to a payment location is received; an authorized pre-payment corresponding to items or an amount associated with the payment location is received; a token is received from the user at the payment location; and the pre-payment is settled using the payment instrument. |
| US09602162B2 |
Method for data transmission
A method for transmitting data in a direction of transmission of a clock signal, wherein positive and negative edges of the clock signal are transmitted by pulses with opposite polarity, wherein the polarity of the pulses is not inverted when no data is transmitted, and wherein the polarity of at least one pulse is inverted when data is transmitted. |
| US09602160B2 |
Apparatus and method for digitally cancelling crosstalk
Described is an apparatus which comprises: a first buffer to receive a first signal from a first transmission media; a second buffer to receive a second signal from a second transmission media separate from the first transmission media; a first summing node coupled to the first buffer, the first summing node to receive output of the first buffer; and a first digital adjustment circuit which is operable to drive a first adjustment signal to the first summing node when a transition edge of the second signal is detected. |
| US09602155B2 |
Transceiver element for an active, electronically controlled antenna system
A transceiver element for an active, electronically controlled antenna system includes a transmit path, a receive path and single-pole change-over switches having a common central connection and two connections for switching between the transmit path and the receive path. An amplitude controller and a phase adjuster are arranged between the common center connections of a first and second single-pole change-over switch. Single-pole multiple toggle switches having a common central connection and a number N of connections are present. The common central connection of the first and second single-pole change-over switch is connected to the common central connection of a first and a second single-pole multiple toggle switch respectively, and an amplitude controller and a phase adjuster are connected between each connection of the number N of connections of the first multiple toggle switch and the second multiple toggle switch. |
| US09602149B1 |
Architecture and control of hybrid coupler based analog self-interference cancellation
An apparatus for interference cancellation in a wireless communication system, includes a cancellation unit configured to receive a transmit (Tx) signal from an output port of a power amplifier and a receive (Rx) signal from an antenna, and generate a cancellation of a primary portion of the Tx signal from the Rx signal at an output thereof, leaving a residual portion as a residual Tx signal, wherein the output of the cancellation unit is coupled to an Rx input port of a transceiver. The apparatus further includes a compensation control unit configured to modify one or more signals within the cancellation unit, based on the residual Tx signal at the output of the cancellation unit. |
| US09602139B2 |
Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 3/15 and 16-symbol mapping, and bit interleaving method using same
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping. |
| US09602136B2 |
Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 4/15 and 256-symbol mapping, and bit interleaving method using same
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping. |
| US09602134B2 |
Operating method of error correction code decoder and memory controller including the error correction code decoder
An operating method of an ECC decoder includes receiving first chunk data and second chunk data from a nonvolatile memory device, the second chunk data subsequent to the first chunk data, performing error correction on the first chunk data, determining if the first chunk data includes an uncorrectable error bit and determining not to perform error correction on the second chunk data in response to the first chunk data including the uncorrectable error bit. |
| US09602132B2 |
Transmitter, encoding apparatus, receiver, and decoding apparatus
An encoding apparatus includes a dividing unit that divides an input signal bit sequence into data blocks and an encoding unit that applies error correction encoding to the data blocks to generate code blocks decodable by repetitive decoding calculations for estimating the reliability of signal bits for a plurality of times and a generation unit that generates redundant bits by performing bit calculations between data blocks of each set combining the divided data blocks; and an output unit that outputs the generated code blocks and redundant bits. |
| US09602131B2 |
Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 3/15 and 16-symbol mapping, and bit interleaving method using same
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping. |
| US09602129B2 |
Compactly storing geodetic points
Mechanisms are provided for the compact storage of geographical geometries as a collection of points, where individual points are encoded as binary/ternary strings (with the property that points closer to each other share a longer binary/ternary prefix) and the geometry is encoded by compressing the binary/ternary representation of common-prefix points. Mechanisms are also provided for the representation of a geometry using a ternary string that allows efficient storage of arbitrary shapes (e.g., long line segments, oblong polygons) as opposed to binary representations that are more efficient when the geometries are square or nearly square shaped. |
| US09602128B2 |
Split gain shape vector coding
The invention relates to an encoder and a decoder and methods therein for supporting split gain shape vector encoding and decoding. The method performed by an encoder, where the encoding of each vector segment is subjected to a constraint related to a maximum number of bits, BMAX, allowed for encoding a vector segment. The method comprises, determining an initial number, Np—init, of segments for a target vector x; and further determining an average number of bits per segment, BAVG, based on a vector bit budget and Np—init. The method further comprises determining a final number of segments to be used, for the vector x, in the gain shape vector encoding, based on energies of the Np—init segments and a difference between BMAX and BAVG. The performing of the method enables an efficient allocation of the bits of the bit budget over the target vector. |
| US09602127B1 |
Devices and methods for pyramid stream encoding
Devices and methods of reducing quantization noise using a pyramid stream encoder are generally described. Groups of D digital symbols are iteratively computed for a digital signal such that each group of symbols minimizes a norm of a weighted residue vector. The weighted residue vector is formed by applying predetermined weighting coefficients to components of a residue vector. Each component is a difference between a sample of the digital signal and a linear combination of different groups of digital symbols with predefined filter coefficients. The norm of the weighted residue vector evaluated at a rate D times slower than a sampling rate of an output signal. The groups of D digital symbols are provided as the output signal. |
| US09602125B1 |
Wideband InP digital-to-analog converter integrated with a SiGe clock distribution network
A digital-to-analog converter (DAC) including a DAC core circuit having a plurality of input lines each being responsive to a digital bit input signal and an output line outputting a converted analog signal of the digital bits. The DAC also includes a clock circuit responsive to a clock input signal at one frequency and outputting a clock output signal at another frequency. The DAC also includes a clock tree distribution network responsive to the clock output signal from the clock circuit and splitting the clock output signal into a plurality of split clock signals that are applied to the DAC core circuit, where the DAC core circuit is fabricated in an indium phosphide (InP) semiconductor material and the clock tree distribution network is fabricated in a silicon germanium (SiGe) semiconductor material. |
| US09602122B2 |
Process variable measurement noise diagnostic
A process variable transmitter, includes an analog-to-digital (A/D) converter that receives a sensor signal provided by a sensor that senses a process variable and converts the sensor signal to a digital signal. A processor receives the digital signal and provides a measurement output indicative of the digital signal. A noise detector receives the sensor signal and generates a first value indicative of a number of positive noise events relative to a positive threshold value and a second value indicative of a number of negative noise events relative to a negative threshold value. The processor evaluates the noise count and generates a noise output, indicative of detected noise, based on the first and second values. |
| US09602121B2 |
Background estimation of comparator offset of an analog-to-digital converter
A pipeline analog-to-digital converter (ADC) converts an analog input signal over several stages, where a stage generates a residue for the subsequent stage to digitize. The residue is generated by coarsely quantizing the analog input signal to generate a digital code, which is used to reconstruct the analog input signal, and the residue is the difference between the analog input signal and the reconstructed version of the analog input signal. The coarse quantization can have errors which are attributed to comparator offsets and bandwidth mismatch. To estimate the comparator offsets while being insensitive to bandwidth mismatch, peak and trough detectors are used to track maximum and minimum values of the residue or the output of the ADC over time, and an expected value estimating the comparator offset can be computed based on the maximum and minimum values. The expected value advantageously “averages” out the bandwidth mismatch contribution to the offset. |
| US09602120B1 |
Analog to digital converter with digital reference voltage signal
An analog to digital converter contain a plurality of comparators, each having a plurality of positive input voltage transistors and a plurality of negative input voltage transistors. Each positive input transistor is in communication with a positive input voltage, and each negative input transistor is in communication with a negative input voltage. Each comparator is configured to adjust a positive reference voltage and a negative reference voltage used to generate a binary comparator output for each comparator indicating a result of a comparison between a voltage differential defined by the positive input voltage and the negative input voltage and a unique voltage range indicated by a unique digital reference signal communicated to each comparator. |
| US09602117B2 |
Detection device, sensor, electronic apparatus, and moving object
A detection device includes a driving circuit and a detection circuit. The detection circuit includes first and second electric charge-voltage conversion circuits to which first and second detection signals are input, first and second gain adjustment amplifiers that amplify output signals of the circuits, a switching mixer that has first and second input nodes to which the output signals of the first and second gain adjustment amplifiers are input, and performs differential synchronous detection thereon on the basis of a synchronization signal from the driving circuit, so as to output first and second output signals to first and second output nodes, first and second filters that receive the first and second output signals from the first and second output nodes of the switching mixer, and an A/D conversion circuit that receives output signals from the first and second filters so as to perform differential A/D conversion thereon. |
| US09602114B2 |
Phase-locked loop with multiple degrees of freedom and its design and fabrication method
A design method for a phase-locked loop comprises: a controlled-frequency oscillator; a phase comparator, to determine a phase difference between an output signal of the controlled-frequency oscillator and a reference signal; a corrector to receive as input a signal representative of the phase difference and to generate at its output a first correction signal; at least one second corrector, to receive as input a signal representative of or affected by a phase noise of the reference signal or of the output signal of the controlled-frequency oscillator and to generate at its output a second correction signal; and a circuit for generating a slaving signal for the controlled-frequency oscillator on the basis of the first and second correction signals; the method using the H-infinity method. Method for fabricating such a loop comprising a design step implementing this method. Phase-locked loop thus obtained. |
| US09602113B2 |
Fast frequency throttling and re-locking technique for phase-locked loops
Certain aspects of the present disclosure support a method and apparatus for fast frequency throttling and re-locking in a phase-locked loop (PLL) device. Aspects of the present disclosure present a method and apparatus for operating in an open loop control (OLC) mode of the PLL device for generating a periodic signal. During the OLC mode, clocking of circuitry interfaced with a digitally-controlled oscillator (DCO) of the PLL device can be disabled. A PLL output frequency associated with the periodic signal generated by the DCO can be controlled directly through a digital control word input into the DCO. |
| US09602112B2 |
Clock delay detecting circuit and semiconductor apparatus using the same
Provided is a clock delay detecting circuit and semiconductor apparatus using the same that is capable of generating a period signal whose period is a delay time of a clock, dividing the period signal, and counting the divided period signal. The clock delay detection circuit comprises a period signal generating unit configured to generate a counting control signal, a period signal dividing unit configured to generate a counting enable signal by dividing the counting control signal, and a counting unit configured to generate a delay information signal by counting the counting enable signal with a clock, wherein the counting control signal has a period with a predetermined time. |
| US09602110B1 |
Oscillator amplifier biasing technique to reduce frequency pulling
An oscillator amplifier biasing technique configures an oscillator amplifier to operate at a bias point causing loading on a tank circuit to have reduced or negligible dependence on amplifier bias conditions or device characteristics. The bias signal level may vary with variation in temperature. The oscillator amplifier biasing technique includes determining a bias signal level that has a minimum sensitivity of the frequency of oscillation as a function of temperature. The technique may store associated data in non-volatile memory to describe the bias signal level dependence on temperature. A digital-to-analog converter may drive the bias signal of the oscillator to the minimum sensitivity point as a function of temperature. The technique may substantially reduce effects of up-conversion of flicker noise in the oscillator output signal as well as improve frequency accuracy in the presence of effects such as mechanical strain and/or aging. |
| US09602108B1 |
Lut cascading circuit
In an example, a LUT for a programmable integrated circuit (IC) includes a plurality of input terminals, and a cascading input coupled to at least one other LUT in the programmable IC. The LUT further includes LUT logic having a plurality of LUTs each coupled to a common set of the input terminals. The LUT further includes a plurality of multiplexers having inputs coupled to outputs of the plurality of LUTs, and an output multiplexer having inputs coupled to outputs of the plurality of multiplexers. The LUT further includes a plurality of cascading multiplexers each having an output coupled to a control input of a respective one of the plurality of multiplexers, each of the plurality of cascading multiplexers comprising a plurality of inputs, at least one of the plurality of inputs coupled to the cascading input. |
| US09602105B1 |
Performance-on-demand IC chip design in integrated-injection logic
A circuit comprising a first injection BJT in a common-base configuration and configured to output a first injection current at its collector. A first multiple-collector BJT is in an open collector configuration, is electrically coupled to the first injection BJT, and is arranged to receive the first injection current at its base. The first multiple-collector BJT has a capacitance load at one of its collectors. A first supply voltage is electrically coupled to the first injection BJT. The first supply voltage is configured to dynamically adjust during operation of the circuit in response to a change in the capacitance load of the first multiple-collector BJT. |
| US09602101B2 |
Integrated device with auto configuration
A method for controlling a configuration in an integrated circuit device with at least one controllable input/output port having a data output driver, a data input driver, a controllable pull-up resistor, a controllable pull-down resistor, each connected with an external pin of the integrated circuit device, has the steps of: enabling only the pull-up resistor and reading the associated input through the data input driver as a first bit; enabling only the pull-down resistor and reading the associated input through the data input driver as a second bit; tri-stating the first port and reading the associated input through the data input driver as another bit; encoding a value from the read bits; and determining a firmware operation form the encoded value. |
| US09602093B2 |
Zero-crossing voltage detection circuit and method thereof
A zero-crossing voltage detection circuit for detecting a phase voltage of a converter includes a comparator, a first transistor and a second transistor. The first transistor has a first base, a first collector and a first emitter. The first base couples with the first collector. The first emitter receives the phase voltage. The first collector provides a first voltage to a first terminal of the comparator. The second transistor has a second base, a second collector and a second emitter. The second base couples with the first base. The second base couples with the second collector. The second emitter receives a ground voltage. The second collector provides a second voltage to a second terminal of the comparator. The comparator compares the first voltage with the second voltage to generate a zero-crossing voltage signal. |
| US09602092B2 |
Dynamic margin tuning for controlling custom circuits and memories
Embodiments of a method that may allow for selectively tuning a delay of individual logic paths within a custom circuit or memory are disclosed. Circuitry may be configured to monitor a voltage level of a power supply coupled to the custom circuit or memory. A delay amount of a delay unit within the custom circuit or memory may be changed in response to a determination that the voltage level of the power supply has changed. |
| US09602083B2 |
Clock generation circuit that tracks critical path across process, voltage and temperature variation
Clock generation circuit that track critical path across process, voltage and temperature variation. In accordance with a first embodiment of the present invention, an integrated circuit device includes an oscillator electronic circuit on the integrated circuit device configured to produce an oscillating signal and a receiving electronic circuit configured to use the oscillating signal as a system clock. The oscillating signal tracks a frequency-voltage characteristic of the receiving electronic circuit across process, voltage and temperature variations. The oscillating signal may be independent of any off-chip oscillating reference signal. |
| US09602073B2 |
Bulk acoustic wave resonator having piezoelectric layer with varying amounts of dopant
A bulk acoustic wave (BAW) resonator structure includes a first electrode disposed over a substrate, a piezoelectric layer disposed over the first electrode, and a second electrode disposed over the piezoelectric layer. The piezoelectric layer includes undoped piezoelectric material and doped piezoelectric material, where the doped piezoelectric material is doped with at least one rare earth element, for improving piezoelectric properties of the piezoelectric layer and reducing compressive stress. |
| US09602055B1 |
Single-ended mixer with reduced loss
A single-ended mixer having a mismatched, high termination impedance is disclosed. The termination impedance can be mismatched by at least one order of magnitude higher than the standard impedance of a given design environment, such as a 50 Ohm environment for a radio frequency (RF) circuit. The termination impedance can be provided in close physical proximity to the mixer core of the single-ended mixer to allow a suitable bandwidth of operation. |
| US09602053B2 |
Audio FM transmitter
An audio FM transmitter is disclosed that may achieve high-precision frequency control as well as compact size and low cost by enabling FM modulation using a fractional-N type PLL circuit. |
| US09602052B2 |
Stable oscillator for use in an electronic circuit
An oscillator includes first, second, and third current sources, a resistor having first and second terminals, first and second capacitors each having first and second terminals, a switch circuit through which each of the current sources is connectable to the first terminal of one of the resistor and the two capacitors to supply current thereto, a comparator, and switch controller configured to generate control signals for the switch circuit and an oscillation output signal for each of multiple periods based on an output signal from the comparator. During one of the periods, the switch circuit is controlled to connect the first current source to the first terminal of the first capacitor, the second current source to the first terminal of the resistor, the first terminal of the resistor to a first input of the comparator, and the first terminal of the first capacitor to a second input of the comparator. |
| US09602050B1 |
System and method for controlling a voltage controlled oscillator
An electrical circuit includes: at least one inductor, at least one varactor, and at least two transistors, all of which electrically arranged to form a voltage controlled oscillator (VCO) having an oscillation frequency; wherein the at least two transistors includes a first transistor and a second transistor; wherein the first transistor has a first bulk terminal and a first parasitic diode disposed between the first bulk terminal and the first transistor; wherein the second transistor has a second bulk terminal and a second parasitic diode disposed between the second bulk terminal and the second transistor; wherein application of a first control voltage to the first bulk terminal, application of a second control voltage to the second bulk terminal, or application of first and second control voltages to the first and second bulk terminals, respectively, is effective to change the oscillation frequency of the VCO. |
| US09602048B2 |
Photovoltaic module
A photovoltaic module is discussed. The photovoltaic module includes a solar cell module including a plurality of solar cells and a junction box attached to a rear surface of the solar cell module, the junction box including a power conversion module to convert direct current (DC) voltage supplied from the solar cell module into alternating current (AC) voltage and to output the AC voltage, wherein the power conversion module included at least one bypass diode to receive the DC voltage from the solar cell module, a converter unit to power-convert the DC voltage from the at least one bypass diode, the converter unit including at least three interleaving converters, a capacitor to store voltage output from the converter unit, and an inverter unit to output the AC voltage using the voltage stored in the capacitor. Consequently, it is possible to stably output AC voltage. |
| US09602041B1 |
Software-controlled electronic circuit for switching power to a three-phase motor
The method of controlling a rotating three-phase motor involves generating in synchronism with the rotation of the motor a variable duty cycle pulse-width modulated signal for each of the switching circuit components used to supply current to the motor coils. The generated variable duty cycle pulse-width modulated signals control the switching circuit components to selectively place pairs of motor coils in current conducting states and to develop an associated varying voltage for each of the phases. This varying voltage is monitored to identify the one phase that is at a voltage in between the voltages of the other two phases. Then for the identified one phase, the variable duty cycle pulse-width modulated signal is specially generated so that when the switching circuit components of the other two phases are concurrently switched on, the switching circuit component of the identified one phase is not switched on. |
| US09602040B2 |
Apparatus for controlling first and second rotary electric machines
In an apparatus, a determiner determines whether a two-MG frequency ratio of a first electrical frequency of a first MG to a second electrical frequency of a second MG is within a specific frequency-ratio range. The specific frequency-ratio range includes 1/6n where n is an integer excluding zero. An update-cycle controller controls an update cycle of a command voltage according to the determined result such that the update cycle during a specific drive of the first MG is longer than the update cycle during a usual drive of the first MG while a cycle of a carrier signal is maintained during both the usual and specific drives. The specific drive represents drive of the first MG while the two-MG frequency ratio is within the specific frequency-ratio range. The usual drive represents drive of the first MG while the two-MG frequency ratio is out of the specific frequency-ratio range. |
| US09602039B2 |
PWM rectifier for motor drive connected to electric storage device
A PWM rectifier includes a main circuit unit which performs a power conversion on the basis of a PWM control signal, a DC voltage loop control unit which generates a current command, a current command restriction unit which sets, when an absolute value of the current command exceeds a limit value, the limit value as a final current command, and otherwise sets the current command as the final current command, a DC voltage loop saturation determination unit which determines a saturation state when the final current command is set to the limit value and otherwise determines as a non-saturation state, a DC voltage command calculation unit which changes the DC voltage command into a value obtained by adding an offset to a minimum or maximum value of the DC voltage value, and a PWM control signal generation unit which generates the PWM control signal from the final current command. |
| US09602037B2 |
Motor drive device and motor drive system
A motor drive device and motor drive system according to the present invention comprise: a power source terminal; a charging and discharging unit connected in series with the power source terminal; connection terminals to be connected to each of primary and secondary excitation coils for an anti-symmetric two phase motor; and a drive control unit which has a plurality of switching elements and respectively forms first and second paths by turning these switching elements on and off. The first path is used for independently supplying power to the respective primary and secondary excitation coils from the power source terminal via the connection terminals, and the second path is used for independent regeneration of each residual energy remaining in the primary and secondary excitation coils from the respective primary and secondary excitation coils into the charging and discharging unit via the connection terminals. |
| US09602035B2 |
Driving apparatus for electric motor
The present invention relates to a driving apparatus which performs vector control based on an output current of an inverter. The driving apparatus of the present invention includes a vector controller (11) for transforming three-phase output currents of an inverter (10) into a torque current and a magnetization current, and controlling the torque current and the magnetization current. The vector controller (11) includes a torque-voltage control section (21) for determining a torque-voltage command value based on a deviation between a torque-current command value and the torque current, a magnetization-voltage output section (23) for outputting 0 as a magnetization-voltage command value, a target-magnetization-current determination section (26) for determining a magnetization-current command value based on a deviation between a torque-voltage command value and a target-output-voltage value, and a target-output-voltage determination section (27) for determining the target-output-voltage value. |
| US09602032B2 |
BLDC motor system including parameter detecting circuit and operating method thereof
Provided is a BrushLess Direct Current (BLDC) motor system including a motor driving circuit configured to control a pulse-width-modulation (PWM) inverter in a first operation mode or a second operation mode according to a control signal, and output a switching signal according to each operation mode, the PWM inverter configured to receive the switching signal to output first three-phase voltages having a first frequency in the first operation mode, and output second three-phase voltages having a second frequency in the second operation mode, a sensorless BLDC motor configured not to operate in the first operation mode by operating based on three-phase voltages having a frequency in a different band from the first frequency, and operate in the second mode by operating based on three-phase voltages having a frequency in an identical band to the second frequency, and a parameter detecting circuit configured to calculate parameter information on the sensorless BLDC motor in the first operation mode by using sensing voltages sensed in the PWM inverter. |
| US09602030B2 |
Motor drive circuit and motor thereof
The present disclosure illustrates a motor drive circuit. The motor drive circuit includes a resistor module, a multiplexer, a data control unit, an analog-to-digital converter and a register. The resistor module receives an input voltage and generates at least one parameter voltage. The parameter voltage is associated with a motor speed curve of a motor. The multiplexer receives the parameter voltage. The data control unit controls the multiplexer to output the parameter voltage. The analog-to-digital converter receives the parameter voltage and converts the parameter voltage to digital form, and then outputs the digital parameter voltage to the data control unit. The register stores the digital parameter voltage outputted by the data control unit. A controller determines the motor speed curve according to the digital parameter voltage stored in the register, and drives the motor in response to the motor speed curve. |
| US09602027B2 |
Systems, methods, and assemblies for detecting stoppage of electric motors
A motor controller for an electric motor having a stator and a rotor. The motor controller includes a power input for receiving AC power from a power source; a control input for receiving a control signal from a control; and circuitry for switching power from the power source to the electric motor in response to the control signal. The circuitry is operable to: apply a driving waveform to the stator to cause rotation of the rotor; remove the driving waveform from the stator to cause the rotor to coast and eventually stop; apply a stop detection waveform to the stator while the rotor is coasting, wherein the stop detection waveform induces a waveform on the rotor which in turn induces a waveform back to the stator while the rotor is rotating; and monitor the stator to detect a characteristic of the waveform induced back to the stator to detect when the rotor has substantially stopped rotating. |
| US09602026B2 |
Temperature compensation for MEMS devices
A microelectromechanical system (MEMS) device includes a temperature compensating structure including a first beam suspended from a substrate and a second beam suspended from the substrate. The first beam is formed from a first material having a first Young's modulus temperature coefficient. The second beam is formed from a second material having a second Young's modulus temperature coefficient. The body may include a routing spring suspended from the substrate. The routing spring may be coupled to the first beam and the second beam. The routing spring may be formed from the second material. The first beam and the second beam may have lower spring compliance than the routing spring. The MEMS device may be a resonator and the temperature compensating structure may have dimensions and a location such that the temperature compensation structure modifies a temperature coefficient of frequency of the resonator independent of a mode shape of the resonator. |
| US09602023B2 |
Single chip grid connected solar micro inverter
The present invention provides an improved grid connected solar micro-inverter. The solar micro-inverter is provided with a single processor that performs both the functions for the control of the micro-inverter and runs the application program associated with it and implements a communication modem for connectivity to the grid or to the Internet cloud. The solar micro-inverter therefore needs only a single processor to perform both the micro-inverter control and modem communication functions, resulting in cheaper and smaller system implementation. |
| US09602019B2 |
Voltage-adjusting device and method in power conversion system
The present disclosure provides a voltage-adjusting device applied in a power conversion system including a Vienna rectifier, a direct current (DC) bus, and an inverter. The voltage-adjusting device includes a grid voltage sampling module for sampling a grid voltage, a given bus voltage calculation module, a voltage-adjusting module, a current control module and a pulse width modulation module. The given bus voltage calculation module calculates a given value of the DC bus voltage based on the grid voltage. The current control module receives a three phase AC current from the grid, the active current given signal and the reactive current given signal to output a three phase control voltage. The pulse width modulation module outputs a pulse control signal to the Vienna rectifier. |
| US09602017B2 |
Switching power source device, method of controlling switching power source device, and circuit for controlling switching power source device
A switching power source device according to one aspect of the present invention is a current-resonant DC-DC converter, and includes a control integrated circuit having an oscillation circuit that determines a switching frequency of switching elements and a burst control circuit that controls a burst operation in the standby mode, as well as an output voltage detecting unit connected to a secondary side of a transformer to detect an output voltage. The switching frequency of the switching element is determined by the oscillation circuit by the smaller of a first frequency control voltage generated from a voltage of an auxiliary coil disposed in the primary side of the transformer and a second frequency control voltage corresponding to the output voltage, and the burst control circuit generates the first frequency control voltage that gradually increases or decreases in accordance with the voltage of the auxiliary coil. |
| US09602016B2 |
Electrical circuit for delivering power to consumer electronic devices
An electrical circuit for providing electrical power for use in powering electronic devices, such as monitors, televisions, white goods, data centers, and telecom circuit boards, is described herein. The electrical circuit includes an input terminal configured to receive an input power signal, an output terminal configured to provide an output power signal, and a forward converter coupled to the input and output terminals. The forward converter includes a transformer, and a primary side regulation circuit coupled to a primary side of the transformer. The primary side regulation circuit includes a switching device coupled to the primary side, a current sense circuit configured to sense a current level on the primary side, and a controller configured to generate a pulse-width modulated control signal delivered to the switching device as a function of the sensed current level to regulate the transformer to deliver the output power signal at a desired voltage level. |
| US09602011B1 |
Gated bi-directional dual-rail series resonant converter power supply
A switching stage includes a first plurality of switches configured to produce an alternating current from a bulk voltage. A transformer has a primary and a plurality of secondaries, the primary configured to receive the alternating current. A second plurality of switches are coupled to a first of the plurality of secondaries through a first resonant filter to provide a first voltage output. A third plurality of switches are coupled to a second of the plurality of secondaries through a second resonant filter to provide a second voltage output, the second voltage output being of opposite polarity to the first voltage output. A controller is configured to control the second plurality of switches and the third plurality of switches according to on-and-off state of the first plurality of switches and criteria including whether an absolute value of the first voltage output or the second voltage output exceeds a reference voltage. |
| US09602001B1 |
Buck converter with a variable-gain feedback circuit for transient responses optimization
A buck converter includes a power stage circuit and a control circuit. The power stage circuit has a pair of switches, an output inductor, and an output capacitor. The control circuit has a current-sensing unit (CCS), an error-amplifying (EA) and transient-holding (TH) unit, a transient-optimized feedback unit (TOF), and a PWM generation unit. The CCS senses an output capacitor current. The EA with the TH receives a feedback voltage and a reference voltage to generate an error signal. The TOF receives the feedback voltage and the reference voltage to generate a proportional voltage signal by a variable gain value. The PWM generation unit receives the proportional voltage signal and a sensing voltage signal to generate a PWM signal. When the proportional voltage signal equals the sensing voltage signal, the switches are controlled by the PWM signal at an optimal time point so that transient responses are optimized. |
| US09602000B2 |
Power supply circuit and control method thereof
According to one embodiment, a power supply circuit includes a switching element to which a drive signal is supplied, a control value generating circuit that compares an output voltage and a reference voltage to generate a control value, and a comparison circuit that compares a feedback current and the control value. The power supply circuit has a generating circuit that generates a clock signal having a constant period in a PWM control mode and a clock signal according to the output voltage in a PFM control mode. The control value of the control value generating circuit is changed so that averages of the feedback current before and after the control mode switching become equal. |
| US09601995B1 |
Low power radio frequency envelope detector
A low power radio frequency envelope detector includes a charging transistor for controlling the charge supplied to an output capacitor. A first input capacitor couples an input signal to a gate of the charging transistor. A second input capacitor couples a first polarity of the input signal to a first diode such that the first diode is operable to couple charge to the first input capacitor and to the gate of the charging transistor in response to a positive excursion of the first polarity of the input signal. A third input capacitor couples a second polarity of the input signal to a second diode coupled in series with the first diode. The first and second diodes are operable to couple charge to the first input capacitor and to the gate of the charging transistor in response to a positive excursion of the first polarity of the input signal. |
| US09601992B2 |
System and method for suppressing a settling voltage in a switched mode power supply
This disclosure relates to a switching power supply with regulated voltage suppression to reduce transformer audio noise. The switching power supply is operable to be fed a zero crossing voltage and to generate an output voltage. The output voltage may have a voltage level set using a modulated gate signal. A circuit is provided to reduce audio noise in a switching power supply by setting a ringing suppression time of the modulated gate signal to a first time period when the zero crossing voltage is below a predetermined voltage threshold and to a second time when the zero crossing voltage is above the predetermined threshold voltage. |
| US09601991B2 |
Switching regulator control circuit
In a switching regulator control circuit according to aspects of the invention, a drain current is converted to a voltage Vis with a resistance. The voltage is delivered to a multiplication circuit. The multiplication circuit generates and outputs a voltage that is a product signal of the voltage and a voltage that is proportional to a duty factor. A comparator circuit compares the voltage with an error signal delivered to the other comparison input terminal of the comparator. When the voltage has reached the error voltage, the comparator delivers a turn-off instruction through an OR circuit to a terminal of a flip-flop. |
| US09601983B2 |
Flyback power converter with weighted frequency and quasi-resonance
The present invention provides a flyback power converter and a control circuit and a control method thereof. The flyback power converter includes: a power stage circuit, a voltage sense circuit, a current sense circuit, and a control circuit. When the flyback power converter operates in a quasi-resonant mode, the control circuit determines a time point of turning OFF a power switch in the power stage circuit according to a current sense signal, a pulse width modulation (PWM) frequency of a PWM signal, and a predetermined threshold, wherein the control circuit adaptively adjusts an ON period of the power switch, or adaptively adjusts an operation bandwidth or an amplifier gain of an error amplifier circuit in a feedback control loop according to the PWM frequency to mitigate an output voltage ripple. |
| US09601982B1 |
Switchable auxiliary supply circuit
A method of and device for reducing power loss in a voltage conversion circuit. The voltage conversion circuit comprises a main power circuit and a switchable auxiliary circuit, which comprises a first and a second winding circuits. A switch controls the use of the first winding circuit, the second winding circuit, or both to reduce power lose during the voltage conversion. |
| US09601980B2 |
Electromechanical transducer and electroacoustic transducer
An electromechanical transducer of the invention comprises a structural unit, an armature, and two elastic units. The structural unit includes magnets, a yoke and a coil. The armature has an inner portion disposed to pass through inside the structural unit and two outer portions protruding from the inner portion, and the armature constitutes a magnetic circuit with the structural unit via two regions through which components of the magnetic flux flow in reverse directions in the inner region. The elastic units give restoring forces to the outer portions in response to displacement of the armature due to magnetic forces of the magnetic circuit. Each of the elastic units includes a pair of elastic members symmetrically arranged via the armature in a direction of the displacement. Each of the elastic members has one end engaging one of the outer portions and another end engaging one of the elastic member attaching portions. |
| US09601978B2 |
Aluminum alloy rotor for an electromagnetic device
A rotor includes a shorting ring defining a plurality of cavities therein, and a plurality of conductor bars each integral with the shorting ring and having an end disposed within a respective one of the plurality of cavities. The shorting ring and each of the conductor bars are formed from an aluminum alloy including a lanthanoid present in an amount of from about 0.1 part by weight to about 0.5 parts by weight based on 100 parts by weight of the aluminum alloy. An aluminum alloy, and a method of forming a rotor are also disclosed. |
| US09601977B2 |
Rotating electric machine and method for manufacturing the rotating electric machine
A rotating electric machine includes: a stator core having a plurality of slots aligned along a circumferential direction; a stator having a stator coil with an enamel coating inserted into the slots of the stator core; and a rotor rotatably arranged over the stator core through a given gap. The stator coil includes: main coils of a plurality of phases in which a plurality of segment coils each having a rectangular cross-section wire formed into a substantially U-shaped wire in advance is connected to each other; a first sub-coil having a lead wire led from the slots and attached with an AC terminal, and connected to one end of the respective main coils; and a second sub-coil having a neutral wire led from the slots, and connected to the other end of the respective main coils. The lead wire and the neutral wire are each formed of a wire with a bend structure having a plurality of straights and bends. |
| US09601975B2 |
High altitude, high voltage rear terminal block assembly
A disclosed terminal block assembly for a generator includes a terminal block with a base with first and second transverse terminal surfaces adjoining one another. One of the terminal surfaces includes an increased width greater than a length of a cable terminal lug for providing a lightning strike and creepage barrier. The terminal surfaces include spaced apart protrusions extending from the first and second surfaces to provide spaced apart terminal areas overlapping the first and second surfaces. First and second terminal studs are disposed within each corresponding first and second terminal areas and are electrically connected by a bus bar. |
| US09601972B2 |
Stator bar clip adapter for liquid cooled dynamoelectric device
A stator bar clip adapter for a liquid cooled dynamoelectric device having a stator bar bottle clip coupled to a first stator bar and a stator bar leaf clip coupled to a second, same series-loop stator bar, and a related dynamoelectric device are disclosed. The stator bar clip adapter includes a bottle clip engaging member configured to engage a stator bar bottle clip; and a leaf clip engaging member coupled to the bottle clip engaging member and configured to engage a stator bar leaf clip. |
| US09601970B2 |
Gas turbine engine and electrical system
A gas turbine engine includes an electrical system that includes a controller coupled to a first inverter/converter controller, a second inverter/converter controller, and a converter/controller that is coupled to an energy storage device. The system is configured to provide electrical power to a first electrical bus and a second electrical bus, from first and second electrical machines, under the direction of the controller. The converter controller is configured to control the amount of electrical power supplied to the first electrical bus and the second electrical bus from the energy storage system. The amount of electrical power received from the first electrical bus and the second electrical bus, and energy supplied to the energy storage system are under the direction of the controller. |
| US09601969B2 |
Inhibiting rocking of loads driven by plural levers
An apparatus includes a load and a first armature. A first lever mechanically couples the first armature and the load. Motion of the first armature causes the first lever to pivot about a first pivot axis. The apparatus also includes a second armature and a second lever that mechanically couples the second armature and the load. Motion of the second armature causes the second lever to pivot about a second pivot axis. At least one stator is provided for creating magnetic flux for the first and second armatures to interact with, thereby to drive motion of the load. The apparatus also includes a coupling mechanism that couples the first lever and the second lever. The coupling mechanism is arranged to encourage common mode oscillation of the first and second levers and inhibit differential mode oscillation of the first and second levers, thereby to inhibit rocking of the load. |
| US09601962B2 |
Wind turbine, a generator, a rotor housing, and a method for making the rotor housing
Described is a wind turbine, a generator and a rotor housing for a generator with an external rotor, the rotor housing comprising a support structure, wherein the support structure is cylindrical shaped, a cone and a ring. The ring and the cone are attached together at an inner side of the cone in a horizontal plane, forming a front part of the rotor housing. The support structure is attached to the cone at a front end of the support structure, forming a side part of the rotor housing, and the support structure is formed out of segmented support structure parts. Also disclosed is the method for making the rotor housing. |
| US09601956B2 |
Three-phase permanent magnet type motor
A three-phase permanent magnet type motor has a stator in which a plurality of windings wound in a same direction are disposed, and the number of slots is 12n; a rotor in which the number of poles of the permanent magnet is 10n or 14n; and multilayer wiring boards for performing the connection so as to be 2m parallel. The three-phase permanent magnet type motor has a circuit configuration in which, among U-phase, V-phase, and W-phase, adjacent in-phase windings are connected in parallel and are connected in series with a like-pole winding of a symmetrical in-phase second winding group facing at 6-slot pitch angle, when a center of a first winding group of the adjacent in-phase windings is set as a reference axis, and in-phase transition wiring patterns are disposed on the same layer of the multilayer wiring boards in a line symmetrical manner. |
| US09601953B2 |
Ring magnet rotor of motor with coating material
A rotor of a motor capable of improving durability of the motor by increasing a bonding force between a ring magnet and a resin. The rotor includes a ring magnet having an insertion hole passing through the center thereof, a shaft inserted into the insertion hole, and a resin that is disposed between the insertion hole and the shaft and fixes the ring magnet and the shaft. The resin extends to upper and lower surfaces of the ring magnet so as to cover at least parts of the upper and lower surfaces of the ring magnet. |
| US09601951B2 |
Modular permanent magnet motor and pump assembly
A permanent magnet machine, a rotor assembly for the machine, and a pump assembly. The permanent magnet machine includes a stator assembly including a stator core configured to generate a magnetic field and extending along a longitudinal axis with an inner surface defining a cavity and a rotor assembly including a rotor core and a rotor shaft. The rotor core is disposed inside the cavity and configured to rotate about the longitudinal axis. The rotor assembly further including a plurality of permanent magnets for generating a magnetic field which interacts with the stator magnetic field to produce torque. The permanent magnets configured as one of internal or surface mounted. The rotor assembly also including a plurality of retaining clips configured to retain the plurality of permanent magnets relative to the rotor core. The pump assembly including an electric submersible pump and a permanent magnet motor for driving the pump. |
| US09601950B2 |
Permanent magnet motor
A permanent magnet motor (1) is configured such that mN≠K is satisfied to an integer m, where the pole number of a rotor (3) is K and the number of divided iron cores (10-12) of a stator (2) is N, and N values of r(θ), r(θ+360°/N), . . . , r(θ+(i−1)×360°/N), . . . , r(θ+(N−1)×360°/N) are equal so that the absolute value of the difference between any two of the N values becomes up to a predetermined value, where r(θ) is an inner radius defined as, on a plane perpendicular to a rotary shaft (7) of the rotor (3), a distance from the rotary shaft (7) center to a surface of the stator iron core (4) facing the rotor (3) where an angle from a fitting portion (15) of the partial iron core (10) is θ on the perpendicular plane, θ taking 0 to 360°/N. |
| US09601948B2 |
Wireless power transmission apparatus and method
A wireless power transmission apparatus includes a resonator configured to transmit power to another resonator, and a power supply unit configured to supply power to the resonator. The apparatus further includes a switching unit including a transistor configured to be turned on to connect the power supply unit to the resonator, and to be turned off to disconnect the power supply unit from the resonator, based on a control signal, and a diode connected in series to the transistor. |
| US09601947B2 |
Seismically responsive utilities control system with occupancy activation mechanism
A utilities control system with a DC powered control system located within a building or room and having in combination an occupant activation device, a seismic sensor and a wireless transmitter; a wireless receiver in combination with a utilities shut-off device, and whereby upon either a change in status of the occupant activation device or the sensing of a seismic event by the seismic sensor, a signal is transmitted from the wireless transmitter to the wireless receiver such that the utilities shut-off device is activated to stop delivery of utilities. |
| US09601942B2 |
Wireless power receiver and wireless power transferring method
Disclosed is a wireless power receiver to transfer power wirelessly received from a wireless power transmitter to a load. The wireless power receiver includes a first reception induction coil coupled with a reception resonant coil to receive AC power; a first rectifying diode to rectify the AC power received through the first reception induction coil; a second reception induction coil connected to the first reception induction coil and coupled with the reception resonant coil to receive the AC power; and a second rectifying diode to rectify the AC power received through the second reception induction coil, wherein the wireless power receiver changes a transferring path of the power provided to the load according to a polarity variation of the AC power received through the first and second reception induction coils. |
| US09601941B2 |
Charging device and method using dual-mode magnetic coupling for an automobile vehicle
A device (10) for charging a mobile terminal by magnetic coupling, includes a first charging module (11) designed to form a charging signal at a first charging frequency, a primary coil (13) composed of a set of turns, a ferromagnetic body (14), a second charging module (12) designed to form a charging signal at a second charging frequency, higher than the first charging frequency. Furthermore, the charging device includes first routing elements (150) designed to connect/disconnect the primary coil (13) to/from the first charging module (11) and to/from the second charging module (12), elements (16) for adjusting the number of turns on the primary coil (13) and elements (19) for saturating the ferromagnetic body (14) at the second charging frequency. A charging method is also described. |
| US09601939B2 |
Sensing temperature within medical devices
Devices, systems, and techniques for monitoring the temperature of a device used to charge a rechargeable power source are disclosed. Implantable medical devices may include a rechargeable power source that can be transcutaneously charged. The temperature of an external charging device and/or an implantable medical device may be monitored to control the temperature exposure to patient tissue. In one example, a temperature sensor may sense a temperature of a portion of a device, wherein the portion is non-thermally coupled to the temperature sensor. A processor may then control charging of the rechargeable power source based on the sensed temperature. |
| US09601935B2 |
Electronic apparatus
An electronic apparatus includes: a cradle includes a pedestal, a protrusion portion that protrudes toward a slope direction from an upper portion of the pedestal including a slope surface, and a first connector formed in the pedestal; and a display device include a display portion and a second connector formed on a surface of the display device, wherein, even when a back surface of the display device comes into contact with the slope surface of the protrusion portion and the display device is mounted on the cradle in a vertically placed manner, the first connector is connected to the second connector, and wherein, even when the back surface of the display device comes into contact with the pedestal and the display device is mounted on the cradle in a horizontally placed manner, the first connector is connected to the second connector. |
| US09601934B2 |
Charging stands arranged adjacently to reduce occupied area
Provided is a charging stand which, with a simple structure, prevents a force applied to a power cord from being transmitted directly to a connecting portion between the charging stand and the power cord.A charging stand 100 comprises a housing 110 having a seat portion 114 for placing an electronic apparatus 300 thereon and a charging mechanism for charging the electronic apparatus 300 when the electronic apparatus 300 is placed on the seat portion 114. A cord winding structure 140 for winding thereon a power cord 220 adapted to be connected to the charging stand 100 is provided at a bottom surface of the housing 100. |
| US09601933B2 |
Tessellated inductive power transmission system coil configurations
A system for inductive power transmission includes at least one interface surface and a plurality of triangular coil elements positioned underneath the interface surface such that at least one edge of the respective triangular coil element is adjacent to an edge of at least one other of the triangular coil elements. Each of the triangular coil elements may be operable to inductively transmit power to at least one coil of at least one electronic device and/or inductively receive power from the coil of the electronic device. Each triangular coil element may be operable to detect the proximity of one or more inductive coils of one or more electronic devices and inductively transmit power upon such detection at different frequencies, power levels, and/or other inductive power transmission characteristics. |
| US09601932B2 |
Balancing voltages between battery banks
A system that balances voltages between battery banks. The system includes battery banks, including a first bank and a second bank, and a first capacitor. The system also includes a first set of switching devices which selectively couple first and second terminals of the first capacitor to first and second terminals of the first bank, and to first and second terminals of the second bank. The system includes a clocking circuit which generates clock signals with substantially non-overlapping first and second clock phases. This clocking circuit is configured so that during the first phase the first and second terminals of the first capacitor are coupled to the first and second terminals of the first bank, respectively, and during the second phase the first and second terminals of the first capacitor are coupled to the first and second terminals of the second bank, respectively. |
| US09601923B2 |
Current limit management for multi-function systems
Exemplary methods are disclosed, which may include providing a conductive component configured to conduct a current to at least two electrical systems or elements. Methods may further include determining one of the electrical elements as a low-priority system and a second one of the electrical elements as a high-priority system, measuring or estimating a current associated with the at least two electrical systems to establish the current exceeds a predetermined parameter, and deactivating the low-priority system in response to at least the determination of the current exceeding the predetermined parameter. |
| US09601920B2 |
Transient voltage protection circuits and devices
According to an embodiment, a transient voltage protection circuit includes a first integrated circuit including an input node, an output node, a first transient voltage protection component coupled between the input node and a reference voltage node, and an impedance element coupled between the input node and the output node. The first transient voltage protection component has a first dynamic resistance and the output node is configured to be coupled to an electrostatic discharge (ESD) protection component having a second dynamic resistance that is greater than the first dynamic resistance. |
| US09601918B2 |
Systems and methods for controlling acceleration of a power generator
An electromagnetic braking system includes an electrically conductive disc coupled to a rotatable shaft of a power generation system for operating in an island mode. The rotatable shaft is operatively coupled between a prime mover and a generator for supplying power to an island grid. The electromagnetic braking system further includes a controller for receiving at least one status or synchronization signal and for generating a control signal based on the at least one signal and an inducting unit for applying an electromagnetic braking force on the electrically conductive disc when commanded by the control signal to regulate a rotational speed of the rotatable shaft. |
| US09601917B2 |
Short circuit prevention device
Disclosed is a device capable of preventing a short circuit even in the event of flooding. A terminal polarity fixing unit is disposed between an input terminal unit and an output terminal unit such that a first output terminal and a second output terminal are electrically connected to a neutral terminal and to a phase voltage terminal, respectively, all the time, regardless of how first and second input terminals are paired with the phase voltage terminal and the neutral terminal of an alternating-current outlet. First and second connecting terminals are electrically insulated from each other and spaced apart from each other while being exposed to one side of a body unit of a connecting terminal block made from an insulating body, and electrically connect the first and second output terminals to a load. A short circuit prevention conductor is connected to the first connecting terminal, which is in turn connected to the neutral terminal but is not connected to the second connecting terminal, and is arranged in the vicinity of the second connecting terminal so as to surround at least a portion of the side of the connecting terminal block, at least a portion of the upper portion of the connecting terminal block, and at least a portion of each of the side and upper parts of the connecting terminal block. When the connecting terminal block is flooded, the electric current flowing out of the second connecting terminal flows into the short circuit prevention conductor via the water, and an electric current sufficient for causing an electric shock does not flow to other sites. |
| US09601913B2 |
Rollable wire dispensing spool rack
A rollable dispenser for spooled wire includes equiangularly-spaced tubular braces which rigidly interconnect the frames adjacent their circular peripheral edges. One or more wire spools are retained between the platters on removable axles which span the distance between both platters at radial intervals. One or more spools may also be retained by a centrally positioned axle. For a preferred embodiment of the invention, each platter is constructed from a length of circularly-bent tubing, the ends of which are butt welded together to form a hoop. Each platter further includes a circular laminar plate that includes a circular rim, a central hub having a single axle aperture, and radial laminar spokes, each having an axle aperture, which join the rim to the hub. |
| US09601912B2 |
Compact transformer bushing
A compact electrical bushing has a separate insulating end cap removably attached to the shaft of the bushing at an end used for mounting a current transformer. The removably attached insulating end cap has a large outer diameter that increases the linear surface distance of the bushing. The outer diameter may be determined in a predefined manner based on the desired length of the shaft, and vice versa, with a larger outer diameter corresponding to a shorter shaft. The increased linear surface distance allows the bushing to meet minimum tracking distance with a shorter shaft relative to existing bushings. The shorter shaft reduces the footprint of switchgear and other electrical isolation equipment to which the bushing may be connected. The insulating end cap may be removed from the bushing as needed to allow the current transformer to be slid onto the bushing without having to pass over the end cap. |
| US09601911B2 |
Wire harness
A wire harness includes a first conductive path, a second conductive path, a first exterior member having a tubular shape and accommodating the first conductive path, and a second exterior member having a tubular shape and accommodating the second conductive path. An exterior accommodating groove is formed in a wall of the first exterior member. The exterior accommodating groove is recessed inward of the first exterior member. The second exterior member is accommodated in the exterior accommodating groove so as to be parallel to the first exterior member. |
| US09601908B2 |
Wire support member for an environmental control system
A wire support member for an environmental control system includes a bracket having an inner surface, an outer surface, and a thickness. A first arm projects from the bracket, a first flange projects from a first end of the first arm. The first flange includes a first harness support opening therethrough. A second arm also projects from the bracket parallel to the first arm, and a second flange projects from a second end of the second arm. The second flange has a second harness support opening therethrough. A ratio of a diameter of the first harness support opening and of the second harness support opening to the thickness of the bracket optimizes the routing and support for the wiring. |
| US09601906B2 |
Wavelength-tunable light source and wavelength-tunable light source module
A first arm portion and a second arm portion are provided so as to have a distance therebetween greater than a distance between input ends of two output waveguides and greater than a distance between an output end of a first output portion and an output end of a second output portion, the first arm portion forming a traveling path of light from one of the two output waveguides to the first output portion through a first optical amplifier, the second arm portion forming a traveling path of light from another one of the two output waveguides to the second output portion through a second optical amplifier. The first optical amplifier and the second optical amplifier have curved portions in which the first output portion and the second output portion are curved in a direction toward each other, and the first optical amplifier and the second optical amplifier respectively output light from the output end of the first output portion and the output end of the second output portion. |
| US09601902B2 |
Optical signal amplification
A method of optical signal amplification. Incident photons are received at a photodetector including a doped semiconductor biased by a power source. The photons generate a change in a reflective property, refractive index, or electrical conductivity of the doped semiconductor. For the change in reflective property or refractive index, a first optical signal is reflected off the photodetector to provide a reflected beam, or the photodetector includes a reverse biased semiconductor junction including the doped semiconductor within a laser resonator including a laser medium, wherein a second optical signal is emitted. For the change in electrical conductivity the photodetector includes a reversed biased semiconductor junction that is within an electrical circuit along with an electrically driven light emitting device, where a drive current provided to the light emitting device increases as the electrical conductivity of the photodetector decreases, and the light emitting device emits a third optical signal. |
| US09601901B2 |
Passive waveguide structure with alternating GaInAs/AlInAs layers for mid-infrared optoelectronic devices
Disclosed is a semiconductor optical emitter having an optical mode and a gain section, the emitter comprising a low loss waveguide structure made of two alternating layers of semiconductor materials A and B, having refractive indexes of Na and Nb, respectively, with an effective index No of the optical mode in the low loss waveguide between Na and Nb, wherein No is within a 5% error margin of identical to a refractive index of the gain section and wherein the gain section is butt-jointed with the low loss waveguide, and wherein the size and shape of the optical mode(s) in the low loss waveguide and gain section are within a 10% error margin of equal. Desirably, at least one of the semiconductor materials A and B has a sufficiently large band gap that the passive waveguide structure blocks current under a voltage bias of 15 V. |
| US09601900B2 |
Method and apparatus for determining optical fibre characteristics
An optical amplifier assembly for determining a parameter of an optical fiber configured to amplify an optical signal being propagated therethrough, the assembly comprising: at least one amplifier pump light source assembly configured to transmit light at a plurality of wavelengths into the optical fiber; a receiver configured to receive light that has propagated through at least part of the optical fiber; and a processor configured to determine the parameter of the optical fiber based on the received light. |
| US09601899B2 |
Adjustable mid-infrared super-continuum generator using a tunable femtosecond oscillator
A super-continuum system including: a fiber laser configured to output a pulse having a center wavelength; a first nonlinear waveguide configured to shift the wavelength of the pulse from the fiber laser; a first fiber amplifier of at least one stage configured to amplify the output from the first nonlinear waveguide; and a second nonlinear waveguide configured to spectrally broaden the output from the first fiber amplifier. |
| US09601896B2 |
Method and system for adjusting the alignment of a photonic beam
The method comprises: detecting the positions (uo, vo) and (u1, v1) of said photonic beam (L) according to the coordinate axes X, Y on a first and second plane XY, which cut an optical axis X at a first and second point, respectively; comparing the results of said positional detections (uo, vo) and (u1, v1), and: if there are discrepancies which lie outside the margin of error (p), adjusting the angle of the photonic beam (L) according to the angle α and/or the angle β in order to overcome said discrepancies; or if there are no discrepancies which lie outside said margin of error (p), considering the angle of said photonic beam (L) as being properly adjusted. The system is adapted to implement the method set out by the invention. |
| US09601891B2 |
Apparatus and method for assembling cable
A cable assembling apparatus for allowing a terminal and a electric wire to be accurately crimped and to resolve increase of facility cost incurred by separation of a press and a crimping machine, includes a press having a downside press mold having a plurality of types of dies arranged in parallel, an electric wire support jig arranged in parallel, having a metal plate guide at an end thereof entering into between the plurality of types of dies, and a feeder adapted to lift the electric wire support jig together with the metal plate above the dies of the downside press mold, and advance and descend the electric wire support jig to an adjacent die of next process. Furthermore, an electric wire chuck disposed in a midstream die of the plurality of types of dies and supplying the electric wire support jig with the electric wire is disposed. |
| US09601890B1 |
Electrical terminal applicator with a composite frame
An electrical terminal applicator with a molded frame composed of a polymer base material mixed with 10% to 25% total weight of a reinforcing material such as glass fiber or carbon fiber. Prior to injecting the mixture into a mold, steel inserts for attaching various components are installed in the mold. A feed mechanism feeds a terminal strip into a crimp region. A plunger with a crimp punch reciprocates vertically within a plunger channel in the frame. An anvil is mounted to the base plate and extends into the crimping region. The punch and anvil are shaped to crimp the terminal to the wire conductor. |
| US09601884B2 |
Connector
A connector includes a first connector having first female contacts, first male contacts and a first insulation portion disposed between each first female contact and an adjacent first male contact, and a second connector having second female contacts, second male contacts and a second insulation portion disposed between each second female contact and an adjacent second male contact, provided that a width of each first female contact and second female contact on fitting is denoted by W1, a width of the first insulation portion and the second insulation potion by W2, and a width of each first male contact and second male contact by W3, a distance between centers of one first female contact and an adjacent first male contact and a distance between centers of one second female contact and an adjacent second male contact are each smaller than a sum of W1/2, W2 and W3/2. |
| US09601883B1 |
USB connector
A USB Type-C connector includes a transmission conductor group arranged according to functions and positions associated with electric characteristics. The transmission conductor group includes a first signal transmission conductor group, a second signal transmission conductor group, and a power transmission conductor group. Considering the way of arrangement, the second signal transmission conductor group is located at one side of the first signal transmission conductor group and the power transmission conductor group is similarly located at one side of the first signal transmission conductor group. As such, with such an arrangement, advantages of improved interference resistance, bettered performance of high frequency, and large electric current can be achieved. |
| US09601876B2 |
Electrical connector assembly
An electrical connector assembly for electrically connecting to a chip module, includes a first metal casing having a first accommodating cavity, a first electrical connecting base received in the first accommodating cavity, a second metal casing having a second accommodating cavity, and a second electrical connecting base received in the second accommodating cavity. The second metal casing includes a fixing portion fixed to an outer surface of the first metal casing, and the second metal casing is fixed onto a circuit board. The first and second electrical connecting bases mate with first and second mating plugs. The first and second mating plugs are configured to transmit signals of different specifications. It is convenient to separate or combine the first electrical connecting base and the second connecting base. |
| US09601875B2 |
Multi-wire shielded cable and method for manufacturing such a cable
A cable includes a connector and a lead. The lead has wires and a shield. The shield is folded over at one end of the lead so that, in a section, a first layer of the shield and a second layer of the shield are disposed at a radial offset to each other. A first crimped sleeve disposed in the section between the first layer and second layers of the shield. A second crimped sleeve disposed in the section radially outwardly with respect to the first and second layers of the shield. |
| US09601874B2 |
Connector and transmission line structure
A connector including one and the other first terminals, a second terminal, and a third terminal that are partially held in a body and spaced from each other along a first direction. The middle portion of each first terminal extends obliquely and has parallel edges. The second middle portion of the second terminal extends obliquely and has parallel edges being non-parallel to the edges of the first middle portions. The third terminal extends between the one first terminal and the second terminal and includes a third middle portion extending obliquely. Of the non-parallel edges of the third middle portion, one edge next to the second middle portion is substantially parallel to the edges of the second middle portion, and the other edge next to the first middle portion of the one first terminal is substantially parallel to the edges of the first middle portion of the one first terminal. |
| US09601873B2 |
Communications jack with jackwire contacts mounted on a flexible printed circuit board
Communications jacks include at least first through third jackwire contacts and a flexible substrate that has a first finger and a second finger. The first jackwire contact and the third jackwire contact are each mounted on the first finger and the second jackwire contact is mounted on the second finger. |
| US09601871B2 |
Locking device for a plug-in connector housing
The invention concerns a locking device for a multi-part plug connector housing (1) comprising a housing upper portion (20) and a housing lower portion (10) fitting thereto, wherein the housing upper portion (20) and the housing lower portion (10) can be reversibly mechanically connected together by way of a spring plate (30), wherein the spring plate (30) is arranged in the interior of the housing upper portion (20) and/or of the housing lower portion (10), wherein the spring plate (30) is operatively connected to a single, outwardly disposed actuating knob (40). |
| US09601870B1 |
Locking structure of connector assembly
A locking structure of a connector assembly has a plug and a receptacle, the plug including a plug shell, a sleeve disposed on outer periphery of the plug shell, and a C-ring disposed between the plug shell and the sleeve, the receptacle including a receptacle shell having an end that is inserted between the plug shell and the sleeve when the receptacle is fitted to the plug, the C-ring having an inclined sleeve contacting surface on its outer periphery and an inclined receptacle shell contacting surface on its inner periphery, the C-ring being elastically deformable between a first state and a second state, a fitted state between the plug and the receptacle being locked when, with the C-ring being in the first state, the sleeve contacting surface comes in contact with the sleeve and the receptacle shell contacting surface comes in contact with the receptacle shell. |
| US09601868B2 |
Module latch actuator
A module having a front/rear and top/bottom orientation comprising a housing having a front and rear end; a connector at the front end of the housing for interengaging with a mating connector having purchase point; a resilient latch having a secured end secured to the housing, and a free end forward of the secured end, the free end being biased toward the housing and configured to releasibly engage the purchase point; and an actuator moveably attached to the housing, the actuator being disposed under the latch and having a contact portion which contacts the latch as the actuator is pulled rearward to urge the latch away from the housing, thereby freeing the free end from the purchase point. |
| US09601867B2 |
Cord retention and moisture seal for electric motors
A fluid-tight strain relief seal for a cable connecting an electric device is disclosed. In a housing for an electrical device an integrally molded nipple is provided that is configured to carry an electrical cable therethrough. The nipple comprises a proximal portion and a distal portion, the distal portion being closer to an exterior wall of the housing and the proximal portion shaped like a barb. A sleeve is fixed over the cable, the barb and the nipple to provide the seal. |
| US09601865B2 |
Closure seal for electrical adaptor
A closure seal that provides an environmental seal about an electrical cable which includes an upper sealing block adapted to be clamped to a lower sealing block so that the cable is encompassed by the two sealing blocks, each block composed of a resilient deformable material and includes a pair of spaced apart arms disposed within the blocks. Each arm lying on a line that is substantially radial to the cable and being pivoted at the end remote from the cable. The seal is useful for sealing an electrical adaptor of the type which incorporates a socket that accepts a plug rated to a first maximum current load, a circuit breaker set for the first maximum current load, a residual circuit device and wherein the socket is enclosed in a compartment adapted to receive the plug and the compartment is provided with a releasable cover. |
| US09601860B2 |
Rotatable power center for a work surface
A rotatable power center is configured for installation along a work surface or the like, and includes an outer housing and a pivotable inner housing having one or more electrical or data outlets. The inner housing is positionable between a use position in which the outlets are accessible along the work surface, and a non-use position in which the outlets are generally not accessible. The outer housing defines an upper opening through which different surfaces of the inner housing are exposed or accessible, depending on the inner housing position. Spindles or spindle caps are used to pivotable mount the inner housing to the outer housing, and may also serve to secure two inner housing pieces together. A separate latch may be provided to secure the inner housing at the use or non-use position. Optionally, a detent arrangement holds the inner housing at the use or non-use position. |
| US09601854B2 |
Female terminal
A terminal contact portion (15) of a female terminal (11) includes: a bottom plate (35); a first side plate (37) and a second side plate (41); a top plate (39) continuously bent from the first side plate (37); an elastic piece (19) bent to be overlaid on the top plate (39) at an elastic piece bent portion (47) corresponding to an end portion of the top plate (39) along a terminal lengthwise direction; a pair of engaging projections (43) provided to project in a bent edge portion of the elastic piece (19); and a pair of engaging holes (45) formed in the first side plate (37) correspondingly to the engaging projections (43). |
| US09601850B2 |
Displaceable insulation barrier
The invention relates to an arrangement for increasing the insulation coordination between at least two electric potentials on a printed circuit board (2), said arrangement comprising the printed circuit board (2) and an insulation barrier (3), wherein the printed circuit board (2) has an opening (7) between the electric potentials, and the insulation barrier (3) is disposed on the printed circuit board (2) so as to be displaceble through the opening (7) and is designed such that the isolating distance between the two electric potentials can be enlarged by displacing the insulation barrier (3) relative to the printed circuit board (2). The arrangement makes it possible obtain a high packing density on the printed circuit board (2). |
| US09601849B2 |
Substrate-connecting electric connector and substrate-connecting electric connector device
A smooth mating operation is enabled by a simple configuration in a state in which electric connectors are easily and reliably positioned. A plug-side mating guide member made of metal projecting to an outer side from a wiring substrate is provided with guide surfaces, which contact part of a counterpart connector and slide so as to carry out positioning of a mating operation. Apart from which the plug-side mating guide member projects from the wiring substrate is directly or indirectly checked visually. As a result, the mating operation can be carried out while approximating the mutual mating positional relation of both of the electric connectors, and the mating positional relation is regulated to a predetermined state by guiding actions of the guide surfaces of the plug-side mating guide member so that the mutual mating operation of the electric connectors is easily and precisely carried out. |
| US09601848B2 |
Vertical socket contact with flat force response
An apparatus includes a plurality of contact elements to provide electrical continuity between an integrated circuit and an electronic subassembly, wherein a contact element includes a spring element and a separate lead element, wherein the spring element is arranged to be substantially vertically slidable over at least a portion of the lead element in response to a force applied to the contact element. |
| US09601847B2 |
High density multichannel twisted pair communication system
A twisted pair communications device and associated twisted pair communications system are disclosed. One twisted pair communications device includes a plurality of twisted pair connectors each associated with a different twisted pair communication channel, and a multi-channel connector communicatively connected to each of the plurality of twisted pair connectors. The multi-channel connector is configured to transmit and receive communication signals associated with each of the twisted pair communication channels on a multi-channel twisted pair cable and includes a plurality of wire pairs disposed in a plurality of rows within the connector. Fewer than all of the plurality of wire pairs are communicatively connected to twisted pair connectors, and wherein unassociated wire pairs in the multi-channel connector separate at least two groups of wire pairs associated with different twisted pair communication channels. |
| US09601846B2 |
Temporary electrical grounding system having a magnetic assembly cooperating with a conductive pipe to be grounded
A system and apparatus for providing a temporary electrical bonding/grounding connection. The apparatus includes an electrically conductive cable having first and second ends. The first conductive coupling is electrically coupled to the first end of the cable and a first magnetic assembly. The magnet assembly includes multiple surfaces which cooperate with an arcuate surface of a first conductive member to be grounded, with respective surfaces of the multiple surfaces being configured to properly mount to respective arcuate surfaces of respective first conductive members having different radiuses of curvature. The first magnetic component is detachably and electrically coupled to the first conductive coupling. The first magnetic component is configured to be electrically and magnetically coupled to the first conductive member. A second conductive coupling is electrically coupled to the second end of the cable, the second conductive coupling configured to be detachably and electrically coupled to a second conductive member. |
| US09601841B2 |
Wire terminal assembly and adapter kit
An assembly is provided for a connector of an electrical wiring device having a base with a plurality of electrical terminals having a connecting screw. The assembly includes a plurality of terminal connector with a base extending from the first end and having a screw hole for coupling to one of the electrical terminals by a connecting screw. The leg has a screw hole receiving a coupling screw for electrically connecting a wire to the terminal connector and the terminal of the electrical wiring device. A clamping member receives the coupling screw for clamping the wire between the leg and clamping member. A cover encloses the terminal connectors and includes one or more apertures directing a wire through the cover to the terminal connector assembly to clamp the wire in place Access openings are provided in a wall of the cover to access the coupling screws for clamping wires to the terminal connector assembly. |
| US09601840B2 |
Terminal connection strip, method of manufacturing crimp terminal, wire crimping device, and method of crimping wire
The terminal connection strip includes: a carrier formed in a strip shape; and a plurality of terminal fitting which project from at least one edge side of the carrier in a width direction. The terminal fitting includes a crimping section which connects by crimping at least a conductor tip of an insulated wire provided with the conductor tip where a conductor is covered with an insulating cover and the conductor is exposed by peeling off the insulating cover on a distal end side of the insulated wire to the terminal fitting. The crimping section is formed into a hollow shape which allows the insertion of at least the conductor tip from a proximal end side of the crimping section and allows the crimping section to surround the conductor tip. |
| US09601837B2 |
Spin-welded electrical ground and spin welding methods
A friction-welded ground assembly that includes an alloy substrate with a clearance hole; an aluminum alloy weld nut having a bolt bore and an outer wall; and a grounding bolt. The bore is located substantially within the clearance hole and a portion of the outer wall is joined to the substrate at a friction-welded attachment. Further, the bolt is threaded within the bore. In addition, a method for making a ground includes the steps: rotating an aluminum alloy weld nut having an outer wall at a predetermined speed; lowering the outer wall of the rotating nut into contact with an aluminum alloy substrate to generate a frictional force for a friction time; arresting the rotation of the nut; and applying an axial forging force to the outer wall and the substrate for a forging time. |
| US09601836B2 |
Front feed microwave antenna
A front feed microwave antenna, which comprises a radiation source, a first metamaterial panel used for radiating an electromagnetic wave emitted by the radiation source, a second metamaterial panel, and a reflective panel affixed to the back of the first metamaterial panel. The electromagnetic wave is emitted via the first metamaterial panel, refracted by entering the second metamaterial panel, reflected by the reflective panel, and finally re-refracted by reentering the second metamaterial panel, then finally parallel-emitted. |
| US09601835B2 |
Offset feed satellite television antenna and satellite television receiver system thereof
Disclosed is an offset feed satellite television antenna comprising a metamaterial panel (100) arranged behind a feed (1). The metamaterial panel (100) comprises a core layer (10) and a reflective panel (200) arranged on a lateral surface of the core layer (10). The core layer (10) comprises at least one core layer lamella (11). The core layer lamella (11) can be divided into multiple belt areas on the basis of refractive indexes. With a fixed point as a center, the refractive indexes on the multiple belt areas are identical at a same radius, while the refractive indexes on each belt area decrease gradually as the radius increases. For two adjacent belt areas, the minimum value of the refractive indexes of the inner belt area is less than the maximum value of the refractive indexes of the outer belt area. A connection between the center and the feed (1) is perpendicular to the core layer lamella (11), while the center does not overlap the center of the core layer lamella (11). In addition, the present invention also provides a satellite television receiver system having the offset feed satellite television antenna. The present invention allows for facilitated manufacturing and processing, and for further reduced costs. |
| US09601833B2 |
Broadband notch antennas
This disclosure is directed to broadband notch antennas. In one aspect, a notch antenna includes a dielectric plate having a first surface and a second surface located opposite the first surface. A conductive layer is disposed on the first surface and has a notch region that exposes the dielectric plate between edges of the conductive layer. The antenna also includes two or more frequency matching circuits that branch from the notch region. Each matching circuit is configured to send and receive electromagnetic radiation in a frequency band of a radio spectrum. |
| US09601831B2 |
Radio device
A radio device of the present invention includes a radiation conductor which converts a radio frequency signal into an electric wave and radiates the electric wave; a circuit board electrically connected to the radiation conductor and incorporating an electric circuit for supplying the radio frequency signal to the radiation conductor a planar grounded conductor electrically connected to the electric circuit on the circuit board and placed such that the grounded conductor faces the radiation conductor, the grounded conductor constituting a ground of the radiation conductor; and a resin-made casing for accommodating the radiation conductor, the circuit board and the grounded conductor; wherein the grounded conductor, the circuit board and the radiation conductor are placed in this order in a thickness direction of the circuit board. |
| US09601825B1 |
Mobile device
A mobile device includes a ground element, a first antenna, a second antenna, and a filter. The filter is disposed between the first antenna and the second antenna. The filter includes a main branch and a tuning branch. The tuning branch is coupled through the main branch to the ground element. The first antenna and the second antenna cover the same operation frequency band. The filter is configured to enhance the isolation between the first antenna and the second antenna in the operation frequency band. |
| US09601824B2 |
Slot antenna integrated into a resonant cavity of an electronic device case
An electronic device case includes a conductive cap section and a conductive bezel section forming a perimeter outside the conductive cap section and separated from the conductive cap section by a bezel gap. A conductive ground plane section forms a perimeter and is positioned opposite the conductive cap section and the conductive bezel section. The conductive ground plane section is separated from the conductive bezel section by a perimeter gap. One or more components reside between the conductive cap section and the conductive ground plane section forming a resonant cavity including a ground plane resonant cavity portion between the one or more components and the conductive ground plane section and a substantially annular resonant cavity portion between the one or more components and the perimeters of the conductive bezel section and the conductive ground plane section. |
| US09601823B2 |
Mobile device housing including at least one antenna
Embodiments of systems and methods for providing in-mold laminate antennas are generally described herein. Other embodiments may be described and claimed. |
| US09601821B2 |
Load cell topology network based on multi-branch cables
The present invention relates to a load cell topology network comprising at least one multi-branch cable and a plurality of load cells. Each multi-branch cable comprises at least three connectors and one or more groups of signal lines; each group of signal lines comprise at least three branch signal lines, with one end of each branch signal line connected to at least three connectors described respectively and correspondingly, and the other end of each branch signal line connected to a common node, thereby realizing the interconnection of the same kinds of electrical signals between respective connectors; each connector is adapted to be connected to another multi-branch cable or a load cell. The plurality of load cells are electrically connected by the multi-branch cable to form a topology network. |
| US09601819B2 |
Dielectric waveguide with extending connector and affixed deformable material
A dielectric wave guide (DWG) has a dielectric core member that has a first dielectric constant value. A cladding surrounding the dielectric core member has a second dielectric constant value that is lower than the first dielectric constant. A mating end of the DWG is configured for mating with a second DWG having a matching non-planar shaped mating end. A deformable material is disposed on the surface of the mating end of the DWG, such that when mated to a second DWG, the deformable material fills a gap region between the mating ends of the DWG and the second DWG. |
| US09601816B2 |
Dielectric line and electronic component
A dielectric line includes a line portion and a surrounding dielectric portion. The line portion is formed of a first dielectric having a first relative permittivity. The surrounding dielectric portion is formed of a second dielectric having a second relative permittivity. The line portion propagates one or more electromagnetic waves of one or more frequencies within the range of 1 to 10 GHz. In a cross section orthogonal to the direction of propagation of the one or more electromagnetic waves through the line portion, the surrounding dielectric portion is present around the line portion. The first relative permittivity is 1,000 or higher. The second relative permittivity is lower than the first relative permittivity. |
| US09601815B2 |
Battery system having battery cells and an apparatus for controlling the temperature of the battery cells
A battery system includes a plurality of battery cells connected to one another and includes an apparatus configured to control the temperature of the plurality of battery cells. The apparatus includes at least one hollow body through which a coolant flows and includes at least one heat conducting element having at least one first contact region and at least one second contact region. The at least one first contact region has a planar configuration and is in thermal contact with a side face of at least one battery cell of the plurality of battery cells. The at least one second contact region is arranged on the at least one hollow body such that the at least one second contact region is in thermal contact with the at least one hollow body. |
| US09601814B2 |
Battery maintenance alert device and process
The invention provides a battery maintenance alert process and device capable of tracking one or more operational variables for a lead-acid battery and lead-acid battery-operated equipment and alerting the user of the battery or battery-operated equipment when it is time to perform battery maintenance or service. |
| US09601803B2 |
Non-flammable quasi-solid electrolyte-separator layer product for lithium battery applications
A separator-electrolyte layer product for use in a lithium battery, comprising: (a) a porous thin-film separator selected from a porous polymer film, a porous mat, fabric, or paper made of polymer or glass fibers, or a combination thereof, wherein the separator has a thickness less than 500 μm; and (b) a non-flammable quasi-solid electrolyte containing a lithium salt dissolved in a liquid solvent up to a concentration no less than 3 M; wherein the porous thin-film separator is coated with the quasi-solid electrolyte so that the layer product exhibits a vapor pressure less than 0.01 kPa when measured at 20° C., a vapor pressure less than 60% of the vapor pressure of the liquid solvent alone, a flash point at least 20 degrees Celsius higher than a flash point of the first liquid solvent alone, a flash point higher than 150° C., or no detectable flash point. |
| US09601800B2 |
Charging method
A charging method to charge a lithium ion battery in a short amount of time at low cost without degradation of the lithium ion battery is provided. A lithium ion battery includes a lithium compound containing iron as a positive electrode active material. The lithium ion battery is charged through a quasi-constant voltage charging procedure. The lithium ion battery includes a lithium compound as a positive electrode active material used for a positive electrode material. With the lithium compound, a voltage in a flat voltage section of a charging characteristic curve is higher than a voltage of a battery including the lithium compound containing iron as the positive electrode active material. The lithium ion battery may be an assembled battery including a plurality of electric cells connected in series. |
| US09601797B2 |
Fuel cell stack manifold with ejector function
A fuel cell stack manifold having an ejector function of which the manufacturing cost and the weight can be reduced by optimizing hydrogen supply and recirculation channels and removing other members. hardware without a separate ejector structure for additionally attaching an ejector, of which the productivity can be improved by removing from an ejector assembly process. The fuel cell system minimizes joints through which hydrogen may leak, by implementing a new structure of a manifold added with an ejector function by integrally forming/manufacturing a stack manifold having a venturi and diffuser structure and adding a nozzle thereto. |
| US09601796B2 |
Fuel cell arrangement
A fuel cell arrangement is disclosed. The fuel cell arrangement includes a fuel cell stack and a housing wall element to form a housing surrounding the fuel cell stack. The housing wall element comprises a penetrating opening for an electric contacting of the fuel cell stack via a conductor. The conductor extends through the penetrating opening. A sheath is arranged between the penetrating opening wall and the conductor around an insulation layer arranged at the conductor. The sheath, together with the insulation layer, is pushed against the conductor in a gas-tight fashion, with the penetrating opening being sealed in a gas-tight fashion via a compensation element to compensate for longitudinal and lateral movements. The compensation element is lastingly fastened at the sheath element and the housing wall element in a gas-tight fashion. |
| US09601787B2 |
Fuel cell system having a circulating circuit, a radiator, a bypass passage and a three-way valve
A radiator cap is connected to a circulating circuit at a connecting point located upstream of a water pump in a flow direction of coolant and that regulates a pressure in the circulating circuit to be within a predetermined pressure range that is higher than or equal to an atmospheric pressure at the connecting point. A rotary valve is disposed in the circulating circuit at upstream of the connecting point of the radiator cap in the flow direction of coolant. Accordingly, a cavitation is restricted from occurring, and the water pump can perform enough efficiency. A communication passage that has an upstream end and a downstream end connected to the circulating circuit may be disposed instead of the radiator cap. In this case, a pressure regulating valve is disposed in the communication passage. |
| US09601785B2 |
Fuel cell
An oxidant gas conduit communicating with both an oxidant gas inlet communication hole and an oxidant gas outlet communication hole is formed in a surface of a cathode-side metallic separator which forms a fuel cell. Continuous linear guide ridges which protrude from intermediate height sections to the oxidant gas conduit side and form continuous guide conduits are provided on the cathode-side metallic separator. The linear guide ridges are continuously connected to ends of rectilinear conduit ridges which form rectilinear conduits, are provided with bend portions, and are set to lengths which are different from each other in a step-like manner. |
| US09601774B2 |
Use of xanthan gum as an anode binder
Xanthan gum has been found to be a superior binder for binding an electrode, especially an anode, in a lithium-ion or lithium-sulfur battery, being able to accommodate large volume changes and providing stable capacities in batteries tested with different types of anode materials. |
| US09601770B2 |
Precursor for preparation of lithium composite transition metal oxide and method of preparing the same
Disclosed are a transition metal precursor for preparation of a lithium composite transition metal oxide, the transition metal precursor including a composite transition metal compound represented by Formula 1 below and a hydrocarbon compound, and a method of preparing the same: MnaMb(OH1-x)2 (1) wherein M is at least two selected from the group consisting of Ni, Co, Mn, Al, Cu, Fe, Mg, B, Cr, and second period transition metals; 0.4≦a≦1; 0≦b≦0.6; a+b≦1; and 0≦x≦0.5, in which the transition metal precursor includes a particular composite transition metal compound and a hydrocarbon compound, and thus, when a lithium composite transition metal oxide is prepared using the same, carbon may be present in lithium transition metal oxide particles and/or on surfaces thereof, whereby a secondary battery including the lithium composite transition metal oxide exhibits excellent rate characteristics and long lifespan. |
| US09601767B2 |
Alkaline collector anode
An alkaline battery includes a cathode, an alkaline electrolyte, and a copper-based anode which reduces hydrogen gassing without a protective coating or plating to less than 50% of the gas production observed using tin-plated 260 brass. An alloy for an anode which reduces hydrogen gassing without a protective coating or plating to less than 50% of the gas production observed using tin-plated 260 brass includes 0.01% to 9.0% tin, no more than 1% of phosphorus, no more than 1% of incidental elements and impurities, and the balance copper, in wt %. Another alloy for an anode which reduces hydrogen gassing without a protective coating or plating to less than 50% of the gas production observed using tin-plated 260 brass includes 1.0% to 40% zinc, about 0.01% to 5.0% tin, no more than 1% of phosphorus, no more than 1% of incidental elements and impurities, and the balance copper, in wt %. |
| US09601763B2 |
Process for mass-producing silicon nanowires and silicon nanowire-graphene hybrid particulates
Disclosed is a process for producing graphene-silicon nanowire hybrid material, comprising: (A) preparing a catalyst metal-coated mixture mass, which includes mixing graphene sheets with micron or sub-micron scaled silicon particles to form a mixture and depositing a nano-scaled catalytic metal onto surfaces of the graphene sheets and/or silicon particles; and (B) exposing the catalyst metal-coated mixture mass to a high temperature environment (preferably from 300° C. to 2,000° C., more preferably from 400° C. to 1,500° C., and most preferably from 500° C. to 1,200° C.) for a period of time sufficient to enable a catalytic metal-catalyzed growth of multiple silicon nanowires using the silicon particles as a feed material to form the graphene-silicon nanowire hybrid material composition. An optional etching or separating procedure may be conducted to remove catalytic metal or graphene from the Si nanowires. |
| US09601762B2 |
Phosphorous-coated lithium metal products, method for production and use thereof
A particulate lithium metal composite materials having a layer containing phosphorous and a method for producing said phosphorous-coated lithium metal products, characterized in that melted, droplet-shaped lithium metal is reacted in a hydrocarbon solvent with a phosphorous source that contains the phosphorous in the oxidation stage 3, and use thereof for the pre-lithiation of electrode materials and the production of battery anodes. |
| US09601758B2 |
Negative electrode material for a rechargeable battery, and method for producing it
The invention relates to a negative electrode powder for a lithium-ion rechargeable battery comprising a mixture comprising carbon and SiOx, with 0 |
| US09601757B2 |
Electrode active material, production method for said electrode active material, electrode and secondary battery
An electrode active material has, as a main component, a mixture of an organic compound containing a rubeanic acid and oxamide. The rubeanic acid is represented by the following general formula: In the formula, n indicates an integer between 1 and 20, and R1-R4 indicate hydrogen atoms, halogen atoms, or a prescribed substituent group such as a hydroxide group, a 1-3C alkyl group, an amino group, a phenyl group, a cyclohexyl group, or a sulfo group. |
| US09601747B2 |
Nanopatterned substrate serving as both a current collector and template for nanostructured electrode growth
A process of forming and the resulting nano-pitted metal substrate that serves both as patterns to grow nanostructured materials and as current collectors for the resulting nanostructured material is disclosed herein. The nano-pitted substrate can be fabricated from any suitable conductive material that allows nanostructured electrodes to be grown directly on the substrate. |
| US09601744B2 |
Secondary battery
A secondary battery includes: a case; an electrode assembly housed in the case and including a first electrode, a second electrode, and a separator between the first electrode and the second electrode, the first electrode having a coating portion coated with a first active material and a non-coating portion absent the first active material; and a collector plate including first and second collector plates enmeshed together with the non-coating portion therebetween. |
| US09601743B2 |
Electric wire routing structure for bus bar module
Provided are: a first-group accommodation part (21) and a second-group accommodation part (22) in each of which accommodation parts (2) each of which accommodates at least one of a bus bar (3), a terminal (4), and an electric wire (5) connected to the terminal (4) are arranged; a linkage part (8) linking the first-group accommodation part (21) and the second-group accommodation part (22) to each other; and an electric wire routing part (9) provided in the linkage part (8) and accommodating the electric wires (5). |
| US09601737B2 |
Lithium-ion secondary battery separator
A lithium-ion secondary battery separator resolves defects of a non-woven fabric separator which is not suitable for use in such a battery. The separator is thin and does not short-circuit and has excellent electrolyte retainability and rate characteristics. The separator includes a composite of a non-woven fabric having a basis weight of 2 to 20 g/m2 formed from fibers of a thermoplastic material having an average fiber diameter of 5 to 40 μm and ultra-microfibers having an average fiber diameter of 1 μm or less in an amount of ⅓ to 3 times the mass of the non-woven fabric. The composite has a thickness of 10 to 40 μm after heat-pressing treatment under conditions that the non-woven fabric has a glossiness (JIS Z 8741) measured at 60° in the range of 3 to 30 and a thickness of 10 to 40. |
| US09601732B2 |
Battery module for mitigating gas accumulation and methods thereof
A battery module is provided. The battery module includes a plurality of battery cell assemblies configured to electrically communicate with each other. Each battery cell assembly has an electrode stack enclosed by a case. The electrode stack is positioned in the case to form one or more peripheral spaces between the electrode stack and the case. Support members are positioned adjacent to each of the battery cell assemblies to contact a desired portion of the electrode stack. The support members are configured to focus a compressive force on a desired portion of the electrode stack. The compressive force urges gases formed during operation of the electrode stack into the peripheral spaces within the case. |
| US09601730B2 |
Secondary battery frame and battery pack including the same
Disclosed is a secondary battery frame with improved dimension management capability and a battery pack including the same.The secondary battery frame according to the present disclosure is used to package a pouch-type secondary battery, the secondary battery frame comprising a frame body comprising a top plate surrounding a circumferential area through which an electrode lead is exposed among a circumferential area of the pouch-type secondary battery, a left plate connected to a left edge of the top plate, a right plate connected to a right edge of the top plate, and a bottom plate connected to a bottom edge of the left plate and a bottom edge of the right plate; and a protrusion protrusively formed from at least one of the top plate, the bottom plate, the left plate, and the right plate in an outward direction of the frame body. |
| US09601726B2 |
Sealing material for secondary battery and sealing material composition for secondary battery
A sealing material for secondary battery contains a conjugated diene-based polymer and a cyclic olefin-based polymer. The weight ratio between the conjugated diene-based polymer and the cyclic olefin-based polymer, as expressed in (conjugated diene-based polymer/cyclic olefin-based polymer), ranges from 40/60 to 80/20, and the total amount of the diene-based polymer and the cyclic olefin-based polymer is 80 wt % or more of an entire amount. |
| US09601722B2 |
Method of manufacturing display device including a surface treatment operation to remove activated fluorine
A method of manufacturing a display device, the method including providing a first electrode on a base substrate; providing a fluorine-containing pixel defining layer on the base substrate and the first electrode such that the pixel defining layer exposes at least a portion of the first electrode; pretreating the first electrode; and providing an organic layer on the first electrode after pretreating the first electrode, wherein pretreating the first electrode includes performing a first treatment operation of treating an exposed surface of the first electrode using a first plasma gas; and performing a second treatment operation after performing the first treatment operation, the second treatment operation including treating the exposed surface of the first electrode using a second plasma gas, wherein the second plasma gas is different from the first plasma gas and includes hydrogen. |
| US09601715B2 |
Method of manufacturing display device, method of exposing terminal of display device and display device
A method of manufacturing a display device includes bonding together a first substrate and a second substrate sandwiching a first bonding material and a second bonding material, a substrate being formed by bonding the first and the second substrate and including a plurality of the display devices, the first bonding material being arranged in at least a display region, the second bonding material being a part of a terminal region and being arranged so as to cover the terminal, and the second bonding material having a stronger adhesion per unit area with respect to the second substrate than the first bonding material; cutting the second substrate at a cutting position between the terminal region and the display region for each of the display devices; removing the second substrate of the terminal region from the display device; and separating each of the display devices from the plurality of display devices. |
| US09601714B2 |
Display device
A display device is disclosed. In one aspect, the display device comprises a display panel, a window cover, at least one align key and a sealing portion. The display panel includes a substrate, a display unit formed over the substrate, and an encapsulation portion formed over the display unit. The window cover is formed over the display panel. The at least one align key is formed on the encapsulation portion and configured to align the display panel with the window cover. The sealing portion is formed between the substrate and the encapsulation portion, wherein the align key has at least one laser beam through portion passing through the encapsulation portion and is connected to the sealing portion. |
| US09601713B2 |
Electro-optic device, method of manufacturing electro-optic device, and electronic apparatus
An electro-optic device includes: a first substrate that includes a first surface; an optical element that is disposed in a first region on the first surface; a casing that is disposed to overlap with a part of the optical element along an outer periphery of the first region on the first surface and includes first and second end portions; a first resin layer that is disposed on an inside of the second end portion of the casing on the first surface and is installed to overlap with at least a part of the optical element; a second resin layer that is disposed on the first resin layer; and a second substrate that faces the first surface and is disposed on the second resin layer. |
| US09601707B2 |
Ambipolar vertical field effect transistor
Various examples are provided for ambipolar vertical field effect transistors (VFETs). In one example, among others, an ambipolar VFET includes a gate layer; a source layer that is electrically percolating and perforated; a dielectric layer; a drain layer; and a semiconducting channel layer. The semiconducting channel layer is in contact with at least a portion of the source layer and at least a portion of the dielectric layer and the source layer and the semiconducting channel layer form a gate voltage tunable charge injection barrier. Another example includes an ambipolar vertical field effect transistor including a dielectric surface treatment layer. The semiconducting channel layer is in contact with at least a portion of the source layer and at least a portion of the dielectric surface treatment layer and where the source layer and the semiconducting channel layer form a gate voltage tunable charge injection barrier. |
| US09601703B2 |
Organic light-emitting device
An organic light-emitting device (OLED) includes a first electrode; a second electrode facing the first electrode; an emission layer (EML) between the first electrode and the second electrode; a hole transport region between the first electrode and the EML; an electron transport region between the EML and the second electrode; and an interlayer between the EML and the hole transport region, wherein the interlayer includes an amine-based compound represented by Formula 1 or 2: where Ar1, Ar2, R1-R4, Z11-Z21, p, and q are as defined in the specification. |
| US09601701B2 |
Organic compound and organic light-emitting device
The present invention relates to a novel stable benzo[h]hexaphene compound and an organic light-emitting device including the compound. The present invention provides a benzo[h]hexaphene shown in claim 1. |
| US09601700B2 |
Condensed cyclic compound and organic light-emitting device including the same
A condensed cyclic compound and an organic light-emitting device including the same, the compound being represented by Formula 1, below: Ar1-(L11)b1-(L1)a1-(L12)b2-Ar2 |
| US09601699B2 |
Chrysene-based compound and organic light-emitting device including the same
A chrysene-based compound and an organic light-emitting device including the same, the chrysene-based compound being represented by Formula 1, below: |
| US09601695B2 |
Polymer compound
A photoelectric conversion device that contains a polymer compound having a structural unit represented by formula (1) having high photoelectric conversion efficiency: wherein, X1 and X2 are the same or different and represent a nitrogen atom or ═CH—; Y1 represents a sulfur atom, an oxygen atom, a selenium atom, —N(R1)— or —CR2═CR3—; R1, R2 and R3 are the same or different and represent a hydrogen atom or a substituent; W1 represents a cyano group, a monovalent organic group having a fluorine atom or a halogen atom; W2 represents a cyano group, a monovalent organic group having a fluorine atom, a halogen atom or a hydrogen atom. |
| US09601694B2 |
Donor substrate and method for manufacturing organic light emitting diode display
A donor substrate for a laser transfer includes a base layer, a primer layer disposed on the base layer, a light-to-heat conversion layer disposed on the primer layer, and an intermediate layer disposed on the light-to-heat conversion layer, where the light-to-heat conversion layer includes graphene. |
| US09601690B1 |
Sub-oxide interface layer for two-terminal memory
Provision of fabrication, construction, and/or assembly of a two-terminal memory device is described herein. The two-terminal memory device can include an active region with a silicon bearing layer, an interface layer, and an active metal layer. The interface layer can created comprising a non-stoichiometric sub-oxide that can be a combination of multiple silicon and/or silicon oxide layers with an aggregate chemical formula of SiOX, where X can be a non-integer greater than zero and less than 2. The sub-oxide can be created in a variety of ways, including various techniques related to growing the sub-oxide, depositing the sub-oxide, or transforming an extant film into the sub-oxide. |
| US09601685B1 |
Fabricating two-dimensional array of four-terminal thin film devices with surface-sensitive conductor layer
A technique relates to a semiconductor device. First metal contacts are formed on top of a substrate. The first metal contacts are arranged in a first direction, and the first metal contacts are arranged such that areas of the substrate remain exposed. Insulator pads are positioned at predefined locations on top of the first metal contacts, such that the insulator pads are spaced from one another. Second metal contacts are formed on top of the insulator pads, such that the second metal contacts are arranged in a second direction different from the first direction. The first and second metal contacts sandwich the insulator pads at the predefined locations. Surface-sensitive conductive channels are formed to contact the first metal contacts and the second metal contacts. Four-terminal devices are defined by the surface-sensitive conductive channels contacting a pair of the first metal contacts and contacting a pair of the metal contacts. |
| US09601683B2 |
Unit of piezoelectric element
In object to provide a unit of piezoelectric element having a preferable bending strength and preferably used as a part of a driving unit, a unit of piezoelectric element comprising: a multilayer piezoelectric element, having internal electrodes laminated having a piezoelectric body layer in-between and a pair of external electrodes formed on side surfaces extending along laminating direction and electrically connected to the internal electrodes, a wiring part connected to the external electrodes via a solder part, wherein a solder is solidified, a resin part, joining one end surface in the laminating direction of the multilayer piezoelectric element and a mounting surface of a connection member placed to face the one end surface, wherein the resin part is continuous from the one end surface and the mounting surface to the solder part; and the resin part covers the solder part, is provided. |
| US09601679B2 |
Thermoelectric module and method of manufacturing the same
In a configuration to join thermoelectric elements with an electrode in a thermoelectric module, reduction in junction reliability between the thermoelectric elements and the electrode is suppressed in a high-temperature environment and in an environment in which vibration and shock are imposed as load, to efficiently transmit the outer-circumferential temperature to the thermoelectric elements. In a thermoelectric module in which a plurality of p-type thermoelectric elements and a plurality of n-type thermoelectric element are alternately arranged by aligning the surfaces thereof on the high-temperature side and the surfaces thereof on the low-temperature side, to electrically connect the thermoelectric elements in series to each other; the p-type thermoelectric elements and the n-type thermoelectric element are joined via an intermediate layer with a deformable stress relaxation electrode, to thereby absorb stress taking place during the module assembling process and the module operation by the electrode. |
| US09601677B2 |
Thermoelectric (TE) devices/structures including thermoelectric elements with exposed major surfaces
A thermoelectric structure may include a thermally conductive substrate, and a plurality of thermoelectric elements arranged on a surface of the thermally conductive substrate. Moreover, each thermoelectric element may be non-parallel and non-orthogonal with respect to the surface of the thermally conductive substrate. For example, each of thermoelectric elements may be a planar thermoelectric element, and a plane of each of the thermoelectric elements may be oriented obliquely with respect to the surface of the thermally conductive substrate. |
| US09601676B2 |
LED support assembly and LED module
An LED support assembly and an LED module are provided. The LED support assembly includes: a metal heat sink, a first ceramic substrate and a second ceramic substrate, the metal heat sink defines an upper surface; the first ceramic substrate is adapted to support a LED chip and disposed on the upper surface of the metal heat sink; the second ceramic substrate is adapted to support electrodes of the LED chip and surrounds the first ceramic substrate. |
| US09601673B2 |
Light emitting diode (LED) components including LED dies that are directly attached to lead frames
A Light Emitting Diode (LED) component includes a lead frame and an LED that is electrically connected to the lead frame without wire bonds, using a solder layer. The lead frame includes a metal anode pad, a metal cathode pad and a plastic cup. The LED die includes LED die anode and cathode contacts with a solder layer on them. The metal anode pad, metal cathode pad, plastic cup and/or the solder layer are configured to facilitate the direct die attach of the LED die to the lead frame without wire bonds. Related fabrication methods are also described. |
| US09601669B2 |
Light-emitting apparatus, backlight unit, liquid crystal display apparatus, and illumination apparatus
A method of manufacturing a light-emitting apparatus includes arranging a plurality of semiconductor light-emitting elements in a straight line on a substrate and applying a sealing material, including an optical wavelength converter, in a straight line on the substrate to collectively seal the semiconductor light-emitting elements with the sealing material. The sealing material is applied so that a contour of a longitudinal end of the sealing material has a curvature, in a plan view of the substrate. |
| US09601668B2 |
Light emitting device
A light emitting device has a plurality of light emitting elements that are arranged with gaps between the devices on a mounting board in a first direction, a wavelength-conversion member that covers the plurality of light emitting elements, a light reflective resin. Each light emitting element has an n-type semiconductor layer, an active layer provided in a part of the n-type semiconductor layer, and a p-type semiconductor layer provided on the active layer. In a second direction which is perpendicular to the first direction, an n-side electrodes are provided at least in regions at both ends of the n-type semiconductor layer, and a p-side electrode is provided on the surface of the p-type semiconductor layer, and wherein in the second direction, the wavelength-conversion member is positioned to approximately align both sides with both active layer side faces, or to dispose its sides outward of the active layer side faces. |
| US09601666B2 |
Light emitting device
A light emitting device includes a substrate, a plurality of light emitting cells separated from each other and disposed on the substrate, and a plurality of conductive interconnection layers electrically connecting two neighboring light emitting cells. Each light emitting cell includes a light emitting structure including a first conductivity-type semiconductor layer, an active layer and a second conductivity-type semiconductor layer, a first electrode, a second electrode, and an etching area. The light emitting structure further includes a first side surface and a second side surface, and if a width between the first side surface and the second side surface is defined as W, the second electrode is disposed in an area between a position separated from the first side surface by 1 5 W and a position separated from the first side surface of the light emitting structure by 1 2 W . |
| US09601664B2 |
Semiconductor light-emitting element and method of manufacturing the same
A step of forming, on a surface of a semiconductor structure layer, easily-to-be-etched portions arranged on the basis of crystal directions on the surface of the semiconductor structure layer and a step of subjecting the surface of the semiconductor structure layer to wet etching to form an uneven structure surface including a plurality of protrusions derived from a crystal structure of the semiconductor structure layer on the surface of the semiconductor structure layer are included. |
| US09601663B2 |
Light-emitting diode chip
A light-emitting diode chip includes a semiconductor body including a radiation-generating active region, at least two contact locations electrically contacting the active region, a carrier and a connecting medium arranged between the carrier and the semiconductor body, wherein the semiconductor body includes roughening on outer surfaces facing the carrier, the semiconductor body mechanically connects to the carrier by the connecting medium, the connecting medium locally directly contacts the semiconductor body and the carrier, and the at least two contact locations are arranged on the upper side of the semiconductor body facing away from the carrier. |
| US09601659B2 |
LED structures for reduced non-radiative sidewall recombination
LED structures are disclosed to reduce non-radiative sidewall recombination along sidewalls of vertical LEDs including p-n diode sidewalls that span a top current spreading layer, bottom current spreading layer, and active layer between the top current spreading layer and bottom current spreading layer. |
| US09601652B2 |
Ohmic N-contact formed at low temperature in inverted metamorphic multijunction solar cells
A method of forming a multijunction solar cell including an upper subcell, a middle subcell, and a lower subcell by providing a substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on the substrate having a first band gap; forming a second solar subcell over the first solar subcell having a second band gap smaller than the first band gap; forming a graded interlayer over the second subcell, the graded interlayer having a third band gap greater than the second band gap; forming a third solar subcell over the graded interlayer having a fourth band gap smaller than the second band gap such that the third subcell is lattice mismatched with respect to the second subcell; and forming a contact composed of a sequence of layers over the first subcell at a temperature of 280° C. or less and having a contact resistance of less than 5×10−4 ohms-cm2. |
| US09601651B2 |
Method and apparatus for manufacturing a solar module strand and a solar module strand of flexible solar cells
A flexible solar module strand manufactured by a method including providing a first conveyor track for applying flexible solar cells; guiding the first conveyor track around two or more deflecting means; providing individual flexible solar cells; applying the individual solar cells to the first conveyor track; deflecting the first conveyor track by guiding the first conveyor track over a first one of the deflecting means; separating the first conveyor track from the at least one deflected solar cell strip in such a manner that the solar cells are released, with their respective first or second sides facing the first conveyor track, from the first conveyor track; and applying the at least one deflected solar cell strip to a first film web in such a manner that the solar cells are oriented, with their respective first or second sides separated from the first conveyor track, away from the first film web. |
| US09601650B1 |
Machine and process for continuous, sequential, deposition of semiconductor solar absorbers having variable semiconductor composition deposited in multiple sublayers
A method of manufacture of I-III-VI-absorber photovoltaic cells involves sequential deposition of films comprising one or more of silver and copper, with one or more of aluminum indium and gallium, and one or more of sulfur, selenium, and tellurium, as compounds in multiple thin sublayers to form a composite absorber layer. In an embodiment, the method is adapted to roll-to-roll processing of photovoltaic cells. In an embodiment, the method is adapted to preparation of a CIGS absorber layer having graded composition through the layer of substitutions such as tellurium near the base contact and silver near the heterojunction partner layer, or through gradations in indium and gallium content. In a particular embodiment, the graded composition is enriched in gallium at a base of the layer, and silver at the top of the layer. In an embodiment, each sublayer is deposited by co-evaporation of copper, indium, gallium, and selenium, which react in-situ to form CIGS. |
| US09601649B2 |
Method for producing a microsystem having a thin film made of lead zirconate titanate
A method for producing a micro system, said method comprising: providing a substrate (2) made of aluminum oxide; producing a thin film (6) on the substrate (2) by depositing lead zirconate titanate onto the substrate (2) with a thermal deposition method such that the lead zirconate titanate in the thin film (6) is self-polarized and is present predominantly in the rhombohedral phase; and cooling down the substrate (2) together with the thin film (6). |
| US09601646B2 |
Solar cell module
A solar cell module having high reliability by increasing heat release of a bypass diode is provided. A solar cell panel including a photoelectric conversion unit, a holding member disposed at a periphery of the solar cell panel to hold the solar cell panel, a heat release plate spaced from the solar cell panel and disposed on the holding member, and a bypass diode attached to the heat release plate so as to be spaced from the solar cell panel and electrically connected to the photoelectric conversion unit are included. An attachment surface of the bypass diode to the heat release plate is disposed to face the holding member. |
| US09601640B2 |
Electrical contacts to nanostructured areas
A process is provided for contacting a nanostructured surface. In that process, a substrate is provided having a nanostructured material on a surface, the substrate being conductive and the nanostructured material being coated with an insulating material. A portion of the nanostructured material is at least partially removed. A conductor is deposited on the substrate in such a way that it is in electrical contact with the substrate through the area where the nanostructured material has been at least partially removed. |
| US09601639B2 |
Semiconductor device
A p-type anode layer (2) is provided on an upper surface of an n-type drift layer (1). An n-type cathode layer (3) is provided on a lower surface of the n−-type drift layer (1). An n-type buffer layer (4) is provided between the n−-type drift layer (1) and the n-type cathode layer (3). A peak impurity concentration in the n-type buffer layer (4) is higher than that in the n−-type drift layer (1) and lower than that in the n-type cathode layer (3). A gradient of carrier concentration at a connection between the n−-type drift layer (1) and the n-type buffer layer (4) is 20 to 2000 cm−4. |
| US09601638B2 |
GaN-on-Si switch devices
A low leakage current switch device (110) is provided which includes a GaN-on-Si substrate (11, 13) with one or more device mesas (41) in which isolation regions (92, 93) are formed using an implant mask (81) to implant ions (91) into an upper portion of the mesa sidewalls and the peripheral region around each elevated surface of the mesa structures exposed by the implant mask, thereby preventing the subsequently formed gate electrode (111) from contacting the peripheral edge and sidewalls of the mesa structures. |
| US09601636B2 |
Semiconductor device and manufacturing method thereof
One object of the present invention is to provide a structure of a transistor including an oxide semiconductor in a channel formation region in which the threshold voltage of electric characteristics of the transistor can be positive, which is a so-called normally-off switching element, and a manufacturing method thereof. A second oxide semiconductor layer which has greater electron affinity and a smaller energy gap than a first oxide semiconductor layer is formed over the first oxide semiconductor layer. Further, a third oxide semiconductor layer is formed to cover side surfaces and a top surface of the second oxide semiconductor layer, that is, the third oxide semiconductor layer covers the second oxide semiconductor layer. |
| US09601635B2 |
Semiconductor device and method for manufacturing the same
By using a conductive layer including Cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased. |
| US09601631B2 |
Semiconductor device and method for manufacturing the same
A semiconductor device in which a shift of the threshold voltage of a transistor is suppressed is provided. A semiconductor device in which a decrease in the on-state current of a transistor is suppressed is provided. The semiconductor device is manufactured as follows: forming a gate electrode layer over a substrate; forming a gate insulating film over the gate electrode layer; forming an oxide semiconductor film over the gate insulating film; forming a metal oxide film having a higher reducing property than the oxide semiconductor film over the oxide semiconductor film; performing heat treatment while the metal oxide film and the oxide semiconductor film are in contact with each other, thereby the metal oxide film is reduced so that a metal film is formed; and processing the metal film to form a source electrode layer and a drain electrode layer. |
| US09601627B2 |
Diode structure compatible with FinFET process
An embodiment integrated circuit (e.g., diode) and method of making the same. The embodiment integrated circuit includes a well having a first doping type formed over a substrate having the first doping type, the well including a fin, a source formed over the well on a first side of the fin, the source having a second doping type, a drain formed over the well on a second side of the fin, the drain having the first doping type, and a gate oxide formed over the fin, the gate oxide laterally spaced apart from the source by a back off region of the fin. The integrated circuit is compatible with a FinFET fabrication process. |
| US09601623B2 |
Methods for forming semiconductor device structures
The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. |
| US09601620B2 |
Transistor and fabrication method thereof
A method for forming transistors includes providing a substrate having at least a dummy gate structure having at least dummy gate layer; forming a first dielectric layer on the substrate; thinning the first dielectric layer with a pre-determined depth to cause a top surface of the dielectric layer to be lower than a top surface of the dummy gate structure and expose top portions of side surfaces of the dummy gate structure; forming a stress layer on the exposed portions of the side surfaces of the dummy gate structure; forming a second dielectric layer on the thinned first dielectric layer; removing the dummy gate layer to form an opening with an enlarged top size caused by releasing stress in the stress layer previously formed on the exposed portions of the side surfaces of the dummy gate structure; and forming a gate electrode layer in the opening. |
| US09601619B2 |
MOS devices with non-uniform P-type impurity profile
An integrated circuit structure include a semiconductor substrate, a gate stack over the semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A silicon germanium region is disposed in the opening, wherein the silicon germanium region has a first p-type impurity concentration. A silicon cap substantially free from germanium is overlying the silicon germanium region. The silicon cap has a second p-type impurity concentration greater than the first p-type impurity concentration. |
| US09601616B2 |
Power MOSFETs and methods for forming the same
Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask. |
| US09601615B2 |
High voltage double-diffused MOS (DMOS) device and method of manufacture
A method of forming an integrated DMOS transistor/EEPROM cell includes forming a first mask over a substrate, forming a drift implant in the substrate using the first mask to align the drift implant, simultaneously forming a first floating gate over the drift implant, and a second floating gate spaced apart from the drift implant, forming a second mask covering the second floating gate and covering a portion of the first floating gate, forming a base implant in the substrate using an edge of the first floating gate to self-align the base implant region, and simultaneously forming a first control gate over the first floating gate and a second control gate over the second floating gate. The first floating gate, first control gate, drift implant, and base implant form components of the DMOS transistor, and the second floating gate and second control gate form components of the EEPROM cell. |
| US09601613B2 |
Gate pullback at ends of high-voltage vertical transistor structure
In one embodiment, a transistor includes a pillar of semiconductor material arranged in a racetrack-shaped layout having a substantially linear section that extends in a first lateral direction and rounded sections at each end of the substantially linear section. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. First and second gate members respectively disposed in the first and second dielectric regions are separated from the pillar by a gate oxide having a first thickness in the substantially linear section. The gate oxide being substantially thicker at the rounded sections. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. |
| US09601612B2 |
MOSFET having dual-gate cells with an integrated channel diode
A semiconductor device includes MOSFET cells having a drift region of a first conductivity type. A first and second active area trench are in the drift region. A split gate uses the active trenches as field plates or includes planar gates between the active trenches including a MOS gate electrode (MOS gate) and a diode gate electrode (diode gate). A body region of the second conductivity type in the drift region abutts the active trenches. A source of the first conductivity type in the body region includes a first source portion proximate to the MOS gate and a second source portion proximate to the diode gate. A vertical drift region uses the drift region below the body region to provide a drain. A connector shorts the diode gate to the second source portion to provide an integrated channel diode. The MOS gate is electrically isolated from the first source portion. |
| US09601611B2 |
Lateral/vertical semiconductor device with embedded isolator
A lateral/vertical device is provided. The device includes a device structure including a device channel having a lateral portion and a vertical portion. The lateral portion of the device channel can be located adjacent to a first surface of the device structure, and one or more contacts and/or a gate can be formed on the first surface. The device structure also includes a set of insulating layers located in the device structure between the lateral portion of the device channel and a second surface of the device structure opposite the first surface. An opening in the set of insulating layers defines a transition region between the lateral portion of the device channel and a vertical portion of the device channel. A contact to the vertical portion of the device channel can be located on the second surface. |
| US09601610B1 |
Vertical super junction III/nitride HEMT with vertically formed two dimensional electron gas
A HEMT device comprising a M-plane III-Nitride material substrate, a p-doped epitaxial layer of III-Nitride material grown on said substrate; a recess etched in said p-doped epitaxial layer, the recess having a plane wall parallel to a polar plane of the III-Nitride material; a carrier carrying layer formed on said plane wall of the recess; a carrier supply layer formed on said at least one carrier carrying layer, such that a 2DEG region is formed in the carrier carrying layer at the interface with the carrier supply layer along said plane wall of the recess; a doped source region formed at the surface of said p-doped epitaxial layer such that the doped source region is separated from said 2DEG region by a channel region; a gate insulating layer formed on the channel region; and a gate contact layer formed on the gate insulating layer. |
| US09601608B2 |
Structure for a gallium nitride (GaN) high electron mobility transistor
A high-electron mobility transistor (HEMT) device employing a gate protection layer is provided. A substrate has a channel layer arranged over the substrate and has a barrier layer arranged over the channel layer. The channel and barrier layers define a heterojunction, and a gate structure is arranged over a gate region of the barrier layer. The gate structure includes a gate arranged over a cap, where the cap is disposed on the barrier layer. The gate protection layer is arranged along sidewalls of the cap and arranged below the gate between opposing surfaces of the gate and the cap. Advantageously, the gate protection layer passivates the gate, reduces leakage current along sidewalls of the cap, and improves device reliability and threshold voltage uniformity. A method for manufacturing the HEMT device is also provided. |
| US09601606B2 |
Integrated circuit heat dissipation using nanostructures
An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer. |
| US09601602B2 |
Semiconductor device and manufacturing method thereof
Disclosed is a semiconductor device including an oxide semiconductor film. A first oxide semiconductor film with a thickness of greater than or equal to 2 nm and less than or equal to 15 nm is formed over a gate insulating layer. First heat treatment is performed so that crystal growth from a surface of the first oxide semiconductor film to the inside thereof is caused, whereby a first crystal layer is formed. A second oxide semiconductor film with a thickness greater than that of the first oxide semiconductor film is formed over the first crystal layer. Second heat treatment is performed so that crystal growth from the first crystal layer to a surface of the second oxide semiconductor film is caused, whereby a second crystal layer is formed. Further, oxygen doping treatment is performed on the second crystal layer. |
| US09601600B2 |
Processes for fabricating FinFET structures with semiconductor compound portions formed in cavities and extending over sidewall spacers
A process for fabricating a fin-type field effect transistor (FinFET) structure is described. A semiconductor substrate is patterned to form a fin. A spacer is formed on the sidewall of the fin. A portion of the fin is removed, such that the spacer and the surface of the remaining fin together define a cavity. A piece of a semiconductor compound is formed from the cavity, wherein the upper portion of the piece of the semiconductor compound laterally extends over the spacer. |
| US09601596B2 |
Electronic device and method of manufacturing semiconductor device
There is provided an electronic device including at least a first electrode, a second electrode disposed to be spaced apart from the first electrode, and an active layer disposed over the second electrode from above the first electrode and formed of an organic semiconductor material. A charge injection layer is formed between the first electrode and the active layer and between the second electrode and the active layer, and the charge injection layer is formed of an organic material having an increased electric conductivity when the charge injection layer is oxidized. |
| US09601595B2 |
High breakdown voltage LDMOS device
A multi-region (81, 83) lateral-diffused-metal-oxide-semiconductor (LDMOS) device (40) has a semiconductor-on-insulator (SOI) support structure (21) on or over which are formed a substantially symmetrical, laterally internal, first LDMOS region (81) and a substantially asymmetric, laterally edge-proximate, second LDMOS region (83). A deep trench isolation (DTI) wall (60) substantially laterally terminates the laterally edge-proximate second LDMOS region (83). Electric field enhancement and lower source-drain breakdown voltages (BVDSS) exhibited by the laterally edge-proximate second LDMOS region (83) associated with the DTI wall (60) are avoided by providing a doped SC buried layer region (86) in the SOI support structure (21) proximate the DTI wall (60), underlying a portion of the laterally edge-proximate second LDMOS region (83) and of opposite conductivity type than a drain region (31) of the laterally edge-proximate second LDMOS region (83). |
| US09601594B2 |
Semiconductor device with enhanced strain
The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate. The semiconductor device includes a gate that is disposed over the substrate. The substrate has a recess. The semiconductor device includes a trench liner that is coated along the recess. The trench liner contains a semiconductor crystal material. The trench liner directly abuts the source/drain stressor device. The semiconductor device also includes a dielectric trench component that is disposed on the trench liner and filling the recess. The semiconductor device includes a source/drain stressor device that is disposed in the substrate. The source/drain stressor device is disposed between the gate and the trench liner. |
| US09601592B2 |
IGBT and method of manufacturing the same
An IGBT has an emitter region, a top body region that is formed below the emitter region, a floating region that is formed below the top body region, a bottom body region that is formed below the floating region, a trench, a gate insulating film that covers an inner face of the trench, and a gate electrode that is arranged inside the trench. When a distribution of a concentration of p-type impurities in the top body region and the floating region, which are located below the emitter region, is viewed along a thickness direction of a semiconductor substrate, the concentration of the p-type impurities decreases as a downward distance increases from an upper end of the top body region that is located below the emitter region, and assumes a local minimum value at a predetermined depth in the floating region. |
| US09601589B2 |
Semiconductor device with surface insulating film
A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, and a surface insulating film disposed in a manner extending across the cell portion and the outer peripheral portion, and in the cell portion, formed to be thinner than a part in the outer peripheral portion. |
| US09601588B2 |
Method for fabricating semiconductor device
A method for fabricating a semiconductor device includes: forming isolation layers and active regions in a substrate, wherein each of the active regions is formed between the isolation layers; forming a silicide layer in each of the active regions; forming trenches and silicide layer patterns simultaneously by etching the silicide layer and each of the active regions, wherein each of the trenches is located between the silicide layer patterns; forming a buried gate in each of the trenches; forming an inter-layer dielectric layer that covers the buried gate and the silicide layer patterns; and forming a first opening that exposes one silicide layer pattern among the silicide layer patterns by selectively etching the inter-layer dielectric layer, wherein the silicide layer patterns are formed before the buried gate is formed. |
| US09601586B1 |
Methods of forming semiconductor devices, including forming a metal layer on source/drain regions
Methods of forming a semiconductor device are provided. A method of forming a semiconductor device includes forming a metal layer on source/drain regions of respective semiconductor structures, after replacing a dummy gate structure of the semiconductor device with a metal gate structure. The method includes forming a contact structure that overlaps the metal layer on one or more, but not all, of the semiconductor structures. Moreover, an insulating material is between the source/drain regions. |
| US09601584B2 |
Thin-film transistor substrate
An embodiment of the invention provides a thin-film transistor substrate, including: a substrate; a gate electrode disposed on the substrate; a gate insulating layer disposed on the substrate and covering the gate electrode; an active layer disposed on the gate insulating layer and above the gate electrode, wherein the active layer includes a metal oxide; a source electrode disposed on and electrically connecting to the active layer; a first insulating layer covering the source electrode; and a drain electrode disposed on and electrically connecting to the active layer, wherein the drain electrode includes a metal oxide layer. |
| US09601582B2 |
Semiconductor device
A semiconductor device includes a semiconductor region made of a material to which conductive impurities are added, an insulating film formed on a surface of the semiconductor region, and an electroconductive gate electrode formed on the insulating film. The gate electrode is made of a material whose Fermi level is closer to a Fermi level of the semiconductor region than a Fermi level of Si in at least a portion contiguous to the insulating film. |
| US09601579B2 |
Growth of semiconductors on hetero-substrates using graphene as an interfacial layer
Graphene is used as an interfacial layer to grow Si and other semiconductors or crystalline materials including two-dimensional Si and other structures on any foreign substrate that can withstand the growth temperature without the limitation matching condition typically required for epitaxial growth. |
| US09601574B2 |
V-shaped epitaxially formed semiconductor layer
The present disclosure provides a method in accordance with some embodiments. The method includes forming a recess in a source/drain region of a semiconductor substrate, wherein the semiconductor substrate is formed of a first semiconductor material. The method further includes epitaxially growing a second semiconductor material within the recess to form a S/D feature in the recess, and removing a portion of the S/D feature to form a v-shaped valley extending into the S/D feature. |
| US09601568B2 |
Semiconductor device including STI structure
Semiconductor devices including STI structures and their fabrication methods are provided. A mask layer is provided on a semiconductor substrate and patterned to form an opening in the mask layer to expose a surface portion of the semiconductor substrate. A trench is then formed in the semiconductor substrate by etching along the opening. A first dielectric layer is formed in the trench and has a top surface lower than a top surface of the semiconductor substrate to provide an uncovered sidewall surface of the trench in the semiconductor substrate. An epitaxial layer is formed on the uncovered sidewall surface of the trench in the semiconductor substrate. The epitaxial layer includes a spacing to expose a surface portion of the first dielectric layer. A second dielectric layer is formed on the exposed surface portion of the first dielectric layer to fill the spacing formed in the epitaxial layer. |
| US09601564B2 |
Deep trench isolation
An integrated semiconductor device includes a substrate of a first conductivity type, a buried layer located over the substrate, an isolated region located over a first portion of the buried layer, and an isolation trench located around the isolated region. A punch-through structure is located around at least a portion of the isolation trench. The punch-through structure includes a second portion of the buried layer, a first region located over the second portion of the buried layer, the first region having a second conductivity type, and a second region located over the first region, the second region having the first conductivity type. |
| US09601562B2 |
Oxide semiconductor film
A highly reliable semiconductor device including an oxide semiconductor is provided. Provided is a semiconductor device including an oxide semiconductor layer, an insulating layer in contact with the oxide semiconductor layer, a gate electrode layer overlapping with the oxide semiconductor layer, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer. The oxide semiconductor layer includes a first region having a crystal whose size is less than or equal to 10 nm and a second region which overlaps with the insulating layer with the first region provided therebetween and which includes a crystal part whose c-axis is aligned in a direction parallel to a normal vector of the surface of the oxide semiconductor layer. |
| US09601561B2 |
Organic light emitting diode display device
An organic light emitting diode display device includes a semiconductor on a substrate with a driving channel, an auxiliary storage electrode on the substrate with a storage electrode formed of a same material as the semiconductor and separated therefrom, a first insulating layer covering the semiconductor and the auxiliary storage electrode, a driving gate electrode overlapping the auxiliary storage electrode to define an auxiliary storage capacitor, a second insulating layer covering the driving gate electrode and the first insulating layer, a main storage electrode overlapping the driving gate electrode to define a main storage capacitor, a passivation layer covering the data wire and the second insulating layer, a pixel electrode on the passivation layer, an organic emission layer on the pixel electrode, and a common electrode on the organic emission layer. |
| US09601557B2 |
Flexible display
A flexible display having an array of pixels or sub-pixels is provided. The display includes a flexible substrate and an array of thin film transistors (TFTs) corresponding to the array of pixels or sub-pixels on the substrate. The display also includes a first plurality of metal lines coupled to gate electrodes of the TFTs and a second plurality of metal lines coupled to source electrodes and drain electrodes of the TFTs. At least one of the first plurality of metal lines and the second plurality of metal lines comprises a non-stretchable portion in the TFT areas and a stretchable portion outside the TFT areas. |
| US09601556B2 |
Organic light emitting display device and method of manufacturing the same
An organic light emitting display device includes a driving thin film transistor (TFT), the driving thin film TFT includes a lower gate, a source, and a drain on a substrate and on the same layer; a first gate insulating layer covering the lower gate, the source, and the drain; an active layer on the first gate insulating layer; a conductive line contacting the source and the drain; a second gate insulating layer on the active layer; and an upper gate on the second gate insulating layer, wherein the lower gate of the driving TFT is a light shield that blocks light from being irradiated onto the active layer, and the lower gate and the source include the same metal. |
| US09601554B2 |
Transparent display device and method of manufacturing the same
A transparent display device includes a first substrate including a pixel region and a light amount controlling region. An organic light emitting display is positioned in the pixel region and includes an anode electrode, a pixel defined layer, an organic light emitting layer positioned on the anode electrode and in an opening part of the pixel defined layer, and a cathode electrode positioned on the organic light emitting layer. A liquid crystal display is positioned in the light amount controlling region and includes a pixel electrode, a roof layer facing the pixel electrode, and a liquid crystal layer having a plurality of microcavities between the pixel electrode and the roof layer. The microcavities include liquid crystal molecules. A second substrate seals the organic light emitting display and the liquid crystal display. |
| US09601545B1 |
Series MIM structures compatible with RRAM process
The present disclosure relates to a method of forming an integrated circuit that prevents damage to MIM decoupling capacitors, and an associated structure. In some embodiments, the method comprises forming one or more lower metal interconnect structures within a lower ILD layer over a substrate. A plurality of MIM structures are formed over the lower metal interconnect structures, and one or more upper metal interconnect structures are formed within an upper ILD layer over the plurality of MIM structures. Together the lower and upper metal interconnect structures electrically couple the plurality of MIM structures in a series connection between a first voltage potential and a second voltage potential. By placing the MIM structures in a series connection, dissipation of the first voltage potential (e.g., a supply voltage) is spread out over the MIM structures, thereby reducing the voltage potential difference between electrodes of any one of the MIM structures. |
| US09601541B2 |
Method of manufacturing semiconductor device
An improvement is achieved in the performance of a semiconductor device. In a method of manufacturing the semiconductor device, in an n-type semiconductor substrate, a p-type well as a p-type semiconductor region forming a part of a photodiode is formed and a gate electrode of a transfer transistor is formed. Then, after an n-type well as an n-type semiconductor region forming the other part of the photodiode is formed, a microwave is applied to the semiconductor substrate to heat the semiconductor substrate. Thereafter, a drain region of the transfer transistor is formed. |
| US09601540B2 |
Method for producing semiconductor device
A method for producing a semiconductor device includes preparing a wafer having plural portions and having an insulator having plural openings thereon, forming an embedding member in each of the plural openings and on the insulator, removing at least a part of the embedding member, and planarizing the embedding member. The plural portions have a first portion and a second portion and each of the first portion and the second portion has a first region and a second region. The density of the openings in the first region is higher than that in the second region. The process of removing at least a part of the embedding member includes removing the embedding member positioned in the second region of the first portion, and removing the embedding member positioned in the second region of the second portion. A first removal amount and a second removal amount in the processes are different. |
| US09601537B2 |
Image pickup device that is provided with peripheral circuits to prevent chip area from being increased, and image pickup apparatus
An image pickup device which suppresses an increase in chip area of peripheral circuits without degrading the performance of a pixel section and makes it possible to prevent costs from being increased. The image pickup device includes a first semiconductor substrate and a second semiconductor substrate. A pixel section includes photo diodes each for generate electric charges by photoelectric conversion, floating diffusions each for temporarily storing the electric charges generated by the photo diode, and amplifiers each connected to the floating diffusion, for outputting a signal dependent on a potential of the associated floating diffusion. Column circuits are connected to vertical signal lines, respectively, for performing predetermined processing on signals output from the pixel section to vertical signal lines. |
| US09601531B2 |
Wafer-level packaging structure for image sensors with packaging cover dike structures corresponding to scribe line regions
A wafer level packaging structure for image sensors and a wafer level packaging method for image sensors are provided. The wafer level packaging structure includes: a wafer to be packaged including multiple chip regions and scribe line regions between the chip regions; pads and image sensing regions located on a first surface of the wafer and located in the chip regions; first dike structures covering surfaces of the pads and the scribe line regions; a packaging cover arranged facing the first surface of the wafer; and second dike structures located on a surface of the packaging cover. The second dike structures are arranged corresponding to the scribe line regions. The packaging cover and the wafer are jointed fixedly via the second dike structures and the first dike structures. |
| US09601529B2 |
Light absorption and filtering properties of vertically oriented semiconductor nano wires
A nanowire array is described herein. The nanowire array comprises a substrate and a plurality of nanowires extending essentially vertically from the substrate; wherein: each of the nanowires has uniform chemical along its entire length; a refractive index of the nanowires is at least two times of a refractive index of a cladding of the nanowires. This nanowire array is useful as a photodetector, a submicron color filter, a static color display or a dynamic color display. |
| US09601518B2 |
Thin film transistor display panel and method for manufacturing the same
A thin film transistor display panel including: a first insulating substrate; a first semiconductor disposed between the first insulating substrate and a first gate insulating layer; a gate electrode disposed on the first gate insulating layer, the gate electrode overlapping the first semiconductor; a second gate insulating layer disposed on the gate electrode; a second semiconductor disposed on the second gate insulating layer, the second semiconductor overlapping the gate electrode; an interlayer insulating layer disposed on the second semiconductor; and a source electrode and a drain electrode disposed on the interlayer insulating layer spaced apart from each other, the source electrode and the drain electrode connected to the first semiconductor and the second semiconductor. |
| US09601517B2 |
Hybrid pixel control circuits for light-emitting diode display
An electronic device may include a display. The display may be formed by an array of light-emitting diodes mounted to the surface of a substrate. The light-emitting diodes may be inorganic light-emitting diodes formed from separate crystalline semiconductor structures. An array of pixel control circuits may be used to control light emission from the light-emitting diodes. Each pixel control circuit may be used to supply drive signals to a respective set of the light-emitting diodes. The pixel control circuits may each have a silicon integrated circuit that includes transistors such as emission enable transistors and drive transistors for supplying the drive signals and may each have thin-film semiconducting oxide transistors that are coupled to the integrated circuit and that serve as switching transistors. |
| US09601516B2 |
Semiconductor device and manufacturing method thereof
The semiconductor device includes a driver circuit portion including a driver circuit and a pixel portion including a pixel. The pixel includes a gate electrode layer having a light-transmitting property, a gate insulating layer, a source electrode layer and a drain electrode layer each having a light-transmitting property provided over the gate insulating layer, an oxide semiconductor layer covering top surfaces and side surfaces of the source electrode layer and the drain electrode layer and provided over the gate electrode layer with the gate insulating layer therebetween, a conductive layer provided over part of the oxide semiconductor layer and having a lower resistance than the source electrode layer and the drain electrode layer, and an oxide insulating layer in contact with part of the oxide semiconductor layer. |
| US09601514B1 |
Method and structure for forming dielectric isolated FinFET with improved source/drain epitaxy
Described herein is a FinFET device in which epitaxial layers of semiconductor material are formed in the source/drain regions on dielectrically isolated fin portions. The fin portions are located within a dielectric layer that is deposited on a semiconductor substrate. Surfaces of the fin portions are oriented in the {100} lattice plane of the crystalline material of the fin portions, providing for good epitaxial growth. Further described are methods for forming the FinFET device. |
| US09601512B2 |
SOI-based semiconductor device with dynamic threshold voltage
A semiconductor device includes a semiconductor substrate, an insulating layer on a top surface of the substrate, and a first semiconductor transistor on the insulating layer, the transistor including an active region with a source region, a drain region, a channel region between the source and drain regions and a gate structure over the channel region, the gate structure extending beyond the transistor to an adjacent area. An outer well is included in the substrate, an inner well of an opposite type as the outer well situated within the outer well and under the active region and adjacent area, and a contact for the inner well in the adjacent area, the contact surrounding the gate structure. Operating the device includes applying a variable voltage at the contact for the inner well, a threshold voltage for the first transistor being altered by the variable voltage. The inner well and gate may be exposed and contacts created therefor together. |
| US09601510B2 |
Semiconductor device with six transistors forming a NAND circuit
A semiconductor device has a small area and constitutes a CMOS 3-input NAND circuit by using surrounding gate transistors (SGTs) that are vertical transistors. In a 3-input NAND circuit including six MOS transistors arranged in a line, the MOS transistors constituting the NAND circuit have the following configuration. Planar silicon layers are disposed on a substrate. The drain, gate, and source of the MOS transistors are arranged in a vertical direction, and the gate surrounds a silicon pillar. The planer silicon layers include a first active region having a first conductivity type and a second active region having a second conductivity type. The first and second active regions are connected to each other via a silicide layer disposed on surfaces of the planar silicon layers. In this way, a semiconductor device constituting a NAND circuit with a small area is provided. |
| US09601508B2 |
Blocking oxide in memory opening integration scheme for three-dimensional memory structure
An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. After formation of a memory opening, all surfaces of the memory opening are provided as silicon oxide surfaces by formation of at least one silicon oxide portion. A silicon nitride layer is formed in the memory opening. After formation of a memory stack structure, backside recesses can be formed employing the silicon oxide portions as an etch stop. The silicon oxide portions can be subsequently removed employing the silicon nitride layer as an etch stop. Physically exposed portions of the silicon nitride layer can be removed selective to the memory stack structure. Damage to the outer layer of the memory stack structure can be minimized or eliminated by successive use of etch stop structures. Electrically conductive layers can be subsequently formed in the backside recesses. |
| US09601501B2 |
Nonvolatile memory cell structure with assistant gate and memory array thereof
An NVM array includes a plurality of NVM cells, a plurality of word lines extending along a first direction, a plurality of bit lines extending along a second direction, and a plurality of source lines. Each of the NVM cells includes a PMOS select transistor and a PMOS floating gate transistor serially connected to the PMOS select transistor. Each word line is electrically connected to the select gate of the PMOS select transistor. Each bit line is electrically connected to a doping region of the PMOS floating gate transistor of each of the plurality of NVM cells. Each source line is electrically connected to a doping region of the PMOS select transistor. |
| US09601500B2 |
Array of non-volatile memory cells with ROM cells
A memory device that includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate with a channel region therebetween, a first gate disposed over and insulated from a first portion of the channel region, a second gate disposed over and insulated from a second portion of the channel region, and a conductive line extending over the plurality of ROM cells. The conductive line is electrically coupled to the drain regions of a first subgroup of the ROM cells, and is not electrically coupled to the drain regions of a second subgroup of the ROM cells. Alternately, a first subgroup of the ROM cells each includes a higher voltage threshold implant region in the channel region, whereas a second subgroup of the ROM cells each lack any higher voltage threshold implant region in the channel region. |
| US09601499B2 |
One-time programmable memory cell capable of reducing leakage current and preventing slow bit response, and method for programming a memory array comprising the same
A one time programmable (OTP) memory cell includes a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor has a first gate terminal, a first drain terminal and a first source terminal. The following gate transistor has a second gate terminal, a second drain terminal and a second source terminal coupled to the first drain terminal. The antifuse varactor has a third gate terminal, a third drain terminal, and a third source terminal coupled to the second drain terminal. The select gate transistor, the following gate transistor, and the antifuse varactor are formed on a substrate structure. |
| US09601498B2 |
Two-terminal nanotube devices and systems and methods of making same
A two terminal memory device includes first and second conductive terminals and a nanotube article. The article has at least one nanotube, and overlaps at least a portion of each of the first and second terminals. The device also includes stimulus circuitry in electrical communication with at least one of the first and second terminals. The circuit is capable of applying first and second electrical stimuli to at least one of the first and second terminal(s) to change the relative resistance of the device between the first and second terminals between a relatively high resistance and a relatively low resistance. The relatively high resistance between the first and second terminals corresponds to a first state of the device, and the relatively low resistance between the first and second terminals corresponds to a second state of the device. |
| US09601493B2 |
Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making
An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or siring includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link. |
| US09601491B1 |
Vertical field effect transistors having epitaxial fin channel with spacers below gate structure
A method of fabricating a vertical field effect transistor comprising that includes forming openings through a spacer material to provide fin structure openings to a first semiconductor material, and forming an inner spacer liner on sidewalls of the fin structure openings. A channel semiconductor material is epitaxially formed on a surface of the first semiconductor material filling at least a portion of the fin structure openings. The spacer material is recessed with an etch that is selective to the inner spacer liner to form a first spacer. The inner spacer liner is removed selectively to the channel semiconductor material. A gate structure on the channel semiconductor material, and a second semiconductor material is formed in contact with the channel semiconductor material. |
| US09601489B2 |
Dummy metal gate structures to reduce dishing during chemical-mechanical polishing
The described embodiments of mechanisms for placing dummy gate structures next to and/or near a number of wide gate structures reduce dishing effect for gate structures during chemical-mechanical polishing of gate layers. The arrangements of dummy gate structures and the ranges of metal pattern density have been described. Wide gate structures, such as analog devices, can greatly benefit from the reduction of dishing effect. |
| US09601487B2 |
Power transistor
A power transistor includes a number of transistor cells. Each transistor cell includes a source region, a drain region, a body region and a gate electrode. Each source region is arranged in a first semiconductor fin of a semiconductor body. Each drain region is at least partially arranged in a second semiconductor fin of the semiconductor body. The second semiconductor fin is spaced from the first semiconductor fin in a first horizontal direction of the semiconductor body. Each gate electrode is arranged in a trench adjacent the first semiconductor fin, is adjacent the body region, and is dielectrically insulated from the body region by a gate dielectric. Each of the first and second semiconductor fins has a width in the first horizontal direction and a length in a second horizontal direction, wherein the length is larger than the width. |
| US09601484B2 |
Magnetic multilayer structure
A mechanism is provided for an integrated laminated magnetic device. A substrate and a multilayer stack structure form the device. The multilayer stack structure includes alternating magnetic layers and diode structures formed on the substrate. Each magnetic layer in the multilayer stack structure is separated from another magnetic layer in the multilayer stack structure by a diode structure. |
| US09601482B1 |
Economical and environmentally friendly chemical mechanical polishing for III-V compound semiconductor device fabrication
Compound semiconductor devices and methods for fabricating compound semiconductor devices (e.g., III-V devices) based on aspect ratio trapping are provided in which economical and environmentally friendly chemical mechanical polishing techniques are implemented to minimize waste of, e.g., III-V precursor material, minimize production costs, and minimize environmental impact from toxic waste generated from chemical mechanical polishing of III-V films. |
| US09601481B2 |
Semiconductor device
A semiconductor device includes a first electrode, a first semiconductor layer of a first dopant type on the first electrode. A first region of the semiconductor device includes a second semiconductor layer of the second dopant type on the first semiconductor layer, a third semiconductor layer of the first dopant type on the second semiconductor layer, and a second electrode extending though the second and third semiconductor layers and inwardly of the first semiconductor layer. A second region of the semiconductor device includes an insulating layer over the first semiconductor layer, a fourth semiconductor layer of the first or second dopant type on the insulating layer, a fifth semiconductor layer of a different dopant type on the insulating layer and surrounding the fourth semiconductor layer, and a sixth semiconductor layer of the same dopant type on the insulation layer and surrounding the fifth semiconductor layer. |
| US09601480B2 |
Single junction bi-directional electrostatic discharge (ESD) protection circuit
In an embodiment, an ESD protection circuit may include a silicon-controlled rectifier (SCR) and a diode sharing a PN junction and forming a bi-directional ESD circuit. The single PN junction may reduce the capacitive load on the pin, which may allow the high speed circuit to meet its performance goals. In an embodiment, a floating P-well contact may be placed between two neighboring SCRs, to control triggering of the SCRs. |
| US09601475B2 |
Workpiece with semiconductor chips, semiconductor device and method for producing a workpiece with semiconductor chips
A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer. |
| US09601472B2 |
Package on package (POP) device comprising solder connections between integrated circuit device packages
Some features pertain to a package on package (PoP) device that includes a first package, a first solder interconnect coupled to the first integrated circuit package, and a second package coupled to the first package through the first solder interconnect. The second package includes a first die, a package interconnect comprising a first pad, where the first solder interconnect is coupled to the first pad of the package interconnect. The second package also includes a redistribution portion coupled to the first die and the package interconnect, an encapsulation layer at least partially encapsulating the first die and the package interconnect. The first pad may include a surface that has low roughness. The encapsulation layer may encapsulate the package interconnect such that the encapsulation layer encapsulates at least a portion of the first solder interconnect. |
| US09601471B2 |
Three layer stack structure
Vertically stacked system in package structures are described. In an embodiment, a package includes a first level molding and fan out structure, a third level molding and fan out structure, and a second level molding and fan out structure between the first and third levels. The second level molding and fan out structure includes back-to-back facing die, with a front surface of each die bonded to a redistribution layer. |
| US09601468B2 |
Magnetic contacts
Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed. |
| US09601467B1 |
Microelectronic package with horizontal and vertical interconnections
In a microelectronic package, a first wire bond wire is coupled to an upper surface of a substrate. A first bond mass is coupled to another end of the first wire bond wire. A second wire bond wire is coupled to the upper surface. A second bond mass is coupled to another end of the second wire bond wire. The first and second wire bond wires laterally jut out horizontally away from the upper surface of the substrate for at least a distance of approximately 2 to 3 times a diameter of both the first wire bond wire and the second wire bond wire. The first wire bond wire and the second wire bond wire are horizontal for the distance with respect to being co-planar with the upper surface within +/−10 degrees. |
| US09601465B2 |
Chip-stacked semiconductor package and method of manufacturing the same
A chip-stacked semiconductor package includes a first chip having a first front surface, a first back surface, and a first connection member on the first front surface, the first back surface being opposite to the first front surface; a second chip having a second front surface, a second back surface, a second connection member and a first through-silicon via (TSV) electrically connected to the second connection member, the second back surface opposite to the second front surface, and the second connection member on the second front face; and a first sealing member between the first front surface and the second front surface, the first sealing member filling a space between the first connection member and the second connection member, the first connection member of the first chip and the second connection member of the second chip being symmetric with respect to each other. |
| US09601463B2 |
Fan-out stacked system in package (SIP) and the methods of making the same
An embodiment package includes a first fan-out tier having a first device die, a molding compound extending along sidewalls of the first device die, and a through intervia (TIV) extending through the molding compound. One or more first fan-out redistribution layers (RDLs) are disposed over the first fan-out tier and bonded to the first device die. A second fan-out tier having a second device die is disposed over the one or more first fan-out RDLs. The one or more first fan-out RDLs electrically connects the first and second device dies. The TIV electrically connects the one or more first fan-out RDLs to one or more second fan-out RDLs. The package further includes a plurality of external connectors at least partially disposed in the one or more second fan-out RDLs. The plurality of external connectors are further disposed on conductive features in the one or more second fan-out RDLs. |
| US09601459B2 |
Method for aligning micro-electronic components
Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force. By applying appropriate charges on the conductor lines, electrostatic self-alignment is realized, which improves the alignment obtained through capillary force and maintains the alignment during evaporation of the liquid. |
| US09601457B2 |
Method for making an electrical connection in a blind via and electrical connection obtained
Method comprising steps as follows: a) depositing a meltable ball on a first conducting zone located in a blind hole formed on a first face of a first support, b) assembling the first support with a second support by transfer of the meltable ball on a second conducting zone, the transfer also being made by thermo-compression so as to compress the ball, the compressed ball being held at a distance from the side walls of the blind hole. |
| US09601454B2 |
Method of forming a component having wire bonds and a stiffening layer
Microelectronic components and methods forming such microelectronic components are disclosed herein. The microelectronic components may include a plurality of electrically conductive vias in the form of wire bonds extending from a bonding surface of a substrate, such as surfaces of electrically conductive elements at a surface of the substrate. |
| US09601453B2 |
Semiconductor package
Provided is a semiconductor package. The semiconductor package includes: a first die that is a monolithic type die, a driver circuit and a low-side output power device formed in the first die; a second die disposed above the first die, the second die comprising a high-side output power device; and a first connection unit disposed between the first die and the second die. |
| US09601451B2 |
Apparatus and methods for creating environmentally protective coating for integrated circuit assemblies
Example methods, apparatus, and products for creating an environmentally protective coating for integrated circuit assemblies are described herein. A preform plastic sheet is places over components of an integrated circuit such that during a reflow process, the preform plastic sheet melts to form a conformal coating over components of the integrated circuit assembly. |
| US09601450B2 |
Semiconductor package
A stacked semiconductor package in an embodiment includes a first semiconductor package including a first circuit board and a first semiconductor element mounted on the first circuit board; and a second semiconductor package including a second circuit board and a second semiconductor element mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package. The first semiconductor package further includes a sealing resin sealing the first semiconductor element; a conductive layer located in contact with the sealing resin; and a thermal via connected to the conductive layer and located on the first circuit board. |
| US09601445B2 |
Semiconductor packages
Semiconductor packages are provided. The semiconductor packages may include a base film having a top surface and a bottom surface, a circuit pattern disposed on the top surface of the base film and connected to a ground terminal, a via hole penetrating the base film, a lower shielding layer that is electrically connected to the circuit pattern and fills the whole region of the via hole and cover the bottom surface of the base. |
| US09601444B2 |
Cable mounted modularized signal conditioning apparatus system
A modularized signal conditioning apparatus system includes at least two slots formed in a coaxial cable. The slots are spaced apart so as to not reduce the measuring performance of the coaxial cable. Slots may be at least 40 mills from one another. In an ESD embodiment, within each slot is an ESD protection component, such as a pair of Shottky diodes coupled between the ground shell and the center conductor of the coaxial cable. Methods of producing modularized signal conditioning apparatus system are also described. |
| US09601440B2 |
Method for manufacturing semiconductor device and exposure mask used in the same method
A method for manufacturing a semiconductor device is disclosed in which the probability of occurrence of a crack is reduced and in which manufacturing cost is also reduced. An exposure mask used in the method is disclosed. Protrusion portions are formed in intersections of scribe lines in an outermost periphery of a scribe line pattern of a surface protection film of the exposure mask, to thereby stick out toward an outer circumference. In this manner, the probability of occurrence of a crack occurring in a device formation section can be reduced so that a reduction in the manufacturing cost can be achieved. |
| US09601436B2 |
Method for semiconductor wafer alignment
A semiconductor wafer is provided. The semiconductor wafer includes a base layer having an active region and an edge region. A number of semiconductor devices is formed on the active region. The semiconductor wafer also includes a wafer identification. The wafer identification is formed on the edge region and used for identifying the semiconductor wafer. The semiconductor wafer further includes an alignment mark. The alignment mark is formed on the edge region and is used for performing an alignment process of the semiconductor wafer. |
| US09601433B2 |
Semiconductor device and method of manufacturing the same
In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high voltage resistant MISFET. At this moment, when a distance from an interface between a semiconductor substrate and a gate insulation film to an upper portion of the gate electrode is defined as “a”, and a distance from the upper portion of the gate electrode to an upper portion of the interlayer insulation film on which the wires are formed is defined as “b”, a relation of a>b is established. In such a high voltage resistant MISFET structured in this manner, the wires are arranged so as not to be overlapped planarly with the gate electrode of the high voltage resistant MISFET. |
| US09601432B1 |
Advanced metallization for damage repair
An electrical contact structure for an integrated circuit device is described. A first patterned dielectric layer comprising at least one contact hole, the contact hole including a bottom surface, and sidewalls extending from the bottom surface to a top surface is provided. A tungsten via is disposed within the at least one contact hole, the tungsten via having a bottom surface in contact with a lower layer of the device and a top surface. A selectively deposited metal layer is disposed on the top surface of the tungsten via to repair etch damage. |
| US09601431B2 |
Dielectric/metal barrier integration to prevent copper diffusion
An interconnect structure for use in semiconductor devices and a method for fabricating the same is described. The method includes positioning a substrate in a vacuum processing chamber. The substrate has an exposed copper surface and an exposed low-k dielectric surface. A metal layer is formed over the copper surface but not over the low-k dielectric surface. A metal-based dielectric layer is formed over the metal layer and the low-k dielectric layer. |
| US09601428B2 |
Semiconductor fuses with nanowire fuse links and fabrication methods thereof
Semiconductor fuses with nanowire fuse links and fabrication methods thereof are presented. The methods include, for instance: fabricating a semiconductor fuse, the semiconductor fuse including at least one nanowire fuse link, and the fabricating including: forming at least one nanowire, the at least one nanowire including a semiconductor material; and reacting the at least one nanowire with a metal to form the at least one nanowire fuse link of the semiconductor fuse, the at least one nanowire fuse link including a semiconductor-metal alloy. In another aspect, a structure is presented. The structure includes: a semiconductor fuse, the semiconductor fuse including: at least one nanowire fuse link, the at least one nanowire fuse link including a semiconductor-metal alloy. |
| US09601426B1 |
Interconnect structure having subtractive etch feature and damascene feature
Methods of forming an interconnect structure include depositing a first conductive material on a substrate. Aspects include subtractively etching the conductive material to form a patterned first conductive layer, and depositing a dielectric layer on interconnect structure. Aspects also include depositing a second conductive material on the dielectric layer and removing the second conductive material through the top of the second metal liner. |
| US09601425B2 |
Circuit substrate and semiconductor package structure
The invention provides a circuit substrate and a semiconductor package structure. The circuit substrate includes a core substrate having a chip-side surface and a bump-side surface opposite to the chip-side surface. A first through via plug passes through the core substrate. A first conductive line pattern and a second conductive line pattern adjacent to the first conductive line are disposed on the chip-side surface. A pad is disposed on the bump-side surface. The first through via plug is in direct contact with and partially overlapping the first conductive line pattern and the pad. The first conductive line pattern, the second conductive line pattern and the first through via plug are configured to transmit voltage supplies of the same type. |
| US09601422B2 |
Printed wiring board, semiconductor package, and method for manufacturing printed wiring board
A printed wiring board includes a first interlayer, a first conductive layer on first-surface side of the first interlayer, a second conductive layer on second-surface side of the first interlayer, a first buildup layer including interlayers and conductive layers and formed on first surface of the first interlayer, and a second buildup layer including interlayers and conductive layers and formed on second surface of the first interlayer. The first conductive layer is formed such that the first conductive layer is embedded in the first interlayer and exposing surface on the first surface of the first interlayer, the second conductive layer is formed on the second surface of the first interlayer, and the interlayers in the first buildup layer include a second interlayer positioned adjacent to the first conductive layer and having the greatest thickness among the first interlayer and interlayers in the first and second buildup layers. |
| US09601421B2 |
BBUL material integration in-plane with embedded die for warpage control
An apparatus including a die including a first side and an opposite second side including a device side with contact points and lateral sidewalls defining a thickness of the die; a primary core adjacent at least a pair of the lateral sidewalls of the die; and a build-up carrier coupled to the second side of the die, the build-up carrier including a plurality of alternating layers of conductive material and insulating material, wherein at least one of the layers of conductive material is coupled to one of the contact points of the die. A method of forming a package and an apparatus including a computing device including a package are also disclosed. |
| US09601420B2 |
Semiconductor device and method of manufacturing the same
A semiconductor device includes a stack structure of a conductive line and an insulating capping line extending in a first direction on a substrate, a plurality of contact plugs arranged in a row along the first direction and having sidewall surfaces facing the conductive line with air spaces between the sidewall surfaces and the conductive line, and a support interposed between the insulating capping line and the contact plugs to limit the height of the air spaces. The width of the support varies or the support is present only intermittently in the first direction. In a method of manufacturing the semiconductor devices, a sacrificial spacer is formed on the side of the stack structure, the spacer is recessed, a support layer is formed in the recess, the support layer is etched to form the support, and then the remainder of the spacer is removed to provide the air spaces. |
| US09601419B1 |
Stacked leadframe packages
A multi-package unit having stacked packages is provided. A multi-package unit may include a first package and a second package mounted on the first package. The first package may be a leadframe package that includes metal leads extending beyond the perimeter of the first package. The first package may include a first integrated circuit die assembled within the first package using the wirebond configuration or the flip-chip configuration. The second package may be a leadframe package or a leadless package that includes a second integrated circuit die. The second package may be smaller than the first package. The first and second integrated circuit dies may be formed using different integrated circuit fabrication technologies. |
| US09601417B2 |
“L” shaped lead integrated circuit package
Various aspects provide for bending a bending a lead frame of a semiconductor device package into a shape of an “L” and mounting the package on a substrate. A horizontal portion of the bent lead-frame is about parallel with a surface of the package. A vertical portion of the bent lead frame is configured to extend the horizontal portion beyond the surface of the package. A device may be mounted between the substrate and the package. |
| US09601416B2 |
Lead frame, mold and method of manufacturing lead frame with mounted component
A lead frame includes one metal plate 10 having a terminal 15, and the other metal plate 50 joined to the one metal plate 10, on which a mounted component 91 is placed. The one metal plate 10 includes a first connection portion 11 connected to the terminal 15, a first extension portion 12 disposed on one end of the first connection portion 11, and a second extension portion 13 disposed on the other end of the first connection portion 11. The other metal plate 50 includes a pair of first clamping portions 62 configured to clamp the first extension portion 12, and a pair of second clamping portions 63 configured to clamp the second extension portion 13. |
| US09601414B2 |
Method for preventing die pad delamination
The invention is directed to a method for inhibiting or preventing delamination at the interface of the die attach/mold compound and the die pad of a semiconductor device and a semiconductor device formed by such method. The method includes providing a leadframe having a top surface; coating the top surface of the leadframe with first and second silane coating; heating the silane coatings to form a porous layer having a porosity of at least 10%; applying a die to the porous layer; securing the die to the porous layer by a die attaching compound; and after the curing of die attach material and wire bonding, a mold compound is applied through molding. |
| US09601409B2 |
Protruding contact for integrated chip
The present disclosure relates to a method of forming a back-end-of-the-line metal contact that eliminates RC opens caused by metal dishing during chemical mechanical polishing. The method is performed by depositing a sacrificial UV/thermal decomposition layer (UTDL) above an inter-level dielectric (ILD) layer. A metal contact is formed that extend through the ILD layer and the sacrificial UTDL. A chemical mechanical polishing (CMP) process is performed to generate a planar surface comprising the sacrificial UTDL. The sacrificial UTDL is then removed through an ultraviolet exposure or a thermal anneal, so that the metal contact protrudes from the ILD layer. |
| US09601407B2 |
System-in-package module and method for forming the same
A system-in-package (SiP) module is disclosed. The SiP module includes a substrate and a dam on the substrate. The dam defines a cavity. At least one chip is on the substrate inside the cavity. A printed circuit board (PCB) is bonded to the dam and covers the cavity. A thermal conductive sheet is in the cavity and is disposed between the chip and the PCB. The chip is in thermal contact with the PCB through the thermal conductive sheet. The disclosure also provides a method for manufacturing the SiP module. |
| US09601406B2 |
Copper nanorod-based thermal interface material (TIM)
A copper nanorod thermal interface material (TIM) is described. The copper nanorod TIM includes a plurality of copper nanorods having a first end thermally coupled with a first surface, and a second end extending toward a second surface. A plurality of copper nanorod branches are formed on the second end. The copper nanorod branches are metallurgically bonded to a second surface. The first surface may be the back side of a die. The second surface may be a heat spread or a second die. The TIM may include a matrix material surrounding the copper nanorods. In an embodiment, the copper nanorods are formed in clusters. |
| US09601404B2 |
Thermal resistance measuring method and thermal resistance measuring device
A temperature of a semiconductor element is measured based on a temperature coefficient of a voltage between the first electrode and the second electrode when no heat is generated when causing a constant current of an extent such that the semiconductor element does not generate heat to be input wherein current is caused to flow from a third electrode to a second electrode in accordance with voltage applied between a first electrode and the second electrode. Also, a constant current such that the semiconductor element generates heat is input into the third electrode, with voltage applied between the first electrode and second electrode of the semiconductor element kept constant, and power is measured based on the current such that the semiconductor element generates heat and on voltage when heat is generated between the third electrode and second electrode when the semiconductor element generates heat. |
| US09601399B2 |
Module arrangement for power semiconductor devices
A module arrangement for power semiconductor devices, including one or more power semiconductor modules, wherein the one or more power semiconductor modules include a substrate with a first surface and a second surface being arranged opposite to the first surface, wherein the substrate is at least partially electrically insulating, wherein a conductive structure is arranged at the first surface of the substrate, wherein at least one power semiconductor device is arranged on the conductive structure and electrically connected thereto, wherein the one or more modules includes an inner volume for receiving the at least one power semiconductor device which volume is hermetically sealed from its surrounding by a module enclosure, wherein the module arrangement includes an arrangement enclosure at least partly defining a volume for receiving the one or more modules, and wherein the arrangement enclosure seals covers the volume. |
| US09601398B2 |
Thin wafer handling and known good die test method
A method of attaching a microelectronic element to a substrate can include aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps each including a bond metal, and reflowing the bumps. The bumps can be exposed at a front surface of the microelectronic element. The substrate can have a plurality of spaced-apart recesses extending from a first surface thereof. The recesses can each have at least a portion of one or more inner surfaces that are non-wettable by the bond metal of which the bumps are formed. The reflowing of the bumps can be performed so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein such that the reflowed bond material in at least some of the recesses mechanically engages the substrate. |
| US09601394B2 |
Substrate processing apparatus, substrate processing method and memory medium
A substrate processing system includes a film-forming device to form photosensitive film on substrate, an exposure device to expose the film on the substrate, a relay device to transfer the substrate between the film-forming and exposure devices, a warping data acquisition device to acquire measured warping data of the substrate, a communication device to perform data communication with the exposure device, and a control device including film-forming, relay, measuring, and communication control sub-devices. The film-forming sub-device controls the film-forming device to form the film on the substrate, the relay sub-device controls the relay device to transfer the substrate to the exposure device, the measuring sub-device controls the warping data acquisition device to acquire the data after the controlling by the film-forming sub-device prior to the controlling by the relay sub-device, and the communication sub-device controls the communication device to transmit the data to the exposure device. |
| US09601389B1 |
Method for local thinning of top silicon layer of SOI wafer
A method for local thinning of a top silicon layer of a SOI wafer includes the consecutive steps of: providing a SOI wafer which successively includes a bottom silicon layer, a buried oxide layer and a top silicon layer; successively forming a silicon dioxide layer and a polysilicon layer over the top silicon layer; etching the silicon dioxide layer and the polysilicon layer until a top surface of the top silicon layer is exposed, such that a pattern is formed in the silicon dioxide layer and the polysilicon layer; oxidizing the silicon dioxide layer and the polysilicon layer and concurrently oxidizing the exposed portion of the top silicon layer until the polysilicon layer has been completely converted to an oxide, thereby forming a cap oxide layer; and removing the cap oxide layer, so that a locally thinned area is formed in the top surface of the top silicon layer. |
| US09601387B2 |
Method of making threshold voltage tuning using self-aligned contact cap
Methods of forming a PFET dielectric cap with varying concentrations of H2 reactive gas and the resulting devices are disclosed. Embodiments include forming p-type and n-type metal gate stacks, each surrounded by SiN spacers; forming an ILD surrounding the SiN spacers; planarizing the ILD, the metal gate stacks, and the SiN spacers; determining at least one desired threshold voltage for the p-type metal gate stack; forming a first cavity in the p-type metal gate stack for each desired threshold voltage and a second cavity in the n-type metal gate stack; selecting a first nitride layer for each first cavity, the first nitride layer for each cavity having a concentration of hydrogen reactive gas based on the desired threshold voltage associated with the cavity; forming the first nitride layers in the respective first cavities; and forming a second nitride layer, with a hydrogen rich reactive gas, in the second cavity. |
| US09601385B1 |
Method of making a dual strained channel semiconductor device
A method of forming a semiconductor device includes forming on a substrate mandrels made from a semiconductor material. A semiconductor material having a lattice constant that is different than the mandrel semiconductor material is deposited onto sidewalls of the mandrels to form strained semiconductor layers. The mandrels are at least partially removed to form free-standing or partially-supported fins that include the strained semiconductor layers. The strained semiconductor layers may include tensile silicon or compressive silicon germanium, which can be used to form a dual strained channel semiconductor device. |
| US09601383B1 |
FinFET fabrication by forming isolation trenches prior to fin formation
A semiconductor structure for a FinFET in fabrication is provided, the structure including a bulk semiconductor substrate initially with a hard mask over the substrate. Isolation trenches between regions of the structure where the fins will be are formed prior to the fins, and filled with selectively removable sacrificial isolation material. Remains of the hard mask are removed and another hard mask formed over the structure with filled isolation trenches. Fins are then formed throughout the structure, including the regions of sacrificial isolation material, which is thereafter selectively removed. |
| US09601379B1 |
Methods of forming metal source/drain contact structures for semiconductor devices with gate all around channel structures
In one example, the method disclosed herein includes, among other things, forming a sacrificial structure around a plurality of stacked substantially un-doped nanowires at a location that corresponds to the channel region of the device, performing a selective etching process through a cavity to remove a second plurality of nanowires from the channel region and the source/drain regions of the device while leaving a first plurality of nanowires in position, and forming a metal conductive source/drain contact structure in each of the source/drain regions, wherein each of the metal conductive source/drain contact structures is positioned all around the first plurality of nanowires positioned in the source/drain regions. |
| US09601375B2 |
UV-cure pre-treatment of carrier film for wafer dicing using hybrid laser scribing and plasma etch approach
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits on a front side of the semiconductor wafer includes adhering a back side the semiconductor wafer on the dicing tape of a substrate carrier. Subsequent to adhering the semiconductor wafer on a dicing tape, the dicing tape is treated with a UV-cure process. Subsequent to treating the dicing tape with the UV-cure process, a dicing mask is formed on the front side of the semiconductor wafer, the dicing mask covering and protecting the integrated circuits. The dicing mask is patterned with a laser scribing process to provide gaps in the dicing mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is plasma etched through the gaps in the dicing mask layer to singulate the integrated circuits. |
| US09601372B2 |
Method of forming metal pads with openings in integrated circuits including forming a polymer plug extending into a metal pad
A device includes a metal pad, and a passivation layer including portions overlapping edge portions of the metal pad. A Post-Passivation-Interconnect (PPI) includes a trace portion overlying the passivation layer, and a pad portion connected to the trace portion. A polymer layer includes an upper portion over the PPI, and a plug portion extending into, and encircled by, the pad portion of the PPI. |
| US09601367B2 |
Interconnect level structures for confining stitch-induced via structures
A design layout is provided such that an underlying conductive line structure underlies a stitch region in an overlying conductive line structure. A stitch-induced via structure can be formed between the underlying conductive line structure and the overlying conductive line structure when a stitch region in a hard mask layer is etched multiple times. At least one of the underlying conductive line structure and the overlying conductive line structure is electrically isolated from other conductive line structures in a same design level so as to avoid unintentional electrical shorts. |
| US09601365B2 |
Peeling device, peeling system, and peeling method
A peeling device separates a superposed substrate, in which a target substrate and a support substrate are joined to each other with an adhesive, into the target substrate and the support substrate. The peeling device includes a holding unit configured to hold the superposed substrate, and a plurality of position adjustment units movable forward and backward with respect to a side surface of the superposed substrate held in the holding unit, and the position adjustment unit configured to perform a position adjustment of the superposed substrate by contacting the side surface of the superposed substrate. |
| US09601361B2 |
Fixture for conveying a mask plate for the production of thin film transistor liquid crystal display
A fixture for conveying a mask plate comprising: a conveying bracket; and a fixation structure that is arranged on the conveying bracket and configured to fix the mask plate to be conveyed. The fixture has the following advantageous effects: it is able to prevent the hands from being in direct contact with the mask plate, thereby reducing the risk of conveyance damage of the mask plate which improves the operation efficiency. |
| US09601360B2 |
Wafer transport method
A wafer transport method is provided. The wafer transport method includes loading an initial carrier containing a first wafer and a second wafer on a first semiconductor apparatus, and processing the first wafer by the first semiconductor apparatus, and loading the first wafer into a first carrier disposed on the first semiconductor apparatus. The wafer transport method also includes processing the second wafer by the first semiconductor apparatus, and loading the second wafer into a second carrier disposed on the first semiconductor apparatus. The wafer transport method further includes processing the first wafer by a second semiconductor apparatus, and loading the first wafer into an integration carrier disposed on the second semiconductor apparatus. The wafer transport method further includes processing the second wafer by the second semiconductor apparatus, and loading the second wafer into the integration carrier disposed on the second semiconductor apparatus. |
| US09601359B2 |
Substrate holding device, semiconductor fabrication device, and substrate clamping ascertainment method
A substrate holding device is provided with an electrostatic chuck that has an electrode therein and is provided with a substrate holding surface, on one side of which a substrate is held; a displacement gauge that is disposed above or below the substrate holding surface; and a controller which, along with using the displacement gauge to measure a first distance to the substrate when a substrate is placed on the substrate holding surface, uses the displacement gauge to measure a second distance to the substrate after a predetermined voltage is applied to the electrode of the electrostatic chuck and, based on the difference between the measured distances, ascertains whether the clamping of the substrate to the electrostatic chuck has been performed in a normal manner. |
| US09601356B2 |
Systems and methods for controlling release of transferable semiconductor structures
The disclosed technology relates generally to methods and systems for controlling the release of micro devices. Prior to transferring micro devices to a destination substrate, a native substrate is formed with micro devices thereon. The micro devices can be distributed over the native substrate and spatially separated from each other by an anchor structure. The anchors are physically connected/secured to the native substrate. Tethers physically secure each micro device to one or more anchors, thereby suspending the micro device above the native substrate. In certain embodiments, single tether designs are used to control the relaxation of built-in stress in releasable structures on a substrate, such as Si (1 1 1). Single tether designs offer, among other things, the added benefit of easier break upon retrieval from native substrate in micro assembly processes. In certain embodiments, narrow tether designs are used to avoid pinning of the undercut etch front. |
| US09601355B2 |
Via structure for packaging and a method of forming
A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps. |
| US09601351B2 |
Method of manufacturing a semiconductor device
The generation of a variation in properties of vertical transistors is restrained. A vertical MOS transistor is formed in a semiconductor substrate. A first interlayer dielectric film and a first source wiring are formed over the front surface of the substrate. The first source wiring is formed over the first interlayer dielectric film, and is overlapped with the vertical MOS transistor as viewed in plan. Contacts are buried in the first interlayer dielectric film. Through the contacts, an n-type source layer of vertical MOS transistor is coupled with the first source wiring. Openings are made in the first source wiring. |
| US09601348B2 |
Interconnect structure and method of forming same
A method of forming a semiconductor device is provided. Metallic interconnects are formed in a dielectric layer of the semiconductor device. A hard mask is used to avoid usual problems faced by manufacturers, such as possibility of bridging different conductive elements and via patterning problems when there are overlays between vias and trenches. The hard mask is etched multiple times to extend via landing windows, while keeping distance between the conductive elements to avoid the bridging problem. |
| US09601347B1 |
Forming semiconductor fins with self-aligned patterning
A method for fabricating a semiconductor device comprises removing a portion of a substrate to form a first cavity in the substrate and depositing an insulator material in the first cavity. A sacrificial pattern is formed on a portion of the insulator material in the first cavity and the substrate. Exposed portions of the substrate are removed to form a fin in the substrate. A gate stack is formed over a portion of the fin. |
| US09601345B2 |
Fin trimming in a double sit process
A semiconductor structure and the method of forming that semiconductor structure. The method includes formation of a plurality of fins from a layer of semiconductor material. At least one fin of the plurality of fins is at least fifty percent wider than each of a group of fins included in the plurality of fins. The method also includes selectively removing the one fin such that only the group of fins remain. |
| US09601339B2 |
Methods for depositing fluorine/carbon-free conformal tungsten
Provided are atomic layer deposition methods to deposit a tungsten film or tungsten-containing film using a tungsten-containing reactive gas comprising one or more of tungsten pentachloride, a compound with the empirical formula WCl5 or WCl6. |
| US09601335B2 |
Trench formation for dielectric filled cut region
A method for forming a gate cut region includes forming a tapered profile gate line trench through a hard mask, a dummy layer and a dummy dielectric formed on a substrate, forming a dummy gate dielectric and a dummy gate conductor in the trench and planarizing a top surface to reach the hard mask. The dummy gate conductor is patterned to form a cut trench in a cut region. The dummy gate conductor is recessed, and the cut trench is filled with a first dielectric material. The dummy layer is removed and spacers are formed. A gate line is opened up and the dummy gate conductor is removed from the gate line trench. A gate dielectric and conductor are deposited, and a gate cap layer provides a second dielectric that is coupled to the first dielectric material in the cut trench to form a cut last structure. |
| US09601334B2 |
Semiconductor device and the method of manufacturing the same
A semiconductor device according to the invention includes p-type well region 3 and n+ source region 4, both formed selectively in the surface portion of n− drift region 2; trench 6 in contact with n+ source region 4 and extending through p-type well region 3 into n− drift region 2; field plate 8 formed in trench 6 with first insulator film 7 interposed between the trench 6 inner surface and field plate 8; gate electrode 10 formed in trench 6 with second insulator film 9 interposed between the trench 6 side wall and gate electrode 10, gate electrode 10 being formed above field plate 8; first insulator film 7 being thicker than second insulator film 9; and n− lightly doped region 21 in n− drift region 2, n− lightly doped region 21 crossing under the bottom surface of trench 6 from the corner portion thereof, n− lightly doped region 21 covering the bottom surface of trench 6. The semiconductor device according to the invention and the method of manufacturing the semiconductor device according to the invention facilitate lowering the ON-state voltage, preventing the breakdown voltage from lowering, lowering the gate capacitance, and reducing the manufacturing costs. |
| US09601332B2 |
Systems and method for ohmic contacts in silicon carbide devices
A silicon carbide device is presented that includes a gate electrode disposed over a portion of a silicon carbide substrate as well as a dielectric film disposed over the gate electrode. The device has a contact region disposed near the gate electrode and has a layer disposed over the dielectric film and over the contact region. The layer includes nickel in portions disposed over the dielectric film and includes nickel silicide in portions disposed over the contact region. The nickel silicide layer is configured to provide an ohmic contact to the contact region of the silicon carbide device. |
| US09601329B2 |
Method of fabricating crystalline island on substrate
Certain electronic applications, such as OLED display back panels, require small islands of high-quality semiconductor material distributed over a large area. This area can exceed the areas of crystalline semiconductor wafers that can be fabricated using the traditional boule-based techniques. This specification provides a method of fabricating a crystalline island of an island material, the method comprising depositing particles of the island material abutting a substrate, heating the substrate and the particles of the island material to melt and fuse the particles to form a molten globule, and cooling the substrate and the molten globule to crystallize the molten globule, thereby securing the crystalline island of the island material to the substrate. The method can also be used to fabricate arrays of crystalline islands, distributed over a large area, potentially exceeding the areas of crystalline semiconductor wafers that can be fabricated using boule-based techniques. |
| US09601328B2 |
Growing a III-V layer on silicon using aligned nano-scale patterns
A method of forming an integrated circuit structure includes providing a wafer having a silicon substrate; forming a plurality of shallow trench isolation (STI) regions in the silicon substrate; and forming recesses by removing top portions of the silicon substrate between opposite sidewalls of the plurality of STI regions. Substantially all long sides of all recesses in the silicon substrate extend in a same direction. A III-V compound semiconductor material is then epitaxially grown in the recesses. |
| US09601323B2 |
Ion transport apparatus and mass spectrometer using the same
Within an intermediate vacuum chamber next to an ionization chamber maintained at atmospheric pressure, an electrode group of a radio-frequency carpet composed of a plurality of concentrically arranged ring electrodes is placed before a skimmer, with its central axis coinciding with that of an ion-passing hole. Each ring electrode has a circular radial sectional shape. Radio-frequency voltages with mutually inverted phases are applied to the ring electrodes neighboring each other in the radial direction. Additionally, a different level of direct-current voltage is applied to each ring electrode to create a potential which is sloped downward from the outer ring electrode to the inner ring electrode. The circular cross section of the electrode produces a steep pseudo-potential near the electrode and thereby increases the repulsive force which acts on the ions to repel them from the electrode. |
| US09601316B2 |
Ignition apparatus for arc sources
The present invention relates to an ignition device for igniting a high-current discharge of an electrical arc evaporator in a vacuum coating system. Ignition is performed by means of mechanically closing and opening a contact between the cathode and the anode. Contact is established by means of an ignition finger that can move on a forced path. On account of the forced path, the ignition finger can be moved by means of a simple mechanical drive to a park position, which is protected against coating, and said ignition finger can also be used to ignite a second target. |
| US09601314B2 |
Ion implantation apparatus and ion implantation method
An ion implantation method in which an ion beam is scanned in a beam scanning direction and a wafer is mechanically scanned in a direction perpendicular to the beam scanning direction, includes setting a wafer rotation angle with respect to the ion beam so as to be varied, wherein a set angle of the wafer rotation angle is changed in a stepwise manner so as to implant ions into the wafer at each set angle, and wherein a wafer scanning region length is set to be varied, and, at the same time, a beam scanning speed of the ion beam is changed, in ion implantation at each set angle in a plurality of ion implantation operations during one rotation of the wafer, such that the ions are implanted into the wafer and dose amount non-uniformity in a wafer surface in other semiconductor manufacturing processes is corrected. |
| US09601311B2 |
Laser SDE effect compensation by adaptive tuning
Laser sub-divisional error (SDE) effect is compensated by using adaptive tuning. This compensated signal can be applied to position detection of stage in ebeam inspection tool, particularly for continuous moving stage. |
| US09601310B2 |
Charged particle microscope with barometric pressure correction
A method of mitigating the effects of environmental pressure variation while using a charged particle microscope is described. The charged particle microscope equipped with a barometric pressure sensor and an automatic controller configured to use the signal from the barometric sensor as an input to a control procedure to compensate for a relative positional error between the charged particle beam and the specimen holder. |
| US09601307B2 |
Charged particle radiation apparatus
The present invention provides a high-throughput scanning electron microscope in which a wafer (9) is held by an electrostatic chuck (10), an image is obtained using an electron beam, and the wafer surface is measured, wherein even in a case where the temperature of the wafer (9) is changed due to the environmental temperature the electron scanning microscope is capable of preventing any loss in resolution or the deterioration of the measurement reproducibility caused by thermal shrinkage accompanied by temperature change of the wafer (9). A drill hole is provided on the rear surface of the electrostatic chuck (10), and a thermometer (34) is secured in place so that the front end is brought into elastic contact with the bottom surface of the drill hole. The output of the thermometer (34) is sent to a computing unit, the computing unit computes a measurement limit time for beginning measurement, based on a predetermined algorithm, from an output value of the thermometer (34), and measuring begins at individual measurement sites after the measurement limit time has elapsed. |
| US09601303B2 |
Charged particle beam device and method for inspecting and/or imaging a sample
A charged particle beam device for imaging and/or inspecting a sample is described. The charged particle beam device includes a beam emitter for emitting a primary charged particle beam; and a retarding field device for retarding the primary beam before impinging on the sample, the retarding field device including a magnetic-electrostatic objective lens and a proxy electrode. The charged particle beam device is adapted for guiding the primary beam along an optical axis to the sample for generating secondary particles released from the sample and backscattered particles. The proxy electrode comprises a first opening allowing the passage of the primary beam and at least one second opening for allowing the passage of off-axial backscattered particles. Further, a proxy electrode and a method for imaging and/or inspecting a sample by a charged particle beam are described. |
| US09601300B2 |
Cathode element for a microfocus x-ray tube
A cathode element for a microfocus x-ray tube includes a heatable filament formed of a wire for thermionic emission of electrons for generating an electron beam. The filament, in a source area of the electron beam, has an elongate extension in two directions perpendicular to the electron beam. |
| US09601294B2 |
Fuse unit
In a fuse unit that includes a bus bar whose bend parts separated from each other are arranged in parallel, and one pair of divided bodies formed by being divided into one side and the other side of the bus bar with the bend parts exposed, and in which the one pair of divided bodies is arranged into an L-letter shape by being bent at the bend parts, a partition wall that is to be arranged between the bend parts in a state of leaving the bend parts bent is provided on one divided body. |
| US09601293B2 |
Temperature switch
A base member includes a terminal fixing part for blocking an entire surface of an opening part of a housing at a position further inner than an opening end part of the housing when the base member is inserted in the housing. A first electrode part formed by a tip part of two bent stages that are composed of a horizontal part, a vertical part, and a horizontal part and configured by bending a portion of a part of the fixed side fixed a conductive member, which is continuous with a first external connection terminal, in a direction perpendicular to a continuous direction. |
| US09601285B2 |
Method and apparatus pertaining to keycap light guides
An apparatus (such as a keyboard) has a plurality of keycaps and a corresponding light guide film disposed on the underside of those keycaps. The light guide film has a periphery, and at least portions of that periphery are thicker than in an interior portion of the light guide film. So configured, more light can be made available for backlighting purposes in the thicker portions than at the thinner portions. These teachings include determining the various (different) thicknesses to employ for the light guide film based upon desired backlighting of one or more of the plurality of keycaps. |
| US09601284B2 |
Hybrid relay
A relay (1) includes a motor (20) and a primary electrical switch assembly (132). Primary electrical switching attachment points (113) are switched by a moveable switching link (101) which is moved in and out of the switch on an switched off position axially by the motor (20) in response to electrical signals delivered to the coil (26) via the flexible leads (32, 33). The switching link (101) includes a mercury reservoir (119). A piezoelectric disk bender (105) displaces mercury to close the gaps between the attachment points (113). |
| US09601283B2 |
Efficient IGBT switching
Embodiments of the invention provide IGBT circuit modules with increased efficiencies. These efficiencies can be realized in a number of ways. In some embodiments, the gate resistance and/or voltage can be minimized. In some embodiments, the IGBT circuit module can be switched using an isolated receiver such as a fiber optic receiver. In some embodiments, a single driver can drive a single IGBT. And in some embodiments, a current bypass circuit can be included. Various other embodiments of the invention are disclosed. |
| US09601282B2 |
Power shut-off unit
The power shut-off unit is equipped with two relays (2) connected to an external circuit, and a tabular baseplate (6). Multiple auxiliary electronic components (7) are mounted on the baseplate (6). The relays (2) are held so as to float over a mounting surface (13) via a pair of retaining members (8). A distance (d) equal to or greater than the thickness of the baseplate (6) is maintained between the relays (2) and the mounting surface (13). The baseplate (6) is not directly fixed to the mounting surface (13) and is connected to the relays (2) via multiple latching members (9). Because no load is acted upon the baseplate (6) by the relays (2), the baseplate (6) can be made thin. |
| US09601281B2 |
Multiphase circuit breaker system having a short-circuit link
The circuit breaker system contains a plurality of phase conductors, a circuit breaker having a plurality of breaker poles, and a short-circuit link having a star point and a plurality of link conductors combined at the star point. Each of the phase conductors is electrically conductively connected to in each case one of the breaker poles and each link conductor is electrically conductively connected to in each case one of the phase conductors in each case one of several first disconnectors to which short-circuit current can be applied. In order to avoid expenditure on assembly and downtimes of the circuit breaker system when carrying out simulation experiments with the aid of the short-circuit link, the circuit breaker system contains a second disconnector which, when closed, electrically conductively connects the star point to ground and which is opened when a short-circuit current is applied to the short-circuit current link. |
| US09601279B2 |
Electrolyte solution and electrochemical device
The present invention aims to provide an electrolyte solution that is less likely to lead to an increase in resistance and realizes high capacity retention factor even after continuous application of a high voltage, and to provide an electrochemical device. The present invention provides an electrolyte solution including: a nitrile compound; and a quaternary ammonium salt, the electrolyte solution having a potassium ion content of less than 10 ppm, a moisture content of 20 ppm or less, a tertiary amine content of 30 ppm or less, a heterocyclic compound content of 30 ppm or less, and an ammonia content of 20 ppm or less. |
| US09601278B2 |
Super-capacitor with separator and method of producing the same
A method of producing a super-capacitor provides a first substrate having a first base, forms a first electrode on the first substrate, and forms a separator so that the electrode is between the first base and the first separator. The method also micromachines holes through the separator, forms a chamber, and adds electrolyte, having ions, to the chamber. The electrolyte is in contact with the first electrode within the chamber. In addition, the holes are sized to permit transmission of the ions of the electrolyte through the holes. |
| US09601277B2 |
Method for manufacturing capacitor element
The present invention provides an anode body for capacitors, which is formed of a sintered body that is obtained by sintering a powder mixture of a tungsten powder and a tungsten trioxide powder, and wherein the ratio of the tungsten trioxide powder to the total amount of the tungsten powder and the tungsten trioxide powder is 1 to 13 mass %. The present invention is able to reduce the number of semiconductor layer formation wherein polymerization of a semiconductor precursor is carried out a plurality of times on a dielectric layer. Consequently, a solid electrolytic capacitor element, in which a semiconductor layer that is composed of a conductive polymer is formed on a dielectric layer that is formed on the outer surface layer and the inner surface layer of the fine pores of a tungsten sintered body, can be produced efficiently. |
| US09601275B1 |
Dielectric ceramic composition and electronic device using the same
A dielectric ceramic composition includes a main component comprising (1-x)BaTiO3-x(Na1-yKy)NbO3, where 0.005≦x≦0.5 and 0.3≦y≦1.0; a first subcomponent comprising an element selected from the group consisting of Mn, V, Cr, Fe, Ni, Co, Cu and Zn; and a second subcomponent comprising SiO2. |
| US09601273B2 |
Winding device and winding method
According to one embodiment, a winding device includes a supporting part, a pressing part, a movement part configured to move a positional relationship between the supporting part and the pressing part, a control part, a target movement speed calculation part configured to detect a target relative movement speed of the pressing part with respect to the supporting part, a wire feed speed detection part configured to detect a feed speed of the wire, a deviation amount calculation part configured to calculate a difference between a detection result of the target movement speed calculation part and a detection result of the wire feed speed detection part, and a determination part configured to determine that the wire has deviated from the movement path. |
| US09601269B2 |
Resonant coil, wireless power transmitter using the same, wireless power receiver using the same
Disclosed is a coil for wirelessly transmitting or receiving power. The coil includes a coil unit formed by winding a plurality of wires insulated from each other; and a capacitor connected to the coil unit. The wires of the coil unit are shorted at a predetermined interval. |
| US09601266B2 |
Multiple connected resonators with a single electronic circuit
Described herein are systems, devices, and methods for a wireless energy transfer source that can support multiple wireless energy transfer techniques. A wireless energy source is configured to support wireless energy transfer techniques without requiring separate independent hardware for each technique. An amplifier is used to energize different energy transfer elements tuned for different frequencies. The impendence of each energy transfer element is configured such that only some of the energy transfer elements is active at a time. The different energy transfer elements and energy transfer techniques may be selectively activated using an amplifier without using active switches to select or activate different coils and/or resonators. |
| US09601264B2 |
Resonance terminal device for resonant wireless power reception system
A shunt capacitor is connected to a wireless charging resonator to prevent harmonics emitted from a power amplifier from radiating to the outside, and at least one circuit having a high impedance relative to a Near Field Wireless Communication (NFC) frequency band is formed at a front side or a rear side of the shunt capacitor for solving the problems of radiating noise components due to wireless charging and of lowering an NFC signal and a power transmission intensity due to a concurrent interference between a wireless charging resonator and an NFC antenna. |
| US09601259B2 |
Electronic component
An electronic component has a laminate including a plurality of laminated insulator layers, the laminate having a top surface and a mounting surface positioned in a first direction perpendicular to a direction of lamination. The direction of lamination is a direction in which the plurality of the insulator layers are laminated. First and second external electrodes are positioned on the mounting surface rather than on the top surface. The first and second external electrodes including first and second Ni-plating films and first and second Sn-plating films provided thereon, respectively. A first total thickness of the first Ni-plating film and the first Sn-plating film and/or a second total thickness of the second Ni-plating film and the second Sn-plating film are/is 11.6 μm or more, respectively. The first and/or second Ni-plating films are/is 1.37 times or more as thick as the first and/or second Sn-plating films, respectively. |
| US09601254B2 |
Apparatus and method for mitigating thermal excursions in air core reactors due to wind effects
An air core, dry type, power reactor (10) of the type having multiple concentrically positioned winding layers (12) extending along a central axis and above arms (24) of a first spider unit (16) when the reactor is horizontally positioned with respect to a horizontal ground plane, the winding layers (12) arranged in spaced-apart relation providing air gaps (20) between the winding layers allowing air to flow along the winding layers. A deflector (40) is positioned between the winding layers (12) and the ground plane to receive air from wind blowing toward the reactor (10) and guide the air in an upward direction from the deflector (40) and along the gaps (20). |
| US09601251B2 |
Correction of angle errors in permanent magnets
At least two partial magnets mechanically connected to each other. The length of each partial magnet runs in the main magnetisation direction of each partial magnet and/or in the main direction in which a partial magnet can be magnetised or in which its magnetisation is intended, and defines a first side and a second side as opposed regions at the ends of the partial magnet in respect of its length The at least two partial magnets are arranged in sequence in respect of their lengths and connected to each other. Deviations in the direction of the magnetisation and/or magnetisability of the first partial magnet deviating from the main magnetisation direction and/or main direction of magnetisability reduce and/or substantially compensate for the deviations in the direction of the magnetisation and/or magnetisability of the other or of the adjacent partial magnet deviating from the main magnetisation direction and/or main direction of magnetisability. |
| US09601244B2 |
Zinc oxide based varistor and fabrication method
A varistor may include a varistor ceramic that includes zinc oxide having a molar percent greater than 90 percent and a set of metal oxides, where the set of metal oxides includes Bi2O3 having a molar fraction between 0.2 and 2.5 percent; Co3O4 having a molar fraction between 0.2 and 1.2 percent; Mn3O4 having a molar fraction between 0.05 and 0.5 percent; Cr2O3 having a molar fraction between 0.05 and 0.5 percent; NiO having a molar fraction between 0.5 and 1.5 percent; Sb2O3 oxide having a molar fraction between 0.05 and 1.5 percent; B2O3 having a molar fraction between 0.001 to 0.03 percent; and aluminum in the form of an oxide having a molar fraction between 0.001 and 0.05 percent. |
| US09601242B2 |
Mold for impregnating a prefabricated condenser core of a high-voltage bushing and device for forming a condenser core of a high-voltage bushing
An exemplary mold is disclosed for impregnating a prefabricated condenser core (C) of a high voltage bushing with a liquid resin and includes two mold modules movable against each other and shaped to form an axially symmetric mold cavity. The mold forms a column of cylindrical design, in which the at least two mold modules are arranged on top of each other. A first of the two mold modules can be executed as a hollow cylinder. Two opposing front faces of the two mold modules and a circular O-ring arranged between the two opposing front faces form a first sealing interface of the metal mold. Such a mold can have a very efficient sealing system and allow high pressures to be applied to the liquid resin and a beneficial forming of the condenser core in a device in which the resin is cured according to a specified temperature profile. |
| US09601237B2 |
Transmission line for wired pipe, and method
A wired pipe transmission line for disposal in a wired pipe segment for use in subterranean drilling. The transmission line includes an assembly including an inner conductor and a dielectric layer including silicon dioxide (SiO2) insulating material surrounding the inner conductor and a protective layer that is formed of a rigid material and surrounding the dielectric layer. Also included is a method of forming a wired pipe transmission line. |
| US09601234B2 |
Three-dimensional (3D) porous device and method of making a 3D porous device
A method of making a three-dimensional porous device entails providing a substrate having a conductive pattern on a surface thereof, and depositing a colloidal solution comprising a plurality of microparticles onto the surface, where the microparticles assemble into a lattice structure. Interstices of the lattice structure are infiltrated with a conductive material, which propagates through the interstices in a direction away from the substrate to reach a predetermined thickness. The conductive material spans an area of the surface overlaid by the conductive pattern. The microparticles are removed to form voids in the conductive material, thereby forming a conductive porous structure having the predetermined thickness and a lateral size and shape defined by the conductive pattern. |
| US09601233B1 |
Plenum rated twisted pair communication cables
Plenum rated communication cables with reduced fluoropoloymer content may include a plurality of twisted pairs of individually insulated conductors, and each conductor may be insulated with a flame retardant polyolefin material. Additionally, each twisted pair may have a respective twist lay between approximately 0.30 inches and approximately 0.80 inches. The plurality of twisted pairs may be twisted together in a first direction and at least one of the plurality of twisted pairs may include conductors twisted together in a second direction opposite the first direction. A jacket may be formed around the plurality of twisted pairs. |
| US09601231B2 |
Hyperbranched olefin oil-based dielectric fluid
The present invention generally relates to a dielectric composition which is a poly-α-olefin or poly(co-ethylene-α-olefin) having a backbone weight average molecular weight less than 10,000 daltons. The dielectric composition uses a metal-ligand complex as a precatalyst and exhibits a hyperbranched structure that enables low viscosity, and therefore good flow characteristics, combined with high fire point due to ability to increase molecular weight via branching rather than backbone growth. Other desirable properties include lowered pour point due to crystallization disruption, and desirable thermal oxidative stability. |
| US09601227B2 |
Microbial nanowires and methods of making and using
Electrically conductive nanowires, and genetically or chemically modified production and use of such nanowires with altered conductive, adhesive, coupling or other properties are described. The disclosed nanowires are used as device or device components or may be adapted for soluble metal remediation. |
| US09601224B2 |
Electron beam irradiation apparatus
An electron beam irradiation apparatus that emits an electron beam into a container, the electron beam irradiation apparatus including: a vacuum housing constituting a vacuum chamber; an electron generator provided in the vacuum housing; a cylindrical nozzle member that is extended from the vacuum housing so as to be inserted into the container and has exit windows on the distal end of the nozzle member, the exit windows being provided for emission of an electron beam generated by the electron generator into the container; and a magnetic shield member for the vacuum chamber and a magnetic shield member for the nozzle member, the magnetic shield members being respectively provided for the vacuum housing and the nozzle member so as to block variable magnetism generated around an electron beam trajectory extended from the electron generator to the exit windows. |
| US09601219B2 |
Method, memory controller, and memory system for reading data stored in flash memory
An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination. |
| US09601218B2 |
Memory device and computing system including the same
A memory system includes a read-only memory (ROM), a main memory and a processor. The ROM stores a basic input/output system (BIOS). The main memory includes a fail address table which stores at least one fail address designating a memory cell row having at least one defective cell. The processor receives fail information of the at least one fail address from the main memory and loads data associated with a booting operation of the memory system in a safe area of the main memory by avoiding a fail area corresponding to the at least one fail address during power-on operation while a power is applied to the memory system. The data associated with the booting operation is stored in a storage device. |
| US09601217B1 |
Methods and circuitry for identifying logic regions affected by soft errors
Integrated circuits with single event upset (SEU) detection circuitry are provided. The SEU detection circuitry may include an error detection block for detecting soft errors and a sensitivity processor that determines whether or not to correct the detected soft errors. The sensitivity processor may be used to access a sensitivity map header (SMH) file that is stored on external memory. The sensitivity map header file contains information that can help identify which logic region on the integrated circuit the soft error affects and whether or not that soft error can critically cause functional failure for the integrated circuit. Depending on the criticality of the soft error, different corrective actions may be taken. |
| US09601215B2 |
Holding circuit, driving method of the holding circuit, and semiconductor device including the holding circuit
A holding circuit includes first to third input terminals, an output terminal, first to third switches, a capacitor, and a node. The first to third switches control conduction between the node and the first input terminal, conduction between the node and the output terminal, and conduction between the second input terminal and the output terminal, respectively. First and second terminals of the capacitor are electrically connected to the node and the third input terminal, respectively. The first to third switches are each a transistor comprising an oxide semiconductor layer comprising a semiconductor region. Owing to the structure, a potential change of the node in an electrically floating state can be suppressed; thus, the holding circuit can retain its state for a long time. The holding circuit can be used as a memory circuit for backup of a sequential circuit, for example. |
| US09601214B2 |
Method and system for improving the radiation tolerance of floating gate memories
A method of improving radiation tolerance of floating gate memories is provided herein. Floating gate memories can include a floating gate transistor or a block of floating gate transistors. A floating gate transistor can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitride-oxide region, and a control gate region. A floating gate transistor or block of floating gate transistors can be written to multiple times in order to accumulate charge on one or more floating gate regions in accordance with an embodiment of the invention. When exposed to radiation, a floating gate region can retain its charge above a certain voltage threshold. A block of floating gate transistors can communicate with an external device where the external device can read a state of the block of floating gate transistors in accordance with an embodiment of the invention. |
| US09601210B2 |
Semiconductor memory device and memory system
A semiconductor memory device includes a first stack of memory cells above a substrate, the first stack including a first memory cell and a second memory cell above the first memory cell, a second stack of memory cells above the substrate, the second stack including a third memory cell, a word line connected to the first, second, and third memory cells, and a controller configured to output data stored in the first memory cell and data stored in the third memory cell during a first cycle, and output data stored in the second memory cell during a second cycle that is different from the first cycle. |
| US09601206B2 |
Semiconductor memory system including a plurality of semiconductor memory devices
A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current. |
| US09601205B2 |
Storage device and method of writing and reading the same
A write method of a storage device including at least one nonvolatile memory device and a memory controller controlling the nonvolatile memory device includes dividing write data into a plurality of page data groups, each page data group including multiple bits of data; encoding the divided page data groups using different binary codes, respectively; mapping the encoded page data groups; programming, in first memory cells connected to one word line, programming states to which binary values of each of the mapped encoded page data groups are mapped, such that, the plurality of page data groups correspond respectively to a plurality of read voltage levels, and for each of the plurality of page data groups, the page data group can be read by performing a single read operation on the first memory cells using the read voltage level corresponding to the page data group. |
| US09601204B2 |
Three-dimensional semiconductor devices and fabricating methods thereof
A three-dimensional (3D) semiconductor memory device includes a CMOS circuit structure including a plurality of column blocks each comprising a plurality of page buffer circuits, and a lower wiring structure and a memory structure sequentially stacked over the CMOS circuit structure. The memory structure overlaps a first circuit region of the CMOS circuit structure and does not overlap a second circuit region of the CMOS circuit structure, and the plurality of column blocks are contained within the first circuit region of the CMOS circuit structure. |
| US09601203B2 |
Floating gate non-volatile memory bit cell
A solid-state non-volatile memory (NVM) device includes a memory bit cell. The memory bit cell includes a field effect transistor (FET) fabricated on a substrate and having a floating gate. The floating gate includes a thick oxide layer. The FET includes drain and source, each fabricated within the substrate and coupled to the floating gate and a channel region with native doping. The drain is fabricated to have a halo region. A method for fabricating a solid-state NVM device includes fabricating solid state device including NVM bit cell which provides multiple storage and includes an FET on substrate. The method also includes fabricating floating gate of the FET including thick gate oxide layer, and fabricating drain and source of FET within the substrate, drain and source coupled to the floating gate and channel region with native doping. Further, the method includes fabricating halo region within the substrate at the drain. |
| US09601198B2 |
Memory circuit provided with bistable circuit and non-volatile element
A memory circuit includes: a bistable circuit (30) that stores data; nonvolatile elements (MTJ1, MTJ2) that store data written in the bistable circuit in a nonvolatile manner, and restore data stored in a nonvolatile manner into the bistable circuit; and a control unit that stores data written in the bistable circuit in a nonvolatile manner and cuts off a power supply to the bistable circuit when the period not to read data from or write data into the bistable circuit is longer than a predetermined time period, and does not store data written in the bistable circuit in a nonvolatile manner and makes the supply voltage for the bistable circuit lower than a voltage during the period to read data from or write data into the bistable circuit when the period not to read or write data is shorter than the predetermined time period. |
| US09601194B2 |
NAND array comprising parallel transistor and two-terminal switching device
Providing for a high performance and efficiency NAND architecture is described herein. By way of example, a NAND array is disclosed comprising memory cells having a 1 transistor-1 two-terminal memory device (IT-1D) arrangement. Memory cells of the NAND array can be arranged electrically in serial with respect to each other, from source to drain. Moreover, respective memory cells comprise a transistor component connected in parallel to a two-terminal memory device. In some embodiments, a resistance of the activated transistor component is selected to be substantially less than that of the two-terminal memory device, and the resistance of the deactivated transistor component is selected to be substantially higher than the two-terminal memory device. Accordingly, by activating or deactivating the transistor component, a signal applied to the memory cell can be shorted past the two-terminal memory device, or directed through the two-terminal memory device, respectively. |
| US09601190B2 |
Semiconductor integrated circuit
A semiconductor integrated circuit according to an embodiment includes: N (≧1) input wiring lines; M (≧1) output wiring lines; N first wiring lines corresponding to the N input wiring lines; K (>M) second wiring lines crossing the N first wiring lines; a plurality of first resistive change elements disposed at intersections of the first wiring lines and the second wiring lines, each of the first resistive change elements including a first electrode connecting to a corresponding one of the first wiring lines, a second electrode connecting to a corresponding one of the second wiring lines, and a first resistive change layer disposed between the first electrode and the second electrode; a first controller controlling a voltage applied to the first wiring lines; a second controller controlling a voltage applied to the second wiring lines; and a selection circuit selecting M second wiring lines from the K second wiring lines. |
| US09601189B2 |
Representing data using a group of multilevel memory cells
A memory device includes a group or block of k-level memory cells, where k>2, and where each of the k-level memory cells has k programmable states represented by respective resistance levels. |
| US09601183B1 |
Apparatuses and methods for controlling wordlines and sense amplifiers
Apparatuses and methods for controlling word lines and sense amplifiers in a semiconductor device are described. An example apparatus includes: a sub word line selection signal decoder which activates at least one of a plurality of sub word selection signals responsive to row address signals; a column segment selection signal decoder which activates at least one of a plurality of column segment signals responsive to a portion of column address signals and a portion of the row address signals; a column segment selection circuit which activates at least one of a plurality of column-subword selection signals responsive to the activated column segment signal and the activated sub word selection signal; and a sub word line driver which activates at least one of a plurality of sub word lines responsive to an activated main word line and the activated sub word selection signal. |
| US09601182B2 |
Frequency synthesis for memory input-output operations
A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal. |
| US09601180B2 |
Automatic partial array self-refresh
Methods of configuring dynamic memory associated with a processing system, are described. The dynamic memory is configured in a plurality of blocks, the method comprises: a) receiving information relating to a utilization status of the memory; b) processing the received information to determine at least one first block of the memory that is currently not in use for information storage; and c) configuring the at least one first block to be excluded from an information refresh process. |
| US09601171B2 |
Storage device including nonvolatile memory and memory controller and operating method of retiming circuit interfacing communication between nonvolatile memory and memory controller
A storage device includes a nonvolatile memory, and a memory controller adapted to control the nonvolatile memory and to transmit a first timing signal to the nonvolatile memory at a read operation. The nonvolatile memory includes a nonvolatile memory device adapted to output read data and a second timing signal in response to the first timing signal, and a retiming circuit adapted to detect a locking delay according to the first timing signal, to produce a third timing signal from the second timing signal using the detected locking delay, to retime the read data by latching the read data in synchronization with the third timing signal and to output the third timing signal and the retimed read data to the memory controller. |
| US09601169B2 |
Semiconductor memory device, memory system including the same and operating method thereof
A semiconductor memory device includes a program and read unit suitable for programming program data in a memory cell array and for reading read data stored in the memory cell array, and a control unit suitable for generating a control signal for controlling the program and read unit in response to a command input from the outside of the semiconductor memory device, in which the control unit controls the program and read unit to read the read data in a state of storing a first bit data of the program data when a read command is input while programming the program data. |
| US09601168B2 |
Memory bank signal coupling buffer and method
A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments within the array. Respective bidirectional buffers couple read data from one of the segments to another in a first direction, and to couple write data from one of the segments to another in a second direction that is opposite the first direction. The data lines may be local data read/write lines that couple different banks of memory cells to each other and to respective data terminals, digit lines that couple memory cells in a respective column to respective sense amplifiers, word lines that activate memory cells in a respective row, or some other signal line within the array. The memory array also includes precharge circuits for precharging the segments of respective data lines to a precharge voltage. |
| US09601162B1 |
Memory devices with strap cells
A device includes a memory array, a first data line, and a second data line. The memory array includes a first strap cell, a first sub-bank, and a second sub-bank, in which the first strap cell is disposed between the first sub-bank and the second sub-bank. The first data line has a first portion and a second portion, in which the first portion of the first data line is disconnected from the second portion of the first data line, and the second portion of the first data line is configured to couple the first sub-bank to a first input/output (I/O) circuit. The second data line and the first portion of the first data line are configured to couple the second sub-bank to the first I/O circuit. |
| US09601158B2 |
Moving image selection apparatus for selecting moving image to be combined, moving image selection method, and storage medium
An image capture apparatus includes a combination candidate selection processing unit. When one moving image is generated by combining a plurality of moving images, the combination candidate selection processing unit judges a possibility of combination between a moving image which is a basis for combination chosen and another moving image based on a predetermined condition. Furthermore, the combination candidate selection processing unit selects, as a candidate of a moving image for a combination target, a moving image that can be combined with the moving image which is a basis for combination, from among other moving images based on a judgment result. |
| US09601154B2 |
Prioritized random access for magnetic recording
A storage device includes a controller that directs incoming data to a storage location based on a capacity of a region or surface of a magnetic disc. According to one implementation, the storage device controller writes new data to data tracks in a first series of data tracks on the magnetic disc until a capacity condition is satisfied. Once the capacity condition is satisfied, the storage device controller writes new data to a second series of data tracks on the storage medium that are interlaced with data tracks of the first series. |
| US09601147B2 |
Optical information recording and reproducing apparatus and optical information recording and reproducing method
To provide an optical information recording and reproducing apparatus capable of correct positioning, in an optical information recording and reproducing apparatus which branches a light beam into reference light and signal light to cause interference and records an obtained interference fringe as a hologram on an optical information recording medium and reproduces the hologram recorded by applying the reference light onto the optical information recording medium, the apparatus has an image pickup element which detects reproduction light passing through an aperture 101 in reproduction light obtained by applying the reference light onto the optical information recording medium and generates a reproduction signal, photo detectors 104a, 104b, 104c, and 104d that are different from the image pickup element and detect reproduction light applied on a location on the periphery of the aperture 101, and a computing unit which computes a position error signal based on outputs from the photo detectors. |
| US09601145B1 |
Heat-assisted magnetic recording (HAMR) disk with multiple continuous magnetic recording layers
A heat-assisted magnetic recording (HAMR) disk has multiple independent data layers, each data layer being a continuous non-patterned layer of magnetizable material. Each data layer can store data independent and not related to the data stored in the other data layers. The data layers are separated by a nonmagnetic spacer layer (SL) and each data layer is formed of high-anisotropy (Ku) material so that the coercivities of lower and upper data layers (RL1 and RL2) are greater than the magnetic write field. At a high laser power both RL1 and RL2 are heated to above their respective Curie temperatures and data is recorded in both RL1 and RL2. At low laser power only upper RL2 is heated to above its Curie temperature and data is recorded only in RL2. The SL prevents lower RL1 from being heated to above its Curie temperature at low laser power. |
| US09601140B1 |
In-situ smear detection and mitigation in heat-assisted magnetic recording head-disk interface
A procedure for detecting the presence of contamination at a head-disk interface in a heat- assisted magnetic recording (HAMR) hard disk drive involves flying a head slider over a magnetic-recording disk at a particular fly height, applying an oscillating signal to a heat source associated with a HAMR near-field transducer (NFT) that is located in the slider to dither the spacing between the NFT and the disk, and determining, based on change to a contact detection signal, that contamination has accumulated on the slider, generally, or on the NFT, specifically. Burnishing the contamination from the slider may then be performed, by bringing the slider into contact with the disk. |
| US09601138B1 |
Bias layer and shield biasing design
A read head is longitudinally biased unidirectionally by laterally abutting soft magnetic layers or multilayers. The soft magnetic layers are themselves magnetically stabilized by layers of antiferromagnetic material that are exchange coupled to them. The same layers of antiferromagnetic materials can be used to stabilize a unidirectional anisotropy of an overhead shield by means of exchange coupling. By including the antiferromagnetic material layer within the patterned biasing structure itself, an additional layer of antiferromagnetic material that normally covers the entire sensor structure is eliminated. The elimination of an entire layer is also advantageous for reducing the inter-sensor spacing in a TDMR (two dimensional magnetic recording) configuration where two sensor are vertically stacked on top of each other. |
| US09601137B2 |
Magnetic read head with magnetoresistive (MR) enhancements toward low resistance X area (RA) product
A method of forming a magnetoresistive (MR) sensor with a composite tunnel barrier comprised primarily of magnesium oxynitride and having a MR ratio of at least 70%, resistance x area (RA) product <1 ohm-μm2, and fewer pinholes than a conventional MgO layer is disclosed. The method involves forming a Mg/MgON/Mg, Mg/MgON/MgN, MgN/MgON/MgN, or MgN/MgON/Mg intermediate tunnel barrier stack and then annealing to drive loosely bound oxygen into adjacent layers thereby forming MgO/MgON/Mg, MgO/MgON/MgON, MgON/MgON/MgON, and MgON/MgON/MgO composite tunnel barriers, respectively, wherein oxygen content in the middle MgON layer is greater than in upper and lower MgON layers. The MgON layer in the intermediate tunnel barrier may be formed by a sputtering process followed by a natural oxidation step and has a thickness greater than the Mg and MgN layers. |
| US09601136B2 |
Data writer front shield with varying throat height
A data storage device employing a data writer may configure the data writer with at least a write pole that is separated from a front shield on an air bearing surface. The front shield can be arranged to continuously extend from the air bearing surface a first throat height distal the write pole and a second throat height proximal the write pole with the first and second throat heights being different. |
| US09601132B2 |
Method and apparatus for managing audio signals
A method comprising: detect a first acoustic signal by using a microphone array; detecting a first angle associated with a first incident direction of the first acoustic signal; and storing, in a memory, a representation of the first acoustic signal and a representation of the first angle. |
| US09601128B2 |
Communication apparatus and voice processing method therefor
A voice processing method for use in a communication apparatus, in an embodiment, includes the following steps. A near-end audio signal is received by at least one microphone of the communication apparatus. Voice and noise energy data are generated by performing voice activity detection on the near-end audio signal. A noise amount is obtained by performing noise energy calculation with the noise energy data. Whether the noise amount exceeds a first noise amount threshold is determined. If the noise amount exceeds the first noise amount threshold, a sidetone mode of the communication apparatus is enabled to produce a sidetone signal according to the voice energy data and play the sidetone signal through a speaker thereof. A noise suppression mode is enabled to produce a far-end audio signal according to the voice energy data and transmitting the far-end audio signal by a communication module of the communication apparatus. |
| US09601126B2 |
Audio splitting with codec-enforced frame sizes
A method and apparatus for splitting the audio of media content into separate content files without introducing boundary artifacts is described. An exemplary method of streaming media content including audio and video involves a computing system receiving a plurality of content files and staging the encoded portion of the audio of the content files for presentation as a continuous stream. Each of the content files comprises an encoded portion of the video encoded according to a frame rate and having a fixed-time duration and an encoded portion of the audio encoded according to a codec-enforced frame size and having a plurality of full audio frames having the codec-enforced frame size. A duration of the encoded portion of the audio of one or more of the content files is greater than or less than the fixed-time duration. |
| US09601124B2 |
Acoustic matching and splicing of sound tracks
Acoustic matching and splicing of sound tracks is described. In one or more implementations, a method to acoustically match and splice first and second sound tracks by one or more computing devices is described. The method includes source separating the first and second sound tracks into first track primary and background sound data and second track primary and background sound data. Features extracted from the first and second primary sound data are matched, one to another, to generate first and second primary matching masks. Features extracted from the first and second background sound data are matched, one to another, to generate first and second background matching masks, which are applied to respective separated sound data. The applied first track primary and background sound data and the applied second track primary and background sound data are spliced to generate a spliced sound track. |
| US09601120B2 |
Working method of sound transmission-based dynamic token
A working method of a sound transmission-based dynamic token comprises: a dynamic token waiting for disconnection of a key; and when the disconnection of the key is detected, judging the type of a pressed key, and performing a corresponding operation according to different types of keys. |
| US09601119B2 |
Systems and methods for segmenting and/or classifying an audio signal from transformed audio information
A system and method may be provided to segment and/or classify an audio signal from transformed audio information. Transformed audio information representing a sound may be obtained. The transformed audio information may specify magnitude of a coefficient related to energy amplitude as a function of frequency for the audio signal and time. Features associated with the audio signal may be obtained from the transformed audio information. Individual ones of the features may be associated with a feature score relative to a predetermined speaker model. An aggregate score may be obtained based on the feature scores according to a weighting scheme. The weighting scheme may be associated with a noise and/or SNR estimation. The aggregate score may be used for segmentation to identify portions of the audio signal containing speech of one or more different speakers. For classification, the aggregate score may be used to determine a likely speaker model to identify a source of the sound in the audio signal. |
| US09601118B2 |
Amusement system
A technique for allowing a virtual experience of more realistic live performance. A main apparatus reproduces music data and audience video data recording a video image of audience. A user holds a microphone and makes a live performance for the audience displayed on a monitor. The microphone sends voice data and motion information of the microphone to the main apparatus. The main apparatus determines that the user makes a live performance when the user calls on the audience with a specific phrase and performs an action corresponding to the specific phrase. The main apparatus reproduces reaction data recording a video image and sound indicating a reaction of the audience to the live performance. |
| US09601117B1 |
Method and apparatus of processing user data of a multi-speaker conference call
A method and apparatus of sharing documents during a conference call data is disclosed. One example method may include initiating a document sharing operation during a conference call conducted between at least two participants communicating during the conference call. The method may also include transferring the document from one of the two participants to another of the two participants, and recording at least one action performed to the document by the participants during the conference call. |
| US09601114B2 |
Method for embedding voice mail in a spoken utterance using a natural language processing computer system
A method for processing a voice message in a computerized system. The method receives and records a speech utterance including a message portion and a communication portion. The method proceeds to parse the input to identify and separate the message portion and the communication portion. It then identifies communication parameters, including one or more destination mailboxes, from the communication portion, and it transmits the message portion to the destination mailbox as a voice message. |
| US09601112B2 |
Speech recognition system and method using incremental device-based acoustic model adaptation
An embodiment of the present invention relates to a speech recognition system and method using incremental device-based acoustic model adaptation. The speech recognition system comprises a model selection module selecting an acoustic model of multi-model tree by verifying and categorizing a device key transmitted from a user device; a model management module generating and incrementally adapting multi-model tree by categorizing voice data based on a user device; and a speech recognition module performing speech recognition by receiving the acoustic model selected from the model selection module and transmitting data of which reliability exceeds a predetermined threshold value to the model management module. |
| US09601109B2 |
Systems and methods for accelerating hessian-free optimization for deep neural networks by implicit preconditioning and sampling
A method for training a deep neural network, comprises receiving and formatting speech data for the training, preconditioning a system of equations to be used for analyzing the speech data in connection with the training by using a non-fixed point quasi-Newton preconditioning scheme, and employing flexible Krylov subspace solvers in response to variations in the preconditioning scheme for different iterations of the training. |
| US09601099B2 |
Electronic bass drum
An Electronic Bass Drum includes one or more loudspeakers, an internal amplifier system, a removable electronic drum module and control panel, at least one impact sensitive electronic kick pad, an attachment for mounting a bass drum pedal, mounting hardware for tom toms or other acoustic or electronic instruments, legs for stabilization, one or more headphone jacks for silent play, input jacks for other instruments and/or microphones, and an MP3 player cradle for playing along with or recording music. |
| US09601095B2 |
Percussion surface apparatus
A percussion surface apparatus includes: a head which is formed by rubber, and which includes a front surface and a back surface, the front surface which functions as a percussion surface; a cushion member which includes: a first layer that is butted against the back surface of the head, and that is formed by a fiber-based non-woven fabric; and a second layer that is adjacent to the first layer, and that is formed by a porous urethane material; and a supporting unit which is configured to fix and support the cushion member in a state where the cushion member is butted against the back surface of the head at a pressure. |
| US09601094B2 |
Drum stick holder
A repositionable support system for drum-related objects comprises an upper assembly including a base plate adapted to removably receive drum related objects; a lower assembly including an attachment member adapted to removably couple the lower assembly to a recipient object; and an intermediate assembly separably coupling the upper and lower assemblies. |
| US09601093B2 |
Restraint item for endpin of musical instrument and stand for speaker
An endpin support 1 as an example of a musical instrument support to which the present invention is applied includes a lower plate member 2, an upper plate member 3, middle plate members 4, and a load receiving member 5. The lower plate member 2 is a portion that vibrates by resonating with sounds of a musical instrument and spreads vibrancy of the sounds. The lower plate member 2 and the upper plate member 3 are joined at a position at which their one end sides are aligned by two middle plate members 4 to form a main body portion 6 that receives a load when supporting an endpin. The two middle plate members 4 are provided at positions of both ends of the lower plate member 2, and a space is formed between the lower plate member 2 and the upper plate member 3. |
| US09601092B2 |
Dynamically managing memory footprint for tile based rendering
The introduction of an “out-of-memory” marker in the sorted tile geometry sequence for a tile may aid in handling out-of-memory frames. This marker allows hardware to continue rendering using the original data stream instead of the sorted data stream. This enables use of the original data stream allows the system to continue rendering without requiring any driver intervention. During the visibility generation/sorting phase, the number of memory pages required for storing the data for a rendering pass is continuously tracked. This tracking includes tracking the pages that are required even if the hardware had not run out-of-memory. This information can be monitored by a graphics driver and the driver can provide more memory pages for the system to work at full efficiency. |
| US09601090B2 |
Graph display processing system
After an operator has roughly moved a plurality of windows 101-103, with a graph (e.g. spectrum) placed in each window, to desired positions by a manual operation, initial positional coordinates of each window are acquired. The operator also makes an input of the selection of an arrangement pattern (e.g. vertical arrangement). According to the selected arrangement pattern and the number of windows, the sizes of display areas to be formed by dividing a main display frame 100 are calculated, and the display position of each window is also determined. Then, the display order of the windows is calculated from the relative positional relationship of the windows revealed from their initial positional coordinates, and a display screen is eventually formed by resizing each window so as to fit it to the size of the display area and then arranging the windows in the calculated display order. |
| US09601089B2 |
Display device with timing controller connected to source drive integrated circuit by a pair of bidirectional transmission lines, and driving method thereof
A display device includes a display panel including data lines, scan lines, and pixels connecting with the data lines and the scan lines, a scan driver configured to supply scan signals to the scan lines, a source drive integrated circuit (“IC”) configured to convert digital video data into data voltages and to supply the data voltages to the data lines, and a timing controller configured to transmit the digital video data to the source drive IC and to control driving timing of the scan driver and the source drive IC, in which a transmitter and a receiver of the source drive IC are connected via a pair of transmission lines to a transmitter and a receiver of the timing controller. |
| US09601083B2 |
Glare reduction system
A glare reduction system is provided for glare reduction. The glare reduction system includes an imaging source configured to receive light from an object, and a display driver configured to process the received light to generate an input signal. The glare reduction system further includes a display device configured to receive the input signal. A glare reduction panel is positioned anteriorly to the display device. The glare reduction panel including a liquid crystal layer configured to receive the input signal and an end polarizer with an axis of transmission relative to an angle of transmission of a second polarizer of the display device. |
| US09601077B2 |
Circuit for compensating a ripple, method of driving display panel using the circuit and display apparatus having the circuit
A circuit includes a reference signal generating part configured to generate a plurality of reference signals having levels different from each other, a comparing part configured to compare a ripple signal with the reference signals to determine a level of the ripple signal, a compensating signal generating part configured to generate a compensation ripple signal corresponding to the level of the ripple signal, where the compensation ripple signal has a phase opposite to the ripple signal, and a push-pull circuit configured to stabilize the compensation ripple signal. |
| US09601076B2 |
Source driver that generates from image data an interpolated output signal for use by a flat panel display and methods thereof
A source driver that responds to image data by generating an output signal which can be used to drive a flat panel display. The source driver includes a gamma decoder and an amplifier. The gamma decoder selects a first voltage among first analog gray voltages based on some upper bits of the image data, selects a second voltage among second analog gray voltages based on other upper bits of the image data, and selectively outputs at least one of the first and second voltages as a plurality of distributed analog signals in response to lower bits of the image data. The amplifier interpolates between the distributed analog signals from the gamma decoder to generate the output signal of the source driver. The amplifier includes bias circuits that are each configured to generate a bias current, and a plurality of MOSFETs. Each of the MOSFETs includes a source, a drain, and a gate terminal. The gate terminal of each of the MOSFETS is separately connected to receive a different one of the distributed analog signals from the gamma decoder. One of the source/drain terminals of each of the MOSFETS is separately connected to a different one of the bias circuits to receive the bias current, and the other one of the source/drain terminals of each of the MOSFETS is connected together at an output node to generate an interpolated signal. The output signal is based on the interpolated signal. |
| US09601074B2 |
Drive device and display device
Included are: refresh a rate changing section (15) for changing a refresh rate of a display panel (2) by configuring settings for scan periods during each of which a plurality of gate signal lines (G) of the display panel (2) are sequentially scanned and for pause periods during each of which sequential scanning of the plurality of gate signal lines (G) is suspended; and a drive amount control section (20) for controlling, in accordance with a ratio of the scan periods to the pause periods, drive time during which each of the gate signal lines is driven in each of the scan periods. |
| US09601070B2 |
Method for performing detection on display panel
A detection circuit of a display panel and a detection method thereof are disclosed. The detection circuit includes two detection lines respectively for providing scan signals for each row of pixel units. One of the detection lines is only connected to one scan line of the pixel unit and the other one of the detection lines is connected to another scan line of the pixel unit. By way of connecting two scan lines of the pixel unit to different detection lines and applying different voltages respectively thereto, the present invention can detect abnormalities of the display panel. |
| US09601068B2 |
Liquid crystal display control method and system, and display device
Disclosed are liquid crystal display control method and system, and a display device. The liquid crystal display control method comprises: performing a decoding operation on input video signals to obtain data corresponding to respective pixels of a display panel; dividing the display panel into a plurality of display regions so that each display region corresponds to one or more light sources of a backlight source and a symmetric center of the one or more light sources is positioned such that an orthographic projection thereof on the display panel is coincided with a center of the corresponding display region; calculating a control signal for controlling display of each display region based on the data corresponding to pixels in the display region; redividing each display region into a plurality of subregions based on a light distribution in the display region and regulating the control signal for controlling the display of each subregion based on data corresponding to pixels in the subregion; and controlling the display panel and the backlight source based on the regulated control signals. |
| US09601060B2 |
Image processing method and apparatus
The disclosure of the present invention provides an image processing method and apparatus. The method comprises acquiring a single picture image displayed on a display panel; determining an average value of each area relating to a display parameter, after the acquired single picture image is divided into a plurality of areas according to a preset regulation; determining differences between average values of respective two adjacent areas, and determining a uniformity of the single picture image displayed on the display panel in accordance with a relationship between each difference and a threshold of a resolvable picture uniformity by an human eye; adjusting the difference between the average values of the respective two adjacent areas to be not greater than the threshold of the resolvable picture uniformity by the human eye, when determining the single picture image displayed on the display panel to be not uniform. |
| US09601059B2 |
Dynamic backlight control selector
A computer-implemented method for automatically controlling a dynamic backlight control (DBC) of a display is disclosed according to one aspect of the subject technology. The method comprises determining whether an image to be displayed on the display comprises a high-resolution still image, and, if the image comprises a high-resolution still image, then disabling the DBC. |
| US09601057B2 |
Pixel circuit, organic electroluminesce display panel and display device
A pixel circuit, an organic electroluminescent display panel and a display device are provided. The pixel circuit includes a light emitting element, a first capacitor, a reset control module, a drive control module, a compensation control module, and a light emission control module. In a reset phase, the reset control module writes a reset signal at a reset signal end into a second end of the first capacitor. In a compensation phase, the reset control module writes a data signal at a data signal end into a first end of the first capacitor, and the drive control module charges the first capacitor through the compensation control module. In a light emission phase, both the light emission control module and the first capacitor enable the drive control module to drive the light emitting element with a stable current for emission of light. |
| US09601054B2 |
Display device, manufacturing method, and electronic apparatus
There is provided a display device including a pixel array unit in which a plurality of pixels are arrayed in a matrix shape. A predetermined amount of light emission variation is added to a light emission state of each pixel and a cycle of the light emission state of the pixel array unit in the case of the addition is shorter than the cycle of a light emission state of the pixel array unit before the predetermined amount of light emission variation is added. |
| US09601051B2 |
Organic light-emitting display and method of compensating for degradation of the same
Provided are an organic light-emitting display comprising: a display panel which comprises a plurality of pixels, each of the pixels having an organic light-emitting diode (OLED); a sensor configured to detect degradation data indicating a degree of degradation of the OLED of each of the pixels and configured to calculate a degradation data difference between two or more adjacent pixels among the pixels; and a controller configured to set a compensation area utilizing the degradation data difference and configured to generate compensated image data by compensating in the compensation area in input image data. |
| US09601045B2 |
Moving image display apparatus
A moving image display apparatus includes a display unit which sequentially displays an image pattern in the form of a moving image on a display screen, a storage unit which stores area sectional information and display format information, the area sectional information defines predetermined divided areas corresponding to the image pattern among a plurality of divided areas into which the display screen is divided, and the display format information defines display formats of the divided areas defined by the area sectional information in a time sequential manner, and a display control unit which controls to display the predetermined divided areas corresponding to the image pattern in accordance with the display formats defined by the display format information. |
| US09601043B2 |
Display device and display driver with sequential transfer of gray scale reference voltages
The display device includes display drivers including first and second ones operable to output, based on display data, gradation signals to source lines of display panel regions. The display device is arranged to be able to suppress the variation in output voltage between display drivers while minimizing the increases in chip area of the display drivers and in wiring area of a display panel and keeping high noise resistance. Each display driver can generate gray scale reference voltages for producing gradation signals corresponding to display data. The first display driver can sequentially transmit gray scale reference voltages generated by itself to the second display driver. Based on the transmitted gray scale reference voltages, the second display driver makes the first display driver execute calibration for decreasing the absolute value of difference between gray scale reference voltages generated by the first and second display drivers, or executes the calibration by itself. |
| US09601040B2 |
Flat-stock aerial vehicles and methods of use
A flat-stock aerial vehicle includes a body having a plurality of flat-stock sheets connected to one another, at least one motor, and at least three aerodynamic propulsors driven by the at least one motor. The aerodynamic propulsors can provide lifting thrust, pitch, yaw, and roll control in both helicopter-like hover flight and airplane-like translational flight. |
| US09601035B2 |
Reconfigurable label assembly
A reconfigurable label assembly including a container capable of storing or holding a liquid and a front panel, a back panel, a bottom panel, and side panels configured primarily as a label and secondarily as a receptacle capable of holding the liquid separate from the container is presented. The bottom and side panels are disposed between and substantially parallel to the front panel and back panels in a first configuration to form a label attached to and separable from the container. The front and back panels are separable and the bottom and side panels are expandable to form a receptacle in a second configuration after the label is separated from the container. The back panel includes a fold. The side and back panels are disposed between and substantially parallel to the front panel and bottom panel in a first configuration to form a label. The front and bottom panels are separable and the side and back panels are expandable to form a receptacle in a second configuration. The side panels may include additional folds facilitating transformation from a label to a receptacle and from a receptacle to a label. |
| US09601031B1 |
Medical attachment device position detection system and method of use thereof
A medical attachment device position detection system for use during medical training including a processor and a medical attachment device communicatively coupled to the processor, a first magnetometer coupled to the medical attachment device and configured to detect a first angle, and a second magnetometer configured to detect a second angle. The second magnetometer is communicatively coupled to the processor. The processor is operably configured to compare a relationship of the first angle relative to the second angle to determine a position of the medical attachment device relative to a subject. |
| US09601028B2 |
Musical instrument training device and method
A musical instrument training device has a sensor array cooperating with a remote device and an electronic controller to assist as a guide for finger placement on the strings of the instrument, and to provide feedback on proper finger use and placement, the sensor being removably mountable on an instrument neck. |
| US09601027B2 |
Online system for training novice drivers and rating insurance products
a system for determining vehicle driver hazard detection proficiency and calculating insurance discounts, the system comprising: an Internet device that presents to an Internet user a visual presentation of a continuous drive through a driving environment comprising at least two hazard modules, wherein each hazard module presents to the Internet user at least one driving scenario that comprises at least one hazard; an Internet device that records user viewing locations within the visual presentation, the user viewing locations corresponding to locations within the visual presentation that are viewed by the user during the visual presentation of the continuous drive; a computer analytics device comprising an algorithm that compares the recorded user viewing locations with defined locations of hazards within the visual presentation of the continuous drive, and determines a hazard detection proficiency of the user based at least on the comparison; a computer memory device comprising at least one minimum hazard detection proficiency criteria corresponding to an insurance discount; and a computer analytics device that compares the determined hazard detection proficiency of the user with the minimum hazard detection proficiency criteria and determines whether to award the insurance discount to the user. |
| US09601024B2 |
Online proctoring process for distance-based testing
A system for enabling real time live proctoring of an exam across a distributed network includes a first remote computer. The first remote computer is capable of real time audio visual capture and display of an image of a user of the first remote computer. A second remote computer is capable of real time audio visual capture and display of an image of the user of the second remote computer. A server is in communication with the first remote computer and the second remote computer, and provides an interactive web based scheduling portal accessible from the first remote computer and the second remote computer. A database is associated with the server for storing data regarding the rules for proctoring of an exam including the rate at which an exam may be proctored at a given date and time. The server enables access to a virtual exam room by the first remote computer and the second remote computer in response to a request from the first remote computer through the scheduling portal for a date and time to take an exam administered at the first computer when the requested date and time fulfils the rules stored in the database. |
| US09601023B2 |
Flight control for flight-restricted regions
Systems, methods, and devices are provided for providing flight response to flight-restricted regions. The location of an unmanned aerial vehicle (UAV) may be compared with a location of a flight-restricted region. If needed a flight-response measure may be taken by the UAV to prevent the UAV from flying in a no-fly zone. Different flight-response measures may be taken based on the distance between the UAV and the flight-restricted region and the rules of a jurisdiction within which the UAV falls. |
| US09601021B2 |
Retrospective analysis of vehicle operations
Method and apparatus for generating and outputting dynamic variance reports for vehicle operations. The dynamic variance reports enable a vehicle operations scheduler to understand trends, patterns, or the like in variances between planned vehicle operations and actual vehicle operations. The understanding of the variances provided by the dynamic variance reports enable the scheduler to apply buffers to vehicle operations plans so that planned vehicle operations more closely match actual vehicle operations and crew assignments are less likely to be disrupted. |
| US09601019B2 |
Cleaning robot and method for controlling the same
A cleaning robot includes a non-circular main body, a moving assembly mounted on a bottom surface of the main body to perform forward movement, backward movement and rotation of the main body, a cleaning tool assembly mounted on the bottom surface of the main body to clean a floor, a detector to detect an obstacle around the main body, and a controller to determine whether an obstacle is present in a forward direction of the main body based on a detection signal of the detector, control the rotation of the main body to determine whether the main body rotates by a predetermined angle or more upon determining that the obstacle is present in the forward direction, and determine that the main body is in a stuck state to control the backward movement of the main body if the main body rotates by the predetermined angle or less. |
| US09601018B2 |
Distributed parking space detection, characterization, advertisement, and enforcement
A mechanism is provided for parking space management of a managed parking structure. Information is received from a vehicle that has parked in the managed parking structure. The information from the vehicle is utilized to determine a probabilistic location of the vehicle within the managed parking structure. Responsive to determining the probabilistic location of the vehicle within the managed parking structure using the information from the vehicle, an occupied parking space evidence data structure is updated with a vehicle identifier of the vehicle as being associated with the location of the vehicle within the managed parking structure. |
| US09601017B2 |
Reckless-vehicle reporting apparatus, reckless-vehicle reporting program product, and reckless-vehicle reporting method
A reckless-vehicle determination section of a vehicle determines whether a reckless driving operation takes place in each of different vehicles based on determination information from each of the different vehicles. A target different vehicle in which a reckless driving operation is determined to take place is displayed on a display in a display mode that is different from that for any different vehicle in which a reckless driving operation is not determined to take place. |
| US09601015B2 |
Maintenance decision support system and method for vehicular and roadside applications
A method and system are provided in which maintenance vehicles collect information from sensors and operators, forward the collected information to a server, and, in response, receive maps and operator instructions. |
| US09601010B2 |
Assessment device, assessment system, assessment method, and computer-readable storage medium
An assessment device (1) includes: a request acquirer (11) that accepts an evaluation target from a user terminal (7); a model acquirer (13) and a data acquirer (14) that select a main model for evaluating the evaluation target accepted by the request acquirer (11) from a plurality of models and select supplemental data to be supplemented for using the main model (data to be input into the main model, a sub-model, or data to be input into the sub-model) when the data to be input into the main model is insufficient; an executor (15) that evaluates the evaluation target based on the main model and supplemental data selected by the model acquirer (13) and the data acquirer (14); and a transmitter (16) that provides a result of the evaluation by the executor (15) to the outside. |
| US09601006B2 |
Universal remote control with automatic state synchronization
Disclosed herein are system, method, and computer program product embodiments for synchronizing a state change at a universal remote control. An embodiment operates by sending a state change of the universal remote control to a remote-controlled device. The universal remote control then receives a confirmation message from the remote-controlled device. The universal remote control then updates a state configuration for the remote-controlled device in the universal remote control based on the sent state change. Because the universal remote control exchanges state change information with the remote-controlled device, the universal remote control does not become out of synchronization with the remote-controlled device which minimizes synchronization time and reduces user experience frustration. |
| US09601000B1 |
Data-driven alert prioritization
A technique provides alert prioritization. The technique involves selecting attributes to use as alert scoring factors. The technique further involves updating, for an incoming alert having particular attribute values for the selected attributes, count data to represent encounter of the incoming alert from perspectives of the selected attributes. The technique further involves generating an overall significance score for the incoming alert based on the updated count data. The overall significance score is a measure of alert significance relative to other alerts. Scored alerts then can be sorted so that investigators focus on the alerts with the highest significance scores. Such a technique is well suited for adaptive authentication (AA) and Security Information and Event Management (SIEM) systems among other alert-based systems such as churn analysis systems, malfunction detection systems, and the like. |
| US09600998B2 |
System, apparatus, and method for sensing gas
According to another exemplary embodiment, a method of cutting power from a source when sensing gas may be provided. The method of cutting a power from a source when sensing gas may include obtaining a gas sensing apparatus, which may a housing, at least one power relay rigidly connected to the inside of the housing, at least one sensor connected to the power relay, at least one alarm connected to the at least one sensor, at least one port power wire outlet connected to the power relay, at least one power socket connected to the power relay, a power transformer connected to the power relay, and a power inlet connected to the power transformer, connecting the gas sensing apparatus to a power supply, connecting an electrical device to the gas sensing apparatus, sensing gas by the sensor, creating a voltage that stops power flow to the at least one outlet, and applying a voltage to the at least one port power wire outlet. |
| US09600993B2 |
Method and system for behavior detection
Described herein are systems and methods for automatically detecting a behavior of a monitored individual, for example, that the individual has fallen. In certain embodiments, a system is presented that includes one energy sensor (e.g., a camera of a mobile electronic device) configured to capture reflected energy (e.g., light) within a field-of view; an optional lens to modify the distance or angular range of the field-of-view; and an optional image obfuscator to blur or distort the images received by the energy sensor, thereby preserving privacy. Techniques are described for determining spatial measurements and body measurements from the images and using these measurements to identify a behavior of the monitored individual, for example, a fall. |
| US09600991B2 |
System and method for measuring physiological parameters
A method for measuring a physiological parameter is disclosed. The method includes providing an electronic device having a radio reader transmitting and receiving a radio signal; providing a physiological parameter measurement device configured with an energy storage module, a transmission module and a strip port for receiving a strip; energy storage in the physiological parameter measurement device in response to a radio energy storage signal transmitted from the electronic device until it reaches a sufficient energy status; and applying a sensing voltage to the strip via the strip port, receiving a sensing signal from the strip, and converting the sensing signal into a physiological parameter measurement signal by the physiological parameter measurement device under the sufficient energy status. |
| US09600990B2 |
System and methods for generating predictive combinations of hospital monitor alarms
Systems and methods are disclosed for monitoring data associated with a plurality of physiological characteristics of a patient, comprising: the methods include generating a set of super-alarm patterns associated with the plurality of physiological conditions, wherein the super-alarm patterns comprising data relating to a combination of at least two individual raw alarms from independent physiological data streams that co-occur within a temporal window, and triggering an alarm if a combination of the input physiological data matches at least a portion of a generated super-alarm pattern. |
| US09600985B1 |
Wearable computing system with temporal feedback during presentations
Aspects include a system for providing feedback to a user with a wearable device. The system including a wearable device and a feedback mechanism disposed within the wearable device. The feedback mechanism configured to vibrate the wearable device. A memory is provided having computer readable instructions. One or more processors are provided for executing the computer readable instructions, the one or more processors being coupled to communicate with the feedback mechanism. The computer readable instructions include defining at least one prompt point that is associated with a first time parameter. The instructions further include determining when the current time is equal to the first time parameter. The instructions provide for actuating the feedback mechanism in response to the current time being equal to the first time period. |
| US09600982B2 |
Methods and arrangements for identifying objects
In some arrangements, product packaging is digitally watermarked over most of its extent to facilitate high-throughput item identification at retail checkouts. Imagery captured by conventional or plenoptic cameras can be processed (e.g., by GPUs) to derive several different perspective-transformed views—further minimizing the need to manually reposition items for identification. Crinkles and other deformations in product packaging can be optically sensed, allowing such surfaces to be virtually flattened to aid identification. Piles of items can be 3D-modeled and virtually segmented into geometric primitives to aid identification, and to discover locations of obscured items. Other data (e.g., including data from sensors in aisles, shelves and carts, and gaze tracking for clues about visual saliency) can be used in assessing identification hypotheses about an item. Logos may be identified and used—or ignored—in product identification. A great variety of other features and arrangements are also detailed. |
| US09600980B2 |
Electronic gaming machine and gaming method
An electronic gaming machine comprises a display for displaying game symbols for playing a first game of chance, and an electronic game controller for controlling the display of the game symbols on the display. In response to a trigger event in the first game, a second game of chance is displayed, where the appearance of one or more special symbols causes the award of one or more tokens associated with one or more token values. At the end of the second game, an accumulated token value is determined and if it is equal to a predetermined number, a plurality of third games of chance is displayed and is selectable by the player. The third games displayed depend on the accumulated token value. A gaming method is also provided. |
| US09600977B2 |
Method and apparatus for electronic gaming
A system and method for providing a card game is provided. Players are provided an option to enter one or more tournaments (for real monies or play monies). In an embodiment, a tournament lasts for a predetermined number of hands for a predetermined duration. As an example, a tournament duration may be defined by the number of players who bust out or complete a requisite number of hands by a predetermined date and time, or is defined by a specified number of players who bust out or complete the requisite number of hands. A tournament payout pool is determined based on the number of players who busted out or played in the tournament for a predetermined number of hands and duration. |
| US09600976B2 |
Adaptive mobile device gaming system
Embodiments disclosed herein concern mobile gaming environments. Portable electronic devices can be supported by the mobile gaming environments. The locations of the portable electronic device can influence how the portable electronic devices operate or what services or features are available to the portable electronic device or their users. According to one embodiment, a mobile gaming system can concern gaming/betting opportunities that can be secured using a portable electronic device even when an individual is located in a location where betting or games of chance are not permitted. According to another embodiment, a mobile gaming system can concern an application program operating on a portable electronic device that supports multiple modes of operation depending upon whether the portable electronic device is in a location where betting or games of chance are permitted. |
| US09600972B2 |
Game system, game server therefor, control method for game server, and computer readable recording medium
A first game system includes plural terminal devices at which a game can be played by a player; and a game server configured to communicate with the terminal devices. The first game server stores game data corresponding to the game in a database, and updates game data stored in the database in accordance with the progress of a game that is played at one of the terminal devices, followed by again updating the game data in accordance with the progress of the game that is played at another of the terminal devices. |
| US09600970B2 |
Electronic gaming machine and gaming method
An electronic gaming machine includes a display for displaying a game including game symbols arranged into an array of predetermined game positions. An electronic game controller designates at least one of the predetermined game positions as a special game position in the array such that a special symbol appearing in the special game position in a play of the game causes the electronic game controller to award a game enhancing element to the player. The special game position is visually indicated on the array to the player during the play by a graphical element associated with the special game position. A gaming method is also provided. |
| US09600966B2 |
Systems and methods for tracking of non-wagering account associated with gaming environment
Systems and methods are disclosed for associating a player identifier with a stored value account. The stored value account can holds funds that are accessible through the player's use of a stored value payment vehicle. Information associated with transactions using the stored value payment vehicle can be used for player relationship purposes. |
| US09600959B2 |
System for managing promotions
In various embodiments, promotions are featured on mobile gaming devices. |
| US09600958B2 |
Gaming, system, method and device including a symbol changing or augmenting feature
Gaming systems, devices and methods are set forth which provide for the selection and application of modifiers to game outcomes. The modifiers confer different functionalities to base game symbols or an augmenting functionality to alter or provide an outcome. Different sets of modifiers may be accessed randomly or under different conditions and events. |
| US09600956B2 |
Wagering gaming device having simulated control of movement of game functional elements
A wagering gaming device that enables a player to affect the movement of a functional element of a game by use of a user input device. More specifically, the present invention provides a processor controlled wagering gaming device that receives input from a user input device. The user manipulates the input device in the manner in which he wishes the functional element or to move. The processor receives the information from the input device and calculates parameters. The processor moves the functional element. This sequence or feature may be employed in a primary game, bonus game or in any stand alone game. |
| US09600950B2 |
Communication system and method
A vehicle system includes a vehicle communication module in the vehicle, a remote start system in the vehicle, and a vehicle processor. The vehicle processor is configured to determine if the vehicle is in a garage, and further configured to receive an indication of a remote start request from the remote start system, receive a garage door status from a garage door opener using the vehicle communication module, and determine, based on the received garage door status, if a garage door is closed. In response to determining that the garage door is closed, the vehicle systems transmits a remote command to the garage door opener formatted to cause the garage door opener to open the garage door. |
| US09600945B2 |
Lifestyle multimedia security system
A method is disclosed for remote monitoring of a premises, comprising the steps of operatively coupling a geographically remote client to a security system server which is capable of authenticating a user of the remote client, operatively coupling the remote client to a security gateway which is capable of managing the monitoring of the premises, activating a signal at the premises for notifying an occupant at the premises that remote monitoring is occurring, and transferring information between the security gateway and the remote client. The transfer of information between the security gateway and the remote client is controlled by the user of the remote client. The security gateway may be operably coupled to at least one camera at the premises and to at least one audio station at the premises. |
| US09600941B2 |
Method and arrangement for transporting cuboidal items
An image, which can be analyzed by a computer and shows at least one face of an item, is generated for an item that is to be transported at a predefined time. By automatic analysis of the image, the arrangement determines, for at least one of a plurality of predetermined optically detectable features, the value of the feature for the image of the item. The identification feature value vector generated is automatically compared with stored registration feature value vectors. A record for a particular item contains six registration feature value vectors and each of the six registration feature value vectors specifies a value for each predefined optically detectable feature for each one of six faces of the item. When the identification feature value vector matches a stored registration feature value vector with sufficient accuracy, a message is generated. |
| US09600939B1 |
Augmented reality platform using captured footage from multiple angles
This disclosure relates to systems and methods for augmenting visual information to simulate an appearance of an object and/or a person at an adjustable position and angle. The visual information may be captured by an image sensor. The object and/or the person may have been captured at multiple angles. A user may select at which particular position and angle the appearance will be superimposed and/or otherwise combined with the visual information. |
| US09600937B1 |
Camera arrangements with backlighting detection and methods of using same
A method of providing an image to be displayed includes providing captured scene data representing one or more images of a real scene and providing illumination data representing real illumination impinging on the real scene, providing a virtual reality image of a theoretical object by modeling said theoretical object using said illumination data to define illumination impinging on the theoretical object, and providing a combined image including elements of the real scene based on said captured scene data and including said virtual reality image. |