| Document | Document Title |
|---|---|
| US09571208B2 |
Input/output device, mobile device, and information displaying device
Provided is an input/output device, including: a touch unit that is touched by a human body; an information processing unit that performs information processing based on a touch made on the touch unit by the human body; and a human-body communication unit that performs human-body communication by using the human body touching the touch unit as a path. |
| US09571204B2 |
LED optical communication receiving lens and LED optical communication system
A LED optical communication receiving lens includes a first surface and a second surface opposite to the first surface. The first surface includes a first spherical surface and a second spherical surface connected to the first spherical surface. The second surface includes a third spherical surface and a planar surface connected to the third spherical surface. A position of the LED optical communication receiving lens is defined as a three-dimensional Cartesian coordinate system (x, y, z). Sphere centers and symmetric central points of the first spherical surface, the second spherical surface, and the third spherical surface are located on the x axis. The first spherical surface and the planar surface are transmitted surfaces. The second spherical surface and the third spherical surface are reflective surfaces. The present application also relates to a LED optical communication system including the LED optical communication receiving lens. |
| US09571202B2 |
Optical connector assembly
An optical connector assembly, includes: a printed circuit board including a supporting surface and a notch; a fixing portion embedded into the notch and comprising a first surface, a second surface, a lead frame and an electrical pin arranged from the fixing portion to the supporting surface to be flush with the supporting surface, a positioning slot disposed on the first surface; a joint portion comprising a first side, plural openings penetrating the first side, the joint portion extending from an edge of the first side to cover the top of the fixing portion, a positioning pin disposed on the first side; plural chips disposed on the fixing portion; plural fibers inserted through the openings. Wherein the positioning pin is engaged into the positioning slot, such that the fibers are coaxially aligned with the chips for light transmission. |
| US09571201B2 |
Transmission apparatus, line card and control method of transmission apparatus
A transmission apparatus includes: a module configured to receive and transmit data externally, the data received and to be transmitted being transferred via an interface internally; a framer configured to process transmission and reception of the data processed by the module; a transmission channel on which predetermined data is transmitted and received to and from the framer; and a controller configured to determine a combination of setting values for transmission and reception in accordance with a surrounding environment of the transmission channel, based on an error rate when the predetermined data is transmitted and received for each combination of setting values for transmission and reception on the transmission channel, and to perform setting for transmission and reception via the interface, based on the determined combination of setting values for transmission and reception. |
| US09571199B1 |
In-band control of network elements
A network element that allows in-band control of the network element includes a plurality of interfaces for connecting to other network elements. The network element includes a high data rate transceiver logic configured for transmitting and receiving communications having a first data rate over a first communication channel. The network element also includes a low data rate transceiver logic configured for transmitting and receiving communications having a second data rate that is substantially lower than the first data rate over a second communication channel. The network element further includes a shared photodiode for receiving optical signals over the first and second communication channels. The shared photodiode also converts received optical signals into electrical signals for processing by one of the high data rate transceiver logic and the low data rate transceiver logic. A shared laser module configured to be driven by the high data rate transceiver logic and the low data rate transceiver logic is also included in the network element to output an optical signal over a fiber optic cable via one of the first and second communication channels. |
| US09571195B2 |
Optical relay cable
Described herein is a system for transmitting an optical signal from a first location to a second location. The system may include first and second mounting fixtures, a reception module, an optical fiber, and a transmission module. The first fixture may define at least a first cavity and a first aperture at the bottom of the cavity. The reception module may be disposed in the cavity, and include a reflector for receiving the optical signal from a first direction through the first aperture and redirecting the optical signal in another direction. The optical fiber may be for receiving the optical signal from the reflector. The second fixture may define at least a second cavity and a second aperture on the side of the cavity. The transmission module may be disposed in the second cavity and direct the optical signal from the optical fiber through the second aperture. |
| US09571192B2 |
Simultaneous multi-channel optical communications system with beam pointing, switching, and tracking using moving focal plane devices
A communications system made up of a number of multi-channel optical node (MCON) platforms uses free space optical communications terminals that have the ability to track, detect, measure, and respond to the acceleration or movement of the platform. Instead of using mirrors or traditional beam steering techniques, the platform uses a series of telecentric lens systems to re-align the focal plane such that beams are maintained in original pointing directions. A network of control systems is used to detect and measure movement of the platform, to re-align the platform after such movement, and to maintain connection with a number of other MCON platforms. |
| US09571188B2 |
Apparatus and method for inline monitoring of transmission signals
An apparatus for inline monitoring of transmit signals is disclosed. The apparatus includes a processor, and one or more fiber optic lines for supplying a transmit signal to/from a remote transmission station. The processor is configured to receive input for selecting one or more fiber optic lines for examination, determine at least one property of the transmit signal to be monitored, and retrieve information corresponding to the at least one property for a predetermined period of time. The processor is further configured to output a visual representation of the retrieved information, perform an analysis of the retrieved information and the visual representation, and facilitate identification of at least one status associated with the transmit signal based, at least in part, on the analysis. |
| US09571185B2 |
Robust, fast unused-code detection
Techniques for processing a received multi-code code-division multiple-access (CDMA) signal to detect unused spreading codes are disclosed. An example method includes, for each of a plurality of observation time intervals and for each of one or more candidate spreading codes, determining a detection threshold for use in detecting whether the candidate spreading code is unused in the received multi-code CDMA signal, based on a target detection sensitivity and at least one of an estimate of received signal quality and an estimate of channel estimation quality. Estimated signal power for the candidate spreading code is compared to estimated noise and interference power corresponding to a spreading code that is known to be unused or corresponding to a spreading code that carries known symbol values, using the calculated detection threshold. Whether or not the candidate spreading code is unused is then determined, based on the comparison. |
| US09571183B2 |
Systems and methods for polarization control
The described technology uses a dual circularly polarized panel antenna and equal amplitude variable phase control between the two circularly polarized components to achieve a rotatable linear polarization tracking system. An example antenna system includes a plurality of antenna elements that include a plurality of polarization transducers to generate a first signal component and a second signal component from a received wave. A polarization control network applies a phase difference based on an orientation of the linear polarization of the wave with respect to the antenna system between the signal components to generate adjusted signal components. The polarization control network combines the adjusted signal components to form a composite signal that corresponds to the linear polarization of the wave. Linearly polarized transmit and receive signals may be co-polarized or cross-polarized. |
| US09571182B2 |
Systems and methods for cancellation of cross-coupled noise
Systems and methods for canceling cross-coupled satellite signals in a LNB IC include receiving a first satellite signal at a first pin of the LNB IC and adjusting the first satellite signal by applying a first adaptive filter to the first satellite signal signal, the first adaptive filter having first filter coefficients; combining the adjusted first satellite signal with a second satellite signal received at a second pin of the LNB IC to generate a first combined satellite signal; measuring the total output power of the combined satellite signal; changing the filter coefficients of the first adaptive filter; remeasuring the total output power of the first combined satellite signal after the changing of the first filter coefficients to determine whether the total power of the first combined satellite signal has decreased. |
| US09571178B2 |
Method and apparatus for transmitting and receiving data in a wireless communication system that supports a relay node
A method and apparatus for transmitting and receiving data in a wireless communication system that supports a relay node are disclosed, wherein an open-loop mode is provided between the relay node and a user equipment. A method for transmitting data from a relay node to a user equipment comprises the steps of receiving information on a first condition related to transmission of the data from a base station; receiving first data including a plurality of sequential codes from the base station; and transmitting second data corresponding a part of the first data to the user equipment in accordance with the first condition if decoding of the first code of the plurality of codes is successfully performed. |
| US09571177B2 |
Communication method of macro base station, macro terminal, micro base station, and micro terminal for interference control in hierarchical cellular network
A communication method of a macro base station, a macro terminal, a micro base station, and a micro terminal determines an interference control scheme for each interference condition between a micro cell and a micro cell and between a macro cell and a micro cell in a hierarchical cellular network, and controls interference in the hierarchical cellular network where a detailed operation for each determined interference control scheme, a message associated with the detailed operation, and a resource management scheme are defined. |
| US09571176B2 |
Active MIMO antenna configuration for maximizing throughput in mobile devices
The disclosure concerns active antenna systems, including active multi-input multi-output (MIMO) antenna systems, and radiofrequency integrated circuit modules for controlling such active antenna systems. |
| US09571174B2 |
Precoding method, precoding device
Disclosed is a precoding method for generating, from a plurality of baseband signals, a plurality of precoded signals that are transmitted in the same frequency bandwidth at the same time. According to the precoding method, one matrix is selected from among matrices defining a precoding process that is performed on the plurality of baseband signals by hopping between the matrices. A first baseband signal and a second baseband signal relating to a first coded block and a second coded block generated by using a predetermined error correction block coding scheme satisfy a given condition. |
| US09571172B2 |
Method of maximizing MIMO throughput by placing antennas in a vehicle
An arrangement of MIMO antennas in a vehicle, such as an automobile, where at least one of the MIMO antennas is placed inside the vehicle in the richer multipath signal propagation environment. The MIMO antennas will include a primary MIMO antenna that may also be used for non-4G cellular services and one or more secondary MIMO antennas that are used only for 4G cellular services. In one embodiment, the primary MIMO antenna is mounted to a roof of the vehicle in a module including other antennas and the one or more secondary antennas are positioned at desired locations within the vehicle. In another embodiment, the primary MIMO antenna and the one or more secondary MIMO antennas are all positioned within the vehicle. |
| US09571171B2 |
Apparatus and method for adaptive beam-forming in wireless communication system
Apparatuses and methods for maintaining an optimal beam direction in a wireless communication system are provided. The method for operating a receiving node in a wireless communication system includes, determining a first transmission beam is determined as a preferred transmission beam using a plurality of reference signals transmitted by a transmitting node, generating preferred transmission beam information, transmitting the preferred transmission beam information to the transmitting node, receiving transmissions from the transmitting node via the first transmission beam, and determining whether a change of a transmission beam is necessary. When the change of the transmission beam is determined to be necessary, generating a beam change request and transmitting the beam change request to the transmitting node. |
| US09571168B2 |
Data transceiver device and receiving method for near field communication
A data transceiver device for near field communication is provided which includes a matching and filtering circuit connected between an antenna and a transceiver and configured to conduct filtering and impedance matching for a reception signal and a transmission signal. The matching and filtering circuit includes a variable attenuator of which the impedance varies with a frequency so that an attenuation ratio of the reception data is smaller than that of the reception carrier signal. |
| US09571167B2 |
Near field communication antenna device of mobile terminal
A near field communication antenna device of a mobile terminal having a near field communication antenna function of 13.56 MHz by Alternating Current (AC) coupling a conductive pattern of a touch screen panel is provided. The device includes a conductive pattern formed in a touch screen panel, a first antenna line AC-coupled to one end of the conductive pattern, a second antenna line AC-coupled to the other end of the conductive pattern, and a near field communication module connected to the first antenna line and the second antenna line. Therefore, a near field communication antenna can be embodied using a conductive pattern of an existing touch screen panel. Accordingly, an increase in thickness and material cost of a mobile terminal can be prevented. |
| US09571166B2 |
Testing tuned circuits
Methods and systems for determining one or more parameters of a tuned circuit forming part of a wireless energy transmission system in an implanted (or implantable) medical device are described. The method involves energizing the tuned circuit then receiving a signal back from it. This signal is then analyzed to determine a property of the circuit such as its quality factor (Q) or resonant frequency. Also described herein is a method and system for determining the implantation depth of a component of an implanted medical device. The method involves determining the position of a magnetic element which is mounted in a fixed physical relationship with the component of the medical device. The methods can be performed on an implanted medical device without the need to explant the device. |
| US09571165B2 |
NFC communication with an information handling system supplemented by a management controller and advertised virtual tag memory
Near Field Communication (NFC) supports server information handling system management through communication between a mobile information handling system and a baseboard management controller. Enhanced transfer by NFC of management information is provided by manipulating the NFC tag memory assigned for information transfer with the aid of a microcontroller coordinating NFC transfers at the baseboard management controller, such as with coordinated storage operations at a tag memory an supporting processors/microcontrollers. The microcontroller manages tag memory and/or system memory so that the portable information handling system writes and reads information beyond the capabilities of unaided tag memory. |
| US09571162B2 |
Non-contact power supply system and non-contact power supply method
A wireless power transfer system includes a transmission device that performs power supply by wireless power transfer to a power receiving device, a position acquiring section that acquires a current position of the power receiving device, and a control section that performs control to authorize the power supply in a case where the power receiving device is in a preset area and to not authorize the power supply in a case where the power receiving device is outside the preset area. |
| US09571161B2 |
Contactless communication unit connector assemblies
Contactless extremely high frequency connector assemblies, passive cable connector assemblies, and active cable connector assemblies are disclosed herein. In one embodiment, a contactless connector assembly can include several (EHF) contactless communication units operable to selectively transmit and receive EHF signals, and several signal directing structures coupled to the EHF CCUs. The signal directing structures can direct the EHF signals along a plurality of EHF signal pathways. |
| US09571158B2 |
System and method for inferring schematic and topological properties of an electrical distribution grid
A system and method for inferring schematic and topological properties of an electrical distribution grid is provided. The system may include Remote Hubs, Subordinate Remotes, a Substation Receiver, and an associated Computing Platform and Concentrator. At least one intelligent edge transmitter, called a Remote Hub Edge Transmitter, may transmit messages on the electrical distribution grid by injecting a modulated current into a power main that supplies an electric meter. The Subordinate Remotes, Remote Hubs, the Substation Receiver, and the associated Computing Platform and Concentrator may contain processing units which execute stored instructions allowing each node in the network to implement methods for organizing the on-grid network and transmitting and receiving messages on the network. The Substation Receiver, Computing Platform and Concentrator may detect and infer schematic grid location attributes of the network and publish the detected and inferred attributes to other application systems including geospatial information systems maintaining the logical and physical network model. |
| US09571153B2 |
Method of cancelling SI signal at RF-front end and UE for the same
A user equipment (UE) for cancelling a self-interference (SI) signal is disclosed. The UE includes a rat-race coupler, a plurality of transceiving antennas capable of transmitting and receiving signals, a receive antenna, a transmission (Tx) chain connected to an input port when the rat-race coupler uses one port as the input port, and a reception (Rx) chain connected to the receive antenna and an isolated port when the rat-race coupler uses the one port as the input port. |
| US09571149B2 |
Tablet computer case
A device case for a portable electronic device includes a device stand attached to a back surface of the case housing. The device stand is formed by an inner stand and outer stand connected by releasable hinged connections to the back surface of the case housing. A track is formed on a surface of the outer stand that the inner stand slides along. A locking portion such as a cavity or channel on the outer stand locks the inner stand into an open position with respect to the outer stand. At least a portion of the outer stand is flexible such that applying a threshold pressure to the device case causes the portion of the outer stand to flex such that the locking portion releases the inner and outer stand from the open position without damaging the stand. |
| US09571142B2 |
Apparatus to detect interference in wireless signals
An apparatus to detect interference in wireless signals, comprising an antenna for receiving a wireless signal; and wherein the apparatus is operable to identify a dominant waveform in the received signal; subtract the dominant waveform from the received signal to create a modified received signal; and repeat the above steps, recursively substituting the modified received signal for the received signal, until all adjusted reference waveforms have been subtracted. |
| US09571141B2 |
Wireless communication device and method of operating the same
A calibrator to process an output signal of an analog digital converter in a wireless communication device, the calibrator comprising a level filter to remove noise from the output signal of the analog digital converter using mask information regulating a signal level; a timing filter to remove pulses from the level-filtered signal that are beyond a reference duty ratio by using timing information; a pattern filter to remove pulses from the timing-filtered signal that are judged to not comprise a reference number of consecutive pulses by using pattern information; and a duty correction circuit to correct a duty of the pattern-filtered signal to improve performance of the wireless communication device by separately performing a filtering operation on noise and a damping component included in a normal signal. |
| US09571140B2 |
Space-time coding for zero-tail spread OFDM system in a wireless network
An example technique may include controlling receiving a first block of time domain symbols and a second block of time domain symbols, converting the blocks of time domain symbols to the frequency domain to create a first pre-equalized block of frequency domain symbols and a second pre-equalized block of frequency domain symbols, respectively, applying, a linear phase shift to the frequency domain symbols to compensate for a conjugating and time-reversing of corresponding pre-spread domain symbols being performed at a transmitter before spreading of the pre-spread domain symbols, and creating a first equalized block of frequency domain symbols and a second equalized block of frequency domain symbols as a function of the first and second pre-equalized blocks of frequency domain symbols wherein at least one of the first and second pre-equalized blocks of frequency domain symbols has the linear phase shift applied. |
| US09571135B2 |
Adjusting power amplifier stimuli based on output signals
Compensation for one or more effects of impedance mismatch between a power amplifier (PA) and at least one filter is discussed. One example system that compensates for impedance mismatch with at least one filter comprises a PA, a measurement component, and a feedback component. The PA is configured to receive PA stimuli comprising a supply voltage and a radio frequency (RF) signal to be amplified, wherein a PA output is configured to be coupled to the at least one filter. The measurement component is coupled to the PA and configured to measure an output signal from the PA, wherein the output signal comprises a forward signal associated with the PA and a reflected signal associated with the at least one filter. The feedback component is configured to receive the output signal and to adjust one or more of the PA stimuli based at least in part on the output signal. |
| US09571134B2 |
Transmit noise reducer
A transmit drive circuit with high signal to noise and frequency agility. In one embodiment, a transmit circuit includes a digital to analog converter, an amplifier, and a signal to noise enhancer, the signal to noise enhancer being a nonlinear passive device that attenuates low-power signals while transmitting high power signals with little loss. The signal to noise enhancer may be fabricated as a thin film of yttrium iron garnet (YIG) epitaxially grown on a gadolinium gallium garnet (GGG) substrate, the GGG substrate secured to a microwave transmission line from the input to the output of the signal to noise enhancer, such that the thin film of yttrium iron garnet is close to the transmission line. |
| US09571133B2 |
Duplexer
A duplexer having good insulation, small geometric dimensions and good decoupling of the transmit signal path from an antenna which may have poor matching is specified. To that end, the duplexer comprises two transmit filters, a receive filter and two 90° hybrids. |
| US09571132B1 |
Radio transmitter system and method
A radio transmitter system includes: a transmitter for deriving a carrier frequency modulated by an input; an electrically short antenna system, and a matching network between the transmitter and antenna system. The matching network includes: a primary circuit responsive to the transmitter, a secondary circuit including the antenna system, and magnetic or capacitive coupling between the primary and secondary circuits. The magnetic coupling is an air core transformer having first and second windings respectively included in the primary and secondary circuits. The matching network has a voltage versus frequency response including at least two horns spaced from each other such that the matching network has a pass band approximately equal to the modulation bandwidth. |
| US09571127B2 |
Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals
The present invention provides a method of transmitting broadcast signals, the method including, encoding service data, building at least one signal frame by mapping the encoded service data, modulating data in the built at least one signal frame by an Orthogonal Frequency Division Multiplexing, OFDM, scheme and transmitting the broadcast signals having the modulated data. |
| US09571123B2 |
Data compression systems and methods
Data compression using a combination of content independent data compression and content dependent data compression. In one aspect, a system for compressing data comprises: a processor, and a plurality of data compression encoders wherein at least one data encoder utilizes asymmetric data compression. The processor is configured to determine one or more parameters, attributes, or values of the data within at least a portion of a data block containing either video or audio data, to select one or more data compression encoders from the plurality of data compression encoders based upon the determined one or more parameters, attributes, or values of the data and a throughput of a communications channel, and to perform data compression with the selected one or more data compression encoders on at least the portion of the data block. |
| US09571120B2 |
Digital to analog converter circuits, apparatus and method for generating a high frequency transmission signal and methods of digital to analog conversion
A digital to analog converter circuit includes a plurality of digital to analog converter cells. The digital to analog converter circuit further includes a control circuit configured to control an operation of a digital to analog converter cell of the plurality of digital to analog converter cells based on a first phase component of a digital signal comprising information to be transmitted during a first time interval and based on a second phase component of the digital signal comprising information to be transmitted during a second time interval. |
| US09571118B1 |
Pre-charge buffer for analog-to-digital converter
A pre-charge buffer for sampling input signals and generating a sampled output signal includes a coarse sampling circuit, a fine sampling circuit, and a sample and hold circuit. The coarse sampling circuit pre-samples the input signals during hold phases and for a first predetermined time interval during sample phases of the corresponding sample and hold cycles, and generates a first output signal. The fine sampling circuit samples the input signals during sample phases and generates a second output signal. The sample and hold circuit receives the first and second output signals, and generates a sampled output signal. The coarse sampling circuit provides the first output signal for a predefined time interval during the sample phases to reduce the effect of charge injection and charge sharing. The system uses bottom plate sampling to reduce charge injection caused by switches in the coarse sampling circuit. |
| US09571109B2 |
Voltage controlled oscillator runaway prevention
A feedback module for preventing voltage controlled oscillator (VCO) runaway in a phase locked loop (PLL) circuit can include a first, a second, and a third input to receive a first output signal from a PLL circuit, a reference signal, and a first control signal. The feedback module may also include a feedback circuit to generate a second control signal, the second control signal being coupled to an input of the PLL circuit, wherein the feedback circuit generates the second control signal by comparing a number of cycles of the first output signal to a first threshold, and a number of cycles of the reference signal to a second threshold. |
| US09571106B2 |
Delay locked loop circuit
A delay locked loop (DLL) circuit may include: a DLL unit suitable for generating an internal clock by delaying an external clock by a delay amount required for locking; a single-to-differential divider suitable for generating multi-phase divided clocks at a specific edge of the internal clock; and a phase correction unit suitable for correcting a phase error between the multi-phase divided clocks. |
| US09571105B2 |
System and method for an accuracy-enhanced DLL during a measure initialization mode
A clock generator having a delay locked loop and a delay control circuit. The delay locked loop receives an input clock signal and adjusts an adjustable delay circuit to generate an output clock signal that is synchronized with received input clock signal. The delay control circuit coupled to the delay locked loop generates a control signal to initialize the delay measure operation to adjust the adjustable delay circuit, after comparing the phase difference of the input clock signal and the output clock signal. The delay control circuit further generates a start measure control signal to start measuring a delay applied to the measurement signal propagating through the adjustable delay circuit, and generates a stop measure control signal to stop the delay measurement of the measurement signal. The delay adjustment of the delay locked loop is then adjusted to apply the delay measurement when synchronizing the input and output clock signals. |
| US09571104B1 |
Programmable body bias power supply
Methods and apparatus permit body biasing to be controlled for transistors of a logic device. By controlling the body biasing, transistor threshold voltages can be controlled—increased during standby modes of the logic device to reduce leakage current and decreased during active modes and to increase switching speed during the active modes. The change in the body biasing can be made relatively slowly to reduce wasted energy that would otherwise be dissipated as heat. In a method embodiment, the method includes obtaining first and second body bias slope parameters, each slope parameter defining, at least in part, a slope of a body bias voltage signal. The method includes charging a body of a transistor with a bias voltage signal per the first body bias slope parameter to lower a threshold voltage, and discharging the body per the second body bias slope parameter to decrease leakage current of the transistor. |
| US09571099B2 |
Electronic device comprising multiplexer and driving method thereof
A method for driving a semiconductor device capable of reducing an area of a multiplexer and reducing its power consumption is provided. In a method for operating a semiconductor device including a memory and a multiplexer, a first transistor is connected to a first capacitor, and a second transistor is connected to a second capacitor. In the multiplexer, in a third transistor, a source is connected to a first input terminal and a drain is connected to an output terminal and, in a fourth transistor, a source is connected to a second input terminal and a drain is connected to the output terminal. Further, a step of holding a first potential in a node to which the first transistor, the first capacitor, and a gate of the third transistor are connected and holding a second potential higher than the first potential in the node is included. |
| US09571098B2 |
Signal receiving circuits including termination resistance having adjustable resistance value, operating methods thereof, and storage devices therewith
A receiving circuit includes a termination resistance circuit and a resistance adjustment circuit. The termination resistance circuit is configured to receive a first differential signal via a first input terminal and a second differential signal via a second input terminal, and to be selectively connected to the first and second input terminals. The termination resistance circuit has an adjustable resistance value. The resistance adjustment circuit is configured to decrease the resistance value of the termination resistance circuit in response to a signal reception preparation command and connection of the termination resistance circuit to the first and second input terminals. |
| US09571095B2 |
Touch device with curved surface
A curved touch device is provided in the present invention including a back cover and a touch panel corresponding to the back cover, where at least one edge portion of the touch panel is a curve surface jointing with the one edge of the back cover. |
| US09571089B2 |
Built-in gate driver
A built-in gate driver includes a shift register provided in a non-display area of a panel, and configured to include first to gth stages outputting a scan signal, a clock supply line part configured to include m number of clock supply lines connected to the shift register, and a power supply line part configured to include n number of power supply lines connected to the shift register. At least one of the lines of the clock supply lines and the power supply lines are in a first side direction of the shift register, and the other at least one or more lines of the clock supply lines and the power supply lines are in a second side direction of the shift register. |
| US09571087B2 |
Method of operating a reverse conducting IGBT
According to an embodiment of a method, a semiconductor device is operated in a reverse biased unipolar mode before operating the semiconductor device in an off-state in a forward biased mode. The semiconductor device includes at least one floating parasitic region disposed outside a cell region of the device. |
| US09571081B2 |
Strobe signal generation circuit and semiconductor apparatus using the same
A strobe signal generation circuit may include: a counter to generate a first source signal and a second source signal by counting an external strobe signal; a delay to generate a first delayed signal and a second delayed signal by delaying the first source signal and the second source signal by a preset time; and a combination unit to generate internal strobe signals by selectively combining the first source signal, the second source signal, the first delayed signal, and the second delayed signal. |
| US09571079B2 |
Integrated circuit and signal monitoring method thereof
An integrated circuit includes a signal generating unit, a signal monitoring unit and a processing unit. The signal generating unit is configured to generate a control signal. The signal monitoring unit is configured to receive the control signal and accordingly output a monitor signal. The processing unit is configured to receive the monitor signal. The control signal is adjusted until the monitor signal is located within a preset range. A signal monitoring method used with the integrated circuit and a signal monitoring method used with a plurality of transistors are also provided. |
| US09571060B2 |
Transformer of the balanced-unbalanced type
A transformer of the balanced-unbalanced type includes a primary inductive circuit and a secondary inductive circuit housed inside an additional inductive winding connected in parallel to the terminals of the secondary circuit and inductively coupled with the primary circuit and the secondary circuit. |
| US09571055B2 |
Level adjustment device and method
A level of an input signal is detected according to a first following rate, and a first level signal indicating the detected level is generated. A level of the input signal is detected according to a second following rate lower than the first following rate, and a second level signal indicating the detected level is generated. One of the first and second level signals is selected based on a relation (e.g., ratio) between the first and second level signals so that a gain is determined based on the selected one of the first and second level signals. The level of the first input signal is adjusted according to the determined gain. For example, if the level variation is dominant, the gain adjustment suitable for the level variation can be performed, whereas, if the stable level is dominant, the gain adjustment suitable for the stable level can be performed. |
| US09571054B2 |
Systems and methods for dynamically adjusting volume based on media content
Systems and methods for dynamically adjusting a volume are provided. A presentation of a media asset is generated with a user equipment device at a first volume level. A user request to adjust a volume level of the media asset is received. Subject matter of the media asset currently being presented is determined. A volume adjustment rate is automatically set based on the determined subject matter. The volume level of the media asset is gradually adjusted from the first volume level to a second volume level at a rate corresponding to the volume adjustment rate based on the user request. |
| US09571049B2 |
Apparatus and methods for power amplifiers
Apparatus and methods for power amplifiers are disclosed. In one embodiment, a power amplifier circuit assembly includes a power amplifier and an impedance matching network. The impedance matching network is operatively associated with the power amplifier and is configured to provide a load line impedance to the power amplifier between about 6Ω and about 10Ω. The impedance matching network includes a fundamental matching circuit and one or more termination circuits, and the fundamental matching circuit and each of the of the one or more termination circuits include separate input terminals for coupling to an output of the power amplifier so as to allow the fundamental matching circuit and each of the one or more termination circuits to be separately tuned. |
| US09571044B1 |
RF power transistors with impedance matching circuits, and methods of manufacture thereof
Embodiments of an RF amplifier include a transistor with a control terminal and first and second current carrying terminals, and a shunt circuit coupled between the first current carrying terminal and a ground reference node. The shunt circuit includes a first shunt inductance, a second shunt inductance, and a shunt capacitor coupled in series. The second shunt inductance and the shunt capacitor form a series resonant circuit in proximity to a center operating frequency of the amplifier, and an RF cold point node is present between the first and second shunt inductances. The RF amplifier also includes a video bandwidth circuit coupled between the RF cold point node and the ground reference node. |
| US09571040B2 |
Audio amplifier and power supply voltage switching method
An audio amplifier is provided with: an amplifier circuit; a power supply circuit that generates a plurality of power supply voltages; a power supply relay that selects one of the power supply voltages as the power supply voltage supplied to the amplifier circuit; a switching condition determiner that determines whether the switching condition of the power supply relay is satisfied; a silent section detector that detects a silent section of the audio signal which is equal to or greater than the operation time of the power supply relay; and a switching instruction unit for providing the power supply relay with an instruction for switching the power supply voltage during the silent section when the switching condition is satisfied and the silent section is detected. |
| US09571038B1 |
Driver circuit for a power stage of a class-D amplifier
Embodiments of a driver circuit for a power stage of a class-D amplifier and a class-D amplifier are described. In one embodiment, a driver circuit for a power stage of a class-D amplifier includes serially connected transistor devices connected to a gate terminal of a power transistor of the power stage of the class-D amplifier, a voltage generator connected between a gate terminal of a first transistor device of the serially connected transistor devices and a source terminal of the power transistor, and a current multiplier connected between the gate terminal of the power transistor and one of a source terminal and a drain terminal of the first transistor device. The current multiplier is configured to produce an output current that is proportional to a current at the one of the source terminal and the drain terminal of the first transistor device. |
| US09571037B2 |
Diversity receiver front end system with impedance matching components
Diversity receiver front end system with impedance matching components. A receiving system can include a controller configured to selectively activate one or more of a plurality of paths between an input of the receiving system and an output of the receiving system. The receiving system can further include a plurality of amplifiers. Each one of the plurality of amplifiers can be disposed along a corresponding one of the plurality of paths and can be configured to amplify a signal received at the amplifier. The receiving system can further include a plurality of impedance matching components. Each one of the plurality of impedance matching components can be disposed along a corresponding one of the plurality of paths and can be configured to reduce at least one of an out-of-band noise figure or an out-of-band gain of the one of the plurality of paths. |
| US09571036B2 |
Heterodyne receiver structure, multi chip module, multi integrated circuit module, and method for processing a radio frequency signal
A heterodyne receiver structure comprises a frequency conversion block arranged to convert an incoming analog radio frequency (RF) signal to an analog intermediate frequency (IF) signal; a filter block arranged to filter said analog IF signal; and an analog-to-digital (AD) converter block arranged to convert said filtered analog IF signal to a digital signal, wherein the AD converter block (309) is arranged to convert the filtered analog IF signal to the digital signal by using a sampling frequency (fs) which is at least N times a maximum bandwidth of the filtered analog IF signal, wherein the frequency spectrum from zero to the sampling frequency is divided into N frequency zones of equal width, wherein N is an even positive number higher than two; the frequency conversion block (304) is arranged to convert the incoming analog RF signal to the analog IF signal such that the analog IF signal is located in any of the N/2-1 frequency zones having lowest frequency; and the filter block (306-308) is arranged to low pass the analog IF signal such that any disturbing signal located in a zone, which would have a mirror image after the AD conversion in the zone, in which the analog IF signal is located, is filtered away, wherein the heterodyne receiver structure further comprises a digital signal processing block (311) arranged to filter said digital signal. |
| US09571035B1 |
Alternating anti-parallel diode mixer structure
An apparatus includes a first circuit and a second circuit. The first circuit may be fabricated in a substrate and generally includes a first diode and a second diode (i) connected as anti-parallel diodes and (ii) physically adjacent to each other in the substrate. The second circuit may be fabricated in the substrate and generally includes a third diode and a fourth diode (i) connected as anti-parallel diodes and (ii) physically adjacent to each other in the substrate. The first circuit and the second circuit may be (a) connected in parallel, (b) physically adjacent to each other in the substrate and (c) configured to mix two input signals to generate an output signal. |
| US09571031B2 |
Mounting clips for panel installation
An exemplary mounting clip for removably attaching panels to a supporting structure comprises a base, spring locking clips, a lateral flange, a lever flange, and a spring bonding pad. The spring locking clips extend upwardly from the base. The lateral flange extends upwardly from a first side of the base. The lateral flange comprises a slot having an opening configured to receive at least a portion of one of the one or more panels. The lever flange extends outwardly from the lateral flange. The spring bonding flange extends downwardly from the lever flange. At least a portion of the first spring bonding flange comprises a serrated edge for gouging at least a portion of the one or more panels when the one or more panels are attached to the mounting clip to electrically and mechanically couple the one or more panels to the mounting clip. |
| US09571030B2 |
Universally mounted solar module
A solar module has a plurality of solar panels framed within a frame member having side frame members connected to end frame members. Each side frame member and end frame member have a groove and a channel, and side frame members also have an elongated flange that raises up the solar panel a distance to allow cooling air to pass under the solar panel. Framed solar panels are connected to lengthwise support members having top, bottom and side channels, such as T-slots. These channels allow for easy adjustment and compensates for variability in the installation process. Each solar panel is connected to the lengthwise support members by way of legs. To connect adjacent solar panels to the lengthwise support members, a pair of legs, one long leg and one short leg, are stacked on top of one another and fastened to the lengthwise support member. |
| US09571027B2 |
Power conversion device control device and power conversion device control method
Provided are a power conversion device control device and a power conversion device control method, which are capable of reducing harm to other electronic devices and electromagnetic noise due to a switching frequency compared to the related art. Carrier change patterns of the respective phases, which are defined by parameters of an average switching frequency, a spectral diffusion index, and a repetition frequency, are generated so that at least the carrier change pattern of one phase differs from the carrier change patterns of the other phases. Semiconductor switching elements are controlled as instructed by duty command values while the switching frequency is switched for each phase separately, from one frequency to another sequentially based on carriers output in patterns that follow the generated carrier change patterns. |
| US09571024B1 |
Multiphase motor generator system and control method thereof
A multiphase motor generator system includes a multiphase induction motor having a plurality of separate terminals, a multiphase inverter coupled to a DC link voltage source and the plurality of terminals of the multiphase induction motor, a plurality of current detectors configured to detect a plurality of currents that flow between the multiphase inverter and the plurality of terminals of the multiphase induction motor, and a controller coupled to the current detectors and the multiphase inverter, and configured to receive the detected currents and output a plurality of control voltages to the multiphase inverter. The controller includes a multiphase to direct-quadrature (dq) conversion unit, a dq equivalent unit, a dq to multiphase conversion unit, and a pulse-width-modulator (PWM) converter. |
| US09571022B2 |
Electrical generator with integrated hybrid rectification system comprising active and passive rectifiers connected in series
An electrical DC generation system is disclosed. According to one aspect, a system for electrical DC generation includes an electrical machine having multiple stator windings and multiple rectifiers for connection to portions of the stator windings. At least one active rectifier and at least one passive rectifier are connected in series to form a DC bus having a positive terminal and a negative terminal, where the positive terminal of the DC bus is connected to a positive output terminal of the electrical machine and where the negative terminal of the DC bus is connected to a negative output terminal of the electrical machine. The at least one active rectifier is used to control a current flowing through the DC bus and/or an output voltage of the electrical machine. |
| US09571015B2 |
DC permanent magnet synchronous motor
A DC permanent magnet synchronous motor, including: a motor body including a rotating shaft, a permanent rotor assembly, a stator assembly, and a housing assembly; a motor controller including a first microprocessor for drive control, an inverter circuit, and a detection circuit for detecting operating parameters of the motor; and an external control card including a second microprocessor for application control. The operating parameters of the motor are input into the first microprocessor by the detection circuit. The first microprocessor outputs a PWM signal to control the inverter circuit. An output end of the inverter circuit is connected to a coil winding. The external control card is disposed outside the motor body and is connected to the motor body via an electric wire. The second microprocessor and the first microprocessor are interconnected so that they can communicate. |
| US09571014B2 |
Drive circuit for an air bearing motor
The invention relates to a drive circuit for an electric motor having an aerodynamic bearing of the motor shaft, wherein the drive circuit comprises at least one storage means for storing electrical energy by which the electric motor can be fed with electrical energy on a failure of the supply voltage or DC-link voltage to obtain a minimum speed of the motor shaft required for the air support at least at times. |
| US09571011B2 |
Power generating element and power generation device
The present disclosure includes: a magnetostrictive plate including a magnetostrictive material; a yoke around which a coil is wound and which has two ends magnetically connected to a surface of the magnetostrictive plate; and a bias magnet that generates bias magnetic flux circulating from one of the two ends of the yoke to the other one of the two ends through the yoke. Here, the magnetostrictive plate is surface-bonded to a non-magnetic structural body. |
| US09571004B2 |
Multi-level power converter
This is a multi-level converter comprising at least one arm (B) formed of n stages (Et1, Et2, . . . , Etn) mounted in cascade. The first stage (Et1) comprises a single switching structure (Ce10) with four voltage levels and an ith stage (i lying between two and n) comprises i identical switching structures (Cei1, Cei2, . . . Ceii) with four voltage levels, mounted in series. Each switching structure with four voltage levels comprises a cell of floating capacitor type (T1, T2, T1′, T2′, C12), two basic switching cells (T3u, T3′u; T3l, T3′l) and a capacitive divider bridge (C9, C10, C11), the basic switching cells being connected between the voltage divider bridge and the cell of floating capacitor type. |
| US09571002B2 |
Voltage adjusting apparatus
In a voltage adjusting apparatus connected in series to a system, an output of an AC/DC converter thereof is reduced. The apparatus includes a second serial transformer having a primary side connected in series to a secondary side of a first serial transformer having a primary side connected in series between a power supply and a load and to a secondary side of a parallel transformer having a primary side connected in parallel between the power supply and the load; and a first AC/DC converter having an AC side connected to a secondary side of the second serial transformer. The first AC/DC converter has a switching element connected between an AC terminal and a DC terminal, an antiparallel diode, and a capacitor. |
| US09571001B2 |
Power conversion device, including serial switching element, that compensates for voltage fluctuations
Aspects of the invention include a step-up/step-down chopper unit, an inverter unit, a rectifier unit, first to third voltage detection means, and a drive control unit. Voltage regulation means of the drive control unit, in accordance with a detected voltage value detected by the voltage detection means, generates control signals for keeping the effective voltage value of a capacitor constant. In some aspects of the invention, the effective voltage value of the capacitor is controlled to be constant by the switching elements of the step-up/step-down chopper unit and inverter unit being driven by the control signals. The rectifier unit can suppress a surge voltage by causing energy stored in a inductor to be absorbed by storage elements when bidirectional switching elements are turned off. |
| US09571000B2 |
Method for controlling of a modular converter
A method for controlling a modular converter, having a plurality of M converter cells, including an active AC-to-DC converter operable in one of a plurality of modes; a DC-to-DC converter; a secondary side of said AC-to-DC converter and a primary side of said DC-to-DC converter connected in parallel with a DC-link capacitor, wherein the primary sides of the converter cells are connected in series, with a first converter cell connected to a line, preferably a medium voltage line, providing an AC line voltage an M-th converter cell connected to a ground; operated by a method placing the converters in bypassed, active or diode mode. |
| US09570999B2 |
DC-DC converter and DC-DC converter system thereof
The present disclosure discloses a DC-DC converter and a DC-DC converter system thereof. The DC-DC converter includes: a power conversion circuit; and a current detection circuit for detecting current flowing into or flowing out of the power conversion circuit, which includes: an inductor coupled to the power conversion circuit; a detection module including an induction winding and an impedance component electrically connected in series, the detection module and the inductor being connected in parallel; and an output module coupled to two ends of the impedance component for generating a current detection signal reflecting the current flowing into or flowing out of the power conversion circuit. |
| US09570997B2 |
Controlled power supply circuit
A power supply circuit for supplying power to at least two loads which are connected to said power supply circuit comprises a current source which can be operated in a clocked manner and has a control input for adjusting the power. At least two load strings are connected in parallel between a power supply connection, which is coupled to the current source, and a reference connection. Each load string has a load and charge storage means which is connected in parallel with the load. A switch is used to selectively switch the current path of the load string. A sensor having a sensor resistor which is connected in the current path of the load string is used to detect a current flowing through the connected load string. Furthermore, the controlled power supply circuit comprises a control circuit which is coupled to the switch and to the sensor of each load string for the purpose of activating each load string in a time-multiplexed manner. |
| US09570995B2 |
Magnetically coupled reactor and power converter
A magnetically coupled reactor includes a coupled core member, a first coil, and a second coil. The coupled core member includes a first core and a second core made of a magnetic material and disposed to face each other, a coil channel, and a sheet-like magnetic body by which a coupling portion between cores is put between the first core and the second core at an outer portion of the first and second cores. Each coil is wound around a leg through the coil channel in a lap winding manner such that the coils are overlapped on top of each other in the coil channel when seen in an axial direction. The sheet-like magnetic body extends from the coupling portion between coils into the coil channel and includes a portion arranged between coils located between the coils in the axial direction. |
| US09570990B2 |
Knee voltage detector
A knee voltage detector for a flyback converter is provided. The knee voltage detector comprises a delay unit, for delaying an auxiliary related voltage for a specific period, to generate a delay signal; a subtracting unit, for generating a subtraction signal according to the auxiliary related voltage and the delay signal; a comparing unit, for generating a sampling signal when the subtraction signal indicates that a voltage difference between the auxiliary related voltage and the delay signal is greater than a threshold; and a sample and hold unit, for sampling the delay signal to generate a knee voltage according to the sampling signal when the voltage difference between the auxiliary related voltage and the delay signal is greater than the threshold. |
| US09570988B2 |
Programming controller parameters through external terminals of a power converter
This relates to systems and processes for programming parameters of a controller of a power converter. In one example, a predetermined signal may be applied to the input or output terminals of the power converter to unlock the controller and cause the controller to enter a programming mode. While in the programming mode, one or more additional predetermined signals may be applied to the terminals of the power converter to program one or more parameters of the controller. Once the desired parameters have been programmed, another predetermined signal may be applied to the terminals of the power converter to cause the controller to exit the programming mode and enter a locked mode. The predetermined signals applied to the terminals of the power converter can include an ac or dc signal having a predetermined pattern of changes in frequency, amplitude, and/or magnitude that are applied for a fixed or variable duration. |
| US09570987B2 |
Method and apparatus for a voltage converter having bidirectional power conversion cells
The invention relates to a voltage converter (100), including: a plurality of two-way conversion cells (303), each cell comprising a primary circuit (307, Wp), and a secondary circuit (308, Ws) that is insulated from the primary circuit, wherein each circuit can be separately activated in order to supply an output voltage from the converter; and at least one control circuit (306) configured to, in a first operating mode, control the activated cells in order to transfer electrical energy from the primary circuit to the secondary circuit, and control the inactivated cells in order to transfer electrical energy from the secondary circuit to the primary circuit. |
| US09570983B2 |
Point of load regulator synchronization and phase offset
An electronic system includes a multiple POL regulators that supply a regulated voltage to a component within the electronic system. A phase spreading scheme may be implemented so that the POL regulators operate under various phases to reduce voltage noise, high input capacitance, and high radiated emissions. One phase spreading scheme includes a single POL regulator controlling phase spreading so that the other POL regulators operate under different phases. Another phase spreading scheme includes an upstream POL regulator determining a phase offset that may be passed to a downstream POL regulator so that the downstream POL regulator may operate under a different phase relative to the upstream POL regulator. |
| US09570982B2 |
DC voltage generation circuit and pulse generation circuit thereof
A pulse generation circuit, for outputting a pulse signal at an output terminal, comprises a PMOS, an NMOS and a logic circuit. The PMOS has a source coupled to a first reference voltage level, a drain coupled to the output terminal, and a gate coupled to a first gate control signal. The NMOS has a source coupled to a second reference voltage level, a drain coupled to the output terminal, and a gate coupled to a second gate control signal. The logic circuit generates the first gate control signal according to a control signal and a first logic signal, relating to the second gate control signal and a delay signal of the second gate control signal, and generates the second gate control signal according to the control signal and a second logic signal, relating to the first gate control signal and a delay signal of the first control signal. |
| US09570975B2 |
Method and apparatus for charge leakage compensation for charge pump with leaky capacitive load
An apparatus comprises a charge pump to receive a phase signal representing a result of a phase detection and to output a current flowing between an internal node of the charge pump and an output node of the charge pump; a capacitive load coupled to the output node; a current source controlled by a bias voltage to output a compensation current to the output node; a current sensor coupled between the internal node and the output node to sense the current; and a feedback network to generate the bias voltage in accordance with an output of the current sensor. A comparable method is also disclosed. |
| US09570972B2 |
CR snubber circuit
A CR snubber circuit capable of increasing a reduction effect of the effective inductance component and suppressing a ringing component generated at the time of switching the switching element is obtained. A first current path formed on one surface of the substrate and a second current path formed on the other surface, which is the opposite side of the one surface of the substrate, are opposed to each other with the substrate being sandwiched therebetween, and the capacitor 5 and the resistor 6 are arranged such that current flows in opposite directions in the first current path and the second current path, and a band elimination filter is formed by the capacitor 5, the resistor 6, and an effective inductance component obtained by coupling an inductance component included in the first current path and an inductance component included in the second current path. |
| US09570971B2 |
Determination of phase offsets in a power supply system having multiple switching converters
A controller for determining switching phases among switching elements of a power supply system having voltage converters, each comprising a switching element. The controller receives signals indicative of a contribution from each converter to a ripple voltage component of an input current of the converters, and ranks the converters. The controller calculates a switching phase offset that is to be applied for the switching element by: (i) calculating phase offsets of two highest ranked converters that would minimize an input voltage ripple caused by said two highest ranked converters, (ii) calculating a phase offset of a next-highest ranked converter that would minimize an input voltage ripple caused by said next-highest ranked converter and converters ranked higher than said next-highest converter; and (iii) repeating step (ii) for each converter in the ranking. The controller generates output signals defining the calculated switching phase offsets to be applied to the switching elements. |
| US09570968B1 |
Rotor of induction motor and method for manufacturing the same
A rotor of an induction motor includes a core assembly including a plurality of core discs formed with a plurality of slots; a plurality of conductive bars passing through the slots, each of the conductive bars having a first end and a second end respectively extended out of a first end surface and a second end surface of the core assembly; a first end ring assembly including a plurality of first conductive rings stacked on each other and penetrated by the first ends of the conductive bars; and a second end ring assembly including a plurality of second conductive rings stacked on each other and penetrated by the second ends of the conductive bars; wherein the first conductive rings and the second conductive rings are respectively welded to the first ends and the second ends of the conductive bars by electron beam welding or laser welding. |
| US09570967B2 |
Power generator
The present invention provides a power generator which can obtain efficient power generation by changing magnetic force acting on electromotive coils.The power generator is provided with a first permanent magnet member 1, a second permanent magnet member 2, and an electromotive coil member 3 arranged concentrically to have a telescoping structure and is configured so that power generation in the electromotive coil member 3 is induced by rotating the first permanent magnet member 1 or/and the second permanent magnet member 2. In the power generator, the first and second permanent magnet members 1 and 2 cooperate with each other to change the magnetic force and, thus, to obtain efficient power generation. |
| US09570966B2 |
Method for manufacturing a coil
A method for manufacturing a coil that is formed by winding a conductor in a loop shape and stacking loops of the conductor and that includes a slot placement portion to be placed in a slot of a stator core, and a coil end placement portion to be placed outside the slot. The method preferably involves a winding step, a protrusion forming step, a crank forming step, an opening step, and an arc forming step. The winding step forms a winding having slot placement and coil end placement portions. The protrusion forming step forms a protruding shape that protrudes in a radially outward direction of the winding. In the crank forming step a stepped portion. The opening step of forming the winding so that an interval between the pair of expected slot placement portions gradually increases. The arc forming step forms an arc-shaped portion curved in the stacking direction. |
| US09570965B2 |
Rotor coil for armature of rotating machine and production method thereof
A rotor coil for a revolving armature includes a strand coil that includes a part arranged in a core slot of the rotor and is composed of a plurality of element wires; and a solid coil welded to an end of the strand coil wherein the end of the strand coil and an end of the solid coil are welded by friction stir welding. A manufacturing method of a rotor coil includes the step of performing friction stir welding wherein the friction stir welding is performed for the butt joint with the end of the strand coil arranged in an advancing side defined by a rotation direction of a tool and with the solid coil arranged in a retreating side. |
| US09570961B2 |
Electronic motor system with common mode inductor
An electric motor system has a motor having motor windings and a motor housing. The motor is a variable speed permanent magnet motor configured to drive a load which is part of a residential or commercial machine. A motor control subsystem includes a power module electrically connected to the motor windings. A common mode inductor is electrically interposed between the motor control subsystem and the motor windings so as to present a high impedance obstacle to common mode transients and to reduce an electromagnetic interference effect of an inherent capacitance of each of the motor windings. The common mode inductor is an air core inductor located substantially within the motor housing, and takes the form of additional turns added to the end of each of the motor windings. |
| US09570960B2 |
Driving-device-integral-type rotary electric machine
A driving-device-integral-type rotary electric machine includes a driving device 8 having a first inverter 27a and a second inverter 27b, which can supply power to stator windings 5a and 5b of the rotary electric machine 2, and the first inverter 27a and the second inverter 27b are arranged and installed in a heat sink 19, in a state where the inverters are linearly symmetrical with respect to an axis X of the rotary electric machine 2, and the heat sink is configured in such a way that at least a heat capacity of a portion with respect to the first inverter 27a is roughly equal to a heat capacity of a portion with respect to the second inverter 27b. |
| US09570959B2 |
Electric motor with cooling of housing
An electric motor having a housing having a front and a rear end plate, a rotor that is mounted in the end plates, a stator, the core of which stator includes stator plates that are aligned with respect to each other in the axial direction of the rotor, and a housing cooling system that includes a tube that surrounds the stator core, the being concentrically surrounded by at least one cooling channel that is open towards the tube. |
| US09570953B2 |
Rotary electric machine
A rotary electric machine includes: a stator around which a coil is wound; a frame which fixes the stator; a rotor which faces the stator via a slight air gap; a shaft which is fixed to the rotor and is rotatably and removably supported via a bearing; and a bracket which supports the bearing inside a bearing box. The rotary electric machine includes: an insulating member which is mounted inside the bearing box of the bracket; a metal holder which is mounted inside the insulating member with a predetermined clearance with respect to an outer ring of the bearing, and supports the bearing; and a pressing body which is mounted between the side surface of the metal holder and the side surface of the outer ring of the bearing. |
| US09570950B2 |
Permanent magnet embedded rotary electric machine
A permanent magnet embedded rotary electric machine includes: permanent magnets 23 respectively accommodated in the magnet accommodation holes 25. In the magnet accommodation hole 25, a portion of each permanent magnet 23 corresponding to the radially outer side of the rotor iron core 21 is fixed to the rotor iron core 21, and a refrigerant passage 27 is formed, in a shaft direction of the rotor iron core 21, between the rotor iron core 21 and a portion of the permanent magnet 23 corresponding to the radially inner side of the rotor iron core 21. Protrusions 28 are provided, perpendicularly to a passing direction of a refrigerant, on an exposed portion 21a of the rotor iron core 21 in the refrigerant passage 27. |
| US09570948B2 |
Magnetic plate used for rotor core of motor and method for manufacturing magnetic plate
A magnet plate used for a rotor core of a motor, includes a magnetic pole portion being set between an outer peripheral edge of a body portion and a magnet slot and having a radial width being smaller than a radial sectional width of the permanent magnet, and a higher hardness portion being formed into a hook shape along an end corner of the magnet slot and have a smaller width than the radial sectional width of the permanent magnet. |
| US09570940B2 |
Backup battery systems for traffic cabinets
Backup battery systems for traffic cabinets that control traffic lights are provided herein. Backup battery systems include a controller operably coupled to 1 or more backup battery panels having rechargeable battery cells. Preferred systems can fit and operate entirely within the traffic cabinet. |
| US09570938B2 |
System, apparatus and method for uninterruptible power supply
An uninterruptible power supply device, and method of use thereof, including a multiple-input source AC converter for receiving an AC input voltage and a DC input voltage, an inverter including a combiner module for combining the input power sources, and an AC/AC switching transformer, the inverter being controlled by a controller to provide an output voltage signal, the controller configured to sample the input voltage signal, the switching signal current and the output voltage signal, and to control the switching transformer based thereon so as to render the output voltage signal sinusoidal. |
| US09570929B2 |
Field device with a battery unit
An apparatus comprising a battery unit and an electronics unit. The battery unit has a battery with a first and a second pole. The battery unit has at least a first, at least a second and at least a third electrical contact, wherein the first contact and the third contact are connected with the first pole, and wherein the second contact is connected with the second pole. The electronics unit has an input circuit with at least a first and at least a second electrical countercontact for receiving electrical energy from the battery unit essentially via the first and second contacts or essentially via the second and third contacts of the battery unit. |
| US09570928B2 |
Power supply system for wireless keyboard
A power supply system includes a charge module, a control module, and a discharge module. The charge module includes a charge circuit and a cell assembly. The control module includes a wireless unit. The discharge module includes a voltage increasing circuit coupled to the cell assembly and a voltage decreasing circuit coupled to the voltage increasing circuit. The charge module is coupled to a direct current power supply to charges the cell assembly. The cell assembly outputs a discharge voltage. The voltage increasing circuit is configured to increase the discharge voltage to a reference voltage. The voltage decreasing circuit decreases the increased discharge voltage to charge the wireless unit. |
| US09570924B2 |
Battery pack
A battery pack of one aspect of an embodiment of the present disclosure comprises a battery, a control unit, a pair of external terminals, a first current cut-off unit, and a second current cut-off unit. The control unit determines whether the first current cut-off unit and the second current cut-off unit are normal or abnormal when neither charge nor discharge of the battery is performed. When the first current cut-off unit and the second current cut-off unit are both normal, the control unit turns the first current cut-off unit and the second current cut-off unit to an energized state. When at least one of the first current cut-off unit and the second current cut-off unit is abnormal, the control unit turns the first current cut-off unit or the second current cut-off unit to a cut-off state. |
| US09570922B2 |
Charging method and electronic device
A charging method for an electronic device having a charging unit and a connection interface unit and the electronic device are provided. The connection interface unit is externally connected to a peripheral device. The charging method includes: detecting a signal level between the charging unit and the connection interface unit; and when a time period that the detected signal level keeps on a particular level is over a threshold, resetting the connection interface unit, so as to restart a charging function of the electronic device for the peripheral device. |
| US09570920B2 |
Feed unit and feed system
A feed unit includes: a power transmission section configured to perform power transmission with use of a magnetic field or an electronic field; a power limiting section provided on a power supply line from an external power source to the power transmission section; and an operation stop section configured to forcibly stop the power transmission. The operation stop section forcibly stops the power transmission when a voltage between an input and an output of the power limiting section exceeds a first threshold. The power limiting section forcibly interrupts power supply to the power transmission section when the voltage between the input and the output exceeds a second threshold that is larger than the first threshold. |
| US09570919B2 |
Power transmission device, power transmission method, and storage medium
A power transmission device includes a reception unit configured to receive, from each of a plurality of power reception devices as power transmission objects, identification information for identification of the power reception device, a device determination unit configured to determine, based on the identification information, whether each of the power reception devices is a registered device that has been registered beforehand, and a power transmission unit configured to transmit power to the registered device. |
| US09570918B2 |
Power transmitting system capable of power flashing and selective power distribution
A wireless power transfer system is disclosed that allows for directed power distribution. A power station that transmits the power can also transmit a distribution instruction that authorizes and/or prohibits various systems/components within a receiver device to receive power. A manager and power router within the receiver device route the power as directed by the distribution instruction. When multiple components/systems are authorized to receive the power, the receiver device can monitor power need and route as needed between authorized components/systems. In addition, the receiver device can act as a transmitter to wireless flash power to another device. The flash consists of bursting a large amount of power over a relatively short time. Several constraints, configurations, and considerations are required to perform this function. |
| US09570917B2 |
Light emitting element drive circuit
A drive circuit that drives a light emitting element coupled to a first output terminal of a differential circuit, the drive circuit includes: a dummy load provided at a second output terminal of the differential circuit, a resistor coupled between the first output terminal and the second output terminal, two transistors coupled to a voltage source and applying a current to the light emitting element and the dummy load, and a comparative amplifying circuit having a non-inverting input terminal coupled to a reference voltage, an inverting input terminal coupled to at least the first output terminal of the differential circuit via a resistor, and an output terminal coupled to gates of the two transistors. |
| US09570915B1 |
Direct integration of photovoltaic device into circuit board
Aspects relate to an integrated system that is electrically powered. The integrated system includes a circuit board and a photovoltaic device. The circuit board includes one or more on-board electronic components and an upper surface configured as a substrate. The photovoltaic device is integrally deposited on the upper surface of the circuit board and electrically connected to the one or more on-board electronic components, wherein the upper surface of the circuit board is a photovoltaic device substrate. |
| US09570914B2 |
Electric power retail management apparatus and electric power retail management method
An electric power retail management apparatus according to an embodiment includes a power generation source selection unit. The power generation source selection unit selects, as a power generation source for supplying electric power corresponding to an amount of electric power supplied to each of electric power consumers, one or more power generation sources of which one or more types are selected by each of the electric power consumers from among a plurality of power generation sources for each electric power consumer on the basis of an amount of electric power supplied from the power generation sources. |
| US09570912B2 |
AC/DC converter station operated in dependence of voltage of capacitor connected in series between AC/DC converter and AC network interface and a method of operating the same
The present invention relates to an AC/DC converter station for interconnection of a DC transmission line and an AC network, the AC/DC converter station including an AC/DC converter and a control system configured to control the AC/DC converter. The AC/DC converter station comprises a capacitor connected in series between the AC/DC converter and the AC network, and a voltage measurement device arranged to measure the voltage across the capacitor. The AC/DC converter further comprises a control system connected to the voltage measurement device and arranged to receive, from the voltage measurement device, a signal indicative of a measured voltage. The control system is arranged to perform the control of the AC/DC converter in dependence of the signal received from the voltage measurement device. The invention further relates to a method of operating an AC/DC converter station. |
| US09570911B2 |
Apparatus for controlling power supply
This specification relates to a power supply control apparatus. In order to solve problems of a power supply control only with respect to a preset time slot and difficulties in power supply to a plurality of consumers and metering of power supplied, which are the drawbacks of the related art electronic power meter, the power supply control apparatus can store or supply power according to a comparison result between a preset reference and a real-time pricing rate. Accordingly, electric charges, which are decided according to an amount of power used and reflect real-time rates thereto, can be saved and an appropriate power supply and an appropriate power reception of a consumer according to the real-time pricing rate can be allowed. |
| US09570910B2 |
Method and apparatus for storing energy
An energy storage apparatus for storing energy transmitted by a power transmission line includes an elastically deformable component and an actuator-generator. The actuator-generator is coupled to the elastically deformable component such that both mechanical and electrical actuation of the actuator-generator causes a generation of electrical energy by the actuator-generator via a release of tension in the elastically deformable component. |
| US09570908B2 |
Power management system
An apparatus is disclosed, which includes a system that includes loads, linear regulators, switches and a controller. The linear regulators supply power to the loads, and the controller is adapted to use the switches to selectively couple power sources to the linear regulators to regulate a collective power dissipation of linear regulators. |
| US09570904B2 |
Transmission bandwidth extender/category 6 surge protector
A surge protector for protecting telecommunications related equipment and other associated sensitive electrical components from over-voltage transient occurring on tip/ring conductors of telecommunication lines coupled thereto includes a printed circuit board and a plurality of surge protection circuits being mounted on the printed circuit board. Each of the plurality of surge protection circuits includes a first set of steering diodes and a second set of steering diodes. A common transient voltage clamping device has a first end connected to a first conductor lead and a second end connected to a second conductor lead so as to be shared by the plurality of surge protection circuits. A common pair of series-connected rectifier diodes has a first end also connected to the first conductor lead and a second end also connected to the second conductor lead so as to be shared by the plurality of surge protection circuits. |
| US09570903B2 |
Systems and methods for protecting power conversion systems under open and/or short circuit conditions
System and method are provided for protecting a power converter. The system includes a first comparator, and an off-time component. The first comparator is configured to receive a sensing signal and a first threshold signal and generate a first comparison signal based on at least information associated with the sensing signal and the first threshold signal, the power converter being associated with a switching frequency and further including a switch configured to affect the primary current. The off-time component is configured to receive the first comparison signal and generate an off-time signal based on at least information associated with the first comparison signal. The off-time component is further configured to, if the first comparison signal indicates the sensing signal to be larger than the first threshold signal in magnitude, generate the off-time signal to keep the switch to be turned off for at least a predetermined period of time. |
| US09570902B2 |
Power supply current monitoring device
A power supply current monitoring device is used for a load drive apparatus with two systems to drive a load. Each system includes a drive circuit connected in parallel with a battery, a capacitor connected between the battery and the drive circuit, and a relay connected between the drive circuit and a point at which power of the battery is divided between the systems. When overcurrent is detected once in one system, a repetitive monitoring process is performed. The monitoring process finally determines that the overcurrent actually occurs when a predetermined condition is satisfied after repeating a monitoring cycle in which an overcurrent time during which the overcurrent continues after the relay is turned ON is accumulated. The condition is satisfied when the monitoring cycle in which the overcurrent time reaches a predetermined threshold is repeated a predetermined consecutive number of times. |
| US09570895B2 |
Cable drag chain and cable drag chain assembly
A cable drag chain includes a number of first coupling members, a number of second coupling members engaging with the first coupling members, a number of latching members each including at least one mounting portion, a first fixing member and a second fixing member engaged with opposite ends of the first and second coupling members, and a sliding member slidably coupled to the first fixing member and including a latching portion. When the sliding member slides from the first fixing member to the second fixing member, the latching portion urges against the at least one mounting portion of each latching member to engage each latching member with corresponding first and second coupling members for holding a cable. |
| US09570893B2 |
Cutting method of flat wire, and cutting tool
A cutting method of the invention cuts a flat wire covered with a film, using a pair of first blades, and a second blade that is arranged between the pair of first blades. This cutting method includes a step of forming tapered cuts in an upper surface of the flat wire, by the pair of first blades cutting part way into the flat wire in a thickness direction, from the upper surface of the flat wire, and a step of cutting the flat wire by the second blade, between the two cuts, so as to form a chamfer on both side surfaces next to the upper surface of the flat wire. |
| US09570889B2 |
Spark plug
A spark plug with an insulator that includes: a first portion having a first inner diameter with a front end of a trunk portion of a metal terminal disposed therein; a second portion having a second inner diameter larger than the first inner diameter, and including a portion 1 mm or more forward of a rear end of the insulator; and a third portion disposed between the first portion and the second portion and having a third inner diameter larger than the first inner diameter and smaller than the second inner diameter. The trunk portion of the metal terminal includes: a front trunk portion and a rear trunk portion with a front end of the rear trunk portion positioned forward of a rear end of the third portion of the insulator, the rear trunk portion having an outer diameter larger than the outer diameter of the front trunk portion. |
| US09570885B2 |
Laser, passive optical network system, apparatus and wavelength control method
The present invention provide a laser, where the laser is divided into a laser region and a grating adjustment region through a first electrical isolation layer; the laser region is configured to generate optical signals, where the optical signals include an optical signal with a wavelength corresponding to a “0” signal and an optical signal with a wavelength corresponding to a “1” signal; the grating adjustment region is configured to adjust a wavelength of the grating adjustment region by controlling current of the grating adjustment region, so that the optical signal with the wavelength corresponding to the “1” signal of the laser region passes through the grating adjustment region, and the optical signal with the wavelength corresponding to the “0” signal of the laser region returns to the laser region, thereby implementing suppression to chirp of a directly modulated laser. |
| US09570876B2 |
Combined supercontinuum source
A supercontinuum optical pulse source provides a combined supercontinuum. The supercontinuum optical pulse source comprises one or more seed pulse sources, and first and second optical amplifiers arranged along first and second respective optical paths. The first and second optical amplifiers are configured to amplify one or more optical signals generated by said one or more seed pulse sources. The supercontinuum optical pulse source further comprises a first microstructured light-guiding member arranged along the first optical path and configured to generate supercontinuum light responsive to an optical signal propagating along said first optical path, and a second microstructured light-guiding member arranged along the second optical path and configured to generate supercontinuum light responsive to an optical signal propagating along said second optical path. The supercontinuum optical pulse source further comprises a supercontinuum-combining member to combine supercontinuum generated in at least the first and second microstructured light-guiding members to form a combined supercontinuum. The supercontinuum-combining member comprises an output fiber, wherein the output fiber comprises a silica-based multimode optical fiber supporting a plurality of spatial modes at one or more wavelengths of the combined supercontinuum. |
| US09570874B1 |
System for laser-based digital marking of objects with images or digital image projection with the laser beam shaped and amplified to have uniform irradiance distribution over the beam cross-section
An optical system including a laser apparatus, a spatial light modulator to receive a laser beam, an optical-conditioning system to capture a propagating diffracted beam of the optical pattern and to form at least one of a magnified version and a demagnified version of the optical pattern and to control a quality of the optical pattern, a uniformity maintaining optical amplifier to receive the laser beam output from the spatial light modulator and generate an amplified laser beam such that a final optical pattern is an amplified version of the optical pattern as generated by the spatial light modulator, the amplified laser beam having a substantially uniform amplification across the cross-section of the beam, and at least one of a time-bandwidth pulse duration control mechanism including at least one of a pulse stretching element and pulse compression element, and a frequency conversion device. |
| US09570871B2 |
Assembly of active cardiac electrical lead
An active bipolar cardiac electrical is assembled by coupling an inner conductor coil to a connector pin to form an inner conductor assembly. The inner conductor assembly is threaded through a connector insulator. An insulating tubing is placed over the inner coil. A proximal end of the insulating tubing is sleeved over the distal extension of the connector insulator. An outer conductor coil is coupled to a ring connector to form an outer conductor assembly. The inner conductor assembly is threaded through the outer conductor assembly. The ring connector is sleeved on the distal extension of the connector insulator and over the insulator tubing. A proximal seal is sleeved over a socket end of the connector pin. The proximal seal is seated on the proximal extension of the connector insulator. |
| US09570870B2 |
Method for producing terminal-equipped wire, terminal-equipped wire and terminal crimping device
The present invention aims to maximally reduce a projecting width of a projecting part formed on a terminal when the terminal is crimped to an exposed core part of an end part of a wire. To achieve this aim, a method for producing a terminal-equipped wire in which a crimping portion of a terminal is crimped to an exposed core part of an end part of a wire includes a) a step of arranging the exposed core part in the crimping portion, b) a step of sandwiching a part of the crimping portion between a lower die surface of a lower die and an upper die surface of an upper die and crimping the part of the crimping portion to the exposed core part, and c) a step of pressing an end part of the crimping portion protruding from the upper die surface from above. |
| US09570868B2 |
Signal distributor
A signal distributor for connecting a trunk line to branch lines, includes a plastic housing having a ceiling with passage openings, a printed circuit board with plug sockets for contacting a respective branch line. The plug sockets pass from the rear side of the ceiling through the passage openings during mounting of the circuit board. The outer wall of each plug socket and the outer wall of the passage opening edge are narrowly spaced so that, during casting of a housing cavity that receives the circuit board with a potting compound after installing the circuit board, no potting compound passes through the passage opening. The ceiling and the printed circuit board are made of a first plastic, which has low elongation at break, and the edge of the passage opening is made of a second plastic having an elasticity greater than the elongation at break of the first plastic. |
| US09570866B2 |
Jack assembly and portable electronic device with same
A jack assembly includes a jack element, an elastic element, and at least one latching portion. The jack element defines a jack opening configured for receiving an electronic element therein. The elastic element is mounted in a side of the jack element. The at least one latching portion protrudes on the elastic element and extends towards the jack opening. The at least one latching portion detachably latches the electronic element to the jack opening so as to secure the electronic element within the jack opening. |
| US09570864B1 |
Cable assembly having a device connection end with a light source
An electronic charging cable assembly is disclosed. The assembly includes a power connection end adapted to be electrically connected to an electrical power source and a device connection end adapted to be logically connected to an electronic device. The device connection end is electrically connected to the power connection end. A light source is located at the device connection end such that, when the power connection end is electrically connected to the electrical power source and the device connection end is not connected to the electronic device, the light source is illuminated and, when the power connection end is electrically connected to the electrical power source and the device connection end is connected to the electronic device, the light source is not illuminated. An exemplary electrical circuit used to provide this feature and a method of operating the electronic charging cable assembly are also disclosed. |
| US09570863B2 |
Grounding apparatus for a safety grounded tree
An artificial lighted tree is presented with power routed through the trunk of the tree and three-wire safety grounding. The tree is divided into sections for easy assembly, disassembly, and storage. The base of the tree is grounded through a three-prong safety grounded electrical cord and each section of the tree makes a ground connection with the base section as it is assembled to the artificial lighted tree. Electrical connections to power the lights may be made outside the trunk of the tree or through electrical connections within the tree. |
| US09570861B2 |
Electrical connector having flexible printed circuit board termination
An electrical connector includes a housing having a cavity and a wafer stack received in the cavity. The wafer stack includes a plurality of electrical wafers arranged parallel to each other within the cavity. Each wafer includes a dielectric body and a leadframe having plural conductors held in the dielectric body, the conductors having terminating contacts and mating contacts with leads therebetween. The terminating contacts are both horizontally staged and vertically staged and exposed in a pocket of the dielectric body for electrical termination. The mating contacts being exposed for electrical connection. The electrical connector includes a flex harness includes a plurality of FPCBs. The FPCBs are electrically connected to corresponding wafers. Each FPCB has a stepped mating interface with conductors along the stepped mating interface configured to be electrically connected to corresponding terminating contacts. |
| US09570859B2 |
Connector having a grounding member
A grounding member for maintaining a ground path in a cable connector includes, in one embodiment, an inner core configured to flex when a force is applied to the grounding member during operation of the connector. The grounding member further includes an outer conductive coating applied to the inner core. The outer conductive coating is configured to flex from a first state to a second state when a force is applied to the grounding member, so as to maintain a conductive path through the connector when the outer conductive coating flexes between the first and second states during operation of the connector. |
| US09570858B2 |
Connector and signal transmission method using same
Provided is a connector, including a plurality of contacts including both of ground contacts and signal contacts forming a differential signal pair. The impedance between the signal contacts and the ground contacts is matched. |
| US09570856B2 |
Communication module and communication module connector
A connector is configured of a plug connector and a receptacle connector. The plug connector has an insertion convex portion including: a first sidewall portion and a second sidewall portion that are in parallel with each other and a plurality of first connection terminals provided on the sidewall portions. The receptacle connector has an insertion concave portion to which the insertion convex portion is inserted and in which a plurality of second connection terminals that are contacted with the first connection terminals are provided. The respective inner side surfaces of the first sidewall portion and the second sidewall portion face each other across a space, and the plurality of first connection terminals are arranged on the respective outer side surfaces of the first sidewall portion and the second sidewall portion. |
| US09570855B2 |
Patch cord having a plug with contacts having a curved segment extending forwardly of a front edge of a printed circuit board
Patch cords are provided that include a communications cable that has at least first through fourth conductors and a plug that is attached to the cable. The plug includes a housing that receives the cable, a printed circuit board, first through fourth plug contacts, and first through fourth conductive paths that connect the first through fourth conductors to the respective first through fourth plug contacts. The first and second conductors, conductive paths, and plug contacts form a first differential transmission line, and the third and fourth conductors, conductive paths, and plug contacts form a second differential transmission line. Each of the first through fourth plug contacts has a first segment that extends longitudinally along a first surface of the printed circuit board, and the signal current injection point into the first segment of at least some of the first through fourth plug contacts is into middle portions of their respective first segments. |
| US09570852B2 |
Network plug
A network plug terminating a cable and configured for mating with a socket, and comprising a plurality of terminal contacts disposed along a forward face thereof, each of the terminal contacts terminating a respective one of a plurality of twisted pairs of conductors and such that when the plug is inserted into the socket each of the terminal contacts comes into contact with a respective tine in the socket. The plug further comprises a flexible tab comprising a tab release member and a slider connected to the tab release member. The slider is configured for movement along a length of the plug against a biasing force between a first position, wherein the flexible tab is in an unflexed state and engageable by a tab engaging feature in the socket and a second position wherein the flexible tab is in a flexed state and not engageable by the tab engaging feature. |
| US09570845B2 |
Connector having a continuity member operable in a radial direction
A connector for a coaxial cable. The connector, in one embodiment, includes a post, a coupler and a continuity member configured to produce a radially-directed biasing force. The continuity member provides an electrical connection between the post and the coupler |
| US09570843B2 |
Conductive structure and electronic assembly
A conductive structure, including a holder, a first magnetic element, and a conductive terminal, is provided. The holder has a receiving space. The first magnetic element is disposed in the holder. The conductive terminal is disposed in the receiving space corresponding to the first magnetic element. The conductive terminal is attracted to the first magnetic element and is hidden in the receiving space of the holder. When the conductive terminal is moved close to a conductive contact provided with a second magnetic element, the conductive terminal is attracted to the second magnetic element and moves from the receiving space to be in contact with and electrically connected with the conductive contact. An electronic assembly, including a housing and the conductive structure, is also provided. |
| US09570840B2 |
Corrosion-resistant terminal, wire with corrosion-resistant terminal and method for producing wire with corrosion-resistant terminal
The present invention concerns a corrosion-resistant terminal (10) before being crimped to an aluminum wire (40) in which a core (41) is covered with a coating (42) and the corrosion-resistant terminal (10) includes a wire barrel (31) to be crimped to the core (41) exposed by removing the coating (42), an insulation barrel (32) to be crimped to the coating (42), and an anticorrosive (50) applied in advance to a surface of the insulation barrel (32) to be held in contact with the coating (40). According to such a configuration, since the anticorrosive (50) is applied in advance to the surface of the insulation barrel (32) to be held in contact with the coating (42) of the aluminum wire (40), the anticorrosive 50 can be filled between the insulation barrel (32) and the coating (42) of the aluminum wire (40) when crimping is performed. |
| US09570837B2 |
Connector plug for insertion into a socket
A connector plug for insertion into a socket. The connector plug having a multipart housing comprising a front part and a rear part. The front part and the rear part are affixed to each other by means of being screwed together by a thread. The front part and the rear part a groove is formed respectively. The two grooves extend in axial direction at the outer circumference of the front part and the rear part and are aligned relative to each other when the front part and the rear part are screwed together completely. A slider can be housed by an adapter at the front part or the rear part whereby the slider has a crosspiece that engages with the groove and when the front part and the rear part are screwed together completely it can be displaced into a locked position. |
| US09570836B2 |
Connector, electrical connection box and connector manufacturing method
In a connector (23), a substantially L-shaped terminal fitting (21) is mounted in a connector housing (25). The terminal fitting (21) includes a first projecting portion (39) projecting backward from a back wall (38) of a receptacle (27) and a second projecting portion (41) bent downward substantially at a right angle from an end of the first projecting portion (39) and to be connected to a circuit board (14). The connector housing (25) is integrally formed with a protection wall (42) extending backward from the back wall (38) of the receptacle (27) and configured to cover the first and second projecting portions (39, 41) from an upper side, opposite lateral sides and a rear side with clearances formed between the protection wall (42) and both the first and second projecting portions (39, 41). |
| US09570835B2 |
Modular electrical wire housing unit
A wire housing unit has a shell body including a rear wall and two substantially parallel side walls extending orthogonally from the rear wall, a top plate removably attached to the top or bottom portion of the shell body closing the top or bottom, a bottom plate removably attached to the bottom or top portion of the shell body closing the bottom or top, a nailing fin disposed on the outside surface of one of the vertical side walls the fin substantially parallel with the rear wall of the shell body, and a modular contact junction block having a contact plug receptacle and terminals connecting house wires to a plugin outlet or switch assembly. The junction block is removably mounted to the inside surface of the top or bottom plates and in a position to accept contact plug-in of the outlet or switch assembly. |
| US09570834B2 |
Electrical socket with shutter and retainer arrangement
An electrical socket (1) comprising a carriage (4), the carriage comprising shutter portions, each shutter portion associated with a respective pin receiving opening (5a, 5b, 5c, 5d, 5e), and the socket comprising a retainer arrangement, and the shutter portions (4a, 4b), when in a closed condition are inhibited from moving to an open condition by the retainer arrangement, and wherein all the shutter portions are required to be in a released condition from the retainer arrangement in order to allow the shutter portions to be moved to an open condition to allow the plug pins to be inserted therein, and also wherein, if not all of the shutter portions are moved to a released condition, the shutter portions are inhibited from movement to the open condition by way of engagement with the retainer arrangement. |
| US09570833B2 |
Systems, apparatuses and methods for reducing access to medical device electrical connections
Systems, apparatuses and methods to enhance the safety of medical devices by reducing unwanted access to electrical connections on such medical devices are provided. A medical electrical connection safety mechanism includes at least a cover or other barrier (106) and a barrier securing mechanism to assist with closing the cover (106) when not in use. |
| US09570828B2 |
Compressible pin assembly having frictionlessly connected contact elements
A compressible contact pin. The contact pin includes a first contact element and a second contact element. A compressible member is coupled between the first contact element and the second contact element to compress when one or more external forces are applied between the first contact element and the second contact element. In addition, the compressible member maintains a separation distance between the first and second contact elements when no external forces are applied. An elastomeric connector is coupled between the first contact element and the second contact element. The elastomeric connector electrically couples the first contact element to the second contact element by deforming when the one or more external forces are applied between the first contact element and the second contact element. |
| US09570824B1 |
Reinforced right-angle type board edge connector
An information handling system (IHS) includes a reinforced edge card connector having a terminal block having a mounting surface attached to a surface of a first Printed Circuit Board (PCB). A connector housing has a connector opening aligned in parallel to the surface of the PCB to receive an edge of a second PCB. An upper row of upper conductors and a lower row of lower conductors are positioned in respective opposition to frictionally engage opposite sides of the edge of the second PCB, wherein the upper conductors are cantilevered pins. The connector housing exposes a bent portion of the cantilevered pins of the upper row of upper conductors. A flexible sheet is attached to an outward surface of the connector housing and to exposed surfaces of the upper row of upper conductors to create a binding force to multiple cantilevered pins to resist deformation. |
| US09570823B2 |
PCI-E connector cover and PCI-E connector module
A PCI-E connector cover includes a first, a second cover lateral sides, a plurality of bending arms, a cover top surface and a plurality of connecting posts. The first, the second cover lateral sides and the cover top surface are adapted to cover a first, a second connector lateral sides and a connector top surface of a PCI-E connector. The bending arms are connected to the first cover lateral side and lean against a first connector concave of the PCI-E connector so as to keep an interval between the first cover lateral side and the first connector concave. The cover top surface is connected to the first, the second cover lateral sides. The connecting posts are extended from the first and the second cover lateral sides to fix to a main board. A PCI-E connector module is further provided. |
| US09570822B2 |
Battery pack identification scheme for power tool systems
A method is provided for identifying a battery pack that is operably coupled to a battery charger. The method comprises: measuring voltage at a plurality of designated terminals of a first battery pack while the battery pack is coupled to the battery charger; determining how many of the designated terminals are connected to a reference voltage, such as battery positive; and identifying an attribute of the battery pack based on how many of the designated terminals are connected to the reference voltage. |
| US09570819B2 |
Coaxial connector with axial and radial contact between outer conductors
An assembly of mated coaxial connectors includes: a first connector with a first central conductor extension and a first outer conductor extension having a free end portion; and a second connector with a second central conductor extension and a second outer conductor extension having an outer body and an inner body with a gap therebetween. The first central conductor extension engages the second central conductor extension. The free end portion of the first outer conductor extension fits within the gap of the second outer conductor extension, such that the inner body applies radially outward pressure to the first outer conductor extension. At least one of the first outer conductor extension and the second outer conductor extension includes a flex member that deflects during axial engagement of the first and second connectors to apply axial pressure to the other of the first outer conductor extension and the second outer conductor extension. |
| US09570814B2 |
Structure, antenna, communication device and electronic component
A structure includes a first conductor pattern, a second conductor pattern, and a plurality of first openings and a plurality of lines. The first conductor pattern has a sheet shape. The second conductor pattern has a sheet shape and is opposite to the first conductor pattern, at least in part. The plurality of first openings are provided in the first conductor pattern. The lines are provided in the first openings, respectively, and one end thereof is connected to the first conductor pattern. Unit cells each containing the first opening and the line are repeatedly arranged. |
| US09570811B2 |
Device to reflect and transmit electromagnetic wave and antenna device
A device includes a dielectric, wherein a front and a back of the dielectric for reflecting and transmitting an electromagnetic wave are defined by a first surface and a second surface, the first or second surface forming a half mirror, the first surface has a height that changes in spiral as leaving from the second surface, and the second surface has a height that changes in spiral as leaving from the first surface. |
| US09570808B2 |
Coplanar antenna
A coplanar antenna including a conductive plane, wherein the length of the conductive plane along a first dimension is less than one-quarter of a wavelength of a resonant frequency; an insulating region within the conductive plane, wherein the insulating region is of a shape that outlines a conductive peninsula, wherein: the conductive peninsula is coupled to the conductive plane, the conductive peninsula is substantially coplanar to a major portion of the conductive plane, the conductive peninsula is operable to be electrically coupled to an electric feed circuit, and the conductive peninsula is operable to electrically couple a tunable inductance to the conductive plane after receiving a current from the electric feed circuit. |
| US09570806B1 |
Dual band transmitter
A dual band transmitter for transmitting a data signal in a first frequency or second frequency band. An antenna receives and sends data in one of the first and second frequency bands. An impedance matching network is connected in series with the antenna, and to a first node, and matches the impedance of the antenna to a predetermined value. The impedance matching network includes first and second antenna matching networks. The first antenna matching network is connected in series with the second matching network. In the first frequency band, the first antenna matching network matches the impedance of the antenna to the predetermined value, and in the second frequency band the second antenna matching network matches the impedance of the antenna to the predetermined value without affecting the first antenna matching network's matching in the first frequency band. |
| US09570805B2 |
Antenna structure and wireless communication device using the antenna structure
An antenna structure includes a main body, a first radiating body, and a second radiating body. The main body includes a feeding portion, a connecting portion, a first coupling portion, and a second coupling portion. The connecting portion is perpendicularly connected to the feeding portion. The first coupling portion and the second coupling portion are positioned at two opposite sides of the connecting portion. The first radiating body is configured to surround and resonate with the first coupling portion. The second radiating body is configured to surround and resonate with the second coupling portion. |
| US09570803B2 |
Multi-band antenna
An antenna which operates in a plurality of frequency bands includes a feeding point, a first conductor which is connected to the feeding point, and at least two second conductors which are branched from the first conductor, have a linear shape, and include open ends as ends on a side opposite to the first conductor. The open ends of the two second conductors face in almost the same direction substantially parallel to a side closest to the feeding point out of the sides of an antenna region. The two second conductors include a part at which the distance between the two conductors at a portion parallel to the side is a first distance, and another part at which the distance is a second distance shorter than the first distance, and are electromagnetically coupled at, at least the other part. |
| US09570799B2 |
Multiband monopole antenna apparatus with ground plane aperture
A monopole antenna coupled to a metallic ground plane includes apertures used to steer a radio frequency (RF) beam of the monopole. The apertures may have a length, width, and distance from the monopole based on the wavelength of the RF signal used to drive the monopole antenna. The aperture may be coupled to one or more selective devices, such as PIN diodes, which may short portions of a metallic ground plane near the aperture. The shorted portions of the metallic ground plane provide for steering of the monopole radiation pattern. A circuit board metallic ground plane may include multiple apertures to direct different RF signal frequencies from a single monopole antenna. Multiple monopole antennas may be implemented over a metallic ground plane within a wireless device, each monopole antenna with corresponding apertures. |
| US09570793B2 |
Directional coupler system
A circuit can include a tandem directional coupler comprising a first directional coupler and a second directional coupler connected in tandem. Each of the first and second directional couplers can have a first strip and a second strip. Port 3 of the first directional coupler can be connected to Port 1 of the second directional coupler. Port 4 of the first directional coupler can be connected to Port 2 of the second directional coupler. |
| US09570792B1 |
RF splitter/combiner system and method
A system/method describing a physically compact broadband radio frequency (RF) splitter/combiner is disclosed. The system and method provide an alternative to traditional broadband Wilkinson-style RF power splitter/combiners while reducing the overall size of the power divider/combiner to a significantly smaller form factor. The system and method utilize a serpentine impedance network (SIN) that incorporates a mirrored series of positive serpentine node (PSN) traces and negative serpentine node (NSN) traces. The PSN and NSN are coupled together within each isolated and mirrored SIN section with paired coupling traces (PCTs) located between the PSN and NSN traces that serve as both power transformers for the system and as an aid to impedance matching between the RF input port (RIP) and RF output ports (ROPs). The system is electrically symmetric and provides for power splitting and/or combining functionality between the RIP and ROPs. |
| US09570791B2 |
Ferrite circulator with reduced-height transformers
A circulator comprises a waveguide housing having a plurality of hollow waveguide arms that communicate with a central cavity, the waveguide housing having a height defined by a plurality of waveguide sidewalls between a waveguide floor and a waveguide ceiling. A ferrite element is disposed in the central cavity of the waveguide housing, with the ferrite element including a central portion. The ferrite element further includes a plurality of ferrite segments that each extend from the central portion and terminate at a distal end. A plurality of dielectric transformers each having an upper surface protrude into the waveguide arms away from the central cavity along the waveguide floor. The dielectric transformers have a height that is less than the height of the waveguide housing such that the upper surface of the transformers is separated from the waveguide ceiling by a gap. |
| US09570789B2 |
Transition structure between a rectangular coaxial microstructure and a cylindrical coaxial cable using step changes in center conductors thereof
Provided are coaxial transmission line microstructures formed by a sequential build process, and methods of forming such microstructures. The microstructures include a transition structure for transitioning between the coaxial transmission line and an electrical connector. The microstructures have particular applicability to devices for transmitting electromagnetic energy and other electronic signals. |
| US09570788B2 |
Dielectric waveguide combined with electrical cable
A communication cable includes one or more conductive elements surrounded by a dielectric sheath. The sheath member has a first dielectric constant value. A dielectric core member is placed longitudinally adjacent to and in contact with an outer surface of the sheath member. The core member has a second dielectric constant value that is higher than the first dielectric constant value. A cladding surrounds the sheath member and the dielectric core member. The cladding has a third dielectric constant value that is lower than the second dielectric constant value. A dielectric wave guide is formed by the dielectric core member surrounded by the sheath and the cladding. |
| US09570787B2 |
Hollow core coaxial cables and methods of making the same
Disclosed and claimed herein is a hollow core coaxial cable, having a dielectric capillary with an inside wall and an outside wall, an inner conductive layer on the inside wall of the hollow core coaxial cable and an outer conductive layer on the outside wall of the hollow core coaxial cable, the conductive layers may be patterned. Further disclosed is a method of making the hollow core coaxial cable. Further disclosed are holey fiber coaxial cables, having a holey fiber capillary having an inside wall and an outside wall, an inner conductive layer on the inside wall of the hollow core coaxial cable and an outer conductive layer on the outside wall of the hollow core coaxial cable, the conductive layers may be patterned. |
| US09570785B2 |
Systems and methods for ferrite circulator phase shifters
Systems and methods for ferrite circulator phase shifters are provided. In one embodiment, a multi-bit phase shifter comprises: a first switching circulator having a first port coupled to a first short circuit of a first phase length; and a second switching circulator coupled in series with the first switching circulator, the second switching circulator having a second port coupled to a second short circuit of a second phase length, the second switching circulator configured to switch in the second short circuit when the first short circuit is switched out by the first switching circulator, and switch out the second short circuit when the first short circuit is switched in by the first switching circulator. |
| US09570782B2 |
Storage element and method for the production thereof
A storage element for a solid electrolyte battery is provided. The storage element has a main member having a porous matrix of sintered ceramic particles in which particles that are made of a metal and/or a metal oxide and jointly form a redox couple are embedded. Along a preferred direction, the storage element has a certain concentration gradient of the particles made of the metal and/or the metal oxide and/or a certain gradient of a pore density and/or a pore size, thereby allowing the diffusion behavior of oxygen ions within the main member to be controlled and thus the charge and discharge kinetics, the life and the capacity of the battery to be improved. |
| US09570780B2 |
Rechargeable battery
A rechargeable battery including an electrode assembly including a first and second electrode, and a separator interposed between the first and second electrode; a case receiving the electrode assembly and having a top end opening; a cap assembly sealing the top end opening of the case, the cap assembly including a first terminal part and a second terminal part outwardly protruding; and a first collector plate received inside the case and electrically connecting the first electrode and the first terminal part, wherein the first collector plate includes a first lead part including a first electrode connection part connected to the first electrode, a first terminal connection part connected to the first terminal part, and a first connecting part electrically connecting the first electrode connection part and the first terminal connection part; and a first resin part on the first lead part, the first resin part covering the first connecting part. |
| US09570772B2 |
Power production apparatus and structure block system for water storage facility
The invention relates to an electric power generation system for a water storage tank and a storage structure system for a water storage tank wherein the electric power generation system for the water storage tank according to the invention comprises: a water storage tank for storing rainwater or water underground for a specific purpose; an electricity generation part for generating electricity by utilizing water stored in the water storage tank; a cooling part for cooling heat generated at the time of generating electricity by the electricity generation part; and a cooling water supply part for supplying the cooling part with the water stored in the water storage tank. Thereby, dispersed electricity generation facilities can be secured by utilizing open underground spaces of the water storage tank. |
| US09570767B2 |
Membrane humidifier for a fuel cell
The present disclosure provides a membrane humidifier for a fuel cell including: a case; a hollow fiber membrane module covering the case; a housing coupled to both ends of the hollow fiber membrane module; a plurality of hollow fiber membranes arranged in the case; and a hollow fiber membrane guide structure installed at one end or both ends of the hollow fiber membrane module and having a potting material layer formed therein to fix the plurality of hollow fiber membranes. |
| US09570766B2 |
Solid oxide fuel cell system
A solid oxide fuel cell system (10) comprises a solid oxide fuel cell stack (12) and a gas turbine engine (14). The solid oxide fuel cell stack (12) comprises a plurality of solid oxide fuel cells (16). The gas turbine engine (14) comprises a compressor (24) and a turbine (26). The compressor (24) supplies oxidant to the cathodes (22) of the fuel cells (16) via an oxidant ejector (60) and the oxidant ejector (60) supplies a portion of the unused oxidant from the cathodes (22) of the fuel cells (16) back to the cathodes (22) of the fuel cells (16) with the oxidant from the compressor (24). The fuel cell system (10) further comprises an additional compressor (64), an electric motor (66) arranged to drive the additional compressor (64), a cooler (70) and a recuperator (72). The compressor (24) supplies oxidant via the cooler (70) to the additional compressor (64) and the additional compressor (64) supplies oxidant to the oxidant ejector (60) via the recuperator (72). The solid oxide fuel cell stack (12) supplies exhaust gases to the turbine (26) and the turbine (26) supplies the exhaust gases through the recuperator (72) to heat the oxidant flowing through the recuperator (72). |
| US09570763B2 |
Hybrid bipolar plate for evaporatively cooled fuel cells
A fuel cell power plant (36) has vertical fuel cells (102) each sharing a half of a hybrid separator plate (100) which includes a solid fuel flow plate (105) having horizontal fuel flow channels (106) on one surface and coolant channels (108) on an upper portion of the opposite surface, bonded to a plain rear side of a porous, hydrophilic oxidant flow field plate (115) having vertical oxidant flow channels (118). Coolant permeates through the upper portion of the porous, hydrophilic oxidant flow field plates and enters the oxidant flow channels, where it evaporates as the water trickles downward through the oxidant flow field channels, thereby cooling the fuel cell. |
| US09570761B2 |
Non-PGM catalyst for ORR based on pyrolysed poly-complexes
Novel catalytic materials and novel methods of preparing M-N—C catalytic materials utilizing a sacrificial support approach and using inexpensive active polymers as the carbon and nitrogen source and readily available metal precursors are described. |
| US09570760B2 |
Fuel cell electrode assembly and method of making the same
According to at least one aspect of the present invention, a fuel cell electrode assembly is provided. In one embodiment, the fuel cell electrode assembly includes a substrate and a plurality of catalyst regions supported on the substrate to provide a passage way formed between the catalyst regions for passing fuel cell reactants, at least a portion of the plurality of catalyst regions including a number of atomic layers of catalyst metals. In certain instances, the number of atomic layers of catalyst metals is greater than zero and less than 300. In certain other instances, the number of atomic layers of catalyst metals is between 1 and 100. In yet certain other instances, the number of atomic layers of catalyst metals is between 1 and 20. |
| US09570756B2 |
Fuel cell electrode with nanostructured catalyst and dispersed catalyst sublayer
Polymer electrolyte membrane (PEM) fuel cell membrane electrode assemblies (MEA's) are provided which have nanostructured thin film (NSTF) catalyst electrodes and additionally a sublayer of dispersed catalyst situated between the NSTF catalyst and the PEM of the MEA. |
| US09570755B2 |
Production process for electrode catalyst for fuel cell and uses thereof
A production process for an electrode catalyst for a fuel cell, which includes a step (I) of mixing a nitrogen-containing organic substance, a transition metal compound and conductive particles with a solvent and a step (II) of calcining a mixture obtained in the step (I). |
| US09570751B2 |
Binder composition for secondary battery, anode including the binder composition, and lithium battery including the anode
A binder composition for a secondary battery, and an anode and a lithium battery that include the binder composition are disclosed. The binder composition may include: first nanoparticles having a glass transition temperature of about 60° C. or greater and an average particle diameter of about 100 nm or less; and a first polymer binder having a glass transition temperature of about 20° C. or less. |
| US09570749B2 |
Negative electrode, lithium battery including the same and method of manufacturing lithium battery
A negative electrode includes a current collector; and a negative active material layer on at least a surface of the current collector. The negative active material layer includes a porous matrix including lithium titanium oxide particles and metal nanoparticles that are alloyable with lithium. An average particle diameter of the lithium titanium oxide particles is at least two times greater than an average particle diameter of the metal nanoparticles. |
| US09570747B2 |
Secondary battery
There is provided a negative electrode for a secondary battery that can provide a secondary battery having high charge and discharge efficiency, and a high capacity retention rate in charge and discharge cycles. A negative electrode for a secondary battery according to this exemplary embodiment contains scale-like graphite, a fluorine-based resin, and an imide-based resin. A method for manufacturing a negative electrode for a secondary battery according to this exemplary embodiment includes applying a negative electrode slurry containing scale-like graphite, a fluorine-based resin, an imide-based resin, and a solvent for dissolving the fluorine-based resin and the imide-based resin to a negative electrode current collector; and heat-treating the negative electrode current collector at a temperature of 100° C. or more and 150° C. or less. |
| US09570745B2 |
Cathode active material and method for making the same
A method for making a cathode active material of a lithium ion battery, the cathode active material being represented by a chemical formula of Li[(Ni0.8Co0.1Mn0.1)1-xMox]O2, wherein 0 |
| US09570742B2 |
Positive electrode active material having improved safety and lifetime characteristics and lithium secondary battery comprising the same
Provided is a secondary battery comprising a positive electrode active material represented by the following Chemical Formula 1, Li{LiaMnxM1-a-x-yM′y}O2 [Chemical Formula 1] where 0 |
| US09570739B2 |
Composite positive active material, method of preparing the same, and positive electrode and lithium battery containing the material
A composite positive active material including an over-lithiated lithium transition metal oxide, the over-lithiated transition metal oxide including a compound represented by Formula 1 or Formula 3: [Formula 1] xLi2-yM″yMO3-(1-x)LiM′O2, [Formula 3] xLi2-yM″yMO3-x′LiM′O2-x″Li1+dM′″2-dO4, x+x′+x″=1, 0 |
| US09570734B2 |
Method for covering particles, especially a battery electrode material particles, and particles obtained with such method and a battery comprising such particle
A method for covering particles having a diameter of maximally 60 μm by means of atomic layer deposition, whereby said method comprises the step of fluidizing said particles in a fluidized bed reactor using a first reactant gas comprising a first reactant for substantially completely covering said particles with a monolayer of said first reactant. |
| US09570731B2 |
Rechargeable battery having insulation case
A rechargeable battery includes an electrode assembly including a first electrode, a second electrode, and a separator located between the first electrode and the second electrode; a case accommodating the electrode assembly; a cap plate sealing an opening of the case; and an insulation case located between the cap plate and the electrode assembly, the insulation case having a base and a side wall protruding from the base, the side wall including avoiding portions formed thereon. |
| US09570727B2 |
Battery separator with Z-direction stability
A battery separator is a microporous membrane. The membrane has a major volume of a thermoplastic polymer and a minor volume of an inert particulate filler. The filler is dispersed throughout the polymer. The membrane exhibits a maximum Z-direction compression of 95% of the original membrane thickness. Alternatively, the battery separator is a microporous membrane having a TMA compression curve with a first substantially horizontal slope between ambient temperature and 125° C., a second substantially horizontal slope at greater than 225° C. The curve of the first slope has a lower % compression than the curve of the second slope. The curve of the second slope is not less than 5% compression. The TMA compression curve is graphed so that the Y-axis represents % compression from original thickness and the X-axis represents temperature. |
| US09570723B2 |
Electric storage apparatus, and method for producing electric storage apparatus
According to an embodiment, an electric storage apparatus includes an electric storage device; an insulating member arranged in alignment with the electric storage device; and a sandwiching member made of metal configured to sandwich the insulating member with the electric storage device, wherein one of the insulating member and the sandwiching member includes a recess having an opening on a first surface and having a recess-side large-diameter portion, on the bottom side, with an inner circumference larger than the opening, and the other of the insulating member and the sandwiching member includes a projection-side large-diameter portion, on the distal end side, with an outer circumference larger than the opening, the projection-side large-diameter portion being arranged inside the recess-side large-diameter portion. |
| US09570722B2 |
Power storage device
Provided is a power storage device that enables a reduction in workload and work risk and thus allows a battery unit to be simply and safely removed from and attached to the power storage device.A power storage device (1) includes a plurality of battery unit receiving portions (70) for receiving battery units (100), a plurality of connectors (20) each floatable in the plane intersecting a direction (X) of insertion of the battery unit (100) into the battery unit receiving portion (70), an attaching object (80) to which the plurality of connectors (20) are attached, and connecting members (93) that connect between the plurality of connectors (20). |
| US09570712B2 |
Organic light-emitting module
An organic light-emitting module including a light-transmissive substrate, a light extracting structure, a first electrode, an organic light-emitting stack, a second electrode, and a transparent carrying board is provided. The light-transmissive substrate has an index of refraction greater than 1.5 and has a first surface and a second surface opposite to the first surface. The light extracting structure is disposed at the first surface. The first electrode is disposed on the second surface of the light-transmissive substrate. The organic light-emitting stack is disposed on the first electrode. The second electrode is disposed on the organic light-emitting stack. The transparent carrying board is connected with the light extracting structure. A minimum distance between the light extracting structure and the transparent carrying board is less than or equal to 125 μm. |
| US09570708B2 |
Organic light emitting display
An organic light emitting display including a back plane including an active area on which an image is displayed, and a bezel area outside the active area; a pixel array on the active area and configured to display the image; an encapsulation plate encapsulating the pixel array; a transparent adhesive film free of a moisture absorption filler, formed on the active area and disposed between the encapsulation plate and the back plane; and a dam including a sealant with a moisture absorption filler formed in the bezel area and adjoining the adhesive layer so as to limit moisture from penetrating into the pixel array. |
| US09570706B2 |
Organic light-emitting diode (OLED) display having a plurality of spacers covering one or more via holes
An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display comprises a display substrate, an encapsulation substrate, and at least one spacer. The display substrate includes a non-pixel area, wherein a plurality of via holes is formed in the non-pixel area. The encapsulation substrate is formed over the display substrate. The spacer is formed between the display substrate and the encapsulation substrate so as to maintain a gap therebetween, wherein the spacer at least partially covers at least one of a plurality of via holes. |
| US09570704B2 |
Display device
A display device includes a first substrate, a second substrate, a connecting element and a display medium. The first and second substrates are disposed opposite to each other, and the connecting element is disposed between the first and second substrates. An accommodating space is formed between the first substrate, the second substrate and the connecting element, and the display medium is disposed in the accommodating space. The connecting element has a first sealing layer, a second sealing layer and an adhesive layer. The first and second sealing layers are departed or partially connected. The second sealing layer is disposed adjacent to the accommodating space. The adhesive layer is disposed between the first and second sealing layers. The adhesive layer includes a water-resisting material. |
| US09570702B2 |
Display apparatus with a seal including a gas hole adjacent to a display portion and method of manufacturing the same
Provided are a display apparatus and a method of manufacturing the same. The display apparatus includes a display substrate arranged with a display portion including a display device; a sealing substrate disposed to face the display substrate; and a sealing portion that bonds the display substrate and the sealing substrate and surrounds the display portion. The sealing portion includes a first sealing portion that includes a sealing material and an insulating layer that includes at least one first opening; and a second sealing portion that is disposed outside the first sealing portion and includes at least one gas hole. |
| US09570700B2 |
Organic electroluminescent device and preparation method thereof including forming a cathode by combining zinc oxide, acetic acid and a phthalocyanine substance
Disclosed are an organic electroluminescent device and a preparation method thereof. The organic electroluminescent device is a top-emitting organic electroluminescent device having a reversed structure, and the preparation method is: dissolving zinc oxide with acetic acid to obtain a zinc oxide solution with a concentration of 0.3 g/ml-0.6 g/ml, adding a phthalocyanine substance in a mass of 1%-10% of the mass of the zinc oxide to obtain a mixture, spin-coating the mixture on a glass substrate (1) and then drying to obtain a cathode (2), and then preparing by vapor deposition, an electron injection layer (3), an electron transport layer (4), a luminescent layer (5), a hole transport layer (6), a hole injection layer (7) and an anode (8), successively, so as to obtain the organic electroluminescent device. |
| US09570699B2 |
Organic light emitting device having transparent electrode where conducting filaments formed and method of manufacturing the same
Provided is an organic light emitting device including a transparent electrode in which conducting filaments are formed and a method of manufacturing the same. In the organic light emitting device, a transparent electrode of an organic light emitting device is formed by using a resistance change material which has high transmittance with respect to light in a UV wavelength range and of which resistance state is to be changed from a high resistance state into a low resistance state due to conducting filaments, which current can flow through, formed in the material if a voltage exceeding a threshold voltage inherent in a material is applied to the material, so that it is possible to obtain the transparent electrode having high transmittance with respect to light in a UV wavelength range as well as light in a visible wavelength range generated by the organic light emitting device and having high conductivity. |
| US09570697B2 |
Light-emitting element
In the present invention, a light-emitting element operating at low driving voltage, consuming low power, emitting light with good color purity and manufactured in high yields can be obtained. A light-emitting element is disclosed with a configuration composed of a first layer containing a light-emitting material, a second layer, a third layer are formed sequentially over an anode to be interposed between the anode and a cathode in such a way that the third layer is formed to be in contact with the cathode. The second layer is made from n-type semiconductor, a mixture including that, or a mixture of an organic compound having a carrier transporting property and a material having a high electron donor property. The third layer is made from p-type semiconductor, a mixture including that, or a mixture of an organic compound having a carrier transporting property and a material having a high electron acceptor property. |
| US09570695B2 |
Carbon mixture ohmic contact for carbon nanotube transistor devices
A cobalt-carbon (Co—C) eutectic metal alloy ohmic contact for a radio-frequency (RF) carbon nanotube (CNT) field effect transistor (FET) device and a method of manufacturing same are disclosed. Embodiments of a method include providing a graphite crucible, placing Co and a C source within the graphite crucible, heating the graphite crucible containing the Co and C source such that the Co and C source combine with graphite from the graphite crucible to thereby form a Co—C eutectic metal alloy, and creating an ohmic contact by depositing the Co—C eutectic metal alloy directly on top surfaces of CNTs of a RF CNT FET device such that the Co—C eutectic metal alloy is in direct contact with the CNTs. The Co—C eutectic metal alloy ohmic contact formed in this manner is consistently stabile and uniform and functions as a high work function layer that also serves as an adhesion layer to the CNTs. |
| US09570694B2 |
All printed and transparent CNT TFT
A transparent thin film transistor is fabricated on a substrate by first depositing a concentrated aqueous metallic carbon nanotube solution using an inkjet printer on the substrate to form source and drain electrodes with a channel therebetween. The deposited metallic carbon nanotubes are then cleaned in mild acid; and the source and drain electrodes are cured by heating. An aqueous semiconducting carbon nanotube solution is then deposited in the channel on the substrate using an inkjet printer on the substrate to form a channel semiconductor. The channel semiconductor is then cleaned using a mild acid. A dielectric gate of ionic gel dielectric is then deposited on the cleaned channel semiconductor using an inkjet printer; and the ionic gel dielectric is cured by heating. |
| US09570687B2 |
Organic light-emitting diode
An organic light-emitting diode including a substrate; a first electrode on the substrate; a second electrode disposed opposite to the first electrode; and an emission layer between the first electrode and the second electrode, the emission layer including an anthracene-based compound represented by Formula 1, below, and a condensed cyclic compound represented by Formula 20, below: |
| US09570686B2 |
Organic light emitting diode with increased radical anion stability and applications thereof
An organic light emitting diode (OLED) having an improved service life and improved transport of negative charge carriers. The organic light emitting diode based on an organic semiconductor material in which the transport of negative charge carriers and the stability with respect to reduction are determined by azahetarylene/Lewis acid complex units. This leads to an improved service life of the emission layer, which firstly increases the service life of the component and avoids readjustment of the brightness during operation. Organic light emitting diodes are disclosed in which the position of the emission zone in the emitter layer and the color of the emission can be specifically influenced by azahetarylene/Lewis acid complex units. |
| US09570685B2 |
Method for forming pattern of organic electroluminescent element
A method includes forming an emission pattern on an organic electroluminescent element including an organic functional layer between two electrodes by light irradiation to the organic electroluminescent element, and controlling at least one of light intensity and exposure time as variable factors during the light irradiation based on reciprocity failure characteristics involving modification of a function of the organic functional layer due to the light irradiation. |
| US09570684B2 |
Method of doping 2-dimensional semiconductor and switching device
Example embodiments relate to methods of doping a 2-dimensional semiconductor. The method includes forming a semiconductor layer on a substrate, implanting ions into the semiconductor layer, forming a doped layer formed of a 2-dimensional semiconductor layer or an organic semiconductor layer on the semiconductor layer, and doping the doped layer by diffusing the ions of the semiconductor layer into the doped layer through annealing the substrate. |
| US09570676B2 |
Method for manufacturing the magnetic field sensor module
In the method of manufacturing a magnetoresistive sensor module, at first a composite arrangement out of a semiconductor substrate and a metal-insulator arrangement is provided, wherein a semiconductor circuit arrangement is integrated adjacent to a main surface of the semiconductor substrate into the same, wherein the metal-insulator arrangement is arranged on the main surface of the semiconductor substrate and comprises a structured metal sheet and insulation material at least partially surrounding the structured metal sheet, wherein the structured metal sheet is electrically connected to the semiconductor circuit arrangement. Then, a magnetoresistive sensor structure is applied onto a surface of the insulation material of the composite arrangement, and finally an electrical connection between the magnetoresistive sensor structure and the structured metal sheet is established, so that the magnetoresistive sensor structure is connected to the integrated circuit arrangement. |
| US09570675B2 |
Magnetoresistive structures, magnetic random-access memory devices including the same and methods of manufacturing the magnetoresistive structure
Magnetoresistive structures, magnetic random-access memory devices including the same, and methods of manufacturing the magnetoresistive structure, include a first magnetic layer having a magnetization direction that is fixed, a second magnetic layer corresponding to the first magnetic layer, wherein a magnetization direction of the second magnetic layer is changeable, and a magnetoresistance (MR) enhancing layer and an intermediate layer both between the first magnetic layer and the second magnetic layer. |
| US09570671B2 |
Magnetic memory device
According to one embodiment, a magnetic memory device includes a stacked structure including a magnetic element, a protective insulating film covering the stacked structure, and an interface layer provided at an interface between the stacked structure and the protective insulating film. The interface layer contains a predetermined element which is not contained in the magnetic element or the protective insulating film. |
| US09570667B2 |
Thermoelectric conversion material, thermoelectric conversion module using the same, and manufacturing method of the same
According to an embodiment, a thermoelectric conversion material is made of a polycrystalline material which is represented by a composition formula (1) shown below and has a MgAgAs type crystal structure. The polycrystalline material includes a MgAgAs type crystal grain having regions of different Ti concentrations. (AaTib)cDdXe Composition formula (1) wherein 0.2≦a≦0.7, 0.3≦b≦0.8, a+b=1, 0.93≦c≦1.08, and 0.93≦e≦1.08 hold when d=1; A is at least one element selected from the group consisting of Zr and Hf, D is at least one element selected from the group consisting of Ni, Co, and Fe, and X is at least one element selected from the group consisting of Sn and Sb. |
| US09570666B2 |
Silicon-based cooling package for light-emitting devices
Various embodiments of a thermal energy transfer apparatus that removes thermal energy from a light-emitting device are described. In one aspect, an apparatus comprises a non-metal base plate and a silicon-based cover element disposed on the base plate. The base plate is coated with a first electrically-conductive pattern that forms a first electrode. The base plate is further coated with a second electrically-conductive pattern that is electrically isolated from the first electrically-conductive pattern. The cover element holds the one or more light-emitting devices between the base plate and the cover element with at least a portion of a light-emitting surface of each of the one or more light-emitting devices exposed. The cover element is coated with a third electrically-conductive pattern that is in contact with the second electrically-conductive pattern to form a second electrode when the cover element is disposed on the base plate. |
| US09570665B2 |
Polyamide composition having high thermal conductivity
The present invention relates to a composition based on a polyamide matrix having a high thermal conductivity and comprising specific proportions of alumina and of graphite and also a flame-retardant system. This composition may in particular be used for producing components for lighting devices comprising light-emitting diodes. |
| US09570663B2 |
Pixel circuit, electro-optical device, and electronic apparatus
An electro-optical device formed on a semiconductor substrate, includes: a first transistor controlling a current level according to a voltage between a gate and a source; a second transistor electrically connected between a data line and the gate of the first transistor; a third transistor electrically connected between the gate and a drain of the first transistor; and a light-emitting element emitting light at a luminance according to the current level, in which one of a source and a drain of the second transistor and one of a source and a drain of the third transistor are formed by a common diffusion layer. |
| US09570658B2 |
Light emitting element
To provide a semiconductor light emitting element with high luminous efficiency, the light emitting element includes: a substrate; a semiconductor laminate placed above the substrate, the semiconductor laminate comprising a second semiconductor layer, an active layer and a first semiconductor layer laminated in this order from the substrate; and a first electrode and a second electrode placed between the substrate and the semiconductor laminate, wherein the semiconductor laminate is divided in a plurality of semiconductor blocks by a groove, wherein the first electrode includes protrusions that are provided in each of the plurality of semiconductor blocks and that penetrate the second semiconductor layer and the active layer to be connected to the first semiconductor layer, and wherein the second electrode is connected to the second semiconductor layer in each of the plurality of semiconductor blocks and has an external connector that is exposed on the bottom of the groove. |
| US09570657B2 |
LED that has bounding silicon-doped regions on either side of a strain release layer
A strain release layer adjoining the active layer in a blue LED is bounded on the bottom by a first relatively-highly silicon-doped region and is also bounded on the top by a second relatively-highly silicon-doped region. The second relatively-highly silicon-doped region is a sublayer of the active layer of the LED. The first relatively-highly silicon-doped region is a sublayer of the N-type layer of the LED. The first relatively-highly silicon-doped region is also separated from the remainder of the N-type layer by an intervening sublayer that is only lightly doped with silicon. The silicon doping profile promotes current spreading and high output power (lumens/watt). The LED has a low reverse leakage current and a high ESD breakdown voltage. The strain release layer has a concentration of indium that is between 5×1019 atoms/cm3 and 5×1020 atoms/cm3, and the first and second relatively-highly silicon-doped regions have silicon concentrations that exceed 1×1018 atoms/cm3. |
| US09570650B2 |
Collapsible photovoltaic module for a large-scale solar power plant
An elongate photovoltaic (PV) module for use in a solar energy conversion plant for the production of electricity from incident light, the PV-module comprising a top portion with a support panel (G) carrying on a front side a plurality of electrically connected PV cells (D), and a transparent protective layer (A) sealed to the support panel (G) so as to encapsulate the PV-cells (D) between the support panel (G) and the protective layer (A), wherein prior to installation of the PV-module at the deployment site a collapsible portion of the PV-module is configured to be collapsible in a longitudinal direction by folding and/or rolling, wherein the collapsible portion includes at least the top portion, wherein the PV-module further comprises one or more integrated ballast chambers (I) in a bottom portion of the PV-module arranged on a rear side of the support panel (G), wherein said integrated ballast chamber (I) after installation of the PV-module at the deployment site contains an amount of a ballasting material (H) with a weight sufficient to immobilize the PV-module on a supporting surface of the deployment site under predetermined characteristic climate conditions for the deployment site. |
| US09570638B2 |
Laser-transferred IBC solar cells
A laser processing system can be utilized to produce high-performance interdigitated back contact (IBC) solar cells. The laser processing system can be utilized to ablate, transfer material, and/or laser-dope or laser fire contacts. Laser ablation can be utilized to remove and pattern openings in a passivated or emitter layer. Laser transferring may then be utilized to transfer dopant and/or contact materials to the patterned openings, thereby forming an interdigitated finger pattern. The laser processing system may also be utilized to plate a conductive material on top of the transferred dopant or contact materials. |
| US09570635B2 |
Semiconductor device and patterning method for plated electrode thereof
The present invention discloses in detail a semiconductor device and a patterning method for the plated electrode thereof. By using the laser ablation method according to the prior art, the semiconductor substrate below the ARC is damaged by direct destructive burning. According to the present invention, an additional protection layer is inserted between the ARC and the semiconductor substrate. Then a laser is used for heating and liquefying the protection layer below the ARC, and thus separating the ARC from the liquefied protection layer underneath and forming pattered openings. Afterwards, by a plating process, nickel and copper can plated. |
| US09570633B2 |
Semiconductor package and manufacturing method thereof
A semiconductor package includes a substrate, at least one support, a cover, and a plate. The substrate has at least one light sensor or thermal sensor, a first surface, and a second surface opposite to the first surface. The light sensor or the thermal sensor is disposed on the first surface. The second surface has an opening to expose the light sensor (or the thermal sensor). The support is disposed on the first surface. The cover is disposed on the support, such that the cover is above the light sensor (or the thermal sensor) to form a first space between the cover and the light sensor (or the thermal sensor). The plate is placed on the second surface to cover the opening, such that a second space is formed between the plate and the light sensor (or the thermal sensor). |
| US09570630B2 |
Schottky diode structure
The invention provides a Schottky diode structure. An exemplary embodiment of a Schottky diode structure includes a semiconductor substrate having an active region. A first well region having a first conductive type is formed in the active region. A first doped region having the first conductive type is formed on the first well region. A first electrode is disposed on the active region, covering the first doped region. A second electrode is disposed on the active region, contacting to the first well region. A gate structure is disposed on the first well region. A second doped region, having a second conductive type opposite to the first conductive type, and is formed on the first well region. The gate structure and the second doped region are disposed between the first and second electrodes. |
| US09570627B2 |
Thim film transistor and method for making the same, thim film transistor panel and display device
A thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, an insulating layer, and a gate electrode. The drain electrode is spaced from the drain electrode. The semiconducting layer is electrically connected to the drain electrode and the source electrode. The semiconducting layer is an oxide semiconductor film comprising indium (In), cerium (Ce), zinc (Zn) and oxygen (O) elements, and a molar ratio of In, Ce, and Zn as In:Ce:Zn is in a range of 2:(0.5 to 2):1. The gate electrode is insulated from the semiconducting layer, the source electrode, and the drain electrode by the insulating layer. |
| US09570625B2 |
Semiconductor device
To provide a semiconductor device which can be miniaturized or highly integrated. To obtain a semiconductor device including an oxide semiconductor, which has favorable electrical characteristics. To provide a highly reliable semiconductor device including an oxide semiconductor, by suppression of a change in its electrical characteristics. The semiconductor device includes an island-like oxide semiconductor layer over an insulating surface; an insulating layer surrounding a side surface of the oxide semiconductor layer; a source electrode layer and a drain electrode layer in contact with top surfaces of the oxide semiconductor layer and the insulating layer; a gate electrode layer overlapping with the oxide semiconductor layer; and a gate insulating layer between the oxide semiconductor layer and the gate electrode layer. The source electrode layer and the drain electrode layer are provided above the top surface of the oxide semiconductor layer. The top surface of the insulating layer is planarized. |
| US09570624B2 |
Thin film transistor and method for fabricating the same
A thin film transistor includes a gate electrode, a gate insulating layer, an oxide semiconductor layer, an oxide buffer layer, a protective layer, and source and drain electrodes. The gate electrode is formed on a substrate. The gate insulating layer is formed on the substrate. The oxide semiconductor layer is formed on the gate insulating layer and includes a source, a channel and a drain region. The oxide buffer layer is formed on the oxide semiconductor layer, and has a carrier concentration lower than that of the oxide semiconductor layer. The protective layer is formed on the oxide buffer layer and the gate insulating layer, and has contact holes formed therein so that the oxide buffer layer in the source and drain regions are exposed therethrough. The source and drain electrodes are coupled with the oxide buffer layer in the source and drain regions through the contact holes. |
| US09570623B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device capable of high speed operation is provided. Further, a semiconductor device in which change in electric characteristics due to a short channel effect is hardly caused is provided. An oxide semiconductor having crystallinity is used for a semiconductor layer of a transistor. A channel formation region, a source region, and a drain region are formed in the semiconductor layer. The source region and the drain region are formed by self-aligned process in which one or more elements selected from Group 15 elements are added to the semiconductor layer with the use of a gate electrode as a mask. The source region and the drain region can have a wurtzite crystal structure. |
| US09570620B2 |
Manufacture method of dual gate oxide semiconductor TFT substrate and structure thereof
The present invention provides a manufacture method of an oxide semiconductor TFT substrate and a structure thereof. The manufacture method of the dual gate oxide semiconductor TFT substrate utilizes the halftone mask to implement one photo process, which cannot only accomplish the patterning to the oxide semiconductor layer but also obtain the oxide conductor layer (52′) with ion doping process, and the oxide conductor layer (52′) is employed as being the pixel electrode of the LCD to replace the ITO pixel electrode in prior art; the method manufactures the source (81), the drain (82) and the top gate (71) at the same time with one photo process; the method implements patterning process to the passivation layer (8) and the top gate isolation layer (32) together with one photo process, to reduce the number of the photo processes to nine for shortening the manufacture procedure, raising the production efficiency and lowering the production cost. |
| US09570619B2 |
Semiconductor device and manufacturing method thereof
As a display device has higher definition, the number of pixels is increased and thus, the number of gate lines and signal lines is increased. When the number of gate lines and signal lines is increased, it is difficult to mount IC chips including driver circuits for driving the gate lines and the signal lines by bonding or the like, whereby manufacturing cost is increased. A pixel portion and a driver circuit for driving the pixel portion are provided on the same substrate, and at least part of the driver circuit comprises a thin film transistor including an oxide semiconductor sandwiched between gate electrodes. A channel protective layer is provided between the oxide semiconductor and a gate electrode provided over the oxide semiconductor. The pixel portion and the driver circuit are provided on the same substrate, which leads to reduction of manufacturing cost. |
| US09570616B2 |
Display device and manufacturing method thereof
A display device includes: a first substrate; a gate electrode on the first substrate; a gate insulating layer on the gate electrode; a semiconductor layer on the gate insulating layer; a source electrode and a drain electrode spaced apart from each other on the semiconductor layer; a first passivation layer including a silicon nitride-based material and on the semiconductor layer, the source electrode, and the drain electrode; a second passivation layer including a silicon nitride-based material and on the first passivation layer; and a third passivation layer including a silicon nitride-based material and on the second passivation layer, where a content ratio of silicon in the first passivation layer is higher than a content ratio of silicon in the second passivation layer, and the content ratio of silicon in the second passivation layer is higher than a content ratio of silicon in the third passivation layer. |
| US09570614B2 |
Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation
Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin. |
| US09570613B2 |
Structure and formation method of FinFET device
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a fin structure over the semiconductor substrate. The semiconductor device structure also includes a gate stack over a portion of the fin structure, and the fin structure includes an intermediate portion under the gate stack and upper portions besides the intermediate portion. The semiconductor device structure further includes a contact layer over the fin structure. The contact layer includes a metal material, and the upper portions of the fin structure also include the metal material. |
| US09570608B2 |
Transistor, method for fabricating the same, and electronic device including the same
A semiconductor device includes a stressed substrate stressed by a first stress, a first stressed channel formed in the substrate and having the first stress, and a first strained gate electrode strained by a first strain generating element. A first strained gate electrode is formed over the first stressed channel, the first strained gate electrode including a first lattice-mismatched layer to induce a second stress to the first stressed channel. |
| US09570607B2 |
Field-effect semiconductor device having alternating n-type and p-type pillar regions arranged in an active area
In a field-effect semiconductor device, alternating first n-type and p-type pillar regions are arranged in the active area. The first n-type pillar regions are in Ohmic contact with the drain metallization. The first p-type pillar regions are in Ohmic contact with the source metallization. An integrated dopant concentration of the first n-type pillar regions substantially matches that of the first p-type pillar regions. A second p-type pillar region is in Ohmic contact with the source metallization, arranged in the peripheral area and has an integrated dopant concentration smaller than that of the first p-type pillar regions divided by a number of the first p-type pillar regions. A second n-type pillar region is arranged between the second p-type pillar region and the first p-type pillar regions, and has an integrated dopant concentration smaller than that of the first n-type pillar regions divided by a number of the first n-type pillar regions. |
| US09570600B2 |
Semiconductor structure and recess formation etch technique
A semiconductor structure has a first layer that includes a first semiconductor material and a second layer that includes a second semiconductor material. The first semiconductor material is selectively etchable over the second semiconductor material using a first etching process. The first layer is disposed over the second layer. A recess is disposed at least in the first layer. Also described is a method of forming a semiconductor structure that includes a recess. The method includes etching a region in a first layer using a first etching process. The first layer includes a first semiconductor material. The first etching process stops at a second layer beneath the first layer. The second layer includes a second semiconductor material. |
| US09570598B2 |
Method of forming a semiconductor structure
A semiconductor structure comprises a first layer. The first layer comprises a first III-V semiconductor material. The semiconductor structure also comprises a second layer over the first layer. The second layer comprises a second III-V semiconductor material different from the first III-V semiconductor material. The semiconductor structure further comprises an insulating layer over the second layer. The insulating layer is patterned to expose a portion of the first layer. The exposed portion of the first layer comprises electrons of the second layer. The semiconductor structure additionally comprises an intermetallic compound over the exposed portion of the first layer. |
| US09570597B2 |
High electron mobility transistor
According to example embodiments, a high electron mobility transistor (HEMT) includes a channel supply layer that induces a two-dimensional electron gas (2DEG) in a channel layer, a source electrode and a drain electrode that are at sides of the channel supply layer, a depletion-forming layer that is on the channel supply layer and contacts the source electrode, a gate insulating layer on the depletion-forming layer, and a gate electrode on the gate insulating layer. The depletion-forming layer forms a depletion region in the 2DEG. |
| US09570596B2 |
Super junction semiconductor device having a compensation structure
A super junction semiconductor device includes a semiconductor portion including mesa regions protruding from a base section and spatially separated in a lateral direction parallel to a first surface of the semiconductor portion, and a compensation structure covering at least sidewalls of the mesa regions. The compensation structure includes at least two first compensation layers of a first conductivity type, at least two second compensation layers of a complementary second conductivity type, and at least one interdiffusion layer between one of the first and one of the second compensation layers. |
| US09570594B2 |
Method for manufacturing semiconductor device
A semiconductor device which is miniaturized while favorable characteristics thereof are maintained is provided. In addition, the miniaturized semiconductor device is provided with a high yield. The semiconductor device has a structure including an oxide semiconductor film provided over a substrate having an insulating surface; a source electrode layer and a drain electrode layer which are provided in contact with side surfaces of the oxide semiconductor film and have a thickness larger than that of the oxide semiconductor film; a gate insulating film provided over the oxide semiconductor film, the source electrode layer, and the drain electrode layer; and a gate electrode layer provided in a depressed portion formed by a step between a top surface of the oxide semiconductor film and top surfaces of the source electrode layer and the drain electrode layer. |
| US09570585B2 |
Field effect transistor devices with buried well protection regions
A method of forming a transistor device includes providing a drift layer having a first conductivity type, forming a first region in the drift layer, the first region having a second conductivity type that is opposite the first conductivity type, forming a body layer on the drift layer including the first region, forming a source layer on the body layer, forming a trench in the source layer and the body layer above the first region and extending into the first region, forming a gate insulator on the inner sidewall of the trench, and forming a gate contact on the gate insulator. |
| US09570583B2 |
Recessing RMG metal gate stack for forming self-aligned contact
Embodiments of the present invention may include methods of incorporating an embedded etch barrier layer into the replacement metal gate layer of field effect transistors (FETs) having replacement metal gates, as well as the structure formed thereby. The embedded etch stop layer may be composed of embedded dopant atoms and may be formed using ion implantation. The embedded etch stop layer may make the removal of replacement metal gate layers easier and more controllable, providing horizontal surfaces and determined depths to serve as the base for gate cap formation. The gate cap may insulate the gate from adjacent self-aligned electrical contacts. |
| US09570581B2 |
Method of forming a self-aligned stack gate structure for use in a non-volatile memory array
A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate. |
| US09570576B2 |
Method for forming a semiconductor device having insulating parts or layers formed via anodic oxidation
A method for forming a semiconductor device includes forming an electrical structure at a main surface of a semiconductor substrate and carrying out an anodic oxidation of a back side surface region of a back side surface of the semiconductor substrate to form an oxide layer at the back side surface of the semiconductor substrate. |
| US09570575B1 |
Capacitor in strain relaxed buffer
Aspects include a semiconductor structure and fabrication method. A semiconductor structure may include alternating first and second crystalline layers and a capacitor. The capacitor may include a first terminal, a second terminal, and a dielectric. The first terminal may include a first central portion and first lobes extending laterally from the first central portion. The second terminal may include a second central portion and second lobes extending laterally from the second central portion. A portion of the second lobes may be fitted between consecutive first lobes. The fabrication method may include forming alternating first and second crystalline layers, forming a first trench, selectively etching the first crystalline layers within the first trench, depositing a dielectric in the first trench, filling the first trench with a metal, forming a second trench, etching the first and second crystalline layers within the second trench, and filling the second trench with a metal. |
| US09570573B1 |
Self-aligned gate tie-down contacts with selective etch stop liner
A method for forming a gate tie-down includes exposing an active area to form trench contact openings and forming trench contacts therein. An etch stop layer is formed on the trench contacts and on spacers of adjacent gate structures. An interlevel dielectric (ILD) is deposited to fill over the etch stop layer. The ILD and the etch stop layer on one side of the gate structure are opened up to provide an exposed etch stop layer portion. The gate structure is recessed to expose a gate conductor. The exposed etch stop layer portion is removed. A conductive material is deposited to provide a self-aligned contact down to the trench contact on the one side of the gate structure, to form a gate contact down to the gate conductor and to form a horizontal connection within the ILD over the active area between the gate conductor and the self-aligned contact. |
| US09570569B2 |
Selective thickening of PFET dielectric
A complementary metal-oxide semiconductor (CMOS) device and a method of fabricating a CMOS device are described. The method includes forming an interfacial layer in a trench on a substrate in both a p-channel field effect transistor (pFET) area of the CMOS device and an n-channel FET (nFET) area of the CMOS device, depositing a high-k dielectric on the interfacial layer in both the pFET area and the nFET area, selectively forming a first metal layer on the high-k dielectric in only the pFET area, and depositing a second metal layer on the first metal layer in the pFET area and on the high-k dielectric in the nFET area. The method also includes performing an anneal that increases a thickness of the interfacial layer in only the pFET area. |
| US09570567B1 |
Source and drain process for FinFET
A FinFET includes a substrate, a fin structure, a dielectric layer, a metal gate, two spacers, a source and a drain. The fin structure is disposed on the substrate. The dielectric layer is disposed on the fin structure and covers two opposite side surfaces of the fin structure. The dielectric layer includes two first portions protruding from the side surfaces of the fin structure, such that two opposite first recesses are formed in the dielectric layer. The metal gate is disposed on a second portion of the dielectric layer which is sandwiched between the first portions. The spacers are disposed on the first portions of the dielectric layer and protrude from the first portions of the dielectric layer respectively, such that two second recesses are formed in the spacers. The source and drain are respectively disposed in the first recesses and the second recesses on the substrate. |
| US09570565B2 |
Field effect power transistor metalization having a comb structure with contact fingers
A metalization of a field effect power transistor having lateral semiconductor layers on an insulator substrate or an intrinsically conducting or doped semiconductor substrate is provided. A metalization of source electrode contact areas, a metalization of drain electrode contact areas and a metalization of gate electrode contact areas are on a semiconductor surface of the semiconductor layers and have a plurality of metalization layers, between which insulation layers are arranged in a lateral direction. The metalization layers both for the source electrode metalization and for the drain electrode metalization have a comb structure with contact fingers. The contact fingers of the source electrode metalization and of the drain electrode metalization intermesh in a spaced-apart fashion and each contact finger has a contact finger foot and a contact finger tip. A width of the contact finger foot is greater than a width of the contact finger tip. |
| US09570558B2 |
Trap rich layer for semiconductor devices
An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer. |
| US09570557B2 |
Tilt implantation for STI formation in FinFET structures
Techniques in fabricating a fin field-effect transistor (FinFET) include providing a substrate having a fin structure and forming an isolation region having a top surface with a first surface profile. A dopant species is implanted using a tilt angle to edge portions of the top surface. The edge portions are then removed using an etch process. In this respect, the isolation region is modified to have a second surface profile based on an etching rate that is greater than an etching rate used at other portions of the top surface. The second surface profile has a step height that is smaller than a step height corresponding to the first surface profile. The tilt implantation and etching process can be performed before a gate structure is formed, after the gate structure is formed but before the fin structure is recessed, or after the fin structure is recessed. |
| US09570553B2 |
Semiconductor chip with integrated series resistances
A semiconductor chip has a semiconductor body with a bottom side and a top side arranged distant from the bottom side in a vertical direction, an active and a non-active transistor region, a drift region formed in the semiconductor body, a contact terminal for externally contacting the semiconductor chip, and a plurality of transistor cells formed in the semiconductor body. Each of the transistor cells has a first electrode. Each of a plurality of connection lines electrically connects another one of the first electrodes to the contact terminal pad at a connecting location of the respective connection line. Each of the connection lines has a resistance section that is formed of at least one of: a locally reduced cross-sectional area of the connection line section; and a locally increased specific resistance. Each of the connecting locations and each of the resistance sections is arranged in the non-active transistor region. |
| US09570551B1 |
Replacement III-V or germanium nanowires by unilateral confined epitaxial growth
A lateral epitaxial growth process is employed to facilitate the fabrication of a semiconductor structure including a stack of suspended III-V or germanium semiconductor nanowires that are substantially defect free. The lateral epitaxial growth process is unidirectional due to the use of masks to prevent epitaxial growth in both directions, which would create defects when the growth fronts merge. Stacked sacrificial material nanowires are first formed, then after masking and etching process to reveal a semiconductor seed layer, the sacrificial material nanowires are removed, and III-V compound semiconductor or germanium epitaxy is performed to fill the void previously occupied by the sacrificial material nanowires. |
| US09570549B2 |
Semiconductor nanocrystal and preparation method thereof
A semiconductor nanocrystal and a preparation method thereof, where the semiconductor nanocrystal include a bare semiconductor nanocrystal and a water molecule directly bound to the bare semiconductor nanocrystal. |
| US09570542B2 |
Semiconductor device including a vertical edge termination structure and method of manufacturing
A semiconductor device includes a semiconductor body with a first surface at a first side, a second surface opposite to the first surface and an edge surface connecting the first and second surfaces. An edge termination structure includes a glass structure and extends along the edge surface, at least from a plane coplanar with the first surface towards the second surface. A conductive structure extends parallel to the first surface and overlaps the glass structure at the first side. |
| US09570541B2 |
Semiconductor device and method of manufacturing the same
A semiconductor device is disclosed. In a surface layer of a front surface of an n-type semiconductor substrate, an anode layer is provided in an element activation portion and an annular p-type guard ring and an n-type high-concentration surface region are provided in an annular termination breakdown voltage region which surrounds the outer circumference of the anode layer. The impurity concentration of the n-type high-concentration surface region is higher than that of the semiconductor substrate and is lower than that of the p-type guard ring. The depth of the n-type high-concentration surface region is less than that of the guard ring. The anode layer and the guard ring are formed while the oxygen concentration of the semiconductor substrate is set to be equal to or more than 1×1016/cm3 and equal to or less than 1×1018/cm3. |
| US09570539B2 |
Integration techniques for MIM or MIP capacitors with flash memory and/or high-κ metal gate CMOS technology
Some embodiments of the present disclosure relate to an integrated circuit (IC) arranged on a semiconductor substrate, which includes a flash region, a capacitor region, and a logic region. An upper substrate surface of the capacitor region is recessed relative to respective upper substrate surfaces of the flash and logic regions, respectively. A capacitor, which includes a polysilicon bottom electrode, a conductive top electrode arranged over the polysilicon bottom electrode, and a capacitor dielectric separating the bottom and top electrodes; is disposed over the recessed upper substrate surface of the capacitor region. A flash memory cell is disposed over the upper substrate surface of the flash region. The flash memory cell includes a select gate having a planarized upper surface that is co-planar with a planarized upper surface of the top electrode of the capacitor. |
| US09570536B2 |
Method for forming an inductor structure with magnetic material
The methods for forming an inductor structure are provided. The method includes forming an oxide layer over a substrate, and the layer includes an opening. The method includes forming a magnetic material over the oxide layer and in the opening and forming a patterned photoresist layer over the magnetic material, wherein the patterned photoresist layer overlaps the opening. The method further includes performing an etching process on the magnetic material using the patterned photoresist as a mask. |
| US09570535B2 |
Integrated magnetics component
The present invention relates to an integrated magnetics component comprising a magnetically permeable core comprising a base member extending in a horizontal plane and first, second, third and fourth legs protruding substantially perpendicularly from the base member. First, second, third and fourth output inductor windings are wound around the first, second, third and fourth legs, respectively. A first input conductor of the integrated magnetics component has a first conductor axis and extends in-between the first, second, third and fourth legs to induce a first magnetic flux through a first flux path of the magnetically permeable core. A second input conductor of the integrated magnetics component has a second coil axis extending substantially perpendicularly to the first conductor axis to induce a second magnetic flux through a second flux path of the magnetically permeable core extending substantially orthogonally to the first flux path. Another aspect of the invention relates to a multiple-input isolated power converter comprising the integrated magnetics component. |
| US09570533B2 |
Organic light emitting diode array substrate, its manufacturing method, and display device
The present disclosure provides an organic light emitting diode array substrate and its manufacturing method, as well as a display device. The organic light emitting diode array substrate includes: gate lines, data lines, and a plurality of pixel units defined by the gate lines and the data lines. Each pixel unit comprises a first region which emits light and a second region which does not emit light. The first region is provided with an organic light emitting diode, and the second region is provided with a conductive unit which is electrically connected in parallel with the data line and created from the same layer from which a cathode of the organic light emitting diode is created. |
| US09570532B2 |
Pixel structure, display panel and display apparatus
The embodiment of the present invention provides a pixel structure, pixel unit structure, display panel and display apparatus, which is used to increase the electrical-optical efficiency of the display apparatus. The pixel structure includes an active matrix driving circuit, also includes at least two light emitting devices connected in series which are connected to the active matrix driving circuit, the light emitting devices compose the light emitting device group, and the active matrix driving circuit drives the light emitting devices to emit light. |
| US09570531B2 |
Power lines disposed in organic light emitting display device
An organic light emitting display device includes a substrate comprising a major surface; a display region and a peripheral region surrounding the display region when viewed in a viewing direction perpendicular to the major surface; an array of a plurality of pixels disposed in the display region; and a first power line extending from the peripheral region into the display region, the first power line being electrically connected to the array of pixels at a contact point in the display region. When viewed in the viewing direction, the first power line includes: a first extension extending from the peripheral region to the display region; and a second extension connected to the first extension; and a third extension connected to the second extension and extending from a location in the display region toward the peripheral region. |
| US09570528B2 |
Organic light-emitting display apparatus
An organic light-emitting display apparatus includes: a thin film transistor including an active layer, a gate electrode, a source electrode, a drain electrode, a first insulating layer, and a second insulating layer; a pad electrode comprising a first pad layer and a second pad layer on the first pad layer; a third insulating layer covering the source electrode and the drain electrode and an end portion of the pad electrode; a pixel electrode comprising a semi-transmissive electrically conductive layer at an opening in the third insulating layer; a protection layer between the pixel electrode and the first insulating layer; a fourth insulating layer having an opening at a location corresponding to the opening formed in the third insulating layer and covering the end portion of the pad electrode; an emission layer on the pixel electrode; and an opposing electrode on the emission layer. |
| US09570527B2 |
Organic light emitting diode display
An organic light emitting diode display may include a front display part including a plurality of front pixels formed on a substrate and realizing an image at a front and a side display part. A side pixel of the side display part may include: a plurality of thin film transistors formed on the substrate; a protective layer covering the plurality of thin film transistor and having an inclination groove that is oblique; a first electrode formed at the inclination groove of the protective layer; a pixel defining layer having an opening exposing the first electrode and formed on the protective layer; an organic emission layer formed on the first electrode and the pixel defining layer; and a second electrode covering the organic emission layer. |
| US09570525B2 |
Organic light emitting display apparatus and method of manufacturing the same
An organic light emitting display apparatus and a method of manufacturing the same are disclosed. The organic light emitting display apparatus includes, for example, a bus electrode, an insulating layer covering the bus electrode and having a bus electrode hole exposing at least a part of the bus electrode, a pixel electrode formed on the insulating layer and electrically coupled with the bus electrode, a pixel defining layer exposing a part of the pixel electrode and a part of the bus electrode, a first intermediate layer on the pixel defining layer and the pixel electrode, the first intermediate layer having a first opening to expose the part of the bus electrode, an emission layer disposed on the first intermediate layer, and an opposite electrode to correspond to the pixel electrode and the bus electrode and contacting the bus electrode through the first opening and the bus electrode hole. |
| US09570519B2 |
Organic light emitting display device with multi-organic layers
Discussed is an organic light emitting display device. The organic light emitting display device includes a substrate in which red, green, and blue pixel areas are defined, a first electrode and a hole transport layer formed on the substrate, first to third emitting material layers formed in each of the red, green, and blue pixel areas on the hole transport layer, a first electron transport layer formed on the first to third emitting material layers, a first charge generation layer formed on the first electron transport layer, a second charge generation layer formed on the first charge generation layer, fourth to sixth emitting material layers formed in each of the red, green, and blue pixel areas on the second charge generation layer, a second electron transport layer formed on the fourth to sixth emitting material layers, and a second electrode formed on the second electron transport layer. |
| US09570504B2 |
Method of manufacturing imaging apparatus having etched and planarized insulating layer
Provided is a method of manufacturing an imaging apparatus. The imaging apparatus is formed on a substrate and includes a pixel region and a peripheral circuit region that is arranged on a periphery of the pixel region. The method includes: forming an insulating layer in the pixel region and the peripheral circuit region; etching the insulating layer formed in the pixel region in a state in which the peripheral circuit region is protected; planarizing a surface of the insulating layer; and forming a waveguide in the pixel region. After the forming an insulating layer and before the etching the insulating layer, an average value of heights of a top surface of the insulating layer in the pixel region is larger than an average value of heights of a top surface of the insulating layer in the peripheral circuit region. |
| US09570503B2 |
Ridge structure for back side illuminated image sensor
Provided is an image sensor device. The image sensor device includes a substrate having a front side and a back side. The image sensor includes first and second radiation-detection devices that are disposed in the substrate. The first and second radiation-detection devices are operable to detect radiation waves that enter the substrate through the back side. The image sensor also includes an anti-reflective coating (ARC) layer. The ARC layer is disposed over the back side of the substrate. The ARC layer has first and second ridges that are disposed over the first and second radiation-detection devices, respectively. The first and second ridges each have a first refractive index value. The first and second ridges are separated by a substance having a second refractive index value that is less than the first refractive index value. |
| US09570502B2 |
Quantum dot optical devices with enhanced gain and sensitivity and methods of making same
Various embodiment include optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit having an array of conductive regions, and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions. Under another aspect, a film includes a network of fused nanocrystals, the nanocrystals having a core and an outer surface, wherein the core of at least a portion of the fused nanocrystals is in direct physical contact and electrical communication with the core of at least one adjacent fused nanocrystal, and wherein the film has substantially no defect states in the regions where the cores of the nanocrystals are fused. Additional devices and methods are described. |
| US09570501B2 |
Sold-state imaging device and electronic apparatus
A solid-state imaging device includes a semiconductor layer on which a plurality of pixels are arranged along a light-receiving surface being a main surface of the semiconductor layer, photoelectric conversion units provided for the respective pixels in the semiconductor layer, and a trench element isolation area formed by providing an insulating layer in a trench pattern formed on a light-receiving surface side of the semiconductor layer, the trench element isolation area being provided at a position displaced from a pixel boundary between the pixels. |
| US09570498B2 |
Image sensor device with first and second source followers and related methods
An image sensor device may include an array of image sensing pixels arranged in rows and columns. Each image sensing pixel may include an image sensing photodiode, a first source follower transistor coupled to the image sensing photodiode, and a switch coupled to the image sensing photodiode. Each image sensor device may include a second source follower transistor coupled to the switch, and a row selection transistor coupled to the first and second source follower transistors. |
| US09570497B2 |
Back side illuminated image sensor having isolated bonding pads
Provided is a method of fabricating an image sensor device. An exemplary includes forming a plurality of radiation-sensing regions in a substrate. The substrate has a front surface, a back surface, and a sidewall that extends from the front surface to the back surface. The exemplary method further includes forming an interconnect structure over the front surface of the substrate, removing a portion of the substrate to expose a metal interconnect layer of the interconnect structure, and forming a bonding pad on the interconnect structure in a manner so that the bonding pad is electrically coupled to the exposed metal interconnect layer and separated from the sidewall of the substrate. |
| US09570495B2 |
Solid-state imaging device with photoelectric conversion region that is not transparent
A solid-state imaging device includes a substrate and a photoelectric conversion region. The substrate has a charge accumulation region. The photoelectric conversion region is provided on the substrate. The photoelectric conversion region is configured to generate signal charges to be accumulated in the charge accumulation region. The photoelectric conversion region comprises a material that is not transparent. |
| US09570494B1 |
Method for forming a semiconductor image sensor device
In one embodiment, a method for forming a backside illuminated image sensor includes providing a region of semiconductor material having a first major surface and a second major surface configured to receive incident light. A pixel structure is formed within the region of semiconductor material adjacent the first major surface. Thereafter, a trench structure comprising a metal material is formed extending through the region of semiconductor material. A first surface of the trench structure is adjacent the first major surface of the region of semiconductor material and a second surface adjoining the second major surface of the region of semiconductor material. A first contact structure is electrically connected to one surface of the conductive trench structure and a second contact structure is electrically connected to an opposing second surface. |
| US09570492B2 |
Pixel array of image sensor and method of fabricating the same
A pixel array of an image sensor includes multiple red, green, blue and panchromatic pixels. The red, green and blue pixels are formed on a substrate during a first process. Planarization material is deposited to form the panchromatic pixels on the substrate and to form a planarization layer on the red, green and blue pixels during the same second process subsequent to the first process. The planarization material of the panchromatic pixels and the planarization layer is characterized in high transmittance and high aspect ratio. |
| US09570491B2 |
Dual-mode image sensor with a signal-separating color filter array, and method for same
A dual-mode image sensor with a signal-separating CFA includes a substrate including a plurality of photodiode regions and a plurality of tall spectral filters having a uniform first height and for transmitting a first electromagnetic wavelength range. Each of the tall spectral filters is disposed on the substrate and aligned with a respective photodiode region. The image sensor also includes a plurality of short spectral filters for transmitting one or more spectral bands within a second electromagnetic wavelength range. Each of the short spectral filters is disposed on the substrate and aligned with a respective photodiode region. The image sensor also includes a plurality of single-layer blocking filters for blocking the first electromagnetic wavelength range. Each single-layer blocking filter is disposed on a respective short spectral filter. Each single-layer blocking filter and its respective short spectral filter have a combined height substantially equal to the first height. |
| US09570490B2 |
Infrared transmission filter and imaging device
There are provided an infrared transmission filter, which is inexpensive, is capable of being sufficiently made lighter and thinner, has no incident angle dependency, and is excellent in permselectivity for infrared light, and an imaging device, which employs such an infrared transmission filter.An infrared transmission filter 10 includes an infrared transmission base material 1 selectively transmitting light in an infrared wavelength range; and a short wavelength side infrared absorbing film 2 formed on one side of the infrared transmission base material 1 and containing a near-infrared absorbent having an optical absorption edge on a short wavelength side of a transmission wavelength band of the infrared transmission base material. An imaging device includes the infrared transmission filter 10. |
| US09570487B2 |
Optical output photodetector
An optical output photodetector includes a substrate having a semiconductor surface and at least one optical photodetector element on the semiconductor surface. The optical photodetector element includes a plurality of integrated sensing regions which collectively provide a plurality of different absorbance spectra. The plurality of sensing regions includes a plurality of different semiconductor materials or a semiconductor material having a plurality of different dopants. The optical photodetector element can be configured as an array of optical photodetector elements and the dopants can be magnetic dopants. |
| US09570484B2 |
Semiconductor device and manufacturing method thereof
The semiconductor device includes a gate electrode over a substrate, a gate insulating layer over the gate electrode, an oxide semiconductor layer over the gate insulating layer, and a source electrode and a drain electrode over the oxide semiconductor layer. A length of part of an outer edge of the oxide semiconductor layer from an outer edge of the source electrode to an outer edge of the drain electrode is more than three times, preferably more than five times as long as a channel length of the semiconductor device. Further, oxygen is supplied from the gate insulating layer to the oxide semiconductor layer by heat treatment. In addition, an insulating layer is formed after the oxide semiconductor layer is selectively etched. |
| US09570481B2 |
Display substrate and method of manufacturing the same
A display substrate includes a first switching element, an organic layer disposed on the first switching element, a capping layer disposed on the organic layer and a cover electrode covering the first emission hole. The first switching element is electrically connected to a gate line extending in a first direction, a data line extending in a second direction crossing the first direction and the pixel electrode disposed adjacent to the data line. The capping layer includes a first emission hole. The cover electrode overlaps the gate line as a first width. The cover electrode overlaps the first switching element as a second width. The second width is smaller than the first width. |
| US09570476B2 |
Structure of crossing datalines and scanning lines and forming method in a display device
The array substrate comprises: data lines and scanning lines in an insulating crossing arrangement, where the data lines comprise first data lines and second data lines, the first data lines are arranged in a same layer with the scanning lines; the second data lines electrically connecting the first data lines via first via holes; first signal lines and common electrodes arranged on a substrate, where the first signal lines are arranged insulating from and in a same layer with the second data lines, the first signal line comprises a main portion and a bending portion which is arranged adjacently to the second data line; and a second insulating layer arranged between the first signal lines and the common electrodes, where second via holes are arranged in the second insulating layer, and the common electrodes are electrically connected to the first signal lines via the second via holes. |
| US09570470B2 |
Display device
A display device including an oxide semiconductor, a protective circuit and the like having appropriate structures and a small occupied area is necessary. The protective circuit is formed using a non-linear element which includes a gate insulating film covering a gate electrode; a first oxide semiconductor layer which is over the gate insulating layer and overlaps with the gate electrode; and a first wiring layer and a second wiring layer each of which is formed by stacking a conductive layer and a second oxide semiconductor layer and whose end portions are over the first oxide semiconductor layer and overlap with the gate electrode. The gate electrode of the non-linear element is connected to a scan line or a signal line, the first wiring layer or the second wiring layer of the non-linear element is directly connected to the gate electrode layer so as to apply potential of the gate electrode. |
| US09570469B2 |
Active-matrix substrate and liquid-crystal display device
An active matrix substrate (100) includes: a gate electrode (12) formed on a substrate; an oxide semiconductor layer (16); a source electrode (14); a drain electrode (15A); a drain connecting portion (15B) as an extended portion of the drain electrode (15A); a first transparent conductive layer (22, 24); and a second transparent conductive layer (26), wherein: the drain connecting portion (15B) is arranged close to the drain electrode (15A); and the drain electrode (15A) extends from a connecting portion thereof for connection with the oxide semiconductor layer (16), across an edge of the gate electrode (12), and to the drain connecting portion (15B), where a width of the drain electrode (15A) is smaller than a width of the drain connecting portion (15B). |
| US09570467B2 |
High voltage three-dimensional devices having dielectric liners
High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers. |
| US09570464B1 |
Method for manufacturing semiconductor device
According to one embodiment, a method for manufacturing a semiconductor device includes forming a first metal nitride film on a side surface of a hole extending in a stacking direction in a stacked body. The method includes forming a second metal nitride film on upper and lower surfaces of second layers and a side surface of the first metal nitride film. The method includes forming metal layers in first air gaps inside the second metal nitride film. The method includes removing the second layers and forming second air gaps between the metal layers. The method includes removing the first metal nitride film exposed to the second air gaps and dividing the first metal nitride film in the stacking direction. |
| US09570463B1 |
Multilevel memory stack structure with joint electrode having a collar portion and methods for manufacturing the same
A three-dimensional memory device including multiple stack structures can be formed with a joint region electrode, which is an electrode formed at a joint region located near the interface between an upper stack structure and a lower stack structure. A memory stack structure is formed through the multiple stack structures. The joint region electrode laterally surrounds a portion of the memory stack structure in proximity to the interface between different stack structures. The joint region electrode includes a layer portion having a thickness and a collar portion that laterally surrounds the memory stack structure and having a greater vertical extent than the thickness of the layer portion. The increased vertical extent of the collar portion with respect to the vertical extent of the layer portion provides enhanced control of a portion of a semiconductor channel in the memory stack structure located near the interface between different stack structures. |
| US09570462B2 |
Electronic device and method for manufacturing the same
A method for manufacturing an electronic device includes forming a first source layer including a trench, forming a first sacrificial layer in the trench, forming a first structure over the first source layer, wherein the first structure includes first material layers and second material layers which are alternately stacked over the each other, forming first openings passing through the first structure and extending to the first sacrificial layer, forming first channel layers in the first openings, forming a slit passing through the first structure and extending to the first sacrificial layer, forming a second opening by removing the first sacrificial layer through the slit, and forming a second source layer in the second opening, wherein the second source layer is coupled to the first channel layers. |
| US09570461B2 |
Method for manufacturing semiconductor memory device
According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a stacked body including a plurality of first layers and a plurality of second layers on a substrate. The method includes forming a first slit and a second slit simultaneously by dry-etching the stacked body. The first slit causes a part of the stacked body to have a comb-shaped pattern including a plurality of line parts isolated in a first direction and extending in a second direction. The second slit surrounds the comb-shaped pattern with a closed pattern. The method includes forming a hole in the line parts of the stacked body. The method includes forming a charge storage film and a semiconductor body in the hole. |
| US09570460B2 |
Spacer passivation for high-aspect ratio opening film removal and cleaning
A method of making a semiconductor device includes forming a stack of alternating layers of a first material and a second material over a substrate, etching the stack to form at least one opening in the stack such that a damaged region is located on a bottom surface of the at least one opening, forming a masking layer on a sidewall of the at least one opening while the bottom surface of the at least one opening is not covered by the masking layer, and further etching the bottom surface of the at least one opening remove the damaged region. |
| US09570458B2 |
Gate fringing effect based channel formation for semiconductor device
Methods and structures for forming semiconductor channels based on gate fringing effect are disclosed. In one embodiment, a NAND flash memory device comprises multiple NAND strings of memory transistors. Each memory transistor includes a charge trapping layer and a gate electrode formed on the charge trapping layer. The memory transistors are formed close to each other to form a channel between an adjacent pair of the memory transistors based on a gate fringing effect associated with the adjacent pair of the memory transistors. |
| US09570457B2 |
Method to control the common drain of a pair of control gates and to improve inter-layer dielectric (ILD) filling between the control gates
A semiconductor structure for a split gate flash memory cell device with a hard mask having an asymmetric profile is provided. A semiconductor substrate of the semiconductor structure includes a first source/drain region and a second source/drain region. A control gate and a memory gate, of the semiconductor structure, are spaced over the semiconductor substrate between the first and second source/drain regions. A charge trapping dielectric structure of the semiconductor structure is arranged between neighboring sidewalls of the memory gate and the control gate, and arranged under the memory gate. A hard mask of the semiconductor structure is arranged over the control gate and includes an asymmetric profile. The asymmetric profile tapers in height away from the memory gate. A method for manufacturing a pair of split gate flash memory cell devices with hard masks having an asymmetric profile is also provided. |
| US09570454B2 |
Structure with emedded EFS3 and FinFET device
The present disclosure relates to an integrated chip having a FinFET device and an embedded flash memory device, and a method of formation. In some embodiments, the integrated chip has a logic region and a memory region that is laterally separated from the logic region. The logic region has a first plurality of fins of semiconductor material protruding outward from a semiconductor substrate. A gate electrode is arranged over the first plurality of fins of semiconductor material. The memory region has a second plurality of fins of semiconductor material extending outward from the semiconductor substrate. An embedded flash memory cell is arranged onto the second plurality of fins of semiconductor material. The resulting integrated chip structure provides for good performance since it contains both a FinFET device and an embedded flash memory device. |
| US09570453B2 |
Memory device
Various embodiments provide memory devices and methods for forming the same. A substrate is provided, the substrate having one or more adjacent memory cells formed thereon. Each memory cell includes a gate structure, a control gate layer, and a first mask layer. A portion of the control gate layer is removed, to reduce a size of an exposed portion of the control gate layer in a direction parallel to a surface of the substrate. An electrical contact layer is formed on an exposed sidewall of the control gate layer and an exposed surface of the substrate. A barrier layer is formed on a sidewall of the memory cell. A conductive structure is formed on the substrate. The conductive structure has a significantly larger distance from control gate layer than from the gate structure, and the barrier layer forms an isolation layer between the conductive structure and the control gate layer. |
| US09570451B1 |
Method to form semiconductor devices
A method of forming semiconductor devices. First, a substrate is provided, and a first implant area and a second implant area are defined in a mask pattern. Subsequently, a resist layer on the substrate is patterned using the mask pattern to form a first opening exposing the first implant area and a second opening to expose the second implant area. After that, an ion implantation process including a partial shadowing ion implant is processed, wherein the second implant area is implanted by the partial shadowing ion implant to a predetermined concentration, and the first implant area is substantially not implanted by the partial shadowing ion implant. |
| US09570450B1 |
Hybrid logic and SRAM contacts
The method includes forming a first opening in a dielectric layer exposing a source drain region of an SRAM device and forming a second opening in the dielectric layer exposing a source drain region of a logic device, forming a third opening in the dielectric layer exposing a gate of the SRAM device and forming a fourth opening in the dielectric layer exposing a gate of the logic device, forming a first sidewall spacer in the third opening and forming a second sidewall spacer in the fourth opening, recessing a portion of the first sidewall spacer without recessing the second sidewall spacer, forming a strapped contact in the first and third openings, the strapped contact creates an electrical connection between the source drain region of the SRAM device and the gate of the SRAM device, the electrical connection is directly above a remaining portion of the first sidewall spacer. |
| US09570448B2 |
Semiconductor device and method for manufacturing the same
A method for manufacturing a semiconductor device includes forming a storage node hole passing through an upper support layer, a bowing prevention layer and an upper mold layer using a dry etching process, forming a lower electrode in the storage node hole, patterning the upper support layer and the bowing prevention layer to expose a portion of the upper mold layer, removing the upper mold layer and at least a portion of the bowing prevention layer using a first wet etching process, and sequentially forming a dielectric layer and an upper electrode that cover the lower electrode. An etch rate of the bowing prevention layer may be substantially equal to an etch rate of the upper support layer during the dry etching process. An etch rate of the bowing prevention layer may be higher than an etch rate of the upper support layer during the first wet etching process. |
| US09570444B2 |
CMOS transistors with identical active semiconductor region shapes
A disposable semiconductor material is deposited to form disposable semiconductor material portions on semiconductor fins. A first dielectric liner is deposited and patterned to form openings above a first set of disposable semiconductor material portions on a first semiconductor fin. The first set of disposable semiconductor material portions is replaced with a first set of active semiconductor regions by a combination of an etch and a selective epitaxy process that deposits a first semiconductor material. A second dielectric liner is deposited and patterned to form openings above the second set of disposable semiconductor material portions. The second set of disposable semiconductor material portions is replaced with a second set of active semiconductor regions employing another epitaxy process that deposits a second semiconductor material. The active semiconductor regions can have the same faceting profile irrespective of the semiconductor materials therein. |
| US09570440B2 |
Semiconductor device and driver circuit with an active device and isolation structure interconnected through a diode circuit, and method of manufacture thereof
Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a body region of the second conductivity type, and the diode circuit is connected between the isolation structure and the body region. The diode circuit may include one or more Schottky diodes and/or PN junction diodes. In further embodiments, the diode circuit may include one or more resistive networks in series and/or parallel with the Schottky and/or PN diode(s). |
| US09570439B2 |
Semiconductor device and semiconductor package
A semiconductor device includes a first semiconductor region of a first conductive type, a second semiconductor region of a second conductive type, a first electrode, a third semiconductor region of the second conductive type, a fourth semiconductor region of the first conductive type, and a conductive portion. The second semiconductor region is provided on the first semiconductor region. The first electrode is provided on the second semiconductor region. The third semiconductor region is provided on the first electrode. The fourth semiconductor region is provided on the third semiconductor region. The conductive portion is surrounded by the third semiconductor region and an intervening insulation portion and is electrically connected to the first electrode. |
| US09570438B1 |
Avalanche-rugged quasi-vertical HEMT
A semiconductor device includes a semiconductor body including first and second lateral surfaces. A first device region includes a drift region of a first conductivity type, and a drift current control region of a second conductivity type being spaced apart from the second lateral surface by the drift region. A second device region includes a barrier layer, and a buffer layer having a different band gap than the barrier layer so that a two-dimensional charge carrier gas channel arises along an interface between the buffer layer and the barrier layer. An electrically conductive substrate contact forms a low ohmic connection between the two-dimensional charge carrier gas channel and the drift region. A gate structure is configured to control a conduction state of the two-dimensional charge carrier gas. The drift current control region is configured to block a vertical current in the drift region via a space-charge region. |
| US09570435B2 |
Surge protection element and semiconductor device
A semiconductor element is provided which does not break down by avalanche current. A surge protection element includes: a semiconductor multi-layer comprising a nitride semiconductor; a first p-type semiconductor and a second p-type semiconductor which are disposed above the semiconductor multi-layer; a first electrode disposed above the first p-type semiconductor; and a second electrode disposed above the second p-type semiconductor. |
| US09570432B2 |
Semiconductor device with inverters having transistors formed in different active regions
A semiconductor device has a first and second transistors formed on an active region defined by an insulating region. The active region is divided into a first and second portions arranged in a first direction, and into a third and fourth portions interposed between the first portion and the second portion, and provided adjacent to each other in a second direction orthogonal to the first direction. The first transistor is provided in the first and third portions, and the second transistor is provided in the second and fourth portions. |
| US09570431B1 |
Semiconductor wafer for integrated packages
An embodiment semiconductor wafer includes a bottom semiconductor layer having a first doping concentration, a middle semiconductor layer over the bottom semiconductor layer, and a top semiconductor layer over the middle semiconductor layer. The middle semiconductor layer has a second doping concentration greater than the first doping concentration, and the top semiconductor layer has a third doping concentration less than the second doping concentration. A lateral surface of the bottom semiconductor layer is an external surface of the semiconductor wafer, and sidewalls of the bottom semiconductor layer, the middle semiconductor layer, and top semiconductor layer are substantially aligned. |
| US09570430B2 |
Articles including bonded metal structures and methods of preparing the same
Articles including bonded metal structures and methods of preparing the same are provided herein. In an embodiment, a method of preparing an article that includes bonded metal structures includes providing a first substrate. A first metal structure and a second metal structure are formed on the first substrate. The first metal structure and the second metal structure each include an exposed contact surface. A bond mask is formed over the contact surface of the first metal structure. A second substrate is bonded to the first substrate through the exposed contact surface of the second metal structure. The bond mask remains disposed over the exposed contact surface of the second metal structure during bonding of the second substrate to the first substrate. A wire is bonded to the exposed contact surface of the first metal structure. |
| US09570425B2 |
Display comprising ultra-small LEDs and method for manufacturing same
Provided are a display including a nano-scale LED and a method for manufacturing the same. In detail, nano-scale LED devices, each of which has a nano unit, are connected to nano-scale electrodes without electrical short-circuit to overcome a limitation in which it is difficult to allow nano-scale LED devices according to the related art to stand up and be coupled to electrodes and a limitation in which it is difficult to allow the nano-scale LED devices to be one-to-one coupled to the nano-scale electrodes different from each other, thereby realizing a display including the nano-scale LEDs. Also, the display may have superior light extraction efficiency and prevent defective pixels and the defect of the whole display due to the defects of the nano-scale LED devices, which may rarely occur, from occurring to minimize the defects of the display including the nano-scale LEDs and maintain its original function. |
| US09570424B2 |
Light source module and manufacturing method thereof, and backlight unit
A light source module includes a circuit board, light emitting diode chips mounted on the circuit board by flip-chip bonding or a surface mounting technology (SMT), and a diffusor covering the circuit board and the light emitting diode chips. |
| US09570423B2 |
Semiconductor package and method of manufacturing the semiconductor package
Embodiments of the inventive concept include a semiconductor package having a plurality of stacked semiconductor chips. A multi-layered substrate includes a central insulation layer, an upper wiring layer disposed on an upper surface of the central insulation layer, and a first lower wiring layer disposed on a lower surface of the central insulation layer. The stacked semiconductor chips are connected to the multi-layered substrate and/or each other using various means. The semiconductor package is capable of high performance operation, like a semiconductor package based on flip-ship bonding, and also meets the need for large capacity by overcoming a limitation caused by a single semiconductor chip. Embodiments of the inventive concept also include methods of manufacturing the semiconductor package. |
| US09570417B2 |
Chip bonding apparatus and chip bonding method
The chip bonding apparatus used in a chip bonding method includes a heating unit for heating an anisotropic conductive film at a first temperature; an attachment unit for attaching an integrated circuit chip to the anisotropic conductive film; a stage on which a substrate is seated; a chip transport unit for moving and aligning the integrated circuit chip that is attached to the anisotropic conductive film on the substrate; and a bonding head arranged above the stage to bond the integrated circuit chip that is attached to the anisotropic conductive film onto the substrate through thermo-compression of the integrated circuit chip onto the substrate at a second temperature that is lower than the first temperature. |
| US09570416B2 |
Stacked packaging improvements
A plurality of microelectronic assemblies are made by severing an in-process unit including an upper substrate and lower substrate with microelectronic elements disposed between the substrates. In a further embodiment, a lead frame is joined to a substrate so that the leads project from this substrate. Lead frame is joined to a further substrate with one or more microelectronic elements disposed between the substrates. |
| US09570414B2 |
Semiconductor device and method of manufacturing the semiconductor device
According to one embodiment, a first electrode is formed on a first face of a first semiconductor chip, and a second electrode and a protrusion are formed on a second face of a second semiconductor chip. The first semiconductor chip and the second semiconductor chip are spaced from one another by the protrusion in such a manner that the first face and the second face face each other. The first semiconductor chip and the second semiconductor chip are subject to reflow to be electrically connected to each other, and then the protrusion is cured at a temperature lower than a reflow temperature. |
| US09570413B2 |
Packages with solder ball revealed through laser
An integrated circuit structure includes a substrate, a PPI over the substrate, a solder region over and electrically coupled to a portion of the PPI, and a molding compound molding a lower portion of the solder region therein. A top surface of the molding compound is level with or lower than a maximum-diameter plane, wherein the maximum-diameter plane is parallel to a major surface of the substrate, and the maximum-diameter of the solder region is in the maximum-diameter plane. |
| US09570410B1 |
Methods of forming connector pad structures, interconnect structures, and structures thereof
Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed. |
| US09570406B2 |
Wafer level fan-out with electromagnetic shielding
The present disclosure integrates electromagnetic shielding into a wafer level fan-out packaging process. First, a mold wafer having multiple modules is provided. Each module includes a die with an I/O port and is surrounded by an inter-module area. A redistribution structure that includes a shield connected element coupled to the I/O port of each module is formed over a bottom surface of the mold wafer. The shield connected element extends laterally from the I/O port into the inter-module area for each module. Next, the mold wafer is sub-diced at each inter-module area to create a cavity. A portion of the shield connected element is then exposed through the bottom of each cavity. A shielding structure is formed over a top surface of the mold wafer and exposed faces of each cavity. The shielding structure is in contact with the shield connected element. |
| US09570404B2 |
Flexible Crss adjustment in a SGT MOSFET to smooth waveforms and to avoid EMI in DC-DC application
A semiconductor power device comprises a plurality of power transistor cells each having a trenched gate disposed in a gate trench wherein the trenched gate comprising a shielding bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed in a top portion of the gate trench by an inter-electrode insulation layer. At least one of the transistor cells includes the shielding bottom electrode functioning as a source-connecting shielding bottom electrode electrically connected to a source electrode of the semiconductor power device and at least one of the transistor cells having the shielding bottom electrode functioning as a gate-connecting shielding bottom electrode electrically connected to a gate metal of the semiconductor power device. |
| US09570399B2 |
Semiconductor package assembly with through silicon via interconnect
The invention provides a semiconductor package assembly with a TSV interconnect. The semiconductor package assembly includes a first semiconductor die mounted on a base. The first semiconductor die includes a semiconductor substrate. A first array of TSV interconnects and a second array of TSV interconnects are formed through the semiconductor substrate, wherein the first array and second array of TSV interconnects are separated by an interval region. A first ground TSV interconnect is disposed within the interval region. A second semiconductor die is mounted on the first semiconductor die, having a ground pad thereon. The first ground TSV interconnect of the first semiconductor die has a first terminal coupled to the ground pad of the second semiconductor die and a second terminal coupled to an interconnection structure disposed on a front side of the semiconductor substrate. |
| US09570397B1 |
Local interconnect structure including non-eroded contact via trenches
A local interconnect structure includes a substrate having a dielectric layer and at least one semiconductor contact structure embedded in the dielectric layer. An electrically conductive material is deposited in a non-eroded contact trench that defines at least one electrically conducive contact via. The contact via extends from a first end that is flush with an upper surface of the dielectric layer to a second end that contacts the at one semiconductor contact structure. A local conductive material layer is formed in the dielectric layer and contacts the first end of the contact via. The non-eroded contact trench includes sharp upper corners formed at approximately ninety degrees with respect to the first end of the contact via. |
| US09570395B1 |
Semiconductor device having buried power rail
A semiconductor device includes: a substrate; a power rail on the substrate; an active layer on the substrate and at same layer as the power rail; and a contact electrically connecting the power rail to the active layer. The active layer includes source/drain terminals. |
| US09570392B2 |
Memory device and method for manufacturing the same
According to one embodiment, a memory device includes a conductive member and a stacked body provided on the conductive member. The stacked body includes a plurality of first interconnections being stacked to be separated from each other, a memory cell connected with one of the first interconnections, a plurality of contact plugs, an insulating member. Each of the contact plugs connects each of the first interconnections with an upper surface of the conductive member. One of the contact plugs includes an upper part, and a lower part. The lower part is provided between the upper part and the conductive member. The lower part includes a first portion and a second portion. The first portion is connected with one of the first interconnections. The second portion is connected with the conductive member. The insulating member is provided between the first portion and the second portion. |
| US09570390B2 |
Semiconductor device with integrated hot plate and recessed substrate and method of production
The semiconductor device comprises a substrate of semiconductor material, a dielectric layer on the substrate, an electrically conductive contact pad arranged in the dielectric layer, a hot plate arranged in the dielectric layer, a recess of the substrate at the location of the hot plate, and an integrated circuit, which operates the hot plate. An electrically conductive layer is arranged on a side of the substrate opposite the dielectric layer. The substrate is provided with a via hole above the contact pad, and an electrically conductive material connecting the electrically conductive layer with the contact pad is applied in the via hole. The recess and the via hole are formed in the same process step. |
| US09570384B2 |
Semiconductor device
A semiconductor device can include a substrate and a trace layer positioned in proximity to the substrate and including a trace for supplying an electrical connection to the semiconductor device. Conductive layers can be positioned in proximity to the trace layer and form a bond pad. A non-conductive thin film layer can be positioned between the trace layer and the conductive layers. The thin film layer can include a via to enable the electrical connection from the trace to the bond pad. A portion of the trace between the substrate and the plurality of conductive layers can have a beveled edge. |
| US09570379B2 |
Power semiconductor package with integrated heat spreader and partially etched conductive carrier
In one implementation, a power semiconductor package includes a power transistor having a first power electrode and a gate electrode on its bottom surface, and a second power electrode on its top surface. The first power electrode is configured for attachment to a first partially etched conductive carrier segment and the gate electrode is configured for attachment to a second partially etched conductive carrier segment. The power semiconductor package also includes a power electrode heat spreader situated over the second power electrode and configured for attachment to a power electrode conductive carrier segment. |
| US09570378B2 |
Semiconductor device including dummy pattern
A semiconductor device includes a substrate including a circuit region, a dummy region, and a dummy clearance section surrounding the circuit region, and a plurality of dummy patterns formed in the dummy region, the plurality of dummy patterns comprising a first dummy pattern and a second dummy pattern, a distance between the first dummy pattern and the circuit region being less than a distance between the second dummy pattern and the circuit region, and a dummy pattern being absent between the first dummy pattern and the circuit region. The first dummy pattern includes an area which is greater than an area of the second dummy pattern. |
| US09570377B2 |
Semiconductor devices having through electrodes capped with self-aligned protection layers
Semiconductor devices having through electrodes capped with self-aligned protection layers. The semiconductor device comprises a semiconductor substrate including an integrated circuit formed therein, an interlayer dielectric layer on the semiconductor substrate to cover the integrated circuit, an intermetal dielectric layer having at least one metal line that is provided on the interlayer dielectric layer and is electrically connected to integrated circuit, and a through electrode that vertically penetrates the interlayer dielectric layer and the semiconductor substrate. The through electrode includes a top portion that is capped with a first protection layer capable of preventing a constituent of the through electrode from being diffused away from the through electrode. |
| US09570376B2 |
Electrical interconnect for an integrated circuit package and method of making same
A chip package includes a first substrate having at least one circuit layer formed on a first surface thereof, a first die mounted on a second surface of the first substrate opposite from the first surface, and an interconnection assembly comprising upper and lower conductive layers provided on an insulating substrate, with the upper conductive layer of the interconnection assembly affixed to the second surface of the first substrate and electrically connected to the at least one circuit layer of the first substrate. A second substrate is positioned on a side of the first die opposite from the first substrate so as to position the die between the first and second substrates, the second substrate having at least one circuit layer formed on an outward facing first surface thereof that is electrically connected to at least one of the lower conductive layers of the interconnection assembly and the first die. |
| US09570372B1 |
Thermally enhanced semiconductor assembly with heat spreader and integrated dual build-up circuitries and method of making the same
The present invention relates to methods of making a semiconductor assembly having a semiconductor device embedded in a heat spreader and electrically connected to a dual-stage formed interconnect substrate. In a preferred embodiment, the interconnect substrate consists of first and second build-up circuitries and the methods are characterized by the step of attaching a semiconductor subassembly having a first build-up circuitry adhered to a sacrificial carrier to a heat spreader using an adhesive with the semiconductor device inserted into a cavity of the heat spreader and the step of detaching the sacrificial carrier from the first build-up circuitry. The heat spreader provides thermal dissipation, and the first and second build-up circuitries provide staged fan-out routing for the semiconductor device. |
| US09570370B2 |
Multi chip package and method for manufacturing the same
A multi chip package includes a protective layer having an upper surface that surrounds a first chip and a second chip, which are mounted over a first substrate, to expose an upper surface of the first chip and an upper surface of the second chip, a heat spreader disposed over the upper surfaces, and a thermal interface material disposed at an interface between the heat spreader and the upper surfaces. |
| US09570369B1 |
Semiconductor package with sidewall-protected RDL interposer and fabrication method thereof
A semiconductor package includes a redistributed layer (RDL) interposer having a first side, a second side opposite to the first side, and a vertical sidewall extending between the first side and the second side; at least one semiconductor die mounted on the first side of the RDL interposer; a molding compound disposed on the first side and covering the at least one semiconductor die and the vertical sidewall of the RDL interposer; and a plurality of solder bumps or solder balls mounted on the second side. |
| US09570365B2 |
Display device and test pad thereof
The present disclosure provides a display device, including: a display region; and a non-display region adjacent to the display region, wherein the non-display region includes: a gate-driving circuit; a driving unit; and a test pad, wherein the driving unit electrically connects the gate-driving circuit through the test pad. The present disclosure also provides a test pad. |
| US09570363B2 |
Vertically integrated memory cell
A method of forming a vertically integrated memory cell including a deep trench extending into a substrate, a trench capacitor located within the deep trench, and a vertical transistor at least partially embedded within the deep trench above the trench capacitor, the vertical transistor is in direct contact with and electrically coupled to the trench capacitor. |
| US09570360B2 |
Dual channel material for finFET for high performance CMOS
Silicon fins are formed in a bulk silicon substrate and thereafter trench isolation regions are formed between each silicon fin. The silicon fins in nFET and pFET device regions are then recessed. A relaxed silicon germanium alloy fin portion is formed on a topmost surface of each recessed silicon fin portion or on exposed surface of the substrate. A compressively strained silicon germanium alloy fin portion is formed on each relaxed silicon germanium alloy fin portion within the pFET device region, and a strained silicon-containing fin portion is formed on each relaxed silicon germanium alloy fin portion within the nFET device region. Sidewall surfaces of each compressively strained silicon-containing germanium alloy fin portion and each tensile strained silicon-containing fin portion are then exposed. A functional gate structure is provided on the exposed sidewall surfaces of each compressively strained silicon-containing germanium alloy fin portion and each tensile strained silicon-containing fin portion. |
| US09570358B2 |
Nano wire structure and method for fabricating the same
A method comprises applying a first patterning process to a first photoresist layer to form a first opening, a second opening, a third opening and a fourth opening in the sacrificial layer, applying a second patterning process to a second photoresist layer to form a fifth opening, a sixth opening, a seventh opening and an eighth opening in the sacrificial layer, wherein distances between two adjacent openings formed from the first and second patterning processes are substantially equal to each other, applying a third patterning process to a third photoresist layer to form a ninth opening, a tenth opening, an eleventh opening and a twelfth opening in the sacrificial layer, wherein distances between two adjacent openings formed from the second and third patterning processes are substantially equal to each other and forming a plurality of nanowires based on the openings. |
| US09570357B2 |
Vertical field effect transistors
Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure. The structure further includes metal material in electrical contact with the ends of the at least one vertical fin. |
| US09570349B2 |
Non-lithographically patterned directed self assembly alignment promotion layers
A method of an aspect includes forming a directed self assembly alignment promotion layer over a surface of a substrate having a first patterned region and a second patterned region. A first directed self assembly alignment promotion material is formed selectively over the first patterned region without using lithographic patterning. The method also includes forming an assembled layer over the directed self assembly alignment promotion layer by directed self assembly. A plurality of assembled structures are formed that each include predominantly a first type of polymer over the first directed self assembly alignment promotion material. The assembled structures are each adjacently surrounded by predominantly a second different type of polymer over the second patterned region. The first directed self assembly alignment promotion material has a greater chemical affinity for the first type of polymer than for the second different type of polymer. |
| US09570344B2 |
Method to protect MOL metallization from hardmask strip process
A method can include forming a contact trench in a semiconductor structure so that the contact trench extends to a contact formation, the forming including using a hardmask layer, and filling the contact trench with a sacrificial material layer, the sacrificial material layer formed over the contact formation. A semiconductor structure can include a sacrificial material layer over a contact formation. |
| US09570343B2 |
Rinsing solution to prevent TiN pattern collapse
The present invention is a new formulation and process for treating TiN semiconductor devices having a high aspect ratio structure formed thereon. The new composition is designed to be used in the chip making process between cleaning a wet etched memory device and its final rinse/drying process. It is intended to include the treatment in order to prevent collapse of the high aspect ratio TiN structure found on the semiconductor device. |
| US09570342B1 |
Via structure and method for its fabrication
In a preferred embodiment of the invention, the via comprises one or more stacks, each stack comprising a seed layer of a first electrically conducting material formed on a smooth surface; a trace of a second electrically material that is electroplated on the seed layer; a column in electrical contact with the trace, the column comprising a third electrically conducting material that is electroplated on the trace; and an insulating material on the substrate and trace, the insulating material having a smooth upper surface in which the column is exposed. Additional vias may be stacked in tiers one on top of the other with the seed layer of one via making non-rectifying electrical contact with the exposed column of the via below it. Methods for forming the via structure are also disclosed. |
| US09570338B2 |
Method for forming isolation member in trench of semiconductor substrate
A method for forming an isolation member in a trench of a substrate may include the following steps: performing a first deposition process to form a first isolation material set, which is at least partially positioned in the trench; partially removing the first isolation material set, such that a remaining portion of the first isolation material set remains in the trench; after the first isolation material set has been partially removed, performing a fluorine-reduction process on at least the remaining portion of the first isolation material set; after the fluorine-reduction process, performing a second deposition process to form a second isolation material set, which is at least partially positioned in the trench, wherein the second isolation material set includes the remaining portion of the first isolation material set; and processing the second isolation material set for forming the isolation member. |
| US09570332B2 |
Regulation jig and a display substrate conveyer using the same
The invention discloses a regulation jig including a regulation part and a scale plate which are movably connected. The regulation part can simultaneously regulate positions of conveying rings having the same sequence, such that they are arranged into a line. The scale plate can accurately control the distance between the lines formed by the rings. The regulation jig not only can guarantee the straightness of a row of conveying rings around different conveying rollers and having the same sequence, but also can ensure that the transmission surface formed by the conveying rings for supporting and conveying the display substrates has a good flatness, in turn preventing the display substrates from deviating from its travelling direction during the transmission. As such, the regulation jig provided by the invention can efficiently and promptly regulate the positions of the conveying rings, so as to ensure the normal transmission of the display substrate. |
| US09570322B2 |
Integrated circuit packages and methods of forming same
Packages and methods of manufacture thereof are described. A package may include a first package and a die structure disposed over the first package. The first package may include: a first encapsulant; a first via structure within the first encapsulant; a first die within the first encapsulant, at least a portion of the first encapsulant being interposed between a sidewall of the first die and a sidewall of the first via structure; a second die within the first encapsulant, an active side of the second die facing an active side of the first die; and a first via chip within the first encapsulant, the first via chip comprising one or more through vias, wherein the first via chip is disposed at the active side of the first die, and between the second die and the first via structure. |
| US09570321B1 |
Use of an external getter to reduce package pressure
A system and method for forming a wafer level package. In one example, a substrate used in the wafer level package includes a surface defined by a wafer level package (WLP) region and an external region, and a layer of getter material is disposed on at least a portion of the external region. According to one embodiment, the external region comprises a saw-to-reveal (STR) region of the wafer. |
| US09570320B2 |
Method to etch copper barrier film
A method of opening a barrier film below copper structures in a stack is provided. A pulsed gas is provided into a plasma processing chamber, wherein the providing the pulsed gas comprises providing a pulsed H2 containing gas and providing a pulsed halogen containing gas, wherein the pulsed H2 containing gas and the pulsed halogen containing gas are pulsed out of phase, and wherein the pulsed H2 containing gas has an H2 high flow period and the pulsed halogen containing gas has a halogen containing gas high flow period, wherein the H2 high flow period is greater than the halogen containing gas high flow period. The pulsed gas is formed into a plasma. The copper structures and the barrier film are exposed to the plasma, which etches the barrier film. In another embodiment, a wet and dry cyclical process may be used. |
| US09570319B2 |
Method of manufacturing a semiconductor device
Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes: providing a workpiece having a recess and a dielectric layer lining the recess; forming a conductive structure within the recess, wherein the conductive structure partially fills the recess; and recessing the dielectric layer, wherein, after the recessing, a top surface of the recessed dielectric layer is disposed within the recess. |
| US09570312B2 |
Plasma etching method
Provided is a plasma etching method capable of favorably forming masks used when etching a multilayer film. This plasma etching method for etching boron-doped amorphous carbon involves using a plasma of a gas mixture comprising a chlorine gas and an oxygen gas, and setting the temperature of a mounting stage (3) to 100° C. or greater. |
| US09570309B2 |
Mask alignment system for semiconductor processing
A mask alignment system for providing precise and repeatable alignment between ion implantation masks and workpieces. The system includes a mask frame having a plurality of ion implantation masks loosely connected thereto. The mask frame is provided with a plurality of frame alignment cavities, and each mask is provided with a plurality of mask alignment cavities. The system further includes a platen for holding workpieces. The platen may be provided with a plurality of mask alignment pins and frame alignment pins configured to engage the mask alignment cavities and frame alignment cavities, respectively. The mask frame can be lowered onto the platen, with the frame alignment cavities moving into registration with the frame alignment pins to provide rough alignment between the masks and workpieces. The mask alignment cavities are then moved into registration with the mask alignment pins, thereby shifting each individual mask into precise alignment with a respective workpiece. |
| US09570307B2 |
Methods of doping substrates with ALD
Provided are methods of doping substrates and making doped semiconductor features. An exemplary method includes providing a substrate having at least one feature having an aspect ratio; depositing a layer of dopants onto the substrate, the layer of dopants having a shape conforming to the at least one feature. A dielectric layer is deposited onto the layer of dopants, the dielectric layer having a shape conforming to the layer of dopants. The dielectric layer is annealed to diffuse the dopants into the substrate. |
| US09570303B2 |
Conformal amorphous carbon for spacer and spacer protection applications
A method of forming a nitrogen-doped amorphous carbon layer on a substrate in a processing chamber is provided. The method generally includes depositing a predetermined thickness of a sacrificial dielectric layer over a substrate, forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate, depositing conformally a predetermined thickness of a nitrogen-doped amorphous carbon layer on the patterned features and the exposed upper surface of the substrate, selectively removing the nitrogen-doped amorphous carbon layer from an upper surface of the patterned features and the upper surface of the substrate using an anisotropic etching process to provide the patterned features filled within sidewall spacers formed from the nitrogen-doped amorphous carbon layer, and removing the patterned features from the substrate. |
| US09570300B1 |
Strain relaxed buffer layers with virtually defect free regions
A strain relaxed buffer layer of a second semiconductor material and of a second lattice constant and containing misfit dislocation defects and threading dislocation defects is formed atop a surface of a first semiconductor material of a first lattice constant that differs from the second lattice constant. The surface of the first semiconductor material includes at least one recessed region and adjoining non-recessed regions. An anneal is then performed on the strain relaxed buffer layer to propagate and amass the misfit dislocation defects and threading dislocation defects at a sidewall of each of the non-recessed regions of the first semiconductor material. |
| US09570298B1 |
Localized elastic strain relaxed buffer
A strain relaxed buffer layer is fabricated by melting an underlying layer beneath a strained semiconductor layer, which allows the strained semiconductor layer to elastically relax. Upon recrystallization of the underlying layer, crystalline defects are trapped in the underlying layer. Semiconductor layers having different melting points, such as silicon germanium layers having different atomic percentages of germanium, are formed on a semiconductor substrate. An annealing process causes melting of only the silicon germanium layer that has the higher germanium content and therefore the lower melting point. The silicon germanium layer having the lower germanium content is elastically relaxed upon melting of the adjoining silicon germanium layer and can be used as a substrate for growing strained semiconductor layers such as channel layers of field-effect transistors. |
| US09570296B2 |
Preparation of low defect density of III-V on Si for device fabrication
A method of forming a semiconducting material includes depositing a graded buffer on a substrate to form a graded layer of an indium (In) containing III-V material, the In containing III-V material being indium-gallium-arsenic (InGaAs) or indium-aluminum-arsenic (InAlAs) and comprising In in an increasing atomic gradient up to 35 atomic % (at. %) based on total atomic weight of InGa or InAl; and forming a layer of InGaAs on the graded layer, the layer of InGaAs comprising about 25 to about 100 at. % In based on total atomic weight of InGa. |
| US09570292B2 |
Method for making an epitaxial structure with carbon nanotube layer
A method for making an epitaxial structure includes the following steps. A substrate having an epitaxial growth surface is provided. A buffer layer is formed on the epitaxial growth surface. A carbon nanotube layer is placed on the buffer layer. A first epitaxial layer is epitaxially grown on the buffer layer. The substrate and the buffer layer are removed to expose a second epitaxial growth surface. A second epitaxial layer is epitaxially grown on the second epitaxial growth surface. |
| US09570290B2 |
Plasma assisted atomic layer deposition titanium oxide for conformal encapsulation and gapfill applications
The embodiments herein relate to methods and apparatus for depositing an encapsulation layer over memory stacks in MRAM and PCRAM applications. The encapsulation layer is a titanium dioxide (TiO2) layer deposited through an atomic layer deposition reaction. In some embodiments, the encapsulation layer may be deposited as a bilayer, with an electrically favorable layer formed atop a protective layer. In certain implementations, gaps between neighboring memory stacks may be filled with titanium oxide, for example through an atomic layer deposition reaction or a chemical vapor deposition reaction. |
| US09570288B2 |
Method to fabricate FinFET sensors, in particular, FinFET sensors for ionic, chemical and biological applications on Si-Bulk
The present invention relates to a method of producing a FinFET sensor device comprising the steps of: providing a silicon substrate; etching the silicon substrate to produce at least one upwardly extending Fin structure externally protruding from a surface of the silicon substrate; depositing a spacer layer on the at least one Fin structure; anisotropically etching a section of the spacer layer to expose the underlying silicon; isotropic etching of the exposed silicon surrounding the at least one Fin structure; and carrying out oxidation of the silicon surrounding the at least one Fin structure to produce a Fin structure of silicon inside the at least one Fin structure. The present invention also relates to FinFET sensor devices produced by the above method. |
| US09570282B2 |
Ionization within ion trap using photoionization and electron ionization
A mass spectrometer is disclosed. The mass spectrometer may include an ion trap configured to trap and analyze an ionized sample. A first aperture may be provided having a first diameter, and a second aperture may be provided having a second diameter. The first aperture may be configured to receive electrons for the purpose of ionizing sample ions within the ion trap. The second aperture may be configured to receive photons for the purpose of ionizing sample ions within the ion trap. |
| US09570281B2 |
Ion generation device and ion generation method
The invention relates to an ion generation device and an ion generation method, and more particularly to a device and a method which generates ions at the low pressure and then said ions can be transferred into the next stage in an off-axis manner. In the invention, ions from electrospray or other types of ion source are generated in the pressure which is lower than atmosphere pressure. A followed ion guide device can then transfer most of said generated ions into next stage in an off-axis manner, while most of neutral noise can be eliminated in this process. |
| US09570279B2 |
Two rotating electric fields mass analyzer
A mass analyzer includes two rotating electric field (REF) units, sinusoidal signal generators and a means for separation of dispersed ions. The REF units include a plurality of elongated electrodes surrounding a central axis, and are lined in tandem at elongated direction. Sinusoidal signals are applied to the electrodes to rotate electric fields within each REF unit. The means for separation is placed adjacent the downstream end of the 2nd REF unit. Ions enter the 1st REF unit, diverge outwards and leave the 1st REF unit on off-axis positions. The ions successively enter the 2nd REF unit and converge inwards because of 180 degrees phase difference from the 1st REF unit. Specified mass ions return to and travel along the central axis. However, unspecified mass ions deviate from the central axis and travel apart from the central axis. The means for separation separates specified ions from unspecified ions. |
| US09570277B2 |
System and method for MALDI-TOF mass spectrometry
A system and method for matrix assisted laser desorption time-of-flight (MALDI-TOF) mass spectrometry. A method for MALDI-TOF mass spectrometry includes initiating a spectral analysis of a sample on a MALDI-TOF spectrometer. The sample is ionized, and a first ion spectrum is detected and stored. Thereafter, the spectrometer is reset, and the ionizing, detecting, storing, and resetting are repeated until a predetermined plurality of spectra of the sample is acquired. |
| US09570276B2 |
Projection-type charged particle optical system and imaging mass spectrometry apparatus
Provided is a projection-type charged particle optical system in which a projection magnification can be changed while a decrease in the accuracy in measuring a mass-to-charge ratio is being suppressed. A projection-type charged particle optical system according to the present invention includes a first electrode disposed so as to face a sample and having an opening formed therein for allowing a charged particle to pass, a second electrode disposed on a side of the first electrode opposite to where the sample is disposed and having an opening formed therein for allowing the charged particle to pass, and a flight-tube electrode disposed such that the charged particle that has been emitted from the sample and has passed through the second electrode enters the flight-tube electrode and being configured to form a substantially equipotential space thereinside. A principal plane is formed at at least two positions in a travel path of the charged particle. |
| US09570273B2 |
Cold plasma treatment devices and associated methods
A compact cold plasma device for generating cold plasma having temperatures in the range 65 to 120 degrees Fahrenheit. The compact cold plasma device has a magnet-free configuration and an induction-grid-free configuration. An additional configuration uses an induction grid in place of the input electrode to generate the cold plasma. A high voltage power supply is provided that includes a controllable switch to release energy from a capacitor bank to a dual resonance RF transformer. A controller adjusts the energy input to the capacitor bank, as well as the trigger to the controllable switch. |
| US09570272B2 |
Plasma processing apparatus and plasma processing method
A plasma processing apparatus includes: a reaction chamber; a stage which is disposed inside the reaction chamber and on which a conveyance carrier is mountable; an electrostatic chuck mechanism including an electrode portion that is disposed inside the stage; a support portion which supports the conveyance carrier between a stage-mounted position on the stage and a transfer position that is distant from the stage upward; and an elevation mechanism which elevates and lowers the support portion relative to the stage. In a case in which the conveyance carrier is mounted on the stage by lowering the support portion, the electrostatic chuck mechanism starts applying a voltage to the electrode portion before contact of an outer circumferential portion of a holding sheet which holds the conveyance carrier to the stage. |
| US09570263B2 |
Vacuum switching assembly
There is provided a vacuum switching assembly for switching an AC or DC current. The vacuum switching assembly comprises a vacuum switch. The vacuum switch includes: first and second electrodes (20, 22) located in a vacuum tight enclosure, the vacuum tight enclosure containing a gas or gas mixture, the first and second electrodes (20, 22) defining opposed electrodes being separated by a gap, each of the first and second electrodes (20,22) being connectable to a respective electrical circuit carrying an AC or DC voltage; and a pressure controller (36) configured to control an internal pressure of the vacuum tight enclosure, wherein the pressure controller (36) is configured to selectively switch the internal pressure of the vacuum tight enclosure between: a first vacuum level that permits formation and maintenance of a glow discharge in the vacuum tight enclosure to allow a current to flow between the first and second electrodes (20, 22) via the glow discharge so as to turn on the vacuum switch; and a second vacuum level that inhibits formation and maintenance of a glow discharge in the vacuum tight enclosure to prevent a current from flowing between the first and second electrodes (20, 22) via the glow discharge so as to turn off the vacuum switch. |
| US09570258B2 |
Magnetic switch
The present invention relates to a magnetic switch, and more particularly, to a magnetic switch provided with a permanent magnet disposed at an outside of an upper frame and an externally fitted permanent magnet holder to reduce a number of components and facilitate maintenance. |
| US09570257B2 |
Method for controlling a contactor device, and control unit
A method performed in a control unit for opening a contactor device. The contactor device includes a carrier being movable between a closed position in which a current is allowed to flow in a current path and an open position in which the current path is broken. The control unit is configured to enable the movement of the carrier between the closed position and the open position by energizing a coil of an electromagnetic circuit. The method includes: initiating the opening of the contactor device by de-energizing the coil, wherein the de-energizing includes using a demagnetization circuit including a discharge element, the discharge element being arranged to consume energy in the coil; bypassing, at a first point of time, the discharge element; and re-energizing the coil. |
| US09570253B1 |
System and method with timing self-configuration
A method of operating an automatic transfer switch to switch an electrical load from one power source to another power source includes measuring one or more characteristics of a switching circuit in the automatic transfer switch. A value of one or more timing variables is determined based on the measured characteristics of the switching circuit. The switching circuit is operated to close relays in the automatic transfer switch. The timing of closing of the relays is based on the value of the timing variables. |
| US09570247B2 |
Switch strip, safety sensor strip and production method thereof, and also anti-trap protection
The invention relates to a switch strip (10) for an apparatus for detecting an obstruction (210) in the movement range (221) of a closure element (220), in particular of an automotive vehicle (200). The switch strip (10) has an inner electrode (20), an outer electrode (30) approximately concentrically surrounding the inner electrode (20) at a distance (D), and a space (40) filled with air, which is arranged between the outer electrode (30) and the inner electrode (20) and which is dielectric. Furthermore, the switch strip (10) has a spacer (50) which is deformable in a direction transverse to the longitudinal direction. The spacer (50) spaces and insulates the two electrodes (20, 30) from one another. The outer electrode (30) is deformable by a force (F) applied from the outside. The deformation of the outer electrode (30) is able to at least in portions bring the inner electrode (20) and the outer electrode (30) into contact with each other. Such a switch strip (10) is also referred to as a tactile switch strip (10). |
| US09570246B2 |
Disconnector for switchgear
Disconnector for switchgear, having a first contact position, in which a contact is between main and first terminals, and a second contact position, in which a contact is between the main and second terminal. The disconnector includes a connector body moveable in a first direction between the first and second positions and having an end extendable in a direction substantially perpendicular to the first direction for providing a contact force between the end and the first, second or main terminals, a first operating mechanism arranged to move the body between the first and second positions, and a second operating mechanism arranged to extend the end when the disconnector is in either the first or second contact positions, in which the end includes a conical inside surface and the second operating mechanism includes a first shaft having a first conically shaped end positioned inside the conical inside surface. |
| US09570243B2 |
Carbonaceous composition for supercapacitor cell electrode, electrode, process for the manufacture thereof and cell incorporating same
A carbonaceous composition usable to constitute a supercapacitor cell electrode, a porous electrode usable to equip such a cell, a process for manufacturing this electrode and one such cell incorporating at least one such electrode, for example in order to equip an electric vehicle. This composition is usable to be in contact with an aqueous ionic electrolyte, is based on a carbonaceous powder and comprises a hydrophilic binder-forming system. The system may include between 3% and 10% by weight a first crosslinked polymer having a number-average molecular weight Mn of greater than 1000 g/mol and having alcohol groups, and between 0.3% and 3% by weight a second polymer of at least one acid and which has a pKa of between 0 and 6 and a number-average molecular weight Mn of greater than 500 g/mol, the first polymer being crosslinked thermally in the presence of the second polymer. |
| US09570242B2 |
Flexible Ti—In—Zn—O transparent electrode for dye-sensitized solar cell, and metal-inserted three-layer transparent electrode with high conductivity using same and manufacturing method therefor
The present invention relates to a flexible transparent electrode for a dye-sensitized solar cell and a manufacturing method for same, and more specifically, to a flexible Ti—In—Zn—O transparent electrode for a dye-sensitized solar cell and a manufacturing method for same, and to a metal-inserted three-layer transparent electrode with high conductivity using the flexible transparent electrode and a manufacturing method for same, wherein compared with the conventional fluorine-doped tin oxide (FTO) and indium-tin oxide (ITO) transparent electrodes with a high deposition temperature, the flexible transparent electrode, despite being deposited at room or low temperature, has low surface resistance, high conductivity and transmittance, superior resistance against external bending, improved surface characteristics and better surface roughness performance. |
| US09570240B1 |
Controlled crystallization to grow large grain organometal halide perovskite thin film
A method of forming perovskite thin films with micron-sized perovskite grains is provided. A layer of PbX2 in a solution containing a metal ion additive is applied to a structure. The structure with the PbX2 layer is annealed a first time. The PbX2 is exposed to CH3NH3X in a solvent. The structure with the exposed PbX2 layer is annealed a second time resulting in a CH3NH3PbX3 layer. X is selected from a group consisting of Cl, Br, I, CN, and SCN. |
| US09570236B2 |
Electronic component and method for manufacturing the same
An electronic component is provided with: an electronic component body including a top face, a bottom face, a pair of side faces, and a pair of end faces provided with an outside electrode; and a pair of metal terminals individually connected to the pair of outside electrodes of the electronic component body, wherein the metal terminals is electrically and mechanically connected to the outside electrode of the electronic component body, and is also in contact with bottom face of the electronic component. The electronic component requires no jig or a simple jig if any for securing a metal terminal and electronic component body in place. |
| US09570235B2 |
Multilayer ceramic capacitor
A multilayer ceramic capacitor that is highly resistant to insulation degradation under high-temperature load includes an inner ceramic layer that has a composition mainly composed of a perovskite-type compound containing Ba and Ti, at least one of Nb and Ta, contains Mn and Al, and optionally contains Mg and a rare-earth element that is at least one of Y, Gd, Tb, Dy, Ho, and Er, with a content of Ti being 100 parts by mole, and (a) a total of Nb and Ta is from about 0.2 to about 1.5 part by mole, (b) Mg is not more than about 0.2 part by mole including 0 part by mole, (c) Mn is from about 1.0 to about 3.5 parts by mole, (d) Al is from about 1.0 to about 4.0 parts by mole, and (e) the rare-earth element is not more than about 0.05 part by mole including 0 part by mole. Furthermore, an average number of particles per one layer of the inner ceramic layer is not more than 3. |
| US09570233B2 |
High-Q multipath parallel stacked inductor
A parallel stacked multipath inductor includes a first layer including turns disposed about a center region, the turns on the first layer having segments that extend length-wise along the turns, the segments having positions that vary from an innermost position relative to the center region and an outermost position relative to the center region. A second layer includes turns electrically connected to the first layer along its length and disposed about the center region, the turns on the second layer having segments that extend length-wise along the turns, the segments having positions that vary from an innermost position and an outermost position relative to the center region. Cross-over architectures are configured to couple the segments on the first layer with the segments on the second layer to form segment paths that have a substantially same length for all segment paths per turn between the first and second layers. |
| US09570231B2 |
Detecting device, power supply system, and detecting device control method
A detecting device includes: a measurement coil made up of a first partial coil to which current in a particular direction is induced by a magnetic field to be supplied to a power reception coil configured to receive power, and a second partial coil to which the current in the opposite direction of the particular direction is induced by the magnetic field; a measurement unit configured to measure the voltage of the measurement coil as measurement coil voltage; and a foreign object detecting unit configured to detect a foreign object within the magnetic field based on the measurement coil voltage. |
| US09570222B2 |
Vector inductor having multiple mutually coupled metalization layers providing high quality factor
An inductor component includes a plurality of conductive elements, each formed as an individual patch of conductive material, with the conductive elements arranged in a vertical stack and tightly coupled to one another. Dielectric is disposed between more adjacent conductive elements, the dielectric has a permittivity and is sufficiently thin so as to provide a mutual inductance factor of at least one-half or greater between adjacent ones of the conductive elements. The dielectric is typically thinner than the adjacent conductors. |
| US09570220B2 |
Remote actuated cryocooler for superconducting generator and method of assembling the same
In one embodiment, a cryocooler assembly for cooling a heat load is provided. The cryocooler assembly includes a vacuum vessel surrounding the heat load and a cryocooler at least partially inserted into the vacuum vessel, the cryocooler including a coldhead. The assembly further includes an actuator coupled to the cryocooler. The actuator is configured to translate the cryocooler coldhead into thermal engagement with the heat load and to maintain constant pressure of the coldhead against the heat load to facilitate maintaining thermal engagement with the heat load as the heat load shrinks during a cool down process. |
| US09570213B2 |
USB cable with heat seal PET mylar film
A USB cable (100), comprising: a power wire (1) transferring positive power, a pair of signal wires (2), a metallic braided layer (6) enclosing on the power wire and the signal wires, and an insulative outer jacket (7) surrounding the metallic braided layer. The power wire comprises a metallic inner conductor and an insulative layer surrounding the inner conductor, a mylar film (11) is surrounding on the power wire, and the mylar film is made of Heat Seal PET. |
| US09570209B2 |
Conductive layer and preparation method for conductive layer
Provided are a conductive layer and a method of manufacturing the same. The conductive layer is formed without, so called, a high temperature process but has suitable crystallinity, excellent transparency and excellent resistance characteristic, and the method of manufacturing the same is also provided. |
| US09570206B2 |
Firing metal with support
A solar cell can include a substrate and a semiconductor region disposed in or above the substrate. The solar cell can also include a conductive contact disposed on the semiconductor region with the conductive contact including a paste, a first metal, and a first conductive portion that includes a conductive alloy formed from the first metal at an interface of the substrate and the semiconductor region. |
| US09570203B2 |
Nuclear reactor power monitor
A nuclear power plant controlling system is provided in which the thermal limit can be brought close to the full limit of operation restrictions by automatic control. The system includes a thermal limit monitor, including a receiver configured to receive a first signal, a prospective time deriving unit configured to derive a prospective time for the first signal to arrive at the full limit, a judging unit configured to judge a remaining time to the prospective time, a compensating unit configured to compensate the first signal based on a second signal, a first transmitter configured to transmit a first instruction to vary a rate factor of the first and second signals by synchronizing the compensation, and a second transmitter configured to transmit a second instruction to hold the first or second signal after arriving at the full limit or at a threshold that is just before the full limit. |
| US09570195B2 |
On chip characterization of timing parameters for memory ports
A circuit and method for memory characterization. The circuit includes first and second programmable delay lines, address and data registers, an output register and a finite state machine controller. The finite state machine controller supplies an address to the address register, data to the data register and controlling a delay of the first programmable delay line and the second programmable delay line in at least one predetermined sequence to determine an operating characteristic of the memory to be tested. The programmable delay lines may be connected as a ring oscillator. Determination of the frequency of the ring oscillator via a counter determines the delay of the delay line. The programmable delay lines, the address register and data registers, the output register, the finite state machine controller and the memory to be tested are preferably constructed on a same semiconductor substrate. |
| US09570194B1 |
Device for detecting fuse test mode using a fuse and method therefor
A fuse test mode detection device is disclosed, which relates to a technology for improving detection efficiency of a fuse test mode. The fuse test mode detection device includes: a fuse unit configured to scan a plurality of fuses in a boot-up operation, and output fuse data; a counter configured to count the fuse data in response to a clock signal; a decoding unit configured to output a decoding signal for controlling a fuse test mode in response to an output signal of the counter; an encoder configured to encode the output signal of the decoding unit, and output a code signal; and a comparator configured to compare the fuse data with the code signal, and output a comparison signal. |
| US09570193B2 |
Implementing hidden security key in eFuses
A method and circuit for implementing a hidden security key in Electronic Fuses (eFuses), and a design structure on which the subject circuit resides are provided. The circuit includes a race condition circuit coupled to a latching structure. The race condition circuit is characterized including respective driver strengths of each stage in the race as well as a sampling clock during chip testing. The data is used to store drive strengths for each stage in eFuses and is used to get a logical one or logical zero out of the final latching stage of the race condition circuit. |
| US09570188B2 |
Semiconductor device
The trimming range of a reference current is extended larger than that of the related art. A semiconductor device includes a reference current generating circuit that generates a reference current. The reference current includes a first base current, a second base current base current, a second base current, a temperature compensating current, and a voltage compensating current. The first base current can be trimmed. The second base current flowing opposite to the first base current can be trimmed. The temperature compensating current flows in the same direction as the first base current and has higher temperature dependence than the first and second base currents. The voltage compensating current flows in the same direction as the first base current and depends on power supply voltages more than the base currents. |
| US09570187B2 |
Data storage device and operating method thereof
A data storage device may include: a nonvolatile memory device including a memory block; and a controller suitable for controlling the nonvolatile memory device to perform a string read operation on the memory block, and estimating a data storage rate of the memory block based on string read data acquired through the string read operation. When performing the string read operation, the nonvolatile memory device may apply the same read voltage to a plurality of word lines included in the memory block at the same time, acquire the string read data from the memory block according to the read voltage, and transmit the string read data to the controller. |
| US09570184B2 |
Dynamic adjustment of read voltage levels based on memory cell threshold voltage distribution
A system and methods to find the threshold voltage distribution across a set of nonvolatile memory cells, such that embodiments may incorporate this distribution information into calculations that may change the read compare voltages used to read the memory cells, while ensuring adequate separation in read voltage between different data states at which the memory cells may be read. |
| US09570182B1 |
Semiconductor memory device and memory system
According to one embodiment, a semiconductor memory device comprises an input circuit configured to input data, a memory cell array which includes memory cells enabling data to be held and to which the input data is written, a control circuit configured to control operation of a memory relating to the data, and a training circuit configured to execute training of the input circuit in parallel with the operation of the memory. |
| US09570181B2 |
Memory system
According to an embodiment, a memory system includes first wiring lines; second wiring lines; third wiring lines; fourth wiring lines; and first and second storages. The first storage includes first memory cells arranged at intersections of the first wiring lines and the second wiring lines. Each of the third wiring lines is connected to any one of the first wiring lines. Each of the fourth wiring lines is pre-associated with a logical address specified by a host apparatus. The second storage includes second memory cells arranged at intersections of the third wiring lines and the fourth wiring lines. A resistance state of each of the second memory cells is set to a first resistance state or a second resistance state where a resistance value is lower than that in the first resistance state, according to a correspondence relationship between the logical address and the first wiring line. |
| US09570176B2 |
Nonvolatile memory device, storage device having the same, operating method thereof
An operating method of a nonvolatile memory device includes determining whether a memory block is a selected block, and when the memory block is not the selected block, determining whether the memory block shares a block word line with the selected block. The method further includes applying an unselected block word line voltage to word lines of the memory block when the memory block shares the block word line with the selected block, and floating the word lines of the memory block when the memory block does not share the block word line with the selected block. |
| US09570170B2 |
Resistive memory device and method of operating the same
A memory device includes a memory cell array having multiple memory cells arranged respectively in regions where first signal lines cross second signal lines. The memory device further includes a decoder having multiple line selection switch units connected respectively to the of first signal lines. Each of the multiple line selection switch units applies a bias voltage to a first signal line corresponding to each of the multiple line selection switch units in response selectively to a first switching signal and a second switching signal, voltage levels of which are different from each other in activated states. |
| US09570167B2 |
Apparatuses and methods of reading memory cells
A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (VTH) region between a first state distribution and a second state distribution. The method includes ramping a bias on a memory cell a first time to determine a first threshold voltage (VTH1) of the memory cell and determining whether the VTH1 is within the overlapped VTH region. Upon determination that the memory cell is within the overlapped VTH region, the method further includes applying a write pulse to the memory cell; ramping a bias on the memory cell a second time to determine a second threshold voltage (VTH2); and determining the state of the memory cell prior to receiving the write pulse based on a comparison between the VTH1 and the VTH2. |
| US09570164B2 |
System and method for performing memory operations on RRAM cells
A resistive RAM (RRAM) device has a bit line, a word line, a source line carrying a bias voltage that is a substantially static and non-negative voltage, an RRAM cell, and a bit line control coupled to the bit line circuit. The RRAM cell includes a gate node coupled to the word line, a bias node coupled to the source line, and a bit line node coupled to the bit line. The bit line control circuit is configured to generate non-negative command voltages to perform respective memory operations on the RRAM cell. |
| US09570163B2 |
Immunity of phase change material to disturb in the amorphous phase
Disturb from the reset to the set state may be reduced by creating an amorphous phase that is substantially free of crystal nuclei when programming the reset state in a phase change memory. In some embodiments, this can be achieved by using a current or a voltage to program that exceeds the threshold voltage of the phase change memory element, but does not exceed a safe current voltage which would cause a disturb. |
| US09570159B1 |
Methods and apparatus to preserve data of a solid state drive during a power loss event
Methods, apparatus, systems and articles of manufacture to preserve data of a solid state drive during a power loss event are disclosed. An example method includes sending, upon detection of the power loss event, from a processor of the solid state drive, a command to abort an ongoing write operation of an aborted memory cell. In response to an indication that the ongoing write operation is aborted, the data to be written to the aborted memory cell is recovered. A first portion of the data to be written to the aborted memory cell is written to a first memory cell. A second portion of the data to be written to the aborted memory cell is written to a second memory cell. |
| US09570158B1 |
Output latch for accelerated memory access
An integrated circuit (IC) is disclosed herein for accelerating memory access with an output latch. In an example aspect, the output latch includes a data storage unit, first circuitry, and second circuitry. The data storage unit includes a first input node configured to receive a first input voltage, a second input node configured to receive a second input voltage, a first output node configured to provide a first output voltage, and a second output node configured to provide a second output voltage. The first circuitry is configured to accelerate a voltage level transition of the first output voltage at the first output node responsive to the first input voltage at the first input node. The second circuitry is configured to accelerate a voltage level transition of the second output voltage at the second output node responsive to the second input voltage at the second input node. |
| US09570156B1 |
Data aware write scheme for SRAM
Approaches for providing write-assist for a Static Random Access Memory (SRAM) array are provided. A circuit includes a control circuit connected to a cell in a SRAM array. The control circuit is configured to: apply a first voltage to a first pull down transistor of the cell during a write operation to the cell; and apply a second voltage, different than the first voltage, to a second pull down transistor of the cell during the write operation. |
| US09570154B2 |
Dual-port SRAM timing control circuit which can reduce the operational power consumption of SRAM without affecting the read reliability
A dual-port SRAM timing control circuit, with three NMOS transistors connected in series respectively between ground and nodes of the two bit lines to which the cell structure corresponds. The gates of the NMOS transistors are connected to a corresponding wordline, a pulse signal and a timing control signal, respectively. The each pulse signals are formed by a corresponding clock signal inputted into a first pulse generator, respectively. An address signal, after passing through an address latch, is inputted into an address comparator for comparison, with the address comparison result outputted to a timing control signal generator; and the pulse signal, after undergoing an AND operation, is inputted into the timing control signal generator, with a timing control signal outputted. When the two address signals are the same, the address comparison result is 1; when the two address signals are not the same, the address comparison result is 0; when the AND result of the two pulse signals is 0, the timing control signal is 1; when the AND result of the two pulse signals is 1, the timing control signal is an inverting signal of the address comparison result. The present invention can reduce the operational power consumption of SRAM without affecting the read reliability. |
| US09570148B2 |
Internal voltage generation circuit, semiconductor memory device and semiconductor memory system
An internal voltage generation circuit includes a charging unit suitable for charging electrical charges for a time corresponding to a control signal; a charge control unit suitable for generating the control signal, which is activated for a time corresponding to temperature information, and controlling a charging operation of the charging unit; and an output unit suitable for generating an internal voltage based on charge amount by the charging operation. |
| US09570145B2 |
Protocol for refresh between a memory controller and a memory device
The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller. |
| US09570144B2 |
Memory refresh method and devices
The present disclosure describes DRAM architectures and refresh controllers that allow for scheduling of an opportunistic refresh of a DRAM device concurrently with normal row activate command directed toward the DRAM device. Each activate command affords an “opportunity” to refresh another independent row (i.e., a wordline) within a memory device with no scheduling conflict. |
| US09570143B2 |
Semiconductor memory device for performing refresh operation
A semiconductor memory device includes: a plurality of memory areas; a target area setting unit suitable for designating a target area according to a number of accesses to the respective memory areas; a random address generation unit suitable for generating a random address within the respective memory areas in a random manner; a target address generation unit suitable for generating a target address based on the target area and the random address; and a driving unit suitable for performing a smart refresh operation according to the target address. |
| US09570142B2 |
Apparatus having dice to perorm refresh operations
Some embodiments include an apparatus that comprise an interface chip having an oscillator to produce an original clock signal, a first memory chip having first memory cells, and a second memory chip having second memory cells. The first memory cells may be refreshed in response to a first clock signal based on the original clock signal. The second memory cells may be refreshed in response to a second clock signal based on the original clock signal. |
| US09570135B2 |
Apparatuses and methods to delay memory commands and clock signals
An example delay circuit may include a delay block configured to receive a command signal and/or a bank address signal, a first clock signal, and a second clock signal and further configured to add an intrinsic delay to the command signal or the bank address signal and add a forward path delay greater than the intrinsic delay to the first and second clock signals. |
| US09570130B2 |
Memory system and memory physical layer interface circuit
A memory physical layer interface circuit electrically connected between a memory controller and a memory device is provided. The memory physical layer interface circuit includes a dock generation module and first-in-first-out (FIFO) modules. The clock generation module generates a reference clock signal and output related clock signals. The reference clock signal is transmitted to the memory device. Each of the FIFO modules writes the input information therein transmitted by the memory controller according to a write-related clock signal and retrieves the input information therefrom according to one of the output related clock signals to generate an output signal. The output signal is transmitted to the memory device to operate the memory device. The write-related clock signal is generated by dividing a frequency of one of the output related clock signals. |
| US09570128B2 |
Managing skew in data signals
An apparatus for controlling memory includes a memory controller, and an interface to data lines connecting it to memory. Each line carries a signal that corresponds to a bit to be written to memory. The interface includes, for each line, circuitry for transmitting a bit to memory via the line, and a data de-skewer. For each line, the de-skewer receives a first data signal that represents a bit to be written. Each line has an inherent skew. The de-skewer generates a second data signal by applying a skew to the first. A selected extent of skew increases a likelihood of sampling the second data signal during a data-valid window thereof. The same de-skewer receives and skews a first data bit read from the memory. |
| US09570123B2 |
Non-volatile memory serial core architecture
A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. The memory bank is divided into two halves, where each half is divided into upper and lower sectors. Each sector provides data in parallel to a shared two-dimensional page buffer with an integrated self column decoding circuit. A serial to parallel data converter within the memory bank couples the parallel data from either half to the serial data path core. The shared two-dimensional page buffer with the integrated self column decoding circuit minimizes circuit and chip area overhead for each bank, and the serial data path core reduces chip area typically used for routing wide data buses. Therefore a multiple memory bank system is implemented without a significant corresponding chip area increase when compared to a single memory bank system having the same density. |
| US09570122B2 |
Device having multiple switching buffers for data paths controlled based on IO configuration modes
A device includes a first data terminal, a second data terminal, a first switching buffer coupled between a data node and the first data terminal and a second switching buffer coupled between the data node and the second data terminal. The first switching buffer and the second switching buffer are arranged such that a distance between the first switching buffer and the second data terminal is shorter than a distance between the second switching buffer and the second data terminal and that a distance between the first switching buffer and the first data terminal is shorter than a distance between the second switching buffer and the first data terminal. |
| US09570113B2 |
Automatic generation of video and directional audio from spherical content
A spherical content capture system captures spherical video and audio content. In one embodiment, captured metadata or video/audio processing is used to identify content relevant to a particular user based on time and location information. The platform can then generate an output video from one or more shared spherical content files relevant to the user. The output video may include a non-spherical reduced field of view such as those commonly associated with conventional camera systems. Particularly, relevant sub-frames having a reduced field of view may be extracted from each frame of spherical video to generate an output video that tracks a particular individual or object of interest. For each sub-frame, a corresponding portion of an audio track is generated that includes a directional audio signal having a directionality based on the selected sub-frame. |
| US09570112B2 |
Multiple views recording
A system and method for providing multiple views recording is provided. In example embodiments, an indication to record serial events including a first event and a second event on a same channel is received. A recording stream is started at a beginning of the first event and ends at an end of the second event. View markings are inserted in the recording stream that differentiate a first view corresponding to the first event from a second view corresponding to the second event. Thus, the recording stream creates a single file that contains multiple views. The single file is stored for later playback. |
| US09570107B2 |
System and method for semi-automatic video editing
A system and a method for semi-automatic video editing is provided herein. The method may include in one embodiment the following steps: processing a media stream comprising at least one of: a plurality of images and a video stream, to extract metadata relating to at least one characteristic of the media stream; displaying to a user the extracted metadata; receiving from the user an instruction to generate a modified media stream wherein said instruction is responsive to the at least one characteristic represented by the extracted metadata; and generating a modified media stream, in response to said instruction. The system may implement the aforementioned method using a computer processor, a display, and a user interface. |
| US09570105B1 |
Magnetic recording system for real time and retry multi-dimensional signal equalization
Systems and methods are disclosed for data processing, and more particularly for equalizing a data signal during both real time (i.e., on the fly) and retry operation. The system may include a first equalizer circuit operable to equalize a first sample set, and a second equalizer circuit operable to equalize a second sample set. The system may include a third equalizer circuit operable to equalize a summed data set to yield a third equalized output. The system may include a summation circuit connected to the first equalizer circuit, the second equalizer circuit, and a switch circuit. The summation circuit is operable to sum at least the first equalized data set and the second equalized data set to yield the summed data set. The switch circuit selectively provides the third equalized data set to the summation circuit. |
| US09570101B2 |
Magnetic adhesion layer and method of forming same
A device having an air bearing surface and a method of forming the device are disclosed. The device can include a writer portion including a surface at the air bearing surface of the device, a magnetic adhesion layer disposed proximate at least a portion of the surface of the writer portion, and an overcoat disposed proximate at least a portion of the magnetic adhesion layer such that the magnetic adhesion layer is between the at least a portion of the surface of the writer portion and the overcoat. |
| US09570100B1 |
Two-dimensional magnetic recording device with center shield stabilized by recessed AFM layer
A two-dimensional magnetic recording (TDMR) read head with an antiferromagnetic (AFM) layer recessed behind a center shield. The TDMR read head comprises a first read sensor and a center shield over the first read sensor, wherein the center shield has a first thickness at an air-bearing surface (ABS) and a second thickness at a back surface, the first thickness being greater than the second thickness. A ferromagnetic layer is disposed over a portion of the center shield, wherein the ferromagnetic layer is recessed from the ABS. The TDMR read head also includes an antiferromagnetic layer over the ferromagnetic layer and a second read sensor over the antiferromagnetic layer. By recessing the AFM layer away from the ABS, the down-track spacing between read sensors is reduced, thereby improving TDMR read head performance. |
| US09570099B2 |
Magnetoresistive devices and methods for manufacturing magnetoresistive devices
A magnetoresistive device that can include a magnetoresistive stack and an etch-stop layer (ESL) disposed on the magnetoresistive stack. A method of manufacturing the magnetoresistive device can include: depositing the magnetoresistive stack, the ESL and a mask layer on a substrate; performing a first etching process to etch a portion of the mask layer to expose a portion of the ESL; and performing a second etching process to etch the exposed portion of the ESL and a portion of the magnetoresistive stack. The method can further include depositing a photoresist layer on the hard mask before the first etching process and removing the photoresist layer from the hard mask following the first etching process. The first and second etching processes can be different. For example, the first etching process can be a reactive etching process and the second etching process can be a non-reactive etching process. |
| US09570098B2 |
Methods of forming near field transducers and near field transducers formed thereby
A method of forming a near field transducer (NFT), the method including the steps of depositing a plasmonic material; depositing an encapsulant material on at least a portion of the plasmonic material; and implanting ions into at least a portion of the plasmonic material through the encapsulant material. |
| US09570097B1 |
Tape head with write pole having multiple layers superimposed in a direction perpendicular to the contact plane
A tape head, configured to contact a magnetic tape, at the level of a contact plane, for writing to the tape, in operation is provided. The tape head includes a transducer, the latter being a write element, configured to write to the magnetic tape, in operation. The transducer includes a layered write pole, the latter comprising a set of two or more superimposed layers of distinct materials, the layers superimposed in a direction perpendicular to the contact plane. A saturation magnetization of each of two material layers of the set is between 1.0 to 2.3 Tesla. A contrast between the saturation magnetizations of the two material layers of the set is between 32% and 130%, the contrast defined as 100×(Bs,max/Bs,min−1), where Bs,max and Bs,min respectively denote a largest one and the smallest one of the saturation magnetizations of the two material layers of the set. |
| US09570096B2 |
Read path compensation for SNR and signal transfer
A method and apparatus is provided for extending a read bandwidth and increasing a high-frequency signal-to-noise ratio (SNR) of a front-end of a read path of a hard disk drive (HDD) by introducing a high impedance section at the front-end of the read path. The high impedance section may mitigate capacitive effects found at the front-end of the read path, thereby improving signal transfer by extending the read bandwidth. |
| US09570095B1 |
Systems and methods for instantaneous noise estimation
In accordance with an implementation of the disclosure, systems and methods are provided for providing an estimate for noise in a speech signal. An instantaneous power value is received that corresponds to a frequency index of a portion of the speech signal. A first weighted power value is updated based on the instantaneous power value and a first weighting parameter. A second weighted power value is updated based on the first weighed power value and a second weighting parameter. An estimate of the noise is computed from the instantaneous power value and the second weighted power value. |
| US09570094B2 |
Multisensory speech detection
A computer-implemented method of multisensory speech detection is disclosed. The method comprises determining an orientation of a mobile device and determining an operating mode of the mobile device based on the orientation of the mobile device. The method further includes identifying speech detection parameters that specify when speech detection begins or ends based on the determined operating mode and detecting speech from a user of the mobile device based on the speech detection parameters. |
| US09570085B2 |
Apparatus and method for efficient synthesis of sinusoids and sweeps by employing spectral patterns
An apparatus for generating an audio output signal based on an encoded audio signal spectrum is provided. The apparatus has a processing unit for processing the encoded audio signal spectrum to obtain a decoded audio signal spectrum having a plurality of spectral coefficients, wherein each of the spectral coefficients has a spectral location within the encoded audio signal spectrum and a spectral value. Moreover, the apparatus has a pseudo coefficients determiner for determining one or more pseudo coefficients. Furthermore, the apparatus has a replacement unit for replacing at least one or more pseudo coefficients by a determined spectral pattern to obtain a modified audio signal spectrum, wherein each of at least two pattern coefficients has a spectral value. Moreover, the apparatus has a spectrum-time-conversion unit for converting the modified audio signal spectrum to a time-domain. |
| US09570084B2 |
Processing method and system for identifying data by an audio conversion device
A processing method for identifying data by an audio conversion device includes: connecting the audio conversion device to a first terminal; sending an identification code stored in the audio conversion device to the first terminal, and sending the identification code to a server via the first terminal, wherein the identification code is used to identify the audio conversion device; obtaining user data; uploading the user data to the server, such that the server stores a correspondence between the identification code and the user data; connecting the audio conversion device to a second terminal; sending the identification code stored in the audio conversion device to the second terminal; sending a data obtaining request containing the identification code to the server; and receiving the user data sent corresponding to the identification code in response to the data obtaining request, or receiving multimedia data matching multimedia using feature information in the user data. |
| US09570079B1 |
Generating call context metadata from speech, contacts, and common names in a geographic area
A computer detects a connected voice or video call between participants and records a brief media sample. Speech recognition is utilized to determine when the call is connected as well as to transcribe the content of the audio portion of the media sample. The recorded media sample and transcribed content is associated with the connected voice or video call such that a user may reference it at a later point. The computer additionally suggests creating or editing contact information associated with the participants of the connected voice or video call based on the transcribed content. |
| US09570077B1 |
Routing queries based on carrier phrase registration
In general, the subject matter described in this specification can be embodied in methods, systems, and program products for receiving a voice query at a mobile computing device and generating data that represents content of the voice query. The data is provided to a server system. A textual query that has been determined by a speech recognizer at the server system to be a textual form of at least part of the data is received at the mobile computing device. The textual query is determined to include a carrier phrase of one or more words that is reserved by a first third-party application program installed on the computing device. The first third-party application is selected, from a group of one or more third-party applications, to receive all or a part of the textual query. All or a part of the textual query is provided to the selected first application program. |
| US09570072B2 |
System and method for noise reduction in processing speech signals by targeting speech and disregarding noise
An exemplary noise reduction system and method processes a speech signal that is delivered in a noisy channel or with ambient noise. Some exemplary embodiments of the system and method use filters to extract speech information, and focus on a subset of harmonics that are least corrupted by noise. Some exemplary embodiments disregard signal harmonics with low signal-to-noise ratio(s), and disregard amplitude modulations that are inconsistent with speech. An exemplary system and method processes a signal that focuses on a subset of harmonics that are least corrupted by noise, disregards the signal harmonics with low signal-to-noise ratio(s), and disregards amplitude modulations that are inconsistent with speech. |
| US09570068B2 |
Automatic accuracy estimation for audio transcriptions
Embodiments of the present invention provide an approach for estimating the accuracy of a transcription of a voice recording. Specifically, in a typical embodiment, each word of a transcription of a voice recording is checked against a customer-specific dictionary and/or a common language dictionary. The number of words not found in either dictionary is determined. An accuracy number for the transcription is calculated from the number of said words not found and the total number of words in the transcription. |
| US09570067B2 |
Text-to-speech system, text-to-speech method, and computer program product for synthesis modification based upon peculiar expressions
According to an embodiment, a text-to-speech device includes a receiver to receive an input text containing a peculiar expression; a normalizer to normalize the input text based on a normalization rule in which the peculiar expression, a normal expression of the peculiar expression, and an expression style of the peculiar expression are associated, to generate normalized texts; a selector to perform language processing of each normalized text, and select a normalized text based on result of the language processing; a generator generate a series of phonetic parameters representing phonetic expression of the selected normalized text; a modifier modifies a phonetic parameter in the normalized text corresponding to the peculiar expression in the input text based on a phonetic parameter modification method according to the normalization rule of the peculiar expression; and a output unit to output a phonetic sound synthesized using the series of phonetic parameters including the modified phonetic parameter. |
| US09570059B2 |
Cadence-based selection, playback, and transition between song versions
A system and methods for acquiring cadence and selecting a song version based on the acquired cadence are disclosed. If the system detects a new cadence, then a new song version that corresponds to the new cadence can be played. The new song version playback can start in a corresponding position as the location of playback in a currently-playing song version. Each related song version shares one or more characteristics, such as melody, but is different in at least one characteristic, such as tempo. |
| US09570057B2 |
Audio signal processing methods and systems
Described are methods and systems of identifying one or more fundamental frequency component(s) of an audio signal. The methods and systems may include any one or more of an audio event receiving step, a signal discretization step, a masking step, and/or a transcription step. |
| US09570055B2 |
System and method for automatically converting textual messages to musical compositions
A method for converting textual messages to musical messages comprising receiving a text input and receiving a musical input selection. The method includes analyzing the text input to determine text characteristics and analyzing a musical input corresponding to the musical input selection to determine musical characteristics. Based on the text characteristic and the musical characteristic, the method includes correlating the text input with the musical input to generate a synthesizer input, and sending the synthesizer input to a voice synthesizer. The method includes receiving a vocal rendering of the text input from the voice synthesizer, generating a musical message from the vocal rendering and the musical input, and outputting the musical message. |
| US09570047B2 |
Interactive electronically presented area representation
The present invention provides computerized systems and methods for providing electronically presented interactive area representation, such as a map, and information associated therewith. A user can select text, imagery, or other information presented on the map and associated with one or more items or locations, causing presentation of information relating to the associated one or more items or locations, such as appropriate contact information or a hyperlink to an appropriate Web site. Additionally or alternatively, a user can input or select, based on a query or otherwise, information relating to one or more items or locations associated with text, imagery, or other information presented on the map, causing presentation of an indication of one or more locations of the associated text, imagery, or other information on the map. A magnifier feature allowing internal navigation within the map can be provided. Additionally, animated images can appear to move over the map. |
| US09570046B2 |
Method and apparatus for rendering content
An approach is provided for rendering content based on chunks and layers. A request is received to render content at a device. One or more layers of the content are determined. One or more patterns are determined corresponding to one or more of the layers. One or more chunks are determined based, at least in part, on the one or more patterns. At least one of the layers and corresponding one or more chunks are determined to be rendered separately from the other layers. |
| US09570043B2 |
Method for processing RGB data and system for the same
The present invention relates to the art of color space conversion technique, and discloses a method for processing RGB data and a system for the same. The method comprises: S1: converting input values of three colors RGB into a HSV color space; S2: adjusting a brightness value V while keeping a hue value H and a saturation value S unchanged in the HSV color space; S3: converting the H, S, V values processed by step S2 from the HSV color space to the R, G, B, W color space to display. By converting the RGB color space to the HSV color space firstly, then enhancing the brightness V while keeping H, S unchanged in the HSV color space, and finally converting the HSV color space to the RGBW color space, it can be achieved that the brightness for display is enhanced while better hue, color saturation and natural color transition are maintained at the same time. |
| US09570042B2 |
Flexible display device and method of controlling the same
Provided are a flexible display device and a method of controlling the same. The flexible display device includes: a display unit including a first display area and a second display area bendable with respect to the first display area; and a control unit correcting at least one of a brightness and color coordinate of an image to be displayed in at least one of the first display area and the second display area according to a degree of bending between the first display area and the second display area. |
| US09570041B2 |
Selective monitor control
Reducing energy usage by a monitor includes a map manager between a monitor interface and a processor that divides a display area of a monitor into areas and stores display information in a staging area. The map manager distinguishes an active window selected by a user from the remainder inactive, unselected areas of a display, and further determines a used subset of areas within the active window distinguished from the remainder unused areas as a function of a user preference. Accordingly, the map manager drives the monitor at each of the used area active window areas with the processor display information stored in the staging area at a normal luminance specified by the processor display information, and at each of the remainder unused, inactive and unselected areas of the total display area at a reduced luminance lower than the specified normal luminance. |
| US09570040B2 |
Display device
A display device includes a color transformer and an image controller. The color transformer receives and transforms a three-color image into a four-color image. The four-color image includes a red image, a green image, a blue image, and a white image. The image controller calculates decrement offsets of the red image, the green image, and the blue image, and a compensation value of the white image. The image controller calculates gray level values of the red image, the green image, and the blue image when a value of the white image is zero. The image controller respectively calculates a red image control signal, a green image control signal, and a blue image control signal based on the gray level values and the decrement offsets, and the image controller calculates a white image control signal based on the gray level values and the compensation value of the white image. |
| US09570035B2 |
Display device
A display device includes a display unit including pixels in an area defined by a plurality of scan lines and a plurality of data lines, a scan driving unit configured to apply a plurality of scan signals to the scan lines, a data driving unit configured to apply a plurality of data signals to the data lines, an inspection circuit unit configured to apply a plurality of inspection signals to the data lines, a plurality of inspection pads configured to transmit a plurality of inspection control signals to the inspection circuit unit, a plurality of first inspection lines electrically connecting the inspection circuit unit to the inspection pads, and a plurality of second inspection lines branching off from the first inspection lines and electrically connecting the inspection circuit unit to the data driving unit. |
| US09570029B2 |
Display device
A gate driver drives a display panel. First and second gate pulse generator circuits each drives a high supply voltage onto respective gate lines via respective high drive transistors during a gate pulse period and discharge their respective gate lines through the respective high drive transistors during a discharge period. A gate pulse modulation circuit provides the high supply voltage to the first gate pulse generator and the second gate pulse generator via an output terminal during the first pulse period and the second pulse period and couples a source terminal of the first high drive transistor and a source terminal of the second high drive transistor to a first return line via the output terminal during the first and second discharge periods. |
| US09570027B2 |
Method of protecting a gate driver circuit and display apparatus performing the method
A method of method of protecting a gate driver circuit configured to provide a gate line of a display panel with a gate signal includes generating a clock signal to drive the gate driver circuit, sensing an output current of the clock signal, detecting an overcurrent of the clock signal based on an overcurrent determining factor, determining whether the clock signal is in an overcurrent condition based on a count number of the overcurrent, generating a shutdown signal when the clock signal is in the overcurrent condition and blocking the clock signal from being applied to the gate driver circuit based on the shutdown signal. |
| US09570020B2 |
Display device having subpixels of four colors in each pixel
A disclosed display device includes a display panel including a plurality of data lines and a plurality of gate lines intersecting the data lines, and a pixel array comprising a plurality of pixels arranged in a matrix form, each pixel being divided into a subpixel having a first color, a subpixel having a second color, a subpixel having a third color, and a subpixel having a fourth color. Two adjacent subpixels in a horizontal line of the pixel array share one of the data lines. For at least one of the first, second, third, and fourth colors, subpixels having a same color are arranged in a hexagonal shape on four adjacent horizontal lines or a diamond shape on three adjacent horizontal lines of the pixel array. |
| US09570017B2 |
Liquid crystal display device and driving method thereof
To provide a hold-type display device without a problem of motion blur and a driving method thereof. The length of a period for displaying a blanking image in one frame period is controlled in accordance with a control parameter showing the degree of motion blur, and the level of a signal supplied to a display element is changed in accordance with the length of the period for displaying the blanking image. Accordingly, the hold-type display device without a problem of motion blur and the driving method thereof can be provided. |
| US09570001B2 |
Pixel circuit, display panel, display device and driving method
An organic light-emitting diode pixel circuit addresses problems associated with power consumption of a conventional 3D image display using two displayed adjacent frames of image signals that are spaced by a black picture. The pixel circuit includes a signal pre-storage module for storing a signal in a current frame of image signal, when the voltage of a first drive signal is higher than the voltage of a second drive signal and a gate line connected with the pixel is enabled; and a drive module for driving a drive transistor when the voltage of the first drive signal is higher than the voltage of the second drive signal; and to generate a current drive signal from the signal stored in the signal pre-storage module in the current frame of image signal, when the voltage of the first drive signal is not higher than the voltage of the second drive signal. |
| US09570000B2 |
Pixel circuit and driving method thereof, organic light-emitting display panel and display apparatus
The present disclosure relates to the field of organic light-emitting display, and provides a pixel circuit, a driving method thereof, an organic light-emitting display panel and a display apparatus, comprising a driving transistor, a first storage capacitor, a collecting unit, a writing unit and a light-emitting unit; wherein, the collecting unit is used for collecting the threshold voltage of the driving transistor and storing the threshold voltage into the first storage capacitor, under the control of the first scan signal; the writing unit is used for storing the data voltage inputted from the input terminal for the data voltage under the control of the second scan signal; and the light-emitting unit is used for emitting lights, driven by the data voltage and a voltage inputted from the input terminal for the controllable low voltage, under the control of the light-emitting control signal. Thus an organic light-emitting device is not affected by the threshold voltage shift of the driving transistor, which may enhance the image uniformity of the organic light-emitting display panel effectively, slow down the decay speed of an organic light-emitting device and ensure the uniformity and a constancy of brightness of the organic light-emitting display panel. |
| US09569998B2 |
Display device and method of driving the same
A display device includes a signal receiver, a signal generator, and a signal corrector. The signal receiver receives an image signal. The signal generator generates a data signal for each of a first color pixel and a second color pixel based on the image signal. The signal corrector generates corrected data for the first color pixel based on the data signal for the second color pixel in a single driving mode. The first color pixel and the second color pixel emit light of different grayscale values of a same color. The first color pixel is driven and the second color pixel is not driven in the single driving mode. |
| US09569991B2 |
Pixel circuit, display device, and inspection method
Checking failures in transistors including driving transistors, switching transistors, and sampling transistors before light emitting elements are formed in a display device. I-V characteristics including threshold voltage of the driving transistor 10C in one pixel circuit can be detected. In a pixel circuit, the sampling transistor 10A and switching transistor 10D are made conductive and the signal potential is given to the gate electrode of the driving transistor 10C from the signal line DTCm. At this time, the current which flows between the drain electrode and source electrode of driving transistor 10C flows through the switching transistor 10D and a reference potential line Vref_r to a test point, and is measured by a current measuring device connected to the test point. |
| US09569989B2 |
Panel driver IC and cooling method thereof
A panel driver integrated circuit (IC) and a cooling method of the panel driver IC are provided. The panel driver IC includes a data encoder, a level shifter, a Digital-to-Analog Converter (DAC), a rearrangement circuit and an output buffer. The data encoder receives and selectively changes an original data for outputting to the level shifter. An input terminal and an output terminal of the level shifter are coupled to an output terminal of the data encoder and a data input terminal of the DAC, respectively. The output terminals of the rearrangement circuit are respectively coupled to the reference voltage input terminals of the DAC for providing different reference voltages. The rearrangement circuit correspondingly rearranges the order of the reference voltages according to the operation of the data encoder. An input terminal of the output buffer is coupled to an output terminal of the DAC. |
| US09569986B2 |
System and method for gathering and analyzing biometric user feedback for use in social media and advertising applications
A system and method for measuring biologically and behaviorally based responses to social media, locations, or experiences and providing instant and continuous feedback in response thereto. The system and method of the invention is capable of monitoring stress levels and well-being and may be implemented using a cloud-based infrastructure for remote monitoring. |
| US09569985B2 |
Transcatheter heart valve delivery deployment simulator
An apparatus for simulation of an anatomical structure may include a left ventricle component having an inlet port configured to receive fluid flow therethrough, an aortic arch component having an outlet port configured to receive fluid flow therethrough, an aortic annulus component attached to and disposed between the left ventricle component and the aortic arch component, and an introducer configured to receive an elongated catheter assembly therethrough. The aortic annulus component may have an inner surface including simulated stenotic nodules. The introducer may be in fluid communication with at least one of the left ventricle component and the aortic arch component. |
| US09569984B2 |
Recording, monitoring, and analyzing driver behavior
A system that monitors, records and analyzes driver performance includes: a vehicle sensor module that receives data from a set of sensors that each measure a driving characteristic associated with a vehicle; a map data access module that retrieves map data elements indicating various features associated with a path of the vehicle including a set of previously-defined segments, each segment having a set of associated joints each including a set of associated attributes including a set of fixed attributes with unchanging values; and a driver behavior engine that monitors and evaluates driver performance; calculates mathematical differences between a set of evaluation curves and each of multiple corresponding performance curves based on the set of measured driving characteristics, where the mathematical differences are quantified by determining a geometrical area between each evaluation curve and each corresponding performance curve, where the curves are associated with a particular driver and a particular trip. |
| US09569983B2 |
Conversion wheel
Latin-derived letters may be converted into Arabic letters by performing processing associated with causing, with a display module in communication with a processor circuit and a display, the display to display a wheel comprising a Latin-derived letter and a corresponding Arabic letter; performing processing associated with receiving, with a UI module in communication with the processor circuit and an input device, a selection of a Latin-derived letter via the input device; and performing processing associated with causing, with the display module, the display to display an Arabic letter corresponding to the Latin-derived letter in a window on the wheel. |
| US09569979B2 |
Physiological and cognitive feedback device, system, and method for evaluating a response of a user in an interactive language learning advertisement
An embodiment is a physiological and cognitive feedback device, system, and method for evaluating a response of a user in an interactive language learning advertisement. Foreign language lessons are provided at no cost to consumers online in exchange for the consumers' feedback on the products or services embedded in the language lessons. The language lessons may use television advertisements as course material, serving both educational and promotional purposes. Revenues are generated through product placement opportunities as well as consumer survey responses that are a part of the lessons. |
| US09569974B2 |
Method and assembly for guidance of an aircraft during a low-altitude flight
A method and assembly for guidance of an aircraft during a low-altitude flight. The guidance assembly comprises a memory forming part of a flight management system, which is configured to store an active flight trajectory and any new flight trajectory, generated by the flight management system, and a memory forming part of a guidance system, which is configured to also store the flight trajectory and any new flight trajectory, which are received from the flight management system, the guidance assembly being configured to periodically transmit from the guidance system to the flight management system identification codes for the flight trajectories recorded in the memory of the guidance system. |
| US09569973B2 |
Method of generating and displaying a flare drift vector symbol
The present disclosure is generally directed to a method of generating and displaying a parachute flare drift vector symbol on a navigation display of the aircraft capable of deploying a flare relative to a real-time navigation map. The flare drift vector symbol includes a flare ignition forward/aft distance relative to the aircraft deploying the flare, a flare ignition left/right distance relative to the aircraft deploying the flare, a flare burn vector distance, and a flare burn vector direction. The flare drift vector symbol is generating based on the flare parameters, the wind parameters, the flare drift distance, the flare drift direction and the aircraft parameters. |
| US09569970B2 |
Back-sideways alarming system for vehicle and alarming control method thereof
Provided are a back-sideways alarming system and an alarming control method, which are capable of reducing the generation of a false alarm by detecting a driving road environment of a vehicle and preventing an unnecessary alarm caused by target information generated at a centerline of a road and an outside of a road. The back-sideways alarming system includes: an image acquiring unit configured to acquire road information of a vehicle; a collecting unit configured to collect target information on targets located around the vehicle; and an electronic control unit configured to recognize a lane based on the road information acquired by the image acquiring unit, reset an alarm area according to information on the recognized lane and the road information, and generate an alarm when the target information is located in the reset alarm area. |
| US09569968B2 |
Method and device for the automated braking and steering of a vehicle
A method for the automated braking and/or steering of a vehicle uses at least one sensor system for detecting the vehicle's surroundings, a potential collision object in the vehicle's surroundings, and a relative speed of the vehicle relative to the potential collision object. The activation and/or the sequence of an automated steering intervention and/or an automated braking intervention is determined based on the relative speed. The braking intervention is activated at first when the relative speed is below or equal to a predefined threshold, and the steering intervention is activated at first when the relative speed is above the predefined threshold. |
| US09569966B2 |
Bicycle tracking system with communication hub
A bicycle tracking system for a bicycle rental system includes a number of bicycles each including a bicycle computer configured to record and transmit trip data information. The bicycle computer transmits the trip data to at least one communication hub that is part of the rental system. The communication hub is located at a bicycle rental kiosk. The kiosk includes a parking rack for securely storing a number of bicycles and includes a kiosk radio head configured to receive the trip data from the computer. The kiosk further includes a kiosk computer configured to transmit the trip data to a server, which may provide a user of the system with the trip data in the form of a route map. The system is configured to aggregate the user's trip data from ride-to-ride to provide the user with his or her ride statistics. |
| US09569963B1 |
Systems and methods for informing driver of traffic regulations
Methods and systems for informing a driver of traffic regulations. A method includes detecting a traffic sign notifying the driver of a prohibited turn, alerting the driver of the prohibited turn if the driver activates a vehicle turn signal corresponding to the prohibited turn, and not alerting the driver of the prohibited turn if the driver does not activate the vehicle turn signal corresponding to the prohibited turn. |
| US09569962B2 |
Method for identifying a vehicle detected by a sensor device
The invention relates to a method for assigning an identity certificate (I1, I2) transmitted by a vehicle (16, 18) to an object (O1, O2, O3, O4), which is detected by a sensor device (28) in identification apparatus (22) external to the vehicle. To this end, the identification apparatus receives the identity certificate (I1, I2), measures by means of the sensor device (28) a first value (V1) relating to at least one operating parameter of the object, receives a second value (V1, V2) of the vehicle (16, 18) relating to the at least one operating parameter and determined by the vehicle (16, 18) itself, compares the first value and the second value of each operating parameter with each other and assigns the identity certificate (I1) to the object (O1) if the two values for each operating parameter match. |
| US09569957B2 |
Systems, devices and methods involving device identification
Systems, devices and methods involving device identification are provided. In this regard, a representative system includes: a first device having a first power line and a first connector, the first connector being coupled to the first power line; and a second device having a second power line and a second connector, the second connector being coupled to the second power line and sized and shaped to mate with the first connector such that the first device electrically communicates with the second device; the first device being operative to modulate impedance exhibited at the first power line; the second device being operative to detect the modulated impedance and correlate the modulated impedance with an identification of the first device. |
| US09569952B2 |
Systems and methods for individual tracking using multi-source energy harvesting
The present inventions are related to monitoring movement, and in particular to systems and methods for extending the service life of a monitoring device. |
| US09569951B2 |
Emergency notification apparatus and method
A system, apparatus and method for alerting an emergency responder to an emergency, which includes a processor obtaining data from at least one sensor, determining, that the data indicates an emergency condition, based on the determining, obtaining location information and a unique identifier, and communicating the location information and the unique identifier to a node via a network connection. |
| US09569943B2 |
Alarm arming with open entry point
A magnet and magnetometer may be integrated into a smart home environment and allow it to be placed into an away mode of operation despite an entry point being semi-open. The disclosed implementations can detect a magnetic field strength and determine, based on the detected field strength, an approximate distance that a moveable partition is open. In some configurations, the presence of a second magnetic source can be detected. A notice may be generated based on one or more signals received from the magnetometer. The notice may be sent to a controller, a remote system, a remote device, and/or a client device as disclosed herein. |
| US09569942B2 |
Sensor system for protection of artworks and other valuable objects
Systems, devices, and methods are disclosed for securing a theft-susceptible movable object at a selected location. A security system is positioned at a selected location for protection of a theft-susceptible movable object. The security system includes a magnetic field source adapted to generate a magnetic field that is positionally-associated with a movable object. A monitoring device includes a magnetic sensor and is adapted for placement proximate to the selected location. The monitoring device is adapted to take one or more measurements of the magnetic field and to detect alteration in the measurements caused by movement of the magnetic field source relative to the monitoring device when the movable object is moved from the selected location. Upon detecting the alteration in the measurements of the magnetic field, the monitoring device is adapted to output an electronic warning signal indicating that the movable object has moved from the selected location. |
| US09569937B2 |
Tactile touch screen
A machine (10) is operative to carry out financial transfers responsive to data included on data bearing records including user cards. The machine includes a user interface (15) including a display (24). The user interface includes a card reader (16) which is operative to read data on user cards which identify at least one of user and a user's financial accounts. Records of the financial transfers are provided by a printer (30). A touch screen display module (608) is operative to securely receive manual inputs and/or card data. The touch screen display module includes a contact surface that can be electronically contoured to provide outputs that can be perceived through finger contact with the contact surface. |
| US09569936B2 |
Systems, methods, and devices for playing wagering games with symbol clumps and non-uniform weighting of reel positions
Gaming devices, gaming systems, methods of conducting wagering games, and computer programs for executing wagering games are disclosed. A gaming system is disclosed which includes one or more processors and one or more memory devices storing instructions that, when executed by at least one of the processors, cause the gaming system to: receive a wager to play a wagering game with symbol-bearing reels, each of which has distinct reel positions populated by various symbols, at least one reel bearing a symbol clump; and, display via a display device a randomly determined outcome of the wagering game. Each wagering-game outcome includes predetermined symbols occupying distinct array positions in a displayed array. Each reel position has a weighted probability of occupying an array position in the array. The weighted probabilities are configured such that the symbol clump, when part of a wagering-game outcome, can only land in its entirety in the array. |
| US09569934B2 |
Systems, apparatuses and methods for enhancing gaming experiences
Systems, apparatuses and methods for enhancing winning result opportunities in gaming activities. Embodiments involve identifying award-enhancing opportunities using dice during a current game to determine award-enhancing opportunities for subsequent games based on the dice results. Award-enhancing opportunities may continue over multiple games until a terminating condition is activated, or single bonus rolls of dice may be used to determine multipliers or other modifiers to enhance awards only in a single subsequent game. The award-enhancing opportunities may be triggered by a mystery or random selection process, or may be based on at least a portion of the outcome of the current game. |
| US09569932B2 |
Central determination gaming system and method for providing a persistence game with predetermined game outcomes
A gaming system which provides a persistence game which utilizes predetermined game outcomes. One or more predetermined game outcomes include a persistence game award value. If a predetermined game outcome including such a persistence game award value is selected to be provided to the player in association with a current play of a primary game, the gaming system determines whether to provide this persistence game award value to a player in association with the current play of the primary game, or to store this persistence game award value to be subsequently provided to a player in association with a subsequent play of the primary game. The determination of whether to provide or store the persistence game award value is based on the then current progress of the persistence game (i.e., the current state of an accumulation meter). |
| US09569924B2 |
Systems and methods for play of casino table card games
A system and method for enabling play of a casino table card game. Multiple randomized sets of playing cards of known composition are formed and delivered, and are set by following automatically generated house way instructions. An automatic card shuffler is configured to deliver randomized sets of physical cards, the shuffler equipped with a playing card reading system that reads at least one of a rank and suit of markings on each of the playing cards. A processor receives the read card information from the playing card reading system and determines a composition of each individual set of playing cards dispensed. At least one display is in communication with a processor programmed with house way rules for displaying instructions on how to set hands from a distributed set of cards a house way. Processors of the present invention may also cause a display of a house commission amount. |
| US09569922B1 |
System and methods related to sports leagues
Systems and methods for providing a game related to fantasy sports is described herein where a database includes information associated with live sporting events, a user module receives information associated with the live sporting events, a gaming server communicatively coupled to the database and the computing device is configured to display a list of the live sporting events, receive selections from teams of event outcomes, receive event outcome information from the database, display event outcome information on the user module, and determine whether the team is a winning team or a losing team. Winning teams are awarded points based on the number of losing teams and a predetermined multiplier. Losing teams are deduced points based on the number of winning teams and a predetermined multiplier. Adjusted spreads associated with the live sporting events may be calculated and applied to confer a competitive advantage to the teams. |
| US09569909B2 |
Portable drum-type banknote box and ATM
A portable drum-type banknote box and an ATM having the portable drum-type banknote box. The portable drum-type banknote box includes a shell, a large winding drum gear, a small winding drum gear, a connecting socket and a self-locking mechanism. The self-locking mechanism includes an electromagnet, a first spring, a second spring, a first locking rod, a second locking rod and a pull rod. The upper end of the pull rod is installed to the electromagnet in a paired mode, and the lower end of the pull rod is movably connected with the first locking rod. The portable drum-type banknote box has a small size and light weight, is convenient to assemble/disassemble and move and is capable of performing audit work on multiple ATMs; and achieves a locking function so as to effectively prevent the banknotes from being exposed and rolled out by human. |
| US09569908B2 |
Cash cassette with electronic money seal
The invention relates to a device (10, 30, 40, 50) for receiving notes of value, comprising a base body (12) and a lid (14) for closing an opening of the base body (12). Another aspect of the invention relates to a device (60) for displaying the opening of a lid (14) closing an opening of a base body (12) of a cash box (10, 30, 40, 50, 80). Both devices (10, 30, 40, 50, 60) comprise a sensor (16, 64) for detecting the opening of the lid (14) and a display unit (18). Further, the devices (10, 30, 40, 50, 60) comprise a control unit (20) that controls the display unit (18) in such a manner that, at least when the sensor (16, 64) has detected an unauthorized opening of the lid (14), that the display unit (18) displays information on the opening of the lid (14). |
| US09569902B2 |
Passenger counter
A passenger counter that counts the number of persons who get on/off a vehicle comprising an imaging unit 2 installed at an inside of a vehicle platform; a setting unit 31 configured to set an inner area I corresponding to a passage inside the vehicle, one outer areas B surrounding the inner area I and inside the vehicle and other outer area A surrounding the inner area I and outside the vehicle; and a count determination unit 35 configured to count the number of persons who move from one outer area A(B) to the other outer area B(A) through the inner area I while a door of the platform is opened, not to count the number of persons while the door is closed, and to perform processing of determining a person existing in the inner area I when the opened (closed) door is closed (opened) to be counted. |
| US09569899B2 |
Wearable electronic glasses that move a virtual object in response to movement of a field of view
A method detects a real object with a wearable electronic device and displays a virtual image of the real object with the real object on a display of the wearable electronic device. The wearable electronic device displays movement of the virtual image of the real object to show a task to be completed and detects a completion of the task. The wearable electronic device moves, in response to the virtual image of the real object no longer being within a field of view of the wearable electronic device, the virtual image of the real object to an opposite side of the real object such that the virtual image of the real object is within the field of view. |
| US09569897B2 |
Head mounted display and optical position adjustment method of the same
Disclosed herein is an optical position adjustment method of a head mounted display, the head mounted display including (a) an eyeglass type frame worn on the head of a viewer, and (b) two image display devices for the right and left eyes attached to the frame, and each of the image display devices including (A) an image forming device, and (B) an optical device adapted to receive, guide and emit light emitted from the image forming device, wherein the optical position adjustment method includes the step of: controlling an image signal that is supplied to the image forming device making up at least one of the image display devices so as to control the position of the image displayed on the optical device making up at least one of the image display devices and adjust the mutual positions of the two images. |
| US09569895B2 |
Information processing apparatus, display control method, and program
There is provided an information processing apparatus including a judgment unit for judging an anteroposterior relationship between a shot actual object and a virtual object for each part by use of depth information, and a display control unit for displaying a virtual image in which the virtual object is projected to be overlapped on a shot image in which the actual object is shot based on the anteroposterior relationship judged by the judgment unit. |
| US09569894B2 |
Glass type portable device and information projecting side searching method thereof
Disclosed are a glass-type portable device and a method of searching an information projecting side thereof. In occurrence of information to be displayed, a screen at which a user is staring is analyzed. Candidate UI regions, on which the information is to be displayed on the analyzed screen, are set. An optimum UI region which satisfies a preset condition is selected from the candidate UI regions. Then the information is displayed on the optimum UI region. Under such configuration, the glass-type portable device can effectively display information without blocking a user's view. |
| US09569892B2 |
Image capture input and projection output
Systems and methods are provided for alternating projection of content and capturing an image. The method includes steps of projecting, by a projection device, content at a first rate, projecting, by the projection device, a capture frame at a second rate, and capturing, by an image capture device, an image including the capture frame at the second rate, wherein capturing the image comprises capturing the image when the capture frame is projected. Systems and methods provided herein may provide increased tracking accuracy by a projecting a capture frame that does not obscure features in the image. |
| US09569891B2 |
Method, an apparatus and an arrangement for visualizing information
A method, an apparatus, an arrangement and a computer readable storage medium for determining an image based at least in part on first data having a first representation is provided. The approach comprises determining a projection of an imaging element on the first representation, the imaging element being arranged to at least partly overlap with the first representation, determining a first subset of data as the subset of the first data corresponding to the projection of the imaging element on the first representation, and determining the image based at least in part on the first subset of data. |
| US09569887B2 |
Methods of modelling and characterising heart fiber geometry
The identification and determination of aspects of the construction of a patient's heart is important for cardiologists and cardiac surgeons in the diagnosis, analysis, treatment, and management of cardiac patients. For example minimally invasive heart surgery demands knowledge of heart geometry, heart fiber orientation, etc. While medical imaging has advanced significantly the accurate three dimensional (3D) rendering from a series of imaging slices remains a critical step in the planning and execution of patient treatment. Embodiments of the invention construct using diffuse MRI data 3D renderings from iterating connections forms derived from arbitrary smooth frame fields to not only corroborate biological measurements of heart fiber orientation but also provide novel biological views in respect of heart fiber orientation etc. |
| US09569884B2 |
Method for generating shadows in an image
As to generate shadows in an image, the method comprises the steps of: Computing a depth-map that comprises an array of pixels, wherein pixels in the depth-map are associated to a single value corresponding to depth value that indicates a depth from a light source to a portion of nearest occluding object visible through the pixel, projecting a point visible through a pixel of said image into a light space, the result of said projection being a pixel of said depth-map, calculating a distance between the said visible point and the light source, fetching the depth value associated to said pixel of depth-map, computing, for said pixel of said image, an adaptive bias as a function of a predetermined base bias and a relationship between the normal of a surface on which the said visible point is located and incident light direction at said visible point, comparing for said pixel in the image, the distance between said visible point and the light source with the sum of the corresponding depth map value and said adaptive bias, labelling said point visible through said pixel as lit or shadowed according to said comparison. |
| US09569882B2 |
Four corner high performance depth test
One or more apparatus and method for multi-pixel/sample level depth testing in a graphics processor is described. In embodiments, a bounding-box of variable size over which a depth test is to be performed is determined based on the pattern of lit pixels or samples within rasterizer tile. A multi-corner depth test may be performed between a source depth data plane and a destination depth plane within a source depth data bound where destination depth data is continuous within the source data bound. A range-based depth test may be performed in response to the destination data being discontinuous. Source depth data prevailing in the depth test may be stored in a compressed plane equation format in response to the source data being continuous within the source data bound, and may be stored as min/max depth data if discontinuous. |
| US09569881B2 |
Method and apparatus processing ray bounding box intersection
A method of processing ray tracing comprising acquiring information about a light source and a bounding box that are located in a three-dimensional graphics (3D) graphics environment, the bounding box containing an object; testing whether a ray generated by the light source intersects the bounding box along each of first to third coordinate axes that define the 3D graphics environment based on the acquired information; and rendering the object in response to a result of the testing being that the ray intersects the bounding box along all of the first through third coordinate axes. |
| US09569878B2 |
Sample culling based on linearized 5D edge equations
Thin invention introduces a five-dimensional rasterization technique that uses a test based on triangle edges in order to obtain high efficiency. A compact formulation of five-dimensional edge equations is used to derive a conservative triangle edge versus tile test in five dimensions, expressed as an affine hyperplane. |
| US09569875B1 |
Ordered list management
Unordered list operations are used to create and modify ordered lists of components. Each list operation specifies an intention to change some aspect of an ordered list, such as the addition or removal of components or a change in the sequence of components. List operations are associated with intrinsic and extrinsic time-independent attributes. Multiple users can collaborate on an ordered list by specifying their own list operations. List operations are cumulative and do not destructively overwrite list operations from previous pipeline activities. An embodiment of the invention interprets list operations in a time independent manner using intrinsic and extrinsic list operation attributes. Because list operations are processed in a time-independent manner, multiple users may collaborate in any order on the creation of an ordered list, including simultaneously editing the ordered list, and still obtain consistent results. |
| US09569874B2 |
System and method for perspective preserving stitching and summarizing views
A method and a system of stitching a plurality of views of a scene, the method including extracting points of interest in each view to include a point set from each of the plurality of image views of the scene, matching the points of interest and reducing an outlier, grouping the matched points of interest in a plurality of groups, determining a similarity transformation with a smallest rotation angle for each grouping of the match points, generating virtual matching points on a non-overlapping area of the plurality of image views, generating virtual matching points on an overlapping area for each of the plurality of image views, and calculating piecewise projective transformations for the plurality of image views. |
| US09569873B2 |
Automated iterative image-masking based on imported depth information
A method, process, and associated systems for automatically selecting and masking areas of a still image or frame of a video clip as a function of depth-information metadata embedded into the image or frame. An image-editing or video-editing workstation receives an image or frame into which has been embedded a set of depth values. Each depth value identifies a distance from the camera position of an object depicted by a pixel of the image or frame. When a user directs the workstation to automatically select or mask a region of the image or frame, the workstation uses the depth values, optionally in conjunction with other graphical properties of each pixel, to automatically select which pixels to include in the selection or mask such that the selection or mask identifies an approximate area of the image or frame that represents a three-dimensional object. |
| US09569870B2 |
System and method for generating multiple master glyph
Disclosed are a system and a method for generating multiple a master glyph. The system for generating a multiple master glyph according to the present invention includes: a user terminal receiving a grapheme from a user and converting the grapheme into a grapheme image; a server extracting vector data of the grapheme image; and an editor generating a basic grapheme glyph and an extended grapheme glyph and grouping the basic grapheme glyph and the extended grapheme glyph into a MMG. |
| US09569869B2 |
Consolidation and customization of graph-based models
Techniques of consolidation and customization of graph-based models are disclosed. A first graph-based representation of a first model can comprise a first set of nodes corresponding to data items of the first model, and a second graph-based representation of a second model can comprise a second set of nodes corresponding to data items of the second model. Matching nodes between the first set of nodes and the second set of nodes can be identified. Matching topological features between the first set of nodes and the second set of nodes can be identified. Matching dependency characteristics between the first set of nodes and the second set of nodes can be identified. A third graph-based representation of a consolidated model can be created based on the matching nodes, the matching topological features, and the matching dependency characteristics. |
| US09569858B2 |
Cloud-based system for water analysis
A cross-platform web-based system for water testing capable of measuring, analyzing and maintaining the quality of water using a plurality of different test strip readers each configured to obtain a digital image of a reagent test strip, normalize and analyze color information in the digital image by colorimetric analysis, and to transmit a set of colorimetric values corresponding to said digital image to a cross-platform cloud-based system for analysis. The cloud-based server(s) receive the colorimetric values, calculate analyte parts-per-million (ppm), and return the calculated analyte ppm with consistant results no matter which reader is used. |
| US09569855B2 |
Apparatus and method for extracting object of interest from image using image matting based on global contrast
An apparatus and method for extracting an object of interest from an image using image matting are disclosed herein. The apparatus for extracting an object of interest from an image using image matting includes a saliency map generation unit, a trimap generation unit, and an alpha map generation unit. The saliency map generation unit generates a saliency map corresponding to an object of interest inside an input image using a color space probability distribution corresponding to the input image. The trimap generation unit generates meta-trimaps using filters, and generates a trimap by clustering the meta-trimaps. The alpha map generation unit generates an alpha map using the trimap and a matting Laplacian matrix, and extracts the object of interest based on image matting using the alpha map and the input image. |
| US09569846B2 |
Ophthalmic reference image selection
A method for selecting a representative image of an eye from a plurality of captured images, comprises associating neighboring images from the plurality of images with each other to determine a spatial relationship (shift) of the images and an initial quality value for each image. The method determines an accumulated quality value for at least one portion of each image using the initial quality values corresponding to those other images of the plurality of images that are spatially related with the portion. The spatial relationship between a portion of an image and the other images is identified based of the determined spatial arrangement of the images. The method selects a representative image from the plurality of images using, for each image, at least the initial quality value for the image and the accumulated quality value of at least one portion of the image. |
| US09569845B2 |
Method and system for characterizing cell motion
A method and system for characterizing cell motion comprising: receiving image data corresponding to a set of images of a cell culture captured at a set of time points; segmenting, from at least one image of the set of images, a cell subpopulation from the cell culture; determining a resting signal for the cell subpopulation; determining a single-peak motion signal based upon the set of images, the set of time points, and the resting signal; detrending the single-peak motion signal of the cell subpopulation based upon the resting signal; determining values of a set of motion features of the cell subpopulation, thereby characterizing cell motion; and clustering the cell subpopulation with at least one other cell subpopulation based upon at least one of the single-peak motion signal and a value of the set of motion features. |
| US09569842B2 |
Medical imaging apparatus
A medical imaging apparatus includes a reconstruction unit, a ROI setting unit, and a controller. The reconstruction unit receives projection data that is based on radiation detected by a detector, divides the projection data into a plurality of subsets, and apply a reconstruction process to the subsets by successive approximation to successively generate images. The ROI setting unit sets a ROI in the images. The controller obtains a variation value indicating a change in image quality from the images, and, when the variation value reaches a predetermined value, instructs the reconstruction unit on a new subset count less than the number of the subsets to sequentially reconstruct subsets as many as the new subset count into an image. The reconstruction unit assigns a weight to the projection data based on the ROI, and divides the projection data into the subsets based on the weight. |
| US09569837B2 |
Label inspection system and method
A label inspection system fixture (1) has a scanner and housing (10) for performing full inline or offline inspection within a printer (20). The fixture (1) comprises a control circuit (5) with a processor within a curved guide plate (6). The scanner (10) communicates with the circuit (5), which in turn communicates with a host computer (VPU). The VPU identifies regions in a scanned label and applies to each region an inspection tool associated with that region. At least some of said tools include a stored training image and associated test data defining said regions and inspection criteria for the regions. |
| US09569830B2 |
Image processing method and electronic apparatus with image processing mechanism
An image processing method comprising: (a) acquiring a first depth value for a first object in a first image; and (b) altering image effect for the first object according the first depth value when the first object is pasted onto a second image. |
| US09569826B2 |
Radiographic image processing device, radiographic image processing method, and recording medium
A radiographic image processing device includes: an image acquisition section that acquires a subject image detected by a shielded detection portion and a non-shielded detection portion; an area information acquisition section that acquires area information which is information for specifying a non-shielded image area and a shielded image area; and a scattered ray suppression section that estimates spreading of scattered rays generated in a non-shielded subject portion, estimates that scattered rays that spread to the non-shielded image area from a shielded subject portion are not present, calculates a scattered ray component in each position in the non-shielded image area as the estimated scattered rays reach each position in the non-shielded image area, and suppresses the scattered ray component in each position in the non-shielded image area according to the calculated scattered ray component. |
| US09569820B2 |
Method and apparatus for image correction
Image correcting methods and apparatuses for removing speckles from an image are provided. The image correcting method includes selecting a first region in an image; removing a speckle from a second region except for the first region from the image by using image information at a predetermined frequency band in the image; and increasing a contrast level of the first region. |
| US09569815B1 |
Optimizing electronic display resolution
Systems and methods for optimizing resolution of an electronic display device are disclosed. A computer program product for optimizing display resolution of an electronic device includes a computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a computing device to cause the computing device to: detect the presence of at least one user; determine an identity of the at least one user; obtain, from a user data storage module, personalized optimal resolution data of the at least one user; and adjust the resolution of the electronic device display based on the personalized optimal resolution data. |
| US09569814B2 |
Display control apparatus, image capture apparatus, display control method, and image capture apparatus control method
A display control apparatus displays, together with an image on a display unit, items related to a plurality of objects in the image. At this time, for the plurality of objects in the image, the display control apparatus displays items related to the respective objects at display positions having a predetermined relative positional relationship with the objects. The display control apparatus decides the order of priority of the plurality of objects. In case that the area of a main object having a highest decided priority level and the display position having the predetermined relative positional relationship for an item related to another object overlap each other, the display control apparatus adjusts the display position of the item related to the other object to eliminate the overlapping, and displays the item related to the other object. |
| US09569809B2 |
Pattern matching method and electronic device therefor
A method and apparatus verify whether a pattern extracted from an image or a video frame is identical to an original pattern in an electronic device. The method includes extracting a pattern and converting the extracted pattern into a first pattern of a binarized grid type, verifying pixel information of the first pattern, and determining whether the first pattern is identical to an original pattern in consideration of a similar degree between the pixel information of the first pattern and pixel information of the original pattern. |
| US09569804B2 |
Systems and methods for energy consumption and energy demand management
Various of the disclosed embodiments contemplate a computer-implemented method of energy consumption and energy demand management in a building. In accordance with some embodiments, interval energy data of a specific building may be collected with a fixed time interval and paired with local historical weather data and other forms of operational data, as well as financial data including historical utility bills, utility rate structures and billing cycle dates. Paired energy interval data and the local historical weather data may be analyzed according to one or more analytic algorithms. |
| US09569803B1 |
System and method for conserving water and optimizing land and water use
Software, databases, computer models, and a series of monitoring devices are provided that are used collectively to optimize farming operations for the purpose of efficiently utilizing the water right associated with the land while recognizing the potential to transfer a proportional amount of the water right in a lease or sale arrangement to other water users. The contemplated system encourages water conservation by allowing those owning water rights to determine the feasibility of changed farming practices intended to maximize net returns and profitability of their overall farming operations. |
| US09569801B1 |
System and method for uniting user accounts across different platforms
Individual users may log into the same online game from multiple different social networking platforms. The disclosed technology provides a way to unite users' accounts such that users that have logged into the online game from different social networking platforms can have their progress in the online game preserved regardless of which social networking platforms the user logged in from. Business intelligence about differences in the user's value when logging in from the different social networking platforms can be determined and incentivizing actions can be performed on the social networking platforms based on the business intelligence. |
| US09569797B1 |
Systems and methods of presenting simulated credit score information
In an embodiment, a computer system receives credit information relating to a consumer, and calculates a credit score associated with the consumer. The system constructs a credit score scenario user interface. The system maintains a plurality of credit score simulation scenarios, and calculates a plurality of simulated credit scores associated with respective credit score simulation scenarios. The system also constructs a credit score simulation control interface. The system maintains a plurality of credit score simulation parameters, and generates a user interface with a graphical indication of the calculated credit score and a plurality of sliders, each slider being divided into segments that are colored to graphically indicate the likely effect of repositioning the slider within the respective segment. When the user repositions the sliders, the graphical indication of the calculated credit score is adjusted, based on a recalculation of the credit score. |
| US09569794B2 |
Apparatus and method for managing data records for associated seals from products
An apparatus is configured to manage N data records for N associated seals from products. The apparatus includes a reception unit configured to receive a challenge message, sent by a capture appliance, with a code associated with one of the N seals. There is a checking unit configured to check the received code for validity and for a first breakage of the seal associated with the received code on the basis of the data record associated with the associated seal. A transmission unit is configured to send a response message, generated on the basis of the check, with a piece of status information pertaining to the first breakage of the seal associated with the received code to the capture appliance. |
| US09569793B2 |
Dynamic content for online transactions
A method of providing dynamic content includes providing a client device with access to an online marketplace over a network. The method also includes facilitating transmission of a user identifier stored by the client device to a payment service provider. The method further includes receiving dynamic content from the payment service provider in response to the user identifier. In addition, the method includes serving the dynamic content to the client device over the network. |
| US09569788B1 |
Systems and methods for associating individual household members with web sites visited
A method executes at a server system with one or more processors and memory. The server receives demographic information for a plurality of household members. The demographic information includes at least age and gender. The server receives web activity information for the household. The server identifies one or more web activity sessions from the web activity information and selects one of the web activity sessions. The server identifies one or more web sites visited during the selected web activity session and accesses demographic skew data for at least a subset of the web sites visited. The demographic skew data for a web site identifies fractions of visitors to the web site from predefined demographic segments. The server associates a household member with the web activity session at least in part by correlating the demographic skew data of the web sites visited with the demographic information of the first household member. |
| US09569782B1 |
Automated customer business impact assessment upon problem submission
A computer-implemented method and system for automated customer business impact assessment upon a problem submission. A problem description of a problem with a product is received from a customer using the product. The problem description is automatically analyzed using natural language processing (NLP) to identify an issue including a subject. The issue and subject is compared with usage information stored in a repository for the customer. The method and system include predicting an impact of the problem to the customer, and prioritizing a solution to the problem based on the predicted impact. |
| US09569781B2 |
Methods for providing cross-vendor support services
An analysis is performed on first and second product information to determine a relationship between a first product and a second product. In response to a first notification from a first backend system, a first message is transmitted to a mobile device of the user indicating that the change of a first activity is needed. It is determined whether a modification of a second activity is needed based on the relationship information of the first product and the second product and in response to determining that the modification of the second activity is needed, a second message is transmitted to the mobile device, indicating a possible modification of the second activity and offering a list of one or more options to modify the second activity. A live communications session is established between the user and a support agent of the server to discuss the possible modification of the second activity. |
| US09569775B2 |
Methods and systems for performing authentication in consumer transactions
The method for authenticating a mail order or telephone order transaction according to the present invention includes receiving authentication information from a cardholder, providing authentication information to an issuer, and determining whether the authentication information is valid. If the authentication information is valid, the issuer informs the merchant that the transaction is valid. In an embodiment, the issuer may not supply a personal assurance message and/or other confidential cardholder information previously supplied by the cardholder in response to the authentication information. |
| US09569773B1 |
Invariant biohash security system and method
Systems, methods, and program products for providing secure authentication for electronic messages are disclosed. A method may comprise generating an asymmetric private key based at least in part upon an invariant biometric feature vector derived from an input biometric reading. The private key may be further based at least in part upon a user password. The resulting private key may not be stored but rather may be generated when required to authenticate an electronic message, at which time it may be used to provide a digital signature for the electronic message. The private key may be deleted after use. The private key may be regenerated by inputting both a new instance of the biometric reading as well as a new instance of the password. |
| US09569772B2 |
Enhancing bank card security with a mobile device
A PIN server system interacts with one or more financial institutions to authenticate a mobile phone and-or a user thereof. The PIN server provides to the mobile phone one or more PIN numbers to use in financial transactions involving the one or more financial institutions, and also provides the one or more PIN numbers to the financial institutions in a manner that results in the one or more PIN numbers being associated with one or more accounts of the mobile phone user with the one or more financial institutions. |
| US09569771B2 |
Method and system for storage and retrieval of blockchain blocks using galois fields
A method and system for storage and retrieval of blockchains with Galois Fields. One or more blocks for a blockchain are securely stored and retrieved with a modified Galois Fields on a cloud or peer-to-peer (P2P) communications network. The modified Galois Field provides at least additional layers for security and privacy for blockchains. The blocks and blockchains are securely stored and retrieved for cryptocurrency transactions including, but not limited to, BITCOIN transactions and other cryptocurrency transactions. |
| US09569767B1 |
Fraud protection based on presence indication
Introduced here is a technology that enables fraud detection and protection in financial transactions using a communication signal identification mechanism. The technology eliminates the uncertainties as to the authenticity of a payment card and/or a customer involved in a transaction. In at least some embodiments, methods and systems are disclosed for facilitating communication with one or more personal computing devices physically present at a merchant's POS device to establish customer presence and/or card presence. The personal computing devices can include a smartphone, a wearable electronic device, or any electronic device capable of communication with other devices. The personal computing devices can also include a payment card in the form of a smartcard with embedded BLE or any other smart chip (e.g., GPS, Wi-Fi, 4G, etc.). In some embodiments, methods and systems are disclosed for applying context-based restrictions on the payment card to assist in protection against fraud. |
| US09569765B2 |
Simultaneous item scanning in a POS system
A plurality of items is positioned in a volume scanned by a three-dimensional non-optical imaging system. The imaging system generates a three-dimensional voxel image of the volume. Voxel regions are identified and surfaces of voxel regions are analyzed to identify a symbol printed thereon. The symbols are resolved into product identifiers, which are then added to a transaction and payment for the transaction is processed. The imaging system may be a magnetic resonance imaging (MRI) system, computed tomography (CT) scanning system, terahertz (T wave) imaging system, or other imaging system. |
| US09569754B2 |
Unified view of aggregated calendar data
Embodiments of the present invention address deficiencies of the art in respect to calendaring and scheduling and provide a novel and non-obvious method, system and computer program product for providing a unified view of aggregated calendar data in a C&S system. In one embodiment of the invention, a method for providing a unified view of aggregated calendar data for an event in a calendar view can be provided. The method can include selecting an event in the calendar view, aggregating calendar data for the event relating to all invitees for the event, computing statistics for the aggregated calendar data, and rendering a display of the computed statistics proximate to the selected event in the calendar view. |
| US09569753B2 |
Hierarchical publish/subscribe system performed by multiple central relays
A method for transmitting messages in a publish/subscribe message system. The method also includes: receiving, at a first relay, a subscription request from a first client; recording, at the first relay, subscription information of the first client based on the subscription request; receiving, at the first relay, a publication request from a second client, wherein the publication request includes a message; and transmitting the message to the first client. |
| US09569747B2 |
Shelf-monitoring system
A system and method for monitoring shelf inventory that combines bar code and RFID technologies to permit electronic data entry of item shelf assignments and real time reporting of item removal from display/dispensing storage shelves. |
| US09569746B2 |
Custom fit sale of footwear
A method whereby a customer may purchase footwear through a remote communication channel, and be assured that the purchased footwear will properly fit upon delivery. The customer purchases footwear by designating the last that is used to construct the footwear. A customer may identify a particular last based upon careful measurement of the customer's feet. A customer may also identify a last based upon previous experience with footwear constructed using the last. |
| US09569744B2 |
Product notice monitoring
Various embodiments include at least one of systems, methods, and software for product notice monitoring. Some embodiments include at least one product notice database that is an aggregation of product notices, such as product recalls, bulletins, safety notices, updated usage guidelines, and the like, that may be issued by various different sources. The product notice database is monitored in such embodiments in view of products of an organization to identify possible matches. When a possible match is identified, the notice is provided to the organization. Some embodiments may include routing the notice to particular people or departments responsible for the relevant product(s) of the notice. The matching in some embodiments may be relative matching based on one or more forms of fuzzy logic, which allows for approximate matching, although not necessarily identical. The product notice monitoring may be performed in whole or in part in the cloud. |
| US09569743B2 |
Funnel analysis
Systems, methods, and media for the application of funnel analysis using desktop analytics and textual analytics to map and analyze the flow of customer service interactions. In an example implementation, the method includes: defining at least one flow that is representative of a series of events comprising at least one speech event, at least one Data Processing Activity (DPA) event, and at least one Computer Telephone Integration (CTI) event; receiving customer service interaction data comprising communication data, DPA metadata, and CTI metadata; applying the at least one flow to the customer service interaction data; determining if the customer service interaction data meets the at least one flow; and producing an automated indication based upon the determination. |
| US09569740B2 |
System and methods for directiing one or more transportation vehicle units to transport one or more end users
Computationally implemented methods and systems that are designed for transmitting one or more requests for one or more identities of one or more transportation vehicle units for transporting one or more end users; receiving the one or more identities of the one or more transportation vehicle units for transporting the one or more end users, the one or more identified transportation vehicle units having been identified based, at least in part, on a determination that the one or more identified transportation vehicle units do not have any package delivery obligation that would be violated if the one or more identified transportation vehicle units transport the one or more end users to one or more destination locations; and directing the one or more identified transportation vehicle units to rendezvous with the one or more end users in order to transport the one or more end users to the one or more destination locations. In addition to the foregoing, other aspects are described in the claims, drawings, and text. |
| US09569731B2 |
Quantum communication device, quantum communication method, and computer program product
According to an embodiment, a quantum communication device includes a receiver, a sift processor, an estimator, first and second storages, a determination unit, an error corrector, a measurement unit, and a privacy amplifier. The sift processor acquires sift processing data by referring to a cryptographic key bit string in a predetermined bit string with a reference basis randomly selected from a plurality of bases. The estimator acquires an estimated error rate by estimating an error rate of the sift processing data from an error rate of part of the sift processing data. When a sift processing data volume stored in the first storage is not smaller than a first threshold, the determination unit determines order of the sift processing data to be corrected based on an estimated error rate, an error rate range that a check matrix can correct, and estimated correction time, and the check matrix used for correction. |