| Document | Document Title |
|---|---|
| US09380285B2 |
Stereo image processing method, stereo image processing device and display device
A stereo image device includes a representative point selection unit for selecting a plurality of representative points in a first image of a stereo-pair image; a corresponding point control unit detecting a plurality of corresponding points corresponding to the plurality of representative points in a second image of the stereo-pair image and excluding any corresponding point(s) judged to be a deviating point; a deviation value calculation unit for judging whether corresponding points are the deviating points or not; an approximation curve calculation unit performing a curve approximation on all the corresponding points except the excluded corresponding points; a height correction value calculation unit calculating a height correction value from a plurality of approximation curves drawn up by the curve approximation; a parallelization execution unit performing parallelization of the second image on the basis of the height correction value. |
| US09380281B2 |
Image processing apparatus, control method for same, and program
An image processing apparatus replays moving image data and includes a control unit configured to carry out control that replays the moving image data; and a generating unit configured to generate images in the case of different depths of field based on the moving image data depending on a replay speed of the moving image data. |
| US09380278B2 |
Video projection device and method with control of light source based on image signal
A video projection device according to this disclosure is provided with a splitter having a first region including a plurality of segments and a second region including at least one segment and configured to split a light flux emitted from a light source into a plurality of light of colors in a time-divisional manner by having the light flux enter into each one of the segments, and a video display element configured to modulate the light of the colors based on a image signal to be input and to form a image, and a controller configured to calculate a light intensity and to control the light source based on a result of the calculation. |
| US09380277B2 |
Imaging device with reduced color mixing and method of manufacturing the same
The present technique relates to an imaging device that can reduce color mixing that occurs between an on-chip lens and a photodiode, and a method of manufacturing the imaging device.The imaging device includes a first unit pixel including a photodiode unit that receives light, a first color filter that faces at least part of the photodiode unit, and a second color filter that faces the first color filter, the first color filter and the second color filter being located at a distance from each other. The present technique can be applied to imaging devices or imaging apparatuses. |
| US09380275B2 |
Augmented video system providing enhanced situational awareness
A facility, comprising systems and methods, for providing enhanced situational awareness to captured image data is disclosed. The disclosed techniques are used in conjunction with image data, such as a real-time or near real-time image stream captured by a camera attached to an unmanned system, previously captured image data, rendered image data, etc. The facility enhances situational awareness by projecting overlays onto captured video data or “wrapping” captured image data with previously-captured and/or “synthetic world” information, such as satellite images, computer-generated images, wire models, textured surfaces, and so on. The facility also provides enhanced zoom techniques that allow a user to quickly zoom in on an object or area of interest using a combined optical and digital zoom technique. Additionally, the facility provides a digital lead indicator designed to reduce operator-induced oscillations in commanding an image capturing device. |
| US09380274B1 |
Methods and systems for presenting alert event indicators
A method at an electronic device includes: displaying a video feed from a camera or a frame from the video feed; and concurrently with displaying the video feed or the frame, displaying a camera history timeline, including: displaying a representation of a camera event associated with one or more alert events in the camera history timeline as a bar overlaid on the event history timeline, the event bar having a length reflecting a duration of the camera event; and displaying, proximate to the event bar, one or more alert event indicators, each of the alert event indicators corresponding to a respective alert event of the alert events associated with the camera event, where each respective alert event indicator has a respective visually distinctive display characteristic associated with the corresponding respective alert event. |
| US09380273B1 |
Multiple aperture video image enhancement system
Disclosed is a helmet mounted enhanced vision system which includes at least one camera, having a circuit board therein with an array thereon of closely spaced apertures, where each aperture includes an electronic light sensor and a computer die coupled to and associated therewith, such that each aperture behaves much like a digital camera coupled via to the other apertures by a network. The array of apertures each including varied sensor types such sensors having: different resolutions, distance to optimal focus point, and light sensitivity, so as to enable foveal displays, multi-focal point images and dynamic range enhancement, respectively. |
| US09380272B2 |
Community internet protocol camera system
An apparatus comprises a server in communication with a camera located on a customer premises. The server is adapted to transmit Internet Protocol formatted video, containing a surveillance portion from the camera and an advertisement portion, to a customer premises device. A method for sending the Internet Protocol formatted video is also disclosed. |
| US09380267B2 |
Bandwidth modulation system and method
A method and computing system for monitoring an AV synchronous communication session of a user. The AV synchronous communication session includes an audio channel and a video channel. A performance characteristic is determined for the audio channel. The performance characteristic is compared to a defined audio performance threshold. If the performance characteristic does not meet the defined audio performance threshold, the video channel is adjusted to reduce the bandwidth requirements of the video channel. |
| US09380266B2 |
Method and systems for optimizing bandwidth utilization in a multi-participant full mesh peer-to-peer video session
An endpoint optimizes bandwidth by initiating a peer-to-peer conference with a plurality of remote devices, generating a first quality list comprising a first device of the plurality of remote devices from which to receive a first data stream at a first quality level, transmit a request to the first device to receive the first data stream at the first quality level, determining that a second device of the plurality of remote devices is not a member of the first quality list, and in response to determining that the second device of the plurality of remote devices is not a member of the first quality list, transmitting a request to the second device to receive a second data stream at a second quality level. |
| US09380265B2 |
Call indicator tool
Embodiments of the invention detail systems, computer program products, and methods for providing a call indicator tool. In an exemplary embodiment the system presents, on the display of a video conference apparatus, a call indicator widget linked with a video conference communication session. The call indicator widget may include (i) at least one selectable feature and (ii) at least one label for presenting information to the customer via the call indicator widget. Through user input the system may receive an indication that the customer selected the at least one feature, and in response to receiving the indication, alter the display to present information related to the selectable feature. |
| US09380262B2 |
Mobile terminal and method for operating same
The present invention relates to a mobile terminal, and a method for operating the same. According to an embodiment of the present invention, a method for operating a mobile terminal includes the steps of: forming an audio beam based on at least one of a photographed image from a camera and motion information from a motion sensor; receiving an audio signal from a speaker through a plurality of microphones; and processing the received audio signal based on the formed audio beam. Thus, the use convenience is improved. |
| US09380261B2 |
Multi-camera access for remote video access
In one embodiment, multiple cameras are logically associated in a guest registry with a mobile device. One of the cameras may be internal to the mobile device, and one of the cameras may be external to the mobile device. A network device accesses the guest registry in response to a request from the mobile device. The request may be a request for a conference call, or the request may be a request for service. A conference call is initiated in response to the request. The network device receives video data from the multiple cameras associated with the mobile device and establishes a multiple party conference call including the multiple cameras and an external device. |
| US09380259B2 |
Information processing device and information processing method
A non-transitory computer-readable recording medium storing a program that causes a computer to execute a process including receiving a setting of an anchor to a subject in an image included in a video; determining whether a movement amount between the subject to which the anchor has been set in a predetermined image in the video and the subject in another image included in the video is greater than or equal to a predetermined value; and storing, in a storage unit, an identifier of the another image that is a determination target, and position information of the anchor, when the movement amount is determined to be greater than or equal to the predetermined value. |
| US09380256B2 |
Method and apparatus for segmented video compression
An archival video system uses profile images as a background for an image and delta images to indicate the difference between a current image and a profile image. An image may be segmented into multiple sectors, with each sector compared to a profile sector. The resulting image may be constructed using references to previously stored sectors from different images. |
| US09380254B2 |
Display and electronic unit
A display includes: a display main unit including a display panel; and a back-face covering member including a back-face section and a side-face section, the back-face section being made of a metal plate and disposed on a rear-face side of the display panel to face the display panel, and the side-face section being made of a resin and provided between an end section of the back-face section and an end section of the display main unit. |
| US09380253B2 |
Method and apparatus for band selection, switching and diplexing
Systems and methods for selecting, combining and duplexing signals in a communications network. Several configurations of diplexers and channel selectors are disclosed which use filters, combiners and splitters to select and combine which the signals to be either received or transmitted. |
| US09380248B1 |
Remote control system
An example system includes a remote control and a host device. The remote control is configured to communication through a first communication interface and a second communication interface. The host device is configured to retrieve command information from a remote computer through a third communication interface, and responsive to one or more requests from the remote control, to transfer the command information to the remote control through the first communication interface, the remote control configured to control a plurality of remote devices through the second communication interface, using the command information. |
| US09380247B2 |
Focus detection apparatus, method for controlling the same and image capturing apparatus
A focus detection apparatus comprises a plurality of sensor groups, each comprising a plurality of sensors, each including a photoelectric converter and a storage portion, and controls part of the sensor groups according to a first accumulation method, in which charge generated by a photoelectric converter is accumulated in itself, and to a second accumulation method, in which charge generated by a photoelectric converter is accumulated in a storage portion. A sensor group corresponding to a selected focus detection area is controlled according to the first accumulation method, and a sensor group adjacent to the sensor group controlled according to the first accumulation method is controlled according to the second accumulation method. A monitor unit monitors a signal level of the charge stored in the storage portion corresponding to the photoelectric converter controlled according to the second accumulation method. |
| US09380246B2 |
Digital correlated double sampling circuit and image sensor including the same
A digital correlated double sampling (CDS) circuit includes a first latch unit, a second latch unit and a calculating unit. The first latch unit stores digital reset component data and digital image component data by latching a count signal in response to a first control signal. The second latch unit stores the digital reset component data by latching an output of the first latch unit in response to a second control signal. The calculating unit generates digital effective image data by subtracting the digital reset component data from the digital image component data. |
| US09380245B1 |
Conditional-reset image sensor with analog counter array
In an image sensor containing an array of pixels, a pixel signal corresponding to the state of a photosensitive element is read-out of each pixel and compared with a threshold. If the pixel signal exceeds the first threshold, the state of the photosensitive element is reset and an analog-count voltage that corresponds to the pixel is incremented. |
| US09380244B2 |
Multi-color superpixel operational constructs for focal plane arrays
A method for sensing using a multi-band photovoltaic detector, the method including biasing the photovoltaic detector using a bias voltage at a mid-point of a detector substrate bias voltage range, selecting a first band of the multi-band photovoltaic detector, sensing a first current from a first diode of the multi-band photovoltaic detector, the first diode being associated with the first band, selecting a second band of the multi-band photovoltaic detector; and sensing a second current from a second diode of the multi-band photovoltaic detector, the second diode being associated with the second band. |
| US09380242B2 |
Image sensor and devices having the same
An image sensor according to an example embodiment of includes a first pixel and a second pixel in a first row. The first pixel includes a first photoelectric conversion element at a first depth in a semiconductor substrate and the first photoelectric conversion element is configured to convert a first visible light spectrum into a first photo charge, and the second pixel includes a second photoelectric conversion element at a second depth from the first depth in the semiconductor substrate, the second photoelectric conversion element is at least partially overlapped by the first photoelectric conversion element in a vertical direction, and the second photoelectric conversion element is configured to convert a second visible light spectrum into a second photo charge. |
| US09380237B2 |
Semiconductor integrated circuit, current control method, ad converter, solid-state imaging device, and electronic system
A semiconductor integrated circuit includes: a plurality of current sources including a first transistor individually connected to a power source line and a bias line; and a plurality of bias blocks including a second transistor configured to constitute a current mirror circuit together with the first transistor, and to divide a reference current to be a reference of the current sources so that the reference current flows through the bias line. |
| US09380230B2 |
Image capture device, anomalous oblique incident light detection method, and recording medium
In an aspect of the invention, plural pixels constituting a color image pickup device include a first pair of RB pixels and a second pair of RB pixels both constituted by a red pixel R having a red color filter and a blue pixel B having a blue color filter in a horizontal direction A and vertical direction B, the red pixel and the blue pixel being adjacent to each other. A position of the red pixel R and a position of the blue pixel B are opposite to each other between the first pair of RB pixels and the second pair of RB pixels. Pixel data of the blue pixel B of the first pair of RB pixels is compared with pixel data of the blue pixel of the second pair of RB pixels to detect whether or not anomalous oblique incident light is incident on the color image pickup device. |
| US09380229B2 |
Digital imaging systems including image sensors having logarithmic response ranges and methods of determining motion
In at least one example embodiment, a method of determining motion in an image includes acquiring pixel data from a plurality of pixels in an image sensor, the plurality of pixels having respective response ranges, the response range of at least a first pixel of the pixels including a linear response range and a logarithmic response range, the plurality of pixels configured to produce pixel data according to light of the image in a scene and the response ranges and determining the motion based on the pixel data generated across the response ranges including the logarithmic response range of the at least first pixel. |
| US09380228B2 |
High dynamic range image sensor system and method thereof
A high dynamic range imager system is provided that includes an imager having a pixel array, and memory in communication with the pixel array, the memory comprising a plurality of memory cells, wherein the number of memory cells is approximately the number of whole row-times of exposures between the first conditional reset and row readout. |
| US09380225B2 |
Systems and methods for receiving infrared data with a camera designed to detect images based on visible light
Systems and methods for receiving infrared data with a camera designed to detect images based on visible light are provided. A system can include a camera and image processing circuitry electrically coupled to the camera. The image processing circuitry can determine whether each image detected by the camera includes an infrared signal with encoded data. If the image processing circuitry determines that an image includes an infrared signal with encoded data, the circuitry may route at least a portion of the image (e.g., the infrared signal) to circuitry operative to decode the encoded data. If the image processing circuitry determines that an image does not include an infrared signal with encoded data, the circuitry may route the image to a display or storage. Images routed to the display or storage can then be used as individual pictures or frames in a video because those images do not include any effects of infrared light communications. |
| US09380223B2 |
Device for contactlessly testing passive routing substrates
A device for fault detecting passive routing substrates. Thermal behavior differences before and after a passive routing substrate is damaged are used. A batch of passive routing substrates is fault detected without running a functional test. In addition, the passive routing substrates are not contacted and are not damaged on detection. The device provides superior and precise detection before stacking the passive routing substrates. |
| US09380220B2 |
Optical filtering for cameras
In one embodiment, a camera includes an image sensor within a camera housing that converts light entering the camera housing through an optical filter into digital image data. The optical filter can have a variable opacity. A processor in communication with the image sensor identifies operation settings for the optical filter and adjusts an opacity level of the optical filter over an exposure period in accordance with the operation settings for the optical filter. In addition, the processor modifies values of the digital image data based at least on the operation settings for the optical filter. |
| US09380218B2 |
Highlight exposure metric and its applications
Systems, methods, and computer readable media for the use of a metric whose value is especially sensitive to the information lost when an image's pixels are clipped are disclosed. The metric may be used as an image's score, where higher values are indicative of lost highlight information (more clipped pixels). One use of the disclosed metric would be to determine when the use of high dynamic range (HDR) techniques are appropriate. The disclosed metric may also be used to bias a scene's exposure value (EV) such as to a lower or underexposed value (EV−) so that the scene may be captured with no more than an acceptable number of clipped pixels. |
| US09380214B2 |
Image photographing apparatus and method thereof
An image photographing apparatus and method are provided. The image photographing method includes inputting images having different view points for a subject; displaying a first image among the images; in response to an input of a user command, changing the first image to a second image having a view point which is different from that of the first image, and displaying the second image; and in response to an input of a photographing command, acquiring the second image. |
| US09380202B2 |
Focus detection apparatus, image pickup apparatus, image pickup system, focus detection method, and non-transitory computer-readable storage medium
A focus detection apparatus performs focus detection by a phase difference method using an image pickup element including first and second pixels, the focus detection apparatus includes a correlation data calculator which calculates correlation data between pixel data obtained from the first pixels and the second pixels in ranges of image data, a detector which detects a saturated pixel having a level of at least a predetermined value in each of the ranges, an adding processor which performs an addition processing of the correlation data calculated in each of the ranges based on a detection result, and a defocus amount calculator which calculates a defocus amount based on a result of the addition processing, and the adding processor performs the addition processing using correlation data obtained from a first range in which the number of the saturated pixels is less than a predetermined number. |
| US09380197B2 |
Techniques for video analytics of captured video content
Examples are disclosed for video analytics of captured video content. In some examples, information may be received from a host processing system for a camera to capture video content. The camera may be a surveillance camera or a camera located with a display device. Video analytics may be performed on the captured video and the captured video content may be encoded. Data associated with the video analytics may then be sent to the host processing system. In some examples, the data as well as encoded captured video content or streaming video may be sent via communication channels included in an interconnect. Other examples are described and claimed. |
| US09380191B2 |
Solid-state imaging device, driving method, and electronic apparatus
Disclosed is a solid-state imaging device including a pixel array, two vertical scanning circuits, and a control part. The pixel array has a plurality of pixels arranged in a two-dimensional matrix form. The two vertical scanning circuits are configured to sequentially select and scan each of the pixels in a vertical direction per row. The control part is configured to generate, based on a mode signal corresponding to an imaging mode, a driving switch signal to stop driving of one of the two vertical scanning circuits. |
| US09380187B2 |
Facsimile apparatus and facsimile communication system
A facsimile apparatus includes a data acquisition section, a facsimile transmission candidate image storage section, a destination receiving section, a facsimile communication section, a print setting information management section, and a facsimile transmission image generating section. The facsimile communication section is configured to transmit and receive, to and from a destination facsimile apparatus, information necessary for facsimile communication including a facsimile transmission candidate image and print setting information. The print setting information management section is configured to store the print setting information received from the destination by the facsimile communication section. The facsimile transmission image generating section is configured to manipulate the facsimile transmission candidate image to meet the printing condition indicated by the print setting information on the destination stored in the print setting information management section, thus generating a facsimile transmission image subject to a facsimile transmission to the destination. |
| US09380185B2 |
Medium having instructions for storing and displaying image data on an output apparatus based on attributes, and output apparatus for storing and displaying image data based on attributes
Computer-executable instructions stored in a medium cause an output apparatus to perform first and second output control processes. The output apparatus includes a storage section for storing a plurality of document data sets having a predetermined order and acquired from a plurality of documents, and an output section for outputting images of a plurality of document data constituting the plurality of document data sets. In the first output control process, the output section outputs an image of a document data belonging to one document data set and to output an image of a document data belonging to the next document data set according to the predetermined order. In the second output control process, the output section outputs an image of a document data belonging to a specified attribute of one document data set and to output the next image based on the attribute. |
| US09380183B2 |
Image sensing device
An image sensing device includes N red light sensing units, N green light sensing units, N blue light sensing units and a control circuit. The control circuit accumulates an exposure capacity Qi generated by the ith red light sensing unit, green light sensing unit, and blue light sensing unit in an exposure time Ti and an exposure capacity Qi+1 generated by the (i+1)th red light sensing unit, green light sensing unit, and blue light sensing unit in next exposure time Ti+1 until an exposure capacity QN generated in the TNth exposure time is accumulated, wherein i is an integer ranging from 1 to N. The exposure capacities Qi to QN are sequentially stored in a register and outputted from the control circuit, so that the image of each scan line can be sequentially transferred to an analog signal with the sum of the exposure capacities Qi to QN. |
| US09380181B2 |
Information processing apparatus and method of controlling launch thereof
An information processing apparatus is capable of quick launch, in which information of memory is held and the apparatus is launched using the information, and includes an RTC that keeps the time and generates an interrupt at a set time. The apparatus detects whether or not there is an instruction to turn a power supply on or off, and if an instruction to turn the power off is detected, determines whether or not the quick launch is active. If it is determined that the quick launch is active, the apparatus sets an interrupt generated by the RTC inactive. |
| US09380178B2 |
Display input apparatus, image forming apparatus having the same, and method for controlling the display input apparatus
Upon accepting a region dividing operation, a display input apparatus sets a line, which passes through a predetermined region, as a first reference line; sets an end edge of the predetermined region, which is opposite to the first reference line, as a second reference line; obtains a ratio for input numerical value calculation, namely, a ratio of a distance from the first reference line to the second reference line and a distance from the first reference line to a division line of the predetermined region divided by the region dividing operation; obtains a numerical value by multiplying a maximum value or minimum value in a numerical value input range by the ratio for input numerical value calculation, and displays the obtained numerical value in a numerical value input screen. |
| US09380176B2 |
Voice band data mode in a universal facsimile engine
A facsimile apparatus includes a user interface operative to facilitate communications between the apparatus and at least one user application in operative communication with the apparatus, a network interface operative to facilitate communications between the apparatus and an analog communications network and an IP communications network. The apparatus further includes a controller connected to the user interface and network interface. The controller is operative in a first mode to communicate with the analog communications network using a first facsimile protocol and being operative in at least a second mode to communicate with the IP communications network using the first facsimile protocol and a voice band data protocol. |
| US09380175B2 |
Image forming apparatus, control method of image forming apparatus, and computer-readable storage medium
An image forming apparatus capable of communicating with an external apparatus includes a reception unit configured to receive E mail transmitted from the external apparatus, a printing unit configured to print the E mail received by the reception unit, a setting unit configured to set a reception function of the Email valid or invalid, and a control unit configured, in a case where it is determined that a factor for shifting a power state of the image forming apparatus to an OFF-state has been detected, to set the power state of the image forming apparatus to the OFF-state if the reception function of the E mail is set invalid by the setting unit, and not to set the power state of the image forming apparatus to the OFF-state if the reception function of the E mail is set valid by the setting unit. |
| US09380172B2 |
Image forming apparatus having image reading device
In an image forming apparatus, when a pivot plate is at a closed position, a free end of the pivot plate is at a vertical level higher than first and second hinge portions which are arranged apart from each other in a width direction along a horizontal direction. A free end of the pivot plate moves in a space defined between first and second virtual vertical planes. The first virtual vertical plane is defined as a virtual vertical plane, on which a widthwise inner end of a first hinge portion is disposed, and which is perpendicular to a rotational center axis of the first hinge portion. The second virtual vertical plane is defined as a virtual vertical plane, on which a widthwise inner end of the second hinge portion is disposed, and which is perpendicular to a rotational center axis of the second hinge portion. |
| US09380171B2 |
Method and system for selective charging by recipients of in-bound communications in communication networks
A method, in the field of communications services, for linking several electronic and information components (including communication network elements, servers, databases and software) to implement a service for, dynamically and selectively, imposing supplementary call charges on behalf of subscribers to the network; whether for self-employed, competent experts, other categories of content provider, or any individuals or organizations receiving communications. Such supplementary tariffs are levied on those calling telephone numbers dynamically and selectively dedicated for this purpose, providing called parties with a way to collect fees for the information they provide to calling parties. The method enables the operating party (a Value added service provider) in partnership with the mobile operator to collect these revenues on behalf of and to share this revenue with, the called subscriber. |
| US09380170B1 |
System, method, and computer program for creating cellular network performance indicators by correlating business data of subscribers with a geographic position
A system, method, and computer program product are provided for creating cellular network performance indicators by correlating business data of subscribers with a geographic position. In use, one or more subscriber measurement reports associated with an authenticated cellular network subscriber identifier are received. Additionally, the one or more subscriber measurement reports are geo-location tagged with a geographic position estimate. Further, business data associated with the authenticated cellular network subscriber identifier is received. Moreover, the received business data is associated with the one or more corresponding subscriber measurement reports, based on the authenticated cellular network subscriber identifier, such that the business data is associated with the geographic position estimate to create one or more performance indicators. |
| US09380169B2 |
Quality of service (QoS)-enabled voice-over-internet protocol (VoIP) and video telephony applications in open networks
A device defines a first bucket for general Internet protocol (IP) traffic provided to and from a user device associated with an open network, and defines a second bucket for quality of service (QoS)-based traffic provided to and from the user device. The device also assigns a first billing rate for the general IP traffic associated with the first bucket, and assigns a second billing rate to the QoS-based traffic associated with the second bucket, where the second billing rate is greater than the first billing rate. The device further associates the first billing rate and the second billing rate with a subscriber associated with the user device. |
| US09380166B2 |
Dynamically constructing and updating social media status for use as ringback tones
Methods and arrangements for constructing ringback tones. A contemplated method includes: obtaining data pertaining to a first user of a communication medium from one or more communication channels comprising at least one channel selected from the group consisting of: an enterprise system, a personal social network, personal information derived from the communication medium, a contacts list, an instant messaging system, a professional social network, and a personal blog; and when a second user attempts communication with the first user via the communication medium: dynamically and automatically constructing a status update based on the obtained data; and using the constructed status update as a ringback tone. Other variants and embodiments are broadly contemplated herein. |
| US09380163B2 |
System for routing interactions using bio-performance attributes of persons as dynamic input
A system for routing an interaction has a queue for staging the interaction, a router running a routing strategy for routing the interaction, and a number of object models maintained for a number of agents, the object models defining one or more agent skills, the values of the object models dynamically affected by real-time bio-metrics of the agents obtained through ongoing monitoring of voice and input actions of the agents. The routing strategy routes the interaction based on comparison of the dynamically-affected skill values of the agents, as evidenced in the object models. |
| US09380156B2 |
Method for sending recorded conference call content
A method and communication device for scheduling a conference call. The method includes receiving, in a first communication device, an invitation message containing at least some conference call scheduling information with respect to a scheduled conference call session; displaying an interface in relation to the invitation message, the interface including an option to send a request for recorded conference call content of the scheduled conference call session; receiving an input selecting the option; and sending a communication to a second communication device including a response to the invitation message and including said request for recorded conference call content. A conference call server is also described for sending recorded conference call content to the communication device. |
| US09380155B1 |
Forming speech recognition over a network and using speech recognition results based on determining that a network connection exists
Systems, methods and apparatus for generating, distributing, and using speech recognition models. A shared speech processing facility is used to support speech recognition for a wide variety of devices with limited capabilities including business computer systems, personal data assistants, etc., which are coupled to the speech processing facility via a communications channel, e.g., the Internet. Devices with audio capture capability record and transmit to the speech processing facility, via the Internet, digitized speech and receive speech processing services, e.g., speech recognition model generation and/or speech recognition services, in response. The Internet is used to return speech recognition models and/or information identifying recognized words or phrases. The speech processing facility can be used to provide speech recognition capabilities to devices without such capabilities and/or to augment a device's speech processing capability. Voice dialing, telephone control and/or other services are provided by the speech processing facility in response to speech recognition results. |
| US09380145B2 |
Dynamic tapping force feedback for mobile devices
Dynamic force feedback is provided in a device to alert a user about a message received on the device from a remote user and to convey content, context, or a type of the message. Producing dynamic force feedback may include activating a motion induction device, which accelerates and decelerates a mass to create tapping within the device. The amplitude and frequency of the tapping may be configured to produce sequences of taps to alert the user about different types, contexts, or content of received messages. Additionally, multiple motion induction devices may be included in a device to produce dynamic force feedback along multiple dimensions. Multiple dimension dynamic force feedback may be used in providing geographical directions to a user. |
| US09380143B2 |
Automatically disabling the on-screen keyboard of an electronic device in a vehicle
A keyboard deactivation module includes a processor configured to generate an on-screen keyboard control signal, a CAN bus interface configured to connect to a CAN bus of a vehicle, and obtain vehicle speed information indicating a current speed of the vehicle from the vehicle via the CAN bus, and a Bluetooth radio configured to transmit the on-screen keyboard control signal to a target electronic device. An on-screen keyboard of the target electronic device is enabled in response to receiving the on-screen keyboard control signal while the vehicle speed information indicates that the current speed of the vehicle is below a specified threshold, and the on-screen keyboard of the target electronic device is disabled in response to receiving the on-screen keyboard control signal while the vehicle speed information indicates that the current speed of the vehicle is above a specified threshold. The keyboard deactivation module is mounted in the vehicle. |
| US09380139B2 |
Speaker and keypad assembly for a portable communication device
An improved keypad and speaker assembly is provided. The assembly (100) comprises a speaker grille formed of torturous porting (220), and a keyboard (108) comprising audio slots (120) which are offset beneath the tortuous porting (220). The speaker (104) is aligned beneath the keyboard (108). The tortuous porting (220) and audio slots (120) provide an unobstructed air passage/path between the speaker and ambient while protecting against water intrusion. |
| US09380138B2 |
Electronic device cover
An electronic device is provided comprising: a display screen; a sensing unit for sensing a respective state of each one of a plurality of sub-covers, the plurality of sub-covers being part of a cover for protecting the display screen; and a controller configured to perform an operation based on the respective state of each one of the plurality of sub-covers. |
| US09380135B2 |
Method and device for information transmission in wireless communication system
The present invention relates to a wireless communication system and more specifically relates to a method and device for transmitting information. A wireless communication system can support carrier aggregation (CA). In one aspect of the present invention, a method, in which a terminal transmits information to a base station in a wireless communication system, comprises the steps of: carrying out rate matching for a preset number of symbols in a subframe for transmitting first information on at least one serving cell formed in the terminal; and transmitting the first information from the subframe in which the rate matching has been carried out, to the base station. Therein, the uplink transmission timing of the one or more serving cells are different from one another, and the preset number is determined in accordance with the difference between the uplink transmission timings of the one or more serving cell. |
| US09380122B1 |
Multi-platform overlap estimation
Panel and census data representing accesses by sets of users with multiple types of media platforms to media content associated with multiple media entities is accessed. An overlap in the accessed panel data that represents users who have accessed media content associated with the media entity with more than one of the multiple types of media platforms is determined. Based on the accessed panel data, the determined overlap in the accessed panel data, and the accessed census data, an overlap function that estimates an overlap in the accessed census data is derived. The derived overlap function is applied to census data associated with a media entity to estimate an overlap in the census data associated with the media entity. The overlap in the census data represents users who have accessed media content associated with the media entity with more than one of the multiple types of media platforms. |
| US09380121B2 |
Method, computer program and computer for estimating location based on social media
To provide a technique to estimate a location relating to a user who has not filled in information about the location in a profile field in social media such as a microblog.A method for estimating association between a user in social media and a location includes the steps of acquiring a first content posted to the social media by a first user associated with a first location, determining regional localization of the first content on the basis of the first location, acquiring a second content posted to the social media by a second user not associated with a location, determining the degree of a relationship between the first content and the second content, and associating the first location with the second user on the basis of the localization and the degree of the relationship. |
| US09380119B2 |
Method, apparatus, and computer program product for network discovery
Embodiments enable discovery of networks in a wireless communications medium. In example embodiments, a method comprises inserting, by an apparatus, an indication associated with a neighbor awareness network to be advertised to an apparatus address field of a wireless advertisement packet; and transmitting, by the apparatus, the wireless advertisement packet including the inserted indication associated with the neighbor awareness network to be advertised. The packet may be a Bluetooth Low Energy ADV_IND PDU packet or a Bluetooth Low Energy ADV_SCAN_IND PDU packet. The apparatus's address field may be a non-resolvable private address format in an AdvA field of either the Bluetooth Low Energy ADV_IND PDU packet or the Bluetooth Low Energy ADV_SCAN_IND PDU packet. The apparatus may be operating in a Neighbor Awareness Networking (NAN) network or intending to operate in a NAN network. |
| US09380118B2 |
Analytics based scoping of HTML5 web storage attributes
A method, system, and computer program product for optimizing storage of Web storage attributes through analytics is provided. The method includes identifying and storing in memory of a computer, utilization of different Web storage attributes by different end users across different Web application sessions from different Web browsers and analyzing the stored utilization of different Web storage attributes to identify a past scope of utilization for each of the different Web storage attributes. The method further includes, responsive to receiving a request from a requestor for an optimal storage location of a particular Web storage attribute, determining an identified past scope of utilization for the particular Web storage attribute, mapping the determined identified past scope of utilization for the particular Web storage attribute to the optimal storage location, and returning an indication of the mapped optimal storage location of the particular Web storage attribute to the requestor. |
| US09380114B1 |
Techniques for peer messaging across multiple storage processors of a data storage array
A technique manages peer messaging across multiple SPs of a data storage array. The technique involves using a token, by a first SP of the data storage array, to identify particular data stored at a source storage location on the data storage array. The technique further involves starting, by the first SP, multiple WUT operations which use the token in response to multiple WUT requests, each WUT operation moving the particular data from the source storage location to a respective destination storage location. The technique further involves providing, by the first SP, a single “touch” message in response to starting the multiple WUT operations by the first SP, the single “touch” message informing a set of other SPs of the data storage array that the token which identifies the particular data has been touched. |
| US09380094B2 |
Error resilient coding and decoding for media transmission
A “Media Transmission Optimizer” provides a media transmission optimization framework for lossy or bursty networks such as the Internet. This optimization framework provides a novel form of dynamic Forward Error Correction (FEC) that focuses on the perceived quality of a recovered media signal rather than on the absolute accuracy of the recovered media signal. In general, the Media Transmission Optimizer provides an encoder that optimizes the transmission of redundant frames of electronic media information encoded at different bit rates, and provides optimized playback quality by providing a decoder that automatically selects an optimal path through one or more available representations of each frame as a function of overall rate/distortion criteria. |
| US09380092B2 |
Method and system for inserting content into streaming media at arbitrary time points
The present invention teaches a method and system of inserting content into streaming media programs without requiring re-encoding and/or re-segmenting of the program, thus allowing the insertion point within the media program to be selected as desired. The system and method operate on the relevant chunks of the streaming program to repackage those chunks, even in real time, to provide a chunk boundary at the desired insertion point in the streamed program to permit seamless playback of the main program and inserted content. |
| US09380089B2 |
System and method for routing media
The system and method for streaming media to a viewer and managing the media comprises an enhanced service routing processor (ESRP), a real time switch management system (RTSMS), a name routing processor (NRP), and a managed media switch (MMS). The RTSMS has a reservation system. The ESRP receives media from an owner, manages the media according to media rules and order rules defined by the owner, and distributes the media to one or more switches, such as the MMS, according to the media rules and the order rules. The RTSMS is configured to receive the media rules and to receive a viewer's media request via the reservation server. The reservation system of the RTSMS processes the media request according to the media rules and builds a reservation for the requested media. The RTSMS generates the reservation to the viewer and to the NRP. The NRP receives the reservation data from the viewer and from the RTSMS. The NRP processes the reservation data and locates an MMS that can stream the media to the viewer. The NRP transmits the IP address of the MMS to the viewer and transmits the reservation data to the MMS. The viewer initiates a session or connection with the MMS using the reservation number. If the reservation data from the viewer matches the reservation data from the NRP, the MMS streams the media to the viewer. |
| US09380087B2 |
Tagging users of a social networking system in content outside of social networking system domain
Users of a social networking system can tag other users in content items that are provided outside of the social networking system, such as pictures that are viewable on a website that is external to the social networking system. To enable a user to tag another user in a content item, an external system provides a user interface that enables the user to tag another user, optionally define a portion of the content item in which the tagged user appears, and provide an identity of the tagged user. The external system communicates with the social networking system to provide the tagging information to the social networking system. The tagging information is received by the social networking system, which imports the content item and displays the content item with the tagging information to other users in the social networking system. |
| US09380086B2 |
Pre-transcoding content items
A content management system pre-transcodes portions of content items provided for storage. When a content item is uploaded to the content management system for storage, the content management system stores the content item in an original format. The content management system transcodes a portion of the content item from the original format to a streaming format. The content management system stores the transcoded portion and makes the content item available for access. When a client device requests the content item from the content management system, the content management system first sends by streaming to the client device the stored transcoded portion in the streaming format. During the sending of the transcoded portion, the content management system transcodes a remainder of the content item that has not been transcoded to the streaming format. The content management system sends the transcoded remainder of the content item to the client device. |
| US09380084B2 |
Method, apparatus and system for implementing login of IP telephone number
Embodiments of the present invention disclose a method, an apparatus and a system for implementing login of an Internet Protocol (IP) telephone number. The method includes: after receiving a neighbor discovery protocol message of a data link layer sent by a connected IP telephone, obtaining, by a communication client, when determining that the communication client has used a communication account to log in to a communication server, from the communication server, an IP telephone number associated with the communication account, and sending the IP telephone number to the IP telephone, so that the IP telephone uses the IP telephone number to execute a login operation, thereby solving the problem in the prior art that the user operation is complex because a manual input manner needs to be used in logging in by using both the communication account and the IP telephone number. |
| US09380081B1 |
Bidirectional network data replications
A system and method establishes bidirectional contact through firewall devices. A method includes establishing a first connection between a first device and a second device and storing a connection record on the second device. When the second device receives a request to connect with the first device, it identifies and searches for the connection record corresponding to the first device. When the second device finds the connection, the second device sends a request to establish a second connection from the second device to the first device. Upon receiving the request to establish a second connection, the first device verifies the request to establish the second connection and the lifetime of the first connection. Upon verification, the first device establishes the second connection between the first computing device and the second device. |
| US09380080B2 |
Session initiation for multimedia services
A method includes receiving, at a first communication service provider, a request (by a first device and including identification information associated with a particular user of a second device) to initiate a session between the first device and the second device for a multimedia service provided by a second communication service provider. The method includes determining access information associated with the second device based on the identification information and sending a call invitation to the second device to initiate the session. Accepting the call invitation causes the second device to receive the particular application (which is executable to facilitate initiation of the session) from the second communication service provider via a connection between the second device and the second communication service provider. |
| US09380071B2 |
Method for detection of persistent malware on a network node
The present invention relates to methods and devices for detecting persistency of a first network node (12). In a first aspect of the invention, a method is provided comprising the steps of monitoring (S101), during a specified observation period, whether the first network node has established a connection to a second network node (13), and determining (S102) a total number of sessions of connectivity occurring during said specified observation period in which the first network node connects to the second network node. Further, the method comprises the steps of determining (S103), from the total number of sessions, a number of sessions comprising at least one communication flow between the first network node and the second network node, and determining (S104) inter-session persistence of the first network node on the basis of the total number of sessions and the number of sessions comprising at least one communication flow. |
| US09380069B2 |
Method and device for data transmission
Embodiments of the present disclosure provide a method and a device for data transmission. In the method, a network layer communication entity of a receiving device receives an IP packet from a sending device, where a header of the IP packet carries a random value corresponding to the sending device. The receiving device decapsulates the IP packet and obtains the random value carried in the header of the IP packet. The receiving device sends the random value to a transport layer communication entity of the receiving device so that the transport layer communication entity of the receiving device verifies the random value. The receiving device in embodiments of the present disclosure includes a receiving module, an obtaining module, and a verifying module. |
| US09380061B2 |
Service protection
A method and system for determining whether user accounts in a client-server architecture are legitimate is described, the method and system including determining a first integer value, hereinafter denoted N, and a second integer value, hereinafter denoted K, such that K |
| US09380056B2 |
Multiple input based passwords
A computer-implemented method, carried out by one or more processors, for utilizing one or more input methods for passwords. In an embodiment, the method comprises the steps of determining, by one or more processors, one or more input methods supported for a password entry, wherein the password entry verifies a user's credentials; receiving, by one or more processors, a candidate password through the one or more input methods, wherein each character of the candidate password has an associated input method; and storing, by one or more processors, the candidate password as the password entry, along with the associated input method for each character of the candidate password. |
| US09380055B2 |
Device control method, device management system, and in-house server apparatus connected to device management system
A method in the disclosure includes: receiving, from an information device, a device password which is used for controlling a target device via an in-house server apparatus and which is input on the information device using a setting screen; managing a device ID of the in-house server apparatus, a user ID, and the device password in association with one another; transmitting the device password to the in-house server apparatus to cause the in-house server apparatus to manage the device ID and the device password; transmitting, when login to an out-of-house server apparatus is authenticated, an authentication screen to the information device; receiving, from the information device, an input password that is input on the information device using the authentication screen; and when the received input password is identical to the device password that is associated with the user ID, approving a control of a target device by the information device. |
| US09380046B2 |
Communication apparatus and control method therefor
It is determined whether a user who has logged in in communication using a selfsigned certificate stored by default is an administrator or a general user. If it is determined that the user is an administrator, an install page for a CA-signed certificate which is more reliable than the selfsigned certificate is returned to the user. Alternatively, if it is determined that the user is a general user, an error page is returned to the user. |
| US09380039B2 |
Systems and methods for automatically logging into a user account
Systems and methods for automatically logging into a user account are described, including receiving, using a device, data from an external source or from two or more sources comprising an internal source and another source, wherein the external source is not a user; determining, using the device, that at least a portion of received data is new data; and based on the received data, automatically logging in, from the device, to an account of the user. |
| US09380034B2 |
Systems and methods for data gathering without internet
Systems and methods are provided in which external key devices are used for sealing and unsealing data-gathering devices without Internet, wherein the data-gathering devices invalidate the external key devices upon completing data collection in order to seal removable storage. Further, a sealed removable storage is transported to same location of a key server, where the key server uses a multi-factor sealing routine to unlock the sealed removable storage. The routine seals and unseals uses multiple factors including a location of the key server, hardware attributes of the removable storage, hardware attributes of the external key devices, and a private key of the key server. The data-gathering device may be used to support workers collecting data in disconnected parts in the world that are without Internet. The workers may collect data by using mobile devices to transfer data to a shared data-gathering device. |
| US09380030B2 |
Firewall traversal for web real-time communications
The system and method monitor a secure Web Real Time Communication (WebRTC) session between browsers. To do so, a WebRTC application receives a first WebRTC offer with a fingerprint of a first browser to establish a secure communication session. The WebRTC application sends session information and the fingerprint of the first browser to a media relay. The WebRTC application receives a fingerprint of a media relay. A second WebRTC offer with a fingerprint of the media relay is sent to a second browser. An answer to the second WebRTC offer is received. Session information and the fingerprint of the second browser are sent to the media relay so the media relay can decrypt the secure communication session. The first WebRTC offer is answered. A secure communication session is established via the media relay using the fingerprints. The media relay, based on the fingerprints, can monitor the secure communication session. |
| US09380028B2 |
Proxy server operation
Data messages having secure data location addresses other than a predefined set are handled by a user terminal (14) in the normal way by setting up a secure tunnel (181) to a server specified in the data message (16). As this would prevent any proxy server from performing any processing on the content of the data message, messages that require the proxy to perform process on the data messages are processed separately. Data messages (251) incorporating secure media access locators identifying a predefined set of known media servers are identified by a message processing function (41, 410, 44) and passed to a proxy server over a connection between the user terminal and the proxy which does not tunnel past the proxy server, such that the proxy server may generate a redirected media access locator for return to the user terminal (14). |
| US09380022B2 |
System and method for managing content variations in a content deliver cache
Embodiments disclosed herein provide a high performance content delivery system in which versions of content are cached for servicing web site requests containing the same uniform resource locator (URL). When a page is cached, certain metadata is also stored along with the page. That metadata includes a description of what extra attributes, if any, must be consulted to determine what version of content to serve in response to a request. When a request is fielded, a cache reader consults this metadata at a primary cache address, then extracts the values of attributes, if any are specified, and uses them in conjunction with the URL to search for an appropriate response at a secondary cache address. These attributes may include HTTP request headers, cookies, query string, and session variables. If no entry exists at the secondary address, the request is forwarded to a page generator at the back-end. |
| US09380021B2 |
Network address translation
Address translation sufficient for use in translating addresses included in messages carried or otherwise transmitted between inside and outside network is contemplated. The contemplated address translation may facilitate operation of a network address translator (NAT), carrier grade network address translator (CGN), or other device similarly configured to facilitate translating inside addresses used to address messages carried over the inside network relative to outside addresses used to facilitate carrying messages over the outside network. |
| US09380017B2 |
Human assisted chat information system
Disclosed is a technology for providing information to users of a chat information system. The chat information system may receive an information request from a user. The information request may be processed to determine its subject area and forwarded to information sources or external communication services, such as social networks, forums, and the like. Answers received from the information sources and external communication services may be validated and selected based on user feedbacks and ratings. The selected answers may be then delivered to the users of the chat information system. After receiving the answers, the user may evaluate them to be further stored for future use by the chat information system. |
| US09380013B1 |
Identifying a second media content to go viral based on a velocity threshold of a first media content
Systems and techniques are disclosed for transmitting a message via one or more platforms, the messages being associated with media content and/or related media content. A related media content may be identified based on the media content and a platform may be selected based on a platform selection criteria. The message may correspond to the related media content and may be transmitted to the platform. |
| US09380011B2 |
Participant-specific markup
A conversation server hosts a conversation having a plurality of participants, the conversation server enables a first client to display at least a portion of a conversation to a first participant. The conversation server receives a notification the portion of the conversation was viewed by the first participant at a first time while in a first state. After receiving a notification that the portion of the conversation has ceased to be viewed by the first participant, the conversation is edited to a second state at a second time. At a third time that is after the second time, the conversation server sends, to the first client, information enabling the first client to display a markup of the portion of the conversation that is indicative of one or more edits that transition the portion of the conversation from the first state to the second state. |
| US09380009B2 |
Response completion in social media
Embodiments are directed towards providing word-by-word message completion for an incomplete response message, wherein the response message is composed in response to a received stimulus message. The message completion is based on a Response Completion Model (RCM) that may model both the language used in the incomplete response message and the contextual information in the received stimulus message. The RCM may be determined based on conversational stimulus-response data including stimulus-response message pairs. The RCM may be a mixture model and include a generic response language model based on an N-gram model, a Stimulus Model based on a Selection Model or a Topic. Model, and a mixture parameter. In some embodiments, at least one candidate next word for the incomplete response message is determined based on the RCM. The at least one candidate next word may be selected and included in the incomplete response message. A complete response message may be generated and provided to a user. |
| US09380005B2 |
Reliable transportation of a stream of packets using packet replication
In one embodiment, a device receives a first packet stream and a second packet stream over different paths through a network, wherein each of said sent first and the second packet streams includes a same replicated stream of packets. The apparatus processes packets of the first packet stream when the first packet stream is in an active packet stream, and while buffering and subsequently dropping packets of the second packet stream when the second packet stream is in a non-active state. In response to identifying a difference in a number of packets in the same replicated stream of packets received in the second packet stream compared to in the first packet stream equaling or exceeding a predetermined threshold, the second packet stream becomes in the active state and missing packets are forwarded from the buffered second stream packets. |
| US09380004B2 |
Determining virtual adapter access controls in a computing environment
A control component of a computing environment initiates sending of request(s) over a network of the computing environment by an activated virtual adapter. The activated virtual adapter is hosted on a physical adapter of a host system coupled to the network, and is for use by a guest, hosted by the host system, in performing data input and output. The request(s) retrieve access control information from the network indicative of access control(s) enforced in controlling access by the activated virtual adapter to network component(s). The initiating provides indication(s) to the physical adapter, absent involvement of the guest, that the request(s) be sent by the virtual adapter. Based on the initiating, the control component obtains the access control information from the physical adapter, and determines, based on that information, the access control(s) being enforced by the network in controlling access by the activated virtual adapter to the network component(s). |
| US09380001B2 |
Deploying and modifying a service-oriented architecture deployment environment model
A method for deploying a Service-Oriented Architecture (SOA) deployment environment model and a method for modifying a deployed SOA deployment environment model. In the deploying method, deployment of the SOA deployment environment model is realized by acquiring a task list including tasks for deploying elements of the model, associating the tasks in the task list with the elements, and executing the tasks to deploy the elements of the model. In the modifying method, modification of the SOA deployment environment model is realized by acquiring a task list including tasks for modifying elements of the model, associating the tasks in the task list with the elements, and executing the tasks to modify the elements. Thus, the deployment of the SOA deployment environment model and the modification of the deployed SOA deployment environment model may be realized in a simple and easy-to-implement manner. |
| US09379990B2 |
System and method for streaming a media file from a server to a client device
A method for streaming a media file from a server to a client device is provided. The method provides for streaming requested chunks of the media file from the server to the client device. The method determines a rate for streaming the requested chunk to the client device by using relationships between the requested chunk, the media file, current chunks, and current streaming rates. Provided a seek operation is determined, the requested chunk is streamed at a burst rate or a throttle rate. The method is especially useful for reducing latency and saving bandwidth. A corresponding system for streaming the media file from the server to the client device is also provided. |
| US09379989B2 |
Congestion avoidance and control for UDP-based protocols
An improved technique involves avoiding congestion in a network by monitoring round trip times of data units sent from a node of the network. Along these lines, a controller at a node of the network sends data units at some transmission rate to a target node with instructions to send a response back to the home node. Upon receiving the response, the controller measures the round-trip time as the difference in time from sending of the message to receipt of the response. Based on the round-trip time, the controller sets a new transmission rate at which to send units of data. |
| US09379988B2 |
Multi-rate MAC to PHY interface
A method and system for a multi-rate Media Access Control layer (MAC) to Physical layer (PHY) interface is provided. The method to provide a multi-rate Media Access Control layer (MAC) interface comprises receiving a first set of signals, sampling the first set of signals to determine a type of interface to be used to transmit or receive the first set of signals or a subset of the first set of signals, generating a select signal indicating type of interface to be used based on the sampling step and transmitting the first set of signals or a subset of the first set of signals using the interface indicated by the select signal. The method to provide a multi-rate Physical layer (PHY) interface comprises receiving a select signal from a Physical layer (PHY) layer indicating data rate of a first set of signals, selecting a first interface and turning off the second interface if the select signal indicates the first interface is to be used, selecting the second interface and turning off the first interface if the select signal indicates the second interface is to be used and transmitting the first set of signals using the second interface or a subset of the first set of signals using the first interface based on the select signal. |
| US09379986B2 |
Network relay device
When a first line card receives a frame at a port, the line card refers to monitoring results by internal communicability monitoring units of other second to fourth line cards and a monitoring result by an internal communicability monitoring unit of its own, determines a first of a transmission destination from band limiting units of other line cards based on the monitoring results, and transmits the frame. The second line card limits the communication band of the frame by the first band limiting unit of its own, and transmits the frame to a predetermined port. If any fault is detected in the communicability in the internal communicability monitoring table to/from the second line card as the communication counterpart, and, if the communicability to/from the third line card as the communication counterpart is normal, the first line card changes the transmission destination into the second band limiting unit. |
| US09379983B2 |
Router, method for controlling router, and computer program
In a bus system including a bus master, a first bus, and a second bus to connect them together, this router is arranged on the second bus to relay packets. The bus master outputs packets including information about at least one of (N+1) predetermined types of quality requirements. The second bus transmits packets designating at most N types of quality requirements. An exemplary router controls sending of the packets, with respect to at most N types of buffers that classify and store the packets by reference to the quality requirement type information and the packets stored in the buffers, so that the packets are sent in the descending order of their level of the quality requirement. The router controls sending schedule of the traffic flows by sensing a difference between the (N+1) different types of quality requirements. |
| US09379981B1 |
Flow level dynamic load balancing
Exemplary embodiments allocate network traffic among multiple paths in a network, which may include one or more preferred paths (e.g. shortest paths) and one or more alternative paths (e.g., non-shortest paths). In one embodiment, network traffic in form of flows may be allocated to the preferred paths until the allocation of additional network traffic would exceed a predetermined data rate. Additional flows may then be sent over the alternative paths, which may be longer than the preferred path. The paths to which each flow is assigned may be dynamically updated, and in some embodiments the path assignment for a particular flow may time out after a predetermined time. Accordingly, the flow traffic of each path may be balanced based on real-time traffic information. |
| US09379980B1 |
Methods and systems for AXI ID compression
Methods and systems for AXI ID compression are disclosed. Bus transaction data and an M-bit ID associated with the bus transaction data are transmitted by a master device via a bus to an ID mapper. The ID mapper is used to select, based on the M-bit ID, an N-bit ID from a plurality of N-bit IDs, where N may be less than M. The N-bit ID is associated with the bus transaction data. The bus transaction data and the N-bit ID associated with the bus transaction data are transmitted via the bus to a slave device. |
| US09379968B2 |
Redundancy support for network address translation (NAT)
Stateful failover redundancy support is provided for network address translation (NAT). A master NAT device is backed-up with at least one back-up NAT device. Existing sessions are synchronized between the two NAT devices, such as via a dedicated link between them. In the event of a failover where the master NAT device is unable to perform its NAT functions, ownership of Internet protocol (IP) addresses is transferred from the master NAT device to the back-up NAT device. The back-up NAT device, which is now owner of the IP addresses, assumes the NAT functionality associated with these IP addresses and continues the existing sessions, as well as processing new sessions. |
| US09379965B2 |
Organizing, managing, and selectively distributing routing information in a signaling message routing node
Methods, systems, and computer program products for managing and selectively distributing routing information in a routing node are disclosed. In one implementation, a method for selectively distributing routing information in a routing node includes organizing internal signaling resources are organized so as to facilitate the efficient mapping of signaling system 7 (SS7) message transfer part (MTP) signaling protocol attributes to Internet protocol (IP)-based signaling resources. A routing status information sharing hierarchy is defined, which enables routing status information to be efficiently shared among members of a signaling mateset group. Members of a signaling mateset replicate and distribute SS7 MTP network management information across non-MTP signaling connections, such as IP connections. |
| US09379964B2 |
Discovering a topology—transparent zone
A network node used to discover a topology-transparent zone (TTZ). In one example embodiment, the network node may obtain a TTZ identifier (ID) that is uniquely associated with the TTZ. Additionally, the network node may identify a link connected to a second network node that is also assigned the TTZ ID. In response to the command to initiate discovering the TTZ, the network node may generate a router information (RI) link-state advertisement (LSA) that comprises the TTZ ID and may distribute the RI LSA to the second network node using the link. In another example embodiment, the network node may not be configured as a TTZ edge node and may receive an RI LSA comprising the TTZ ID. The network node may store at least a portion of the information within the RI LSA and may flood the RI LSA using a plurality of links. |
| US09379961B2 |
Method and apparatus for initiating routing messages in a communication network
Switches within a telecommunications network exchange so-called available bandwidth messages, each of which advertises how much bandwidth remains unassigned on a respective link. The network is of a type in which circuits are provisioned with various predefined numbers of time slots (equivalent to bandwidth). The sending of an available bandwidth message for a given link is triggered by a change in the number of time slots available on that link if that change results in a change in the number of circuit bandwidths that can be accommodated by that link for a newly provisioned circuit. |
| US09379958B1 |
Using data pattern tracking to debug datapath failures
A method and system are provided for profiling data packets as they flow along a datapath in a device under test to locate and debug problems with the datapath or the individual nodes constituting the datapath to thereby expedite formal verification of a device under test and resolve any problems found. |
| US09379954B2 |
Configuration management for a resource with prerequisites
Embodiments are directed towards employing a configuration management system to report one or more assumptions based on whether or not prerequisites for a resource are satisfied. The configuration management system may determine at least one prerequisite that corresponds to a provided resource. The prerequisites may indicate what the resource requires in order to put the system into the target state. If the prerequisites are unsatisfied, then assumptions regarding the system may be determined and reported to a user of the system. The assumptions may include at least a state transition that upon occurrence puts the system into the target state. If the system is in a non-operational mode, such that state actions and state transitions are simulated, rather than being executed, the system may be enabled to perform other actions as if the prerequisites were satisfied and the state transition occurred, even if it is not. |
| US09379946B2 |
Model-based virtual networking
Architecture that facilitates the virtual specification of a connection between physical endpoints. A network can be defined as an abstract connectivity model expressed in terms of the connectivity intent, rather than any specific technology. The connectivity model is translated into configuration settings, policies, firewall rules, etc., to implement the connectivity intent based on available physical networks and devices capabilities. The connectivity model defines the connectivity semantics of the network and controls the communication between the physical nodes in the physical network. The resultant virtual network may be a virtual overlay that is independent of the physical layer. Alternatively, the virtual overlay can also include elements and abstracts of the physical network(s). Moreover, automatic network security rules (e.g., Internet Protocol security-IPSec) can be derived from the connectivity model of the network. |
| US09379944B2 |
Computer system, computer system information processing method, and information processing program
A management server acquires software configuration information, hardware configuration information, and operation achievement information from each server system; generates server operation achievement information for managing operation achievements of each server system based on each acquired information; generates server operation achievement statistic information by aggregating the software configuration information about each server system based on the generated server operation achievement information; and, upon receipt of a software configuration decision request from a requestor server system, selects the software configuration information which matches a hardware configuration of the requestor server system, from the server operation achievement statistic information. |
| US09379941B2 |
Autonomic computer configuration based on location
A system and apparatus for noticing and creating relational settings, actions, profiles, and tasks by tying resources to a location based on user behavior. |
| US09379936B2 |
IP address managing method, program thereof, network communication device
A method of managing IP addresses in a device performing communication using the IP address includes acquiring IP addresses by a plurality of methods; storing the plurality of IP addresses such that the methods are discernable when the plurality of acquired IP addresses are the same, determining an effective IP address used in the communication from the plurality of IP addresses according to predetermined priority in the methods, and setting the IP address to be used in the communication; and determining the valid IP address according to the priority from the stored IP addresses except for the disappearing IP address when the set IP address disappears, and setting the IP address to be used in the communication. |
| US09379935B2 |
Cached routing service
A device may receive a packet, determine whether the received packet is encapsulated with a first header associated with a cached routing service, and determine whether the received packet is to be provided with the cached routing service when the received packet is not encapsulated with the first header associated with the cached routing service. In response to determining that the received packet is to be provided with the cached routing service, the device may encapsulate the received packet with a second header associated with the cached routing service, send the encapsulated packet toward a destination of the packet, and store the encapsulated packet in a buffer in a memory. |
| US09379934B2 |
Server device for recommending electronic contents
The server device according to the embodiments provides users with more reliable recommendation information on electronic contents. This server device includes a game progression control unit for controlling progression of a game, an information storage unit for storing information, and a display control unit. The information storage unit includes: a use status management table for managing use status for each user of a plurality of online games provided by the server device; and a user-to-user relationship management table for managing information on relationship between users. The display control unit determines games to be recommended to a user based on information stored in the use status management table and the user-to-user relationship management table, and causes a terminal device to display information related to the games. |
| US09379933B1 |
Dynamically adjusting media content cache size
Disclosed are various embodiments for dynamically adjusting the amount of media content to transmit to a client for caching during a media streaming event. To begin, the location of the user may be determined. Based on the location of the user, a route may be predicted if the user is moving. A future connectivity interruption in the network coverage may be identified by comparing known areas of network coverage with the location of the user and/or the predicted route. Based on the likelihood of a future connectivity interruption, the amount of media content to transmit to a client for caching may be dynamically adjusted so that the user have a seamless media experience even in times of network coverage disconnect. |
| US09379932B1 |
Personal video recorder with limited attached local storage
This disclosure generally relates to systems and methods that facilitate employing a server based content recording component for recording content remotely for a client content video recording device that has limited storage and limited number of content streams to which it can access concurrently, while satisfying content rules for broadcast and re-transmission. |
| US09379926B2 |
Modulation technique for transmitting and receiving radio vortices
A device for generating Orbital Angular Momentum (OAM) modes for radio communications. The device is designed to receive one or more input digital signals, each of which has a respective sampling period which is a respective multiple of a given sampling period, and occupies a frequency bandwidth which is a respective fraction of a given available frequency bandwidth. The device is operable to apply, to each input digital signal, a respective space modulation associated with a respective OAM mode having a respective topological charge to generate a corresponding digital signal carrying the respective OAM mode. The device is configured to apply, to each input digital signal, the respective space modulation by interpolating said input digital signal and phase-modulating the interpolated input digital signal so as to generate a corresponding phase-modulated digital signal carrying the respective OAM mode, having the given sampling period, and occupying the given available frequency bandwidth. |
| US09379924B2 |
Cognitive radio spectrum sensing with improved edge detection of frequency bands
A spectrum sensing method for cognitive radio wherein spectrum holes are detected in a wireless environment having spectrum scarcity. First, a cognitive radio user (CR) determines the power spectral density (PSD) of a wideband signal and detects subbands within the wideband using wavelet transforms (WT). WT coefficients are calculated by convolving the PSD with first derivatives of wavelet smoothing functions. The extrema of the WT coefficients demark frequency subband edges. Detecting subband edges becomes more robust against noise by median filtering the PSD before calculating WT coefficients, summing over WT coefficients with different scale factors, and suppressing WT coefficients below a noise threshold. After identifying subbands, the CR determines subband availability by measuring the subband power and signaling the power to a fusion center receiving power measurements from multiple cooperating CRs, and final decisions are based on data and decision fusion. |
| US09379920B1 |
Decision feedback equalization with precursor inter-symbol interference reduction
In a receiver, a decision feedback equalizer (“DFE”) receives an analog input signal. The DFE includes a subtraction block for subtracting weighted postcursor decisions from an analog input signal to provide an analog output signal. A postcursor decision block coupled to the DFE compares the analog output signal against positive and negative values of a postcursor coefficient to provide first and second possible decisions for selecting a current postcursor-based decision therebetween responsive to a previous postcursor-based decision. A precursor cancellation block receives the analog output signal, the previous postcursor-based decision and the current postcursor-based decision for providing a digital output signal for a previous sample of the analog input signal. |
| US09379919B2 |
Transmission circuit for ethernet and protection component set thereof
A transmission circuit including four transmission component sets for Ethernet is provided. Each transmission component set is coupled between an Ethernet connector and an Ethernet chip and has a protection component set. For each transmission component set, a first capacitor is coupled between first and second transmission lines (TLs), and coupled to the Ethernet connector via the first TL and to the Ethernet chip via the second TL; a second capacitor is coupled between third and fourth TLs, and coupled to the Ethernet connector via the third TL and to the Ethernet chip via the fourth TL; first and second inductors are cascaded and coupled between the first and third TLs; a third inductor is coupled between the second and fourth TLs; and a contact between the first and second inductors is coupled to a ground via a fifth TL. |
| US09379916B2 |
Wireless communication system and device for coupling a base station and mobile stations
Wireless communication devices, comprising: a first transceiver in wireless communication with a terrestrial base station, wherein the station is in wireless communication with wireless communication devices; and a second wireless LAN transceiver in wireless communication with computing devices located within a coverage area of the second transceiver, the second transceiver being coupled to the first transceiver wherein: the first transceiver receives a first signal from the station, the first signal intended for a first computing device of the computing devices, the second wireless LAN transceiver determines signal characteristics of the first computing device, and the second transceiver transmits the first signal to the first computing device based on the determined signal characteristics of the first computing device; and the second transceiver receives a second signal from the first computing device, the second signal intended for the station, and the first transceiver transmits the second signal to the station. |
| US09379912B2 |
Mitigating email SPAM attacks
The present disclosure relates to mitigating email spam attacks. A gateway is configured to receive mail from one or more mail systems. If mail is intended for delivery to an invalid address, the gateway can generate status messages for delivery to the mail systems or determine if a threshold for delivery attempts to the invalid address has been met. If the threshold has been met, the gateway can request creation of a honeypot email address, and future mail intended for delivery to the invalid address are delivered to a mailbox associated with the honeypot email address. Various actions can be taken with respect to the mail delivered to the honeypot email address including analysis, blacklisting of senders, and/or other actions. |
| US09379910B2 |
System and method of mimetic messaging settings selection
Systems and methods of selecting message settings mimetically on a messaging client. When an outgoing message is composed on a messaging client, the messaging client determines whether the outgoing message is related to a received message. Where the outgoing message is related to the received message, the messaging client determines the messaging settings used in the received message, and selects the messaging settings used in the received message to control message characteristics of the outgoing message. |
| US09379909B2 |
Method and system for managing enterprise-related mobile calls
Methods, systems, and mobile devices for managing mobile calls to or from an enterprise-associated mobile device. The system and mobile device are configured to ensure all calls over a public land mobile network are routed through an enterprise communications system. The mobile device is prevented from directly calling remote parties through the public land mobile network and the public land mobile network forwards all calls addressed to the mobile device to the enterprise communications system. The enterprise communication system responds to a request to connect the mobile device and the remote party by establishing a first call with the mobile device, establishing a second call with the remote party, and bridging the two calls to connect the mobile device to the remote party. |
| US09379907B2 |
Multichannel intelligent electronic device with advanced communication capabilities
An intelligent electronic device (IED) for monitoring/measuring parameters of electrical services to a plurality of loads and receiving/transmitting information over communication networks is disclosed. The electrical services may be connected to the same or different AC services. The IED may be configured as a terminal or a server of an Intranet, LAN, WAN, or the Internet. In one application, these techniques are implemented in IEDs such as digital electrical power and energy meters. |
| US09379902B2 |
Method and apparatus for transmitting multimedia broadcast data in wireless communication system
A core network node and method for use in a wireless system are provided. The method includes transmitting, by a core network node, one or more service data unit (SDUs) to a base station; and transmitting, by the core network node, a control message including respective length information of the one or more SDUs to the base station. The length information included in the control message is used by the base station for processing the one or more SDUs, and the control message is transmitted after the one or more SDUs are transmitted. |
| US09379901B2 |
Communication method using multi-radio and communication apparatus
Provided is a communication method and apparatus using a multi-radio. The communication method includes establishing a link via at least one node included in a group that uses a low data-rate radio (LDR); transmitting a data frame to the at least one node included in the group; and receiving, using a multi-radio based on an availability of the LDR, an acknowledgement (ACK) with respect to the transmitted data frame. |
| US09379894B1 |
Authentication using cryptographic value derived from a shared secret of a near field communication tag
An apparatus comprises a first processing device comprising near field communication (NFC) interface circuitry, a memory and a processor coupled to the memory. The first processing device is configured to establish an NFC connection with an NFC tag using the NFC interface circuitry, receive a shared secret established between the NFC tag and an authentication server in an authentication protocol, and present a cryptographic value derived from the shared secret to a second processing device. The cryptographic value is utilizable by the second processing device for authenticating to the authentication server. |
| US09379891B2 |
Method and system for ID-based encryption and decryption
Provided are identifier (ID)-based encryption and decryption methods and apparatuses for the methods. The ID-based encryption method includes having, at a transmitting terminal, a transmitting-side private key corresponding to a transmitting-side ID issued by a key issuing server, generating, at the transmitting terminal, a session key using the transmitting-side ID, a receiving-side ID, and the transmitting-side private key, extracting, at the transmitting terminal, a secret key from at least a part of the session key, and encrypting, at the transmitting terminal, a message using a previously set encryption algorithm and the secret key. |
| US09379890B1 |
System and method for managing cryptographic keys
In various implementations, a first device retrieves, from a memory, encrypted data encrypted using a first key. The first device transmits, to a second device, a request for an encrypted first key, where the encrypted first key is generated by encrypting the first key using a second key. The first device receives the encrypted first key. The first device transmits, to an identity and access management device (IAM), a request for an encrypted second key, where the encrypted second key is generated by encrypting the second key using a third key. The first device receives the encrypted second key. The first device decrypts the encrypted second key using the third key, decrypts the encrypted first key using the decrypted second key, and decrypts the encrypted data using the decrypted first key. The first device deletes, from its cache, the decrypted first key after a period of time. |
| US09379882B2 |
Synchronization and control using out-of-band channels in passive optical network-based systems
Systems and methods are provided to use of out-of-band (OOB) channels for the transport of network-synchronization signals and network control information. These OOB channels transport synchronization and control channels over low-frequency bands outside of the frequency bands used for the data channels. Locating expensive network-synchronization functions in the optical network unit (ONU) and sharing the derived synchronization signals among multiple downstream customer premises equipment (CPE) devices results in cost savings and provides a means for maintaining a continuous, end-to-end synchronization reference, even during periods when the data channels on the copper network segment are in an energy-efficiency mode (e.g., a low-power and/or sleep mode). |
| US09379881B1 |
Phase interpolator circuit, clock data recovery circuit including the same, and phase interpolation method
A phase interpolator circuit that includes an interpolator suitable for generating synthesized clocks through synthesizing two multi-phase clocks; and an interpolation code generator suitable for generating an interpolation code for controlling the interpolator in response to a shift request. The interpolation code generator generates the interpolation code so that a (K+1)-th multi-phase clock is output as the synthesized clock when a phase of the synthesized clock is to be changed from a phase between K-th and (K+1)-th multi-phase clocks to a phase between (K+1)-th and (K+2)-th multi-phase clocks in response to a multi-shift-up request. |
| US09379876B2 |
Mobile station device, radio communication method and circuit device
A mobile station apparatus, that communicates with a base station apparatus, includes a reception unit that receives a physical downlink shared channel and information indicating radio resources for transmission of a physical uplink shared channel associated with contention based procedure and a transmission unit that transmits Hybrid Automatic Repeat Request (HARQ) information in response to the physical downlink shared channel and the physical uplink shared channel. The transmission unit also transmits, in case that transmissions of the HARQ information and the physical uplink shared channel happen in a single subframe, either both of the HARQ information and the physical uplink shared channel or the physical uplink shared channel without the HARQ information in the single subframe on the basis of a configuration. |
| US09379875B2 |
Downlink channel parameters determination for a multiple-input-multiple-output (MIMO) system
Embodiments of methods and apparatus for providing downlink channel parameters determination for downlink channels associated with a multiple-input-multiple-output (MIMO) system are generally described herein. Other embodiments may be described and claimed. |
| US09379874B2 |
Controlling uplink power
The disclosure is related to multiplexing an uplink channel and an uplink reference signal transmitted on uplink, and controlling an uplink power, in user equipment in the case of carrier aggregation. |
| US09379872B2 |
Channel quality indicator method, and associated system, base station, and user equipment
It would be to provide a method which will work with future versions of LTE-A, be backwards compatible and alleviate interference to signals for basic system operation. The method includes generating one or more Reference Signals associated with the one or more Channel Quality Indicators, and includes mapping the one or more Channel Quality Indicator-Reference Signals to the last symbol of the second slot of the one or more subframes. |
| US09379869B2 |
Apparatus and method for allocating code resources to uplink ACK/NACK channels in a cellular wireless communication system
A method and apparatus are provided for allocating code resources to ACK/NACK channel indexes, when UEs need ACK/NACK transmission in a wireless communication system in which a predetermined number of orthogonal cover Walsh codes is selected from among available orthogonal cover Walsh codes, at least one subset is formed, having the selected orthogonal cover Walsh codes arranged in an ascending order of cross interference, subsets are selected for use in first and second slots of a subframe, and the orthogonal cover Walsh codes of the subset selected for each slot and ZC sequence cyclic shift values are allocated to the ACK/NACK channel indexes. |
| US09379868B2 |
Subsequent association identifier (AID) update within single user, multiple user, multiple access, and/or MIMO wireless communications
Subsequent association identifier (AID) update within single user, multiple user, multiple access, and/or MIMO wireless communications. Even while a given communication device maintains continuous association within a given communication system, a unique identifier associated with that particular communication device may be updated. For example, considering and implementation including an access point (AP) and a number of wireless stations (STAs), even while at least some of the STAs remain in association with the AP, the respective unique identifiers associated with one or more of those STAs may be updated (e.g., the respective AID values associated with one or more of those STAs may be updated). For example, after an initial assignment of unique identifiers associated with a group of respective communication devices within the communication network, the unique identifier associated with one or more of those respective communication devices may be updated or changed after the initial assignment. |
| US09379866B2 |
Method for transmitting CPC information, radio access method and system based on CPC information
The disclosure provides a method for transmitting Cognitive Pilot Channel (CPC) information, a radio access method and system based on CPC information, wherein the method for transmitting CPC information includes: dividing a CPC into a primary CPC for transmitting primary CPC information and a secondary CPC for transmitting secondary CPC information; loading the primary CPC information periodically into fixed physical resources, and sending the primary CPC information to a user equipment; after a base station receives a preset triggering event, loading the secondary CPC information into variable physical resources, and sending the secondary CPC information to the user equipment. In the disclosure, the base station loads the primary CPC information into fixed physical resources of an RAT according to an RAT coverage condition, reducing the amount of information required to be delivered by fixed physical resources, decreasing occupation of fixed physical resources, speeding up radio access of the user equipment; and after receiving a triggering event, the base station loads the secondary CPC information into variable physical resources and sends the secondary CPC information to the user equipment, thus implementing optimization of a user network and radio resources. |
| US09379864B2 |
Reference signal generation technique
A technique for generating a reference signal for use in a communication system in which for reference signal generation multiple base sequences are defined is presented. A method implementation of the technique comprises generating a first reference signal sequence from a first base sequence and a second reference signal sequence from a second base sequence. A reference signal is generated that comprises the first reference signal sequence and the second reference signal sequence. The first reference signal sequence occupies a first spectral fragment of the reference signal, and the second reference signal sequence occupies a second spectral fragment of the reference signal. The second spectral fragment and the first spectral fragment do not overlap. |
| US09379863B2 |
Method for signaling information by modifying modulation constellations
Methods and systems for communicating in a wireless network may distinguish different types of packet structures by modifying the phase of a modulation constellation, such as a binary phase shift keying (BPSK) constellation, in a signal field. Receiving devices may identify the type of packet structure associated with a transmission or whether the signal field is present by the phase of the modulation constellation used for mapping for the signal field. In one embodiment, the phase of the modulation constellation may be determined by examining the energy of the I and Q components after Fast Fourier Transform. Various specific embodiments and variations are also disclosed. |
| US09379855B2 |
Method and apparatus for a remote modular test system
Certain embodiments generally relate to equipment under test measurements and reports, such as, but not limited to methods and apparatuses for a remote modular test system. For example, the method may include determining a test strategy (TS) file based on input from cloud-based equipment under test questionnaire and a cloud-based standards library. The method may also include reading the TS via a system controller. The method may further include configuring test hardware, for example, analyzers and power meters via a test RF system interface based on the read TS. The method may also include sequentially executing the TS based on the configuring. The method may further include generating a test document comprising result data. The method may also include uploading and processing the generated test document in the cloud. The method may further include grouping and compiling the generated test document in a predetermined layout. |
| US09379852B2 |
Packet recovery method, communication system, information processing device, and program
A packet recovery method of the present invention is a packet recovery method upon loss of a plurality of packets transmitted from a first node 111 to second node 112 through a network in the order of sequence numbers assigned to each of said packets, wherein second node 112, upon detection of a loss of a packet transmitted from first node 111, transmits an acknowledgement message, including a sequence number of a packet whose receipt has been confirmed or whose loss has been detected and including information on the lost packet, to first node 111 through the network. Then, first node 111, upon receipt of the acknowledgement message from second node 112, assigns a sequence number that is different from that of any of the plurality of packets to a retransmission packet which is a packet to be retransmitted, and subsequently, transmits an acknowledgement-to-acknowledgement message attached to the retransmission packet through the network for notifying that the acknowledgement message has been received to second node 112. |
| US09379850B2 |
Controlling retransmissions
A method and apparatus for controlling retransmissions in multipoint reception is disclosed. In the method it is determined that additional information is needed for decoding of at least one received information block. A procedure is selected for obtaining the additional information from a plurality of options to proceed based on information about predicted result of at least one of the options. In accordance with an aspect an indication of one of a positive acknowledgement of the information block, a negative acknowledgement of the information block and suspension of retransmission of the information block is generated and communicated on a retransmission control channel. |
| US09379847B2 |
Method and apparatus for transmitting and receiving in a communication/broadcasting system
Methods and apparatuses are provided for transmitting and receiving in a communication system. Input information is encoded by using a first parity check matrix to generate a codeword. Additional parity bits are generated by using a second parity check matrix which is related with the first parity check matrix. The codeword is transmitted by using a first resource. The additional parity bits are transmitted by using a second resource which is different from the first resource. |
| US09379845B2 |
Transmission device, reception device, transmission method, and reception method
A transmission device for rigorously protecting important information when information is transferred via a best-effort network. In this transmission device, a quality control information retention unit (203) holds quality control information set by a user. A recovery strength instruction unit (204) sets redundant code strength on the basis of transmission quality information from a reception device (104) and the quality control information held by means of the quality control information retention unit (203). Redundant encoding units (205, 206) generate, on the basis of the redundant code strength outputted from the recovery strength instruction unit (204), redundant code packets by means of an FEC for the packets outputted from encoding units (201, 202). |
| US09379841B2 |
Mobile device prevention of contactless card attacks
Technologies related to mobile device prevention of contactless card attacks are generally described. In some examples, a mobile computing device may monitor for electromagnetic signals at frequencies used for short range communications with contactless cards. Detection of such electromagnetic signals by the mobile computing device may indicate an attack attempt on a proximal contactless card. In response to detection of such electromagnetic signals, the mobile computing device may automatically generate a disruption signal effective to disrupt communications between contactless card readers and any proximal contactless cards, to thereby foil the attack before sensitive contactless card data is stolen. |
| US09379837B2 |
Channel sharing within wireless communications
A wireless communication device includes communication interface configured to receive and transmit signals and a processor configured to generate and process such signals. The communication interface of the wireless communication device is configured to receive a first signal from a first other wireless communication device, and the processor of the wireless communication device is configured to process the first signal to determine one or more concurrent transmission parameters. The processor of the wireless communication device is configured to generate the second signal based on the one or more concurrent transmission parameters and direct the communication interface to transmit the second signal to a second other wireless communication device during receipt of the first signal from the first other wireless communication device. The wireless communication device may be configured to make such concurrent transmissions based on one or more considerations such as the power level of the first signal. |
| US09379836B2 |
Resource allocation server and communication system for cloud-based radio access network
The server receives location data of the access points (APs) and channel request data of the APs corresponding to the location data of the APs. The server groups the channel request data of the APs into clusters according to available physical channels of the APs and the channel request data of the APs. The server allocates the available physical channels of the APs for the channel request data of the APs and transmission power configurations on each of the allocated physical channels of the APs according to the channel request data and the location data of the APs in each of the clusters. The server transmits allocated results of the allocated physical channels of the APs for the channel request data of the APs and the transmission power configurations on each of the allocated physical channels of the APs. |
| US09379832B2 |
Reception apparatus, reception method, transmission apparatus, transmission method, program, and broadcasting system
A reception apparatus for receiving transmitted AV (Audio/Video) content includes: an extraction section configured to extract trigger information associated with control of an application program transmitted with the AV content to be executed in cooperation with the AV content; and a control section configured to control processing associated with the application program in accordance with a command indicated by the extracted trigger information, wherein the application program in an active status started up in accordance with the command indicated by the extracted trigger information executes at least one of processing of generating view status information indicative of a user view status and processing of uploading the view status information to a predetermined server. |
| US09379830B2 |
Digitized broadcast signals
Methods, systems, and computer-readable media can facilitate digitizing a broadcast transmission and transporting the digitized broadcast transmission along with one or more digitized narrowcast transmissions to a subscriber. In embodiments, a digitized broadcast transmission and one or more digitized narrowcast transmissions can be separately demodulated and the transmissions can be combined at one or more receiving nodes. In embodiments, a digitized broadcast transmission can be combined with one or more digitized narrowcast transmissions. Lossless compression and de-compression techniques can be used to optimally transport digitized broadcast and narrowcast signals. |
| US09379822B2 |
Optical receiving apparatus
There is provided an optical receiving apparatus, including a receiver configured to perform coherent reception by mixing first light of a received optical signal and second light generated by a local oscillator, a monitor configured to monitor a first frequency of the first light, and a controller configured to control a second frequency of the second light, based on a difference between the first frequency and the second frequency so as to reduce the difference. |
| US09379815B2 |
Electro-optical payload for high-bandwidth free space optical communications
An electro-optical payload for free space optical communication includes: a plurality of optical beam expanders, each for receiving a respective optical signal; an optical cross-connect switch for directing respective optical signals to respective optical output signals; an electrical-to-optical conversion circuit coupled to an input of the optical cross-connect switch for converting an electrical signal to an optical signal for inputting to the optical cross-connect switch; an optical-to-electrical conversion circuit for converting an optical signal output from the optical cross-connect switch to an electrical signal; and an electrical regeneration circuit including a second optical-to-electrical conversion circuit coupled to an output of the optical cross-connect switch and a second electrical-to-optical conversion circuit coupled to an input of the optical cross-connect switch for converting an optical out signal of the optical cross-connect switch to an electrical signal. |
| US09379811B2 |
Method and device for optimizing performance of an optical module
Embodiments of the present invention provide a method and device for optimizing performance of an optical module. The optical module includes: an optical receiver, configured to receive an optical signal from an optical network, convert the optical signal into a first electrical signal, and process the first electrical signal according to a set control parameter for performance optimization, so as to obtain a second electrical signal; a connector, configured to send the second electrical signal obtained by the optical receiver to a host connected to the optical module, so that the host obtains bit error information according to the second electrical signal, and configured to receive the bit error information delivered by the host; and a processor, configured to adjust, according to the bit error information of the connector, the control parameter for performance optimization of the optical receiver. |
| US09379810B2 |
Rapid recovery in packet and optical networks
A node may determine a failure in a first path for routing first optical network traffic between a first set of networking devices, where the first path includes a first set of optical transport nodes. The node may determine a second path for routing the first optical network traffic between the first set of networking devices, where the second path includes a second set of optical transport nodes that route second optical network traffic between a second set of networking devices. The second set of optical transport nodes may include at least one node that is not included in the first set of optical transport nodes. The node may pre-empt routing of the second optical network traffic via the second path, and may route the first optical network traffic via the second path after pre-empting routing of the second optical network traffic via the second path. |
| US09379803B2 |
Antenna switching device
An antenna switching apparatus of an embodiment can perform wireless communication with another wireless communication apparatus. The antenna switching apparatus includes: an antenna unit which switches a polarized wave and a beam direction in the wireless communication and which radiates the polarized wave to the other wireless communication apparatus in the beam direction; a communication controller which acquires a communication characteristic corresponding to the polarized wave and the beam direction from the other wireless communication apparatus; an antenna detector which determines an antenna of the other wireless communication apparatus based on the acquired communication characteristic corresponding to the polarized wave and the beam direction; and an antenna switcher which switches the polarized wave and the beam direction in the wireless communication with the other wireless communication apparatus depending on the determined antenna of the other wireless communication apparatus. |
| US09379800B2 |
Method and apparatus for channel state information feedback
Embodiments of the present invention provide a method and apparatus for channel state information feedback. The method comprises: estimating channel state information from the mobile terminal to a serving cell and neighboring cells according to channel state information reference signals (CSI-Reference Signal) received from a plurality of coordinating cells; calculating a precoding matrix based on the estimated channel state information of the serving cell; calculating precoded channel state information respectively for the serving cell of the mobile terminal and neighboring cells in the coordinating cells according to the obtained precoding matrix; and feeding the precoded channel state information back to the serving cell of the mobile terminal. The above technical scheme can implement flexible and efficient channel status information feedback with low overhead, and enable multi-cell coordinated transmission to perform flexible and efficient precoding processing based on the feedback. |
| US09379798B2 |
Modulation circuit for a radio device and a method thereof
The present disclosure relates to a modulation circuit and a method for suppressing energy content of spectral side lobes caused by high-frequency content present in a baseband signal, with the energy content of the spectral side lobes being outside an intended operational bandwidth in a modulated radio-frequency signal. An example circuit is configured to: receive a digital baseband signal, feed the digital baseband signal to a first and a second signal path, with the first signal path comprising a first mixer and the second signal path comprising a delay circuit and a second mixer. The first mixer and the second mixer may receive a same local oscillator signal, and may respectively provide a first radio-frequency signal and a second radio-frequency signal that are delayed with respect to each other. The example circuit is further configured to generate an output radio-frequency signal by combining the first and second radio-frequency signals. |
| US09379793B2 |
Radio communication system, radio base station apparatus, user terminal and radio communication method
The present invention is designed to reduce the space to install antennas and still increase the system capacity despite the state of the distribution of user terminals in cells. According to the radio communication method of the present invention, a radio base station apparatus selects precoding vectors from a codebook that is set in advance to be uneven with respect to the direction of the arrangement of antenna elements, based on communication quality information of the user terminals in the cell, multiplies signals to supply to each antenna element by the selected precoding vectors, and transmits the signals multiplied by the precoding vectors to the user terminals, and the user terminal receives a signal from the radio base station apparatus, extracts a reference signal from the received signal and measures channel quality; and feeds back a communication quality feedback signal, including the measured channel quality, to the radio base station apparatus, via the uplink. |
| US09379787B2 |
Method and apparatus for composing a set of cells in a radio network
A method in a mobile station for enabling the composing of a set of a cells within a coverage area of a radio access network within which the same information is transmitted time synchronously using a modulation and coding scheme common for the cells of the set. The method includes: identifying one or more pilot signals from respective one or more cells monitored by the mobile station; determining signal and interference levels from the one or more monitored cells if a signal would be transmitted time synchronously using a common modulation and coding scheme within cells of a candidate set of cells; determining one or more modulation and coding schemes selectable with regard to the determined signal and interference levels and the candidate set of cells; and, indicating the one or more determined selectable modulation and coding schemes towards a network node performing the composition of the set of cells. |
| US09379779B2 |
Electronic device and a method of operating the same
The present invention concerns an first electronic device and a method of operating the first electronic device, which comprises receiving an identifier of a second electronic device from the second electronic device via a communication link formed by a first communication carrier; determining whether the second electronic device is a pre-registered based on the received identifier of the second electronic device; and when the second electronic device is not pre-registered according to a result of the determination, displaying a user interface for selecting a second communication carrier that is to be formed with the second electronic device. |
| US09379778B2 |
Near field communication circuit and operating method of the same
The near field communication (NFC) circuit includes an NFC reader circuit configured to communicate with an outside through an antenna, a resonant and matching circuit connected between the NFC reader circuit and the antenna, an NFC card circuit connected to nodes and configured to communicate with the outside through the antenna, and a processor configured to output a plurality of control signals when the NFC reader circuit is enabled, wherein the NFC card circuit is configured to control a resonant frequency of the antenna in response to the plurality of control signals. |
| US09379777B2 |
Near field communication circuitry used for hearing aid compatibility
An apparatus including a coil antenna; and near field communication (NFC) circuitry connected to the coil antenna. The NFC circuitry is configured to create a modulated signal from an input audio signal, and output the modulated signal to the coil antenna. |
| US09379776B2 |
System and method for low data-rate communication over a carrier current
The invention relates to a system for low data-rate communication over a modulated direct carrier current, having one or more communication transmitters (6, 8), a communication receiver (10), and a wire bus (12) forming a shared transmission channel. Each communication transmitter (6, 8) is configured to form a first raw staggered transmission frame according to a second staggered transmission frame, said staggered transmission frames using a set of separate basic chip-encoding sequences. The basic encoding sequences or staggering the symbols used by all the communication transmitters (4, 6) are identical, and the times of the initial transmission of the second staggered frames produced by each transmitter (6, 8) are autonomously and freely determined by each transmitter (6, 8), without taking into account any synchronization signal external to the transmitter (6, 8). |
| US09379775B2 |
Data communication system and method
A communication system includes a router transceiver unit and a bandwidth module. The router transceiver unit includes a network adapter module and a signal modulator module. The network adapter module is configured to receive high bandwidth network data from one or more data sources disposed on board a vehicle. The signal modulator module is configured for electrical connection to a wired connection, and to convert the high bandwidth network data into modulated network data in a form suitable for transmission over the wired connection. The bandwidth module is configured to allocate different portions of a data communication bandwidth of the wired connection to the modulated network data. The allocation is based on categories representing at least one of the one or more data sources or contents of the high bandwidth network data. |
| US09379771B2 |
Fiber length measurement system
A system for measuring a length of one or more spans between a first optical transceiver and a second optical transceiver in a fiber-optic network, which can determine, at a processor associated with the first optical transceiver, a round-trip time of an optical signal communicated from the first optical transceiver to the second optical transceiver and back to the first optical transceiver. The system can also determine, at the processor, a half-round-trip time by dividing the round-trip time by two. The system can also determine, at the processor, a distance between the first and the second optical transceivers by multiplying the speed of light by the half-round-trip time. |
| US09379769B2 |
Approach for managing the use of communications channels based on performance
An approach for selecting sets of communications channels involves determining the performance of communications channels. A set of channels is selected based on the results of performance testing and specified criteria. The participant generates data that identifies the selected set of channels and provides that data to other participants of the communications network. The participants communicate over the set of channels, such as by using a frequency hopping protocol. When a specified time expires or monitoring of the performance of the channel set identifies poor performance of the set of channels, the participant selects another set of channels for use in communications based on additional performance testing. By selecting channels based on the initial performance testing and performance monitoring, the communications network adaptively avoids channels with poor performance. |
| US09379768B2 |
Communication system with narrowband interference mitigation and related methods
A communications device may include a wireless receiver, and a processor coupled to the wireless receiver. The processor may be configured to receive a spread OFDM signal having narrowband interference associated with the same, the spread OFDM signal having subcarriers with data distributed among the subcarriers. The processor may be configured to excise the narrowband interference from the spread OFDM signal, and despread the spread OFDM signal after excising and based upon the excising to recover the data. |
| US09379767B2 |
Apparatus and method for performing resource allocation and communication in a wireless communication system, and system using same
Methods and apparatus are provided for transmitting and receiving uplink data in a wireless communication system. Hopping-related information is received at a mobile station from a base station. Resource allocation information is received at the mobile station from the base station. The uplink data is transmitted from the mobile station to the base station through at least one resource determined based on a sequence for sub-band hopping and a sequence for local hopping. |
| US09379765B2 |
Method and receiver for receiving a binary offset carrier composite signal
A data processor selects a set of BOC correlations in accordance with a BOC correlation function for the sampling period if the primary amplitude exceeds or equals the secondary amplitude for the sampling period. The data processor selects a set of QBOC correlations in accordance with a QBOC correlation function for the sampling period if the secondary amplitude exceeds the primary amplitude for the sampling period. The data processor uses either the BOC correlation function or the QBOC correlation function, whichever with greater amplitude, at each sampling period to provide an aggregate correlation function that supports unambiguous code acquisition of the received signal. |
| US09379764B2 |
Transceiver front end with low loss T/R switch
A transceiver or RF front end employing a transformer with a low loss transmit/receive (T/R) switch circuit in the ground path. In various embodiments, differential outputs of a power amplifier are coupled to the first winding of the transformer, while the input of a low noise amplifier is coupled to the second side of the transformer via a matching inductor. The T/R switch circuit, which may be a thin oxide CMOS transistor, is coupled between the second side of the transformer and ground. In operation, the T/R switch circuit may be enabled during transmit mode operations of the power amplifier, such that a low impedance path to ground is provided at the input of the low noise amplifier, thereby protecting it from high voltage swings generated by the power amplifier. |
| US09379762B2 |
Reconfigurable communication device and method
A communication device includes a transmitter operable to couple to a plurality of transceivers via a plurality of transmission channels, transmit payload data via the plurality of transmission channels, and obtain monitored transmission conditions for one or more transmission channels in the plurality of transmission channels. During operation, the transmitter is further operable to generate reconfiguration request signals resultant from processing the monitored transmission conditions and transmit the reconfiguration request signals on transmission channels in the plurality of transmission channels. |
| US09379761B2 |
Impedance measurement system and mobile communication device comprising an impedance measurement system
An impedance measurement system (IMS) is provided that comprises an RSSI chain (RSSI), a limiter RSSI chain (LIMRSSI) and a limiter chain (LIM). The RSSI chain and the limiter RSSI chain are connected to a subtraction circuit (SC) and the limiter RSSI chain and the limiter chain are connected to a phase detector (PD). Further, a mobile communication device is provided that comprises the impedance measurement system in an adaptive impedance control system. |
| US09379760B2 |
Radio frequency communication
A bidirectional radio frequency communication unit includes: a transmit modem; a receive modem; an RF transceiver circuit; a coupling waveguide arrangement; and an antenna. The RF transceiver circuit transmits and receives at RF frequencies greater than or equal to 50 GHz. At least a majority of the RF transceiver circuit is provided on a single multilayer PCB. The coupling waveguide arrangement is provided in the form of respective transmit and receive waveguides provided within a diplexer that has a common antenna coupling port and is in the form of a block. The multilayer PCB and the diplexer form a laminated structure; and transition interfaces between the RF transceiver circuit and the waveguide include one or more buried layer probe elements in a buried layer of the multilayer PCB. |
| US09379755B2 |
Scored smart card
The invention relates to a SIM (2) card in a first format, with an electronic module (4). The card body comprises a score line (6) surrounding the electronic module (4) in order to define the second card format (3). The said score line (6), comprises residual matter thickness that is smaller than the thickness of the card body. The thickness of the residual matter comprises a first thickness (9) over a first part of the score line (6), at least one second thickness (10) smaller than the first thickness (9) over a second part of the score line and at least one residual thickness change zone (11, 17), where the said thickness change zone is a gradual thickness change zone (11, 17) that goes from the first thickness to the second thickness. |
| US09379752B2 |
Compensation scheme for MHL common mode clock swing
Embodiments of the invention are generally directed to compensation for common mode signal swing. An embodiment of an apparatus includes a connector for the transfer of the data, the connector including connections for a first set of one or more conductors; a receiver for the reception of data via the connector, the received data including a first signal and a second signal transmitted via the set of one or more conductors, the second signal being a common mode signal modulating the first signal, the receiver including an amplifier to amplify the received data with a positive gain; and a common mode compensation circuit to compensate for a voltage swing of the common mode signal in the amplified received data. The common mode compensation circuit is to sense the common mode signal, amplify the sensed common mode signal with a negative gain, and feed back the amplified common mode to output nodes of the receiver. |
| US09379751B2 |
Noise canceling system and method, smart control method and device and communication equipment
The present invention discloses a noise canceling system and method, a smart control method and device and a communication equipment. Said smart control method includes: when it is detected there is no voice signal output at a receiving end of a communication equipment, receiving an outside noise signal from a reference microphone away from ears and a detection signal from a monitoring microphone near ears; implementing performance analysis on said received outside noise signal and said detection signal to estimate a noise reduction performance curve after said feed-forward active noise cancellation; and regulating parameters of the control circuit in said feed-forward active noise cancellation according to said estimated noise reduction performance curve and the preset noise reduction performance curve to make a difference between said estimated noise reduction performance curve and said preset noise reduction performance curve within a preset range. |
| US09379747B2 |
Detection and mitigation of interference based on interference location
Embodiments include a novel receiver architecture to optimize receiver performance in the presence of interference. In various embodiments, the presence of interference is detected, and the relative frequency location of the interference is detected. The relative frequency location specifies whether the frequency of the interference is high side (above the desired signal, i.e., at a higher frequency) or low side (below the desired signal). The receiver is configured based on the detected interference and relative location thereof. For a device such as a cellular phone that operates in a dynamic and changing environment where interference is variable, embodiments advantageously provide the capability to modify the receiver's operational state depending on the interference. |
| US09379746B2 |
Isolation circuits for digital communications and methods to provide isolation for digital communications
Isolation circuits for digital communications and methods to provide isolation for digital communications are disclosed. An example isolation circuit includes an isolation barrier, a burst encoder in a first circuit, and an edge pattern detector in a second circuit. The example isolation barrier electrically isolates the first circuit from the second circuit. The example burst encoder generates a first pattern in response to receiving a rising edge on an input signal and generates a second pattern in response to receiving a falling edge on the input signal. The example edge pattern detector detects the first pattern or the second pattern received from the burst encoder via the isolation barrier, sets an output signal at a first signal level in response to detecting the first pattern, and sets the output signal at a second signal level in response to detecting the second pattern. |
| US09379744B2 |
System and method for digital predistortion
The radio system comprises a radio unit and an antenna unit coupled to the radio unit. The antenna unit is physically separate and located remote from the radio unit. The antenna unit further comprises a digital pre-distortion engine configured to pre-distort a modulated digital data signal; a digital to analog converter configured to convert the pre-distorted digital data signal to a pre-distorted analog data signal; and a power amplifier configured to amplify the pre-distorted analog data signal which distorts the pre-distorted analog data signal. The distortion introduced by the power amplifier is opposite to the pre-distortion introduced by the digital pre-distortion engine such that the pre-distortion introduced by the digital pre-distortion engine approximately cancels the distortion introduced by the power amplifier. The radio unit further comprises a coefficient computation engine configured to calculate coefficients used by the digital pre-distortion engine to pre-distort the modulated digital data signal. |
| US09379742B2 |
RF transmitter, integrated circuit device, wireless communication unit and method therefor
A radio frequency (RF) transmitter including at least one digital signal processing module is described. The at least one digital signal processing module is arranged to receive a complex digital input signal, successively apply pre-distortion to the received complex digital input signal with a progressively finer granularity, simultaneously progressively increase a sampling rate of the received complex digital input signal, and output a first, in-phase digital control word and a second, quadrature, digital control word for controlling at least one digital power amplifier component to generate an RF signal representative of the received complex digital input signal. |
| US09379740B2 |
Channel coding method of variable length information using block code
A method for channel-coding information bits using a code generation matrix including 32 rows and A columns corresponding to length of the information bits includes, channel-coding the information bits having “A” length using basis sequences having 32-bit length corresponding to columns of the code generation matrix, and outputting the channel-coded result as an output sequence. If “A” is higher than 10, the code generation matrix is generated when (A-10) additional basis sequences were added as column-directional sequences to a first or second matrix. The first matrix is a TFCI code generation matrix composed of 32 rows and 10 columns used for TFCI coding. The second matrix is made when at least one of an inter-row location or an inter-column location of the first matrix was changed. The additional basis sequences satisfy a value 10 of a minimum Hamming distance. |
| US09379734B2 |
Method and arrangement for setting an effective resolution of an output signal in incremental delta-sigma analog-to-digital converters
A method and arrangement for setting an effective resolution of an output signal in an incremental delta-sigma analog-to-digital conversion by an incremental delta-sigma analog-to-digital converter, includes feeding a difference between an input signal and a reference voltage signal formed in a feedback branch to a first integrator. Safeguarding the stability of multi-stage incremental delta-sigma analog-to-digital converters for large input signal ranges and not requiring direct damping of the input signal, such that a direct SNR impairment with regard to the ADC-inherent noise sources can be avoided, is achieved by a virtual reference voltage in the feedback branch of the incremental delta-sigma analog-to-digital converter. The reference voltage signal is adapted to a changing input signal range by a settable reference capacitance and a clock cycle number dependent thereon is set. |
| US09379731B1 |
Closed loop linearized VCO-based ADC
A device and method for analog to digital conversion is disclosed. The device can have a first amplifier operable to receive an input voltage and output a first control signal. The device can also have a first voltage-controlled oscillator (VCO) operably coupled to the first amplifier and configured to output a first signal based on the first control signal, the first signal having a sensor frequency. The device can also have a first switched-capacitor resistor operably coupled to the first VCO and to the first amplifier, the first switched-capacitor resistor configured to receive and be controlled by the sensor frequency. The device can also have a sensor counter operably coupled to the first VCO and configured produce a sensor count based on the sensor frequency. The device can also have a register configured provide a digital output proportional to the input voltage based on the sensor count. |
| US09379723B2 |
Method and apparatus for generating a digital signal of tunable frequency and frequency synthesizer employing same
A method for generating a digital signal of tunable frequency may include generating a periodic first analog signal, determining a sign of a first difference between a value of the first analog signal and a first control value to determine sign flips, wherein the first control value is a variable value, and generating the digital signal of tunable frequency on the basis of the determined sign of the first difference, wherein the digital signal of tunable frequency is generated such that a subset of switches of the signal level are coincident with a respective sign flip of the determined sign of the first difference. |
| US09379721B2 |
Capacitive arrangement for frequency synthesizers
An electronic device has a capacitive arrangement for controlling a frequency characteristic. The capacitive arrangement has varactor banks having a number of parallel coupled varactors and a control input for switching the respective varactors on or off. A main varactor bank has N varactors and a series varactor bank has A varactors, the main varactor bank being connected in series with the series varactor bank. A shunt varactor bank of B varactors may be coupled to a ground reference and connected between the main varactor bank and the series varactor bank. When a varactor is switched in the main varactor bank, it provides an equivalent capacitance step size (or frequency step) smaller than size of a capacitance step when switching a single varactor on or off. According to the number of varactors selected in the shunt varactor, B, this frequency step can be made programmable. By the arrangement of unitary varactors a very small step size is achieved for providing a high resolution of frequency of a digitally controlled oscillator. |
| US09379711B2 |
Programmable logic device and semiconductor device
A programmable logic device includes a plurality of programmable logic elements (PLE) whose electrical connection is controlled by first configuration data. Each of The PLEs includes an LUT in which a relationship between a logic level of an input signal and a logic level of an output signal is determined by second configuration data, an FF to which the output signal of the LUT is input, and an MUX. The MUX includes at least two switches each including first and second transistor. A signal including third configuration data is input to a gate of the second transistor through the first transistor. The output signal of the LUT or an output signal of the FF is input to one of a source and a drain of the second transistor. |
| US09379710B2 |
Level conversion circuit and method
A level conversion circuit is provided for generating an output signal having one of a higher output level and a lower output level in response to an input signal having one of a higher input level and a lower input level. The level conversion circuit has input circuitry which, in response to a transition of the input signal between the higher and lower input levels, output a rising transition of a temporary output signal on the output line towards the higher input level. Output control circuitry detects the rising transition of the temporary output signal and pulls the output signal to the higher output level. This arrangement allows for fast level conversion without a DC leakage path. |
| US09379709B2 |
Signal conversion
A circuit may include an input terminal configured to receive an input signal with a first voltage swing and an output terminal. The circuit may also include a first transistor, a second transistor, a third transistor, and a control circuit. The control circuit may be coupled to the input terminal, a gate terminal of the first transistor, and a gate terminal of the second transistor. The control circuit may be configured to adjust voltages provided to the gate terminals based on the input signal such that the first transistor conducts in response to the input signal being at a first logical level and the second transistor conducts in response to the input signal being at a second logical level to generate an output signal output on the output terminal. The second voltage swing of the output signal may be different from the first voltage swing of the input signal. |
| US09379706B2 |
Programmable logic device
Disclosed is a programmable logic device (PLD) which can undergo dynamic configuration at a high speed. The PLD includes a plurality of programmable logic elements (PLEs) and a switch for selecting electrical connection between the PLEs. The switch includes a plurality of circuit groups each of which includes first and second transistors. The second transistors of the circuit groups are electrically connected in parallel with one another. In each of the circuit groups, the electrical conduction between a source and a drain of the second transistor is determined based on configuration data held at a node between the gate of the second transistor and a drain of the first transistor, which allows the selection of the electrical connection and disconnection between the programmable logic elements by the selection of one of the circuit groups. |
| US09379705B2 |
Integrated circuit and semiconductor device including the same
An integrated circuit (IC) includes at least one unit cell. The at least one unit cell includes a first bit circuit configured to process a first bit signal, a second bit circuit configured to process a second bit signal, a first well spaced apart from boundaries of the at least one unit cell and biased to a first voltage, and a second well biased to a second voltage that is different from the first voltage. Each of the first and second bit circuits includes at least one transistor from among a plurality of transistors disposed in the first well. |
| US09379704B2 |
Touch panel
A touch panel including a substrate, a plurality of first electrode lines, and a plurality of second electrode lines is provided. The first electrode lines are arranged on the substrate in parallel and extended along a first axial direction. Each first electrode line includes multiple first electrode pads and multiple first bridge portions serially connecting the first electrode pads. Each first electrode pad includes a first central portion and two first side portions connected to the first central portion. The second electrode lines are arranged on the substrate in parallel and extended along a second axial direction perpendicular to the first axial direction. Each second electrode line includes multiple second electrode pads alternatively disposed with the first electrode lines and multiple second bridge portions serially connecting the second electrode pads. Each second electrode pad includes a second central portion and two second side portions connected to the second central portion. |
| US09379697B2 |
Gate driver circuit and display apparatus having the same
This disclosure provides a gate driver circuit in a display. The gate driver circuit includes shift registers configured for receiving clock and start signals and generating a gate signal to drive a row of the pixels, arranged at intersections of the gate lines and the data lines on a panel, each register comprising: a control unit having a clock input, a first voltage input, a second voltage input, and a first output; and a first output unit having a first pull-down TFT electrically connected to one of the first outputs and a gate-driving terminal configured for providing the gate signal; wherein one of the clock signals at the clock input is provided to the first output unit; and a first control signal's period at the first output is longer than the clock signal's period at the clock input and shorter than the period of a frame. |
| US09379696B2 |
High voltage bootstrap gate driving apparatus
A high voltage bootstrap gate driving apparatus is provided. The gate driving apparatus includes a high-end transistor, a low-end transistor, a buffer, a boost capacitor, and a high voltage depletion transistor. The high-end transistor receives a first power voltage. The buffer provides a high-end driving signal to the high-end transistor according to a bias voltage. The boost capacitor is serial coupled between a base voltage and a bias voltage. A first end of the depletion transistor is coupled to a second power voltage, a second end of the depletion transistor is coupled to the bias voltage, and a control end of the depletion transistor receives the reference ground voltage. |
| US09379694B2 |
Control-voltage of pass-gate follows signal
A pass-gate has a passageway between an input node and an output node. The pass-gate selectively opens or closes the passageway for a signal at the input node under control of a voltage. The pass-gate has a field-effect transistor with a gate electrode and a current channel. The current channel is arranged between the input node and the output node. The gate electrode receives the voltage. The pass-gate is configured so as to have the voltage at the control electrode substantially follow the signal at the input node when the passageway is open to the signal. |
| US09379690B2 |
Duty cycle controller
In one aspect, a duty cycle controller includes a first port configured to receive a voltage bias signal, a second port configured to receive an input voltage signal, a third port configured to provide an output signal of the duty cycle controller having a duty cycle and a n-bit digital-to-analog converter (DAC) configured to receive the voltage bias signal and to provide a DAC output signal to a comparator. The DAC output signal has a peak value. The duty cycle controller also includes the comparator configured to compare the DAC output signal from the n-bit DAC with the input voltage signal to provide a comparator output signal. The comparator output signal is used to provide the output signal of the duty cycle controller and the duty cycle changes with changes to the input voltage signal. |
| US09379689B2 |
Integrated circuit
An integrated circuit includes a latch block suitable for storing a signal through four or more even-numbered coupling lines inverted and driven alternately with each other, wherein the coupling lines are divided into two or more coupling line groups each including coupling lines inverted and driven to the same logic level, and a charge buffer block coupled between two or more coupling lines included in one of the coupling line groups and suitable for slowing down a charge movement speed therebetween. |
| US09379687B1 |
Pipelined systolic finite impulse response filter
A systolic FIR filter circuit includes a plurality of multipliers, a plurality of sample pre-adders, each respective one of the sample pre-adders connected to a sample input of a respective multiplier, and an output cascade adder chain including a respective output adder connected to a respective multiplier. The output cascade adder chain includes a selectable number of delays between adjacent output adders. An input sample chain has a first leg and a second leg. Each respective one of the sample pre-adders receives a respective input from the first leg and a respective input from the second leg. The input sample chain has, between adjacent sample points in at least one of the legs, a selectable number of sample delays related to the selectable number of output delays. Connections of inputs from the input sample chain to the sample pre-adders are adjusted to account for the selectable number. |
| US09379684B2 |
Recorder
The recorder includes: a converter acquiring external sound and converting the sound into a first signal; an amplifier amplifying the first signal to generate a second signal; a recording unit recording the second signal; a display unit displaying a level of the second signal; and a controller controlling the amplifier and the display unit. The amplifier includes an ALC (automatic level control) unit adjusting an amplification degree for amplifying the first signal according to the level of the second signal. The controller allows a choice of whether or not to cause the ALC unit to operate, allows a choice of whether to display or hide the level of the second signal on the display unit when the automatic level control unit operates, and keeps the level of the second signal displayed on the display unit when the automatic level control unit does not operate. |
| US09379683B2 |
Volume interactions for connected playback devices
Methods and systems are provided for volume interactions for connected playback devices. In one example, a playback device applies a state variable update associated with a playback device in a plurality of playback devices, the state variable update indicating a limited volume range associated with the playback device. The playback device receives data indicating a group volume adjustment for the plurality of playback devices. The playback device determines that applying the group volume adjustment to the playback device would not result in the playback volume of the playback device exceeding the volume limitation of the playback device. Based on the determination that applying the group volume adjustment to the playback device would not result in the playback volume of the playback device exceeding the volume limitation of the playback device, the playback device adjusts the playback volume of the playback device according to the group volume adjustment. |
| US09379682B2 |
Digital equalizer adaptation using on-die instrument
Systems and methods are provided for adjusting gain of a receiver. Adaptation circuitry is operable to identify, based on a matrix representation of a receiver's output generated from horizontal and vertical sweeps of the receiver's output, an eye opening of the receiver's output. The adaptation circuitry is also operable to determine whether a size of the eye opening needs to be changed. When it is determined that the size of the eye opening needs to be changed, the adaptation circuitry is operable to generate a digital signal to change a gain setting of the receiver. When the signal at the receiver's output is under-equalized, the AC gain of the receiver is increased. When the signal at the receiver's output is over-equalized, the AC gain of the receiver is decreased. |
| US09379674B2 |
Transimpedance pre-amplifier with improved bandwidth
A transimpedance pre-amplifier (TIA) with an improved bandwidth. In the TIA, a feedback circuit is added to a regulated cascode structure to be connected in parallel, so that an input resistance value is reduced and a bandwidth is easily broadened. Alternatively, an inductor is added to the regulated cascode structure, so that an input capacitance is reduced and bandwidth is easily broadened. |
| US09379670B2 |
Communications based adjustments of an offset capacitive voltage
A parallel amplifier and an offset capacitance voltage control loop are disclosed. The parallel amplifier has a parallel amplifier output, which is coupled to an envelope tracking power supply output via an offset capacitive element. The offset capacitive element has an offset capacitive voltage. The offset capacitance voltage control loop regulates the offset capacitive voltage, which is adjustable on a communications slot-to-communications slot basis. |
| US09379668B1 |
Envelope tracking circuits and methods with adaptive switching frequency
The present disclosure includes envelope tracking circuits and methods with adaptive switching frequency. In one embodiment, a circuit comprising an amplifier to receive an envelope tracking signal having an envelope tracking frequency and output voltage and current to a power supply terminal of a power amplifier circuit. A programmable comparator receives an output signal from the amplifier and generates a switching signal having a switching frequency. A switching regulator stage receives the switching signal and outputs a switching current to the power supply terminal. A frequency comparison circuit configures the programmable comparator based on the envelope tracking frequency and the switching frequency so that the switching frequency tracks the envelope tracking frequency. |
| US09379665B2 |
Oscillator
A terahertz wave oscillator that oscillates includes a negative resistance element, a resonator including a first conductor, a second conductor, and a dielectric, and a transmission line configured to supply a bias voltage to the negative resistance element. In this case, the negative resistance element and the dielectric are disposed between the first conductor and the second conductor, and the first conductor and the transmission line are connected at a node of an electric field of terahertz waves having oscillation frequency fOSC and standing in the resonator. |
| US09379662B2 |
System and method using temperature tracking for a controlled oscillator
A system using temperature tracking for a controlled oscillator (CO) is provided. The system includes at least one coarse tuning capacitor circuit including a plurality of selectable coarse tuning capacitors operable in at least three modes of operation, thereby allowing switching between each coarse capacitor of the plurality of selectable coarse capacitors when a selected coarse tuning capacitor has reached one of its high tuning range and low tuning range. |
| US09379651B2 |
Method and assembly for operating synchronous motors
A method is disclosed for operating a synchronous machine by way of a three-phase AC power controller, which is connected to a three-phase network. The embodiment of the method includes determining the phase difference between the magnet-wheel voltage of the synchronous machine and the network voltage of the three-phase network; determining the rotational speed of the rotor of the synchronous machine; determining the phase position of the three-phase network; determining a decision characteristic number on the basis of a stored data table calculated in advance, which data table associates a decision characteristic number with value triples of phase difference, phase position, and rotational speed; and determining at least one switching time point on the basis of the decision characteristic number. |
| US09379649B2 |
Linear motor system
A linear motor system includes a stator, a mover, and a controller. The stator includes a plurality of armature coil units arranged so as to be spaced apart from one another at certain intervals. The mover includes a permanent magnet. The controller is configured to sequentially select, as a power-feeding target, an armature coil unit opposing the mover from among the plurality of armature coil units, perform, for the power-feeding target, computation for power-feeding control on the basis of a speed command, and sequentially feed power to the armature coil unit. The controller includes a power-feeding-switching compensation function of performing switching compensation when the power-feeding target is switched to a next armature coil unit. |
| US09379646B2 |
Method and assembly for operating synchronous motors
A method is disclosed for operating a synchronous machine via a three-phase power controller including three semiconductor controllers and connected to a three-phase network. The method includes determining the phase difference between the magnet-wheel voltage of the synchronous machine and the network voltage of the three-phase network; determining the rotational speed of the rotor of the synchronous machine; determining the phase position of the three-phase network; determining at least some of the stator currents of the synchronous machine; determining a decision characteristic number based upon an advance calculation of the torque curve in the event of activation of at least two of the semiconductor controllers while taking into account the current values for phase difference, rotational speed, stator current, and phase position; and determining at least one switching time point based upon the decision characteristic number, wherein the at least two semiconductor controllers are activated at the switching time point. |
| US09379643B2 |
Electrosurgical generator controller for regulation of electrosurgical generator output power
An electrosurgical generator may reduce unintended tissue damage by improving regulation of output power. The electrosurgical generator may control the power during a cycle, and react to a change in power if arcing occurs. Voltage sources, especially, demonstrate the tendency to have large, uncontrolled power excursions during normal electrosurgical use. The magnitude of the power excursions may be dependent on various factors. An exemplary electrosurgical generator control scheme reduces or minimizes the thermal spread by accurately supplying the specified power within a few cycles. Additionally, fast and accurate regulation provided by the constant voltage mode reduces or minimizes unintentional tissue charring. Thus, reduced thermal spread and charring should result in better surgical outcomes by reducing scarring and decreasing healing times. An electrosurgical generator controller may be configured to control both a DC-DC buck converter and a DC-AC boost inverter based in part on electrical parameters of the electrosurgical generator. |
| US09379641B2 |
Energy recovery circuit for distributed power converters in solar cells
A method of operating an inverter device configured on a back plane of a solar module, the inverter device comprising an energy recovery circuit device coupled to a rectifier circuit, the method comprising transferring a charge from a rectifier output to a storage capacitor configured in an energy recovery circuit; storing the charge at the storage capacitor for a time period associated with a reverse recovery time; and transferring the charge to an output of a DC bus structure to reduce a diode recovery loss in the rectifier circuit. |
| US09379630B2 |
Control circuit for a synchronous rectification circuit, LLC resonant converter and associated method
A control circuit for a synchronous rectification circuit, a LLC resonant converter and a control method. The control circuit has a first comparing circuit, a second comparing circuit, a blanking circuit, a first logic circuit and a second logic circuit. The blanking circuit is configured to provide a first blanking signal and a second blanking signal to avoid one or more repeated conduction of a first synchronous rectifier and a second synchronous rectifier respectively, and the first blanking signal and the second blanking signal are logic complementary. |
| US09379626B2 |
Power supply circuit for a PFC converter
A PFC converter (100) is disclosed that includes a voltage rectifier circuit (126, 127, 153) and a voltage regulator circuit (81, 90, 33, 54). The PFC converter (100) also includes an inductor (140) having a plurality of auxiliary windings (141, 142) coupled to the voltage rectifier circuit (126, 27, 153) and the voltage regulator circuit (81, 90,33, 54). One of the auxiliary windings (142) is arranged to supply a start up voltage (V1), during a start up stage, using the voltage rectifier circuit (126, 127, 153) to the voltage regulator circuit (81, 90, 33, 54). Another of the auxiliary windings (141) is arranged to supply a voltage (V1), during a steady-state stage, using the voltage rectifier circuit (126, 127, 153) to the voltage regulator circuit (81, 90, 33, 54). |
| US09379625B2 |
Current meter for load modulation communication receiver architecture
A load device on a secondary side of an isolated switching power converter communicates a digital message to a primary side controller by modulating the load current in accordance with certain predefined timing patterns. The load current modulation is detected by the primary side controller and the digital message is decoded based on the predefined timing patterns. The load device may encode the digital message in order to control the primary side controller to operate in a particular mode compatible with the load device. |
| US09379620B2 |
Zero voltage soft switching scheme for power converters
A control scheme and architecture for a power conversion circuit employs two bidirectional switches and a zero voltage switching (ZVS) scheme for the high-side switch. Methods of incorporating the control scheme into multiple power conversion circuit topologies are disclosed. Methods of device integration including co-packaging and monolithic fabrication are also disclosed. |
| US09379619B2 |
Dividing a single phase pulse-width modulation signal into a plurality of phases
Dividing a single phase PWM signal into a plurality of phases includes: receiving, from a phase controller by a PWM frequency divider, an input pulse train comprising a period; and dividing, by the PWM frequency divider, the input pulse train amongst a plurality of output phases of the PWM frequency divider, including, at the onset of each period of the input pulse train: providing, on a next output phase of the PWM frequency divider, an output pulse train; and holding all other output phases at a tri-state voltage level. |
| US09379618B2 |
Power device for delivering power to electronic devices and methods of assembling same
An energy efficient apparatus includes a switching device, a frequency dependent reactive device, and a control element is provided. The switching device is coupled to a source of electrical power and includes a pair of transistors and is adapted to receive a control signal and to produce an alternating current power signal. The frequency of the alternating current power signal is responsive to the control signal. The frequency dependent reactive device is electrically coupled to the pair of transistors for receiving the alternating current power signal and producing an output power signal. The frequency dependent reactive device is chosen to achieve a desired voltage of the output power signal relative to the frequency of the alternating current power signal. The control element senses an actual voltage of the direct current power signal and modifies the control signal delivered to achieve the desired voltage of the direct current power signal. |
| US09379611B2 |
SIMO (single inductor multiple output) bidirectional dual-boost architecture
A switching power converter circuit comprises an input port, a first circuit supply rail having a first positive voltage greater than circuit ground, a second circuit supply rail having a second positive voltage greater than circuit ground, and an inductor electrically coupled to the input port, wherein inductor current flows in a first direction through the inductor to generate the first circuit supply rail and flows in an opposite direction through the inductor to generate the second circuit supply rail. |
| US09379610B2 |
Buck variable negative current
An active diode formed within a buck power regulator with an NMOS transistor is connected to a PMOS transistor at a node that is further connected to the regulator output through an inductor. The active diode combines the NMOS transistor with circuitry to prevent conduction once the active diode passes a threshold voltage. Additional circuitry compares the output voltage to the target input voltage and varies the threshold voltage of the active diode such that the active diode can discharge excess current from the regulator each cycle until the output voltage is less than the target voltage. |
| US09379605B2 |
Clocking circuit, charge pumps, and related methods of operation
A charge pump includes a voltage multiplier core and a clocking circuit. The voltage multiplier core includes first and second cross-coupled CMOS devices, first and second output CMOS devices, a first capacitive node coupled between the first cross-coupled CMOS device and the first output CMOS device, and a second capacitive node coupled between the second cross-couple CMOS device and the second output CMOS device. The clocking circuit configured to control the first and second output CMOS devices to inhibit a drop in respective output voltages there from, while simultaneously controlling the first and second cross-coupled CMOS device and input voltages applied to the first and second capacitive nodes to minimize leakage from the first and second capacitive nodes. |
| US09379604B2 |
Low noise radio frequency switching circuitry
Radio frequency (RF) switching circuitry includes support circuitry for maintaining one or more RF switching elements in either an ON or OFF state. The support circuitry includes a negative charge pump adapted to quickly generate a negative voltage during a “boost” mode of operation, and maintain the negative voltage during a normal mode of operation. The negative charge pump includes an oscillator adapted to generate a high frequency oscillating signal for driving the charge pump during the boost mode of operation and a low frequency oscillating signal for driving the charge pump during the normal mode of operation. By generating the high frequency oscillating signal only during a boost mode of operation, spurious noise coupled to the RF switch circuitry is minimized during a normal mode of operation. |
| US09379598B2 |
Absolute encoder device and motor
The present invention provides an absolute encoder device, including: a permanent magnet including a first magnetic pattern (bipolar) and a second magnetic pattern (multipolar); a first magnetic sensor for detecting a magnetic field of the first magnetic pattern; a second magnetic sensor for detecting a magnetic field of the second magnetic pattern; and a signal processing circuit for calculating an absolute rotation angle of a rotation shaft based on output signals of the first and second magnetic sensors. The first and second magnetic sensors and the signal processing circuit are fixed to a single substrate. The first magnetic pattern is formed on a plane extending in a direction crossing an axial direction inside the permanent magnet, and the second magnetic pattern is formed on an outer peripheral surface of the permanent magnet. |
| US09379597B2 |
System for driving electromagnetic appliance and motor driven vehicle
In one embodiment, system for driving an electromagnetic appliance includes an electromagnetic appliance, a main-drive unit and a sub-drive unit. The electromagnetic appliance includes coils for n number of phases, the coils for each of the n phases being arranged in a pair and wound so as to be excited in a predetermined direction by being energized with opposite-phase currents. The main drive unit is connected to each of the coils and energizes the paired coils with opposite-phase currents. The sub-drive unit is provided parallel with the main-drive unit and is configured to suppress a short-circuit current occurring at the main-drive unit when switching energization of the coils. |
| US09379592B2 |
Actuator for a flap for opening and closing an air passage
The invention relates to an actuator for a flap for opening and closing an air passage in an air conditioner, ventilator, and/or heater, comprising a housing (1) shaped to accommodate a motor as well as a gearing arrangement. The actuator is characterized in that the housing (1) includes at least one abutment element (5) for limiting the movement of a rotational shaft (3) with respect to the casing of the motor, as well as a means (6) for compensating for a space between the abutment element (5) and a free end of the rotational shaft (3). |
| US09379591B2 |
Motor with integrated coupler
Couplings between driven shafts of an actuator and a motor of an actuator are provided. The coupling may be directly integrated into a rotor of the motor. The coupling may be provided by an adaptor that includes a shaft that extends into a central bore of the rotor of the motor. The adaptor can include a collar that defines a coupling recess that receives a distal end of the driven shaft of the actuator. The collar may take the form of a clamp. |
| US09379588B2 |
Stator of rotating electrical machine and rotating electrical machine
A stator of a rotating electrical machine includes a stator core, plural stator coil groups constituting plural phases, plural pieces of interphase insulation paper for insulation of coils belonging to different phases, and plural connecting strips formed integrally with the interphase insulation paper pieces. Each interphase insulation paper piece has ends inserted between coil ends of unit coils belonging to an identical phase thereby to function as interphase insulation paper for insulation of coils belonging to the identical phase. Each interphase insulation paper piece for insulation of coils belonging to the different phases, functioning as the interphase insulation paper piece for insulation of coils of the identical phase, insulates between coil ends of the first unit coils of respective first and second series circuits constituting the inner circumference side phase and a coil end of the unit coil constituting the outer circumference side phase. |
| US09379581B2 |
Drive unit, particularly for a revolving door, with an electronically commutated multipole motor
A drive unit for a door includes an electronically commutated multipole motor having: a stator part configured to be arrangable at a stationary structural component part; and a rotor part configured to be gearlessly connectable to a rotationally drivable element. The stator part and the rotor part include sheet metal elements stacked in a package-like manner. The sheet metal elements of the stator part and the sheet metal elements of the rotor part extend parallel to one another. |
| US09379575B2 |
Battery charger noise reduction by frequency switching
A method of charging a battery in a charging system having a power convertor that coverts AC electrical power to DC electrical power includes operating the power convertor at a first frequency during a first charging phase of the charging system; ending the first charging phase upon determining that a predetermined criterion is satisfied; and subsequent to ending the first charging phase, operating the power convertor at a second frequency during a second charging phase of the charging system, wherein the first frequency is different than the second frequency. |
| US09379566B2 |
Apparatus and method for controlling charge for battery
An apparatus for controlling a charge for a battery is provided. The apparatus includes an input unit that is configured to convert alternating current (AC) input power into direct current (DC) power. A first converter is configured to store or output the DC power and a circuit unit is configured to filter or boost output power based on a normal operation state or an instantaneous power failure state of the AC input power. In addition, a second converter is configured to convert the filtered or boosted power and supply the power to a high voltage battery. |
| US09379565B2 |
Battery pack, method of charging the same, and vehicle including the same
A battery pack, a method of charging the same, and a vehicle including the same. The battery pack includes: a battery cell for storing electric power; and a Battery Management System (BMS) for controlling charging or discharging the battery cell, wherein, in order to charge the battery cell, the BMS increases a charge current in a first period of time, decreases the charge current in a second period of time, and increases the charge current again in a third period of time. |
| US09379564B2 |
Charging control apparatus and charging control method
A charging control method for controlling a charge operation to a storage unit E2 of a vehicle, using a charging cable CC that is connected to a charging inlet E1 of the vehicle and supplies power to the storage unit E2 from an external power supply BP provided outside the vehicle, the method has detecting connection of the charging cable CC to the charging inlet E1, detecting a command signal of a disconnection command unit C22 of the charging cable CC, pausing the charge operation to the storage unit E2 while maintaining a closed state of relay switches C42, E5, E6 of a vehicle side power supply line for only a predetermined time when detecting the command signal of the disconnection command unit C22 which indicates the disconnection in a state where the charging cable CC is connected to the charging inlet E1, and restarting the charge operation to the storage unit E2 when detecting a command signal of the disconnection command unit C22 which indicates cancel of the disconnection during the predetermined time. |
| US09379562B2 |
Holding assembly for portable electronic device
Holding assembly for a portable electronic device includes a base, a holder, and a charging unit. The holder is pivotably coupled to the base and supports the portable electronic device. The charging unit includes a radio frequency (RF) transmission module and a RF receiving module. The RF transmission module is coupled to the holder, the RF receiving module is integrated with the portable electronic device. The RF receiving module communicates with the RF transmission module via electromagnetic induction to charge the portable electronic device. |
| US09379558B2 |
Dual rate charger for notebook computer
A apparatus includes an AC adapter input, a main battery charger coupled to the input to charge a main battery, system logic to execute code stored on storage devices, and an expansion battery connector coupled to the input to provide sufficient current to enable charging of an expansion battery at a rate higher than a maximum charge rate of the main battery charger. |
| US09379555B2 |
Adaptive power source for wireless power transmitter
A system includes an adaptive power source, a wireless power transmitter, and a wireless power receiver. The adaptive power source supplies a supply voltage across a Universal Serial Bus (USB) connector onto the wireless power transmitter that thereby transmits energy to the wireless power receiver. The wireless power transmitter has a USB plug that is inserted into a USB port of the adaptive power source. The wireless power transmitter sends a power control command to the adaptive power source across the USB connector. The power control command determines the supply voltage to be supplied to the wireless power transmitter. If the wireless power receiver determines the power level should be adjusted, then the wireless power receiver sends a wireless control communication to the wireless power transmitter. The wireless power transmitter reads the wireless control communication and sends a power control command to set the supply voltage to a desired level. |
| US09379552B2 |
Power conversion system for a multi-stage generator
An electric power generation system is provided, including a generator having a plurality of stages engaged by a prime mover; and a plurality of branches for connecting the stages to an electrical load, each of the branches having a switch for connecting or disconnecting the branch to the stages. Power from a prime mover, such as a turbine, is sent by a controller to one or more of the branches as appropriate to handle the power level generated. |
| US09379551B2 |
Methods and systems for controlling a power converter
A line angle shift logic controller for use with a power generation system coupled to an electrical grid is disclosed. The line angle shift controller includes a line angle shift controller configured to receive a phase locked loop (PLL) error signal representative of a difference between a phase angle of the power generation system and a phase angle of the electrical grid, receive a threshold phase from the electrical grid, and generate a PLL shift signal based at least partially on the PLL error signal and the threshold phase. |
| US09379543B2 |
Integrated circuit energy harvester
A system for energy harvesting comprises a first interface for receiving energy from at least one renewable energy source (ERS); a second interface coupled to at least one load circuit; a third interface coupled to an least one primary energy storage (PES); a DC-to-DC converter connected to one of a single inductor and a single capacitor; a switching circuitry connected to the first, second, and third interfaces and the DC-to-DC converter; a control unit connected to the DC-to-DC converter and the switching circuitry, the control unit controls the system to operate in an operation mode including any one of: provide energy from the ERS to the at least one load via the DC-to-DC converter, charge the least one PES from the at least one ERS via the DC-to-DC converter, and provide energy from the at least one PES to the at least one load circuit via the DC-to-DC converter. |
| US09379542B2 |
System for multiple inverter-driven loads
A system for controlling multiple inverter-driven loads includes a controller that is configured to be coupled with an inverter that receives direct current and converts the direct current into an alternating current in order to supply the alternating current to plural loads that are connected to the inverter by plural respective contactors. The controller also is configured to control operations of the inverter and of the contactors in order to individually control which of the loads remain connected to and powered by the inverter and which of the loads are disconnected from the inverter. |
| US09379541B2 |
EOS protection circuit with FET-based trigger diodes
An integrated circuit is disclosed, including a circuit with a first type of FET having a first breakdown voltage (VBD), resulting from a first set of design and manufacturing process parameters and having VBD tracking characteristics resulting from a second set of design and manufacturing process parameters. The IC may include a trigger device circuit a having a trigger FET that may generate, in response to the supply voltage exceeding a specified maximum, a signal on a trigger device output, causing a clamping device to couple the supply voltage node to the ground, to reduce the supply voltage. The trigger FET may be of a second type having a second VBD less than the first VBD, resulting from modifications to the first set of design and manufacturing process parameters, and VBD tracking characteristics resulting from the second set of design and manufacturing process parameters. |
| US09379540B2 |
Controllable circuits, processes and systems for functional ESD tolerance
An electronic circuit (100) includes a first circuit (140) having an output and operable to give a warning but that has a sensitivity to an electrostatic discharge (ESD) event, a second circuit (120) that is operationally at least sometimes coupled with the output of said first circuit (140), whereby subject to some of the sensitivity, and a third circuit (240) interposed between said first circuit (140) and said second circuit (120) and operable to filter out at least one instance of an unnecessary warning so as to reduce the sensitivity to the ESD event. |
| US09379539B2 |
Protection circuit, circuit protection method using the same and display device
A protection circuit includes: a temperature measuring unit which compares a voltage corresponding to a temperature at each of a plurality of sense points with a reference voltage, and generates a measurement result based on a result of comparison; a controller which generates a plurality of current control signals, which controls currents of a plurality of channels corresponding to the plurality of sense points, respectively, based on the measurement result from the temperature measuring unit; and a plurality of phase converter which outputs the currents of the plurality of channels based on the plurality of current control signals, wherein the controller generates the plurality of current control signals until the voltage corresponding to the temperature of each of the plurality of sense points is substantially equal to the reference voltage. |
| US09379538B2 |
Output over-voltage protection circuit for power factor correction
An output over-voltage protection circuit for power factor correction, which includes a chip external compensation network, a chip external resistor divider network, a static over-voltage detection circuit, a dynamic over-voltage detection circuit and a compare circuit; The chip external compensation network is connected between the chip external resistor divider network and the dynamic over-voltage detection circuit, the chip external compensation network converts the dynamic over-voltage signal conversion to the dynamic current signal and conveys it to the dynamic over-voltage detection circuit, the dynamic over-voltage detection circuit detects the dynamic current signal and ultimately produces the dynamic over-voltage signal (DYOVP); The dynamic over-voltage signal (DYOVP) is inputted into the compare circuit, which converts the dynamic over-voltage signal (DYOVP) into a voltage compared with a reference voltage and outputs a over-voltage control signal (OVP), so as to achieve a dynamic over-voltage protection function. |
| US09379537B2 |
Power system including a circuit providing smart zone selective interlocking communication
A power system includes main circuit interrupters each having a load output, feeder circuit interrupters, a number of tie circuit interrupters, and a circuit. The circuit is structured to block communication, at least when at least one of the tie circuit interrupters has an open state between a first and a second of the main circuit interrupters, of a zone selective interlocking output of one of the feeder circuit interrupters having a line input electrically connected to the load output of the first main circuit interrupter to a zone selective interlocking input of the second main circuit interrupter, and of a zone selective interlocking output of a different one of the feeder circuit interrupters having a line input electrically connected to the load output of the second main circuit interrupter to a zone selective interlocking input of the first main circuit interrupter. |
| US09379534B2 |
Recloser device and method of operation
A device for interrupting a flow of electrical power in an electrical distribution system is provided. The electrical distribution network includes a circuit interrupting device, the circuit interrupting device having a reclose time. The device includes a sensor configured to generate a signal in the event of loss of system power. A switch is coupled to the electrical distribution system and is movable between an open and closed position. A controller is operably coupled to the sensor and the switch, the controller having a processor that initiates a timer in response to the signal and determines a measured reclose time with the timer. The processor is further responsive to actuate the switch in response to the measured reclose time is substantially equal to the reclose time of the at least one circuit interrupting device. |
| US09379533B1 |
Input surge protection circuit and method for an LED load
A light fixture includes a surge protection circuit for a non-isolated DC-DC converter. The converter is coupled to a circuit ground and further provides output power to a light source chassis configured to house a light source. The chassis is coupled to earth ground. The surge protection circuit includes a voltage triggering device having a breakdown voltage value and coupled to either the circuit ground or an output of the converter. A first capacitor is coupled in series between the voltage triggering device and the earth ground, and a second capacitor is coupled in parallel with the voltage triggering device. The first capacitor is configured with a sufficiently large capacitance wherein a voltage across the first capacitor, and likewise a voltage between the chassis and the earth ground, is effectively clamped to a light source threshold value during a surge condition. |
| US09379528B2 |
Cable tray service trolley
A cable tray trolley having a cushioned body configured to support a human, a frame configured to support the body and wheels that roll atop the rails of a cable tray to enable the trolley to travel along the length of the cable tray, the cable tray supporting the trolley. The trolley has adjustable torso and pelvic cushions and an adjustable leg support. The trolley also comprises a brake mechanism to slow or stop the travel of the trolley along the length of the cable tray. The trolley wheels are attached to the frame with adjustable shafts to enable the trolley to fit cable trays of varying widths. |
| US09379527B2 |
Stringing messenger clamp and methods of using the same
A stringing messenger clamp for use in overhead transmission and distribution systems and method of installing a messenger cable is provided. The stringing messenger clamp includes a bracket and an assembly body supported by the bracket, wherein the assembly body has a cable channel sized to receive a portion of a messenger cable. An assembly clamp is movable with respect to the assembly body and closable upon the cable channel. When the assembly clamp is in a closed position, it retains in place the portion of the messenger cable within the cable channel. |
| US09379520B2 |
Surface emitting laser and optical coherence tomography apparatus
In order to provide a wavelength tunable surface emitting laser capable of improving a wavelength tuning efficiency, provided is a surface emitting laser, including: a first reflector; a semiconductor cavity including an active layer; and a second reflector, the first reflector, the semiconductor cavity, and the second reflector being formed in the stated order, a gap portion being formed between the first reflector and a semiconductor layer, a cavity length being tunable, in which the surface emitting laser has a high reflectivity structure formed between the gap portion and the semiconductor cavity, and an expression of “(λ/2)×m+λ/8 |
| US09379507B2 |
Feedthrough system for implantable device components
The present subject matter provides feedthrough or interconnect systems for components of an implantable medical device and methods for their manufacture. A feedthrough system includes a wire or nailhead having a protruded tip. The wire or nailhead extends from an aperture in an encasement of a first component and is connected to a terminal conductor adapted to electrically connect to circuitry within the encasement. A ribbon wire has a distal end adapted to electrically connect to a second component and a proximal end having a pattern adapted to fit to the protruded tip of the wire or nailhead to provide for subsequent attachment of the ribbon wire to the nailhead. |
| US09379505B2 |
Method of manufacturing lead frame
A method of manufacturing a lead frame includes, firstly, forming a metal plate which has a frame portion, a pad portion for mounting semiconductor elements, and lead portions. After that, the lead portions are etched to form a support end, a connecting terminal and a jointing end of each lead portion. Then a receiving portion for receiving the semiconductor elements is formed, wherein the receiving portion is collectively defined by the connecting terminals, the support ends and the pad portion. After that, step portions are formed on the lead portions and the pad portion by half-etching. A method of manufacturing a semiconductor package which includes the lead frame is also provided. |
| US09379503B2 |
Electrified rail for powering metal shelving units and method for manufacturing the same
An electrified rail for metal shelving units, the rail comprising a body of electrically insulating material, provided with longitudinal slots. Each slot having a wire of electrically conducting metal surrounded for more than 180° of its cross section by the walls of the respective slot, the remaining section of the wires being exposed for electric contact. The body of the rail being formed to allow transversal elastic deformation of the rail itself after the surrounding and holding of the wires the slots are open on a visible planar side of the rail body with longitudinal mouths having a width always inferior to the diameter of wires, the wires being held in slots by the monolithic body of the rail itself, while through the narrow mouths of said slots every electric wire can be reached by the devices mounted on the rail. |
| US09379498B2 |
Coaxial connector with improved impedance characteristics
A coaxial connector includes an outer conductive member including a board mounting portion and a main body portion; an insulation member disposed in the outer conductive member; a central conductive member supported with the insulation member; and a metal member disposed in the outer conductive member below the insulation member. The metal member includes a through hole for retaining the central conductive member therein. The central conductive member is situated in the through hole away from an inner surface of the through hole by a first distance at an upper portion of the through hole. The central conductive member is situated in the through hole away from the inner surface of the through hole by a second distance at a lower portion of the through hole. The first distance is greater than the second distance. |
| US09379495B2 |
Electrical outlet provided with identification means, and associated electrical plug and electrical assembly
A socket outlet (100A; 100B; 100C; 100D) presenting given intrinsic characteristics so as to be suitable for delivering continuously, and without being damaged, an electrical signal that presents a determined maximum current, includes identification elements (130A; 130B; 130C; 130D) that are adapted to communicate or to co-operate with an electric plug (200A; 200B; 200C; 200D) so as to generate a pilot signal that is representative of the maximum current of the electrical signal that can be delivered by the socket outlet without being damaged. An electric plug and an electrical assembly are also described. |
| US09379491B2 |
Electrical connecting device
An electrical connecting device is provided, which includes a plate part fixed a first structure, and a leg extending from the plate part. When the first structure is mounted on a second structure, the leg is electrically connected to a housing part provided in the second structure. |
| US09379488B2 |
Enclosure assembly for a connector, strain relief element, and method
The invention relates to a mating enclosure having a flange, wherein the flange has a forward face, a rearward face, and a first outer perimeter, a central opening, wherein the central opening has a second outer perimeter contained within the first outer perimeter, at least one protrusion protruding substantially perpendicularly from the forward face of the flange, wherein the protrusion has an inner surface facing the central opening, an outer surface facing away from the central opening, and a forward surface facing in the same direction as the forward face of the flange, and at least one locking element positioned on the outer surface of the protrusion, wherein the locking element is at rest such that a distance between the outer perimeter of the flange and the locking element is less than a distance between the outer perimeter of the flange and the outer surface of the protrusion. |
| US09379486B2 |
Ratcheting lever actuated connector assembly
A connector assembly including a first and second connector configured to be connected to the first connector. The first connector has a slide including a cam groove for receiving a latch pin defined by the second connector. The slide is moved by a lever such that the cam groove and the latch pin cooperate to draw the first and second connectors from an uncoupled position to a fully coupled position when moved from an initial to final position. A ratcheting mechanism couples the lever to the slide allowing the lever to return from the final position to the initial position without disconnecting the first and second connectors. The lever is configured to move through more than one stroke from the initial position to the final position to bring the first and second connectors from the uncoupled position to the fully coupled position. |
| US09379485B2 |
Lever-type connector
A lever-type connector has a housing (20) and a linking wall (25) projects from the housing (20) to define a stop for a mating housing (90). A seal ring (70) is mounted adjacent to the linking wall (25) to provide sealing between the housing (20) and the mating housing (90). A lever (60) includes a coupling (61) and arm plates (62) to define a U-shape. The lever (60) is mounted from an outer side to straddle the housing (20). The linking wall (25) is arranged at a position facing the arm plates (62) from inner sides of the arm plates (62). Cam grooves (64) are provided in the arm plates (62) and function as confirmation windows through which the seal ring (70) is visible to confirm whether sealing is ensured. |
| US09379469B1 |
Method for assembling a multiple layer electronic assembly
Mechanisms for aligning electrical contacts of electronic components in a multiple layer electronic assembly are disclosed. A mounting plate is configured to align multiple layers of the multiple layer electronic assembly. The mounting plate includes a surface that a plurality of first anchor features at first predetermined locations of the surface configured to anchor a plurality of first layer electronic assemblies with respect to the surface. The mounting plate also includes a plurality of second anchor features at second predetermined locations configured to anchor at least one second layer electronic assembly with respect to the plurality of first layer electronic assemblies. |
| US09379463B2 |
Assembly comprising an adapter and a smart card
In an assembly including an adapter and a smart card, the outer dimensions of the adapter are compliant with the 3FF microcircuit card format, the format further defining the positioning and minimum dimensions of contact areas; the smart card includes a plurality of contact surfaces, the dimensions of which are greater than those defined by the 3FF format for the contact areas, the outer dimensions of the card being smaller than those of the 3FF format; and the adapter includes a recess, the outline of which is defined by a plurality of arms that surround the recess, the recess being shaped so as to receive the smart card so the contact areas of the adapter fit inside the contact surfaces of the smart card, each of the contact areas being off-center relative to each of the contact surfaces, so each arm has a width of 700 micrometers, ensuring mechanical stability. |
| US09379462B2 |
Cable connector and method of making the same
A cable connector includes an insulative housing, at least one group of circuit boards retained on the insulative housing, cables connecting with the circuit boards electrically, and insulator fixing the insulative housing, the circuit boards and the cables together. The insulative housing has a first receiving space and a second receiving space. The first receiving space spaces apart from the second receiving space along a front to back direction. Each circuit board has a front part received in the first receiving space and a rear part received in the second receiving space. The front part is formed with electrical contacts. The cables connect with the rear parts. The insulator is insert-molded in the second receiving space and encloses the rear parts. |
| US09379460B2 |
Terminal welded and crimped to a wire and a shrinkable tube covering the wire and the terminal
A terminal-provided wire (10) includes a wire (11) formed by covering a core (12) with an insulation coating (13), a terminal (20) to be connected to the core (12) exposed at an end of the wire (10), and a shrinkable tube (28) for sealing a wire connecting portion (25) formed by connecting the exposed core (11) and the terminal (20). An inclined surface (12A) for making a thickness of the core (12) smaller toward the tip of the core (12) is formed by welding on a part of the exposed core (12) before the wire connecting portion (25). |
| US09379459B2 |
Electrical connector
An electrical connector comprises a first single-piece contact bracket, a second single-piece contact bracket and a flat, flexible, electrically conductive strip. The first contact bracket and the second contact bracket are secured to the strip with spacing. |
| US09379458B2 |
Electrical connector element
The invention relates to an electrical connector element for creating a contact to a conductive structure, the same being located on a flat support, by means of a thermal bonding material, wherein means for fixing a conductor, the same being preferably flexible, are arranged on the side of said support which faces away from the conductive structure. According to the invention, the connector element is designed as a soldering foot which has the shape of a single circular ring, or of multiple circular rings arranged laterally. |
| US09379448B2 |
Polarization independent active artificial magnetic conductor
An active artificial magnetic conductor includes a ground plane and an array of unit cells coupled to the ground plane. Each unit cell includes a low impedance shunt coupled to the ground plane and an impedance element coupled to the low impedance shunt. A plurality of non Foster circuits are coupled in two different directions between impedance elements of adjacent neighboring unit cells in the array of unit cells. |
| US09379446B1 |
Methods and apparatus for dual polarized super-element phased array radiator
Methods and apparatus for a dual polarization super-element radiator assembly. In one embodiment, an assembly comprises a first waveguide, a series of slot couplers formed in the first waveguide, first and second conductive strips, a second waveguide adjacent to the first waveguide, a series of notches formed in a conductive material extending along or parallel to the longitudinal axis of the second waveguide, the notches having respective throats, a series of slots located proximate the notch throats, and a third conductive strip disposed over and aligned with the notches, wherein the slot couplers and the notches provide a dual polarization super-element radiator. |
| US09379445B2 |
Electronic device with satellite navigation system slot antennas
An electronic device may be provided with a satellite positioning system slot antenna. The slot antenna may include a slot in a metal housing. The slot may be directly fed or indirectly fed. In indirectly fed configurations, the antenna may include a near-field-coupled antenna feed structure that is near-field coupled to the slot. The near-field-coupled antenna feed structure may be formed from a planar metal structure. The planar metal structure may be a metal patch that overlaps the slot and that has a leg that protrudes towards the metal housing. A positive antenna feed terminal may be coupled to the leg and a ground antenna feed terminal may be coupled to the metal housing. |
| US09379438B1 |
Fragmented aperture for the Ka/K/Ku frequency bands
A system, device, and method for a broad-band array antenna are presented. More particularly, the application relates to a broad-band fragmented aperture phased array antenna for the Ka, K, and/or Ku frequency bands. In various exemplary embodiments, the antenna system may support dynamic polarization degradation correction. In one exemplary embodiment a method and system for a broad-band fragmented aperture phased array antenna for the Ka, K, and/or Ku frequency band is presented. In one exemplary embodiment, the fragmented aperture design functions in one or more of the Ku-band, K-band, and/or Ka-band. In another exemplary embodiment, the antenna system may include full electronic polarization agility. In one exemplary embodiment, the antenna system may further comprise a printed circuit board radiating element. The printed circuit board radiating element may be configured to function as an antenna. In one exemplary embodiment, the antenna system may support operation over multiple frequency bands. |
| US09379437B1 |
Continuous horn circular array antenna system
A continuous horn or flared radiator antenna system is provided. The antenna system provides for steering a beam within at least a first plane (e.g., in azimuth). Steering a beam includes selecting an operative portion or segment of a circular array of elements or probe feeds. Steering can also include electronically steering the resulting beam within a coverage area provided by the selected segment of probe feeds. The electronic steering within the coverage area can be performed through the selective operation of phase shifters. Multiple continuous horn radiator structures can be provided to support pointing or steering of a beam in a second plane (e.g., in elevation), operation in multiple frequency bands, and/or simultaneous transmission and reception of signals. |
| US09379432B2 |
Antenna device, electronic apparatus, and wireless communication method
An antenna device, includes: a ground plate to which first and second antennas, each including a radiating element and a ground terminal, are connected, with one of the first and second antennas being powered, the ground plate including: a first slit extending from a portion where the ground terminal of one antenna of the first and second antennas is connected to the ground plate, in a direction along to the ground terminal, and a second slit extending from the tip of the first slit in a direction along to the radiating element. |
| US09379430B2 |
Multiband antenna
A multiband antenna comprising a substrate having first and second surfaces. A first conductive plate is provided on the first surface and a second conductive plate is provided on the second surface. The second conductive plate at least partially overlaps the first conductive plate in the plane of the substrate. The antenna also comprises a ground plane, wherein the substrate is connected to and is substantially perpendicular to the ground plane, and a feeding port (412) that is electrically coupled to both the first and second conductive plates. The first conductive plate is configured to transmit or receive signals in a first frequency band and the second conductive plate (408) is configured to transmit or receive signals in a second frequency band. |
| US09379427B2 |
Methods for manufacturing an antenna tuning element in an electronic device
Custom antenna structures may be used to improve antenna performance and to compensate for manufacturing variations in electronic device antennas. An electronic device antenna may include an antenna tuning element and conductive structures formed from portions of a peripheral conductive housing member and other conductive antenna structures. The antenna tuning element may be connected across a gap in the peripheral conductive housing member. The custom antenna structures may be used to couple the antenna tuning element to a fixed custom location on the peripheral conductive housing member to help satisfy design criteria and to compensate for manufacturing variations in the conductive antenna structures that could potentially lead to undesired variations in antenna performance. Custom antenna structures may include springs and custom paths on dielectric supports. |
| US09379425B2 |
Signal splitter
A signal splitter for creating at least two symmetrical equal-power signals from an input signal for use in an amplifier device includes at least one input terminal pair and at least two output terminal pairs. A primary conductor structure supplied from the at least one input terminal pair is provided for induction of a current flow in at least two secondary conductor structures each connected to an output terminal pair of the at least two output terminal pairs and the at least two secondary conductor structures. A center of a conductor length of each of the at least two secondary conductor structures is connected to ground, and the primary conductor structure and the at least two secondary conductor structures are realized as conductor tracks applied to a printed circuit board. |
| US09379424B2 |
Compensation for length differences in vias associated with differential signaling
A circuit may include a differential via that may include a first via having a first-via length and a second via having a second-via length longer than the first-via length. The circuit may also include a differential stripline coupled to the differential via. The differential stripline may include a first trace and a second trace that are broadside coupled to each other over at least a portion of the differential stripline to form a broadside coupled portion of the differential stripline. The first trace may be coupled to the first via and may have a first-trace length. The second trace may be coupled to the second via and may have a second-trace length. The broadside coupled portion of the differential stripline may be offset from a plane intersecting substantially half-way between the first via and the second via such that the second-trace length is shorter than the first-trace length. |
| US09379422B2 |
Hydrogen-treated semiconductor metal oxides for photoelectrical water splitting
A method of electrode hydrogenation for photoelectrochemical (PEC) water oxidation is provided that includes annealing a PEC electrode in air, and annealing the PEC electrode in hydrogen to form a hydrogenated-PEC electrode, where PEC performance is improved by enhancing charge transfer and transport in the hydrogenated-PEC electrode. |
| US09379421B2 |
Sodium-oxygen cells
The present invention relates to sodium oxygen cells comprising (A) at least one anode comprising sodium, (B) at least one gas diffusion electrode comprising at least one porous support, and (C) a liquid electrolyte comprising at least one aprotic glycol diether with a molecular weight Mn of not more than 350 g/mol. The present invention further relates to the use of the invention sodium oxygen cells and to a process for preparing sodium supperoxide of formula NaO2. |
| US09379420B2 |
Battery system and method for cooling the battery system
A battery system having a cooling plate with a conduit therein is provided. The system further includes a battery module having first and second battery cells. The system further includes a compressor, and a condenser coupled between the compressor and the conduit of the cooling plate. The system further includes a microprocessor that determines a maximum temperature level of the first and second battery cells, and determines a target temperature level for the cooling plate based on the maximum temperature level. The microprocessor determines a temperature error value based on a difference between a temperature level and the target temperature level of the cooling plate, and determines a desired RPM value for the compressor based on the temperature error value. |
| US09379417B2 |
Lithium sulfur battery cathode electrode surface treatment during discharge
Methods and apparatus are provided for discharging a Li—S battery having at least one battery unit comprising a lithium-containing anode and a sulfur-containing cathode with an electrolyte layer there between. One method comprises electrochemically surface treating the sulfur-containing cathode during discharge of the battery. A method of electrochemically surface treating a cathode of a lithium-sulfide battery comprises applying at least one oxidative voltage pulse during a pulse application period while the lithium-sulfur battery discharges and controlling pulse characteristics during the pulse application period, the pulse characteristics configured to affect a morphology of lithium sulfide forming on the sulfur-containing cathode during discharge. |
| US09379416B2 |
Method for performing cell balancing of a battery system based on cell capacity values
A method for calculating the charge to balance for cells in a multi-cell battery. The method determines a depletion-goal state of charge (SOC) for the battery cells. The method determines a corresponding set of depletion-goal charges and usable charges for the set of cells, where the depletion-goal charge is calculated using the corresponding charge capacity and depletion-goal SOC and the usable charge is calculated using the corresponding actual charge and depletion-goal charge. The method determines a charge-bias using the set of usable charges. The method determines for the set of cells a corresponding set of charges to balance from the set of usable charges and the charge-bias. |
| US09379415B2 |
Entire solid lithium secondary battery
The present invention provides an entire solid lithium secondary battery comprising: a cathode; an anode; and a solid electrolyte layer disposed between the cathode and the anode. The solid electrolyte layer is formed of a Li(1-x)TaO3 crystal (where 0.12≦x≦0.46) having a trigonal ilmenite crystal structure. This entire solid lithium secondary battery has a good charge-discharge property. |
| US09379411B2 |
Non-aqueous electrolyte secondary battery
A non-aqueous electrolyte secondary battery has a negative electrode containing graphite particles as a negative electrode active material, a positive electrode containing a lithium-containing oxide of a transition metal or a lithium-containing phosphate of a transition metal as a positive electrode active material, and a non-aqueous electrolyte in which a lithium salt is dissolved in an organic solvent. The graphite particles have an exposed crystal face and are bonded with each other to be parallel to the orientation plane of each other, and the non-aqueous electrolyte contains a phosphate ester compound represented by the following general formula (1) to which an alkynyl group is bonded and/or an unsaturated phosphate ester compound represented by the following general formula (2): |
| US09379408B2 |
Hemmed fuel cell stack enclosure
A fuel cell system is provided which includes a compression retention enclosure with upper and lower compression shells and side sheet components coupled by interlocking hem joints. Methods for manufacturing compression retention enclosures with hem joints such that the enclosure remains sealed upon operational swelling of the fuel stack are also provided. A compression shell may be formed from a light weight composite structure having a polymeric layer interposed between steel skins, and an extension of the top steel skin may form a hemmed edge or may form a side sheet having a hemmed edge. Side sheet panels may be coupled to the end plates by interlocking two opposing hemmed edges to form the hem joint, or by sliding an opposing C-linking element between two hemmed edges held under compression force in an interlocking position. |
| US09379407B2 |
Fuel cell module
In a fuel cell stack constituting a fuel cell module, electrolyte/electrode assemblies and separators are alternately laminated. An electrolyte/electrode assembly is arranged on one end of the fuel cell stack in the lamination direction, while a separator is arranged on the other end of the fuel cell stack in the lamination direction. A terminal separator is arranged adjacent to the electrolyte/electrode assembly, while a load relaxation member is arranged adjacent to the separator. The terminal separator controls the supply of a fuel gas to a fuel gas channel, and the load relaxation member is configured of a laminate of a plurality of flat metal plates. |
| US09379405B2 |
Polymer electrolyte membrane having alkylether graft chain
An electrolyte membrane having alkylether graft chains for use in a fuel cell produced by a method of producing an electrolyte membrane for use in a fuel cell, including: performing radiation-induced graft polymerization of a vinyl monomer having nucleophilic functional groups, the vinyl monomer selected from an acylvinyl ether derivative, a styrene derivative, and a methacrylic acid derivative, with a polymer substrate comprising a polymer selected from a fluorine-containing polymer, an olefinic polymer, and an aromatic polymer; deprotecting the nucleophilic functional group, which is protected by an ester bond, of a graft chain on the polymer substrate introduced by the radiation-induced graft polymerization; and introducing an alkylethersulfonic acid structure into the deprotected nucleophilic functional group of the graft chain, by use of an electrophilic reagent selected from cyclic sulfonic acid ester and alkylhalide-sulfonate. |
| US09379399B2 |
Solid oxide fuel cell system
To provide a solid oxide fuel cell system capable of efficiently and simply controlling a low speed fuel cell module and a high speed inverter. The invention is a solid oxide fuel cell system, comprising: a fuel cell module, a fuel flow regulator unit, a control section comprising a first power demand detection circuit for controlling the fuel supply amount and for setting the value of current extractable from the fuel cell module; an inverter for extracting current from fuel cell module; and a second power demand detection circuit; and having an inverter control section for controlling the inverter independently from the fuel cell controller so that a current responsive to power demand is extracted from the fuel cell module in a range not exceeding the extractable current value input from the fuel cell controller. |
| US09379398B2 |
Apparatus and method of in situ catalyst degradation detection during fuel cell operation
Disclosed herein are catalyst degradation detection assemblies and methods of catalyst degradation detection that can be performed in-situ. One embodiment of an in-situ fuel cell catalyst degradation detection assembly comprises a humidified hydrogen supply configured to supply humidified hydrogen to an anode of a fuel cell, a humidified nitrogen supply configured to supply humidified nitrogen to a cathode of the fuel cell, a collection cell containing a liquid, the collection cell configured to receive either cathode exhaust from the fuel cell through a cathode exhaust line or anode exhaust from the fuel cell through an anode exhaust line and means for detecting a gas. |
| US09379395B2 |
Active cathode temperature control for metal-air batteries
A metal-air battery is disclosed, including a cathode temperature controller that identifies a power-boosted operating temperature at which a projected power boost exceeds a projected battery lifetime penalty and a temperature regulator that adjusts the cathode temperature to the power-boosted operating temperature using power generated by the metal-air battery when the metal-air battery is in a discharge state. |
| US09379391B2 |
Air electrode material powder for solid oxide fuel cell and its production process
To provide an air electrode material powder for a solid oxide fuel cell, comprising a novel LSCF powder having a highly uniform composition suitable as an air electrode material for a solid oxide fuel cell, and its production process.A composite oxide having a perovskite structure and containing lanthanum, strontium, cobalt, iron and oxide, wherein the dispersion point determined by the peak intensity [La] of the Lα1 characteristic X-ray of lanthanum and the peak intensity [Sr] of the Lα1 characteristic X-ray of strontium as obtained by EPMA measurement, is present within a range of the formula (1) and the dispersion point determined by the peak intensity [Co] of the Kα1 characteristic X-ray of cobalt and the peak intensity [Fe] of the Kα1 characteristic X-ray of iron is present within a range of the formula (2): a[La]−150≦[Sr]≦a[La]+150 (1) b[Co]−300≦[Fe]≦b[Co]+300 (2) wherein 0.2≦a≦1.0 and 0.1≦b≦4.0. |
| US09379390B2 |
Process for producing catalyst for direct-liquid fuel cell, catalyst produced by the process and uses thereof
In a direct-liquid fuel cell supplied directly with a liquid fuel, a process for producing an electrode catalyst for a direct-liquid fuel cell is provided which is capable of suppressing decrease in cathode potential caused by liquid fuel crossover and providing an inexpensive and high-performance electrode catalyst for a direct-liquid fuel cell. The process for producing an electrode catalyst for a direct-liquid fuel cell includes Step A of mixing at least a transition metal-containing compound with a nitrogen-containing organic compound to obtain a catalyst precursor composition, and Step C of heat-treating the catalyst precursor composition at a temperature of from 500 to 1100° C. to obtain an electrode catalyst, wherein part or entirety of the transition metal-containing compound includes, as a transition metal element, at least one transition metal element M1 selected from Group IV and Group V elements of the periodic table. |
| US09379384B2 |
Method for producing non-graphitizable carbon material, negative electrode material for lithium ion secondary battery, and lithium ion secondary battery
A method for producing a non-graphitizable carbon material includes providing a raw material of a non-graphitizable carbon material. The raw material is cross-linked to obtain a cross-linked product. The cross-linked product is infusibilized to obtain an infusibilized product. The infusibilized product is baked to obtain the non-graphitizable carbon material. A mechanochemical treatment is performed on the cross-linked product or the infusibilized product. |
| US09379383B2 |
Lithium battery and method of preparing the same
A method of preparing a lithium battery according to an embodiment of the present invention may include preparing a mixture including lithium phosphorus sulfide and metal sulfide, preparing an electrode composite by applying a physical pressure to the mixture, wherein the electrode composite includes lithium phosphorus sulfide, lithium metal sulfide, and amorphous sulfide, preparing an electrode active layer by using the electrode composite, forming an electrode current collector on one side of the electrode active layer, and forming an electrolyte layer on another side of the electrode active layer. |
| US09379381B2 |
Mesoporous silicon/carbon composite for use as lithium ion battery anode material and process of preparing the same
A silicon/carbon composite comprises mesoporous silicon particles and carbon coating provided on the silicon particles, wherein the silicon particles have two pore size distribution of 2-4 nm and 20-40 nm. A process of preparing the silicon/carbon composite comprises the steps of preparing mesoporous silicon particles via a mechanochemical reaction between SiCl4 and Li33Si4 under ball milling and subsequent thermal treatment and washing process, and coating the mesoporous silicon particles with carbon. An anode for lithium ion battery comprises the silicon/carbon composite. A lithium ion battery comprises the silicon/carbon composite. |
| US09379378B2 |
Electrode for lead acid storage battery
An electrode for a lead acid battery is provided. The electrode includes a pasting material distributed on the electrode and arranged to provide uniform current density. A lead acid battery having a plurality of electrodes, each electrode having pasting material providing uniform current density across the electrodes is also provided. A method for manufacturing a battery electrode is also provided and includes applying a portion of the electrode with a pasting material providing uniform current density. |
| US09379377B2 |
Cathode for lithium secondary battery and lithium secondary battery comprising the same
Disclosed is a cathode for a lithium secondary battery and a lithium secondary battery comprising the same. The cathode may include a current collector, a first composite layer formed from a mixture of olivine-type lithium iron phosphate cathode active material powder and a binder on the current collector, and a second composite layer formed from a mixture of olivine-type lithium iron phosphate cathode active material powder and a binder on the first composite layer. A specific surface area of the olivine-type lithium iron phosphate cathode active material powder in the second composite layer may be at least 1.2 times larger than that of the olivine-type lithium iron phosphate cathode active material powder in the first composite layer. The cathode for a lithium secondary battery has excellent safety, high energy density, and high output performance. |
| US09379376B2 |
Positive electrode containing lithium nickel composite oxide for non-aqueous electrolyte secondary battery, non-aqueous electrolyte secondary battery using the same, and method for producing the same
A method for producing a positive electrode for non-aqueous electrolyte secondary battery of the present invention includes the steps of: (1) producing a positive electrode precursor by applying a positive electrode slurry including a positive electrode active material comprising a lithium-containing composite oxide including nickel, a binder, and a conductive agent on a positive electrode core material, the positive electrode active material including secondary particles having an average particle diameter of 8 μm or more, and then drying the positive electrode slurry to form a positive electrode material mixture layer; and (2) rolling while heating the positive electrode precursor to produce a positive electrode in which 3.5 g or more of the positive electrode active material is included per 1 cm3 of the positive electrode material mixture layer, and the positive electrode active material includes secondary particles having an average particle diameter of 5 μm or more. |
| US09379372B2 |
Battery and method of manufacturing the same
A battery includes a battery container containing a power generating element, a lid plate covering a top opening of the battery container, and including a baffling portion, whose upper surface includes at least one of a first projecting portion and a first recessed portion, and an external terminal including a base portion and a second projecting portion that projects upward from the base portion. The base portion is engaged with the baffling portion of the lid plate. |
| US09379371B2 |
Secondary battery
A secondary battery including: an electrode assembly including a plurality of first and second electrode plates, and a plurality of separators between the first and second electrode plates; a first electrode tab on the first electrode plate, and a second electrode tab on the second electrode plate; a case housing the electrode assembly, and the first and second electrode tabs; and first and second external lead terminals at an outer side of the case and electrically coupled to the first and second electrode tabs, respectively. |
| US09379368B2 |
Electrochemical systems with electronically conductive layers
Provided are electrochemical systems with electronically and ionically conductive layers that have electronic, mechanical and chemical properties useful for a variety of applications including electrochemical storage and conversion. State of the art electrochemical cells are made with electronically non-conductive separators between the opposite electrodes as the natural choice to prevent any electronic path between the opposite electrodes. Herein, electronically conductive layers are introduced between an electrode and the separator without producing any direct electronic path between the opposite electrodes. Embodiments provide structural, physical and electrostatic attributes useful for managing and controlling dendrite formation and for improving the cycle life and rate capability of electrochemical cells including silicon anode based batteries, air cathode based batteries, redox flow batteries, solid electrolyte based systems, fuel cells, flow batteries and semisolid batteries. Disclosed electronically and ionically conductive layers include multilayer, porous geometries supporting excellent ion transport properties, providing a barrier to prevent dendrite initiated mechanical failure, shorting or thermal runaway, or providing improved electrode conductivity and improved electric field uniformity. Disclosed electronically and ionically conductive layers between the separator and an electrode include metals, metal alloys, a carbon materials, semiconductors, electronically conductive polymers, electronically conductive ceramics and any combination of these. |
| US09379366B2 |
Battery module
A battery module includes a plurality of battery cells arranged in a first direction; first and second end plates, the first and second end plates being located along the first direction at opposite ends of the plurality of battery cells; and at least one support plate coupling the first and second end plates to each other, the first end plate including at least one first fastening portion, the second end plate including at least one second fastening portion, and the support plate including a third fastening portion and a fourth fastening portion, the first and second fastening portions being coupled at an inner surface of the third and fourth fastening portions, respectively. |
| US09379365B2 |
Cell frame for EREV GEN2 battery module (liquid fin concept) with heat exchanger (HEX) insertion features
A support frame assembly for holding a plurality of battery cells includes a first end frame having a first plurality of protruding strips, a second end frame having a second plurality of protruding strips, and a structural frame having a plurality of grooves for receiving the first plurality of protruding strips and the second plurality of protruding strips. The first end frame and the second end frame attach to the structural frame to hold a first battery cell, a second battery cell and a foam pad positioned between the first battery cell and the second battery cell. The structural frame has curved features therein for receiving a cooling assembly and a chamfered slot for receiving a cooling fin from the cooling assembly. The support frame assembly also includes interlocking features that mate to another support frame with a gap defined between adjacent support frames. |
| US09379360B2 |
Organic light emitting display apparatus including lower and upper auxiliary electrodes
An organic light emitting display apparatus includes a plurality of first electrodes disposed in each of a plurality of pixels on a substrate, a plurality of lower auxiliary electrodes insulated from the first electrodes and in which the lower auxiliary electrodes are disposed in a first direction, an organic layer disposed on the first electrodes, and a second electrode facing the first electrodes and covering the organic layer. The second electrode is disposed on substantially an entire surface of the substrate. The organic light emitting display apparatus further includes a plurality of upper auxiliary electrodes disposed on the second electrode in a second direction. |
| US09379356B2 |
Sealed thin-film device as well as method of repairing, system for repairing and computer program product
The invention relates to a sealed thin-film device, to a method of repairing a sealing layer applied to a thin-film device to produce the sealed thin-film device, to a system for repairing the sealing layer applied to the thin-film device to generate the sealed thin-film device and to a computer program product. The sealed thin-film device comprises a thin-film device and a sealing layer applied on the thin-film device for protecting the thin-film device from environmental influence. The sealing layer comprises at least a first and a second barrier layer and a getter layer arranged between the first and the second barrier layer. The sealed thin-film device further comprises locally applied mending material for sealing a local breach in an outer one of said barrier layers. |
| US09379355B1 |
Flexible display device having support layer with rounded edge
There is provided a flexible display having a plurality of innovations configured to allow bending of a portion or portions to reduce apparent border size and/or utilize the side surface of an assembled flexible display. |
| US09379352B2 |
OLED encapsulating structure and manufacturing method thereof, and light-emitting device
An OLED encapsulating structure and a manufacturing method thereof, and a light-emitting device are disclosed. The OLED encapsulating structure comprises: a base substrate, an OLED, barrier layers, and optical modulation layers; the OLED is formed on the base substrate; the barrier layers and the optical modulation layers are alternately and periodically formed on the OLED. The OLED encapsulating structure can reduce viewing-angle dependence of an OLED caused by a micro-cavity effect. |
| US09379351B2 |
Display element and method for producing the same
Disclosed are a production process of a display device, which can prevent the oxidation of a lower electrode and can maintain luminescence efficiency, high contract, and durability, and a display element. The display element comprises a first electrode, a luminescent layer, a second electrode, and a transparent substrate. The first electrode comprises a metal layer and a corrosion-resistant charge injection accelerating layer. The corrosion-resistant charge injection accelerating layer has been formed by subjecting a surface layer in the metal layer to plasma treatment using an oxygen atom-containing gas. |
| US09379344B2 |
Display panel and display device
The invention belongs to the field of display technology, and particularly to a display panel and a display device. The display panel includes a driving substrate and an OLED provided on the driving substrate, the OLED includes a first electrode and a second electrode, and further includes an electron transporting layer, a light-emitting layer and a hole transporting layer provided between the first electrode and the second electrode, and a plurality of color conversion units are uniformly distributed in the electron transporting layer, the light-emitting layer or the hole transporting layer. Advantageous effects of the invention are as follows: with the configuration that the color conversion units are directly doped into any one of the hole transporting layer, the light-emitting layer, and the electron transporting layer, structure of display panel and corresponding manufacturing procedure are simplified, and color purity of the display panel and carrier mobility are efficiently increased. |
| US09379343B2 |
Light transmissive electrode, organic photoelectric device, and image sensor
According to example embodiments, a transmissive electrode may include a light transmission layer. The light transmission layer may include a metal and a metal oxide that is included in a smaller amount than the metal. According to example embodiments, an organic photoelectric device, as well as an image sensor, may include the transmissive electrode. |
| US09379342B1 |
Semi-conductor device with programmable response
An apparatus with a programmable response includes a semiconductor device with a junction formed thereon, the junction having a built-in potential, a quantum well element proximate to the junction that provides an energy well within a depletion region of the junction. The energy well comprises one or more donor energy states that support electron trapping, and/or one or more acceptor energy states that support hole trapping; thereby modulating the built-in potential of the junction. The semiconductor device may be a diode, a bipolar diode, a transistor, or the like. A corresponding method is also disclosed herein. |
| US09379338B1 |
Organic electroluminescence device
A compound is represented by the following formula (I): wherein N represents a nitrogen atom; C represents a carbon atom; Pt represents a platinum atom; Z1, Z4, Z5, and Z8 represent a carbon atom or a nitrogen atom; Z2, Z3, Z6, and Z7 represent a carbon atom, a nitrogen atom, an oxygen atom or a sulfur atom; Z11 and Z16 represent a carbon atom or a nitrogen atom; Z12, Z13, Z14, Z15, Z17, Z18, Z19, and Z20 represent a carbon atom, a nitrogen atom, an oxygen atom, or a sulfur atom; Y1 and Y2 represent a single bond, an oxygen atom, a sulfur atom, a nitrogen atom; A11 represents a divalent linking group; B1 and B2 represent a single bond or a divalent linking group. |
| US09379334B2 |
Organic light-emitting device
Provided is an organic light-emitting device with a blue emission layer. The blue emission layer is an emission layer that emits blue light by a fluorescent emission mechanism. The blue emission layer includes a compound represented by Formula 4 below: |
| US09379330B2 |
Materials for electronic devices
The present invention relates to an electronic device comprising anode, cathode and at least one organic layer which comprises a compound of the formula (I) to (IV). The invention furthermore encompasses the use of compounds of the formula (I) to (IV) in an electronic device and to a compound of the formula (Ic) to (IVc). |
| US09379329B2 |
Low band-gap organic semiconductor compounds, and transistors and electronic devices including the same
An organic semiconductor compound including a structural unit represented by Chemical Formula 1. |
| US09379328B1 |
Thin-film electro devices based on derivatized poly (benzo-isimidazobenzophenanthroline) ladder polymers
A method for making electronic devices based on derivatized ladder polymer poly(benzo-isimidazobenzophenanthroline) (BBL) including photovoltaic modules and simple thin film transistors in planar and mechanically flexible and stretchable constructs. |
| US09379326B2 |
Selective etching of a matrix comprising silver nano wires
The present invention refers to a method for selectively structuring of a polymer matrix comprising AgNW (silver nano wires) or CNTs (carbon nano tubes) or comprising mixtures of AgNW and CNTs on a flexible plastic substructure or solid glass sheet. The method also includes a suitable etching composition, which allows to proceed the method in a mass production. |
| US09379325B2 |
Donor mask and method of manufacturing organic light emitting display apparatus using the same
A donor mask includes a base substrate, a light-to-heat conversion layer disposed on the base substrate and including a first upper surface portion and a second upper surface portion, and a reflection layer interposed between the base substrate and the light-to-heat conversion layer and including through holes corresponding to the first upper surface portion and the second upper surface portion. The first upper surface portion includes a first upper surface and a second upper surface connected to the first upper surface and inclined at an angle other than 90 degrees with respect to the first upper surface. |
| US09379321B1 |
Chalcogenide glass composition and chalcogenide switch devices
Embodiments of the present disclosure describe chalcogenide glass compositions and chalcogenide switch devices (CSD.) The compositions generally may include 3% to 15%, silicon, 8% to 16% germanium in, greater than 45% selenium, and 20% to 35% arsenic, by weight. The amount of silicon and germanium in a composition generally may include more than 10% by weight. CSDs may include various compositions of chalcogenide glass, and a plurality of them may be used in a memory device, such as die with a memory component, and may be used in various electronic components and systems. Other embodiments may be described and/or claimed. |
| US09379319B2 |
Nonvolatile memory transistor and device including the same
Provided are nonvolatile memory transistors and devices including the nonvolatile memory transistors. A nonvolatile memory transistor may include a channel element, a gate electrode corresponding to the channel element, a gate insulation layer between the channel element and the gate electrode, an ionic species moving layer between the gate insulation layer and the gate electrode, and a source and a drain separated from each other with respect to the channel element. A motion of an ionic species at the ionic species moving layer occurs according to a voltage applied to the gate electrode. A threshold voltage changes according to the motion of the ionic species. The nonvolatile memory transistor has a multi-level characteristic. |
| US09379318B2 |
Method for forming a magnetic sensor
A method for forming a magnetic sensor includes: forming a hard mask film on a tantalum nitride film; forming a patterned photoresist layer on the hard mask film; implementing an isotropic dry etching process to the hard mask film by taking the photoresist layer as a mask, so as to form a hard mask layer; and implementing an etching process to the tantalum nitride film and the magnetic film by taking the hard mask layer as a mask, so as to form a tantalum nitride layer and a magnetic resistive layer. As an isotropic dry etching process is implemented to the hard mask film, the hard mask film located which is above the other sidewalls and is not used for forming the magnetic sensor can be effectively removed. In addition, shadow effect will not take place, thus dimension of the magnetic sensor formed is able to be easily controlled. |
| US09379317B2 |
Spin-polarised current source
Method of filtering electrons to obtain spin-polarization of a current conducting at least 75% of electrons at the Fermi level, used with a spin-polarized current source comprising: a polarized spin injection device comprising an electrically conducting substrate of which a first face has magnetic properties and an organic layer in contact with the first face of the substrate; an electrically conducting material called the ground, the organic layer being arranged between the ground and the substrate; a current source electrically connected to the first face of the substrate and the ground; the method comprising circulation of the electron conduction current by means of the current source, between the first face of the substrate and the ground, at a temperature higher than −220° C. |
| US09379304B2 |
Internal electrode for piezoelectric device, piezoelectric device including the same, and method for manufacturing piezoelectric device
There is provided a piezoelectric device, including: a multilayered body in which a piezoelectric layer having a first internal electrode formed thereon and a piezoelectric layer having a second internal electrode formed thereon are alternately formed; a first insulating via formed in the first internal electrode layer; a second insulating via formed in the second internal electrode layer; a first conductive via formed in the multilayered body and penetrating through the first insulating via; and a second conductive via formed in the multilayered body and penetrating through the second insulating via, wherein a diameter of the first insulating via is larger than a diameter of the first conductive via, and a diameter of the second insulating via is larger than a diameter of the second conductive via. |
| US09379302B2 |
Method of manufacturing the thermal fluid flow sensor
In a thermal sensor with a detection part and a circuit part formed on the same substrate, an insulating film for protection of the circuit part causes problems of lowering in sensitivity of a heater, deterioration in accuracy due to variation of a residual stress in the detection part, etc. A layered film including insulating films is formed on a heating resistor, an intermediate layer is formed thereon, and a layered film including insulating films is formed further thereon. The intermediate layer is specified to be a layer made up of any one of aluminum nitride, aluminum oxide, silicon carbide, titanium nitride, tungsten nitride, and titanium tungsten. This configuration enables the layered film on the upper part of the detection part to be removed using the intermediate layer as an etch stop layer, which solves problems of lowering in sensitivity, a variation in residual stress, etc. resulting from these. |
| US09379300B2 |
Floating heat sink support with copper sheets and LED package assembly for LED flip chip package
A floating heat sink support with copper sheets for a LED flip chip package may include at least two copper sheets and a flexible polymer for fixing the copper sheets, where the copper sheets separated from each other, and where each of the copper sheets is electrically connected with a positive or negative pole of a LED flip chip. Further, a LED package assembly may comprise the floating heat sink support mentioned above and one or more LED chips welded in a flip chip manner on the floating heat sink support. A number of copper sheets in the floating heat sink support are heated separately and expand separately to avoid breakage of a chip substrate resulting from the thermal expansion of a whole bulk of copper sheet, thereby improving the reliability of the LED package structure and prolonging the service life of a LED light source. |
| US09379298B2 |
Laminate sub-mounts for LED surface mount package
An LED package is described that acts as a sub-mount between a printed circuit board and an LED. The sub-mount includes a laminate to thermally isolate the LED from the PCB while providing a thermal heat dissipative sink for the LED. |
| US09379295B2 |
Method for manufacturing LED module, and LED module
A method for manufacturing an LED module is provided that includes the steps of mounting an LED chip 2 on an obverse surface of leads 1A′, 1B′, and after the step of mounting the LED chip 2, providing a case 6 that covers part of the leads 1A′, 1B′ and includes a reflective surface 61 surrounding the LED chip 2 in an in-plane direction of the leads 1A′, 1B′. With this arrangement, there is no risk that the arm for handling the LED chip 2 interferes with the case 6. This allows the distance between the reflective surface 61 and the LED chip 2 to be reduced, and hence allows making the LED module more compact. |
| US09379294B2 |
Semiconductor light emitting device
A light emitting device includes a substrate, a light emitting element mounted on the substrate, a light transmissive member placed on an upper surface of the light emitting element, and a sealing member which seals the light emitting element and the light transmissive member. The light transmissive member is a plate-shaped member not containing a phosphor and is larger than the light emitting element when viewed from above. The sealing member includes a first sealing member which is formed of a light reflecting member for reflecting light emitted from the light emitting element and covers side surfaces of the light emitting element, and a second sealing member which contains a phosphor for converting the light emitted from the light emitting element into light having wavelength different from wavelength of the light emitted from the light emitting element and covers at least an upper surface of the light transmissive member. |
| US09379290B2 |
LED module
A LED module includes a substrate, a LED chip supported on the substrate, a metal wiring installed on the substrate, the metal wiring including a mounting portion on which the LED chip is mounted, an encapsulating resin configured to cover the LED chip and the metal wiring, and a clad member configured to cover the metal wiring to expose the mounting portion, the encapsulating resin arranged to cover the clad member. |
| US09379283B2 |
Method of manufacturing nanostructure semiconductor light emitting device by forming nanocores into openings
A method of manufacturing a nanostructure semiconductor light emitting device including providing a base layer formed of a first conductivity type semiconductor. A mask including an etch stop layer is formed on the base layer. A plurality of openings are formed in the mask so as to expose regions of. A plurality of nanocores are formed by growing the first conductivity type semiconductor on the exposed regions of the base layer to fill the plurality of openings. The mask is partially removed by using the etch stop layer to expose side portions of the plurality of nanocores. An active layer and a second conductivity type semiconductor layer are sequentially grown on surfaces of the plurality of nanocores. |
| US09379281B2 |
Fabrication of thin, flexible, and efficient light emitting diodes
A light emitting structure may include a light emitting element(s) arranged in a transparent dielectric material. The light emitting element(s) may include a semiconductor nanostructure arranged in a display orientation different from a growth orientation of the semiconductor nanostructure. The light emitting element(s) may also include a well layer on the semiconductor nanostructure. The light emitting element(s) may further include a capping layer on the well layer. The light emitting structure may also include a contact layer coupled to the light emitting element(s). |
| US09379276B2 |
Optical interconnection module and optical-electrical hybrid board
There are provided an optical interconnection module and an optical-electrical hybrid board using the same to process optical and electric signals on a board at a low transmission loss at high speed in transmitting high-speed optical signals sent and received between chips or between boards in a data processing apparatus. An optical interconnection module has a structure in which an optical signal is emitted from a laser optical source device, propagates the inside of a modulator device, and is deflected by a beam turning structure in the vertical direction of a substrate, an optical signal is incident from the outside of a semiconductor substrate, and transmitted and received at a photo diode provided on the semiconductor substrate, and the optical signals are optically connected to each other through the inside of the semiconductor substrate in the vertical direction of the substrate with the outside of the semiconductor substrate. |
| US09379275B2 |
Apparatus and method for reducing dark current in image sensors
A method for reducing dark current in image sensors comprises providing a backside illuminated image sensor wafer, depositing a first passivation layer on a backside of the backside illuminated image sensor wafer, depositing a plasma enhanced passivation layer on the first passivation layer and depositing a second passivation layer on the plasma enhanced passivation layer. |
| US09379272B2 |
Light receiving element and optically coupled insulating device
A light receiving element includes: a semiconductor layer; an insulating layer; an interconnect layer; and a film. The semiconductor layer includes a light receiving unit configured to convert a signal light incident on the light receiving unit into an electrical signal. The insulating layer is provided on the semiconductor layer. The interconnect layer is provided on the insulating layer. The film is provided on the insulating layer to cover the light receiving unit and be connected to the interconnect layer, the film being made of a metal or a metal nitride. |
| US09379269B2 |
Bifacial crystalline silicon solar panel with reflector
Bifacial crystalline solar cells and associated solar panel systems are provided. The cells include a p-type crystalline silicon layer and a barrier layer. The panels include at least two rows of cells. The cells in each row are connected to one another in series. The rows are connected in parallel. A reflector is used to reflect light towards the underside of the panel. A long axis of the reflector is arranged to be parallel to the rows of cells. |
| US09379267B2 |
Solar cell module
A solar cell module including two or more adjacent solar cells (1a, 1b), a connection member (2) for electrically connecting the solar cells (1a, 1b) to each other, and a solder layer (5) disposed between the solar cells (1) and the connection member (2), wherein first and second opening holes (4a, 4b) are formed at a connection portion of the connection member (2) corresponding to the first and the second solar cells (1a, 1b), the first and the second opening holes (4a, 4b) are configured that solder is deposited into them, and first and second protruding parts (3a, 3b) are formed at a part of the outer periphery of each of the first and second opening holes (4a, 4b) of the connection member (2). By the present invention, it is possible to ensure sufficient thickness of the solder joining layer and to improve reliability for long-term use. |
| US09379264B2 |
Multilayered film and photovoltaic module including the same
A multilayered film, a back sheet for a photovoltaic cell, methods of manufacturing the film and cell, and a photovoltaic module including the film and cell are provided. The multilayered film includes a resin layer formed on a substrate, and the resin layer contains a fluorine-based polymer and a reactive functional group having an equivalent weight of 30,000 or less. The resin layer containing the fluorine-based polymer has good durability and weatherability and is highly adhesive to the substrate at an interface between the resin layer and the substrate. Also, since a drying process may be performed at a low temperature during manufacture of the multilayered film, manufacturing costs may be reduced, productivity may be increased, and degradation in the quality of products due to thermal deformation or thermal shock may be prevented. The multilayered film may be effectively used as, for example, a back sheet for various photovoltaic modules. |
| US09379262B2 |
Wafer with high rupture resistance
A wafer with high rupture resistance includes a plurality of surfaces, wherein the surfaces include a largest surface having a largest area than others and a side surface connected to the fringe of the largest surface. The side surface forms a nanostructured layer thereon to assist the stress dispersion of the wafer. Accordingly, the wafer is provided with a high rupture resistance so as to prevent the wafer from damages during semiconductor or other processes. |
| US09379261B2 |
Ultra thin film nanostructured solar cell
Improved solar cells are provided by nano-structuring the solar cell active region to provide high optical absorption in a thin structure, thereby simultaneously providing high optical absorption and high carrier collection efficiency. Double-sided nano-structuring is considered, where both surfaces of the active region are nano-structured. In cases where the active region is disposed on a substrate, nano-voids are present between the substrate and the active region, as opposed to the active region being conformally disposed on the substrate. The presence of such nano-voids advantageously increases both optical and electrical confinement in the active region. |
| US09379260B2 |
Solar cell and method of fabricating the same
Provided is a solar cell including a first electrode, a first semiconductor layer on the first electrode, a second semiconductor layer on the first semiconductor layer, and a second electrode on the second semiconductor layer. The second semiconductor layer may include a nano wire that may be formed along a grain boundary of a top surface thereof to have a mesh-shaped structure. |
| US09379258B2 |
Fabrication methods for monolithically isled back contact back junction solar cells
Fabrication methods for making back contact back junction solar cells. A base dopant source, a field emitter dopant source, and an emitter dopant source are deposited on the back surface of a solar cell substrate. The solar cell substrate is annealed forming emitter contact regions corresponding to the emitter dopant source, field emitter regions corresponding to the field emitter dopant, and base contact regions corresponding to the base dopant source. The base dopant source, field emitter dopant source, and the emitter dopant source are etched. A backside passivation layer is deposited on the back surface of the solar cell. Contacts are opened to the emitter contact regions and the base contact regions through the backside passivation layer. Patterned base metallization and patterned emitter metallization is formed on the back surface of the solar cell with electrical interconnections to the base contact regions and the emitter contact regions. |
| US09379256B2 |
Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device includes a charge storage layer on a first insulating film, a second insulating film which is provided on the charge storage layer, formed of layers, and a control gate electrode on the second insulating film. The second insulating film includes a bottom layer (A) provided just above the charge storage layer, a top layer (C) provided just below the control gate electrode, and a middle layer (B) provided between the bottom layer (A) and the top layer (C). The middle layer (B) has higher barrier height and lower dielectric constant than both the bottom layer (A) and the top layer (C). The average coordination number of the middle layer (B) is smaller than both the average coordination number of the top layer (C) and the average coordination number of the bottom layer (A). |
| US09379251B1 |
Self-aligned metal oxide thin film transistor and method of making same
A method for forming a TFT includes providing a substrate, a gate electrode on the substrate, an electrically insulating layer on the substrate to totally cover the gate electrode, a channel layer on the electrically insulating layer, a first photoresist pattern on the channel layer, a metal layer on the electrically insulating layer, the channel layer and the first photoresist layer, and a second photoresist pattern on the metal layer. A middle portion of the metal layer is then removed to form a source electrode and a drain electrode and to expose the first photoresist pattern and a portion of the channel layer between the first and second photoresist patterns. The exposed portion of the channel layer is then processed to have its electrical conductivity be lowered to thereby reduce a hot-carrier effect of the channel layer. |
| US09379249B2 |
Thin-film transistor, method for manufacturing the same and display device comprising the same
A thin-film transistor includes a substrate, a first gate electrode formed on the substrate, a first active layer that is formed on the substrate and includes a first oxide semiconductor layer and a first barrier layer, a second active layer that is formed on the first active layer and includes a second oxide semiconductor layer and an intermediate barrier layer, a gate insulating layer that is formed on the second active layer, a second gate electrode that is formed on the gate insulating layer and is electrically connected to the first gate electrode, an interlayer insulating film formed on the second gate electrode, the first active layer and the second active layer, and a source electrode and a drain electrode electrically connected to the first active layer and the second active layer. |
| US09379241B2 |
Semiconductor device with strained channels
In various method embodiments, a device region in a semiconductor substrate and isolation regions adjacent to the device region are defined. The device region has a channel region and the isolation regions have strain-inducing regions laterally adjacent to the channel regions. The channel region is strained with a desired strain for carrier mobility enhancement, where at least one ion type is implanted with an energy resulting in a peak implant in the strain-inducing regions of the isolation regions. Other aspects and embodiments are provided herein. |
| US09379236B2 |
LDMOS device and structure for bulk FinFET technology
A lateral double-diffused MOS (LDMOS) bulk finFET device for high-voltage operation includes a first-well region and two or more second-well regions formed on a substrate material and one or more non-well regions including substrate material. The non-well regions are configured to separate well regions of the second-well regions. A source structure is disposed on a first fin that is partially formed on the first-well region. A drain structure is disposed on a second fin that is formed on a last one of the second-well regions. One or more dummy regions are formed on the one or more non-well regions. The dummy regions are configured to provide additional depletion region flow paths including vertical flow paths for charge carriers to enable the high-voltage operation. |
| US09379233B2 |
Semiconductor device
A semiconductor device 100 includes a plurality of vertical transistors 50 provided to stand from a silicon substrate 1 and having a pillar lower diffusion layer 9 at their end portions on the silicon substrate 1 side, a metal contact plug 31 provided to stand from the silicon substrate 1 and connected to the pillar lower diffusion layer 9 of the plurality of vertical transistors 50, the plurality of vertical transistors 50 are uniformly arranged around the metal contact plug 31 and share the pillar lower diffusion layer 9 and the metal contact plug 31. |
| US09379231B2 |
Transistor having increased breakdown voltage
A transistor includes a source finger electrode having a source finger electrode beginning and a source finger electrode end. The transistor also includes a drain finger electrode with a curved drain finger electrode end having an increased radius of curvature. The resulting decreased electric field at the curved drain finger electrode end allows for an increased breakdown voltage and a more robust and reliable transistor. |
| US09379229B2 |
Semiconductor apparatus including protective film on gate electrode and method for manufacturing the semiconductor apparatus
A semiconductor apparatus includes a substrate, a semiconductor layer formed above the substrate and including a nitride semiconductor, an electrode formed above the semiconductor layer and including gold, a barrier film formed above the electrode and a protection film formed above the semiconductor layer and including one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The protection film is formed on the barrier film. The barrier film includes a metal oxide material, a metal nitride film, or a metal oxynitride film. |
| US09379228B2 |
Heterojunction field effect transistor (HFET) variable gain amplifier having variable transconductance
A heterojunction semiconductor field effect transistor HFET having a pair of layers of different semiconductor materials forming a quantum well within the structure to support the 2DEG. Source, drain and gate electrodes are disposed above the channel. The HFET has a predetermined transconductance. A transconductance control electrode varies an electric field within the structure under the channel to vary the shape of the quantum well and thereby the transconductance of the FET in accordance with a variable control signal fed to the transconductance control electrode. |
| US09379227B2 |
High-electron-mobility transistor
A high-electron-mobility transistor (HEMT) device includes a plurality of semiconductor layers formed on a substrate, wherein a two-dimensional electron gas (2DEG) layer is formed in the semiconductor layers; an etch-stop layer formed on the plurality of semiconductor layers; a p-type semiconductor layer pattern formed on the etch-stop layer; and a gate electrode formed on the p-type semiconductor layer pattern. |
| US09379221B1 |
Bottom-up metal gate formation on replacement metal gate finFET devices
A method of fabricating a replacement metal gate in a transistor device, a fin field effect transistor (finFET), and method of fabricating a finFET device with the replacement metal gate are described. The method of fabricating the replacement metal gate includes forming a dummy gate structure over a substrate, the dummy gate structure being surrounded by an insulating layer, and removing the dummy gate structure so as to expose a trench within the insulating layer. The method also includes conformally depositing a dielectric material layer and a work function metal layer over a the insulating layer and in the trench and removing the dielectric material layer and the work function metal layer from a tip surface of the insulating layer, recessing the work function metal layer below a top of the trench, and selectively forming a gate metal only on exposed surfaces of the work function metal layer. |
| US09379220B2 |
FinFET device structure and methods of making same
Embodiments of the present disclosure are a method of forming a semiconductor device and a method of forming a FinFET device. An embodiment is a method of forming a semiconductor device, the method including forming a first dielectric layer over a substrate, forming a first hardmask layer on the first dielectric layer, and patterning the first hardmask layer to form a first hardmask portion with a first width. The method further includes forming a second dielectric layer on the first dielectric layer and the first hardmask portion, forming a third dielectric layer on the second dielectric layer, and etching the third dielectric layer and a portion of the second dielectric layer to form a first and second spacer on opposite sides of the first hardmask portion. |
| US09379219B1 |
SiGe finFET with improved junction doping control
A semiconductor device and a method for fabricating the device. The method includes: providing a FinFET having a source/drain region, at least one SiGe fin, a silicon substrate, a local oxide layer is formed on the silicon substrate, a gate structure is formed on the at least one SiGe fin and the local oxide layer, the gate structure is encapsulated by a gate hard mask and sidewall spacer layers; recessing the at least one SiGe fin in the source/drain region to the sidewall spacer layers and the silicon substrate layer; recessing the local oxide layer in the source/drain region to the sidewall spacer layer and the silicon substrate; growing a n-doped silicon layer on the silicon substrate; growing a p-doped silicon layer or p-doped SiGe layer on the n-doped silicon layer; and forming a silicide layer on the p-doped silicon layer or p-doped SiGe layer. |
| US09379216B2 |
Semiconductor device and method for manufacturing same
According to an embodiment, a method for manufacturing a semiconductor device includes forming a gate trench extending into a first semiconductor layer; forming a gate insulating film on an internal wall of the gate trench; forming a polysilicon in the gate trench; etching the polysilicon into the gate trench; forming an interlayer insulating film on the polysilicon; etching the first semiconductor layer so as to project the interlayer insulating film from the first semiconductor layer; forming a second semiconductor layer on the first semiconductor layer; forming a third semiconductor layer on the second semiconductor layer; forming a sidewall contacting a side face of the interlayer insulating film; forming a fourth semiconductor layer of the second conductivity type in the second semiconductor layer; and forming a first electrode electrically connected to the third semiconductor layer and the fourth semiconductor layer. |
| US09379214B2 |
Reduced variation MOSFET using a drain-extension-last process
A MOSFET structure and method of manufacture that minimize threshold variations associated with statistical uncertainties of implanted source and drain extensions. The source and drain extensions are fabricated very late in the process using a material added to etched recesses immediately adjacent to the transistor's channel. In various embodiments, the added material may be germanium grown by selective epitaxy, doped silicon grown by selective epitaxy, or metallic materials created by deposition or by deposition and reaction. |
| US09379206B2 |
Semiconductor device and fabrication method thereof
A semiconductor device fabrication method is provided in which recesses are formed at source/drain positions in the substrate, removable sidewalls are formed on side walls of the recess, and the recesses then are etched to form Sigma shaped recesses. Selective epitaxial growth of substantially un-doped SiGe in the Sigma shaped recesses is performed, and the Sigma shaped recesses close to the surface of the substrate can be protected from epitaxial growth by the removable sidewalls. Epitaxial growth of SiGe doped with a P-type impurity can be performed in the Sigma shaped recesses after removing the sidewalls. |
| US09379204B2 |
Lattice matched aspect ratio trapping to reduce defects in III-V layer directly grown on silicon
A structure having application to electronic devices includes a III-V layer having high crystal quality and a low defect density on a lattice mismatched substrate. Trenches are formed in a layer of III-V semiconductor material grown on a substrate having a different lattice constant. Dielectric material is deposited within the trenches, forming dielectric regions. A portion of the layer of III-V material is removed, leaving new trenches defined by the dielectric regions. A new layer of III-V semiconductor material having reduced defect density is grown on the remaining portion of the originally deposited III-V semiconductor layer and within the trenches defined by the dielectric regions. |
| US09379201B2 |
Electrostatic discharge diodes and methods of forming electrostatic discharge diodes
A method includes thinning a back-side of a substrate to expose a portion of a first via that is formed in the substrate. The method also includes forming a first diode at the back-side of the substrate. The first diode is coupled to the first via. |
| US09379199B2 |
Semiconductor device including a contact plug with barrier materials
Disclosed herein is a semiconductor device that comprises a plug including an upper portion, a lower portion and a side surface and comprising tungsten, a barrier metal comprising tungsten nitride and covering the side surface and the lower portion of the contact plug, a conductive layer, and a barrier layer comprising titanium and intervening between the barrier metal and the first conductive layer. |
| US09379197B1 |
Recess array device
A recess array device includes a semiconductor substrate and at least an active area in a main surface of the semiconductor substrate. A gate trench penetrates through the active area. The gate trench includes a first sidewall, a second sidewall facing the first sidewall, and a bottom surface extending between the first and the second sidewalls. A bump portion is disposed in the gate trench. The bump portion has two opposite sidewalls and a top portion extending between the two opposite sidewalls. A gate oxide layer is formed in the gate trench. The gate oxide layer has a first thickness on the first and second sidewalls, a second thickness on the two opposite sidewalls of the bump portion, and a third thickness on the top portion of the bump portion. The first thickness is greater than the second thickness. The second thickness is greater than the third thickness. |
| US09379193B2 |
Semiconductor package for a lateral device and related methods
A semiconductor package. Implementations may include a lateral device that may include a lateral semiconductor device including one of interspersed and interdigitated source and drain regions and one or more gate regions, a single layer clip, and a leadframe. The single layer clip may be coupled to the one of interspersed and interdigitated source and drain regions and the one or more gate regions and to the leadframe. The single layer clip may be configured to redistribute and to isolate source, drain, and gate signals passing into and out from the lateral semiconductor device during operation of the semiconductor device package. |
| US09379190B2 |
Crystalline multilayer structure and semiconductor device
Provided is a crystalline multilayer structure which has good electrical properties and is useful for semiconductor devices. A crystalline multilayer structure includes a base substrate and a crystalline oxide semiconductor thin film disposed directly on the base substrate or with another layer therebetween and including a corundum-structured oxide semiconductor as a major component. The oxide semiconductor contains indium and/or gallium as a major component. The crystalline oxide semiconductor thin film contains germanium, silicon, titanium, zirconium, vanadium, or niobium. |
| US09379187B2 |
Vertically-conducting trench MOSFET
A semiconductor device and a fabricating method thereof are provided. The semiconductor device include: a trench disposed within a substrate, the trench comprising an upper trench part that is wider than a lower trench part in width; a gate disposed in the trench; an interlayer insulating layer pattern disposed above the gate in the trench; a source region disposed within the substrate and contacting a sidewall of the upper trench part; a body region disposed below the source region in the substrate; and a contact trench disposed above the body to region and filled with a conductive material. |
| US09379185B2 |
Method of forming channel region dopant control in fin field effect transistor
A dummy gate structure straddling at least one semiconductor fin is formed on a substrate. Active semiconductor regions and raised active semiconductor regions may be formed. A planarization dielectric layer is formed over the at least one semiconductor fin, and the dummy gate structure is removed to provide a gate cavity. Electrical dopants in the channel region can be removed by outgassing during an anneal, thereby lowering the concentration of the electrical dopants in the channel region. Alternately or additionally, carbon can be implanted into the channel region to deactivate remaining electrical dopants in the channel region. The threshold voltage of the field effect transistor can be effectively controlled by the reduction of active electrical dopants in the channel region. A replacement gate electrode can be subsequently formed in the gate cavity. |
| US09379184B1 |
Secure chip with physically unclonable function
A first trench having a first aspect ratio and a second trench having a second aspect ratio that is greater than the first trench are provided into a material stack of a semiconductor substrate and a dielectric material. An epitaxial semiconductor material having a different lattice constant than the substrate is then grown within each of the first and second trenches. The semiconductor material which is epitaxially formed in the first trench has an upper semiconductor material portion that is entirely defect free, while the semiconductor material which is epitaxially formed in the second trench has defects that randomly propagate to the topmost surface of the semiconductor material. At least one semiconductor device is then formed on each epitaxially grown semiconductor material. The at least one semiconductor device located on the epitaxially grown semiconductor material formed in the second trench is a physical unclonable function device. |
| US09379182B1 |
Method for forming nanowire and semiconductor device formed with the nanowire
A method for forming germanium nanowires comprises forming a semiconductor fin structure including alternating fin and shallow trench structures, etching a top portion of the fin to form a fin recess and depositing a germanium-based semiconductor into the fin recess as a germanium-based plug. The method comprises etching the shallow trench structure to expose the germanium-based semiconductor side faces. The exposed germanium-based semiconductor undergoes annealing to form high carrier mobility nanowire structures. The nanowire structures can also be formed of different diameters by selective oxidation of some of the deposited germanium-based plugs. Alternately, forming fin structures of different widths results in deposited germanium plugs of different widths to be deposited to form different thicknesses of nanowires. |
| US09379181B2 |
Semiconductor device
A semiconductor device is provided with a semiconductor substrate in which a power semiconductor element part and a temperature sensing diode part are provided. The temperature sensing diode part includes a first semiconductor region, a second semiconductor region, a first base region, and a first drift region. In the semiconductor substrate, an isolation trench is formed, which passes through the first base region, extends to the first drift region, and surrounds an outer periphery of the temperature sensing diode part. At least a part of one of side walls of the isolation trench is in contact with the power semiconductor element part, and the other side wall of the isolation trench is in contact with the temperature sensing diode part. |
| US09379180B2 |
Super junction for semiconductor device and method for manufacturing the same
A super junction for semiconductor device includes a silicon substrate with a first conductive type epitaxial layer, a plurality of highly-doped second conductive type columns formed in the first conductive type epitaxial layer, and a plurality of lightly-doped (first conductive type or second conductive type) side walls formed on outer surfaces of the highly-doped second conductive type. The semiconductor device is super-junction MOSFET, super junction MOSFET, super junction Schottky rectifier, super junction IGBT, thyristor or super junction diode. |
| US09379178B2 |
Manufacturing method of semiconductor device comprising a capacitor element
A method for manufacturing a semiconductor device includes a capacitor element in which a capacitance dielectric film is provided between an upper electrode film and a lower electrode film, includes forming the lower electrode film over the semiconductor substrate, forming the capacitance dielectric film over the lower electrode film, and forming the upper electrode film over the capacitance dielectric film, wherein, an entire surface layer of the lower electrode film is formed of a polycrystalline titanium nitride. At the portion of the capacitance dielectric film where directly contacting the entire surface layer of the lower electrode is formed of a polycrystalline metal oxide, and the polycrystalline metal oxide is formed by an ALD method and inherits a crystallinity of the polycrystalline titanium nitride. |
| US09379175B2 |
Integrated circuits and fabrication methods thereof
An integrated circuit includes a first polysilicon region having a first grain size formed on a substrate. The integrated circuit also includes a second polysilicon region, having a second grain size different from the first grain size, formed on the substrate. Furthermore, a method of fabricating an integrated circuit is also provided. The method includes forming a first polysilicon region having an initial grain size on a substrate. The first polysilicon region is implanted with a first dopant of a first conductivity type and a second dopant. After the implantation, the first polysilicon region has a first grain size larger than the initial grain size. Then, a laser rapid thermal annealing process is performed to the first polysilicon region. |
| US09379171B2 |
Display device and a method of manufacturing display device
Disclosed herein is a display device including, a pixel array portion, a drive portion; and a power source wiring; the pixel array portion, at least a part of the drive portion configured to drive the pixel array portion and the power source wiring form a panel, the pixel array portion includes scanning lines disposed in rows, signal lines disposed in columns, and pixels disposed in matrix in portions where the scanning lines and the signal lines cross each other, respectively, and the drive portion includes a scanner portion configured to drive the pixels in a line-sequential manner through the scanning lines, and a signal portion configured to supply a video signal to each of the signal lines in correspondence to the line-sequential drive, so that an image is displayed on the pixel array portion. |
| US09379165B2 |
Semiconductor memory device
A semiconductor memory device according to an embodiment described below comprises: first lines arranged in a first direction perpendicular to a main surface of a substrate and extending in a second direction crossing the first direction; second lines arranged in the second direction, extending in the first direction, and intersecting the first lines; memory cells disposed at intersections of the first lines and the second lines; and an interlayer insulating film provided between the second lines. The interlayer insulating film has an air gap extending continuously in the first direction so as to intersect at least some of the first lines aligned along the first direction. The interlayer insulating film also includes an insulating film positioned above the air gap and having a curved surface that protrudes toward a direction of the substrate. |
| US09379161B2 |
Monolithic semiconductor chip array
A semiconductor chip (10) is provided which comprises: a semiconductor layer sequence (20) with a p-type semiconductor region (5) and an n-type semiconductor region (3), a plurality of p-contacts (11a, 11b), which are connected electrically conductively with the p-type semiconductor region (5), and a plurality of n-contacts (12a, 12b), which are connected electrically conductively with the n-type semiconductor region (3), wherein: the p-contacts (11a, 11b) and the n-contacts (12a, 12b) are arranged on a rear side of the semiconductor chip (10), the semiconductor chip (10) comprises a plurality of regions (21, 22) arranged adjacent one another, and the regions (21, 22) each comprise one of the p-contacts (11a, 11b) and one of the n-contacts (12a, 12b). |
| US09379160B2 |
Solid-state imaging apparatus, method of manufacturing the same, and electronic apparatus
A solid-state imaging apparatus includes a semiconductor substrate in which a charge transfer section configured to transfer a charge generated in a photoelectric conversion section is formed. The semiconductor substrate includes a surface that is formed in a convex shape in an area in which the charge transfer section is formed. |
| US09379156B2 |
Per-channel image intensity correction
Techniques for per-channel image intensity correction includes linear interpolation of each channel of spectral data to generate corrected spectral data. |
| US09379155B2 |
Semiconductor device and method of manufacturing the same
A semiconductor device including a semiconductor substrate having oppositely facing first and second surfaces, the first surface being an active surface and provided with an electronic element thereon, a pad electrode to be connected to the electronic element in a peripheral portion of the electronic element on the active surface, a first opening extending from the second surface toward the pad electrode so as not to reach the first surface of the semiconductor substrate, a second opening formed to reach the pad electrode from a bottom surface of the first opening and having a diameter smaller than that of the first opening, an insulating layer formed to cover sidewall surfaces of the first opening and the second opening, and a conductive layer formed, inside of the insulating layer, to cover at least an inner wall surface of the insulating layer and a bottom surface of the second opening. |
| US09379146B2 |
Method for manufacturing array substrate and method for forming through hole
A method for manufacturing an array substrate and a method for forming a through hole are provided. The method for manufacturing the array substrate comprise: coating photoresist in an insulating layer through-hole region on a substrate; depositing an insulating layer on the substrate provided with the photoresist in the insulating layer through-hole region; and stripping off the photoresist in the insulating layer through-hole region to form an insulating layer through hole. The manufacturing method simplifies the process of forming the insulating layer through hole. |
| US09379142B2 |
Semiconductor device, display device, and electronic device
A pixel includes a load, a transistor which controls a current supplied to the load, a storage capacitor, and first to fourth switches. By inputting a potential in accordance with a video signal into the pixel after the threshold voltage of the transistor is held in the storage capacitor, and holding a voltage of the sum of the threshold voltage and the potential, variations of a current value caused by variations of threshold voltage of a transistor can be suppressed. Consequently, a predetermined current can be supplied to the load such as a light-emitting element. Further, by changing the potential of a power supply line, a display device with a high duty ratio can be provided. |
| US09379140B2 |
Array substrate for liquid crystal display devices and method of manufacturing the same
An array substrate for LCD devices and a method of manufacturing the same are provided. By using a structure where an empty space is secured in a data line area as in a DRD structure in which the number of data lines is reduced by half, a capacitance is sufficiently secured by forming a sub storage capacitor in the data line area of the empty space, and thus, an area of a main storage capacitor can be reduced. Accordingly, the cost can be reduced, and moreover, an aperture ratio can be enhanced. |
| US09379139B2 |
Display apparatus and multi-panel display apparatus
A display apparatus includes a thin film transistor substrate, a gate driver, and a connection line. The thin film transistor substrate includes a display area and a non-display area surrounding the display area. The display area includes gate lines extending along a first direction and data lines extending along a second direction crossing the first direction. The data lines are insulated from the gate lines. The gate driver is at a first non-display area of the non-display area, located outside the display area along the second direction, and is configured to apply a gate signal to the gate lines. The connection line extends along the second direction and couples the gate driver and the gate lines. A resistance of the connection line coupled to a gate line is substantially equal to a resistance of the connection line coupled to another gate line. |
| US09379136B2 |
Semiconductor device and manufacturing method thereof
When a transistor having bottom gate bottom contact structure is manufactured, for example, a conductive layer constituting a source and a drain has a three-layer structure and two-step etching is performed. In the first etching process, an etching method in which the etching rates for at least the second film and the third film are high is employed, and the first etching process is performed until at least the first film is exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. The side wall of the second film is slightly etched when a resist mask is removed after the second etching process. |
| US09379134B2 |
Semiconductor memory devices having increased distance between gate electrodes and epitaxial patterns and methods of fabricating the same
A semiconductor memory device is provided including a substrate, a plurality of interlayer insulating layers and gate electrodes alternately stacked on the substrate. The plurality of interlayer insulating layers and the gate electrodes define a channel hole that vertically penetrates the plurality of interlayer insulating layers and the gate electrodes to expose at least a portion of the substrate. A channel recess is provided in the substrate exposed by the channel hole. An epitaxial pattern fills the channel recess. The epitaxial pattern has an upper surface that is concave and curves inward in a middle portion thereof. |
| US09379133B1 |
Semiconductor device and method of manufacturing the same
A method of manufacturing a semiconductor device includes forming stepped stack structures each including conductive patterns stacked in a shape of steps while exposing respective ends thereof and surrounding channel layers, the stepped stack structures being separated from one another by slits, forming first and second contact plugs connected to the ends of the conductive patterns to extend along an extending direction of the channel layers, and simultaneously forming, using a spacer patterning technology (SPT), bit lines connected to one or more of the channel layers and extending along a first direction, first connecting lines extending along a second direction intersecting the first direction, and contact pads extending from the first connecting lines to be connected to the first contact plugs. |
| US09379131B2 |
Three dimensional stacked semiconductor structure and method for manufacturing the same
A 3D stacked semiconductor structure is provided, comprising a plurality of multi-layered pillars formed on a substrate and spaced apart from each other, a plurality of first conductors formed between the adjacent multi-layered pillars, a plurality of charging-trapping layers formed on the substrate and on the sidewalls of the multi-layered pillars for separating the first conductor and the multi-layered pillars, and a second conductor formed on the first conductors and on the charging-trapping layers. One of the multi-layered pillars comprises a plurality of insulating layers and a plurality of conductive layers arranged alternately. The top surfaces of the first conductors are higher than the top surfaces of the multi-layered pillars so as to create a plurality of receiving trenches respectively on the multi-layered pillars. The second conductor fills up the receiving trenches on the multi-layered pillars. |
| US09379130B2 |
Nonvolatile semiconductor memory device
According to one embodiment, a memory device, includes: a stacked body including first electrode layers stacked alternately with first insulating layers; a selection gate stacked body including selection gate electrode layers stacked alternately with second insulating layers in a stacking direction of the stacked body; a semiconductor member provided inside the stacked body and the selection gate stacked body, the semiconductor member extending in the stacking direction; a memory film provided between the semiconductor member and each of the f first electrode layers; and a gate insulator film provided between the semiconductor member and each of the selection gate electrode layers. Selection transistors are provided on the stacked body, the plurality of selection transistors included the selection gate electrode layers, the gate insulator film, and the semiconductor member, at least two of the selection transistors have mutually different threshold potentials. |
| US09379128B1 |
Split gate non-volatile memory device and method for fabricating the same
A split gate NVM device includes a semiconductor substrate, an ONO structure disposed on the semiconductor substrate, a first gate electrode disposed on the ONO structure, a second gate electrode disposed on the semiconductor substrate, adjacent to and insulated from the first gate electrode and the ONO structure, a first doping region with a first conductivity formed in the semiconductor substrate and adjacent to the ONO structure, a second doping region with the first conductivity formed in the semiconductor substrate and adjacent to the second gate electrode, and a third doping region with the first conductivity formed in the semiconductor substrate, disposed between the first doping region and the second doping region and adjacent to the ONO structure and the second gate electrode. |
| US09379119B1 |
Static random access memory
A static random access memory (SRAM) is disclosed. The SRAM includes a plurality of SRAM cells on a substrate, in which each of the SRAM cells further includes: a gate structure on the substrate, a plurality of fin structures disposed on the substrate, where each fin structure is arranged perpendicular to the arrangement direction of the gate structure, a first interlayer dielectric (ILD) layer around the gate structure, a first contact plug in the first ILD layer, where the first contact plug is strip-shaped and contacts two different fin structures; and a second ILD layer on the first ILD layer. |
| US09379116B1 |
Fabrication of a deep trench memory cell
A method including forming a buffer layer between a top pad layer and a bottom pad layer all above a deep trench capacitor embedded in a substrate, forming a fin pattern, defined by one or more sidewall spacers, above the top pad layer using a sidewall image transfer technique, transferring the fin pattern into the top pad layer stopping of the buffer layer, and forming a fin in direct contact with a strap by transferring the fin pattern into the buffer layer, into the bottom pad layer, and into the substrate and an inner electrode of the deep trench capacitor, the fin is formed from a portion of the substrate and the strap is formed from a portion of the inner electrode of the deep trench capacitor. |
| US09379114B2 |
Semiconductor device and method of fabricating the same
Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include storage node pads disposed adjacent to each other between word lines but spaced apart from each other by an isolation pattern. Accordingly, it is possible to prevent a bridge problem from being caused by a mask misalignment. This enables to improve reliability of the semiconductor device. |
| US09379112B2 |
Integrated circuit with transistor array and layout method thereof
An integrated circuit includes a plurality of transistors. The transistors are electrically connected in series and with their respective gates tied together. The transistors are implemented within a transistor array. The transistors are electrically connected between a first reference terminal and a second reference terminal. A non-dominator part of the transistors adjacent to the first reference terminal are implemented at corner regions of the transistor array. |
| US09379109B1 |
Integrated circuit having improved radiation immunity
An integrated circuit device having improved radiation immunity is described. The integrated circuit device comprises an n-type wafer having a first surface and a second surface; a p-type epitaxial layer formed on the first surface of the n-type wafer, the p-type epitaxial wafer having first elements storing charge; and an n-well formed in the p-type epitaxial layer, the n-well having second elements storing charge; wherein the n-type wafer is positively biased to attract excess minority carriers in the p-type epitaxial layer. A method of improving radiation immunity in an integrated circuit is also described. |
| US09379106B2 |
Semiconductor devices having 3D channels, and methods of fabricating semiconductor devices having 3D channels
A semiconductor device includes a substrate including first to third fins aligned in a first direction, a first trench arranged between the first fin and the second fin, and a second trench arranged between the second fin and the third fin. The semiconductor device further includes a first field insulating film arranged in the first trench, a second field insulating film formed in the second trench, a first dummy gate arranged on the first field insulating film, and a second dummy gate at least partly arranged on the second field insulating film. A lower surface of the second field insulating film is arranged to be lower than a lower surface of the first field insulating film. |
| US09379104B1 |
Method to make gate-to-body contact to release plasma induced charging
Methods for preparing a FinFET device with a protection diode formed prior to M1 formation and resulting devices are disclosed. Embodiments include forming plural fins on a substrate, with a STI region between adjacent fins; forming a dummy gate stack over and perpendicular to the fins, the gate stack including a dummy gate over a dummy gate insulating layer; forming sidewall spacers on opposite sides of the dummy gate stack; forming source/drain regions at opposite sides of the dummy gate stack; forming an ILD over the STI regions between fins; removing the dummy gate stack forming a gate cavity; forming a gate dielectric in the gate cavity; removing the gate dielectric from the gate cavity in a protection diode area, exposing an underlying fin; implanting a dopant into the exposed fin; and forming a RMG in the gate cavity, wherein a protection diode is formed in the protection diode area. |
| US09379103B2 |
Semiconductor device and method of preventing latch-up in a charge pump circuit
A charge pump circuit includes a substrate and first well region formed in the substrate. A first transistor includes first and second conduction regions disposed in the first well region. A second well region is formed in the substrate. A third well region is formed within the second well region. A second transistor includes first and second conduction regions disposed in the third well region. The second well region and third well region are coupled to a common terminal. The common terminal receives a local potential and the first well region and second well region are commonly maintained at the local potential. The first transistor and second transistor operate within the charge pump cell. A plurality of charge pump cells can be cascaded together with an output of a first charge pump cell coupled to an input of a second charge pump cell. |
| US09379102B2 |
Nitride-based semiconductor device
A nitride-based semiconductor diode includes a substrate, a first semiconductor layer disposed on the substrate, and a second semiconductor layer disposed on the first semiconductor layer. The first and second semiconductor layers include a nitride-based semiconductor. A first portion of the second semiconductor layer may have a thickness thinner than a second portion of the second semiconductor layer. The diode may further include an insulating layer disposed on the second semiconductor layer, a first electrode covering the first portion of the second semiconductor layer and forming an ohmic contact with the first semiconductor layer and the second semiconductor layer, and a second electrode separated from the first electrode, the second electrode forming an ohmic contact with the first semiconductor layer and the second semiconductor layer. |
| US09379091B2 |
Semiconductor die assemblies and semiconductor devices including same
Methods of fabricating multi-die assemblies including a wafer segment having no integrated circuitry thereon and having a plurality of vertically stacked dice thereon electrically interconnected by conductive through vias, resulting multi-die assemblies, and semiconductor devices comprising such multi-die assemblies. The wafer segment may function as a heat sink to enhance heat transfer from the stacked dice in the resulting multi-die assembly. The die stacks are fabricated at the wafer level on a base wafer, from which the wafer segment and die stacks are singulated after at least peripheral encapsulation. |
| US09379088B2 |
Stacked package of voltage regulator and method for fabricating the same
The present disclosure relates to a stacked package of a voltage regulator and a method for fabricating the same. The method comprises: providing a first chip and a second chip which are integrated with each other, the first chip and the second chip each having a front surface provided with a plurality of bumps; forming a non-conductive layer and a conductive layer side by side on the back surface of the second chip; providing a first leadframe and a second leadframe each having at least a group of leads, the plurality of bumps on the first chip being electrically coupled to the first leadframe, the plurality of bumps on the second chip being electrically coupled to the second leadframe, and the back surface of the second chip being electrically coupled to a back surface of the first leadframe; the first leadframe being electrically coupled to the second leadframe; the first chip, the second chip, the conductive layer, the non-conductive layer, the bumps, the first leadframe, and the second leadframe forms a stacked package to reduce the footprint of a chip and reducing manufacture cost. |
| US09379087B2 |
Method of making a QFN package
A method of making a flat no lead package including attaching a first plurality of leads in spaced apart relationship in a predetermined pattern on a tape and attaching a first die to the tape at a predetermined position within the predetermined lead pattern. |
| US09379084B2 |
Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
A semiconductor device has a semiconductor die with a die bump pad. A substrate has a conductive trace with an interconnect site. A conductive bump material is deposited on the interconnect site or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and interconnect site. The bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the die and substrate. The bump material is self-confined within the die bump pad or interconnect site. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material substantially within a footprint of the die bump pad and interconnect site. The interconnect structure can have a fusible portion and non-fusible portion. An encapsulant is deposited between the die and substrate. |
| US09379083B2 |
Semiconductor device and method for manufacturing semiconductor device
A semiconductor device is a composite module in which three power semiconductor modules are arranged at a predetermined interval in the same plane and pin-shaped conductors that are drawn from the power semiconductor modules to the outside are connected to three main terminal plates such that they are integrated with each other. When the entire composite module is accommodated in a protective case and a radiation fin is provided, bolts are inserted into through holes to fix the protective case to the radiation fin. In this way, it is possible to accommodate the composite module in the protective case while reliably bringing the bottom of an insulating substrate into close contact with the radiation fin. |
| US09379078B2 |
3D die stacking structure with fine pitches
A package includes package includes a first package component including a first plurality of electrical connectors at a top surface of the first package component, and a second plurality of electrical connectors longer than the first plurality of electrical connectors at the top surface of the first package component. A first device die is over the first package component and bonded to the first plurality of electrical connectors. A second package component is overlying the first package component and the first device die. The second package component includes a third plurality of electrical connectors at a bottom surface of the second package component. The third plurality of electrical connectors is bonded to the second plurality of electrical connectors. A fourth plurality of electrical connectors is at a bottom surface of the second package. The second and the fourth plurality of electrical connectors comprise non-solder metallic materials. |
| US09379076B2 |
Semiconductor device and manufacturing method thereof
A method of manufacturing a semiconductor structure includes receiving a substrate including a die pad disposed thereon; disposing a passivation over the substrate and around the die pad; disposing a polymer over the passivation; forming a post passivation interconnect (PPI) including an elongated portion and a via portion contacting with the die pad; depositing a metallic paste on the elongated portion of the PPI by a stencil; disposing a conductive bump over the metallic paste; and disposing a molding over the PPI and around the metallic paste and the conductive bump. |
| US09379075B2 |
Semiconductor device with bump stop structure
A method for manufacturing semiconductor devices is provided. In the method, a conductive pad and a metal protrusion pattern are formed in a metallization layer. A passivation layer is conformally deposited over the metallization, and a protection layer is conformally deposited over the passivation layer. Further, a post-passivation interconnect structure (PPI) is conformally formed on the protection layer, and the PPI structure includes a landing pad region, a protrusion pattern over at least a portion of the landing pad region and a connection line electrically connected to the conductive pad. A solder bump is then placed on the landing pad region in contact with the protrusion pattern of PPI structure. A to semiconductor device with bum stop structure is also provided. |
| US09379074B2 |
Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
An apparatus relating generally to a die stack is disclosed. In such an apparatus, a substrate is included. A first bond via array includes first wires each of a first length extending from a first surface of the substrate. An array of bump interconnects is disposed on the first surface. A die is interconnected to the substrate via the array of bump interconnects. A second bond via array includes second wires each of a second length different than the first length extending from a second surface of the die. |
| US09379073B2 |
Multi-layer pad ring for integrated circuit
Some embodiments of the disclosed subject matter include an integrated circuit. The integrated circuit includes a solid state device controller configured to control a plurality of flash memory devices, a first set of input output IO pads, coupled to the solid state device controller, arranged as a first pad ring around a perimeter of the integrated circuit, and a second set of IO pads arranged adjacent to at least one side of the first pad ring, wherein one of the second set of IO pads includes a power source node configured to receive a power supply voltage for the solid state device controller, a ground node, and a bond pad configured to receive an external signal. |
| US09379071B2 |
Single inline no-lead semiconductor package
Embodiments of a packaged semiconductor device with no leads are disclosed. One embodiment includes a semiconductor chip and a no leads package structure defining a boundary and having a bottom surface and includes three or more pads exposed at the bottom surface of the package structure. Each of the pads is located in a single inline row. |
| US09379069B2 |
Semiconductor arrangement comprising transmission line surrounded by magnetic layer
A semiconductor arrangement is provided. The semiconductor arrangement includes a first dielectric layer surrounding a first transmission line and a magnetic layer surrounding the first dielectric layer. The magnetic layer increases the inductance of the transmission line. The semiconductor arrangement having the magnetic layer surrounding the first transmission line has increased impedance, which promotes current flow through the transmission line, without having increased resistance as compared to a semiconductor arrangement that does not have a magnetic layer. Increased resistance requires increased power, which results in a shorter semiconductor arrangement life span than the semiconductor arrangement without the increased resistance. |
| US09379067B2 |
Semiconductor devices and methods of manufacture thereof having guard ring structure
In some embodiments, an integrated circuit (IC) device includes a substrate having a first functional region, a second functional region and a third functional region. The IC device also includes a plurality of dielectric layers over the substrate, a first guard ring in the plurality of dielectric layers and around the first functional region, and a second guard ring in the plurality of dielectric layers and around the second functional region. The second guard ring is separate from the first guard ring, and the third functional region is free of a guard ring. The IC device further includes a seal ring in the plurality of dielectric layers. The seal ring encircles the first and the second guard rings, and is separate from the first and the second guard rings. |
| US09379065B2 |
Crack stopping structure in wafer level packaging (WLP)
Some implementations provide a semiconductor device (e.g., die, wafer) that includes a substrate, metal layers and dielectric layers coupled to the substrate, a pad coupled to one of the several metal layers, a first metal redistribution layer coupled to the pad, an under bump metallization (UBM) layer coupled to the first metal redistribution layer. The semiconductor device includes several crack stopping structures configured to surround a bump area of the semiconductor device and a pad area of the semiconductor device. The bump area includes the UBM layer. The pad area includes the pad. In some implementations, at least one crack stopping structure includes a first metal layer and a first via. In some implementations, at least one crack stopping structure further includes a second metal layer, a second via, and a third metal layer. In some implementations, at least one crack stopping structure is an inverted pyramid crack stopping structure. |
| US09379061B2 |
High density dielectric etch-stop layer
Some embodiments of the present disclosure relate to an integrated circuit device. The integrated circuit device includes a semiconductor substrate, and an inter-level dielectric layer arranged over the semiconductor substrate. An etch-stop layer is arranged over the inter-level dielectric layer. The etch-stop layer comprises silicon oxide, silicon nitride, or silicon oxynitride, and has a density greater than or equal to 2.15 g/cm3. |
| US09379059B2 |
Power and ground routing of integrated circuit devices with improved IR drop and chip performance
An integrated circuit chip includes a semiconductor substrate having thereon a plurality of IMD layers and a plurality of first conductive layers; a first passivation layer overlying the plurality of IMD layers and the first conductive layers; at least a first power/ground mesh wiring line in a first aluminum layer overlying the first Insulating layer; and at least a second power/ground mesh wiring line in a second aluminum layer overlying the first aluminum layer. |
| US09379058B2 |
Grounding dummy gate in scaled layout design
A semiconductor device includes a gate and a first active contact adjacent to the gate. Such a device further includes a first stacked contact electrically coupled to the first active contact, including a first isolation layer on sidewalls electrically isolating the first stacked contact from the gate. The device also includes a first via electrically coupled to the gate and landing on the first stacked contact. The first via electrically couples the first stacked contact and the first active contact to the gate to ground the gate. |
| US09379057B2 |
Method and structure to reduce the electric field in semiconductor wiring interconnects
Embodiments of the present invention provide increased distance between vias and neighboring metal lines in a back end of line (BEOL) structure. A copper alloy seed layer is deposited in trenches that are formed in a dielectric layer. The trenches are then filled with copper. An anneal is then performed to create a self-forming barrier using a seed layer constituent, such as manganese, as the manganese is drawn to the dielectric layer during the anneal. The self-forming barrier is disposed on a shoulder region of the dielectric layer, increasing the effective distance between the via and its neighboring metal lines. |
| US09379054B2 |
Chip on film and display apparatus
The present disclosure of the present invention provides a chip on film and a display apparatus. The chip on film comprises a substrate having an input end lead and an output end lead, a region where the input end lead is located and a region where the output end lead is located are defined as a binding region, wherein the maximum thickness of the binding region is larger than the maximum thickness of other parts of the substrate than the binding region. |
| US09379049B2 |
Semiconductor apparatus
The semiconductor apparatus includes: the first lead frame; the second lead frame; the second insulation resin which is disposed between the first lead frame and the second lead frame; the sealing resin which seals the semiconductor elements, the first lead frame and the second lead frame; the electric wiring part which electrically connects the semiconductor elements and the first lead frame; and the interlayer connecting part which electrically connects the first lead frame and the second lead frame. |
| US09379048B2 |
Dual-flag stacked die package
In one embodiment, a semiconductor package includes a first and a second die flag, wherein the first and second die flags are separated by a gap. First and second metal oxide semiconductor field effect transistor (MOSFET) die are on the first and the second die flags, respectively. A power control integrated circuit (IC) is stacked on top of at least one of the first or the second MOSFET die. A mold compound is encapsulating the power control IC, the first and second MOSFET die, and the first and second die flags. |
| US09379046B2 |
Module comprising a semiconductor chip
A module includes a semiconductor chip having at least a first terminal contact surface and a second terminal contact surface. A first bond element made of a material on the basis of Cu is attached to the first terminal contact surface, and a second bond element is attached to the second terminal contact surface. The second bond element is made of a material different from the material of the first bond element or is made of a type of bond element different from the type of the first bond element. |
| US09379043B1 |
TSV structure having insulating layers with embedded voids
Disclosed is a TSV structure having insulating layers with embedded voids, including a chip layer, a dielectric liner and a conductive filler. There is at least a via reentrant from one surface of the semiconductor body of the chip layer. A plurality of air-gap cavities are formed on the sidewall of the via where the cavities have a depth-to-width ratio not less than one. The dielectric liner covers the sidewall of the via without filling into the air-gap cavities. The conductive filler is disposed in the via without filling into the air-gap cavities due to the isolation of the dielectric liner so as to form an air insulating layer with a plurality of enclosed voids embedded between the semiconductor body and the dielectric liner. Accordingly, RC Delay of the TSV structure can be improved. |
| US09379041B2 |
Fan out package structure
Packages and methods of forming packages are disclosed. In an example, a structure comprises a die comprising an electrical pad on an active side, and an encapsulant laterally around the die and extending directly over the active side of the die. A conductive pattern is over the encapsulant, and the conductive pattern comprises a via in an opening through the encapsulant to the electrical pad. The via contacts the electrical pad. In some embodiments, a dielectric layer is over the encapsulant, and the conductive pattern is over the dielectric layer. In other embodiments, the encapsulant is a dielectric-encapsulant, and the conductive pattern adjoins the dielectric-encapsulant. In some embodiments, the encapsulant may be a photo-patternable material, a molding compound, or an Ajinomoto Build-up Film. The structure may further comprise additional dielectric layers and conductive patterns. |
| US09379037B2 |
Thermal module accounting for increased board/die size in a portable computer
This application relates to a low profile, small footprint cooling stack that does not extend substantially beyond a footprint of an integrated circuit to which it is affixed. The cooling stack utilizes a number of beam springs that supply a seating force to the integrated circuit by way of a metal slug. In some embodiments, a bottom surface of the metal slug can be contoured in accordance with a top surface of the integrated circuit and/or socket. In other embodiments a gap between peripheral portion of a bottom surface of the metal slug and an associated printed circuit board can be filled by a layer of foam to reduce auditory signals generated by the integrated circuit. |
| US09379036B2 |
3DIC packages with heat dissipation structures
A package includes a first die and a second die underlying the first die and in a same first die stack as the first die. The second die includes a first portion overlapped by the first die, and a second portion not overlapped by the first die. A first Thermal Interface Material (TIM) is over and contacting a top surface of the first die. A heat dissipating lid has a first bottom surface contacting the first TIM. A second TIM is over and contacting the second portion of the second die. A heat dissipating ring is over and contacting the second TIM. |
| US09379032B2 |
Semiconductor packaging having warpage control and methods of forming same
An embodiment method for forming a semiconductor device package comprises bonding a first die to a package substrate and forming a molding compound over the package substrate and around the first die. A surface of the first die opposing the package substrate is exposed after forming the molding compound. The method further comprises bonding a plurality of second dies to the surface of the first die opposing the package substrate after forming the molding compound. |
| US09379030B2 |
Ion implantation method and ion implantation apparatus
Provided is an ion implantation method of transporting ions generated by an ion source to a wafer and implanting the ions into the wafer by irradiating an ion beam on the wafer, including, during the ion implantation into the wafer, using a plurality of detection units which can detect an event having a possibility of discharge and determining a state of the ion beam based on existence of detected event having a possibility of discharge and a degree of influence of the event on the ion beam. |
| US09379028B2 |
SOI CMOS structure having programmable floating backplate
SOI CMOS structures having at least one programmable electrically floating backplate are provided. Each electrically floating backplate is individually programmable. Programming can be performed by injecting electrons into each conductive floating backplate. Erasure of the programming can be accomplished by tunneling the electrons out of the floating backplate. At least one of two means can accomplish programming of the electrically floating backgate. The two means include Fowler-Nordheim tunneling, and hot electron injection using an SOI pFET. Hot electron injection using pFET can be done at much lower voltage than injection by tunneling electron injection. |
| US09379026B2 |
Fin-shaped field-effect transistor process
A fin-shaped field-effect transistor process includes the following steps. A substrate is provided. A first fin-shaped field-effect transistor and a second fin-shaped field-effect transistor are formed on the substrate, wherein the first fin-shaped field-effect transistor includes a first metal layer and the second fin-shaped field-effect transistor includes a second metal layer. A treatment process is performed on the first fin-shaped field-effect transistor to adjust the threshold voltage of the first fin-shaped field-effect transistor. A fin-shaped field-effect transistor formed by said process is also provided. |
| US09379021B2 |
Method to reduce K value of dielectric layer for advanced FinFET formation
Embodiments described herein generally relate to methods for forming gate structures. Various processes may be performed on a gate dielectric material to reduce the K value of the dielectric material. The gate dielectric having a reduced K value may provide for reduced parasitic capacitance and an overall reduced capacitance. The gate dielectric may be modified without thermodynamic constraint. |
| US09379019B2 |
Methods of manufacturing a semiconductor device
In a method, an isolation layer pattern is formed on a substrate to define first and second active fins. An ARC layer is formed on the isolation layer pattern to at least partially cover sidewalls of the first and second active fins. A level of a top surface of the ARC layer is equal to or less than, and equal to or greater than half of, those of the first and second active fins. A photoresist layer is formed on the first and second active fins and the ARC layer. A portion of the photoresist layer is removed to form a photoresist pattern covering the first active fin and exposing the second active fin. A portion of the ARC layer under the removed portion of the photoresist layer is removed to form an ARC layer pattern. Impurities are implanted into the exposed second active fin to form an impurity region. |
| US09379016B2 |
Wafer processing method
A wafer processing method including a wafer supporting step of attaching a front side of a dicing tape formed of synthetic resin to a back side of a wafer and supporting a peripheral portion of the dicing tape to an annular frame, a dicing tape heating step of heating a back side of the dicing tape attached to the wafer to soften the dicing tape, thereby flattening the back side of the dicing tape, and a modified layer forming step of applying a laser beam having a transmission wavelength to the wafer through the dicing tape from the back side thereof along the division lines in the condition where the focal point of the laser beam is set inside the wafer, thereby forming a modified layer inside the wafer along each division line. |
| US09379015B2 |
Wafer processing method
A wafer processing method divides a wafer into individual devices along crossing streets formed on the front side of the wafer. The wafer has a substrate and a functional layer formed on the front side of the substrate. The individual devices are formed from the functional layer and are partitioned by the streets. A laser beam is applied along the streets from the front side of the functional layer to thereby remove the functional layer along the streets. A resist film is formed on the front side of the functional layer except on each street. The substrate of the wafer is plasma-etched along each street where the functional layer is absent to the depth corresponding to the finished thickness of each device, thereby forming a division groove along each street and also etching off a modified layer formed on the opposite sides of each street. |
| US09379014B1 |
Static random-access memory (SRAM) array
A static random-access memory (SRAM) array includes a first metal layer and a second metal layer. The metal layer includes multiple first source lines spanning multiple columns of cells. The multiple first source lines include a first source line and a second source line. The second metal layer includes multiple second source lines spanning multiple rows of cells. The SRAM array further includes a set of vias coupled to the multiple first source lines and to the multiple second source lines. A first via of the set of vias is coupled to the first source line and multiple vias of the set of vias are coupled to the second source line. Two vias of the multiple vias that are closest to the first via are each substantially the same distance from the first via. |
| US09379011B2 |
Methods for depositing nickel films and for making nickel silicide and nickel germanide
In one aspect, methods of silicidation and germanidation are provided. In some embodiments, methods for forming metal silicide can include forming a non-oxide interface, such as germanium or solid antimony, over exposed silicon regions of a substrate. Metal oxide is formed over the interface layer. Annealing and reducing causes metal from the metal oxide to react with the underlying silicon and form metal silicide. Additionally, metal germanide can be formed by reduction of metal oxide over germanium, whether or not any underlying silicon is also silicided. In other embodiments, nickel is deposited directly and an interface layer is not used. In another aspect, methods of depositing nickel thin films by vapor phase deposition processes are provided. In some embodiments, nickel thin films are deposited by ALD. Nickel thin films can be used directly in silicidation and germanidation processes. |
| US09379010B2 |
Methods for forming interconnect layers having tight pitch interconnect structures
Processes for forming interconnection layers having tight pitch interconnect structures within a dielectric layer, wherein trenches and vias used to form interconnect structures have relatively low aspect ratios prior to metallization. The low aspect ratios may reduce or substantially eliminate the potential of voids forming within the metallization material when it is deposited. Embodiments herein may achieve such relatively low aspect ratios through processes that allow for the removal of structures, which are utilized to form the trenches and the vias, prior to metallization. |
| US09379009B2 |
Interconnection structures in a semiconductor device and methods of manufacturing the same
Methods of fabricating interconnection structures of a semiconductor device are provided. The method includes, inter alia: forming a first insulation layer on a semiconductor substrate, forming a mold layer having trenches on the first insulation layer, forming a sidewall protection layer including a first metal silicide layer on sidewalls of the trenches, forming second metal lines that fill the trenches, forming upper protection layers on the second metal lines, removing the mold layer after formation of the upper protection layers to provide gaps between second metal lines, and forming a second insulation layer in the gaps and on the upper protection layers. The second insulation layer is formed to include air gaps between the second metal lines. Related interconnection structures are also provided. |
| US09379007B2 |
Electromigration-resistant lead-free solder interconnect structures
Embodiments of the invention include a lead-free solder interconnect structure and methods for making a lead-free interconnect structure. The structure includes a semiconductor substrate having a last metal layer, a copper pedestal attached to the last metal layer, a barrier layer attached to the copper pedestal, a barrier protection layer attached to the barrier layer, and a lead-free solder layer contacting at least one side of the copper pedestal. |
| US09379005B2 |
Three dimensional memory and methods of forming the same
Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described. |
| US09379002B2 |
Semiconductor device having air-gap
A semiconductor device includes a bit line structure located on a semiconductor substrate, an outer bit line spacer located on a first side surface of the bit line structure, an inner bit line spacer including a first part located between the bit line structure and the outer bit line spacer and a second part located between the semiconductor substrate and the outer bit line spacer, and a block bit line spacer located between the outer bit line spacer and the second part of the inner bit line spacer. A first air-gap is defined by the outer bit line spacer, the inner bit line spacer, and the block bit line spacer. |
| US09379001B2 |
Semiconductor device and method of fabricating the same
A semiconductor device includes line patterns disposed on a substrate, the line patterns extending in a first direction and being parallel to one another. The semiconductor device includes conductive patterns spaced apart from each other in the first direction between an adjacent pair of the line patterns. The semiconductor device includes insulating fences electrically isolating the conductive patterns from each other and having chamfered corners. The semiconductor device includes insulating patterns filling gaps between side surfaces of the line patterns and the chamfered corners of the insulating fences. |
| US09378998B2 |
Semiconductor structure and method of forming a harmonic-effect-suppression structure
A method of forming a harmonic-effect-suppression structure is disclosed. The method includes: providing a semiconductor substrate having a base semiconductor substrate, a buried dielectric on the base semiconductor substrate, and a surface semiconductor layer on the buried dielectric. Next, a deep trench is formed extending through the surface semiconductor layer and the buried dielectric into the base semiconductor substrate, a silicon layer is formed within a lower portion of the deep trench, the silicon layer allowed to have a top surface height substantially the same as or lower than a top surface height of the base semiconductor substrate, and a dielectric layer is formed within the deep trench and on the silicon layer. |
| US09378996B2 |
Holding device for holding a patterned wafer
This invention relates to a mounting apparatus for mounting and supporting one structure side of a substrate, which structure side has structures thereon. The apparatus having a mounting element with a flat mounting surface for supporting the structures and a suction surface F2 which penetrates the mounting surface solely in an outer ring surface for effecting a fluid flow which produces suctions on the substrate. |
| US09378995B2 |
Port door positioning apparatus and associated methods
A loadport has a port door and a frame with an opening through which the port door interfaces with a container door of a container for holding semiconductor workpieces. In one embodiment, a movable closure mechanism is connected to the port door and is defined to be movable in a controlled manner relative to both the port door and the frame. In this embodiment, a stationary closure mechanism is disposed on the frame proximate to the opening. In another embodiment, a stationary closure mechanism is connected to the port door, and a movable closure mechanism is disposed on the frame proximate to the opening. In both embodiments, the movable closure mechanism is defined to engage with the stationary closure mechanism such that movement of the movable closure mechanism to engage with the stationary closure mechanism applies a closing force between the port door and the container door. |
| US09378994B2 |
Multi-position batch load lock apparatus and systems and methods including same
Various embodiments of batch load lock apparatus are disclosed. The batch load lock apparatus includes a load lock body including first and second load lock openings, a lift assembly within the load lock body, the lift assembly including multiple wafer stations, each of the multiple wafer stations adapted to provide access to wafers through the first and second load lock openings, wherein the batch load lock apparatus includes temperature control capability (e.g., heating or cooling). Batch load lock apparatus is capable of transferring batches of wafers into and out of various processing chambers. Systems including the batch load lock apparatus and methods of operating the batch load lock apparatus are also provided, as are numerous other aspects. |
| US09378993B2 |
Wafer-related data management method and wafer-related data creation device
A wafer-related data creation device including a setting stand for setting wafer pallets, a test-use suction nozzle for picking up die on dicing sheet of a wafer pallet set on the setting stand, a test-use pusher pin for pushing up the adhesive section of die from dicing sheet which is being attempted to be picked up by test-use suction nozzle, and a test-use camera for capturing an image of die on dicing sheet is used. The wafer pallet for which wafer-related data is to be created is set on the setting stand of wafer-related device creation device, an image captured by test-use camera is processed, pusher movement of test-use pusher pin and die pickup movement of test-use pickup nozzle is performed, and wafer-related data is created. |
| US09378990B2 |
Adjusting intensity of laser beam during laser operation on a semiconductor device
Among other things, a system and method for adjusting the intensity of a laser beam applied to a semiconductor device are provided for herein. A sensor is configured to measure the intensity of a laser beam reflected from the semiconductor device. Based upon the reflection intensity, an intensity of the laser beam that is applied to the semiconductor device is adjusted, such as to alter an annealing operation performed on the semiconductor device, for example. |
| US09378985B2 |
Method of thinning a wafer to provide a raised peripheral edge
A first area of a first surface of an encapsulated component can be thinned, the component including: a semiconductor chip having an active surface opposite the first surface, and an encapsulant extending outwardly from edges of the semiconductor chip. An entire area of the active surface may be aligned with the first area. After the abrading, a second area of the encapsulated component beyond the first area may have a thickness greater than a thickness of the first area. The second area can be configured to fully support the abraded encapsulated component in a state of the encapsulated component being manipulated by handling equipment. |
| US09378982B2 |
Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package
Various embodiments of mechanisms for forming through package vias (TPVs) with openings surrounding end-portions of the TPVs and a package on package (PoP) device with bonding structures utilizing the TPVs are provided. The openings are formed by removing materials, such as by laser drill, surrounding the end-portions of the TPVs. The openings surrounding the end-portions of the TPVs of the die package enable solders of the bonding structures formed between another die package to remain in the openings without sliding and consequently increases yield and reliability of the bonding structures. Polymers may also be added to fill the openings surrounding the TPVs or even the space between the die packages to reduce cracking of the bonding structures under stress. |
| US09378979B2 |
Methods of fabricating semiconductor devices and devices fabricated thereby
Methods of fabricating semiconductor devices are provided including performing two photolithography processes and two spacer processes such that patterns are formed to have a pitch that is smaller than a limitation of photolithography process. Furthermore, line and pad portions are simultaneously defined by performing the photolithography process once and, thus, there is no necessity to perform an additional photolithography process for forming the pad portion. Related devices are also provided. |
| US09378977B2 |
Non-volatile memory devices and methods of fabricating the same
A non-volatile memory device comprises a substrate, a control gate electrode on the substrate, and a charge storage region between the control gate electrode and the substrate. A control gate mask pattern is on the control gate electrode, the control gate electrode comprising a control base gate and a control metal gate on the control base gate. A width of the control metal gate is less than a width of the control gate mask pattern. An oxidation-resistant spacer is at sidewalls of the control metal gate positioned between the control gate mask pattern and the control base gate. |
| US09378976B2 |
Method for forming interconnects
A conductive interconnect including trenches (110) and (186) and vias (202) are formed in a workpiece (100) by applying a dielectric film stack (120) over the workpiece, and thereafter applying photoresist (140) over the film stack. Trenches (142) are patterned in the photoresist, wherein the trenches are in segments disposed end-to-end to each other. The segments are longitudinally spaced apart from each other at locations where the vias (202) are to be located. The trenches are etched into the dielectric film stack, and then filled with conductive material to form metal line segments (186). Vias (192) are patterned in the gaps separating the adjacent ends of the longitudinally-related lines (186). The patterned vias are etched and then filled with a conductive material, with the ends of the adjacent line segments (186) serving to accurately locate the vias, in a direction along the lengths of the trenches. |
| US09378973B1 |
Method of using sidewall image transfer process to form fin-shaped structures
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region; forming a plurality of mandrels on the first region and a plurality of patterns on the second region, in which the widths of the patterns on the second region are greater than the widths of the mandrels on the first region; forming a hard mask on the second region to cover the patterns; and forming a cap layer on the first region and the second region to cover the mandrels and the hard mask. |
| US09378972B2 |
Integration of dense and variable pitch fin structures
Methods for forming semiconductor devices. Methods for forming fin structures include forming first sidewalls around a first set of mandrels. The first set of mandrels is removed and second sidewalls are formed around the first sidewalls and a second set of mandrels. The first sidewalls and the second set of mandrels are removed and an underlying layer around the second sidewalls is etched. |
| US09378970B2 |
Plasma etching process
A method and system are provided for etching a layer to be etched in a plasma etching reactor, including: forming a reactive layer by injection of at least one reactive gas to form a reactive gas plasma, which forms, together with the layer to be etched, a reactive layer which goes into the layer to be etched during etching of said layer to be etched, wherein the reactive layer reaches a steady state thickness upon completion of a determined duration of said injection; said injection being interrupted before said determined duration has elapsed so that, upon completion of the forming of the reactive layer, the thickness of the reactive layer is smaller than said steady state thickness; and removing the reactive layer by injection of at least one inert gas to form an inert gas plasma, which makes it possible to remove only the reactive layer. |
| US09378965B2 |
Highly conductive source/drain contacts in III-nitride transistors
In one embodiment, a method for fabricating a III-Nitride transistor on a III-Nitride semiconductor body is disclosed. The method comprises etching dielectric trenches in a field dielectric overlying gate, source, and drain regions of the III-Nitride semiconductor body, and thereafter forming a gate dielectric over the gate, source and drain regions. The method further comprises forming a blanket diffusion barrier over the gate dielectric layer, and then removing respective portions of the blanket diffusion barrier from the source and drain regions. Thereafter, gate dielectric is removed from the source and drain regions to substantially expose the source and drain regions. Then, ohmic contacts are formed by depositing contact metal in the source and drain regions. The method results in highly conductive source/drain contacts that are particularly suitable for power transistors, for example, III-Nitride transistors, such as GaN transistors. In another embodiment, a structure for highly conductive source/drain contacts is disclosed. |
| US09378963B2 |
Self-aligned contact and method of forming the same
Some embodiments of the present disclosure relate to a method to form a source/drain SAC for a transistor. The method comprises forming a pair of gate structures within a first dielectric material on a surface of a substrate, which are isolated from the first dielectric material by an etch stop material. A cap material is formed over the pair of gate structures and the first dielectric material. A pattern of mask material is formed by implanting regions of the cap material with dopants. The implanted regions of the cap material are then removed by a selective etch, which forms the pattern of mask material over each gate structure. The pattern of mask material is configured to shield each gate structure during a subsequent etch step to prevent shorting of the gate structure to the SAC. |
| US09378962B2 |
Nonvolatile semiconductor storage device having a charge storage layer that includes metal grains
A nonvolatile semiconductor storage device includes a semiconductor layer, a first insulating film formed on the semiconductor layer, a charge storage layer formed on the first insulating film and having fine metal grains, a second insulating film formed on the charge storage layer, and a gate electrode formed on the second insulating film. During a write operation, a differential voltage is applied across the gate electrode and the semiconductor layer to place the gate electrode at a lower voltage than the semiconductor layer and cause a positive electric charge to be stored in the charge storage layer. |
| US09378960B2 |
Method and structure for improved floating gate oxide integrity in floating gate semiconductor devices
Methods for forming floating gate transistors provide for using a self-aligned plug formed over a floating gate electrode without use of an additional photolithography operation. The plug is centrally disposed and is formed and aligned using spacers. The spacers are formed alongside edges of a patterned sacrificial, oxidation resistant layer that includes an opening that defines the floating gate region. The plug may be formed of a silicon material and which becomes oxidized along with the floating gate such that the plug eventually forms part of the floating gate electrode or the plug may be formed of a nitride or other oxidation resistant material to retard or prevent oxidation in the central portion of the floating gate in which the plug is aligned. |
| US09378958B2 |
Electrostatic discharge protection structure and fabricating method thereof
A method of fabricating an electrostatic discharge protection structure includes the following steps. Firstly, a semiconductor substrate is provided. Plural isolation structures, a well region, a first conductive region and a second conductive region are formed in the semiconductor substrate. The well region contains first type conducting carriers. The first conductive region and the second conductive region contain second type conducting carriers. Then, a mask layer is formed on the surface of the semiconductor substrate, wherein a part of the first conductive region is exposed. Then, a first implantation process is performed to implant the second type conducting carriers into the well region by using the mask layer as an implantation mask, so that a portion of the first type conducting carriers of the well region is electrically neutralized and a first doped region is formed under the exposed part of the first conductive region. |
| US09378954B2 |
Plasma pre-treatment for improved uniformity in semiconductor manufacturing
Methods for forming a semiconductor devices are provided. A plasma pre-treatment operation is performed on a photoresist pattern formed over a material disposed over a substrate, and reduces critical dimensions (CDs) of features of the photoresist pattern to a greater extent at a central portion of the substrate than at outer portions of the substrate, thereby forming a treated pattern with a gradient of CDs. The material is then etched using the treated pattern as a photomask. An overetch operation that tends to reduce CDs of the etched features of the material to a greater extent at outer portions of the substrate than at the central portion of the substrate, is employed. The plasma pre-treatment operation is designed in conjunction with the overetch characteristics and, in combination, the operations produce etched features having CDs with a high degree of uniformity across the substrate. |
| US09378950B1 |
Methods for removing nuclei formed during epitaxial growth
A method for removing nuclei formed during a selective epitaxial growth process includes epitaxially growing a first group of one or more semiconductor structures over a substrate with one or more mask layers. A second group of a plurality of semiconductor structures is formed on the one or more mask layers. The method also includes forming one or more protective layers over the first group of one or more semiconductor structures. At least a subset of the second group of the plurality of semiconductor structures is exposed from the one or more protective layers. The method further includes, subsequent to forming the one or more protective layers over the first group of one or more semiconductor structures, etching at least the subset of the second group of the plurality of semiconductor structures. |
| US09378949B1 |
Monolithic integration of group III nitride epitaxial layers
A monolithically integrated device includes a substrate, a first set of Group III nitride epitaxial layers grown for a first HFET on a first region of the substrate, and a second set of Group III nitride epitaxial layers for a second HFET grown on a second region of the substrate. |
| US09378942B2 |
Deposition method and deposition apparatus
Disclosed is a method for depositing an insulating film with a high coverage through a low temperature process. The deposition method deposits an insulating film on a substrate using a deposition apparatus which includes a processing container that defines a processing space in which plasma is generated, a gas supply unit configured to supply a gas into the processing space, and a plasma generating unit configured to generate plasma by supplying microwave into the processing container. The deposition method includes depositing an insulating film that includes SiN on the substrate by supplying into a gas formed by adding H2 to trisilylamine into the processing container and generating plasma. |
| US09378941B2 |
Interface treatment of semiconductor surfaces with high density low energy plasma
An electron beam plasma source is used in a soft plasma surface treatment of semiconductor surfaces containing Ge or group III-V compound semiconductor materials. |
| US09378939B2 |
Electric lamp and manufacture method therefor
A high pressure gas discharge lamp includes a ceramic discharge vessel that has a container wall enclosing a discharge space having a filling. First and second electrodes are mutually oppositely arranged in the discharge space and are mounted on first and second feedthroughs, respectively, which extend in a gas-tightly sealed manner through the container wall. The high pressure gas discharge lamp further includes a UV-enhancer that has a wall portion and a chamber. The chamber is enclosed by the wall portion of the UV-enhancer and an end part of the container wall. |
| US09378935B2 |
Geiger-Muller counter tube and radiation measurement apparatus
A Geiger-Muller counter tube includes a cylindrical enclosing tube, an anode electrode, a cylindrical cathode electrode, an inert gas, and a quenching gas. The cylindrical enclosing tube has a sealed space. The anode electrode is disposed inside the space and formed in a rod shape. The cylindrical cathode electrode surrounds a peripheral area of the anode electrode inside the space to have an opening. The inert gas and the quenching gas are sealed inside the space. At least one of the anode electrode and the cathode electrode includes a plurality of electrodes inside the enclosing tube. |
| US09378934B2 |
Racetrack-shaped magnetic-field-generating apparatus for magnetron sputtering
A racetrack-shaped magnetic-field-generating apparatus for magnetron sputtering having a linear portion and corner portions, which comprises a center magnetic pole member; a peripheral magnetic pole member surrounding the center magnetic pole member; pluralities of permanent magnets arranged between the center magnetic pole member and the peripheral magnetic pole member to have magnetic poles aligned in one direction; and a non-magnetic base member supporting them; permanent magnets arranged in at least the linear portion being inclined with their surfaces on the side of the center magnetic pole member lower, and with their outside magnetic pole surfaces not in contact with the peripheral magnetic pole member in lower portions; the distance between the center magnetic pole member and the target being the same as the distance between the peripheral magnetic pole member and the target, thereby generating a uniform magnetic field on a target surface. |
| US09378933B2 |
Apparatus for generating reactive gas with glow discharges and methods of use
An apparatus for generating a flow of reactive gas for decontaminating a material, surface or area, which comprises a first electrode member comprising a first conductive sheet and a first plurality of conductive pins protruding from a surface of the first conductive sheet and a second electrode member comprising a second conductive sheet and a second plurality of conductive pins protruding from a surface of the second conductive sheet. The second electrode member is arranged in spaced relationship with the first electrode member to define a reactor channel between the first conductive sheet and the second conductive sheet The first plurality of conductive pins protrude within the reactor channel towards the second conductive sheet and the second plurality of conductive pins protrude within the reactor channel towards the first conductive sheet so as to form air gaps between the first plurality of conductive pins and the second plurality of conductive pins. An air blower generates a flow of air through the reactor channel. An electric pulse generator repetitively generates voltage pulses between the first and second electrode members so as to produce glow discharges in the air gaps between the conductive pins of the first plurality and the conductive pins of the second plurality, the voltage pulses being generated at a pulse repetition frequency greater than about 1 kHz and voltage pulse duration less than about 100 ns, the glow discharges being adapted to transform part of the flow of air into reactive gas. An output section delivers the reactive gas from the reactor channel to a sample or region to be decontaminated. |
| US09378932B2 |
Device and process for preventing substrate damages in a DBD plasma installation
The present invention relates to a process for preventing substrate damages in an installation for surface treatment by dielectric barrier discharge (DBD) and a surface treatment DBD installation for carrying out such process. It comprises:—detecting the amplitude of the voltage at the terminals of the electrodes and the amplitude of the current circulating between said electrodes;—defining the maximum number of alternations of voltage at the terminals of the electrodes in the presence of a hot electric arc (n max) in order not to exceed 50 Joules as dissipated energy in said substrate;—when a hot electric arc appears between said electrodes, modifying with inverse feedback the voltage at the terminals of said electrodes before the defined maximum number of alternations of voltage at the terminals of the electrodes is reached. |
| US09378930B2 |
Inductively coupled plasma reactor having RF phase control and methods of use thereof
Embodiments of the present invention generally provide an inductively coupled plasma (ICP) reactor having a substrate RF bias that is capable of control of the RF phase difference between the ICP source (a first RF source) and the substrate bias (a second RF source) for plasma processing reactors used in the semiconductor industry. Control of the RF phase difference provides a powerful knob for fine process tuning. For example, control of the RF phase difference may be used to control one or more of average etch rate, etch rate uniformity, etch rate skew, critical dimension (CD) uniformity, and CD skew, CD range, self DC bias control, and chamber matching. |
| US09378928B2 |
Apparatus for treating a gas in a conduit
Apparatus for treating a gas in a conduit of a substrate processing system are provided. In some embodiments, an apparatus for treating a gas in a conduit of a substrate processing system includes: a dielectric tube to be coupled to a conduit of a substrate processing system to allow a flow of gases through the dielectric tube, wherein the dielectric tube has a conical sidewall; and an RF coil wound about an outer surface of the conical sidewall of the dielectric tube, the RF coil having a first end to provide an RF input to the RF coil, the first end of the RF coil disposed proximate a first end of the dielectric tube and a second end disposed proximate a second end of the dielectric tube. In some embodiments, the RF coil is hollow and includes coolant fittings to couple the hollow RF coil to a coolant supply. |
| US09378923B2 |
Three-dimensional mapping using scanning electron microscope images
A method includes irradiating a surface of a sample, which is made-up of multiple types of materials, with a beam of primary electrons. Emitted electrons emitted from the irradiated sample are detected using multiple detectors that are positioned at respective different positions relative to the sample, so as to produce respective detector outputs. Calibration factors are computed to compensate for variations in emitted electron yield among the types of the materials, by identifying, for each material type, one or more horizontal regions on the surface that are made-up of the material type, and computing a calibration factor for the material type based on at least one of the detector outputs at the identified horizontal regions. The calibration factors are applied to the detector outputs. A three-dimensional topographical model of the surface is calculated based on the detector outputs to which the calibration factors are applied. |
| US09378917B2 |
Chip-type fuse
A terminal-integrated fuse (2) includes two planar members (10), (10) serving as terminals for mounting on a substrate. The two planar members (10), (10) are spaced on a same horizontal plane. A fuse body (4) is located on a horizontal plane at a level different from the level of the said horizontal plane and between the planar members (10), (10). The fuse body (4) is formed integral with the planar members (10), (10). A casing (14) has side walls (18), (20) and end walls (22), (24) disposed around an opening. The fuse body (4) is positioned in the casing (14), and the two planar members (10, (10) are in contact with the end walls (22), (24), respectively. An arc suppressing material portion (26) is provided in the casing (14) in such a manner the fuse body (4) is embedded therein. |
| US09378916B2 |
Heater apparatus, circuit interrupter, and related method
A heater apparatus is structured for use in a circuit interrupter having a thermal trip and includes a conductive device having a terminal and a heater that are co-formed with one another. The terminal includes a base and a support. The conductive device is formed from an individual metallic plate that is bent to form a number of plate elements. The base includes at least one plate element, and the heater includes at least another plate element, with the base and the heater being co-formed. A compression element is threadably receivable on the terminal and is structured to compressively retain an electrical conductor between the compression element and the base. |
| US09378911B2 |
Fuse and fuse attachment structure
A fuse includes: a conductive fuse element having a pair of connection terminals formed by bending two ends of a conductive wire rod in such a manner that the ends extend parallel with each other, and a meltable portion provided between the pair of connection terminals and formed to have a smaller cross-sectional area than the remainder of the fuse element; and an insulative shape retaining member fixed to the fuse element and retaining the shape of the fuse element. |
| US09378910B2 |
Thermal cut-off device
A thermal cut-off device can include a case, a first electrically conductive lead disposed at a first end of the case, a thermally responsive pellet housed within the case, a second electrically conductive lead disposed at a second end of the case and having a distal end including a contact surface, an electrically conductive contact disposed between the pellet and the second lead, a first biasing member disposed between the pellet and the contact, and a second biasing member disposed between the contact and the second end of the case. |
| US09378907B2 |
Liquid MEMS component responsive to pressure
A liquid micro-electro-mechanical system (MEMS) component includes a board, a channel frame, a flexible channel side, a liquid droplet, and one or more conductive elements. The channel frame is within the board and mates with the flexible channel side to form a channel within the board. The liquid droplet is contained within the channel. When a pressure is applied to the flexible side, the shape of the liquid droplet is changed with respect to the one or more conductive elements thereby changing an operational characteristic of the liquid MEMS component. |
| US09378904B2 |
Circuit breaker and handle locking device thereof
Disclosed is a handle locking device, including a first frame, a first snap hook and a second frame. A second snap hook is provided on the first frame; the first snap hook is rotatably mounted on the first frame; the second frame is rotatably mounted on the first frame; a protruding portion is formed on the second frame; and the protruding portion can push the first snap hook towards the first frame. By having the first snap hook and second snap hook disposed asymmetrically on the first frame, accidental mounting of the “OFF” position of the handle locking device in the “ON” position of the circuit breaker during installation by an operator can be avoided. Moreover, since the protruding portion can push the first snap hook towards the first frame, forced deformation of the snap claw and second snap hook can be prevented. |
| US09378898B2 |
Linear-hyperbranched polymers as performance additives for solid electrolytic capacitors
Provided herein is an improved capacitor and a method for forming an improved capacitor. The method includes providing an anode and forming a dielectric on the anode. A linear-hyperbranched polymer is formed and a conductive polymer dispersion is prepared comprising at least one conducting polymer, one polyanion and the linear-hyperbranched polymer. A layer of the conductive polymer dispersion if formed wherein said dielectric is between the anode and the layer. |
| US09378896B2 |
Solid electrolytic capacitor and method for manufacturing the same
A solid electrolytic capacitor includes a porous sintered body made of a valve metal, a dielectric layer on the porous sintered body, a solid electrolyte layer on the dielectric layer, and a cathode layer on the solid electrolyte layer. The solid electrolyte layer includes an inner electrode layer covering the dielectric layer inside the porous sintered body and an outer electrode layer covering the inner electrode layer outside the porous sintered body. The outer electrode layer includes a solid particle containing layer formed by applying a dispersion material liquid containing a conductive polymer dispersion material, solid particles and a solvent to the inner electrode layer and then removing the solvent. |
| US09378890B2 |
Ceramic capacitor having a small variation in capacity
When a voltage two times a rated voltage is applied between a first external electrode and a second external electrode of a ceramic capacitor, the electric field intensity generated at portion connected between a first internal electrode and an end of a portion of a second external electrode at a side of a first side surface by a shortest distance FS is about 0.34 kV/mm or less. |
| US09378888B2 |
Power transfer system
A power-transmission-unit-side resonant circuit includes a resonant capacitor connected in series with a power transmission coil and a power-reception-unit-side resonant circuit including a resonant capacitor connected in series with a power reception coil resonate with each other to cause sympathetic vibration. This allows power to be transferred using two kinds of coupling via the magnetic field and the electric field between the power transmission coil and the power reception coil. Also, operation is performed at a switching frequency that is higher than a specific resonant frequency of the entire multi-resonant circuit, such that a ZVS operation is performed. As a result, a switching loss is reduced by a large amount and a highly efficient operation is performed thus enabling a power transfer system with a reduced size and an increased power conversion efficiency to be provided. |
| US09378887B2 |
Wireless power interface and device
A wireless power interface includes a plurality of coils and a control module. At least two of the plurality of coils has a different orientation with respect to at least two axes of a multi-dimensional axis system. The control module is configured to enable at least one of the plurality of coils based on electro-magnetic coupling by at least one of the plurality of coils with a coil of a wireless power device. |
| US09378886B2 |
Electronic power transformer
A multi-phase electronic power transformer includes a set of primary windings, wherein each primary winding is configured to couple with an input voltage. The transformer includes a pair of primary switching devices that includes a first primary switching device coupled to a first end of each primary winding and a second primary switching device coupled to a second end of each primary winding distinct from the first end of each primary winding. The transformer includes a set of secondary windings, wherein each secondary winding is configured to inductively couple with a respective primary winding and to output a voltage. The transformer includes a pair of secondary switching devices that includes a first secondary switching device coupled to a first end of each secondary winding and a second secondary switching device coupled to a second end of each secondary winding distinct from the first end of the each secondary winding. |
| US09378885B2 |
Flat coil windings, and inductive devices and electronics assemblies that utilize flat coil windings
A low cost, reduced form factor, high performance electronic device for use in electronic circuits and methods. In one exemplary embodiment, the device includes a unitary header assembly construction that ensures device coplanarity and also includes vertically oriented terminal pins. The device utilizes preconfigured flat coil windings that are disposed directly within a planar core. The flat coil windings further include features that are configured to mate with the header assembly terminal pins which substantially simplify the manufacturing process. Methods for manufacturing the device are also disclosed. |
| US09378882B2 |
Method of fabricating an electronic circuit
Circuits and methods of fabricating circuits are disclosed herein. A method of fabricating an electronic circuit includes placing an electronic component on a substrate. A ferromagnetic material is mixed into a mold compound to produce a mixed mold compound having an increased permeability over the mold compound. The mixed mold compound is applied to the substrate by way of a transfer mold process, wherein the mixed mold compound encapsulates the electronic component. |
| US09378880B2 |
Magnetic-core polymer-shell nanocomposites with tunable magneto-optical and/or optical properties
Methods are disclosed for synthesizing nanocomposite materials including ferromagnetic nanoparticles with polymer shells formed by controlled surface polymerization. The polymer shells prevent the nanoparticles from forming agglomerates and preserve the size dispersion of the nanoparticles. The nanocomposite particles can be further networked in suitable polymer hosts to tune mechanical, optical, and thermal properties of the final composite polymer system. An exemplary method includes forming a polymer shell on a nanoparticle surface by adding molecules of at least one monomer and optionally of at least one tethering agent to the nanoparticles, and then exposing to electromagnetic radiation at a wavelength selected to induce bonding between the nanoparticle and the molecules, to form a polymer shell bonded to the particle and optionally to a polymer host matrix. The nanocomposite materials can be used in various magneto-optic applications. |
| US09378875B2 |
Ferromagnetic nano metal powder
The present invention related to ferromagnetic nano-metal powders and more particularly, to ferromagnetic nano-metal powders for increasing packing density by decreasing the porosity between micro-sized soft magnetic metal powders. According to an embodiment of the present invention, the ferromagnetic nano-metal powder allows high packing density and high magnetic property at a high frequency to fill the pores inevitably generated during the manufacturing process of an inductor using the soft magnetic metal powders. |
| US09378874B2 |
Ceramic electronic component
A ceramic electronic component includes a ceramic base, first and second internal electrodes, and first and second external electrodes. The first external electrode is disposed at a first end portion of a first major surface in the longitudinal direction. The second external electrode is disposed at a second end portion of the first major surface in the longitudinal direction. A portion of each of the first and second external electrodes is opposed in the thickness direction to a region where the first and second internal electrodes are opposed to each other in the thickness direction. A condition ( 1/10)t0≦t1 ≦(⅖)t0 is satisfied, where to is the thickness of each of the first and second external electrodes and t1 is the thickness of a portion in which each of the first and second external electrodes is embedded in the first major surface. |
| US09378865B2 |
High strength tether for transmitting power and communications signals
An electro-optical-mechanical tether to transmit both optical signals and electricity to and from airborne and other movable devices from a base structure, in which the tether includes a mechanical strengthening core covered by a first intermediate compressive layer which is helically wrapped by a plurality of electrical and fiber optic conductors, which constitute an second intermediate layer of the tether, and a outer protective layer. |
| US09378861B2 |
Nanoparticle composition and methods of making the same
A method of fabricating copper nanoparticles includes heating a copper salt solution that includes a copper salt, an N,N′-dialkylethylenediamine, and a C6-C18 alkylamine in an organic solvent to a temperature between about 30° C. to about 50° C.; heating a reducing agent solution that includes a reducing agent, an N,N′-dialkylethylenediamine, and a C6-C18 alkylamine in an organic solvent to a temperature between about 30° C. to about 50° C.; and adding the heated copper salt solution to the heated reducing agent solution, thereby producing copper nanoparticles. A composition includes copper nanoparticles, a C6-C18 alkylamine and an N,N′-dialkylethylenediamine ligand. Such copper nanoparticles in this composition have a fusion temperature between about 100° C. to about 200° C. A surfactant system for the stabilizing copper nanoparticles includes an N,N′-dialkylethylenediamine and a C6-C18 alkylamine. |
| US09378859B2 |
Polymer compositions, polymer films, polymer gels, polymer foams, and electronic devices containing such films, gels and foams
A polymer film, polymer gel, and polymer foam each contain an electrically conductive polymer and an ionic liquid and are each useful as a component of an electronic device. |
| US09378858B2 |
Repair apparatus
There is provided a repair apparatus including a gas field ion source which includes an ion generation section including a sharpened tip, a cooling unit which cools the tip, an ion beam column which forms a focused ion beam by focusing ions of a gas generated in the gas field ion source, a sample stage which moves while a sample to be irradiated with the focused ion beam is placed thereon, a sample chamber which accommodates at least the sample stage therein, and a control unit which repairs a mask or a mold for nano-imprint lithography, which is the sample, with the focused ion beam formed by the ion beam column. The gas field ion source generates nitrogen ions as the ions, and the tip is constituted by an iridium single crystal capable of generating the ions. |
| US09378857B2 |
Lamp systems and methods for generating ultraviolet light
Apparatus for generating ultraviolet light and methods of operating an ultraviolet light source. The apparatus may include a microwave chamber (16) enclosing an interior space, a light source (10) with a lamp head (28) coupled to the microwave chamber (16), an ultraviolet (UV) transmissive member (88) positioned above the lamp face (32) and below the interior space to define a plenum (116) therebetween, and an exhaust system (100) coupled in fluid communication with the plenum. The lamp head (28) has a lamp face (32) through which ultraviolet light (34) and cooling air (30) are emitted. The UV transmissive member (88) is configured to transmit the ultraviolet light (34) into the interior space and to divert the cooling air (30) from the interior space. The exhaust system (100) configured to exhaust the cooling air (30) from the plenum (116). |
| US09378851B2 |
Nuclear fuel
This invention relates to a method of preparing nuclear fuel including the step of depositing at least two adjacent series of layers (16, 18) around a kernel (12) of fissile material, each series comprising a layer of pyrolytic carbon (16) contiguous with a layer of silicon carbide (18) and each layer (16, 18) having a thickness of at most (10) micrometers, such that alternate layers of (16, 18) of pyrolytic carbon and silicon carbide are deposited around the kernel (12). The invention extends to a nuclear fuel element (10). |
| US09378850B2 |
Method for operating a nuclear reactor and use of a specific fuel rod cladding alloy in order to reduce damage caused by pellet/cladding interaction
A method for operating a nuclear reactor in order to produce electricity, such that the reactor is controlled so that, during a transient power occurrence for at least one of: a linear power density of the nuclear fuel rod remains lower than a limit linear power density, the limit linear power density being greater than 430 W/cm, and a variation of linear power density of the nuclear fuel rod remains lower than a limit variation, the limit variation being greater than 180 W/cm. |
| US09378846B2 |
Non-mounted storage test device based on FPGA
A non-mounted storage test device based on FPGA includes a processor unit for performing enumeration and configuration for device, creating a scenario for test and performing test; a device driver unit for managing storage device; a data engine unit for generating pattern data for test and performing test; a system memory interface unit for receiving data for test and storing test result; a monitoring unit for monitoring packet; a DMA driver/address translation unit for performing DMA operation and transmitting Memory Read Request to Root Complex; a message input/output unit for transmitting to the data engine unit and the device driver unit; a switch unit for constituting DUT unit; a storage-in DUT unit as device under test which is storage for direct interface to PCIe including HBA; and a memory unit for storing data for test and record generated between tasks. |
| US09378843B1 |
Collaborative analog-to-digital and time-to-delay conversion based on signal prediction
Methods and apparatuses are described for performing adaptive analog-to-digital conversion and time-to-delay conversion by using signal prediction to adjust reference voltages of adjustable comparators. |
| US09378840B2 |
Systems and methods for sub-zero threshold characterization in a memory cell
Systems and methods relating generally to data processing, and more particularly to systems and methods for characterizing a solid state memory. In one embodiment, the systems and methods may include programming a first cell of a solid state memory device to a negative voltage, programming a second cell of the solid state memory device to a positive voltage, wherein the second cell is adjacent to the first cell, calculating a voltage shift on the negative voltage programmed to the first cell, characterizing a shifted voltage level on the first cell as an interim voltage, and subtracting the voltage shift from the interim voltage to yield an actual voltage on the first cell. |
| US09378838B2 |
Mixed voltage non-volatile memory integrated circuit with power saving
An integrated circuit die has a first die pad for receiving a first voltage and a second die pad for receiving a second voltage. The second voltage is less than the first voltage and is generated by a voltage regulator that receives the first voltage. A first circuit which is operable at the first voltage is in the integrated circuit die. A second circuit which is operable at the second voltage is in the integrated circuit die and is connected to the second die pad. The voltage regulator is enabled by a controller. |
| US09378836B1 |
Sensing circuit for a non-volatile memory cell having two complementary memory transistors
Voltage is increased on a wordline signal. The wordline signal is applied to a programmed FET and an unprogrammed FET of a memory cell. The programmed FET has a higher threshold voltage than the unprogrammed FET. The programmed FET is connected to a first bitline and the unprogrammed FET is connected to a second bitline. It is determined that the second bitline has reached a threshold voltage. In response to determining the second bitline has reached the threshold voltage, the first bitline is pulled towards ground. A signal is output based on a low voltage of the first bitline and a high voltage of the second bitline. |
| US09378834B2 |
Bitline regulator for high speed flash memory system
A bitline regulator for use in a high speed flash memory system is disclosed. The bitline regulator is responsive to a set of trim bits that are generated by comparing the bias voltage of a bitline to a reference voltage. |
| US09378827B2 |
Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells. |
| US09378825B2 |
Buffering systems for accessing multiple layers of memory in integrated circuits
Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles. |
| US09378822B2 |
Method for programming selected memory cells in nonvolatile memory device and nonvolatile memory device thereof
A method for programming memory cells of a selected word line has steps of: providing a first word line programming signal being at plurality of voltage levels in different programming slots of a current programming operation to the memory cells of the selected word line, wherein the first word line programming signal is a ramping voltage signal; and providing a second line programming signal being at plurality of voltage levels in different programming slots of a next programming operation to the memory cells of the selected word line, wherein the second word line programming signal is another one ramping voltage signal; wherein the highest voltage levels of the first and second word line programming signals are identical to each other, and a number of the voltage levels of the first word line programming signal is larger than that of the second word line programming signal. |
| US09378815B2 |
Resistive memory device capable of increasing sensing margin by controlling interface states of cell transistors
A resistive memory device includes a memory cell array having a plurality of memory cells therein, which operate in response to word line driving and column selecting signals. Each of memory cells includes a resistive device and a cell transistor connected in series. An I/O sense amplifier senses and amplifies data output from the memory cell array to thereby generate output data, and also generate program current based on input data and provide the program current to the memory cell array. The resistive memory device is also configured to read output data from the I/O sense amplifier and adjust interface states of the cell transistors based on a voltage level of the output data during a test mode. |
| US09378809B1 |
Relaxing verification conditions in memory programming and erasure operations
A method for data storage includes setting a plurality of memory cells to hold respective target analog values, by applying to the memory cells a sequence of iterations, each iteration includes attempting to set the target analog values and then verifying whether the target analog values have been reached in accordance with a verification condition. After applying a predefined number of the iterations, the verification condition is relaxed and a condition of whether the target analog values have been reached in accordance with the relaxed verification condition is verified. |
| US09378806B2 |
Boosting voltage level
A circuit comprises a driver, a first capacitive device, and a second capacitive device. The driver has an input node, an output node, and a driver supply voltage node. The first capacitive device has a first terminal and a second terminal. The second capacitive device has a first terminal and a second terminal. The first terminal of the first capacitive device is configured to receive a first signal. The second terminal of the first capacitive device is coupled with the driver supply voltage node. The output of the driver is coupled with a first end of the second capacitive device. |
| US09378801B2 |
Semiconductor memory device
A semiconductor memory device includes a plurality of banks; a plurality of word lines; an advanced refresh operation mode where two or more word lines are selected in parallel in each bank; a pulse generation unit suitable for generating a single bank refresh pulse that toggles for a given time in response to a single bank refresh command of a single bank refresh operation mode; and an address generation unit suitable for generating an advanced single bank address for selecting at least two word lines in one of the banks in response to the single bank refresh pulse and an input address in an entry section of the advanced refresh operation mode. |
| US09378799B2 |
Semiconductor device having a memory and calibration circuit that adjusts output buffer impedance dependent upon auto-refresh commands
A semiconductor device having a circuit that selectively adjusts an impedance of an output buffer. A calibration operation can be performed automatically without issuing a calibration command from a controller. Because a calibration operation to a memory is performed in response to an auto refresh command having been issued for a predetermined number of times, a periodic calibration operation can be secured, and a read operation or a write operation is not requested from a controller during a calibration operation. A start-up circuit activates the calibration circuit when a refresh counter indicates a predetermined value, and prohibits a refresh operation in response to the auto refresh command when the calibration circuit is activated. A temperature detecting circuit may be used to change the frequency of performing a calibration operation. |
| US09378797B2 |
Provide a memory device capable of increasing performance by performing a write operation using stable multi voltages that are applied to a word line
A voltage generator comprises a reference voltage providing unit, a comparison voltage providing unit and a comparison unit. The reference voltage providing unit comprises a reference element and a current source series-connected between a power supply voltage and a ground voltage, and outputs a reference voltage through a reference voltage node, which couples the reference element to the current source. The comparison voltage providing unit comprises a magnetic tunnel junction unit coupled between the power supply voltage and a comparison voltage node, and a transistor switch unit coupled between the ground voltage and the comparison voltage node. The comparison unit provides a write voltage to the transistor switch unit by comparing the reference voltage and the comparison voltage. The voltage generator according to example embodiments may increase the performance of the memory device by performing the write operation using stable multi voltages that are applied to a word line. |
| US09378796B2 |
Method for writing to a magnetic tunnel junction device
A method of applying a write current to a magnetic tunnel junction device minimizes sub-threshold leakage. NMOS- and PMOS-follower circuits are used in applying the write current, and bias signals for the follower circuits are isolated from global bias signals before the write current is applied. |
| US09378794B2 |
Storage element and memory
A storage element includes a magnetization fixed layer, and a magnetization free layer. The magnetization fixed layer includes a plurality of ferromagnetic layers laminated together with a coupling layer formed between each pair of adjacent ferromagnetic layers. The magnetization directions of the ferromagnetic layers are inclined with respect to a magnetization direction of the magnetization fixed layer. |
| US09378793B2 |
Integrated MRAM module
Systems and methods for integrated magnetoresistive random access memory (MRAM) modules. An integrated circuit includes a processor without a last level cache integrated on a first chip a MRAM module comprising a MRAM last level cache and a MRAM main memory integrated on a second chip, wherein the MRAM module is a unified structure fabricated as monolithic package or a plurality of packages. The second package further includes memory controller logic. A simplified interface structure is configured to couple the first and the second package. The MRAM module is designed for high speed, high data retention, aggressive prefetching between the MRAM last level cache and the MRAM main memory, improved page handling, and improved seal ability. |