| Document | Document Title |
|---|---|
| US09344365B1 |
Mesh network addressing
In embodiments of mesh network addressing, a router receives a packet to deliver to a network destination and determines if the network destination is within the mesh network. The network destination enables the router to discover a Routing Locator (RLOC) that is associated with the network destination and provides a routable network address for the network destination. The router can forward the received packet using the routable network address from the discovered Routing Locator. The router can discover the RLOC by searching a cache of RLOCs stored in the router, or by sending an address query. |
| US09344357B2 |
Label-switched path aggregation
Techniques are disclosed for aggregating label-switched paths (LPSs). One method for aggregating LSPs may include a first node comparing forwarding equivalence classes (FECs) associated with respective label-switched paths (LSPs). The first node identifies FECs that differ by a given number of bits, such as one or two bits based on the comparison. The first node generates an aggregate FEC that masks out the differing bits, thereby reducing the number of LSPs. The first node transmits the aggregate FEC to an ingress node. |
| US09344354B2 |
Redirecting telephone call to packet-switched data call via voicemail
In embodiments of the disclosed technology, devices and methods for redirecting a telephone call from a public-switched telephone to a packet-switched data network. The phone call is initially received via the public-switched telephone network having a dialed number associated with a hand-held wireless device of a called party. Upon initialization of the phone call, a route is determined from the telecommunications switch to the hand-held wireless device of the called party via a packet-switched network. The bandwidth of the packet-switched network is then detected to determine the ability of the network to handle the call. If the packet-switched network is determined to be capable of handling the call, the call is forwarded over the packet-switched data, thereby reducing or eliminating charges for wireless minutes. |
| US09344348B2 |
Managing the quality of service levels (QoS) of network traffic
A network element and method for marking traffic in a packet-switched data network which comprises a distributed hierarchical naming system and the network element. The network element comprises a marking rule store for storing marking rules, in which each marking rule is indicative of a quality of service level allocated to traffic on a connection impinging on the network element. The network element derives from the distributed hierarchical naming system quality of service level data for a connection, stores in the marking rule store a marking rule for the connection based on the retrieved quality of service level data and marks traffic on the connection in accordance with the marking rule. |
| US09344347B2 |
Delay time measuring apparatus, computer readable record medium on which delay time measuring program is recorded, and delay time measuring method
In a delay time measuring apparatus a sequence number, data length, and receiving time of a data packet transmitted from a source unit to a destination unit are stored in a storage section. In addition, an ACK number and receiving time of an ACK packet returned from the destination unit to the source unit are stored in the storage section. After that, a calculation section obtains an ACK packet an ACK number of which is equal to a value obtained by adding data length of a second data packet of two successive data packets transmitted without waiting for the ACK packet to a sequence number of the second data packet of the two successive data packets from the storage section. Then the calculation section calculates round trip time from receiving time of the second data packet of the two successive data packets and receiving time of the ACK packet obtained. |
| US09344343B2 |
Methods and apparatus to determine impressions using distributed demographic information
An example method to monitor media exposure involves receiving, at a first internet domain, a first request from a client computer, the first request indicative of access to the media at the client computer. The example method also involves determining if the client computer is known. If the client computer is not known, a response is sent from the first internet domain to the client computer, the response to instruct the client computer to send a second request to a second internet domain, the second request to be indicative of access to the media at the client computer. If the client computer is known, an impression of the media is logged. |
| US09344335B2 |
Network communication and cost awareness
Network communication and cost awareness techniques are described. In one or more implementations, functionality is exposed through one or more application programming interfaces (APIs) that is accessible to a plurality of applications of the computing device to perform network communication. Data is returned to one or more of the plurality of applications regarding a cost network used to perform the network communication. |
| US09344333B2 |
Automating network build-out in self building networks
Various exemplary embodiments relate to a method performed by a network node device for provisioning the device on a network, the method including detecting one or more ports, sending discovery messages from one or more of the discovered ports, receiving an offer message including network information, storing the received network information, receiving a promotion message, and listening for discovery messages. In some embodiments, the method further includes receiving one or more messages including configuration information. In various embodiments, the configuration information includes one or more of node interface parameters, management parameters, OAM parameters, and MPLS parameters. |
| US09344331B2 |
Implementation of network device components in network devices
A network device includes an execution engine having an implementation of a network device component to process data received by the network device, and a compiler to dynamically generate the implementation of the network device component through compilation of a general representation using network device data for compiler optimization. |
| US09344329B2 |
Intelligent subscriber notification
A network device may receive a subscriber's activity data for a network resource associated with the subscriber. The subscriber's activity data may be analyzed and a tailored notification instruction may be provided for alerting the subscriber. |
| US09344328B1 |
Fast port failover in a network switch
A first port of a network device having a plurality of ports. The first port includes a memory configured to store an identifier of a backup port associated with the first port a redirect circuit, and a loopback circuit. The redirect circuit is configured to, in response to a failure of the first port, redirect first frames of data, to be received from the first port by the network device, to the backup port associated with the first port. The loopback circuit is configured to, in response to the failure of the first port, redirect second frames of data, received by the first port from the network device, to the backup port associated with the first port. |
| US09344324B2 |
Method and apparatus for setting radio link of terminal in which multiple carriers are integrated in mobile communication system
A method and apparatus for configuring a radio link of a terminal communicating via aggregated carriers including a primary cell and a secondary cell are provided. The method includes detecting a Radio Link Failure (RLF) for the secondary cell, deactivating the secondary cell, and reporting at least one of a measurement result of the secondary cell and a measurement result of neighboring cell of the secondary cell to a base station. The apparatus includes a transceiver for communicating with a base station, and a controller configured to detect a RLF for the secondary cell, to deactivate the secondary cell, and to report at least one of a measurement result of the secondary cell and a measurement result of neighboring cell of the secondary cell to the base station. |
| US09344320B1 |
Return path trace
A reverse network tracing mechanism is described. In an embodiment, a network information request is received that is addressed to a predetermined destination. It is determined that the network information request has an expired timer and a message is returned indicating that a return network path routing procedure has been initiated. After determining that the network information request has an unexpired timer, contents of the network information request are modified to enable identification of at least a portion of the return path from the predetermined destination to a source address of the network information request. |
| US09344319B1 |
Edge-QAM and M-CMTS core timing lock
Systems and methods can provide for Edge-QAM and M-CMTS timing lock. In some implementations, an Edge-QAM can provide for timing lock with an M-CMTS core by observing DOCSIS-SYNC MAC messages. In other implementations, an Edge-QAM can provide for timing lock with an M-CMTS core by observing per-modem ranging MAC messages. In other implementations, an EQAM can provide for timing lock with an M-CMTS core by performing timing lock check and adjustment. Using existing protocol messages defined in the M-CMTS architecture, the EQAM can intercept, snoop, and extract timing values from the M-CMTS core thereby reducing or even eliminating the need for a DTI server. |
| US09344317B2 |
OFDM signal modulation-demodulation method, device and system based on compressed sensing
An OFDM signal modulation method based on compressed sensing is provided, the method includes: acquiring a demodulation parameter of a receiver, where the demodulation parameter includes Tnyq of a periodic square signal of the receiver in sampling, Tnyq is a length of a minimum timeslot during which the periodic square signal maintains a high level or a low level; performing an OFDM modulation on an inputted information symbol to generate an OFDM baseband signal, and controlling a sampling interval TsampleOFDM=Ts/k of the OFDM baseband signal to be integral multiple of Tnyq, where Ts is a duration of valid data in the OFDM baseband signal, and k is the number of sub-carriers in the OFDM baseband signal; and up-converting the OFDM baseband signal and transmitting the processed signal to the receiver. Also provided are a demodulation method, device and system. |
| US09344315B2 |
Transmitting system and receiving system, and transmitting method and receiving method
A transmitting system, a receiving system, a transmitting method and a receiving method capable of implementing communications with multiple rates are described. The transmitting system comprises: a transmitting-side selection apparatus for selectively inputting input bit data to one of a first constellation mapping modulation apparatus and a second constellation mapping modulation apparatus based on a rate to be transmitted; the first constellation mapping modulation apparatus for performing a first constellation mapping modulation on the signal input thereto based on a selection made by the transmitting-side selection apparatus, so as to obtain a constellation-mapped signal; the second constellation mapping modulation apparatus for performing a second constellation mapping modulation on the signal input thereto based on the selection made by the transmitting-side selection apparatus, so as to obtain a constellation-mapped signal; and an OFDM modulation apparatus for performing an OFDM modulation on the constellation-mapped signal to obtain an OFDM-modulated signal for transmission. |
| US09344314B2 |
Computer generated sequences for downlink and uplink signals in wireless communication systems
The present disclosure provides a base station transmitter, a user equipment transmitter and methods of operating the base station and user equipment transmitters. In one embodiment, the base station transmitter is for use with a cellular communication system and includes a synchronization unit configured to provide a randomly-generated constant amplitude zero autocorrelation (random-CAZAC) sequence corresponding to a downlink synchronization signal. Additionally, the base station transmitter also includes a transmit unit configured to transmit the downlink synchronization signal using the random-CAZAC sequence. In another embodiment, the user equipment transmitter is for use with a cellular communication system and includes a reference signal unit configured to provide a random-CAZAC sequence for an uplink reference signal corresponding to a one resource block allocation of the user equipment. The user equipment transmitter also includes a transmit unit configured to transmit the uplink reference signal using the random-CAZAC sequence. |
| US09344312B2 |
Method and apparatus for multiple frame transmission for supporting MU-MIMO
A method of transmitting multiple frames in a wireless local area network (WLAN) system supporting multi user-multiple input multiple output (MU-MIMO) is provided. The method comprises transmitting a first frame and a second frame consecutively to a first station (STA) and transmitting a third frame and a fourth frame consecutively to a second STA, wherein a transmission start time of the first frame and a transmission start time of the third frame are aligned to each other, and wherein a transmission start time of the second frame and a transmission start time of the fourth frame are aligned to each other. |
| US09344311B2 |
Wireless transmission
A wireless communication device (400) is arranged to transmit a transmission signal in an assigned channel bandwidth. The wireless communication device (400) comprises: a local oscillator (460) arranged to generate a local oscillator signal at a local oscillator frequency and a modulator (434) arranged for converting in-phase and quadrature-phase components of a modulation signal at a modulation frequency to a radio frequency by mixing the in-phase and quadrature-phase components with the local oscillator signal. The local oscillator frequency is arranged to place a third order intermodulation product having a frequency equal to the local oscillator frequency minus three times the modulation frequency within the assigned channel bandwidth. |
| US09344309B2 |
Decision circuit, receiver device, and processor
A decision circuit includes: a first decision block to distinguish a first bit of bits using an amplitude of an analog signal as a discrimination point, the analog signal being an amplitude shift keyed signal; a superposition block to acquire an absolute value of a difference of the analog signal in respect to an amplitude center value of the analog signal by superposing divided analog signals; an inversion block to control inverting of the signal based on a first distinction result of the first decision block; a second decision block to distinguish a second bit of the bits based on an amplitude of an output signal from the inversion block and the discrimination point; and an output buffer to output the first distinction result and a second distinction result of the second decision block in synchronization with a clock. |
| US09344307B2 |
Method and apparatus for sub-carrier frequency control
The invention pertains to methods, apparatus, and systems for controlling the sub-carrier frequencies in an optical frequency division multiplex communication system by using a metric available from the sub-carrier modem's digital receive block as an indicator of cross-talk between sub-carriers and adjusting the sub-carrier frequency separation as a function of that metric. |
| US09344302B2 |
Loopback technique for IQ imbalance estimation for calibration in OFDM systems
A transceiver for orthogonal frequency division multiplex communication has a transmitter module (1) and a receiver module (2). The transmitter (1) has an l-path (3) and a Q-path (4) to receive signals on a number of subcarriers provided by a signal generator (9). The receiver module (2) has a receiver l-path (7) and a receiver Q-path (8) to deliver signals to a processor (15). IQ imbalance is calculated for each of the transmitter and receiver by the signal generator sending a sample signal (Xl(k), XQ(k)) over a one of the transmitter paths. The signal is then applied to one or each of the inputs to the receiver paths (7,8) to generate receiver output signals Yl(k), YQ(k), RQ(k). The processor (15) is responsive to the output signals to calculate the transmitter and receiver IQ imbalance for that subcarrier. A calibrator (19) and compensator (20) are responsive to the calculated IQ imbalance to correct or compensate each subcarrier of the transceiver band. |
| US09344301B2 |
Acquisition device with multistage digital equalization
An acquisition device includes an analog to digital converter (ADC) composed of multiple interleaved ADCs (sub-ADCs), which receives an analog signal which is converted to digital form. The digitized signal is processed seriatim by a pre-(or trigger-) equalizer, an acquisition memory and a post-(or memory) equalizer. In a calibration mode, frequency responses of the respective sub-ADCs are determined and trigger coefficients are determined for application to the trigger equalizer to effect a preliminary equalization of the digitized signal sufficient to permit operation of the trigger processor in an acquisition mode. Memory coefficients are determined based on residual frequency responses of the sub-ADCs, for application to the memory equalizer. A trigger processor is responsive to the trigger equalizer to select a subset of samples of the digitized signal for loading to the acquisition memory. The trigger equalizer and a memory equalizer are configured for consecutive operation so that, in an acquisition mode, the memory equalizer receives as its input, a digitized signal from the ADC that has been pre-processed in the trigger equalizer, and the memory equalizer corrects only the residue of misalignments and frequency distortions that remain after the trigger equalizer operation. |
| US09344299B2 |
CSI-RS based channel estimating method in a wireless communication system and device for same
The present invention relates to a user equipment to perform an estimation operation in a wireless communication system. In more detail, the method includes: receiving configuration information of CSI-RSs (channel status information-reference signals) defined by a plurality of antenna ports from a base station; combining CSI-RSs defined by specific antenna ports among the plurality of antenna ports; and performing the measurement based on the combined CSI-RSs. Here, performing the measurement comprises measuring at least one of a RSRP (reference signal received power), a RSRQ (reference signal received quality) and a pathloss based on the combined CSI-RSs. |
| US09344297B2 |
Systems and methods for email response prediction
Techniques for predicting a user response to the e-mail content are described. According to various embodiments, member email interaction data associated with a particular member and email content data describing a particular email content item is accessed. The data is then encoded into one or more feature vectors and assembled to thereby generate an assembled feature vector. Thereafter, a prediction modeling process is performed, based on the assembled feature vector and a trained prediction model, to predict a likelihood of the particular member performing a particular user action on the particular email content item. |
| US09344295B2 |
Wireline communication system and method employing a military standard 1553 bus
A wireline communication system and method are provided that utilize a military standard 1553 bus to transmit both military standard 1553 communication signals and other communication signals, such as those transmitted in accordance with another communications protocol. A wireline communication system may include a military standard 1553 bus and a military standard 1553 node configured to communicate with military standard 1553 communication signals at a first predefined range of frequencies. The wireline communication system further includes a first interface node configured to communicate via the military standard 1553 bus with second communication signals having a second predefined range of frequencies, different than the first predefined range of frequencies. The second communication signals are transmitted along the military standard 1553 bus at less than a predetermined decibel level. The second predefined range of frequencies and the predetermined decibel level are selected to limit interference between the different signals. |
| US09344294B2 |
Device abstraction proxy
Described are systems and methods for implementing and operating a Device Abstraction Proxy (DAP). In one embodiment, the DAP includes a communications interface to connect the DAP to one or more access aggregation devices, each having a plurality of physical ports to provide Digital Subscriber Line (DSL) communication services to a plurality of remote DSL terminals via the plurality of physical ports. The DAP may further include a memory and processor to execute a virtual access aggregation device, in which a subset of the plurality of physical ports are allocated and linked to corresponding logical ports. The DAP may further include a global rule-set module to define operational constraints for the DSL communication services, and a management interface to allow at least one broadband access management system to manage the subset of physical ports allocated to the virtual access aggregation device subject to the operational constraints. |
| US09344287B2 |
Scalable transport system for multicast replication
Embodiments disclosed herein provide advantageous methods and systems that use multicast communications via unreliable datagrams sent on a protected traffic class. These methods and systems provide effectively reliable multicast delivery while avoiding the overhead associated with point-to-point protocols. Rather than an exponential scaling of point-to-point connections (with expensive setup and teardown of the connections), the traffic from one server is bounded by linear scaling of multicast groups. In addition, the multicast rendezvous disclosed herein creates an edge-managed flow control that accounts for the dynamic state of the storage servers in the cluster, without needing centralized control, management or maintenance of state. This traffic shaping avoids the loss of data due to congestion during sustained oversubscription. Other embodiments, aspects and features are also disclosed. |
| US09344282B2 |
Central and implicit certificate management
Facilitating management of digital certificates is addressed. More specifically, digital certificates as well as public and private keys can be stored in a centrally accessible location and dynamically acquired from the location as needed. Additionally, binding of digital certificates and associated keys can be implicit and determined as a function of a host name provided during protocol negotiation, for example. |
| US09344279B2 |
Mobile device-based keypad for enhanced security
An authentication channel is established between a mobile device and a transaction terminal that uses a keypad for access control. The terminal keypad is assumed to be untrusted, whereas the mobile device has a trusted interface that only the device user can access and use. The transaction terminal includes a short-range communication device, and a keypad interface application configured to communicate with an external keypad device in lieu of the transaction terminal's own keypad. The mobile device includes a mobile app. In response to detecting a user access request, a handshake protocol is performed between the keypad interface application in the transaction terminal and the keypad interface function in the mobile device. If the handshake protocol succeeds, the user is notified that the transaction terminal is trusted. The user then enters his or her password and/or PIN on the mobile device in lieu of direct entry via the terminal keypad. |
| US09344278B2 |
Secure data transfer using random ordering and random block sizing
Encrypted information is conventionally broken into blocks which are transmitted sequentially. Because the order and the size of such blocks can be easily determined, an eavesdropper can gain valuable information regarding the content of the communication. More specifically, if known types of information exist within a block, the encryption key may be determined allowing the content of other encrypted blocks to be obtained. Embodiments of a system, method and computer program product described herein can overcome this deficiency by securely transferring information through random ordering and random block sizing. An original data set to be transferred is divided into a plurality of blocks, where at least two blocks have different sizes. The blocks are encrypted and inserted into a sequence of data transfer slots. The blocks are then selected for transfer in random order by selecting a slot to transfer based on a generated random number. |
| US09344277B2 |
Mass serialization analytics
A method of determining whether a mass serialization engine is cryptographically secure is provided herein. The method includes performing (202) a specified number of mass serializations to generate a corresponding number of mass serialization sets. A size of the mass serialization sets is increased from a first portion size to a second portion size by the mass serialized engine. The method further includes determining (204) a corresponding number of collisions for each of the specified number of mass serializations. Additionally, the method includes comparing (206) the number of collisions to an expected number of collisions. Further, the method includes determining (208) whether the mass serialization engine is cryptographically secure based on the comparison. |
| US09344273B2 |
Cryptographic device for implementing S-box
Provided is a cryptographic device implementing an S-Box of an encryption algorithm using a many-to-one binary function. The cryptographic device includes: arrays of first logic gates including I first logic gates which each receive 2 bits of an input signal; 2N second logic gates which each receive corresponding J bits from among I bits output from the arrays of the first logic gates; and L third logic gates which each receive K bits from among 2N bits output from the second logic gates, wherein there is a many-to-one correspondence between the N bits of the input signal and the K bits input to each of the third logic gates, and wherein the N, I, J, K, and L are positive integers. Because a signal output from each array includes only one active bit, current is always consumed constantly to prevent internal data from leaking out to a hacker. |
| US09344268B1 |
Phase alignment architecture for ultra high-speed data path
A phase alignment architecture enhances the performance of communication systems. The architecture aligns a divided clock (e.g., in differential Inphase (I) and Quadrature (Q)) to a main clock, even at extremely high speeds, where skew variations of the divided clock are comparable to the main clock period. The improvement in phase alignment facilitates ultra high-speed communications. |
| US09344259B2 |
Control channel provisioning and signaling
There is provided a communication device and a base unit, and methods thereof, for determining control information. The communication device receives a control channel message associated with the communication device in a control region on a first carrier from a base unit. The communication device also determines a set of resources in a search space within the control region, attempts to decode the set of resources in the search space for the control channel message, and determines control information from the decoded control channel message. The base unit generates a control channel message comprising control information associated with the communication device, determines a set of resources in a search space within a control region, selects a subset of resources within the determined set of resources for transmitting the control channel message, and transmits the control channel message on the selected resources in the control region on a first carrier. |
| US09344255B2 |
Method and apparatus for mitigating interference in wireless communication system
A method for mitigating interference in a wireless communication system includes a first transmission point determining the number of subframes that need to be shifted at a second transmission point using information from the second transmission point for an ABS configuration, wherein the ABS configuration is for a UE belonging to a third transmission point. |
| US09344254B2 |
Two outer loop link adaptations for legacy user equipment
A base station determines first quality information indicative for a quality of a first part of subframes of a communication channel and a second quality information indicative for a quality of a second part of the subframes of the communication channel. Feedback information is received from a UE being indicative for the quality of the communication channel. A first compensation value is determined based on the first quality information and the feedback information, wherein the compensation value compensates a difference between the first quality information and the feedback information. A second compensation value is determined based on the second quality information and the feedback information, wherein the compensation value compensates a difference between the second quality information and the feedback information. The feedback information is adjusted based on the determined first and second compensation values. The communication channel is configured based on the adjusted feedback information. |
| US09344253B2 |
Radio communication apparatus and radio communication method
Provided is a radio communication device which can make Acknowledgement (ACK) reception quality and Negative Acknowledgement (NACK) reception quality to be equal to each other. The device includes: a scrambling unit (214) which multiplies a response signal after modulated, by a scrambling code “1” or “e−j(π/2)” so as to rotate a constellation for each of response signals on a cyclic shift axis; a spread unit (215) which performs a primary spread of the response signal by using a Zero Auto Correlation (ZAC) sequence set by a control unit (209); and a spread unit (218) which performs a secondary spread of the response signal after subjected to the primary spread, by using a block-wise spread code sequence set by the control unit (209). |
| US09344251B2 |
Method and apparatus of transmitting uplink signal
A method for transmitting an uplink signal by a communication apparatus in a wireless communication system is discussed. The method includes multiplexing control information with at least one of a plurality of data blocks to generate a bit sequence; and transmitting the uplink signal including the bit sequence. When the control information includes a first type of control data, the control information is multiplexed with all of the plurality of data blocks. When the control information includes a second type of control data, the control information is multiplexed only with a specific data block among the plurality of data blocks. The first type of control data includes acknowledgement/negative acknowledgement (ACK/NACK) information, and the second type of control data includes channel quality information. |
| US09344244B2 |
System and method of processing antenna configuration information
A base station (BS) encodes antenna configuration information of a neighboring cell of a first cell, and sends encoded information relating to the antenna configuration information of the neighboring cell to a user equipment (UE). The UE is capable of communicating with the BS in the first cell. The UE receives the encoded information; decodes the antenna configuration information of the neighboring cell from the encoded information; and performs determination of predetermined time-frequency resource according to the antenna configuration information of the neighboring cell. The predetermined time-frequency resource is used by a BS of the neighboring cell for transmitting pilot measurement information. |
| US09344242B2 |
Method and apparatus for transmitting uplink
A method, performed by a user equipment, is described for uplink transmission in a wireless communication system. A first time alignment (TA) to a first cell belonging to a first timing advance group (TAG) is performed. A second TA to a second cell belonging to a second TAG is performed. A determination is made as to whether to transmit or drop a sounding reference signal (SRS) on a subframe. The SRS is determined to be dropped based on whether the first and second TAGs are configured, whether at least one symbol of the subframe is used to transmit the SRS toward the second cell of the second TAG and also used to transmit a physical uplink shared channel (PUSCH) toward the first cell of the first TAG, and whether a total uplink transmission power exceeds a maximum value. |
| US09344241B2 |
Radio communication system, base station apparatus, mobile terminal apparatus, and interference measurement method
The present invention is designed to measure interference with high accuracy, without changing the density of CSI-RSs, in a future system that does not reply on CRSs. A base station apparatus (20) allocates CSI-RS to CSI resources that are defined for CSI-RS transmission, changes arbitrary resources in the CSI-RS resources in resource block units or in resource block group units, and determines and reports to a mobile terminal apparatus (10) the resources to be muted, and the mobile terminal apparatus (10) is configured to measure interference using the muted resources. |
| US09344240B2 |
256QAM signal transmission/reception method and apparatus for use in mobile communication system
A method and an apparatus for transmitting and receiving signals modulated with 256 Quadrature Amplitude Modulation (256QAM) for use in a mobile communication system are provided. The method includes receiving a first signal from a terminal, determining a modulation application criterion for data communication with the terminal based on the first signal, receiving a second signal including an index from the terminal, and determining a modulation scheme to be applied to at least one of the signals communicating with the terminal based on the modulation application criterion and the received index. |
| US09344239B2 |
Allocating orthogonal frequency-division multiple access (OFDMA) resources in ethernet passive optical network(PON) over coaxial (EPOC)
A method implemented in a Fiber Coaxial Unit (FCU) comprising receiving a plurality of Ethernet Passive Optical Network (EPON) report messages from a plurality of Coaxial Network Units (CNUs) across a coaxial network, receiving an EPON gate message comprising Time Quanta (TQ) information indicating an upstream transmission time grant for the FCU across the optical network, translating the TQ based upstream transmission time grants to OFDM resource block grants in a time domain and in a frequency domain across the coaxial network for each CNU based on the configurable constants, and transmitting an EPON over Coaxial (EPoC) gate message to each CNU, wherein each EPoC gate message comprises a CNU profile indicating the Orthogonal Frequency-Division Multiplexing (OFDM) resource block grants for the an associated CNU and a start time. |
| US09344237B2 |
WiFi remote displays
A wireless peripheral mode is provided by a host system that communicates to a WiFi infrastructure and, utilizing the same WiFi RF subsystem, also communicates to peripherals. The host system may employ additional RF channels for communicating with high bandwidth peripherals, such as display devices, where high levels of QoS may be managed locally. The host system may be a conventional desktop computer system, a notebook computer system, a multi-media access point, a cell phone, a game machine, a portable game machine, a Personal Digital Assistant (PDA), a smart phone or any other type of device that benefits from accessing both a WiFi infrastructure and local peripherals. |
| US09344230B2 |
Method for searching for enhanced PDCCH area
The present invention relates to a method for searching for an enhanced physical downlink control channel (E-PDCCH), and devices supporting same. The method for searching for an E-PDCCH in a wireless access system, in one embodiment of the present invention, comprises the steps of: blind decoding a control channel area and searching for a legacy PDCCH; obtaining allocation location information of the E-PDCCH using one or more of initiation location information, completion location information, and size information on the allocation area of the legacy PDCCH; and searching for the E-PDCCH using the allocation location information of the E-PDCCH, wherein the E-PDCCH being allocated to a data channel area is more desirable than being allocated to the control channel area. |
| US09344229B2 |
Method and device for allocating carriers in carrier aggregation system
A method for allocating a carrier in a carrier aggregation system is disclosed. The method includes a network side allocating a component carrier and identifier information of a user equipment to the user equipment, and notifying the user equipment of the allocated component carrier and the identifier information of the user equipment, and/or a corresponding relationship between the allocated downlink component carrier and the identifier information of the user equipment. A device for allocating a carrier in carrier aggregation system is disclosed. The device includes an allocation unit configured to allocate a component carrier and identifier information of a user equipment to the user equipment, and a notification unit configured to notify the user equipment of the allocated component carrier and the identifier information of the user equipment, and/or the corresponding relationship between the allocated downlink component carrier and the identifier information of the user equipment. |
| US09344226B2 |
Data packet transmission method
This transmission comprising a first transmission of a packet (52), comprising the steps consisting in: a first processing (54) of said packet (52) to obtain a first packet (56); and a coding (57, 59) of the first packet (56); wherein, when the first coded packet is received erroneous, the method comprises a second transmission of said packet, comprising: the steps implemented in the transmitter, consisting in: a second processing (84) of said packet (52) to obtain a second packet (86); and a coding (87, 89) of the second packet (86); and the steps implemented in the receiver, consisting in: a modification of the first and/or the second coded packets to obtain two packets in which the difference due to the first and second processings is compensated for: a combination (110) of both packets according to a HARQ procedure; and a decoding (112) of the combined packet. |
| US09344225B2 |
Distributed ARQ for wireless communication system
Systems and methods for providing distributed Automatic Repeat Request (ARQ) in a wireless communication system are described herein. In one embodiment, a relay station interconnects a base station of the wireless communication system and one or more mobile stations. A first ARQ process is performed for a first connection between the base station and the relay station. A separate second ARQ process is performed for a second connection between the relay station and a mobile station. In this manner, rather than having end-to-end ARQ between the base station and the mobile station, a distributed ARQ process is provided. |
| US09344220B2 |
Forward error correction scheme for high rate data exchange in a wireless system
A transmitter/receiver system for high data transfer in a wireless communication system includes a physical layer processor that comprises an FEC coder, a demultiplexer and a plurality of modem processors. The FEC coder applies error correction codes to the high data rate signal. Thereafter, the demultiplexer distributes portions of the coded high data rate signal to the modem processors. Each modem processor processes its respective portion of the coded signal for transmission in an independent channel. |
| US09344219B2 |
Increasing communication safety by preventing false packet acceptance in high-speed links
Methods, apparatus, and systems for preventing false packet acceptance in high-speed links. Under one aspect, correctable symbol errors are detected, and determination is made to whether a symbol error rate or ratio (SER) exceeds an SER threshold. In response to detection of such a condition, the link is disconnected or temporarily paused. The value for the SER threshold is determined using a statistical analysis of various link parameters to meet desired performance levels, such as a mean time to false packet acceptance (MTTFPA) of >approximately 15 billion years while providing a mean time to disconnect of >100 years. |
| US09344217B2 |
Devices and methods for reconstructing corrupted control channel bits
UEs are adapted to facilitate reconstruction of a segment of corrupted bits. According to one example, a UE can receive a control channel transmission such as a HS-SCCH transmission. The control channel transmission may include a plurality of information bits and a plurality of cyclic redundancy check (CRC) bits. The UE may further determine that a contiguous segment of the received information bits is corrupt. The UE may accordingly utilize the uncorrupted information bits and CRC bits to reconstruct the corrupt information bits. In some instances, the UE may utilize the uncorrupted bits to reconstruct the corrupt information bits using a new generator polynomial. In other instances, the UE may utilize the uncorrupted bits to reconstruct the corrupt information bits using the original generator polynomial. |
| US09344216B2 |
Error concealment method for wireless communications
The invention relates to a method of reconstructing pixel values of a video frame for concealing corrupted pixel values. The method comprising receiving, by a receiving unit, of a signal from a communication channel and delivering by the receiving unit of video packets comprising pixel values possibly corrupted with errors; associating confidence levels with pixel values comprised in the video packets as delivered by the receiving unit; and reconstructing pixel values usable for display from the received pixel values, wherein a reconstructed value for a given pixel is obtained from the received values of a set of pixels, including the given pixel, weighted by their associated confidence levels.The invention allows for better reconstruction of corrupted pixel values and reduces the perceived distortion when displaying the video frame. |
| US09344214B2 |
Optical wavelength path rearranging method, computer product, optical transmission managing apparatus, and optical transmission apparatus
An optical wavelength path rearranging method includes detecting time that elapses since a setting of optical wavelength paths in an optical wavelength division multiplexing network; and moving to a predetermined long-period optical wavelength range, an optical wavelength path that is among the optical wavelength paths and for which the detected elapsed time is long, where the optical wavelength path rearranging method is executed by a processor. |
| US09344212B2 |
Communication system, response notifying method and apparatus
To solve a problem that unless all of a plurality of AICH signature states are correctly decoded, the contents of reception results cannot be recognized and the error rate of signature decoding will be high. In this embodiment, a base station uses, out of a signature combination, the signature of at least one predetermined position to indicate information containing a preamble reception result and uses the signature of a position other than the predetermined position to indicate a transmission profile information number of an uplink channel for notification to a user equipment. Thus, the error rate related to reception results can be reduced as compared with the case where a single signature combination is used to notify all pieces of information. |
| US09344208B2 |
Systems and methods for packet based timing offset determination using timing adjustment information
Systems and methods for performing timing offset and or fractional frequency offset for the purpose of time and/or frequency synchronization are provided. Timing packets are exchanged between a master device and a slave device. In addition, timing adjustment information is received by the slave device. The slave device uses the timing adjustment information in conjunction with the transmit and receive times for the timing packets to estimate at timing offset and/or fractional frequency offset. |
| US09344207B2 |
Techniques for time transfer via signal encoding
Techniques for time transfer via signal encoding are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for time transfer via signal encoding comprising generating a time service ordered-set for inclusion in a physical coding sublayer frame of a physical layer device, generating time service data for inclusion in the physical coding sublayer frame of the physical layer device, and transmitting the physical coding sublayer frame. |
| US09344205B2 |
Methods and apparatus to count persons in a monitored environment
Methods and apparatus to count persons in a monitored environment are disclosed. An example apparatus to count the number of people in a monitored environment is described, which includes an image sensor to collect a plurality of pixels, a pseudorandom number generator to pseudorandomly select at least one of a row of the pixels or a column of the pixels, a reader to read first pixel data generated by first pixels of the image sensor at a first time, the first pixels located in at least one of the row of the pixels or the column of the pixels, a comparator to compare the first pixel data with second pixel data generated by the first pixels at a second time different than the first time to generate first change values, and a counter to generate a count of persons based on the first change values. |
| US09344202B2 |
Received signal quality indicator
The invention generally relates to a method of indicating signal quality at an input to a radio receiver, and to a radio receiver. In particular, such a method is described, wherein a receiver comprises first (RF) and second (IF) gain control loops respectively using first and second gain control signals, and comprising indicating signal quality dependent on said first gain control signal and said second gain control signal. In an embodiment, a difference between the first and second gain control signals is used to indicate presence of interference and/or received signal strength. |
| US09344200B2 |
Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxial semiconductor material formed using lateral overgrowth
An electrical device that includes a first semiconductor device positioned on a first portion of a substrate and a second semiconductor device positioned on a third portion of the substrate, wherein the first and third portions of the substrate are separated by a second portion of the substrate. An interlevel dielectric layer is present on the first, second and third portions of the substrate. The interlevel dielectric layer is present over the first and second semiconductor devices. An optical interconnect is positioned over the second portion of the semiconductor substrate. At least one material layer of the optical interconnect includes an epitaxial material that is in direct contact with a seed surface within the second portion of the substrate through a via extending through the least one interlevel dielectric layer. |
| US09344197B2 |
Wave dielectric transmission device, manufacturing method thereof, and in-millimeter wave dielectric transmission method
A millimeter wave transmission device, the millimeter wave transmission device with (a) a first signal processing board for processing a millimeter wave signal; (b) a second signal processing board signal-coupled to the first signal processing board to receive the millimeter wave signal and perform signal processing with respect to the millimeter wave signal; and (c) a member provided between the first signal processing board and the second signal processing board and having a predetermined relative dielectric constant and a predetermined dielectric dissipation factor. The member constitutes a dielectric transmission path via which the millimeter wave signal is transmitted between the first signal processing board and the signal processing board. |
| US09344196B1 |
Integrated interferometric optical transmitter
A monolithic integrated optical transmitter comprising (a) an optical source including two output optical paths and (b) a modulator section that includes an interferometric optical signal combiner is described. Each of the two output optical paths of the optical source includes a reflector. The optical source is configured to output a first light beam through the first optical path and a second light beam through the second optical path. The optical transmitter is capable of generating advanced modulation format signals based on amplitude and phase modulation. |
| US09344190B2 |
Flexible placement of spectral inverters in optical networks
Methods and systems are provided for flexible placement of spectral inverters in an optical network. The method includes identifying a first transmission path coupling a transmitter and a receiver. The first transmission path includes a first node for assignment of a first spectral inverter. The method further includes estimating a first optical signal-to-noise ratio (OSNR) penalty of nonlinear phase noise (NLPN) on the first transmission path with the first spectral inverter assigned to the first node, and based on the first estimated OSNR penalty of NLPN being less than an NLPN penalty threshold, assigning the first spectral inverter to the first node. |
| US09344187B2 |
Apparatus and methods for enabling recovery in optical networks
Apparatus for enabling an M:N recovery scheme in an optical network includes a set of N working DSP-enabled optical transceivers/transponders including at least one working DSP-enabled optical transceiver/transponder that uses a first set of transmission parameters and at least one working DSP-enabled optical transceiver/transponder that uses a second set of transmission parameters which is different from the first set of transmission parameters, and a set of M protection DSP-enabled optical transceivers/transponders operable to protect the set of N working DSP-enabled optical transceivers/transponders and including L protection DSP-enabled optical transceivers/transponders, each having a capability of using a set of adjustable transmission parameters enabling it to protect every one of the N working DSP-enabled optical transceivers/transponders, and, when M>L, M−L protection DSP-enabled optical transceivers/transponders, each having a capability of protecting at least one, but not all, of the N working DSP-enabled optical transceivers/transponders. Related network and methods are also disclosed. |
| US09344186B2 |
Method for relaying data in wireless communication system based on time division duplex
A method of relaying data in a time division duplex (TDD)-based wireless communication system is provided. The method includes configuring a downlink subframe as a multicast/broadcast single frequency network (MBSFN) subframe, receiving downlink data in the MBSFN subframe; and relaying uplink data to a base station in an uplink subframe, wherein the downlink subframe is linked to the uplink subframe which is reserved to transmit an acknowledgement (ACK)/non-acknowledgement (NACK) signal for downlink data transmission in the downlink subframe. Accordingly, in the TDD-based wireless communication system, efficiency of resource allocation can be increased, and uplink ACK collision can be avoided. |
| US09344184B2 |
Apparatus and method for the production of food
A method for the transmission of process data between different devices that are involved in a process for the production of food, in particular devices involved in a filling line, wherein the data communication between two devices takes place exclusively between at least one transmitter of a first device and at least one receiver of a second device, and/or between at least one transmitter of the second device and at least one receiver of the first device. |
| US09344178B2 |
Method of aiding uplink beamforming transmission
A method of aiding uplink transmission is disclosed. One method includes a base station downlink transmitting signals to at least a first terminal, the transmitted signals directed and conveying data to at least the first terminal. The method further includes a second terminal eavesdropping the transmitted signals, and measuring a signal quality. The second terminal estimates uplink channel information based on the measured signal quality, for aiding uplink transmission. Based at least in part on the estimated transmission channel, the second terminal transmits uplink signals to the base station. |
| US09344176B2 |
Method and apparatus for providing elevation plane spatial beamforming
In one embodiment, the present disclosure provides a method and apparatus for spatially filtering inter-cell co-channel interference in the elevation plane, which in turn will improve network spectral efficiency. |
| US09344174B2 |
Systems, apparatus, and methods for antenna selection
This disclosure provides systems, methods, and apparatus for mobile transmit diversity. In one aspect, a wireless communication apparatus is provided. The wireless communication apparatus includes a plurality of antennas. The wireless communication apparatus further includes a plurality of transmit circuits, each transmit circuit of the plurality of transmit circuits being configured to transmit according to a different radio access technology. The wireless communication apparatus further includes a controller configured to selectively switch each of the transmit circuits of the plurality of transmit circuits to transmit wireless communications via a corresponding one of the plurality of antennas based on priority levels of data for each of the transmit circuits and a detected operating mode of the wireless communication apparatus. |
| US09344171B2 |
Transmission method, transmission device, reception method, and reception device
Provided is a precoding method for generating, from a plurality of baseband signals, a plurality of precoded signals to be transmitted over the same frequency bandwidth at the same time, including the steps of selecting a matrix F[i] from among N matrices, which define precoding performed on the plurality of baseband signals, while switching between the N matrices, i being an integer from 0 to N−1, and N being an integer at least two, generating a first precoded signal z1 and a second precoded signal z2, generating a first encoded block and a second encoded block using a predetermined error correction block encoding method, generating a baseband signal with M symbols from the first encoded block and a baseband signal with M symbols the second encoded block, and precoding a combination of the generated baseband signals to generate a precoded signal having M slots. |
| US09344165B2 |
Method and apparatus of beam training for MIMO operation and multiple antenna beamforming operation
The disclosed invention provides an efficient method for MIMO beam training for multiple antennas to enable spatial multiplexing MIMO operation and spatial combining in a wireless network. The invention discloses a simple and efficient beam-training algorithm and protocol for MIMO operation that operates in high SNR condition for reliable MIMO operation. In one novel aspect, the best MIMO beam combinations are determined after TX sector sweeping and RX sector sweeping. The best MIMO beam combinations are determined in such a way that no any selected TX/RX sectors come from the same TX/RX antenna/beamformer. The selection criteria includes not only signal quality, but also considers mutual interference and leakage among multiple MIMO spatial streams to improve overall MIMO performance. Simultaneous RX or TX training are also supported to reduce training time. |
| US09344164B2 |
Method, system and device for feeding back and receiving PMI
The embodiments of the disclosure relate to the technical field of wireless communications, and particularly relate to a method, a system and a device for feeding back and receiving a Pre-coding Matrix Indicator (PMI), which is used for feeding back a vertical dimension PMI. The method for feeding back the PMI provided by the embodiments of the disclosure comprises: confirming the PMI needed to be fed back, wherein the PMI comprises a horizontal dimension PMI and a vertical dimension PMI, or a PMI combined by horizontal dimension and vertical dimension (801); feeding back the confirmed PMI in a non periodic Channel State Information (CSI) feedback mode or a periodic CSI feedback mode (802). Since the capability of feeding back the vertical dimension PMI, dynamic 3D beam shaping technology can be implemented and the throughput of the user equipments in the edge of cell and the average throughput can be improved. |
| US09344161B2 |
Coverage enhancement using dynamic antennas and virtual access points
Mechanisms for wireless local area network coverage enhancement using dynamic antennas are provided. The dynamic antennas may be used, for example, in an antenna apparatus of an access point. The access point maps a plurality of virtual access points (VAPs), each VAP corresponding to at least one of a plurality of directional antenna patterns of the antenna apparatus. The processor transmits broadcast communication on each of the VAPs a further distance from the access point as compared to transmitting on an omnidirectional antenna pattern of the antenna apparatus. |
| US09344160B2 |
Data transmission method and system, transmitter, and receiver
A data transmission method and system, transmitter and receiver. The method includes: mapping, by a transmitter, a plurality of data streams to a plurality of antennas of the transmitter by using precoding matrices and transmitting the plurality of data streams to a receiver via the plurality of antennas, wherein the transmitter selects the precoding matrices by taking a resource block as a granularity. With the embodiments of the present invention, the transmitter may transmit data streams to the receiver by using the precoding matrices W, and selects the precoding matrices W by taking a resource block (RB) as a granularity, so as to support DM-RS demodulation, and the receiver is not needed to perform PMI feedback, which is also applicable to a scenario where user feedback is not supported or PMI feedback is inaccurate, thereby achieving open-loop spatial multiplexing CoMP transmission. |
| US09344157B2 |
Method and apparatus for communication by means of a transformer
A method for communication by means of a transformer, which has at least a primary coil and a secondary coil, which are parts of an oscillatory circuit, wherein the oscillatory circuit is supplied on the primary side with an exciter frequency. For transmission of a signal from the secondary side to the primary side, the inductance of the secondary coil is modulated. A corresponding apparatus for performing the method is likewise provided. |
| US09344153B2 |
Reader receivers and reader transceivers including the same
Reader receivers including a sample clock providing unit are provided. The sample clock providing unit may be configured to generate a plurality of first clock signals of equivalent frequency that are out-of-phase relative to each other and further configured to generate first and second sample clock signals of unequal phase from selected ones of the plurality of first clock signals by comparing a respective phase of each of the plurality of first clock signals against a phase of a reference clock signal. |
| US09344148B2 |
Input/output signal processing circuit and input/output signal processing method
The present invention discloses an input/output (I/O) signal processing circuit and processing method. The I/O signal processing circuit includes a level adjustable I/O circuit and an adjustment circuit. The I/O signal processing circuit includes an output driver and/or an input comparator. The output driver transmits an output signal via a signal transmission line according to an output data. The output driver has an adjustable high operation voltage level and an adjustable low operation voltage level, which determine a high level and a low level of the output signal, respectively. The input comparator receives an input signal via the signal transmission line and comparing the input signal with an adjustable reference voltage, so as to generate an input data. The adjustment circuit generates an adjustment signal according to voltage drop related information, to correspondingly adjust the adjustable high and low operation voltage level and/or the adjustable reference voltage. |
| US09344142B2 |
Communication system and a method for mitigating leakage signals
A communication system that includes a transmit antenna, a radio frequency (RF) phase shifting module, an RF combiner, a first receive antenna and a second receive antenna; wherein the first and second receive antennas are located at a same distance from the transmit antenna; wherein the first and second receive antennas are arranged to receive first and second leakage signals resulting from a transmission of RF radiation by the transmit antenna; wherein the RF phase shifting module is configured to receive signals from the first and second receive antennas, to phase shift signals from at least one of first and second receive antennas to provide intermediate RF signals; wherein the phase shift caused by the RF phase shifting module introduces a destructive phase shift between the first and second leakage signals; wherein the RF combiner is configured to add the intermediate RF signals to provide combined RF signals. |
| US09344141B2 |
Electronic device and data control method
The disclosure provides an electronic device including a coupler, a transceiver, and a control circuit. The coupler generates a coupled downlink signal according to a downlink signal from a head-end unit. The transceiver switches between the transmission of a downlink signal and the reception of an uplink signal according to a control signal. The control circuit receives the coupled downlink signal, generates a status counting signal according to the power status of the coupled downlink signal, and generates the control signal according to the status counting signal. Only when the level of the coupled downlink signal is lower than an amplitude threshold level with a duration longer than a status counting time, the control circuit converts the status counting signal from a first logic level to a second logic level opposite to the first logic level. Otherwise, the control circuit maintains the status counting signal on the first logic level. |
| US09344139B2 |
Transceiver, method, computer program and communication device
A transceiver is disclosed comprising a transmitter; a receiver; and a signal transmission arrangement. The transmitter comprises a power amplifier, and the signal transmission arrangement is arranged to transmit signals provided from the transmitter through its power amplifier, and arranged to receive signals and provide them to the receiver. The transceiver further comprises an auxiliary power amplifier which has controllable phase shift and gain; a first impedance element; a second impedance element; and a controller. The auxiliary power amplifier has its input connected to the input of the power amplifier of the transmitter, the first impedance element is connected between an output of the auxiliary power amplifier and an input of the receiver, the second impedance element is connected between an output of the power amplifier of the transmitter and the input of the receiver, and the controller is arranged to control the auxiliary power amplifier to provide a signal that has a phase and amplitude in relation to the output of the power amplifier of the transmitter and the impedances of the first and second impedance elements such that the transmitter contribution at the input of the receiver is suppressed. A method, computer program and communication device is also disclosed. |
| US09344138B2 |
Method and system for providing improved high power RF splitter/combiner
The present invention provides an improved high power RF (radio frequency) splitter/combiner that is appropriate for use in a wide range of frequencies and applications, including KHz to GHz, including in the L, S, and C bands. The present invention provides a high power RF splitter/combiner that operates without the inconvenience of the balanced isolation load requirement of the Wilkinson splitter/combiner topology—i.e. the isolation load returns to ground rather than being connected between a pair of floating nodes. |
| US09344132B2 |
Femto node power adjustment in wireless communications systems
Systems, devices, and methods for adjusting a transmission power at a femto node are described herein. According to the systems, devices, and methods herein, a measurement of a signal transmitted from a transmitting node may be communicated to the femto node, for example from a user equipment or a neighboring femto node, for use in adjusting the power. The transmitting node may comprise the femto node, a macro node, or a neighboring femto node. In addition, statistics regarding such measurements may be communicated to the femto node for use in adjusting the power. The femto node may also adjust the power based on unsuccessful registration attempts or interference communications received at the femto node. |
| US09344128B2 |
System and method for decoding a radio signal
A method of decoding a radio signal by an electronic device is provided. The method includes receiving the radio signal, digitizing the radio signal, auto-correlating the radio signal to generate a first signal and determining periodic information of the radio signal using the first signal. An electronic device, such as a software defined radio, is also provided. The electronic device includes a radio frequency front end, a processing unit and memory. The processing unit may also include a field programmable gate array and a graphics processing unit. |
| US09344127B2 |
Graphene resonator based mixer-first receiver on CMOS for digitally controlled and widely tunable RF interface
A radio frequency (RF) receiver including a baseband circuitry. The baseband circuitry can include a graphene nano-electro-mechanical (GNEMS) based system, a receiver, and a front-end mixer. The GNEMS based system can include a source, a drain, a gate and a nano-scale suspended graphene resonator. The graphene resonator can be suspended between the source and the drain. The receiver circuitry can be disposed on the baseband and configured to receive an RF signal. The front-end mixer can be disposed between the GNEMS based system and the receiver circuitry. The baseband circuitry can be configured such that an incoming signal sees frequency selective impedance at the receiver circuitry. |
| US09344126B2 |
Receiving apparatus, receiving method, and program
Disclosed are a receiving apparatus, a receiving method, and a program capable of reliably obtaining predetermined information. In a case where a broadband signal where the same control information is arranged in different frequency bands is received and processed, a frequency where the control information is stably received is detected, and the control information is obtained again using the detected frequency. This frequency detection is performed by detecting a frequency capable of avoiding a no-signal band in a signal array of the broadband signal determined based on the obtained control information and the like. This technology can be applied to a receiving apparatus that receives a signal conforming to a DVB-C2 standard. |
| US09344125B2 |
Remote interference cancellation for communications systems
An interference cancellation system (ICS) may be used with a communication system to prevent or minimize interference from one or more sources. The ICS may receive radio frequency (RF) signals comprised of one or more signals of interest (SOI) and multiple interfering signals. An interference estimation processor (IEP) may be used to estimate the one or more interfering signals. The interfering signals may be estimated using spatial and/or time diversity, which may be combined with statistical methods. The estimated interfering signals may be sent to the ICS, which may use the estimated interference signal to cancel the interference and output the SOI. |
| US09344122B1 |
Adaptive filtering for canceling distortion in radio frequency signals
Adaptive filtering is used to substantially cancel distortion in radio frequency (RF) signals. Such adaptive filtering can be used in an RF transmitting module to pre-compensate an RF signal with compensation (inverse) distortion to cancel inherent transmission path distortion from the RF signal. Adaptive filtering can also be used in a multi-carrier RF receiving module to cancel from a given carrier signal distortion due to cross talk from adjacent carrier signals. Adaptive filtering in an RF transceiver can be used to cancel from a received RF signal distortion arising from leakage of a transmit signal into the receive path. |
| US09344121B2 |
Radio communication transmission system and method based on software defined radio
The disclosure discloses a Software Defined Radio (SDR)-based radio communication transmission system. A front-end analog interface unit, a Digital-to-Analog (D/A) and Analog-to-Digital (A/D) conversion unit, a core processing unit and a storage unit adopt the universal bus for interconnection and interworking. The core processing unit is configured to acquire the front-end processed data from the front-end analog interface unit, and to choose to transmit the front-end processed data to the D/A and A/D conversion unit by the control of the universal bus according to whether the radio communication standard of the current data accords with the current working mode. The disclosure further discloses an SDR-based radio communication transmission method, which includes that: the core processing unit chooses to transmit the front-end processed data to the D/A and A/D conversion unit by the control of the universal bus according to whether the radio communication standard of the current data accords with the current working mode. The system and method of the disclosure can adapt to the coexistence of multiple radio communication standards and complement the advantages of each structure at the same time. |
| US09344118B2 |
Apparatus and method for generating interleaver index
An apparatus for generating indexes of an interleaver for input data comprises: a main processor for calculating an index for a predetermined bit of the input data; and an index operator for receiving the index calculated by the main processor, calculating in parallel indexes for bits after the predetermined bit, and deriving a plurality of indexes. The main processor calculates the index for ith to (i+15)th bits of the input data where i is an integer equal to or larger than 0, and transfers a result of (128*f2)modK to the index operator. The index operator calculates an index for an (i+j+16)th bit where j is an integer which satisfies 0≦j≦7 by using an equation of Π(i+j+16)=(2*Π(i+j+8)−Π(i+j)+128*f2)modK where K is a size of the input data and f2 is a coefficient calculated from K. |
| US09344115B2 |
Method of compressing and restoring configuration data
A method of compressing configuration data used in a reconfigurable processor including generating one piece of combined data by combining configuration data used at two or more cycles and generating a bit table indicating valid operations at each of the two or more cycles among operations included in the combined data. |
| US09344114B1 |
Compressed caching in a virtual memory system
Data compression systems, methods, and computer program products are disclosed. For each successive input word of an input stream, it is determined whether the input word matches an entry in a lookback table. The lookback table is updated in response to the input word. Input words may be of a number of data types, including zero runs and full or partial matches with an entry in the lookback table. A codeword is generated by entropy encoding a data type corresponding to the input word. The lookback table may be indexed by the position of the input word in the input stream. |
| US09344113B1 |
Lempel Ziv compression architecture
A data compression architecture comprises a shift register structure comprising first and second parallel paths, each comprising several shift register elements for storing previously received data characters. Each shift register element in the first path is paired with a respective shift register element in the second path. An input shift register stores input data characters in pairs during successive clock cycles. Logic circuitry compares the input data characters with each of the previously received data characters stored in the pairs of shift register elements to detect a match during one or more clock cycles. The logic circuitry determines a length of a sequence of received input data characters by determining a number of clock cycles during which a match is detected in a particular pair of shift register elements, and applies a correction factor based on a type of match detected at a beginning and end of the sequence. |
| US09344112B2 |
Sampling based elimination of duplicate data
A technique for eliminating duplicate data is provided. Upon receipt of a new data set, one or more anchor points are identified within the data set. A bit-by-bit data comparison is then performed of the region surrounding the anchor point in the received data set with the region surrounding an anchor point stored within a pattern database to identify forward/backward delta values. The duplicate data identified by the anchor point, forward and backward delta values is then replaced in the received data set with a storage indicator. |
| US09344110B2 |
Delta-sigma modulator and communication device
A delta-sigma modulator capable of outputting an output signal including a plurality of signals having different frequencies. The delta-sigma modulator includes: a plurality of input ports to which a plurality of input signals having different frequencies are inputted, respectively; a plurality of loop filters provided corresponding to the plurality of input ports, respectively; an adder configured to add outputs of the plurality of loop filters; and a quantizer configured to quantize an output of the adder. The plurality of loop filters each receive the input signal inputted to the corresponding input port and a feedback signal of an output of the quantizer. The plurality of loop filters each have a characteristic of stopping noise in the vicinity of a frequency of the input signal inputted to the corresponding input port. |
| US09344109B2 |
Method, system and apparatus for dual mode operation of a converter
Methods, systems and apparatuses for operating a converter or other circuits are disclosed. More particularly, in one embodiment a converter or other circuit can be operated in two modes which may include the count-to-time and time-to count modes to determine an output value corresponding to an input signal. During operation in the count-to-time mode a converter may be operated using a reference signal to determine a number of clock cycles needed until an output corresponds to a scaling factor is reached. During operation of the circuit in the time-to-count mode then, the converter may be operated for this number of clock cycles using the input signal to determine an output. This output may be proportional to the level on the input signal. |
| US09344108B2 |
Device having a delta-sigma modulator and a switching amplifier connected thereto
A delta-sigma modulator for a switching amplifier, which achieves a high signal-to-noise ratio (SNR) in the multi-MHz range and keeps the noise-transfer function over the useful frequency range as low and as flat as possible. A series connection of a parallel-serial converter and a downstream swap element for the serial output signal ya2 of the parallel serial converter is connected to the multi-bit output of the delta-sigma-modulator. The swap element swaps, based on the last bit value 0 or 1 of a preceding word in the resulting output signal ya3, the sequence of the binary zeroes and ones of the current word, where present, and then an input signal is fed to the delta-sigma-modulator. The signal is capable of having a frequency range above 25 kHz, and is prepared with a low oversampling ratio and a high SNR. And, 1-0 or 0-1 transitions are largely eliminated at the word boundaries. |
| US09344107B1 |
Continuous time ADC and filter
The invention concerns an analog to digital conversion and filtering circuit comprising: an input for receiving an analog input signal; an asynchronous continuous-time analog to digital converter adapted to generate, based on the analog input signal, a digital continuous-time signal; a feedback path comprising a digital continuous-time filter adapted to generate a filtered signal to be combined with the analog input signal, the digital continuous-time filter being adapted to generate the filtered signal by: filtering out at least one first frequency range of the digital continuous-time signal; and amplifying at least one second frequency range of the digital continuous-time signal. |
| US09344105B2 |
Successive approximation analog-to-digital converter and conversion method thereof
A successive approximation analog-to-digital converter and conversion method thereof are provided, the successive approximation analog-to-digital converter includes a segmented-multiple-stage capacitor array with redundancy bits, a comparator, a weight-storage circuit, a code reconstruction circuit and a control logic circuit. The successive approximation analog-to-digital converter helps to decrease the complexity of circuit design, featuring small size and low power. Without auxiliary capacitor array, switches and control logic, the circuit can work to precisely measure and correct capacitor mismatch errors. |
| US09344101B2 |
Semiconductor device, electronic device and sensing method
In order to reduce power consumption, a semiconductor device includes an RTC for generating a piece of time information and a first activation signal SW3, a comparator for determining whether the value of an analog input signal exists within a predetermined range, an AD conversion circuit for converting the analog input signal to a digital signal in response to a common activation signal, and a CPU for processing the digital signal in response to the common activation signal. When the analog input signal does not exist within the predetermined rang, the comparator generates the common activation signal. Then, the CPU stores the piece of digital information corresponding to the digital signal as well as the piece of time information from the RTC into a storage circuit. |
| US09344100B2 |
Reconfigurable local oscillator for optimal noise performance in a multi-standard transceiver
A transceiver for multi-standard operation (usable, for example, to communicate signals both of a first wireless communication standard and of a second wireless communication standard) has a mixer that receives a local oscillator signal generated by a local oscillator. A PLL of the local oscillator involves a VCO, a digitally programmable analog loop filter, a digitally programmable VCO supply voltage circuit, and a digitally programmable VCO varactor bias control circuit. In one aspect, the bandwidth of the analog loop filter is adjusted depending on the communication standard of the signal being communicated. In other aspects, the VCO supply voltage circuit and/or the varactor bias control circuit are configured in different ways to optimize PLL performance depending on the communication standard of the signal being communicated. |
| US09344097B2 |
Fast acquisition frequency detector
A phase-frequency detector (PFD) circuit that includes a binary phase detector and a ternary phase detector coupled to the binary phase detector. The binary phase detector is configured to, based on the PFD circuit being in a frequency acquisition state, compare a clock signal with a data signal and output up and down signals based on the comparison. The binary phase detector is also configured to be disabled based on the PFD circuit being in a frequency locked state. The ternary phase detector is configured to compare the clock signal with the data signal and output up, down, and hold signals based on the comparison. |
| US09344096B2 |
Method for detecting frequency offset of oscillator and associated circuit
A method for detecting frequency offset of an oscillator includes: receiving an oscillation signal having an oscillation frequency; generating a self-mixing signal according to the oscillation signal; performing frequency division upon the self-mixing signal to obtain a down-converted self-mixing signal; obtaining a down-converted self-mixing frequency corresponding to a maximum power in a specific frequency range of the down-converted self-mixing signal; and computing a frequency offset of the oscillation frequency according to at least the oscillation frequency and the down-converted self-mixing frequency. A related circuit is also disclosed. |
| US09344095B2 |
Temperature compensation for an oscillator crystal
An electronic device is equipped with an oscillator interface to be coupled to an oscillator crystal of an oscillator element. The electronic device includes an oscillator circuit which is coupled to the oscillator interface and generates an oscillator signal. The electronic device is further provided with a temperature measurement interface to be coupled to a temperature sensor of the oscillator element so as to receive the temperature signal. For accomplishing temperature compensation, the electronic device is provided with a measurement controller coupled to the measurement interface and configured to measure a first value of the temperature signal at a first point of time and a second value of the temperature signal at a second point of time. A frequency drift estimator is provided so as to estimate a frequency drift of the oscillator signal on the basis of the first value of the temperature signal and a second value of the temperature signal. By means of a compensation logic, a frequency compensation signal for the oscillator circuit is generated on the basis of the estimated frequency drift. |
| US09344092B2 |
Tunable superconducting notch filter
A technique relates to a superconductor tunable notch filter. A Josephson junction filter array is connected to a coupling pad and connected to ground. The Josephson junction filter array includes a filter inductance. The Josephson junction filter array connected to the coupling pad forms a filter capacitance. A Josephson junction bias array is connected to the coupling pad and connected to a current source. The Josephson junction bias array includes a bias inductance. A transmission line is connected to the coupling pad in which connection of the transmission line and the coupling pad forms a coupling capacitance, such that the filter inductance and the filter capacitance connect to the transmission line through the coupling capacitance. The Josephson junction filter array includes a notch filter frequency that is tunable according to a magnitude of a current bias from the current source. |
| US09344091B2 |
Die-stacked memory device with reconfigurable logic
A die-stacked memory device incorporates a reconfigurable logic device to provide implementation flexibility in performing various data manipulation operations and other memory operations that use data stored in the die-stacked memory device or that result in data that is to be stored in the die-stacked memory device. One or more configuration files representing corresponding logic configurations for the reconfigurable logic device can be stored in a configuration store at the die-stacked memory device, and a configuration controller can program a reconfigurable logic fabric of the reconfigurable logic device using a selected one of the configuration files. Due to the integration of the logic dies and the memory dies, the reconfigurable logic device can perform various data manipulation operations with higher bandwidth and lower latency and power consumption compared to devices external to the die-stacked memory device. |
| US09344089B2 |
Semiconductor integrated circuit and power-supply voltage adaptive control system
A semiconductor integrated circuit has N input terminals; N output terminals; a plurality of flip-flops (FFs) including N FFs and R redundant FFs; a selector section configured to select N selected FFs from the plurality of FFs depending on reconfiguration information and to switch data flow such that data input to the N input terminals are respectively output to the N output terminals by the N selected FFs; and an error detection section. In a test mode, the N FFs form a scan chain and a scan data is input to the scan chain. The error detection section detects an error FF included in the N FFs based on scan input/output data respectively input/output to/from the N FFs in the test mode and further generates the reconfiguration information such that the detected error FF is excluded from the N selected FFs. |
| US09344086B2 |
Receiving circuits for core circuits
A receiving circuit for a core circuit is provided and includes a first receiving-path unit. The first receiving-path unit is capable of receiving an input signal and outputting an output signal to the core circuit according to the input signal. The first receiving-path unit includes an input buffer which is capable of operating in a core power domain of the core circuit and receiving a first clamped signal. When a level of the input signal is substantially equal to or lower than a first predetermined voltage level, the input signal is passed to the input buffer to serve as the first clamped signal, and the input buffer is capable of outputting the output signal in the core power domain according to the first clamped signal. When the level of the input signal is higher than the first predetermined voltage level, the input signal is not passed to the input buffer. |
| US09344085B2 |
Keypad with optical sensors
A keypad with optical sensors is provided. The keypad comprises keycaps, each keycap having a top surface. One or more optical sensors are located beneath top surfaces of adjacent keycaps. One or more light guides extend from a respective optical sensor towards the top surfaces. |
| US09344080B1 |
Dual-gate transistor control based on calibration circuitry
Disclosed are various embodiments related to dual-gate transistors and associated calibration circuitry. In one embodiment, dual-gate transistors may be configured in a sense amplifier arrangement, and calibration circuitry can be used to adjust an input offset of the sense amplifier. In another embodiment, a reference level voltage utilized in an amplifier with dual-gate transistors can be adjusted during a calibration sequence, and may be substantially unchanged from its nominal value outside of the calibration sequence. In another embodiment, a calibration sequence can be utilized to determine circuit results from a circuit including dual-gate transistors, and to adjust control gates to more closely coincide with expected or desired results. In yet another embodiment, a semiconductor memory device can include a memory array with amplifiers that include dual-gate transistors, as well as associated calibration circuitry. |
| US09344079B2 |
From a voltage level-shifting device determining a status of a voltage supply based on a test input
Methods and implementation of low-power power-on control circuits are disclosed. In a particular embodiment, a computer readable tangible medium stores instructions executable by a computer. The instructions may be executable by the computer to determine whether a power detector circuit powered by a first voltage supply has received a test input from at least one voltage level-shifting device coupled to a second voltage supply. |
| US09344078B1 |
Inverse current protection circuit sensed with vertical source follower
A monolithic integrated circuit includes a low-voltage control circuit, a vertical power transistor, and a source follower. The vertical power transistor includes at least a drain. The source follower includes a drain that is coupled to the drain of the vertical power transistor, a gate that is coupled to a limit voltage node, and a source that is coupled to a high impedance node. The source follower is arranged such that a source voltage at the source of the source follower is a voltage-limited version of the drain voltage of the vertical power transistor. The low-voltage control circuit includes a driver and protection circuit that is arranged to detect the source voltage, to drive the vertical power transistor, and to adjust how the vertical power transistor is biased based, at least in part, on the source voltage. |
| US09344076B2 |
Bypass circuits and network security devices using the same
A bypass circuit is provided. The bypass circuit is integrated in a single chip. The bypass circuit includes a first pin set, a second pin set, an output pin set, and a switching circuit. The first pin set receives a first input signal from outside of the single chip. The switching circuit is coupled to the first pin set and transmits the first input signal to the second pin set or the output pin set. |
| US09344074B2 |
Low-latency, frequency-agile clock multiplier
In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock. |
| US09344073B2 |
Semiconductor device
A semiconductor device includes: a power supply; a circuit block that has at least one storage element and operates by receiving a power supply voltage from the power supply; a power management unit that controls the power supply to change the power supply voltage; and a storage element monitor circuit that generates a first malfunction signal at a first margin voltage that is higher than a voltage at which the storage element does not normally operate in a case where the power supply voltage lowers, wherein the power management unit controls the power supply so that the power supply voltage does not become lower than the first margin voltage. |
| US09344072B2 |
High-resolution pulse width modulation signal generation circuit and method
A pulse width modulation (PWM) signal generation circuit and method are disclosed herein. The PWM signal generation circuit includes an integer part pulse generation circuit, and a fractional part pulse generation circuit. The integer part pulse generation circuit generates an integer part pulse using the integer part of the digitized value of a duty cycle, i.e., the ratio of the time during which any one of high and low levels is maintained to the period of a PWM signal. The fractional part pulse generation circuit generates the PWM signal using the integer part pulse and the fractional part of the digitized value of the duty cycle. |
| US09344068B2 |
Device for generating short electrical pulses
A device for the generation of short electric pulses, comprising a base generator for the generation of base monocycle pulses, wherein the base generator is followed by a transistor stage 4. |
| US09344061B1 |
Low frequency coaxial capacitors and tuners
A new type of variable coaxial, low frequency capacitor uses two cylindrical blocks, which are interdigitally insertable into each-other to create an adjustable capacitance. Each block is made using a conductive (aluminum, brass or copper) strip which is mounted vertically on a conductive basis and is wound in spiral form around a center axis. The blocks are guided coaxially into each-other and the relative orientation angle allows approaching the surfaces of the conductive strips from a maximum distance, which is half the width of the spiral gap, to full galvanic contact. The block penetration is motor controlled and a cascade of three or four such capacitors and associated lengths of coaxial cable is used to make wideband impedance tuners operating in the low MHz frequency range. |
| US09344057B2 |
Tuning-fork type crystal resonator plate
For a tuning-fork type crystal resonator plate, a crystal plate having a crystal orientation is used. The tuning-fork type crystal resonator plate includes: a base portion; and a pair of first and second leg portions protruding from the base portion in one direction. In the first leg portion and the second leg portion, grooves are formed so that each of the grooves is biased relative to a center of the corresponding first or second leg portion in a width direction. A lowermost point of the groove is positioned in a middle of the groove in the width direction (width direction of the first leg portion and the second leg portion) in a state viewed from an end surface of the first and second leg portions in the width direction. |
| US09344049B2 |
Wireless microphone mute control override
An audio system is configured to support a number of wireless microphones, and each of the wireless microphones has one or more touch sensitive mute switches and a touch sensitive mute guard band switch. The mute guard band switch is connect to an electrically conductive surface that is proximate to a microphone peripheral surface that a user is likely to touch when they move the microphone. Logical instructions running in conjunction with a DSP associated with the microphone cause the audio system to override any mute commands it receives from any of the mute switches during the time that the guard band switch is activated. |
| US09344043B2 |
Output buffer circuit, array substrate and display device
The embodiments of the present invention provide a output buffer circuit, comprising: a first stage operational amplifying circuit configured as a differential input circuit; a second stage operational amplifying circuit configured as a common source amplifying circuit having an active load; and a feedback circuit provided between the first stage operational amplifying circuit and the second stage operational amplifying circuit and configured to have driving capability of providing source current and sink current alternately. By forming a unit gain amplifier comprising the first stage operational amplifying circuit, the second stage operational amplifying circuit and the feedback circuit connected therebetween, the output buffer circuit has the driving capability of providing source current and sink current alternately. No special voltage stabilizing circuit is needed, thus the circuit structure is simple and the chip area is decreased; since the power consumption can be reduced without a special voltage stabilizing circuit, the fluctuation of the output voltage is suppressed at the same time, the stability of the circuit is ensured in operation and offset is suppressed optimally, the output signal is more accurate and the quality of image displayed is improved. |
| US09344042B2 |
High efficiency power amplifiers with advanced power solutions
A device comprises a switch network having a plurality of switch cells connected in series, an output voltage at an output voltage port with an output capacitor, and an impedance network coupled between the switch network and an output voltage port with an output capacitor. Each switch cell has a plurality of input voltages and a plurality of switches, in which each switch is coupled to an input voltage, and a first input voltage coupled to a first switch has a different value from a second input voltage coupled to a second switch. The output voltage is configured to be a combination of the input voltages of the switch network in the form of: Vo=Σ1NKi×Vi, where Vo is the output voltage, N is the number of input voltages, Vi is the ith input voltage, and Ki is an integer equal to 0 or 1 depending on the ON/OFF status of the switches in the switch network. |
| US09344037B2 |
Oscillator circuit and semiconductor device including the same
Controllability of an oscillator circuit is improved. The oscillator circuit has inverters in odd-numbered stages. A circuit is electrically connected to a power supply node of the inverters to which a high power supply potential is input. The circuit includes a first transistor, a second transistor, and a capacitor. The first transistor includes an oxide semiconductor in its channel. A holding circuit including the first transistor and the capacitor has a function of holding an analog potential that is input from the outside. The potential held by the holding circuit is input to a gate of the second transistor. A power supply potential is supplied to the inverters through the second transistor, so that the delay time of the inverter can be controlled by the potential of the gate of the second transistor. |
| US09344036B1 |
Voltage-controlled oscillator (VCO) with amplitude control
Certain aspects of the present disclosure generally relate to automatic amplitude control of an oscillating signal output from a voltage-controlled oscillator (VCO) using feedback from an amplitude adjustment circuit. The VCO may comprise cross-coupled metal oxide semiconductor (MOS) transistors coupled to a resonant tank circuit. Gates of the cross-coupled transistors are configured to control an amplitude of the oscillating signal generated by the resonant tank circuit. In certain aspects, the amplitude adjustment circuit may comprise a peak detector that generates a signal that is representative of the amplitude of the oscillating signal. The signal generated by the peak detector may be compared to a reference voltage by an amplifier. The amplifier may generate a feedback signal to control the gates of the cross-coupled MOS transistors based on the comparison, thereby adjusting the amplitude of the oscillating signal. |
| US09344035B2 |
System and method for a voltage controlled oscillator
In accordance with an embodiment, an oscillator includes a tank circuit and an oscillator core circuit having a plurality of cross-coupled compound transistors coupled to the tank circuit. Each of the plurality of compound transistors includes a bipolar transistor and a field effect transistor (FET) having a source coupled to a base of the bipolar transistor. |
| US09344032B2 |
Module for mixed photovoltaic and thermal power generation from solar radiation, and plant provided with such modules
The invention relates to a power generation module (M1, M2, M3), using solar radiation, which includes a caisson (2) comprising: a first wall (3) exposed to solar radiation, at least partially made up of a photovoltaic panel (4) with the other part made up of at least one transparent plate (5) or separated photovoltaic cells; at least one second dark wall spaced apart from the inner surface of the first wall (3); an intake (9) for fresh or recycled air with a view to circulating air inside the caisson between the walls; and an outlet (13a) for the air that swept through the inside of the caisson and which was heated by the part of the radiation that passed through the first wall including the transparent plate, the power being generated as electricity by the photovoltaic panel and as thermal power using the heated air. |
| US09344031B2 |
Concentrator-driven, photovoltaic power generator
A concentrator-driven, photovoltaic power generator system and method for capturing and transmitting electromagnetic radiation utilizing a reflector having a concave reflecting surface for concentrating electromagnetic radiation to a focal point. |
| US09344030B2 |
Solar cell module, and production method for solar cell module
A solar cell module is configured from a solar cell panel, and a frame structural body. The frame structural body is provided with: a plurality of frame members which are provided to peripheral edges of the solar cell panel, and which have a cross-sectional shape having a hollow portion; corner members which are provided in the hollow portions; holding sections which are provided in the hollow portions, and which hold the corner members; and a plurality of formed rivet sections which apply pressure to the frame members. |
| US09344029B2 |
Asynchronous motor unit comprising a frequency converter with electrical isolation in the DC voltage intermediate circuit
The invention relates to an asynchronous motor unit including a frequency converter for regulating the asynchronous motor. The frequency converter comprises an input-side, uncontrolled bridge rectifier, a DC voltage intermediate circuit and an output-side inverter. According to the invention, the DC voltage intermediate circuit furthermore comprises a DC-to-DC converter with galvanic isolation, with the result that electrical isolation between the bridge rectifier and the inverter is produced. |
| US09344023B2 |
Motor device
A motor device includes a motor unit and a converter unit. The motor unit includes an inverter circuit; an inverter drive circuit; a brushless DC motor comprising a rotor and a stator; a first shunt resistor; a first input terminal; a second input terminal; a third input terminal; a first output terminal; and a first ground terminal. The converter unit includes a case; a AC/DC converter; a microcomputer; a first output terminal; a second output terminal; a third output terminal; a first input terminal; a second shunt resistor; and a second grounding terminal. The microcomputer calculates a current value by using the terminal voltage and a resistance value of the second shunt resistor, compares the current value with a specified current value, and limit or cut off the output of the analog control signal when the current value exceeds the specified current value. |
| US09344022B2 |
Circuits and methods for driving resonant actuators
The present disclosure includes circuits and methods for driving resonant actuators. In one embodiment, a drive signal is applied to an actuator during a portion of a plurality of half cycles of a period of the drive signal. The actuator has a resonant frequency and may vibrate in response to the drive signal. An induced voltage is generated on terminals of the actuator in response to the vibration. A detection circuit may detect when the induced voltage on the actuator crosses a threshold after the drive signal is turned off. The drive signal may be triggered based on when the induced voltage crosses the threshold to align a frequency and phase of the drive signal with the resonant frequency and a phase of the actuator. |
| US09344020B2 |
Power conversion apparatus and electrical-mechanical energy conversion system
A power conversion apparatus includes arms in each of which one or more unit converters each including a capacitor and capable of outputting an arbitrary voltage are connected in series, and a point P as a first node to which one end of the respective arms are Y-connected, and a point N as a second node to which a neutral terminal of the rotary electric machine is connected. The other end of the respective arms are connected to one ends of respective phase windings of a rotary electric machine. |
| US09344018B2 |
Method for making a motor quieter
The method is for making a brushless direct-current (DC) motor quieter. A predetermined high frequency pulse width modulated (PWM) signal is generated. The PWM signal is sent to a first filter. The first filter truncates the PWM signal to provide the PWM signal with a rise time. The rise time allows transistors connected thereto to open smoothly. A second filter is provided that has a non-polarized capacitor. In a coil switching process, the non-polarized capacitor operates as a voltage or current absorption circuit between driving transistors. The coil switching process creates transient energy of voltage transients. The non-polarized capacitor absorbs the transient energy. |
| US09344011B2 |
Systems and methods for generating power for an electric sub-assembly of a motor vehicle
A system for generating power for an electric sub-assembly of a motor vehicle may include at least one reverse electrowetting energy harvesting element coupled to a tire of the motor vehicle. The system may further include at least one controller configured to accumulate electric energy generated by the at least one reverse electrowetting energy harvesting element and supply the accumulated electric energy to at least one sub-assembly mounted on the tire. |
| US09344007B2 |
Auxiliary resonant commutated pole converter with voltage balancing circuit
A resonant power converter is provided. The resonant power converter comprises a balancing circuit for balancing the voltage in a feeding connection. The balancing circuit comprises: a first positive control means in series with an inductor, wherein the first positive control means and the inductor is coupled between the positive DC conductor and the feeding connection, and a second negative control means in series with the inductor, wherein the second negative control means are coupled between the negative DC conductor and the feeding connection. The first positive and second negative control means are adapted to be alternatingly switched on and off for balancing the resonant power converter, such that the voltage in the feeding connection is substantially the mean voltage of the positive DC conductor and the negative DC conductor. |
| US09344006B2 |
Driving circuit for a transistor
In various embodiments, a driving circuit for a transistor is provided, wherein the transistor may include a transistor having a control terminal, a diode, a capacitance with a first terminal and a second terminal, wherein the first terminal may be coupled to the control terminal and the second terminal may be coupled to a reference potential via the diode, and a resistor, which is coupled in parallel to the capacitance. |
| US09344005B2 |
Method and apparatus for producing three-phase current
Exemplary embodiments are directed to methods and systems for producing a three-phase current to a three-phase output. Switching converters are used to generate a positive current, a negative current, and an intermediate current. The system is configured such that the produced positive current follows a path of a highest phase of a sinusoidal three-phase signal at a given time, the produced negative current follows a path of a lowest phase of the three-phase signal at the given time, and the produced intermediate current follows a path of a phase of the three-phase signal between the highest and the lowest phase at the given time. The produced currents are switched to each phase conductor of the three-phase output in sequence so that phase currents of the three-phase current are formed in the output conductors. |
| US09344000B2 |
Power module varying bias power and distributed power supply apparatus
There are provided a power module in which a bias voltage is varied and supplied to a control circuit controlling power conversion when an idle mode is switched to a normal mode, and a distributed power supply apparatus having the same. The power module includes: a power factor correction stage; a DC/DC conversion stage switching power to convert the power into pre-set DC power in a powering mode in which normal power is output; a standby stage converting the power into pre-set standby power in a cold standby mode in which the DC/DC conversion stage outputs power having a level lower than that of normal power; and a variable bias supply unit varying a voltage level of bias power for controlling DC/DC power conversion and supplying the same to the DC/DC conversion stage in the cold standby mode and the powering mode. |
| US09343998B2 |
Load control device for high-efficiency loads
A two-wire load control device (such as, a dimmer switch) for controlling power delivered from an AC power source to an electrical load (such as, a high-efficiency lighting load) includes a thyristor coupled between the source and the load, a first circuit coupled between a first main terminal and a gate terminal of the thyristor to conduct current through the gate terminal, a second circuit coupled between the first main terminal and a second main terminal of the thyristor to conduct current through the load when the thyristor is non-conductive, and a control circuit configured to individually control the first and second circuits. The control circuit renders the first circuit conductive to conduct a pulse of current through the gate terminal to render the thyristor conductive at a firing time, and allows the first circuit to conduct at least one other pulse of current through the gate terminal after the firing time. |
| US09343993B2 |
DC/AC converter and method of controlling a DC/AC converter
A DC/AC converter includes a DC/DC conversion stage with galvanic isolation and a DC/AC conversion stage, wherein the DC/DC conversion stage comprises a pair of first side terminals providing or receiving a first DC voltage, a pair of second side terminals providing or receiving a second DC voltage and coupled to the DC/AC conversion stage, at least one first side converter circuit coupled between the pair of first side terminals, a series connection of a plurality of second side converter circuits coupled between the pair of second side terminals, and at least one transformer circuit coupling the plurality of second side converter circuits to the at least one first side converter circuit, wherein a connection point between two of the plurality of second side converter circuits is coupled to the DC/AC conversion stage and forms a neutral phase point thereof. |
| US09343988B2 |
Current mode regulator
Circuits, systems, and methods of current mode regulation include a primary side for receiving an input signal and a secondary for outputting an output signal. A regulator spans the primary and secondary sides in a configuration by which the input signal may be rectified and thereafter provided to the output node as an output signal. A current monitor is provided at the output node for comparing the output signal to a reference. A communication link is included for providing feedback to the primary side of the regulator for use in regulating the signal. |
| US09343986B2 |
Power converter with current feedback loop
In a power converter, a driver drives a switching element using a manipulated variable therefor to convert input power into output power. A first measuring unit measures a value of a first electric parameter depending on the input power. A first determiner determines, from the measured value of the first electric parameter, a first feedback controlled variable. A second measuring unit measures a value of a second electric parameter indicative of the output power, and a calculator calculates, based on the measured value of the second electric parameter and a command value for the second electric parameter, a second feedback controlled variable. A selector selects, based on the measured value of the first electric parameter, one of the first feedback controlled variable and the second feedback controlled variable. A second determiner determines the manipulated variable using the selected one of the first and second feedback controlled variables. |
| US09343981B2 |
Charging device for charging a battery pack
A charging device for charging a battery pack, having a control circuit for a switched-mode power supply transformer assigned to the charging device, the transformer having at least one primary winding switchable using a power switch and at least one first secondary winding for generating an electrical output voltage for charging the battery pack, the output voltage having a first amplitude which is predefinable by a control unit and adjustable using a first voltage limiting control loop. The transformer has at least one second secondary winding for generating at least one electrical auxiliary voltage having a second amplitude which is predefinable by the control unit and adjustable using a second voltage limiting control loop in order to at least reduce an energy feed assigned to an operation of the control circuit from the primary winding to the secondary windings in a standby mode of the control circuit. |
| US09343971B2 |
Synchronous VCC generator for switching voltage regulator
A capacitor is charged synchronously with the beginning of an ON portion of a pulse width modulated (PWM) signal to generate a voltage across the capacitor using charging current sourced from an inductor on a primary side of a transformer. The voltage is supplied as a supply voltage to control circuitry in an integrated circuit used to generate the pulse width modulated signal. The charging is stopped when either the charging current goes above a predetermined charging current level or when the capacitor voltage goes above a predetermined capacitor voltage. |
| US09343970B2 |
Converter and method for reducing a voltage of node thereof
A converter and method for reducing voltage of node thereof are disclosed herein. The converter includes a first transmitting circuit and a second transmitting circuit. The first transmitting circuit is configured to receive a first AC voltage. The second transmitting circuit is electrically coupled to the first transmitting circuit and the second transmitting circuit is configured to transmit a second AC voltage according to the first AC voltage. One of the first transmitting circuit and the second transmitting circuit includes at least one divider unit and the other one of the first transmitting circuit and the second transmitting circuit includes at least two divider units. Each of the divider units includes an inductor network and a capacitor network coupled in series. The inductor network and the capacitor network of the adjacent divider units are coupled in series alternately. |
| US09343964B2 |
I2 average current mode (ACM) control for switching power converters
Providing a fast current sensor direct feedback path to a modulator for controlling switching of a switched power converter in addition to an integrating feedback path which monitors average current for control of a modulator provides fast dynamic response consistent with system stability and average current mode control. Feedback of output voltage for voltage regulation can be combined with current information in the integrating feedback path to limit bandwidth of the voltage feedback signal. |
| US09343961B1 |
Ultrahigh voltage charge pump apparatus implemented with low voltage technology
An charge pump architecture capable of generating ultra high DC voltages but implemented in low voltage CMOS technology uses a cascade of NMOS stages with the bulk terminal of the latter stages biased to a voltage just below the reverse breakdown of the parasitic bulk diode. The bias voltage is tapped from a lower voltage point within the charge pump. The upper limit of the output voltage is then increased to the maximum allowable oxide voltage plus the parasitic diode reverse bias breakdown voltage. |
| US09343958B2 |
Voltage regulator devices and voltage regulating method
Various embodiments provide voltage regulator circuitry and devices. An exemplary voltage regulator circuitry can include a current comparing unit configured to convert an output voltage from a charge pump to a current and to compare the current with at least two different reference currents to generate a comparison result. A logic controller can be configured to generate a clock frequency adjustment signal based on the comparison result. A programmable clock unit can be configured to adjust a frequency of a clock signal according to the clock frequency adjustment signal to send the clock signal to the charge pump. Accordingly, the disclosed voltage regulator device can have reduced power consumption and improved reliability. |
| US09343956B2 |
Passive power factor correction circuit, electronic device applying the same and operation methods thereof
A passive power factor correction circuit includes: a DC capacitor and an input capacitor, coupled to a rectifying circuit and charged by a DC voltage from the rectifying circuit; an output capacitor, coupled to a load; first diode and a second diode, coupled to the input capacitor and the output capacitor; and an inductor, coupled to the load, the input capacitor and the output capacitor. Charging into and discharging from the DC capacitor are completed within a half cycle of an input AC voltage. |
| US09343954B2 |
Multi-input DC converter and PFC circuit
The application discloses a multi-input DC converter and a PFC circuit. The multi-input DC converter of the application includes n diodes, a transformer, a switching transistor, a rectifier and filter circuit, and a load. The transformer includes a primary winding and a secondary winding, the number of turns of the primary winding is N1, and the primary winding is divided into n sections by leading out n−1 taps in a specific manner; anodes of the n diodes are respectively connected to n input sources in turn, cathodes of the n diodes are respectively connected to a first terminal of the primary winding and n−1 tap terminals in turn, a second terminal of the primary winding is grounded through the switching transistor, and the secondary winding delivers energy to the rectifier and filter circuit and then to the load. The structure is simple, and the cost is low. |
| US09343953B2 |
Pre-distortion of sensed current in a power factor correction circuit
An example controller includes a power factor enhancer, an on-time controller, and a switching signal generator. The power factor enhancer is coupled to generate a pre-distortion signal each half-line cycle of an ac input voltage of a PFC converter. The on-time controller ends an on-time of a PFC switch in response to a sensed PFC switch current of the PFC converter multiplied by the pre-distortion signal. The switching signal generator controls an input current waveform of the PFC converter to substantially follow a shape of an input voltage waveform by generating a switching signal in response to the on-time controller to control switching of the PFC switch. The power factor enhancer adjusts the pre-distortion signal to pre-distort the sensed PFC switch current to compensate for distortion in the input current waveform. |
| US09343944B2 |
Stator for electric rotary machine
A stator for an electric rotary machine includes: a stator core having a plurality of slots; and segmented coils of a plurality of phases, wherein: the segmented coils of a plurality of phases have pluralities of coil bars which are inserted individually in the plurality of slots in the stator core and which extend substantially in a straight line and pluralities of connection coils which connect together the coil bars of the same phase to thereby make up extending portions; and the coil bars are fixed in place individually in the slots in the stator core in such a state that the coil bars each are covered by an insulation material. |
| US09343938B2 |
Armature winding of rotating electrical machine
According to one embodiment, there is provided a 3-phase 2-pole 2-layer armature winding, housed in 72 slots provided in a laminated iron core, a winding of each phase including six parallel circuits separated into two phase belts. Upper coil pieces of first and fourth parallel circuits are placed at 3rd, 4th, 7th, and 12th positions, and lower coil pieces of the first and fourth parallel circuits are placed at 1st, 6th, 9th, and 10th positions, upper and lower coil pieces of second and fifth parallel circuits are placed at 2nd, 5th, 8th, and 11th positions, and upper coil pieces of third and six parallel circuits are placed at 1st, 6th, 9th, and 10th positions, and lower coil pieces of the third and six parallel circuits are placed at 3rd, 4th, 7th, and 12th positions, from the center of a pole. |
| US09343937B2 |
Rotary electric machine equipped with rotor core of step skew structure
In a rotary electric machine having a rotor core of a skew structure, when one of the core blocks is sequentially stacked on the other of the core blocks to form a step skew, a communication reference groove is formed along an axial direction of the rotor core by aligning a side section of a short protruding section in one core block with a side section of the long protruding sections in the other core block, and by aligning a side section of a long protruding section in one core block with a side section of a short protruding section in the other core block. The core blocks are correctly stacked by aligning the side section of the long protruding sections with the side section of the short protruding sections. |
| US09343936B2 |
Rotor for an electric machine
A rotor for an electric machine has a rotor member extending circumferentially about the axis of rotation of the rotor, and a locking device in an axial end region of a guide to mount permanent magnets in the direction of the axis of rotation of the rotor. The locking device is retained on the rotor member in the radial direction and in the direction of rotation of the rotor by guides. The locking device has a movable movement element and is designed such that when the movement element is moved, the locking device is positively or non-positively connected to the rotor member. |
| US09343934B2 |
Electric motor
An electric motor has a wound stator and a permanent magnet rotor. The rotor includes a shaft, a hub fixed on the shaft, a plurality of rotor core segments and magnets fixed around the hub. The rotor core segment includes at least two rotor blocks inwardly extending from the innermost portion thereof. The hub includes a plurality of hub blocks equidistantly and outwardly extending from the outer surface thereof. The rotor blocks of each rotor core segment engage with at least one hub block to fix the rotor core segment to the hub. The number of rotor blocks is greater than the number of hub blocks. |
| US09343930B2 |
Segmented stator assembly
A stator has a plurality of segments connected with connectors to define a core for the stator. Each of the segments comprises a plurality of laminations arranged side by side forming a lamination stack with axially opposite sides. The lamination stack has an end cap abutting an axial side of the lamination stack. The end cap has first and second posts extending axially therefrom. At least one of the posts defines a wire path for wire wound around the stack. Each of the connectors comprises a bridge portion. The bridge portion has openings dimensioned to receive the posts in a manner that the connector is removably attachable to the post of the end cap of a segment and the post of the end cap of an adjacent segment. The connector has an insulator portion projecting from the bridge portion. The insulator portion extends between adjacent segments. |
| US09343929B2 |
Dual mode wireless power receiver
A dual mode wireless power receiver (DMWPR) selectively applying a received power to a load device and utilizing at least a part of the power to power-up, communicate, and charge a secondary wireless power receiver (SWPR) is provided. The DMWPR includes a first circuitry having an impedance network, a switch network, a filter capacitor, and one or more switches, and a second circuitry having a security engine, a control logic circuit, and a modulator/demodulator circuit. The first circuitry receives power in charging mode and transmits power in communication mode. The second circuitry configures the first circuitry to allow receipt and transmission of power, receives and interprets data from SWPR in the identified wireless power protocol, and based on the type of SWPR authenticates, decrypts, and encrypts data transfer between DMWPR and SWPR, and receives and executes on a request from SWPR to perform a function associated with transmitted power. |
| US09343928B2 |
Wireless power transmitter, wireless power receiver, and method of wirelessly receiving power
Disclosed are a wireless power transmitter, a wireless power receiver, and a method of wirelessly receiving power. The wireless power receiver includes a receiving unit receiving the power from the wireless power transmitter using resonance, and a rectifying unit rectifying the power received therein from the receiving unit to supply the power to a load side. The rectifying unit changes an output impedance of the wireless power receiver in order to change an input current of the wireless power transmitter. |
| US09343923B2 |
Implantable medical device with backscatter signal based communication
An implantable medical device is disclosed that includes a charging coil configured to inductively couple to a first external coil to receive a charging signal to charge a charge storage element of the implantable medical device. The implantable medical device also includes a circuit coupled to the charging coil. The circuit includes a circuit component that, in response to the charging signal, generates a backscatter signal. The implantable medical device also includes a communication coil orthogonal to the charging coil and coupled to the circuit component. The communication coil is configured to inductively couple to a second external coil to communicate the backscatter signal to the second external coil. |
| US09343918B2 |
Balancing apparatus, balancing method, and battery module
According to an example embodiment, a balancing apparatus includes: bi-directional switches that are respectively connected to cells that are connected in series, a controller configured to measure voltages of the cells, and a multiwinding transformed connected to the bi-directional switches. The bi-directional switches are configured to control a flow of an electric current bi-directionally. The controller is configured to select a number of the cells for balancing based on the measured voltages of the cells. The controller is configured to turn on and turn off the bi-directional switches that are connected to selected cells based on the measured voltages. The multi-winding transformer is configured to transfer energy between the cells when the bi-directional switches connected to the selected cells are turned on. |
| US09343914B2 |
System and method for charging the energy storage cells of an energy storage device
The invention relates to a method for charging the energy storage cells of an energy storage device, which comprises: n first output connections, wherein n>1, for issuing a supply voltage at each of the output connections, a second output connection, wherein a charging device can be connected between the first output connections and the second output connection, and n parallel-connected energy supply branches, which are each coupled between a first output connection and the second output connection, wherein each of the energy supply branches comprises a plurality of series-connected energy storage modules, which each comprise an energy storage cell module comprising at least one energy storage cell, and a coupling device having coupling elements that are designed to selectively connect or bridge the energy storage cell module in the respective energy supply branch. The method according to the invention comprises the following steps: determining a maximum possible charging voltage of a charging apparatus, which provides a charging voltage for the energy storage device; determining the maximum number of the energy storage cell modules of an energy supply branch at which the sum of the output voltages of the energy storage cell modules, which is dependent on the instantaneous charge states of the energy storage cells of all the energy storage cell modules of an energy supply branch, is still lower than the maximum possible charging voltage; and selecting and controlling the coupling elements of energy storage modules of the energy supply branch, such that in each case only the maximum number of energy storage cell modules is coupled into the energy supply branch. |
| US09343911B2 |
Response to detection of an overcharge event in a series connected battery element
A system and method for identifying and responding to exceptional charge events of series-connected energy storage elements can include: a first charge imbalance detection system monitoring, using the microprocessor, the energy storage system for a charge imbalance using a first detection modality, said first charge imbalance detection system initiating a reduction of said charge imbalance using a first response modality; a second charge imbalance detection system monitoring, using the microprocessor, the energy storage system for an exceptional charge event of a particular one battery element of the plurality of battery elements using a second detection modality different from said first detection modality; and a remediation system initiating a response to said exceptional charge event using a second response modality different from said first response modality, said response decreasing a risk associated with said exceptional charge event. |
| US09343906B2 |
High dynamic DC-voltage controller for photovoltaic inverter
A method for initializing a power inverter of a photovoltaic system includes: opening an AC mains switch and a DC switch to disconnect the power inverter from an electrical grid and to disconnect a capacitor bank associated with the inverter from a solar cell array; closing the AC mains switch to allow power to flow from an electrical grid to the DC capacitor bank to charge the DC capacitor bank; monitoring the DC capacitor bank until a desired voltage is reached; initiating the operation of the power inverter; stabilizing the DC voltage received from the DC capacitor bank at a predetermined power up voltage for the power inverter; waiting for an inverter initialization period to elapse; and adjusting DC voltage received by the power inverter to a voltage associated with a maximum power output level of the solar cell array. |
| US09343905B2 |
Power control device, power management device and power management system
A power control device forms energy storage equipment together with a storage battery. The power control device includes: a communication portion that communicates with a power management device, which manages charge and discharge of the storage battery; a power conditioner that supplies electricity to a predetermined destination for supply; a control portion that controls operation of the power conditioner based on instructions from the power management device that are received by the communication portion; and an authentication processing portion that performs authentication processing with the power management device. |
| US09343900B2 |
Passive network for electrostatic protection of integrated circuits
Embodiments of the invention provide an electrostatic discharge protection device or network for an integrated circuit. The network includes a first circuit branch and a second circuit branch connected in a parallel configuration. The first branch has a first inductance, a first resistance, and includes a first capacitive component. The second branch has a second inductance, a second resistance, and includes a second capacitive component. A first end of the first circuit branch and a first end of the second circuit branch are coupled to a first node, and a second end of the first circuit branch and a second end of the second circuit branch are coupled to zero-voltage reference level. The network is capable of providing a low impedance path away from a terminal of the integrated circuit during an electrostatic discharge event. |
| US09343898B2 |
Driver current control apparatus and methods
Apparatus and methods disclosed herein implement steady-state and fast transient electronic current limiting through power transistors, including power transistors used as pass elements associated with general purpose drivers. Embodiments herein prevent excessive steady-state current flow through one or more driver pass elements and/or through load elements in series with the pass element(s) via a current sensing and driver preamplifier feedback loop. A transient over-current protection circuit includes a fast transient switch and a transient over-current control circuit. The transient over-current control circuit rectifies one or more transient voltage spikes to create a momentary direct current (DC) voltage power supply (MVS) to power a fast transient driver circuit and to trip the fast transient switch. The fast transient switch discharges a transient pass element input voltage (e.g., a gate voltage on a MOSFET power transistor in some embodiments) and terminates current flow through the pass element current channel. |
| US09343891B2 |
Gel sealing device
The present invention relates to a gel sealing device for sealing a passage of elongate parts through an opening. Such gel sealing device is preferably arranged in a housing used in telecommunication technology. The present invention solves the problem of providing a gel sealing device having improved cable access properties. The inventive gel sealing device comprises a gel sealing block (5) which provides a sealing section (22) through which the elongate parts (13, 14) extend, wherein the gel sealing block (5) comprises an upper flange (11) and a lower flange (12) with a support section (11a, 12a, 12b) disposed therebetween. The upper and lower flanges (11, 12) sandwiches in direction of extension of the elongate parts (13, 14), a gel inner ring (7) supported by said support section (2) and a gel outer ring (6, 10a) covering the gel inner ring (7) in a radial direction extending transverse to said extension direction. The gel inner ring (7) and the gel outer ring (6, 10a) are made of a gel sealing material, wherein the sealing section (22) is formed therebetween. The gel outer ring (6, 10a) comprises a first circumferential segment (6) and at least one second circumferential segment (10a) which is adapted to be detachable from the first circumferential segment (6) to provide a separate accessible sealing section. |
| US09343890B2 |
Electrical cable restrain device using a double wedge chuck
A cable fitting includes a gland nut, a body, and a chuck. The gland nut includes first threads, an axial gland bore, and a first sloped surface along a portion of the axial gland bore. The body includes second threads to receive the first threads, an axial body bore, and a second sloped surface along a portion of the axial body bore. The chuck includes multiple segments joined in a hinged fashion to create a ring. Each of the multiple segments includes a distal end tapered surface and a proximal end tapered surface. When the gland nut is advanced onto the body, the first sloped surface applies a first compressive force to the distal end tapered surfaces, and the second sloped surface applies a second compressive force to the proximal end tapered surfaces. The compressive forces cause inward deformation of the chuck to secure a cable within an axial pathway. |
| US09343888B2 |
Arrangement and method for locking an automatic reeling mechanism of a charging cable for an electric vehicle
An automatic reeling mechanism for an electric vehicle or a charging post can automatically reel a charging cable and thus protect it against dirt and weather. In order to reduce mechanical loads and damage to the plug and minimize a risk for stumbling to a person, the automatic reeling mechanism is switched in a passive mode as long as a plug of the charging cable is plugged in and is not touched by a person. This is the case during the charging process. In this way, the automatic reeling mechanism can be comfortably used because no traction forces are active during the charging process and the charging cable can be laid out so that there is no risk of stumbling. |
| US09343880B2 |
Modular subsea electrical distribution system having subsea cable harness assembly and method for assembling same
A system and method for coupling electrical power subsea. The system comprises a subsea electrical distribution system having at least one modular subsea circuit breaker assembly. The modular subsea circuit breaker assembly may be coupled to sources of power and/or subsea loads via one or more subsea power cable harness assemblies. The modular subsea circuit breaker assembly has at least electrical connector. Each subsea power cable harness assembly has a corresponding electrical connector. At least one of these electrical connectors is extendable to engage an electrical connector opposite it. |
| US09343878B2 |
Manufacturing method of main metal fitting for spark plug and manufacturing method of spark plug
A metallic shell extends in the direction of an axial line and has a threaded portion on its outer circumferential surface for threading engagement with a mounting hole of a combustion apparatus. A process of manufacturing the metallic shell includes a step of forming a metallic shell tubular intermediate having the first tubular portion and the second tubular portion and a rolling step of forming the threaded portion on the metallic shell tubular intermediate. In the rolling step, a bearing member is inserted into the metallic shell tubular intermediate for nipping the metallic shell tubular intermediate in cooperation with working surfaces of the rolling dies, and rolling is performed simultaneously on at least the first tubular portion and the second tubular portion. |
| US09343872B2 |
Optical amplification device and optical amplification method
An optical amplification device includes: a port group that has a plurality of ports that have a semiconductor optical amplifier and a port that does not have a semiconductor optical amplifier, an optical burst signal being input into each of the ports at a different timing; and a control unit, wherein: when an optical inputting into the port that has the semiconductor optical amplifier is detected, the control unit activates the semiconductor optical amplifier of the port where the optical inputting is detected, inactivates the other semiconductor optical amplifier and remains an activation until another optical inputting is detected in another semiconductor optical amplifier; and when an optical inputting into the port that does not have the semiconductor optical amplifier is detected, the control unit inactivates the semiconductor optical amplifiers of the plurality of the ports that have the semiconductor optical amplifier. |
| US09343871B1 |
Facet on a gallium and nitrogen containing laser diode
Nonpolar or semipolar laser diode technology incorporating etched facet mirror formation and conventional optical coating layer techniques for reflectivity modification to enable a method for ultra-high catastrophic optical mirror damage thresholds for high power laser diodes are disclosed. |
| US09343870B2 |
Semiconductor laser diode with integrated heating region
A semiconductor laser diode with integrated heating generally includes a lasing region and a heating region integrated into the same semiconductor structure or chip. The lasing region and the heating region include first and second portions, respectively, of the semiconductor layers forming the semiconductor structure and include first and second portions, respectively, of the active regions formed by the semiconductor layers. Separate laser and heater electrodes are electrically connected to the respective lasing and heating regions for driving the respective lasing and heating regions with drive currents. The heating region may thus be driven independently from the lasing region, and heat may be conducted through the semiconductor layers from the heating region to the lasing region allowing the temperature to be controlled more efficiently. |
| US09343869B1 |
Mode-hop tolerant semiconductor laser design
Described herein are methods, systems, and apparatuses to utilize a laser device comprising a gain section, a wavelength filter, a first reflector, and a second reflector to form a laser cavity with the first reflector, the laser cavity to include the gain section and the wavelength filter. The wavelength filter is temperature stabilized to a predetermined temperature range and the remaining portions of the laser cavity are not temperature stabilized. The wavelength filter, when at the predetermined temperature range, comprises a plurality of adjacent longitudinal modes such that a difference in modal gain values associated with each of the adjacent longitudinal modes is within a predetermined delta. Thus, the cavity of the laser device is designed to experience some mode hops when the device temperature changes; however, because the wavelength filter is stabilized in temperature, the cavity drift due to these mode hops is within a limited range. |
| US09343866B2 |
Optical pumping structure
An optical pumping structure for lasers includes: an active medium in the form of a cylindrical rod with a circular cross-section, said rod being inserted at its ends into two rings made of a thermally conductive material; at least three stacks of pumping diode strips arranged in the form of a star around the rod; and a support temperature-regulated by a Peltier-effect module. The rings are in contact with the support, and a stack of diodes, called bottom stack, being situated between the rod and the support, and the structure comprises, for each other stack, a thermal conduction block forming a support for said stack, these blocks being mounted on the cooled support and not being in contact with one another or with the rings. |
| US09343853B2 |
Solenoid
A clip installation seat of a holder, which is installed to an outer surface of a yoke, includes a recessed slope surface that is sloped in such a manner that an amount of recess of a radially-inner-side section of the recessed slope surface is larger than an amount of recess of a radially-outer-side section of the recessed slope surface. A clip includes an engaging hole, which is press fitted to an outer peripheral surface of a positioning projection projected from the outer surface of the yoke, and a radially-inner-side engaging portion, which resiliently contacts the outer peripheral surface of the positioning projection. The clip includes a radially-outer-side engaging portion that is configured into a form of a loop and is placed at a radially-outer-side area of the clip. The radially-outer-side engaging portion resiliently contacts the recessed slope surface. |
| US09343851B2 |
Pluggable connector configured to transfer thermal energy away from internal electronics of the pluggable connector
Pluggable connector including a connector housing having a leading end configured to mate with a receptacle assembly. The connector housing has an interior cavity. The pluggable connector also includes a communication assembly held by the connector housing. The communication assembly includes internal electronics located within the interior cavity, and a mating terminal located proximate to the leading end. The mating terminal is communicatively coupled to the internal electronics. The pluggable connector also includes a thermal-transfer assembly that is disposed within the interior cavity. The thermal-transfer assembly includes first and second thermal-transfer modules that each include a plurality of spaced-apart projections. The corresponding projections of the first and second thermal-transfer modules are interleaved with one another. The first thermal-transfer module is coupled to the internal electronics, and the second thermal-transfer module is coupled to the connector housing. |
| US09343847B2 |
Mating coaxial connectors having anti-rotational features
An electric connector includes a first housing including a guide shaft and a second housing including a guide hole into which the guide shaft is inserted. The guide shaft includes a main body, and a projection radially projecting from the main body, the guide hole being formed at an inner surface thereof with a groove into which the projection is fit. The projection and the groove are formed such that a first imaginary line intersects with a second imaginary line, the first imaginary line being defined by extending a contact plane at which the projection and the groove make contact with each other when the first housing rotates relative to the second housing, towards a center of the main body. The second imaginary line is defined as a line bisecting a top surface of the projection and extending towards a center of the main body. |
| US09343846B2 |
Connector unit
A connector unit for connecting at least two cables includes at least a male part, a female part, and a shuttle piston. The shuttle piston includes an opening configured for receiving at least a section of the male part, at least one latching device, and at least one latching structure. The male part includes the section configured for insertion into the opening of the shuttle pin, at least one latching aid, and an interaction area configured for a force-fitting interaction with at least one backing latch of the female part. The female part includes the at least one backing latch. |
| US09343842B2 |
Connector
A connector includes a housing which accommodates terminals connected to end portions of wires therein and which has locking pawls on an exterior surface of the housing; a rear holder having locking frames which are locked with or unlocked from the locking pawls by elastic deformation, in which the rear holder is mounted on a back side of the housing, and prevents rubber plugs that contact an outer periphery of the wires from dropping off the housing; and a shield shell mounted on an outer periphery of the housing to which the rear holder has been mounted. The shield shell includes a rear end portion which is arranged at an elastic deformation region of the locking frames in an assembling process of the rear holder to the housing and obstructs the elastic deformation of the locking frames. |
| US09343840B2 |
Interface connector
An interface connector includes a housing, a plurality of contacts, and a square tube shaped shell. The housing integrally forms a header portion and a frame portion. The plurality of contacts is arranged in parallel on one face of the header portion, the shell is attached so as to cover an outer face of the housing. The shell includes a highly solderable layer formed on an inner face and an outer face including a plate-thickness face thereof, a pair of locking strips soldered to the printed circuit board, and an opening portion that is exposed outward and through which a counterpart housing is inserted and extracted, the opening portion including an end part (a plate-thickness face) of the opening portion which is turned black by laser irradiation. |
| US09343839B2 |
Wall-mount box with isolated interior regions
Certain types of wall-mount boxes provide a local power receptacle in a first interior region that is physically isolated from a second interior region. The local power receptacle is accessible from an exterior of the box. The local power receptacle is electrically connected to an internal connector interface that is accessible from the second interior region. An electronic device may be installed in the second interior region and electrically connected to the local power receptacle via the internal connector interface. Second receptacles are disposed in the second interior region and coupled to (or are integral with) the electronic device. The second receptacles are accessible from the exterior of the box. |
| US09343834B2 |
Header, receptacle, connector, and method of manufacturing the header
A disclosed header connectable to a receptacle includes a first contact including a pair of first plate portions, which are electrically conductive and are separated by an interval, and a plate-like conductive member which is conductive and is accommodated between the pair of first plate portions. |
| US09343820B2 |
Crimp contact and cable assembly including the same
Cable assembly including an electrical wire and a crimp contact engaged to a terminal end of the electrical wire. The crimp contact has a centerline and first and second sidewalls that extend from the centerline in opposite directions. The centerline extends parallel to a longitudinal axis of the crimp contact. Each of the first and second sidewalls has a base section and a leg section. The leg section extends a lateral distance from the centerline to a longitudinal edge of the leg section. The base section extends a lateral distance from the centerline to a longitudinal edge of the base section. The lateral distance of the leg section is greater than the lateral distance of the base section for each of the first and second sidewalls. The leg sections of the first and second sidewalls are located opposite the base sections of the second and first sidewalls, respectively. |
| US09343817B2 |
Conformal mm-wave phased array antenna with increased scan coverage
A system according to one embodiment includes a phased array antenna comprising a plurality of slot loop antenna elements, the plurality of slot loop antenna elements configured in a planar array disposed on a flexible dielectric substrate, wherein each of the plurality of slot loop antenna elements generates a beam pattern orthogonal to the plane of the planar array; and driver circuitry coupled to each of the plurality of antenna elements, wherein the driver circuitry comprises a plurality of transceivers, the plurality of transceivers configured to provide independently adjustable phase delay to each of the plurality of slot loop antenna elements. |
| US09343810B2 |
Method of making an extremely low profile wideband antenna
A very low profile wideband antenna adapted to operate from 30 MHz to 300 MHz or in another desired range. The maximum diameter and height of one embodiment of this antenna is only 60.96 cm and 5.08 cm, respectively. This design is comprised of a fat grounded metallic plate placed 5.08 cm over a ground plane. In one embodiment, ferrite loading strategically placed between the plate and ground plane improves the low frequency gain and the pattern at high frequencies. A minimal amount of ferrite may be used to keep weight low. |
| US09343808B2 |
Multi-beam MIMO time division duplex base station using subset of radios
A system and method may include a plurality of transmit and receive antennas covering one sector of a cellular communication base station; a multi-beam RF beamforming matrix connected to the transmit and receive antennas; a plurality of radio circuitries connected to the multi-beam RF beamforming matrix; and a baseband module connected to the radio circuitries. The multi-beam RF beamforming matrix may be configured to generate one sector beam and two or more directional co-frequency beams pointed at user equipment (UEs) within the sector, as instructed by the baseband module. A number M denotes the number the directional beams and a number N denotes the number of the radio circuitries and wherein M>N. |
| US09343803B2 |
Rearview mirror device integrating a radio-frequency reception system
The invention relates to a rearview mirror device for vehicles incorporating a radio-frequency reception system. The rearview mirror device comprises: a light-reflective surface made of an electrically conductive material, and at least one planar conductive element lying on a plane substantially parallel to said reflective surface. The light-reflective surface and said conductive element are capacitively coupled and are used in combination for the reception of radio-frequency signals. The invention provides a rearview mirror with great simplicity and very-low cost. |
| US09343799B2 |
Clamp device for mounting antenna to rail
A device for mounting an antenna to a rail is provided. The device includes a first clamp member and a second clamp member. The first clamp member includes a planar base plate having a first surface and a second surface. The planar base plate has at least two slots spaced apart on a longitudinal axis. At least two extension sections extend from the first surface of the planar base plate and being spaced apart along the longitudinal axis and closer to a center than the at least two slots. Each extension section includes a patterned cutout area configured to receive the rail. A plurality of threaded fasteners extend from the first surface of the planar base plate and being positioned outside the patterned cutout area along a transverse axis perpendicular to the longitudinal axis. The second clamp member has a plurality of through-holes configured to receive the plurality of threaded fasteners and a planar surface facing toward the first surface of the first clamp member. |
| US09343798B2 |
High performance (mini-cube) indoor HDTV antenna
This invention discloses a design and fabrication of a high performance compact antenna to receive public airwaves HDTV signals. The subject antenna consists of a high efficient cone shape broadband element excited over a small metal ground plane. A reflecting surface is implemented to help rejecting any unwanted multiple reflecting signals from the surrounding objects. Outstanding impedance characteristics and broad pattern coverage have been obtained. The pattern coverage is omnidirectional. The polarization is linear along the cone axis. This antenna design operates well in a weak signal environment and as a result the antenna can receive a large number of public channels. Although the antenna measures only 5¾×5¾×3¼ inches in a cubical enclosure or in a 6⅜ inches diameter by 3½ inches depth cylindrical body, the antenna packaged in either enclosure can receive more public channels than a much larger antenna twice of its size. Two invention antennas have been fabricated and tested and the test results confirmed that all antennas of either enclosure were performing well as expected. The invention antennas receive more than 130 public channels. |
| US09343794B2 |
Millimeter wave bands semiconductor package
A millimeter wave bands semiconductor package includes a metal base body, a circuit board, and a metal cover body. The base body has a first non-penetration hole and a second non-penetration hole. The circuit board is disposed on the base body and has an input signal line and an output signal line on a front side surface thereof. The cover body is disposed on the circuit board and has a first penetration hole and a second penetration hole. The cover body is disposed such that the first penetration hole is disposed directly above the first non-penetration hole of the base body and the second penetration hole is disposed directly above the second non-penetration hole of the base body. Further, the first penetration hole and the first non-penetration hole constitute a first waveguide, and the second penetration hole and the second non-penetration hole constitute a second waveguide. |
| US09343785B2 |
Vehicular battery cooling device through rear seat
A vehicular battery cooling device in which a rear seat is disposed on the upper surface of a rear floor panel, a battery pack is disposed on the upper surface of the rear floor panel at the rear of the rear seat, and an air intake duct extending from the battery pack to the vehicle front is installed between the cushion part of the rear seat and the rear floor panel. A concave part extending in the vehicle longitudinal direction is formed in the lower surface of the cushion part in the central portion in the vehicle width direction, an opening is formed at the front end of the air intake duct, and the air intake duct is formed so as to have a strength capable of supporting the weight of a passenger and is brought into contact with the lower surface of the cushion part. |
| US09343774B2 |
Method for producing a lithium hexafluorophosphate concentrated liquid
Disclosed is a method for forming lithium hexafluorophosphate by reacting together phosphorus trichloride, chlorine and lithium chloride in a nonaqueous organic solvent and then making the reaction product formed in the solvent react with hydrogen fluoride. This method is characterized by that a lithium hexafluorophosphate concentrated liquid is obtained by conducting a filtration after making the reaction product formed in the solvent react with hydrogen fluoride and then subjecting the filtrate to a concentration by degassing. By this method, it is possible to easily produce a high-purity, lithium hexafluorophosphate concentrated liquid at a low cost. |
| US09343772B2 |
Rechargeable battery
A rechargeable battery includes an electrode assembly undergoing charging and discharging, a pressurization holder covering the electrode assembly and fixing the electrode assembly, a positive terminal and a negative terminal electrically connected to the electrode assembly, and a case accommodating the electrode assembly and the pressurization holder in a state in which the positive terminal and the negative terminal protrude from the case. |
| US09343770B2 |
Microbial fuel cell, and related systems and methods
A microbial fuel cell is provided that includes a cell housing, a membrane dividing an internal chamber of the cell housing into an anode compartment and a cathode compartment, an anode including a graphite and first microorganisms contained in the anode compartment, a cathode including graphite and a second microorganisms contained in the cathode compartment, and a watercourse communicating the anode compartment and the cathode compartment with one another. A system including at least one microbial fuel cell and methods of operating the microbial fuel cell and system are also provided. |
| US09343762B2 |
Controller for estimating relative humidity and condensed water, and method for controlling condensed water drain using the same
The present invention provides a relative humidity and condensed water estimator for a fuel cell and a method for controlling condensed water drain using the same. Here, the relative humidity and condensed water estimator is utilized in control of the fuel cell system involving control of anode condensed water drain by outputting at least two of signals comprising air-side relative humidity, hydrogen-side relative humidity, air-side instantaneous or cumulative condensed water, hydrogen-side instantaneous or cumulative condensed water, instantaneous and cumulative condensed water of the humidifier, membrane water contents, catalyst layer oxygen partial pressure, catalyst layer hydrogen partial pressure, stack or cell voltage, air-side catalyst layer relative humidity, hydrogen-side catalyst layer relative humidity, oxygen supercharging ratio, hydrogen supercharging ratio, residual water in a stack, and residual water in a humidifier. |
| US09343757B2 |
Gas storage system
Among other things, a gas storage system includes a group of capsules and an activation element coupled to the group. The group of capsules are formed within a substrate and contain gas stored at a relatively high pressure compared to atmospheric pressure. The activation element is configured to deliver energy in an amount sufficient to cause at least one of the capsules to release stored gas. |
| US09343755B2 |
Method and system for cooling charge air for a fuel cell, and three-fluid charge air cooler
A method and system for cooling a pressurized charge air in the fuel cell system of a vehicle, using first and second charge air coolers. The system further includes a gas-to-gas humidifier and a fuel cell stack. According to the method and system, cathode exhaust gas passes through the gas-to-gas humidifier and is also used as the coolant gas in the first charge-air cooler. Therefore, the fuel cell cathode exhaust is heated and reduced in water content, reducing the tendency of water in the exhaust to condense and pool underneath the vehicle. Also provided is a three-fluid heat exchanger which integrates the first and second charge air coolers. |
| US09343753B2 |
Fuel cell device and system
Fuel cell devices and systems are provided. A reaction zone positioned along a portion of the length is configured to be heated to an operating reaction temperature, and has at least one active layer therein comprising an electrolyte separating an anode from an opposing cathode, and fuel and oxidizer gas passages adjacent the respective anode and cathode. At least one cold zone positioned from the first end along another portion of the length is configured to remain below the operating reaction temperature. The anode and cathode each have electrical pathways extending to an exterior surface in the cold zone for electrical connection at the lower temperature. The electrolyte includes at least a portion thereof comprising a ceramic material sintered from a nano-sized powder. In one embodiment, the sintered nano-sized powder provides an uneven surface topography on the electrolyte. |
| US09343742B2 |
Nickel hydride secondary battery
A nickel hydride secondary battery houses an electrode group including a positive electrode and a negative electrode which are overlapped with each other via a separator with an alkaline electrolyte solution, the negative electrode includes a hydrogen absorbing alloy, a negative-electrode additive agent, a thickening agent, and a conductive material, and the negative-electrode additive agent includes at least one selected from calcium fluoride, calcium sulfide, and calcium chloride. |
| US09343740B2 |
Lithium ion battery
There is provided a lithium ion battery which maintains the flame retardancy of an electrolyte over a long period of time, has high energy density, and has improved charge/discharge cycle characteristics, high temperature storage characteristics, and rate characteristics. The lithium ion battery according to the present exemplary embodiment is a lithium ion battery comprising an electrolyte containing at least an ionic liquid and a lithium salt, a positive electrode, and a negative electrode, wherein the negative electrode includes a negative electrode active material which is a carbon material treated with a surface treatment agent. |
| US09343739B2 |
Positive active material including lithium nickel composite oxide core and coating layer containing lithium metal phosphate and metal phosphate, manufacturing method thereof, and electrode and lithium battery containing the same
In one aspect, a positive active material is provided that may have increased thermal stability and resistance to capability deterioration due to repeated charging and discharging, a method of manufacturing the same, and a lithium battery that includes the positive active material. |
| US09343738B2 |
Production of battery grade materials via an oxalate method
An active electrode material for electrochemical devices such as lithium ion batteries includes a lithium transition metal oxide which is free of sodium and sulfur contaminants. The lithium transition metal oxide is prepared by calcining a mixture of a lithium precursor and a transition metal oxalate. Electrochemical devices use such active electrodes. |
| US09343737B2 |
Hydrogen-absorbing alloy powder, negative electrode, and nickel hydrogen secondary battery
Provided are hydrogen storage alloy powder capable of providing a nickel-hydrogen rechargeable battery with simultaneous excellence in initial activity, discharge capacity, and cycle characteristics, which are otherwise in a trade-off relationship, an anode for a nickel-hydrogen rechargeable battery as well as a nickel-hydrogen rechargeable battery employing the same. The hydrogen storage alloy has a particular composition represented by formula (1), R1-aMgaNibAlcMd, and has at its outermost surface a Mg-rich/Ni-poor region having a composition with a Mg molar ratio higher than that in formula (1) and a Ni molar ratio lower than that in formula (1), and has inside a Mg/Ni-containing region having a composition with a Mg molar ratio lower than and a Ni molar ratio higher than those in the Mg-rich/Ni-poor region. |
| US09343736B2 |
Lithium compensation for full cell operation
Disclosed herein are embodiments of a lithium-ion battery system comprising an anode, an anode current collector, and a layer of lithium metal in contact with the current collector, but not in contact with the anode. The lithium compensation layer dissolves into the electrolyte to compensate for the loss of lithium ions during usage of the full cell. The specific placement of the lithium compensation layer, such that there is no direct physical contact between the lithium compensation layer and the anode, provides certain advantages. |
| US09343732B2 |
Electrode active material, electrode comprising the same, lithium battery comprising the electrode, and method of preparing the electrode active material
An electrode active material, an electrode including the electrode active material, a lithium battery including the electrode, and a method of preparing the electrode active material. The electrode active material includes a core having at least one of a metal or a metal oxide that enables intercalation and deintercalation of lithium ions and a crystalline carbon thin film that is formed on at least a portion of a surface of the core. The electrode active material has a nano-structure. |
| US09343731B2 |
Battery comprising a liquid inlet for electrolyte injection
A battery includes a winding electrode body, a battery case provided with a liquid inlet and positive and negative terminal members. The positive terminal member has a junction part compressed in a direction orthogonal to a winding axis direction. The negative terminal member has a junction part compressed in the direction orthogonal to the winding axis direction. The liquid inlet is positioned leaning to either the positive terminal junction part or the negative terminal junction part. In the winding electrode body, a separation distance from the junction part further away from the liquid inlet to the end lying on the relevant junction side in the winding axis direction is greater than a separation distance from the junction part closer to the liquid inlet to the end on the relevant junction side in the winding axis direction. |
| US09343726B2 |
Rechargeable battery
A rechargeable battery comprises an electrode assembly comprising a plurality of electrodes, wherein each of the plurality of electrodes comprises a coated region and an uncoated region; a case housing the electrode assembly; a cap plate coupled to the case for enclosing the electrode assembly in the case; a current collection plate coupled to the cap plate; and a connecting member electrically connected to the uncoated regions of at least two electrodes. |
| US09343720B2 |
Pre-treating separator to enable separator for pick and place operation
The described embodiments relate to methods and apparatus for improving pick and place operations. Pick and place operations involving the movement of flexible substrates can be improved by cooling a flexible substrate below a threshold temperature at which the flexible substrate transitions from a flexible state to a rigid state. Once in the rigid state, the flexible substrate can be handled and maneuvered by pick and place operations for a period of time with a limited risk of the flexible substrate wrinkling and tearing. In some embodiments, the flexible substrate is a thin polymeric substrate used to separate oppositely charged battery cells within a battery assembly. |
| US09343708B2 |
Mask strips and method for manufacturing organic light emitting diode display using the same
A mask strip for manufacturing an organic light emitting diode (OLED) display is disclosed. In one aspect, the mask strip is extended in a length direction and fixed to a frame. The frame includes a plurality of masking pattern units arranged in a matrix format in which an opening pattern includes a plurality of rows that are substantially parallel to a width direction crossing the length direction and a plurality of columns that are substantially parallel to the length direction. The rows respectively have a curvature which is concave toward an inside of the masking pattern unit, and the columns respectively have a curvature which is convex toward an outside of the masking pattern unit. |
| US09343706B2 |
Sealing structure, device, and method for manufacturing device
Provided is a device in which heat conduction from a sealant to a functional element is suppressed and whose bezel is slim. The sealing structure includes a first substrate, a second substrate whose surface over which a sealed component is provided faces the first substrate, and a frame-like sealant which seals a space between the first substrate and the second substrate with the first substrate and the second substrate. The second substrate includes a groove portion between the sealant and the sealed component. The groove portion is in a vacuum or includes a substance whose heat conductivity is lower than that of the second substrate. |
| US09343705B2 |
Light emitting element and light emitting device including a conductive section
According to one embodiment, a light emitting element includes a first electrode, a second electrode, a light emitting layer, and a conductive section. The second electrode is provided opposite to the first electrode. The light emitting layer is provided between the first electrode and the second electrode. The second electrode includes a plurality of layers, and the plurality of layers include a first layer. The conductive section pierces the first layer in thickness direction. The conductive section includes a conductive material. Each of the plurality of layers includes at least one of Al, Al alloy, Ag, Ag alloy, alkali metals, and alkaline-earth metals and being different from one another. |
| US09343702B2 |
Adhesive film and method for encapsulating organic electronic device using same
The present invention relates to an adhesive film, to an encapsulated product of an organic electronic device using same and to a method for encapsulating an organic electronic device using same. More particularly, an adhesive film for encapsulating an organic electronic device comprises: a protective film layer, a first adhesive layer, a second adhesive layer and a release film layer sequentially arranged. The peel strength (A) between the first adhesive layer and the protective film layer is lower than the peel strength (B) between the second adhesive layer and the release film layer, and the peel strength (B) between the second adhesive layer and the release film layer is lower than the peel strength (C) between the first adhesive layer and an encapsulation substrate, thus improving faults during a peeling process. |
| US09343700B2 |
Display apparatus and method of fabricating the same
Provided is a display apparatus including: a substrate including a display area and a periphery; a display element disposed on the display area of the substrate; and an encapsulation layer including a first inorganic layer, an organic layer, and a second inorganic layer that are sequentially formed to cover the display element, wherein the organic layer includes: a first organic layer formed on of the periphery of the substrate and on the substrate; and a second organic layer formed on the first inorganic layer so as to overlap the display element. |
| US09343699B2 |
Organic light-emitting display apparatus and method of manufacturing the same
An organic light-emitting display apparatus including a substrate; a display unit which defines an active area of the substrate and includes a thin film transistor; concave-convex portions protruded from the substrate in an area outside the active area; and an encapsulation layer which encapsulates the display unit. The thin film transistor includes an active layer, a gate insulating layer on the active layer, a gate electrode, a source electrode, a drain electrode, and an interlayer insulating layer between the gate electrode and the source electrode, and between the gate electrode and the drain electrode. The concave-convex portions include portions of the gate insulating layer and the interlayer insulating layer, and the encapsulation layer covers the concave-convex portions. |
| US09343698B2 |
Organic EL display and electronic apparatus
An organic EL display includes: a first insulating layer on a lower side as well as a second insulating layer on an upper side, the first insulating layer and the second insulating layer being provided to a display region and a peripheral region; a first separation groove provided in the first insulating layer between the display region and the peripheral region; a first conductive layer provided on the first insulating layer in the peripheral region, with a side face and a bottom of the first separation groove in between; a covering section in which at least a part of an end face of the second insulating layer is covered by the organic layer or the second electrode; and a sealing section provided on an outer edge side of the covering section, and formed by laminating the first conductive layer and the second electrode. |
| US09343687B1 |
Imidazo[1,2-A]pyrimidine-containing compounds, method for preparing the same, and their use in electronic devices
The present disclosure describes novel imidazo[1,2-a]pyrimidine-containing organic light-emitting compounds represented by formula (I): wherein R1 and R2 independently represent hydrogen, an alkyl group, or an aryl group which is unsubstituted or substituted with at least one substituent selected from the group consisting of an alkyl group, an alkoxy group, and a halo group with the proviso that at least one of R1 and R2 is the aryl group. The disclosure further relates to methods for preparing these compounds, to electronic devices comprising the same, and to the use of the compounds as OLED material. |
| US09343685B2 |
Organic electroluminescent element
Provided is an organic electroluminescent device (EL device) that uses an indolocarbazole compound. The organic EL device includes an anode, a plurality of organic layers including a phosphorescent light-emitting layer, and a cathode laminated on a substrate, in which at least one organic layer selected from the phosphorescent light-emitting layer, a hole-transporting layer, an electron-transporting layer, and a hole-blocking layer contains an indolocarbazole compound represented by the general formula (1). In the general formula (1), a ring I and a ring II represent rings represented by the formula (1a) and the formula (1b), respectively, each of which are fused to an adjacent ring. X's each represent nitrogen or C—Y and at least one of X's represents nitrogen. Y's each represent hydrogen, an alkyl group, a cycloalkyl group, or an aromatic group. A represents an alkyl group, a cycloalkyl group, or an aromatic group. At least one of Y and A represents an alkyl group or a cycloalkyl group. R's each represent hydrogen, an alkyl group, a cycloalkyl group, an aromatic hydrocarbon group, or an aromatic heterocyclic group. |
| US09343682B2 |
Organic electroluminescence device and organic light emitting medium
An organic electroluminescence device having a layer of an organic light emitting medium which comprises (A) a specific arylamine compound and (B) at least one compound selected from specific anthracene derivatives, spirofluorene derivatives, compounds having condensed rings and metal complex compounds and is disposed between a pair of electrodes and an organic light emitting medium comprising the above components (A) and (B) are provided. The organic electroluminescence device exhibits a high purity of color, has excellent heat resistance and a long life and efficiently emits bluish to yellowish light. The organic light emitting medium can be advantageously used for the organic electroluminescence device. |
| US09343679B2 |
Method for producing multiple-surface imposition vapor deposition mask, multiple-surface imposition vapor deposition mask obtained therefrom, and method for producing organic semiconductor element
A method for producing a multiple-surface imposition vapor deposition mask enhances definition and reduces weight even when a size is increased. Each of multiple masks in an open space in a frame is configured by a metal mask having a slit, and a resin mask that is positioned on a front surface of the metal mask and has openings corresponding to a pattern to be produced by vapor deposition arranged by lengthwise and crosswise in a plurality of rows. In formation of the plurality of masks, after each of the metal masks and a resin film material for producing the resin mask are attached to the frame, the resin film material is processed, and the openings corresponding to the pattern to be produced by vapor deposition are formed in a plurality of rows lengthwise and crosswise, whereby the multiple-surface imposition vapor deposition mask of the above described configuration is produced. |
| US09343678B2 |
Apparatus and techniques for electronic device encapsulation
Apparatus and techniques for use in manufacturing a light emitting device, such as an organic light emitting diode (OLED) device can include using one or more modules having a controlled environment. The controlled environment can be maintained at a pressure at about atmospheric pressure or above atmospheric pressure. The modules can be arranged to provide various processing regions and to facilitate printing or otherwise depositing one or more patterned organic layers of an OLED device, such as an organic encapsulation layer (OEL) of an OLED device. In an example, uniform support for a substrate can be provided at least in part using a gas cushion, such as during one or more of a printing, holding, or curing operation comprising an OEL fabrication process. In another example, uniform support for the substrate can be provided using a distributed vacuum region, such as provided by a porous medium. |
| US09343676B2 |
Heating phase change material
A phase change memory may be formed of two vertically spaced layers of phase change material. An intervening dielectric may space the layers from one another along a substantial portion of their lateral extent. An opening may be provided in the intervening dielectric to allow the phase change layers to approach one another more closely. As a result, current density may be increased at this location, producing heating. |
| US09343665B2 |
Methods of forming a non-volatile resistive oxide memory cell and methods of forming a non-volatile resistive oxide memory array
A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Metal oxide-comprising material is formed over the first conductive electrode. Etch stop material is deposited over the metal oxide-comprising material. Conductive material is deposited over the etch stop material. A second conductive electrode of the memory cell which comprises the conductive material received is formed over the etch stop material. Such includes etching through the conductive material to stop relative to the etch stop material and forming the non-volatile resistive oxide memory cell to comprise the first and second conductive electrodes having both the metal oxide-comprising material and the etch stop material therebetween. Other implementations are contemplated. |
| US09343658B2 |
Magnetic memory bits with perpendicular magnetization switched by current-induced spin-orbit torques
A basic Spin-Orbit-Torque (SOT) structure with lateral structural asymmetry is provided that produces a new spin-orbit torque, resulting in zero-field current-induced switching of perpendicular magnetization. More complex structures can also be produced incorporating the basic structure of a ferromagnetic layer with a heavy non-magnetic metal layer having strong spin-orbit coupling on one side, and an insulator layer on the other side with a structural mirror asymmetry along the in-plane direction. The lateral structural asymmetry and new spin-orbit torque, in effect, replaces the role of the external in-plane magnetic field. The direction of switching is determined by the combination of the direction of applied current and the direction of symmetry breaking in the device. |
| US09343657B2 |
Storage element, storage apparatus, and magnetic head
There is provided a storage element including a layered construction including a storage layer that has magnetization perpendicular to a surface of the storage layer and whose direction of magnetization is changed corresponding to information, a pinned magnetization layer that has magnetization perpendicular to a surface of the pinned magnetization layer and serves as a standard for information stored in the storage layer, and an insulating layer that is composed of a non-magnetic material and is provided between the storage layer and the pinned magnetization layer. |
| US09343655B2 |
Method for manufacturing bimorph actuator
To manufacture a switching apparatus that includes a piezoelectric actuator with increased lifespan, provided is a method for manufacturing a bimorph actuator, comprising first piezoelectric element layer formation of forming a first piezoelectric element layer on a substrate; support layer formation of forming a support layer made of an insulator on the first piezoelectric element layer; second piezoelectric element layer formation of forming a second piezoelectric element layer on the support layer; and removal of removing a portion of the substrate to form an actuator that includes the first piezoelectric element layer, the support layer, and the second piezoelectric element layer. |
| US09343650B2 |
Piezoelectric material, piezoelectric element, multilayered piezoelectric element, liquid ejection head, liquid ejection apparatus, ultrasonic motor, optical equipment, vibration apparatus, dust removing apparatus, imaging apparatus, and electronic equipment
Provided is a lead-free piezoelectric material having a satisfactory and stable piezoelectric constant and electric insulation property in a wide practical temperature range. Provided is a piezoelectric material, including a perovskite-type metal oxide represented by the following general formula (1) as a main component, the piezoelectric material containing Mn in a content of 0.01 part by weight or more and 0.80 part by weight or less with respect to 100 parts by weight of the perovskite-type metal oxide: (LiαxNaαyKαzBaβBi0.5α+γ)a(Tiα+βFeγ) O3 . . . (1), where 0.800≦α≦0.999, 0≦β≦0.150, 0.001≦γ≦0.050, α+β+γ=1, 0≦x≦0.050, 0.045≦y≦0.450, 0.045≦z≦0.450, 0.450≦x+y+z≦0.500, and 0.980≦a≦1.020. |
| US09343648B2 |
Method for manufacturing a thermoelectric device, particularly intended to generate an electric current in a motor vehicle, and thermoelectric device obtained by such a method
The invention relates to a method of manufacturing a thermoelectric device comprising a plurality of thermoelectric components (4) for creating an electric current from a temperature gradient applied between two faces (3a, 3b) thereof. In the method, a thermally conductive support (30) is provided in contact with a hot or cold source, a thermally conductive and electrically insulating material is thermally sprayed on the support (30) to produce a coating (21), and an electrically conductive material is thermally sprayed onto the coating (21) to form electric conduction tracks (22) which are intended to receive the thermoelectric components (4) via the faces (3a, 3b) thereof. The invention also relates to a thermoelectric device obtained by the method. |
| US09343645B2 |
Thermo-electric power harvesting bearing configuration
A power generating bearing assembly (100) comprises a bearing subassembly (120) retained by a bearing housing (110). During operation, friction and other factors increase a temperature of the bearing assembly (100). The housing (110) includes a bearing cooling passage system comprising a coolant supply port (130), a liquid cooling passage (134), and a coolant return port (138). The liquid cooling passage (134) is routed proximate the bearing subassembly (120) to remove heat therefrom. A thermo-generator cavity (180) is formed into the housing (110) between the coolant supply port (130) and the coolant return port (138). A Thermo-Electric Generator (TEG) (200) is inserted into the cavity (180), orienting a cold carrier side (220, 222) towards the supply port (130) and a hot carrier side (240) towards the return port (138). The Thermo-Electric Generator (TEG) (200) utilizes a temperature difference between the supply port (130) and the return port (138) to generated electric power. The power can be used to operate electrically powered devices, such as condition sensors (150), communication devices, and the like. |
| US09343644B2 |
Light emitting diode module for surface mount technology and method of manufacturing the same
Provided is a light emitting diode (LED) in which a side surface of a reflective metal layer has a predetermined angle, and occurrence of cracks in a conductive barrier layer formed on the reflective metal layer can be prevented. Also, an LED module using LEDs is disclosed. A reflection pattern electrically connected to a second semiconductor layer is partially exposed by patterning a first insulating layer. Accordingly, a first pad is formed through the partially opened first pad region. Also, a conductive reflection layer electrically connected to a first semiconductor layer forms a second pad region formed by patterning a second insulating layer. A second pad is formed on the second pad region. |
| US09343641B2 |
Non-reactive barrier metal for eutectic bonding process
A eutectic metal layer (e.g., gold/tin) bonds a carrier wafer structure to a device wafer structure. In one example, the device wafer structure includes a silicon substrate upon which an epitaxial LED structure is disposed. A layer of silver is disposed on the epitaxial LED structure. The carrier wafer structure includes a conductive silicon substrate covered with an adhesion layer. A layer of non-reactive barrier metal (e.g., titanium) is provided between the silver layer and the eutectic metal to prevent metal from the eutectic layer (e.g., tin) from diffusing into the silver during wafer bonding. During wafer bonding, the wafer structures are pressed together and maintained at more than 280° C. for more than one minute. Use of the non-reactive barrier metal layer allows the total amount of expensive platinum used in the manufacture of a vertical blue LED manufactured on silicon to be reduced, thereby reducing LED manufacturing cost. |
| US09343640B2 |
Light emitting device, light emitting device package and lighting system including the same
A light emitting device is described, including a second conductive type semiconductor layer; an active layer over the second conductive type semiconductor layer; a first conductive type semiconductor layer over the active layer; a second electrode in a first region under the second conductive type semiconductor layer; a current blocking layer including a metal; and a first electrode over the first conductive type semiconductor layer. Further, the first electrode has at least one portion that vertically overlaps the current blocking layer. |
| US09343639B2 |
Light emitting diode (LED) device having lens protective structure and method of fabrication
A light emitting diode (LED) device includes a substrate, a light emitting diode (LED) die mounted to the substrate configured to emit electromagnetic radiation, a lens covering the (LED) die, and a lens protective structure configured to protect the lens and a lens bonding layer from electromagnetic radiation emitted by the light emitting diode (LED) die and from reflected electromagnetic radiation within the lens. The lens protective structure can also be configured to reflect electromagnetic radiation increasing light extraction from the (LED) device. A method for fabricating the (LED) device includes the step of forming an opaque lens protective structure on the lens or on the lens bonding layer configured to protect the lens and the lens bonding layer from electromagnetic radiation emitted by the light emitting diode (LED) die and from reflected electromagnetic radiation within the lens. |
| US09343638B2 |
Electro-optic PN junction modulator formed with a self-aligned process
An electro-optic device, comprising a layer of light-carrying material; and a rib, projecting from the layer of light-carrying material, for guiding optical signals propagating through the device. The layer of light-carrying material comprises a first doped region of a first type extending into the rib, and a second doped region of a second, different type extending into the rib such that a pn junction is formed within the rib. The pn junction extends substantially parallel to at least two contiguous faces of the rib, resulting in a more efficient device. In addition, a self-aligned fabrication process can be used in order to simplify the fabrication process and increase reliability and yield. |
| US09343634B2 |
Light emitting device
Disclosed are a light emitting device. The light emitting device comprises a board comprising a plurality of lead frames, a light emitting diode chip electrically connected to the lead frames, and a reflective member formed coupled on the board while surrounding the light emitting diode. |
| US09343625B2 |
Semiconductor light emitting diode and method for manufacturing the same
A semiconductor light emitting diode is provided. The semiconductor light emitting diode comprises a metal electrode; an n-type cladding over the metal electrode, the n-type cladding comprising a pillar support part formed of an n-type semiconductor material, and a pillar part having a plurality of pillars formed of an n-type semiconductor material over the pillar support part; an active part conformally formed over the pillar part so as to enclose the pillar part and over the pillar support part between the pillar parts, the active part having a quantum well layer and a barrier layer stacked alternately; a p-type cladding conformally formed of a p-type semiconductor material over the active part; and a transparent electrode formed over the p-type cladding. |
| US09343621B2 |
Liquid crystal display panel and manufacturing method thereof
A liquid crystal display panel includes a substrate, a thin film transistor array, a circuit, and a dummy circuit. One surface of the substrate is divided into a display region and a wiring region. The thin film transistor array is formed on the display region. The circuit and the dummy circuit are formed on the wiring region, the dummy circuit is adjacent to the circuit, and the circuit and the dummy circuit protrude from the substrate. |
| US09343619B2 |
Group III nitride semiconductor light-emitting device and method for producing the same
The present invention provides a Group III nitride semiconductor light-emitting device exhibiting high light efficiency achieved by relaxing a piezoelectric field generated in a light-emitting layer without deteriorating the crystal quality of the light-emitting layer, and a method for producing the same. The light-emitting device has a light-emitting layer in which layer units are repeatedly deposited. Each layer unit comprises an AlGaN layer, an n-type InGaN layer, an InGaN layer, a GaN layer, and an AlGaN layer which are deposited in this order on the n-side superlattice layer. The n-type InGaN layer is doped with Si at a Si concentration of 1×1017/cm3 to 3×1018/cm3. |
| US09343618B2 |
Method of manufacturing light-emitting device
A method of manufacturing a light-emitting device includes providing a case including an annular sidewall and an LED chip including a chip substrate and a crystal layer and mounted in a region surrounded by the sidewall of the case, and dripping a droplet of an electrically-charged phosphor-containing resin so as to fill a space between the sidewall and the LED chip. The droplet is attracted toward the sidewall by an electrostatic force during the dripping. |
| US09343616B2 |
Heterojunction light emitting diode
A method for forming a light emitting device includes forming a monocrystalline III-V emissive layer on a monocrystalline substrate and forming a first doped layer on the emissive layer. A first contact is deposited on the first doped layer. The monocrystalline substrate is removed from the emissive layer by a mechanical process. A second doped layer is formed on the emissive layer on a side from which the substrate has been removed. The second doped layer has a dopant conductivity opposite that of the first doped layer. A second contact is deposited on the second doped layer. |
| US09343611B2 |
Method for producing interconnected optoelectronic components, and interconnected optoelectronic components
The invention relates to a method for producing serially interconnected optoelectronic components as well as optoelectronic components interconnected according to the method. In a first step, an electrically non-conductive layer with optoelectronic material introduced therein and at least one first wire or thread (2) located in the layer is produced. The first wire or thread either is electrically conductive from the outset or can subsequently be treated in such a way that it becomes electrically conductive as a result of the treatment. A first and second electrooptically active region of the layer is electrically connected to the first wire or thread in such a way that they are electrically interconnected to each other in series. By the wire, regions of the layer are subdivided in a simple manner, as a result of which a plurality of optoelectronic components are produced in a technically simple manner. Continuous production is possible. |
| US09343610B2 |
Device and method for precipitating a layer on a substrate
The invention relates to a device for depositing a layer made of at least two components on an object, with a deposition chamber for disposing the object, at least one source with material to be deposited, as well as at least one device for controlling the deposition process, implemented such that the concentration of at least one component of the material to be deposited can be modified in its gas phase prior to deposition on the substrate by selective binding of a specified quantity of the at least one component, wherein the selectively bound quantity of the at least one component can be controlled by modifying at least one control parameter that is actively coupled to a binding rate or the component. It further relates to a device for depositing a layer made of at least two components on an object, wherein a device for controlling the deposition process has at least one gettering element made of a reactive material, wherein the reactive material includes copper and/or molybdenum. It further relates to a method for depositing a layer made of at least two components on an object, wherein a selectively bound quantity of at least one component is controlled by modifying a binding rate of a device for controlling the deposition process. |
| US09343609B2 |
Mesoscopic optoelectronic devices comprising arrays of semiconductor pillars deposited from a suspension and production method thereof
The invention illustrates an innovative way to fabricate low cost, efficient, rigid or flexible mesoscopic optoelectronic devices such as photovoltaic (PV) solar cells or photo sensors (b) comprising three-dimensional arrays of semi-conductive micro- or nano-pillars (3b) deposited from suspensions e.g. by inkjet printing. Said pillars additionally increase the surface area of the device composed of an interpenetrating network of semiconductor particles of mesoscopic (2-50 nm) size forming junctions. In the present invention the active surface area is significantly increased when compared to previous flat structures (a, 3a), being fabricated preferably by inkjet patterning. Additionally, the invention allows for production of much more functional devices when compared with conventional mesoscopic PV cells due to smaller structure density what makes the layer more resistive to mechanical failure when bending. The invention also describes the device substrate (1), contact and electrode (2, 8), ion conductor (6) and fabrication parameters (h, d). |
| US09343608B2 |
Depletion-mode field-effect transistor-based phototransistor
A depletion-mode phototransitor is disclosed. The phototransistor having a substrate, a gate, a source, a drain and a channel. The source, drain and channel are doped to be the same type of semiconductor. The substrate can be made of silicon and/or germanium. The gate can be made of either aluminum or polysilicon. |
| US09343607B2 |
PN-structured gate demodulation pixel
A novel photo-sensitive element for electronic imaging purposes and, in this context, is particularly suited for time-of-flight 3D imaging sensor pixels. The element enables charge-domain photo-detection and processing based on a single gate architecture. Certain regions for n and p-doping implants of the gates are defined. This kind of single gate architecture enables low noise photon detection and high-speed charge transport methods at the same time. A strong benefit compared to known pixel structures is that no special processing steps are required such as overlapping gate structures or very high-ohmic poly-silicon deposition. In this sense, the element relaxes the processing methods so that this device may be integrated by the use of standard CMOS technology for example. Regarding time-of-flight pixel technology, a major challenge is the generation of lateral electric fields. The element allows the generation of fringing fields and large lateral electric fields. |
| US09343602B2 |
Solar cell unit and method for manufacturing the same
The present invention provides a solar cell unit, which comprises a semiconductor plate of first-type doping or second-type doping; wherein the semiconductor plate has a first surface and a second surface opposite to the first surface; the semiconductor plate comprises a first-type doping region and second-type doping region, both the first-type doping region and the second-type doping region are located on the first surface of the semiconductor plate; a first sheet is provided on the side surface of the semiconductor plate that is adjacent to the first-type doping region, and a second sheet is provided on the side surface of the semiconductor plate that is adjacent to the second type doping region. |
| US09343599B2 |
Solar cell and method for manufacturing the same
A method of manufacturing a solar cell includes forming jagged portions non-uniformly on a surface of a substrate, forming a first type semiconductor and a second type semiconductor in the substrate, forming a first electrode to contact the first type semiconductor, and forming a second electrode to contact the second type semiconductor. An etchant used in a wet etching process in manufacturing the solar cell includes about 0.5 wt % to 10 wt % of HF, about 30 wt % to 60 wt % of HNO3, and up to about 30 wt % of acetic acid based on total weight of the etchant. |
| US09343597B2 |
Image pickup apparatus and camera module
An image pickup apparatus includes an optical device, a transparent conductive film, an electrode pad, and a penetrating electrode. In the optical device, an optical element area for receiving light is formed on a first surface side of a substrate, and an external connection terminal is formed on a side of a second surface opposite to the first surface of the substrate.The transparent conductive film is formed to face the first surface of the substrate. The electrode pad is formed on the first surface of the substrate and configured to perform connection with a fixed potential.The penetrating electrode is connected to the electrode pad and formed to penetrate the substrate between the first surface and second surface. The transparent conductive film is connected to the electrode pad, and the penetrating electrode is connected to the external connection terminal on the side of the second surface of the substrate. |
| US09343596B2 |
Method for producing at least one radiation-emitting and/or -receiving semiconductor component, and semiconductor component
A method for producing a radiation-emitting or radiation-receiving semiconductor component is specified. In a method step, a carrier body having a mounting surface is provided. In a further method step, a barrier frame is formed on the mounting surface, in such a way that the barrier frame laterally encloses a mounting region of the mounting surface. In a further method step, a radiation-emitting or radiation-receiving semiconductor chip is mounted within the mounting region on the mounting surface. The semiconductor chip is potted with a liquid lens material, wherein the lens material is applied to the mounting surface within the mounting region. The lens material is cured. The mounting surface, the barrier frame and the lens material are adapted to one another. |
| US09343584B2 |
Semiconductor device and method for manufacturing the same
An object is to provide a semiconductor device including an oxide semiconductor film, which has stable electrical characteristics and high reliability. A stack of first and second material films is formed by forming the first material film (a film having a hexagonal crystal structure) having a thickness of 1 nm to 10 nm over an insulating surface and forming the second material film having a hexagonal crystal structure (a crystalline oxide semiconductor film) using the first material film as a nucleus. As the first material film, a material film having a wurtzite crystal structure (e.g., gallium nitride or aluminum nitride) or a material film having a corundum crystal structure (α-Al2O3, α-Ga2O3, In2O3, Ti2O3, V2O3, Cr2O3, or α-Fe2O3) is used. |
| US09343581B2 |
Semiconductor device
To provide a transistor with stable electrical characteristics, a transistor with a low off-state current, a transistor with a high on-state current, a semiconductor device including the transistor, or a durable semiconductor device. The semiconductor device includes a first transistor using silicon, an aluminum oxide film over the first transistor, and a second transistor using an oxide semiconductor over the aluminum oxide film. The oxide semiconductor has a lower hydrogen concentration than silicon. |
| US09343579B2 |
Semiconductor device
To provide a semiconductor device that includes an oxide semiconductor and is miniaturized while keeping good electrical properties. In the semiconductor device, an oxide semiconductor layer filling a groove is surrounded by insulating layers including an aluminum oxide film containing excess oxygen. Excess oxygen contained in the aluminum oxide film is supplied to the oxide semiconductor layer, in which a channel is formed, by heat treatment in a manufacturing process of the semiconductor device. Moreover, the aluminum oxide film forms a barrier against oxygen and hydrogen, which inhibits the removal of oxygen from the oxide semiconductor layer surrounded by the insulating layers including an aluminum oxide film and the entry of impurities such as hydrogen in the oxide semiconductor layer. Thus, a highly purified intrinsic oxide semiconductor layer can be obtained. The threshold voltage is controlled effectively by gate electrode layers formed over and under the oxide semiconductor layer. |
| US09343574B2 |
Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack
Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode. |
| US09343569B2 |
Vertical compound semiconductor field effect transistor on a group IV semiconductor substrate
Group IV semiconductor devices can be formed on a semiconductor-on-insulator substrate including a handle substrate containing a group IV semiconductor material. A cavity is formed to physically expose a top surface of the handle substrate through a stack, from bottom to top, of a buried insulator layer, a doped semiconductor material portion in a top semiconductor layer, and a dielectric material layer. A gate dielectric is formed around the cavity by a conformal deposition of a dielectric material layer and an anisotropic etch. A lower active region, a channel region, and an upper active region are formed by selective epitaxy processes in, and/or above, the trench and from the top surface of the handle substrate. The selective epitaxy processes deposit a compound semiconductor material. The doped semiconductor material portion functions as the gate of a vertical compound semiconductor field effect transistor. |
| US09343563B2 |
Selectively area regrown III-nitride high electron mobility transistor
Methods for forming a HEMT device are provided. The method includes forming an ultra-thin barrier layer on the plurality of thin film layers. A dielectric thin film layer is formed over a portion of the ultra-thin barrier layer to leave exposed areas of the ultra-thin barrier layer. A SAG S-D thin film layer is formed over the exposed areas of the ultra-thin barrier layer while leaving the dielectric thin film layer exposed. The dielectric thin film layer is then removed to expose the underlying ultra-thin barrier layer. The underlying ultra-thin barrier layer is treating with fluorine to form a treated area. A source and drain is added on the SAG S-D thin film layer, and a dielectric coating is deposited over the ultra-thin barrier layer treated with fluorine such that the dielectric coating is positioned between the source and the drain. |
| US09343562B2 |
Dual-gated group III-V merged transistor
There are disclosed herein various implementations of a group III-V merged cascode transistor. Such a group III-V merged cascode transistor includes a group III-V body disposed over a substrate and configured to produce a two-dimensional electron gas (2DEG). The group III-V body includes a group III-V barrier layer situated over a group III-V channel layer, and a source electrode and a drain electrode. The group III-V merged cascode transistor also includes an enable gate disposed in a recess extending substantially through the group III-V barrier layer, and an operational gate disposed over the group III-V barrier layer, the operational gate not being in physical contact with the enable gate. |
| US09343560B2 |
Gallium nitride power devices
Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices. |
| US09343559B2 |
Nanowire transistor devices and forming techniques
Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein. |
| US09343557B2 |
Vertical power component
A high-voltage vertical power component including a silicon substrate of a first conductivity type, and a first semiconductor layer of the second conductivity type extending into the silicon substrate from an upper surface of the silicon substrate, wherein the component periphery includes: a porous silicon ring extending into the silicon substrate from the upper surface to a depth deeper than the first layer; and a doped ring of the second conductivity type, extending from a lower surface of the silicon surface to the porous silicon ring. |
| US09343556B2 |
Methods and apparatus for ESD protection circuits
Methods and apparatus are disclosed for ESD protection circuits. An ESD protection circuit may comprise a lateral silicon controlled rectifier (SCR) circuit and a lateral PNP bipolar junction transistor (BJT) circuit. The SCR circuit comprises a first region on an n type buried layer (NBL), a second region on the NBL, a fourth region formed within the first region, and a fifth region formed within the second region. The PNP circuit comprises the second region on the NBL, a third region on the NBL, and a sixth region formed within the third region. The first region is the 1st N node of the SCR circuit and is connected with the base of the PNP circuit, which is the third region, by the NBL, and the 2nd P node of the SCR circuit is shared with the collector of the PNP circuit. |
| US09343553B2 |
Photoresist composition, method of forming a pattern and method of manufacturing a thin film transistor substrate
A photoresist composition, a method of forming a pattern, and a method of manufacturing a thin film transistor substrate, the composition including a solvent, a novolak resin, a diazide-based photo-sensitizer, an acryl compound represented by the following Chemical Formula 1: |
| US09343551B2 |
Methods for manufacturing a fin structure of semiconductor device
Semiconductor devices and methods of manufacturing the same are disclosed. In some embodiments, a method of manufacturing a semiconductor device comprises forming a fin structure over a substrate. The fin structure may comprise a lower portion protruding from a major surface of the substrate, an upper portion, and a middle portion between the lower portion and the upper portion, wherein the lower portion and the middle portion differ in composition. The method may further include forming an isolation structure surrounding the fin structure and oxidizing the fin structure. The oxidizing may form a pair of notches extending from sidewalls of the fin structure into the middle portion of the fin structure. |
| US09343539B2 |
Reacted conductive gate electrodes and methods of making the same
A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material. |
| US09343535B2 |
Semiconductor packages having a guide wall and related systems and methods
A semiconductor package includes a first package board, a first semiconductor chip arranged on the first package board, a heat transfer layer arranged on the first semiconductor chip, a heat spreader arranged on the heat transfer layer, and a housing having a molding part arranged on the first package board and directly surrounding side surfaces of the first semiconductor chip and a guide wall arranged on the molding part, with the guide wall spaced apart from the heat spreader and surrounding side surfaces of the heat spreader. |
| US09343532B2 |
Semiconductor device containing graphene p-n junctions and method for producing same
The aim of the present invention is to provide a semiconductor device containing a graphene p-n vertical tunneling-junction diode by assessing the optical and electrical characteristics of a graphene p-n junction produced by varying the doping concentration. The semiconductor device includes first graphene of a first doping type, and second graphene of a second doping type different from the first doping type, which is arranged on the first graphene and is in contact therewith. |
| US09343531B2 |
Field effect transistor and method for fabricating field effect transistor
A field effect transistor includes a substrate, an isolation layer, a gate, a channel, drain and a source. The substrate has an active region having a rectangular area and at least one protrusion protruded from the rectangular area. The isolation layer is formed on the substrate and encircling the active region. The gate crosses the active region and is formed above a middle portion of the active region. The channel is formed in the active region directly under the gate, extends to the at least one protrusion, and divides the active region into a first section and a second section. The drain formed in the first section and the source formed in the second section. |
| US09343529B2 |
Method of formation of germanium nanowires on bulk substrates
A material stack comprising alternating layers of a silicon etch stop material and a germanium nanowire template material is formed on a surface of a bulk substrate. The material stack and a portion of the bulk substrate are then patterned by etching to provide an intermediate fin structure including a base semiconductor portion and alternating portions of the silicon etch stop material and the germanium nanowire template material. After recessing each germanium nanowire template material and optionally the base semiconductor portion, and etching each silicon etch stop material to define a new fin structure, a spacer is formed on sidewall surfaces of the remaining portions of the new fin structure. The alternating layers of germanium nanowire template material are then suspended above a notched surface portion of the bulk substrate and thereafter a functional gate structure is formed. |
| US09343528B2 |
Process of forming an electronic device having a termination region including an insulating region
An electronic device can include an electronic component and a termination region adjacent to the electronic component region. In an embodiment, the termination region can include an insulating region that extends a depth into a semiconductor layer, wherein the depth is less than 50% of the thickness of the semiconductor layer. In another embodiment, the termination region can include a first insulating region that extends a first depth into the semiconductor layer, and a second insulating region that extends a second depth into the semiconductor layer, wherein the second depth is less than the first depth. In another aspect, a process of forming an electronic device can include patterning a semiconductor layer to define a trench within termination region while another trench is being formed for an electronic component within an electronic component region. |
| US09343527B2 |
Semiconductor device including an isolation film buried in a groove
A first MISFET which is a semiconductor element is formed on an SOI substrate. The SOI substrate includes a supporting substrate which is a base, BOX layer which is an insulating layer formed on a main surface (surface) of the supporting substrate, that is, a buried oxide film; and an SOI layer which is a semiconductor layer formed on the BOX layer. The first MISFET as a semiconductor element is formed to the SOI layer. In an isolation region, an isolation groove is formed penetrating though the SOI layer and the BOX layer so that a bottom surface of the groove is positioned in the middle of a thickness of the supporting substrate. An isolation film is buried in the isolation groove being formed. Then, an oxidation resistant film is interposed between the BOX layer and the isolation film. |
| US09343526B2 |
Deep trench isolation
An integrated semiconductor device includes a substrate of a first conductivity type, a buried layer located over the substrate, an isolated region located over a first portion of the buried layer, and an isolation trench located around the isolated region. A punch-through structure is located around at least a portion of the isolation trench. The punch-through structure includes a second portion of the buried layer, a first region located over the second portion of the buried layer, the first region having a second conductivity type, and a second region located over the first region, the second region having the first conductivity type. |
| US09343523B2 |
Selector device using low leakage dielectric MIMCAP diode
MIMCAP diodes are provided that can be suitable for memory device applications, such as current selector devices for cross point memory array. The MIMCAP diodes can have lower thermal budget as compared to Schottky diodes and controllable lower barrier height and lower series resistance as compared to MIMCAP tunneling diodes. The MIMCAP diode can include a barrier height modification layer, a low leakage dielectric layer and a high leakage dielectric layer. The layers can be sandwiched between two electrodes. |
| US09343517B2 |
Display device
A display device includes a pixel portion in which a pixel electrode layer is arranged in a matrix, and an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen is provided corresponding to the pixel electrode layer. In the periphery of the pixel portion in this display device, a pad portion is provided to be electrically connected to a common electrode layer formed on a counter substrate through a conductive layer made of the same material as the pixel electrode layer. One objection of our invention to prevent a defect due to separation of a thin film in various kinds of display devices is realized, by providing a structure suitable for a pad portion provided in a display panel. |
| US09343514B2 |
Organic light emitting diode display and method of manufacturing the same
An organic light-emitting diode (OLED) display according to an exemplary embodiment of the present invention includes a substrate, a thin film transistor formed on the substrate, a pixel electrode formed on the thin film transistor and electrically connected to the thin film transistor, a pixel definition layer formed on the pixel electrode so as to define a pixel region, an emission layer formed on the pixel electrode and contacting the pixel electrode in the pixel region, and an interlayer formed on the pixel definition layer and contacting part of the emission layer. One side of the interlayer has an uneven shape so that a surface area of the interlayer is increased. |
| US09343513B2 |
Organic electroluminescent display device having an input function
An organic electroluminescent display device includes a first substrate having a pixel area including a plurality of pixels each including a plurality of sub pixels, a light emitting devices are provided in correspondence with the sub pixels, and a partition layer covering a peripheral portion of each of the sub pixels; and a second substrate having a sensing unit including a first electrode pattern extending in one direction and a second electrode pattern extending in a direction intersecting the one direction, and the first electrode pattern and the second electrode pattern is provided out of contact from each other. The first electrode pattern is located to overlap the partition layer so as to enclose the sub pixels. The first electrode pattern included in the sensing unit encloses the sub pixels, and thus light is prevented from leaking to adjacent sub pixels. |
| US09343508B2 |
Wafer for forming imaging element, method for manufacturing solid-state imaging element, and imaging element chip
A wafer for forming an imaging element has a test pattern and a plurality of imaging element units. The wafer has an imaging region which includes a great number of photoelectric conversion pixels, an imaging element units and a test pattern. The test pattern includes a testing organic photoelectric conversion film and a testing counter electrode having the same configuration and formed at the same time as the organic photoelectric conversion film and a counter electrode, respectively of the photoelectric conversion pixels. A first testing terminal is electrically connected to the undersurface side of the testing organic photoelectric conversion film, and a second testing terminal is electrically connected to the testing counter electrode. A protective film is formed over the entire semiconductor wafer so as to cover the imaging region and the test pattern, and is then partially removed so that a part of each testing terminal is exposed. |
| US09343504B2 |
Low cross-talk for small pixel barrier detectors
Methods and structures of barrier detectors are described. The structure may include an absorber that is at least partially reticulated. The at least partially reticulated absorber may also include an integrated electricity conductivity structure. The structure may include at least two contact regions isolated from one another. The structure may further include a barrier layer disposed between the absorber and at least two contact regions. |
| US09343503B2 |
Electromagnetic wave detecting element
The present invention provides an electromagnetic wave detecting element that can suppress occurrence of cracking at a substrate peripheral portion, and occurrence of breakage of lead-out wires. An interlayer insulating film is formed so as to cover TFT switches on a substrate. An interlayer insulating film is formed so as to cover semiconductor layer of sensor portions that generate charges due to electromagnetic waves that are an object of detection being irradiated, and cover a region on the substrate where the interlayer insulating film is formed. |
| US09343501B2 |
Photoelectric conversion apparatus, manufacturing method of photoelectric conversion apparatus, and electronic device
A photoelectric conversion apparatus includes a TFT 10 provided on one surface of a substrate 1, a second interlayer insulation film 7 provided so as to cover the TFT 10, a shading film 9 provided on the second interlayer insulation film 7 in an area overlapping the TFT 10 when seen from a thickness direction of films that are formed on the substrate 1, a lower electrode 8 provided on the second interlayer insulation film 7, and a semiconductor film 21 having a chalcopyrite structure provided on the lower electrode 8. A group 16 element is included in the shading film 9, the lower electrode 8 and the semiconductor film 21. |
| US09343498B2 |
Semiconductor device, imaging device and semiconductor device manufacturing method
A semiconductor device manufacturing method includes a wafer stack manufacturing process and a dicing process. The wafer stack manufacturing process includes: a first wafer manufacturing process of manufacturing a resin film covering circuits and heated to a temperature higher than a glass transition point of the resin film, manufacturing first holes extending from a surface of the resin film to wirings of the circuits, and providing electrodes electrically connected to the wirings in the first holes to form a first wafer; a second wafer manufacturing process of manufacturing a resin film covering circuits and heated to a temperature lower than a glass transition point of the resin film, manufacturing second holes extending from a surface of the resin film to wirings of the circuits, and providing the electrodes electrically connected to the wirings in the second holes to form a second wafer; and a wafer bonding process. |
| US09343497B2 |
Imagers with stacked integrated circuit dies
An imager may include an imaging die that is stacked with an image processing die. The imaging die may generate output signals from received light. The image processing die may process the output signals. Through-silicon vias of the imaging die or solder balls may electrically couple the imaging die to the image processing die and convey the output signals to the image processing die. The imaging die may include a pixel array that generates pixel signals from the received light. The image processing die may generate control signals that control the imaging die and are conveyed to the imaging die over the through-silicon vias or solder balls. |
| US09343490B2 |
Nanowire structured color filter arrays and fabrication method of the same
Color filter array devices and methods of making color filter array devices are disclosed herein. A color filter array may include a substrate having a plurality of pixels thereon, one or more nanowires associated with each of the plurality of pixels, wherein each of the one or more nanowires extends substantially perpendicularly from the substrate, and an optical coupler associated with each of the one or more nanowires. A method of making a color filter array may include, making an array of nanowires, wherein each of the nanowires extend substantially perpendicularly from a substrate, disposing a transparent polymer material to substantially encapsulate the nanowires, removing the nanowires from the substrate, providing a pixel array comprising a plurality of pixels, wherein a hard polymer substantially covers an image plane of the pixel array, disposing the array of nanowires on the pixel array, and removing the transparent polymer encapsulating the nanowires. |
| US09343486B2 |
Light emitting display device having auxiliary wire buried in substrate and method of manufacturing the same
Provided is a display device and a method of manufacturing the same. The display device includes a thin film transistor, a first electrode electrically connected to the thin film transistor, a self-light emitting pixel layer disposed on the first electrode, a second electrode disposed on the self-light emitting pixel layer, a substrate in which an auxiliary wire is buried, the substrate being disposed on the second electrode, and a reflective pixel layer disposed on the substrate. |
| US09343477B2 |
Semiconductor device and method for fabricating the same
Provided is a semiconductor device including a substrate and a stack layer. The substrate includes a first region, a second region, and a third region. The third region is disposed between the first region and the second region. Since a top surface of the substrate in the first region is lower than the top surface of the substrate in the second region, the substrate in the third region has a first step height. The stack layer is disposed on the substrate in the first and third regions. The top surface of the stack layer in the first region and the third region and the top surface of the substrate in the second region are substantially coplanar. |
| US09343475B2 |
Vertical memory devices and methods of manufacturing the same
In a method of a vertical memory device, insulation layers and sacrificial layers are alternately and repeatedly formed on a substrate. A hole is formed through the insulation layers and the sacrificial layers that expose a top surface of the substrate. Then, an interior portion of the hole may be enlarged. A semiconductor pattern is formed to partially fill the enlarged portion of the hole. A blocking layer, a charge storage layer and a tunnel insulation layer may be formed on a sidewall of the hole and the semiconductor pattern. Then, the tunnel insulation layer, the charge storage layer and the blocking layer are partially removed to expose a top surface of the semiconductor pattern. A channel is formed on the exposed top surface of the semiconductor pattern and the tunnel insulation layer. The sacrificial layers are replaced with gate electrodes. |
| US09343471B2 |
Embedded flash memory
An embedded flash memory cell and a corresponding method for fabricating the embedded flash memory cell are disclosed. In some embodiments, the flash memory cell comprises a floating gate that has been formed using a metal gate and local interconnect metal. For some embodiments, the embedded flash memory can be fabricated with little-to-no additional processes than what one would normally employ in fabricating a metal-oxide semiconductor field-effect transistor (MOSFET). |
| US09343470B2 |
Integration of semiconductor memory cells and logic cells
A polysilicon gate electrode is formed in a memory cell area, and a dummy polysilicon gate electrode is formed in a logic cell area of a silicon substrate. The dummy polysilicon gate electrode is removed and a gate insulation film and a metal gate electrode having a recess portion are formed. Further, contact holes are formed on source regions and drain regions of the memory cell area and the logic cell area. The recess portion of the metal gate electrode and the contact holes are filled with a wiring metal, substantially simultaneously, and thereafter the wiring metal is planarized by polishing. |
| US09343464B2 |
Implementing eDRAM stacked FET structure
A method and circuit for implementing an embedded dynamic random access memory (eDRAM), and a design structure on which the subject circuit resides are provided. The embedded dynamic random access memory (eDRAM) circuit includes a stacked field effect transistor (FET) and capacitor. The capacitor is fabricated directly on top of the FET to build the eDRAM. |
| US09343462B2 |
Thyristor-based memory cells, devices and systems including the same and methods for forming the same
Semiconductor devices including a plurality of thyristor-based memory cells, each having a cell size of 4F2, and methods for forming the same are provided. The thyristor-based memory cells each include a thyristor having vertically superposed regions of alternating dopant types, and a control gate. The control gate may be electrically coupled with one or more of the thyristors and may be operably coupled to a voltage source. The thyristor-based memory cells may be formed in an array on a conductive strap, which may function as a cathode or a data line. A system may be formed by integrating the semiconductor devices with one or more memory access devices or conventional logic devices, such as a complementary metal-oxide-semiconductor (CMOS) device. |
| US09343457B2 |
Semiconductor device
In order to provide a semiconductor device having a high ESD tolerance, a source wiring (32a) is formed on a gate (31) and a source (32) in a region of an NMOS transistor (30). The source wiring (32a) electrically connects the gate (31), the source (32), and a ground terminal. A drain wiring (33a) is formed on a drain (33) in the region of the NMOS transistor (30) . The drain wiring (33a) electrically connects the drain (33) and a pad (20) serving as an external connection electrode. Moreover, in the region of the NMOS transistor (30), the drain wiring (33a) has the same wiring width as the source wiring (32a). |
| US09343456B2 |
Metal gate for robust ESD protection
A method of forming a metal gate diode ESD protection device and the resulting device are provided. Embodiments include forming a metal gate diode including a metal gate on a substrate; forming an n-type cathode on a first side of the metal gate diode; and forming a p-type anode on a second side of the metal gate diode, opposite the first side. |
| US09343454B2 |
Electrostatic discharge protection structure and fabrication method thereof
An electrostatic discharge protection structure includes: substrate of a first type of conductivity, well region of a second type of conductivity, substrate contact region in the substrate and of the first type of conductivity, well contact region in the well region and of the second type of conductivity, substrate counter-doped region between the substrate contact region and the well contact region and of the second type of conductivity, well counter-doped region between the substrate contact region and the well contact region and of the first type of conductivity, communication region at a lateral junction between the substrate and the well region, first isolation region between the substrate counter-doped region and the communication region, second isolation region between the well counter-doped region and the communication region, oxide layer having one end on the first isolation region and another end on the substrate, and field plate structure on the oxide layer. |
| US09343452B2 |
Semiconductor devices having conductive pads and methods of fabricating the same
A semiconductor device includes a substrate having a cell region and a connection region. A plurality of gate electrodes is stacked in a vertical direction in the cell region of the substrate. Conductive pads that are electrically connected to a peripheral circuit extend horizontally from the gate electrodes to the connection region. The conductive pads form a cascade structure in the connection region. Contact plugs that have different vertical lengths are electrically connected to respective ones of the conductive pads. The conductive pads have contact portions that are thicker in the vertical direction than the gate electrodes. |
| US09343451B2 |
Method of manufacturing semiconductor device
To improve the reliability in applying a tape to the rear surface of a substrate while securing the heat resistance of the tape applied to the rear surface of the substrate. There is a gap between a bottom surface of a ditch provided in a support member and an upper surface of a driver IC chip. On the other hand, the upper surface side of a lead frame is supported by the support member so that the bottom surface of the ditch contacts the upper surface of a Low-MOS clip mounted over a Low-MOS chip. Thus, even in a state where the driver IC chip and the Low-MOS chip are mounted on the upper surface side of the lead frame, the tape can be reliably applied to the rear surface of the lead frame (in particular, to the rear surface of the product region). |
| US09343450B2 |
Wafer scale packaging platform for transceivers
A wafer scale implementation of an opto-electronic transceiver assembly process utilizes a silicon wafer as an optical reference plane and platform upon which all necessary optical and electronic components are simultaneously assembled for a plurality of separate transceiver modules. In particular, a silicon wafer is utilized as a “platform” (interposer) upon which all of the components for a multiple number of transceiver modules are mounted or integrated, with the top surface of the silicon interposer used as a reference plane for defining the optical signal path between separate optical components. Indeed, by using a single silicon wafer as the platform for a large number of separate transceiver modules, one is able to use a wafer scale assembly process, as well as optical alignment and testing of these modules. |
| US09343447B2 |
Optically pumped sensors or references with die-to-package cavities
An optoelectronic packaged device includes stacked components within a package including a package substrate providing side and a bottom wall. The stacked components includes a comb structure on the bottom wall formed from a material having a thermal resistance > a substrate material for the bottom die providing spaced apart teeth separated by gaps. The bottom die has a top surface including electrical trace(s) and a light source die for emitting light coupled to the electrical trace and a bottom surface on the comb structure. A first cavity die is on the top surface of the bottom die or on legs of the package which extend above the bottom wall. An optics die is on the first cavity die, a second cavity die is on a sealing die which is on the optics die, and a photodetector (PD) die is optically coupled to receive light from the light source die. |
| US09343446B2 |
Diode lighting arrangement
The invention describes a diode lighting arrangement (1A,1B,1C) comprising a light-emitting diode arrangement (1,2) comprising at least two exposed serially connected light-emitting diodes (1) connected in parallel with an electrostatic discharge protection diode arrangement (2); and an electrostatic discharge diverting arrangement (4,50) extending in physical proximity to an interconnect (10) between adjacent light-emitting diodes (1), which diverting arrangement (4,50) is realized to divert electrostatic discharge (S2) from the interconnect (10) to a region of low potential (21,22, GND). The invention further describes an automotive lighting assembly (3A,3B) comprising such a diode lighting arrangement (1A,1B,1C). The invention also describes a method of manufacturing a diode lighting arrangement (1A,1B,1C) which method comprises the steps of serially connecting a light-emitting diode arrangement (1,2) comprising at least two exposed serially connected light-emitting diodes (1) in parallel with an electrostatic discharge protection diode arrangement (2); and arranging an electrostatic discharge diverting arrangement (4,50,60) to extend in physical proximity to at least one interconnect (10) between adjacent light-emitting diodes (1), which diverting arrangement (4,50) is realized to divert electrostatic discharge (S2) from the interconnect (10) to a region of low potential (21,22, GND). |
| US09343441B2 |
Light emitter devices having improved light output and related methods
Light emitter devices having improved light output and related methods are disclosed. In one embodiment, light emitter devices can include a light emission area including one or more light emitting chips. The emitter device can further include a filling material at least partially disposed over the one or more light emitting chips. The filling material can include a first discrete layer of phosphor containing material and a second discrete layer of optically clear material. The device can optionally include more than one discrete layer of optically clear material. Each of the discrete layers of material can be separately dispensed within the light emission area such that the filling material is dispensed to a level that is substantially flush with an upper surface of the emitter device. |
| US09343437B2 |
Semiconductor package devices
Semiconductor package devices and methods of forming the semiconductor package devices are provided. The semiconductor package devices may include a lower package including a lower semiconductor chip on a lower substrate, an upper package including an upper semiconductor chip on an upper substrate. The upper substrate may include a protruding part corresponding to the lower semiconductor chip and a connection part that has a bottom surface lower than a bottom surface of the protruding part and is disposed around the protruding part. The semiconductor package devices may also include a heat dissipation part in a space between the lower semiconductor chip and the protruding part on the upper substrate and a package connection pattern electrically connecting the lower package to the upper package. |
| US09343435B2 |
Semiconductor device and related manufacturing method
A method for manufacturing a semiconductor device may include providing a first dielectric layer and a first set of conductive pads on a first substrate. Each conductive pad of the first set of conductive pads may be positioned between portions of the first dielectric layer. The method may further include providing a first insulating material layer to cover the first dielectric layer and the first set of conductive pads. The method may further include removing portions of the first insulating material layer to form a first insulating layer. Openings of the first insulating layer may expose the first set of conductive pads. |
| US09343434B2 |
Laser marking in packages
A package includes a device die, a first plurality of redistribution lines underlying the device die, a second plurality of redistribution lines overlying the device die, and a metal pad in a same metal layer as the second plurality of redistribution lines. A laser mark is in a dielectric layer that is overlying the metal pad. The laser mark overlaps the metal pad. |
| US09343431B2 |
Dam structure for enhancing joint yield in bonding processes
A package structure includes a bottom package component, a top package component overlying and bonded to the bottom package component, and a dam between the bottom package component and the top package component. The dam has a top surface attached to a bottom surface of the top package component, and a bottom surface spaced apart from a top surface of the bottom package component. |
| US09343429B2 |
Semiconductor device and method of forming double-sided through vias in saw streets
A semiconductor device is made by creating a gap between semiconductor die on a wafer. An insulating material is deposited in the gap. A first portion of the insulating material is removed from a first side of the semiconductor wafer to form a first notch. The first notch is less than a thickness of the semiconductor die. A conductive material is deposited into the first notch to form a first portion of the conductive via within the gap. A second portion of the insulating material is removed from a second side of the semiconductor wafer to form a second notch. The second notch extends through the insulating material to the first notch. A conductive material is deposited into the second notch to form a second portion of the conductive via within the gap. The semiconductor wafer is singulated through the gap to separate the semiconductor die. |
| US09343417B2 |
Hollow metal pillar packaging scheme
An integrated circuit includes a bottom substrate, a metal layer disposed over the bottom substrate and a hollow metal pillar disposed on the metal layer. The metal layer and the hollow metal pillar are electrically connected. |
| US09343415B2 |
Copper post structure for wafer level chip scale package
In a method for forming a packaging structure, a metal pad is formed on a semiconductor substrate, and a first polymer insulating layer is formed over the semiconductor substrate. An opening passing through the first polymer insulating layer is formed to expose a portion of the metal pad. A copper-containing material is deposited in the opening and over the first polymer insulating layer, thereby forming a copper-containing layer having a first thickness and a first width over the first polymer insulating layer. A conductive bump having a second width is formed over the copper-containing layer, in which the second width is smaller than the first width. An exposed portion of the copper-containing layer is etched using the conductive bump as a mask until the exposed portion is reduced to a second thickness, thereby forming a monolithic copper-containing structure. |
| US09343413B2 |
ESD protection for high voltage applications
An ESD module includes an ESD circuit coupled between a first source and a second source. A trigger circuit is also included in the ESD module for activating the ESD circuit to provide a low resistance current path between the first and second sources. The trigger circuit includes a reverse diode between the first source and the ESD circuit or between the second source and main ESD circuit. The trigger circuit provides a low trigger voltage to activate the ESD circuit. |
| US09343412B2 |
Method of forming MOSFET structure
A method of forming a MOSFET structure is provided. In the method, an epitaxial layer is formed. A cap layer is formed above the epitaxial layer. A first trench is formed above the epitaxial layer. A protection layer is deposited within the first trench. The protection layer is a material selected from the group consisting of germanium and silicon-germanium. |
| US09343405B2 |
Semiconductor device and method of manufacturing the same
A semiconductor device includes a substrate; a stack structure including a plurality of insulating films and a plurality of metal films disposed alternately one above another. The stack structure is provided above the substrate and has a stairway portion including a plurality of terraces located at least at one end portion thereof. A liner film and a stopper film are disposed so as to cover an upper portion the stack structure in the stairway portion formed of the terraces. A plurality of holes are connected to each of the terraces. Each of the terraces is formed of a stack of the insulating films and the metal films. Each of the holes extends through the stopper film and the liner film and connect to the metal films of the terraces. |
| US09343402B2 |
Semiconductor device having Ti- and N-containing layer, and manufacturing method of same
A manufacturing method of a semiconductor device comprises releasing an oxidation source included in an interlayer dielectric film having an opening portion formed on a surface thereof and being present on the surface of the interlayer dielectric film at a first substrate temperature, forming a first layer containing Ti and N to contact with at least a part of the interlayer dielectric film at a second substrate temperature lower than the first substrate temperature, wherein a Ti content in the first layer is more than 50 at % in all components, provided that oxygen and precious metals are excluded from the all components, and forming a Cu metal layer above the first layer. |
| US09343401B2 |
Semiconductor package and fabrication method thereof
A method for fabricating a semiconductor package is provided, which includes the steps of: providing a packaging substrate having a first surface with a plurality of bonding pads and an opposite second surface; disposing a plurality of passive elements on the first surface of the packaging substrate; disposing a semiconductor chip on the passive elements through an adhesive film; electrically connecting the semiconductor chip and the bonding pads through a plurality of bonding wires; and forming an encapsulant on the first surface of the packaging substrate for encapsulating the semiconductor chip, the passive elements and the bonding wires. By disposing the passive elements between the packaging substrate and the semiconductor chip, the invention saves space on the packaging substrate and increases the wiring flexibility. Further, since the bonding wires are not easy to come into contact with the passive elements, the invention prevents a short circuit from occurring. |
| US09343398B2 |
BGA ballout partition techniques for simplified layout in motherboard with multiple power supply rail
A microelectronic package can include a substrate and a microelectronic element. The substrate can include terminals comprising at least first power terminals and other terminals in an area array at a surface of the substrate. The substrate can also include a power plane element electrically coupled to the first power terminals. The area array can have a peripheral edge and a continuous gap between the terminals extending inwardly from the peripheral edge in a direction parallel to the surface. The terminals on opposite sides of the gap can be spaced from one another by at least 1.5 times a minimum pitch of the terminals. The power plane element can extend within the gap from at least the peripheral edge at least to the first power terminals. Each first power terminal can be separated from the peripheral edge by two or more of the other terminals. |
| US09343397B2 |
Method of connecting a semiconductor package to a board
A method of connecting a semiconductor package to a board includes providing a board having a plurality of contact regions, providing a semiconductor package having a plurality of contact areas, selecting a specific contact area out of the plurality of contact areas, applying solder balls to the contact areas and therein applying two or more specific solder balls to the specific contact area, and connecting the semiconductor package to the board in such a way that the two or more specific solder balls are connected with each other and with a contact region of the plurality of contact regions of the board. |
| US09343396B2 |
Semiconductor device and method of forming IPD in fan-out wafer level chip scale package
A semiconductor wafer contains semiconductor die. A first conductive layer is formed over the die. A resistive layer is formed over the die and first conductive layer. A first insulating layer is formed over the die and resistive layer. The wafer is singulated to separate the die. The die is mounted to a temporary carrier. An encapsulant is deposited over the die and carrier. The carrier and a portion of the encapsulant and first insulating layer is removed. A second insulating layer is formed over the encapsulant and first insulating layer. A second conductive layer is formed over the first and second insulating layers. A third insulating layer is formed over the second insulating layer and second conductive layer. A third conductive layer is formed over the third insulating layer and second conductive layer. A fourth insulating layer is formed over the third insulating layer and third conductive layer. |
| US09343391B2 |
Semiconductor package and method of manufacturing the same
Disclosed herein are a semiconductor package and a method of manufacturing the same. The semiconductor package includes: a substrate including a mounting electrode formed on both sides and a wiring; a plurality of first electronic devices mounted on the substrate; a second electronic devices mounted on the substrate; and a via through which the wiring of the substrate and the second electronic devices are connected. |
| US09343389B2 |
Magnetic contacts
Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed. |
| US09343386B2 |
Alignment in the packaging of integrated circuits
A method includes aligning a top package to a bottom package using an alignment mark in the bottom package, and placing the top package over the bottom package, wherein the top package is aligned to the bottom package after the placing the top package over the bottom package. A reflow is then performed to bond the top package to the bottom package. |
| US09343382B2 |
Electronic device and manufacturing method thereof
An electronic device includes a substrate; an element configured to be formed on the substrate; a sidewall member configured to enclose the element on the substrate; a cover member configured to be disposed on the sidewall member, and to partition a space around the element along with the sidewall member on the substrate; and a seal member configured to be disposed outside of the sidewall member, to bond the sidewall member and the cover member to a surface of the substrate, and to seal the space. |
| US09343381B2 |
Semiconductor component with integrated crack sensor and method for detecting a crack in a semiconductor component
A first embodiment relates to a semiconductor component. The semiconductor component has a semiconductor body with a bottom side and a top side spaced distant from the bottom side in a vertical direction. In the vertical direction, the semiconductor body has a certain thickness. The semiconductor component further has a crack sensor configured to detect a crack in the semiconductor body. The crack sensor extends into the semiconductor body. A distance between the crack sensor and the bottom side is less than the thickness of the semiconductor body. |
| US09343380B2 |
High-frequency power amplifier and method for manufacturing the same
A high-frequency power amplifier includes: a semiconductor substrate; transistor cells separated from each other and located on the semiconductor substrate; and testing electrodes respectively connected to individual transistor cells, wherein an electrical signal and power to individually operate each corresponding transistor cell are supplied to each transistor cell, independently, from outside, using the testing electrodes. |
| US09343376B1 |
Method of fabricating a semiconductor device
A method of fabricating a semiconductor device includes following steps. First of all, a first nanowire structure and a second nanowire structure are formed on a substrate. Next, a compressive stress layer is formed on the first nanowire structure, and the first nanowire structure is driven to a compressive nanowire structure. Then, a tensile stress layer is formed on the second nanowire structure, and the second nanowire structure is driven into a tensile nanowire structure. |
| US09343367B2 |
Integrated device die and package with stress reduction features
An integrated device die and package is disclosed. The integrated device die includes a unitary body. The unitary body can have an upper portion comprising one or more active components. The upper portion can have first and second opposing lateral sides defining at least a portion of a periphery of the upper portion such that an upper surface of the upper portion is disposed between upper edges of the first and second opposing lateral sides. The unitary body can also have a lower portion monolithically formed with the upper portion. The lower portion can comprise a pedestal extending downwardly from the upper portion. The pedestal can be laterally inset from lower edges of the first and second opposing lateral sides. The pedestal can include a distal end portion configured to couple to a carrier. |
| US09343366B2 |
Dicing wafers having solder bumps on wafer backside
Approaches for hybrid laser scribe and plasma etch dicing process for a wafer having backside solder bumps are described. For example, a method of dicing a semiconductor wafer having integrated circuits on a front side thereof and corresponding arrays of metal bumps on a backside thereof involves applying a dicing tape to the backside of the semiconductor wafer, the dicing tape covering the arrays of metal bumps. The method also involves, subsequently, forming a mask on the front side of the semiconductor wafer, the mask covering the integrated circuits. The method also involves forming scribe lines on the front side of the semiconductor wafer with a laser scribing process, the scribe lines formed in the mask and between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the scribe lines to singulate the integrated circuits, the mask protecting the integrated circuits during the plasma etching. |
| US09343365B2 |
Method and apparatus for plasma dicing a semi-conductor wafer
The present invention provides a method for plasma processing a substrate, the method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; loading a work piece onto the work piece support, the work piece having a support film, a frame and the substrate; providing at least two cutting regions on the substrate, the cutting regions being positioned between all adjacent device structures on the substrate; generating a plasma using the plasma source; and processing the work piece using the generated plasma. |
| US09343364B2 |
Semiconductor device and method for manufacturing the same
A semiconductor device includes a semiconductor substrate having two surfaces. First side faces second side and includes recesses, and a plurality of through silicon vias (TSV), which penetrate through the semiconductor substrate, are exposed by the recesses. Even when the TSVs have different heights from each other or the degree of back-grinding is changed, due to a process parameters, yield of the semiconductor device is improved by reducing failure caused when a TSV is not exposed. |
| US09343362B2 |
Microelectronic devices with through-silicon vias and associated methods of manufacturing
Microelectronic devices with through-silicon vias and associated methods of manufacturing such devices. One embodiment of a method for forming tungsten through-silicon vias comprising forming an opening having a sidewall such that the opening extends through at least a portion of a substrate on which microelectronic structures have been formed. The method can further include lining the sidewall with a dielectric material, depositing tungsten on the dielectric material such that a cavity extends through at least a portion of the tungsten, and filling the cavity with a polysilicon material. |
| US09343355B2 |
Wiring structures including spacers and an airgap defined thereby, and methods of manufacturing the same
A method of manufacturing a wiring structure may include forming a first conductive pattern on a substrate, forming a hardmask on the first conductive pattern, forming a first spacer on sidewalls of the first conductive pattern and the hardmask, forming a first sacrificial layer pattern on a sidewall of the first spacer, forming a second spacer on a sidewall of the first sacrificial layer pattern, removing the first sacrificial layer pattern, and forming a third spacer on the second spacer, may be provided. The third spacer may contact an upper portion of the sidewall of the first spacer and define an air gap in association with the first and second spacers. The first spacer has a top surface substantially higher than a top surface of the first conductive pattern. The second spacer has a top surface substantially lower than the top surface of the first spacer. |
| US09343354B2 |
Middle of line structures and methods for fabrication
A contact structure includes a permanent antireflection coating formed on a substrate having contact pads. A patterned dielectric layer is formed on the antireflective coating. The patterned dielectric layer and the permanent antireflective coating form openings. The openings correspond with locations of the contact pads. Contact structures are formed in the openings to make electrical contact with the contacts pads such that the patterned dielectric layer and the permanent antireflective coating each have a conductively filled region forming the contact structures. |
| US09343353B2 |
SOI structure for signal isolation and linearity
Disclosed is a structure for improved electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and an associated method for the structure's fabrication. The structure comprises a first portion of a trench extending through the top semiconductor layer and through a base oxide layer below the top semiconductor layer. A handle wafer is situated below the base oxide layer and a second portion of the trench, having sloped sidewalls, extends into the handle wafer. The sloped sidewalls are amorphized by an implant, for example, Xenon or Argon, to reduce carrier mobility in the handle wafer and improve electrical signal isolation between the adjacent devices situated in the top semiconductor layer. |
| US09343348B2 |
Substrate-product substrate combination and device and method for producing a substrate-product substrate combination
The invention relates to a substrate for producing a substrate-product substrate combination by aligning, bringing into contact, and bonding a contact side of the large-area substrate to a support surface of a carrier substrate, whereby the substrate has a diameter d1, which can be reduced during back-thinning. |
| US09343344B2 |
End effector device
The end effector device includes a hand having a storing space, and a plurality of holding portions provided to the hand and configured to respectively peripheral portions of each plate member. Each holding portion includes a plurality of receiving portions which respectively receive a plurality of plate members keeping vertical pitches among them, and a pitch changing mechanism configured to change intervals by vertically moving the plurality of receiving portions respectively. A plurality of linearly moving portions configured to respectively move linearly integrally with the plurality of receiving portions are provided to the hand being exposed outside of the hand, and a plurality of drive portions configured to drive the plurality of linearly moving portions of the pitch changing mechanism are stored in the storing space of the hand. |
| US09343341B2 |
End effector device and substrate conveying robot including end effector device
An end effector device attached to a tip end portion of a robot arm includes a plurality of support units provided on a blade. Each of the support units includes: a plurality of nail pieces configured to support peripheral portions of a plurality of semiconductor wafers such that the semiconductor wafers are parallel to one another and spaced apart from one another; and a pitch changing mechanism configured to change upper-lower intervals of the nail pieces. The pitch changing mechanism includes: a coil spring configured to support the plurality of nail pieces such that the plurality of nail pieces are spaced apart from one another in an upper-lower direction and elastically deform in the upper-lower direction; and an operating mechanism configured to cause the coil spring to elastically deform in the upper-lower direction. The operating mechanism includes a piston pin fitted in the coil spring to move up and down. |
| US09343340B2 |
Vacuum processing apparatus
A vacuum processing apparatus is disclosed for processing workpieces. The apparatus includes a load lock adapted to store the workpiece inside and to be switched between atmosphere and vacuum. Vacuum transport chambers are connected to the load lock and to the corresponding process chambers in a state where the load lock and each of the process chambers are isolated. The workpiece can be transferred between each of the process chambers and the load lock via the corresponding vacuum transport chamber. The apparatus also includes load lock valves for switching between interrupt and opening between the load lock and the corresponding vacuum transport chambers, and process chamber valves for switching between interrupt and opening between the process chambers and the corresponding vacuum transport chambers. Timing for opening and closing the valves is controlled in synchronization with the transfer of the workpieces. |
| US09343335B1 |
Cleaning photoresist nozzles for coater module
Methods and systems for cleaning photoresist dispense nozzles of a wafer processing photoresist coater module are disclosed. A method comprises dispensing a photoresist cleaning solvent from an edge bead removal dispense of the coater module onto a central portion of a substrate disposed on a spin chuck to form a puddle, making contact between the photoresist dispense nozzles and the puddle and washing for a select amount of time, thereby removing photoresist from the photoresist dispense nozzles. A system comprises a process controller controlling positioning of the photoresist dispense nozzles over the substrate, positioning of the edge bead dispense over the central portion of the wafer, dispensing photoresist cleaning solvent on the central portion of the wafer, and positioning of the spin chuck such that the photoresist dispense nozzles contact the solvent for cleaning. |
| US09343334B2 |
Electronic component and method for manufacturing electronic component
An electronic component comprises: a resin frame; a semiconductor substrate housed in the resin frame; a plate shape metal member having at least one end fixed in the resin frame at a position spaced apart from the semiconductor substrate; an electrical connection region portion formed on the surface on the side of the plate shape metal member of the semiconductor substrate with an electrically conductive material; and a solder layer formed on the surface on the side of the plate shape metal member of the electrical connection region portion, wherein the plate shape metal member supports the semiconductor substrate without contact through the solder layer and the electrical connection region portion, and is electrically connected to the electrical connection region portion. |
| US09343333B2 |
Wafer level semiconductor package and manufacturing methods thereof
A semiconductor package includes at least one semiconductor die having an active surface, an interposer element having an upper surface and a lower surface, a package body, and a lower redistribution layer. The interposer element has at least one conductive via extending between the upper surface and the lower surface. The package body encapsulates portions of the semiconductor die and portions of the interposer element. The lower redistribution layer electrically connects the interposer element to the active surface of the semiconductor die. |
| US09343332B2 |
Alignment to multiple layers
A method of aligning a new pattern to more than one previously defined pattern during the manufacture of an integrated circuit. A method of aligning a photolighography pattern reticle to a first previously defined pattern in a first direction and also aligning the photolithography pattern reticle to a second previously defined pattern in a second direction. A method of aligning a photolighography pattern reticle to two previously defined patterns in the same direction. |
| US09343329B2 |
Contact formation in Ge-containing semiconductor devices
A process for creating a contact on a Ge-containing contact region of a semiconductor structure, said process comprising the steps of: providing said semiconductor structure comprising: (i) a Ge-containing contact region, (ii) optionally, a SiO2 layer coating said Ge-containing contact region, (iii) a Si3N4 layer coating said SiO2 layer if present or said Ge-containing contact region; etching selectively the Si3N4 layer by means of an inductively coupled plasma, thereby exposing the underlying SiO2 layer if present or the Ge-containing contact region; etching selectively the SiO2 layer if present, thereby exposing the SiGe:B contact region; and creating said contact on said Ge-containing contact region. |
| US09343328B2 |
Photolithographic, thickness non-uniformity, compensation features for optical photolithographic semiconductor structure formation
A semiconductor structure having a substrate; an active device formed in an active semiconductor region of the substrate, the active device having a control electrode for controlling a flow of carriers through the active semiconductor region between a pair of electrical contacts; and a photolithographic, thickness non-uniformity, compensation feature, disposed on the surface substrate off of the active semiconductor region. In one embodiment the feature comprises pads on the surface of the substrate and off of the active semiconductor region. |
| US09343324B2 |
Resist underlayer film-forming composition which contains alicyclic skeleton-containing carbazole resin
There is provided a resist underlayer film used in lithography process that has a high n value and a low k value, and can effectively reduce reflection of light having a wavelength of 193 nm from the substrate in a three-layer process in which the resist underlayer film is used in combination with a silicon-containing intermediate layer. A resist underlayer film-forming composition used in lithography process including: a polymer containing a unit structure including a product obtained by reaction of a condensed heterocyclic compound and a bicyclo ring compound. The condensed heterocyclic compound is a carbazole compound or a substituted carbazole compound. The bicyclo ring compound is dicyclopentadiene, substituted dicyclopentadiene, tetracyclo[4.4.0.12,5.17,10]dodeca-3,8-diene, or substituted tetracyclo[4.4.0.12,5.17,10]dodeca-3,8-diene. |
| US09343322B2 |
Three dimensional stacking memory film structure
A memory device includes a plurality of stacks of alternating active strips and insulating strips. The insulating strips have effective oxide thicknesses (EOT) so that the stacks have non-simple spatial periods on a line through the alternating active strips and insulating strips. A plurality of conductive lines are arranged orthogonally over, and have surfaces conformal with, the plurality of stacks, defining a multi-layer array of interface regions at cross-points between side surfaces of the active strips in the stacks and the conductive lines. Memory elements are disposed in the interface regions, which establish a 3D array of memory cells accessible via the plurality of active strips and the plurality of conductive lines. The insulating strips in the stacks can include a first group of strips having a first EOT and a second group of strips having a second EOT that is greater than the first EOT. |
| US09343318B2 |
Salicide formation using a cap layer
A semiconductor device having a source feature and a drain feature formed in a substrate. The semiconductor device having a gate stack over a portion of the source feature and over a portion of the drain feature. The semiconductor device further having a first cap layer formed over substantially the entire source feature not covered by the gate stack, and a second cap layer formed over substantially the entire drain feature not covered by the gate stack. A method of forming a semiconductor device including forming a source feature and drain feature in a substrate. The method further includes forming a gate stack over a portion of the source feature and over a portion of the drain feature. The method further includes depositing a first cap layer over substantially the entire source feature not covered by the gate stack and a second cap layer over substantially the entire drain feature not covered by the gate stack. |
| US09343315B2 |
Method for fabricating semiconductor structure, and solid precursor delivery system
A method for fabricating a semiconductor structure is provided, including: providing a solid precursor having a first average particle size; solving the solid precursor in an organic solvent into an intermediate; recrystallizing the intermediate to form solid granules, wherein the solid granules has a second average particle size larger than the first average particle size; vaporizing the solid granules to form a film-forming gas; and depositing the film-forming gas on a substrate to form a resistance film. A method for modifying a resistance film source in a semiconductor fabrication and a solid precursor delivery system are also provided. The method for fabricating a semiconductor structure in the present disclosure can remove small particles or ultra-small particles from solid precursor, and does not need extra time to dump cracked solid precursor. |
| US09343314B2 |
Split gate nanocrystal memory integration
A method of making a split gate non-volatile memory (NVM) includes forming a charge storage layer on the substrate, depositing a first conductive layer, and depositing a capping layer. These layers are patterned to form a control gate stack. A second conductive layer is deposited over the substrate and is patterned to leave a first portion of the second conductive layer over a portion of the control gate stack and adjacent to a first side of the control gate stack. The first portion of the second conductive layer and the control gate stack are planarized to leave a dummy select gate from the first portion of the second conductive layer, where a top surface of a remaining portion of the first conductive layer is lower relative to a top surface of the dummy select gate. The dummy select gate is replaced with a select gate including metal. |
| US09343307B2 |
Laser spike annealing using fiber lasers
The disclosure is directed to laser spike annealing using fiber lasers. The method includes performing laser spike annealing of a surface of a wafer by: generating with a plurality of fiber laser systems respective CW output radiation beams that partially overlap at the wafer surface to form an elongate annealing image having a long axis and a length LA along the long axis; heating at least a region of the wafer to a pre-anneal temperature TPA; and scanning the elongate annealing image over the wafer surface and within the pre-heat region so that the annealing image has a dwell time tD in the range 30 ns≦tD≦10 ms and raises the wafer surface temperature to an annealing temperature TA. |
| US09343306B2 |
Method of fabricating thin film transistor array substrate having polysilicon with different grain sizes
A thin film transistor array substrate includes a substrate, a plurality of poly-silicon islands and a plurality of gates. The substrate has a display region, a gate driver region and a source driver region. Each poly-silicon island disposed on the substrate has a source region, a drain region and a channel region disposed therebetween. The poly-silicon islands include several first poly-silicon islands and several second poly-silicon islands. The first poly-silicon islands having main grain boundaries and sub grain boundaries are only disposed within the display region and the gate driver region. The main grain boundaries of the first poly-silicon islands are only disposed within the source regions and/or the drain regions. The second poly-silicon islands are disposed in the source driver region. Grain sizes of the first poly-silicon islands are substantially different from those of the second poly-silicon islands. Gates corresponding to the channel regions are disposed on the substrate. |
| US09343304B2 |
Method for depositing films on semiconductor wafers
An exemplary embodiment of the present invention provides a method of depositing of a film on semiconductor wafers. In a first step, a film thickness of 3 um or less is deposited on wafers accommodated in a wafer boat in a vertical furnace at a deposition temperature of the furnace while a deposition gas is flowing. During the first step, the temperature may be held substantially constant. In a second step, a temperature deviation or variation of at least 50° C. from the deposition temperature of the first step is applied and the furnace temperature is returned to the deposition temperature of the first step while the flow of the deposition gas is stopped. The first and second steps are repeated until a desired final film thickness is deposited. |
| US09343303B2 |
Methods of forming low-defect strain-relaxed layers on lattice-mismatched substrates and related semiconductor structures and devices
Methods of forming strain-relaxing semiconductor layers are provided in which a porous region is formed in a surface of a semiconductor substrate. A first semiconductor layer that is lattice-matched with the semiconductor substrate is formed on the porous region. A second semiconductor layer is formed on the first semiconductor layer, the second semiconductor layer being a strained layer as formed. The second semiconductor layer is then relaxed. |
| US09343301B2 |
Quantum dots made using phosphine
A process is disclosed for producing quantum dots (QDs) by reacting one or more core semiconductor precursors with phosphine in the presence of a molecular cluster compound. The core semiconductor precursor(s) provides elements that are incorporated into the QD core semiconductor material. The core semiconductor also incorporates phosphorus, which is provided by the phosphine. The phosphine may be provided to the reaction as a gas or may, alternatively, be provided as an adduct of another material. |
| US09343298B2 |
Metal-insulator-metal capacitor and method for manufacturing thereof
The disclosure provides a method for producing a stack of layers on a semiconductor substrate. The method includes producing a substrate a first conductive layer; and producing by ALD a sub-stack of layers on said conductive layer, at least one of said layers of the sub-stack being a TiO2 layer, the other layers of the sub-stack being layers of a dielectric material having a composition suitable to form a cubic perovskite phase upon crystallization of said sub-stack of layers. Crystallization is obtained via heat treatment. When used in a metal-insulator-metal capacitor, the stack of layers can provide improved characteristics as a consequence of the TiO2 layer being present in the sub-stack. |
| US09343295B2 |
Vaporizing unit, film forming apparatus, film forming method, computer program and storage medium
A vaporizing unit, in supplying a gas material produced by vaporizing a liquid material onto a substrate to conduct a film forming process, can vaporize the liquid material with high efficiency to suppress generation of particles. With the vaporizing unit, positively or negatively charged bubbles, which have a diameter of 1000 nm or less, are produced in the liquid material, and the liquid material is atomized to form a mist of the liquid material. Further, the mist of the liquid material is heated and vaporized. The fine bubbles are uniformly dispersed in advance in the liquid material, so that very fine and uniform mist particles of the liquid material are produced when the liquid material is atomized, which makes heat exchange readily conducted. By vaporizing the mist of the liquid material, vaporization efficiency is enhanced, and generation of particles can be suppressed. |
| US09343294B2 |
Interconnect structure having air gap and method of forming the same
A method for forming a semiconductor device includes forming a first dielectric layer overlying a substrate, forming at least a first opening in the first dielectric layer, forming a conformal dense layer lining the at least first opening in the first dielectric layer, forming a barrier layer overlying the conformal dense layer, forming a conductive feature in the at least first opening, removing a portion of the first dielectric layer between any two adjacent conductive features to form a second opening, wherein the second opening exposes the conformal dense layer between the two adjacent conductive features, and depositing between the two adjacent conductive features a second dielectric layer having an air gap formed therein. |
| US09343292B2 |
Stacked semiconductor device, and method and apparatus of manufacturing the same
Provided is a method of manufacturing a stacked semiconductor device, which includes forming a stacked film on a semiconductor substrate, the stacked film including a plurality of silicon oxide films and a plurality of silicon nitride films, which are alternately arranged on top of each other, and the stacked film being obtained by repeatedly performing a series of operations of forming the silicon oxide film on the semiconductor substrate using one of triethoxysilane, octamethylcyclotetrasiloxane, hexamethyldisilazane and diethylsilane gases, and forming the silicon nitride film on the formed silicon oxide film; etching the silicon nitride films in the stacked film; removing carbons contained in the silicon oxide films, which are not removed in the etching, to reduce a concentration of the carbons; and forming electrodes in regions where the silicon nitride films are etched in the etching. |
| US09343285B2 |
Annular ion guide
An annular ion guide is disclosed comprising inner and outer electrodes. Ions are confined within an annular ion guiding region by RF or pseudo-potential barriers in both an outward and inward radial direction. |
| US09343284B2 |
Ion trap mass spectrometer
An electrostatic mass spectrometer and a method of mass spectrometric analysis utilizing novel traps are disclosed. The mass spectrometer includes an ion source, an ion pulse injector, an ion detector, a set of analyzer electrodes connected to a set of power supplies, and a vacuum chamber enclosing the set of analyzer electrodes. The analyzer electrodes have multiple sets of elongated slits forming an array of elongated volumes. Each elongated volume is formed by a single set of slits aligned between the electrodes, and each volume forms a two-dimensional electrostatic field in an X-Y plane and is extended in a locally orthogonal Z-direction. Each two-dimensional field is arranged to trap moving ions in the X-Y plane and to enable isochronous ion motion along a mean ion trajectory within the X-Y plane. |
| US09343283B1 |
Internal standardization with enriched stable isotopes and cool plasma ICPMS
A method for internal standardization of cool plasma ICP-MS using one or more enriched stable isotopes includes introducing an enriched stable isotope of a chemical species to a sample containing a non-enriched isotope of the chemical species to form a sample and standard mixture. In implementations, the enriched stable isotope is introduced via an inline syringe addition to a flow of a sample solution containing a non-enriched isotope of the chemical species to be analyzed. The method also includes introducing the sample and standard mixture to an ICP-MS under cool plasma conditions. The method also includes determining an ionization amount of the enriched stable isotope by the ICP-MS. The method further includes correlating an ionization amount of the non-enriched isotope based on the determined ionization amount of the enriched stable isotope. |
| US09343281B2 |
Methods and apparatus for increased ion throughput in tandem mass spectrometers
In a tandem mass spectrometry system, a first mass analyzer filters parent ions using a wide mass passband with a narrow rejection notch defined according to a modulation format. A wide mass range of parent ions is transmitted to an ion fragmentation device. Daughter ions produced thereby are transmitted to a second mass analyzer to produce a daughter ion mass spectrum. The modulation of the measured daughter ion mass spectrum, when correlated with the passband modulation of the first mass analyzer (i.e., parent ion spectrum), allows definitive identification of each daughter mass peak with the appropriate parent ion. Due to the wide mass passband, the ion detector signal is in proportion to the increased ion flux passed by the first mass analyzer. |
| US09343279B2 |
Data independent acquisition of product ion spectra and reference spectra library matching
Systems and methods are disclosed for identifying detectable compounds of a sample. Sample product ion spectra are received for each mass selection window of precursor mass selection windows for each time step. The received sample product ion spectra are searched for the presence of known compounds of interest with known product ion spectra by retrieving a known product ion spectrum from a library, retrieving the sample product ion spectra corresponding to the precursor mass selection window expected to contain a precursor ion corresponding to the known product ion spectrum, generating product ion traces in time for the retrieved sample product ion spectra, calculating a score for the product ion traces and the retrieved sample product ion spectra that represents how well the retrieved sample product ion spectra and the known product ion spectrum match, and confirming the identity of a precursor ion using the score. |
| US09343276B2 |
Use of windowed mass spectrometry data for retention time determination or confirmation
A scan of a separating sample is received by a mass spectrometer at each interval of a plurality of intervals. The spectrometer performs at each interval one or more mass spectrometry scans. The scans have one or more sequential mass window widths in order to span an entire mass range at each interval and produce a collection of spectra for the entire mass range for the plurality of intervals. One or more peaks at one or more different intervals in the collection of spectra are identified for a fragment ion. A mass spectrum of the entire mass range is retrieved for each interval of each peak. Values for one or more ion characteristics of a mass-to-charge ratio peak in the mass spectrum corresponding to each peak are compared to one or more known values for the fragment ion. Each peak is scored based on the comparison. |
| US09343271B2 |
Apparatus for generating thermodynamically cold microwave plasma
The invention relates to an apparatus for generating a thermodynamically cold plasma under standard atmospheric conditions by injecting microwave radiation at a frequency of >3 GHz into a plasma chamber (6) and subsequent superposition of a plurality of waves with constructive interference. The microwave radiation, which is generated in specifically geometrically arranged, preferably cylindrical resonant cavities in an evacuated anode block, is coupled out via hollow waveguides (5) and fed to a separated plasma chamber (6). Using the combination of a plurality of microwave generators (7) it is possible to inject a multiplicity of microwaves into the plasma chamber (6). A material stream, for example a process gas, can be fed in through an inlet (9) at the upper side of the plasma chamber and be discharged through an outlet for example in nozzle form at the lower side of the plasma chamber (6) and be fed to the surface that is to be processed. |
| US09343257B2 |
Circuit breaker with a magnet fixing means
The present invention provides a magnet fixing means having a circuit breaker including a heater generating heat due to a conduction current induced to a moving contact of the circuit breaker; a bimetal deformed due to heat generated by the heater to separate a contact point of the moving contact; a magnet generating a magnetic force to move an armature bar when a current above a previously set reference current is induced; a trip case accommodating the bimetal and magnet, at least part of which is made of a synthetic resin material; a magnet fixing portion integrally formed in the trip case, and made of a synthetic resin material; a magnet fixing means fastening the magnet to the magnet fixing portion; and a bimetal fixing means fixing the bimetal to the heater, where a magnet-side separating gap exists between the magnet and the heater such that the heater does not contact the magnet. |
| US09343254B2 |
Battery relay for automobile
Disclosed is a battery relay for a vehicle. The battery relay has a strengthened operation structure, which includes divided upper plunger and lower plunger by dualizing an internal plunger and induces shocks of the upper plunger and the lower plunger upon initial movement of the lower plunger thereby minimizing the amount of arc generated upon contact and improving durability by shortening a switching time between a movable contact and a fixed contact. |
| US09343249B2 |
Pressure and rotationally actuated control element for a motor vehicle
A pressure and rotationally actuated control element for a vehicle steering wheel includes a bearing block and an input element. The bearing block is mounted on actuating elements of switching elements. The input element is mounted rotatably on the bearing block. The input element transmits a rotational actuation to a code disk and an actuating pressure on the input element actuates at least one of the switching elements. The bearing block forms two swivel pins perpendicular to the axis of rotation of the input element and which are supported by the actuating elements of switching elements. The bearing block has a stop element between the swivel pins which limits the path of actuation of the input element by an actuating pressure. |
| US09343246B2 |
Trigger switch
Disclosed a trigger switch including: a case having a switch chamber in which a switch mechanism is arranged in a sealed state; a plunger inserted slidably into a shaft hole formed on one end side of the case, coupled to the switch mechanism, and biased forward; and a trigger provided on a distal end of the plunger for operating the switch, wherein the switch mechanism includes an air pressure stabilizing mechanism configured to cancel an air compressing action in the interior of the switch chamber caused by the switch mechanism moving in the interior of the switch chamber. The air pressure stabilizing mechanism includes a communication hole extending from a rear end opening facing the switch chamber to a distal end opening on the plunger, and a plunger-engaging portion of the trigger includes a discharge port communicating with the communication hole and configured to release air from the communicating hole. |
| US09343242B2 |
Method of making contact posts for a microelectromechanical device
A device 20 includes a substrate 22 coupled with a substrate 24 such that a volume 32 is formed between the substrates 22, 24. Contact posts 48, 50 on the substrate 22 and a cantilever beam structure 36 on the substrate 24 are located within the volume 32. The cantilever beam structure has a conductive trace 38 that is selectively contactable with the contact posts 48, 50 to yield a microelectromechanical (MEMS) switch within the volume 32. Fabrication methodology for making the contact posts 48, 50 entails forming post protrusions 68, 70 on the substrate 22 and shaping post protrusions 68, 70 so that they acquire a rounded shape. Input and output signal lines 42, 44 are constructed such that respective portions of input and output signal lines 42, 44 overly corresponding post protrusions 68, 70 and take on the shape of post protrusions 68, 70. |
| US09343235B2 |
Multilayer ceramic capacitor and assembly board having the same
A multilayer ceramic capacitor may include: a ceramic body having upper and lower surfaces opposing each other in a thickness direction thereof and first and second end surfaces opposing each other in a length direction thereof, a thickness of the ceramic body being greater than a width thereof; a first external electrode disposed on the first end surface to allow a predetermined region of the first end surface adjacent to the upper surface to be exposed; a second external electrode disposed on the second end surface to allow a predetermined region of the second end surface adjacent to the upper surface to be exposed; and first and second internal electrodes disposed within the ceramic body, stacked in a width direction of the ceramic body, and connected to the first and second external electrodes, respectively. |
| US09343233B2 |
Additively deposited electronic components and methods for producing the same
An exemplary embodiment of the present invention provides a passive electrical component comprising a substrate, a first electrically conductive layer, a first dielectric layer, and a second electrically conductive layer. The first electrically conductive layer can be additively deposited on the substrate. The first dielectric layer can be additively deposited on the first conducive layer. The first dielectric layer can comprise a cross-linked polymer. The second electrically conductive layer can be additively deposited on the first dielectric layer. The resonant frequency of the passive electrical component can exceed 1 gigahertz. |
| US09343226B2 |
Entering a battery power down mode using over-the-air command for wireless devices
A wireless electronic device includes a rechargeable battery, a receiver, and a shut down module. The rechargeable battery is at least partially charged. The receiver is configured to enable wireless communications for the wireless device. The receiver is capable of receiving wireless commands configured to cause corresponding functions to be performed in the wireless electronic device, which may include test functions, calibration functions, and shut down functions. The shut down module is configured to cause the wireless electronic device to initiate a shut down protocol according to a shut down command received by the receiver. |
| US09343225B2 |
Power receiving device, power transmitting device and control device
There provided a power receiving device connectable with a first load circuit operating according to AC power from a power transmitting device in which the power receiver receives the AC power from the power transmitting device via magnetic coupling, the impedance adjuster is capable of converting at least one of voltage and current of the AC power received at the power receiver, the controller controls increase in output voltage of the power transmitting device, the AC power is supplied to the first load circuit via the impedance adjuster when the first load circuit is connected to the power receiving device, and the controller controls the impedance adjuster such that an input impedance of the impedance adjuster is lower than an input impedance of the first load circuit during at least a part of a time period where the output voltage of the power transmitting device is increased. |
| US09343223B2 |
Reactor
A reactor includes an annular core, coils, a sensor detecting a state of the reactor, and a connector outputting signal from the sensor. Resin-molded bodies are provided around the annular core. The resin-molded body has bobbins for the respective coils and core covering portions formed integrally with each other. An exposed area where no resin covers the bottom of the core is formed in the lower face of the covering portions. A holder to fasten the connector is formed integrally with the upper portion of the covering portion. An assembly including the resin-molded bodies in which the annular core is embedded, and the coils wound around the bobbins are retained in a metal casing. A clearance is formed between the assembly and the casing, and a filler is filled in this clearance. The filler covers the exposed area of the core bottom. |
| US09343222B2 |
Insulation for power transformers
A power transformer is provided that includes a first transformer component, a second transformer component; and an electrical insulator. The electrical insulator is disposed between the first transformer component and the second transformer component. The electrical insulator includes a first layer and a second layer. The first layer has a binder fiber. The binder fiber is a staple fiber coated with a binder material. The second layer has an uncoated staple fiber. The first layer and the second layer are bound together with the binder material. |
| US09343221B2 |
Resin-mold core and reactor using the same
A resin-mold core includes right and left leg portions, and a yoke portion interconnecting those. The resin-mold core includes a magnetic core, and a mold component having the magnetic core embedded therein by molding. Openings where the magnetic core in the mold component is exposed are formed in multiple faces of the mold component that are upper, lower, front, rear, and right and left faces. A part of the yoke portion of the resin-mold core corresponding to a location where terminals are drawn to the exterior of the core from coils attached to the outer circumferences of the leg portions of the core has no opening formed in the multiple faces of the mold component. Positioning members to coaxially align the leg portions of the opposing resin-mold core are formed in abutting faces of the leg portions of the resin-mold core. |
| US09343217B2 |
Electromagnetic positioning device
An electromagnetic actuator with an armature unit (18) that can be driven relative to a stationary core unit (10) in reaction to the application of current to a stationary coil unit (14), which armature unit has a permanent magnetic agent (28) as well as a plunger unit (31), designed so as to interact with an actuation partner, guided out of a magnetically flux-conducting housing (35), wherein, on the outer surface of a shaft section (20) of the armature unit (18) a magnetically non-conducting bushing agent (32) is provided such that in a zero applied current state of the coil unit (14) a permanent magnetic flux (40) of the permanent magnetic agent (28) flows through the core unit (10) and the shaft section (20) so as to hold the armature unit (18) on the core unit (10), and in a state of the core unit (14) in which current is applied the permanent magnetic flux (40′, 40″) is displaced out of the core unit (10) into a housing section (50, 52) of the housing and a permanent magnetic flux circuit is closed by a section (54) of the plunger unit facing towards the housing. |
| US09343216B2 |
Energy efficient bi-stable permanent magnet actuation system
In a bi-stable permanent magnet actuator system, an electrical circuit arrangement for activating bi-stable permanent magnet actuators that is more adaptable to energy saving power sources, includes a power source that can be of any power level, a voltage conditioner, an energy storage device, an output circuit, and a control circuit for controlling delivery of a discharge current from the energy storage device through the output circuit to the control coil of a bi-stable permanent magnet actuators. Thus, low voltage batteries, solar cells, and energy harvesting devices with low average watts (energy per time) can be used as the power source for bi-stable permanent magnet actuators. |
| US09343215B2 |
Solenoid including a dual coil arrangement to control leakage flux
A solenoid includes a magnetic frame, a bobbin having a length, a hold coil, a pick up coil having a length, a fixed pole, a movable armature having a length, and a return spring biasing the armature away from the pole. The solenoid includes a pick up state when the armature and the pole are separated by a magnetic gap, and a holding state when the armature and the pole are proximate each other. The pick up coil is wound around the bobbin for a portion of the length of the bobbin and the hold coil is wound around the bobbin for a remaining portion of the length of the bobbin. The length of the pick up coil is about the same as the length of the armature and is less than the length of the bobbin. |
| US09343210B2 |
Three-phase magnetic cores for magnetic induction devices and methods for manufacturing them
Three-phase magnetic cores for magnetic induction devices (e.g., transformers, coils, chokes), and methods for manufacturing them, are disclosed. The magnetic cores are generally constructed from three generally rectangular magnetic core frames having a stair-stepped configuration extending along side portions of the frames. The frames are arranged to form a triangular prism structure such that side portions of locally adjacent frames are uniformly engaged to form three core legs over which coils of a three-phase magnetic induction device may be placed. |
| US09343208B2 |
Chip resistor and manufacturing method thereof
A method of manufacturing a chip resistor includes forming a resistor assembly in which a conductive member including portions separated from each other in a first direction is provided in a resistance body member; and dividing the resistor assembly into chip resistors, each including a chip-shaped resistance body formed by a part of the resistance body member, a pair of main electrodes formed by a part of the conductive member and separated from each other in the first direction, and a pair of sub-electrodes formed by a part of the conductive member, separated from each other in the first direction, and adjacent to the main electrodes in a second direction perpendicular to the first direction with concave portions recessed in the first direction interposed therebetween, by punching. |
| US09343207B2 |
Resistance change device, and method for producing same
To provide a resistance change device that can be protected from an excess current without enlarging a device size. A resistance change device 1 according to the present embodiment includes a lower electrode layer 3, an upper electrode layer 6, a first metal oxide layer 51, a second metal oxide layer 52, and a current limiting layer 4. The first metal oxide layer 51 is disposed between the lower electrode layer 3 and the upper electrode layer 6, and has a first resistivity. The second metal oxide layer 52 is disposed between the first metal oxide layer 51 and the upper electrode layer 6, and has a second resistivity higher than the first resistivity. The current limiting layer 4 is disposed between the lower electrode layer 3 and the first metal oxide layer 51, and has a third resistivity higher than the first resistivity and lower than the second resistivity. |
| US09343205B2 |
Tubular cable protection and guide device
A tubular cable protection and guide device is provided. The tubular cable protection and cable device includes an elastomer resin sheet that has: an outer circumference wall forming portion, a pair of sidewall forming portions on the left and right sides, and a pair of inner circumference wall forming portions on the left and right sides. The inner circumference wall forming portions have a pair of locking portions. When a cable receiving room is formed, the pair of locking portions is engaged with each other along a sheet longitudinal direction on a flexional inner circumference side, such that the inner circumference wall forming portions form a wall facing the outer circumference wall forming portion. The locking portions each includes a plurality of ridges that extend in the sheet longitudinal direction and are arranged in the transverse direction to be alternately inserted between each other when engaged with each other. |
| US09343204B2 |
Electrical insulator apparatus and methods of retaining an electrical conductor with an electrical insulator apparatus
An electrical insulator apparatus and methods of using the same are provided. The apparatus includes an insulator body formed about a central axis, the insulator body having a plurality of spaced fins positioned along an exterior of the insulator body. A first jaw portion is positioned on an upper portion of the insulator body. A second jaw portion is positioned proximate to the first jaw portion and is movable with respect to the first jaw portion. At least one fastener is connected between the first and second jaw portions. A jaw platform is positioned at least partially between the first and second jaw portions, wherein the first and second jaw portions and the jaw platform form a notch sized to receive an electrical conductor, wherein the jaw platform substantially lies within a first plane angled substantially between 6° and 184° with respect to the central axis of the insulator body. |
| US09343199B2 |
Umbilical
An umbilical for use in the offshore production of hydrocarbons, and in particular to a power umbilical for use in deep water applications, is described comprising a plurality of longitudinal strength members, said strength members having one or more varying characteristics along the length of the umbilical. In this way, the longitudinal strength members in the umbilical can be provided to have for example a higher or greater tensile strength where required, usually nearer to the surface of the water or topside, while having lower or less tensile strength, and usually therefore lower or less weight, where higher or greater strength is not as critical. |
| US09343198B2 |
Polyolefin composition for medium/high/extra high voltage cables with improved electrical breakdown strength
This application relates to a polyolefin composition comprising a polyolefin and an aromatic compound. The polyolefin composition can be used in producing medium and high voltage cables with improved electrical breakdown strength. |
| US09343194B2 |
Process for the formation of a silver back electrode of a passivated emitter and rear contact silicon solar cell
A process for the formation of an electrically conductive silver back electrode of a PERC silicon solar cell comprising the steps: (1) providing a silicon wafer having an ARC layer on its front-side and a perforated dielectric passivation layer on its back-side, (2) applying and drying a silver paste to form a silver back electrode pattern on the perforated dielectric passivation layer on the back-side of the silicon wafer, and (3) firing the dried silver paste, whereby the wafer reaches a peak temperature of 700 to 900° C., wherein the silver paste has no or only poor fire-through capability and comprises particulate silver and an organic vehicle. |
| US09343193B2 |
XRF system having multiple excitation energy bands in highly aligned package
An x-ray analysis apparatus for illuminating a sample spot with an x-ray beam. An x-ray tube is provided having a source spot from which a diverging x-ray beam is produced having a characteristic first energy, and bremsstrahlung energy; a first x-ray optic receives the diverging x-ray beam and directs the beam toward the sample spot, while monochromating the beam; and a second x-ray optic receives the diverging x-ray beam and directs the beam toward the sample spot, while monochromating the beam to a second energy. The first x-ray optic may monochromate characteristic energy from the source spot, and the second x-ray optic may monochromate bremsstrahlung energy from the source spot. The x-ray optics may be curved diffracting optics, for receiving the diverging x-ray beam from the x-ray tube and focusing the beam at the sample spot. Detection is also provided to detect and measure various toxins in, e.g., manufactured products including toys and electronics. |
| US09343189B2 |
Circuit for direct energy extraction from a charged-particle beam
Provided herein is a fusion energy extraction circuit (FEEC) device having a grid-tied bidirectional converter and a resonant converter. The resonant converter can include an inverse cyclotron converter with two or more or quadruple plates and a plurality of circuit switches. The bidirectional converter can include a three-phase grid-tied converter. The FEEC device is capable of decelerating plasma particle beams, thereby extracting the energy from the deceleration, converting the extracted energy to electric energy, and sending the electric energy to a power grid. |
| US09343183B2 |
Memory device retention mode based on error information
A controller for a memory device has a power control section to control power to a memory element in an operation mode and in a retention mode. A monitoring section receives and monitors error information and a storage section stores a retention parameter. In the operation mode, the power control section causes an operation voltage to be applied to the memory element, and in the retention mode, the power control section causes a time-varying voltage to be applied to the memory. The power control section also causes the voltage across the memory element to change in the retention mode between a first retention voltage and a second retention voltage based on the retention parameter. |
| US09343182B2 |
Direct memory based ring oscillator (DMRO) for on-chip evaluation of SRAM cell delay and stability
A novel and useful direct memory based ring oscillator (DMRO) circuit and related method for on-chip evaluation of SRAM delay and stability. The DMRO circuit uses an un-modified SRAM cell in each delay stage of the oscillator. A small amount of external circuitry is added to allow the ring to oscillate and detect read instability errors. An external frequency counter is the only equipment that is required, as there is no need to obtain an exact delay measurement and use a precise waveform generator. The DMRO circuit monitors the delay and stability of an SRAM cell within its real on-chip operating neighborhood. The advantage provided by the circuit is derived from the fact that measuring the frequency of a ring oscillator is easier than measuring the phase difference of signals or generating signals with precise phase, and delivering such signals to/from the chip. In addition, the DMRO enables monitoring of read stability failures. |
| US09343181B2 |
Memory module errors
Techniques for handling errors on memory modules are provided. An uncorrected error from a pair of memory modules may be received. Memory modules other than the pair of memory modules producing the error may be de-configured. Diagnostic tests may be run on the faded pair of memory modules. The memory module of the pair of memory modules that caused the uncorrected error may be determined. |
| US09343178B2 |
Gate driver and shift register
A gate driver has a plurality of shift registers. Each of the shift registers has at least three input terminals, two signal input terminals, a pull-up circuit, a driving circuit, a stability pull-down control circuit, and a stability pull-down circuit. The three input terminals of each shift register receive three different clock signals. Accordingly, the driving circuit and the stability pull-down control circuit of each shift register are controlled according to the three clock signals, such that a glitch causing by the coupling effect of the parasitic capacitor of the driving circuit is avoided and the stability of the gate driver is improved. |
| US09343175B2 |
Fuse data reading circuit having multiple reading modes and related devices, systems and methods
A fuse data reading circuit is configured to read fuse data in multi-reading modes. The fuse data may be stored in a fuse array that includes a plurality of fuse cells configured to store fuse data. The fuse data reading circuit may include a sensing unit configured to sense the fuse data stored in the fuse cells of the fuse array, and a controller configured to control an operation of reading the fuse data stored in the fuse cells. The controller sets different sensing conditions for sensing the fuse data according to an operation period during the fuse data reading operation to read the fuse data. Methods include operations and use of the fuse data reading circuit. |
| US09343171B1 |
Reduced erase-verify voltage for first-programmed word line in a memory device
An erase operation for a memory cells in a block provides a consistent and sufficient erase depth regardless of the number of programmed word lines in the block. A lower erase-verify voltage is used for a first-programmed word line of a set of word lines than for remaining word lines in the set. As a result, the resistance of a memory cell of the first-programmed word line dominates during sensing of the NAND string so that the number of erase loops can be controlled in a predictable way regardless of the number of programmed word lines. The lower erase-verify voltage can be optimized so that it does not change the number of erase loops to complete an erase operation, compared to the case where a common erase-verify voltage is used on all word lines. |
| US09343170B2 |
Word-line inter-cell interference detector in flash system
Read signals are obtained from memory cells, and a first read signal and a second read signal are identified, from among the plurality of read signals. The first read signal is associated with a first memory cell in a first word line and the second read signal is associated with a second memory cell in a second word line, and the second word line is adjacent to the first word line. An output for the first memory cell is generated, wherein the output is based on the first and the second read signals. |
| US09343164B2 |
Compensating source side resistance versus word line
A method and non-volatile storage system are provided in which the voltage applied to the source end of a NAND string depends on the location of the non-volatile storage element that is selected for sensing. This may be done without body-biasing the NAND string. Having the magnitude of the voltage applied to the source end of a NAND string depend on the location of the selected memory cell (without any body biasing) helps to mitigate failures that are dependent on which word line is selected during a sensing operation of one embodiment. Additionally, the magnitude of a read pass voltage may depend on either the source line voltage or the location of the selected memory cell. |
| US09343158B2 |
Methods of programming multi-level cell nonvolatile memory devices and devices so operating
To program in a nonvolatile memory device include a plurality of memory cells that are programmed into multiple states through at least two program steps, a primary program is performed from an erase level to a first target level with respect to the memory cells coupled to a selected word line A preprogram is performed from the erase level to a preprogram level in association with the primary program with respect to the memory cells coupled to the selected word line, where the preprogram level is larger than the erase level and smaller than the first target level A secondary program is performed from the preprogram level to a second target level with respect to the preprogrammed memory cells coupled to the selected word line. |
| US09343156B1 |
Balancing programming speeds of memory cells in a 3D stacked memory
Programming techniques for a three-dimensional stacked memory device provide compensation for different intrinsic programming speeds of different groups of memory cells based on the groups' locations relative to the edge of a word line layer. A larger distance from the edge is associated with a faster programming speed. In one approach, the programming speeds are equalized by elevating a bit line voltage for the faster programming memory cells. Offset verify voltages which trigger a slow programming mode by elevating the bit line voltage can also be set based on the group locations. A programming speed can be measured during programming for a row or other group of cells to set the bit line voltage and/or the offset verify voltages. The compensation for the faster programming memory cells can also be based on their speed relative to the slower programming memory cells. |
| US09343149B2 |
Enhancing nucleation in phase-change memory cells
Various embodiments disclosed herein comprise methods and apparatuses for placing phase-change memory (PCM) cells of a memory array into a temperature regime where nucleation probability of the PCM cells is enhanced prior to applying a subsequent SET programming signal. In one embodiment, the method includes applying a nucleation signal to the PCM cells to form nucleation sites within the memory array where the nucleation signal has a non-zero rising-edge. A programming signal is subsequently applied to achieve a desired level of crystallinity within selected ones of the plurality of PCM cells. Additional methods and apparatuses are also described. |
| US09343148B2 |
Method and apparatus for faster determination of a cell state of a resistive memory cell using a parallel resistor
A device for determining an actual cell state of a resistive memory cell having a plurality M of programmable cell states comprising a sensing circuit, a settling circuit, a prebiasing circuit, and a resistor coupled in parallel to the resistive memory cell, wherein the resistor is configured to reduce an effective resistance seen by the prebiasing circuit. The sensing circuit is configured to sense a sensing voltage of the resistive memory cell and output a resultant value in response to the sensing voltage which is indicative for the actual cell state. The settling circuit is configured to settle the sensing voltage to a certain target voltage representing one of the M programmable cell states. The prebiasing circuit is configured to prebiase a bitline capacitance of the resistive memory cell such the sensing voltage is close to the certain target voltage. |
| US09343147B2 |
Resistive random access memory (ReRAM) and conductive bridging random access memory (CBRAM) cross coupled fuse and read method and system
By arranging both a conductive and non-conductive resistive memory cell in a cross coupled arrangement to facilitate reading a data state the memory cells can have very small differences in their resistance values and still read correctly. This allows both of the memory cells' resistances to change over time and still have enough difference between their resistances to read the desired data state that was programmed. A pair of ReRAM or CBRAM resistive memory devices are configured as a one bit memory cell and used to store a single data bit wherein one of the resistive memory devices is in an ERASE condition and the other resistive memory devices of the pair is in a WRITE condition. Reading the resistance states of the resistive memory device pairs is accomplished without having to use a reference voltage or current since a trip-point is between the conductive states thereof. |
| US09343146B2 |
Apparatuses and methods for low power current mode sense amplification
Memory apparatuses and methods for low power current mode sense amplification are disclosed. An example memory apparatus may include a current mode sense amplifier and a current circuit. The current mode sense amplifier may be configured to provide an output current. The current circuit may comprise a bias generator that is configured to generate a bias signal as well as a current control circuit coupled to both the current mode sense amplifier and the bias generator. The current control circuit may be configured to receive both the output current and the bias signal and control the output current based, at least in part, on the bias signal. |
| US09343139B2 |
Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage
In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use. |
| US09343137B2 |
Semiconductor devices and semiconductor systems including the same
The semiconductor memory device includes a power control signal generator and a sense amplifier circuit. The power control signal generator generates a first power control signal that is enabled in response to a temperature latch signal generated in response to latching a temperature signal in a predetermined mode. The sense amplifier circuit generates a first power signal having a first drive voltage in response to the first power control signal. In addition, the sense amplifier circuit senses and amplifies a voltage level of a bit line using the first power signal as a power supply voltage. |
| US09343136B2 |
Semiconductor devices and integrated circuits including the same
A first semiconductor device equalizes levels of a bit line and a complementary bit line of a high-order bit line pair in a first memory block using a first drive voltage signal whose level is controlled when a power-down mode or a self-refresh mode is activated according to a level combination of high-order command/address signals. A second semiconductor device equalizes levels of a bit line and a complementary bit line of a low-order bit line pair in a second memory block using a second drive voltage signal whose level is controlled when the power-down mode or the self-refresh mode is activated according to a level combination of low-order command/address signals. |
| US09343129B2 |
Magnetic memory
A magnetic memory according to an embodiment includes: a first MTJ element including a first storage layer including a first magnetic film having a changeable magnetization direction, a first reference layer including a second magnetic film having a fixed magnetization direction, and a first tunnel barrier layer provided therebetween; and a second MTJ element including a second storage layer including a third magnetic film having a changeable magnetization direction and magnetically connected to the first storage layer, a second reference layer including a fourth magnetic film having a fixed magnetization direction parallel to the magnetization direction of the first reference layer, and a second tunnel barrier layer provided therebetween, the second MTJ element being arranged in parallel with the first MTJ element in a direction perpendicular to a stacking direction of the first MTJ element. |
| US09343128B2 |
Magnetoresistive device
A magnetoresistive device having a magnetic junction including a first fixed magnetic layer structure, a second fixed magnetic layer structure, and a free magnetic layer structure, wherein the first, second and third fixed magnetic layer structures are arranged one over the other, have respective magnetization orientations configured to orient in a direction at least substantially perpendicular to a plane, wherein the respective magnetization orientations of the first fixed magnetic layer structure and the second fixed magnetic layer structure are oriented in opposite directions, and wherein the magnetization orientation of the first fixed magnetic layer structure is configured to oscillate in a first direction in response to a current or a voltage applied across the magnetic junction so as to change the magnetization orientation of the free magnetic layer structure. |
| US09343126B2 |
Frequency selection granularity for integrated circuits
Clock signal generation circuitry. A frequency multiplier is coupled to receive a clock signal and to generate a frequency-multiplied clock signal. A switching circuit is coupled to receive at least two reference clock signals. The switching circuit provides one of the reference clock signals in response to a reference select signal. A phase locked loop (PLL) is coupled to receive the frequency-multiplied clock signal and the selected reference clock signal. The PLL generates an output clock signal. |
| US09343123B2 |
Memory access alignment in a double data rate (‘DDR’) system
Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations. |
| US09343122B2 |
Circuit configuration for selecting and outputting digital input data and operating method for same
A circuit configuration includes a first input for inputting a first set of digital input data, an output for outputting digital output data, and a control input for receiving a control signal. At least two register units are provided and the circuit configuration is designed to write, as a function of the control signal, into a first register unit optionally at least a part of the first set of input data or of the second set of digital input data and to write into a second register unit optionally at least a part of the first set of input data or of the second set of input data. |
| US09343120B2 |
High speed processing unit with non-volatile register
A semiconductor device in which the power consumption of a register is low is provided. Further, a processing unit whose operation speed is high and whose power consumption is low is provided. In the semiconductor device, a register operating at high speed and a nonvolatile FILO (first-in-last-out) register capable of reading and writing data from/to the register are provided. |
| US09343119B2 |
Bus circuits for memory devices
Embodiments of bus circuits and related techniques are disclosed herein. In some embodiments, a bus circuit may include: a source follower arrangement, including a first transistor and a second transistor, coupled between a supply voltage and an access line of a memory cell, wherein the first transistor and the second transistor each have a gate terminal and wherein the access line is a bit line or a word line; a capacitor having a first terminal coupled to the gate terminal of the first transistor and having a second terminal coupled to a reference voltage; and a switch coupled between the first terminal of the capacitor and a voltage regulator. Other embodiments may be disclosed and/or claimed. |
| US09343118B2 |
Voltage regulator and apparatus for controlling bias current
A voltage regulator includes: a comparator configured to compare a feedback voltage with a reference voltage to output an enable signal and operate based on a bias current; a pass transistor turned on according to the enable signal and configured to output an external power voltage as an output voltage; a voltage distribution circuit configured to distribute and output the output voltage to an input terminal of the comparator; and a bias current control unit configured to control an amount of the bias current supplied to the comparator based on the output voltage. |
| US09343117B1 |
Semiconductor integrated circuit and method of driving the same
Provided is a semiconductor integrated circuit including a plurality of memory chips stacked therein. Each of the memory chips may include: a pumping enable signal control unit suitable for generating a pumping enable signal in response to a power-up signal or a trigger signal received from a first adjacent memory chip, delaying the pumping enable signal by a given time, and outputting the delayed pumping enable signal to a second adjacent memory chip; and a pumping unit suitable for generating a pumping voltage by performing a pumping operation in response to the pumping enable signal. |
| US09343113B2 |
Control apparatus and control method
A control apparatus includes a storage unit and a processor. The storage unit is configured to store diagnosis information regarding storage apparatuses to be diagnosed. The processor is configured to receive a write request from an information processing apparatus. The write request requests to write first data into a first logical area corresponding to a first physical area of a first storage apparatus. The processor is configured to determine, on basis of the diagnosis information, whether the first storage apparatus is one of the storage apparatuses to be diagnosed. The processor is configured to cause, when it is determined that the first storage apparatus is one of the storage apparatuses to be diagnosed, the first storage apparatus to execute a write-and-verify process including: writing the first data into the first physical area, and confirming whether the first data is normally read from the first physical area. |
| US09343111B2 |
Reducing total seek time for determining an access sequence of data stored on a tape medium
A first data group in an access sequence is selected. Those data groups located in specified regions of the tape medium are separated from other data groups located in alternative specified regions of the tape medium. The distance from the current position of the tape medium is set to be a logical distance value, determined by a calculation function, that is substituted for the physical distance value for the data groups that are located in the specified regions as compared with other data groups located in the alternative specified regions. A second data group in the access sequence is selected. The logical distance value is then determined by multiplying a coefficient based on a physical positioning of each of the data groups in the tape medium, and a percentage of those of the plurality of data groups that have already been selected as the first data group and the second data group. |
| US09343105B1 |
Wide-band multi-format audio/video recording and production system with frame rate conversion
Wide-band multi-format audio/video recording and production system with frame-rate conversion and methods performed by the audio/video production system. In one aspect, a method is performed by a portable video image recording device including an image sensor and high-capacity digital storage means supporting asynchronous access for recording and reproducing. The image sensor receives an input video image and the output of the image sensor is sampled using a sampling frequency of at least 30 megahertz to generate frames of video image data employing a first frame rate and having a first image dimension in pixels. A video program is recorded by processing the frames of video image data and storing video program content in a compressed progressive format using the high-capacity digital storage means. Concurrent to recording the video program, video image data is manipulated in real-time on a selective basis to output video content in an output video format having a second frame rate different than the first frame rate. |
| US09343103B2 |
Serial port communication for storage device using single bidirectional serial data line
A method is provided to enable communication between a controller and a preamplifier in a storage device. For example, the method includes implementing a serial port which is configured to transmit digital signals between the controller and the preamplifier over a single bidirectional serial data line. The serial port is controlled to selectively transmit digital signals over the bidirectional serial data line in either a first direction from the controller to the preamplifier or a second direction from the preamplifier to the controller. |
| US09343101B2 |
Hard disk drive low profile disk clamp to tied-shaft motor assembly
A hard disk drive is described, including a low-profile disk clamp to tied-shaft spindle/spindle motor assembly, in which a clamping nut is threaded onto a threaded spindle sleeve and a stationary shaft screw, or tied-shaft, penetrates through the HDD cover and into a shaft. The disk clamp may include a central opening for centering about the sleeve by way of the outer diameter of the clamping nut mating with the outer diameter of the clamp opening. |
| US09343096B2 |
Perpendicular magnetic recording medium
According to one embodiment, a perpendicular magnetic recording medium is provided, which includes a non-magnetic granular underlayer formed on a substrate and containing metal grains of a first metal and a grain boundary layer surrounding the metal grains, each metal grain including a projection projecting from the boundary layer and a bottom portion embedded in the grain boundary layer, and a contact angle of the edge of the projection to the surface of the grain boundary layer being 45° to 85°, a non-magnetic intermediate layer formed on a surface of each projection and a magnetic recording layer having a projection pattern formed on the basis of a pattern of the projections in the non-magnetic intermediate layer via the non-magnetic intermediate layer. |
| US09343093B2 |
Servo control
A tape head includes a set of one or more segments, wherein each segment of the set is individually movable with respect to a frame; each segment of the set comprising at least one of a write element configured to write data to a tape and a read element configured to read data from the tape; and each segment of the set comprising a further read element having a width transverse to a motion direction of the tape being at least a width of the write element of the segment or, in the event that no write element is comprised in the segment, of a write element of a different segment. |
| US09343088B2 |
Near field transducer for heat-assisted magnetic recording
An apparatus and method for heat-assisted magnetic recording (HAMR) employing a near-field transducer (NFT) made of plasmonic ceramic materials or intermetallics are disclosed. The NFT is made of a plasmonic material as well as a protective outer layer, which provides for longer usefulness and improved performance of the NFT and recording device. The plasmonic materials used include but are not limited to TiNx, ZrNx, HfNx, TaNx, VNx, TiSi2−x, TiAlxNy, TiZrxNy, ZnO, SnO2, In2O3, RuO2, Lu2O3, WO2, and MgB2. Such materials, in combination with a protective layer, provide higher resistances and greater performance at temperatures required for HAMR, ranging from 300 up to 500 degrees Celsius. |
| US09343087B1 |
Method for fabricating a magnetic writer having half shields
A method manufacturing a magnetic writer provides an intermediate layer including multiple sublayers is provided. The sublayers include first and second nonmagnetic layers and an etch stop layer being between the first and second nonmagnetic layers. A trench is formed in the intermediate layer using at least one etch, such as a reactive ion etch. The trench has a location and profile corresponding to the main pole. A main pole having a bottom and a top is provided in the trench. At least a portion of the second nonmagnetic layer is removed using at least a second etch, such as a wet etch process. The etch stop layer is resistant to the at least the second etch. A half side shield is provided on at least part of the first nonmagnetic layer. The half side shield bottom is between the top and the bottom of the main pole. |
| US09343084B2 |
Systems and methods for correcting slider parallelism error using compensation lapping
Systems and methods for correcting slider parallelism error using compensation lapping are described. One such system includes a lapping support including at least one mounting surface having a preselected mounting angle such that a line normal to the at least one mounting surface is not parallel to a centerline of the lapping support, a rowbar including a plurality of magnetic transducers spaced apart along a length of the rowbar, and a lapping plate configured to lap the rowbar, where the rowbar is mounted to the at least one mounting surface, and where the rowbar is configured to be brought into contact with the lapping plate. |
| US09343083B2 |
Method and apparatus for determining relative head-to-disk speed
A system including a write head, a read head, a mixer, and a filter. The write head is configured to write a pattern on a track of a medium of a hard disk drive, wherein the pattern has a first frequency. The read head is configured to read the pattern written on the track of the medium of the hard disk drive. The mixer is configured to mix a first signal generated by reading the pattern with a second signal to obtain a mixed signal. The second signal has a second frequency, and wherein the second frequency is different than the first frequency. The filter is configured to filter the mixed signal to determine a relative head-to-disk speed. The filter has a parameter selected based on a difference between the first frequency and the second frequency. |
| US09343082B2 |
Systems and methods for detecting head contact
Various embodiments of the present invention provide systems and methods for determining contact with a storage medium. As an example, a data storage system is disclosed that includes: a head assembly and a data processing circuit. The head includes a head disk interface sensor operable to provide a contact signal indicating contact between the head and a storage medium disposed in relation to the head. The data processing circuit is operable to process the contact signal to yield an indication of a contact between the storage medium and the head. |
| US09343070B2 |
Sound transmission-based verification method
A sound transmission-based verification method comprises: a client receiving a data packet set generated by a server according to request information, and converting the data packet set into audio data and play the audio data; a dynamic password apparatus collecting the audio data played by the client, decoding the audio data to obtain data information, and when the information is integral, generating and outputting display information; after the client receives a dynamic password, the client sending the dynamic password to the server; and the server generating, according to the request information, a verifying dynamic password to verify whether the dynamic password is valid, and if the dynamic password is valid, performing an operation according to the request information. |
| US09343065B2 |
System and method for processing a keyword identifier
A mobile device for accessing information over a communication network using a keyword identifier. The mobile device comprises: i) transceiver circuitry configured to transmit information to, and receive information, from the communication network; ii) voice recognition circuitry configured to receive from a microphone of the mobile device a voice input spoken by a user of the mobile device and convert the voice input to a text string; and ii) a controller configured to determine if the text string includes a valid keyword identifier. In response to a determination that the text string includes a valid keyword identifier, the controller generates a query from the valid keyword identifier and transmits the query to a remote server. In response to a determination that the text string does not include a valid keyword identifier, the controller identifies in the text string at least one candidate keyword and at least one candidate domain name. The controller transmits the at least one candidate keyword and at least one candidate domain name to a keyword server associated with a keyword management database. |
| US09343063B2 |
System and method for customized voice response
Disclosed herein are systems, methods, and non-transitory computer-readable storage media for approximating an accent source. A system practicing the method collects data associated with customer specific services, generates country-specific or dialect-specific weights for each service in the customer specific services list, generates a summary weight based on an aggregation of the country-specific or dialect-specific weights, and sets an interactive voice response system language model based on the summary weight and the country-specific or dialect-specific weights. The interactive voice response system can also change the user interface based on the interactive voice response system language model. The interactive voice response system can tune a voice recognition algorithm based on the summary weight and the country-specific weights. The interactive voice response system can adjust phoneme matching in the language model based on a possibility that the speaker is using other languages. |
| US09343060B2 |
Voice processing using conversion function based on respective statistics of a first and a second probability distribution
In voice processing, a first distribution generation unit approximates a distribution of feature information representative of voice of a first speaker per a unit interval thereof as a mixed probability distribution which is a mixture of a plurality of first probability distributions corresponding to a plurality of different phones. A second distribution generation unit also approximates a distribution of feature information representative of voice of a second speaker as a mixed probability distribution which is a mixture of a plurality of second probability distributions. A function generation unit generates, for each phone, a conversion function for converting the feature information of voice of the first speaker to that of the second speaker based on respective statistics of the first and second probability distributions that correspond to the phone. |
| US09343057B1 |
Suppressing sudden cabin noise during hands-free audio microphone use in a vehicle
A vehicle audio quality system for suppressing sudden vehicle cabin noise is provided, as well as methods of using the system. The system includes: an arrangement of heterogeneous microphones and a noise cancellation module (NCM). The microphone arrangement includes: a first microphone and a plurality of secondary microphones. The NCM includes a controller and a non-transitory computer-readable medium for storing application software executable by the controller to improve the quality of desired cabin audio received by the first microphone, the software performing the steps of: receiving a desired audio input from the first microphone; receiving supplemental audio input via the plurality of secondary microphones that includes a sudden cabin noise input; and applying a suppression procedure to the sudden cabin noise input. |
| US09343054B1 |
Techniques for ordering digital music tracks in a sequence
Techniques are described for automatically re-ordering digital music tracks in a sequence for playback on a digital device. The sequence of digital music tracks is algorithmically arranged to provide better transitions between the digital music tracks in the sequence. |
| US09343053B2 |
Adding audio sound effects to movies
A method of adding sound effects to movies, comprising: opening a file comprising audio and video tracks on a computing device comprising a display and touch panel input mode; running the video track on the display; selecting an audio sound suitable to a displayed frame from an audio sounds library; and adding audio effects to said selected audio sound using hand gestures on displayed art effects. |
| US09343050B2 |
Channeled shaker
A percussive shaker instrument with improved control in producing rhythmic sound and capable of producing different percussive sounds in a single shaker is disclosed. The shaker comprises one or more channels filled with a striker material. The channel isolates the striker material from the striker material in other channels and from any other part of the shaker. The striker material is freely movable within the channel such that it may collide with a striking surface when the shaker is moved. |
| US09343049B1 |
Cymbal clamp assembly
A single unit that is used to support a cymbal on a stanchion and also secure the unit to the stanchion. The cymbal is supported between a pair of soft discs with a nut provided that can be tightened or loosened for the drummer to select how tight the cymbal is secured or how not so tight thereby varying the sound emitted from the cymbal when struck by a drumstick. The unit also has a slotted collet through which the mounting rod of the stanchion is conducted. The exterior surface of the collet is tapered which fits in a tapered cavity in a body. A nut is mounted by threads on the body and when turned on the body will cause the collet to press further into the tapered cavity which will cause the collet to tightly engage with the mounting rod. |
| US09343047B2 |
High performance guitar bridge pins
Guitar bridge pins are formed of hard materials shaped to mechanically cooperate with standard guitar bridge configurations. Either molded or machined into a prescribed shape, guitar bridge pins fit into tapered shaped holes of most common guitar bridges. Guitar bridge pins of these systems include a main body portion into which a recess seat is formed. Further a string via is arranged from the recess seat to an exit aperture, the string via provides a path through which a guitar string may pass. These guitar pins provide a high-performance system for mounting and fixing guitar strings at the bridge of a standard guitar. Specifically these bridge pin devices include at least four major integrated elements including a main body, a recess seat, a string via and a stud element. Additionally, these bridge pin systems may also include cooperating spacing and locking washers which may be used in conjunction with threaded fasteners. When fastened to a guitar bridge as prescribed, these bridge pins securely couple guitar strings there to while additionally holding together a bridge assembly including the bridge plate, sound board and bridge. |
| US09343046B2 |
Stringed musical instrument with surface mounted neck insert
A stringed musical instrument with a base portion and neck portion with an inlaid fretboard snugly secured within a recess between an upper wall and a lower wall on the neck portion is disclosed. The geometry of the upper and lower walls maybe optimized and includes walls that are substantially perpendicular to the face of the instrument, walls that are angled with respect to each other to define a wedge-shaped slot for slidably receiving and securing the mating fretboard therein, and walls that are angled to define inwardly extending protrusions that allow the fretboard to be “snapped” in place on the neck portion of the instrument. The fretboard may be rigidly secured to the neck portion with glue or the like or it may be detachably secured within the slot thereby allowing fretboards to be changed as desired for aesthetic or performance purposes. |
| US09343039B2 |
Efficient displayport wireless AUX communication
In accordance with some embodiments, a DisplayPort control plane may be supported over a Wireless Gigabit Alliance or other wireless air interface. Some embodiments may efficiently optimize the amount of wireless bandwidth needed to accomplish tasks. |
| US09343038B2 |
Image projection apparatus and image display system
An image projection apparatus configured to project an image on the projection surface includes a light modulation unit configured to modulate light from a light source unit, an image processing unit configured to generate an image signal to be input to the light modulation unit, disposed in the image projection apparatus and, a light intensity measuring unit configured to measure an intensity of part of the modulated by the light modulation unit, a light guide optical system configured to guide the part of the light to the light intensity measuring unit and another part of the light to the projection surface, and a correction unit configured to correct brightness of the image projected on the projection surface based on a video signal supplied to the image projection apparatus and a measurement result of the light intensity measuring unit. |
| US09343029B2 |
Gate driving circuit and related LCD device capable of separating time for each channel to turn on thin film transistor
A gate driving circuit for an LCD device includes a shift register module for generating a plurality of scan signals corresponding to a plurality of channels according to a start signal and a clock signal, a plurality of logic circuits each corresponding to a channel of the plurality of channels, for outputting a driving signal to the channel according to a scan signal of the plurality of scan signals and a shutdown indication signal, and a plurality of shaping and delay units each coupled between two neighboring channels for outputting the shutdown indication signal to another channel after shaping and delaying the shutdown indication signal of a previous stage. |
| US09343027B2 |
Gate drive circuit, array substrate and display device
A gate drive circuit including cascaded gate drive units, an array substrate and a display device are provided. In each gate drive unit, a first phase inverter module is connected with first and second driving modules and an intermediate signal generation module, and is used for inverting a clock signal received by a clock signal input terminal; the intermediate signal generation module is connected with first and second signal input terminals, a clock signal input terminal, first and second signal output terminals and an output terminal of the first phase inverter module, and generates an intermediate signal under the control of control signals received by the first and the second signal input terminals, the clock signal and the inverted clock signal; the first and the second driving modules scan the respective gate lines connected thereto under the control of the inverted clock signal and the intermediate signal. |
| US09343025B2 |
Display device
A display device includes a display module and a protective member that accommodates the display module. The protective member includes a first curved-line part extending in a horizontal direction and curved to have a concave surface on the top, a second curved-line part spaced apart from the first curved-line part to face the first curved-line part, formed below the first curved-line part, extending in the horizontal direction, and have a concave surface on the bottom, and connection parts that connect the first curved-line part and the second curved-line part to define an opening portion through which the portion of a display area is exposed. The display area comprises a display part exposed through the opening portion to display the effective image, a first peripheral part overlapped with the first curved-line part, and a second peripheral part overlapped with the second curved-line part. |
| US09343023B2 |
Stereoscopic display having a gray level zone and a method for driving the same
A stereoscopic display and a driving method are disclosed herein. The stereoscopic display includes a sensor, a barrier cell, and a control unit. The sensor is configured to detect a user to generate a sensing signal. The barrier cell is configured to generate a 3D image with a 2D image. The barrier cell includes barrier pitches disposed in parallel. Each of the barrier pitches includes switchable barrier units. The control unit is configured to generate control signals to adjust the switchable barrier units according to the sensing signal, so as to make at least one of the switchable barrier units of each of barrier pitches form a shading zone, to make the switchable barrier units disposed at the two adjacent sides of the shading zone form a gray level zone, and to make the rest of the switchable barrier units in the same barrier pitch form a photic zone. |
| US09343020B2 |
Methods and apparatus for visual display
In exemplary implementations of this invention, light from a backlight is transmitted through two stacked LCDs and then through a diffuser. The front side of the diffuser displays a time-varying sequence of 2D images. Processors execute an optimization algorithm to compute optimal pixel states in the first and second LCDs, respectively, such that for each respective image in the sequence, the optimal pixel states minimize, subject to one or more constraints, a difference between a target image and the respective image. The processors output signals to control actual pixel states in the LCDs, based on the computed optimal pixel states. The 2D images displayed by the diffuser have a higher spatial resolution than the native spatial resolution of the LCDs. Alternatively, the diffuser may be switched off, and the device may display either (a) 2D images with a higher dynamic range than the LCDs, or (b) an automultiscopic display. |
| US09343014B2 |
Pixel driving circuit
A pixel driving circuit includes first to seventh switches, a capacitor and a light emitting unit. The first and sixth switches are connected and receive data voltage and second reference voltage according to second and third control signals, respectively. One capacitor end connects to the serial-connected first and sixth switches and the other capacitor end connects to a control end of the second switch. The serial-connected third and fourth switches are connected between the control and first end of the second switch. The third and fourth switches are ON by the second control signal. The fifth switch is ON by a first control signal. An end of the fifth switch connects to the serial-connected third and fourth switches and another end receives a first reference voltage. The seventh switch is connected between the second switch and the light emitting unit. The seventh switch is ON by the third control signal. |
| US09343013B2 |
Pixel circuit driving method, light emitting device, and electronic apparatus
Provided is a method of driving a pixel circuit including a light emitting element and a driving transistor which are connected in series to each other, and a storage capacitor disposed between a path between the light emitting element and the driving transistor and a gate of the driving transistor, the method including the steps of: supplying a driving signal to a gate of the driving transistor; and changing the potential of the driving signal over time so that the time rate of change of the potential of the driving signal at the point in time when the supply of the driving signal stops becomes the time rate of change corresponding to a specified gradation of the pixel circuit. |
| US09343012B2 |
Driving circuit of AMOLED and method for driving the AMOLED
A driving circuit of an active matrix/organic light emitting diode (AMOLED) includes a first semiconductor controllable switch, a second semiconductor controllable switch, an energy-storage capacitor, an organic light emitting diode, and a sequential control unit that divides a driving time of one frame of the organic light emitting diode into driving times of N subframes. An output end of the second semiconductor controllable switch is coupled to an anode of the organic light emitting diode, a source electrode of the first semiconductor controllable switch receives a data driving signal of the AMOLED, a gate electrode of the first semiconductor controllable switch receives a scan driving signal of the AMOLED, a drain electrode of the AMOLED is connected with a gate electrode of the second semiconductor controllable switch, and the energy-storage capacitor is connected in series between a source electrode and the gate electrode of the second semiconductor controllable switch. The data driving signal is divided into an active signal that drives display of the organic light emitting diode and a blanking signal that turns off display of the organic light emitting diode in the driving time of each of the subframes. |
| US09343011B2 |
Pixel for controlling current flowing from power supply and organic light emitting display using the same
A pixel capable of displaying an image with uniform brightness is disclosed. In one aspect, the pixel includes an organic light emitting diode (OLED), a first transistor for controlling an amount of current that flows from a first power supply to a second power supply via the OLED in response to a voltage applied to a first node. The pixel also includes a second transistor that is coupled between a bias power supply and the first node and whose gate electrode is coupled to an emission control line. The pixel further includes a third transistor that is coupled between an anode electrode of the OLED and a feedback line and whose gate electrode is coupled to a control line. |
| US09343010B2 |
Gamma reference voltage generating circuit and display device including the same
A gamma reference voltage generating circuit and a display device including the same are disclosed. The gamma reference voltage generating circuit includes a first voltage follower which receives a first reference voltage generated by a first digital-to-analog converter and outputs a first gamma reference voltage, an nth voltage follower which receives a second reference voltage generated by a second digital-to-analog converter and outputs an nth gamma reference voltage, where n is a natural number equal to or greater than 3, a resistor string for dividing the first gamma reference voltage and the nth gamma reference voltage, and second to (n−1)th voltage followers which receives the first gamma reference voltage and the nth gamma reference voltage divided by the resistor string and outputs second to (n−1)th gamma reference voltages. |
| US09343009B2 |
Organic light emitting diode display device
An organic light emitting diode display device includes a display panel and a power supply. The power supply applies a first power supply voltage and a second power supply voltage to a first power supply voltage line. The first power supply voltage line includes a first extension, a second extension, and third extension. The first extension is disposed along a first direction from the first side portion to the second side portion. The first extension has a width that gradually decreases along the first direction. The second extension is disposed along a second direction that is perpendicular to the first direction. The third extension is disposed along a third direction that is opposite to the first direction. The third extension has a width that gradually decreases along the third direction. |
| US09343008B2 |
Organic light emitting diode display
An organic light emitting diode (OLED) display includes: a substrate; and a red subpixel, a green subpixel, a blue subpixel, and a white subpixel arranged in a matrix of rows and columns on the substrate, wherein three different-colored subpixels selected from the red subpixel, the green subpixel, the blue subpixel, and the white subpixel form one pixel in which the three different-colored subpixels are simultaneously driven. Four red subpixels in the matrix enclose two green subpixels, two white subpixels, and one blue subpixel. Accordingly, the organic light emitting diode (OLED) display has a RGBW structure, and improves the luminance by the two white subpixels. |
| US09342999B2 |
Machine readable information interface for a container
The present application is directed to systems and methods for an information delivery system for a container. At least one machine readable indicia may be printed on an outer surface of the container. A top label may cover at least a portion of the outer surface of the container. The top label may be rotatable about the outer surface of the container. The top label may have a transparent window allowing at least one of the machine readable indicia to be visible through the transparent window. |
| US09342991B2 |
Systems and methods for generating a high-level visual vocabulary
Systems and methods for learning a high-level visual vocabulary generate inter-visual-word relationships between a plurality of visual words based on visual word-label relationships, map the visual words to a vector space based on the inter-visual word relationships, and generate high-level visual words in the vector space. |
| US09342980B2 |
Communication apparatus, which communicates with an external terminal, method of controlling a communication apparatus which communicates with an external terminal, program, and server
A generation unit generates a command based on operation history information read from a storage unit and operation status information obtained by an obtainment unit when power is supplied from a first power source unit to a communication apparatus, and generates the command based on the operation history information read from the storage unit when the power is not supplied from the first power source unit to the communication apparatus, when power is supplied from a second power source unit to each of the storage unit, the generation unit, and a proximity wireless communication unit. |
| US09342976B2 |
Incident response system
A method for responding to incidents includes receiving incident information corresponding to an incident at an incident location. An incident scenario is generated based at least in part on the incident information, where the incident scenario identifies a number of responders for responding to the incident. A responder is identified based at least in part on an incident effectiveness of the responder with respect to the incident, where the incident effectiveness is based at least in part on past performance of the responder. A request for assistance with the incident is sent to a mobile device of the responder. |
| US09342974B2 |
Autonomous aggregated search platform and methods using the same
Systems and methods for searching for lost moving objects such as children are disclosed. In some embodiments, the systems and methods initiate an autonomous, expanding electronic search by emitting a search activation signal from a search initiation device. The search activation signal may include the target tag identifier of a target tag conveyed by the moving object. Search devices detecting the target tag may generate a hit signal, which may be used to determine the location of the target tag. In some instances, focused human searching for the moving object may be initiated based on this determined location, and/or on location information included in one or more hit signals. |
| US09342971B2 |
Duress alarm system for clothing
An article of clothing includes a sensor attached to a fabric body for detecting forces applied to the fabric body. A processor is attached to the fabric body and is communicatively coupled to the sensor. The processor receives signals from the sensor, analyzes the signals, and discerns therefrom whether a physical attack is occurring on a wearer of the fabric body. The processor emits a distress signal if it is discerned that an attack is occurring. |
| US09342969B2 |
Pneumatic detector assembly with bellows
In one aspect, a pneumatic detector assembly is provided. The assembly includes a housing, a sensor tube, a contact pin, and at least one switch having a bellows operatively associated with the sensor tube and the contact pin. The bellows is configured to move into and out of contact with the contact pin based on a pressure in the sensor tube. |
| US09342967B2 |
Motion activated off grid LED light
The claimed subject matter provides systems and/or methods that facilitate remotely controlling a wireless lighting module. The wireless lighting module can include a power source such as a battery, a solar cell, and the like as well as an array of light emitting diodes (LEDs). The LEDs can be controlled based upon a received input (e.g., communicated by way of a radio frequency signal, an infrared signal, . . . ). For example, the input can be obtained from a remote control, a sensor, a differing wireless lighting module, an radio frequency identification (RFID) tag, and so forth. The input can be utilized to switch one or more LEDs on or off, change the intensity or color of illumination, modulate illumination, alter the direction of illumination, etc. |
| US09342958B2 |
Gaming device and method for providing player selection of modifiers to game components
In one embodiment, the gaming device and method disclosed herein provides a player one or more modifiers to apply to different components or characteristics of a game. In one such embodiment, the gaming device enables a player to selectively apply or associate a plurality of modifiers to a single game component or apply the plurality of modifiers across the plurality of game components. For each game component with at least one applied modifier, the gaming device disclosed herein modifies said game component based on each applied modifier. The gaming device generates any awards based on any modified game components and any unmodified game components and provides any generated awards to the player. |
| US09342956B2 |
Gaming system, gaming device and method for shifting progressive award contribution rates
A gaming system and method which maintains a plurality of progressive awards. Each progressive award is associated with a progressive award contribution rate wherein at least two of the maintained progressive awards are associated with different progressive award contribution rates. Upon an occurrence of a progressive award contribution rate reconfiguration event, the gaming system shifts, modifies or changes which progressive awards are associated with which progressive award contribution rates. |
| US09342955B2 |
Methods and systems for tracking an event of an externally controlled interface
A method for tracking an event of an externally controlled interface (ECI) is described. The method includes generating the externally controlled interface independent of an outcome of a wager-based game regulated by a regulatory authority, and logging the event of the externally controlled interface. |
| US09342954B1 |
Games and gaming machines having wheel features
Gaming machines and games are configured with one or more wheel events or features. The wheel events or features may comprise main games or bonus games, or may comprise entertaining representations of outcomes of other games or events. The wheel events comprise the selection of one or more segments of a wheel having associated awards. Wheel events may have various entertaining configurations, such as morphing wheels, symbols that reveal awards and the like. |
| US09342953B2 |
Wagering game with positive banking of positive expectation situations
A method, apparatus, and computer readable storage to implement a disbursement of potential awards in a wagering game that have not been fully awarded yet. In a wagering game that comprises multiple states, a value of a favorable state relative to a prior state can be banked for later redemption by a player. |
| US09342952B2 |
Systems and methods for creating and maintaining an inventory list and verifying components of gaming equipment
Systems and methods for authenticating an inventory list of the components installed on electronic gaming machines, including receiving, from an input device, an input signal indicating the identity and location of a gaming machine, an electronic signature of each installed component, receiving the electronic signature and software components which should be installed on the gaming machine, and comparing electronic signature of the components. If the electronic signature of the components does not match the received electronic signature of what should be installed on the gaming machine, and sending a confirmation to the inventory database component indicating the correct software is not installed. |
| US09342947B2 |
News ticker as game display mechanism
Systems and methods provide a game of chance based using information stream items such as items in a news ticker. Information stream items are received for display in a series of information stream items such as a news ticker. Game symbols are assigned to the information stream items based on the output of a random number generator. In response to determining that the game symbols assigned to the series of information stream items form a winning combination of game symbols, an account may be credited with cash or points. |
| US09342945B2 |
Gaming device with a virtualization manager
Gaming devices with virtualization managers are described herein. In one embodiment, a gaming device includes a plurality of operating systems, each of the operating systems to facilitate execution of one or more gaming applications. The gaming device also includes gaming device resources for use by ones of the plurality of operating systems and a virtualization manager to share the gaming device resources between the plurality of operating systems during virtually simultaneous execution of the plurality of operating systems. |
| US09342939B1 |
Method and system utilizing magnetic card key with a QRC
A method and system for self-service access to a card key locked room of a facility is disclosed herein. A magnetic card key with a QRC is utilized with a mobile application resident on a mobile communication device to activate the card and allow for self-service access to check into a hotel. |
| US09342936B2 |
Smart lock systems and methods
A door lock system can comprise a door lock movable between a locked state and an unlocked state. The door lock system can detect a first indication suggestive of a presence of a visitor. The door lock system can also detect a second indication suggestive of an identity of the visitor. As well, the door lock can validate that the first indication and the second indication are associated with a first identity. |
| US09342935B2 |
Smartphone based system for vehicle monitoring security
An apparatus and method for monitoring a vehicle. Some embodiments include: capturing and securely storing OBD and location data from the vehicle, maintaining the data on storage in control of a user for a user-specified amount of time, securely transmitting the stored data to an internet-based server, storing the data on the internet server and processing the data for retrieval, retrieving the data from the internet server for display via a web server or specialized application, and performing remote diagnostics in the vehicle based on the VIN. Some embodiments include extracting a make and model of the vehicle from the VIN; wirelessly transmitting the make and model to a server; wirelessly receiving, from the server, a particular set of on-board-diagnostic (OBD) queries to perform to determine whether any abnormal measurements exist for this make and model; and executing a plurality of queries from the particular set of OBD queries. |
| US09342934B2 |
Vehicle specific reset device and method
There is provided a device, system, and method for generating vehicle-specific diagnostic reset procedures using a data signal representative of vehicle identifying information. Diagnostic reset procedures corresponding to a vehicle are generated in response to converting vehicle identifying information into a data signal representative of the vehicle's VIN or license plate number, and matching the data signal with corresponding reset procedures stored in a reset procedure database. The vehicle-specific reset procedure(s) may be displayed on a mobile communication device, such as a smart phone, for instructing the user to manually perform the corresponding reset procedure(s). Alternatively, the corresponding reset procedure(s) may be communicated directly to the vehicle's electronic control unit for electronically implementing the corresponding reset procedure(s). |
| US09342933B2 |
Vehicle maintenance systems and methods
A system that enables a fleet of vehicles to be maintained is provided. The disclosed system allows a fleet operator to review the history of the vehicles in the fleet along with vehicle sensor data to identify earmarks in the vehicle sensor data that are predictive of faults that the vehicles have experienced. The operator develops statistical algorithms that can detect an earmark in vehicle sensor data. The system then collects vehicle sensor data and applies the statistical algorithms the vehicle data to determine if a potential fault is going to occur in a vehicle. In response to determining that a potential fault is going to occur, the disclosed system automatically alerts the vehicle driver, automatically schedules a maintenance visit, automatically checks the fleet inventory for components required for a maintenance visit and orders unavailable components, and automatically dispatches the components to the mechanic. |
| US09342927B2 |
Augmented reality system for position identification
A system, method, and computer program product for automatically combining computer-generated imagery with real-world imagery in a portable electronic device by retrieving, manipulating, and sharing relevant stored videos, preferably in real time. A video is captured with a hand-held device and stored. Metadata including the camera's physical location and orientation is appended to a data stream, along with user input. The server analyzes the data stream and further annotates the metadata, producing a searchable library of videos and metadata. Later, when a camera user generates a new data stream, the linked server analyzes it, identifies relevant material from the library, retrieves the material and tagged information, adjusts it for proper orientation, then renders and superimposes it onto the current camera view so the user views an augmented reality. |
| US09342926B2 |
Information processing apparatus, method of controlling the same, and storage medium
An information processing apparatus acquires a low resolution indirect illumination buffer having a resolution less than an indirect illumination buffer information used for specifying a specular reflection direction in a position of an object and a reflection characteristic of the object in a 3D scene corresponding to each pixel of the indirect illumination buffer to be generated. Then it generates an indirect illumination buffer by increasing the resolution of the low resolution indirect illumination buffer. Here the apparatus generates the pixels of the indirect illumination buffer generated by the increase in resolution based on at least the level of similarity of the specular reflection lobes of objects corresponding to the pixels and objects corresponding to the pixels of the low resolution indirect illumination buffer used for the generation of the pixels. |
| US09342922B2 |
Medical imaging apparatus and method of constructing medical images
Apparatus and method of medical diagnostic imaging. The apparatus includes: an image unit for constructing volume image data by capturing images from a multiplicity of tomographic images of a sampling specimen and for constructing internal three dimensional images of the diagnosing object of the sampling specimen as seen from a viewing point; a display for displaying the three-dimensional images; an input unit for entering parameters for setting up a precutting plane at an inter-voxel image data boundary between voxel image data of the volume image data closer to the viewing point than the diagnosing object and voxel image data associated with the diagnosing object; and a control unit for controlling the structure of the three-dimensional images constructed by the image unit based on the precutting plane set up via the input unit, wherein the control unit extracts a boundary based on one of the parameters inputted to the input unit. |
| US09342921B2 |
Control apparatus, electronic device, control method, and program
There is provided a control apparatus including a control unit configured to control information to be displayed on a display screen in a manner that a different type of information is visually recognized according to a positional relationship between the display screen and a predetermined portion of a user viewing the display screen. The information to be displayed on the display screen under control of the control unit is information extracted from information capable of being displayed on the display screen as information having an attribute satisfying a predetermined condition set for each positional relationship. |
| US09342911B1 |
Automatically generating panorama tours
In one aspect, a request to generate an automated tour based on a set of panoramic images is received. Each particular panoramic image is associated with geographic location information and linking information linking the particular panoramic image with one or more other panoramic images in the set. A starting panoramic image and a second panoramic image are determined based at least in part on the starting panoramic image and the linking information associated with the starting and second panoramic images. A first transition between the starting panoramic image and the second panoramic image is also determined based at least in part on the linking information for these panoramic images. Additional panoramic images as well as a second transition for between the additional panoramic images are also determined. The determined panoramic images and transitions are added to the tour according to an order of the tour. |
| US09342903B2 |
Method for generating image for PET attenuation correction from MR image and computer program
When an image for PET attenuation correction is generated from an MR image, the MR image captured by MRI is segmented into regions according to pixel values. In a region in which a radiation attenuation coefficient is considered to be uniform, a radiation attenuation correction value is determined by referring to an existing radiation attenuation correction value table. In a region including multiple tissues having different radiation attenuation coefficients, a radiation attenuation correction value is determined by referring to a standard image. In such a manner, an image for PET attenuation correction in which tissues having similar pixel values in the MR image but different attenuation coefficients for radiation can be distinguished and that can accommodate individual differences and an affected area such as a space occupying lesion (for example, a cancer, abscess, or the like) and an organic defect is generated. |
| US09342899B2 |
Method for measuring microphysical characteristics of natural precipitation using particle image velocimetry
A method and video sensor for precipitation microphysical features measurement based on particle image velocimetry. The CCD camera is placed facing towards the light source, which forms a three-dimensional sampling space. As the precipitation particles fall through the sampling space, double-exposure images of precipitation particles illuminated by pulse light source are recorded by CCD camera. Combined with the telecentric imaging system, the time between the two exposures are adaptive and can be adjusted according to the velocity of precipitation particles. The size and shape can be obtained by the images of particles; the fall velocity can be calculated by particle displacement in the double-exposure image and interval time; the drop size distribution and velocity distribution, precipitation intensity, and accumulated precipitation amount can be calculated by time integration. This invention provides a method for measuring the shape, size, velocity, and other microphysical characteristics of various precipitation particles. |
| US09342893B1 |
Method and apparatus of performing image segmentation
In general, embodiments of the invention comprise systems and methods for performing image segmentation from image data. According to certain aspects, methods of the invention include constructing a fragment tree representation of image data. An image is segmented into regions of pixels having similar image characteristics, called fragments, each fragment (region) is then compared to its neighbors to determine a graph or hierarchical relationship among all regions. Groups of fragments can be selected by an operator or automatically to define a signature of an object. This signature can then be used to search or traverse a fragment tree any image in order to identify similar objects either automatically or manually. |
| US09342888B2 |
System and method for mapping, localization and pose correction of a vehicle based on images
A system and method for mapping, localization and pose correction including, determining a current position of a vehicle along a travel route and a set of currently observable landmarks along the travel route relative to the current position, the set of currently observable landmarks extracted from one or more stereo images obtained from an imaging device, and querying a survey landmark database to identify a subset of surveyed landmarks relative to the current position of the vehicle. The method including determining one or more two-dimensional transform estimates between the set of currently observable landmarks and the subset of surveyed landmarks and identifying a best transform estimate from the one or more two-dimensional transform estimates that minimizes distances between the set of currently observable landmarks and the subset of surveyed landmarks. The method including correcting a pose of the vehicle based on the best transform estimate. |
| US09342886B2 |
Devices, methods, and apparatuses for homography evaluation involving a mobile device
Components, methods, and apparatuses are provided that may be used to access information pertaining to a two-dimensional image of a three-dimensional object, to detect homography between said image of said three-dimensional object captured in said two-dimensional image indicative of said three-dimensional object and a reference object image and to determine whether said homography indicates pose suitable for image augmentation based, at least in part, on characteristics of an elliptically-shaped area that encompasses at least some of a plurality of inliers distributed in said two-dimensional image. |
| US09342885B2 |
Method of generating a multi-modality anatomical atlas
Method of generating a multi-modality anatomical atlas. The method includes receiving first and second medical images of a region-of-interest (ROI) of a same individual. The first and second medical images are acquired by different first and second imaging modalities. The method includes generating first and second feature images based on the first and second medical images. The first and second feature images include a same designated anatomical feature of the ROI. The method includes determining a transformation function by registering the first and second feature images and applying the transformation function to the first and second medical images to register the medical images. The method includes generating a multi-modality anatomical atlas. The multi-modality atlas has the first and second medical images. The first and second medical images are first and second reference images. The multi-modality anatomical atlas includes an organ model that corresponds to an organ in the ROI. |
| US09342879B2 |
Method and apparatus for reviewing defect
A method for reviewing defect, comprising the steps of: as an image acquisition step, imaging a surface of a sample using arbitrary image acquisition condition selected from a plurality of image acquisition conditions and obtaining a defect image; as a defect position calculation step, proceeding the defect image obtained by the image acquisition step and calculating a defect position on the surface of the sample; as a defect detection accuracy calculation step, obtaining a defect detection accuracy of the defect position calculated by the defect position calculation step; and as a conclusion determination step, determinating whether the defect detection accuracy obtained by the defect detection accuracy calculation step meets a predetermined requirement or not; wherein until it is determined that the defect detection accuracy obtained by the defect detection accuracy calculation step meets a predetermined in the conclusion determination step, the image acquisition condition is selected from the plurality of image acquisition conditions once again and the image acquisition step, the defect position calculation step, the defect detection accuracy calculation step and the conclusion determination step are repeated. |
| US09342874B2 |
Noise determination apparatus and method, and noise filter
A technique for determining noise is provided that suppresses misrecognition of significant components in an image as noise in any image captured under any condition. A noise determination apparatus for determining noise in image data that is input in units of frames decomposes the image data into frequency components, samples a predetermined number of data pieces for low-frequency components that have relatively low frequencies and a predetermined number of data pieces for high-frequency components that have relatively high frequencies from the frequency components, and analyzes whether or not the image data includes an edge image, on the basis of a ratio of high-frequency data to low-frequency data. |
| US09342869B2 |
Discriminative indexing for patch-based image enhancement
Methods for enhancing images with increased efficiency include using a discriminative index tree to expedite image optimization processes. The discriminative index tree indexes patch-based image priors for modifying an image by using classifiers determined by exploiting a structure of the patch-based image priors. The discriminative index tree quickly and efficiently parses a space of patch-based image patches to determine approximate dominant patch-based image priors for the space of image patches. To further improve the efficiency of the discriminative index tree, one or more embodiments can limit a number of potential patch-based image priors from which a dominant patch-based image prior is selected. |
| US09342868B2 |
Image display device, image display method, and image display program
An image display device is capable of realizing an effective corrected shape of the image. The image display device includes an image input section to which an image is input, an aspect ratio determination section adapted to determine an aspect ratio of the image input to the image input section, a correction section adapted to perform a correction on the image input to the image input section so that the image has an aspect ratio corresponding to an aspect ratio determined by the aspect ratio determination section, and a projection section adapted to project the image on which the correction is performed by the correction section. |
| US09342860B2 |
Memory management system and method
There is provided a method and apparatus for managing memory in a system for generating 3-dimensional computer images. The image is subdivided into a plurality of rectangular areas. A memory is provided and a page of the memory is allocated for storing object data for objects in the image. Object data for objects in the image are then written to the allocated page of memory. Finally, a bit mask for the allocated page of memory is compiled, the bit mask indicating the rectangular areas having object data stored in the allocated page of memory. A rectangular area of the image can then be rendered by deriving data for display from the object data stored in the memory, for objects in that rectangular area. Once the rectangular area has been rendered, the bit mask for each page of memory which stored, before the step of rendering, object data for that rectangular area, is updated so that the bit mask no longer indicates that rectangular area. |
| US09342855B1 |
Dating website using face matching technology
A system having a dating website using facial images technology to match a first user to a second user having similar facial features and electronically introducing the users for establishing a dating relationship. The website further selects matches to the first user among the matches bearing a facial resemblance to the user based on complementary styles, values and compatible personalities. The website is accessed directly, through social networking sites or through mobile applications on smart phones and other handheld computing devices. The mobile application notifies the website where the user is and informs the user if any matching users are nearby or in the same location. If no matches are available in the location, the user photographs new acquaintances using the handheld computing device and uploads the photos to determine if the new acquaintances bear a facial resemblance to the user. |
| US09342852B1 |
Visual indicators for account access in a social network
A method includes receiving login with a first identity. The first identity is associated with a first set of privileges. The reception of login with the first identity enables a first presentation of content associated with a first user account. The content is displayed on a page that has a visual indicator identifying the first user account. The method further includes receiving an interactive input in a location associated with the visual indicator. The received interaction input causes an identity selection menu to be generated on the page. When selection of a second identity other than the first identity is received, the method includes enabling a second set of privileges associated with the second identity. The reception of selection with the second identity enables a second presentation of content associated with a second user account. |
| US09342849B2 |
Near-duplicate filtering in search engine result page of an online shopping system
Reducing near-duplicate entries in online shopping system search results. For each pair of entries in a set of entries, each entry characterizing a product in a data store of an online shopping system and each entry characterized by a set of attributes, determining a distance between the entries in the pair based on the attributes. Determining entry clusters from a graph formed with each determined distance as an edge between nodes representing the entries used to determine the distance, each entry cluster identified by cluster identifier. Returning an ordered list of results responsive to the query from the data store of an online shopping system, filtered as a function of at least one of the distance and the cluster identifier. |
| US09342847B2 |
Methods, systems, and products for ordering items
Electronic commerce is enhanced for customer convenience. When an online order is received, a profile may be checked. A customer may her profile with items that are automatically added to the online order. Food and beverages, for example, may be items that are frequently consumed and thus automatically added to any online order. Electronic commerce may thus be enhanced to restock items that are frequently purchased. |
| US09342844B2 |
Rebroadcasting of advertisements in a social network
The subject matter of this specification can be embodied in, among other things, a method that receives at a server a first request to rebroadcast a first sponsored content item that was displayed on the social network to the first user to a second user. A second request to display at least one sponsored content item to the second user when the second user accesses an electronic document associated with the social network is received at the server. The first sponsored content item is retrieved for rebroadcast from one or more sponsored content items indicated for rebroadcast to the second user. The first sponsored content item is output to the second user of the social network in response to the second request to display and without requiring the second user to select the first sponsored content item for display. |
| US09342841B2 |
System and method for dynamic price setting and facilitation of commercial transactions
The present invention provides methods and systems for defining commercial transaction components; defining rules for mapping customer transactions into individual components; market segmentation in light of these individual definitions and bundling individual components of an offer into optimized packages for presentation and sale. A data processing system in accordance with one embodiment of the present invention, examines the commercial behavior of enrolled customers, breaks each of the constituent transactions into purchases of atom-level components; catalogues those components; extracts demographic information from said transactions and other sources; facilitates demographic studies of groups of such customers; optimizes offerings to such groups; and facilitates the consummation of those offers of sale. The processing system may also facilitate customers fiscal management through the communication of data necessary to practice the instant invention. |
| US09342833B2 |
Method of aggregating business and social networks
A method and system for facilitating relationships across multiple networks is described. The meta-network includes relationship information describing users, the networks to which such users belong, and the relationships that they have established within such networks. When a relationship is established in a network, it can be used to propagate relationships across any number of networks with the same or different users. The meta-network enhances the users' ability to search for information and manage their relationships across multiple networks. A user can search for other users according to one or more user-specified attributes. One or more users satisfying the user-specified attributes are identified, and a similarity measure may be determined for each of the identified users. A mapping interface is displayed to the user to enable the user to visually compare the identified users having a similarity measure within the displayed range. The mapping interface allows the user to invite one or more of the displayed users to establish a relationship with the user. |
| US09342831B1 |
Facilitating same day payment transactions
The present disclosure relates to systems, methods, and devices for sending and receiving payments using an integrated payment and messaging system. In particular, the integrated payment and messaging system allows users to send and receive electronic payments as well as exchange messages. For example, one or more implementations involve facilitating same day push-to-debit payment transactions between a user and a co-user. To illustrate, one or more implementations involve sending a push-to-debit request to credit funds for the payment amount of the payment transaction to a debit card of a co-user, the push-to-debit request being formatted for same day processing. |
| US09342830B2 |
Classifying open-loop and closed-loop payment cards based on optical character recognition
A user captures an image of a payment card via a user computing device camera. An optical character recognition system receives the payment card image from the user computing device. The system performs optical character recognition and visual object recognition algorithms on the payment card image to extract text and visual objects from the payment card image, which are used by the system to identify a payment card type. The system may categorize the payment card as an open-loop card or a closed-loop card, or as a credit card or a non-credit card. In an example embodiment, the system allows or prohibits extracted financial account information from the payment card to be saved in the digital wallet account based on the determined payment card category. In another example embodiment, the system transmits an advisement to the user based on the determined payment card category. |
| US09342829B2 |
Systems and methods for mobile application, wearable application, transactional messaging, calling, digital multimedia capture and payment transactions
Systems and method are disclosed for multimedia capture and encrypting using an ephemeral messaging and multimedia application associated with a digital device for secured payment by selecting as a first user input a haptic control for a particular type of multimedia content to be captured; interacting as a second user input with a touch display of the digital device by touching a touch display and holding a touch contact of a user finger or stylus for a predetermined time; capturing multimedia content based on the contact and sending a command to a sensor, of the digital device to capture video and starting a timer to determine a duration of the touch contact of the user with the touch display; and making a secured payment with the digital device. |
| US09342824B2 |
System and method for providing customers with seamless entry to a remote server
The present invention provides a seamless entry system that comprises a universal session manager. Users connect to the host service provider with a unique username and password. Then, through a series of data exchanges between the universal session manager, a validation database, and the remote service module, the customer may be transparently logged into remote service providers. Internet banking customers utilize a browser system to connect to a host server providing a range of banking services supported by a remote or distinct server. According to the method, the customer first enters a username and password to gain access to the host service provider. The universal session manager transmits data required for login to the remote service provider. The user is thus able to utilize the remote services with his/her web browser system without having entered a username or password particular to the remote service. |
| US09342823B2 |
Payment clearing network for electronic financial transactions and related personal financial transaction device
Described herein are networks and related devices and methods for facilitating the electronic transfer of funds and electronic purchases between consumers, merchants, and other parties. Also facilitated by the principles described herein is the electronic transfer of funds or payments between individuals. The disclosed principles provide for the funds of a user's account to never leave his original financial account until the financial transaction takes place. Thus, no special accounts within the payment system are required to be opened, maintained, or funded by a user. Instead, funds are simply transferred to or from a user's associated financial account by the financial institution maintaining that account and in accordance with instructions from the network. Thus, the present disclosure provides for fund transfers and purchases between parties in a secure, efficient, and the user-friendly manner. The disclosed principles provide for such transactions using, in some embodiments, portable devices, which may be dedicated devices associated with the disclosed network, or available consumer devices configured to operate with the network. |
| US09342820B2 |
Method for managing e-mail attachments in an email in an email application
The invention proposes a method for managing email attachments in an email application, said method used, on opening an attachment using an editing application defined based on the nature of said attachment, to edit a copy of said attachment and to save the modifications made to said copy as a modified version of said attachment, said method also allowing a logical link to be created between the modified version and the email, said logical link being used to attach said modified version to said email as a modified attachment. |
| US09342818B2 |
System and method for managing incoming and outgoing email messages
A system and method for managing incoming email messages. A computing device operating an email client receives an incoming email message from an email server. A first time rule is applied to a time attribute in the email header. The email message is saved in a hidden folder when the time attribute satisfies the first time rule. A second time rule is applied to a current time. When the current time satisfies the second time rule, email messages in the hidden folder are moved to a folder that is accessible to the email client. |
| US09342814B2 |
Presentation access tracking system
A system comprises a database configured to store a presentation, the presentation having a presentation identifier and comprising a sequence of discrete presentation items, a first discrete presentation item of the plurality being associated with first content with first content type and a second discrete presentation item of the sequence being associated with second content of a second content type. A presenter interface is configured to receive viewer identification information identifying a viewer to which the presentation is to be made accessible. An access controller is configured to create an access credential using both the presentation identifier and the viewer identification information, the access credential to enable access to the presentation by a viewer computer system. A tracker configured to generate access history data pertaining to access by the viewer computer system to each of the sequence of discrete presentation items. The presenter interface is further configured to present the access history data to a presenter computer system. |
| US09342813B2 |
Apparatus and method for displaying log information associated with a plurality of displayed contents
The present invention relates to an apparatus for displaying log information, comprising: a receiving unit for receiving at least one content and correlation information; the correlation information including correlation that correlates each of a plurality of segments formed at a display and each of the at least one content outputted to the plurality of segments, an output unit for outputting the at least one content to the plurality of segments based on the correlation information; and a processor; wherein the processor is configured to generate the log information including segment information and content information, the log information representing content output history, the segment information identifying each of the plurality of segments, and the content information identifying each of the at least one content, extract part of the log information based on either of the segment information or the content information, and output the extracted log information. |