最新美国发明专利第2016-05-10期 - 专利汇|PatentHub专利检索|专利查询网|发明专利查询分析

Document	Document Title
US09337896B2	Block filter for power line communication Provided is a blocking filter for PLC, the blocking filter including a low pass filter unit including a capacitor and a plurality of inductors, a plurality of magnetic saturation prevention circuits each connected to the inductor in parallel to prevent magnetic saturation of the inductor, and operating in response to an interruption control signal inputted from outside, and a first switch connected or opened in response to the interruption control signal and interconnected between the low pass filter unit and a neutral line.
US09337895B2	Electromagnetic surface wave guiding medium having a first surface with coupling nodes repositionable at arbitrary locations An apparatus for radio communication using surface waves, the apparatus comprising: a guiding medium having a first surface suitable for the propagation of surface waves, the first surface having a reactive impedance; at least one communication node, the node having a transmitter and/or receiver coupled to a transducer, the transducer positioned on or adjacent the first surface of said guiding medium; wherein the at least one communication node is arranged to launch and/or receive surface waves, over the first surface of said guiding medium.
US09337885B2	Systems and methods for hybrid self-interference cancellation A system for hybrid self-interference cancellation includes a transmit coupler that samples an RF transmit signal, a RF self-interference canceller that transforms the sampled RF transmit signal to an RF self-interference cancellation signal, an IF self-interference canceller that transforms a downconverted version of the RF transmit signal to an ISRF self-interference cancellation signal, and a receive coupler that combines the RF and ISRF self-interference cancellation signals with an RF receive signal.
US09337879B2	Systems and methods for multi-channel transceiver communications Systems and methods for transceiver communication are discussed herein. A filter module may be configured to filter each carrier signal of a multicarrier transmit signal with a different bandpass filter, each bandpass filter configured to filter a different frequency band. A carrier control module may be configured to control the plurality of bandpass filters of the filter module using a carrier selection signal to enable or disable each bandpass filter, thereby coupling carrier signals of the multicarrier transmit signal to a first set of bandpass filters and decoupling a second set of bandpass filters. Filtering the carrier signals of the multicarrier transmit signal is performed by the first set of bandpass filters while the decoupling of the second set of bandpass filters limits energy in the respective frequency band. An antenna may be configured to transmit the filtered multicarrier transmit signal.
US09337876B2	Digital wireless transmitter having parallel structure and wireless communication system including the same A digital wireless transmitter is provided. The digital wireless transmitter includes a serial-to-parallel converter, a delta-sigma modulator (DSM), and a radio frequency (RF) converter. The serial-to-parallel converter is configured to interpolate a serial digital input signal and to output N parallel signals, where N is a positive integer greater than one. The DSM is configured to perform delta-sigma modulation on the N parallel signals in parallel. The RF converter is configured to arrange N delta-sigma modulated signals into K parallel signals, to delay the K parallel signals by different delay times, and to convert delayed signals into an RF signal, where K is a positive integer greater than N.
US09337875B2	Method and apparatus for reducing charge and discharge time of capacitive elements A system that incorporates teachings of the subject disclosure may include, for example, emulating a behavior of an RF capacitive device utilizing a mirror circuit; and providing feedback signals to an input of an operational amplifier via a feedback node coupled with the mirror circuit. Other embodiments are disclosed.
US09337874B1	High-speed digital signal processing systems Apparatus and method to provide a high speed digital signal processor may implemented in a substantially all digital transmitter designs. In an embodiment, input binary bits are divided into two sets of bits, where one set is provided to a binary to thermometer coder to generate an output mixed with a clock signal to operatively provide a reverse order inverted bit pattern. The other set of binary bits is subject to exclusive-or processing such that processing of the two sets operatively provides a mixed hybrid code to be fed from high speed digital signal processor. Additional apparatus, systems, and methods are disclosed.
US09337871B2	Method and apparatus for processing data Embodiments of the present invention provide a method and an apparatus for processing data. The method includes: performing code block segmentation on a data block to obtain multiple first blocks, wherein a difference between numbers of bits of any two first blocks in the multiple first blocks is not more than 1 bit; determining multiple second blocks according to a padding bit and the multiple first blocks, wherein a value of the padding bit is a preset value; adding consecutive N−K fixed bits to each of the multiple second blocks to obtain multiple third blocks, wherein a value of the fixed bit is a preset value, and N−K≧0; and performing polar encoding according to the multiple third blocks.
US09337869B2	Encoding and syndrome computing co-design circuit for BCH code and method for deciding the same An encoding and syndrome computing co-design circuit for BCH code and a method for deciding the circuit are disclosed. The method includes the steps of: building up matrices of XR, XG and XS according to p parallel computations and 2t syndromes; building up FP; building up F′; building up F″; building up matrix of [XSRG F″]; and designing a circuit which fulfills the operation of [XSRG F″].
US09337868B2	Iterative decoding for cascaded LDPC and TCM coding At a receiver side, to enhance the performance of concatenated LDPC and TCM coding, an iterative decoding between TCM decoder and LDPC decoder enables improvement in the reliability of received LLRs of each symbol after each iteration. A SOVA output of the TCM is used for LDPC decoding, and then the updated LLRs from LDPC decoder are further looped back to the TCM decoder for the next iteration. In such a manner, the decoding performance could be significantly improved after just several iterations.
US09337867B2	Cyclic decoding for cascaded forward error-correction FEC codes A computer implemented method for a cyclic (forward-backward) decoding for a forward error-correction FEC scheme includes decoding a given k−1th codeword in a block code of length N in an optical communication system, forwarding M symbols' enhanced log likelihood ratios LLRs produced by decoding the k−1th codeword, decoding the kth codeword together with forwarded M symbols' enhanced LLRS, and feeding backward, to the initial step i) decoding, corresponding overlapped M symbols' enhanced LLRs for decoding of the k−1th codeword again.
US09337865B2	Log-likelihood ratio (LLR) dampening in low-density parity-check (LDPC) decoders Described embodiments provide a media controller to read data stored in a media. The media controller determines a value for each bit of a shortened codeword from the media. The shortened codeword includes a plurality of non-shortened bits of a full codeword, where the full codeword includes the plurality of non-shortened bits and one or more shortened bits. Shortened bits correspond to bits unused in the shortened codeword. The media controller converts the determined values for each bit of the shortened codeword into a first set of log-likelihood ratio (LLR) values. The full codeword is decoded using the first set of LLR values for the shortened codeword. The media controller dampens one or more LLR values corresponding to non-shortened bits of the codeword to produce a second set of LLR values and decodes the second set of LLR values.
US09337864B1	Non-binary LDPC decoder using binary subgroup processing In one embodiment, an electronic system includes a decoder configured to decode an encoded data unit using multiple variable nodes and multiple check nodes to perform a low-density parity check (LDPC) decoding process. The encoded data unit can be received from a solid-state memory array. As part of performing the LDPC decoding process, the decoder can (i) convert reliability information representing first non-binary values to reliability information representing first binary values, (ii) determine reliability information representing second binary values using the reliability information representing first binary values, and (iii) convert the reliability information representing the second binary values to reliability information representing second non-binary values.
US09337861B2	Method and system for generating a data set Systems, methods, and stored coded instruction sets for reducing the amount of data captured, i.e., retained, by a computerized system, such as an aircraft flight control or monitoring system. Such systems can, for example, be used in monitoring and/or controlling the operation of one or more aircraft engines, flight controls, or other aircraft systems, in order to optimize storage required for collected data, and/or to reduce or otherwise control the time required to off-load captured data to another computer system, such as a land-based analysis system. The amount of data collected, e.g., captured or retained in memory, may be reduced by discarding data points that are within a specified tolerance of, for example, a previously observed or expected value in a manner which assists with preserving the accuracy and precision of the original measured data.
US09337857B2	Analog conversion device and programmable controller system An analog conversion device includes an analog-to-digital (A/D) converter; a shared memory that has an A/D conversion-value storage area for storing the converted digital value and a log storage area for logging a digital value that is stored in the A/D conversion-value storage area and that can be read and accessed from a central processing unit (CPU) that controls an entire programmable controller; a logging execution unit that stores the digital value stored in the A/D conversion-value storage area in the log storage area as logging data; a fixed-number logging detection unit that monitors whether the number of the logging data to be stored in the log storage area has reached a predetermined number since the last interrupt generation request has been made; and an interrupt generation unit that makes an interrupt generation request to the CPU when the number of the logging data has reached the predetermined number.
US09337853B2	Interleaved A/D converter It is a problem that each ADC sampling circuit connected in parallel in an interleaved ADC releases an electric charge depending on an input signal when sampling is performed and other ADCs connected in parallel sample the input signal disturbed thereby so that resolution of the interleaved ADC is decreased.The problem is improved by inputting a common differential sampling clock signal to one set of two ADCs which is sampled at a π-phase shift of each ADC connected in parallel in a time interleaved ADC, providing an individual buffer in a prior stage of an input sampling circuit, isolating a common analog input signal line from an ADC input terminal, and digitally correcting characteristics degradation by insertion of the buffer.
US09337851B2	Phase locked loop circuit equipped with unity gain bandwidth adjustment An electronic circuit is described in which a charge pump-based digital phase locked loop circuit is augmented with additional circuitry to monitor and control noise and power consumption. The additional circuitry includes a comparator and a measurement stage configured to measure and adjust a unity gain bandwidth of the phase locked loop. In one embodiment, the measurement stage includes two frequency-to-current converters and associated current mirrors.
US09337845B2	Solving constraint satisfaction problems using a field programmable gate array A method for configuring a Field Programmable Gate Array (FPGA) with a Constraint Satisfaction Problem (CSP) assignment having multiple constraint expressions, the method comprising: setting each of the multiple constraint expressions as a configurable logic block (CLB) in the FPGA, to yield multiple CLBs; setting an assignment vector in the FPGA, wherein the assignment vector is a number vector configured to store a candidate solution to the CSP assignment; and forming a feedback loop by connecting the assignment vector to inputs of the multiple CLBs, and connecting outputs of the multiple CLBs to the assignment vector. Further disclosed is a design structure for the FPGA, optionally residing on a storage medium as a data format used for the exchange of layout data of integrated circuits.
US09337841B1	Circuits for and methods of providing voltage level shifting in an integrated circuit device A circuit for providing voltage level shifting in an integrated circuit includes an inverter having an input coupled to receive an input signal having a first voltage level; an output stage having a first transistor coupled in series with a second transistor, and an output node between the first transistor and the second transistor generating an output signal having a second voltage level. A gate of the second transistor is coupled to an output of the inverter. A pull-up transistor is coupled between a reference voltage having the second voltage level and a gate of the first transistor. A switch is coupled between the gate of the first transistor and the gate of the second transistor to control a voltage at the gate of the first transistor. A method of providing voltage level shifting in an integrated circuit is also disclosed.
US09337839B2	Pre-driver and power circuit including the same Disclosed are a pre-driver having a modified circuit for gate pulse modulation and a power circuit including the same. The pre-driver includes a level shifter that outputs pulses having a phase difference and a gate pulse modulator that performs gate pulse modulation. The gate pulse modulator outputs a modulated gate pulse obtained by modulating a pulse by a reference voltage, and has a structure in which the number of switches provided therein is reduced.
US09337837B2	Physical unclonable function generation and management Methods, systems and devices related to authentication of chips using physical unclonable functions (PUFs) are disclosed. In preferred systems, differentials of PUFs are employed to minimize sensitivity to temperature variations as well as other factors that affect the reliability of PUF states. In particular, a PUF system can include PUF elements arranged in series and in parallel with respect to each other to facilitate the measurement of the differentials and generation of a resulting bit sequence for purposes of authenticating the chip. Other embodiments are directed to determining and filtering reliable and unreliable states that can be employed to authenticate a chip.
US09337836B2	Method for driving semiconductor device A method for driving a semiconductor device capable of reducing an area of a multiplexer and reducing its power consumption is provided. In a method for operating a semiconductor device including a memory and a multiplexer, a first transistor is connected to a first capacitor, and a second transistor is connected to a second capacitor. In the multiplexer, in a third transistor, a source is connected to a first input terminal and a drain is connected to an output terminal and, in a fourth transistor, a source is connected to a second input terminal and a drain is connected to the output terminal. Further, a step of holding a first potential in a node to which the first transistor, the first capacitor, and a gate of the third transistor are connected and holding a second potential higher than the first potential in the node is included.
US09337834B2	CMOS input buffer circuit A high-linearity CMOS input buffer circuit is provided for neutralizing non-linearity of follower circuits' transconductance and output impedance resulting from input signals' variation. In doing so, the linearity of CMOS input buffer is improved. The buffer circuit includes a CMOS input follower circuit, a linearity improvement circuit of follower transistor, a current source load, and a linearity improvement circuit of load impedance. The buffer circuit is fabricated in standard CMOS process, featuring low cost, simplicity and strong linearity at high frequency. It has wide applications in analog and hybrid analog-digital CMOS ICs requiring high linearity input buffer.
US09337833B2	Driven shield for shaping an electric field of a touch sensor In one embodiment, a method comprises generating, by a control unit, a first drive signal and a second drive signal. The method further includes emitting, by a touch sensor, a first electric field that extends in a plurality of directions in response to reception of the first drive signal. The method also includes attenuating, by a conductive shield, a portion of the first electric field that extends from the touch sensor towards the conductive shield by generating a second electric field in response to reception of the second drive signal.
US09337832B2	Proximity switch and method of adjusting sensitivity therefor A vehicle proximity switch and method are provided having sensitivity control. The switch includes a proximity sensor, such as a capacitive sensor, installed in a vehicle and providing a sense activation field. Control circuitry processes the activation field to sense user activation of the switch by comparing the activation field to a threshold. The threshold is adjusted down when a substantially stable sensor signal is detected below the threshold for a minimum time period, and the threshold is adjusted up when a sensor signal greater than the threshold by a predetermined value is detected.
US09337824B2	Drive circuit with adjustable dead time A drive circuit includes a first input terminal configured to receive a first input signal, a first output terminal configured to provide a first drive signal, a second output terminal configured to provide a second drive signal, and a mode selection terminal configured to have a mode selection element connected thereto. The drive circuit is configured to generate the first and second drive signals dependent on the first input signal such that there is a dead time between a time when one of the first and second drive signals assumes an off-level and a time when the other one of the first and second drive signals assumes an on-level, and evaluate at least one electrical parameter of the mode selection element and is configured to adjust a first signal range of the first drive signal and a second signal range of the second drive signal dependent on the evaluated parameter and to adjust the dead time dependent on the evaluated parameter.
US09337819B2	Programmable delay unit A tunable delay unit and methods of tuning are provided, comprising a plurality of first delay elements and a plurality of first delay element taps between the first delay elements, wherein the first delay element taps are inputs to a first multiplexer and wherein the output of the first multiplexer is selected from among the inputs according to a first tap select input, further comprising a plurality of second delay elements connected in series to the output of the first multiplexer and a plurality of second delay element taps between the second delay elements, wherein the second delay element taps are inputs to a second multiplexer and wherein the output of the second multiplexer is selected from among the inputs according to a second tap select input, the output of the second multiplexer forming the output of the programmable delay unit. The programmable delay unit provides for highly accurate calibration of timed circuits, in particular delay lines.
US09337817B2	Hold-time optimization circuit and receiver with the same A hold-time optimization circuit includes a correction circuit and a delay control circuit. The delay control circuit delays a clock signal for a delay time so as to generate a delay clock signal. The correction circuit generates a correction pulse signal according to transition edges of a data signal and transition edges of the delay clock signal. The delay time of the delay control circuit is optimized according to the correction pulse signal. The data signal is sampled according to the delay clock signal.
US09337816B2	Delay circuit using capacitor as delay element A delay circuit using a capacitor with an MOS structure as a delay component, includes a clamp circuit operating a clamp operation and a clamp release operation in response to levels of an input signal, the clamp circuit clamping a voltage applied to the capacitor to a specified charging initiation voltage during the clamp operation; a charging circuit charging the capacitor with a constant current when the clamp operation is released; and a delayed signal producing circuit producing a delayed signal when the voltage of the capacitor being charged reaches a voltage of a predetermined value.
US09337814B2	Microwave pulse generator with variable frequency emission A variable frequency microwave pulse generator that includes a high voltage charger for charging with a high voltage, a high pressure gas tank for supplying insulation gas, and an electrode discharge unit. The electrode discharge unit includes a case, an accommodation section defined inside the case, and a pair of electrode sections disposed at one side and the other side of the accommodation section so as to face each other. The pair of electrode sections is spaced apart from each other to define a spark gap therebetween where the insulation gas supplied from the high pressure gas tank is loaded. An annular resonance recess is defined at the central portion of one electrode section of the pair of electrode sections, the depth of the resonance recess being variable in response to an adjustment knob disposed on the case being manipulated.
US09337812B2	Avalanche pulser Circuits and methods for generating a pulse are provided. The generating can comprise receiving at least one trigger input signal with a pulse generating circuit; generating a voltage pulse having a duration less than the avalanche time of a transistor in response to at least a portion of the at least one trigger input signal with the pulse generating circuit; transmitting the voltage pulse from the pulse generating circuit to a terminal of the transistor, the transistor constructed and arranged to be operable in an avalanche mode; and outputting an avalanche pulse from at least one terminal of the transistor in response to the voltage pulse. In some embodiments, the pulse can be transmitted with an antenna in a radar system, and a return pulse can be received and processed.
US09337810B2	Semiconductor device There is provided a semiconductor device in which an influence of a power source noise is suppressed and the number of pins and the area of the semiconductor device are reduced. A power source line for a first internal circuit and a power source line for a second internal circuit are coupled to a common pin terminal. A ground line for the first internal circuit and a ground line for the second internal circuit are coupled to another common pin terminal. A power source noise generated on the power source line for the first internal circuit during an operation of the first internal circuit is absorbed by a P-channel MOS transistor and a capacitor. A power source noise generated on the ground line is absorbed by an N-channel MOS transistor and the capacitor.
US09337808B2	Semiconductor devices and semiconductor systems including the same A semiconductor system includes a controller and a semiconductor device. The controller receives a temperature code signal and responsively generates a mode set signal operable to adjust a level variation and a voltage variation rate of a temperature voltage signal, wherein the temperature voltage signal level varies according to temperature when a logic level combination of the temperature code signal is different from a predefined logic level combination. The semiconductor device generates the temperature voltage signal from a drivability and a resistance value set by the mode set signal. The semiconductor device generates the temperature code signal based on a comparison of the temperature voltage signal and a reference voltage signal.
US09337805B2	Efficient digital microphone decimation filter architecture A new and more efficient filtering system (e.g., digital microphone decimation filter architecture system) is described. A key to this architecture is the use of two parallel filter paths. Each path operates at the output sample rate, and comprises a shorter FIR filter followed by a series of allpass stages (e.g., implementing IIR filters). The FIR filter is designed to remove all but the last octave of out-of-band noise. The allpass stages are designed such that when the two paths are summed together, the out-of-band noise for the final octave cancels out, leaving only the desired sign.
US09337804B2	Impedance matching network with high frequency switching An impedance matching network having a plurality of reactance elements is disclosed. Each of the plurality of switching circuits comprises a first node and a second node; a first diode having an anode coupled to the first node and a cathode coupled to the second node; a second diode having an anode to couple to the second voltage line and a cathode to couple to the first node; and a transistor having a first, second, and control terminals. Each of the plurality of reactance elements is switched into the impedance matching network when the transistor in the respective one of the plurality of switching circuits is on and switched out after the transistor in the respective one of the plurality of switching circuits is off.
US09337791B1	System and method for generating multimedia accompaniments to broadcast data A method and system is presented for coordinating the transmission of supplemental digital data to accompany broadcast data, and in particular, analog radio broadcasts, among a plurality of broadcasters. The supplemental digital data may provide information about the particular broadcast data being transmitted (i.e. cut data) or may be supplemental to such data (i.e. news, weather and traffic data). The supplemental digital data to be presented is sorted based on particular algorithms which may take into account broadcaster-specified criteria such as target audience, time of day, type of broadcast data presented, and the like. The supplemental digital data may be audio data, visual data, or audio-visual data for presentation with the broadcast data. The supplemental digital data may further be advertisement data. The advertisement data may be sold by the broadcasters or the party coordinating the IBOC transmission of the supplemental digital data. The supplemental digital data may play simultaneously with muted broadcast data or at a user-specified time.
US09337785B1	High-linearity, ultra-wideband multi-stage track-and-hold amplifier with shunted source-follower first-stage Examples are provided for a multi-stage track-and-hold amplifier (THA). The multi-stage THA may include a first stage, a second stage, and a third stage. The first stage may be coupled to an input signal and configured to sample the input signal. The second stage may be coupled to the first stage and may include a buffer circuit. The third stage may be coupled to the second stage and can include a bootstrapped THA. The first stage may further include a shunted source-follower circuit and a switched source-follower circuit. The shunted source-follower circuit may include a first switch that can be operable to couple an output node of the shunted source-follower circuit to ground potential.
US09337782B1	Methods and apparatus for adjusting transmit signal clipping thresholds Integrated circuits are provided with wireless communications circuitry having digital predistortion (DPD) circuitry, peak canceling circuitry, a power amplifier, and signal conditioning circuitry for controlling the DPD and peak canceling circuitry. The peak canceling circuitry may receive transmit signals and may clip peaks in the transmit signals that exceed a magnitude threshold value. The DPD circuitry may compensate for non-linear characteristics of the power amplifier by outputting a predistorted version of the clipped transmit signals. The power amplifier may receive the predistorted signals and may perform amplification to generate amplified signals. The signal conditioning circuitry may identify power transfer characteristics of the power amplifier and DPD circuitry using the predistorted signals and the amplified signals. The signal conditioning circuitry may update the magnitude threshold value imposed by the peak canceling threshold based on the identified power transfer characteristics to mitigate out-of-band spectral regrowth in the predistorted signals.
US09337770B2	Solar cell module A long-side frame piece has a cylindrical portion. The cylindrical portion is formed from one side end along the direction in which the long-side frame piece extends to the other side end. The cylindrical portion has threaded holes. The threaded holes are provided inside a through hole. Screws are inserted in the threaded holes. A short-side frame piece has a plate-shaped portion. The plate-shaped portion covers the end of the cylindrical portion in the direction in which the long-side frame piece extends. Openings are formed in the plate-shaped portion, through which pass the screws inserted in the threaded holes. The plate-shaped portion has a cutout exposing a portion of the module body from a first surface toward a second surface, formed closer to a first direction side than the threaded holes of the through hole.
US09337764B2	Drive control device, electrical apparatus and drive control method A drive control device is provided with a physical amount detection unit which detects the physical amount pertaining to the output of a motor, a rotational frequency determination unit for determining whether the rotational frequency of the motor is equal to or greater than a base rotational frequency, a threshold value selection unit for selecting a threshold value for the physical amount in accordance with the determination result of the rotational frequency determination unit, and a rotational frequency control unit for controlling the rotational frequency of a rotating shaft in accordance with the magnitude relationship between the detected physical amount and the selected threshold value.
US09337761B1	Generator excitation regulation using pulse width modulation A system may be configured to provide a regulated generator field current to a generator to acquire a regulated output voltage of the generator. In one example, the system comprises a controller configured to provide an actuator control signal on the basis of an error signal, an actuator configured to provide on the basis of the actuator control signal a pulse-width modulated output voltage that is configured to drive the regulated generator field current into the generator, the pulse-width modulated output signal having a duty cycle controlled by the actuator control signal, and an error evaluator configured to provide the error signal based on a combination of a first deviation signal and a second deviation signal.
US09337757B2	Motor controller The outputs from a first magnetic detector and a second magnetic detector are supplied to first to fourth output circuits which are differential amplifiers, whereby first and second detected outputs which are analogous to a sine wave and whose positive-negative polarities are opposite to each other, and third and fourth detected outputs which are analogous to a cosine wave and whose positive-negative polarities are opposite to each other are obtained. The first to fourth detected outputs are supplied to a switching circuit, and detected output portions are obtained at intervals of 90° from the first to fourth detected outputs. A bias adding circuit applies a bias voltage to each of the detected output portions to obtain an angle detection output analogous to a linear function. The angle detection output is used to determine the supply timing at which a three-phase driving current is supplied.
US09337754B2	Control apparatus for AC motor A control apparatus for an AC motor that drives and controls the AC motor includes a damping control unit that calculates a damping manipulated variable that suppresses a fluctuation in the capacitor voltage, wherein the damping control unit calculates a fluctuation rate of the capacitor voltage, calculates the damping manipulated variable based on the fluctuation rate and a predetermined value that is set as a value in a predetermined range around a maximum torque of the AC motor, generates a torque command or a current command of the AC motor based on the damping manipulated variable, and controls an inverter so as to change a current flowing in the inverter in a fluctuation suppressing direction with respect to a fluctuation in the capacitor voltage based on the torque command or the current command.
US09337753B2	System and method for cold start of vehicle A system and method for a cold start of a vehicle are provided. The method includes setting a target electrical angle by adding a setting angle to a previously stored initial electrical angle of a driving motor and applying an electric current value that corresponds to the set target electrical angle to the driving motor.
US09337750B2	Power conversion apparatus A power conversion apparatus includes an inverter circuit including a switching element, a system voltage measurement unit measuring a system voltage of a power system, a voltage drop detector detecting a voltage drop of the power system, a carrier wave generator generating a carrier wave, a carrier wave frequency modulator increasing a frequency of the carrier wave, when the voltage drop is detected, a signal wave generator generating a signal wave to control the inverter circuit, a gate signal generator comparing the carrier wave with the signal wave, and generating a gate signal, and a power conversion controller controlling the inverter circuit, based on the gate signal.
US09337748B2	System and method for a DC-to-DC power converter with inverter stage coupled to the DC input In accordance with a preferred embodiment of the present invention, an inverter circuit includes a direct current (DC)-to-DC power converter configured to receive an input energy from a device via a first input terminal and a second input terminal, where the DC-to-DC power converter is configured to convert a first portion of the input energy to a DC energy. The inverter circuit also includes an inverter stage coupled to an output of the DC-to-DC power converter, and is connected to the first input terminal of the DC-to-DC power converter and the second input terminal of the DC-to-DC power converter, where the inverter stage is configured to convert a second portion of the input energy to a first output energy.
US09337745B2	Integrated circuit device for power supply An integrated circuit device, for a power supply that is connected to an AC power source via an input circuit having a capacitor, is able to reliably discharge the capacitor when the AC power source is interrupted. The integrated circuit device includes a first discharge circuit that operates in response to an internal supply voltage and discharges the capacitor via a first switch element that is turned on when the input voltage provided via the input circuit falls below a set voltage, and a second discharge circuit having a second switch element that is turned off when receiving the internal supply voltage but is turned on in response to the input voltage when the supply of internal supply voltage is interrupted.
US09337738B2	Transformer-coupled gate-drive power regulator system A transformer-coupled gate-drive power regulator system is provided that includes a feedback stage that generates a PWM signal having a duty-cycle that is based on a magnitude of an output voltage in an output stage. A switch driver stage configured to provide each of a first control signal and a second control signal based on the PWM signal. A switching stage comprising a first transformer input stage, a second transformer input stage, and a control switch. The first transformer input stage activates the control switch via the first control signal while the second transformer input stage is deactivated, and the second transformer input stage activates the control switch via the second control signal while the first transformer input stage is deactivated. The control switch can be configured to provide current through an output inductor in the output stage to generate the output voltage in response to being activated.
US09337737B2	Control circuit with fast dynamic response for power converters A control circuit of a power converter is provided. It comprises a voltage detection circuit detecting a reflected signal for generating a voltage-loop signal. A current detection circuit detects a current of a transformer for generating a current-loop signal. An oscillator generates an oscillation signal in accordance with an output load of the power converter. A PWM circuit generates a switching signal according to the voltage-loop signal, the current-loop signal and the oscillation signal for regulating an output of the power converter. A load detection circuit receives a detection signal through an signal-transfer device for increasing a switching frequency of the switching signal. The detection signal is generated once the output is lower than a low-voltage threshold. The oscillation signal determines the switching frequency of the switching signal. The control circuit reduces the voltage drop of the output when the output load is changed.
US09337736B2	Controller with power saving for power converters and method for the same A controller with power saving for a power converter includes a delay circuit, a detection circuit, an output circuit, a counter circuit, a wake-up circuit and a PWM circuit. The delay circuit determines a delay time. The detection circuit activates the delay circuit whenever an output load of the power converter is lower than a light-load threshold. The output circuit generates a power-saving signal to cease a regulation of the power converter after the delay time ends. The regulation of the power converter is resumed once the output load increases during the regulation of the power converter is being ceased. The counter circuit coupled to the delay circuit is counted by the delay circuit to determine a sleep period. The output circuit generates the power-saving signal to cease the regulation of the power converter after the sleep period ends.
US09337733B2	Adaptive pre-charge voltage converter A voltage converting device includes a feedback module, for generating a comparing signal according to a feedback voltage and a reference voltage; a pulse-width-modulation module, for generating a driving signal according to comparing signal; a voltage-converting module including a low-side switch for controlling a connection between a node and ground according to driving signal, a high-side switch for controlling a connection between the node and an output end according to a control signal, an inductor coupled between the node and an input end, a feedback-voltage-generating unit for generating feedback voltage according to an output voltage of output end and a ratio, an adaptive current-generating unit for generating a current signal according to an adjusting signal, and a control unit for selecting driving signal or current signal as the control signal according to output voltage and an input voltage; and a current-adjusting module for generating adjusting signal according to comparing signal.
US09337731B2	Power converter for generating both positive and negative output signals A power converting system produces an input signal regulated with respect to an input signal. The power converting system has a first inductive element having a first node coupled to an input node, and a second inductive element having a first node coupled to an output node. A first switching element is coupled to a second node of the first inductive element. A first capacitive element is coupled between the second node of the first inductive element and of the second inductive element. A control circuit sets a duty cycle of the first switching element to a first value for providing the output signal of a first polarity responsive to the input signal of the first polarity, and to set the duty cycle of the first switching element to a second value for providing the output signal of a second polarity responsive to the input signal of the first polarity.
US09337729B2	High efficiency DC-DC converter with fast clock operation and load change response The DC-DC converter includes a reference voltage generating circuit that generates a reference voltage. The DC-DC converter includes a modulation clock signal generating circuit that generates a modulation clock signal. The DC-DC converter includes a modulator that performs modulation of the reference voltage in synchronization with the modulation clock signal and outputs a resulting reference signal. The DC-DC converter includes a first comparator that compares the reference signal and a first feedback signal, which is based on the output voltage, and outputs a signal based on a result of the comparison. The DC-DC converter includes a driver that shapes a waveform of a PWM signal, which is based on the signal output from the first comparator, and outputs the PWM signal with the shaped waveform to the control node.
US09337723B2	Charge pump system and memory Charge pump system and memory are provided. The system includes: a first enabling control unit, adapted to delay at least one start-up signal of the system to obtain and output an oscillating enabling signal after receiving the at least one start-up signal and a voltage boosting enabling signal; a second enabling control unit, adapted to delay the oscillating enabling signal to obtain and output a charge pump enabling signal after receiving the oscillating enabling signal and the voltage boosting enabling signal; a clock oscillating unit, adapted to generate a clock signal after receiving the oscillating enabling signal; and at least one charge pump cell, adapted to output a boosting voltage after receiving the charge pump enabling signal and the clock signal, obtain the voltage boosting enabling signal based on the boosting voltage, and output the voltage boosting enabling signal. Power consumption of the system in a start-up process is reduced.
US09337719B2	Power converter control device A power converter control device includes an alarm signal generation circuit which detects information necessary for a protection operation of a semiconductor element configuring a power converter, and generates and externally outputs an alarm signal with a pulse width responding to a protection factor; a temperature signal generation circuit which detects a temperature of the semiconductor element, and generates a PWM signal, correlated with the temperature, the cycle of which is different from the pulse width of the alarm signal; and an output control circuit which selects the PWM signal in normal time, and selects and externally outputs the alarm signal in place of the PWM signal when the alarm signal is generated.
US09337716B2	Power supply circuit with PFC function, and automatic gain control circuit therefor and control method thereof The present invention discloses a power supply circuit with power factor correction (PFC) function, and an automatic gain control circuit therefor and a control method thereof. The power supply circuit includes the automatic gain control circuit and a load driver circuit. The automatic gain control circuit converts an input voltage to a regulation voltage, and the load driver circuit generates an output current according to the regulation voltage. The automatic gain control circuit automatically adjust the regulation voltage such that the regulation voltage has a substantially fixed amplitude or fixed average value under different input voltages of different specifications, and the output current provided by the load driver circuit varies in phase with the input voltage to provide a PFC function.
US09337713B2	Sampling circuit for measuring the reflected voltage of transformer for power converter A sampling circuit of the power converter according to the present invention comprises an amplifier circuit receiving a reflected voltage for generating a first signal. A first switch and a first capacitor are utilized to generate a second signal in response to the reflected voltage. A sample-signal circuit generates a sample signal in response to a falling edge of a switching signal. The switching signal is generated in accordance with a feedback signal for regulating an output of the power converter. The feedback signal is generated in accordance with the second signal. The sample signal is utilized to control the first switch for sampling the reflected voltage. The sample signal is disabled once the first signal is lower than the second signal. The sampling circuit precisely samples the reflected voltage of the transformer of the power converter for regulating the output of the power converter.
US09337712B2	Eccentric magnetic gear system based on repulsion An eccentric magnetic, non-contacting gear system which can affect shaft speed and torque while minimizing mechanical friction and wear has bi-axial shafts. This efficient, non-contacting gear system can be produced by the interaction of circular arrays (or pitch circles) of permanent magnets with eccentric engagement. Coupling is provided by magnetic field repulsion. Input torque is applied to a circular array of permanent magnets representing a first gear, which then through magnetic fields, not physical contact, transfers the torque to another circular array of permanent magnets representing a second gear having an offset output shaft. Gearing may be done in one step or in stages.
US09337711B2	Actuator, optical scanner, and image forming apparatus An actuator including a movable portion that swings about a swing axis, a connecting portion that extends from the movable portion and torsionally deforms in response to the swinging of the movable portion, and a support portion that supports the connecting portion, wherein the movable portion is so shaped that the length thereof parallel to the swing axis decreases stepwise with distance from the swing axis in a plan view, and the movable portion, the support portion, and the connecting portion are formed by anisotropically etching a silicon substrate.
US09337707B2	System, apparatus, and method for controlling a motor Mechanisms are provided to control the operation of a motor. In particular, a variable frequency drive motor controller is described which resides within a motor housing. Additionally, the speed at which the motor operates is based on a signal received from a Hall Effect switch or from a communication device in communication with a remote interface. The Hall Effect switch is also described; in particular, the Hall Effect switch features a magnet rotatably connected with one side of a motor housing. A Hall Effect sensor, located on the opposite side of the motor housing, detects the position of the magnet and outputs a signal to the motor controller, located within the motor housing, indicating the detected magnet position. Additional operating features are described relating to the safe operation and control of the motor in potentially hazardous environments.
US09337701B2	Generator motor and work machine A generator motor connected to an output shaft of an engine mounted in a work machine includes a terminal box that houses a plurality of connectors for connecting an exterior electric-power-supplying cable to the generator motor. While the terminal box is provided to the generator motor, the plurality of connectors are juxtaposed in a direction intersecting an orthogonal plane that is orthogonal to a rotation shaft of the generator motor.
US09337699B2	Modularized elongation ring for air outlet in self-ventilated traction motor An elongation ring adapted for use in a self-ventilated traction motor and for fixed placement between the non-driving end of the motor housing and a motor end shield. The ring has radial air outlet openings placed along its circumference and is adapted to enclose a fan wheel fixed on a motor driving shaft. A traction motor having such an elongation ring is also contemplated. The elongation ring provides a possibility to easily adapt a motor housing to different motor types such as a self-ventilated motor with the ring, or one with forced ventilation without the ring.
US09337696B2	Rotary electric machine, stator unit and wire connection substrate A rotary electric machine includes: a rotating shaft having an axis extending in an axial direction; a rotor fixed to the rotating shaft; a stator provided with a plurality of stator coils; a wire connection part provided at one side of the stator coils in the axial direction, the wire connection part connecting end portions of the stator coils in a specified wire connection pattern; and a resin molded part arranged to cover the wire connection part and the stator coils. The wire connection part includes a plurality of conductive members connected to the end portions of the stator coils and an insulating member arranged to at least partially cover surfaces of the conductive members. The insulating member has projection portions protruding toward the resin molded part existing at the one side of the stator coils in the axial direction.
US09337695B2	Single-layer coil with one bent endwinding and one straight endwinding The present invention provides an improved single-layer coil for a rotating or linear electrical machine. The coil has a first endwinding that is substantially straight to a longitudinal axis of the coil and a second endwinding that is bent relative to the longitudinal axis of the coil. The coil therefore has differently shaped endwindings with one end 12 being ‘straight’ and the other end being ‘bent.’
US09337692B2	Permanent magnet rotor with flux barrier for reduced demagnetization A flux barrier includes a radially outer proximate part and a radially inner proximate part that are a rotor radially outer side surface and a rotor radially inner side surface extending from a communicating part, at least one of the radially outer proximate part and the radially inner proximate part is connected to an end part of a magnet fixing part of a magnet hole in an inward direction of the magnet hole, and a projecting part projecting in an inward direction of the flux barrier is provided on at least one of the radially outer proximate part and the radially inner proximate part connected to the magnet fixing part. A constricted part in which a width of the flux barrier is narrower than on a side closer to the communicating part than the projecting part is formed by the projecting part.
US09337688B2	Environmental system and modular power skid for a facility A set of two or more modular-critical-power-distribution skids are arranged in a redundant power center configuration to supply power to electrical loads in a modular data center facility. The skids are housed in hardened buildings. The uninterruptable power supply is electrically and mechanically connected into the multiple power distribution cabinets, all of which are mounted onto a steel framed support structure, which supports a weight of those uninterruptable power supplies and power distribution cabinets. The environmental control system controls a cooling system for the modular-critical-power-distribution skids. Electrical power from the A-side and B-side connects in a redundant power configuration to electrical loads in the cooling system.
US09337687B2	Charging control system and device A charging control system for charging a secondary battery from a solar battery, including a first path for transmitting power from the solar battery to the secondary battery, a second path for sensing the voltage of the secondary battery, and a comparison unit for comparing the solar battery voltage with the sensed voltage of the secondary battery. The first path includes a first interrupter, controlled by the comparison unit, which interrupts the first path to prevent discharge of the secondary battery through the solar battery when the solar battery voltage falls below the secondary battery voltage. The second path includes a second interrupter that interrupts the second path after the first path is interrupted, to prevent the secondary battery from discharging through the second path when not being charged through the first path.
US09337684B2	Battery charging device and method An improved battery charging method is usable by a battery charger to charge a battery. The charging method may include an optional desulfation process, a first constant current process, a constant voltage process, a second constant current process and a float charge process. The charging method preferably improves various charge and usage characteristics of the battery through a single or continued use of the battery charger utilizing the charging method.
US09337683B2	Controlling battery states of charge in systems having separate power sources A control system is designed or configured to control the state of charge of a battery or battery pack in a system containing a separate power source, which is separate from the battery or battery pack. In operation, the battery or battery pack is called upon to intermittently provide power for certain functions. The separate power source may be, for example, an AC electrical power source for a UPS or an engine of a vehicle such as a micro hybrid vehicle. The battery may be a nickel zinc aqueous battery. The control system may be designed or configured to implement one or more of the following functions: monitoring the state of charge of the battery or battery pack; directing rapid recharge of the battery or battery pack from the separate power source when the battery or battery pack is not performing its functions; and directing charge to fully charged level or a float charge level, which is different from the fully charged level, in response to operating conditions.
US09337674B2	Desktop charger A desktop charger includes a housing having a face panel with multiple insertion slots and an openable front cover plate for closing the face panel, a rack mounted inside the housing and defining multiple insertion slots in communication with the insertion slots of the face panel, and a power supply module including a system circuit board holding multiple electrical connectors in respective connector holes in the face panel for the connection of transmission cables of mobile electronic products being inserted into the insertion slots of the face panel and the insertion slots of the rack, a power adapter connectable to an external power source for power input and a control system for controlling the operation of the system circuit board and the power adapter and for charging the inserted mobile electronic products and for allowing the inserted mobile electronic products to transmit signals and data during charging.
US09337673B2	Battery charging apparatus and method of controlling battery charging apparatus A battery charging apparatus that controls charging of a battery by an alternating-current generator, the battery charging apparatus has a first switch element connected to a first battery terminal to which a positive electrode side of the battery is connected in a normal connection of the battery at a first end thereof and to a first generator terminal to which a first output of the alternating-current generator is connected at a second end thereof, and a second switch element connected to the first battery terminal at a first end thereof and to a second generator terminal to which a second output of the alternating-current generator is connected at a second end thereof. In a case when a controlling circuit stops controlling the first switch element and the second switch element, and the first switch element and the second switch element are turned off, a detecting circuit, which detects a reverse connection condition of the battery, forcedly turns on at least one of the first switch element and the second switch element when the detecting circuit detects the reverse connection condition of the battery.
US09337672B2	Displaying apparatus and mobile electronic device and displaying frame thereof Disclosed are a displaying apparatus, a mobile electronic device, and a displaying frame. The displaying apparatus includes a mobile electronic device and a displaying frame. The mobile electronic device includes an electrical power contact, a circuit-breaking contact, and a battery circuit. The electrical power contact is electrically connected to the battery circuit, and the circuit-breaking contact is positioned corresponding to a control point of the battery circuit. The displaying frame includes a conductive part and an insulation part. When the mobile electronic device is disposed in the displaying frame, the conductive part is configured to press against the electrical power contact for transmitting electric power to the mobile electronic device, and the insulation part is configured to be inserted into the circuit-breaking contact to push the control point for breaking the battery circuit.
US09337666B2	Controlling field distribution of a wireless power transmitter Exemplary embodiments are directed to control of field distribution of a wireless power transmitter. A transmitter may include a transmit antenna configured to generate a field. The transmitter may further include least one parasitic antenna proximate the transmit antenna and configured to modify a distribution of the generated field.
US09337664B2	Wireless power receiver circuitry Exemplary embodiments are directed to wireless power receivers. A device may include a power converter configured to receive an input voltage. The device may further include circuitry configured to limit a pulse width modulation duty cycle of the power converter to prevent the input voltage from dropping below a threshold voltage.
US09337661B2	Power management system and method An apparatus including a storage area to store instructions and a controller to control power in a first device based on the instructions. In operation, the controller generates one or more signals to combine power from a first power source and a second power source for a hybrid power operation. The controller is to generate the one or more signals based on a connection state of the first device, multiple connection states of the first device, a charge level of a battery of the first device, or a combination thereof.
US09337659B2	Systems configured to transmit optical power signals transdermally out of a living subject, and devices and methods In an embodiment, a system includes an internal optical power transmitter configured to be disposed within a living subject. The internal optical power transmitter includes a power source configured to provide electrical energy and an electrical-optical converter operably coupled to the power source. The electrical-optical converter may be configured to convert at least a portion of the electrical energy into one or more optical power signals transdermally transmittable out of the living subject. The system further includes an external optical-electrical converter configured to convert the one or more optical power signals into one or more electrical power signals and at least one external device configured to be operably coupled to the external optical-electrical converter and powered by the one or more electrical power signals. Embodiments of methods, biocompatible electrical-optical converters, and internal optical power transmitters are also disclosed.
US09337658B2	Network system Provided is a network system including: a utility network including an energy generating unit; a home network consuming energy generated from the energy generating unit and including an energy consuming unit operating based on energy information including at least one energy price information; and a power adjusting device through which a current or a voltage supplied for an operation of the energy consuming unit is passed, wherein the power adjusting device reduces energy cost or an energy amount used by adjusting a voltage or current amount applied to the energy consuming unit based on the energy information.
US09337657B2	Power unit control system A system is provided that includes a plurality of power units each configured to supply power. Additionally, the system includes a plurality of contacts each configured to toggle an electrical connection of each of the plurality of power units as a network. Moreover, the network is configured to supply power to a load. Furthermore, the system includes a controller configured to control when each of the plurality of contacts toggle according to a power state, and the power state includes information regarding a charge of each power unit, a load demand, and a supplied power being supplied by the plurality of power units.
US09337656B2	Method and system for forecasting wind energy A method for forecasting wind energy production is disclosed. The method includes collecting power data indicative of power output from a set of wind energy installations with a first wind energy installation at a first site and a second wind energy installation at a second site, and estimating the available power output at a forecasting site located at a geographic position. The estimating is based on power data from the set of wind energy installations by projecting the power data towards the future and/or the geographic position of the forecasting site. Further disclosed is a method for scheduling wind energy production for an electricity grid and a wind energy production forecasting system configured for forecasting output power of a wind energy installation.
US09337655B2	Method and device for the directional transmission of electrical energy in an electricity grid A method for the directional transmission of electrical energy in an electricity grid and to a method for transmitting electrical energy via an electricity grid having at least at least one generator for electrical energy, at least one network node and at least one consumer. A method and a system are provided for transmitting electrical energy, which method and system are highly flexible and make it possible to design the energy distribution in a grid dynamically so as to deal with even short-term fluctuations both on the supply side and on the demand side. A method for the directional transmission of electrical energy in an electricity grid is included, which method comprises the following steps: receiving a data packet, receiving an energy packet associated with the data packet, determining a receiver from the information contained in the data packet, transmitting the data packet to the previously determined receiver and transmitting the energy packet, which is defined by the voltage U(t), the electric current I(t) and the duration T of the packet, associated with the data packet to the same previously determined receiver.
US09337648B2	Device, method, and system for integrated battery power control A device, method, and system includes an integrated battery power controller configured to monitor a voltage difference between a first output terminal and a second output terminal; disconnect, via a switch, at least one of the first output terminal and the second output terminal from a power source if the voltage difference between the first output terminal and the second output terminal is less than a predetermined voltage threshold; and connect, via the switch, both the first output terminal and the second output terminal to the power source if the voltage difference between the first output terminal and the second output terminal is equal to or greater than the predetermined voltage threshold.
US09337646B2	Electrode arrangement for an electrical component An electrode configuration for an electrical component, in particular a surge protector, includes two electrodes extending in a plate-shaped manner parallel to a radial plane relative to a connection axis of the electrodes, defining an axial direction. At least one electrode has a connection region lying in the radial plane and at least two, three or four ribbon-shaped strips each extending away from the connection region and at least partially in circumferential direction relative to the axial direction. A fault arc, occurring during a lightning strike, can be conducted outwards away from the electrical component and forced into rotation around the electrical component in an effective manner due to the ribbon-shaped strips at the outer edge of the connection region and at least two ribbon-shaped strips overlapping each other at a spacing with respect to their delimiting surfaces lying perpendicular to the axial direction.
US09337644B2	ESD protection circuit An electrostatic discharge (ESD) protection circuit is provided. The ESD protection circuit includes an impedance device coupled between a pad and a power line and a clamp unit coupled between the pad and a ground line.
US09337642B2	Surge protection apparatus having multiple surge protection devices and display A surge protection apparatus includes a first surge protection device (10) having a number of first transient suppressing elements, a second surge protection device having a number of second transient suppressing elements, and a circuit coupled to the surge protection devices. The circuit has a number of display elements, wherein the circuit is structured to receive input signals from the first and second surge protection devices and (i) responsive to any one of the first transient suppressing elements failing, causes the number of display elements to provide a first indication indicating that at least one of the first transient suppressing elements has failed, and (ii) responsive to any one of the second transient suppressing elements failing, cause the number of display elements to provide a second indication indicating that at least one of the second transient suppressing elements has failed.
US09337640B2	Electrical protection device and method A voltage measurement is made between two points in a circuit. If the measured voltage exceeds a predetermined amount, a switch is operated to electrically connect the two points.
US09337634B2	Wire harness and method of manufacturing wire harness A wire harness includes a wire harness main body and a protective member. The wire harness main body includes a trunk line and a branch line branching from the trunk line. In a state where a non-woven member covers the trunk line and a base end of the branch line, the protective member is formed by hot pressing a portion of the non-woven member covering at least the trunk line. A portion of the protective member covering the base end of the branch line is formed to be more pliable than a portion covering the trunk line.
US09337632B2	Splice sleeve retainer with three coupling members for securing a sleeve to an electrical joint body A splice sleeve retainer for securing a sleeve to a leg of an electrical joint body has a retention axis and includes at least one connecting strap extending along the retention axis, and first, second and third coupling members secured to the at least one connecting strap at axially spaced apart locations along the at least one connecting strap. The splice sleeve retainer is configured such that, when the sleeve is installed on the leg and the splice sleeve retainer is installed on the sleeve: the first coupling member engages the sleeve at a first axial location; the second coupling member engages the sleeve at a second axial location nearer the leg than the first axial location; and the third coupling member engages the joint body to resist axial displacement of the sleeve relative to the leg.
US09337622B2	Compact distributed bragg reflectors Ultra compact DBRs, VCSELs incorporating the DBRs and methods for making the DBRs are provided. The DBRs are composed of a vertical reflector stack comprising a plurality of adjacent layer pairs, wherein each layer pair includes a layer of single-crystalline Group IV semiconductor and an adjacent layer of silicon dioxide.
US09337617B2	Tunable semiconductor lasers A tunable semiconductor laser having, in one embodiment, a higher bias voltage end, a lower bias voltage end, and an optically active gain region comprising a band-gap configured to emit light at an emission wavelength that is tunable when an electric field is generated across the optically active gain region by applying a bias voltage thereto, an electron quantum well (QW) layer positioned closer to the higher bias voltage end than the lower voltage bias end, and a hole QW layer positioned closer to the lower bias voltage end than the higher bias voltage end and comprising a type-II band alignment with the electron QW layer such that the band-gap is determined by an energy difference between a ground electron state in the electron QW layer and a ground hole state in the hole QW layer, wherein the emission wavelength is redshifted upon an increase in a bias voltage applied to the optically active gain region.
US09337615B2	Vertical cavity surface emitting laser cavity with low thermal impedance The present invention concerns new designs of VCLs with high contrast gratings (HCG) combined with diamond layer as a bottom mirror. They can be realized either with a classical V-shaped pumping scenario, or through the introduction of the pumping beam from the bottom direction, through the HCG that can be designed to be transparent at the wavelength of the pumping light. They can also be completed by a HCG combined with diamond layer as top mirror, reflecting the pump diode laser and transparent to the VCL emission in the case the pumped and emitted beams are collinear.
US09337614B1	Cooling disk lasers A laser disk module includes a lasing element including an active gain medium, the lasing element including opposite top and bottom end surfaces, and a heat transfer element adjacent the bottom end surface, the heat transfer element including a ceramic material that defines a plurality of cooling structures. The heat transfer element is configured to transfer heat generated in the lasing element to a coolant in contact with the heat transfer element in the plurality of cooling structures during operation of the laser disk module.
US09337613B1	Chip on submount carrier fixture Heat assisted magnetic recording uses a laser diode (LD) to provide energy during the writing process. The LD is bonded on a submount chip which is referred to as the Chip-On-Submount-Assembly (COSA). COSA devices undergo burn-in and testing in COSA burn-in fixtures, which include a first non-conductive layer having through holes and a second conductive layer having first openings. The second conductive layer is disposed over the first non-conductive layer with each of the first openings overlaying one of the through holes. COSA burn-in fixtures also include a third non-conductive layer having second openings that are larger than the first openings. The third non-conductive layer is disposed over the second conductive layer with each of the second openings overlaying one of the first openings, which forms pockets with a seat on the conductive layer for disposing the LD with one electrode in contact with the conductive layer.
US09337610B2	Laser damage resistant optical components for alkali vapor laser cells A laser damage resistant optical component exposed to alkali vapor and intense (>1 kW/cm2) light is formed by making the outermost surface of the component from a specified metal oxide or metal fluoride whose metal boils at a temperature lower than the melting temperature of that metal's oxide or fluoride, such as BaO, CdO, CaO, MgO, SrO, ZnO, CdF2, MgF2 or SrF2. This allows the metal formed by the alkali's reduction of the metal compound to be vaporized and removed by the laser beam at a temperature that does not melt or deform the host compound or substrate. The alkali reduction of metal compounds, other than those listed above, leaves metals that are heated by the laser beam to a temperature above the melting point of the host compound and/or common substrates such as silica or alumina which can lead to their damage.
US09337609B2	Passively Q-switched element and passively Q-switched laser device Provided is a passively Q-switched element or the like, which enables mode selection without increasing the number of components in a resonator in a Q-switched pulse laser or the like that oscillates in a great number of high-order modes and which is also applicable to a waveguide type laser in which a mode cannot be controlled spatially. By combining a saturable absorber (2) with a transparent material (3) which is transparent to a laser oscillation wavelength or the like, a passively Q-switched element having a mode selection function and a passively Q-switched laser device in which a passively Q-switched element has a mode selection function, and a planar waveguide type passively Q-switched element and passively Q-switched laser device are provided.
US09337603B2	Ultra-short terahertz pulse generator having multiple foils This specification relates to a terahertz pulse generator capable of generating ultra-short terahertz pulses by use of electron beams transported through a plurality of foils. The plurality of foils in a shape of disc are arranged in an overlapped state and form a conical shape that diameters of the disc-shaped foils sequentially decrease along a direction that the electron beam is transported. Coherent radiation, which is generated as the ultra-short electron beam is transported through the foils in respective spaced gaps of the foils, is propagated toward the outside of the disc-shaped foils and gathered with forming a conical wave surface at edges of the disc-shaped foils. This may result in enhancement of generation efficiency of the terahertz waves.
US09337599B2	Carbon brush for fuel pump and method for manufacturing same A carbon brush for a fuel pump includes a brush body and a lead wire connected to the brush body, and the brush body has carbon and polyether ether ketone as main components. Abnormal wear does not occur even if a fuel pump motor is operated at a high voltage.
US09337597B2	Busbar connection system for use with a power distribution system, and electrical device including the busbar connection system The invention relates to an improved busbar connection system, an electrical device incorporating same, and an electrical system comprising at least one electrical device. Such a busbar connection system comprises for receiving and for electrically contacting at least two conductors of a busbar, and a signal connector for receiving and for electrically contacting a link module with a plurality of contact pads. The busbar connector has at least two, spaced apart, openings defined by an open cross-section along a mating direction that enable the busbar connector to partially surround, on opposite sides, each of the at least two conductors of the busbar. The signal connector has an opening defined by a closed cross-section along the mating direction that enables the signal connector to guide the link module into a contacting position for electrically contacting the plurality of contact pads.
US09337587B2	Electrical connectors The present invention discloses an electrical connector that includes a front zinc-alloy shell and a rear zinc-alloy shell. The front zinc-alloy shell and the rear zinc-alloy shell are made from die casting. The two shells are fitted tightly to provide shielding against electromagnetic interference. There is a cable plastic block with holding grooves to hold wires for electrical grounding and an isolation plate underneath the cable to provide electrical isolation. The holding grooves increase the connection strength of a connector cable. There is also a plastic block with an engagement hook. The engagement hook has a hook portion at one end and a curved fixing portion at the other end with an extending portion. The engagement hook provides an elastically supportive force. When a downward force is applied to the engagement hook, the curved fixing portion provides a counteracting force to press the extension portion against the front zinc-alloy shell.
US09337584B2	Patch cord having a plug contact with a signal injection point in its middle Patch cords are provided that include a communications cable that has at least first through fourth conductors and a plug that is attached to the cable. The plug includes a housing that receives the cable, a printed circuit board, first through fourth plug contacts, and first through fourth conductive paths that connect the first through fourth conductors to the respective first through fourth plug contacts. The first and second conductors, conductive paths, and plug contacts form a first differential transmission line, and the third and fourth conductors, conductive paths, and plug contacts form a second differential transmission line. Each of the first through fourth plug contacts has a first segment that extends longitudinally along a first surface of the printed circuit board, and the signal current injection point into the first segment of at least some of the first through fourth plug contacts is into middle portions of their respective first segments.
US09337579B2	Connector assembly having an improved latch member A cable connector assembly includes a connector and a cable. The connector includes: a housing including a mating portion and a body portion, a latch mechanism mounted on the housing, and a metal casing enclosing the housing. The body portion includes a receiving slot at a front end thereof and a post projecting upwardly. The latch mechanism includes a latch member received in the receiving slot and a pulling member coupled to the latch member. The latch member includes a locking portion extending beyond the body portion and above the mating portion, a holding portion held on the body portion, and a connecting portion. The connecting portion of the latch member includes a first opening mating with the post. The first opening extends from a middle line of the mating portion sidewardly to both sides of the mating portion.
US09337575B1	Electronic device including electronic card connector An electronic device includes a housing and a connector mounted in the housing. An open portion is defined in the housing. The connector includes a mounting portion coupled to the housing, a rotating member rotatably mounted to the mounting portion and a tray mounted in the open portion. The rotating member includes a magnet arranged to one end of the rotating arm and a resisting portion extending from the other end of the rotating arm. The magnet is adjacent to an inside surface of the housing, and the resisting portion resists against the tray. The magnet rotates the rotating member to partly push the tray out from the open portion. The electronic device has a good sealing ability.
US09337569B2	Fluid-tight contact implementation A fluid-tight contact implementation includes a plastic body and a flat contact(s). The plastic of the plastic body is composed of a non-shrinking, duroplastic material. The flat contact has a region encapsulated by the plastic body. The encapsulated region of the flat contact has a cross-sectional width which varies along an axial direction of the flat contact. Longitudinal edges of the encapsulated region of the flat contact along the axial direction are rounded.
US09337567B2	Seal for an electric terminal A sealed terminal housing includes a header that defines a terminal opening. An electric terminal extends through the terminal opening. The electric terminal includes a terminal stop. A terminal seal is located in the terminal opening and is compressed against the header and the electric terminal. A seal cap is also located in the terminal opening and engages the header and the terminal stop.
US09337566B2	Electrical connector assembly and mounting structure thereof An electrical connector assembly is disclosed having an electrical connector positionable over an opening in a wall to form an airtight seal and an electrical connection between the inside and an outside of the wall. The electrical connector has an insulating board made of insulating material. The insulating board includes a first surface facing the wall, a second surface on the side opposite to the first surface, and a side surface extending from a peripheral edge of the first surface to a peripheral edge of the second surface. An electrical connection portion made of electrically conductive material extends from the first surface through the insulating board to the second surface to electrically connect the first surface to the second surface. A surface roughness region provided at the peripheral edge of the first surface.
US09337563B2	Holder assembly for relay connector A holder assembly includes long terminals and a holder that includes long grooves in which the terminals are installed. Each of the long grooves is positioned between sidewalls which stand on both sides of the long groove. Each of the sidewalls includes engagement lock arms at a plurality of places arranged in a longitudinal direction of the long groove. Engagement claws are formed on each of the engagement lock arms.
US09337559B2	Printed circuit board, method of manufacturing the same and connection terminal A read wiring trace and a write wiring trace are formed on an insulating layer. Connection terminals made of conductor are connected to the read wiring trace and the write wiring trace, respectively. Each connection terminal has at least one corner with a radius of curvature of not larger than 35 μm.
US09337558B2	Connector rod assembly for AC inverter output An electrical system includes an alternating current (AC) connector rod assembly and a polyphase electric machine. The electric machine has a plurality of phase leads each electrically connected to the AC connector rod assembly. The assembly includes spaced AC connector rods each having a center axis. The assembly also includes insulating housings and a carrier plate defining through holes that receive and space the AC connector rods. The carrier plate defines features that engage mating features of the insulating housings while allowing each of the rods to rotate about its respective center axis within the carrier plate. A vehicle includes a direct current (DC) battery pack, a DC bus, an AC bus, a PIM that is electrically connected on a first side to the DC bus and on a second side to the AC bus, the AC connector rod assembly, a traction motor, and a transmission.
US09337549B2	Antenna module An antenna module mainly includes at least one antenna capable of radiating signals of two frequencies, a grounding portion, and at least one isolation metal sheet capable of isolating signals of a frequency generated by different antennas from each other to avoid interference. The antenna module is integrally formed, which can reduce the volume of the antenna module, and provide a stable radiation pattern and broadband and multi-band functions.
US09337547B2	Internal antenna having wideband characteristic An internal antenna having a wideband characteristic includes a printed circuit board, a first antenna unit fed with electricity from a feeding unit of the printed circuit board, and a second antenna unit spaced apart from the first antenna unit by a predetermined distance and indirectly fed with electricity by means of coupling to the first antenna unit, wherein the second antenna unit is indirectly fed with electricity with a phase difference from the first antenna unit due to an electric distance from a feeding point of the first antenna unit.
US09337544B2	Configurable backing structure for a reflector antenna and corrective synthesis for mechanical adjustment thereof A reflector support system is provided that includes a backing structure having a plurality of struts. The backing structure may have a plurality of hubs, each of the plurality of hubs may be configured to couple to two or more of the plurality of struts, each of the plurality of hubs may be configured to couple to another one of the plurality of hubs using one of the plurality of struts, each of the plurality of struts is configured to couple to at least two of the plurality of hubs. The backing structure may have a plurality of feet, each of the plurality of feet configured to couple to a corresponding one of the plurality of hubs, the plurality of feet are configured to couple to a reflector. In addition, a synthesis for mechanical adjustment of the reflector support system is provided.
US09337542B2	Modular gridded tapered slot antenna A planar antenna comprising: a substrate, a resonant element generating an electromagnetic wave, a plurality of parallel, spaced apart conductive strips on the substrate, wherein conductive strips form collinear rows of at least two strips that are physically separated by a slot to guide the electromagnetic wave in a specific direction.
US09337540B2	Ultra-wideband, low profile antenna An antenna system that includes a ground plane substrate, a first antenna, and a second antenna is provided. The first antenna includes a first loop conductor electrically connected to a feed network and to the ground plane substrate, a second loop conductor electrically connected to the feed network and to the ground plane substrate, and a first conductor mounted to and electrically connected to a first edge of the first loop conductor and to a second edge of the second loop conductor. The second antenna includes a third loop conductor electrically connected to the feed network and to the first conductor, a fourth loop conductor electrically connected to the feed network and to the first conductor, and a second conductor mounted to and electrically connected to a third edge of the third loop conductor and to a fourth edge of the fourth loop conductor.
US09337535B2	Low cost, high-performance, switched multi-feed steerable antenna system An apparatus for satellite communication may include a reflector configured to redirect electromagnetic energy. Each of multiple feeds may be positioned at a predetermined location with respect to the reflector. A feed-switching mechanism may be configured to selectively activate for use at least one of the multiple feeds. A steering mechanism may be configured to steer the reflector such that a focal point of the reflector approximately coincides with a position of an activated feed of the multiple feeds. The reflector may be mechanically independent of the plurality of feeds and the feed-switching mechanism.
US09337534B2	Method and device for radio reception using an antenna tuning apparatus and a plurality of antennas A receiver for radio communication comprises: four antennas; an antenna tuning apparatus for simultaneously tuning the four antennas, the antenna tuning apparatus comprising adjustable impedance devices, each of the adjustable impedance devices having a reactance at a frequency, the reactance of any one of the adjustable impedance devices being adjustable by electrical means; four single-input and single-output low-noise amplifiers; four analog processing and conversion circuits; a multiple-input signal processing device delivering a signal to a destination, the multiple-input signal processing device delivering a tuning instruction; a tuning control unit, the tuning control unit receiving the tuning instruction from the multiple-input signal processing device, the tuning control unit delivering tuning control signals to the antenna tuning apparatus as a function of the tuning instruction.
US09337533B2	Ground plane meandering in Z direction for spiral antenna An antenna has a spiral driven element that meanders in a z direction, perpendicular to the x-y plane of the spiral, and a ground plane that also meanders in the z direction, such that spacing between the ground plane and the driven element is an odd multiple of one-quarter wavelength, along at least a portion of the length of the driven element. The spacing promotes constructive interference from signals reflected by the ground plane, increasing the front-to-back ratio of the antenna and, thereby, providing gain. The ground plane of a wideband version of the spiral antenna meanders, such that the spacing varies between about an odd multiple of one-quarter wavelength of an upper frequency to about an odd multiple of one-quarter wavelength of a lower frequency of a frequency range, thereby providing gain over a range of frequencies.
US09337530B1	Cover for converting electromagnetic radiation in electronic devices Methods and apparatuses for capturing at least a portion of the radio frequency (“RF”) radiation emitted from an electronic device or other external sources and converting it into electric current that can be used for a number of different functional purposes including to drive a circuit that provides an indication when the RF radiation is captured and its relative intensity. One of the advantages of these techniques is that users can be protected from the potential harmful effects of long-term exposure to the RF radiation emitted from electronic devices, particularly for wireless phones which are often held in close proximity to a user's body. The indication can provide users with an indication that the circuit is redirecting the RF radiation away from their bodies and dissipating it as electrical energy.
US09337529B2	Portable terminal A portable terminal is described where the portable terminal includes a first frame body and a second frame body. The first frame body is used for an antenna unit of the portable terminal and a gap is set in a first partial area of the first frame body with the first partial area with a gap being set is covered by the second frame body.
US09337524B2	Fixing mechanism and antenna device therewith A fixing mechanism includes a shaft, a constraining member, a sleeve member, a resilient bushing, a pivot member and a handle. The constraining member is connected to an end portion of the shaft. The sleeve member sheathes the shaft. The resilient bushing sheathes the shaft and is disposed between the constraining member and the sleeve member. The pivot member is connected to the other end portion of the shaft. The handle is pivoted to the pivot member and abuts against the sleeve member. The handle pushes the sleeve member and drives the pivot member to activate the shaft to pull the constraining member when the handle pivots relative to the pivot member, so that the constraining member and the sleeve member cooperatively compress the resilient bushing, so as to make the resilient bushing generate a radial deformation.
US09337523B2	Digital camera A digital camera is capable of performing wireless communication with an external device. The digital camera includes a camera body and a lens barrel assembly mounted to the camera body and comprising a plurality of barrels for accommodating a plurality of photographing lenses, wherein at least one of the plurality of barrels is used as an antenna barrel configured as an antenna for the wireless communication, wherein the antenna barrel is formed from a metal material and comprises at least one slit filled with a dielectric material, so that the antenna barrel emits radio waves to perform the antenna function, and wherein an outer casing of the camera body, which surrounds an outer surface of the antenna barrel, is formed from a metal material so as to operate as a ground of the antenna barrel.
US09337522B2	Millimeter-wave system including a waveguide transition connected to a transmission line and surrounded by a plurality of vias According to an embodiment, a circuit board includes a signal line including at least portion of a first conductive layer that has a first portion extending over a cavity in the circuit board from a first side of the cavity. The circuit board also includes a first plurality of conductive vias surrounding the cavity and the first plurality of vias include at least one blind via disposed adjacent to the first side of the cavity.
US09337517B2	Solar powered cart A solar powered cart is provided with a cabinet including a plurality of drawers, a plurality of doors, and a plurality of wheels mounted under the cabinet; a pivotal solar photovoltaic panel disposed on the cabinet and being capable of converting energy of light directly into electricity; a plurality of rechargeable batteries disposed in the drawers and capable of storing the electricity supplied from the solar photovoltaic panel; a controller electrically connected to the rechargeable batteries and capable of regulating charging and discharging of the rechargeable batteries and protecting overload; a transformer electrically connected to the controller for outputting DC voltage or AC voltage; and an air compressor disposed in the cabinet and electrically connected to the transformer, the air compressor being configured to output pressurized air.
US09337514B2	Electropolymerization of a coating onto an electrode material Methods for reductively polymerizing vinylic based monomers from a solution thereof onto the surface of an electrode material, resulting in thin, electrically insulating solid-polymer electrolyte coatings strongly bound to the surface of the electrode material, are described. The strong bond permits a second electrode to be coated directly onto the solid-polymer electrolyte, thereby incorporating the required components for a Li-ion battery cell. At least one initiator species, which is readily reduced by accepting an electron from the electrode material, is included in electropolymerization deposition solution for permitting the polymerization of vinylic species that would otherwise not electrochemically polymerize without damage to either the electrode material or to the solvents employed.
US09337513B2	Non-aqueous electrolyte secondary battery A non-aqueous electrolyte secondary battery which is one example of an embodiment of the present disclosure is a non-aqueous electrolyte secondary battery including a non-aqueous electrolyte which contains a non-aqueous solvent. The non-aqueous solvent contains a fluoroethylene carbonate, a difluorobutylene carbonate, and at least one of a fluorinated chain carbonate and a fluorinated chain carboxylic acid ester, total volumetric contents of which is more than 50 percent with respect to the total volume of the non-aqueous solvent.
US09337512B2	Non-aqueous electrolyte for lithium secondary battery and lithium secondary battery comprising the same Disclosed is a non-aqueous electrolyte for a lithium secondary battery and a lithium secondary battery comprising the same. The non-aqueous electrolyte including a lithium salt and an organic solvent may further include, as an additive, (a) halogenated alkyl silane and (b) any one of (b-1) succinic anhydride, (b-2) (meth)acrylic acid ester of pentaerythritol or dipentaerythritol, and (b-3) mixtures thereof. The non-aqueous electrolyte for a lithium secondary battery may improve the high-temperature storage performance and the cycling performance.
US09337511B2	Nonaqueous secondary battery Disclosed is a nonaqueous secondary battery using a positive electrode containing a transition metal and lithium. The battery is prevented from deterioration due to elution of the transition metal from the positive electrode and thereby capable of maintaining small internal resistance and high electrical capacity even after high temperature storage or high-temperature charge and discharge cycles. The battery includes a negative electrode capable of intercalating and deintercalating lithium, a positive electrode containing a transition metal and lithium, and a nonaqueous electrolyte having a lithium salt dissolved in an organic solvent, the nonaqueous electrolyte containing a polycarboxylic ester compound represented by general formula (1) or (2).
US09337509B2	Solid electrolyte material, solid state battery, and method for producing solid electrolyte material A main object of the present invention is to provide a solid electrolyte material having excellent electron conductivity. The present invention solves the problem by providing the solid electrolyte material including: a solid electrolyte particle; and a carbon coating layer formed on a surface of the solid electrolyte particle.
US09337506B2	Fuel cell module A fuel cell module includes a first area where an exhaust gas combustor and a start-up combustor are provided, an annular second area disposed around the first area where a heat exchanger is provided, an annular third area disposed around the second area where a reformer is provided, and an annular fourth area disposed around the third area where an evaporator is provided. The fuel cell module includes a first partition plate having first combustion gas holes, a second partition plate having second combustion gas holes, and a third partition plate having third combustion gas holes.
US09337504B2	Fuel cell system and fuel cell status detection method A fuel cell system (100) is provided with a voltage detection device (41) that detects a cell voltage of a cell group containing one or more cells (11), a current density detection device (42) that detects a generated current density of the cell group, and a determination portion (52) that determines the presence or absence of an inflection point of a change in the cell voltage relative to the generated current density based on the detection results of the voltage detection device and the current density detection device.
US09337503B2	Fuel cell power control by offset estimation A system and method for managing power flow in a fuel cell vehicle. The method provides a difference between a power limit signal and an actual power signal to a PI controller to generate a power offset signal. The method determines whether a fuel cell stack is able to provide enough power to satisfy a power request, and if so, adds the power request and the power offset signal to generate a stack power request signal to cause the upper power limit signal to move towards and be matched to the actual power signal. If the stack is not able to provide enough power to satisfy the load power request signal, the method subtracts the power offset signal from the power limit signal to provide a load limit signal to cause the actual stack power signal to move towards and be matched to the upper power limit signal.
US09337501B2	Hydrogen-generating fuel cell cartridges The present application is directed to a gas-generating apparatus and various pressure regulators or pressure-regulating valves. Hydrogen is generated within the gas-generating apparatus and is transported to a fuel cell. The transportation of a first fuel component to a second fuel component to generate of hydrogen occurs automatically depending on the pressure of a reaction chamber within the gas-generating apparatus. The pressure regulators and flow orifices are provided to regulate the hydrogen pressure and to minimize the fluctuation in pressure of the hydrogen received by the fuel cell. Connecting valves to connect the gas-generating apparatus to the fuel cell are also provided.
US09337499B2	Dual electrolyte fuel cell assembly A fuel cell assembly in which one or more dual cell modules is created by “sandwiching” a first reactant chamber between two electrolyte assemblies and enclosing the result within a surrounding vessel containing the second reactant. Each dual cell module thereby contains two operating electrolyte assemblies. In such a configuration separate electrical conductors must be provided to create the proper connections. In order to avoid the resistance losses inherent in the use of edge connections, the present invention preferably includes conductors that actually pass through the electrolytes. These conductors are contained within an assembly that electrically insulates the conductor where needed and provides a gas-tight seal where needed.
US09337494B2	Ionic layer with oxygen evolution reaction catalyst for electrode protection A fuel cell includes a first electrode and a second electrode with an ion conducting polymer membrane positioned between these electrodes. The fuel cell further comprises a first OER catalyst-containing ionic layer positioned between the first electrode and the ion conducting polymer membrane. The first OER catalyst-containing layer includes an OER catalyst-containing compound, an ion conducting polymer and carbon. Characteristically, the weight ratio of ion conducting polymer to carbon is from about 10 to about 100. A method for forming the fuel cell is also provided.
US09337486B2	Spinel-type lithium-manganese composite oxide Provided is a novel spinel-type lithium-manganese composite oxide, allowing gas generation amount to be limited for a gas generated via a reaction with an electrolytic solution. Proposed is a spinel-type lithium-manganese composite oxide, wherein, when the spinel-type lithium-manganese composite oxide is placed in an ion-exchanged water at 20° C., stirred for 10 minutes, then, left to stand undisturbed for 2 minutes, separated into a supernatant and a precipitate and recovered, with respect to the “16d-site-to-32e-site inter-atomic distance (100%)” of the spinel-type lithium-manganese composite oxide contained in the precipitate measured by the Rietveld method using the fundamental method, proportionally, the “16d-site-to-32e-site inter-atomic distance” of the spinel-type lithium-manganese composite oxide contained in the supernatant is less than 101.5%.
US09337484B2	Electrodes having a state of charge marker for battery systems One embodiment includes a battery cell electrode having a first material constructed and arranged to be charged and discharged and having a first potential versus state of charge relationship; a second material having a second potential versus state of charge relationship; wherein said second material is constructed and arranged to become active to transfer ions at a selected state of charge level to produce an observable change in measured potential from said first to said second potential versus relationship, and wherein the amount of the second material ranges from about 2 to about 30 weight percent of the battery cell electrode.
US09337483B2	Pasted nickel hydroxide electrode and additives for rechargeable alkaline batteries A pasted positive nickel hydroxide electrode for use in battery cells (e.g., in nickel zinc cells, and nickel metal hydride cells) includes nickel hydroxide particles, a cobalt metal and/or cobalt compound and a sulfur-containing complexing agent capable of forming a complex with cobalt. The presence of the sulfur-containing complexing agent, such as dialkyldithiocarbamate (e.g., sodium diethyldithiocarbamate) improves lifetime and capacity utilization of the nickel electrode. The resulting pasted nickel hydroxide electrode includes a CoOOH conductive matrix after formation. The surface of the nickel hydroxide particles in the electrode is modified in some embodiments by providing a cobalt-containing coating onto the surface of the nickel hydroxide particles, followed by oxidation with a strong oxidizing agent. The complexing agent can be added before, after, or during the oxidation.
US09337482B2	Composite nitride, method of preparing the same, electrode active material including the composite nitride, electrode including the electrode active material, and lithium secondary battery including the electrode A composite nitride, a method of preparing the composite nitride, an electrode active material including the composite nitride, an electrode including the electrode active material, and a lithium secondary battery including the electrode, the composite nitride including a core material including a bronze-phase titanium oxide; and a nitrogen atom doped on at least part of the core material.
US09337480B2	Anode mixture, button cell with an anode comprising metal particles, and production thereof A method of producing a button cell having an anode including metal particles, including providing an anode mixture including as constituents metal particles, at least one binder, at least one conducting agent and, optionally, a gassing inhibitor, providing a button cell housing, introducing the mixture into the button cell housing, admixing the mixture with an electrolyte, and liquid-tight sealing of the housing, wherein the constituents of the mixture are contacted in the presence of water prior to introduction into the housing, and after the contacting the water is removed from the mixture at least partially.
US09337479B2	Nonaqueous electrolyte secondary battery [Problem] To provide a nonaqueous electrolyte secondary battery exhibiting superior stability characteristics and having charge/discharge characteristics exhibiting a high-rate discharge stroke, even when a lithium-nickel-cobalt manganate and a spinel-type lithium manganate are used as the positive electrode active material. [Solution] A mixture having a specific ratio of a tungsten- and zirconium-modified lithium-nickel-cobalt manganate and a spinel-type lithium manganate is used as the positive electrode active material. Furthermore, a nonaqueous electrolyte having a specific ratio of the content of dimethyl carbonate and the content of a cyclic carbonate is used.
US09337477B2	Lithium secondary battery electrode including coated layer having acrylic copolymer chemically bonded to binder of active material layer and manufacturing process for the same To provide a lithium ion secondary battery electrode in which a coated layer is held on a surface of an active material layer over a long period of time to suppress decomposition of the electrolysis solution and to enhance the cyclability, a manufacturing process for the same, and a lithium ion secondary battery using the electrode. A lithium ion secondary battery electrode includes a current collector, an active material layer containing a binder formed on a surface of the current collector, and a coated layer formed on the surface of at least a part of the active material layer, wherein the coated layer is an acrylic type copolymer cured substance including an acrylic type main chain and a side chain having polyester or polyether graft-polymerized to the acrylic type main chain and the coated layer is chemically bonded with the binder.
US09337476B2	Lithium sulfide-carbon complex, process for producing the complex, and lithium ion secondary battery utilizing the complex The present invention provides a process for producing a lithium sulfide-carbon composite, the process comprising placing a mixture of lithium sulfide and a carbon material having a specific surface area of 60 m2/g or more in an electrically-conductive mold in a non-oxidizing atmosphere, and applying a pulsed direct current to the mold while pressurizing the mixture in a non-oxidizing atmosphere, thereby subjecting the lithium sulfide and the carbon material to heating reaction; and a lithium sulfide-carbon composite obtained by this process, the composite having a carbon content of 15 to 70 weight %, and a tap density of 0.4 g/cm3 or more when the carbon content is 30 weight % or more, or a tap density of 0.5 g/cm3 or more when the carbon content is less than 30 weight %. The present invention can improve the electronic conductivity of lithium sulfide, which is expected to be put into practical use as a high-capacity positive electrode active material, so as to further enhance the performance of lithium sulfide as a positive electrode active material for lithium ion secondary batteries.
US09337473B2	Positive electrode active material, positive electrode for nonaqueous electrolyte battery, and nonaqueous electrolyte battery The present invention provides a nonaqueous electrolyte battery that exhibits high energy density and excellent cycle characteristics, as well as a cathode for use in such a battery, and a cathode active material for use in such a cathode. The cathode active material of the present invention has a composition represented by the formula (1) and a crystallite size in the (110) plane of not smaller than 85 nm: LixCo1-y-zNbyMzO2 (1) wherein M stands for at least one element selected from Mg, Y, rare earth elements, Ti, Zr, Hf, V, Ta, Cr, Mo, W, Mn, Fe, Ni, Cu, Zn, B, Al, Ga, C, Si, Sn, N, S, F, and Cl; and 0.9≦x≦1.1, 0.0002≦y≦0.01, and 0≦z≦0.05.
US09337468B2	Secondary battery Provided is a secondary battery including an electrode assembly, a case accommodating the electrode assembly, and a cap assembly, including a cap plate having a short-circuit hole, configured to seal the case. The secondary battery includes a first connection plate at an exterior surface of the case and coupled to the electrode assembly, a capacitive member between the first connection plate and the cap plate, and a short-circuit unit including an inversion plate positioned in the short-circuit hole, and a second connection plate at an exterior side surface of the case spaced apart from the cap plate and extending over at least a portion of the short-circuit hole, the second connection plate being coupled to the electrode assembly.
US09337467B2	Electrical bypass element, in particular for storage cells of an energy storage device An electrical bypass element, suitable for bypassing defective storage cells in energy storage devices includes two electrical conductors between which is formed a layer sequence with at least one electrical insulation layer and one or more reactive layer stacks, in which an exothermic reaction can be triggered. The reactive layer stacks and the insulation layer are matched to one another such that the insulation layer disintegrates as a result of the thermal energy released during the exothermic reaction and an electrical connection is produced between the electrical conductors. The electrical bypass element can be actively triggered even before the ultimate failure of a storage cell so that higher power losses in the energy storage device can be avoided.
US09337466B2	Power terminal connector A power terminal connector includes a flexible conductor having a first mounting portion, a second mounting portion and a flexible section between the first and second mounting portions. The first mounting portion is terminated directly to a power terminal of a first battery module. A female terminal is coupled to the second mounting portion. The female terminal has a terminal body having a receptacle receiving a power terminal of a second battery module. The terminal body is terminated to the second mounting portion to mechanically and electrically connect the terminal body to the flexible conductor. A contact spring is received in the receptacle and is electrically connected to the terminal body. The contact spring has spring beams defining interfaces for the power terminal to create a power path to the power terminal of the second battery module.
US09337461B2	Composite porous membrane and method of producing the same A composite porous membrane is a composite porous membrane, wherein a porous membrane B including a heat-resistant resin is laminated on the surface of a polypropylene resin of an outermost layer of a porous membrane A composed of at least one layer, wherein at least one of the outermost layers comprises the polypropylene resin. The composite porous membrane satisfies a particular range of peeling strength at the interface between the porous membrane A and the porous membrane B and a particular range of difference between air resistance of the whole composite porous membrane and air resistance of the porous membrane A, provided that the porous membrane A satisfies a particular range of average pore size and porosity.
US09337460B2	Battery module A battery module includes a cell unit, a first end plate, and a binding band. The cell unit includes a plurality of battery cells arranged in a first direction. The first end plate is located on one side of the cell unit in the first direction. The binding band extends in the first direction and is coupled with the first plate so as to bind the first end plate and the cell unit. The first end plate has an external terminal surface directed to an opposite side with respect to the cell unit in the first direction. An external terminal is connected to the external terminal surface. The binding band is located on a side surface of the cell unit and is coupled with the external terminal surface.
US09337457B2	Battery assembly with cooling A battery assembly has a structure that can effectively cool batteries. A battery assembly according to an exemplary embodiment of the present invention includes a housing, a first battery pack in the housing, and a second battery pack in the housing, the second battery pack being spaced from the first battery pack with a first flow path therebetween, wherein a second flow path is between the battery packs and an inner surface of the housing.
US09337448B2	Organic light emitting display An organic light emitting display includes an array substrate, a plurality of light emitting devices disposed over the array substrate, and a plurality of color filters having different colors. The plurality of light emitting devices include a first light emitting device configured to emit light having a first color and a second light emitting device configured to emit light having a second color different from the first color, and the plurality of color filters include first and second color filters disposed over the first light emitting device and the second light emitting device, respectively.
US09337446B2	Encapsulated RGB OLEDs having enhanced optical output Methods of making an integrated barrier stack and optical enhancement layer for protecting and improving the light out coupling of an encapsulated OLED are described. The method includes optimizing the thickness of various layers including the initial inorganic barrier layer and the inorganic barrier layer and polymeric decoupling layer for the barrier stack. The thickness is optimized for at least one of maximum efficiency, minimum dispersion, or minimum spectral shift so that the encapsulated OLED has enhanced light outcoupling compared to the bare OLED.
US09337445B2	Organic light-emitting display apparatus and method of manufacturing the same Provided is an organic light-emitting display apparatus. The organic light-emitting display apparatus includes a substrate, an organic light-emitting unit formed on the substrate and including a stacked structure of a first electrode, an intermediate layer, and a second electrode, an organic layer formed on the organic light-emitting unit, a first adhesion promoting layer formed on the organic layer, and a first inorganic layer formed on the adhesion promoting layer and including a low temperature viscosity transition (LVT) inorganic material.
US09337443B1	OLED device, packaging method thereof and display device A packaging method for an OLED device, including: opening at least one through hole in a cover plate in a region between the region for forming glass cement and the region for applying UV glue; regulating the pressure in a cell-assembling chamber to a first pressure, and cell-assembling a back plate with the cover plate placed on a base board in the cell-assembling chamber with the first pressure lower than the atmospheric pressure; regulating the pressure in the cell-assembling chamber to the atmospheric pressure; curing the UV glue; regulating the pressure in the cell-assembling chamber to a second pressure that is lower than the atmospheric pressure and higher than the first pressure and detaching the cover plate from the base board; and sealing the through hole in the cover plate; and sintering the glass cement.
US09337439B2	Pixel, organic light emitting display including the pixel, and method of driving the same In an organic light emitting display including a pixel, and a method of driving the same, the pixel includes an organic light emitting diode (OLED), a storage capacitor coupled between a first power supply and a first node, a first transistor for controlling a current that flows from the first power supply to a second power supply through the OLED in response to a voltage applied to the first node, a second transistor coupled between a data line and a first electrode of the first transistor and turned on when a control signal is supplied through a control line, a third transistor coupled between the first node and a second electrode of the first transistor and turned on when a scan signal is supplied through an nth (n is a natural number) scan line, and a fourth transistor coupled between an initializing power supply and the first node and turned on when the scan signal is supplied through an (n−1)th scan line.
US09337438B2	Light-emitting element, light-emitting device, and electronic device In a light-emitting element including an EL layer between a pair of electrodes, a structure is formed in which the EL layer includes at least a first layer having a hole-injecting property (a hole-injecting layer) and a second layer having a hole-transporting property (a hole-transporting layer) between the electrode functioning as an anode and a third layer having a light-emitting property (a light-emitting layer), and the absolute value of the highest occupied molecular orbital level (HOMO level) of the second layer is larger than that of the first layer, so that the injection amount of holes from the electrode side which functions as an anode is suppressed, and thus luminous efficiency of the light-emitting element is increased.
US09337437B2	Photoelectric conversion element and imaging device A photoelectric conversion element is formed by laminating, in order, a substrate, a lower electrode, an organic layer which generates electric charge by light irradiation, an upper electrode which transmits light, a buffer layer and a protective film. The buffer layer is formed from hydrogenated silicon oxide containing hydrogen ions, and has a thickness of 1 to 100 nm. The protective film contains hydrogenated silicon nitride containing hydrogen ions or hydrogenated silicon oxynitride containing hydrogen ions and has a thickness of 30 to 500 nm.
US09337435B2	Dye sensitized solar cell A dye sensitized solar cell, wherein a compacting compound whose molecular structure comprises a terminal group, a hydrophobic part and an anchoring group is co-adsorbed together with the dye on the semi-conductive metal oxide layer of the photoanode, forming a dense mixed self-assembled monolayer.
US09337429B2	Organic electronic material, ink composition, and organic electronic element Provided is an organic electronic material which is excellent in storage stability in the case as an ink composition, and able to prepare, at a high yield, an organic electronic element capable of reducing the driving voltage and of being driven stably for a long period of time, and an ink composition including the organic electronic material. The organic electronic material is characterized in that it contains at least an ionic compound represented by the following general formula (1), and a compound including a charge transporting unit, and the ink composition including the material. In the general formula (1), Ra to Rc each independently represent a hydrogen atom (H), an alkyl group, or a benzyl group. A represents an anion.
US09337428B2	Donor mask and method of manufacturing organic light emitting display apparatus using the same A method of manufacturing an organic light emitting display apparatus using a donor mask. The donor mask includes a base substrate, a light to heat conversion layer provided on the base substrate, and a reflection layer disposed between the base substrate and the light to heat conversion layer and comprising a through hole corresponding to a first transfer region, a non-transfer region having a first thickness and a second transfer region having a second thickness smaller than the first thickness, and the organic light emitting display apparatus using the same.
US09337425B2	Method of manufacturing resistance change layer using irradiation of electron beam and resistive random access memory device using the same Methods of manufacturing a resistance change layer and a resistive random access memory device are provided. The method of manufacturing a resistance change layer includes forming a preliminary resistance change layer including an oxide semiconductor material on a substrate and irradiating the preliminary resistance change layer with an electron beam to a predetermined depth. On a path along which the electron beam is irradiated, a composition ratio of the resistance change layer changes in a direction in which a density of oxygen vacancies of the oxide semiconductor material increases. Accordingly, the composition ratio of a resistance change layer is easily controlled using electron beam irradiation. In addition, since interfacial surface roughness and internal defect structures of an oxide semiconductor are controlled by electron beam irradiation, a resistance change ratio is improved and thereby device characteristics can be improved.
US09337417B2	Magnetic random access memory with perpendicular interfacial anisotropy The present invention is directed to an MRAM element comprising a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween. The magnetic free layer structure has a variable magnetization direction substantially perpendicular to the layer plane thereof. The magnetic reference layer structure includes a first magnetic reference layer formed adjacent to the insulating tunnel junction layer and a second magnetic reference layer separated from the first magnetic reference layer by a first non-magnetic perpendicular enhancement layer. The first and second magnetic reference layers have a first fixed magnetization direction substantially perpendicular to the layer plane thereof. The second magnetic reference layer has a multilayer structure comprising a first magnetic reference sublayer formed adjacent to the first non-magnetic perpendicular enhancement layer and a second magnetic reference sublayer separated from the first magnetic reference sublayer by an intermediate metallic layer.
US09337410B2	Multilayer piezoelectric element An element body having a first and second internal electrodes exposure surface comprising a piezoelectric active area, wherein a first internal electrode faces a second internal electrode sandwiching piezoelectric body layer in-between along laminating direction, and a piezoelectric inactive area, wherein the piezoelectric body layer contacts only first or second internal electrode at one face along laminating direction, or the first internal electrodes or the second internal electrodes respectively face each other sandwiching piezoelectric body layer in-between along laminating direction, an insulating layer which covers the piezoelectric active area of the first and second internal electrodes exposure surface, and a resistance layer which is isolated from the piezoelectric active area by the insulating layer, placed at the first and second internal electrodes exposure surface connecting at least a part of the first and that of the second internal electrode in the piezoelectric inactive area and has lower electrical resistance value relative to that of the piezoelectric body layer.
US09337409B2	Thermoelectric conversion module A thermal stress of electrode members (121 to 123) due to an operation temperature may be relaxed by thermal stress relaxation layers (141 to 144), and thus peeling of the electrode members (121 to 123) due to thermal stress at the operation temperature may be prevented in a satisfactory manner. Furthermore, diffusion of a constituent component of the thermoelectric conversion members (111 and 112) due to the operation temperature and the like may be prevented by diffusion prevention layers (151 to 154), and thus durability and stability of the thermoelectric conversion module (100) may be improved.
US09337408B2	Light-emitting diode device A light-emitting diode device has a first carrier and at least one light-emitting diode chip, which is arranged on the first carrier. The first carrier has at least one first and one second carrier part, wherein the light-emitting diode chip rests only on the first carrier part. Furthermore, the first and second carrier parts each have a thermal conductivity. The thermal conductivity of the first carrier part is at least 1.5 times the thermal conductivity of the second carrier part. The first carrier part is surrounded laterally by the second carrier part.
US09337406B2	GaN-based light emitting diode with current spreading structure A GaN-based LED with a current spreading structure, the LED including a substrate, a light-emitting epitaxial layer over the substrate, and a current spreading structure over the light-emitting epitaxial layer. The current spreading structure includes a transparent electrode spreading bar, and a metal electrode spreading bar attached to the side wall of the transparent electrode spreading bar. The current spreading structure can improve the current spreading effect, reducing or eliminating of electrode shading, improving luminous efficiency of the LED, and avoid or reduce high voltage (Vf).
US09337402B2	Method for manufacturing semiconductor light emitting device The method for manufacturing the semiconductor light emitting device includes steps of forming a plurality of semiconductor light emitting element regions on a substrate, forming a recess portion between the plurality of semiconductor light emitting element regions on a surface of the substrate, disposing a light reflective sealing resin on the substrate to cover the plurality of semiconductor light emitting element regions with the sealing resin and to fill the recess portion with a part of the sealing resin that covers the plurality of semiconductor light emitting element regions, removing the substrate, disposing a light transmissive resin on surfaces of the plurality of semiconductor light emitting element regions where the substrate has been removed, and dividing the plurality of semiconductor light emitting element regions into individual pieces, wherein the recess portion includes a first recess portion and one or more second recess portions shallower than the first recess portion.
US09337397B2	Radiation-emitting semiconductor device A radiation-emitting semiconductor device includes a chip connection region, a radiation-emitting semiconductor chip, and a light-absorbing material, wherein the radiation-emitting semiconductor chip is fixed to the chip connection region, the chip connection region is covered with the light-absorbing material at selected locations at which said chip connection region is not covered by the radiation-emitting semiconductor chip, and the radiation-emitting semiconductor chip is free of the light-absorbing material in locations.
US09337387B2	Emitting device with improved extraction A profiled surface for improving the propagation of radiation through an interface is provided. The profiled surface includes a set of large roughness components providing a first variation of the profiled surface having a characteristic scale approximately an order of magnitude larger than a target wavelength of the radiation. The set of large roughness components can include a series of truncated shapes. The profiled surface also includes a set of small roughness components superimposed on the set of large roughness components and providing a second variation of the profiled surface having a characteristic scale on the order of the target wavelength of the radiation.
US09337386B2	Light emitting device package A light emitting device package is provided. The light emitting device includes: a substrate; a light emitting device disposed at one side of the substrate; and a formation layer formed on the substrate and having a slope at an edge portion of the formation layer.
US09337384B2	Light-emitting diode and fabrication method thereof A light-emitting diode includes a substrate; a light-emitting epitaxial layer, laminated by semiconductor material layers and formed over the substrate; a first current spreading layer over the light-emitting epitaxial layer; an adhesive layer with alternating second current spreading layers and first metal barrier layers over the first current spreading layer, including three structure layers; a second metal barrier layer over the adhesive layer with alternating second current spreading layers and metal barrier layers; and a metal electrode layer over the second metal barrier layer.
US09337383B2	Light emitting device Disclosed is a light emitting device including a first conductive type semiconductor layer; a second conductive type semiconductor layer disposed on the first conductive type semiconductor layer; and an active layer disposed between the first conductive type semiconductor layer and the second conductive type semiconductor layer, the active layer comprising quantum well layers and quantum barrier layers, wherein each of the quantum well barrier layers comprises first barrier layers and a second barrier layer disposed between the first barrier layers, and an energy bandgaps of the second barrier layer is larger than energy bandgaps of the quantum well layers and smaller than energy bandgaps of the first barrier layers.
US09337380B2	Method for fabricating heterojunction interdigitated back contact photovoltaic cells The disclosed technology generally relates photovoltaic devices, and more particularly to methods of fabricating heterojunction interdigitated back contact photovoltaic cells having interdigitated emitter regions and back surface field regions. In one aspect, a method of forming on a substrate a patterned n+ a-Si:H layer and a patterned p+ a-Si:H layer, the patterned n+ a-Si:H layer and the patterned p+ a-Si:H layer being interdigitated and electrically isolated from each other, the method comprising: forming a patterned p+ a-Si:H layer on the substrate, the patterned p+ a-Si:H layer covering first regions of the substrate surface and leaving second regions of the substrate surface exposed; depositing a first intrinsic a-Si:H layer on the substrate; depositing an n+ a-Si:H layer on the first intrinsic a-Si:H layer; providing a patterned masking layer covering the n+ a-Si:H layer at least in the second regions; and selectively removing the n+ a-Si:H layer and the first intrinsic a-Si:H layer in regions not covered by the masking layer and stopping at an underlying portion of the p+ a-Si:H layer substantially without removing a substantial amount of the underlying portion of the p+ a-Si:H layer, wherein selectively removing the n+ a-Si:H layer and the first intrinsic a-Si:H layer comprises etching in a solution comprising a diluted TMAH solution.
US09337373B2	Light-guide solar module, method of fabrication thereof, and panel made therefrom A photovoltaic light guide solar concentration apparatus has a deflecting layer, a light-guide layer optically coupled to the deflecting layer, a secondary optic and a photovoltaic cell. The photovoltaic concentration apparatus has a central optical axis that, in operation, is parallel to incident sunlight. A deflecting layer includes a plurality of focusing elements symmetrically arranged with respect to the central optical axis. The light-guide layer is optically coupled to the plurality of focusing elements of the deflecting layer. The light-guide layer has a reflective surface and a plurality of opposite facets symmetrically arranged with respect to the central axis and focused sunlight from the deflection layer enters the light-guide layer and is directed and trapped by the reflective surface and the opposite facets and guided inside the light-guide layer towards an exit aperture through total internal reflections. A secondary optic is coaxially located with respect to the central optical axis and is coupled to the light guide layer the secondary optic that has at least one reflective surface. The secondary optic redirects the light towards the exit aperture. A photovoltaic cell is located at the exit aperture and on the central axis to receive sunlight from the secondary optic within an acceptance angle relative to the central axis.
US09337372B2	Photovoltaic device A photovoltaic device may be provided having a semiconductor substrate, an i-type amorphous layer or an i-type amorphous layer formed over a front surface or a back surface of the semiconductor substrate, and a p-type amorphous layer or an n-type amorphous layer formed over the i-type amorphous layer or the i-type amorphous layer. The i-type amorphous layer or the i-type amorphous layer has an oxygen concentration profile in which a concentration is reduced in a step-shape from a region near an interface with the semiconductor substrate and along a thickness direction.
US09337370B2	Apparatus and method for the automatic assembly of photovoltaic panels Apparatus and method for the automatic assembly of photovoltaic panels with back-contact architecture, the apparatus comprising a series of six stations that are configured in sequence in a carousel with recirculation of trays and a control device, which is adjacent to one or more of the stations, for controlling the correctness of the processes performed, the control device enabling the processing or the mere transit of the tray into the subsequent station by comparing the actual state with a predefined state. If one or more of the controls performed in the transfers between the six stations yields a negative outcome regarding the correctness of the operation performed previously, the control device enables the mere transit of the tray with its content to the subsequent stations until it reaches the first station without undergoing any tipping.
US09337366B2	Textured optoelectronic devices and associated methods of manufacture Textured optoelectronic devices and associated methods of manufacture are disclosed herein. In several embodiments, a method of manufacturing a solid state optoelectronic device can include forming a conductive transparent texturing material on a substrate. The method can further include forming a transparent conductive material on the texturing material. Upon heating the device, the texturing material causes the conductive material to grow a plurality of protuberances. The protuberances can improve current spreading and light extraction from the device.
US09337363B2	Low resistance, low reflection, and low cost contact grids for photovoltaic cells The instant disclosure relates to contact grids for use in photovoltaic cells, wherein a cross-section of the contact grid fingers is shaped as a trapezoid, as well as a method of making photovoltaic cells comprising these contact grids. The contact grids of the instant disclosure are cost effective and, due to their thick metal grids, exhibit minimum resistance. Despite having thick metal grids, the unique shape of the contact grid fingers of the instant disclosure allow the photovoltaic cells in which they are employed to retain more solar energy than traditional solar cells by reflecting incoming solar energy back onto the surface of the solar cell instead of reflecting this energy away from the cell.
US09337362B2	Conductive composition and conductive feature formed at low temperatures A method for forming a conductive feature. The method includes providing a substrate and providing a conductive composition. The conductive composition includes metal particles, a non-acid protic solvent, and a high polarity solvent. The non-acid protic solvent and high polarity solvent are present in concentrations sufficient to ionize the non-acid protic solvent and remove oxides when heated. The method further includes heating the composition to a temperature less than about 250° C. to form a conductive feature having less than about ten times the resistivity of bulk copper.
US09337346B2	Array substrate and method of fabricating the same An array substrate for an electronic display includes a substrate; a gate electrode on the substrate; a gate insulating layer on the gate electrode; an oxide semiconductor layer on the gate insulating layer; a source electrode and a drain electrode on the oxide semiconductor layer; a silicide layer on the source and drain electrodes; and a first passivation layer on the source electrode and the drain electrode. The array substrate and fabrication method thereof prevent degradation of a thin-film transistor (TFT) used in driving pixels of the electronic display.
US09337343B2	Semiconductor device, driver circuit, and display device To provide a semiconductor device having a high aperture ratio and including a capacitor with a high charge capacitance. To provide a semiconductor device with a narrow bezel. A transistor over a substrate; a first conductive film over a surface over which a gate electrode of the transistor is provided; a second conductive film over a surface over which a pair of electrodes of the transistor is provided; and a first light-transmitting conductive film electrically connected to the first conductive film and the second conductive film are included. The second conductive film overlaps the first conductive film with a gate insulating film of the transistor laid between the second conductive film and the first conductive film.
US09337339B1	Metal oxide semiconductor device and method for forming the same The present invention provides a metal oxide semiconductor (MOS) device, comprising a gate structure and an epitaxial structure. The gate structure is disposed on a substrate. The epitaxial structure is disposed in the substrate at two sides of the gate structure and apart thereof serves a source/drain of the MOS, wherein the epitaxial structure comprises: a first buffer layer with a second conductive type, a second buffer layer, and an epitaxial layer with a first conductive type complementary to the second conductive type. The present invention further provides a method of forming the same.
US09337338B2	Tucked active region without dummy poly for performance boost and variation reduction In one embodiment, a semiconductor device is provided that includes a semiconductor substrate including an active region and at least one trench isolation region at a perimeter of the active region, and a functional gate structure present on a portion of the active region of the semiconductor substrate. Embedded semiconductor regions are present in the active region of the semiconductor substrate on opposing sides of the portion of the active region that the functional gate structure is present on. A portion of the active region of the semiconductor substrate separates the outermost edge of the embedded semiconductor regions from the at least one isolation region. Methods of forming the aforementioned device are also provided.
US09337336B2	Replacement metal gates to enhance tranistor strain Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain.
US09337332B2	III-Nitride insulating-gate transistors with passivation A field-effect transistor (FET) includes a plurality of semiconductor layers, a source electrode and a drain electrode contacting one of the semiconductor layers, a first dielectric layer on a portion of a top semiconductor surface between the source and drain electrodes, a first trench extending through the first dielectric layer and having a bottom located on a top surface or within one of the semiconductor layers, a second dielectric layer lining the first trench and covering a portion of the first dielectric layer, a third dielectric layer over the semiconductor layers, the first dielectric layer, and the second dielectric layer, a second trench extending through the third dielectric layer and having a bottom located in the first trench on the second dielectric layer and extending over a portion of the second dielectric, and a gate electrode filling the second trench.
US09337326B2	Compound semiconductor device and method for fabricating the same A first GaN layer (2), a first AlGaN layer (3), a second GaN layer (4) and a third GaN layer (5) are formed in layers on a substrate (1). A second AlGaN layer (6) is formed on the sidewall of an opening (10A) formed in the multilayer structure. A gate electrode (8) is formed to fill an electrode trench (7a) in an insulating film (7). A portion (7c) of the insulating film (7) between the gate electrode (8) and the second AlGaN layer (6) functions as a gate insulating film. A source electrode (11) is formed above the gate electrode (8) and a drain electrode (12) is formed below the gate electrode (8). This configuration enables implementation of a miniatuarizable, reliable vertical HEMT that has a sufficiently high withstand voltage and high output power and is capable of a normally-off operation without problems that could otherwise result from the use of a p-type compound semiconductor.
US09337324B2	Bipolar transistor, band-gap reference circuit and virtual ground reference circuit The present invention provides a bipolar transistor, a method for forming the bipolar transistor, a method for turning on the bipolar transistor, and a band-gap reference circuit, virtual ground reference circuit and double band-gap reference circuit with the bipolar transistor. The bipolar transistor includes: a Silicon-On-Insulator wafer; a base area, an emitter area and a collector area; a base area gate dielectric layer on a top silicon layer and atop the base area; a base area control-gate on the base area gate dielectric layer; an emitter electrode connected to the emitter area via a first contact; a collector electrode connected to the collector area via a second contact; and a base area control-gate electrode connected to the base area control-gate via a third contact. Processes of forming the bipolar transistor are fully compatible with traditional standard CMOS processes; and the base current to turn on the bipolar transistor is based on the GIDL current and formed by applying a voltage to the base area control-gate electrode without any need of contact to the base.
US09337316B2	Method for FinFET device Provided is a method of forming a fin field effect transistor (FinFET). The method includes forming a fin on a substrate, the fin having a channel region therein. The method further includes forming a gate structure engaging the fin adjacent to the channel region and forming a spacer on sidewalls of the gate structure. The method further includes forming two recesses in the fin adjacent to the spacer and on opposite sides of the gate structure and epitaxially growing a solid phase diffusion (SPD) layer in the two recesses, the SPD layer containing a high concentration of a dopant. The method further includes performing an annealing process thereby diffusing the dopant into the fin underneath the spacer and forming lightly doped source/drain (LDD) regions therein. The LDD regions have substantially uniform dopant concentration on top and sidewalls of the fin.
US09337312B2	Method for system for manufacturing TFT, TFT, and array substrate The method for manufacturing the TFT includes: forming a semiconductor film, a doped semiconductor film, a source/drain electrode film, and a first patterned photoresist layer sequentially; performing first etching to remove the source/drain electrode film on a region that is not covered by the first patterned photoresist layer; performing second etching to remove the doped semiconductor film and the semiconductor film on a region that is not covered by the first patterned photoresist layer; performing ashing treatment on the photoresist layer to remove the photoresist layer on the channel region; hard-baking the photoresist layer after the ashing treatment; performing third etching to remove the source/drain electrode film on a region that is not covered by the photoresist layer; and performing fourth etching to remove the doped semiconductor film on the region that is not covered by the photoresist layer.
US09337309B1	Reducing direct source-to-drain tunneling in field effect transistors with low effective mass channels An approach to providing a barrier in a vertical field effect transistor with low effective mass channel materials wherein the forming of the barrier includes forming a first source/drain contact on a semiconductor substrate and forming a channel with a first channel layer on the first source/drain contact. The approach further includes forming the barrier on the first channel layer, and a second channel layer on the barrier followed by forming a second source/drain contact on the second channel layer.
US09337307B2	Method for fabricating transistor with thinned channel A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
US09337306B2	Multi-phase source/drain/gate spacer-epi formation Approaches for forming an epitaxial (epi) source/drain (S/D) and/or a semiconductor device having an epi S/D are provided. In embodiments of the invention, a first portion of the epi S/D is formed in the S/D region on a fin in a finned substrate. After the first portion is formed, but before completion of the formation of the S/D, a secondary spacer is formed in the S/D region. Then, the remainder portion of the S/D is formed in the S/D region. As a result, the S/D is separated from the gate stack by the secondary spacer.
US09337303B2	Metal gate stack having TiAICN as work function layer and/or blocking/wetting layer A metal gate stack having a titanium aluminum carbon nitride (TiAlCN) as a work function layer and/or a multi-function blocking/wetting layer, and methods of manufacturing the same, are disclosed. In an example, an integrated circuit device includes a semiconductor substrate and a gate stack disposed over the semiconductor substrate. The gate stack includes a gate dielectric layer disposed over the semiconductor substrate, a multi-function blocking/wetting layer disposed over the gate dielectric layer, wherein the multi-function blocking/wetting layer includes TiAlCN, a work function layer disposed over the multi-function blocking/wetting layer, and a conductive layer disposed over the work function layer.
US09337302B2	On-SOI integrated circuit comprising a subjacent protection transistor An integrated circuit features a FET, an UTBOX layer plumb with the FET, an underlayer ground plane with first doping plumb with the FET's gate and channel, first and second underlayer semiconducting elements, both plumb with the drain or source, electrodes in contact respectively with the ground plane and with the first element, one having first doping and being connected to a first voltage, the other having the first doping and connected to a second bias voltage different from the first, a semiconducting well having the second doping and plumb with the first ground plane and both elements, a first trench isolating the first FET from other components of the integrated circuit and extending through the layer into the well, and second and third trenches isolating the FET from the electrodes, and extending to a depth less than a plane/well interface.
US09337300B2	Nitride-based semiconductor device A semiconductor device according to an embodiment includes a nitride semiconductor layer, a gate electrode provided above the nitride semiconductor layer, a source electrode provided above the nitride semiconductor layer, a drain electrode provided above the nitride semiconductor layer at a side opposite to the source electrode with respect to the gate electrode, a first silicon nitride film provided above the nitride semiconductor layer between the drain electrode and the gate electrode, and a second silicon nitride film provided between the nitride semiconductor layer and the gate electrode, an atomic ratio of silicon to nitrogen in the second silicon nitride film being lower than an atomic ratio of silicon to nitrogen in the first silicon nitride film.
US09337299B2	Bi-directional ESD diode structure with ultra-low capacitance that consumes a small amount of silicon real estate A bi-directional electrostatic discharge diode structure consumes substantially less silicon real estate and provides ultra-low capacitance by utilizing a p− epitaxial layer that touches and lies between an n+ lower epitaxial layer and an n+ upper epitaxial layer. A metal contact touches and lies over a p+ layer, which touches and lies over the n+ upper epitaxial layer.
US09337298B2	Silicon carbide semiconductor device and method for producing the same In a method for producing an SiC semiconductor device, a p type layer is formed in a trench by epitaxially growing, and is then left only on a bottom portion and ends of the trench by hydrogen etching, thereby to form a p type SiC layer. Thus, the p type SiC layer can be formed without depending on diagonal ion implantation. Since it is not necessary to separately perform the diagonal ion implantation, it is less likely that a production process will be complicated due to transferring into an ion implantation apparatus, and thus manufacturing costs reduce. Since there is no damage due to a defect caused by the ion implantation, it is possible to reduce a drain leakage and to reliably restrict the p type SiC layer from remaining on the side surface of the trench.
US09337296B2	Integrated circuits having a metal gate structure and methods for fabricating the same Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming an interfacial layer material over a semiconductor substrate and forming a gate insulation layer over the interfacial layer material that includes a combination of a layer of a hafnium oxide material and a layer of hafnium silicate material. The layer of the hafnium silicate material includes less than about 40 % of an overall height of the gate insulation layer.
US09337295B2	Semiconductor devices and methods of manufacturing the same Semiconductor devices and methods of manufacturing the same are disclosed. The semiconductor device a gate dielectric pattern on a substrate and a gate electrode on the gate dielectric pattern opposite the substrate. The gate electrode includes a first conductive pattern disposed on the gate dielectric pattern and including aluminum, and a second conductive pattern disposed between the first conductive pattern and the gate dielectric pattern. The second conductive pattern has an aluminum concentration that is higher than an aluminum concentration of the first conductive pattern. The second conductive pattern may be thicker than the first conductive pattern.
US09337285B2	Contact structure of semiconductor device The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a cavity below the major surface; a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; a Ge-containing dielectric layer over the strained material; and a metal layer over the Ge-containing dielectric layer.
US09337284B2	Closed cell lateral MOSFET using silicide source and body regions A closed cell lateral MOSFET device includes minimally sized source/body contacts formed in one or more source cells with silicided source and body diffusion regions formed therein. In this manner, the cell pitch of the cellular transistor array is kept small while the ruggedness of the transistor is ensured. In other embodiments, a closed cell lateral MOSFET device is formed using silicided source and body diffusion regions and self-aligned contacts or borderless contacts as the source/body contacts. The polysilicon gate mesh can be formed using minimum polysilicon-to-polysilicon spacing to minimize the cell pitch of the cellular transistor array.
US09337283B2	Semiconductor device with field plate A semiconductor device includes a first semiconductor layer, a second semiconductor layer of a second conductivity type formed on the first semiconductor layer, a first electrode which extends in a first direction and is surrounded by the first semiconductor layer except at one end thereof, and a first insulation film which is formed between the first semiconductor layer and the first electrode. A film thickness of the first insulation film between the other end of the first electrode in a second direction opposite to the first direction and the first semiconductor layer includes a thickness that is greater than a thickness of the first insulation film along a side surface of the first electrode. The semiconductor device also includes a second electrode which faces the second semiconductor layer, and a second insulation film which is formed between the second electrode and the second semiconductor layer.
US09337282B2	Semiconductor device with point defect region doped with transition metal A simplified manufacturing process stably produces a semiconductor device with high electrical characteristics, wherein platinum acts as an acceptor. Plasma treatment damages the surface of an oxide film formed on a n− type drift layer deposited on an n+ type semiconductor substrate. The oxide film is patterned to have tapered ends. Two proton irradiations are carried out on the n− type drift layer with the oxide film as a mask to form a point defect region in the vicinity of the surface of the n− type drift layer. Silica paste containing 1% by weight platinum is applied to an exposed region of the n− type drift layer surface not covered with the oxide film. Heat treatment inverts the vicinity of the surface of the n− type drift layer to p-type by platinum atoms which are acceptors. A p-type inversion enhancement region forms a p-type anode region.
US09337277B2	High voltage power semiconductor device on SiC 4H SIC epiwafers with thickness of 50-100 μm are grown on 4° off-axis substrates. Surface morphological defect density in the range of 2-6 cm−2 is obtained from inspection of the epiwafers. Consistent carrier lifetime in the range of 2-3 μs has been obtained on these epiwafers. Very low BPD density has been confirmed in the epiwafers with BPD density down to below 10 cm−2. Epitaxial wafers with thickness of 50-100 μm have been used to fabricate diodes. High voltage testing has demonstrated blocking voltages near the theoretical values for 4H-SiC. Blocking voltage as high as 8 kV has been achieved in devices fabricated on 50 μm thick epitaxial films, and blocking voltage as high as 10 kV has been obtained in devices fabricated on 80 μm thick films. Failure analysis confirmed triangle defects, which form from surface damage or particles present during epitaxy, are killer defects and cause the device to fail in reverse bias operation. In addition, the leakage current at the high blocking voltages of the JBS diodes showed no correlation with the screw dislocation density. It is also observed that the main source of basal plane dislocations in the epilayer originates in the crystal growth process.
US09337275B2	Electrical contact for graphene part An electrical or electronic device is disclosed. In some embodiments, an electrical device includes a single-layer graphene part extending in a lateral direction and a multi-layer graphene structure laterally contacting the single-layer graphene part. The electrical or electronic device further includes a graphite part in contact with a surface of the multi-layer graphene structure. In other embodiments, an electrical device includes a graphene part extending in a lateral direction and a graphite part is configured to provide a lateral contact for the graphene part.
US09337270B2	Semiconductor device A semiconductor device includes at least one field effect transistor structure, which is formed on a semiconductor substrate. The field effect transistor structure includes a drift region, a body region, a source region and a gate. The source region and the drift region include at least mainly a first conductivity type, wherein the body region includes at least mainly a second conductivity type. The body region includes at least one low doping dose portion extending from the drift region to at least one of the source region or an electrical contact interface of the body region at a main surface of the semiconductor substrate, wherein a doping dose within the low doping dose portion of the body region is less than 3 times a breakdown charge.
US09337266B2	Methods and apparatuses including an active area of a tap intersected by a boundary of a well Apparatuses and methods are disclosed. One such apparatus includes a well having a first type of conductivity formed within a semiconductor structure having a second type of conductivity. A boundary of the well intersects an active area of a tap to the well.
US09337265B2	Compound semiconductor structure A semiconductor structure comprises a substrate comprising a first crystalline semiconductor material, a dielectric layer, above the substrate, defining an opening, a second crystalline semiconductor material at least partially filling the opening, and a crystalline interlayer between the substrate and the second crystalline semiconductor material. The first crystalline semiconductor material and the second crystalline semiconductor material are lattice mismatched, and the crystalline interlayer comprises an oxygen compound. A method for fabricating semiconductor structure comprises the steps of providing a substrate including a first crystalline semiconductor material, patterning an opening in a dielectric layer above the substrate, the opening having a bottom, forming a crystalline interlayer on the substrate at least partially covering the bottom, and growing a second crystalline semiconductor material on the crystalline interlayer thereby at least partially filling the opening. The crystalline semiconductor materials are lattice mismatched, and the crystalline interlayer comprises an oxygen compound.
US09337264B2	Process for forming a surrounding gate for a nanowire using a sacrificial patternable dielectric Techniques for defining a damascene gate in nanowire FET devices are provided. In one aspect, a method of fabricating a FET device is provided including the following steps. A SOI wafer is provided having a SOI layer over a BOX. Nanowires and pads are patterned in the SOI layer in a ladder-like configuration. The BOX is recessed under the nanowires. A patternable dielectric dummy gate(s) is formed over the recessed BOX and surrounding a portion of each of the nanowires. A CMP stop layer is deposited over the dummy gate(s) and the source and drain regions. A dielectric film is deposited over the CMP stop layer. The dielectric film is planarized using CMP to expose the dummy gate(s). The dummy gate(s) is at least partially removed so as to release the nanowires in a channel region. The dummy gate(s) is replaced with a gate conductor material.
US09337260B2	Shallow trench isolation in bulk substrate The semiconductor structure includes a plurality of first insulators in a substrate, a common insulating layer surrounding the sidewall and the bottom of said first insulators in said substrate, and suspended portions of said substrate on said common insulating layer.
US09337255B1	Reducing direct source-to-drain tunneling in field effect transistors with low effective mass channels An approach to providing a barrier in a vertical field effect transistor with low effective mass channel materials wherein the forming of the barrier includes forming a first source/drain contact on a semiconductor substrate and forming a channel with a first channel layer on the first source/drain contact. The approach further includes forming the barrier on the first channel layer, and a second channel layer on the barrier followed by forming a second source/drain contact on the second channel layer.
US09337254B1	Integrated FinFET capacitor A technique relates to forming a semiconductor device. A field-effect transistor structure having a substrate, a fin structure patterned in the substrate, a gate stack structure, and an insulator layer is first provided. A non-capacitor region and a capacitor region are then formed on the field-effect transistor structure by masking portions of the field-effect transistor structure with a mask such that a non-capacitor region is masked and a capacitor region is exposed, and etching the insulator layer to further recess the fin structure and gate stack structure within the capacitor region such that a revealed height of the fins within the capacitor region is increased relative to the revealed height of the fins in the non-capacitor region. A high-k layer can be deposited over the recessed fins and gate stack structures and a gate metal can fill the recessed portions therein.
US09337252B1	Method for making semiconductor device with stacked analog components in back end of line (BEOL) regions A method for making a semiconductor device may include forming a first dielectric layer above a semiconductor substrate, forming a first trench in the first dielectric layer, filling the first trench with electrically conductive material, removing upper portions of the electrically conductive material to define a lower conductive member with a recess thereabove, forming a filler dielectric material in the recess to define a second trench. The method may further include filling the second trench with electrically conductive material to define an upper conductive member, forming a second dielectric layer over the first dielectric layer and upper conductive member, forming a first via through the second dielectric layer and underlying filler dielectric material to the lower conductive member, and forming a second via through the second dielectric layer to the upper conductive member.
US09337251B2	Integrated magnetic core inductors with interleaved windings A coupled inductor topology for a thin-film magnetic core power inductor that enables efficient integrated power conversion. Coupled magnetic core inductors with interleaved windings inductors comprise magnetic films and partially or fully interleaved conductors. Methods described herein are suitable for integration into monolithic, chip stacking fabrication or other traditional semiconductor device fabrication techniques and equipment. Soft ferromagnetic materials exhibiting high permeability and low coercivity are deposited using thin-film techniques. A plurality of electrical conductors surround at least one ferromagnetic core giving rise to two or more windings. Windings are coupled to one another through magnetic core(s). Windings are used to control permeability, inductance and magnetic saturation, finding particular utility in high magnetic flux applications.
US09337246B2	Organic light emitting display device and method of manufacturing the same using a solution process An organic light emitting display device includes a substrate in which a first pixel area and a second pixel area different from each other are defined, a first electrode, a pixel defining layer, a common layer, a first surface processing layer, a second surface processing layer, a first liquid solution layer, a second liquid solution layer, and a second electrode. The first surface processing layer has a first width and is correspondingly included in the first pixel area. The second surface processing layer has a second width different from the first width and is correspondingly included in the second pixel area. The first liquid solution layer has the first width, and the second liquid solution layer has the second width. The first and second liquid solution layers have the same volume and different thicknesses.
US09337244B2	Light-emitting device and electronic device using light-emitting device Provided is a highly reliable light-emitting device in which a light-emitting element is prevented from being damaged when external physical force is applied. The light-emitting device includes a light-emitting element formed over a first substrate, including a first electrode layer, a light-emitting layer, and a second electrode layer; a structure body formed over the first substrate; a second substrate provided to face the first substrate; and a bonding layer provided between the first substrate and the second substrate. The light-emitting layer is separated by the structure body. By strengthening adhesion between the structure body and the bonding layer, or between the structure body and the second electrode, the highly reliable light-emitting device in which damage of the light-emitting element is prevented can be provided.
US09337239B2	Electronic device having flash memory array formed in at different level than variable resistance memory cells An electronic device includes a memory. The memory includes a first cell array including a plurality of flash memory cells, a first peripheral circuit suitable for controlling the first cell array, a second cell array including a plurality of variable resistance memory cells, and a second peripheral circuit suitable for controlling the second cell array. The first cell array, the first peripheral circuit, and the second peripheral circuit are formed at a first level over a surface of a semiconductor substrate, and the second cell array is disposed at a second level over the surface of a semiconductor substrate, the second level being higher than the first level. A portion of the second cell array overlaps in a plan view the second peripheral circuit and/or the first cell array.
US09337234B2	Photoelectric converter, photoelectric converter array and imaging device A photoelectric converter includes a first pn junction comprised of at least two semiconductor regions of different conductivity types, and a first field-effect transistor including a first source connected with one of the semiconductor regions, a first drain, a first insulated gate and a same conductivity type channel as that of the one of the semiconductor regions. The first drain is supplied with a second potential at which the first pn junction becomes zero-biased or reverse-biased relative to a potential of the other of the semiconductor regions. When the first source turns to a first potential and the one of the semiconductor regions becomes zero-biased or reverse-biased relative to the other semiconductor regions, the first pn junction is controlled not to be biased by a deep forward voltage by supplying a first gate potential to the first insulated gate, even when either of the semiconductor regions is exposed to light.
US09337233B1	Photodiode array for imaging applications Embodiments of a photodiode array are provided herein. In some embodiments, a photodiode array may include a semiconductor layer configured to convert photons into analog electrical signals; and a passive layer having a first surface and a second surface disposed opposite the first surface, wherein the semiconductor layer is coupled to the first surface, and wherein the passive layer is configured to have a signal receiving component coupled directly to the second surface of the passive layer.
US09337231B2	Solid state image sensor with plural overlapping photoelectric conversion units A solid-state image sensor includes: four or more photoelectric conversion units having spectral sensitivity characteristics different from one another; an amplifier unit disposed in correspondence to each group of photoelectric conversion units among N groups (N represents an integer less than a quantity of the four or more photoelectric conversion units and equal to or greater than one), the four or more photoelectric conversion units being divided into the N groups; and transfer units, each disposed in correspondence to one of the four or more photoelectric conversion units, which transfer a signal generated at the photoelectric conversion unit to the amplifier unit disposed for the group to which the photoelectric conversion unit belongs.
US09337230B2	Solid-state imaging device with suppression of color mixture, manufacturing method thereof, and electronic apparatus A solid-state imaging device having a backside illuminated structure, includes: a pixel region in which pixels each having a photoelectric conversion portion and a plurality of pixel transistors are arranged in a two-dimensional matrix; an element isolation region isolating the pixels which is provided in the pixel region and which includes a semiconductor layer provided in a trench by an epitaxial growth; and a light receiving surface at a rear surface side of a semiconductor substrate which is opposite to a multilayer wiring layer.
US09337228B2	Stack chip package image sensor An image sensor cell is divided into two chips, and a capacitor for noise reduction is formed in a bottom wafer in correspondence with a unit pixel of a top wafer in a stack chip package image sensor having a coupling structure of the two chips, so that noise characteristics of the image sensor are improved. A stack chip package image sensor includes: a first semiconductor chip that includes a photodiode, a transmission transistor, and a first conductive pad and outputs image charge, which is output from the photodiode, through the first conductive pad; and a second semiconductor chip that includes a drive transistor, a selection transistor, a reset transistor, and a second conductive pad and supplies a corresponding pixel with an output voltage corresponding to the image charge received from the first semiconductor chip through the second conductive pad. The second semiconductor chip includes a capacitor for noise reduction.
US09337220B2	Solar blind ultra violet (UV) detector and fabrication methods of the same Described herein is device configured to be a solar-blind UV detector comprising a substrate; a plurality of pixels; a plurality of nanowires in each of the plurality of pixel, wherein the plurality of nanowires extend essentially perpendicularly from the substrate.
US09337219B1	Method for manufacturing flexible display device Disclosed is a method for manufacturing a flexible display device. The method includes: providing a substrate, the substrate having a first surface and the second surface opposite to each other; forming a first flexible substrate on the first surface of the substrate and forming the second flexible substrate on the second surface of the substrate in such a way that a force acting from the first flexible substrate to the substrate is equal to, but in opposite direction, a force acting from the second substrate to the substrate; forming a displaying component on a surface of the first flexible substrate that is distant from the substrate; and peeling the first flexible substrate on which the displaying component is formed off the substrate so as to form a flexible display device. The flexible display device manufactured with the method has an enhanced quality.
US09337218B2	Liquid crystal display device and manufacturing method thereof In the liquid crystal display device in which a guest-host liquid crystal layer is provided between a first substrate having a reflective film which is a pixel electrode layer (also referred to as a first electrode layer) and a second substrate having a common electrode layer (also referred to as a second electrode layer), the reflective film which is a pixel electrode layer is projected into the liquid crystal layer, and a micron-sized first unevenness and a nano-sized second unevenness on the first unevenness are provided.
US09337210B2	Vertical ferroelectric field effect transistor constructions, constructions comprising a pair of vertical ferroelectric field effect transistors, vertical strings of ferroelectric field effect transistors, and vertical strings of laterally opposing pairs of vertical ferroelectric field effect transistors A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating core and has a lateral wall thickness of 1 monolayer to 7 monolayers. A ferroelectric gate dielectric material encircles the transition metal dichalcogenide material. Conductive gate material encircles the ferroelectric gate dielectric material. The transition metal dichalcogenide material extends elevationally inward and elevationally outward of the conductive gate material. A conductive contact is directly against a lateral outer sidewall of the transition metal dichalcogenide material that is a) elevationally inward of the conductive gate material, or b) elevationally outward of the conductive gate material. Additional embodiments are disclosed.
US09337206B2	Semiconductor device, related manufacturing method, and related electronic device A method for manufacturing a semiconductor device may include the following steps: providing a composite structure that includes a gate material layer, a first mask material layer, and a sacrificial layer; partially removing, through a first mask, the sacrificial layer to form a sacrificial members; providing a second mask material layer on the sacrificial members; partially removing the second mask material layer to form mask units that contact sides of the sacrificial members; removing the sacrificial members; providing a third mask material layer between two of the mask units for forming a second mask; partially removing, through the second mask, the first mask material layer to form a third mask; and partially removing, through the third mask, the gate material layer to form a control gate and a select gate.
US09337205B2	Butted contact shape to improve SRAM leakage current The present disclosure relates to an SRAM memory cell. The SRAM memory cell has a semiconductor substrate with an active area and a gate region positioned above the active area. A butted contact extends from a position above the active area to a position above the gate region. The butted contact contains a plurality of distinct regions having different widths (i.e., the smaller dimensions of the butted contact), such that a region spanning the active area and gate region has width less than the regions in contact with the active area or gate region. By making the width of the region spanning the active area and gate region smaller than the regions in contact with the active area or gate, the etch rate is reduced at a junction of the gate region with the active area, thereby preventing etch back of the gate material and leakage current.
US09337201B2	Memory cells, arrays of memory cells, and methods of forming memory cells A memory cell includes a vertically oriented transistor having an elevationally outer source/drain region, an elevationally inner source/drain region, and a channel region elevationally between the inner and outer source/drain regions. The inner source/drain region has opposing laterally outer sides. One of a pair of data/sense lines is electrically coupled to and against one of the outer sides of the inner source/drain region. The other of the pair of data/sense lines is electrically coupled to and against the other of the outer sides of the inner source/drain region. An access gate line is elevationally outward of the pair of electrically coupled data/sense lines and is operatively adjacent the channel region. A charge storage device is electrically coupled to the outer source/drain region. Other embodiments and additional aspects, including methods, are disclosed.
US09337200B2	Dynamic random access memory cell employing trenches located between lengthwise edges of semiconductor fins After formation of semiconductor fins in an upper portion of a bulk semiconductor substrate, a shallow trench isolation layer is formed, which includes a dielectric material and laterally surround lower portions of each semiconductor fin. Trenches are formed between lengthwise sidewalls of neighboring pairs of semiconductor fins. Portions of the shallow trench isolation layer laterally surrounding each trench provide electrical isolation between the buried plate and access transistors. A strap structure can be formed by etching a via cavity overlying a portion of each trench and a source region of the corresponding access transistor, and filling the via cavity with a conductive material. A trench top oxide structure electrically isolates an inner electrode of each trench capacitor from an overlying gate line for the access fin field effect transistor.
US09337199B2	Semiconductor device and method of fabricating the same A semiconductor device may include a substrate having a first region and a second region on a surface thereof, and a first semiconductor fin on the first region of the substrate with the first semiconductor fin including a first trench therethrough. A first gate electrode may be provided in the first trench, and first and second source/drain regions may be provided in the first semiconductor fin, with the first gate electrode between the first and second source/drain regions. A second semiconductor fin may be provided on the second region of the substrate with the second semiconductor fin including a second trench therethrough, a second gate electrode may be provided in the second trench, and third and fourth source/drain regions may be provided in the second semiconductor fin with the second gate electrode being between the third and fourth source/drain regions.
US09337198B2	Semiconductor device and method of manufacturing the same A semiconductor memory device includes a first substrate on which a cell region is defined. In the cell region, memory cells are stacked. A second substrate is located above the first substrate, and a peripheral region is defined on the second substrate. One or more conductive lines are located in the peripheral region. The one or more lines extend through the second substrate and couple to the cell region.
US09337196B2	III-V FinFET CMOS with III-V and germanium-containing channel closely spaced Closely spaced III-V compound semiconductor fins and germanium-containing semiconductor fins are provided by utilizing mandrel structures for III-V compound semiconductor material epitaxial growth and subsequent fin formation. Mandrel structures are formed on a semiconductor material stack that includes an uppermost layer of a relaxed germanium-containing material layer. A hard mask portion is formed on a pFET device region of the semiconductor material stack, and then recessed regions are provided in the relaxed germanium-containing material layer of the material stack semiconductor and in an nFET device region. An III-V compound semiconductor material plug is then formed in each recessed region. First sacrificial spacers are formed adjacent the sidewalls of each mandrel structures, and then each mandrel structure is removed. III-V compound semiconductor fins and germanium-containing semiconductor fins are then formed in the different device regions utilizing each first sacrificial spacer as an etch mask.
US09337195B2	Semiconductor devices and methods of manufacture thereof Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes providing a workpiece including a gate dielectric and a gate disposed over the gate dielectric, and reshaping a top surface of the gate to form a gate with a rounded profile.
US09337194B2	Semiconductor device and method of forming the same A semiconductor device includes a first NMOS device with a first threshold voltage and a second NMOS device with a second threshold voltage. The first NMOS device includes a first gate structure over a semiconductor substrate, first source/drain (S/D) regions in the semiconductor substrate and adjacent to opposite edges of the first gate structure. The first S/D regions are free of dislocation. The second NMOS device includes a second gate structure over the semiconductor substrate, second S/D regions in the semiconductor substrate and adjacent to opposite edges of the second gate structure, and a dislocation in the second S/D regions.
US09337193B2	Semiconductor device with epitaxial structures A semiconductor device includes at least two fin-shaped structures, a gate structure, at least two epitaxial structures and a cap. The fin-shaped structures are disposed on a substrate and are covered by the gate structure. The epitaxial structures spaced apart from each other are disposed at one side of the gate structure and respectively directly contact each fin-shaped structure. The cap simultaneously surrounds the epitaxial structures, and at least two adjacent caps are merged together.
US09337191B2	Display device and electronic device A transistor whose channel region includes an oxide semiconductor is used as a pull down transistor. The band gap of the oxide semiconductor is 2.0 eV or more, preferably 2.5 eV or more, more preferably 3.0 eV or more. Thus, hot carrier degradation in the transistor can be suppressed. Accordingly, the circuit size of the semiconductor device including the pull down transistor can be made small. Further, a gate of a pull up transistor is made to be in a floating state by switching of on/off of the transistor whose channel region includes an oxide semiconductor. Note that when the oxide semiconductor is highly purified, the off-state current of the transistor can be 1 aA/μm (1×10−18 A/μm) or less. Therefore, the drive capability of the semiconductor device can be improved.
US09337190B2	Semiconductor device including dummy isolation gate structure and method of fabricating thereof A device having a first active transistor, a second active transistor, an isolation gate structure, and an active region underlying each of the first active transistor, the second active transistor, and the isolation gate structure is provided. The first and second active transistors each have a metal gate with a first type of conductivity (e.g., one of n-type and p-type). The isolation gate structure interposes the first and second active transistors. The isolation gate structure has a metal gate with a second type of conductivity (e.g., the other one of n-type and p-type). A method of fabricating devices such as this are also described.
US09337185B2	Semiconductor devices A semiconductor device includes a first doping region extending from a main surface of a semiconductor substrate into the semiconductor substrate. Further, the semiconductor device includes a second doping region arranged adjacent to the first doping region. The first doping region includes at least one low doping dose portion extending from the main surface of the semiconductor substrate to the second doping region. A doping dose within the low doping dose portion of the first doping region is less than 3 times a breakdown charge. Additionally, the semiconductor device includes a first electrode structure in contact with the first doping region at the main surface of the semiconductor substrate. The work function of the first electrode structure at the main surface of the semiconductor substrate is larger than 4.9 eV or lower than 4.4 eV.
US09337184B2	Display device and electronic device including the same It is an object to decrease the number of transistors connected to a capacitor. In a structure, a capacitor and one transistor are included, one electrode of the capacitor is connected to a wiring, and the other electrode of the capacitor is connected to a gate of the transistor. Since a clock signal is input to the wiring, the clock signal is input to the gate of the transistor through the capacitor. Then, on/off of the transistor is controlled by a signal which synchronizes with the clock signal, so that a period when the transistor is on and a period when the transistor is off are repeated. In this manner, deterioration of the transistor can be suppressed.
US09337181B2	Semiconductor device and method of manufacturing same A semiconductor device includes a substrate, a first trough structure and a second trough structure. The first trough structure which is in the substrate includes a first conductive layer, a first doping layer and a first insulation layer, which is placed between the first conductive layer and the first doping layer. The second trough structure which is in the substrate and separated from the first trough structure by a separation part of the substrate includes a second conductive layer and a second insulation layer. A first contact connects the first doping layer, a second contact connects the separation part, and a third contact connects the second conductive layer. The separation part forms a resistor, coupled between the first contact and the second contact, and the substrate, the second insulation layer and the second conductive layer together form a capacitor, coupled between the second contact and the third contact.
US09337179B2	Electrostatic discharge protection circuit An electrostatic discharge (ESD) protection circuit includes a substrate, a semiconductor layer provided on the substrate to have a first conductivity type, a first well provided in a first region of the semiconductor layer to have a second conductivity type, an insulating pattern provided in the first well to cross the first well, and first and second doped regions provided in an upper portion of the first well to have the first conductivity type. The first and second doped regions may be laterally spaced apart from each other with the insulating pattern interposed therebetween.
US09337169B2	Environmentally-assisted technique for transferring devices onto non-conventional substrates A device fabrication method includes: (1) providing a growth substrate including an oxide layer; (2) forming a metal layer over the oxide layer; (3) forming a stack of device layers over the metal layer; (4) performing fluid-assisted interfacial debonding of the metal layer to separate the stack of device layers and the metal layer from the growth substrate; and (5) affixing the stack of device layers to a target substrate.
US09337167B2	Wire bonding method employing two scrub settings A method of attaching bond wires to bond pads on an active surface of a semiconductor die, where the bond pads are disposed along four side edges of the die, and have aluminum top layers. The method includes attaching first bond wires to first bond pads on first and second opposing sides of the die using a first group of settings and attaching second bond wires to the bond pads on third and fourth sides of the die that oppose each other and are adjacent the first and second sides, using a second group of settings. The first and second groups of settings include first and second scrub settings that are different from each other. Employing two separate scrub settings allows for reduced splashing of the aluminum cap layer on the die pad from splashing onto passivation edges of the bond pads.
US09337161B2	Integrated circuit package system with removable backing element having plated terminal leads and method of manufacture thereof A method of manufacture of an integrated circuit package system includes: attaching a first die to a first die pad; connecting electrically a second die to the first die through a die interconnect positioned between the first die and the second die; connecting a first lead adjacent the first die pad to the first die; connecting a second lead to the second die, the second lead opposing the first lead and adjacent the second die; and providing a molding material around the first die, the second die, the die interconnect, the first lead and the second lead, with a portion of the first lead exposed.
US09337159B2	Semiconductor package with integrated microwave component A semiconductor device package includes an encapsulant and a semiconductor chip. The semiconductor chip is at least partly embedded in the encapsulant. A microwave component including at least one electrically conducting wall structure is integrated in the encapsulant. Further, the semiconductor device package includes an electrical interconnect configured to electrically couple the microwave component to the semiconductor chip.
US09337155B2	Semiconductor component with moisture barrier for sealing semiconductor body A semiconductor component includes a semiconductor body having a top side and a bottom side opposite the top side. A top metallization is applied to the top side and a bottom metallization is applied to the bottom side. A moisture barrier completely seals the semiconductor body in cooperation with the top metallization and the bottom metallization.
US09337151B2	Semiconductor device Provided is a semiconductor device. The semiconductor device includes a semiconductor substrate having a contact region. An interlayer insulating layer is disposed on the semiconductor substrate. A lower contact plug passing through the interlayer insulating layer and electrically connected to the contact region is disposed. An interconnection structure is disposed on the interlayer insulating layer. An adjacent interconnection spaced apart from the interconnection structure is disposed on the interlayer insulating layer. A bottom surface of the interconnection structure includes a first part overlapping a part of an upper surface of the lower contact plug, and a second part overlapping the interlayer insulating layer.
US09337150B2	Semiconductor devices including supporting patterns in gap regions between conductive patterns An integrated circuit device includes spaced apart conductive patterns on a substrate surface, and a supporting pattern on the substrate surface between adjacent ones of the conductive patterns and separated therefrom by respective gap regions. The adjacent ones of the conductive patterns extend away from the substrate surface beyond a surface of the supporting pattern therebetween. A capping layer is provided on respective surfaces of the conductive patterns and the surface of the supporting pattern. Related fabrication methods are also discussed.
US09337147B2	Semiconductor device and a method of manufacturing the same and designing the same A semiconductor device includes grooves defining an active region, including a MISFET, and dummy regions. A first interlayer insulation film is formed over the MISFET, the active region and the dummy regions. A first wiring, and first and second dummy wirings are formed over the first interlayer insulation film. A second interlayer insulation film is formed over the first wiring and the dummy wirings. The second dummy wirings are arranged between the first wiring and the first dummy wirings, and the pitch of the first dummy wirings is larger than that of the second dummy wirings. In planar view, the first and second dummy wirings are arranged over the dummy regions, and the size of each of the first dummy wirings is larger than size of each of the second dummy wirings. The first wiring and the first and second dummy wirings are formed of copper as a major component.
US09337144B2	E-fuse structure with methods of fusing the same and monitoring material leakage The present disclosure generally provides for an e-fuse structure and corresponding method for fusing the same and monitoring material leakage. The e-fuse structure can include a metal dummy structure and an electrical fuse link substantially aligned with a portion of the metal dummy structure, wherein the metal dummy structure cools at least part of the electrical fuse link in response to an electric current passing through the electrical fuse link.
US09337139B2	Semiconductor device having compensation capacitor to stabilize power supply voltage Disclosed herein is a device that includes: first and second memory cell arrays arranged in a first direction; a plurality of first bump electrodes disposed between the first and second memory cell arrays and arranged in line in a second direction crossing the first direction; a plurality of second bump electrodes disposed between the first bump electrodes and the second memory cell arrays and arranged in line in the second direction; a first area being between the first and second bump electrodes; a plurality of third bump electrodes disposed in the first area; and a first capacitor formed in the third area.
US09337135B2	Pop joint through interposer A package includes a package component and an interposer over and bonded to the package component. The package component includes a solder region. The interposer includes a core dielectric material, a conductive pipe penetrating through the core dielectric material, with the first solder region in contact with a bottom end of the conductive pipe, and a through-opening in a center region of the interposer.
US09337133B2	Passivation scheme An integrated circuit includes a conductive pad disposed over a substrate. A first passivation layer is disposed over the conductive pad. A second passivation layer is disposed over the first passivation layer. A stress buffer layer is disposed over the second passivation layer. A conductive interconnect layer is over and coupled to the conductive pad and over the stress buffer layer with the conductive interconnect layer adjoining sidewalls of the first passivation layer and the stress buffer layer.
US09337130B2	Leadframe strip and leadframes A leadframe strip including a first leadframe having a first die pad and a first plurality of generally parallel leads each extending outwardly relative to the first die pad and terminating in a free end and a second leadframe having a second die pad and a second plurality of generally parallel leads extending outwardly relative to the second die pad and terminating in a free end. The free ends of the second plurality of leads are positioned in close nontouching adjacent relationship with the free ends of the first plurality of leads. The two leadframes may be separated from each other by a single saw cut.
US09337122B2	Transferring heat through an optical layer of integrated circuitry A computer program product or hardware description language (“HDL”) design structure in a computer-aided design system for generating a functional design model of an integrated circuitry structure including generating a functional representation of at least first and second regions of the integrated circuitry structure, generating a functional representation of an optical layer comprising optical waveguides, and generating a functional representation of a heat-conductive material for transferring heat from at least the second region through the optical layer to a heat sink.
US09337121B2	Semiconductor device and method of fabricating the same Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: an active region provided on a substrate; an inlet channel formed as a single cavity buried in one side of the substrate; an outlet channel formed as a single cavity buried in the other side of the substrate; a micro channel array comprising a plurality of micro channels, wherein the plurality of micro channels are formed as a plurality of cavities buried in the substrate, and one end of the micro channel array is connected to a side of the inlet channel and the other end of the micro channel array is connected to a side of the outlet channel; and a micro heat sink array separating the micro channels from one another.
US09337118B2	Stress buffer structures in a mounting structure of a semiconductor device A semiconductor device includes a bonding pad on a substrate. The semiconductor device further includes a passivation layer covering a peripheral portion of the bonding pad while exposing a middle portion of the bonding pad. Additionally, the semiconductor device includes a stress buffer layer over the passivation layer where the stress buffer layer exposes a portion of the bonding pad, and where a wall of the stress buffer layer extends, in steps, upwardly from the exposed portion of the bonding pad. Furthermore, the semiconductor device includes an under-bump metallurgy (UBM) layer over the stress buffer layer, where the UBM layer contacts a portion of the bonding pad.
US09337116B2	Semiconductor device and method of forming stepped interposer for stacking and electrically connecting semiconductor die A semiconductor substrate has a plurality of different size recesses formed in the substrate to provide a stepped interposer. A conductive via can be formed through the stepped interposer. An insulating layer follows a contour of the stepped interposer. A conductive layer is formed over the insulating layer following the contour of the stepped interposer. A first semiconductor die is partially disposed in a first recess and electrically connected to the conductive layer. A second semiconductor die is partially disposed in a second recess and electrically connected to the conductive layer. The first semiconductor die is electrically connected to the second semiconductor die through the conductive layer. The first and second semiconductor die can be flipchip type semiconductor die. An encapsulant is deposited over the first and second semiconductor die. A portion of the stepped interposer can be removed to reduce thickness.
US09337107B2	Semiconductor device and method for forming the same Various embodiments provide semiconductor devices and methods for forming the same. A substrate having a dielectric layer formed thereon is provided. The dielectric layer has six openings. A gate dielectric layer and a cap layer are sequentially formed in each opening of the six openings. A first work function layer is formed in a first opening and a second opening. A diffusion layer is formed in the first opening, a fifth opening, and a sixth opening. A material of the diffusion layer is diffused into the first work function layer and the cap layer, to form a doped work function layer in the first opening and a doped cap layer in the fifth opening and in the sixth opening. A second work function layer is formed in a fourth opening and the fifth opening. A third work function layer and a metal gate are formed in the each opening.
US09337106B2	Implant profiling with resist A process for forming at least two different doping levels at the surface of a wafer using one photo resist pattern and implantation process step. A resist layer is developed (but not baked) to form a first resist geometry and a plurality of sublithographic resist geometries. The resist layer is baked causing the sublithographic resist geometries to reflow into a continuous second resist geometry having a thickness less that the first resist geometry. A high energy implant implants dopants through the second resist geometry but not through the first resist geometry. A low energy implant is blocked by both the first and second resist geometries.
US09337105B1	Methods for fabricating semiconductor devices with wet etching A method for fabricating a semiconductor device is provided. The method for fabricating a semiconductor device includes forming transistors on a semiconductor substrate, each of the transistors having a gate structure and source/drain regions, forming an oxide film on the transistors, forming a mask film pattern on the oxide film, the mask film pattern comprising a first pattern having a first width and a second pattern having a second width different from the first width, removing a part of the oxide film using the mask film pattern to form first and second trenches, filling the first and second trenches with a nitride film, removing the rest part of the oxide film to form third and fourth trenches, and forming conductive contacts by filling the third and fourth trenches. A top width of each of the third trenches is equal to the first width, and a top width of each of the fourth trenches is equal to the second width.
US09337103B2	Method for removing hard mask oxide and making gate structure of semiconductor devices A method includes forming a first gate above a semiconductor substrate, forming a hard mask on the first gate, and forming a contact etch stop layer (CESL) on the hard mask. No hard mask is removed between the step of forming the hard mask and the step of forming the CESL. The method further includes forming an interlayer dielectric (ILD) layer over the CESL, and performing one or more CMP processes to planarize the ILD layer, remove the CESL on the hard mask, and remove at least one portion of the hard mask.
US09337101B1	Methods for selectively removing a fin when forming FinFET devices One illustrative method disclosed herein includes, among other things, forming a plurality of fins in a semiconducting substrate, each of which has a corresponding masking layer feature positioned thereabove, forming a masking layer that has an opening that exposes at least two fins of the plurality of fins, performing an angled etching process through the opening in the masking layer so as to remove the masking layer feature formed above one of the at least two exposed fins, and thereby define an exposed fin, while leaving the masking layer feature intact above the other of the at least two exposed fins, and performing an anisotropic etching process through the opening in the masking layer to remove the exposed fin while leaving the other of the at least two exposed fins intact.
US09337100B2	Apparatus and method to fabricate an electronic device An apparatus and method to fabricate an electronic device is disclosed. In a particular embodiment, an apparatus includes a template having an imprint surface. The imprint surface includes a first region having a first pattern adapted to fabricate a fin field effect transistor (FinFET) device and a second region having a second pattern adapted to fabricate a planar electronic device.
US09337096B2	Apparatus and methods for molding die on wafer interposers Methods and apparatus for performing molding on die on wafer interposers. A method includes receiving an interposer assembly having a die side and an opposite side including two or more integrated circuit dies mounted on the die side of the interposer, the interposer assembly having spaces formed on the die side of the interposer between the two or more integrated circuit dies; mounting at least one stress relief feature on the die side of the interposer assembly in one of the spaces between the two or more integrated circuit dies; and molding the integrated circuit dies using a mold compound, the mold compound surrounding the two or more integrated circuit dies and the at least one stress relief feature. An apparatus is disclosed having integrated circuits mounted on a die side of an interposer, stress relief features between the integrated circuits and mold compound over the integrated circuits.
US09337095B2	Method of manufacturing leadless integrated circuit packages having electrically routed contacts A method of manufacturing a leadless integrated circuit (IC) package comprising an IC chip mounted on a metal leadframe and a plurality of electrical contacts electrically coupled to the IC chip. The IC chip, the electrical contacts, and a portion of the metal leadframe are covered with an encapsulation compound, with portions of the electrical contacts exposed on a bottom surface of the encapsulation compound. The electrical contacts of the IC package having metal traces connecting bonding areas on a top surface thereof and contact areas on a bottom surface thereof, wherein at least some of the bonding areas are laterally disposed from the contact areas connected thereto.
US09337092B2	Method of manufacturing semiconductor device A method of manufacturing a semiconductor device includes a groove portion formation process of forming a groove portion in a base body, a bather layer formation process of forming a barrier layer covering at least the inner wall surface of the groove portion, a seed layer formation process of forming a seed layer covering the barrier layer, and a seed layer melting process of causing the seed layer to be melted using the reflow method. The seed layer is made of Cu.
US09337089B2	Method for fabricating a semiconductor device having a bit line contact A semiconductor device includes a semiconductor substrate having an active region defined by an isolation layer, a gate line defining a bit line contact region in the active region and extending in one direction, and a dielectric layer covering the semiconductor substrate and the gate line formed in the semiconductor substrate. The semiconductor device is provided with a bit line contact hole formed in the dielectric layer and exposing the bit line contact region. In order to alleviate a self-aligned contact (SAC) fails caused by a conductive material remaining in a contact hole, the semiconductor device contains a bit line contact spaced apart from a sidewall of the bit line contact hole and formed in the bit line contact hole.
US09337088B2	MOL resistor with metal grid heat shield An semiconductor structure, method of fabrication therefor, and design structure therefor is provided. A thermal grid is formed over at least a portion of a substrate. An insulating layer is formed over at least a portion of the thermal grid. A resistor is formed over at least a portion of the insulating layer. A buried interconnect is connected to the thermal grid via at least one contact. The buried interconnect is adapted to receive thermal energy from the thermal grid via the at least one contact.
US09337085B2	Air gap formation between bit lines with side protection Air gaps are formed between bit lines by etching to remove sacrificial material from between bit lines. Bit lines are protected from etch damage. Sacrificial material may be selectively oxidized prior to deposition of bit line metal so that protective oxide lies along sides of bit lines during etch. Portions of protective material may be selectively formed on tops of bit lines prior to etching sacrificial material.
US09337084B1	Method for manufacturing contact holes of a semiconductor device The present invention provides a method for manufacturing contact holes of a semiconductor device, including a first dielectric layer is provided, a first region and a second region are defined on the first dielectric layer respectively, at least two cutting hard masks are formed and disposed within the first region and the second region respectively, at least two step-height portions disposed right under the cutting hard masks respectively. Afterwards, at least one first slot opening within the first region is formed, where the first slot opening partially overlaps the cutting hard mask and directly contacts the cutting hard mask, and at least one second contact opening is formed within the second region, where the second contact opening does not contact the cutting hard mask directly, and at least two contact holes are formed, where each contact hole penetrates through each step height portion.
US09337080B2	Method for manufacturing SOI wafer The present invention is a method for manufacturing an SOI wafer, including: implanting one or more gas ion selected from a hydrogen ion and a rare gas ion into a bond wafer composed of a semiconductor single crystal substrate from a surface of the bond wafer to form an ion-implanted layer; bonding the surface from which the ion is implanted into the bond wafer and a surface of a base wafer through an oxide film; and then delaminating the bond wafer at the ion-implanted layer by performing a delamination heat treatment with a heat treatment furnace to form the SOI wafer, wherein after the delamination heat treatment, a temperature of the heat treatment furnace is decreased to 250° C. or less at temperature-decreasing rate of less than 3.0° C/min, and then the SOI wafer and the bond wafer after delamination are taken out from the heat treatment furnace.
US09337079B2	Prevention of contact to substrate shorts Isolation trenches are etched through an active silicon layer overlying a buried oxide on a substrate into the substrate, and through any pad dielectric(s) on the active silicon layer. Lateral epitaxial growth of the active silicon layer forms protrusions into the isolation trenches to a lateral distance of at least about 5 nanometers, and portions of the isolation trenches around the protrusions are filled with dielectric. Raised source/drain regions are formed on portions of the active silicon layer including a dielectric. As a result, misaligned contacts passing around edges of the raised source/drain regions remain spaced apart from sidewalls of the substrate in the isolation trenches.
US09337077B2	Semiconductor device A semiconductor device includes a P-type semiconductor substrate including a pad, a ground pad, and a power supply pad, a first N-type diffusion region formed on the P-type semiconductor substrate and connected to the pad, an internal circuit region formed on the P-type semiconductor substrate, and a minority carrier capture region formed between the first N-type diffusion region and the internal circuit region for capturing minority carriers in the P-type semiconductor substrate caused by a surge to the pad. The minority carrier capture region has a triple guard ring including a first P-type diffusion region, a second P-type diffusion region, and a second N-type diffusion region located between the first P-type diffusion region and the second P-type diffusion region. Each of the first P-type diffusion region and the second P-type diffusion region is connected to the ground pad respectively through metal film wirings that are separately formed.
US09337075B2	Chemical mechanical polishing fixture having lateral perforation structures A chemical mechanical polishing fixture having lateral perforation structures includes: a holder and a retaining ring. The holder includes: an annular substrate, a plurality of third holes and a plurality of lateral perforation structures. The annular substrate has a first joint surface, an outer periphery and an inner periphery. The third holes are annularly arranged on the first joint surface, and each third hole includes a first inner thread structure for individually providing a screw to be locked to a semiconductor machine. The lateral perforation structures penetrate from the outer periphery to the inner periphery of the annular substrate, where the lateral perforations are selected from: a converse U-shaped cube structure, an converse U-shaped cube structure, a cuboid structure, a cylinder structure, an elliptic cylinder structure, a flat cuboid structure or a hybrid structure of at least one cuboid structure and the above.
US09337073B2	3D shielding case and methods for forming the same A package includes a die, and a molding material molding the die therein. A metal shield case includes a first metal mesh over and contacting the molding material and the die, a second metal mesh underlying the die, and a Through-Assembly Via (TAV) in the molding material and forming a ring encircling the die. The TAV is electrically connected to the first metal mesh and the second metal mesh.
US09337061B2	Fabrication method of semiconductor package A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a carrier; disposing at least a semiconductor element on the carrier; forming an encapsulant on the carrier and the semiconductor element for encapsulating the semiconductor element; removing the carrier; disposing a pressure member on the encapsulant; and forming an RDL structure on the semiconductor element and the encapsulant, thereby suppressing internal stresses through the pressure member so as to mitigate warpage on edges of the encapsulant.
US09337059B2	Apparatus and methods for annealing wafers A method includes performing an anneal on a wafer. The wafer includes a wafer-edge region, and an inner region encircled by the wafer-edge region. During the anneal, a first power applied on a portion of the wafer-edge region is at least lower than a second power for annealing the inner region.
US09337051B2	Method for critical dimension reduction using conformal carbon films Embodiments of the disclosure generally provide a method of forming a reduced dimension pattern in a hardmask that is optically matched to an overlying photoresist layer. The method generally comprises of application of a dimension shrinking conformal carbon layer over the field region, sidewalls, and bottom portion of the patterned photoresist and the underlying hardmask at temperatures below the decomposition temperature of the photoresist. The methods and embodiments herein further involve removal of the conformal carbon layer from the bottom portion of the patterned photoresist and the hardmask by an etch process to expose the hardmask, etching the exposed hardmask substrate at the bottom portion, followed by the simultaneous removal of the conformal carbon layer, the photoresist, and other carbonaceous components. A hardmask with reduced dimension features for further pattern transfer is thus yielded.
US09337049B1	Manufacturing method of wafer level chip scale package structure A manufacturing method of wafer level chip scale package structure is provided. Firstly, a wafer including a plurality of semiconductor devices is provided. An active surface of one of the semiconductor devices has an active an active region and an outer region. A first electrode and a second electrode are arranged on the active region, and the outer region has a cutting portion and a channel portion. Next, a patterned protecting layer having a plurality of openings is formed on the active surface to respectively expose the first and second electrodes and channel portion. Subsequently, a wafer back thinning process is performed and then a back electrode layer is deposited. Subsequently, the channel portion is etched to form a trench exposing the back electrode layer, and a conductive structure connected to the back electrode layer is formed through the trench. Thereafter, the wafer is cut along the cutting portion.
US09337047B2	Semiconductor device and method of making semiconductor device One or more embodiments are related to a semiconductor device, comprising: a high-K dielectric material; and a nitrogen-doped silicon material disposed over said high-k dielectric material.
US09337046B1	System and method for mitigating oxide growth in a gate dielectric Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.
US09337044B2	System and method for mitigating oxide growth in a gate dielectric Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.
US09337040B1	Angled ion beam processing of heterogeneous structure A method for fabricating a multilayer structure includes providing a mask on a device stack disposed on the substrate, the device stack comprising a first plurality of layers composed of a first layer type and a second layer type; directing first ions along a first direction forming a first non-zero angle of incidence with respect to a normal to a plane of the substrate, wherein a first sidewall is formed having a sidewall angle forming a first non-zero angle of inclination with respect to the normal, the first sidewall comprising a second plurality of layers from at least a portion of the first plurality of layers and composed of the first layer type and second layer type; and etching the second plurality of layers using a first selective etch wherein the first layer type is selectively etched with respect to the second layer type.
US09337029B2	Structure including gallium nitride substrate and method of manufacturing the gallium nitride substrate A structure includes a silicon substrate, a plurality of silicon rods on the silicon substrate, a silicon layer on the plurality of silicon rods, and a GaN substrate on the silicon layer.
US09337028B2	Passivation of group III-nitride heterojunction devices Passivation of group III-nitride hetero junction devices is described herein. The passivation facilitates simultaneous realization of effective/high current collapse suppression and low leakage current without the use of a sophisticated multiple-field plate technique. The passivation can be achieved by growing a charge-polarized AlN thin film on the surface of a group III-nitride based heterojunction device by plasma-enhanced atomic layer deposition such that positive polarization charges are induced at the interface to compensate for a majority of negative charges at the interface.
US09337027B2	Method of manufacturing substrates having improved carrier lifetimes This invention relates to a method for depositing silicon carbide material onto a substrate such that the resulting substrate has a carrier lifetime of 0.5-1000 microseconds, the method comprising a. introducing a gas mixture comprising a chlorosilane gas, a carbon-containing gas, and hydrogen gas into a reaction chamber containing a substrate; and b. heating the substrate to a temperature of greater than 1000° C. but less than 2000° C.; with the proviso that the pressure within the reaction chamber is maintained in the range of 0.1 to 760 torr. This invention also relates to a method for depositing silicon carbide material onto a substrate such that the resulting substrate has a carrier lifetime of 0.5-1000 microseconds, the method comprising a. introducing a gas mixture comprising a non-chlorinated silicon-containing gas, hydrogen chloride, a carbon-containing gas, and hydrogen gas into a reaction chamber containing a substrate; and b. heating the substrate to a temperature of greater than 1000° C. but less than 2000° C.; with the proviso that the pressure within the reaction chamber is maintained in the range of 0.1 to 760 torr.
US09337024B2	Methods and structures for preparing single crystal silicon wafers for use as substrates for epitaxial growth of crack-free gallium nitride FILMS and devices This document describes the fabrication and use of ceramic stabilizing layer fabricated right on the product silicon wafer to facilitate its use as a substrate for fabrication of gallium nitride films. A ceramic layer is formed and then attached to a single crystal silicon substrate to form a composite silicon substrate that has coefficient of thermal expansion comparable with GaN. The composite silicon substrates prepared by this invention are uniquely suited for use as growth substrates for crack-free gallium nitride films, benefiting from compressive stresses produced by choosing a ceramic having a desired higher coefficient thermal expansion than those of silicon and gallium nitride.
US09337015B2	Method of manufacturing a semiconductor device, method of processing a substrate, substrate processing apparatus, and recording medium Disclosed is a method of manufacturing a semiconductor device. The method includes forming a film containing carbon on a substrate by repeating a cycle plural times. The cycle includes: in a state in which a substrate housed in a processing chamber is heated, supplying an organic-based gas into the processing chamber and confining the organic-based gas inside the processing chamber; maintaining a state in which the organic-based gas is confined inside the processing chamber; and exhausting an inside of the processing chamber.
US09337012B2	Fluorine-containing resin film and solar cell module Disclosed is a fluorine-containing resin film which is formed from a fluorine-containing resin composition and has a thickness of 10 to 50 μm, wherein the fluorine-containing resin composition is prepared by adding 10 to 30 parts by mass of titanium oxide or a composite-oxide-type inorganic pigment to 100 parts by mass of a resin component comprising 60 to 95 parts by mass of a vinylidene fluoride resin and 5 to 40 parts by mass of a methacrylic acid ester resin, and wherein the peak intensity ratio of a II-type crystal, which is expressed by (A)/((A)+(B))×100 wherein A represents the peak height at 840 cm−1 and B represents the peak height at 765 cm−1 in a measurement chart produced by an infrared absorption spectrum, is 60% or more and the total crystallinity is 30% or more as calculated from an X-ray diffraction profile.
US09337011B2	Electrical device, system and method for operating with reduced acoustic noise generation Disclosed herein is a device for reducing noise generated by an electrical component, the device including a stiffening component secured to an electrical component, wherein the stiffening component provides rigidity to the electrical component, thereby reducing the mechanical resonance of the electrical component during operation. The electrical component has at least one end face and a flange portion that includes a flange face that extends about a perimeter of the end face. The flange face is substantially parallel to the end face, wherein the stiffening component is secured to the flange face of the electrical component such that it does not extend into a plane of the end face. Further, the stiffening component can include a stiffening portion and a securing portion, wherein the stiffening portion is secured to the flange face of the electrical component by the securing portion. Further, the electrical component can be a power semiconductor device.
US09337005B2	Method of MS/MS mass spectrometry A method of mass spectrometry is disclosed comprising alternating between a first mode in which parent ions are mass analyzed and a second mode in which the parent ions are subjected to Electron Capture Dissociation (“ECD”) at atmospheric pressure so as to produce fragment ions which are then mass analyzed. The parent ions are associated with their fragment ions based on the times at which they were detected. This method enables parent ions to be associated with their fragment ions, even when the ECD fragmentation is performed at atmospheric pressure.
US09337003B2	Plasma processing apparatus and constituent part thereof A constituent part is included in a plasma processing apparatus for performing a plasma process on a substrate mounted on a susceptor by using a plasma generated in a processing chamber. The constituent part has at least one recessed corner formed by intersection of two surfaces. The recessed corner is exposed to the plasma when the plasma is generated in the processing chamber. An intersection angle of the two surfaces seen from a plasma side is 115 degrees to 180 degrees.
US09336997B2	RF multi-feed structure to improve plasma uniformity A plasma source assembly for use with a processing chamber is described. The assembly includes a multi-feed RF power connection to a single or multiple RF hot electrodes.
US09336991B2	Ion implantation device The disclosed ion implantation apparatus has a vacuum chamber 11, a roller electrode 13 having a portion of an outer circumferential part on which a film 3 is wound, voltage application unit 23 for applying a voltage to the roller electrode, and a gas introduction unit having a gas supply outlet for supplying an ion implantation gas into the vacuum chamber, wherein the gas introduction unit and a gas discharge outlet are disposed so as to be opposite each other along the axial direction of the roller electrode, the roller electrode intervening therebetween.
US09336989B2	Method of cleaving a thin sapphire layer from a bulk material by implanting a plurality of particles and performing a controlled cleaving process Embodiments relate to use of a particle accelerator beam to form thin layers of material from a bulk substrate. In particular embodiments, a bulk substrate (e.g. donor substrate) having a top surface is exposed to a beam of accelerated particles. In certain embodiments, this bulk substrate may comprise a core of crystalline sapphire (Al2O3) material. Then, a thin layer of the material is separated from the bulk substrate by performing a controlled cleaving process along a cleave region formed by particles implanted from the beam. Embodiments may find particular use as hard, scratch-resistant covers for personal electric device displays, or as optical surfaces for fingerprint, eye, or other biometric scanning.
US09336982B2	Method of detecting electrons, an electron-detector and an inspection system An electron-detector comprises a scintillator plate 207, electron optics 204 for directing a plurality of electron beams 9 onto the scintillator plate so that the electron beams are incident onto the scintillator plate at locations of incidence disposed at a distance from each other, a light detector 237 comprising a plurality of light receiving areas 235 disposed at a distance from each other, and light optics for generating a first light-optical image of at least a portion of the scintillator plate at a region 243 where the light receiving areas of the light detector are disposed so that, by the imaging, each of the locations of incidence is associated with a light receiving area; and wherein the electron optics comprise an electron beam deflector 255 for displacing the locations of incidence of the electron beams on the scintillator plate in a direction orthogonal to a normal 249 of a surface 208 of the scintillator plate.
US09336979B2	Focused ion beam apparatus with precious metal emitter surface A focused ion beam apparatus has an ion source chamber in which is disposed an emitter for emitting ions. The surface of the emitter is formed of a precious metal, such as platinum, palladium, iridium, rhodium or gold. A gas supply unit supplies nitrogen gas to the ion source chamber so that the nitrogen gas adsorbs on the surface of the emitter. An extracting electrode is spaced from the emitter, and a voltage is applied to the extracting electrode to ionize the adsorbed nitrogen gas and extract nitrogen ions in the form of an ion beam. A temperature control unit controls the temperature of the emitter.
US09336976B2	Relay driving device and method for driving a relay A relay driving device includes first and second power supply modules, a switching circuit, and a control module. The first power supply module outputs a first voltage that has a magnitude sufficient to activate the relay. The second power supply module outputs a second voltage that has a magnitude sufficient to maintain an activated state of the relay. The control module is configured to control the switching circuit to connect the relay to the first power supply module so as to provide the first voltage to the relay for activating the relay, and to subsequently connect the relay to the second power supply module so as to provide the second voltage to the relay for maintaining the activated state of the relay.
US09336975B2	Power distribution apparatus supplying direct-current power A power distribution apparatus for supplying power from a direct-current power supply to a load via a first connector and a second connector includes a sensor unit configured to detect connected and disconnected states between the first connector and the second connector, a switch unit configured to make and break a connection between the first connector and the direct-current power supply, a receiver unit configured to receive a signal indicating whether to supply or cut off power to the load, and a control unit configured to control the switch unit to make or break the connection in response to the signal received by the receiver unit and the connected and disconnected states between the first connector and the second connector detected by the sensor unit.
US09336972B2	Switch device A switch device includes a lever and a pusher. The pusher includes a surface that contacts the lever. When force is applied from the lever to the pusher, an inclined surface of the pusher produces a force that moves the pusher from a one-side pushing position to a two-side pushing position. This allows for a user to apply a smaller force to the lever in order to move the pusher from the one-side pushing position to the two-side pushing position and thereby push two switch units.
US09336971B2	Switch A switch has an actuating arm including an actuating portion and a driving portion, a base including a support that supports the actuating arm, and a recess having a first fixed electrode and a second fixed electrode arranged on the inner side face, and an electrically conductive elastic member that is housed within the recess of the base. The electrically conductive elastic member includes at least one driven part that is driven by the driving portion of the driving body and at least one stretching part that is extendable and compressible through input to the at least one driven part, at least one movable contacting member having a movable contact capable of being connected to the first fixed electrode, and at least one fixed contacting part having a fixed contact capable of being connected to the second fixed electrode.
US09336969B2	Press detection sensor, input device and electronic apparatus A press detection sensor contains a base member having predetermined length and width and also having a predetermined shape, a first conductor having predetermined length and being arranged on the base member, and a second conductor that is arranged on the base member with the second conductor being faced to the first conductor. The press detection sensor also contains a conductive contact body that is arranged between the first conductor and the second conductor. The conductive contact body connects the first and second conductors electrically in response to an external force. The press detection sensor further contains a covering member that includes the contact body on the inside thereof. The covering member covers a top of the base member which includes the first and second conductors. The covering member contains at least one of flexibility and elasticity.
US09336965B2	Sealed contact device The invention provides a sealed contact device capable of extinguishing an arc which extends in an arbitrary direction. The sealed contact device includes a housing; a fixed contact and a movable contact disposed in the housing in such a manner as to face each other; and permanent magnets which are disposed with the fixed contact and the movable contact interposed therebetween and which attracts an arc between the fixed contact and the movable contact using a magnetic force. An arc shielding member is disposed at a position to which the arc is attracted by current flowing between the fixed contact and the movable contact and by the magnetic force between the permanent magnets, in the housing.
US09336963B1	Interlock assembly for network transformer primary disconnect assembly A mechanical interlock assembly for a network transformer primary disconnect assembly is provided. The mechanical interlock assembly includes a blocking member assembly with a body. The a blocking member assembly body includes an obstruction portion and a lacunar portion. The blocking member assembly is movably disposed adjacent to a movable operation contact carriage and a ground contact carriage. The blocking member assembly body is movable between a first position, wherein the blocking member assembly body obstruction portion is disposed in the path of the ground contact carriage, a neutral position, wherein the blocking member assembly body obstruction portion is disposed in the path of the ground contact carriage and the operation contact carriage, and a second position, wherein the blocking member assembly body obstruction portion is disposed in the path of the operation contact carriage.
US09336953B2	MEMS lifetime enhancement The present invention generally relates to methods for increasing the lifetime of MEMS devices by reducing the number of movements of a switching element in the MEMS device. Rather than returning to a ground state between cycles, the switching element can remain in the same state if both cycles necessitate the same capacitance. For example, if in both a first and second cycle, the switching element of the MEMS device is in a state of high capacitance the switching element can remain in place between the first and second cycle rather than move to the ground state. Even if the polarity of the capacitance is different in successive cycles, the switching element can remain in place and the polarity can be switched. Because the switching element remains in place between cycles, the switching element, while having the same finite number of movements, should have a longer lifetime.
US09336946B2	Multilayer ceramic electronic component and assembly board having the same The present application describes a multilayer ceramic electronic component including a ceramic body having a thickness greater than a width and includes a dielectric layers, and has upper and lower surfaces opposing each other in a thickness direction. First and second side surfaces oppose each other in a width direction, and first and second end surfaces oppose each other in a length direction. First and second internal electrodes are stacked with at least one of the dielectric layers interposed therebetween within the ceramic body in the width direction. A volume increasing part is disposed in a lower portion of the ceramic body in the thickness direction to allow a volume of a lower margin portion of the ceramic body to be greater than that of an upper margin portion thereof.
US09336942B2	Reactor, converter, and power conversion device A reactor that includes a coil with a pair of coil elements connected to each other, a magnetic core with a pair of interior core portions disposed inside the coil elements and an exterior core portion which connects the interior core portions to form a closed magnetic path, and an insulator interposed between the coil and the magnetic core.
US09336939B2	High-voltage transformer module A high-voltage transformer module includes a transformer core including at least one winding, and a mechanical supporting structure having the transformer core integrated permanently therein. The mechanical supporting structure has corner points arranged in the form of a right-parallelepiped. The corner points are in the form of load transfer points and are arranged corresponding to the dimensions of a CSC (International Convention for Safe Containers) container.
US09336936B1	Magnetic pathway cleaning assemblies and vehicles incorporating the same Embodiments of a magnetic pathway cleaning assembly include a magnet having a pathway facing surface and a magnet sweeper having a sweeping portion that is slidably engageable with the pathway facing surface of the magnet and a translation shaft having a first end opposite a second end. The first end is coupled to the sweeping portion and the second end terminates at a contact surface. A spring is engaged with the translation shaft such that the spring biases the magnet sweeper into a retracted position offset from the pathway facing surface of the magnet. Further, the magnet sweeper is actuatable such that a force applied to the contact surface of the translation shaft moves the sweeping portion along the pathway facing surface of the magnet.
US09336935B2	Levitation device with horizontal spin axis A levitation device including an object levitatable at a predetermined position, wherein the object comprises a spinning magnet, the spinning magnet having a substantially horizontal spin axis defining an axial direction and the spinning magnet having a magnetization direction parallel to the spin axis, the device further comprising: a pusher magnet arrangement configured to produce a magnetic field at the predetermined position that is in the opposite direction to the magnetization direction of said spinning magnet; a lifter magnet arrangement lower than and to either side of the predetermined position, having a magnetization direction parallel to the magnetization direction of the spinning magnet, and having a recess under the predetermined position; and a puller magnet arrangement above said predetermined position and having a magnetization direction antiparallel to the magnetization direction of the spinning magnet.
US09336924B2	Self-wrapping textile sleeve with protective coating and method of construction thereof A self-wrapping, textile sleeve for routing and protecting elongate members from exposure to abrasion, thermal and other environmental conditions and method on construction thereof. The sleeve has an elongate wall constructed from interlaced yarns having interstices between adjacent yarns. At least one of the yarns is heat formed at one temperature to form the wall as a self-wrapping wall curling about a longitudinal axis of the sleeve. The wall has an inner surface providing a generally tubular cavity in which the elongate members are received. The wall also has an outer surface with a cured layer thereon. The cured layer is cured at the one temperature at which the yarns are heat formed into their self-wrapping configuration, wherein the cured layer fills the interstices between adjunct yarns to form an impervious layer on the wall.
US09336923B2	Electrically conductive polymer resin and method for making same Disclosed are polymer resins, including polymer resin sheets, having good electroconductivity and a method for manufacturing the same. The polymer resins exhibit flexibility and show electroconductivity on their surface as well as along their thickness, and thus can be used as electromagnetic wave-shielding materials having impact- and vibration-absorbing properties as well as conductivity.
US09336922B2	Method of fabricating thermoelectric materials using core-shell structured nano-particles, and thermoelectric materials fabricated by the same A fabrication method of thermoelectric materials using core-shell structured nano-particles and thermoelectric materials fabricated by the same are provided. The method includes preparing core-shell structured nano-particles having thermoelectric elements coated on the surface thereof (step 1); adding and mixing the prepared core-shell structured nano-particles of step 1, bismuth (Bi) salts, tellurium (Te) salts and a surfactant in a solvent (step 2); adding and dispersing a reducing agent in the mixture of step (step 3); and heating the mixture of step 3 in which reducing agent is added and dispersed (step 4). According to the present invention, thermoelectric materials, nano-phase is homogeneously dispersed inside of thermoelectric grain boundary, can be fabricated and if the fabricated materials are used after sintering and bulking, the thermoelectric materials are maintained in a state that the nano-particles remain in dispersed phase even after sintering.
US09336921B2	Electrically conducting composites, methods of manufacture thereof and articles comprising the same Disclosed herein is a composition comprising a regioregular polyalkylthiophene and/or a regioregular poly[2,5-bis(3-alkylthiophen-2-yl)thieno(3,2-b)thiophene]; and a metallocene; where the metallocene is present in an amount of greater than 50 wt %, based on the total weight of the composition. Disclosed herein too is a method of manufacturing a thin film comprising dissolving a regioregular polyalkylthiophene or a regioregular poly[2,5-bis(3-alkylthiophen-2-yl)thieno(3,2-b)thiophene] in a solvent to form a solution; dissolving a metallocene in the solution; disposing the solution on a substrate; and annealing the substrate.
US09336920B2	Composite oxide sintered body and oxide transparent conductive film To provide a composite oxide sintered body from which an oxide transparent conductive film having lower light absorption properties in a wide wavelength region and having a low resistance can be obtained, and an oxide transparent conductive film.A composite oxide sintered body containing indium, zirconium, hafnium and oxygen, wherein the atomic ratio of the elements constituting the sintered body satisfies the following formulae, where In, Zr and Hf are respectively contents of indium, zirconium and hafnium: Zr/(In+Zr+Hf)=0.05 to 4.5 at % Hf/(In+Zr+Hf)=0.0002 to 0.15 at %.
US09336911B2	Core thermal limit value monitoring device, core monitoring system and core thermal limit value monitoring method According to an embodiment, core thermal limit monitoring device is provided with calculating units, and signal input processing units, synchronization processing units and signal output processing units, corresponding to the calculating units. The calculating unit determines if it is necessary to output a signal to the control unit by calculating the thermal state values of the monitoring regions based on a signal representing the state of the core. The synchronization processing unit, if it is necessary to output a signal to the control unit, transmits a signal-output stop signal to the other synchronization processing units, and otherwise, the synchronization processing unit transmits a signal-output stop cancellation signal to the other synchronization processing units. The signal output processing unit, when the synchronization processing unit does not receive a signal stop signal, outputs a signal representing the calculation results of the calculating unit to the control unit.
US09336909B2	Deposition of integrated protective material into zirconium cladding for nuclear reactors by high-velocity thermal application A zirconium alloy nuclear reactor cylindrical cladding has an inner Zr substrate surface (10), an outer volume of protective material (22) consisting of Zr—Al, and an integrated middle volume (20) of zirconium oxide, zirconium and protective material, where the protective material is applied by impaction at a velocity greater than 340 meters/second to provide the integrated middle volume (20) resulting in structural integrity for the cladding.
US09336906B2	Semiconductor memory devices including redundancy memory cells A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.
US09336904B2	Semiconductor apparatus A semiconductor apparatus includes a plurality of memory blocks including a plurality of unit memory blocks, respectively, a first area extending in a first direction among areas formed among the plurality of memory blocks, a second area extending in a second direction among the areas formed among the plurality of memory blocks, and a test mode-related circuit block arranged at an edge part of the first area.
US09336901B2	Track and hold feedback control of pulsed RF A system and method of providing feedback control to a pulsed RF generator includes an RF generator having an RF output and a feedback input. An RF electrode is coupled to the RF output and an RF sampling circuit having a sampling input coupled to the RF electrode. The sampling circuit including a feedback signal output coupled to the feedback input of the RF generator. A method of providing feedback control to a pulse RF generator includes receiving an RF sample of an RF pulse, sampling the RF sample multiple sampling times to produce multiple feedback levels during the duration of the RF pulse and coupling the multiple feedback levels to a feedback input on an RF generator, the RF generator outputting the RF pulse.
US09336899B2	Bidirectional shift register and image display device using the same A bidirectional shift register capable of performing a stable shift operation in both directions and an image display device using the same are provided. In forward shift operation, when reference point N1 is at H level, (n+4)-th unit register circuit as a rear stage of the bidirectional shift register outputs pulse G(n+4) in synchronization with clock pulse V (n+4) inputted to (n+4)-th unit register circuit. A backward direction trigger signal VSTB is generated not only at the time of start of backward shift, but also, for example, in period (time t4 to t5) of one-phase clock immediately after G(n+4) is outputted in vertical blanking interval of the forward shift. The backward direction trigger signal VSTB is inputted to gate of a transistor provided to set reference point N1 of (n+4)-th unit register circuit to H level at the time of start of the backward shift.
US09336894B2	Memory device including nonvolatile memory cell A memory device may include nonvolatile memory cells. A first memory cell of the nonvolatile memory cells may have a first resistance value in a first state and a second memory cell of the nonvolatile memory cells may have a second resistance value less than the first resistance value in a second state. A third memory cell of the nonvolatile memory cells may have a third resistance value less than the first resistance value and greater than the second resistance value in a third state, and a fourth memory cell of the nonvolatile memory cells may have a fourth resistance value less than the third resistance value and greater than the second resistance value in a fourth state.
US09336890B1	Simultaneous programming of many bits in flash memory A semiconductor device includes: a plurality of memory cells; a plurality of local bit lines connected to respective memory cells of the plurality of memory cells; and a first amplifier. The first amplifier receives read data from each local bit line of the plurality of local bit lines and determines a transition speed of an output level of the first amplifier in response to receiving a combination of at least two pieces of read data. The first amplifier transfers, based on the determined transition speed, multivalued data of the read data to a read global bit line.
US09336889B2	Nonvolatile memory system and refresh method A memory system including non-volatile memory devices and a corresponding refresh method are disclosed. The method groups memory blocks of the non-volatile memory devices into memory groups, determines a refresh sequence for the memory groups, and refreshes the memory groups in accordance with the refresh sequence.
US09336887B2	Nonvolatile memory device including memory cell array with upper and lower word line groups A nonvolatile memory device includes a memory cell array having multiple memory blocks. Each memory block includes memory cells arranged at intersections of multiple word lines and multiple bit lines. At least one word line of the multiple word lines is included in an upper word line group and at least one other word line of the multiple word lines is included in a lower word line group. The number of data bits stored in memory cells connected to the at least one word line included in the upper word line group is different from the number of data bits stored in memory cells connected to the at least one other word line included in the lower word line group.
US09336885B1	Reading and writing to NAND flash memories using charge constrained codes A charge constrained bit sequence is processed to obtain a lower bound on a number of bit errors associated with the charge constrained bit sequence. The lower bound is compared against an error correction capability threshold associated with an error correction decoder. In the event the lower bound is greater than or equal to the error correction decoder threshold, an error correction decoding failure is predicted.
US09336884B2	Non-volatile memory device having vertical structure and method of operating the same A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality of word lines are coupled to the plurality of memory cells of the NAND string. A first selection line is commonly connected to the at least one pair of first selection transistors of the NAND string.
US09336881B2	Variable resistance nonvolatile memory device including a variable resistance layer that changes reversibly between a low resistance state and a high resistance state according to an applied electrical signal A variable resistance nonvolatile memory device includes: a nonvolatile memory element; an NMOS transistor connected to the nonvolatile memory element; a source line connected to the NMOS transistor; a bit line connected to the nonvolatile memory element. When a control circuit causes the nonvolatile memory element to be in the low resistance state, the control circuit controls to flow a first current from a first voltage source to a reference potential point, and applies a first gate voltage to a gate of a NMOS transistor, and when the control circuit causes the nonvolatile memory element to be in the high resistance state, the control circuit controls to flow a second current from a second voltage source to the reference potential point, and applies a second gate voltage to the gate of the NMOS transistor, the second gate voltage being lower than the first gate voltage.
US09336879B2	Multiple phase change materials in an integrated circuit for system on a chip application A device includes first and second pluralities of memory cells with memory elements and first and second capping materials on the first and second pluralities of memory cells. First and second capping materials can comprise lower and higher density silicon nitrides. The memory elements can include a programmable resistance memory material, and the capping materials can contact the memory elements. The first and second pluralities of memory cells can have a common cell structure. The first memory cells in the can comprise a top and bottom electrodes with a memory material therebetween and the first capping material contacting the memory material. Control circuits can apply different write algorithms to the first and second pluralities of memory cells. The first and second sets of memory cells can have different operational memory characteristics by forming the first and second capping layers using different capping materials but with the same cell structure.
US09336877B2	Nonvolatile memory device using variable resistive element A nonvolatile memory device utilizes a variable resistive element. The nonvolatile memory device includes a plurality of banks and first to third write global bit lines arranged to cross the plurality of banks. Each of the plurality of banks includes a plurality of nonvolatile memory cells using resistive material. The first, the second and the third write global bit lines are disposed directly adjacent to one another in order. When a write current is supplied to the first write global bit line during a write period, a fixed voltage is applied to the second write global bit line while the third global bit line floats.
US09336876B1	Soak time programming for two-terminal memory Providing for improved programming techniques for endurance and memory retention in two-terminal memory is described herein. In some embodiments, a programming pulse can be configured to provide a minimum pulse time over which a program signal is applied to a two-terminal memory cell, following programming of the two-terminal memory cell. This minimum pulse time can help to stabilize the program state of the two-terminal memory cell, improving stability of the program state (e.g., related to memory retention) and overall increased endurance (e.g., in program cycles) of the two-terminal memory cell. The minimum pulse time can be initiated separately to a programming pulse, or can be integrated as part of the program pulse, in various embodiments. In some embodiments, current compliance or voltage control can be implemented in conjunction with providing programming and minimum pulse time functionality.
US09336875B2	Memory systems and memory programming methods Memory systems and memory programming methods are described. In one arrangement, a memory system includes a memory cell configured to have a plurality of different memory states, an access circuit coupled with the memory cell and configured to provide a first signal to a memory element of the memory cell to program the memory cell from a first memory state to a second memory state, and a current source coupled with the memory cell and configured to generate a second signal which is provided to the memory element of the memory cell after the first signal to complete programming of the memory cell from the first memory state to the second memory state.
US09336873B2	Apparatus for time domain offset cancellation to improve sensing margin resistive memories Described are apparatuses for time domain offset cancellation. One example of the apparatus includes: a variable resistance memory cell; a reference resistive memory cell; a detector to generate an output indicating timing relationship between a pulse arriving from the variable resistance memory cell and a pulse arriving from the reference resistive memory cell; and a logic unit to receive the output from the detector and to generate a control signal to the adjust timing relationship as indicated by the detector.
US09336860B1	Complementary bipolar SRAM A complementary lateral bipolar SRAM device. The device includes: a first set and second set of lateral bipolar transistors forming a respective first inverter device and second inverter device, the first and second inverter devices being cross-coupled for storing a logic state. In each said first and second set, a first bipolar transistor is an PNP type bipolar transistor, and a second bipolar transistor is an NPN type bipolar transistor, each said NPN type bipolar transistor having a base terminal, a first emitter terminal, a second emitter terminal, and a collector terminal. Emitter terminals of the PNP type transistors of each first and second inverter devices are electrically coupled together and receive a first applied wordline voltage. The first emitter terminals of each said NPN transistors of said first inverter and second inverter devices are electrically coupled together and receive a second applied voltage. 'The second emitter terminal of one NPN bipolar transistor of said first inverter is electrically coupled to a first bit line conductor, and the second emitter terminal of the NPN bipolar transistor of said second inverter device is electrically coupled to a second bit line.
US09336859B2	Memory array A memory array includes a first memory cell and a second memory cell aligned along a column direction. Each of the first memory cell and the second memory cell includes a pair of cross-coupled inverters, a first switch on a first side, along the column direction, of the pair of cross-coupled inverters, a second switch aligned with the first switch along the column direction, on a second side of the pair of cross-coupled inverters opposing to the first side, a third switch on the first side of the pair of cross-coupled inverters, and a fourth switch aligned with the third switch along the column direction, on the second side of the pair of cross-coupled inverters. The memory array also includes a first data line, a first complementary data line, a second data line and a second complementary data line.
US09336855B2	Methods and systems for smart refresh of dynamic random access memory Methods and devices for refreshing a dynamic memory device, (e.g., DRAM) to eliminate unnecessary page refresh operations. A value in a lookup table for the page may indicate whether valid data including all zeros is present in the page. When the page includes valid data of all zeros, the lookup table value may be set so that refresh, memory read, write and clear accesses of the page may be inhibited and a valid value may be returned. A second lookup table may contain a second value indicating whether a page has been accessed by a page read or write during the page refresh interval. A page refresh, by issuing an ACT−PRE command pair, and a page address may be performed according to the page refresh interval when the second value indicates that page access has not occurred.
US09336853B2	Memory device, electronic component, and electronic device Provided is a memory device having a plurality of memory cells and a refresh circuit. Each of the memory cells is configured to retain multiple data as a potential of a node connected to a gate of a first transistor, one of a source and a drain of a second transistor, and one of electrodes of a capacitor. The refresh circuit is configured to refresh the memory cells. That is, the refresh circuit is configured to determine an interval between refresh operations, estimate a change of the potential of the node due to the leakage of the charge, and provide a refresh potential to the memory cells, where the refresh potential is a sum of the potential read from the node and the potential lost due to the charge leakage.
US09336852B2	Memory and memory system including the same A memory includes a plurality of word lines, a measurement block suitable for measuring an active duration of an activated word line among the multiple word lines, and a refresh circuit suitable for controlling a refresh operation to refresh one or more of the multiple word lines adjacent to the activated word line when the active duration exceeds a predetermined threshold.
US09336851B2	Memory device and method of refreshing in a memory device In a method of refreshing in a memory device having a plurality of pages, a candidate refresh address corresponding to a page scheduled to be refreshed after a monitoring period is generated. Whether an active command is processed for the candidate refresh address is monitored during the monitoring period. If an active command is processed for the candidate refresh address during the monitoring period, the scheduled refresh for that page is skipped. If no active command is processed for the candidate refresh address during the monitoring period, the scheduled refresh operation is performed.
US09336848B2	Memory device with differential bit cells In some examples, a memory device may be configured to utilize differential bit cells formed from two or more tunnel junctions. In some cases, the tunnel junctions forming the differential bit cell may be arranged to utilize shared read circuitry to reduce device mismatch. For instance, the read operations associated with both tunnel junction may be time multiplexed such that the same preamplifier circuitry may sense voltages representative of the tunnel junctions.
US09336845B2	Register circuit including a volatile memory and a nonvolatile memory A semiconductor device capable of assessing and rewriting data at a desired timing is provided. A semiconductor device includes a register circuit, a bit line, and a data line. The register circuit includes a flip-flop circuit, a selection circuit, and a nonvolatile memory circuit electrically connected to the flip-flop circuit through the selection circuit. The data line is electrically connected to the flip-flop circuit. The bit line is electrically connected to the nonvolatile memory circuit through the selection circuit. The selection circuit selectively stores data based on a potential of the data line or a potential of the bit line in the nonvolatile memory circuit.
US09336842B2	Address counting circuit and semiconductor apparatus using the same A semiconductor apparatus includes a first memory die; a second memory die; and a processor configured to provide an external command, an external start address and an external end address which are associated with a read operation, to the first memory die, and provide an external command, an external start address and an external end address, which are associated with a write operation, to the second memory die, in the case where data stored in the first memory die is to be transferred to and stored in the second memory die.
US09336838B1	Semiconductor memory apparatus and system including the same A semiconductor memory apparatus includes a DBI calculation block, an inversion latch block, an inverted data selective output block, and a pipe latch block. The DBI calculation block performs a DBI calculation and outputs a DBI result signal based on a result of the DBI calculation. The inversion latch block inverts data and outputs the inverted data when a DBI enable signal is enabled. The inverted data selective output block outputs the inverted data as a data inversion signal in response to the DBI result signal and a pipe input signal. The pipe latch block receives the data, which is not inverted, and the inverted data, and outputs one of the data and the inverted data according to the result of the DBI calculation.
US09336837B2	Low voltage sensing scheme having reduced active power down standby current A low voltage sensing scheme reduces active power down standby leakage current in a memory device. A clamping device or diode is used between a Psense amplifier control line (e.g. ACT) and Vcc and/or between an Nsense amplifier control line (e.g. RNL) and Vss (ground potential). The clamping diode is not enabled during normal memory operations, but is turned on during active power down mode to reduce leakage current through ACT and/or RNL nodes. The clamping device connected to the ACT node may reduce the voltage on the ACT line during power down mode, whereas the clamping device connected to the RNL* node may increase the voltage on the RNL* line during power down mode to reduce sense amplifier leakage current through these nodes. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
US09336835B2	Flash dual inline memory modules with multiplexing support circuits In one implementation, flash memory chips are provided with an operating power supply voltage to substantially match a power supply voltage expected at an edge connector of a dual inline memory module. The one or more of the flash memory chips and a memory support application integrated circuit (ASIC) may be mounted together into a multi-chip package for integrated circuits. The one or more flash memory chips and the memory support ASIC may be electrically coupled together by routing one or more conductors between each in the multi-chip package. The multi-chip package may be mounted onto a printed circuit board (PCB) of a flash memory DIMM to reduce the number of packages mounted thereto and reduce the height of the flash memory DIMM. The number of printed circuit board layers may also be reduced, such as by integrating address functions into the memory support ASIC.
US09336833B2	Identifying a digital data handling unit A digital data handling unit has a manually graspable part operable for removal of the unit from a digital data handling host. The manually graspable part includes an illuminable portion which, when illuminated, serves to distinguishably identify a particular digital data handling unit. The illuminable portion may be an illuminable strip. The digital data handling unit may be one of a data processing unit, a data storage unit, a data controller subsystem unit or a data communication unit.
US09336829B2	Data recording medium, method for generating a reference clock signal, and data storage device Various embodiments provide a recording medium. The recording medium may include: a dedicated servo layer for providing servo information, wherein the dedicated servo layer comprises a plurality of tracks, wherein a first track comprises a first servo signal of a first frequency, wherein a second track comprises a second servo signal of a second frequency, and wherein the first servo signal and the second servo signal comprise a common single tone signal.
US09336826B2	Method for facilitating online interactions initiated using optical disc players Online interactions using optical disc players are facilitated by extracting information from a user request that was initiated from an optical disc player, and then using the extracted information to identify pre-existing user-specific data. A short code, which is specific to the desired online interaction and associated with the extracted information and pre-existing information, is generated and transmitted back to the optical disc player. This short code is then provided back to the back-end server by the user from a secondary consumer electronic device, and used to retrieve associated information, such as the target website for consummating the desired interaction and the previously-identified pre-existing information. Retrieved information is used to populate data fields on the target website prior the user being re-directed to the target website.
US09336825B2	Method of editing a video with video editing software executed on a computing device A method of editing a video with video editing software executed on a computing device includes loading a video clip into the video editing software, the video clip being displayed in a linear video editing frame, displaying a first control icon above or below a beginning portion of the video clip, the first control icon being a first variable icon, and displaying a second control icon above or below an ending portion of the video clip, the second control icon being a second variable icon. The method further includes dragging the first variable icon to modify contents of the beginning portion of the video clip or dragging the second variable icon to modify contents of the ending portion of the video clip.
US09336813B2	Thermal-assisted magnetic recording device capable of writing magnetic patterns on lower multi-step driving signals According to one embodiment, there is provided a magnetic disk device including a light irradiation element and a control unit. The light irradiation element is configured to irradiate a magnetic disk with light according to a driving signal. The control unit is configured to lower, in multistep manner, active level of the driving signal contributing intensity of the light when a low frequency pattern of write data is recorded into the magnetic disk.
US09336810B2	Method for manufacturing glass blank for magnetic disk, method for manufacturing glass substrate for magnetic disk A method for manufacturing a glass substrate for magnetic disk is provided in which a glass is kept from being fused to a mold during press forming and shape processing to achieve a good circularity is efficiently performed. The method includes: a forming process of forming a disk-shaped glass blank by direct-pressing a molten glass by a pair of dies; and a shape processing process of performing at least one of inner hole formation and outer shape formation for forming a disk-shaped glass substrate by forming a cutting line on the principal face of the glass blank, followed by growing the cutting line to perform cutting. In the forming process, press forming is performed while the temperature of the pair of dies, over a period of time until a molten glass is separated from the die after coming into contact with the die, is set at a temperature lower than a glass transition point (Tg) and a mold release material is not attached to the surfaces of the pair of dies.
US09336807B1	Unstable reader detection Method and apparatus for detecting unstable read sensors (readers) for data storage systems. In some embodiments, a transducer is supported adjacent a rotating data recording medium having servo data patterns interspersed with calibration test data patterns. A read sensor of the transducer reads the servo and calibration test data patterns while the transducer is maintained at a passive fly height adjacent the medium. A corresponding location on the medium is identified for an error detected during the reading of the servo and calibration test patterns. The servo and calibration test patterns at the location are reread using the read sensor to characterize the read sensor as an unstable reader.
US09336804B2	Systems and methods for multi-resolution data sensing Systems and methods relating generally to sensing information, and more particularly to systems and methods for utilizing multiple readers to sense information.
US09336803B1	Pseudo-differential shared-pin reader for two-dimensional magnetic recording An apparatus for two-dimensional magnetic recording includes a storage medium, an array of magnetoresistive read heads disposed adjacent the storage medium and spaced to read a data track, wherein the array of magnetoresistive read heads share a common terminal, a number of leads connected to the array of magnetoresistive read heads, with one lead for each of the magnetoresistive read heads, plus a common lead connected to the common terminal, wherein each of the plurality of leads other than the at least one common lead are referenced to the at least one common lead, and a preamplifier connected to the array of magnetoresistive read heads by the plurality of leads and operable to perform pseudo-differential sensing or single-ended sensing of signals from the array of magnetoresistive read heads.
US09336798B1	Magnetic head for perpendicular magnetic recording including a main pole with a lower protrusion A main pole includes a main body and a lower protrusion. The lower protrusion is located at a distance from a medium facing surface. The main body includes a front portion and a rear portion. The front portion has a first side surface and a second side surface. The lower protrusion has a third side surface and a fourth side surface. A first side shield has a first sidewall opposed to the first side surface. A second side shield has a second sidewall opposed to the second side surface. A bottom shield includes a receiving section. The receiving section has a third sidewall opposed to the third side surface, and a fourth sidewall opposed to the fourth side surface. The receiving section and the lower protrusion are formed in a self-aligned manner by using the first and second side shields.
US09336797B2	Extended spin torque oscillator The present disclosure generally relates to a high-frequency oscillator for use in a recording device having a microwave-assisted magnetic recording head. The microwave-assisted magnetic recording head achieves a large assist effect by using an extended spin torque oscillator disposed between a main magnetic pole and a pole opposite the main magnetic pole. The spin torque oscillator obtains a strong high-frequency magnetic field and comprises a first non-magnetic spin scatterer, a reference layer, a first non-magnetic spin transfer layer, a first magnetic field generating layer, a second non-magnetic spin transfer layer, a second magnetic field generating layer, and a second non-magnetic spin scatterer. The spin torque oscillator has a drive current flowing though in the direction from the first magnetic field generating layer to the reference layer.
US09336796B2	Method and apparatus for detecting speech/non-speech section Provided is an apparatus for detecting a speech/non-speech section. The apparatus includes an acquisition unit which obtains inter-channel relation information of a stereo audio signal, a separation unit which separates each element of the stereo audio signal into a center channel element and a surround element on the basis of the inter-channel relation information, a calculation unit which calculates an energy ratio value between a center channel signal composed of center channel elements and a surround channel signal composed of surround elements, for each frame, and an energy ratio value between the stereo audio signal and a mono signal generated on the basis of the stereo audio signal, and a judgment unit which determines a speech section and a non-speech section from the stereo audio signal by comparing the energy ratio values.
US09336789B2	Systems and methods for determining an interpolation factor set for synthesizing a speech signal A method for determining an interpolation factor set by an electronic device is described. The method includes determining a value based on a current frame property and a previous frame property. The method also includes determining whether the value is outside of a range. The method further includes determining an interpolation factor set based on the value and a prediction mode indicator if the value is outside of the range. The method additionally includes synthesizing a speech signal.
US09336787B2	Encoding apparatus and encoding method Provided is an encoding apparatus. A threshold value calculating unit (32) calculates a threshold value from a statistical amount of conversion factors of an extended band. A representative conversion factor extracting unit (33) uses the calculated threshold value to extract conversion factors having large amplitudes. If the number of extracted conversion factors does not reach a specified number, the threshold value calculating unit (32) determines, in accordance with a lacking number of conversion factors, an amount by which the threshold value should be lowered, and modifies the threshold value accordingly. The representative conversion factor extracting unit (33) uses the threshold value, which has been modified, to extract conversion factors. Such threshold value modification by the threshold value difference calculating unit (32) and such conversion factor extraction by the representative conversion factor extracting unit (33) are repeated until the number of extracted conversion factors reaches the specified number.
US09336783B2	Method and apparatus for performing packet loss or frame erasure concealment A method for performing packet loss or Frame Erasure Concealment (FEC) for a speech coder receives encoded frames of compressed speech information transmitted from an encoder. The method determines whether an encoded frame has been lost, corrupted in transmission, or erased, synthesizes properly received frames, and decides on an overlap-add window to use in combining a portion of the synthesized speech signal with a subsequent speech signal resulting from a received and decoded packet, where the size of the overlap-add window is based on the unavailability of packets. If it is determined that an encoded frame has been lost, corrupted in transmission, or erased, the method performed an overlap-add operation on the portion of the synthesized speech signal and the subsequent speech signal, using the decided-on overlap-add window.
US09336777B2	Speech processing device, speech processing method, and speech processing program A speech processing device includes a speech recognition unit configured to sequentially recognize recognition segments from an input speech, a reverberation influence storage unit configured to store a degree of reverberation influence indicating an influence of a reverberation based on a preceding speech to a subsequent speech subsequent to the preceding speech and a recognition segment group including a plurality of recognition segments in correlation with each other, a reverberation influence selection unit configured to select the degree of reverberation influence corresponding to the recognition segment group which includes the plurality of recognition segments recognized by the speech recognition unit from the reverberation influence storage unit, and a reverberation reduction unit configured to remove a reverberation component weighted with the degree of reverberation influence from the speech from which at least a part of recognition segments of the recognition segment group is recognized.
US09336776B2	Enhancing speech recognition with domain-specific knowledge to detect topic-related content Methods, systems, and computer-readable storage media for providing action items from audio within an enterprise context. In some implementations, actions include determining a context of audio that is to be processed, providing training data to a speech recognition component, the training data being provided based on the context, receiving text from the speech recognition component, processing the text to identify one or more action items by identifying one or more concepts within the text and matching the one or more concepts to respective transitions in an automaton, and providing the one or more action items for display to one or more users.
US09336774B1	Pattern recognizing engine Methods, systems, and apparatus, for pattern recognition. One aspect includes a pattern recognizing engine that includes multiple pattern recognizer processors that form a hierarchy of pattern recognizer processors. The pattern recognizer processors include a child pattern recognizer processor at a lower level in the hierarch and a parent pattern recognizer processor at a higher level of the hierarchy, where the child pattern recognizer processor is configured to provide a first complex recognition output signal to a pattern recognizer processor at a higher level than the child pattern recognizer processor, and the parent pattern recognizer processor is configured to receive as an input a second complex recognition output signal from a pattern recognizer processor at a lower level than the parent pattern recognizer processor.
US09336772B1	Predictive natural language processing models Features are disclosed for updating or generating natural language processing models based on information associated with items expected to be referenced in natural language processing input, such as audio of user utterances, user-entered text, etc. Natural language processing models may include, e.g., language models, acoustic models, named entity recognition models, intent classification models, and the like. The models may be updated or generated based on selected features of input data and a machine learning model trained to produce probabilities based on the selected features.
US09336768B2	Smartphone security masking enclosure The Mobile Phone/PDA Security Masking Enclosure is a sound insulated enclosure for use as a temporary storage location for cellular and other mobile devices in locations at which confidential and sensitive conversations and discussions are being conducted. A pink/white noise generating device within the enclosure generates a masking noise such that the cellular or other mobile devices inside the enclosure are unable to pick up or record conversations outside the enclosure.
US09336766B2	Musical performance device for guiding a musical performance by a user and method and non-transitory computer-readable storage medium therefor In the present invention, a CPU obtains in advance a loop period LP corresponding to the beat (minimum note length) of a musical piece from musical performance data. In a case where key pressing is not performed even when the key-press timing of a guided key is reached, the CPU sets a loop start point in musical-piece waveform data in accordance with the obtained loop period LP, and instructs a sound source to perform the loop replay of the musical-piece waveform data from the set loop start point to an end address.
US09336765B2	Pickup device A pickup device includes: a speed detector which is configured to detect speed of vibration of a soundboard of an acoustic musical instrument; and a signal generator which is configured to generate an audio signal from the speed detected by the speed detector and to output the audio signal.
US09336758B1	Drum having interchangeable drum shell segments A drum includes a drum shell having a first drum shell segment and a separate, second drum shell segment. The drum shell segments each including a hollow cylindrical member having a rim, a protrusion formed in an upper surface of the rim, and an annular groove formed in a lower surface of the rim. The protrusion of the first drum shell segment is received in the groove of the second drum shell segment so that the drum shell segments are in axially stacked relation. A first hoop mounts a first drum skin to the drum shell. Tensioning structure is constructed and arranged to removably secure the drum shell to the first hoop.
US09336757B2	Shoulder rest for violin/viola A shoulder rest structure for a violin and a viola is disclosed. The shoulder rest structure comprises a first body and a second body. The first body has a positioning piece in which the positioning piece has a first connecting part and a first counterpart connected to two ends thereof. The first connecting part connects at least one first adjustment piece; the first counterpart connects at least one second adjustment piece. The second body has a first side and a second side; the first side of the second body attaches to the first body correspondingly. By means of the ergonomic design of the present invention, the violin/viola practice is made more comfortable and the length of the shoulder rest can be adjusted by the user according to requirements.
US09336756B2	Chin rest, chin rest system and musical instrument Provided is a chin rest for a musical instrument, comprising a chin support, a holding device for holding the chin support on the musical instrument and at least one support foot via which the chin support supports itself on a top of the musical instrument, wherein the at least one support foot is releasably arranged on the chin support.
US09336754B2	Methods and apparatuses for controlling display refresh rate A method and an apparatus for controlling a display refresh rate of a display device are provided. The control method comprises: obtaining a display parameter of current display content of the display device; determining, based on the display parameter, whether a reduction condition of a display refresh rate is met, so as to obtain a first determination result; controlling the display device to reduce the display refresh rate from a first display refresh rate to a second display refresh rate, when the first determination result indicates that the reduction condition of the display refresh rate is met. The above schemes may collect automatically the display parameter of the current display content of the display device, and determine, depending on the display parameter, whether the display refresh rate needs to be reduced. When it is determined that the display refresh rate needs to be reduced, the display refresh rate will be automatically reduced. All of the processes may be completed automatically without participation of the user. This may significantly improve flexibility of adjusting the display refresh rate.
US09336752B1	Microprocessor including a display interface in the microprocessor A processing system is disclosed. The processing system comprises a first integrated circuit. The first integrated circuit includes a processor core, a display interface and memory controller coupled to a first bus interface. The display interface is adapted to display graphical information generated by a graphics engine. A graphics engine is not on the first integrated circuit. The processing system includes a second bus interface for allowing communication with the first integrated circuit via the first bus interface. The second bus interface is adapted to allow for communication to a graphics engine.
US09336749B2	Display device and means to measure and isolate the ambient light A display method and display device are described having at least one sensor for detecting a property of light such as the intensity, color and/or color point of light emitted from at least one display area of a display device into a viewing angle of the display device and to measure and isolate the contributions of ambient light. An advantage of the sensor system is that it can be used for real-time measurements, e.g. while the display device is in use, and off-line, e.g. when the normal display functionality is interrupted, with a high signal to noise ratio and simultaneously can isolate the contributions of the signals from the backlight of the display device and the signals from the ambient light.
US09336747B2	Display dimming to save mobile device power during webpage, web content, and device application loading Systems, methods, and apparatus are herein disclosed for controlling a display brightness based on user action or user interest in the display. In particular, the display brightness can be dimmed upon identification of a first marker indicative of a user action such as a request for a webpage. The brightness of the display can be increased or returned to its original state upon identification of a second marker indicative of completion of a user equipment activity triggered by the user action. In some embodiments, another brightness state between these two can be used as an intermediary and is triggered when a third marker, indicative of a progression of the user equipment activity, is identified.
US09336746B2	Image display device and control method thereof An image display device is provided in which a difference in color appearance between visual angles can be reduced. The image display device includes: a light-emitting unit including a first light source configured such that a peak wavelength of a spectral spectrum of the light source is within a wavelength region in which a difference between color matching functions of different visual angles is small and a second light source that differs from the first light source; a control unit configured to switch a light source to be lighted to one of the first light source and the second light source based on an instruction; and a display panel that is illuminated by the light-emitting unit.
US09336743B2	Video signal transmitting apparatus and video signal receiving apparatus An interface is realized that can prevent video signals from being copied easily and which uses a luminance/color difference signal transmission scheme with an excellent harmony with a television circuit. In a video transmission using a digital interface, colorimetry information for defining the conversion from the luminance/color difference signal into a primary color signal and video aspect ratio information are transmitted along with the luminance/color difference type video signal. This allows reproduction of video with high quality and high resolution and also realizes a copyright protection which allows only the users authorized by key information to use the content of the video. With this transmission scheme, it is possible to provide a transmitting apparatus, a receiving apparatus and an interface which highly harmonize with a rationalized television-based circuit.
US09336738B2	Display controller configured to maintain a stable pixel writing period and a gate slope period when a refresh rate is changed, display device, and control method for controlling display system and display device In one or more example embodiments, a display controller includes a stable pixel writing period in one horizontal period in a display device, the stable pixel writing period being a period during which a voltage outputted from a gate driver is at a high level. The display controller also includes a first stable pixel writing period determination circuit which determines, by using a reference signal independent from the frame rate in the display device, the stable pixel writing period during which the voltage is at the high level. Thus, the display controller can be provided in which, regardless of whether and how the frame rate is changed, the stable pixel writing period can be of a target length.
US09336736B2	Liquid crystal display device and method for driving auxiliary capacitance lines Provided is a liquid crystal display device with reduced power consumption employing a CS drive method.A CS driver (500) consists of a CS shift register (510) and a CS output portion (520). The CS shift register (510) outputs control signals (COUT(1) to COUT(m)) in accordance with a CS clock signal CCK. The CS output portion (520) outputs auxiliary capacitance signals (CSS(1) to CSS(m)) in accordance with the control signals (COUT(1) to COUT(m)), respectively. An idle period (T2) is set following a scanning period (T1). During the idle period (T2), the CS driver (500) is driven in accordance with the CS clock signal (CCK) at an idle-period CS frequency (fcck2). The idle-period CS frequency (fcck2) is lower than a scanning-period CS frequency (fcck1).
US09336735B2	Display device The plurality of stages of circuit blocks of a driver circuit in a display device include a first transistor and a second transistor. The first transistor is connected at its gate with a first node and controls conductivity between a scanning signal line and a first clock signal line applied with a first clock signal. The first node is at an active potential when at least any one signal of signals output from one stage in each of a forward direction and a reverse direction is at the active potential. The second transistor is connected at its gate with the first node and controls conductivity between the first clock signal line and an input signal line of another stage of circuit block.
US09336733B2	Display apparatus and driving device for displaying A liquid crystal display system including: a liquid crystal display panel for displaying image data; a semiconductor device including a display driving circuit configured to drive the liquid crystal display panel, said display driving circuit having a function of generating gray scale voltages based on a gamma characteristic curve, said display driving circuit including: an interface circuit coupled to plurality of external terminals for inputting a first, second and third value which define the gamma characteristic curve; a first register configured to store the first value that adjusts an amplitude of the gamma characteristic curve; a second register configured to store the second value that adjusts a gradient of the gamma characteristic curve; a third register configured to store the third value making a micro adjustment of the gamma characteristic curve; and a generation circuit configured to generate the gray scale voltages based on the gamma characteristic curve.
US09336730B2	Drive method for an electrophoretic display device and an electrophoretic display device A drive method for an electrophoretic display device that has an electrophoretic device composed of a suspension fluid containing electrophoretic particles disposed between a common electrode and pixel electrodes is provided. No holding electrode is necessary. A driver drives the electrophoretic device by applying voltage between the common electrode and the pixel electrodes, and a controller controls the driver. The method involves redrawing the display to change the displayed image by applying to the common electrode pulse trains of different widths, each composed of a first potential and a second potential, at different times, based on certain conditions.
US09336728B2	System and method for controlling a display backlight In one embodiment, a backlight controller for a zoned backlight display includes a processor having a brightness value output. The processor is configured to provide a brightness value for at least one brightness zone of the display based on a target brightness value for the at least one zone, a past brightness value of the at least one zone, and a brightness time response.
US09336727B2	Driving method of display device An object is to reduce crosstalk between consecutive frame periods. The writing period of image signals to each pixel and the lighting period of light sources corresponding to the image signals in one frame period are rearranged so that the lighting period of the light sources corresponding to the image signals does not overlap with a previous frame period and the next frame period, and the image signals are written and the light sources corresponding to the image signals are on. Specifically, a display region is divided into a plurality of regions, and each of the plurality of regions is divided for rows in a first half and rows in a latter half. The image signals written to the rows in the latter half are written in the previous frame period, and the light sources corresponding to the image signals are on in the frame period.
US09336725B2	Electronic device, display controlling apparatus and method thereof There are provided an electronic device and a display controlling apparatus and method. The display controlling apparatus that is driven in a paper mode and includes a backlight includes an image processing device that first converts a gradation value of an input image so as to have image characteristics of the paper mode, and second converts the first converted gradation value of the input image so as to have a upper limit gradation value is scaled up to the maximum gradation value, and a backlight brightness determining unit that determines brightness of light irradiated by the backlight to be lowered in response to the second conversion of the gradation value.
US09336721B2	Display apparatus and display-apparatus driving method Disclosed herein is a driving method and display apparatus, the display apparatus including light emitting units, scan lines, data lines, a driving circuit provided for each of the light emitting units to serve as a circuit having a signal writing transistor, a device driving transistor, a capacitor and a first switch circuit, and a light emitting device.
US09336719B2	Pixel circuit and display device, and a method of manufacturing pixel circuit The display device including a pixel circuit has a first line, a transistor, a light emitting element, and a second line. The transistor is located between the second line and an electrode of the light emitting element. Either the first line or the second line is wired in a region that overlaps a light emitting region of the light emitting element in a lamination direction of layers. The second line intersects the first line outside of the light emitting region and overlaps a non-light emitting region of the light emitting element.
US09336718B2	Display device and method for driving same In a pixel circuit, during a period during which an organic EL element is not emitting light, a transistor is in an “on” state and a reverse-direction voltage determined by a reverse-direction current that depends on the degree to which degradation of the organic EL element has progressed is written to a capacitor. The transistor then turns off, another transistor turns on, and a compensating current that depends on the reverse-direction voltage flows from another capacitor towards a reverse-biasing power-supply line, causing a drive voltage maintained by the capacitor to change by a compensating voltage change. This makes it possible to minimize decreases in the emission luminance of an electro-optical element such as an organic EL element due to degradation thereof over time.
US09336717B2	Pixel circuits for AMOLED displays A system for controlling a display in which each pixel circuit comprises a light-emitting device, a drive transistor, a storage capacitor, a reference voltage source, and a programming voltage source. The storage capacitor stores a voltage equal to the difference between the reference voltage and the programming voltage, and a controller supplies a programming voltage that is a calibrated voltage for a known target current, reads the actual current passing through the drive transistor to a monitor line, turns off the light emitting device while modifying the calibrated voltage to make the current supplied through the drive transistor substantially the same as the target current, modifies the calibrated voltage to make the current supplied through the drive transistor substantially the same as the target current, and determines a current corresponding to the modified calibrated voltage based on predetermined current-voltage characteristics of the drive transistor.
US09336716B2	Organic light emitting display An organic light emitting display includes a scan driving unit applying scan signals and light emitting control signals through a plurality of scan lines and light emitting control lines, a data driving unit applying data signals through a plurality of data lines, a power supply supplying an electric power to a plurality of power supply entries, a pixel unit including a plurality of pixels receiving the plurality of scan signals, light emitting control signals, data signals, and the electric power to display an image, the pixel unit being divided into a plurality of regions corresponding to the plurality of power supply entries, and a current limiting circuit using data current values accumulated region by region in the plurality of regions to output current limiting signals for limiting brightness of the pixel unit.
US09336707B2	Gamma voltage supply device and display device using the same A display device includes a display unit, a gamma voltage generator, a gamma voltage unit, a data driver, and a timing controller. The display unit includes pixels emitting light according to data signals supplied through data lines. The gamma voltage generator is configured to generate a first set of reference gamma voltages, and to supply the first set of reference gamma voltages to a gamma voltage unit. The gamma voltage unit is configured to generate gamma voltages using the first set of reference gamma voltages and a second set of reference gamma voltages, and to supply the generated gamma voltages to a data driver. The data driver is configured to generate the data signals using the generated gamma voltages, and to supply the generated data signal to the data lines. The timing controller is configured to control the data driver according to an image signal.
US09336706B2	Organic light-emitting diode (OLED) display and method for driving the same An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a plurality of pixels, a luminance measuring unit, a current measuring unit, and a compensation data generator. The luminance measuring unit measures the luminance of each pixel and generates luminance information corresponding to the measured luminances. The current measuring unit measures the current output from each pixel and generates current information corresponding to the measured currents. The compensation data generator generates compensation data including a compensation value for each pixel based on the luminance information and/or the current information.
US09336705B2	Self-luminous display device, control method of self-luminous display device, and computer program Provided is a self-luminous display device including a data calculation section configured to calculate, by using a supplied video signal, data relating to a luminance amount accumulated in a unit of a first block in a target region for luminance control in a screen on which a plurality of pixels are arranged in a matrix, each of the pixels including a light emitting element which emits light by itself according to a current amount, a resampling section configured to resample the data relating to the luminance amount in the target region, in a unit of a second block, the data relating to the luminance amount being calculated by the data calculation section, the second block being larger than the first block, and a scaling section configured to generate data for luminance control in the target region by scaling the data resampled by the resampling section.
US09336704B2	Apparatus and method for powering LED driver A driver circuit for an LED display panel has a first constant current driver to drive green LEDs, a second constant current driver to drive blue LEDs, and a third constant current driver to drive red LEDs. The driver circuit also has an analog power module electrically coupled to the first, the second, and the third constant current drivers. The analog power module has two or more power sources. The driver circuit further includes a digital controller for transmitting digital control signals to the analog driver. The digital controller is powered by a digital power module.
US09336701B2	Method of driving a pixel circuit A pixel circuit includes an organic light emitting diode, a first PMOS transistor coupled between a first power voltage and an anode electrode of the organic light emitting diode, a second PMOS transistor coupled between a first node and the anode electrode of the organic light emitting diode, a first capacitor coupled between a second node and the first node, a second capacitor coupled between the first power voltage and the second node, a third PMOS transistor coupled between a data line and the second node, a fourth PMOS transistor coupled between a third node and the second node, a third capacitor coupled between the third node and a gate terminal of the third PMOS transistor, and a fifth PMOS transistor coupled between the data line and the third node.
US09336699B2	Illuminated sign apparatus A sign apparatus includes a front display panel and a solid halo panel that are illuminated by a light module. The front display panel is arranged along one side of a frame and the solid halo panel is arranged on the other side of the frame. The light module is disposed within the frame between the front display panel and the solid halo panel. The solid halo panel follows a contour of the front display panel and extends beyond a periphery of the front display panel such that the solid halo panel forms a halo border along the periphery of the front display panel when viewed from a direction toward the front display panel.
US09336698B2	Flashing LED message box A message box for presenting messages, such as advertising material to target consumers. The message box is suitable for being integrated into existing infrastructure. Further, the message box includes an electronic illumination source that can be pulsed on or off, and at varying intensity levels so as to maximize or increase the ability to attract the attention of the target consumers. Other controls can be applied in operation of the illumination sources so as to create additional attractions to target consumers. The messages can be manually or automatically changed.
US09336693B2	Wearable partial task surgical simulator A wearable device for simulating wounds and injuries received during a trauma event includes a raiment and vest for covering the torso of a person. The raiment has an outer surface with a color and a texture comparable to human skin. Mounted on the outer surface is at least one wound simulator formed with an orifice that is in fluid communication with a fluid reservoir. Thus, the person can selectively expel a blood-like fluid from the reservoir, and through the wound simulator orifice, to simulate a trauma event. The vest includes an artificial rib cage and prosthetic internal organs juxtaposed with at least one wound simulator to simulate internal effects of a trauma event.
US09336684B2	Travelling vehicle system and method for controlling travel of travelling vehicle in curved section A ground controller in a travelling vehicle system stores travel permissions for a curved section that are provided to travelling vehicles, and deletes the travel permissions when the travelling vehicles leave the curved section. When a request for a permission to travel in the curved section is received from a travelling vehicle, the ground controller references the memory, provides a first travel permission if a permission to travel has not been provided to another travelling vehicle, and provides a low-order travel permission that permits travel with a lower speed than the first travel permission if a permission to travel has been provided to another travelling vehicle.
US09336683B2	Travel distance measurement device A travel distance measurement device includes a transmitting antenna that is disposed in a vehicle and emits a transmission signal, as a radio wave, toward a ground surface, a receiving antenna that is disposed in the vicinity of the transmitting antenna, and receives a radio wave reflected from the ground surface and acquires a reflection signal, a distance calculator (an IQ demodulator and a phase conversion integrator) that calculates the travel distance of the vehicle on the basis of the acquired reflection signal, a gyro sensor that measures a predetermined parameter regarding curve traveling of the vehicle, and a correcting operation unit that corrects the calculated travel distance on the basis of the measured parameter.
US09336679B1	Measuring traffic condition based on mobile devices connection information Systems and methods for measuring traffic condition based on mobile device connection information are provided. An example method includes, at a computer system having one or more processors and memory storing one or more programs for execution by the one or more processors: identifying, in a plurality of geographical areas, a first geographical area; selecting, in a plurality of cellular towers, a first cellular tower providing cellular coverage to the first geographical area; determining a first total number of cellular signal pings received by the first cellular tower over a first predefined time period; estimating a traffic volume factor for the first geographical area in accordance with the first total number of cellular signal pings; and providing traffic condition associated with the first geographical area to a user, in accordance with the traffic volume factor.
US09336669B2	Tamper evident point of containment, inventory and accountability system and method The system in at least one embodiment includes a tamper evident specimen sample locking device that in a further embodiment includes an embedded data storage mechanism. A method for using the system in at least one embodiment allows for efficiently and securely creating, maintaining, identifying, tracking, and controlling inventories (either prospective or retrospective) of biological and chemical sample containers and their contents, while eliminating potential loss and degradation associated with handling the samples. The system in at least one embodiment includes a sample container tray or cryogenic box having one or more integrated RFID readers within an associated smart lid that sense RFIDs associated with the individual samples thereby eliminating the need to remove, visually inspect, and/or handle the samples.
US09336667B2	Electronic mailbox system An electronic mailbox system features: a mailbox housing with an inner cavity and slot for holding mail, a lid, an electrically-operable lock system for the lid, a mail sensor for detecting the mail being inserted into the slot, a first transmitter, a first receiver and a mailbox microprocessor; and a control box with a second transmitter, a second receiver, a control box indicator light, an unlock button, a reset button, and a control box microprocessor. When the mail sensor detects mail delivery the control box indicator light becomes illuminated. When the unlock button is pushed the lock system unlocks. When the reset button is pressed the indicator light is deactivated. An alarm system may be activated upon receipt of mail and/or if a tamper sensor detects tampering. Another embodiment features control and monitoring of the mailbox via a mobile consumer electronics device, as a smart phone or tablet.
US09336666B2	Corner sensor assembly A corner sensor assembly includes a housing having at least one magnet attached thereto, wherein the magnets allow the corner sensor assembly to be readily attached and relocated to corner structures within a building. The assembly includes at least one motion sensor for detecting motion within two opposing fields of monitoring. At least one visual indicator is activated when the motion sensors detect motion within both fields of monitoring and are deactivated when no motion is sensed in at least one of the fields of monitoring. The assembly includes an integrated power supply located within the housing.
US09336662B1	Method and apparatus for visually and audibly indicating the setup and maintenance of a system Example embodiments of the present invention relate to a method and apparatus for visually and audibly indicating the setup and maintenance of a system.
US09336661B2	Safety communication system and method thereof Disclosed are a safety communication system and a method thereof that provide a risk occurrence position and a notification function, and more particularly, disclosed is communication technology including a sensor based lighting for rapidly responding to a risk situation. The safety communication system according to an exemplary embodiment of the present invention includes: a device sensing a risk situation; a lighting crime prevention system analyzing risk situation data received from the device and including a position ID to generate situation data; and a lighting control system controlling an operation of a lighting depending on the situation data.
US09336657B2	Side bet option for blackjack In additional to a conventional bet in Blackjack, the player also may make a side bet. The game may be played on a video gaming machine or on-line. For the side bet game, if the player obtained the card combination of either 6:7, 6:8, or 7:8, in any order and any suit, on the two cards initially dealt, the player wins 10 times the side bet. The Blackjack game then continues in the normal manner until completed. If the player receives 6:7:8 with three cards, the player also wins an enhanced prize for the side bet. If, in the next Blackjack game, the player also obtains either 6:7, 6:8, or 7:8, an enhance side bet prize is awarded.
US09336656B2	Multilayer hybrid games Systems and methods in accordance with embodiments of the invention operate a multilayer hybrid game including: a gambling game; a multilayer entertainment game that triggers at least one wager in the gambling game to the gambling game and provides outcomes at a plurality of gameplay layers, where: players at a same gameplay layer are engaged in gameplay subject to the same standards for gameplay progression and utilization of gameplay resources; where the game world engine utilizes a multilayer module constructed to: detect at least one player action responsive to gameplay within a first gameplay layer of the plurality of gameplay layers; determine a gameplay impact for at least one player at a second gameplay layer in response to the detection of the at least one player action; and apply the gameplay impact to the gameplay of at least one player at the second gameplay layer.
US09336654B2	Gaming system and method for dynamically grouping gaming devices to provide progressive awards A gaming system enables players of a group of gaming devices to wager on progressive or other awards for that group and tracks an amount of player activity at the group. If player activity of the group exceeds an upper reconfiguration threshold, the gaming system disassociates one or more gaming devices from the group to reduce the amount of player activity. If the player activity of the group falls below a lower reconfiguration threshold, the gaming system associates one or more additional gaming devices with that group to increase player activity. Reallocation of gaming devices can occur following a player winning the award for the group. The system can incrementally increase an award reset amount, while reducing the odds of winning the award, to maintain a desired range of gaming experiences. The system can also enable a player to select an initial groups based on a characteristic of that player.
US09336652B2	Wagering game system with player awards for modifying game contents A gaming system includes one or more processors and one or more memory devices storing instructions that, when executed by at least one of the one or more processors, cause the gaming system to perform a plurality of operations. The operations include awarding a plurality of points to a player, and, in response to a predetermined number of the points being redeemed by the player, accessing or modifying wagering game content.
US09336642B2	Shared-use bicycle systems This disclosure is directed to bicycle storage systems and, in particular, to shared-use bicycle systems. Several embodiments herein are directed to a shared-use bicycle system, comprising a bicycle having a locking device and an accessory-receiving area. The locking device can extend horizontally from the bicycle, and the accessory-receiving area being positioned below the locking device. The shared-use bicycle system also comprises a bicycle rack having a horizontally-extending rigid member with at least one opening thereon to receive the locking device of the bicycle in a secured manner. When the bicycle is received in the at least one opening of the bicycle rack in the secured manner, access to the accessory-receiving area of the bicycle is restricted by the horizontally-extending rigid member.
US09336641B2	Authentication apparatus and method An authentication apparatus operative to determine the authenticity of an item comprising a film substrate responsive to detection that a portion of said item located in a measuring region of said apparatus has a predetermined birefringence characteristic, said apparatus comprising: an item detection arrangement operative to determine if at least a portion of an item is located in a measuring region of said authentication apparatus; and an optically-based birefringence measuring apparatus, wherein said authentication apparatus is operative to compare a measured birefringence characteristic with a predetermined birefringence characteristic and to produce an authenticity signal indicative of authenticity or otherwise of said item based upon said comparison, said apparatus further comprising a control means operative to control output of said authenticity signal from said apparatus responsive to determination, by said item detection arrangement, of presence or otherwise of said at least a portion of said item in said measuring region.
US09336634B2	Hand geometry biometrics on a payment device The present invention discloses a system and methods for biometric security using multiple biometrics in a transponder-reader system. The biometric security system also includes a biometric sensor that detects biometric samples and a device for verifying biometric samples. In one embodiment, the biometric security system includes a transponder configured with a biometric sensor. In another embodiment, the system includes a reader configured with a biometric sensor. In yet another embodiment, the present invention discloses methods for proffering and processing multiple biometric samples to facilitate authorization of transactions.
US09336633B2	Security control access system An access control system for controlling access to an enclosed area, the access control system comprising a radio-frequency communication module configured to receive a card identification signal, a mode module configured to determine an operational mode of the access control system, the operational modes including a standalone mode and a network mode, a communication module configured to authenticate the card identification signal by transmitting the card identification signal to an access control server when the access control system is determined to be operating in the network mode, a local authentication module configured to authenticate the card identification signal against entries of one or more internal tables stored in the access control system when the access control system is determined to be operating in the standalone mode, and a local input/output module configured to send a signal to unlock a door at an entrance to the enclosed area when the card identification signal has been successfully authenticated.
US09336630B2	Method and apparatus for providing augmented reality A method and apparatus for providing augmented reality are provided and include a controller that is configured to match a head up display area of a windshield and an input image and determine an area in which an information amount is a minimum in the matched image as a position of a display window to display virtual information. In addition, the controller is configured to output virtual information at the determined position.
US09336628B2	Systems and methods involving surface fitting Systems and methods involving surface fitting are provided. In this regard, a representative method includes: receiving information corresponding to discrete data points of a portion of a surface; determining curvature estimates associated with the data points prior to performing curve fitting with respect to the data points; identifying curvature shock based on the curvature estimates, the curvature shock being defined as a curvature threshold corresponding to an absolute value of curvature between adjacent data points; breaking C2 continuity between adjacent data points exhibiting curvature shock; and performing surface fitting with respect to the data points to generate Non-Uniform Rational B-Splines (NURBS) data such that breaks in the C2 continuity associated with curvature shock are maintained in the NURBS data.
US09336624B2	Method and system for rendering 3D distance fields A method and system renders a 3D model of a 3D object as an image including image samples. The 3D model is a distance field, and the distance field includes surface cells representing portions of a surface of the 3D object. A set of image samples in the image is determined in an object-order phase for each surface cell. Each surface cell is then processed independent of other surface cells. The processing casts a ray, in an image order phase from each image sample in the set of image samples, through the surface cell to determine a contribution of the surface cell to the image sample, and then the image is rendered.
US09336623B2	Multilevel display control list in tile based 3D computer graphics system A method and apparatus are provided for rendering a 3 dimensional computer graphics image. The image is divided into plurality of rectangular tiles which are arranged in a multi level structure comprising a plurality of levels of progressively larger groupings of tiles. Image data is divided into a plurality of primitive blocks and these are assigned to groupings of tiles within the multi level structure in dependence on the groupings each one intersects. Control stream data is derived for rendering the image and this comprises references to primitive blocks for each grouping of tiles within each level of the multi level structure, the references corresponding to the primitive blocks assigned to each grouping and control stream data is used to render the primitive data into tiles within the groupings of tiles for display. This is done such that for primitive blocks which intersect a plurality of tiles within a grouping, control stream data is written for the grouping of tiles rather than for each tile within the grouping.
US09336619B2	Method and apparatus for generating photograph image The present disclosure relates to a method and an apparatus for generating a photograph image. The method includes: measuring an illumination value, acquiring a plurality of source images used to generate one final image, generating a set final image either by selecting one source image with best quality among the plurality of acquired source images, or by combining the plurality of acquired source images, based on the measured illumination value. The present disclosure allows to acquire a clear and bright photograph image in a low-light environment.
US09336607B1	Automatic identification of projection surfaces Techniques are described for identifying suitable surfaces within a room upon which visual content may be displayed. One or more images of the room are obtained and used to identify planar surfaces. The images may also be analyzed to determine the visual textures of the surfaces within the room. Suitable projection surfaces may then be selected from the identified planar surfaces, based on the visual textures of the planar surfaces.
US09336605B2	Medical imaging system, computer-implemented method, and computer program product for identifying a treated region in a medical image A medical imaging system (900, 1000, 1100, 1200) for acquiring medical image data (930), the medical imaging system comprising: a tissue treating system (910, 1080, 1180, 1190, 1280, 1290) for treating a target volume (908); a computer system (918) comprising a processor (922), wherein the computer system is adapted for controlling the medical imaging system; and a memory (928) containing machine readable instructions (954, 956, 958, 962, 964, 966, 968, 970, 972, 974). Execution of the instructions cause the processor to: acquire (100, 200, 308) medical image data; reconstruct (102, 202, 310) a medical image (932) using the medical image data; receive (104, 204, 312) an image segmentation seed (600, 934) derived from a treatment plan (936), and identify (106, 210, 314) a treated volume (400, 700, 800) in the medical image by segmenting the medical image in accordance with the image segmentation seed.
US09336598B2	Shape-extraction method and shape-extraction system An unknown surface shape of a physical object can be extracted with good precision. Image data of a projective image that has been acquired by radiation projection to an object is acquired. Next, a predetermined mesh structure is used to acquire cross-sectional images of the subject from image data of the projective images by reconstruction using tomography. Lattice points constituting the mesh structure are then moved in conformity with the surface shape of the object, based on the cross-sectional image that has been acquired by reconstruction. Reconstruction is carried out again using the mesh whose lattice point positions have been corrected. Movement on the reconstruction of the lattice points is then repeated as many times as required.
US09336597B2	System and method for determining the three-dimensional location and orienation of identification markers A three-dimensional position and orientation tracking system comprises one or more pattern tags, each comprising a plurality of contrasting portions, a tracker for obtaining image information about the pattern tags, a database with geometric information describing patterns on pattern tags; and a controller for receiving and processing the image information from the tracker, accessing the database to retrieve geometric information, and comparing the image information with the geometric information. The contrasting portions are arranged in a rotationally asymmetric pattern and at least one of the contrasting portions on a pattern tag comprising a perimeter with a polygonal shape. The pattern tags may be borne on tracking markers that have a three-dimensional shaped surface. The tracking system can be implemented in a surgical monitoring system in which the pattern tags are attached to tracking markers or are themselves tracking markers. A method associated with the system employs the rotationally asymmetric patterns on the tags to determine the three-dimensional locations and orientations of items bearing the tags using non-stereo image information.
US09336594B2	Cardiac pulse rate estimation from source video data What is disclosed is a system and method for estimating cardiac pulse rate from a video of a subject being monitored for cardiac function. In one embodiment, batches of overlapping image frames are continuously received and processed by isolating regions of exposed skin. Pixels of the isolated regions are processed to obtain a time-series signal per region and a physiological signal is extracted from each region's time-series signals. The physiological signal is processed to obtain a cardiac pulse rate for each region. The cardiac pulse rate for each region is compared to a last good cardiac pulse rate from a previous batch to obtain a difference. If the difference exceeds a threshold, the cardiac pulse rate is discarded. Otherwise, it is retained. Once all the regions have been processed, the retained cardiac pulse rate with a minimum difference becomes the good cardiac pulse rate for comparison on a next iteration.
US09336593B2	Methods for automated tissue sample processing and imaging Methods are provided for performing automated digital processing of a tissue sample. A tissue sample that is to be processed to produce a three-dimensional representation of the tissue sample is received, and is aligned with a cutting mechanism that comprises a blade. A plurality of sections of the tissue sample are produced by way of a rotating blade. The sections are moved from a first location to a second location on a surface of a transporting mechanism. During this move, electronic images of the each of the sections are captured using image capturing devices. The images for the each of the sections are compiled to generate a composite image for the each of the plurality of sections. The composite images are used to generate the three-dimensional representation of the tissue sample.
US09336590B2	Advanced fiber tracking and medical navigation in a brain A method for finding fibers in image data of a brain, comprising the steps of: matching (S2) a functional atlas of the brain to an image data set which represents a medical image of the brain; performing functional atlas segmentation (S3) in order to segment the image data set into functional areas; using (S4, S8) the segmented image data set to determine at least one seed point for a fiber tracking algorithm; and - performing (S5) fiber tracking in order to find the fiber.
US09336587B2	Semiconductor circuit pattern measuring apparatus and method Included is a multiple resolution image generating unit which applies a plurality of noise removing filters to a semiconductor circuit pattern image and generates a multiple resolution image, a multiple resolution differential image generating unit which generates a multiple resolution differential image from a difference of images between hierarchies of the multiple resolution image, and a contour extracting unit which extracts a contour of the semiconductor circuit pattern based on an intensity signal of the semiconductor circuit pattern image. The contour extracting unit calculates an intensity signal level upon extracting a contour of the semiconductor circuit pattern from the multiple resolution image by using an image signal of the multiple resolution differential image, and extracts a contour of the semiconductor circuit pattern based on the calculated intensity signal level.
US09336586B2	Image processing apparatus and image processing method using compressed image data or partial image data Provided is an image processing apparatus capable of viewing even a characteristic portion of an inspection object even if partial image data of the inspection object is used for inspection. The image processing apparatus includes: an imaging portion for imaging an inspection object; a compression processing portion for executing compression processing on image data captured by the imaging portion, to generate compressed image data; and an image processing portion for executing image processing for an inspection. The image processing portion generates partial image data as part of the captured image data, and accepts a selection of any of the compressed image data and the partial image data as the image data for use in the image processing. The image processing portion executes the image processing for the inspection by use of the compressed image data or the partial image data, the selection of which has been accepted.
US09336585B2	Method and system for drafting a map for a “tube-sheet” A tester and a method that evaluate the condition of a bundle of plurality of tubes are disclosed. Embodiments of the tester obtains an image of a tube-sheet of the bundle; obtaining one or more parameters related to the tube-sheet image. Next one or more feature-detecting methods can be implemented on the tube-sheet image to define tube endings on a grid of the tube-sheet. Further, optimization methods can be implemented on the results and a map with the result can be presented to a user of the tester. Feedback from the user can be utilized to improve the map of the tube sheet.
US09336581B2	Method for correcting gradations and device or method for determining threshold of epsilon filter An object is to correct gradations in such a manner that both halo reduction effect and Retinex calculation effect are satisfied. Each JND value corresponding to each obtained luminance value to be assigned to each unit gradation of a panel is obtained. A pixel value corresponding to the each JND value is obtained for each of the unit gradations of the panel. A threshold ε is obtained by inverse gamma-correcting the ratio between discernible JND values corresponding to the unit gradations of the panel and the maximum output value of the panel. Linear function-based approximations are obtained using least squares. The threshold ε is determined as an increasing function of a pixel value on the basis of the allowable number of JND steps. The threshold ε is changed using this function. The threshold ε can be changed according to the center pixel value.
US09336580B2	Methods and apparatuses for image processing Methods and apparatuses for image enhancement are provided, with which convolution operations can be carried out directly in a filter space, for example in a wavelet space, in particular directly on compressed data.
US09336577B2	Image processing apparatus for removing haze contained in still image and method thereof An image processing apparatus for removing haze from an image includes a haze brightness measurer, a transmission estimator and an image reconstructor. The haze brightness measurer is configured to measure haze brightness in the image. The transmission estimator is configured to estimate a blockwise transmission based on a final cost function value calculated by a contrast and an image loss of the image, and to estimate a pixelwise transmission by using the blockwise transmission. The image reconstructor is configured to generate a reconstructed image by using the haze brightness and the pixelwise transmission.
US09336564B2	GPU enabled database systems Methods for resolving a number of in-memory issues associated with parallel query execution of a database operation on a database utilizing a graphics processing unit (GPU) are presented including: tying a table choice to a number of accesses per second made to a table; and synchronizing threads in a same shared GPU multiprocessor to avoid compromising concurrency, and where the parallel query execution of the database operation is performed solely by the GPU. In some embodiments, methods further include storing data from the GPU to a disk to solve volatility; and enabling a user, at any time, to query the amount of memory being used by the table created by the user to monitor memory consumption.
US09336562B2	Method of compressing and recovering compressed data based on detecting a maximum and minimum data cell value A data processing method that includes: detecting a maximum data cell having a maximum value and a minimum data cell having a minimum value in a compression unit cell; converting the maximum data cell and the minimum data cell into a non-compressed data format; converting remaining data cells of the compression unit cell except for the maximum and minimum data cells into a compressed data format; and generating stream data in which the converted data cells are arranged, wherein the non-compressed data format and the compressed data format include a header field with different values and the non-compressed data format includes a data field corresponding to the value of the converted maximum or minimum data cell.
US09336561B2	Color buffer caching A color buffer cache may be implemented in a way that reduces memory bandwidth. In one embodiment this may be done by determining whether a corresponding tile being rendered is completely inside a triangle. If so, the cache lines that correspond to this tile may be marked as “less useful”. As a result of being marked as less useful, those cache lines may be replaced before other cache lines in one embodiment. Thus a color buffer cache is used for those tiles that overlap with at least one triangle edge. The use of such a color buffer cache scheme may be more efficient and therefore may reduce memory bandwidth in some embodiments.
US09336547B2	Integrating local products into global web services Systems and methods are disclosed herein for integrating locally carried products into web services provided by a global server. A user computing device, such as a mobile phone, is used to scan optical codes for products. A product identifier extracted from the optical code is used to request product information from a global server system with respect to the product or to take an action with respect to the product, such as adding the product to an electronic shopping cart. For locally carried products, notice may be provided to the user computing device to scan the product using an in-store scanner. Upon scanning the optical code, the in-store scanner retrieves product information from a local server system and encodes this information in an optical code, which the user computing device scans in order to use with respect to a web service or web-integrated transaction.
US09336546B2	Recommendation system with multi-dimensional discovery experience Example apparatus and methods perform matrix factorization (MF) on a collaborative filter based usage matrix to create a multi-dimensional latent space that embeds users, items, and features. A full distance matrix is extracted from the latent space. The full distance matrix may be extracted from the latent space by defining a distance metric between item pairs based on the multi-dimensional representation in the latent space. The full distance matrix may be populated with values computed for item pairs using the distance metric. A plurality of vectors associated with a multi-dimensional Euclidean space are produced from the full distance matrix. The plurality of vectors produce a navigable data set. The plurality of vectors may be produced in a manner that minimizes strain on the distances vectors. A representation of the navigable data set may be presented as, for example, a virtually traversable landscape that supports an interactive user experience.
US09336544B2	On-device offline purchases using credits This is directed to providing offline purchasing of media items using an electronic device. One or more media items that are not part of a user's media library can be stored on an electronic device. When a user later wishes to play back one of the media items, but the device cannot connect to a communications network to provide payment information for purchasing the media items, the electronic device can use pre-paid credits that were purchased and stored by the device when a communications network was available to complete the purchase. By using pre-paid credits, the media store can be assured that the user has sufficient funds for the media item purchase.
US09336541B2	Augmented reality product instructions, tutorials and visualizations In a system for augmented reality product instructions, tutorials and visualizations a method may include receiving a request for information from a client device, the request including image data and a request type; converting, using at least one processor, the image data into a digital fingerprint; comparing the digital fingerprint to a plurality of stored fingerprints to identify an object in the image data; and generating an augmented reality view of the identified object based on the request type; and transmitting the augmented reality view to the client device.
US09336539B2	Systems and methods for providing advertising services in a predictive manner to devices with an advertising exchange Methods and systems are described for providing advertising services in a predictive manner to a device with an advertising exchange. In one embodiment, a system receives a configuration call from a device upon initiation of a software application and associated advertising services software on the device. The system generates, prior to a predicted ad play event on the device, a predictive ad request for obtaining at least one advertisement (ad) from at least one of an ad store and an advertising exchange prior to the predicted ad play event.
US09336535B2	Neuro-response data synchronization An example system includes a headset to gather first data comprising first neuro-response data and second neuro-response data from a user while the user is exposed to stimulus material. In the example system, the headset comprises a first sensor to gather the first neuro-response data, the first neuro-response data comprising at least one of electroencephalographic data or magnetoencephalographic data, and a second sensor to gather the second neuro-response data, the second neuro-response data comprising facial emotion encoding data. The headset also comprises a processor to synchronize the first neuro-response data, the second neuro-response data and the stimulus material to generate synchronized data and determine an effectiveness of a portion of the stimulus material based on the synchronized data.
US09336534B2	Geofenced event-based fan networking: systems The present invention is a fan networking system (FNS), available through a software application, executing on fans' portable smart devices for an event to be held in a venue. A FNS may offer event-customized services to fans, such as messaging, fan groups, mementos, coupons, “friends”, and contests. The level of services might depend on whether a fan is attending; timing (pre-, during, post-performance); for a competitive event, whether the fan affiliates with the home or away team; and the category of fan (e.g., audience, management, performer). Determination of whether a fan is attending may be done with geolocation services, e.g., through GPS. A fan might need to remain within the venue for some period of time to qualify as attending. Services to attending fans may extend for a period beyond the event itself.
US09336533B2	Systems, methods, and apparatuses for implementing a similar command with a predictive query interface Disclosed herein are systems and methods for implementing a SIMILAR command with a predictive query interface including means for generating indices from a dataset of columns and rows, the indices representing probabilistic relationships between the rows and the columns of the dataset; storing the indices within a database of a host organization; exposing the database of the host organization via a request interface; receiving, at the request interface, a query for the database specifying a SIMILAR command term, a specified row as a parameter for the SIMILAR command term, and a specified column as a parameter for the SIMILAR command term; querying the database using the SIMILAR command term and passing the specified row and the specified column to generate a predictive record set; and returning the predictive record set responsive to the query, the predictive record set having a plurality of elements therein, each of the returned elements of the predictive record set including (i) a row identifier which corresponds to a row of the dataset assessed to be similar, according to a latent structure, to the specified row passed with the SIMILAR command term based on the specified column and (ii) a confidence indicator which indicates a likelihood of a latent relationship between the specified row passed with the SIMILAR command and the row identifier returned for the respective element. Other related embodiments are further disclosed.
US09336529B1	Method and system for eliciting consumer data by programming content within various media venues to function cooperatively Disclosed is an interactive venue individuals. At least one database stores trait information, preference information, and identification information that includes visual and/or audio information. The database also stores advertiser information that includes information representing at least one of goods and services of one or more advertisers. Video media is provided that features at least one participant. The participant is at least one of the plurality of persons. Further, a web site is provided that shows at least part of the video media and at least some of the electronic advertiser information. Some of the electronic advertiser information corresponds to at least one selected from the group consisting of the at least one participant and at least one user of the web site.
US09336526B2	Method for providing support using answer engine and dialog rules According to one embodiment, a self-service system is to provide self-support knowledgebase (KB) information to allow users to navigate the self-support KB. A monitor is to track user interaction with the self-support KB while a user navigates through the self-support KB. An answer engine is to receive a query from the user to ask a question and in response to the query, to identify a predefined response to the query in view of a set of dialog rules. The answer engine is to transmit one or more related questions that the user will likely ask based on the dialog rules and the user interaction. The answer engine further transmits an invitation to allow the user to initiate a live support session after a predetermined condition has been satisfied.
US09336523B2	Managing a secure transaction A method, system or computer usable program product for secure short range protocol based transaction processing including using a mobile device capable of short range protocol communication to receive a user password; exchanging transaction data between the mobile device and a point of transaction device through a short range protocol communication, the transaction data including a timestamp; using the mobile device, generating a hash including the user password and the timestamp as inputs; providing the hash and the timestamp to an authorization agent; and receiving an authorization from the authorization agent for an account transaction with the point of transaction device based on the password in the hash.
US09336521B2	System and method for chopping up and processing gift cards Systems, methods, and computer-readable media for chopping up a gift card/code into smaller multiple gift card/codes. The system receives a request from a user to convert a closed-loop card/code having a value amount into two different closed-loop cards/codes and divides (or “chops up”) the closed-loop card/code into a first closed-loop card/code having a first value amount and a second closed-loop card/code having a second value amount, wherein the first value amount and the second value amount add up to no more than the value amount. The system offers the first closed-loop card/code and the second closed-loop card/code to one of the user and a third party.
US09336517B1	Systems and methods for alignment of check during mobile deposit An alignment guide may be provided in the field of view of a camera associated with a mobile device used to capture an image of a check. When the image of the check is within the alignment guide in the field of view, an image may be taken by the camera and provided from the mobile device to a financial institution. The alignment guide may be adjustable at the mobile device. The image capture may be performed automatically by the camera or the mobile device as soon as the image of the check is determined to be within the alignment guide. The check may be deposited in a user's bank account based on the image. Any technique for sending the image to the financial institution may be used.
US09336516B2	Scheduling for service projects via negotiation Assignment scheduling for service projects, in one aspect, may comprise preparing input parameter data for servicing a client service request; generating a schedule for servicing the client service request by executing an optimization algorithm with the input parameter data; determining whether the schedule is acceptable by the client; and repeating automatically the preparing, the generating, the transmitting and the determining until it is determined that the schedule is acceptable by the client, wherein each iteration automatically prepares different input parameter data for inputting to the optimization algorithm and generates a different schedule based on the different input parameter data.
US09336514B2	System and method for automatic social messaging A system and method for automatic social messaging is provided. The social networking device includes an automatic social messaging module and one or more applications configured to coordinate with the automatic social messaging module. In a social network device, the automatic messaging module receives, from an application, an indication that a predefined trigger event has occurred. The automatic messaging module then accesses a set of event parameters for the predefined trigger event. The set of parameters includes a set of recipients for a notification message associated with the trigger event. The parameters may also include update information, message details, a filter criteria for the trigger event. The automatic messaging module then transmits the notification message associated with the predefined trigger event to the set of recipients according to the trigger event parameters.
US09336506B2	Machine-readable delivery platform for automated package delivery A user requests a package delivery from a package delivery system. The package delivery system provides the user with a machine-readable code for display at the delivery location. An aerial delivery device receives, from the package delivery system computing device, information associated with the delivery location of the package. The information comprises information matching the information in the machine-readable code associated with the delivery location and a delivery address. The delivery device secures the package for transporting to the delivery location and transports the package to the delivery address. The delivery device locates the machine-readable code on a display at the delivery address and verifies that the information from the machine-readable code is associated with the package. The delivery device deposits the package on the display.
US09336505B1	Apparatus for portal based scanning A system, apparatus, and method for the rapid inspection of shipping containers during transport and for intelligent data gathering for risk analysis are provided. More specifically, a portal based scanner is disclosed which includes a plurality of sensors positioned to create a target zone so that the shipping containers can be automatically scanned during loading and offloading operations. According to one aspect of the invention, the scanner is capable of wirelessly communicating with the containers, gathering data about each container, and reporting data to a Data Fusion Center for risk profile analysis.
US09336500B2	System and method for authorizing and connecting application developers and users A system and method for authorizing application use of a user that can include creating a developer account associated with an application of an application platform; receiving an authorization request to authorize the application to act on a user account; creating a subaccount of a user, wherein the subaccount is associated with the developer account; creating an authorization record, that includes setting a permission profile for the subaccount; and returning a subaccount identifier to the developer.
US09336498B2	Method and apparatus for improving resilience in customized program learning network computational environments An apparatus and a method are provided for learning a program with a large number of parameters. In one embodiment, a method not only distorts the input values, but also distorts some of the parameters in the program model. Such an approach not only forces the learned program to acquire parameter values to predict missing or desired data, but also to correct errors in the input data and the program parameters themselves, thereby rendering the learned program more resilient to overfitting and falling into local optima.
US09336497B2	System and method for an expert question answer system from a dynamic corpus Various embodiments provide systems, computer program products and computer implemented methods. Some embodiments include a method of updating an expert corpus set, including obtaining a query from a user, obtaining a raw data source, determining a relevance score for the raw data source with respect to the query, by performing actions including creating a first vector of statistical variables for the query using at least one natural language processing (NLP) socket, the statistical variables having category types, creating a second vector for the first raw data source, having category types that are the same as those for the query and generating a hypothesis regarding the relevance of the raw data source, testing the hypothesis by comparing relative statistical variables, calculating a gradient between the vectors to determine the relevance score and updating the expert corpus set with the raw data in response to the relevance score exceeds a threshold.
US09336492B1	Modeling of re-moistening of stored grain crop for acceptable time-of-sale moisture level and opportunity windows for operation of storage bin fans based on expected atmospheric conditions A modeling framework for evaluating the impact of weather conditions on farming and harvest operations applies real-time, field-level weather data and forecasts of meteorological and climatological conditions together with user-provided and/or observed feedback of a present state of a harvest-related condition to agronomic models and to generate a plurality of harvest advisory outputs for precision agriculture. A harvest advisory model simulates and predicts the impacts of this weather information and user-provided and/or observed feedback in one or more physical, empirical, or artificial intelligence models of precision agriculture to analyze crops, plants, soils, and resulting agricultural commodities, and provides harvest advisory outputs to a diagnostic support tool for users to enhance farming and harvest decision-making, whether by providing pre-, post-, or in situ-harvest operations and crop analyses.
US09336487B2	Method and system for creating a predictive model for targeting webpage to a surfer System, methods, and computer-program products include receiving requests for a web page, retrieving predictive information related to the requests, and determining one or more predictive factors for an object presented with the web page, the one or more predictive factors being determined using the retrieved predictive information. The systems, methods, and computer-program products further include generating a plurality of predictive models for the object using the one or more predictive factors, determining a score for each predictive model, selecting a group of predictive models from the plurality of predictive models using the score of each predictive model in the group, and generating a representative predictive model for the object using the group of predictive models, the representative predictive model being associated with the object.
US09336483B1	Dynamically updated neural network structures for content distribution networks Dynamically updating neural network systems may be implemented to generate, train, evaluate and update artificial neural network data structures used by content distribution networks. Such systems and methods described herein may include generating and training neural networks, using neural networks to perform predictive analysis and other decision-making processes within content distribution networks, evaluating the performance of neural networks, and generating and training pluralities of replacement candidate neural networks within cloud computing architectures and/or other computing environments.
US09336481B1	Organically instinct-driven simulation system and method An organically instinct-driven simulation system and method that enables organically instinct-driven simulation agents to intuitively, instinctively and logically anticipate future simulation states based upon inputs into the simulation; and proactively execute aggressive actions that are organically instinctive, forward looking, emotional and aggressively proactive resulting in a simulation that is more challenging to human participants. The system and method utilizes symbolic emotional and organically instinct-driven mathematical architectures; and inference processing algebras enabling instinct-driven simulation agents with the organically instinctive, predictive, aggressively proactive and the emotional behavior patterns of humans.
US09336480B1	Self-aware swarms for optimization applications Described is a high-dimensional optimization system implementing a modification of particle swarm optimization called self-aware particle swarm optimization. A plurality of software agents is configured to operate as a cooperative swarm to locate an objective function optima in a multi-dimensional solution space. The plurality of software agents is influenced by a set of parameters which influence exploration of the multi-dimensional solution space and convergence on the objective function optima. The plurality of software agents automatically modifies the set of parameters in response to at least one measure of convergence progress. Self-aware particle swarm optimization allows for monitoring of simple convergence properties to provide feedback to the swarm dynamics and make the swarm self-aware and adjust itself to the problem being solved.
US09336477B2	RFID wrist band The RFID wrist band includes an elastic block section including an airtight storage part, an elastic band section connected to the elastic block section to form an annular shape, and an inlay stored in the storage part and including a base substrate, an antenna on the base substrate, and an IC chip connected electrically with the antenna. The inlay is not fixed to an inner wall of the storage part, and the storage part is larger than a volume occupied by the inlay.
US09336474B2	Identification and purchasing platform A graphically based encoded image, symbol or icon that can serve as a link from physical material or visual displays to electronic data to retrieve specific or general information. In one example, a graphic image is encoded with a value that is linked to a reference lookup table. For example, a numeric value may be encoded to form an encoded image by providing a primary image, such as a logo, and by positioning one or more secondary images or shapes in reference to the primary image, wherein the position of the secondary image relative to the primary image corresponds or relates to the numeric value. Generally, the encoded image may be in the form of any shape, figure or logo, and may be associated with, for example, an advertisement, web site, marketing program, corporate promotion, product promotion, sweepstakes, business cards, personal information, and other mediums for the exchange of information.
US09336473B2	Virtual ink channels Virtual ink channels are created with colored media and white ink to afford multi-channel ICC profile creation by using ICC profiling software. The available color gamut is enhanced for an device that defines a color space with a color profiler, e.g. an ICC profiler. Thus, an available color gamut for an input or output device is enhanced or extended by creating virtual ink channels for use with profiling software. This allows the use of media types and/or inks that are otherwise not supported by the profiling software.
US09336469B2	Apparatus and method for color conversion for an image processing apparatus by extracting embedded color space information A non-transitory computer readable medium storing a program causing a computer to execute a process, the process including extracting first color space information from first image data in which the first color space information and n-color values in a first color space are described in a page description language, the first color space information being information for determining the first color space, which is a target, generating a color conversion profile in accordance with the first and second color space information, the second color space information being information for determining a second color space corresponding to output characteristics of an image output device that outputs second image data generated from the first image data, and converting the n-color values in the first color space into n-color values in the second color space in accordance with the color conversion profile.
US09336465B2	Method and apparatus for color print management In a color printing environment, functions for printing color management are dissociated. An abstraction layer is also provided to facilitate setting and evaluation of all factors relating to color print and prediction.
US09336463B2	Image forming apparatus capable of changing partitions of storage unit, and control method and storage medium therefor An image forming apparatus capable of changing partitions of a storage unit without using another storage unit stored with a system for partition change. At startup of the image forming apparatus, a file system is developed on a DRAM from a flash memory and executed by a CPU of the image forming apparatus. When determining that partition change is to be performed, a partition change module that operates on the CPU performs the partition change in a state where the flash memory is not mounted. Subsequently, an operating system placed on the flash memory is started up.
US09336462B2	Tray-type card connector capable of receiving at least two cards simultaneously A card connector (100) used for receiving at least two cards includes an insulative housing (1) having a bottom wall (11), a number of first contacts (21) and a number of second contacts (22) retained in the bottom wall along a front-and-rear direction, a metal shield (4) covering the insulative housing for defining a tray receiving space, and a tray (3) is moveably received in the tray receiving space. The tray includes a first front card receiving cavity (311), a second rear card receiving cavity (312), and a first supporting portion (3112) and a second supporting portion (3121) respectively located below the front card receiving cavity and the rear card receiving cavity. The front card receiving cavity is isolated from the rear card receiving cavity along the front-and-rear direction.
US09336452B2	System and method for identification of printed matter in an image A system and method of identifying a printed matter in an image that includes the printed matter by rectifying the image, identifying a series of pre-defined areas in the image relative to a frame or other form in the printed matter in the image, and comparing a characteristic of the pre-defined area in the printed matter in the image, to a characteristic of a corresponding pre-defined area from a sample of printed matters.
US09336448B2	Variable speed sign value prediction and confidence modeling Systems, methods, and apparatuses are disclosed for predicting the value of a variable speed sign (VSS) and determining the predicted value's associated confidence level. Highly assisted driving (HAD) vehicles may read or capture images of the VSS. The speed limit values, images, or videos of the VSS are reported and received by a network and database for analysis. A predicted speed limit value is determined for the variable speed sign from at least a portion of the received traffic data. A confidence level is also calculated for the predicted speed limit value for the variable speed sign.
US09336446B2	Detecting moving vehicles A method of detecting at least one moving vehicle includes receiving (202) image data representing a sequence of image frames over time. The method further includes analyzing (204-206) the image data to identify potential moving vehicles, and comparing (208-212) at least one said potential moving vehicle with a vehicle movement model that defines a trajectory of a potential moving vehicle to determine whether the at least one potential moving vehicle conforms with the model.
US09336444B2	System and method for occupancy detection using differential image sensing and optical markers A system and method for detecting occupancy of live objects, using differential image sensing and optical markers is provided. The system includes a live object(s) or a human, a stationary object(s), an image capturing device, an imaging system, a network, and an occupancy determination and parsing server. The image capturing device may capture the image sequences from a physical location which may be within the camera viewing area. The image capturing device may also be configured to track motions of the live objects. The imaging system may be connected to the occupancy determination and parsing server through the network. The occupancy determination and parsing server based on the information received from the imaging system may determine whether the physical location is occupied with the live objects or the stationary objects. The occupancy determination module and parsing server may be connected with at least one the imaging system.
US09336440B2	Power efficient use of a depth sensor on a mobile device Systems, apparatus and methods in a mobile device to enable and disable a depth sensor for tracking pose of the mobile device are presented. A mobile device relaying on a camera without a depth sensor may provide inadequate pose estimates, for example, in low light situations. A mobile device with a depth sensor uses substantial power when the depth sensor is enabled. Embodiments described herein enable a depth sensor only when images are expected to be inadequate, for example, accelerating or moving too fast, when inertial sensor measurements are too noisy, light levels are too low or high, an image is too blurry, or a rate of images is too slow. By only using a depth sensor when images are expected to be inadequate, battery power in the mobile device may be conserved and pose estimations may still be maintained.
US09336434B2	Method for detecting a true face Detecting a true face includes: capturing a parallel image of a face captured by a camera having a filter polarizing parallel to a polarization direction and an orthogonal image of the face captured by a camera's filter polarizing orthogonally to the polarization direction; computing a difference image from difference between the parallel and orthogonal images; filtering the difference image in wavelet packets on 5 levels, eliminating “low” resolution levels; dividing the filtered image into sub-images; the filtered image and each sub-image undergoes: a Fourier or discreet cosine transformation; and modelling during which the frequency decrease profile is modelled by a model of the power type (a.x^b+c); extracting, from the filtered image and each sub-image, texture characteristics of face surface specularities; analyzing, for each face region, coefficient “b” and the texture characteristics extracted regarding the model corresponding to said face region; and deciding the veracity of the face from the analysis.
US09336431B2	Three-dimensional region of interest tracking based on key frame matching A method and system for key frame based region of interest (ROI) tracking is disclosed. The method includes storing a key ROI set in a key ROI buffer, the key ROI set including at least one key ROI; designating one of the key ROI in the key ROI set as an active key ROI; receiving a point cloud representing a particular ROI to be processed for tracking; establishing a correspondence between that particular ROI and the active key ROI; determining whether to switch the active key designation to another key ROI in the key ROI set and switching the active key designation accordingly; and determining whether to modify the key ROI set and modifying the key ROI set accordingly.
US09336430B2	Computer-assisted karyotyping A system and method for computer-assisted karyotyping includes a processor which receives a digitized image of metaphase chromosomes for processing in an image processing module and a classifier module. The image processing module may include a segmenting function for extracting individual chromosome images, a bend correcting function for straightening images of chromosomes that are bent or curved and a feature selection function for distinguishing between chromosome bands. The classifier module, which may be one or more trained kernel-based learning machines, receives the processed image and generates a classification of the image as normal or abnormal.
US09336428B2	Integrated fingerprint sensor and display A fingerprint swipe sensor includes fingerprint sensor lines disposed on a surface of an LCD protective glass covered on an opposite surface with motion sensing lines. The fingerprint swipe sensor also includes a controller coupled to the fingerprint sensor lines to capture a fingerprint image when a user's finger is swiped about the fingerprint sensor lines.
US09336425B2	Method for segmenting fingers A method for segmenting fingers may include: a capture step during which the acquisition device captures an image of the fingers and of the sight; a computing step during which the processing unit computes the unrolled phase image from the image of the thus captured; a derivation step during which, for each pixel of the phase image thus computed, the processing unit computes the derivative of the phase along the isointensity axis of the sight; a regionalisation step during which the processing unit associates each pixel where the derivative of the phase has been computed with a region grouping all the adjoining pixels step by step where the derivative of the phase has the same polarity; and a recognition step during which the location of each finger is recognised from the analysis of the regions thus determined.
US09336420B2	Systems and methods for programming an RFID reader A remote access system includes an RFID reader and a credential having a cellular phone interface and an nfc interface. The credential is operable to receive authorization information and to communicate with the RFID reader. A server is operable to receive an authorization request for the credential and to access the credential to provide the authorization information. An RFID reader authorization application is included in the credential. The credential is operable to transfer the RFID authorization code to the RFID reader via the nfc interface over an nfc communication channel.
US09336418B2	System and method for polling NFC-A devices alongside RF barcode devices A NFC reader is connected for communication to NFC devices such as an NFC-A device and an RF barcode device. The reader detects and logs the active and sleep intervals of the RF barcode device in response to receipt of periodically received UID communications. The transmission and reception of data to and from each NFC-A device is then synchronized to occurs only when the RF barcode device is in a sleep interval between UID communications.
US09336414B2	Method of activating a mechanism, and device implementing such a method A method of activating a function such as unlocking a mobile telephone keypad by an instruction sequence {xi, . . . , xn} of a length n given to a user, who validates the sequence to activate the function. The instruction sequence is determined randomly, and for each instruction xi, the method includes: sending an instruction xi to the user; receiving a response yi from the user; analysis for validation of instruction xi; instruction xi is said to be validated when yi is a valid response for xi and the time elapsed between the sending of xi and the receipt of yi is shorter than a set period Δi; if instruction xi is not validated then the function is not activated; sending the next instruction, if any, after validation of xi; activating the function when at least the last instruction sent is validated.
US09336413B2	Method and system for fast permission changes for virtual addresses A method for accessing shared memory, the method includes loading a private context ID into a private context ID register, where the first private context ID enables a thread to access a private memory region only accessible by the thread. The method further includes receiving, from the thread, a first request to access a shared memory region, loading a shared context ID into a shared context register, permitting, by a memory management unit (MMU), the thread to access the shared memory region using the shared context ID, and receiving, from the thread, a second request to disable access to the shared memory region. The method further includes removing, in response to the second request, the shared context ID from the shared context ID register, where after removing the shared context ID from the shared context ID register the thread is no longer able to access the shared memory region.
US09336412B2	Storage system and method for controlling storage system The storage system according to the present invention has a function to encrypt write data from the host and store the same in a storage media. Further, validation information of write data is added to the write data during storage thereof, and the data having the validation information added thereto is encrypted and stored in the storage media. When starting the storage system or restoring the encryption key information, the encrypted data stored in the storage media is read from the disk and decrypted prior to receiving a data access request from the host, and validation of data is performed using the validation information added to the decrypted data, so as to determine whether the encryption key stored in a storage controller is valid or not.
US09336409B2	Selective security masking within recorded speech A marker is derived from an interaction between a person and an agent of a business and the agent's user interface. A part of a speech signal that corresponds to a portion of the person's special information is located with the marker. The speech signal results from the interaction between the person and the agent. The part of the speech signal that corresponds to the portion of the person's special information is rendered unintelligible.
US09336408B2	Solution for continuous control and protection of enterprise data based on authorization projection Extracting data from a source system includes generating an authorization model of the data protection controls applied to the extracted data by the source system. The authorization model is used to map the data protection control applied to the extracted data to generate corresponding data protection controls provided in target system. The extracted data is imported to the target system including implementing the corresponding data protection controls.
US09336406B2	Multiprotocol access control list with guaranteed protocol compliance An approach to multiprotocol ACL implementation with guaranteed protocol compliance is described. In one approach, a method of access rights validation for a multiprotocol supported file server is detailed. The method involves receiving a request to store a file with a security descriptor and storing the security descriptor in an extended attribute associated with the file. Subsequently, the security descriptor is expanded to extract a set of ACEs. Access to the file can then be validated against the ACEs expanded from the security descriptor according to the specifications of the protocol that created the security descriptor.
US09336400B2	Information asset placer A computer-implemented method for the placing of information assets, including: discovering information about a new or changed information asset; determining one or more characteristics of an ideal location for the information asset; determining one or more characteristics of one or more locations in an information technology environment; determining the compatibility of the information asset with the location(s) by comparing the characteristic(s) of the ideal location to the characteristic(s) of the actual location(s); reporting the compatibility to a user; and optionally suggesting alternative placement locations. The locations may be part of one or more locational schemas.
US09336396B2	Method and system for generating an enforceable security policy based on application sitemap A system for generating a security policy for protecting an application-layer entity. The system comprises a security sitemap generator for generating a security sitemap of a protected application-layer entity, the security sitemap is stored in a first repository connected to the security sitemap generator; and a policy builder for generating a security policy for the application-layer entity based on the security sitemap, the security policy is stored in a second repository connected to the policy builder, wherein the security policy includes a plurality of enforcement rules for at least one of a resource, a group of resources, and a client-side input parameter of at least a portion of the protected application-layer entity.
US09336394B2	Securely recovering a computing device A method and an apparatus for establishing an operating environment by certifying a code image received from a host over a communication link are described. The code image may be digitally signed through a central authority server. Certification of the code image may be determined by a fingerprint embedded within a secure storage area such as a read only memory (ROM) of the portable device based on a public key certification process. A certified code image may be assigned a hash signature to be stored in a storage of the portable device. An operating environment of the portable device may be established after executing the certified code.
US09336390B2	Selective assessment of maliciousness of software code executed in the address space of a trusted process System and method for detection of malicious code injected into processes associated with known programs. Execution of processes in a computer system is monitored. From among the processes being monitored, only certain processes are selected for tracking. For each of the processes selected, function calls made by threads of the process are tracked. From among the tracked function calls, only those function calls which are critical function calls are identified. For each identified critical function call, program instructions that caused the critical function call are subjected to analysis to assess their maliciousness.
US09336388B2	Method and system for thwarting insider attacks through informational network analysis One embodiment of the present invention provides a system for detecting insider attacks in an organization. During operation, the system collects data describing user activities. The system extracts information from the data that includes user information and user communications. The system then generates a topic-specific graph based on the extracted information. The system analyzes a structure of the graph to determine if one or more rules have been violated. The system may determine that a rule associated with the graph has been violated and signal an alarm in response to detecting the rule violation.
US09336387B2	System, method, and computer program product for detecting access to a memory device Discrete events that take place with respect to a hard disk drive or other I/O device or port are indicated to logic that implements Self-Monitoring Analysis and Reporting Technology (SMART) or similar technology. These events are communicated to SMART as event data. Examples of such discrete events include power on, power off, spindle start, and spindle stop, positioning of the actuator, and the time at which such events occur. SMART then compiles event data to create compiled activity data. Compiled activity data represents summary statistical information that is created by considering some or all of the event data. Examples of compiled activity data include the Time Powered On and Power Cycle Count. Collection logic then writes the compiled activity data to a memory medium. An analyst can then read data from log file(s).
US09336386B1	Exploit detection based on heap spray detection Various techniques for exploit detection based on heap spray detection are disclosed. In some embodiments, exploit detection based on heap spray detection includes executing a program in a virtual environment; and detecting heap spray in memory while executing the program in the virtual environment. In some embodiments, exploit detection based on heap spray detection includes executing a program in a virtual environment; and detecting heap spray related malware in response to a modification of an execution environment in the virtual environment.
US09336383B2	Mitigating just-in-time spraying attacks in a network environment An example method for mitigating JIT spraying attacks in a network environment is provided and includes protecting an output of a just-in-time (JIT) compiler against attacks during application execution at least by intervening from outside the application into a JIT page generated by the JIT compiler in a memory element of a host. In a specific embodiment, the intervening can include rewriting the JIT page. In specific embodiments, the method can further include generating a shadow page corresponding to the JIT page in the memory element. The method can further include randomly choosing at least one block of instructions in the JIT page, moving the at least one block of instructions to the shadow page, and replacing the at least one block of instructions in the JIT page with at least one of invalid opcodes and halt instructions.
US09336376B2	Multi-touch methods and devices The present disclosure relates to a multi-touch method, configured to a touch panel. The method comprises: applying a first object to touch a first image on the touch panel for inputting a first password; and determining whether inputting a second password, and if not, removing the first object from the touch panel for ending a first round of password input.
US09336374B2	Method, module, and computer program product for identifying user of mobile device A module for authenticating a user of a mobile device. The mobile device has an orientation sensor and a touch screen sensor. The module includes: a behavioral biometrics conversion element, used to perform calculation by matching timestamps with a plurality of behavioral data of operations, sensed by the orientation sensor and the touch screen sensor, on the mobile device to acquire a plurality of behavioral biometrics quantities, and convert, by using a statistical method, multiple sets of the behavioral biometrics quantities into a behavioral biometrics pattern in a histogram constructing manner; and an authentication mechanism core element, used to determine whether the behavioral biometrics pattern conforms to a behavioral biometrics model pattern in a histogram manner. The present invention further includes a method and a computer program product for authenticating a user of a smart phone.
US09336370B2	Method and apparatus for dynamic obfuscation of static data A method and an apparatus that provide rewriting code to dynamically mask program data statically embedded in a first code are described. The program data can be used in multiple instructions in the first code. A code location (e.g. an optimal code location) in the first code can be determined for injecting the rewriting code. The code location may be included in two or more execution paths of first code. Each execution path can have at least one of the instructions using the program data. A second code may be generated based on the first code inserted with the rewriting code at the optimal code location. The second code can include instructions using the program data dynamically masked by the rewriting code. When executed by a processor, the first code and the second code can generate identical results.
US09336362B2	Remote installation of digital content Various embodiments relating to remote installation of digital content on unlicensed computing machines are provided. In one embodiment, an unlicensed computing machine at which to install a licensed digital content item is identified by a licensed computing machine, a request to transfer a license for the licensed digital content item to the unlicensed computing machine is sent from the licensed computing machine to an authorization service computing machine, and delivery of the licensed digital content item to the unlicensed computing machine is initiated.
US09336357B2	Secure access management of devices Systems and methods may provide implementing one or more device locking procedures to block access to a device. In one example, the method may include receiving an indication that a user is no longer present, initiating a timing mechanism to set a period to issue a first device lock instruction to lock a peripheral device, relaying timing information from the timing mechanism to a controller module associated with the peripheral device; and locking the peripheral device upon expiration of the period.
US09336355B2	Apparatus and method for generating a condition indication An apparatus for generating a condition indication using a time sequence of data values, each data value representing a physiological measure of a condition of a subject at a time, includes: a transformer for transforming the time sequence of data values into a transformed sequence of data values using a transform rule, wherein the transform rule is such that a certain characteristic in a time course of the physiological measure is represented by the transformed sequence of data values is more linear than the time course before the transform; a rate of change calculator for calculating an estimated rate of change for the transformed sequence of data values; and a processor for processing the estimated rate of change to output the condition indication.
US09336351B2	Method and system for collecting, storing and analyzing clinical and radiologic data The invention relates to an online web-based medical database and collaboration tool that can be used by surgeons, hospitals, medical institutions, manufacturers and others to collect, store, analyze and harvest clinical and radiologic data. The clinical registry system includes a registry database and a registry processor in electrical communication with the registry database and performing operations on the registry database. The registry database stores patient data from a plurality of sites, a plurality of registry groups and an indicator for each of the plurality of sites identifying which of the plurality of registry groups each site is a member. The members of a registry group have access to aggregated data and comparative reports of all the registry group members in real-time. Each site may be a member of one registry group, multiple registry groups, or no registry groups.
US09336348B2	Method of forming layout design A method of forming a layout design for fabricating an integrated circuit (IC) is disclosed. The method includes identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design; and generating a set of layout patterns overlapping the identified one or more areas. The plurality of gate structure layout patterns has a predetermined pitch smaller than a spatial resolution of a predetermined lithographic technology. A first layout pattern of the set of layout patterns has a width less than twice the predetermined pitch.
US09336345B2	Methods for converting planar designs to FinFET designs in the design and fabrication of integrated circuits Methods for converting planar designs to FinFET designs in the design and fabrication of integrated circuits are provided. In one embodiment, a method for converting a planar integrated circuit design to a non-planar integrated circuit design includes identifying a rectangular silicon active area in the planar integrated circuit design, superimposing a FinFET design grid comprising a plurality of equidistantly-spaced parallel grid lines over the rectangular silicon active area such that two sides of the rectangular silicon active area are parallel to the grid lines, and generating a rectangular active silicon marker area encompassing the silicon active area. Furthermore, the method includes generating fin mandrels longitudinally along every other grid line of the plurality of grid lines and within the active silicon marker area and the silicon active area, and removing the fin mandrels from areas of the design grid outside of the active silicon marker area.

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