最新美国发明专利
Document Document Title
US09325488B2 Noise shaped interpolator and decimator apparatus and method
An interpolator or decimator includes an elastic storage element in the signal path between first and second clock domains. The elastic element may, for example, be a FIFO which advantageously allows short term variation in sample clocks to be absorbed. A feedback mechanism controls a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified interpolator and decimator.
US09325482B2 Method for coordinated scheduling in wireless communication system and apparatus therefor
In an aspect of the present application, provided herein is a method for transmitting signals for coordinated scheduling in a wireless communication system, the method performed by a base station and comprising: transmitting, to a neighbor base station, information on a transmission scheme in a specific channel state information-interference measurement (CSI-IM) resource; and receiving, from a mobile terminal served by the base station, a measurement result with respect to a downlink signal transmitted from the neighbor base station according to the transmission scheme in the specific CSI-IM resource, wherein the transmission scheme is determined according to whether there is downlink data to be transmitted by the base station in a subframe to which the specific CSI-IM resource belongs and/or whether the mobile terminal configured with the specific CSI-IM resource is allocated a single CSI process or multiple CSI processes.
US09325474B2 Method for base station transmitting downlink control channel in wireless communication system and apparatus for same
In the present invention, a method for a base station transmitting a downlink channel is disclosed. More particularly, the method comprises the steps of: dividing each of one or more resources blocks, which are allocated for the downlink control channel, into a predetermined number of subsets; deciding the number of subsets that comprise a resource allocation basic unit for the downlink control channel, based on a start symbol and/or an end symbol of the downlink control channel; mapping a transmission resource on the downlink control channel as the resource allocation basic unit comprising the predetermined number of subsets; and transmitting the downlink control channel by using the transmission resource that is mapped.
US09325471B2 Mobile station apparatus and communication method
A mobile station (MS) receives, from a base station (BS), information which is used to assign a PUSCH resource; transmits uplink control information using a single PUCCH resource in case that the PUSCH resource is not assigned and a plurality of PUCCH resources is assigned; transmits the uplink control information using the PUSCH resource assigned on a first uplink component carrier (UCC) in case that the PUSCH resource is assigned on the first UCC, the first UCC is used for transmitting the uplink control information using the single PUCCH resource in case that the PUSCH resource is not assigned and the plurality of PUCCH resources is assigned; and receives the uplink control information using the PUSCH resource assigned on a second UCC in case that the PUSCH resource is not assigned on the first UCC but the PUSCH resource is assigned on the second UCC.
US09325470B2 Method and device for sending pilot signal
Embodiments of the invention disclose a method and device for sending a pilot signal. The method includes: generating a sub-frame carrying user-specific pilot signals, wherein the sub-frame includes one or more resource blocks, the resource block includes a plurality of resource elements in a symbol-subcarrier plane, locations of the resource elements in the symbol-subcarrier plane are determined by an OFDM symbol and subcarrier, a first part of the user-specific pilots signal are carried by the resource elements of the initial one or more OFDM symbols in the resource block, and a second part of the user-specific pilot signals are carried by resource elements of other OFDM symbols in the resource block; and sending the sub-frame carrying the user-specific pilot signals. The methods and devices are capable of improving the precision of channel estimation.
US09325462B2 User equipment, base station device, and mobile communication method
In a user equipment UE according to the present invention which appropriately measures downlink radio quality when multi-carrier transmission is performed, the user equipment UE includes a measurement unit 22B configured to perform measurement processes in the first carrier and the second carrier, wherein when simultaneous communication of a downlink signal in the first carrier and a downlink signal in the second carrier is performed, the measurement unit 22B is configured to perform only the measurement process in the second carrier.
US09325458B2 Backoff adaptation for digital communication systems with channel quality information
System and method for backoff correction of channel quality information (CQI). A correction factor is calculated based on a goodness measure such as packet error rate (PER). The selection of modulation and coding scheme (MCS) is made considering the channel quality information (CQI) adjusted by the correction factor. A meaningful goodness measure can be imposed if the goodness measure is very low. A different correction factor can be calculated for different confidence levels, MCSs and transmission modes.
US09325457B2 Method of providing HARQ feedback information
In a wireless communication system where a terminal and a base station communicate with each other using a frame including at least one downlink sub-frame and at least one uplink sub-frame, the terminal and the base station calculate the number of hybrid automatic repeat request (HARQ) feedback regions of the downlink sub-frames and the uplink sub-frames in accordance with a third value corresponding to an absolute value of subtraction between a first value corresponding to the number of downlink sub-frames of the frame and a second value corresponding to the number of uplink sub-frames of the frame or the sum of the first value and the second value and configure HARQ feedback regions in the downlink sub-frames and the uplink sub-frames.
US09325455B2 Device, system and method of communicating aggregate data units
Some demonstrative embodiments include devices, systems and/or methods of communicating aggregate data units. For example, a device may include a wireless communication unit to communicate an aggregate data unit including a plurality of data units in an increasing order of sequence numbers assigned to the data units, such that a first data unit having a first sequence number always precedes a second data unit having a second sequence number, greater than the first sequence number.
US09325451B1 Maximum likelihood decoding apparatus
A decoding apparatus for decoding a signal transmitted over a channel in a communication system, the signal comprising at least one data symbol and one pilot symbol the data symbol comprising a first encoded sequence encoding a transmitted sequence, the pilot symbol comprising a pilot signal.The decoding apparatus performs an additional processing after the operations of a conventional maximum likelihood decoding. A predetermined number of hypotheses of the conventional maximum likelihood decoding are selected to perform a maximum likelihood processing where channel estimation is improved by considering data symbol information. A receiver, a LTE receiver, a method and a computer program are also claimed.
US09325444B2 Scrambling code resolution
A code division multiple access wireless network (10) comprises a plurality of base stations (11-14) which operate asynchronously with respect to one another. A set of scrambling codes are allocated to the base stations for scrambling signals transmitted from the base stations. A node (30) of the wireless network receives (102) a first type of measurement report from wireless terminals (20), which comprises an observed time difference measurement acquired by the wireless terminal (20) for a signal received from one of an active set of base stations (11, 12, 13) that currently serve the wireless terminal. A timing reference is determined (103) for each of the base stations using a plurality of the observed time difference measurements. A second type of measurement report is received (105) from a wireless terminal (20) which comprises an observed time difference measurement acquired by the wireless terminal for a signal received from a base station (14) which is not currently serving the wireless terminal and a scrambling code of the received signal. An identity of the base station (14) in the second type of measurement report is determined by using the scrambling code of the signal received from the base station (14) which is not currently serving the wireless terminal and the observed time difference measurement in the second type of measurement report and the determined timing reference for that base station.
US09325443B2 Radio base station apparatus, mobile terminal device and wireless communication method
To provide a radio base station apparatus, mobile terminal device and wireless communication method for transmitting and receiving downlink channel quality measurement reference signals in consideration of interference estimation of high accuracy, in a wireless communication method of the invention, a radio base station apparatus generates channel quality measurement reference signals, and maps the channel quality measurement reference signals to two adjacent symbols, and a mobile terminal device receives a downlink signal including the channel quality measurement reference signals mapped to two adjacent symbols, and performs interfering power estimation using the channel quality measurement reference signals mapped to two adjacent symbols.
US09325439B2 Audio signal processing device
An output channel processing an audio signal after mixing in a mixing bus in a digital mixer is configured such that output points PreHPF and PostON are provided at locations before and after a signal processing module group composed of signal processing modules from a high-pass filter to an ON/OFF control module, an output selecting switch selects one of the output points to supply the audio signal at the selected output point to a direct-out output module which is provided corresponding to the output channel and includes an ON/OFF control module and a level adjustment module so that the audio signal can be outputted via the direct-out output module.
US09325438B2 Broadcast-signal transmitter/receiver and method for transmitting/receiving broadcast signals
The broadcast-signal transmitter according to one embodiment of the present invention includes: an encoder for encoding physical layer pipe (PLP) data, including a base layer and an enhancement layer of a broadcasting service, and signaling information through a SISO, and/or MIMO technique; a frame builder for generating a transmission frame, which includes a preamble having the encoded signaling information and the PLP data and an OFDM generator for modulating and transmitting a broadcast signal including the transmission frame.
US09325435B2 System and method for facilitating comparison of radio frequency (RF) data signals transmitted by a device under test (DUT) and received by a test system
A system and method for facilitating comparison of radio frequency (RF) data signals transmitted by a device under test (DUT) and received by a test system. A RF data signal received from a DUT is analyzed to provide analysis data indicative of conformance of the DUT operation with one or more applicable signal standards. The RF data signal is also converted to related conversion data that can be stored with state machine data corresponding to states of the signal testing subsystem. This state machine data can then be processed as needed with the analysis data and conversion data for off-line tasks such as debugging new test programs and procedures.
US09325434B2 Systems and methods for reducing digital interference of external signals
A mobile device may include a digital data driver and digital data receiver for communication of digital signals within the mobile device at a selected clock rate. The mobile device may also have a device external for the digital data driver and digital data receiver for communication of external signals, such as radio-frequency signals, to and from the mobile device. To avoid interference of frequency harmonics of a digital signal with such external signals, the digital data driver may be configured to control the digital signal based on the frequency of the external signals, such that interference of the external signal by spectral content of the digital signal is minimized, while maintaining the selected clock rate.
US09325433B2 High dynamic range transceiver
This invention uses one or more cancellation modules to eliminate the transmitter leakage at the output of the receive antenna and prior the receiver circuitry so that the received signals can be analyzed without degradation in quality due to simultaneous operation of the transmitter and receiver. Each cancellation circuit could be limited to only 30-50 dB of rejection due to component mismatches and other circuit non-idealities. To obtain further cancellation, more than one cancellation circuit can be applied after the first low noise amplifier. The output of the low noise amplifier can be repeatedly mixed with additional cancellation signals “n” number of times such that the “n” low noise amplifier is mixed with the “nth” cancellation signal. For each additional cancellation signal added a 20-30 dB reduction in noise may be achieved such that cascading three or four cancellation signals from cancellation modules may produce a 150 dB gain.
US09325430B2 Communication system and communication apparatus
A communication system includes: an interrogator transmitting an interrogation signal while switching a carrier-wave frequency and receiving a response signal; and a plurality of responders each having a unique resonant frequency and returning the response signal in response to the interrogation signal with the own resonant frequency.
US09325427B1 Maximum likelihood decoding
In a coherent receiver of an optical communication system, a method of processing a detected symbol estimate to determine a most likely value of a corresponding transmitted data word, the transmitted data word comprising one or more data bits encoded in a transmitter using a predetermined constellation of at least two symbols. A set of two or more virtual constellation points are define in a decision region corresponding to a possible value of the data word. The detected symbol estimate is processed to find a most likely virtual constellation point given the detected symbol estimate. The most likely value of the corresponding transmitted data word is determined based on the most likely virtual constellation point.
US09325426B2 Burst-mode receiver having a wide dynamic range and low pulse-width distortion and a method
A burst-mode Rx is provided that has a wide dynamic range, low pulse-width distortion and low technological overhead. The Rx is capable of processing signals having levels that range from low noise levels up to high noise levels. In addition, the Rx is capable of quickly and simultaneously adapting the TIA gain and the bit decision threshold level, thereby eliminating the need to transmit and receive a training bit sequence prior to transmitting and receiving actual data. By simultaneously adapting the TIA gain and the bit decision threshold level on the first bit of actual data received in the Rx, the Rx is capable of being used with short packets and with packets of varying lengths transmitted from different types of transmitters located in the same network.
US09325423B1 Systems and methods for complementary signal transmission
This disclosure provides systems, methods, and apparatus for improving a signal-to-noise ratio of a signal transmitted over a communication link. The communication system can include a transmitter, a receiver and a communication link for communicating data between the transmitter and the receiver. In some implementations, the transmitter employs a modulator for generating a modulated data signal and a complementary modulated data signal and send over the fiber link through two orthogonal polarizations. The receiver utilizes both the modulated data signal and the complementary modulated data signal for regenerating the transmitted data at the receiver. In some implementations, the receiver determines and transmits a polarization parameter to the transmitter, which adjusts the polarizations of the transmitted modulated and complementary modulated data signals to compensate for polarization angle rotation introduced by the communication link.
US09325420B2 Electro-optical transceiver device to enable chip-to-chip interconnection
An apparatus includes a substrate and a waveguide coupled to a surface of the substrate. The surface forms a cladding layer of the waveguide. The apparatus includes a photodetector optically coupled to an end of the waveguide. The photodetector is configured to output an electrical signal responsive to receiving a light signal from a core of the waveguide. The apparatus also includes an amplifier device coupled to the substrate. The amplifier device is electrically coupled to the photodetector to amplify the electrical signal to produce an amplified electrical signal.
US09325416B2 Network interface device for optical premises signals and networks
A network interface device (NID) demarcates an access network and a premises network. The NID receives a broadband signal via an access network and transmits optical device signals to pieces of premises equipment. The broadband signal may be a single-mode fiber (SMF) optical signal transmitted over an SMF cable. In these embodiments, the NID may include a transponder including a first stage to convert the SMF signal to an intermediate electrical signal and a second stage to convert the intermediate electrical signal to a premises optical signal. In other embodiments, the broadband signal may be a very high bit rate digital subscriber line (VDSL) or other type of electrical signal and the NID's transponder may convert the VDSL signal to the premises optical signal. The NID may further include a multiplexer to multiplex the premises optical signal into the optical device signals for delivery to premises devices via corresponding premises device ports and plastic optical fiber cables.
US09325415B2 Method and system for wireless transmission of analog signals between antenna and baseband processor
A wireless communication method and system utilizing optical transmission technology to transport analog signals directly to/from the antenna, without ADC/DAC, so that the optical transport facility can be utilized more efficiently and there is no need to adapt the digital data rate to the transport capacity, as the analog transmission is independent of the digits buried in the given spectrum. Complicated operation is moved into a centralized location, so that a cell site (base station) is light and flexible. In contrast, the standardized approach in the industry, which involves digitized interface between the antenna and the control processor, hits capacity limits of the current transport technology.
US09325413B2 Apparatus and methods for enabling recovery from failures in optical networks
Apparatus for enabling recovery from failures in up to M working paths of a set of N working paths that are allocated N frequency slots of L different slot widths, where M, N and L are positive integers, N≧L>1, and N>M>1. The apparatus includes a processor and a control plane interface. The processor is operative to allocate protection frequency slots to M protection paths in different manners depending on whether M is greater than L, equal to L or less than L. The control plane interface is operatively associated with the processor and is operative to effect provisioning of the M protection paths for supporting recovery from the failures. Related network, apparatus and methods are also disclosed.
US09325412B2 Transceiver system, transmission device, reception device, and control method of transceiver system
A transmission circuit of a transmission device transmits a signal to a reception circuit of a reception device via a plurality of signal paths included in a communication line. A first interface circuit is connected to the transmission circuit and one or more signal paths. A second interface circuit is connected to the transmission circuit and remaining signal paths expect for the one or more signal paths. A third interface circuit is connected to the reception circuit and the one or more signal paths. A fourth interface circuit is connected to the reception circuit and the remaining signal paths. An operation for transmitting and receiving the signal via the plurality of signal paths is changed to an operation for transmitting and receiving the signal via the remaining signal paths when the one or more signal paths enter a disconnected state.
US09325409B1 Non-line of sight wireless communication system and method
A non-line of sight backhaul system and method are described that provides self-alignment of the antennas beams of the wireless radios of the system, that provides robust operation in licensed and unlicensed frequency bands, that facilitates the use of a reduced number of frequency channels from M to 1 and that enables operation in a non-line of sight (NLOS) propagation environment.
US09325402B2 Method and apparatus for transmitting and receiving codebook subset restriction bitmap
A method for transmitting and receiving a codebook subset restriction bitmap is provided. The Codebook Subset Restriction (CSR) bitmap transmission method of an evolved Node B (eNB) in transmission mode 9 for communication with 8 antenna ports includes generating a CSR bitmap including bits corresponding to restricted precoding matrix indicators and rank indicators that are not allowed for reporting and transmitting the CSR bitmap to a User Equipment (UE). The CSR bitmap comprises 53 bits corresponding to a first codebook and 56 bits corresponding to a second codebook, the 53 bits corresponding to a first codebook comprise 16, 16, 4, 4, 4, 4, and 1 bits for layers 1, 2, 3, 4, 5, 6, 7, and 8, respectively, and the 56 bits corresponding to a second codebook comprise 16, 16, 16 and 8 bits for layers 1, 2, 3, and 4, respectively.
US09325401B2 Beamforming from multiple transmission sites
According to one embodiment, a method includes selecting a first transmission site from a plurality of transmission sites based on the quality of a first channel between the first transmission site and an endpoint. The method further includes determining a first precoding matrix corresponding to the first transmission site. The first precoding matrix may be applied to data transmitted by the first transmission site to the endpoint. The method further includes determining a second precoding matrix corresponding to a second transmission site of the plurality of transmission sites. The second precoding matrix may be determined based on at least a first spatial direction that is calculated based on at least the first channel.
US09325397B2 Methods of selecting MIMO ranks and related devices
A method of operating a wireless network node may include transmitting a first MIMO downlink communication to a wireless terminal according to a first MIMO rank, and receiving at least one HARQ ACK/NACK, message from the wireless terminal corresponding to the first MIMO downlink communication. A report may be received from the wireless terminal identifying a reported MIMO rank, and a second MIMO rank may be selected for a second MIMO downlink communication responsive to the at least one HARQ ACK/NACK message. The second MIMO downlink communication may be transmitted to the wireless terminal according to the second MIMO rank.
US09325391B2 Method and system for relaying data using a plurality of relay nodes
Provided is a method and system for relaying data using a plurality of relay nodes. The method may include obtaining a first channel matrix related to a first-hop channel and a second channel matrix related to a second-hop channel, generating an effective interference channel matrix based on the first channel matrix and the second channel matrix, and calculating a null space vector of the effective interference channel matrix.
US09325385B2 User equipment, communication method, program, and communication system
The present disclosure relates to user equipment for, a communication method of, a program for, and a communication system for starting wireless communication among pieces of user equipment without placing operational load on a user. In the communication system according to the present disclosure, child equipment includes a detection module that detects different user equipment and performs authentication processing with the different user equipment that is detected, a notification module that notifies the parent equipment of identification information indicating the different user equipment that has been authenticated, and a communication module that performs the wireless communication with the different user equipment that is caused to belong to the group that is managed by the parent equipment, and the parent equipment includes an obtainment module that obtains the identification information which is notified from the child equipment, and an authentication module that, if there is a connection request from different user equipment that does not belong to the group, authenticates connection of the different user equipment that does not belong to the group, based on the identification information that is notified from the child equipment. The present disclosure, for example, can be applied to the user equipment that performs the wireless communication according to Wi-Fi Direct.
US09325384B2 Misalignment-tolerant high-density multi-transmitter/receiver modules for extremely-high frequency (EHF) close-proximity wireless connections
Docked devices communicate wirelessly and in close proximity using multiple transmitters of Extremely High-Frequency (EHF) signals of 30-300 GHz. The devices may not be precisely aligned when docked. Tolerance of misalignment is improved by adding barriers such as solid metal blocks or rows of metal-filled vias that have a spacing of less than one-quarter the EHF wavelength. The barriers reflect EHF radiation and prevent EHF radiation from penetrating the barrier. Barriers placed between adjacent transmitters and receivers block stray electromagnetic radiation from causing cross-talk. The barriers can be placed closer to the transmitters than to the receivers to allow for a wider area for reception, permitting a wider misalignment. EHF reflecting features such as ground planes spaced a quarter-wavelength apart may be added to an end of a substrate near a connecting edge to act as a barrier and reflect electromagnetic radiation back toward an intended receiver.
US09325380B2 Method and apparatus for data transfer via near field interaction
In accordance with an example embodiment of the present invention, a method is disclosed. Data is provided at a first section. A second section is detected proximate the first section. The first section is wirelessly coupled with the second section. The data is transferred from the first section to the second section based, at least partially, on the wireless coupling. At least one of the first and the second sections includes a transmitting feature and/or a receiving feature.
US09325372B2 Upstream power amplifier
A communication device includes a communication interface, a number of variable power amplifiers (VPAs), and a processor. Some of the VPAs are configured to process analog signals to generate processed analog signals (e.g., each VPA configured to process one of the analog signals to generate one of the processed analog signals based on a respective VPA control signal). A composite VPA processes a summation of the processed analog signals, which are generated by certain of the VPA, to generate a processed composite signal based on a composite VPA control signal. The processor generates the a first, a second, and a composite VPA control signals based, at least in part, on configuration information from another communication device via the communication interface. The processor may be configured to consider other information as well, such as locally generated information (within the communication device), operational history, current operating conditions, etc.
US09325371B2 Method for managing data transport using crosstalk data
A method and device are provided for affecting data conveyance within a cable comprising a plurality of copper wire lines. The method comprises: providing information about crosstalk interference experienced by the copper wire lines; for each copper wire line experiencing crosstalk interference (interfered line), identifying which other copper wire lines induce crosstalk interference to that interfered line; partitioning the copper wire lines into interference groups, where each interference group comprises at least one copper wire line, wherein at least one of the interference groups comprises at least three copper wire lines, and wherein in case that a given interference group comprises more than two copper wire lines, then each of the copper wire lines belonging to that interference group is subjected to interference induced by another copper wire line that belongs to that interference group; and based on the partitioning step, changing operational settings of at least one copper wire line.
US09325370B2 Synchronization method and system
A method of emission of a frequency synchronization signal comprises a first step of determining at least two first emission frequencies respectively associated with at least two first intervals separated temporally by a first duration. The first temporal intervals are of identical duration. The first durations are identical for identical first frequencies and the first durations are different for different first frequencies. The method also comprises a second step of emitting at least one synchronization signal in the first temporal intervals and by using the first frequency, the signal emitted in the first intervals being identical.
US09325368B2 Gateway wireless communication instrument, wireless communication system, and communication control method
A period is defined to execute the sequences (processes) of communication data acquisition, measuring communication quality, communication quality data acquisition, and channel change. Processing is controlled to execute each process within a time limit set for each process and execute all processes in one cycle. This avoids that a delayed sequence influences and delays other sequences and can suppress delays. If processing fails to finish a sequence, it will resume the same sequence in the next cycle. For communication stations sharing timeslots, there are provided offset periods differing in length before the start of carrier sense in the timeslots for these stations. Consequently, even under a condition in which packet collision may occur, the collision of packets can be avoided by detecting a packet sent to another station by carrier sense. Moreover, by controlling sending priority of packets in the send queue of the gateway, sending delay can be avoided.
US09325366B1 Apparatus for protecting and mounting a personal electronic device having a camera
An apparatus for protecting and mounting a smartphone is provided, comprising: a case comprising: a front cover comprising: a frame; a screen protector coupled to the frame so as to contact a touchscreen of the smartphone; a first plurality of cushions disposed on the interior of the frame so as to contact the sides of the smartphone; and a protrusion, having an aperture, that extends from the exterior of the frame; and a rear cover comprising: a panel; a ridge extending from the interior surface of the panel to engage the interior of the frame when operatively coupled; a second plurality of cushions disposed so as to contact a surface of the smartphone opposite the touchscreen; an aperture through the panel; and optics within the aperture substantially aligned with the a camera of the smartphone.
US09325364B2 Methodology to define optimal sun position using the capability provided by smart phone technology
A smart phone for using to optimize the energy production of a solar panel in real time by a user features a signal processor to receive GPS signaling containing information about the global position of the smart phone, and input signaling containing control information to initiate a GUI algorithm in the signal processor to determine visual and/or audio cues for a user on a proper alignment of a solar panel for optimal solar energy collection efficiency; and provide display imaging signaling from a screen of the smart phone, or audio signaling from a speaker in the smart phone containing information about the visual and/or audio cues for the user on the proper alignment of the solar panel for optimal solar efficiency, so as to enable the user to simultaneously adjust the planar orientation of the solar panel having the smart phone placed thereon, based on the visual and audio cues.
US09325360B2 Reducing non-linearities in a differential receiver path prior to a mixer using calibration
A receiver for a wireless device is described. The receiver includes a low noise amplifier that includes differential inputs. The receiver also includes a mixer coupled to the low noise amplifier. The receiver further includes second-order intermodulation reduction circuitry coupled to a stage subsequent to the low noise amplifier. The second-order intermodulation reduction circuitry provides a biasing of the differential inputs.
US09325355B2 Methods and apparatus for performing impedance matching
A system that incorporates teachings of the subject disclosure may include, for example, determining a first voltage standing wave ratio (VSWR), selecting a VSWR circle from among a group of VSWR circles based on the first VSWR, identifying a group of sets of tuning settings for variable reactance elements of a matching network of the communication device where the identifying of the group of sets of tuning settings is based on each set of tuning settings of the group of sets of tuning settings being associated with the VSWR circle, and selecting a set of tuning settings from among the group of sets of tuning settings responsive to a second VSWR determined for the set of tuning settings satisfying a VSWR threshold. Other embodiments are disclosed.
US09325354B2 Wideband frequency shift modulation using transient state of antenna
Described herein are architectures, platforms and methods for implementing modulating a radiating signal of a high Q antenna in order to transmit from one frequency to one or more different frequencies which may be in the same narrow band frequency spectrum or in a wide band frequency spectrum.
US09325349B2 Encoder, decoder and semiconductor device including the same
Provided is a semiconductor device configured to encode input data into a codeword including M different symbols, each of which includes Nm symbols. The semiconductor device including a first storage unit configured to store a first state value which is reset according to M and Nm; a second storage unit corresponding to any one of the M different symbols and configured to store M second state values determined through the corresponding symbol and the first state value; a third storage unit configured to store a third state value.
US09325341B2 Excess loop delay compensation (ELC) for an analog to digital converter (ADC)
In one embodiment, a circuit includes a quantizer configured to convert an analog input signal to a digital signal. The quantizer includes a first feedback path including a first digital to analog converter (DAC) coupled from an output of the quantizer to a summing junction that is coupled to an input of the quantizer. The first feedback path converts the digital signal to a first corresponding analog value for combining with the analog input signal at the summing junction. Also, the quantizer includes a plurality of excess loop delay (ELD) compensation paths coupled to the summing junction configured to compensate for excess loop delay from a second feedback path coupled from the output of the quantizer to input of the quantizer via a loop filter. Second DACs in the second feedback path convert the digital signal to a second corresponding analog value for combining with the analog input signal.
US09325339B2 System for analog to digital conversion with improved spurious free dynamic range
Generally, this disclosure describes an apparatus, systems and methods for analog to digital conversion with improved spurious free dynamic range. The system includes a segmented ADC circuit with a plurality of interleaved ADC segments, the segmented ADC circuit configured to generate a digital signal including a channel with an associated channel frequency; a frequency down-converter circuit coupled to the segmented ADC circuit, the frequency down-converter circuit configured to frequency shift the digital signal by a frequency offset; a spur frequency prediction circuit coupled to the frequency down-converter circuit, the spur frequency prediction circuit configured to predict frequencies of spurs generated by the ADC segments, the prediction based on the number of ADC segments and based on the sampling rate of the digital signal; the spur frequency prediction circuit further configured to generate the frequency offset based on the predicted spur frequencies and based on a frequency band of the channel; and a filter circuit coupled to the frequency down-converter circuit, the filter circuit configured to remove one or more of the spurs from the frequency shifted digital signal to generate a filtered signal.
US09325330B2 Semiconductor device including a clock adjustment circuit
Disclosed herein is a semiconductor device that includes a first circuit comprising a plurality of first logic elements coupled in cascade and configured, in response to first and second clock signals and a control signal, to produce control information that indicates a first number of the first logic elements through which the control signal has been propagated during a period defined by a first change in logic level of the first clock signal and by a second change in logic level of the second clock signal, the first and second changes occurring adjacently to each other in same directions as each other, and a second circuit comprising a delay circuit configured to receive the first clock signal and the control information and to produce a third clock signal by delaying the first clock signal by an amount responsive to the control information.
US09325325B2 Method and device for managing the time transition of a CMOS logic circuit as a function of temperature
A method includes generation of a first current proportional to absolute temperature and formation of a second current representative of the temperature variation of the threshold voltages of the transistors of the inverter and limited to a fraction of the first current. This fraction is less than one. The inverter is supplied with a supply current equal to the first current minus the limited second current.
US09325324B1 Phase locked loop (PLL) circuit with compensated bandwidth across process, voltage and temperature
A phase locked loop (PLL) circuit includes a phase comparison circuit configured to compare phase of an input signal to phase of a feedback signal and generate a control signal responsive to the phase comparison and an oscillator circuit configured to generate an output signal at a frequency set by said control signal, where said feedback signal is derived from said output signal. The PLL circuit further operates in a calibration mode of operation wherein the oscillator circuit operates in a frequency locked loop mode to compare frequency of the input signal to frequency of the output signal and center a gain of the oscillator circuit across process, voltage and temperature in response to the frequency comparison. Furthermore, bias current for a charge pump within the phase comparison circuit is calibrated during calibration mode of operation to match a temperature independent reference current.
US09325323B2 CMOS oscillator having stable frequency with process, temperature, and voltage variation
A clock signal generation circuit configured to generate the clock signal having a frequency that is maintained across variations in a number of operating conditions, such as changes in supply voltage, temperature and processing time. In an embodiment, the frequency spread of the generated clock signal of a PVT-compensated CMOS ring oscillator is configured to compensate for variations in the supply voltage, as well as for variations in process and temperature via a process and temperature compensation circuit. The PVT-compensated CMOS ring oscillator includes a regulated voltage supply circuit to generate a supply voltage that is resistant to variations due to changes in the overall supply voltage.
US09325321B2 Background auto-refresh apparatus and method for non-volatile memory array
A method for automatically refreshing a non-volatile memory array in the background without memory interruption includes selecting an unrefreshed segment of the memory, reading data from each row in the selected segment during memory dead time and storing the data read from each row in a local temporary storage memory until an entire segment is read out, remapping all memory addresses in the selected segment to the temporary storage memory, isolating column lines in the selected segment from global column lines, erasing the data in the selected segment without disturbing the column lines, rewriting memory data in each row of the selected segment, remapping all memory addresses in the selected segment to the memory, and repeating the process until all segments have been refreshed.
US09325317B2 Semiconductor device and high side circuit drive method
Aspects of the invention can include a pulse generating means that outputs a set signal and reset signal for driving the high potential side switching element is such that, while either one of the set signal or reset signal is in an on-state as a main pulse signal for putting the high potential side switching element into a conductive state or non-conductive state, the other signal is turned on a certain time after the rise of the main pulse signal, thereby generating a condition in which the set signal and reset signal are both in an on-state.
US09325315B2 Nand gate circuit, display back plate, display device and electronic device
The NAND gate circuit includes at least two input transistors, at least two pull-up modules and at least two input control transistors. A first electrode of each input transistor is connected to a second level output end via the pull-up module. The input control transistor is configured to enable a potential of the control end of the pull-up module connected to the first electrode of the input transistor to be the first level when the input signal connected to the gate electrode of the input control transistor is at a second level. The at least two pull-up modules are configured to cut off the connection between the second level output end and the NAND gate output end when all the input signals are at the second level, and enable the connection therebetween when none of the input signals is at the second level.
US09325313B2 Low-power level-shift circuit for data-dependent signals
A low-power level-shift circuit for data-dependent signals includes a buffer circuit, a coupling capacitor, and a biasing circuit. The buffer circuit is biased by a low-voltage domain voltage supply and configured to receive a data-dependent signal. The coupling capacitor is coupled, at a first node, to an output node of the buffer circuit. The biasing circuit is coupled to a second node of the coupling capacitor and a switch. The level-shift circuit can translate a voltage level of the received data-dependent signal to a high-voltage domain that is suitable for proper operation of the switch.
US09325311B1 Gate driver and display device using the same
A gate driver comprises an ith stage gate driver circuit including a latch circuit and a first output circuit. The latch circuit includes a first input for receiving an (i−1)th gate signal, a second input for receiving a first clock signal, a first output for outputting a first output signal, and a second output for outputting a second output signal. The first output circuit comprises a first transistor, a second transistor and a capacitor. The first transistor includes a control terminal coupled to the first output, a first terminal coupled to a first clock input and a second terminal coupled to a first output node. The second transistor includes a control terminal coupled to the second output, a first terminal coupled to the first output node and a second terminal coupled to a reference signal. The capacitor is coupled between the first transistor and the first output node.
US09325307B2 Semiconductor device
The semiconductor device includes first and second output terminals each coupled to one end side and another end side of an inductive or capacitive load, a first MOS transistor coupled between a first voltage and the first output terminal, a second MOS transistor coupled between a second voltage and the first output terminal, a third MOS transistor coupled between the first voltage and the second output terminal, a fourth MOS transistor coupled between the second voltage and the second output terminal, and a drive circuit driving the first to fourth MOS transistors for controlling the inductive or capacitive load, and further includes first and second bypass transistors for bypassing a forward current of a parasitic diode of a PN-junction formed in the MOS transistor in the dead-off period.
US09325306B1 High voltage switch
A high-voltage switching device is formed by: connecting a number of normally-on transistors, such as JFETs, in series with each other, where the drain of each transistor is connected to the source of the next; connecting the chain of normally-on transistors in series with a normally-off switch component, such as a MOSFET, where the drain of the normally-off switch component is connected to the source of the first transistor in the chain in the chain; and, for each transistor, connecting a voltage-clamping device, such as a diode, with the anode of the voltage-clamping device connected to the source of the transistor and the cathode of the voltage-clamping device connected to the gate of the next transistor in the chain.
US09325304B2 Apparatus for controlling comparator input offset voltage
An apparatus to remove an input offset voltage of a comparator circuit includes an input voltage offset capacitor, control logic to charge and discharge the capacitor to provide an offset cancelation voltage. The offset cancellation voltage removes the input offset voltage of the comparator dependent upon an output of the comparator circuit. A switching arrangement controlled by the control logic switches signals between the capacitor and the control logic.
US09325303B2 Button detecting circuit
The present disclosure illustrates a button detecting circuit and method thereof. The button detecting circuit includes a determining circuit, a voltage selector and a button module. The voltage selector is electrically connected to the determining circuit. The voltage selector has a plurality of candidate voltages arranged in sequence based on magnitudes of the candidate voltages. The button module which is electrically connected to the determining circuit via a single one pin comprises a threshold unit and a button network. The determining circuit receives the candidate voltage outputted from the voltage selector and outputs the candidate voltage to the button module for testing whether the threshold unit will be conducted to find a threshold voltage. The button module generates a scanning current based upon the threshold voltage. The determining circuit senses the scanning current and determines which one of a plurality of buttons disposed in the button network is pressed.
US09325301B2 Ramp signal generator and image sensor including the same
A ramp signal generator includes a rising-edge current unit, a falling-edge current unit and a current-voltage converter. The rising-edge current unit provides a rising-edge output current that sequentially increases or decreases in synchronization with rising edges of a clock signal. The falling-edge current unit provides a falling-edge output current that sequentially increases or decreases in synchronization with falling edges of the clock signal. The current-voltage converter outputs a ramp voltage by converting a summed current of the rising-edge output current and the falling-edge output current.
US09325298B2 Receiving circuit
A receiving circuit includes first input transistors of a first conductivity type including control terminals to which differential input signals are applied; load transistors of a second conductivity type connected between a first wiring to which a first voltage is supplied and first terminals of the first input transistors; second input transistors of the second conductivity type including control terminals to which the differential input signals are applied; a latch circuit connected between a second wiring to which a second voltage is supplied and first terminals of the second input transistors; and conversion transistors of the second conductivity type connected in parallel to the second input transistors, the conversion transistors including control terminals that are connected to output nodes to which the first input transistors and the load transistors are connected.
US09325297B2 Power supply control
An integrated circuit includes a clock generation stage that generates a clock signal having a clock frequency dependent on a reference signal. A delay stage generates a delayed clock signal by delaying the clock signal. A control stage generates a control signal indicative of a delay of the delayed clock signal relative to the clock signal. A frequency divider generates a divided signal by dividing a dividend signal having a dividend frequency dependent on the reference signal. A power supply regulator supplies power to the frequency divider at a first power level, which is dependent on the control signal.
US09325295B2 Elastic wave device with integrated inductor
An elastic wave device includes an interdigital transducer (IDT) electrode disposed on an upper surface of a piezoelectric substrate, a wiring electrode disposed on the upper surface of the piezoelectric substrate and connected to the IDT electrode, and a first insulator layer disposed on the upper surface of the piezoelectric substrate. The first insulator layer seals the IDT electrode and the wiring electrode and includes a first resin and a first filler. A resin layer including no filler is provided on an upper surface of the first insulator layer. An inductor electrode is disposed on an upper surface of the resin layer. A second insulator layer is disposed on the upper surface of the resin layer and covers the inductor electrode. A terminal electrode is disposed on an upper surface of the second insulator layer. A connecting electrode electrically connects the wiring electrode, the terminal electrode, and the inductor electrode.
US09325294B2 Microwave acoustic wave filters
An acoustic microwave filter comprises an input and an output, and a plurality of acoustic resonators coupled between the input and the output. The difference between the lowest resonant frequency and the highest resonant frequency of a plurality of resonators in the filter is at least 1.25 times the frequency separation of the resonator with the highest resonant frequency in the plurality of resonators. Another acoustic microwave filter comprises an input and an output, and a plurality of acoustic resonators coupled between the input and the output to form a passband. The frequency difference between a local minimum or a local maximum of a return loss magnitude of the acoustic microwave filter and the edge of the passband is at least once the frequency separation of the resonator with the highest resonant frequency.
US09325290B1 Impedance tuner with adjustable electrical length
Single and multi-probe slide screw impedance tuners use a slabline filled with dielectric and the same probe and center conductor as in air. The dielectric filling reduces the overall tuner length by a factor of 1/√∈r. The increase in loss, and associated reduction in reflection factor, is partly compensated by the shorter size and travel of the probes. A typical length reduction is 40%. Using low loss oil reduces the electric field between probe and center conductor and increases Corona threshold; lubrication of sliding contact between probe and slabline walls and cooling of the center conductor are additional benefits. Probe grounding is established either by adjustable top mounted conductive slabs or spring loaded grounding contact on the probes. The method is most effective for tuners with lowest frequency between 100 and 200 MHz and harmonic tuners with lowest frequency between 200 and 400 MHz.
US09325286B1 Audio clipping prevention
Audio clipping is prevented by attenuating an audio signal in accordance with values retrieved from a gain table. Corresponding amplitude values of a stereo audio signal are evaluated to determine a maximum of the values. The amount by which the maximum exceeds a predetermined threshold is used to calculate a table index, which is used to retrieve a gain value from the gain table. The gain value is then applied to the audio signal. The gain table is configured so that increasing index values produce decreasing gain values.
US09325283B2 Modulation method for switching modulator
An exemplary embodiment of the present disclosure illustrates a modulation method for a switching modulator. Firstly, a data signal is received. Then, a first output signal at a first output side of the switching modulator and a second output signal at a second output side of the switching modulator are generated according to the data signal received, wherein the first output signal is an addition signal of a first pulse signal and the data signal, the second output signal is a second pulse signal, the first pulse signal and the second pulse signal are aligned to a same pulse width, and the pulse width equals to a minimum resolution of the switching modulator.
US09325279B1 Integrated power device with a metal oxynitride active channel for power switching and microwave amplification
One object of this invention is to provide a structure of integrated power transistor device having low thermal budget metal oxynitrides as the active channel on a CMOS logic and control circuit chip to form an integrated intelligent power switching module for power switching. The other object of this invention is to provide a structure of integrated power amplifier transistor device having low thermal budget metal oxynitride active channel layer on a CMOS logic and control circuit chip to form an integrated intelligent microwave power amplifier for RF power amplification.
US09325275B2 Control apparatus and shift-by-wire system using the same
A current limiting circuit restricts electric currents flowing through windings and MOSs such that an average of a current value of the electric currents detected by a current detection circuit is within a predetermined value span. An MPU functions as a reference position learning controller that performs a reference position learning control to restrict the electric currents that flow through the windings and the MOSs using the current limiting circuit while rotating a motor until a detent plate stops at a limit position of a working span, to thereby learn the reference position of the motor. An anomaly detection section of the MPU functions as an anomaly detection controller to detect an anomaly in the current limiting circuit based on the current value detected by the current detection circuit during the reference position learning control.
US09325272B2 Hot standby power supply for a variable frequency drive
A hot standby power supply for a variable frequency drive of a floating vessel is provided. The variable frequency drive may power an electric motor of the floating vessel. The hot standby power supply includes a power input for receiving electric power from a main power supply of the floating vessel. The hot standby power supply also includes a first electric connection configured to supply electric power at a first voltage level to a converter power input of the variable frequency drive, and a second electric connection configured to supply electric power at a second voltage level to control power input of the variable frequency drive. The first voltage level is higher than the second voltage level. A transformer is further provided for transforming received electric power to the first voltage level or to the second voltage level.
US09325271B2 Parallel running control apparatus for inverter generators
In a parallel running control apparatus for an inverter generator A having a first, second and third inverters each connected to three windings wound around an alternator driven by an engine and converts alternating current outputted therefrom to direct/alternating current to output alternating current, and first, second and third controllers to control turning ON/OFF of the switching elements, and the inverter generator A is configured to run in parallel with at least one inverter generator B which is configured to be same as the inverter generator A to output a three-phase alternating current.
US09325269B1 Two stage flux switching machine for an electrical power generation system
An electrical power generation system includes a flux switching machine (FSM) including an FSM rotor operatively connected to an FSM stator, the FSM rotor operatively connected to a shaft, wherein the FSM includes an electrical input/output (i/o) in electrical communication with the FSM stator, and a permanent magnet machine (PMM) including a PMM rotor operatively connected to a PMM stator, the PMM rotor operatively connected to a the shaft, wherein the PMM is electrically connected to the FSM.
US09325264B2 Electric motor drive device
An electric motor drive device 1000 includes: an inverter 3 that drives a motor 4, a voltage division circuit 2 that serves as a neutral point potential detection unit that detects a neutral point potential of a stator winding of the motor 4; and a controller 1 that estimates a rotor position of the motor 4 based on the detected neutral point potential, and that controls the inverter 3 based on an estimation result. A ground potential of the controller 1 is set to a negative side potential or a positive side potential of a DC voltage that is supplied to the inverter 3. The voltage division circuit 2 detects the neutral point potential with reference to the negative side potential or the positive side potential. The controller 1 estimates the rotor position based on a difference between a first neutral point potential detected during the ON/OFF operation of the inverter 3 and a first fixed reference potential (⅔)Emax, and based on a difference between a second neutral point potential detected during the ON/OFF operation and a second fixed reference potential (⅓)Emax.
US09325263B1 Sensorless rotor angle detection circuit and method for a permanent magnet synchronous machine
An estimate of the initial position of a rotor is made by monitoring sensed motor current signals which are amplitude and phase modulated with the rotor flux position in response to a high frequency voltage signal injection. The motor current signals are envelope detected to determine zero crossing points. Samples are taken of the motor current signals at positive and negative offsets from the zero crossing point, with the samples processed to identify a direction of the rotor flux axis. Further samples of at least one motor current signal are taken with respect to a certain phase reference, and the samples compared to resolve a polarity of the rotor flux axis which is indicative of the angular position of the rotor.
US09325261B2 Motor driving method and operating method thereof
Provided is a motor driving circuit which transmits a driving signal to a motor, including a gate driver generating the driving signal corresponding to a pulse width modulation signal, a pulse width modulation signal generator generating the pulse width modulation signal according to Hall sensor signals received from Hall sensors mounted in the motor, a current sensor measuring a link current provided to the gate driver, a low pass filter outputting a filter current that high frequency components are removed from the measured link current, and a minimum power consumption estimating unit generating a lead angle according to a start signal with reference to the filter current, wherein the pulse with modulating signal is changed according to the lead angle.
US09325257B2 Power semiconductor device to reduce voltage variation between terminals
The purpose of the present invention is to reduce variance of a voltage to be applied between the terminals of each of the power semiconductor elements, and to improve lifetime of the power semiconductor elements and reliability of the power semiconductor device. In order to achieve the purpose, in this power semiconductor device, which is provided with three or more power semiconductor elements that are aligned and mounted on a metal wire, and another metal wire different from the metal wire, one terminal of each of the power semiconductor elements being connected to the wire and another one terminal thereof being connected to the other wire, the resistance value of the metal wire in a region where the power semiconductor elements are mounted is higher in the downstream side than that in the upstream side in the electric current flowing direction.
US09325252B2 Multilevel converter systems and sinusoidal pulse width modulation methods
Sinusoidal pulse width modulation (SPWM) control techniques, computer readable mediums, and apparatus are presented for operating a multilevel converter, in which a desired AC node voltage level is determined through comparison of a plurality of carrier signals or values to at least one reference signal or value, and a switching state is selected from a plurality of redundant switching states corresponding to the desired AC node voltage level for generating switching control signals based at least partially on a switched capacitor voltage balancing goal or other control objective.
US09325249B2 Single stage boost-asymmetric LLC
An AC/DC power converter utilizing a single stage boost-asymmetric LLC topology is disclosed. The converter uses a combined pulse width modulation (PWM) and frequency modulation (FM) to achieve dual control for a single main magnetic element (transformer). The transformer provides an output voltage regulation throughout the primary-secondary isolation operating in resonant mode (LLC) by means of frequency modulation, while at the same time its magnetizing inductance is conditioning the input current and providing a boosted high voltage for energy storage purpose by means of duty cycle control. A single pair of complementary primary switches is used to drive the primary winding of the transformer in order to achieve both voltage regulation and power conditioning. The secondary side capacitors and the resonant inductor, which may be either integrated into the transformer or external to the transformer, achieve the resonant function of the transformer.
US09325247B1 Clamped capacitor resonant power converter
A power converter including a transformer, a resonant circuit including the transformer and a resonant capacitor having a characteristic resonant frequency and period, and output circuitry connected to the transformer for delivering a rectified output voltage to a load. Primary switches drive the resonant circuit, a clamp switch is connected to shunt the resonant capacitor, and a switch controller operates the primary switches and the clamp switch in a series of converter operating cycles. The converter operating cycles include power transfer intervals including resonant intervals during which a resonant current at the characteristic resonant frequency flows through a winding of the transformer; and a clamp interval during which the clamp switch provides a low impedance shunt across the resonant capacitor holding the resonant capacitor at a voltage at or near zero volts. The operating cycles may also include energy recycling intervals for charging and discharging capacitances within the converter.
US09325246B1 Flyback apparatus with voltage superposition circuit and overpower protection
A power supply apparatus includes a main converter, a voltage superposition circuit, a voltage detection circuit and a pulse width modulation controller. The voltage superposition circuit is electrically connected to the main converter. The voltage detection circuit is electrically connected to the main converter and the voltage superposition circuit. The pulse width modulation controller is electrically connected to the main converter and the voltage detection circuit. The main converter includes a sensing resistor. The voltage detection circuit detects a sensing voltage of the sensing resistor. The voltage superposition circuit supplies a superposition voltage to the voltage detection circuit when an output voltage of the power supply apparatus is less than a predetermined output voltage, and then the voltage detection circuit sends the sensing voltage and the superposition voltage to the pulse width modulation controller.
US09325244B2 Power supply system
A power supply system includes a plurality of DC-DC converters and at least one operating unit. The DC-DC converters are connected in parallel to one another. The at least one operating unit operates the DC-DC converters such that power is supplied through the DC-DC converters to a predetermined power-supplied object. The at least one operating unit includes a voltage controller, a current limiter, and an increasing unit. The voltage controller operates the DC-DC converters such that output voltages thereof are controlled to be respective target voltage. The current limiter limits output currents of the DC-DC converters so that they are limited with respect to a respective specified value. The increasing unit increases a specified value for at least one DC-DC converter of the DC-DC converters, when all of the plurality of DC-DC converters are activated and output current of at least one other DC-DC converter of the DC-DC converters reaches a specified value for the at least one other DC-DC converter.
US09325238B2 Voltage adjustment method, and voltage pre-regulator power supply circuit and system
A voltage adjustment method, and a voltage pre-regulator power supply circuit and system, that implements highly-efficient output of a power supply in a quasi straight-through state and increases voltage output precision of a circuit. The voltage adjustment method includes receiving a to-be-adjusted voltage through a positive wire input end and a negative wire input end; changing, in a control mode in which a connection time is fixed and a disconnection time is adjusted, a duty cycle for the to-be-adjusted voltage to obtain a primary adjusted voltage; and changing, in a control mode in which a disconnection time is fixed and a connection time is adjusted, a duty cycle for the primary adjusted voltage to obtain an output voltage. The present disclosure is applied to a non-isolated direct-current quasi straight-through pre-regulator power supply.
US09325234B2 Systems and methods for protecting power conversion systems from thermal runaway
System and method for protecting a power conversion system. An example system controller includes a protection component and a driving component. The protection component is configured to receive a feedback signal, a reference signal, and a demagnetization signal generated based on at least information associated with the feedback signal, process information associated with the feedback signal, the reference signal, and the demagnetization signal, and generate a protection signal based on at least information associated with the feedback signal, the reference signal, and the demagnetization signal. The demagnetization signal is related to multiple demagnetization periods of the power conversion system, the multiple demagnetization periods including a first demagnetization period and a second demagnetization period. The driving component is configured to receive the protection signal and output a drive signal to a switch configured to affect a current flowing through a primary winding of the power conversion system.
US09325233B2 DC to DC converter and PWM controller with adaptive compensation circuit
DC to DC converters and PWM controllers are presented in which a slope compensation ramp signal is provided for current control operation via a frequency adaptive compensation circuit with a phase locked loop that provides a control output signal having an amplitude generally proportional to the frequency of a clock signal, and a slope generator circuit generating the slope compensation ramp signal with an amplitude generally proportional to the control output signal amplitude.
US09325231B2 Method and apparatus for storing energy
An energy storage apparatus for storing energy transmitted by a power transmission line includes an elastically deformable component and an actuator-generator. The actuator-generator is coupled to the elastically deformable component such that electrical actuation of the actuator-generator generates tension in the elastically deformable component. The actuator-generator is further coupled to the elastically deformable component such that mechanical actuation of the actuator-generator via a release of tension in the elastically deformable component causes a generation of electrical energy by the actuator-generator.
US09325227B2 Cutting apparatus
A cutting apparatus that includes a base member having a receptacle designed for receiving an accessory, for example a shaft cutting guide when cutting a shaft of an electric motor, or a shaft removal pedestal when cutting a shaft of an electric fan motor. The receptacle is centrally disposed on a first member on the base. The receptacle defines a chamber and a bore for threadably receiving a wing screw, the wing screw for releasably securing the accessory received in the chamber of the receptacle. The shaft cutting guide includes a sleeve sized and shaped for receiving a motor's shaft. The sleeve includes a bore for threadably receiving a wing screw, the wing screw for releasably securing the motor's shaft received in the sleeve. The sleeve further defines a blade guide for guiding a cutting tool during the cutting operation, and includes a mounting shaft sized and shaped for receipt in the chamber of the receptacle.
US09325226B2 Electric motor having a commutator and brushes in sliding contact therewith
An electric motor for moving a vehicle part, the electric motor having a stator with a stator housing, a drive shaft rotatable with respect to the stator, a rotor on the drive shaft and having a rotor winding, a commutator on the drive shaft for supplying an electric current to the rotor winding, at least two brushes mounted on the stator housing, the brushes in sliding contact with the commutator for supplying electric current to the rotor winding, a bushing mounted on the drive shaft adjacent to the commutator, and a cone element mounted on the drive shaft adjacent to the bushing on a side of the bushing facing away from the commutator, the cone element having an outer surface which conforms to the shape of a cone concentrical to the drive shaft and having a tip pointing away from the bushing.
US09325221B2 Apparatus and method for efficiently generating power when a door is acted upon by an outside force
A system for generating electricity from the motion of a door is provided. In one embodiment, the system includes an AC or a DC generator acted upon by a flexible member coupled to at or near an edge of a door opposite a hinge. The sweep of the door causes the flexible member to impart rotary motion to the generator, thereby generating electricity.
US09325219B2 Magnetic motor and method of use
Embodiments of the present invention may include a method of producing mechanical power by moving a coil coupled to a shaft partially into a magnetic cylinder having a magnetic end cap containing a plurality of stacked magnetic forces, changing the magnetic polarity of the shaft, moving the coil out of the magnetic cylinder. In other embodiments, there is an electric motor apparatus comprising a magnetic cylinder, a coil coupled to a shaft, and a means for reversing the magnetic polarity of the shaft.
US09325215B2 Inner-rotor-type motor
An inner-rotor-type motor includes four outer surface portions flush or substantially flush with the motor outer surface of the core-back portion provided in the frame portion of each of the two insulating members of the insulator to secure electrical insulation between the stator core and the coil. The outer surface portions of the frame portion of each of the insulating members are inserted between the leg portions of four corners of each of the cover members attached to the axial opposite sides of the stator core. In this state, the cover members are attached to the stator core. The inner-rotor-type motor makes it possible to easily and cost-effectively manufacture a cover member without impairing the dust-proofness of the interior of the motor and greatly improves ease of assembly.
US09325211B2 Wave winding coil for rotary electrical machine
A wave winding coil for a rotary electrical machine includes a coil conductor including coil side portions and coil end portions, the coil conductor being wound to include a wave winding configuration, a relational expression expressing a total number of the coil side portions included in a phase coil is expressed by a mathematical expression 1 m×k=n×q×2p, and m refers to the number of the phase unit coils that are parallelly connected to each other, k refers to the number of the coil side portions that are serially connected to each other, q refers to the number of serially-connected-conductors per magnetic pole, the serially-connected-conductor belongs to one of the kinds of the coil side portions, 2p refers to the number of the magnetic pole, m refers to a common divisor between q×2p and n.
US09325208B2 Stator with radially mounted teeth
A stator for an electric motor or generator comprising a circumferential support having a plurality of protrusions circumferentially distributed about the support; and a plurality of teeth arranged to receive coil windings, wherein each tooth includes a recess with interlocking means formed within the recess for engaging with a protrusion mounted on the circumferential support in a radial direction.
US09325205B2 Method for driving power supply system
The frequency of high-frequency voltage which is output by a variable high frequency power source included in a power transmitting device is controlled in accordance with the value of electric power received by a power receiving device. That is to say, the frequency of the high-frequency voltage is controlled in accordance with data directly relating to power supply. Thus, electric power is accurately supplied with high transmission efficiency in the power supply system.
US09325202B2 Power control device, power control method, and feed system
Provided is a power control device including a power path switching unit, a voltage conversion unit, a characteristic measurement circuit, and a control unit, wherein the power path switching unit forms a path in which an output of the power generating element is connected to the storage element side by connecting the power generating element to the voltage conversion unit, or a path in which the power generating element is directly connected to the storage element side according to the path switching signal.
US09325201B1 High-power charging devices for charging energy-storage devices
The present invention discloses charging devices for charging energy-storage devices. Charging devices include: an Electro-Magnetic Interference/Radio-Frequency Interference (EMI/RFI) filter for passively suppressing conducted interference present on an alternating-current (AC) power source; optionally, a transformer for transforming power from the AC power source without changing frequency; a rectifier for converting an AC input to a direct-current (DC) output; and a voltage-controlled charger for providing a high-power output having an output voltage and an output current from the AC power source, wherein the output voltage and the output current from the voltage-controlled charger are pulsating DC signals. Preferably, the high-power output has a power-factor value of: greater than about 0.70, greater than about 0.80, greater than about 0.90, greater than about 0.95, or greater than about 0.97. Preferably, the high-power output is a wattage of: greater than about 40W, greater than about 50W, greater than about 60W, or greater than about 70W.
US09325200B2 Charger, control method and terminal apparatus
A charger includes a contactless charging unit that contactlessly charges an apparatus to be charged, a position aligning unit that performs position aligning of the apparatus to be charged, and a reducing unit that reduces an effect of the position aligning unit.
US09325199B2 Wireless charging device
A wireless charging device includes a wireless transmitting module and a wireless receiving module. The wireless transmitting module includes a first outer casing and a wireless transmitting unit disposed inside the first outer casing for generating electromagnetic fields. The wireless receiving module includes a second outer casing, a wireless receiving unit disposed inside the second outer casing for wirelessly receiving the electromagnetic fields generated by the wireless transmitting unit, and at least one electrical connector exposed outside the second outer casing and electrically contacting a portable electronic device. The first outer casing of the wireless transmitting module has at least one first receiving space for receiving the second outer casing and at least one second receiving space for receiving the at least one electrical connector.
US09325197B2 Coil module and electronic apparatus
A coil module is disposed inside an electronic apparatus and receives prescribed power. The coil module includes a loop coil, a plate-like magnetic body that is disposed on the loop coil, and a conductive member that has prescribed conductivity and is disposed parallel with the plate-like magnetic body and on a surface, opposite to a surface on which the loop coil is disposed, of the magnetic body. The conductive member projects outward relative to at least a portion of a circumferential surface of the magnetic body.
US09325196B2 Wireless power transmission apparatus for mobile device
A wireless charging apparatus includes a charging unit configured to transmit power wirelessly to a mobile device, and a power supply unit configured to supply power to the charging unit. The wireless charging apparatus further includes a connecting unit configured to connect the charging unit to the power supply unit such that a position and an angle of the charging unit are adjustable.
US09325194B2 Method of forming a power supply controller and structure therefor
In one embodiment, a power supply controller may be formed including configuring the power supply controller to use an error signal and a ramp signal to control a duty cycle of a switching control signal that is configured to control first and second switches to charge a battery, and configuring the power supply controller to selectively offset a dc value of the ramp signal responsively to detecting the adapter current is greater than a first value wherein offsetting the dc value of the ramp signal changes the duty cycle of the switching control signal to supply current from the battery to a load.
US09325192B2 Battery charging management system for automated guided vehicle and battery charging management method for automated guided vehicle
A battery charging management system for an automated guided vehicle that travels in an unpiloted manner by using a battery as a driving power source and performs a charging operation for the battery using a battery charger provided in a charging station, comprises a charge/discharge monitoring part that monitors a charge/discharge amount of the battery, a charging needlessness threshold voltage setting part that sets a charging needlessness threshold voltage for the battery, and a charging control part that performs the charging operation for the battery using the battery charger when it is determined that a voltage of the battery of the automated guided vehicle arriving at the charging station is lower than the charging needlessness threshold voltage set by the charging needlessness threshold voltage setting part. The charging needlessness threshold voltage setting part is configured to lower the charging needlessness threshold voltage during a particularly set time period.
US09325190B2 Power storage system having current limiting means to control multiple parallel connected battery packs
A power storage system has a plurality of secondary battery packs and a host device. The secondary battery packs each have: secondary batteries; a charge switch means that turns a charging path to the secondary batteries ON and OFF; a discharge switch means that turns a discharging path from the secondary battery ON and OFF; and a current-limiting means that causes the secondary battery to discharge while limiting the current to, or below, a fixed value. When switching from the secondary battery pack connected to the input/output terminals of the system to a first secondary battery pack in which voltage is higher than in the second secondary battery pack, the host device causes the charge switch means of the second secondary battery pack to turn OFF the charging path while in a state in which the current limiting means of the first secondary battery pack will cause a discharge operation to begin while limiting the flow of current.
US09325187B2 Structure of transmission and reception unit in wireless charging system
The present disclosure provides the structure of a transmission and reception unit in a wireless charging system. To this end, according to an embodiment, there is provided a wireless power receiver configured to receive a wireless power signal from a wireless power transmitter to receive wireless power, and the wireless power receiver may include a receiving coil unit comprising a primary coil and a secondary coil receiving the wireless power signal; and a charger configured to charge power which is a sum of wireless power received by the primary coil and the secondary coil, respectively, based on the wireless power signal.
US09325186B2 Charging area displayable wireless charger and controlling method thereof
A wireless charger and controlling method thereof are disclosed, by which a charging area can be displayed in further consideration of user's convenience. The present invention includes a power supply unit configured to supply a power by wireless to a power receiver located in a charging area within a predetermined distance, a light projection unit configured to project a light on an area around the wireless charger, and a control unit configured to control the light projection unit to project the light on the area around the wireless charger to visually discriminate the charging area.
US09325184B2 Apparatus for wirelessly charging a rechargeable battery
The present application relates to apparatus for wirelessly charging a rechargeable battery, the apparatus comprising: a charging resonator assembly for converting energy from a magnetic field external to the apparatus into an electric current; and a charging circuit for charging the battery using the electric current, wherein the charging resonator assembly includes a plurality of microelectromechanical system (MEMS) switches which, when open, divide the charging resonator into a plurality of electrically unconnected resonator portions, and which, when closed, connect the plurality of resonator portions to form a continuous resonator.
US09325177B2 Apparatus and method for balancing cells in a plurality of batteries
An apparatus for balancing a plurality of cells in a battery includes common bus having a connector for connecting to a common bus of another battery. Each of plurality of balancing circuits has a bidirectional voltage converter connected to a given cell of the plurality of cells and a linear current regulator arrangement controls the magnitude of current flow between the bidirectional voltage converter. A controller is connected to the common bus and the plurality of cells and selectively operatives the plurality of balancing circuits to transfer energy between the plurality of cells and the common bus to balance the states of charge of the cells. The balancing circuits are operated in response to actual states of charge of the cells, an average state of charge, a desired voltage level for the common bus, and an actual voltage level on the common bus.
US09325171B2 Impute DC link (IDCL) cell based power converters and control thereof
Power flow controllers based on Imputed DC Link (IDCL) cells are provided. The IDCL cell is a self-contained power electronic building block (PEBB). The IDCL cell may be stacked in series and parallel to achieve power flow control at higher voltage and current levels. Each IDCL cell may comprise a gate drive, a voltage sharing module, and a thermal management component in order to facilitate easy integration of the cell into a variety of applications. By providing direct AC conversion, the IDCL cell based AC/AC converters reduce device count, eliminate the use of electrolytic capacitors that have life and reliability issues, and improve system efficiency compared with similarly rated back-to-back inverter system.
US09325170B2 Matrix-based power distribution architecture
A power management and distribution (PMAD) system includes first and second power supplies, first and second loads and a matrix of solid state power controllers (SSPCs) connected between the first and second power supplies and the first and second loads. The matrix is configured to selectively supply each of the first and second loads with a plurality of different power levels based on on/off states of the SSPCs of the matrix.
US09325166B2 Disconnection of a string carrying direct current power
A direct current (DC) power combiner operable to interconnect multiple interconnected photovoltaic strings is disclosed. The DC power combiner may include a device adapted for disconnecting at least one photovoltaic string from the multiple interconnected photovoltaic strings, each photovoltaic string connectible by a first and second DC power line. The device may include a differential current sensor adapted to measure differential current by comparing respective currents in the first and second DC power lines. A first switch is connected in series with the first DC power line. A control module is operatively attached to the differential current sensor and the first switch. The control module may be operable to open the first switch when the differential current sensor measures the differential current to be greater than a maximum allowed current differential, thereby disconnecting the photovoltaic string from the interconnected photovoltaic strings.
US09325164B2 Electrostatic discharge (ESD) protection device for an output buffer
An electrostatic discharge (ESD) protection device is disclosed. The ESD protection device comprises a trigger circuit, a switch, and an output buffer. When an ESD event occurs, the trigger circuit turns on the switch. One part of the current of the electrostatic discharge (ESD) event may be routed to a ground through the switch from the output buffer coupled to the output pad.
US09325163B2 Cable restrain device with dual-material double wedge chuck
A chuck for a cable fitting includes multiple segments substantially forming a ring shape. Each segment of the multiple segments includes a first tapered surface on a distal end, wherein the first tapered surface slopes from the distal end away from a central axis of the ring, and a second tapered surface on a proximal end, wherein the second tapered surface slopes from the proximal end away from the central axis. The chuck also includes a flexible band to hold the multiple segments in the ring shape. Each segment of the multiple segments is configured to receive compressive forces on the first tapered surface and the second tapered surface to force each segment of the multiple segments inwardly toward the central axis. The multiple segments are configured to engage a cable to secure the cable within the ring shape.
US09325158B2 Electrical enclosure including an integrated dead front and door
An electrical enclosure includes a rear wall, a first side wall, a second side wall, a third side wall and a fourth side wall that define an interior portion for receiving electrical devices. The electrical enclosure further includes a plurality of mounting members mounted to, and projecting outwardly from, the rear wall, and a dead front operatively connected to the plurality of mounting members. The dead front includes a surface having at least one opening receptive of an electrical device and a door pivotally mounted relative to the surface. A trim member is operatively connected to the first and second side walls. The trim member includes first, second, third and fourth sides, and a central opening configured and disposed to enable the door to transition between an open position and a closed position.
US09325154B2 Wavelength-tunable laser apparatus having wavelength measuring function
The present invention relates to a wavelength-tunable laser apparatus which can measure a wavelength in a wavelength-tunable laser diode package structure for dense wavelength division multiplexing (DWDM) having a transistor outline (TO) type appearance. The wavelength-tunable laser apparatus of the present invention is a TO-can type wavelength-tunable laser apparatus comprising: a laser diode chip for emitting a laser beam; a collimator lens for collimating the laser beam; a wavelength-selective filter through which the selected wavelength passes; and a reflecting mirror having an inclined reflective surface, wherein the laser beam is split into a beam which is emitted from the laser diode chip (100), collimated by the collimator lens (200) and emitted through a 45-degree reflective mirror (300) to the outside of a TO-can type package, and a beam which passes through the 45-degree reflective mirror (300), the beam passing through the 45-degree reflective mirror (300) is split into at least two branched beams, a first photodiode (510) is arranged on the path of one branched beam so as to monitor the beam, and wavelength-selective filters (400, 600) having variable transmittance according to the wavelengths and a second photodiode (520) are further arranged on the path of the other branched beam.
US09325153B2 Method to control transmitter optical module
An optical module capable of monitoring an inner temperature thereof by a simple arrangement is disclosed. The optical module installs an avalanche photodiode (APD). The APD generates the first photocurrent under a bias where the APD shows the multiplication factor thereof M equal to the unity, and the second photocurrent under another bias where the multiplication factor becomes greater than the unity. The operating temperature of the laser diode (LD) may be estimated from a ratio of the first photocurrent to the second photocurrent.
US09325145B2 Method for separating FEL output beams from long wavelength radiation
A method for improving the output beam quality of a free electron laser (FEL) by reducing the amount of emission at wavelengths longer than the electron pulse length and reducing the amount of edge radiation. A mirror constructed of thermally conductive material and having an aperture therein is placed at an oblique angle with respect to the beam downstream of the bending magnet but before any sensitive use of the FEL beam. The aperture in the mirror is sized to deflect emission longer than the wavelength of the FEL output while having a minor impact on the FEL output beam. A properly sized aperture will enable the FEL radiation, which is coherent and generally at a much shorter wavelength than the bending radiations, to pass through the aperture mirror. The much higher divergence bending radiations will subsequently strike the aperture mirror and be reflected safely out of the way.
US09325144B2 Two-dimensional multi-beam stabilizer and combining systems and methods
A system and method for stabilizing and combining multiple emitted beams into a single system using both WBC and WDM techniques.
US09325142B2 Optical fiber and fiber laser apparatus using same
An optical fiber propagates a light beam at a predetermined wavelength at least in an LP01 mode and an LP02 mode. A dopant that changes a Young's modulus is doped to at least a part of a waveguide region 12a of a cladding 12 through which a light beam at a predetermined wavelength is propagated and to a region 11b in a core 11 in which the intensity of the light beam in the LP01 mode is greater than the intensity of the light beam in the LP02 mode. At least a part of the Young's modulus in the waveguide region 12a of the cladding 12 is smaller than a Young's modulus in the region 11b in the core 11 in which the intensity of the light beam in the LP01 mode is greater than the intensity of the light beam in the LP02 mode.
US09325140B2 Photonic devices and methods of using and making photonic devices
Examples of the present invention include integrated erbium-doped waveguide lasers designed for silicon photonic systems. In some examples, these lasers include laser cavities defined by distributed Bragg reflectors (DBRs) formed in silicon nitride-based waveguides. These DBRs may include grating features defined by wafer-scale immersion lithography, with an upper layer of erbium-doped aluminum oxide deposited as the final step in the fabrication process. The resulting inverted ridge-waveguide yields high optical intensity overlap with the active medium for both the 980 nm pump (89%) and 1.5 μm laser (87%) wavelengths with a pump-laser intensity overlap of over 93%. The output powers can be 5 mW or higher and show lasing at widely-spaced wavelengths within both the C- and L-bands of the erbium gain spectrum (1536, 1561 and 1596 nm).
US09325138B2 Cable remover
A cable removal device comprises a body comprising a head portion and a rear portion, the rear portion adapted as a handle portion, the head portion comprising a bent portion extending from a front end of the head portion, the bent portion further containing tabs surrounding a gap that extends inward from the front end, the gap adapted to allow the bent portion to extend over a latch release tab of a cable connector device while the latch release tab is maintained in a latched position, without contact therewith until a subsequent movement of the body causes the body to contact the latch release tab and thereby move the latch release tab into a released position that disengages the cable connector device from a commodity connector device.
US09325137B2 Plug connector assembly with firm structure and method of assembling the same
A plug connector assembly includes a mating member, a cable, an internal member, and a strain relief member. The mating member includes an insulative body, some terminals, a latch, and an insulative member. The latch includes a base portion, a latching arm extending from a respective side of the base portion, and a latching portion projecting from an end thereof The internal member has some recessing portions on an surface thereof The strain relief member has some projecting portions filling the recessing portions. A method of assembling the plug connector assembly comprises molding an internal member to enclose a respective part of the mating member and molding plural recessing portions on an outer surface of the internal member, and molding a strain relief member to enclose a respective part of the internal member and molding plural projecting portions on the strain relief member to fill the recessing portions.
US09325133B2 Electrical adapter power rating determination
Electronic circuits are provided for use with various electrical adapters. Two resistors define a voltage divider circuit. One or more resistors are coupled in parallel arrangement with the voltage divider by way of controlled switching. A voltage present within the voltage divider is converted into a digital signal, which is used to determine a power rating for the respective electrical adapter. The power rating is used to control normal operations of a computer or other device. The electrical adapter can optionally include a second resistor that is switched into parallel circuit arrangement with a first resistor during the power rating determination process.
US09325132B2 Power extension cord with movable outlet modules
The present disclosure provides a power extension cord with movable outlet modules, which includes a power input portion, a casing, and a plurality of outlet modules. The power input portion is connected to a city power source. The casing at least includes a first accommodating portion having at least a first sliding track. Each of the outlet modules is electrically connected to the power input portion, and at least one outlet module is movably disposed on the first sliding track. When all the outlet modules are arranged on the first accommodating portion, at least one outlet module becomes immovable on the first sliding track. When one or more outlet modules are dislocated from the first accommodating portion, at least one of the outlet modules becomes movable along the first sliding track. Accordingly, the present disclosure may thus effectively utilize the pin holes associated with each outlet module.
US09325124B2 Photovoltaic connector
Embodiments of the present invention provide a photovoltaic (PV) connector, comprising a first connecting unit and a second connecting unit detachably connected with the first connecting unit, wherein the first connecting unit includes a first conductor, a first stop ring, a first housing and a first conductor core provided inside and detachably connected to the first housing; the first conductor is electrically connected with a pressing end of the first conductor core; the first stop ring is detachably connected with the first housing; the second connecting unit includes a second conductor, a second housing, a second stop ring and a second conductor core provided inside and detachably connected to the second housing; the second conductor is electrically connected with a pressing end of the second conductor core; the second stop ring is detachably connected with the second housing.
US09325112B2 Connector device
A connector device comprises a connector and a mating connector. The connector is mateable with the mating connector and removable from the mating connector. The mating connector includes a mating primary terminal and a mating secondary terminal. The connector includes a housing, a sub-connector, a first operation member and a second operation member. The housing holds a primary terminal while the sub-connector holds a secondary terminal. When the first operation member is operated, the housing is moved, and the primary terminal is connected to the mating primary terminal. When the second operation member is operated, the sub-connector is moved, and the secondary terminal is connected to the mating secondary terminal.
US09325111B2 Electrical center and connector assembly system
An electrical junction box has a connector retainer assembly with a first contact surface, as well as a connector housing assembly with a pivotal lever arm. The lever arm has a first engagement surface. The connector retainer assembly and the connector housing assembly configured so that when the lever arm is moved in a single direction relative to the connector housing assembly, the first engagement surface engages the first contact surface and the connector housing assembly moves relative to the connector retainer assembly from a pre-staged position to an assembled position.
US09325104B2 Gelatinous dielectric material for high voltage connector
A connector device includes a device body and a pin assembly. The connector device includes a bushing portion with a conductive bus having a first bore, a conductive housing with a second bore that is axially aligned with the first bore, an internal chamber separating the first bore and the second bore, and a gelatinous silicone material enclosed within the internal chamber. The pin assembly includes a non-conductive tip and a conductive pin secured to the non-conductive tip. The pin assembly is configured to move axially, within the first and second bores, between a closed position that provides an electrical connection between the conductive bus and the conductive housing and an open position that provides no electrical connection between the conductive bus and the conductive housing. The gelatinous silicone material inhibits voltage arcing across a surface of the non-conductive tip when the pin assembly is in the open position.
US09325103B2 Connector having a housing and a sealing member with contact portion and accomodated portion held in an accomodation portion of the housing
This connector is capable of engaging with a mating-side connector along the vertical direction. The connector is provided with a housing, a plurality of contacts, and a seal member. The housing has a top surface in the vertical direction, and an accommodation part recessed downward from the top surface. The contacts are held in the housing. The contacts are partially accommodated in the accommodation part. The seal member has a contact part and an accommodated part. The contact part is located on the top surface of the housing. The accommodated part extends from the contact part into the accommodation part. The accommodated part is held inside the accommodation part.
US09325100B2 Adapter frame with integrated EMI and engagement aspects
A receptacle assembly with improved EMI leakage reduction and construction is described. The assembly includes a housing in the form of a guide frame that has a hollow interior which accommodates the insertion of an electronic module therein. A heat sink is provided to dissipate heat generated during operation of a module and the heat sink has a base portion that defines a ceiling of the hollow interior. An opening in the top of the guide frame provides an attachment location for the heat sink. A separately formed base plate is inserted into the housing and it defines a bottom of the interior of the housing.
US09325097B2 Connector contacts with thermally conductive polymer
An improved electronic receptacle connector employs contacts that are partially encapsulated with a thermally conductive polymer. The thermally conductive polymer aids in the distribution of heat within the contact and may further form heat transfer features to conduct heat to other connector components such as the shell. The thermally conductive polymer may be used to encapsulate multiple contacts within a substantially unitary block.
US09325096B2 Audio connector receptacle having a U-shaped terminal formed by blanking
A receptacle connector for a male end of an audio plug connector to be inserted therein, includes an insulating body having an interface and a receiving cavity extended backwards from the interface, and at least one first terminal and two second terminals disposed inside the insulating body. The first terminal is located on a side of the male end, and has an extending arm in a plate-type U form. The two second terminals are disposed below or above the male end. All terminals are formed by punching a same strip and each have a soldering portion. The soldering portions are located on a same plane. The two second terminals contact two different contact regions away from a tail end of the male end. The first terminal contacts a contact region that adjoins the tail end of the male end.
US09325092B2 Electric connecting structure
An electric connecting structure includes L-shaped terminals having electric connecting portions and a resin member which contains the electric connecting portions. The L-shaped terminals are assembled to a circuit board so that a mounting direction of electric components to the resin member is substantially parallel to an extending direction of the circuit board. The electric components are mounted to the resin member in a plurality of stages which are stacked in a substantially vertical direction with respect to the extending direction of the circuit board. Mounting planes of the resin member in which the electric components are mounted to the resin member are arranged in a step-like shape so as to be displaced backward in the mounting direction by a unit of the stage in accordance with increasing of a distance from the circuit board.
US09325091B2 Electrical card connector with improved metallic cover
An electrical connector, for receiving an electrical card, includes an insulative housing, a plurality of conductive contacts retained in the insulative housing and a metallic shell covering the insulative housing. The metallic cover and the insulative housing define a receiving cavity. The shell has a top plate, the top plate is formed with a plurality of openings, a plurality of resisting pieces bent downwardly from front edges of the openings, and a plurality of gaps defined between each two adjacent resisting pieces. Each contact has a conductive portion extending into the receiving cavity, and the conductive portions and the gaps of the top plate are alternatively disposed.
US09325088B2 Leg unit with projections with arcuate outer surfaces for engaging a fixing hole in a printed circuit board
A leg unit used for a connector housing, the leg unit being inserted into a fixing hole formed through a printed circuit board from a first surface towards a second surface of the printed circuit board, the leg unit including a first projection having elasticity, a second projection, and a contact portion making contact with the first surface when the leg unit is inserted into the fixing hole, the first and second projections being spaced away from each other and facing each other, a distance between an outer surface of the first projection and an outer surface of the second projection being greater within a predetermined range than an inner diameter of the fixing hole, the first projection including a unit for preventing the leg unit from being released out of the fixing hole after the leg unit has been inserted into the fixing hole.
US09325086B2 Doubling available printed wiring card edge for high speed interconnect in electronic packaging applications
An interconnection assembly for a motherboard uses right-angle edge connectors attached to a bottom side of the motherboard, and vertical header connectors attached to the top side. The header connectors mate with a transition card assembly which includes a transition card having plated through holes that receive pins of the header connectors. Right-angle mezzanine connectors mounted on the transition card have pins that extend into the plated through holes from the top side. The edge connectors and mezzanine connectors both face forward in a common direction. The transition card has holes along a rear edge to retain pressed-in nuts for mounting to a stabilizing bezel. Instead of pins being part of the header connectors, connector caps may be provided with pins having first ends that extend into sockets of the header connectors and second ends that extend into the plated through holes of the transition card.
US09325084B2 Annular coupler for drill stem component
A pair of contact or capacitive HF couplers for drill stem components. Each of the first and second couplers includes a central conductor, a supplemental conductor, and an annular dielectric mechanism. The dielectric mechanism is disposed between the conductors. The conductors are isolated from each other. The supplemental conductor includes two electrical contact surfaces. The central conductor includes an electrical contact surface or electrode such that the couplers are capacitive. The central conductors of the first and second couplers interact electrically in the coupled state. The supplemental conductors of the first and second couplers are in electrical contact in the coupled state. The supplemental conductors surround the central conductors. In the mounted state, the supplemental conductors form a shielding for the central conductors.
US09325081B2 Cable connector with low impedance
A cable connector for soldering to a cable defining some core wires includes an insulative body, a plurality of terminals, and a spacer. Each terminal includes a soldering portion extending rearwardly out of the insulative body soldering to the core wires. The spacer includes some stalls and a respective receiving slot formed between every two adjacent stalls for receiving the soldering portions. The receiving slot includes a first receiving slot proximal to the insulative body and a second receiving slot distal from the insulative body. The second receiving slot includes a lower receiving space and an upper receiving space with a smaller width. The soldering portion of the terminal includes a first portion received in the lower receiving space and a second portion received in the first receiving slot. The width of the first portion is larger than the width of the second portion to reduce the impedance.
US09325080B2 Electronic device with shared antenna structures and balun
An electronic device may be provided with shared antenna structures that can be used to form both a near-field-communications antenna such as a loop antenna and a non-near-field communications antenna such as an inverted-F antenna. The antenna structures may include conductive structures such as metal traces on printed circuits or other dielectric substrates, internal metal housing structures, or other conductive electronic device housing structures. A main resonating element arm may be separated from an antenna ground by an opening. A non-near-field communications antenna return path and antenna feed path may span the opening. A balun may have first and second electromagnetically coupled inductors. The second inductor may have terminals coupled across differential signal terminals in a near-field communications transceiver. The first inductor may form part of the near-field communications loop antenna.
US09325071B2 Patch antenna
A patch antenna includes a dielectric substrate having a body that extends a thickness from a first side to a second side that is opposite the first side. The body of the substrate has a perimeter that is defined by at least one side wall that extends along the thickness of the substrate from the first side to the second side. The body of the substrate has a dielectric constant that is greater than air. The patch antenna also includes a radiating patch positioned on the first side of the body of the substrate, a ground plane positioned on the second side of the body of the substrate, and at least three feed probes electromagnetically coupled to the radiating patch such that the patch antenna is configured to generate a circularly polarized radiation pattern. The feed probes are positioned relative to the body of the substrate such that adjacent feed probes are spaced apart from each other along the body. The feed probes are configured to feed the radiating patch at at least three points with approximately equal power amplitude.
US09325059B2 Communication device and antenna structure thereof
A communication device has an antenna structure including a substrate, a ground element, an open slot and a radiating metal portion. The ground element is disposed on a first surface of the substrate. The open slot is formed on the ground element and substantially parallel with an edge of the ground element, wherein the open slot at least generates a first resonant mode, and a distance between the open slot and the edge of the ground element is shorter than 0.05 wavelength of a center frequency of the first resonant mode. The radiating metal portion is disposed on a second surface of the substrate, wherein the open slot at least partially covers the radiating metal portion, the radiating metal portion at least generates a second resonant mode, and a feed point of the radiating metal portion is electrically coupled to a signal source on the substrate.
US09325058B2 Broadband aircraft wingtip antenna system
An isotropic antenna system internally mounted in the outermost portion of an aircraft wing and in the elevated winglet or similar vertical member of an aircraft wing. The antenna includes a shaped dielectric substrate including a horizontally oriented section located in the horizontally oriented member of the aircraft wing, a vertically oriented section located in the vertically oriented member of the aircraft wing, a first antenna element on the top surface of the dielectric substrate in the vertically oriented member of the aircraft wing, a second antenna element on the top surface and the bottom surface of the dielectric substrate, an antenna feed point coupled to the first antenna element and to the second antenna element, and a Radio Frequency (RF) energy guide coupled to the second antenna element. When the antenna is implemented and installed it does not substantially alter the appearance or aerodynamic characteristics of the aircraft.
US09325057B2 Antenna radiating element
The antenna radiating element includes an antenna configured to transmit a signal having one or more measurable characteristics and a shroud surrounding the antenna and configured to change the one or more measurable characteristics.
US09325055B2 Antenna apparatus having vibration isolation
An antenna apparatus is provided which has a centroid close to a vibration isolation structure and which is hard to vibrate like a pendulum motion when vibration is applied. The antenna apparatus includes a first base plate, an antenna unit disposed at a side of the first base plate and supported by the first base plate, and a counter weight unit disposed at another side of the first base plate opposite to the antenna unit and supported by the first base plate. The antenna apparatus further includes a vibration isolation structure having one end fixed to the first base plate to suppress a vibration of the first base plate, and a second base plate to which other end of the vibration isolation structure is fixed and which is fixed to a moving object or a structural object.
US09325053B2 Method for producing a radio frequency identification (RFID) transponder
A method for producing an RFID transponder. An RFID chip is attached onto a conductive sheet. A portion of an antenna element is cut from the conductive sheet using a laser beam after the RFID chip has been attached to the conductive sheet.
US09325050B2 Compact microstrip to waveguide dual coupler transition with a transition probe and first and second coupler probes
A compact microstrip to waveguide dual coupler transition includes a multilayer printed circuit board configured with a rectangular region on an upper surface of the multilayer printed circuit board, wherein the rectangular region has a pair of long edges and a pair of short edges; a transition probe configured on the upper surface of the multilayer printed circuit board, wherein a terminal of the transition probe extends into the rectangular region through a long edge of the rectangular region, and another terminal of the transition probe is electrically connected to a power amplifier; a first coupler probe configured on the upper surface of the multilayer printed circuit board, wherein a terminal of the first coupler probe extends into the rectangular region; and a second coupler probe configured on the upper surface of the multilayer printed circuit board, wherein a terminal of the second coupler probe extends into the rectangular region.
US09325048B2 Multiplexer with common port feeding structure
A multiplexer with a common port feeding structure is disclosed. The multiplexer with a common port feeding structure of the present invention comprises: a housing comprising an antenna connector connected to an antenna for bidirectional transmitting and receiving and a plurality of input/output connectors bidirectionally inputting and outputting a specific frequency band of wireless signals which are input/output through the antenna; a plurality of band-pass filter units mounted inside the housing to transmit wireless signals at between the antenna connector and the input/output connector to pass a specific frequency band; and a coupling unit having a plurality of feeding members to couple the antenna connector and each of the plurality of band-pass filter units.
US09325047B1 Dynamically reconfigurable bandpass filters
In one embodiment, a dynamically reconfigurable bandpass filter includes a resonator loop and a microfluidic channel proximate to the resonator loop, the channel containing a conductor, wherein the position of the conductor within the channel can be adjusted to change capacitive loading of the resonator loop and therefore change the frequencies that the filter passes. In another embodiment, a filter includes a second resonator loop having comprising switches located at discrete positions along a length of the second resonator loop, wherein opening and closing of the switches changes the effective length of the second resonator loop to change capacitive loading of the first resonator loop.
US09325045B2 Filter and resonator
A filter according to embodiments includes n resonators, an input line, and an output line. Each of the resonators includes a first comb-like structure, a second comb-like structure, and a connection line that connect the first and the second comb-like structure. The first and second comb-like structures have a plurality of first lines and a second line that is connected to one end of the first lines. The first lines of the first and the second comb-like structures are arranged parallel to each other. The connection line has bending portions. Further, a second comb-like structure of a k-th resonator and a first comb-like structure of a (k+1)-th resonator are arranged so as to have an interlaced arrangement, and a second comb-like structure of the (k+1)-th resonator and a first comb-like structure of a (k+2)-th resonator are arranged so as to have an interlaced arrangement.
US09325042B2 RF front end module and mobile wireless device
A wireless communication module comprising including a first transmission bandpass filter that takes a first transmit frequency band as a passband; a second transmission bandpass filter that takes a second transmit frequency band as a passband; a first reception bandpass filter that takes a first receive frequency band as a passband; a second reception bandpass filter that takes a second receive frequency band as a passband; and a plurality of switches, each switch connected to a single one of the bandpass filters.
US09325041B2 Redox polymer energy storage system
An energy storage system includes, in an exemplary embodiment, a first current collector having a first surface and a second surface, a first electrode including a plurality of carbon nanotubes on the second surface of the first current collector. The plurality of carbon nanotubes include a polydisulfide applied onto a surface of the plurality of nanotubes. The energy storage system also includes an ionically conductive separator having a first surface and a second surface, with first surface of the ionically conductive separator positioned on the first electrode, a second current collector having a first surface and a second surface, and a second electrode including a plurality of carbon nanotubes positioned between the first surface of the second current collector and the second surface of the ionically conductive separator.
US09325039B2 System and method for detecting venting of a sealed storage cell
In a system and method for detecting venting of a sealed storage cell, the sealed storage cell comprises a container with a sealing cap adapted to be detached from the container and move in the presence of gas overpressure inside the container to allow venting of the storage cell. The detection system comprises a printed circuit board with a central portion designed to be situated opposite the sealing cap, a peripheral portion surrounding the central portion and connected to the central portion by a hinge adapted to flex during movement of the sealing cap, and at least one frangible portion adapted to break upon movement of the sealing cap. An electrical printed track connects the peripheral portion to the central portion through the hinge and frangible portion(s), and is designed to be broken upon breaking of the frangible portion(s) following movement of the sealing cap.
US09325030B2 High energy density battery based on complex hydrides
A battery and process of operating a battery system is provided using high hydrogen capacity complex hydrides in an organic non-aqueous solvent that allows the transport of hydride ions such as AlH4− and metal ions during respective discharging and charging steps.
US09325021B2 Systems and methods for selective cell and/or stack control in a flowing electrolyte battery
The invention provides in various embodiments methods and systems relating to controlling energy storage units in flowing electrolyte batteries.
US09325019B2 Composite body, collector member, fuel battery cell device, and fuel battery device
A composite body in which the Cr diffusion can be sufficiently reduced and conductivity is good, a collector member, a fuel battery cell device, and a fuel battery device are provided. The composite body includes a substrate containing Cr, and a coating layer covering at least a part of the substrate, in which the coating layer includes a first layer containing Cr among constituent elements excluding oxygen, and including a chromium oxide crystal, a second layer disposed on the first layer, containing Zn, Al, and Cr among the constituent elements excluding oxygen, and including a spinel type crystal, a third layer disposed on the second layer, containing Zn and Mn among the constituent elements excluding oxygen, and including a spinel type crystal, and a fourth layer disposed on the third layer, containing Zn among the constituent elements excluding oxygen, and including a zinc oxide crystal.
US09325014B2 Branched nanostructures for battery electrodes
The invention relates to electrochemical electrodes containing branched nanostructures having increased surface area and flexibility. These branched nanostructures allow for higher anode density, resulting in the creation of smaller, longer-lasting, more efficient batteries which require less area for the same charging capacity. Also disclosed are methods for creating said branched nanostructures and electrodes.
US09325008B2 Solid electrolyte battery and positive electrode active material
Provided are: a solid electrolyte battery using a novel positive electrode active material that functions in an amorphous state; and a novel positive electrode active material that functions in an amorphous state. The solid electrolyte battery includes: a positive electrode layer including a positive electrode active material layer; a negative electrode layer; and a solid electrolyte layer formed between the positive electrode layer and the negative electrode layer, and the positive electrode active material includes a lithium-boric acid compound in an amorphous state, which contains Li, B, any element M1 selected from Cu, Ni, Co, Mn, Au, Ag, and Pd, and O.
US09325006B2 Method for preparing positive active material for lithium ion secondary battery, positive active material prepared thereby, and lithium ion secondary battery including the same
A method for preparing a positive active material for a lithium ion secondary battery, the method including obtaining a mixture by mixing a lithium containing compound and metal oxide, distributing powder of a lithium containing compound into a furnace, and heat treating the mixture in the furnace, wherein a thermal decomposition temperature of the lithium containing compound power distributed into the furnace is lower than that of the lithium containing compound mixed with the metal oxide.
US09325001B2 Composite active material, method for producing composite active material, and battery
The problem of the present invention is to provide a composite active material, which may restrain cracking and peeling of a coating layer, when the composite active material having an active material and the coating layer for coating the surface thereof is kneaded. The present invention solves the above-mentioned problem by providing a composite active material including an active material and a coating layer for coating the surface of the above-mentioned active material, in which microparticles are disposed on the surface thereof, characterized in that the above-mentioned microparticles have a smaller particle diameter than the particle diameter of the active material, and contain Si.
US09324996B2 Carbon nanostructure, metal-supported carbon nanostructure, lithium-ion secondary battery, method for producing carbon nanostructure, and method for producing metal-supported carbon nanostructure
This invention provides a carbon nanostructure including: carbon containing rod-shaped materials and/or carbon containing sheet-shaped materials which are bound three-dimensionally; and graphene multilayer membrane walls which are formed in the rod-shaped materials and/or the sheet-shaped materials; wherein air-sac-like pores, which are defined by the graphene multilayer membrane walls, are formed in the rod-shaped materials and/or the sheet-shaped materials.
US09324994B2 Positive electrode active material with high capacity and lithium secondary battery including the same
A high capacity lithium secondary battery includes a lithium manganese oxide having a layered structure exhibiting a great irreversible capacity in the event of overcharging at a high voltage and a spinel-based lithium manganese oxide. Because it is activated at a high voltage of 4.45 V or higher based on a positive electrode potential, additional lithium for utilizing a 3V range of the spinel-based lithium manganese oxide can be provided and an even profile in the entire SOC area can be obtained. Because the lithium secondary battery includes the mixed positive electrode active material including the spinel-based lithium manganese oxide and the lithium manganese oxide having a layered structure, and is charged at a high voltage, its stability can be improved. Also, the high capacity battery having a large available SOC area and improved stability without causing an output shortage due to a rapid voltage drop in the SOC area can be implemented.
US09324990B2 Battery module
A battery module, which can improve safety against overcharge and puncture on a module basis. The battery module includes a plurality of battery cells arranged in a row, each of the plurality of battery cells including terminals and a safety vent, a plurality of bus bars connecting the plurality of battery cells, a duct mechanically coupled to the plurality of battery cells to seal the safety vent, an extension plate electrically connected to a first battery cell among the plurality of battery cells and extending toward the duct, and a short-circuit plate electrically connected to a second terminal of a second battery cell among the plurality of battery cells and extending toward the duct, wherein the duct is electrically connected to the extension plate and is spaced apart from the short-circuit plate.
US09324985B2 Block copolymer battery separator
The invention herein described is the use of a block copolymer/homopolymer blend for creating nanoporous materials for transport applications. Specifically, this is demonstrated by using the block copolymer poly(styrene-block-ethylene-block-styrene) (SES) and blending it with homopolymer polystyrene (PS). After blending the polymers, a film is cast, and the film is submerged in tetrahydrofuran, which removes the PS. This creates a nanoporous polymer film, whereby the holes are lined with PS. Control of morphology of the system is achieved by manipulating the amount of PS added and the relative size of the PS added. The porous nature of these films was demonstrated by measuring the ionic conductivity in a traditional battery electrolyte, 1M LiPF6 in EC/DEC (1:1 v/v) using AC impedance spectroscopy and comparing these results to commercially available battery separators.
US09324983B2 Battery module for vehicle
An object of exemplary embodiments is to prevent increasing the height of a battery module housing a battery pack and a junction box. In the junction box, resin cases of a high-profile relay and an electric component are fixed to the shielding case wall. A low-voltage electric wire or a high-voltage electric wire is laid out on the metal plate. A resin case cover is put on when the relay and electric component is fixed to the bottom wall or the metal plate. The low-voltage electric wire or the high-voltage electric wire is covered with the case cover, predetermined contact portions of the relay and the electric component are exposed, the low-voltage electric wire or the high-voltage electric wire and a bus bar are disposed on the case cover, and the bus bar, the low-voltage electric wire or the high-voltage electric wire are connected to the exposed contact portions.
US09324979B2 Slidable battery door assembly
A slidable battery door assembly is described. In implementations, the slidable battery door assembly (hereinafter “door assembly”) includes a door that is slidable to control access to a battery compartment for a device. Also included is a battery contact inside the battery compartment that is coupled to the door. When the door is closed, the battery contact holds a battery in place and serves as a portion of an electrical circuit that includes the battery. The door may be slidably opened such that the battery contact releases the battery, allowing the battery to be removed from the battery compartment. Thus, the door assembly enables easy installation and removal of a battery. Further, the door assembly can be positioned to hold a battery securely in place and provide an electrically conductive connection between the battery and an electrical circuit.
US09324977B2 Secondary battery
A secondary battery including an electrode assembly; a case containing the electrode assembly; a cap plate covering an opening of the case; a safety device on the cap plate; a stiffener on the safety device and holding the safety device against the cap plate; and an electrode terminal electrically connected to the electrode assembly and fixing the safety device and the stiffener to the cap plate.
US09324974B2 Laser induced thermal imaging apparatus and laser induced thermal imaging method using the same
A laser induced thermal imaging apparatus includes a nozzle part disposed over a donor film in a vacuum chamber so as to be spaced apart from the donor film, and configured to spray an inactive gas onto an upper surface of the donor film. Also included is a shielding layer disposed on the upper surface of the donor film to make contact with the donor film and shaped so as to be positioned along a circumference or outer edge of the donor film.
US09324971B2 Light-emitting module and light-emitting device
A light-emitting module which efficiently extracts light emitted from a light-emitting element is provided. Alternatively, a light-emitting module having lower power consumption or improved reliability is provided. A light-emitting module includes a window material having a light-transmitting property, a light-emitting element that emits light transmitted from a light-transmitting layer to the window material, and an optical bonding layer between the window material and the light-transmitting layer. The optical bonding layer includes a thick part overlapping the light-emitting element and a thin part surrounding the thick part. The light-transmitting layer, the optical bonding layer, and the window material are provided in decreasing order of refractive index.
US09324970B2 Organic light-emitting display apparatus
An organic light-emitting display apparatus for selectively realizing circular polarization according to external light conditions, including a substrate; an organic light-emitting device on the substrate; a sealing member on the organic light-emitting device; a phase retardation layer on a surface of the substrate, the organic light-emitting device, or the sealing member; and a linear polarization layer on another surface of the substrate, the organic light-emitting device, or the sealing member, wherein the linear polarization layer is located to be closer to a source of external light than the phase retardation layer, and wherein the linear polarization layer comprises a photochromic material.
US09324969B2 Lighting apparatus and lighting unit
A lighting apparatus and a lighting unit. The lighting apparatus includes: a first substrate; an organic light-emitting diode (OLED) which is disposed on the first substrate to define an emission region and emits light; a second substrate which faces the first substrate with the OLED interposed therebetween; and a sealant which is disposed between the first substrate and the second substrate, bonds the first substrate and the second substrate together, and surrounds the OLED at a set or predetermined distance from the OLED, wherein the sealant includes first light-scattering particles which are dispersed in the sealant and diffuse light incident to the sealant.
US09324965B2 Method and system for an organic light emitting diode structure
Disclosed is a system and method for a nano-pillar geometry for increased light extraction properties of an Organic Light Emitting Diode.
US09324963B2 Organic light emitting display device
An organic light emitting display device is disclosed which includes: a first electrode including red, green and blue sub-pixel regions; a first hole injection layer disposed on the first electrode; a first hole transport layer disposed on the hole injection layer; second, third and fourth hole transport layers arranged on the first hole transport layer corresponding to the red, green and blue regions, respectively; an organic emission layer disposed on the second, third and fourth hole transport layers; an electron transport layer disposed on the organic emission layer; and a second electrode disposed on the electron transport layer, the second, third and fourth hole transport layers each having a hole mobility different from an electron mobility of the electron transport layer.
US09324955B2 Triazolium and tetrazolium derivatives as organic light emitters
Provided herein are organic compounds useful in a variety of OLED applications.
US09324954B2 Materials for organic electroluminescent devices
The present invention relates to compounds of the formula (1) and formula (2) which are suitable for use in electronic devices, in particular in organic electroluminescent devices.
US09324951B2 Pyrazine derivative, and light emitting element, display device, electronic device using the pyrazine derivative
It is an object to provide a novel material having a bipolar property, a light emitting element provided with the novel material, and a display device that includes the light emitting element. It is an object to provide a pyrazine derivative represented by the following general formula (g-1).
US09324948B2 Compound for organic optoelectronic device, organic light emitting diode including the same and display including the organic light emitting diode
A compound for an organic optoelectronic device, an organic light emitting diode including the same, and a display device including the organic light emitting diode are disclosed and the compound for an organic optoelectronic device represented by the following Chemical Formula 1 or 2 provides an organic light emitting diode having life-span characteristics due to excellent electrochemical and thermal stability, and high luminous efficiency at a low driving voltage.
US09324947B2 Organic electroluminescent display device and method of manufacturing the same
A substrate on which a plurality of pixel electrodes are disposed is prepared. An organic electroluminescent film 22 is formed with the inclusion of a common layer that continuously covers the plural pixel electrodes. A common electrode is formed on the organic electroluminescent film. The common layer is irradiated with an energy ray above areas between the respective adjacent pixel electrodes with the avoidance of irradiation above the plural pixel electrodes. An electric conductivity of the common layer is reduced above the areas between the respective adjacent pixel electrodes, by irradiation of the energy ray. With this configuration, a current leakage can be prevented between the adjacent pixels.
US09324945B2 Memory cells and methods of forming memory cells
A method of forming a memory cell includes forming an outer electrode material elevationally over and directly against a programmable material. The programmable material and the outer electrode material contact one another along an interface. Protective material is formed elevationally over the outer electrode material. Dopant is implanted through the protective material into the outer electrode material and the programmable material and across the interface to enhance adhesion of the outer electrode material and the programmable material relative one another across the interface. Memory cells are also disclosed.
US09324944B2 Selection device and nonvolatile memory cell including the same and method of fabricating the same
A selection device, non-volatile memory cell, and method of fabricating the same. The selection device employs an oxide laminate structure including a tunneling oxide layer and a metal-cluster oxide layer between first and second electrodes, enabling a high selection ratio and sufficient on-current density to allow program data recordation in a memory cell at relatively low voltage. The non-volatile memory cell includes the selection device electrically connected to a resistive random access memory device, including a resistance change layer, enabling suppression of current leakage from a non-selected adjacent memory cell in an array structure. In the method of fabrication, a tunneling oxide layer is formed by depositing and oxidizing a metal layer to control oxygen vacancy density in the metal-cluster oxide layer, and an interface oxide layer is formed in the tunneling oxide layer by doping of metal-clusters in the metal-cluster oxide layer, improving on-current density of the selection device.
US09324941B2 Semiconductor devices and methods for fabricating the same
A method of fabricating a semiconductor device includes providing a wafer in a chamber of a point-cusp magnetron physical vapor deposition (PCM-PVD) apparatus, the chamber including a metal target. The method further includes providing an inert gas and a reactive gas in the chamber and forming an amorphous conductive layer on the wafer by reacting the reactive gas with a metal atom separated from the metal target by the inert gas.
US09324935B2 Storage element and storage device
Provided is an information storage element comprising a first layer, an insulation layer coupled to the first layer, and a second layer coupled to the insulation layer opposite the first layer. The first layer has a transverse length that is approximately 45 nm or less, or an area that is approximately 1,600 nm2 or less, so as to be capable of storing information according to a magnetization state of a magnetic material. The magnetization state is configured to be changed by a current. The insulation layer includes a non-magnetic material. The second layer includes a fixed magnetization so as to be capable of serving as a reference of the first layer.
US09324934B2 Piezoelectric thin film, piezoelectric element, ink-jet head, and ink-jet printer
A piezoelectric thin film which is of a perovskite type having a tetragonal crystal structure, the tetragonal crystal having a degree of (100) orientation of 80% or higher. The piezoelectric thin film is constituted of a lead lanthanum zirconate titanate (PLZT) which is a lead zirconate titanate (PZT) in which some of the lead has been replaced with lanthanum.
US09324933B2 Piezoelectric material, piezoelectric element, liquid ejecting head, liquid ejecting apparatus, ultrasonic sensor, piezoelectric motor, and power generator
A piezoelectric material contains a first component that is a rhombohedral crystal and that is configured to have a complex oxide with a perovskite structure and Curie temperature Tc1, a second component that is a crystal other than a rhombohedral crystal and that is configured to have a complex oxide with a perovskite structure and Curie temperature e Tc2, and a third component that is a rhombohedral crystal and that is configured to have a complex oxide with a perovskite structure and Curie temperature Tc3 different from the first component, and in which Tc2 is higher than Tc1, Tc3 is equal to or higher than Tc2, and a value of (0.1×Tc1+0.9×Tc2) is equal to or lower than 280° C.
US09324932B2 Piezoelectric device
A piezoelectric device includes a nanoimprinted film which is made from a ferroelectric polymer having a first conformation state and coated on a substrate. The ferroelectric polymer is heated at a temperature between a Curie point (Tc) and a melting point (Tm) of the ferroelectric polymer to cause a change in conformation of the ferroelectric polymer from the first conformation state to a second conformation state, and is then subjected to a nanoimprinting process at an imprinting temperature lower than Tc to cause a change in conformation of the ferroelectric polymer from the second conformation state to a third conformation state that is different from the first conformation state, thereby obtaining the nanoimprinted film.
US09324930B2 Thermal management in electronic devices with yielding substrates
In accordance with certain embodiments, heat-dissipating elements are integrated with semiconductor dies and substrates in order to facilitate heat dissipation therefrom during operation.
US09324925B2 Light emitting device having a metal film extending from the first electrode
To provide a method of manufacturing at low cost a light emitting device that converts the wavelength of light radiated by a light emitting element and emits, the method includes: forming a phosphor layer on a translucent substrate; arranging a plurality of light emitting elements with a predetermined spacing, the light emitting elements having an electrode formed face provided with positive and negative electrodes respectively and arranged with the electrode formed faces on the top; embedding a resin containing phosphor particles so that an upper face of the embedded resin does not bulge over a plane containing the electrode formed faces; and curing the resin, and then cutting and dividing the cured resin, the phosphor layer and the translucent substrate into a plurality of light emitting devices each including one or more of the light emitting elements.
US09324923B2 Multiple-chip excitation systems for white light emitting diodes (LEDs)
Embodiments of the present invention are directed toward white light illumination systems (so called “white LEDs”) that comprise a multi-chip excitation source and a phosphor package. In a two-chip source, the two LEDs may be UV-emitting and blue emitting, or blue-emitting and green-emitting. The phosphor package is configured to emit photoluminescence in wavelengths ranging from about 440 nm to about 700 nm upon co-excitation from the first and second radiation sources. The photoluminescence emitted by the phosphors is at least 40 percent of the total power in the white light illumination, and the portion of the total power in the white light illumination contributed by the first and second radiation sources (LEDs) is less than about 60 percent. This ratio can vary in alternative embodiments, and includes 50/50, 60/40, 70/30, and 80/20, respectively. The white light illumination emitted by the system has in one embodiment a color rendering index (CRI) greater than about 90.
US09324918B2 Semiconductor light emitting device and semiconductor light emitting apparatus
A semiconductor light emitting device includes: a stacked structure unit including first and second semiconductor layers and a light emitting layer between the first and second semiconductor layers; a first electrode on a first major surface of the stacked structure unit on the second semiconductor layer side to connect to the first semiconductor layer; and a second electrode on the first major surface of the stacked structure unit to connect to the second semiconductor layer. The second electrode includes: a first film on the second semiconductor layer and a second film on a rim of the first film. The first film has a relatively lower contact resistance with the second semiconductor layer, compared to the second film. A distance from an outer edge of the second film to the first film is smaller at a central portion than at a peripheral portion of the first major surface.
US09324917B2 Semiconductor light emitting device
According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a second semiconductor layer, a light emitting layer, a bonding pad, a narrow wire electrode and a first insulating layer. The light emitting layer is provided between the first semiconductor layer and the second semiconductor layer and is in contact with the first semiconductor layer. The narrow wire electrode includes a first portion and a second portion. The first portion is provided on a surface of the first semiconductor layer not in contact with the light emitting layer and is in ohmic contact with the first semiconductor layer. The second portion is provided on the surface and located between the first portion and the bonding pad. The narrow wire electrode is electrically connected to the bonding pad. The first insulating layer is provided between the second portion and the first semiconductor layer.
US09324914B2 Semiconductor light-emitting device and process for production thereof
A semiconductor light-emitting device capable of keeping high luminance intensity even if electric power increases, and suitable for lighting instruments such as lights and lamps. The semiconductor device includes a metal electrode layer provided with openings, and is so large in size that the electrode layer has, for example, an area of 1 mm2 or more. The openings have a mean diameter of 10 nm to 2 μm, and penetrate through the metal electrode layer. The metal electrode layer can be produced by use of self-assembling of block copolymer or by nano-imprinting techniques.
US09324912B2 Group III nitride semiconductor light-emitting element and method for producing same
A group III nitride semiconductor light-emitting element having a pn junction hetero structure composed of: an n-type aluminum gallium indium nitride layer; a light-emitting layer disposed contacting the n-type aluminum gallium indium nitride layer and including a gallium indium nitride layer containing crystals having a larger lattice constant than the n-type aluminum gallium indium nitride layer; and a p-type aluminum gallium indium nitride layer provided on the light-emitting layer. Further, the relative atomic concentrations of donor impurities at either interface of the light-emitting layer and within respective layers of the light-emitting element are specified herein.
US09324910B2 Light emitting diode
A device includes: a substrate; and a doped III-V compound layer disposed over the substrate; wherein: the doped III-V compound layer includes an upper boundary; the upper boundary has a micro-roughened texture and a macro-roughened texture where the micro-roughened texture located on; and the upper boundary includes dopant ions that are not present in a remainder of the doped III-V compound layer underneath the upper boundary.
US09324908B2 Nitride semiconductor light-emitting element
Provided is a nitride semiconductor light-emitting element including in order a first n-type nitride semiconductor layer, a second n-type nitride semiconductor layer, an n-type electron-injection layer, a light-emitting layer, and a p-type nitride semiconductor layer, wherein the average n-type dopant concentration of the second n-type nitride semiconductor layer is 0.53 times or less as high as the average n-type dopant concentration of the first n-type nitride semiconductor layer, and the average n-type dopant concentration of the n-type electron-injection layer is 1.5 times or more as high as the average n-type dopant concentration of the second n-type nitride semiconductor layer.
US09324907B2 Gallium-nitride-based light emitting diodes with multiple potential barriers
A light emitting diode (LED) includes an active layer having one or more multilayer potential barriers and at least one well layer. Each multilayer potential barrier includes interlacing first and second InAlGaN thin layers. The first and second InAlGaN thin layers have compositions selected with respect to the well layer such that a polarization effect is substantially reduced.
US09324904B2 Semiconductor light emitting device and light emitting apparatus
A semiconductor light emitting device includes a first conductive semiconductor layer, an active layer, a second conductive semiconductor layer, a first internal electrode, a second internal electrode, an insulating part, and first and second pad electrodes. The active layer is disposed on a first portion of the first conductive semiconductor layer, and has the second conductive layer disposed thereon. The first internal electrode is disposed on a second portion of the first conductive semiconductor layer separate from the first portion. The second internal electrode is disposed on the second conductive semiconductor layer. The insulating part is disposed between the first and second internal electrodes, and the first and second pad electrodes are disposed on the insulating part to connect to a respective one of the first and second internal electrodes.
US09324901B2 Precursor solution for forming a semiconductor thin film on the basis of CIS, CIGS or CZTS
The present invention relates to a precursor solution for forming a semiconductor thin film on the basis of CIS, CIGS or CZTS by printing, comprising metal complexes of at least two different metal cations, wherein the first metal cation is a copper cation and the second is selected from the group consisting of (i) In, (ii) a combination of In and Ga, and (iii) a combination of Zn and Sn, wherein Cu and Sn, if Sn is present, is/are complexed by at least one sulfur or selenium containing anionic complex ligand or polyanion selected from the group consisting of trithiocarbonate, polysulfide or the selenium analogs thereof. If In, In with Ga, or Zn is present, their cations are complexed by an excess of trithiocarbonate and/or triselenocarbonate, and a solvent. A method for preparing such solutions and their use for manufacturing a solar cell or optoelectronic device is provided.
US09324900B2 Method of fabricating a superlattice structure
A method of fabricating a superlattice structure requires that atoms of a first III-V semiconductor compound be introduced into a vacuum chamber such that the atoms are deposited uniformly on a substrate. Atoms of at least one additional III-V compound are also introduced such that the atoms of the two III-V compounds form a repeating superlattice structure of alternating thin layers. Atoms of a surfactant are also introduced into the vacuum chamber while the III-V semiconductor compounds are being introduced, or immediately thereafter, such that the surfactant atoms act to improve the quality of the resulting SL structure. The surfactant is preferably bismuth, and the III-V semiconductor compounds are preferably GaSb along with either InAs or InAsSb; atoms of each material are preferably introduced using molecular beam epitaxy. The resulting superlattice structure is suitably used to form at least a portion of an IR photodetector.
US09324899B2 Emitter diffusion conditions for black silicon
In some cases, it is desirable to perform doping when manufacturing a solar cell to improve efficiency. Dopant diffusion may include the steps of: (a) an initial temperature ramp, (b) dopant vapor flow, (c) drive-in, and (d) cool down. However, doping may result in excessive doping, such as in regions where the solar cell has been nanoscale textured to provide black silicon, thereby creating a dead zone with excessive recombination of charge carriers. In the systems and method discussed herein, dopant vapor flow and drive-in steps may be performed at two different temperature set points to minimize or eliminate the formation of dead zones. In some embodiments, the dopant vapor flow may be performed at a lower temperature set point than the drive-in.
US09324898B2 Varying cadmium telluride growth temperature during deposition to increase solar cell reliability
A method for forming thin films or layers of cadmium telluride (CdTe) for use in photovoltaic modules or solar cells. The method includes varying the substrate temperature during the growth of the CdTe layer by preheating a substrate (e.g., a substrate with a cadmium sulfide (CdS) heterojunction or layer) suspended over a CdTe source to remove moisture to a relatively low preheat temperature. Then, the method includes directly heating only the CdTe source, which in turn indirectly heats the substrate upon which the CdTe is deposited. The method improves the resulting CdTe solar cell reliability. The resulting microstructure exhibits a distinct grain size distribution such that the initial region is composed of smaller grains than the bulk region portion of the deposited CdTe. Resulting devices exhibit a behavior suggesting a more n-like CdTe material near the CdS heterojunction than devices grown with substrate temperatures held constant during CdTe deposition.
US09324896B2 Thermal receiver for high power solar concentrators and method of assembly
A device for dissipating heat from a photovoltaic cell is disclosed. A first thermally conductive layer receives heat from the photovoltaic cell and reduces a density of the received heat. A second thermally conductive layer conducts heat from the first thermally conductive layer to a surrounding environment. An electrically isolating layer thermally couples the first thermally conductive layer and the second thermally conductive layer.
US09324892B2 Solar panel support with integrated ballast channels
A solar panel support sub-assembly includes a bottom rail, a first top rail and a second top rail, each rail having first and second longitudinally opposite ends. The first end of the bottom rail is pivotally coupled to the first end of the first top rail and the second end of the bottom rail is pivotally coupled to the first end of the second top rail. The sub-assembly also includes a ballast rail having a first end that is pivotally coupled to the bottom rail at a first location intermediate the first and second longitudinally opposite ends of the bottom rail. The sub-assembly may be unfolded for assembly by pivoting the first and second top rails within a first plane and pivoting the ballast rail within a second plane that is normal to the first plane.
US09324891B2 Solar cell, solar cell panel, and device comprising solar cell
A solar cell (1) of the present invention includes a photoelectric conversion layer (2) and a photonic crystal provided inside the photoelectric conversion layer (2) in order to have a photonic band gap. The photonic crystal has defects (31) in order to provide a defect level in the photonic band gap. QV which is a Q value representing a magnitude of a resonance effect yielded by coupling between the photonic crystal and an outside is substantially equal to Qα which is a Q value representing a magnitude of a resonance effect yielded by a medium of the photoelectric conversion layer (2).
US09324886B2 Solar cell and method of manufacturing the same
A solar cell and a method of manufacturing the same are disclosed. The solar cell includes a substrate, at least one emitter layer on the substrate, at least one first electrode electrically connected to the at least one emitter layer, and at least one second electrode electrically connected to the substrate. At least one of the first electrode and the second electrode is formed using a plating method.
US09324885B2 Systems and methods to provide enhanced diode bypass paths
Systems and methods are herein disclosed for efficiently allowing current to bypass a group of solar cells having one or more malfunctioning or shaded solar cells without overwhelming a bypass diode. This can be done using a switch (e.g., a MOSFET) connected in parallel with the bypass diode. By turning the switch on and off, a majority of the bypass current can be routed through the switch, which is configured to handle larger currents than the bypass diode is designed for, leaving only a minority of the current to pass through the bypass diode.
US09324883B2 Semiconductor device and method of manufacturing the same
In a power feeding region of a memory cell (MC) in which a sidewall-shaped memory gate electrode (MG) of a memory nMIS (Qnm) is provided by self alignment on a side surface of a selection gate electrode (CG) of a selection nMIS (Qnc) via an insulating film, a plug (PM) which supplies a voltage to the memory gate electrode (MG) is embedded in a contact hole (CM) formed in an interlayer insulating film (9) formed on the memory gate electrode (MG) and is electrically connected to the memory gate electrode (MG). Since a cap insulating film (CAP) is formed on an upper surface of the selection gate electrode (CG), the electrical conduction between the plug (PM) and the selection gate electrode (CG) can be prevented.
US09324879B2 Thin film transistor, method for manufacturing same, and display device
According to one embodiment, a thin film transistor includes a substrate, a gate electrode, a first insulating film, an oxide semiconductor film, a second insulating film, a source electrode, and a drain electrode. The gate electrode is provided on a part of the substrate. The first insulating film covers the gate electrode. The oxide semiconductor film is provided on the gate electrode via the first insulating film. The second insulating film is provided on a part of the oxide semiconductor film. The source and drain electrodes are respectively connected to first and second portions of the oxide semiconductor film not covered with the second insulating film. The oxide semiconductor film includes an oxide semiconductor. Concentrations of hydrogen contained in the first and second insulating films are not less than 5×1020 atm/cm3, and not more than 1019 atm/cm3, respectively.
US09324878B2 Semiconductor device and method for manufacturing the same
It is an object to provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a semiconductor device including an inverted staggered thin film transistor whose semiconductor layer is an oxide semiconductor layer, a buffer layer is provided over the oxide semiconductor layer. The buffer layer is in contact with a channel formation region of the semiconductor layer and source and drain electrode layers. A film of the buffer layer has resistance distribution. A region provided over the channel formation region of the semiconductor layer has lower electrical conductivity than the channel formation region of the semiconductor layer, and a region in contact with the source and drain electrode layers has higher electrical conductivity than the channel formation region of the semiconductor layer.
US09324877B2 Semiconductor device, power diode, and rectifier
An object is to provide a semiconductor device having electrical characteristics such as high withstand voltage, low reverse saturation current, and high on-state current. In particular, an object is to provide a power diode and a rectifier which include non-linear elements. An embodiment of the present invention is a semiconductor device including a first electrode, a gate insulating layer covering the first electrode, an oxide semiconductor layer in contact with the gate insulating layer and overlapping with the first electrode, a pair of second electrodes covering end portions of the oxide semiconductor layer, an insulating layer covering the pair of second electrodes and the oxide semiconductor layer, and a third electrode in contact with the insulating layer and between the pair of second electrodes. The pair of second electrodes are in contact with end surfaces of the oxide semiconductor layer.
US09324875B2 Semiconductor device
A semiconductor device includes a transistor which includes a gate electrode, a gate insulating film in contact with the gate electrode, and a stacked-layer oxide film facing the gate electrode with the gate insulating film provided therebetween. In the semiconductor device, the stacked-layer oxide film includes at least a plurality of oxide films, at least one of the plurality of oxide films includes a channel formation region, a channel length of the transistor is greater than or equal to 5 nm and less than 60 nm, and a thickness of the gate insulating film is larger than a thickness of the oxide film including the channel formation region.
US09324872B2 Back gate single-crystal flexible thin film transistor and method of making
A gate dielectric material and a gate conductor portion are formed on a single-crystal semiconductor material of a substrate. A dielectric structure is then formed surrounding the gate conductor portion and thereafter a stressor layer is formed on the dielectric structure. A controlled spalling process is then performed and thereafter a material removal process can be used to expose a surface of the single-crystal semiconductor material. A source region and a drain region are then formed on the exposed surface of the single-crystal semiconductor material, which exposed surface is opposite the surface including the gate dielectric.
US09324867B2 Method to controllably etch silicon recess for ultra shallow junctions
A method of forming a semiconductor device that includes forming a germanium including material on source and drain region portions of a silicon containing fin structure, and annealing to drive germanium into the source and drain region portions of the fin structure. The alloyed portions of fin structures composed of silicon and germanium are then removed using a selective etch. After the alloyed portions of the fin structures are removed, epitaxial source and drain regions are formed on the remaining portions of the fin structure.
US09324865B2 Method of forming a semiconductor device
A semiconductor device having dislocations and a method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having an isolation feature therein and two gate stacks overlying the substrate, wherein one of the gate stacks is atop the isolation feature. The method further includes performing a pre-amorphous implantation process on the substrate. The method further includes forming a stress film over the substrate. The method also includes performing an annealing process on the substrate and the stress film.
US09324863B2 Semiconductor device
A semiconductor device includes a source/drain feature in a substrate. The source/drain feature has an upper portion and a lower portion, the upper portion having a lower concentration of Ge than the lower portion. A Si-containing layer over the source/drain feature includes a metal silicide layer.
US09324854B2 Semiconductor device comprising self-aligned contact elements and a replacement gate electrode structure
A semiconductor device includes a high-k metal gate electrode structure that is positioned above an active region, has a top surface that is positioned at a gate height level, and includes a high-k dielectric material and an electrode metal. Raised drain and source regions are positioned laterally adjacent to the high-k metal gate electrode structure and connect to the active region, and a top surface of each of the raised drain and source regions is positioned at a contact height level that is below the gate height level. An etch stop layer is positioned above the top surface of the raised drain and source regions and a contact element connects to one of the raised drain and source regions, the contact element extending through the etch stop layer and a dielectric material positioned above the high-k metal gate electrode structure and the raised drain and source regions.
US09324853B2 III-V semiconductor device having self-aligned contacts
A method including forming a pair of inner spacers along a vertical sidewall of a gate trench, gate trench extending into a III-V compound semiconductor-containing heterostructure, forming a gate conductor within the gate trench, removing a portion of a first dielectric layer selective to the gate conductor and the pair of inner spacers, forming a pair of outer spacers adjacent to the pair of inner spacers, the outer spacers are in direct contact with and self-aligned to the inner spacers, and forming a pair of source-drain contacts within an uppermost layer of the III-V compound semiconductor-containing heterostructure, the pair of source-drain contacts are self-aligned to the pair of outer spacers such that an edge of each individual source-drain contact is aligned with an outside edge of each individual outer spacer.
US09324849B2 Structures and techniques for using semiconductor body to construct SCR, DIAC, or TRIAC
Switch devices, such as Silicon Controlled Rectifier (SCR), DIAC, or TRIAC, on a semiconductor body are disclosed. P/N junctions can be built on a semiconductor body, such as polysilicon or active region body on an insulated substrate, with a first implant in one end and a second implant in the other end. The first and second implant regions are separated with a space. A silicide block layer can cover the space and overlap into both implant regions to construct P/N junctions in the interface.
US09324848B2 Semiconductor device
A semiconductor device includes a first conductivity-type drift layer, a second conductivity-type base layer formed in a front surface portion of the drift layer, a second conductivity-type collector layer formed in the drift layer and separated from the base layer, gate insulation layers formed on a surface of the base layer, gate electrodes individually formed on the gate insulation layers, an emitter layer formed in a front surface portion of the base layer, an emitter electrode electrically connected to the emitter layer and the base layer, and a collector electrode electrically connected to the collector layer. A rate of change in a gate voltage of a part of the gate electrodes is smaller than a rate of change in a gate voltage of a remainder of the gate electrodes. The emitter layer is in contact with only the gate insulation layers provided with the part of the gate electrodes.
US09324846B1 Field plate in heterojunction bipolar transistor with improved break-down voltage
A method of forming a heterojunction bipolar transistor including a field plate. The method may include forming: a substrate having a selectively implanted collector (SIC) and a collector separated by a shallow trench isolation (STI), a field plate in the STI, the field plate extends below a top surface of the SIC, a base layer directly on the SIC, a heterojunction bipolar transistor (HBT) structure above the SIC, the HBT includes an emitter, the emitter is directly on the base layer, a fourth dielectric layer covering the HBT structure, the field plate and the collector, and an emitter contact, a field plate contact and a collector contact extending through the fourth dielectric layer, the emitter contact is in electrical connection with the emitter, the field plate contact is in electrical connection with the field plate and the collector contact is in electrical connection with the collector.
US09324843B2 High germanium content silicon germanium fins
Thermal condensation is employed to obtain a finned structure including strained silicon germanium fins having vertical side walls and a germanium content that may be high relative to silicon. A hard mask is used directly on a low-germanium content silicon germanium layer. The hard mask is patterned and fins are formed beneath the hard mask from the silicon germanium layer. Thermal condensation in an oxidizing ambient causes the formation of regions beneath the hard mask that have a high germanium content. The hard mask is trimmed to a target critical dimension. The regions beneath the hard mask and adjoining oxide material are subjected to reactive ion etch, resulting in the formation of high-germanium content fins with planar, vertically extending sidewalls.
US09324841B2 Methods for preventing oxidation damage during FinFET fabrication
Embodiments of the present invention provide improved methods for fabricating field effect transistors such as finFETs. Stressor regions are used to increase carrier mobility. However, subsequent processes such as deposition of flowable oxide and annealing can damage the stressor regions, diminishing the amount of stress that is induced. Embodiments of the present invention provide a protective layer of silicon or silicon oxide over the stressor regions prior to the flowable oxide deposition and anneal.
US09324837B2 Semiconductor device with vertical gate and method of manufacturing the same
A gate electrode is formed in a trench reaching a drain region so as to leave a concave portion on the top of the trench. A first insulating film is formed, which fills the concave portion and of which the thickness increases as the distance from an end of the trench increases on the substrate surface on both sides of the trench. First and second source regions are formed in a self-alignment manner by introduction of impurities through the first insulating film.
US09324836B2 Methods and apparatus for doped SiGe source/drain stressor deposition
A method of manufacturing a semiconductor device includes etching a recess into a substrate and epitaxially growing a source/drain region in the recess. The source/drain region includes a first undoped layer of stressor material lining the recess, a lightly doped layer of stressor material over the first undoped layer, a second undoped layer of stressor material over the lightly doped layer, and a highly doped layer of stressor material over the second undoped layer.
US09324829B2 Method of forming a trench electrode device with wider and narrower regions
A method includes forming a trench extending from a first surface of a semiconductor body into the semiconductor body such that a first trench section and at least one second trench section adjoin the first trench section, wherein the first trench section is wider than the second trench section. A first electrode is formed, in the at least one second trench section, and dielectrically insulated from semiconductor regions of the semiconductor body by a first dielectric layer. An inter-electrode dielectric layer is formed, in the at least one second trench section, on the first electrode. A second electrode is formed, in the at least one second trench section on the inter-electrode dielectric layer, and in the first trench section, such that the second electrode at least in the first trench section is dielectrically insulated from the semiconductor body by a second dielectric layer.
US09324825B2 Manufacturing method of a graphene-based electrochemical sensor, and electrochemical sensor
A manufacturing method of an electrochemical sensor comprises forming a graphene layer on a donor substrate, laminating a film of dry photoresist on the graphene layer, removing the donor substrate to obtain an intermediate structure comprising the film of dry photoresist and the graphene layer, and laminating the intermediate structure onto a final substrate with the graphene layer in electrical contact with first and second electrodes positioned on the final substrate. The film of dry photoresist is then patterned to form a microfluidic structure on the graphene layer and an additional dry photoresist layer is laminated over the structure. In one type of sensor manufactured by this process, the graphene layer acts as a channel region of a field-effect transistor, whose conductive properties vary according to characteristics of an analyte introduced into the microfluidic structure.
US09324820B1 Method for forming semiconductor structure with metallic layer over source/drain structure
A semiconductor structure and a method for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a source/drain structure over a substrate and forming a metal layer on the source/drain structure. The method for manufacturing a semiconductor structure further includes reacting a portion of the metal layer with the source/drain structure to form a metallic layer on the source/drain structure. The method for manufacturing a semiconductor structure further includes removing an unreacted portion of the metal layer on the metallic layer by an etching process. In addition, the etching process includes using an etchant including HF and propylene carbonate, and the volume ratio of HF to propylene carbonate in the etchant is in a range from about 1:10 to about 1:10000.
US09324816B2 Semiconductor device
According to one embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer provided in a portion on the first semiconductor layer, a first insulating layer provided on the first semiconductor layer on a terminal region side of the second semiconductor layer, a third semiconductor layer provided on the first semiconductor layer on the terminal region side of the first insulating layer, a second insulating layer provided on the first semiconductor layer on the terminal region side of the third semiconductor layer, a fourth semiconductor layer provided between the first semiconductor layer and the second insulating layer, and a plurality of field plate electrodes provided inside an inter-layer insulating film, the plurality of field plate electrodes having mutually-different distances from the first semiconductor layer.
US09324815B2 Semiconductor device
According one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode and being in contact with the first electrode; a second semiconductor layer including a first part and a second part, and the second part being contact with the first electrode, and the second semiconductor layer having an effective impurity concentration lower than an effective impurity concentration in the first semiconductor layer; a third semiconductor layer provided between the second semiconductor layer and the second electrode, and having an effective impurity concentration lower than an effective impurity concentration in the second semiconductor layer; and a fourth semiconductor layer provided between the third semiconductor layer and the second electrode, and being in contact with the second electrode.
US09324811B2 Structures and devices including a tensile-stressed silicon arsenic layer and methods of forming same
Structures including a tensile-stressed silicon arsenic layer, devices including the structures, and methods of forming the devices and structures are disclosed. Exemplary tensile-stressed silicon arsenic layer have an arsenic doping level of greater than 5 E+20 arsenic atoms per cubic centimeter. The structures can be used to form metal oxide semiconductor devices.
US09324809B2 Method and system for interleaved boost converter with co-packaged gallium nitride power devices
An electronic package includes a leadframe and a plurality of pins. The electronic package also includes a first gallium nitride (GaN) transistor comprising a source, gate, and drain and a second GaN transistor comprising a source, gate, and drain. The source of the first GaN transistor is electrically connected to the leadframe and the drain of the second GaN transistor is electrically connected to the leadframe. The electronic package further includes a first GaN diode comprising an anode and cathode and a second GaN diode comprising an anode and cathode. The anode of the first GaN diode is electrically connected to the leadframe and the anode of the second GaN diode is electrically connected to the leadframe.
US09324796B2 Gate-all-around nanowire MOSFET and method of formation
A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench.
US09324795B2 Gate-all-around nanowire MOSFET and method of formation
A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench.
US09324794B2 Self-formation of high-density arrays of nanostructures
A method for forming nanostructures includes bonding a flexible substrate to a crystalline semiconductor layer having a two-dimensional material formed on a side opposite the flexible substrate. The crystalline semiconductor layer is stressed in a first direction to initiate first cracks in the crystalline semiconductor layer. The first cracks are propagated through the crystalline semiconductor layer and through the two-dimensional material. The stress of the crystalline semiconductor layer is released to provide parallel structures including the two-dimensional material on the crystalline semiconductor layer.
US09324792B1 FinFET including varied fin height
According to another embodiment, a semiconductor finFET device includes a semiconductor substrate. The finFET device further includes at least one first semiconductor fin on the semiconductor substrate. The first semiconductor fin comprises a first semiconductor portion extending to a first fin top to define a first height, and a first insulator portion interposed between the first semiconductor portion and the semiconductor substrate. A second semiconductor fin on the semiconductor substrate has a second semiconductor portion extending to a second fin top to define a second height, and a second insulator portion interposed between the second semiconductor portion and the semiconductor substrate, the second height being different from the first height.
US09324789B1 Memory device and method for fabricating the same
The memory device is provided to include a substrate, a plurality of stack structures, conductive pillars, charge storage layers, and third conductive layers. The stack structures are arranged along a first direction and extend along a second direction, wherein each stack structure includes a plurality of first conductive layers and a plurality of dielectric layers that are alternately stacked along a third direction. Each conductive pillar is located on the substrate between two adjacent stack structures. Each charge storage layer is disposed between the stack structures and the conductive pillars. Each third conductive layer extending along the first direction overlaps the stack structures in a plurality of overlapped regions and covers a portion of top parts of the stack structures and the conductive pillars. An air gap is formed along the third direction in each overlapped region where the stacked structures and the third conductive layers overlap.
US09324788B2 Semiconductor device
In a semiconductor device, a lightly doped second semiconductor layer of a first conductive type is joined with a heavily doped first semiconductor layer of the first conductive type. A power transistor having a first conductive type channel and a transistor are formed in surface regions of the second semiconductor layer, respectively. A first diffusion layer of a second conductive type is formed in a surface region of the second semiconductor layer to provide a boundary between the power transistor and the transistor. The first semiconductor layer functions as a drain of the power transistor. The first diffusion layer region is set to the same voltage as that of the drain.
US09324786B2 Semiconductor device and method for fabricating the same
A semiconductor device includes a semiconductor layer, a plurality of first doped regions, a gate structure, and second and third doped regions. The semiconductor layer has a first conductivity type. The first doped regions are in parallel disposed in a portion of the semiconductor layer along a first direction and have a second conductivity type and a rectangular top view. The gate structure is disposed over a portion of the semiconductor layer along a second direction, covering a portion of the first doped regions. The second doped region is disposed in the semiconductor layer along the second direction, being adjacent to a first side of the gate structure and having the second conductivity type. The third doped region is formed in the semiconductor layer along the second direction, being adjacent to a second side of the gate structure opposing the first side and having the second conductivity type.
US09324781B2 Semiconductor devices and methods of fabricating the same
Provided are semiconductor devices and methods of fabricating the same. The methods may include forming a molding layer on a semiconductor substrate. A storage electrode passing through the molding layer is formed. A part of the storage electrode is exposed by partially etching the molding layer. A sacrificial oxide layer is formed by oxidizing the exposed part of the storage electrode. The partially-etched molding layer and the sacrificial oxide layer are removed. A capacitor dielectric layer is formed on the substrate of which the molding layer and the sacrificial oxide layer are removed. A plate electrode is formed on the capacitor dielectric layers.
US09324777B2 Organic light emitting display device
There is provided an organic light emitting display device for preventing short and voltage drop between lines to improve yield. The organic light emitting display device includes: a plurality of sub-pixels located at crossing regions of a plurality of gate lines and a plurality of data lines; first power lines for supplying a voltage for driving the sub-pixels, each of the first power lines being shared by two adjacent sub-pixels from among the plurality of sub-pixels; and initial power lines for supplying an initial power to the sub-pixels, each of the initial power lines being shared by the two adjacent sub-pixels and located between the two adjacent sub-pixels.
US09324775B2 Light emitting device
A light emitting device is provided which can prevent a change in gate voltage due to leakage or other causes and at the same time can prevent the aperture ratio from lowering. A capacitor storage is formed from a connection wiring line, an insulating film, and a capacitance wiring line. The connection wiring line is formed over a gate electrode and an active layer of a TFT of a pixel, and is connected to the active layer. The insulating film is formed on the connection wiring line. The capacitance wiring line is formed on the insulating film. This structure enables the capacitor storage to overlap the TFT, thereby increasing the capacity of the capacitor storage while keeping the aperture ratio from lowering. Accordingly, a change in gate voltage due to leakage or other causes can be avoided to prevent a change in luminance of an OLED and flickering of screen in analog driving.
US09324771B2 Organic light-emitting display apparatus and method of manufacturing the same
An organic light-emitting display apparatus includes a first substrate including a display unit having a light-emitting region and a non-light-emitting region, a second substrate parallel to the first substrate, and a reflective member on a surface of the second substrate that faces the first substrate, the reflective member corresponding to the non-light-emitting region of the display unit and being configured to sense touch, and the reflective member including a plurality of first pattern parts electrically connected along a first direction and a plurality of second pattern parts electrically connected along a second direction.
US09324768B1 System and method of shared bit line MRAM
An STT magnetic memory includes adjacent columns of STT magnetic memory elements having a top electrode and a bottom electrode. A shared bit line is coupled to the top electrode of the STT magnetic memory elements in at least two of the adjacent columns. The bottom electrodes of the STT magnetic memory elements of one of the adjacent columns are selectively coupled to one source line, and the bottom electrodes of the STT magnetic memory elements of another among the adjacent columns are selectively coupled to another source line.
US09324767B1 Superconducting junctions
Provided are superconducting tunnel junctions, such as Josephson tunnel junctions, and a method of fabricating thereof. A junction includes an insulator disposed between two superconductors. The junction may also include one or two interface layers, with each interface layer disposed between the insulator and one of the superconductors. The interface layer is configured to prevent oxygen from entering the adjacent superconductor during fabrication and operation of the junction. Furthermore, the interface layer may protect the insulator from the environment during handling and processing of the junction, thereby allowing vacuum breaks after the interface layer is formed as well as new integration schemes, such as depositing a dielectric layer and forming a trench in the dielectric layer for the second superconductor. In some embodiments, the junction may be annealed during its fabrication to move oxygen from the superconductors and/or from the insulator into the one or two interface layers.
US09324764B2 Array substrate and display device
Embodiments of the present invention relate to an array substrate and a display device comprising the array substrate. According to an embodiment of the invention, there is provided an array substrate which comprises: a terminal region; and an active pixel region, the active pixel region comprising: a plurality of pixel units; a plurality of gate lines; a plurality of data lines; and a plurality of gate leading wires, wherein two columns of the plurality of pixel units are provided between two adjacent data lines among the plurality of data lines, each of the plurality of gate leading wires is disposed between the two columns of the plurality of pixel units, and each of the plurality of gate lines is connected to respective one of the plurality of gate leading wires.
US09324760B2 CMOS integrated method for fabrication of thermopile pixel on semiconductor substrate with buried insulation regions
A method for manufacturing an imaging device in a semiconductor substrate is disclosed. The substrate includes a first surface, a second surface substantially opposite the first surface, and a thickness defined by a distance between the first surface and the second surface. A trench is fabricated in the semiconductor substrate first surface. A passivation layer is applied over the substrate first surface and the trench, optionally filling the trench by depositing a conformal layer over the substrate first surface. The conformal layer and the passivation layer are planarized from the substrate first surface, and a membrane is fabricated on the substrate first surface. From the substrate second surface, a cavity is formed in the substrate abutting the membrane and at least a portion of the trench via the unmasked region.
US09324759B2 Image sensor pixel for high dynamic range image sensor
An image sensor pixel for use in a high dynamic range image sensor includes a first photodiode and a second photodiode. The first photodiode include a first doped region, a first lightly doped region, and a first highly doped region disposed between the first doped region and the first lightly doped region. The second photodiode has a second full well capacity substantially equal to a first full well capacity of the first photodiode. The second photodiode includes a second doped region, a second lightly doped region, and a second highly doped region disposed between the second doped region and the second lightly doped region. The first photodiode can be used to for measuring low light and the second photodiode can be used for measuring bright light.
US09324755B2 Image sensors with reduced stack height
An imaging system may include an image sensor die stacked on top of a digital signal processor (DSP) die. The image sensor die may be a backside illuminated image sensor die. Through-oxide vias (TOVs) may be formed in the image sensor die and may extend at least partially into in the DSP die to facilitate communications between the image sensor die and the DSP die. Bond pad structures may be formed on the surface of the image sensor die and may be coupled to off-chip circuitry via bonding wires soldered to the bad pad structures. Color filter elements may be formed over active image sensor pixels on the image sensor die. Microlens structures may be formed over the color filter elements. An antireflective coating (ARC) liner may be simultaneously formed over the microlens structures and over the bond pad structures to passivate the bond pad structures.
US09324750B2 Imaging device and imaging apparatus
Disclosed herein is an imaging device including at least one special pixel with a configuration having a layout made different from the layout of the configuration of each pixel other than the special pixel. The special pixel is a pixel having an imaging characteristic steadily different from that of the other pixels. A difference in layout between the configuration of the special pixel and the configuration of the other pixels is used to suppress a non-uniformity of the imaging characteristic exhibited by the special pixel.
US09324748B2 Semiconductor package including an image sensor and a holder with stoppers
A semiconductor package includes a substrate, an image sensor chip mounted on the substrate, a holder disposed on the substrate and surrounding the image sensor chip, and the holder has an inner surface facing the image sensor chip and an outer surface opposite to the inner surface. The semiconductor package further includes a transparent cover combined with the holder, and the transparent cover is spaced apart from and faces the substrate. The holder includes: a hole penetrating the holder from the inner surface to the outer surface. In addition, the semiconductor package further includes a first stopper disposed in the hole and a second stopper disposed at a position corresponding to the hole on the outer surface of the holder.
US09324747B2 Imaging device
An imaging device is provided at a lower manufacturing cost. In a light-receiving portion of an imaging device which includes the light-receiving portion, a first transistor connected to the light-receiving portion, and a peripheral circuit, a comb-like n-type semiconductor and a comb-like p-type semiconductor are arranged so as to engage with each other in a plan view. Further, the light-receiving portion and the first transistor overlap with each other. The peripheral circuit includes a second transistor and a third transistor. Further, the second transistor and the third transistor include semiconductor layers having different bandgaps. Further, one of the semiconductor layers of the second transistor and the third transistor has the same bandgap as a semiconductor layer of the first transistor.
US09324745B2 Large format short wave infrared (SWIR) focal plane array (FPA) with low noise and high dynamic range
The present invention presents unit cell architecture for infrared imaging, which has two input stages covering for both low and high light levels, and automatic input selection circuitry inside to extend dynamic range. The invention mainly helps to extend dynamic range of near visible (NIR) and short wave infrared (SWIR) image sensors by improving SNR value. The idea is applicable to not only infrared bands including NIR, SWIR, MWIR and LWIR but also full spectrum light.
US09324740B2 Organic light emitting diode display device and method of fabricating the same
An organic light emitting diode display device comprises a driving thin film transistor including a first semiconductor layer, a gate insulating layer formed on the first semiconductor layer. The device further includes a storage capacitor including a first capacitor electrode electrically coupled to a drain electrode of the driving thin film transistor, a buffer layer formed on the first capacitor electrode, a second semiconductor layer formed on the buffer layer, and a second capacitor electrode formed on the second semiconductor layer and electrically coupled to a gate electrode of the driving thin film transistor. The device also includes an organic light emitting diode connected to the drain electrode of the driving transistor. The gate insulating layer has at least one hole in a region where the gate insulating layer overlaps the second semiconductor layer, thereby exposing the second semiconductor layer to the second capacitor electrode.
US09324736B2 Thin film transistor substrate having metal oxide semiconductor and manufacturing the same
The present disclosure relates to a thin film transistor substrate having a metal oxide semiconductor for flat panel displays and a method for manufacturing the same. The present disclosure suggests a thin film transistor substrate including: a gate electrode on a substrate; a gate insulating layer covering the gate electrode; a source electrode overlapping with one side of the gate electrode on the gate insulating layer; a drain electrode being apart from the source electrode and overlapping with other side of the gate electrode on the gate insulating layer; an oxide semiconductor layer contacting an upper surface of the source electrode and the drain electrode, and extending from the source electrode to the drain electrode; and an etch stopper having the same shape with the oxide semiconductor layer, and contacting an upper surface of the oxide semiconductor layer.
US09324735B2 Array substrate and manufacturing method thereof, display panel and display device
The present invention provides an array substrate and a manufacturing method thereof, a display panel and a display device. The array substrate includes a plurality of pixel units, each of which includes: a TFT area provided with a TFT including a gate, a gate insulation layer, an active area, a source and a drain; and a display area provided with a pixel electrode.
US09324734B2 Semiconductor device having semiconductor layers with different thicknesses
A semiconductor device has a first element region, a second element region, and a first isolation region in a thin film region and a third element region, a fourth element region, and a second isolation region in a thick film region. It is manufactured with step (a) of providing a substrate having a silicon layer formed via an insulating layer, step (b) of forming element isolation insulating films in the silicon layer in the first isolation region and the second isolation region of the substrate step (c) of forming a hard mask in the thin film region, step (d) of forming silicon films over the silicon layer exposed from the hard mask in the third element region and the fourth element region, and step (e) of forming element isolation insulating films between the silicon films in the third element region and the fourth element region.
US09324732B2 Three-dimensional (3D) non-volatile memory device
A three-dimensional (3D) non-volatile semiconductor memory device including a U-shaped channel structure is disclosed. The 3D non-volatile semiconductor memory device includes a pipe gate, an upper pipe channel disposed in the pipe gate at a first depth, a first lower pipe channel disposed in the pipe gate at a second depth different from the first depth, and neighboring the upper pipe channel in a first direction, and a second lower pipe channel disposed in the pipe gate at the second depth, and neighboring the upper pipe channel in a second direction perpendicular to the first direction, wherein the upper pipe channel and the lower pipe channels have the same length.
US09324729B2 Non-volatile memory device having a multilayer block insulating film to suppress gate leakage current
According to one embodiment, a non-volatile memory device includes electrodes, one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film extends between the conductive layers and the semiconductor layer in the first direction. The second insulating film is provided between each electrode and the conductive layers. The conductive layers become smaller in a thickness as the conductive layers are closer to an end in the first direction or a direction opposite to the first direction. The second insulating film includes a first film contacting the conductive layers, and a second film provided between each electrode and the first film.
US09324723B2 Semiconductor integrated circuit device and a method of manufacturing the same
A semiconductor device including a memory cell featuring a first gate insulating film over a semiconductor substrate, a control gate electrode over the first gate insulating film, a second gate insulating film over the substrate and a side wall of the control gate electrode, a memory gate electrode over the second gate insulating film arranged adjacent with the control gate electrode through the second gate insulating film, first and second semiconductor regions in the substrate positioned on a control gate electrode side and a memory gate side, respectively, the second gate insulating film featuring a first film over the substrate, a charge storage film over the first film and a third film over the second film, the first film having a first portion between the substrate and memory gate electrode and a thickness greater than that of a second portion between the control gate electrode and the memory gate electrode.
US09324722B1 Utilization of block-mask and cut-mask for forming metal routing in an IC device
A method of forming metal routing in an IC device utilizing a cut mask in conjunction with a block mask is disclosed. Embodiments include forming a hard-mask layer on an upper surface of a silicon-oxide layer; forming spaced parallel mandrels on an upper surface of the hard-mask; forming spacers on opposite sides of each mandrel, removing the mandrels, forming alternating mandrel and non-mandrel spaces; forming block-mask portions over the mandrel and non-mandrel spaces; removing exposed sections of the hard-mask exposing sections of the silicon-oxide, removing the block-mask portions; forming a cut-mask with openings shorter than the block-mask portions over the upper surface of the hard-mask where the block-mask portions had been; removing the hard-mask through the cut-mask openings, removing the cut-mask; forming cavities in exposed regions of the silicon-oxide; removing the spacers and any remaining hard-mask; and forming metal lines in the cavities.
US09324721B2 Pitch-halving integrated circuit process
A pitch-halving IC process is described. Parallel base line patterns are formed over a substrate, each being connected with a hammerhead pattern at a first or second side of the base line patterns, wherein the hammerhead patterns are arranged at the first side and the second side alternately, and the hammerhead patterns at the first or second side are arranged in a staggered manner. The above patterns are trimmed. A spacer is formed on the sidewalls of each base line pattern and the corresponding hammerhead pattern, including a pair of derivative line patterns, a loop pattern around the hammerhead pattern, and a turning pattern at the other end of the base line pattern. The base line patterns and the hammerhead patterns are removed. A portion of each loop pattern and at least a portion of each turning pattern are removed to disconnect each pair of derivative line patterns.
US09324717B2 High mobility transistors
An integrated circuit containing an n-channel finFET and a p-channel finFET has a dielectric layer over a silicon substrate. The fins of the finFETs have semiconductor materials with higher mobilities than silicon. A fin of the n-channel finFET is on a first silicon-germanium buffer in a first trench through the dielectric layer on the substrate. A fin of the p-channel finFET is on a second silicon-germanium buffer in a second trench through the dielectric layer on the substrate. The fins extend at least 10 nanometers above the dielectric layer. The fins are formed by epitaxial growth on the silicon-germanium buffers in the trenches in the dielectric layer, followed by CMP planarization down to the dielectric layer. The dielectric layer is recessed to expose the fins. The fins may be formed concurrently or separately.
US09324712B2 Integrated circuit and related manufacturing method
A method for manufacturing an integrated circuit may include the following steps: forming a first transistor, which includes a first active region; forming a second transistor, which includes a second active region; forming a third transistor, which includes a gate electrode that overlaps each of the first active region and the second active region; and providing a predetermined voltage to the gate electrode for turning off the third transistor to isolate the first transistor from the second transistor.
US09324711B2 Semiconductor device and method of manufacturing semiconductor device
A first transistor includes a first impurity layer of a first conduction type formed in a first region of a semiconductor substrate, a first epitaxial semiconductor layer formed above the first impurity layer, a first gate insulating film formed above the first epitaxial semiconductor layer, a first gate electrode formed above the first gate insulating film, and first source/drain regions of a second conduction type formed in the first epitaxial semiconductor layer and in the semiconductor substrate in the first region. A second transistor includes a second impurity layer of the first conduction type formed in a second region of the semiconductor substrate, a second epitaxial semiconductor layer formed above the second impurity layer and being thinner than the first epitaxial semiconductor layer, a second gate insulating film formed above the second epitaxial semiconductor layer, a second gate electrode formed above the second gate insulating film, and second source/drain regions of the second conduction type formed in the second epitaxial semiconductor layer and in the semiconductor substrate in the second region.
US09324706B2 Method of making an integrated switchable capacitive device
A method is provided for forming an integrated circuit chip with a variable capacitor disposed in a metallization. A back end of line metallization is formed over the semiconductor substrate. The variable capacitor is formed within a cavity of the back end of line metallization. The variable capacitor includes a fixed main capacitor electrode disposed in a first metal layer of the back end of line metallization, a second main capacitor electrode electrically connected to a second metal layer of the back end of line metallization and vertically spaced from the fixed main capacitor electrode, and a movable capacitor electrode disposed in the first metal layer adjacent the fixed main capacitor electrode.
US09324704B2 Electronic device, circuit and method for trimming electronic components
A circuit comprises a plurality of electronic components integrated on a substrate, and a trim arrangement arranged to provide trim data to a respective electronic component of the plurality of electronic components. The electronic components are programmable such that the electronic components are enabled to be assigned desired properties. The trim arrangement comprises a first trim data source providing a first trim data set represented by a first number of bits, and at least one second trim data source providing a second trim data set representing an offset from the first trim data set. The second trim data set is represented by a second number of bits. The second number is less than the first number. At least one of the plurality of electronic components is provided with a trim data set formed from the first and second trim data sets such that the at least one of the plurality of electronic components is enabled to adjust its properties based on the trim data set. An electronic device comprising such a circuit and a method of trimming at least two electronic components of a circuit comprising a plurality of electronic components integrated on a substrate and a trim arrangement are also disclosed.
US09324701B2 Diode circuit layout topology with reduced lateral parasitic bipolar action
Diode circuit layout topologies and methods are disclosed that exhibit reduced lateral parasitic bipolar characteristics at lateral parasitic bipolar circuit emitter edges during ESD or other voltage events as compared to conventional circuit layout topologies. The disclosed diode circuit layout topologies may be implemented to recess parasitic emitter ends relative to surrounding well ties, for example, to reduce or substantially eliminate parasitic bipolar action at lateral emitter edges of the circuitry during ESD events so as to provide higher current threshold for device failure, allowing for smaller device area and/or improved ESD robustness for a given circuit device.
US09324700B2 Semiconductor device and method of forming shielding layer over integrated passive device using conductive channels
A semiconductor device is made by providing a substrate, forming a first insulation layer over the substrate, forming a first conductive layer over the first insulation layer, forming a second insulation layer over the first conductive layer, and forming a second conductive layer over the second insulation layer. A portion of the second insulation layer, first conductive layer, and second conductive layer form an integrated passive device (IPD). The IPD can be an inductor, capacitor, or resistor. A plurality of conductive pillars is formed over the second conductive layer. One conductive pillar removes heat from the semiconductor device. A third insulation layer is formed over the IPD and around the plurality of conductive pillars. A shield layer is formed over the IPD, third insulation layer, and conductive pillars. The shield layer is electrically connected to the conductive pillars to shield the IPD from electromagnetic interference.
US09324691B2 Optoelectronic device
An optoelectronic device comprising: a substrate; a plurality of semiconductor units electrically connected with each other and disposed jointly on the substrate, wherein each semiconductor unit comprises a first semiconductor layer, a second semiconductor layer, and an active region interposed between thereof; a plurality of first electrodes disposed on each first semiconductor layer respectively; and a plurality of second electrodes disposed on each second semiconductor layer respectively, wherein at least one of the first electrodes comprises a first extension, and at least one of the second electrodes comprises a second extension, wherein at least one of the first extension and the second extension comprises a curve which is not parallel to the edge of the semiconductor units.
US09324685B2 Semiconductor device and method of manufacturing the same
There is provided a semiconductor device having a converter circuit, a brake circuit and an inverter circuit and manufacturable by a simplified manufacturing process. The semiconductor device has a plurality of die pads, IGBTs, diodes, freewheel diodes, an HVIC and LVICs mounted on the plurality of die pads, a plurality of leads, and an encapsulation resin body that covers these component parts. In a manufacturing process, a single-plate lead frame having the above-described plurality of die pads and leads connected together can be prepared. The semiconductor device may be manufactured by using this single-plate lead frame.
US09324679B2 Two-shaft drive mechanism and die bonder
A two-shaft drive mechanism includes a processing unit, a first linear motor provided with a first movable portion and a first fixed portion, which elevates the processing unit along a first linear guide, and a second linear motor provided with a second movable portion and a second fixed portion, which moves the processing unit in a horizontal direction vertical to the direction for elevating the processing unit, a support body that fixes the first fixed portion, a second linear guide that is provided between the support body and the second fixed portion, and allows the second fixed portion to freely move, and a control unit that controls a position of the first movable portion in the horizontal direction based on an output of the linear sensor that detects a position of the first movable portion in a horizontal direction with respect to the support body.
US09324678B2 Low profile zero/low insertion force package top side flex cable connector architecture
An integrated circuit package is presented. In an embodiment, the integrated circuit package has contact pads formed on the top side of a package substrate, a die electrically attached to the contact pads, and input/output (I/O) pads formed on the top side of the package substrate. The I/O pads are electrically connected to the contact pads. The integrated circuit package also includes a flex cable receptacle electrically connected to the I/O pads on the top side of the package substrate. The flex cable receptacle is non-compressively attachable to a flex cable connector and includes receptacle connection pins electrically connected to the I/O pads.
US09324675B2 Structures for reducing corrosion in wire bonds
A semiconductor structure includes a bond pad and a wire bond coupled to the bond pad. The wire bond includes a bond in contact with the bond pad. The wire bond includes a coating on a surface of the wire bond, and a first exposed portion of the wire bond in a selected location. The wire bond is devoid of the coating over the selected location of the wire bond, and an area of the first exposed portion is at least one square micron.
US09324673B2 Integrated circuit packaging system with wafer level reconfiguration and method of manufacture thereof
A method of manufacture of an integrated circuit packaging system includes: removing a portion of a leadframe to form a partially removed region and an upper portion of a peripheral lead on the leadframe first side; mounting a first integrated circuit over the partially removed region with a first adhesive; forming a first molding layer directly on the first integrated circuit and the peripheral lead; removing a portion of a leadframe second side exposing the first adhesive; mounting a second integrated circuit on the first adhesive of the first integrated circuit; forming a first interconnection layer directly on the first integrated circuit with the first integrated circuit and the peripheral lead electrically connected; and forming a second interconnection layer directly on the second integrated circuit with the second integrated circuit and the peripheral lead electrically connected.
US09324672B2 Semiconductor device and method of forming dual-active sided semiconductor die in fan-out wafer level chip scale package
In a semiconductor device, a plurality of conductive pillars is formed over a temporary carrier. A dual-active sided semiconductor die is mounted over the carrier between the conductive pillars. The semiconductor die has first and second opposing active surfaces with first contact pads on the first active surface and second contact pads on the second active surface. An encapsulant is deposited over the semiconductor die and temporary carrier. A first interconnect structure is formed over a first surface of the encapsulant. The first interconnect structure is electrically connected to the conductive pillars and first contact pads of the dual-active sided semiconductor die. The temporary carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant opposite the first surface of the encapsulant. The second interconnect structure is electrically connected to the conductive pillars and second contact pads of the dual-active sided semiconductor die.
US09324666B2 Electronic device and electronic apparatus
The present invention relates to electronic technology and discloses an electronic device and an electronic apparatus, capable of solving the problem that an electronic device cannot perform a wireless data communication with another electronic device. The electronic device comprises: a first communication chip provided in a first body and operative to transmit/receive a signal directionally; and at least one second communication chip provided in a second body and operative to transmit/receive a signal directionally, the second body being physically connected to the first body in a detachable manner, wherein the first body is capable of performing wireless data communication with the second body by using the first communication chip for transmitting/receiving data to/from the second communication chip.
US09324665B2 Metal fuse by topology
Embodiments of the present disclosure describe techniques and configurations for overcurrent fuses in integrated circuit (IC) devices. In one embodiment, a device layer of a die may include a first line structure with a recessed portion between opposite end portions and two second line structures positioned on opposite sides of the first line structure. An isolation material may be disposed in the gaps between the line structures and in a first recess defined by the recessed portion. The isolation material may have a recessed portion that defines a second recess in the first recess, and a fuse structure may be disposed in the second recess. Other embodiments may be described and/or claimed.
US09324663B2 Semiconductor device including a plurality of magnetic shields
A semiconductor device includes a semiconductor chip having a first main surface, a second main surface opposite to the first main surface, a side surface arranged between the first main surface and the second main surface, and a magnetic storage device, a first magnetic shield overlaying on the first main surface, a second magnetic shield overlaying on the second main surface, and a third magnetic shield overlaying on the side surface. The first and second magnetic shields are mechanically connected via the third magnetic shield.
US09324647B2 Circuit module and method of manufacturing the same
Manufacturing method and circuit module, which comprises an insulator layer and, inside the insulator layer, at least one component, which comprises contact areas, the material of which contains a first metal. On the surface of the insulator layer are conductors, which comprise at least a first layer and a second layer, in such a way that at least the second layer contains a second metal. The circuit module comprises contact elements between the contact areas and the conductors for forming electrical contacts. The contact elements, for their part, comprise, on the surface of the material of the contact area, an intermediate layer, which contains a third metal, in such a way that the first, second, and third metals are different metals and the contact surface area (ACONT 1), between the intermediate layer and the contact area is less that the surface area (APAD) of the contact area.
US09324646B2 Open source power quad flat no-lead (PQFN) package
According to an exemplary implementation, a power quad flat no-lead (PQFN) leadframe includes U-phase, V-phase, and W-phase power switches situated on the PQFN leadframe. A drain of the U-phase power switch is connected to a U-phase output strip of the PQFN leadframe. A source of the U-phase power switch is connected to a U-phase current sense terminal. The U-phase output strip can substantially traverse across the PQFN leadframe. Another U-phase power switch is situated on the PQFN leadframe with a source of the another U-phase power switch connected to the U-phase output strip of the PQFN leadframe. The PQFN leadframe can include a leadframe island within the U-phase output strip. At least one wirebond may be connected to the U-phase output strip.
US09324641B2 Integrated circuit packaging system with external interconnect and method of manufacture thereof
A method of manufacture of an integrated circuit packaging system includes: providing a routable distribution layer on a leadframe; mounting an integrated circuit over the routable distribution layer; encapsulating with an encapsulation over the routable distribution layer; peeling the leadframe away from the routable distribution layer with a bottom distribution side of the routable distribution layer exposed from the encapsulation; and mounting an external interconnect on the routable distribution layer.
US09324640B1 Triple stack semiconductor package
A method for forming a stacked semiconductor package includes providing a bottom leadframe (LF) panel including LFs downset each including at least a plurality of terminals. Low side (LS) transistors are attached to the first die attach area. A first clip panel including first clips downset and interconnected are placed on the bottom LF panel. A dielectric interposer is attached on the first clips over the LS transistors. High side (HS) transistors are attached on the interposers. A second clip panel including a plurality of second clips is mated to interconnect to the HS transistors including mating together the second clip panel, first clip panel and bottom LF panel. The LFs can include a second die attach area, and a controller die attached on the second die attach area, and then pads of the controller die wirebonded to the plurality of terminals.
US09324636B2 Resin-sealed semiconductor device and associated wiring and support structure
A wiring device for a semiconductor device, a composite wiring device for a semiconductor device and a resin-sealed semiconductor device are provided, each of which is capable of mounting thereon a semiconductor chip smaller than conventional chips and being manufactured at lower cost. The wiring device connects an electrode on a semiconductor chip with an external wiring device, and has an insulating layer, a metal substrate and a copper wiring layer. The wiring device has a semiconductor chip support portion provided on the side of the copper wiring layer with respect to the insulating layer. The copper wiring layer includes a first terminal, a second terminal and a wiring portion. The first terminal is connected with the electrode. The second terminal is connected with the external wiring device. The wiring portion connects the first terminal with the second terminal.
US09324633B2 Multi-level package assembly having conductive vias coupled to chip carrier for each level and method for manufacturing the same
A package assembly and a method for manufacturing the same are disclosed. The package assembly includes semiconductor chips, encapsulant layers, and a chip carrier. The plurality of semiconductor chips are stacked in a plurality of levels, including a lowermost level and at least one upper level. The plurality of encapsulant layers cover respective levels of semiconductor chips. The chip carrier is used for mounting lowermost-level semiconductor chips. At least one upper-level semiconductor chips are electrically coupled to the chip carrier by conductive traces. The conductive traces include extension conductors on a surface of a lower-level encapsulant layer and conductive vias which penetrate the lower-level encapsulant layer and are exposed at a bottom surface of the package assembly. The package assembly has improved high-frequency performance while having a small size and supporting multifunctionality.
US09324629B2 Tooling for coupling multiple electronic chips
A method for use with multiple chips, each respectively having a bonding surface including electrical contacts and a surface on a side opposite the bonding surface involves bringing a hardenable material located on a body into contact with the multiple chips, hardening the hardenable material so as to constrain at least a portion of each of the multiple chips, moving the multiple chips from a first location to a second location, applying a force to the body such that the hardened, hardenable material will uniformly transfer a vertical force, applied to the body, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded, at the second location, without causing damage to the individual chips, element, or bonding surface.
US09324628B2 Integrated circuit heat dissipation using nanostructures
An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.
US09324627B2 Electronic assembly for mounting on electronic board
An embodiment of an electronic assembly for mounting on an electronic board includes a plurality of electric contact regions exposed on a mounting surface of the electronic board. The electronic assembly includes a chip of semiconductor material in which at least one electronic component is integrated, at least one support element including a first main surface and a second main surface opposite to the first main surface, the chip being enclosed by the at least one support element, a heat dissipation plate thermally coupled to said chip to dissipate the heat produced by it, exposed on the first main surface of the support element, a plurality of contact elements, each electrically coupled to a respective electric terminal of the electronic component integrated in the chip, exposed on the same first main surface of which is exposed to the dissipation plate. Also included are a plurality of electric connection elements, each adapted to electrically intercouple a respective contact element of the electronic assembly with a corresponding electric contact region of the electronic board, in such a way that the second main surface of the at least one support element faces the mounting surface of the electronic board.
US09324620B2 Metal gate structure and method of making the same
A metal gate structure includes a substrate including a dense region and an iso region. A first metal gate structure is disposed within the dense region, and a second metal gate structure is disposed within the iso region. The first metal gate structure includes a first trench disposed within the dense region, and a first metal layer disposed within the first trench. The second metal gate structure includes a second trench disposed within the iso region, and a second metal layer disposed within the second trench. The height of the second metal layer is greater than the height of the first metal layer.
US09324618B1 Methods of forming replacement fins for a FinFET device
One illustrative method includes, among other things, forming a plurality of trenches in a semiconductor substrate so as to define a substrate fin, forming a layer of insulating material in the trenches, and forming a layer of CTE-matching material above the upper surface of the layer of insulating material, wherein the layer of CTE-matching material has a CTE that is within ±20% of the replacement fin CTE and wherein the layer of CTE-matching material partially defines a replacement fin cavity that exposes an upper portion of the substrate fin. In this example, the method also includes forming the replacement fin on the substrate fin and in the replacement fin cavity, removing the layer of CTE-matching material and forming a gate structure around at least a portion of the replacement fin.
US09324617B1 Methods of forming elastically relaxed SiGe virtual substrates on bulk silicon
One method disclosed herein includes forming a virtual substrate by forming a sacrificial semiconductor material in a trench between a plurality of silicon fin structures formed in a bulk silicon substrate, forming a layer of silicon above the silicon fin structures and the sacrificial semiconductor material, performing at least one etching process to selectively remove the sacrificial semiconductor material relative to the silicon fin structures and the layer of silicon so as to define a cavity, forming a non-sacrificial semiconductor material on the layer of silicon and forming a layer of strained channel semiconductor material above the non-sacrificial semiconductor material positioned above the upper surface of the layer of silicon.
US09324616B2 Method of manufacturing flip-chip type semiconductor device
An object of the present invention is to provide a method of manufacturing a flip-chip type semiconductor device with a simplified process, in which various types of information are supplied in a visually recognizable manner. The present invention relates to a method of manufacturing a flip-chip type semiconductor device comprising: a step A of laminating on a semiconductor wafer a film for the backside of a flip-chip type semiconductor, in which the film is to be formed on the backside of a semiconductor element that is flip-chip connected onto an adherend; a step B of dicing the semiconductor wafer; and a step C of laser marking the film for the backside of a flip-chip type semiconductor, wherein the film for the backside of a flip-chip type semiconductor in the step C is uncured.
US09324613B2 Method for forming through substrate vias with tethers
A method for forming through silicon vias (TSVs) in a silicon substrate is disclosed. The method involves forming a silicon post as an substantially continuous annulus in a first side of a silicon substrate, removing material from an opposite side to the level of the substantially continuous annulus, removing the silicon post and replacing it with a metal material to form a metal via extending through the thickness of the substrate. The substantially continuous annulus may be interrupted by at least one tether which connects the silicon post to the silicon substrate. The tether may be formed of a thing isthmus of silicon, or some suitable insulating material.
US09324610B2 Method for fabricating semiconductor device
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least one metal gate thereon, a source/drain region adjacent to two sides of the at least one metal gate, and an interlayer dielectric (ILD) layer around the at least one metal gate; forming a plurality of contact holes in the ILD layer to expose the source/drain region; forming a first metal layer in the contact holes; performing a first thermal treatment process; and performing a second thermal treatment process.
US09324607B2 GaN power device with solderable back metal
A method for fabricating a vertical gallium nitride (GaN) power device can include providing a GaN substrate with a top surface and a bottom surface, forming a device layer coupled to the top surface of the GaN substrate, and forming a metal contact on a top surface of the vertical GaN power device. The method can further include forming a backside metal by forming an adhesion layer coupled to the bottom surface of the GaN substrate, forming a diffusion barrier coupled to the adhesion layer, and forming a protection layer coupled to the diffusion barrier. The vertical GaN power device can be configured to conduct electricity between the metal contact and the backside metal.
US09324605B2 Method of fabricating a vertically oriented inductor within interconnect structures and capacitor structure thereof
The present disclosure involves a method of fabricating a semiconductor device. The method includes providing a substrate having a horizontal surface. The method includes forming an interconnect structure over the horizontal surface of the substrate. The forming the interconnect structure includes forming an inductor coil that is wound substantially in a vertical plane that is orthogonal to the horizontal surface of the substrate. The forming the interconnect structure includes forming a capacitor disposed proximate to the inductor coil. The capacitor has an anode component and a cathode component. The inductor coil and the capacitor each include a plurality of horizontally extending elongate members.
US09324604B2 Gap-fill methods
Provided are gap-fill methods. The methods comprise: (a) providing a semiconductor substrate having a relief image on a surface of the substrate, the relief image comprising a plurality of gaps to be filled, wherein the gaps have a width of 50 nm or less; (b) applying a gap-fill composition over the relief image, wherein the gap-fill composition comprises a first polymer comprising a crosslinkable group, a second polymer comprising a chromophore, wherein the first polymer and the second polymer are different, a crosslinker, an acid catalyst and a solvent, wherein the gap-fill composition is disposed in the gaps; (c) heating the gap-fill composition at a temperature to cause the first polymer to self-crosslink and/or to crosslink with the second polymer to form a crosslinked polymer; (d) forming a photoresist layer over the substrate comprising the crosslinked polymer-filled gaps; (e) patternwise exposing the photoresist layer to activating radiation; and (f) developing the photoresist layer to form a photoresist pattern. The methods find particular applicability in the manufacture of semiconductor devices for the filling of high aspect ratio gaps with an antireflective coating material.
US09324599B2 Container opening/closing device
The present invention provides a container opening/closing device for opening and closing a lid of a container. The container comprises a container body including an opening and the lid detachably attached to the opening. The device comprises an opening/closing mechanism including a holding portion for holding the lid and a pressing mechanism. The opening/closing mechanism opens and closes the opening by moving the holding portion between a closing position and an open position. The pressing mechanism presses a peripheral edge of the holding portion toward the container body when the opening/closing mechanism moves the lid from the open position to the closing position.
US09324598B2 Substrate processing system and method
A system for processing substrates has a vacuum enclosure and a processing chamber situated to process wafers in a processing zone inside the vacuum enclosure. Two rail assemblies are provided, one on each side of the processing zone. Two chuck arrays ride, each on one of the rail assemblies, such that each is cantilevered on one rail assemblies and support a plurality of chucks. The rail assemblies are coupled to an elevation mechanism that places the rails in upper position for processing and at lower position for returning the chuck assemblies for loading new wafers. A pickup head assembly loads wafers from a conveyor onto the chuck assemblies. The pickup head has plurality of electrostatic chucks that pick up the wafers from the front side of the wafers. Cooling channels in the processing chucks are used to create air cushion to assist in aligning the wafers when delivered by the pickup head.
US09324597B2 Vertical inline CVD system
The present invention generally relates to a vertical CVD system having a processing chamber that is capable of processing multiple substrates. The multiple substrates are disposed on opposite sides of the processing source within the processing chamber, yet the processing environments are not isolated from each other. The processing source is a horizontally centered vertical plasma generator that permits multiple substrates to be processed simultaneously on either side of the plasma generator, yet independent of each other. The system is arranged as a twin system whereby two identical processing lines, each with their own processing chamber, are arranged adjacent to each other. Multiple robots are used to load and unload the substrates from the processing system. Each robot can access both processing lines within the system.
US09324595B2 Load port apparatus and method of detecting object to be processed
To enable appropriate wafer mapping in the case where a wafer is stored at the highest level, which is provided as a reserve, of a pod, a load port apparatus drives a mapping frame that supports a sensor by a first driving unit that drives the mapping frame in a first direction parallel to the direction along which wafers in the pod are arranged in an overlapping manner and a second driving unit that drives the mapping frame in a second direction that crosses the first direction in such a way as to form an acute angle in the side in which the sensor starts the mapping.
US09324593B2 Wafer processing tape
A wafer processing tape includes a release film having a large length; an adhesive layer formed on a first surface of the release film and having a predetermined planar shape; a pressure-sensitive adhesive film having a label portion and a surrounding portion surrounding outside the label portion; and a support member formed on a second surface of the release film opposite to the first surface on which the adhesive layer and the pressure-sensitive adhesive film are formed. The label portion has a predetermined planar shape and covers the adhesive layer so that the label portion contacts with the release film around the adhesive layer. The support member is disposed at both end portions of the release film in a short side direction of the release film. The support member has a coefficient of linear expansion of 300 ppm/° C. or less.
US09324591B2 Heat treatment apparatus and heat treatment method
A heat treatment apparatus including: a processing container for processing wafers held in a boat; heaters for heating the processing container; and a control section for controlling the heaters. Heater temperature sensors are provided between the heaters and the processing container, in-container temperature sensors are provided in the processing container, and movable temperature sensors are provided in the boat. The temperature sensors are connected to a temperature estimation section. The temperature estimation section selects two of the three types of temperature sensors, e.g. the movable temperature sensors and the in-container temperature sensors, and determines the temperature of a wafer according to the following formula: T=T1×(1−α)+T2×α, α>1, where T1 and T2 represent detection temperatures of the selected temperature sensors, and α represents a mixing ratio.
US09324589B2 Multiplexed heater array using AC drive for semiconductor processing
A heating plate for a substrate support assembly in a semiconductor plasma processing apparatus, comprises multiple independently controllable planar heater zones arranged in a scalable multiplexing layout, and electronics to independently control and power the planar heater zones. A substrate support assembly in which the heating plate is incorporated includes an electrostatic clamping electrode and a temperature controlled base plate. Methods for manufacturing the heating plate include bonding together ceramic or polymer sheets having planar heater zones, branch transmission lines, common transmission lines and vias. The heating plate is capable of being driven by AC current or direct current phase alternating power, which has an advantage of minimizing DC magnetic field effects above the substrate support assembly and reduce plasma non-uniformity caused by DC magnetic fields.
US09324584B2 Integrated circuit packaging system with transferable trace lead frame
System and method of manufacturing an integrated circuit packaging system using transferable trace lead frame. A lead frame is provided having lower metal contacts. A masking layer can be formed on an upper surface of the lead frame for protection and shielding purposes. Routing layer and conductive lands may subsequently be formed by shaping the lead frame, along with bottom encapsulation. The masking layer may subsequently be removed for additional processing steps including connecting an integrated circuit die to the upper surface of the lead frame.
US09324581B2 Method for manufacturing semiconductor device
A wafer is mounted to a dicing frame using a holding tape. A plurality of semiconductor devices are provided on a center portion of a major surface of the wafer. A ring-like reinforcing section is provided on a periphery of the major surface. The holding tape is adhered to the major surface The holding tape is heated to at least 0.6 times of melting temperature of the holding tape so as to adhere the holding tape along a step of the ring-like reinforcing section.
US09324580B2 Process for fabricating a circuit substrate
A process for fabricating a circuit substrate is provided. The process includes the following steps. A carrier is provided. A conductive layer and a dielectric layer are placed on the carrier, and the conductive layer is located between the carrier and the dielectric layer. The dielectric layer is patterned to form a patterned-dielectric layer having first openings partially exposing the conductive layer. Arc-shaped grooves are formed on the exposed part of the conductive layer. A first-patterned-photoresist layer having second openings respectively connecting the first openings is formed. Conductive structures are formed, wherein each of the conductive structures is integrally formed and includes a pad part, a connection part, and a protruding part; the second openings, the first openings and the arc-shaped grooves are respectively filled with the pad parts, the connection parts and the protruding parts. The first patterned photoresist layer, the carrier and the conductive layer are removed.
US09324575B2 Plasma etching method and plasma etching apparatus
In a plasma etching method for forming a hole in an etching target film, a process of generating a plasma of a processing gas containing at least CxFy gas and a rare gas having a mass smaller than a mass of Ar gas into the processing chamber in the processing chamber by switching on a high frequency power application unit under a first condition and a process of extinguishing the plasma of the processing gas in the processing chamber by switching off the high frequency power application unit under a second condition are alternately repeated. A negative DC voltage from a DC power supply is applied such that an absolute value of the negative DC voltage of the second condition becomes greater than an absolute value of the negative DC voltage of the first condition.
US09324573B2 Method for manufacturing semiconductor device
One method includes sequentially forming an insulating film and a first material film on a semiconductor substrate, forming on the first material film a mask film having a rectangular first opening, and dry-etching the first material film using the mask film as a mask to form an ellipsoidal second opening having its shorter side aligned in a first direction of the first material film. Forming the mask film includes forming a second material film having a side surface that faces the first direction of the first opening, and a third material film having side surfaces facing a second direction of the first opening, and the thickness of the third material film is greater than the thickness of the second material film.
US09324572B2 Plasma etching method, method for producing semiconductor device, and plasma etching device
Provided is a plasma etching method increasing the selectivity of a silicon nitride film in relation to the silicon oxide film or silicon functioning as a base. In a plasma etching method setting a pressure in a processing container as a predetermined level by exhausting a processing gas while supplying the processing gas into the processing container, generating plasma by supplying external energy to the processing container, and setting a bias applied to a holding stage holding a substrate in the processing container as predetermined value to selectively etch the silicon nitride film with respect to a silicon and/or silicon oxide film, the processing gas includes a plasma excitation gas, a CHxFy gas, and at least one oxidizing gas selected from the group consisting of O2, CO2, CO, and a flow rate of the oxidizing gas with respect to the CHxFy gas is set to be 4/9 or greater.
US09324571B2 Post treatment for dielectric constant reduction with pore generation on low K dielectric films
A method and apparatus for depositing a low K dielectric film with one or more features is disclosed herein. A method of forming a dielectric layer can include positioning a substrate in a processing chamber, delivering a deposition gas to the processing chamber, depositing a dense organosilicon layer using the deposition gas on the surface of the substrate, the dense organosilicon layer comprising a porogenic carbon, transferring a pattern into the dense organosilicon layer, forming a pore-forming plasma from a reactant gas, exposing the dense organosilicon layer to the pore-forming plasma to create a porous organosilicon layer, wherein the pore-forming plasma removes at least a portion of the porogenic carbon and exposing the porous organosilicon layer to a desiccating post treatment.
US09324569B2 Plasma etching method and plasma etching apparatus
A groove shape can be improved. A plasma etching method includes plasma-processing a photoresist film that is formed on a mask film and has a preset pattern; exposing an organic film formed under the mask film by etching the mask film with the pattern of the plasma-processed photoresist film; and etching the organic film by plasma of a mixture gas containing O2 (oxygen), COS (carbonyl sulfate) and Cl2 (chlorine).
US09324560B2 Patterned substrate design for layer growth
A patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers, is provided. The patterned surface can include a set of substantially flat top surfaces and a plurality of openings. Each substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the openings can have a characteristic size between approximately 0.1 micron and five microns. One or more of the substantially flat top surfaces can be patterned based on target radiation.
US09324556B2 Field electron emission film, field electron emission device, light emission device, and method for producing them
A field electron emission film that is capable of being operated with low electric power and enhancing the uniformity in luminance within the light emission surface contains from 60 to 99.9% by mass of tin-doped indium oxide and from 0.1 to 20% by mass of carbon nanotubes. The film has a structure wherein grooves having a width in a range of from 0.1 to 50 mm are formed in a total extension of 2 mm or more per 1 mm2 on a surface of the film, and carbon nanotubes are exposed on a wall surface of the grooves. After forming an ITO film containing carbon nanotubes on a substrate, grooves are formed on a surface of the ITO film, and the end portions of the carbon nanotubes exposed to the wall surface of the grooves are designated as an emitter.
US09324555B2 Amalgam spheres for energy-saving lamps and their production
Energy-saving lamps contain a gas filling of mercury vapor and argon in a gas discharge bulb. Amalgam spheres are used for filling the gas discharge bulb with mercury. A tin amalgam having a high proportion by weight of mercury in the range from 30 to 70% by weight is proposed. Owing to the high mercury content, the amalgam spheres have liquid amalgam phases on the surface. Coating of the spheres with a tin or tin alloy powder converts the liquid amalgam phases on the surface into a solid amalgam having a high tin content. This prevents conglutination of the amalgam spheres during storage and processing.
US09324551B2 Mass spectrometer and method of driving ion guide
A method of operating an electrode changeover switch which switches the connection state of electrodes, the electrode changeover switch is provided in the wiring path between eight electrodes through, arranged rotation-symmetrically about ion optical axis, and voltage generation switch which generates square wave high voltage ±V. When switch is switched as shown in the drawing, two circumferentially adjacent rod electrodes are connected to form one set, a square wave voltage of opposite phase is applied to circumferentially adjacent sets, and an effectively quadrupole electric field is formed. When switch is switched, a square wave voltage of opposite phase is applied to circumferentially adjacent rod electrodes and an octupole electric field is formed. In this way, by switching the switch according to the mass range, etc., it becomes possible to rapidly switch the number of poles of a multipole electric field and to suitably transport ions.
US09324541B1 Certified wafer inspection
A method for certifying an inspection system using a calibrated surface, comprising: acquiring a calibrated list from said calibrated surface, with said calibrated list comprising information about features located on said calibrated surface; inspecting said calibrated surface with said inspection system to generate an estimated list, with said estimated list comprising information about features located on said calibrated surface; generating a matched list by searching for the presence of one or more calibrated features in said estimated list, wherein said calibrated features are listed in said calibrated list; computing an estimated characteristic parameter from said matched list, wherein said estimated characteristic parameter quantifies features in said matched list having a unifying characteristic; and comparing said estimated characteristic parameter with a calibrated characteristic parameter, wherein said calibrated characteristic parameter quantifies features in said calibrated list having said unifying characteristic, whereby the ability of said inspection system to detect features with one or more characteristics is certified. A system and method for imaging a surface to generate an adaptive resolution image, comprising: determining a weakly scattering feature, wherein said weakly scattering feature produces a weak image response to be resolved by said adaptive resolution image; determining a coarse spot size such that said weakly scattering feature is detected in an image captured with said coarse spot size; capturing a coarse image of region with said coarse spot size, wherein said coarse image of region comprises one or more pixels corresponding to a predetermined region of said surface; classifying said coarse image of region into a coarse image of feature and a coarse image of surface, wherein a feature is detected in said coarse image of feature and a feature is not detected in said coarse image of surface; estimating a feature position from said coarse image of feature, wherein said feature position is the location of feature on said surface; capturing a fine image of feature at said feature position, wherein said fine image of feature is captured with a fine spot size having a smaller spot size than said coarse spot size; and combining said fine image of feature and said coarse image of surface to generate said adaptive resolution image, whereby feature regions are captured with finer resolution than featureless surface regions in said adaptive resolution image.
US09324538B2 Coaxial drive apparatus for multidirectional control
A coaxial drive apparatus for multidirectional control, including: a housing; a stage pivotally installed in the housing, with the object laid on the stage; a rotary shaft connected to the stage and rotated to cause the stage to pivot; a rotation transmitting unit transmitting a rotating force of the rotary shaft to the stage; a sliding pipe coaxially fitted over the rotary shaft so as to be moved along a lengthwise direction of the rotary shaft or to be rotated on a central axis of the rotary shaft; a moving unit moving the object laid on the stage in the lengthwise direction of the rotary shaft according to a movement of the sliding pipe, and moving the object in a transverse direction of the rotary shaft according to a rotation of the sliding pipe; and a controller providing a driving force to the rotary shaft and to the sliding pipe.
US09324535B2 Self contained irradiation system using flat panel X-ray sources
The present disclosure describes a self-contained irradiator comprising at least one X-ray source inside a shielded enclosure, the one or more sources each operable to emit X-ray flux across an area substantially equal to the proximate facing surface area of material placed inside the enclosure to be irradiated. The irradiator may have multiple flat panel X-ray sources disposed, designed or operated so as to provide uniform flux to the material being irradiated. The advantages of the irradiator of the present disclosure include compactness, uniform flux doses, simplified thermal management, efficient shielding and safety, the ability to operate at high power levels for sustained periods and high throughput.
US09324532B2 Fuse failure display
Circuitry for fuse failure display for monitoring the trip status of a fuse is disclosed, wherein a light-emitting diode is provided in order to display the trip status of the fuse, which light-emitting diode is arranged in a current path parallel to the fuse. If the fuse is not tripped, the parallel current path has a high resistance in relation to the resistance across the fuse, such that the current across this current path is insufficient for operation of the light-emitting diode. If the fuse is tripped, this parallel current path has a low resistance in relation to the resistance across the fuse, such that the current across this current path is sufficient for operation of the light-emitting diode, wherein a current-limiting device for limiting the current across the light-emitting diode and a voltage-limiting device for limiting the voltage across the tripped fuse are also provided.
US09324524B2 Electromagnetic relay
An electromagnetic relay includes a movable iron core arranged to move up and down within a center hole of an electromagnet unit formed by winding a coil, and a contact switch where an upper end surface of the movable iron core attaches to and detaches from a lower end surface of a fixed iron core arranged in the center hole according to magnetization and demagnetization of the electromagnet unit and a movable contact attaches to and detaches from a fixed contact by a movable shaft which reciprocates along with the movable iron core where the movable iron core includes a sliding portion which always abuts an auxiliary yoke disposed within a yoke, and where a height dimension of the sliding portion is at least equal to or larger than a plate thickness dimension of the yoke.
US09324523B2 Power generation device
A power generation device includes a push button, a slider, a first spring, and a power generation unit. A first spring has a first end engaging the push button, and a second end engaging the slider. The power generation unit includes a first yoke member, a second yoke member, and a coil. The second yoke member includes a first movable member and a second movable member. The first movable member includes a first permanent magnet and is held in the slider. The second movable member includes a second permanent magnet and is held in the slider. The first yoke member is disposed between the first movable member and the second movable member. The coil is disposed to the outer periphery of the first yoke member.
US09324520B2 Vacuum chamber with a one-piece metallic cover for self-centering
The disclosure relates to a vacuum chamber including at least one ceramic isolating cylinder with two face ends. At least one of the two face ends of the ceramic isolating cylinder is closed by a metallic cover including an outer and an inner part. A distal end of the outer part of the metallic cover is thinner relative to the remainder of the outer part of the metallic cover and forms a metallic lid. The metallic lid is connected to at least one of the two face ends of the ceramic isolating cylinder in a vacuum tight manner. The metallic cover can be formed in one piece and fits with the inner part of the metallic cover at an inner girthed area of the ceramic isolating cylinder to realize a self-centering of the metallic lid to at least one of the two face ends of the ceramic isolating cylinder.
US09324519B2 Switching device
A low-voltage switching device including a plurality of arc-extinguishing chambers, wherein each of the arc-extinguishing chambers encloses a contacting unit including a stationary contact and a movable contact and arcs are formed when the movable contact is disconnected to the stationary contact, each of the arc-extinguishing chamber including a plurality of U-shaped arc extinguishing plates arranged for splitting, guiding and cooling the arc formed between the contacts and sidewalls provided with guiding means for guiding the arms of the arc extinguishing plates. The guiding means includes a plurality of supporting plates and the supporting plates are arranged protruding towards interior of the arc-extinguishing chamber for receiving the arms of the arc-extinguishing plates and for providing electrical isolation between arms of two adjacent arc extinguishing plates.
US09324516B2 Click module and operation switch
A click module which gives a feeling of click when an operation knob which is tiltably and pivotally supported on a casing of an operation switch is tiltably operated has a click face on which a crest portion or a valley portion is formed, a click element which slides on the click face, and a resilient member which biases the click element to a click face side. The click module is detachably mounted on the casing. The click element and the click face slide relative to each other in an interlocking manner with a tilting operation of the operation knob.
US09324515B2 Touchsurface assembly utilizing magnetically enabled hinge
Methods and apparatus for a touchsurface assembly such as a key assembly are described. The touchsurface assembly includes a base, a keycap and a magnet physically coupled to the base near to the keycap. A keycap coupler has a first portion magnetically attracted to the magnet and a second portion cantilevered from the magnet to support the keycap in an unpressed position. When a press force applied to the keycap overcomes a magnetic force pulling the keycap coupler toward the magnet, the keycap coupler pivots away from the magnet to allow the keycap to move toward a pressed position.
US09324505B2 Compounds for electrochemical and/or optoelectronic devices having peri-fused ring system
The invention relates to substituted ullazine and analogs of ullazine as sensitizers for dye-sensitized solar cells (DSSCs) and other photoelectrochemical and/or optoelectronic devices. The sensitizers may comprise donor substituents and/or acceptor substituents, besides an anchoring group suitable for attaching the sensitizer on a semiconductor surface. DSSCs based on this type of sensitizers exhibit high power conversion efficiencies.
US09324503B2 Solid electrolytic capacitor
A capacitor for use in relatively high voltage environments is provided. The solid electrolyte is formed from a plurality of pre-polymerized particles in the form of a dispersion. In addition, the anode is formed such that it contains at least one longitudinally extending channel is recessed therein. The channel may have a relatively high aspect ratio (length divided by width), such as about 2 or more, in some embodiments about 5 or more, in some embodiments from about 10 to about 200, in some embodiments from about 15 to about 150, in some embodiments from about 20 to about 100, and in some embodiments, from about 30 to about 60.
US09324502B2 Lithium ion capacitor
Provided is a lithium ion capacitor that can maintain a high capacity retention rate and suppress an increase in internal resistance even after high-load charging-discharging is repeated many times and that has long service life because the occurrence of a short circuit due to precipitation of lithium on the negative electrode is prevented.The lithium ion capacitor comprises a positive electrode, a negative electrode, and an electrolyte solution, the negative electrode including a current collector and electrode layers that contain a negative electrode active material and are formed on front and back surfaces of the current collector, wherein, in the negative electrode, ratios of deviations of respective thicknesses of the electrode layers formed on the front and back surfaces of the current collector from an average of the thicknesses of the electrode layers to the average is −10 to 10%.
US09324501B2 Hard start kit for multiple replacement applications
A hard start capacitor replacement unit has a plurality of capacitors in a container sized to fit in existing hard start capacitor space. The capacitors are 4 metallized film capacitors wound in a single cylindrical capacitive element. The container has a common terminal and capacitors value terminals for the plurality of capacitors, which may be connected singly or in combination to provide a selected capacitance. An electronic or other relay connects the selected capacitance in parallel with a motor run capacitor. The hard start capacitor replacement unit is thereby adapted to replace a wide variety of hard start capacitors.
US09324497B2 Dielectric thin film, dielectric thin film element and thin film capacitor
A thin film capacitor includes a substrate and a dielectric thin film element formed on the substrate. The substrate can include an Si plate, an SiO2 film on the Si plate, and a Ti film formed on the SiO2 film. The dielectric thin film element includes a lower electrode, a dielectric thin film on the lower electrode, and an upper electrode formed on the dielectric thin film. The dielectric thin film is a thin film formed of a nanosheet, and a void portion of the dielectric thin film is filled with a p-type conductive organic polymer. Ti0.87O2, Ca2Nb3O10 or the like, is used as a dielectric material to form a major component of the nanosheet. As the p-type conductive organic polymer, polypyrrole, polyaniline, polyethylene dioxythiophene or the like, is suitable.
US09324495B2 Planar inductors with closed magnetic loops
A planar closed-magnetic-loop inductor and a method of fabricating the inductor are described. The inductor includes a first material comprising a cross-sectional shape including at least four segments, at least one of the at least four segments including a first edge and a second edge on opposite sides of an axial line through the at least one of the at least four segments. The first edge and the second edge are not parallel.
US09324492B2 Magnetic device
A magnetic device is provided. The magnetic device includes a bobbin including a hollow portion extending in a longitudinal direction, coils wound around the outside of the bobbin, a core coupled to the bobbin outside the bobbin. The bobbin includes a first winding portion around which the coil is wound, a second winding portion which is disposed at one side of the first winding portion in the longitudinal direction, and around which the coil is wound, a tolerance relief part disposed between the first and second winding portions, coupling parts symmetrically disposed to each other on the outsides of the first and second winding portions, respectively. The tolerance relief part is elastically deformable in the longitudinal direction.
US09324487B1 Damper for magnetic coupler
This disclosure is directed at least partly to reducing an acceleration of a magnet when a magnet is moved toward an attracting object. An apparatus may include a dampening mechanism to dissipate kinetic energy of the magnet as it traverses within a housing from a first position to a second position. The housing may be at least partially coupled to another surface as a result of a magnetic attraction when the magnet is located in the second position. The dampening mechanism may include use of a fluid and/or gas that is displaced by the magnet to slow acceleration of the magnet as the magnet traverses between the first position and the second position. In some embodiments, the dampening mechanism may be implemented using threads that cause rotation of the magnet or by rollers that slow acceleration of the magnet.
US09324486B2 Partial insulation superconducting magnet
The present invention is a superconducting partial insulation magnet and a method for providing the same. The magnet includes a coil with a non-insulated superconducting wire winding wound around a bobbin. The coil has a first wire layer, a second wire layer substantially surrounding the first layer, and a first layer of insulating material disposed between the first wire layer and the second wire layer. Each wire layer comprises a plurality of turns, and the first layer of insulating material substantially insulates the second wire layer from the first wire layer.
US09324485B2 Material for anisotropic magnet and method of manufacturing the same
A material for anisotropic magnet, comprising, (1) a Pr-T-B—Ga-based composition containing Pr: 12.5 to 15.0 atomic percent, B: 4.5 to 6.5 atomic percent, Ga: 0.1 to 0.7 atomic percent, and the balance of T and inevitable impurities, wherein T is Fe or obtained by substituting Co for a portion of the Fe; and having, (2) a degree of magnetic alignment of 0.92 or more, wherein the degree of magnetic alignment is defined by remanence (Br)/saturation magnetization (Js); and (3) a crystal grain diameter of 1 μm or less.
US09324484B2 Nanoferrite flakes
A ferrite layer having a columnar structure is formed, and ferrite flakes are separated from the ferrite layer. The ferrite flakes include a metal oxide having a spinel cubic crystal structure with a stoichiometry represented by AB2O4, where A and B represent different lattice sites occupied by cationic species, and O represents oxygen in its own sublattice.
US09324483B2 Chip thermistor and method of manufacturing same
A chip thermistor 1 has a thermistor portion 7 comprised of a ceramic material containing respective metal oxides of Mn, Ni, and Co as major ingredients; a pair of composite portions 9, 9 comprised of a composite material of Ag—Pd, and respective metal oxides of Mn, Ni, and Co and arranged on both sides of the thermistor portion 7 so as to sandwich in the thermistor portion 7 between the composite portions 9, 9; and external electrodes 5, 5 connected to the pair of composite portions 9, 9, respectively. In this manner, the pair of composite portions 9, 9 are used as bulk electrodes and, for this reason, the resistance of the chip thermistor 1 can be adjusted mainly with consideration to the resistance in the thermistor portion 7, without need for much consideration to the distance between the external electrodes 5, 5 and other factors.
US09324478B2 High-speed data cable with shield connection
A high speed cable with terminating assemblies at the respective ends of the cable includes a ground wire, one or more signal wires, and a conductive layer enclosing the ground wire and the signal wires. The ground wire as well as the signal wires and the conductive layer extend into the terminating assemblies, in each of which corresponding inductive elements are coupled between the conductive layer and the ground wire. In each terminating assembly, the ground wire is shunted to the conductive layer by inductive elements, thus providing added low frequency connectivity in the cable, while at the same time blocking high frequency noise energy that may be present in the ground wire and preventing it from being coupled into, and transmitted through, the conductive layer.
US09324472B2 Metal and metallized fiber hybrid wire
Conductive metal and metallized fiber hybrid wires are disclosed, wherein such wires have a central member and a peripheral member and comprise at least one conductive metallized fiber. The peripheral member comprises (i) at least one conductive metal filament; and (ii) optionally, at least one conductive metallized fiber. The central member comprises (i) at least one non-metallized fiber; (ii) at least one conductive metallized fiber; (iii) at least one conductive metal filament; or (iv) combinations thereof.
US09324470B2 Disordered metal hydride alloys for use in a rechargeable battery
A structurally and compositionally disordered electrochemically active alloy material is provided with excellent capacity and cycle life, as well as superior high-rate dischargeability. The alloy employs a disordered A2B4+x(AB5) structure, wherein x is a number between 1 and 4. This crystal structure combined with a tailored amount of electrochemically active AB5 secondary phase material produces superior electrochemical properties.
US09324465B2 Methods and apparatuses for operating nuclear reactors and for determining power levels in the nuclear reactors
An apparatus may include two or more electrical conductors, one or more signal devices, and an analyzer. The one or more signal devices may be adapted to apply one or more signals to the two or more electrical conductors and receive one or more signals from the two or more electrical conductors. The analyzer may be adapted to determine power level in the nuclear reactor using at least one of the applied signals and at least one of the received signals. A method of determining power level in a nuclear reactor may include: measuring impedance values of two or more electrical conductors disposed in the nuclear reactor and using the measured impedance values to determine the power level. A method of operating a nuclear reactor may include: measuring the impedance values and using the measured impedance values to determine parameters of the nuclear reactor.
US09324461B2 Fuel channel annulus spacer
An annulus spacer for a fuel channel assembly of a nuclear reactor. The fuel channel assembly includes a calandria tube and a pressure tube positioned at least partially within the calandria tube. The annulus spacer includes a garter spring configured to surround a portion of the pressure tube to maintain a gap between the calandria tube and the pressure tube. The garter spring includes a first end and a second end. The annulus spacer also includes a connector coupled to the first end and the second end of the garter spring. The connector allows movement of the annulus spacer when the pressure tube moves relative to the calandria tube during thermal cycles of the fuel channel assembly. The annulus spacer further includes a girdle wire positioned substantially within the garter spring and configured to form a loop around the pressure tube.
US09324454B2 Data pattern generation for I/O testing of multilevel interfaces
One feature is a method of reading data from a plurality of pattern registers, generating a first output at a mapping register from the read data, generating a second output, different from the first output, at the mapping register from the read data, and generating a multi-level signal using the first and second outputs. In one embodiment, generating the first output is done by adding a first plurality of bits to a second plurality of bits, and generating the second output is done by adding the first plurality of bits to an inverse of the second plurality of bits.
US09324451B2 All voltage, temperature and process monitor circuit for memories
A device for monitoring process variations across memory bitcells includes a bitcell inverter that provides an output voltage to be used for identifying skewed corners of the memory bitcells. A first comparator compares the output voltage with a first reference voltage, and a second comparator compares the output voltage with a second reference voltage. The first and the second comparators generate a corner code based on comparison results.
US09324449B2 Driver circuit, signal processing unit having the driver circuit, method for manufacturing the signal processing unit, and display device
Disclosed is a driver circuit including a latch circuit, a shift register circuit, and a switching circuit, where the latch circuit is provided over the shift register circuit and the switching circuit. The shift register circuit and the switching circuit may have a silicon-based semiconductor, while the latch circuit may have an oxide semiconductor. The latch circuit includes a first transistor and a second transistor connected in series. The latch circuit may further include a first capacitor and a second capacitor which are electrically connected to the first transistor and the second transistor. A display device using the driver circuit as well as a method for preparing the driver circuit is also disclosed.
US09324448B2 Fuse element programming circuit and method
In one embodiment, a programming circuit is configured to form a programming current for a silicide fuse element by using a non-silicide programming element.
US09324444B2 Data storage device
A data storage device includes a nonvolatile memory device; and a controller electrically coupled with the nonvolatile memory device, and configured to control an operation of the nonvolatile memory device, wherein the controller is configured to change a frequency of an internal clock and a level of an internal voltage, according to whether data is being transmitted through a channel.
US09324443B2 Compensating for off-current in a memory
A memory cell is accessed by determining an off-current of a set of memory cells, accessing a memory cell of the set of memory cells during an access period, and compensating for the off-current of the set of memory cells.
US09324439B1 Weak erase after programming to improve data retention in charge-trapping memory
Techniques are provided to improve long term data retention in a charge-trapping memory device. In addition to a primary charge-trapping layer in which most charges are stored, the memory device may include a tunneling layer comprising an engineered tunneling barrier such as oxide-nitride-oxide. The nitride in the tunneling layer may also store some charges after programming. After the programming, a data retention operation is performed which de-traps some electrons from the tunneling layer, in addition to injecting holes into the tunneling layer which form neutral electron-hole dipoles in place of electrons. These mechanisms tend to lower threshold voltage. Additionally, the data retention operation redistributes the electrons and the holes inside the charge-trapping layer, resulting in an increase in threshold voltage which roughly cancels out the decrease when the data retention operation is optimized.
US09324436B2 Method and apparatus for controlling operation of flash memory
A method and apparatus for controlling the operation of flash memory are provided. The apparatus for controlling the operation of flash memory includes a control unit and a voltage adjustment unit. The control unit outputs a control signal adapted to change one or more of the program, erase and read voltage conditions for the flash memory to the voltage adjustment unit in response to the input of a PUF mode selection signal. The voltage adjustment unit changes the one or more of the program, erase and read voltage conditions for the flash memory in response to the input of the control signal.
US09324435B2 Data transmitting method, memory control circuit unit and memory storage apparatus
A data transmitting method for a memory storage apparatus is provided. The method includes: initially setting a first threshold and a first accumulated value; and updating the first threshold by using the first threshold plus the first accumulated value at intervals of a first predetermined time. The method also includes when a detected temperature of the memory storage apparatus is greater than or equal to a temperature threshold, determining whether a size of received writing data is greater than or equal to the first threshold; and if no, writing the writing data into a rewritable non-volatile memory module and then updating the first threshold by using the first threshold minus the size of the writing data; and if yes, not writing the writing data into the rewritable non-volatile memory module. Accordingly, the method can effectively prevent overheat of system during operations of the memory storage apparatus.
US09324431B1 Floating gate memory device with interpoly charge trapping structure
A nonvolatile memory cell has a semiconductor substrate, a multilayer stack including a charge trapping layer over a floating gate, a top conductive layer, and circuitry controlling program and erase operations on the nonvolatile memory cell. The program and erase operations change a first charge density on the floating gate by a larger magnitude than a second charge density on the charge trapping dielectric layer.
US09324429B2 Semiconductor storage device
A semiconductor storage device 1 includes: an input controller (3); and a content-addressable memory block (2) connected to the input controller (3). Each word circuit (4) of the content-addressable memory block (2) includes: a k-bit 1st-stage sub word (4a) connected to search line 1 (SL1) of the input controller (3); and an (n-k)-bit 2nd-stage sub word (4b) connected to search line 2 (SL2) of the input controller (3). The k-bit 1st-stage sub word (4a) and the (n-k)-bit 2nd-stage sub word (4b) are separated by a segmentation circuit (5). When the 1st-stage sub word outputs a match signal, the match result is stored in the segmentation circuit (5), and a plurality of local match circuits within the 2nd-stage sub word (4b) are operated.
US09324428B1 Memory device and operation method thereof
An operation method for a memory device is disclosed. An operation state of the memory device is determined. If to be operated in a first operation state, the memory device is applied by a reset pulse. If to be operated in a second operation state, the memory device is applied by the reset pulse and at least a first incremental pulse set verification current, and an allowable maximum current of the first incremental pulse set verification current is lower than a melt current. If to be operated in a third operation state, the memory device is applied by the reset pulse and at least a first identical pulse set verification current, and an allowable maximum current of the first identical pulse set verification current is lower than the melt current. If to be operated in a fourth operation state, the memory device is applied by a set pulse.
US09324427B2 Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device includes: a cell array including MATs (unit cell arrays) arranged in matrix, each of the MATs having memory cells, each of the memory cells having a variable resistive element of which resistance is nonvolatilely stored as data; and write/erase circuits connected to the MATs and operative to execute data write or erase to the memory cells inside the MATs in accordance with input data. A part of the write/erase circuits writes data to memory cells inside a corresponding MAT while another part of the write/erase circuits erases data from memory cells inside a corresponding MAT at the same time.
US09324425B2 Memory device, method of controlling memory device, and memory system
A memory device according to an embodiment comprises a data processing circuit that includes: a data write pre-processing circuit that processes input data to generate first intermediate data; a data write processing circuit that sequentially sets a voltage difference between a selected row line and a selected global bit line based on the first intermediate data; a data read processing circuit that detects a current flowing in the selected global bit line or a voltage of the selected global bit line and sequentially generates second intermediate data from a result of that detection; and a data read post-processing circuit that processes the second intermediate data to generate output data, the data write pre-processing circuit and the data read post-processing circuit having a correcting function that corrects a difference that may occur between the input data and the output data.
US09324418B2 Nonvolatile memory and method for improved programming with reduced verify
A group of memory cells of a nonvolatile memory is programmed in parallel in a programming pass with a minimum of verify steps from an erased state to respective target states by a staircase waveform. The memory states are demarcated by a set of increasing demarcation threshold values (V1, . . . , VN). Initially in the programming pass, the memory cells are verified relative to a test reference threshold value. This test reference threshold has a value offset past a designate demarcation threshold value Vi among the set by a predetermined margin. The overshoot of each memory cell when programmed past Vi, to be more or less than the margin can be determined. Accordingly, memory cells found to have an overshoot more than the margin are counteracted by having their programming rate slowed down in a subsequent portion of the programming pass so as to maintain a tighter threshold distribution.
US09324416B2 Pseudo dual port memory with dual latch flip-flop
A memory and a method for operating the memory provided. In one aspect, the memory may be a PDP memory. The memory includes a control circuit configured to generate a first clock and a second clock in response an edge of a clock for an access cycle. A first input circuit is configured to receive an input for a first memory access based on the first clock. The first input circuit includes a latch. The second input circuit configured to receive an input for a second memory access based on the second clock. The second input circuit includes a flip-flop.
US09324415B2 Clamping circuit for multiple-port memory cell
A circuit includes a memory cell, a first data line, a second data line, and a clamping unit. The memory cell includes a data node, a first pass gate, and a second pass gate. The first pass gate is between the first data line and the data node. The second pass gate is between the second data line and the data node. The clamping unit is electrically coupled to the first data line and configured to pull a voltage level of the first data line toward a clamped voltage level when the clamping unit is enabled, and to function as an open circuit to the first data line when the clamping unit is disabled. The clamping unit is disabled when a first control signal indicates that a voltage level of the second data line is pulled toward a reference voltage level.
US09324406B2 Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a memory cell and a control circuit. The memory cell is such that a ferroelectric film is provided as a gate dielectric film. When data is stored in the memory cell, the control circuit applies a first voltage to the gate dielectric film and thereafter applies a second voltage, whose amplitude is smaller than that of the first voltage and whose polarity is opposite to that of the first voltage.
US09324402B2 High density low power GSHE-STT MRAM
Systems and methods are directed to a memory element comprising a hybrid giant spin Hall effect (GSHE)-spin transfer torque (STT) magnetoresistive random access memory (MRAM) element, which includes a GSHE strip formed between a first terminal (A) and a second terminal (B), and a magnetic tunnel junction (MTJ), with a free layer of the MTJ interfacing the GSHE strip, and a fixed layer of the MTJ coupled to a third terminal (C). The orientation of the easy axis of the free layer is perpendicular to the magnetization created by electrons traversing the GSHE strip between the first terminal and the second terminal, such that the free layer of the MTJ is configured to switch based on a first charge current injected from/to the first terminal to/from the second terminal and a second charge current injected/extracted through the third terminal into/out of the MTJ via the third terminal (C).
US09324400B2 Semiconductor memory device and semiconductor memory system
A semiconductor memory device includes a unit memory bank having a plurality of memory cell mats, which shares a local data line, and divided by a row address; and at least one dummy cell mat disposed between the plurality of memory cell mat.
US09324398B2 Apparatuses and methods for targeted refreshing of memory
Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory.
US09324397B1 Common die for supporting different external memory types with minimal packaging complexity
A configurable die including a logic element configured to communicate a control and address (CA) signal and a data (DQ) signal, and a first generic physical interface (PHY) and a second generic PHY in communication with the logic element, wherein each of the first generic PHY and the second generic PHY is configurable as a CA PHY and as a DQ PHY, and wherein the logic element is configurable to communicate the CA signal and the DQ signal to different ones of the first and second generic PHYs.
US09324396B2 Semiconductor apparatus and operating method thereof
A sense amplifier control circuit of a semiconductor apparatus includes a driving unit configured to apply a first voltage to a sense amplifier in response to a first driving signal. The driving unit may also be configured to apply a second voltage to the sense amplifier in response to a second driving signal. In addition, the driving unit may also be configured to apply a third voltage to the sense amplifier in response to a third driving signal. A switching unit may be configured to electrically couple a first node to a second node in response to a control signal. The first driving signal is output to the first node, and the second driving signal is output to the second node.
US09324395B2 Data sensing circuit of semiconductor apparatus
A data sensing circuit of a semiconductor apparatus includes a sensing unit configured to drive a pair of output lines based on a voltage level difference between a pair of input/output lines in response to a pair of enable signals, a timing control unit configured to perform an equalizing operation between the pair of output lines while the pair of enable signals are in a deactivated state in response to a control signal, and to interrupt the equalizing operation between the pair of output lines when a predetermined period of time has passed following the activation of the pair of enable signals, and a control signal generation unit configured to generate the control signal in response to the enable signal.
US09324391B2 Dual event command
A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.
US09324389B2 High performance system topology for NAND memory systems
A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes. The modes include a pass-through mode, where the main portions of the memory circuit are inactive and commands and data are passed through to other devices in the tree structure, and an active mode, where the main portions of the memory circuit are active and can receive and supply data. Reverse active and reverse pass-through modes, where data flows in the other direction, can also be used. The pads of the memory chip can be configurable to swap input and output pads to more efficiently form the memory chips into a package.
US09324386B2 Wide common mode range sense amplifier
A device for comparing voltage levels of a pair of input signals is presented. The device may include a pre-amp circuit and a differential amplifier. The pre-amp circuit may be configured to receive a first input signal and a second input signal, adjust a voltage level of each of the pair of input signals, and assert a control signal after a pre-determined period of time from the assertion of an enable signal. The differential amplifier may be configured to amplify a voltage difference between the first input signal and the second input signal dependent upon the adjusted voltage level of the pair of input signals in response to the assertion of the control signal.
US09324385B2 Semiconductor device for generating initialization of information in response to a first clock and outputting the initialization information in response to a second clock
A semiconductor device includes an initialization information generation unit configured to operate in response to a first clock and generate first initialization information having a value that is adjusted according to a value of an address signal that corresponds to output data, a domain crossing unit configured to receive the first initialization information in response to the first clock and output the first initialization information as second initialization information by outputting the second initialization information in response to a second clock, and a pulse generation unit configured to operate in response to the second clock and adjust a toggling point in time of a control pulse in response to the second initialization information.
US09324384B2 Sense amplifiers and memory devices having the same
In a sense amplifier, a switching transistor is configured to apply a ground voltage to a ground node in response to a sense enable signal. A first detection circuit is configured to output a first detection signal to the first detection node based on a mode signal and a voltage of a bit-line. A second detection circuit is configured to output a second detection signal to the second detection node based on a voltage of a complementary bit-line. A latch circuit is connected to a supply voltage, the first detection node and the second detection node, and configured to output a first amplified signal and a second amplified signal through a latch node and a complementary latch node, respectively, based on the first detection signal and the second detection signal.
US09324382B2 Resistive memory device capable of improving sensing margin of data
A resistive memory device includes a cell block having a plurality of unit memory cells in which a resistive element and a cell select element are connected to each other in series, the cell block operating in response to a word line, a bit line, and a source line, and a dummy line, when different interconnection layers form the source line and the bit line, respectively, connected to one of the interconnection layers which is formed at a lower side the remaining interconnection layer between the interconnection layers for the source line and the bit line, wherein the dummy line has a resistance lower than a resistance of the lower interconnection layer.
US09324377B2 Systems and methods for facilitating rendering visualizations related to audio data
Systems and methods for facilitating rendering a visualization related to audio data are described. One of the methods includes accessing an audio file that is stored within a server computing system. The audio file includes the audio data. The method further includes extracting acoustic profile data from audio data. The extraction of the acoustic profile data is performed within the server computing system. The method also includes associating the acoustic profile data with the audio file and sending the acoustic profile data to a client device for displaying at the client device during playback of the audio file the visualization that is based on the acoustic profile data.
US09324372B2 Systems and methods for local iteration randomization in a data decoder
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for local iteration randomization in a data decoder circuit.
US09324370B2 Identifying a defect in a data-storage medium
An embodiment of a data-read path includes a defect detector and a data-recovery circuit. The defect detector is operable to identify a defective region of a data-storage medium, and the data-recovery circuit is operable to recover data from the data-storage medium in response to the defect detector. For example, such an embodiment may allow identifying a defective region of a data-storage disk caused, e.g., by a scratch or contamination, and may allow recovering data that was written to the defective region.
US09324362B1 Post-write scan operations for interlaced magnetic recording
A storage device includes a data degradation management module that tracks a risk of data degradation by incrementing a track write counter of a first data track responsive to each data write command to a second data track, such as a data track directly adjacent to the first data track. If a count of the track write counter exceeds a count threshold, one or more post-write scan operations are performed to assess and/or repair data degradation of the first data track.
US09324361B2 Protecting stored data from traffic analysis
A method including: reading a portion of stored data from a storage medium, decrypting the portion of stored data, then if changes are requested, making the changes to the portion of stored data to produce changed data, encrypting the changed data, and writing the encrypted changed data to the storage medium. An apparatus that performs the method is also included.
US09324356B2 Optical data storage medium and use of such medium
A multi-stack optical data storage medium (30) for recording and reading using a focused radiation beam (40) entering through an entrance face (41) of the medium (30) is described. It has a first substrate (31a) with present on a side thereof a first recording stack (33) named L0, comprising a recordable type L0 recording layer (35), formed in a first L0 guide groove (38a, 38b). A first reflective layer (39) is present between the first L0 recording layer (35) and the first substrate (31a). A second substrate (31b) with present on a side thereof a second recording stack (32) named L1 is present at a position closer to the entrance face (41) than the L0 recording stack (33) and formed in a second L1 guide groove (37). A transparent spacer layer (36) is sandwiched between the recording stacks (32, 33). The first L0 guide groove (38a, 38b) has a depth GL0<100 nm. In this way a relatively high reflection value of the L0 stack is achieved at a radiation beam wavelength of approximately 655 nm.
US09324352B1 Location association identification between wireless communication devices
Embodiments disclosed herein provide systems and methods for identifying similarly located wireless devices. In a particular embodiment, a method provides processing location information that indicates past locations of the wireless communication devices to generate location profiles for the wireless communication devices. The method further provides processing groups of the location profiles to determine location-similarity metrics among the location profiles within the groups and determining if any of the location-similarity metrics for any of the groups satisfies a similarity criteria indicating similarly located devices. If one of the location-similarity metrics for one of the groups satisfies the similarity criteria, then the method provides generating device information indicating a location-association among the wireless communication devices that correspond to the location profiles in that one group.
US09324349B2 Magnetic data storage apparatus for use with linear recording media having a reduced servo band width
In one embodiment, a magnetic data storage apparatus includes a magnetic head having at least one group of N servo readers, a drive mechanism for passing a linear magnetic recording medium over the head, and a controller electrically coupled to the head. The controller is configured to position a first servo reader of the at least one group of N servo readers in a first lateral medium region of the recording medium with a servo band having a width b that is less than or equal to about 1.2 B/N, where N is an integer greater than or equal to 2, and B corresponds to a distance between data read/write transducers of the magnetic head, and position the magnetic head in a second lateral region of width b with a second servo reader of the at least one group of N servo readers for reading the servo band.
US09324343B2 Systems and methods for protecting a sensitive device from corrosion
A magnetic storage system according to one embodiment includes a magnetic head having a removable organic coating thereon in an amount sufficient for reducing exposure of the head to oxidation promoting materials. A kit according to one embodiment includes a drive having a magnetic head, and a tape having an applicator portion for applying an organic coating to the magnetic head for reducing exposure of the head to oxidation promoting materials.
US09324341B2 Magnetic head for perpendicular magnetic recording including a heater
A magnetic head includes a main pole, an expansion member, and a heater. The main pole has an end face located in a medium facing surface. The expansion member is located farther from the medium facing surface than is the main pole and adjacent to the main pole in a direction perpendicular to the medium facing surface. The heater heats the expansion member. The expansion member has a linear expansion coefficient higher than that of the main pole.
US09324339B2 Methods and systems for enhancing pitch associated with an audio signal presented to a cochlear implant patient
An exemplary method of enhancing pitch of an audio signal presented to a cochlear implant patient includes 1) determining a frequency spectrum of an audio signal presented to a cochlear implant patient, the frequency spectrum comprising a plurality of frequency bins that each contain spectral energy, 2) generating a modified spectral envelope of the frequency spectrum of the audio signal, 3) identifying each frequency bin included in the plurality of frequency bins that contains spectral energy above the modified spectral envelope and each frequency bin included in the plurality of frequency bins that contains spectral energy below the modified spectral envelope, 4) enhancing the spectral energy contained in each frequency bin identified as containing spectral energy above the modified spectral envelope, and 5) compressing the spectral energy contained in each frequency bin identified as containing spectral energy below the modified spectral envelope. Corresponding methods and systems are also disclosed.
US09324336B2 Method of managing a jitter buffer, and jitter buffer using same
The present invention relates to a method of managing a jitter buffer and a jitter buffer using same. The method of managing a jitter buffer includes the steps of: receiving audio information frames; and adjusting a jitter buffer on the basis of the received audio information frames, wherein the adjusting step of the jitter buffer includes compensation of an audio signal, and the compensation of the audio signal can be performed for each sub frame of the audio information frames.
US09324332B2 Method and encoder and decoder for sample-accurate representation of an audio signal
A method for providing information on the validity of encoded audio data is disclosed, the encoded audio data being a series of coded audio data units. Each coded audio data unit can include information on the valid audio data. The method includes: providing either information on a coded audio data level which describes the amount of data at the beginning of an audio data unit being invalid, or providing information on a coded audio data level which describes the amount of data at the end of an audio data unit being invalid, or providing information on a coded audio data level which describes both the amount of data at the beginning and the end of an audio data unit being invalid. A method for receiving encoded data including information on the validity of data and providing decoded output data is also disclosed. Furthermore, a corresponding encoder and a corresponding decoder are disclosed.
US09324330B2 Automatic conversion of speech into song, rap or other audible expression having target meter or rhythm
Captured vocals may be automatically transformed using advanced digital signal processing techniques that provide captivating applications, and even purpose-built devices, in which mere novice user-musicians may generate, audibly render and share musical performances. In some cases, the automated transformations allow spoken vocals to be segmented, arranged, temporally aligned with a target rhythm, meter or accompanying backing tracks and pitch corrected in accord with a score or note sequence. Speech-to-song music applications are one such example. In some cases, spoken vocals may be transformed in accord with musical genres such as rap using automated segmentation and temporal alignment techniques, often without pitch correction. Such applications, which may employ different signal processing and different automated transformations, may nonetheless be understood as speech-to-rap variations on the theme.
US09324329B2 Method for parametric spatial audio coding and decoding, parametric spatial audio coder and parametric spatial audio decoder
A method for parametric spatial audio coding of a multi-channel audio signal comprising a plurality of audio channel signals is provided, the method comprising: calculating at least two different spatial coding parameters for an audio channel signal of the plurality of audio channel signals, selecting at least one spatial coding parameter of the at least two different spatial coding parameters associated with the audio channel signal on the basis of the values of the calculated spatial coding parameters; including a quantized representation of the selected spatial coding parameter into a parameter section of an audio bitstream; and setting a parameter type flag in the parameter section of the audio bitstream indicating the type of the selected spatial coding parameter being included into the audio bitstream.
US09324326B2 Voice agent device and method for controlling the same
A voice agent device includes: a position detection unit which detects a position of a person in a conversation space to which the voice agent device is capable of providing information; a voice volume detection unit which detects a voice volume of the person from a sound signal in the conversation space obtained by a sound acquisition unit; a conversation area determination unit which determines a conversation area as a first area including the position when the voice volume has a first voice volume value and determines the conversation area as a second area including the position and being smaller than the first area when the voice volume has a second voice volume value smaller than the first voice volume value, the conversation area being a spatial range where an utterance of the person can be heard; and an information provision unit which provides provision information to the conversation area.
US09324325B2 Converting data between users during a data exchange session
A method and system for converting voice data to text data between users is provided. The method includes receiving voice data from at least one user and determining phoneme data items corresponding to the voice data. Conversion candidate string representations of the phoneme data items are identified by referencing a conversion dictionary defining the conversion candidate string representations for each phoneme data item. The plurality of conversion candidate string representations are scored and a specified conversion candidate string representation is selected as text data based on the scores. The text data is transmitted to a terminal device accessed by the at least one user.
US09324322B1 Automatic volume attenuation for speech enabled devices
A speech recognition system that also automatically recognizes and acts in response to significant audio interruptions. Received audio is compared with stored acoustic signatures of noises which may trigger a change in device operation, such as pausing, loudening or attenuating of content playback after hearing a certain audio interruption, such as a doorbell, etc. If the received audio matches a stored acoustic model, the system alters an operational state of one or more devices, which may or may not include itself.
US09324320B1 Neural network-based speech processing
Pairs of feature vectors are obtained that represent speech. Some pairs represent two samples of speech from the same speakers, and other pairs represent two samples of speech from different speakers. A neural network feeds each feature vector in a sample pair into a separate bottleneck layer, with a weight matrix on the input of both vectors tied to one another. The neural network is trained using the feature vectors and an objective function that induces the network to classify whether the speech samples come from the same speaker. The weights from the tied weight matrix are extracted for use in generating derived features for a speech processing system that can benefit from features that are thus transformed to better reflect speaker identity.
US09324313B1 Methods and systems for implementing bone conduction-based noise cancellation for air-conducted sound
A wearable computing device can receive, via at least one input transducer, a first audio signal associated with ambient sound from an environment of the device. The device can then process the first audio signal so as to determine a second audio signal that is out of phase with the first audio signal and effective to substantially cancel at least a portion of the first audio signal. The device may then generate a noise-cancelling audio signal based on the second audio signal, based on a third audio signal, and based on one or more wearer-specific parameters, where the third audio signal is representative of a sound to be provided by the device. The device may then cause a bone conduction transducer (BCT) to vibrate so as to provide to an ear a noise-cancelling sound effective to substantially cancel at least a portion of the ambient sound.
US09324306B2 Keyboard device and keyboard instrument
A keyboard device including a plurality of transmission members which are provided corresponding to a plurality of keys arranged in parallel and each of which makes a rotating motion in response to a depression operation on a corresponding key, a plurality of hammer members which are provided corresponding to the plurality of keys and each of which makes a rotating motion in response to the rotating motion of the transmission member and thereby provides an action load to the key, and a plurality of interlock control sections each of which controls the rotating motion of the hammer member made in response to the rotating motion of the transmission member by a relative motion of an interlock projecting section of the transmission member with respect to a guide hole provided in the hammer member.
US09324304B2 Information display apparatus, method thereof and program thereof
An information display apparatus creates determination image which indicates the fact that a reference object in a plurality of objects arranged in a row satisfies a predetermined rule or that the reference object does not satisfy the rule, creates an image to be displayed by superimposing the determination image on the acquired image, and displays the image to be displayed.
US09324298B2 Image processing system, image processing apparatus, storage medium having stored therein image processing program, and image processing method
A marker image that, if included in a captured image captured by an image capturing apparatus, performs image processing on the captured image and is thereby allowed to cause a predetermined virtual object to appear is placed in a virtual space. Then, a viewpoint for displaying a part of the virtual space on a display apparatus is changed in accordance with a user input, and the virtual space viewed from the viewpoint is displayed on the display apparatus.
US09324291B2 LCD device control system and LCD device
A liquid crystal display (LCD) device control system or an LCD device includes a control circuit board includes a sequence control circuit, a panel includes a source drive circuit, and a scalar circuit board includes a first voltage reduction module. The sequence control circuit is configured with a main power end and an auxiliary power end. The main power end of the sequence control circuit and the source drive circuit are coupled to the first voltage reduction module to supply power.
US09324290B2 Liquid crystal display (LCD) and method of driving the same
A liquid crystal display (LCD) and method of driving the same are disclosed. In one aspect, the LCD includes a display panel that includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels each electrically connected to a corresponding gate line and a corresponding data line. The LCD also includes a timing controller that receives present frame data, stores previous frame data, and outputs first line data of the previous frame data and a data driver that converts the first line data to a first previous line data voltage and applies the first previous line data voltage to the data lines during a portion of a vertical blank period between a present frame and a previous frame.
US09324287B2 Liquid crystal display device
A pixel electrode is formed on a TFT substrate, and a gate insulating film is formed thereon. On the gate insulating film, formed is an inorganic passivation film, on which a common electrode having slits is formed. Through-holes are formed in the gate insulating film at areas where the pixel electrode faces the common electrode, and the pixel electrode is not connected to a source electrode in the through-hole. The through-holes are filled with the inorganic passivation film, and the common electrode is formed on the inorganic passivation film at a position corresponding to each through-hole. The pixel electrode faces the common electrode at the position through not the gate insulating film but only the inorganic passivation film, and thus the pixel capacity can be increased. Accordingly, it is possible to prevent changes in the electric potential of the pixel electrode caused by ON/OFF operations.
US09324282B2 Liquid crystal pixel circuit and driving method thereof
A liquid crystal pixel circuit and a driving method thereof are provided. The liquid crystal pixel circuit has a main pixel, a sub pixel and a charge sharing switch. The charge sharing switch is electrically coupled between the main pixel and the sub pixel. The main pixel, the sub pixel and the charge sharing switch are controlled by the same gate line. The provided driving method is used for driving the liquid-crystal pixel circuit mentioned above.
US09324281B2 Display device and driving method thereof
A display device includes a first gate driver that applies a gate-on voltage to gate lines of a first gate line group in each period of n first scan periods for a first frame, n being a natural number. A second gate driver applies a gate-on voltage to gate lines of a second gate line group in each period of n second scan periods for a first frame. A data driver applies a data voltage to a plurality of data lines. A signal controller transmits a control signal to the first and second gate drivers and the data driver, wherein an interval between start points of the n first scan periods is gradually decreased according to time, and an interval between start points of the n second scan periods is gradually increased according to time.
US09324279B2 Illumination device, display device, data generation method, non-transitory computer readable recording medium including data generation program for generating light amount adjustment data based on temperature
A micon unit (11) performs, along at least one direction within the plane of planar light, brightness correction processing for adjusting brightness distribution of the planar light on light source color video signals (RSd, Gsd and BSd) so as to change them into light source color video signals (RSd′, GSd′ and BSd′), and the micon unit (11) further calculates the total light emission power of all LEDs (52) based on the light source color video signals (RSd′, GSd′ and BSd′), and performs, when the total light emission power exceeds an allowable light emission power, light emission power correction processing on the light source color video signals (RSd′, GSd′ and BSd′).
US09324278B2 Ambient black level
Techniques for operating a display system in a wide range of ambient light conditions are provided. An intensity of ambient light on a display panel may be detected. The display panel may be illuminated by light sources in addition to the ambient light. An individual light source may be individually settable to an individual light output level. If it is determined that the luminance level of the ambient light is above a minimum ambient luminance threshold, an ambient black level may be calculated using the intensity of ambient light. Light output levels of one or more of the light sources may be elevated to first light output levels. Here, the one or more light sources may be designated to illuminate one or more dark portions of an image. The first light output levels may create a new black level equaling the determined ambient black level.
US09324270B2 Emission driving unit for adjusting emission signal, emission driver having the same, and organic light emitting display device having the emission driver
In one aspect, an emission driving unit and an organic light emitting diode (OLED) display having the same are disclosed. The emission driving unit includes an input signal generating circuit that receives a FLM signal according to a first clock signal, receives a second clock signal according to the FLM signal, and outputs a sequential input signal. The emission driving unit also includes an inverter circuit that receives the FLM signal according to the first clock signal, and that inverts the FLM signal to generate an inverter output signal. The emission driving unit also includes an output switching circuit that outputs a first voltage having a logic high level or a second voltage having a logic low level as an emission signal in response to the inverter output signal. The input signal generating circuit, the inverter circuit, and the output switching circuit are implemented by transistors of the same kind.
US09324265B2 Pixel, display device including the same, and driving method thereof
A plurality of pixels each including a first capacitor coupled between a data line and a first node, a switching transistor for electrically connecting the first node and a second node, a second capacitor coupled between the second node and a third node, an initialization transistor for transmitting a first power source voltage to the second node, and a driving transistor including a gate electrode coupled to the third node to control a driving current to an organic light emitting diode, in which light emission of the organic light emitting diode by the driving current is concurrently performed in the plurality of pixels according to data signals transmitted during a previous frame.
US09324264B2 Pixel and organic light emitting diode display having a bypass transistor for passing a portion of a driving current
A pixel and an organic light emitting diode (OLED) display using the pixel are disclosed. The pixel includes a driving transistor for transmitting a driving current, an organic light emitting diode (OLED) receiving a first portion of the driving current, and a bypass transistor receiving a second portion of the driving current.
US09324253B2 Modular electronic displays
Modular displays are made up of arrays of modules that include light sources and light modulators. The modules may include control circuits that perform some image processing functions. The modules may illuminate a screen directly or may include optical systems that project light onto a screen.
US09324247B2 Interactive education system for teaching patient care
An eye assembly for use in a patient simulator is provided. The eye assembly includes an iris diaphragm having a moveable inner portion defining an opening. The inner portion of the iris diaphragm is movable radially from a first position wherein the opening has a first diameter and a second position wherein the opening has a second diameter greater than the first diameter. The iris diaphragm is configured for use in a simulated eye. The eye assembly also includes a dilation actuator in communication with the inner portion of the iris diaphragm for selectively moving the inner portion between the first and second positions to simulate dilation of an eye.
US09324230B2 System and method for configuring a wireless control system of a vehicle using induction field communication
A system for mounting in a vehicle and for providing a control signal to a remote device based on information stored in a portable electronic device includes a radio frequency transmitter for transmitting a control signal to the remote device. The system also includes a first circuit configured to receive first information from the portable electronic device via inductive-coupling between the portable electronic device and the first circuit when the portable electronic device is brought within the induction field of the first circuit. The system also includes a second circuit configured to use the first information received from the portable electronic device and to at least one of format the control signal in accordance with the first information and to cause the radio frequency transmitter to format the control signal in accordance with the first information.
US09324228B2 Pipe system, and pipe flow monitoring and alerting systems and methods
A pipe system includes a pipe for containing a pipe flow therethrough having a first flow rate, a sampling tube coupled in fluid communication to the pipe for receiving and containing a portion of the pipe flow therethrough, for interacting with the portion of the pipe flow therethrough so as to form a second flow rate of the portion of the pipe flow being an amplification of the first flow rate, and for returning the portion of the pipe flow to the pipe, and a sensor for sensing the second flow rate and for transmitting a signal being a function of the second flow rate.
US09324223B2 Electronic monitoring home unit and installation methods
A new and improved electronic monitoring home units and associated installation methods. The present disclosure provides for an electronic monitoring home unit capable of automated confirmation of location and method of automated confirmation of location when a home unit has been installed. The present disclosure provides for a home unit capable of intelligent inclusion zone setting for a home unit and a method of such inclusion zone setting. The present disclosure also provides for a streamlined installation method with automated communication between a home unit and central monitoring system.
US09324221B2 Anti-fraud tag
A highly visible single use tag prevents the fraudulent return of garments. Two members are connected by a hinge. The hinge allows the members to move from an open configuration to a closed configuration where the members form and enclose a space. Complementary latch elements on the members engage and hold the members in the closed configuration. At least one of the members has a tack extending inwardly into the space enclosed by the members. This tack pierces a garment intended to be protected by the tag and maintains the tag on the garment. At least one of the members has at least one perforated line across the width of the member. This perforated line allows that member to be pulled apart and the tag removed without the need of any tool to do so.
US09324220B2 Theft detection device and method for controlling same
A theft detection device, configured to be coupled to a product, includes a light sensor, a motion sensor, an emitter configured to emit a signal, and a controller coupled to the light sensor, the motion sensor, and the emitter. The controller is configured to determine a light level sensed by the light sensor. The controller is also configured to determine, via the motion sensor, whether the theft detection device is in motion. Further, the controller is configured to operate the emitter based on the sensed motion of the theft detection device and the light level sensed by the light sensor. The controller is further configured to deactivate the theft protection device when the light sensor detects a coded light sequence.
US09324217B2 System for transmitting an alert
An alert beacon carried directly by a human being is equipped with a transmit circuit able to produce an alert signal transmitted on the same channel as that used by a walkie-talkie. The transmit circuit has a memory containing, for each symbol of the coordinates of the current position of the alert beacon, an audio transcription of the symbol, and a microcontroller able to introduce, into the alert signal produced, the audio transcriptions recorded in the memory corresponding to each symbol of the coordinates in such a way that the coordinates can be played back in the form of a voice message comprehensible to a user of any walkie-talkie that has received this message on a channel that is being listened to.
US09324216B2 Pattern matching slot mechanic
A pattern matching mechanic for touch screen slot machines. A pattern consisting of a sequence of randomly selected cells in a displayed symbol matrix is generated and momentarily displayed to a player as their spin is ending. The sequence can be displayed whether the spin is lost or won. A player sequence is received and compared to the pattern. A reward is provided to the player if the player sequence matches the pattern sequence. The pattern sequence can be generated with a cadence that must be matched by the player sequence. The pattern can be generated at different levels, and the reward based on the level of the pattern generated. The level can be increased when a number of consecutive patterns are matched, and decreased when a number of consecutive patterns are not matched.
US09324215B2 Game machine, method of controlling computer, and storage medium
A game machine uses a lottery region having cell columns and symbol columns for providing a game opportunity, causes a special symbol column to appear in it, determines by lottery symbols of the special symbol column, causes the special symbol column containing the symbols obtained by a lottery result to appear and moves and stops the special symbol column so that the symbols of the special symbol column are arranged on the cells to be changed, and determines whether the symbols arranged in a cell group of a determination target form a prize winning pattern based on the symbols arranged by the special symbol column. Further, the game machine moves the special symbol column along each cell so that at least a direction crossing a movement direction of each symbol column is included as a movement direction of the special symbol column.
US09324212B2 Gaming machine, and control method of same
A gaming machine 1: variably displays a plurality of symbols on a lower image display panel 141 in response to an external input; randomly determining symbols 501 to be rearranged on the lower image display panel 141; determining one of game results based on the symbols 501 randomly determined; execute a common indication effect common to all the game results; and after common indication effect is executed, executes an individual indication effect according to the game result determined while the symbols are variably displayed.
US09324211B2 Multiple-game gaming machine
A gaming machine includes a gaming console. A display is mounted in the gaming console for displaying a wagering game and its result. A controller controls operation of the game, the controller displaying the result of a first game on the display, making payment of a prize if the first game has a prize winning result and, thereafter, irrespective of the result of the first game, varying a result displayed on the display without requiring any additional wager by a player whether before or after completion of the first game.
US09324206B2 Managing information relating to secure module applications
An apparatus capable of hosting a secure module, which secure module comprises at least one secure module application. The apparatus is configured to provide connectivity to the secure module. A processing module is configured to obtain from the secure module information concerning the at least one secure module application. The processing module is, based on the obtained information, configured to check whether a compatible counterpart application is present in the apparatus. A communication module is configured to obtain the compatible counterpart application from an outside source in case no compatible counterpart application is present in the apparatus.
US09324202B2 Method and system for providing location-based services
A method and system for providing location-based services are proposed, wherein the objective is the determination of the authorization of a person to use location-based services using non-contact detection and the evaluation of media information from a customer medium, whereby the location of the customer medium is carried out based on the detection of the medium and where the media information of the customer medium is recorded based on an automatically implementable non-contact interaction between at least one reading device assigned one location and connected to computer and the customer medium, if the customer medium is within the range least one reading device, where the customer medium comprises an RF transceiver and communicates with the computer via at least one reading device in a predetermined frequency range, where location-based services are provided cases of a valid authorization, the provision of which depends on the detection of the customer medium via at least one reading device assigned to the location, and where the customer medium is controlled by a computer via least one reading device in such a manner that the energy consumption of the customer medium is minimized.
US09324199B2 Method and system for controlling an engine cooling system
Methods and systems are provided for expediting engine system heating by stagnating coolant in one of a plurality of loops in an engine cooling system. Degradation of the various valves and thermostats of the cooling system can be diagnosed by adjusting the valve and monitoring changes in one or more of coolant temperature, transmission temperature and cabin temperature. Based on engine operating conditions, the various valves may be adjusted to vary coolant temperature in different regions of the cooling system, thereby providing fuel economy benefits.
US09324197B2 Method and system for managing the hand-off between control terminals
A vehicle control and gateway module comprising an electronic control module controlling one or more vehicle systems, a vehicle communications bus, a wireless communications module, an electronic gateway module acting as a translator of information between the vehicle communications bus and the wireless communications module, and a software program, whereby an operator using a remote mobile device can send and receive wireless commands to and from the vehicle with the electronic gateway module translating messages from one data protocol to the other as required.
US09324195B2 Recreational vehicle interactive, telemetry, mapping, and trip planning system
An interactive system for use in connection with recreational vehicle usage includes a server system, including an off-road trail database containing trail data, trail condition information, and points-of-interest information, as well as a trip mapping system accessible by any of a plurality of riders, allowing a rider to create a route based on the data in the off-road trip database. The server system further includes a trail maintenance interface accessible by users affiliated with an authorized group to edit the trail data, trail condition information, and points-of-interest information associated with the authorized group. The server system includes a location data management system configured to receive location data, allowing a rider to publish location information to one or more other riders, and a user feedback interface configured to receive trip data from riders for publication, including information describing an actual route and user data associated with that route.
US09324194B2 Method and system for database compilation on a remote electronic device
A system and method of customizing a data retrieval and storage device for communication with a specific vehicle after the device is initially connected to the vehicle. The system includes a master database having communication information arranged by vehicle specific information, and an automotive scan tool having an incomplete set of preloaded communication information stored thereon. The automotive scan tool is configured to retrieve an electronic VIN from the vehicle and upload the electronic VIN to the master database. After receiving the electronic VIN, the master database identifies the specific communication information associated with the vehicle and communicates such information to the automotive scan tool to compliment the preloaded communication information.
US09324192B2 Real-time monitoring of vehicle
A monitoring unit for vehicle monitoring comprising a receiving module configured to receive data from an OBD, wherein the data is associated with a plurality of jerks detected by a 3-axis accelerometer. The monitoring unit comprises an analytics module configured to compare an intensity of each jerk of the plurality of jerks to a predefined jerk threshold and capture high intensity jerks from the plurality of jerks. The high intensity jerks have intensity equal to or more than the predefined jerk threshold. The method further comprises determining an elapsed time for each of the high intensity jerks. The elapsed time for each of the high intensity jerks is compared to a predefined time threshold. Further it is determined whether an analysis on the high intensity jerks is to be performed at the vehicle or at a server located remotely.
US09324190B2 Capturing and aligning three-dimensional scenes
Systems and methods for building a three-dimensional composite scene are disclosed. Certain embodiments of the systems and methods may include the use of a three-dimensional capture device that captures a plurality of three-dimensional images of an environment. Some embodiments may further include elements concerning aligning and/or mapping the captured images. Various embodiments may further include elements concerning reconstructing the environment from which the images were captured. The methods disclosed herein may be performed by a program embodied on a non-transitory computer-readable storage medium when executed the program is executed a processor.
US09324188B1 Manipulation of 3D medical objects
Easy-to-learn, efficient, and/or unambiguous methods for controlling rotation and/or other manipulation of multi-dimensional (for example, 2D and/or 3D) images and/or objects are disclosed. The systems and methods may be used for any type of image display/manipulation on a wide variety of computer systems and coupled displays including personal computers with monitors, phones, tablets, and televisions. In general, a user may select a particular rotation plane (for example, rotation only in x axis) by placement of a cursor, or touch of a finger, over a certain portion of the image such that subsequent movements of the mouse result in only rotations in the particular plane, and unwanted rotations and/or other manipulations in other planes do not occur. In this way, the user can more precisely control rotations of the 3D image and/or object.
US09324182B2 Single pass radiosity from depth peels
Techniques for single pass radiosity from depth peels are described. In one or more embodiments, radiosity for frames of a graphics presentation is computed using depth peel techniques. This may occur by rendering geometry for a frame and then computing two depth peels per frame based on the geometry, which can be used to determine occlusion of secondary bounce lights as well as color and intensity of third bounce lights for radiosity. The two depth peels may be generated in a single rendering pass by reusing rejected geometry of a front depth peel as geometry for a back depth peel. The use of depth peels in this manner enables accelerated radiosity computations for photorealistic illumination of three dimensional graphics that may be performed dynamically at frame rates typical for real-time game play and other graphics presentations.
US09324180B2 Culling using masked depths
A simple technique for zmax-culling on a per-tile basis conservatively estimates the maximum depth of the samples in a tile using a layer of masks and a number of zmax-values. No feedback loop is needed from the depth unit, in some embodiments. In addition, the occlusion test may be masked.
US09324172B2 Method of overlap-dependent image stitching for images captured using a capsule camera
A method of processing images captured by an in vivo capsule camera is disclosed. The images having large overlap exceeding a threshold are stitched into larger images. If the current image and none of its neighboring images has large overlap, the current image is designated as a non-stitched image. Any image, that exists between two images stitched and is not included in the stitched image, is also designated as a non-stitched image. The large-overlap stitching can be performed on the images iteratively by treating the stitched images and non-stitched image as to be processed images in the next round. A second stage stitching can be applied to stitch small-overlap images. The small-overlap image stitching can also be applied iteratively. A third stage stitching can be further applied to stitch the output images from the second stage processing.
US09324171B2 Image overlaying and comparison for inventory display auditing
Example methods disclosed herein include overlaying a semi-transparent version of a reference image over a sequence of captured images as respective ones of the captured images are displayed on a display of a portable device. Such disclosed example methods also include determining a directional difference between a first one of the captured images and the reference image. Such disclosed example methods further include presenting a directional prompt to indicate a direction to move the portable device to cause a subsequent second one of the captured images to coincide with the reference image.
US09324167B2 Apparatus and method for generating an attenuation correction map
The invention relates to an apparatus for generating an attenuation correction map. An image providing unit (5, 6) provides an image of an object comprising different element classes and a segmentation unit (11) applies a segmentation to the image for generating a segmented image comprising image regions corresponding to the element classes. The segmentation is based on at least one of a watershed segmentation and a body contour segmentation based on a contiguous skin and fat layers in the image. A feature determination unit (12) determines features of at least one of a) the image regions and b) boundaries between the image regions depending on image values of the image and an assigning unit (13) assigns attenuation values to the image regions based on the determined features for generating the attenuation correction map. The performed image processing steps can allow for producing a high quality attenuation correction map, even if the initial image does not comprise image values related to the attenuation of radiation like a CT image.
US09324165B2 Method and device for generating a predicted value of an image using interpolation and motion vectors
A method and device for generating a predicted value of image that are mostly used to generate a predicted value of a current block during image encoding or decoding. The method includes: determining a searching scope, wherein multiple motion vectors are included in the searching scope; performing up-sampling interpolations on first reference blocks, corresponding to the motion vector in the searching scope, in a reference image of the current block by using a first filter to obtain up-sampled first reference blocks; by using the up-sampled first reference blocks, obtaining at least one candidate motion vector corresponding to the current block; performing up-sampling interpolations on second reference blocks, corresponding to the at least one candidate motion vector, in the reference image of the current block by using a second filter to obtain up-sampled second reference blocks; combining the up-sampled second reference blocks to obtain a predicted value of the current block.
US09324157B2 Medical image data processing apparatus and method
An image data processing apparatus comprising a image data processing unit for obtaining segmented image data segmented using a segmentation process and including a representation of a vessel, wherein a region of the vessel is missing from the representation, a boundary identification unit for identifying at least one point at or near a boundary of the missing region, wherein the image data processing unit is configured to perform a further segmentation process to identify the missing region of the vessel, using the location of the at least one identified point at or near the boundary of the missing region, and the image data processing unit is further configured to generate a revised representation of the vessel including the missing region of the vessel.
US09324153B2 Depth measurement apparatus, image pickup apparatus, depth measurement method, and depth measurement program
Provided is a depth measurement apparatus that measures depth information on a subject by using a plurality of images taken under different imaging parameters and having different blurs, the depth measurement apparatus including a spatial frequency determination unit that determines a spatial frequency band from a spatial frequency present in at least one of the plurality of images, an image comparison unit that compares the plurality of images by using the component of the spatial frequency band of the plurality of images and outputs a depth dependence value dependent on the depth of the subject, and a depth calculation unit that calculates the depth from the depth dependence value and the spatial frequency band.
US09324151B2 System and methods for world-scale camera pose estimation
System and methods for determining where a digital photograph was taken by estimating the camera pose with respect to a global scale three-dimensional database. Accurate location and orientation of the digital photograph is established through feature correspondence and geometry estimated from photograph collections.
US09324147B2 Method and apparatus for computing a parallax
A method and an apparatus for computing a parallax are provided. The method includes: obtaining a plurality of views of a pixel point; computing gradients in a plurality of directions of the pixel point in the plurality of view; computing a matching error corresponding to a parallax of the pixel point according to the gradients; and computing the parallax of the current pixel point according to the matching error. Through the method and the apparatus for computing a parallax, the accuracy of parallax estimation is increased.
US09324146B2 Photometric and radiometric calibration using optical feedback
Certain examples provide photometric or radiometric calibration using optical feedback. A disclosed example includes dithering between a first display pixel value and a second display pixel value to create a light source from a display. The disclosed example includes capturing the light source using a camera via a plurality of photographs taken by the camera. Each photograph includes a plurality of camera pixels. The disclosed example includes determining a camera response by measuring plurality of camera quantization levels associated with the plurality of camera pixels based on the first display pixel value and the second display pixel value. The disclosed example also includes determining a display response based on the plurality of camera quantization levels. The display response includes a plurality of luminance output values of the display.
US09324143B2 Systems and methods for diagnosing strokes
The invention relates to systems and methods for diagnosing strokes. In particular, systems and methods for acquiring timely patient status information are described that enable a physician to make diagnostic and treatment decisions relating to ischemic and hemorrhagic strokes. The systems and methods enable the efficient and quantitative assessment of arterial collaterals within the brain for aiding these decisions in the case of ischemic strokes. In the case of hemorrhagic strokes, the systems and methods are effective in determining if there is a leak and what is the rate of leaking.
US09324136B2 Method, electronic apparatus, and computer readable medium for processing reflection in image
A method, an electronic apparatus, and a computer readable medium for processing reflection in an image are proposed. In the method, a first image and a second image are obtained. A plurality of objects in the first image and the second image are recognized and a plurality of lighting regions having a brightness higher than a first threshold in the first image and the second image are detected. Then, a plurality of displacements between corresponding objects and corresponding lighting regions in the first image and the second image are calculated. It is determined whether a ratio of the displacement of the object nearby one of the lighting regions to the displacement of the lighting region is over a second threshold. Finally, the lighting region is determined as a reflection if the ratio is over the second threshold.
US09324132B2 Image signal processing device, image processing system having the same, and image signal processing method using the image signal processing device
An image signal processing device is disclosed, including a sensitivity improvement unit, a Bayer RGB conversion unit, and a color correction unit. The sensitivity improvement unit interpolates input white, red, green, and blue (WRGB) data, mixes a luminance signal of first color space data for the interpolated WRGB data with a first type pixel signal of the interpolated WRGB data to convert the first color space data into second color space data, and converts the second color space data into converted RGB data. The Bayer RGB conversion unit converts color spaces of a second type pixel signal, a third type pixel signal, and a fourth type pixel signal of the interpolated WRGB data to generate the first color space data, and separates the luminance signal and color difference signals from the first color space data. The color correction unit corrects the converted RGB data into output RGB data.
US09324127B2 Techniques for conservative rasterization
This disclosure describes a method for performing conservative rasterization in a processor comprising determining vertices of a primitive, defining edges of the primitive by determining a set of edge equations based on the determined vertices, wherein the edge equations are based on an edge shifting parameter plus an offset, determining pixels that touch the edges of the primitive using the determined edge equations, and rasterizing the primitive using the determined pixels.
US09324125B2 Methods and apparatuses for rendering CT image data
The present disclosure provides a method for rendering of CT image data. The method includes acquiring 2D image data of a background and 2D image data of a target; rendering the 2D image data of the target into a 3D image of the target to obtain a first hit position of a ray; rendering the 2D image data of the background into a 3D image of the background; adjusting the 3D image of the background based on the first hit position; and synthetically rendering the 3D image of the background and the 3D image of the target. The present disclosure also provides apparatus for implementing the method.
US09324121B2 Systems and methods for warning a vehicle occupant of probable unsafe texting
A system and method are described to track and warn a person suspected of texting while driving a moving vehicle. The position and speed of a user's cell phone are compared with those of other cell phone users in the vicinity. If the position and speed of a phone track that of one or more neighboring phones, it is assumed that a user may under certain conditions be texting while driving. For circumstances where persons suspected to be in the same vehicle utilize different service providers, parameters such as for instance cell phone position, velocity, and direction of travel are time stamped and then compared. Cell phone users who are determined likely to be texting while driving based on the disclosed methods may be warned without disabling their texting capability.
US09324119B2 Identity and asset risk score intelligence and threat mitigation
Techniques are provided that produce a risk profile consisting of a risk score and trends of risk scores across entities such as user identities and other objects. For example, an identity is assigned a risk score which is based on baseline factors such as HR attributes, such as training and screening status; access to and conflicts across physical, logical, and operational systems; historical and current usage of these systems, as well as anomalies from normal behavior patterns. Techniques herein encompass the management of a risk profile (“behavior profile”) for each entity, e.g. identity, and maintains a risk score that is correlated with behavior, e.g. an individual's behavior, to track anomalies or irregularities in every day routines of the entity, e.g. individual.
US09324118B2 Infant formula tracking system and method
There is described herein a system and method for tracking an infant formula product. Coded data representative of a unique identity of the formula product is attached thereto and read to allow inventory control and track the allocation of the infant formula product to a user. For instance, safety mechanisms can be put into place to ensure the authenticity of the formula product and that the user is fed the product in accordance with a prescribed composition.
US09324116B2 Energy services interface
An energy services bridge interposed between one or more energy service providers and an energy distribution network operator manages a plurality of diversified energy consumer service plans so as to be compliant with the physical and technical constraints of the transmission/distribution gird. The energy services bridge further conveys real-time information regarding the state of the transmission/distribution grid to the plurality of energy service providers enabling active management of the service plans and correspondingly active management of the transmission/distribution grid.
US09324115B2 Activity review for a financial and social management system
Embodiments of the invention comprise systems, computer program products, and methods for a financial and social management system that provides improved tracking and management related to how, where, when, and with whom a user enters into activities. The financial and social management system captures activity information and images from various sources of information, including but not limited to social networking accounts, e-receipts, location determination devices, and the like, and associates the activity information and images with the activities. The financial and social management system aggregates the activity information for a number of activities based on the location, user, entity, category, cost, time period, or the like and displays the aggregated activity information in an activity review interface. The financial and social management system may supplement the aggregated activity information with educational data.
US09324110B2 System and method for purchasing a prepaid bebit account
Disclosed herein are systems, methods, and non-transitory computer-readable storage media for auctioning gift cards on the secondary market. The system can receive a prepaid debit account for resale from an owner and determine a face value for the prepaid debit account. The system can establish a floor price and offer the prepaid debit account for sale via an auction, starting at an initial price above the floor price and up to and including the face value, and can decrement the sale price at regular time intervals. The system can end the auction when a purchaser purchases the prepaid debit account at the decremented price. However, if no purchaser purchases the prepaid debit account before the decremented price is below the floor price, the system can purchase the prepaid debit account from the owner for the floor price. The system can store the prepaid debit account in an inventory for resale.
US09324105B2 Method and apparatus to buy and sell items via a local area network
A wireless device capable of matching a user with content based on the user's proximity to other users, by searching for a match between profiles of wireless devices within a wireless coverage area. Wireless devices broadcast profiles within a wireless coverage area. Other wireless devices within the wireless coverage area receive the broadcasted profiles, determine a match between the received profile and a profile stored on the wireless device, and display a match indicator if a match is determined. In this manner, a user having a wireless device may be matched with content based on the user's proximity to other users.
US09324104B1 Systems, methods, and devices for measuring similarity of and generating recommendations for unique items
The disclosure herein provides methods, systems, and devices for measuring similarity of and generating recommendations for unique items. A recommendation system for generating recommendations of alternative unique items comprises an items information database, a penalty computation engine, a recommendation compilation engine, and one or more computers, wherein the penalty computation engine comprises a customizations filter, a condition filter, and a dissimilarity penalty calculator.
US09324102B2 System and method to retrieve relevant inventory using sketch-based query
In various example embodiments, a system and method for sketch based queries are presented. A sketch corresponding to a search item may be received from a user. At least a portion of the sketch may be generated by the user. An item attribute may be extracted from the sketch. The item attributed may correspond to a physical attribute of the search item. A set of inventory items similar to the search item may be identified based on the extracted item attribute and a search scope. The identified set of inventory items may be presented to the user.
US09324098B1 Hosted payment service system and method
Various embodiments of a hosted payment service are disclosed. In some embodiments, a merchant can enable customer use of the payment service by adding a line or sequence of widget code to a web page, such as a shopping cart page, of the merchant's site. Thereafter, a user who is registered with the payment service can invoke the payment service and complete a purchase transaction directly from the merchant site. For example, while viewing a shopping cart page, the user may be able to securely interact with the payment service and complete the purchase transaction via a transaction display object that is incorporated into the shopping cart page. In some embodiments, the transaction display object prompts the registered customer to enter a secondary authentication input, and the payment service uses this input in combination with a browser cookie to authenticate the user.
US09324091B2 Location based mobile user selected time, location, and number limited automatic location based reserve and redeem discounts on products or services with automatic security and feedback features
Methods, systems, software, computer readable non-transitory media, applications, devices, and the like for providing location based, mobile, user selected, time, location, and number limited or unlimited electronic coupon card selection of automatic location based reserve and redeem discounts on products or services with a profile picture, tag, motion enabled watermark, or other visual, 2D or mechanism for security purposes.
US09324088B2 Systems and methods to provide messages in real-time with transaction processing
In one aspect, a computing apparatus is configured to generate trigger records for a transaction handler to identify authorization requests that satisfy the conditions specified in the trigger records, identify communication preferences of the users associated with the identified authorization requests, and use the communication preferences to target real-time messages at the users in parallel with the transaction handler providing responses to the respective authorization requests.
US09324087B2 Method, system, and computer program product for linking customer information
In a business where a database tracks customers and manages customer accounts, a method and system correctly link accounts with customers. The method entails reading customer information for a first customer and for a second customer, and then utilizing personal identification information obtained from other sources to determine if the first customer is the same as the second customer. If the first customer and the second customer are the same person, the first customer and the second customer are identified as being the same unique person. Accounts associated with the two customers are identified as belonging to the same unique person. Viewed another way, the method and system of the present invention takes an existing database of personal identification information, and cross-references that database against other sources of personal identification information to identify persons who appear to be separate persons, but who are actually one and the same individual.
US09324086B2 Method of sharing multi-media content among users in a global computer network
In one embodiment of the present invention, a method for sharing multi-media content among a plurality of users in a computer network comprises creating a plurality of user accounts, each of said user accounts corresponding to one of the plurality of users, and having a plurality of interactive features including a first feature that permits the user to upload the multi-media content to the computer network; forming a user network including one or more of the plurality of user accounts in communication with one or more other user accounts and to the uploaded multi-media content via the computer network; categorizing the uploaded multi-media content in accordance with the subject matter of the uploaded multi-media content; organizing the uploaded multimedia content in a competitive format; and establishing a hierarchy for the uploaded multi-media content within the competitive format as a function of a competitive measurement system.
US09324075B2 Geotagged image for checking validity of purchase transaction
A service provider receives, from a merchant device, a geotagged image of a payment instrument, such as a credit card, provided to the merchant by a buyer for payment. It first determines the validity of the payment instrument using the captured image and then assesses the validity of the claimed purchase transaction by comparing the GPS data in the geotagged image, representing the geotagging location, with a separately transmitted GPS data, representing the location of transmitting the geotagged image. For further assessment, it may further compare the time of geotagging the image with the time of transmitting the image. The service provider then determines on the overall validity of the claimed purchase transaction based on the determination on the validity of the payment instrument and the assessment results, and if it determines the purchase transaction is valid, processes requested payment to the merchant's account.
US09324072B1 Bit-flipping memory controller to prevent SRAM data remanence
A memory is organized into blocks. In a bit-flipping operation, a memory block is read, the read bit data values are inverted, and the inverted data is written back to the memory block. Inverted memory blocks are tracked by setting a flag bit in the memory block, or by storing a pointer to a memory block. In a read operation, a memory block is read and, if the tracking method indicates the memory block is inverted, the read data values are reverted before being returned. In a write operation, a memory block is read and, if the tracking method indicates the memory block is inverted, the write data values are inverted before being written. Inversion of data values and tracking of inverted memory blocks may be performed by a specialized memory controller or by a processor executing secure memory code. Data remanence is thus prevented in the memory.
US09324070B1 Background OCR during card data entry
Financial transaction card data can be entered by providing a picture of the card to a server programmed with a text recognition algorithm. The server can perform text recognition on the image at the same time that a consumer enters additional required data, such as a zip code. The server can perform as much text recognition processing as possible in the time the consumer is entering the additional data. Once the additional data is received, a signal can be provided to the server indicating that the user is now waiting for results of the text recognition process, meaning the server should provide them as quickly as possible. Once text recognition results are received, a consumer can make a selection to identify a character which the text recognition algorithm did not sufficiently identify. Based on known account number constraints, the user selection can cause multiple characters to be identified.
US09324059B2 Method for providing context aware access in global software project management
A method and system for managing communication between a plurality of team members are provided. The method includes, at a first agent associated with a team member, receiving inputs from a team member about an event associated with one or more team members. The method further includes sending an event request to agents of one or more team members and receiving responses from them. Based on the responses, the first agent either cancels the event, schedules the event, or reschedules the event.
US09324058B2 Caching message fragments during real-time messaging conversations
Creating and managing an editable cache of unsent message fragments during conversations using real-time messaging systems (such as instant messaging, text messaging, chat sessions, and so forth). Using this cache, a user participating in a real-time messaging conversation can cache at least one message fragment, and can then recall selected fragments for review and/or editing (as desired by the particular user) before sending to other conversation participants. Preferably, any unsent message fragment from the cache can be sent, upon request of the user, through a mouse click or keystroke.
US09324057B2 System and method for establishing a relationship based on a prior association
Disclosed herein are systems, methods, and non-transitory computer-readable storage media for automatically establishing trusted relationships between users across organizational boundaries. A user makes a request to his system to create a trusted relationship with an individual of another organization. The system then analyzes the previous communication history between the user and the other individual, and, based on that analysis, sends a query to the other individual's system. The system then receives a response from the other individual's system, and if the response matches an expected response the system forms a trusted relationship between the user and the other individual.
US09324054B2 Cross-platform document exchange using mobile devices
Document exchange is disclosed between a computer and a portable device equipped with camera functionality, memory storage, network interface, and appropriate software. An image of a computer screen is captured by the portable device. The computer screen is displaying a document intended for exchanging. The portable device examines the image to identify marking indicia that provides location information about the document. When such marking indicia is found, it is translated and used to transmit a request for a copy to the computer where the document is stored. On receipt of the request, the computer transmits the copy to the portable device.
US09324053B1 RFID tag cylinder inventory control method
A method of RFID inventory control for vending containers is provided, including providing a modular vending unit including a rotatable RFID-tagged container storage and dispensing unit, capable of incrementally rotating and locking in predetermined positions, comprising multiple discrete storage volumes each configured to contain a single RFID-tagged container, an access device for accessing the interior of the rotatable RFID-tagged container storage and dispensing unit, capable of switching between a locked and an unlocked state, and configured to cooperate with the rotatable storage and dispensing unit. The system also includes providing an RFID inventory interrogation and data collection device, comprising an RFID transducer capable of sending an interrogate signal, and receiving a RFID response signal from each RFID-tagged container, and an electronic container inventory device in communication with the RFID inventory interrogation and data collection device, configured to indicate a quantity of available containers, and a quantity of unoccupied storage volumes.
US09324052B2 System, method, and apparatus for barcode identification workflow
A method, system, and corresponding apparatus are provided for translating components of a data set from a barcode to complete an information set. In particular, a method may include receiving a first data string corresponding to a first scanned barcode; decoding the first data string according to the first barcode format to generate a first data payload; and identifying, by a processor, from the first data payload a first set of rules for extracting information from the first data payload. Methods may include extracting information from the first data payload according to the first set of rules to obtain one or more components; translating the one or more components of the first data payload into at least one translated component; and providing for display of the at least one translated component.
US09324046B2 Enterprise ecosystem
A method includes identifying a plurality of content hubs associated with an enterprise. Each content hub represents a type of content associated with an enterprise. The method also includes identifying primary nodes dependent on each content hub. The primary nodes represent subgroups of the content associated with the content hub. The method includes identifying secondary nodes associated with each primary node. The secondary nodes represent content items from the subgroups of content associated with the primary nodes. The method further includes arranging the content hubs in a visual representation of an enterprise ecosystem. The enterprise ecosystem displays a relationship between the content hubs. The method also includes displaying dependent nodes within a relationship context of the enterprise ecosystem based on user selection.
US09324043B2 Reservation system and method
A reservation system for travel, accommodation, venue ticketing and other purposes may be accessed on-line, for example via a social networking website. A user enters their social networking identification into the reservation system, which is stored for future use. When a subsequent user makes a reservation, they also enter their social networking ID and the system retrieves a list of associated parties from the social networking website, which may be a friends or contacts list, and searches for reservations made by any of those parties which have an overlapping criterion, such as date and destination. It then sends the subsequent user the social networking ID of the overlapping party. The overlap may be used to identify parties who will be at the same destination at the same time as the subsequent user, and/or are travelling on the same flight or journey. The list of associated parties may also be used to identify parties who are listing as living at the destination to which the subsequent user is travelling and those parties social networking IDs may be sent to the subsequent user. On check-in, the system may use the list of associated parties to notify the party checking-in that one of their friends or contacts has also check-in.
US09324041B2 Function stream based analysis
A method of identifying an element. The method comprises setting a training set comprising a plurality of data units, selecting a function group of building block functions adapted for processing said plurality of data units, combining members of said function group to create a stream of a plurality of combination functions each complied from at least two members of said function group, applying each member of said stream on each of said plurality of data units to create a set of results, analyzing said set of results to identify a correlation between at least one member of said stream and a target variable for an analysis of said plurality of data units, and outputting said at least one member or an indication thereof.
US09324040B2 Training ensembles of randomized decision trees
A method training a randomized decision tree through multiple iterations, each is based on: a) Receiving multiple data samples that include data subsets, each data subset corresponds to an attribute. b) Distributing the data subsets to slave processing units after sorting the data samples in consecutive ascending order by updating a first index that identifies trajectories of the training data samples through the tree nodes of the previous tree level. c) Simultaneously processing the data subsets to identify split functions for each tree node with respect to each data subset and updating a second index that identifies the trajectories of the training data samples through the tree node of the current tree level. d) Collecting the split functions from the slave processing units and constructing the current tree level by selecting a preferred split function for each tree node of the current tree level.
US09324037B2 Method for monitoring of rotating machines
Method for monitoring of a wind power plant operated in variable operating states. Start sensor data is obtained in at least one basic operating state of the machine; based on the start sensor data, a starting model with a rule set for conducting the monitoring is set up, the rule set determining which parameters are to be monitored, in which manner and with which weighting and which sensor data are to be obtained and used for this purpose; a reference SOM is prepared using the rule set with sensor data selected using the rule set and obtained in a reference operating phase of the machine; during a monitoring operating phase, time characteristics of a quantization error of the sensor data selected using the rule set being tracked with respect to the reference SOM, troubleshooting being started if the quantization error meets a criterion which is dictated by the rule set.
US09324035B2 Apparatus and method for predicting potential change of coronary artery calcification (CAC) level
An apparatus and a method predict a patient's potential change of Coronary Artery Calcification (CAC) level using various risk factors including a Coronary Artery Calcification Score (CACS). The apparatus includes a receiving unit, a cluster determining unit, a risk factor score extracting unit, a prediction model storage unit, a prediction model learning unit, and a predicting unit, and the method includes a receiving process, a risk factor score extracting process, and an operation performing process.
US09324033B2 Method and apparatus for providing standard data processing model through machine learning
An approach for providing a standard data processing model through machine learning is described. A machine learning data processing platform may process and/or facilitate a processing of the at least one data set associated with one or more computation closures to determine at least one data pattern. The machine learning data processing platform may also determine one or more data processing models associated with the one or more computation closures, the at least one data set, or a combination thereof. The machine learning data processing platform may further cause, at least in part, a training of the one or more data processing models to reflect the at least one data pattern.
US09324032B2 Method of creating a computer model of the physical world
A method of executing a computer application in the context of a computer model comprising the steps of retrieving computer model data from a model server, retrieving application information from an application server, and executing said application information in the context of the model in an execution environment.
US09324031B2 System interconnect dynamic scaling by predicting I/O requirements
Interface management techniques provide reduced power consumption along with reducing heat and EMI generation in a computer system having multiple interconnected processing units. Physical link layers of external interfaces that interconnect the processing units of have dynamically adjustable bandwidth and the bandwidths are dynamically adjusted by predicting interface bandwidth requirements. An interface control method detects events other than I/O requests that occur in a processing unit that are indicators of potential future transactions on one of the external interfaces connected to the processing unit. The method predicts, from the detected events, that future transactions will likely occur on the interface, and in response, controls the dynamically adjustable bandwidth of physical link layer of the interface to accommodate the future transactions.
US09324030B2 System interconnect dynamic scaling by predicting I/O requirements
Interface management techniques provide reduced power consumption along with reducing heat and EMI generation in a computer system having multiple interconnected processing units. Physical link layers of external interfaces that interconnect the processing units of have dynamically adjustable bandwidth and the bandwidths are dynamically adjusted by predicting interface bandwidth requirements. An interface controller detects events other than I/O requests that occur in a processing unit that are indicators of potential future transactions on one of the external interfaces connected to the processing unit. The interface controller predicts, from the detected events, that future transactions will likely occur on the interface, and in response, controls the dynamically adjustable bandwidth of physical link layer of the interface to accommodate the future transactions.
US09324026B2 Hierarchical latent variable model estimation device, hierarchical latent variable model estimation method, supply amount prediction device, supply amount prediction method, and recording medium
A hierarchical latent structure setting unit 81 sets a hierarchical latent structure that is a structure in which latent variables are represented by a tree structure and components representing probability models are located at nodes of a lowest level of the tree structure. A variational probability computation unit 82 computes a variational probability of a path latent variable that is a latent variable included in a path linking a root node to a target node in the hierarchical latent structure. A component optimization unit 83 optimizes each of the components for the computed variational probability. A gating function optimization unit 84 optimizes a gating function model that is a model for determining a branch direction according to the multivariate data in a node of the hierarchical latent structure, based on the variational probability of the latent variable in the node.
US09324022B2 Classifying data with deep learning neural records incrementally refined through expert input
Embodiments are directed towards classifying data using machine learning that may be incrementally refined based on expert input. Data provided to a deep learning model that may be trained based on a plurality of classifiers and sets of training data and/or testing data. If the number of classification errors exceeds a defined threshold classifiers may be modified based on data corresponding to observed classification errors. A fast learning model may be trained based on the modified classifiers, the data, and the data corresponding to the observed classification errors. And, another confidence value may be generated and associated with the classification of the data by the fast learning model. Report information may be generated based on a comparison result of the confidence value associated with the fast learning model and the confidence value associated with the deep learning model.
US09324015B2 Solid housing tag
A solid housing tag and method to form the solid housing tag, the method including for example, an injection molding process. The solid housing tag has a single, continuous housing of which at least partially surrounds one or more various tag components arranged about a frame. The tag components may include a lock component and/or security component. The security component may include EAS elements, such as AM, EM, and/or RF technology elements; RFID elements; and/or benefit denial type elements.
US09324014B1 Automated user content processing for augmented reality
A method and system for augmenting images in physical documents with additional digital media content is described. A user device can scan the images and automatically retrieve and render the associated digital media content. Combinations of photographs, audio, maps and videos may be generated to allow users to create a cohesive interactive story. Some aspects of the disclosure involve gathering content to generate a physical document with augmented images, analyzing images for suitability to be augmented, linking images with digital media content, and generating augmented images from digital media content such as digital images, videos, and maps.
US09324012B2 Methods, systems and apparatus for clear texturing
Disclosed are a method and system of rendering clear texturing on a media substrate. According to one exemplary method, one or more parameters are provided by a user, via a UI (User Interface), to control the clear texturing process, wherein the parameters are associated with, but are not limited to, media sheet area coverage, object type the clear texturing process is to be performed on and maximum/minimum percentage of clear material to be used for rendering the clear texturing.
US09324007B2 Systems and methods for detecting and coordinating changes in lexical items
Systems and methods for efficiently detecting and coordinating step changes, trends, cycles, and bursts affecting lexical items within data streams are provided. Data streams can be sourced from documents that can optionally be labeled with metadata. Changes can be grouped across lexical and/or metavalue vocabularies to summarize the changes that are synchronous in time. The methods described herein can be applied either retrospectively to a corpus of data or in a streaming mode.
US09323998B2 Method for identifying postal mailings
A method for identifying postal mailings includes registering the mailings by means of at least one recognizable pictorial feature and at least one external information item, or both. Further, the method includes carrying out recognition of the pictorial feature to identify a mailing, and if identification is incomplete, performing identification using the external information item.
US09323989B2 Tracking device
A tracking device is provided which includes an image information acquiring unit configured to acquire image information in the form of successive frames; and a tracking unit configured to generate a plurality of sub images each smaller than a frame of the acquired image information, to calculate likelihoods with eye images, and to decide locations of eyes using a sub image having a large likelihood value. The tracking unit decides locations of the sub images, based on locations decided by a frame of image information acquired before the one frame.
US09323987B2 Apparatus and method for detecting forgery/falsification of homepage
An apparatus and method for detecting forgery/falsification of a homepage. The apparatus includes a homepage image shot generation module for generating homepage image shots of an entire screen of an accessed homepage. A character string extraction module extracts character strings from each homepage image shot using an OCR technique. A character string comparison module compares each of the extracted character strings with character strings required for determination of homepage forgery/falsification, thus determining whether the extracted character string is a normal character string or a falsified character string. A homepage falsification determination module determines whether the corresponding homepage has been forged/falsified, based on results of the comparison. A character string learning module learns the character string extracted from the homepage image shot, based on results of the determination, and classifies the character string as the normal character string or the falsified character string.
US09323983B2 Real-time image and audio replacement for visual acquisition devices
According to some aspects, disclosed systems and methods include obtaining an image displaying an object; and performing pattern recognition on the image to determine a characteristic of the object. The systems and methods also include searching a central repository based on the characteristic to determine a candidate match associated with the object, the candidate match being associated with a preference, the preference comprising display instructions for the image; and modifying the image based on the display instructions for the image.
US09323978B2 Image processing device, endoscope apparatus, and image processing method
An image processing device includes an image acquisition section that acquires a captured image, the captured image having been captured by an imaging section, and including an image of an object, a distance information acquisition section that acquires distance information based on the distance from the imaging section to the object when the imaging section has captured the captured image, a known characteristic information selection section that selects known characteristic information corresponding to a motion amount, and outputs the selected known characteristic information, the known characteristic information being information that indicates known characteristics relating to the structure of the object, and a concavity-convexity information extraction section that extracts information that indicates a concavity-convexity part of the object that meets the characteristics specified by the selected known characteristic information from the distance information as extracted concavity-convexity information.
US09323977B2 Apparatus and method for processing 3D information
An apparatus and method for processing three-dimensional (3D) information is described. The 3D information processing apparatus may measure first depth information of an object using a sensor apparatus such as a depth camera, may estimate a foreground depth of the object, a background depth of a background, and a degree of transparency of the object, may estimate second depth information of the object based on the estimated foreground depth, background depth, and degree of transparency, and may determine the foreground depth, the background depth, and the degree of transparency through comparison between the measured first depth information and the estimated second depth information.
US09323976B2 Anti-fraud device
The invention concerns an antifraud device (100) for validating the use of a real part of a body as an imprint-bearing substrate (150) and comprising: a control unit (106), a sensor (102) intended to capture the image of an imprint carried by the substrate (150) placed on said sensor (102), a movement module (104) on which said sensor (102) is mounted and which is intended to move said sensor (102), an analysis module (108) intended to receive the data representing an image of an imprint captured before the movement of said sensor (102) and an image of an imprint (200) captured after the movement of said sensor (102) and to analyze them, and a decision-making module (110) intended to make a decision as to whether or not the substrate (150) is a real part of a body, from information transmitted by the analysis module (108).
US09323975B2 Fingerprint sensing system and method
The present invention relates to a method of determining a representation of a fingerprint pattern. The method comprises the steps of acquiring a reference signal indicative of an electric coupling between a hand surface having friction ridges and a reference sensing structure extending across a plurality of the friction ridges; and determining the representation of the fingerprint pattern based on the reference signal and a capacitive coupling between the finger and each of a plurality of sensing elements. The acquired reference signal can, for example, be used for controlling the sensing elements so that the sensing performed by the sensing elements is carried out using favorable timing, when the signal quality is good. Alternatively, or in combination, the acquired reference signal may be used for post-processing, whereby the signals/signal values obtained by the sensing elements are modified depending on the corresponding values of the reference signal.
US09323971B2 Biometric authentication apparatus and biometric authentication method
A biometric authentication apparatus of the present invention comprises: a finger-tip placing detecting means for detecting placing of a finger-tip onto a finger-tip placing section; a finger-base-part placing detecting means for detecting placing of a finger-base part onto a finger-base-part placing section; and a guidance means for conducting guidance of whether or not the finger-tip or the finger-base part has been placed, on the basis of the results of the detections conducted by the finger-tip placing detecting means and the finger-base-part placing detecting means.
US09323969B2 Indicia reading terminal including frame quality evaluation processing
There is described an indicia reading terminal that can be operative to capture a succession of frames of image data and that can be operative so that a certain frame of the succession of frames is subject to quality evaluation processing where a result of the quality evaluation processing is responsive to one or more of an incidence and sharpness of edge representations of the frame of image data.
US09323968B2 RFID reading apparatus for shelf occupancy detection
An RFID reading apparatus (20) for shelf occupancy detection, the RFID reading apparatus (20) having an antenna (16, 18, 24), wherein the antenna (16, 18, 24) comprises a housing and an antenna circuit board (24) arranged in the housing, wherein the housing has an elongate hollow profile element (18) with the antenna circuit board (24) inserted into the hollow profile element (18).
US09323967B2 Method and system of pallet packing, and method for providing data of pallet packing
There are provided a method and a system of pallet packing that generate information on an article to be loaded and a loading place of the article on a specific pallet by recognizing a 3D position on which articles are loaded on a pallet, and a method for providing loading information of the article on the pallet by using loading information of the article generated by the method. More particularly, there are provided a method and a system of pallet packing that generate information on a 3D loading position of each article by using identification information of the pallet and each article and depth information for a whole area of the pallet acquired through a depth measurement sensor and a method for providing information on a loading shape of all articles or a state in which a specific article is loaded by using loading information of the article generated through the method.
US09323966B2 Device for backscatter communication
Backscatter communication includes receiving electromagnetic energy from a base station and encoding first data and second data. The first data is encoded at a first frequency by adjusting a radar cross-section of a device to modulate the electromagnetic energy reflected back to the base station. The second data is encoded at a second frequency by limiting the adjusting of the plurality of radar cross-sections to either a first subset or a second subset of the plurality of radar cross-sections for a length of time. The second frequency is lower than the first frequency.
US09323964B2 Card detection and selection
Techniques for CSC detection and selection include generating a radio frequency (RF) field that defines a range of communication for the CSC reader, transmitting a signal in the RF field, and detecting a modulation in the RF field indicating that a first CSC is within the RF field and has responded to the signal. The modulation is inspected for collision, wherein collision occurs if more than one CSC within the RF field responds to the poll signal. After determining that the modulation does not contain a collision, a halt command is transmitted to the first CSC instructing the CSC to only respond to one or more specific commands.
US09323958B2 Method and apparatus for prevention of tampering and unauthorized use, and unauthorized extraction of information from secured devices
The present invention considers an apparatus for prevention of tampering, unauthorized use, and unauthorized extraction of information from at least one secure system including at least one information device arranged to process information, at least one integrated encryption segment arranged to encrypt the information using at least one encryption process enabled by a set of encryption key information incorporated in at least one secure information storage of the at least one information device, at least one destruction driver arranged to initiate and support at least one controllable energy release in a proximity of the at least one secure information storage of the at least one information device incorporating the set of encryption key information, such that at least fraction of the set of encryption key information has been obliterated during the controllable energy discharge.
US09323956B2 Merging external NVRAM with full disk encryption
Methods and arrangements for managing a flash drive, hard disk, or connection between the two, in a manner to ensure that sensitive data is not decrypted at any time when it would be vulnerable. Accordingly, in a first implementation, the data may preferably be encrypted as it first goes into a flash drive and decrypted when it comes out of the flash drive. In another implementation, the flash drive may be logically bound to the hard disk, so that they would both use the same encryption key. In yet another implementation, if a hard disk is moved to another system, then the flash drive may also preferably be simultaneously moved.
US09323952B2 Cryptographic equipment implementing red/black communication modes
The described technology relates to cryptographic equipment which includes an input interface, a red module, a cryptographic module, a black module, and an output interface. The cryptographic module includes a cryptographic unit, which interacts with the red module and with the black module, and a management device, which interacts with the input interface and with either the red module or the black module, but not with both simultaneously. The cryptographic unit and the management device are physically and logically separate from one another and independent, and have an identical protection mechanism capable of protecting the integrity of the management device so as to detect any attempt at tampering.
US09323951B2 Encrypted warranty verification and diagnostic tool
According to one embodiment of the present disclosure, an approach is provided in which a diagnostic system retrieves encrypted utilization data from an electronic system that were generated from utilization data corresponding to the electronic system's usage. The diagnostic system decrypts the encrypted utilization data and determines whether the decrypted utilization data are valid. When the decrypted utilization data are valid, the diagnostic system displays the decrypted utilization data on a display. In another embodiment, the diagnostic system retrieves cryptographically-protected utilization data from the electronic system and determines the authenticity of the cryptographically-protected utilization data. Once the cryptographically-protected utilization data are authenticated, the diagnostic system displays the corresponding utilization data on a display.
US09323948B2 De-identification of data
The present invention relates to a method, computer program product and system for de-identifying data, wherein a de-identification protocol is selectively mapped to a business rule at runtime via an ETL tool.
US09323947B1 System, method and computer program product for controlling access to protected personal information
A computer-based system, method and computer program product for controlling access to protected personal information is disclosed. Protected personal information that is accessible by an information management application program is stored in a computer memory. In response to a request from an authenticated user for information, which includes protected personal information, information is displayed indicating that user has requested protected personal information, but the protected personal information is not displayed. In response to receiving user input requesting access to the protected personal information, a determination is made as to whether the user is authorized to access the requested protected personal information. If so, requested protected personal information is displayed to the user and information is stored relating to the user's access to protected personal information. Otherwise, requested protected personal information is not displayed to the user and information relating to the user's access to protected personal information is not stored.
US09323946B2 Educating users and enforcing data dissemination policies
An authoring component determines the sensitivity of an authored document and generates a user interface conveying contextual educational information about data dissemination policies that apply to the document. The user interface also provides user input mechanisms that allow the user to provide inputs affect the enforcement of a given data dissemination policy on the document.
US09323942B2 Protecting information processing system secrets from debug attacks
Embodiments of an invention for protecting information processing system secrets from debug attacks are disclosed. In one embodiment, a processor includes storage, a debug unit, and a test access port. The debug unit is to receive a policy from a debug aggregator. The policy is based on a value of a first fuse and has a production mode corresponding to a production value of the first fuse and a debug mode corresponding to a debug value of the fuse. The test access port is to provide access to the storage using a debug command in the debug mode and to prevent access to the storage using the debug command in the production mode.
US09323941B2 Secure method for processing a content stored within a component, and corresponding component
The component comprises a first memory (MM) comprising a first portion (P1) having a content modified with a first modification entity (K1) and a second portion (P2) having a content modified with a second entity (K2), a storage means (MS) configured to store the first entity (K1) secretly, a non-volatile memory (NVM) storing an item of entity information representative of the second entity (K2) in a location (END) designated by a first indication (INDK2) contained in the said first portion of the first memory.
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