| Document | Document Title |
|---|---|
| US09306616B2 |
Analog baseband filter apparatus for multi-band and multi-mode wireless transceiver and method for controlling the filter apparatus
An analog baseband filter apparatus for a multi-mode and multi-band wireless transceiver and a method for controlling the analog baseband filter apparatus are provided. The analog baseband filter apparatus includes a plurality of Radio Frequency (RF) units, each of the plurality of RF units being for receiving RF signals of one of a plurality of frequency bands and outputting baseband signals, a plurality of filter blocks for filtering and amplifying the baseband signals, and a switching unit for connecting at least two of the plurality of RF units to at least one of the plurality of filter blocks according to a selected communication mode, wherein the at least one of the plurality of filter blocks is configured to be connected to a capacitor region of an adjacent filter block from among the plurality of filter blocks. |
| US09306613B2 |
Variable antenna match linearity
In embodiments of variable antenna match linearity, a wireless device includes a first transceiver and a second transceiver, an antenna via which signals are received, and a linearity controller that varies a linearity of an antenna match circuit associated with the antenna. The linearity controller can determine whether a frequency of an intermodulated signal that includes transmissions from the first and second transceivers is within one of a respective receive band of the first transceiver or the second transceiver. The linearity controller can increase a linearity of the antenna match circuit to mitigate an amplitude of the intermodulated signal in the receive band. |
| US09306609B1 |
DC-coupled differential circuit front end
A front-end of a first differential circuit is DC-coupled to a second differential circuit. The front-end comprises a resistive element, a voltage sensor and a current adjustor. The resistive element has a resistivity between a first end that is DC-coupled to the second circuit and a second end that is DC-coupled to the first circuit and accepts a programmable current passing therethrough to impose a voltage across the element that varies in direction and amplitude according to the current value. The voltage sensor senses a difference between a DC voltage at the second end of the resistive element and a desired reference voltage of the first circuit. The current adjustor adjusts a direction and amplitude of the programmable current so that the voltage of the first circuit matches the desired reference voltage of the first circuit. The first circuit may be a receiver circuit and the second circuit may be a transmitter circuit. The front-end may further comprise a current canceller comprising a second resistive element connected at a first end to the output of the second circuit. The current canceller senses the programmable current and generates a current of equal amplitude through the second resistive element and away from the output of the second circuit. The current canceller may be implemented in digital or analog form and/or in differential or common-mode operation. |
| US09306607B2 |
Wideband interference mitigation system with negative group delay and method for wideband interference cancellation
Embodiments of a wideband interference mitigation (IM) system with negative group delay (NGD) compensation and method for wideband interference cancellation are generally described herein. In some embodiments, the wideband IM system may include first frequency-selective circuitry to capture interfering signals within a bandwidth of interest from a primary signal path after removal of a desired signal, cancellation circuitry to implement a negative group delay (NGD) on output signals from the first frequency-selective circuitry to generate negative group-delayed signals, and second frequency-selective circuitry to generate interference cancellation signals from the negative group-delayed signals for combining with signals from the primary signal path. The negative group delay provided by the cancellation circuitry may compensate for a group delay of the first frequency-selective circuitry, a group delay of the second frequency-selective circuitry and a group delay of primary signal path so that the interference cancellation signals have little or no group delay with respect to signals of the primary signal path within the bandwidth of interest. |
| US09306597B1 |
Data compression
Data compression is described herein. The encoder transmits a coded word having replacement bits, as well as a code that defines the starting location of the replacement bits in a data sample. The replacement bits may be actual bits from a selected location in the new data sample. The selected location of the replacement bits can vary from data sample to data sample. The encoder may select the location based on the most significant bit that has changed. Thus, reconstructed data will be bit-accurate from the replaced bits all the way to the highest-order bit. A limited number of key values can be transmitted losslessly. Moreover, the data compression does not need forward error correction (FEC), which is a necessary part of many lossy delta encoding schemes. Furthermore, the encoding and decoding can be done very efficiently in terms of hardware and/or software. |
| US09306596B2 |
Hybrid CAM assisted deflate decompression accelerator
Disclosed is an integrated circuit including a memory device including a first portion and a second portion. The first portion is a first type of content addressable memory (CAM) with a first set of cells and the second portion is a second type of CAM with a second set of cells. The first set of cells is smaller than the second set of cells. The integrated circuit further includes a decompression accelerator coupled to the memory device, the decompression accelerator to generate a plurality of length codes. Each of the plurality of length codes include at least one bit. The plurality of length codes are generated using a symbol received from an encoded data stream that includes a plurality of symbols. The decompression accelerator further to store the plurality of length codes in the first portion of the memory device in an order according to their respective number of bits. |
| US09306595B2 |
System and method for low-power digital signal processing
A system and method for low-power digital signal processing, for example, comprising adjusting a digital representation of an input signal. |
| US09306589B1 |
Analog-digital conversion system and method for controlling the same
An analog-digital conversion system includes an analog-digital converter; and a preamplifier circuit which is provided in the previous stage of the analog-digital converter and differentially amplifies an input analog signal. In the preamplifier circuit, an offset voltage and/or a noise occurs and/or is mixed. The preamplifier circuit outputs two types of analog amplified differential signals where a phase is inverted only with respect to the offset voltage and/or the noise. The analog-digital converter has an averaging circuit which averages the two types of analog amplified differential signals for each clock cycle of sampling preceding an analog-digital conversion and outputs a digital signal based on the differential signal averaged by the averaging circuit. |
| US09306587B2 |
Oscillator circuit and configuration method thereof
The present disclosure provides an oscillator circuit. The oscillator circuit includes a signal selecting unit, a control voltage generating unit, a reference voltage generating unit, an output adjusting unit, and a frequency-dividing unit. The signal selecting unit is configured to select a reference signal or a frequency-divided signal as an input signal. The control voltage generating unit is configured to generate a control voltage based on the input signal. The reference voltage generating unit is configured to generate a reference voltage. The output adjusting unit is configured to generate an output signal based on the control voltage and the reference voltage. The frequency-dividing unit is configured to divide the frequency of the output signal and generate the frequency-divided signal. |
| US09306586B2 |
Methods and devices for implementing all-digital phase locked loop
An all-digital phase locked loop includes a time to digital converter that determines a fractional portion of a phase count. The time to digital converter has a quantization error that may be caused by phase noise, delay errors or skew errors. Several methods and devices may reduce the quantization error. A noise source may add dithering to the reference clock at an input of the time to digital converter. A digital processor may use two successive rising edges of the oscillator signal to count time delays of the time to digital convertor to the reference clock. The digital processor uses these counts to determine a ratio of the time delays and the time period of the oscillator signal for controlling a digitally controlled oscillator. A radio frequency counter circuit detects whether the oscillator signal leads or lags the reference clock because of skew and generates a phase signal to correct the skew. |
| US09306583B2 |
Delay locked loop, method of operating the same, and memory system including the same
A delay locked loop (DLL) is provided. The DLL includes a delay line, a phase detector, a delay line control unit, and a DLL controller. The delay line outputs an output clock by delaying an input clock by a first time on the basis of a select value. The phase detector detects a phase of the output clock. The delay line control unit determines a select value so that the first time corresponds to n periods of the input clock on the basis of the detected phase and an initial select value. The DLL controller provides the initial select value to the delay line control unit. The DLL controller updates the initial select value according to a change of a frequency of the input clock, and to provide the updated initial select value to the delay line control unit. |
| US09306582B2 |
Output control circuit for semiconductor apparatus and output driving circuit including the same
An output control circuit may include a period setting signal generation unit configured to output a setup signal enabled during a designated period, in response to a delayed locked loop (DLL) locking signal and an output enable reset signal. The output control circuit may also include a clock division unit configured to divide an internal clock at a preset division ratio in response to the setup signal, and output a divided clock. In addition, the output control circuit may include a shift unit configured to shift the setup signal by a preset first time in response to the divided clock, and output a first delayed setup signal. Further, the output control circuit may include an output unit configured to receive and process the first delayed setup signal in response to the divided clock, and output the output enable reset signal. |
| US09306581B2 |
Synchronization signal processing method and apparatus
The present invention provides a synchronization signal processing method and apparatus, which solves problems of low accuracy and a slow speed of synchronization operation executed on the synchronization signal. The specific steps include: acquiring multiple to-be-processed signals of a power supply, where the to-be-processed signals are signals changing periodically; generating a synchronization signal that has the same period as the to-be-processed signals by generating pulses in each period of the to-be-processed signals, where each period of the synchronization signal includes at least two pulses; detecting whether the synchronization signal is normal by determining whether parameters of all the pulses in the synchronization signal are accurate; and if the synchronization signal is normal, synchronizing the to-be-processed signals by performing time alignment on the pulses in the synchronization signal. The synchronization signal processing method and apparatus can be applied in a synchronization operation between signals. |
| US09306579B2 |
Output driver robust to data dependent noise
Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may each receive a data segment to transmit and a plurality of data segments that other drivers will transmit. A driver controller may adjust the time at which the data segment is transmitted in response to the plurality of data segments that the other drivers will transmit. The adjustment may compensate for simultaneous switching noise and cross-talk by, for example, delaying the transmission of a data segment or changing the slew rate of the signal carrying the data segment. |
| US09306578B2 |
Oscillator
An oscillator includes an oscillator circuit, a crystal filter, a package portion, and a heating portion. The oscillator circuit is configured to output an oscillation signal. The crystal filter has a frequency characteristic where an attenuation at a detuned frequency is larger than an attenuation at an oscillation frequency of the oscillation signal. The detuned frequency is a frequency different from the oscillation frequency. The package portion covers a crystal blank of the oscillator circuit and a crystal blank of the crystal filter. The heating portion is configured to heat the crystal blank of the oscillator circuit and the crystal blank of the crystal filter using a resistor disposed between: a wiring board to which the package portion is secured, and the package portion. |
| US09306577B2 |
Supply voltage drift insensitive digitally controlled oscillator and phase locked loop circuit
A digitally controlled oscillator includes a ring oscillator and a first supplementary circuit. The ring oscillator is coupled to a supply voltage and generates a signal oscillated at an oscillating frequency. The oscillating frequency is controlled by a digital code and further varies with a supply voltage drift in a first direction. The first supplementary circuit is coupled to the ring oscillator and facilitates the oscillating frequency to vary with the supply voltage drift in a second direction reverse to the first direction. |
| US09306576B2 |
Modular gray code counter
A Gray code counter has multiple two-bit Gray code counter modules, clock gated integrated cells (CGICs), and a parity bit generator. The CGICs gate clock signals provided to the two-bit counter modules, which reduces dynamic power consumption. The parity bit generator generates a parity bit that indicates a count of binary ones in a counting state. |
| US09306570B1 |
Continuous diffusion configurable standard cell architecture
At least one configurable circuit cell with a continuous active region includes at least one center subcell, a first-side subcell, and a second-side subcell. Each center subcell includes first and second pMOS transistors and first and second nMOS transistors. The first pMOS transistor has a first-pMOS-transistor gate, source, and drain. The first-pMOS-transistor source is coupled to a first voltage source. The second pMOS transistor has a second-pMOS-transistor gate, source, and drain. The second-pMOS-transistor source is coupled to the first voltage source. The first-pMOS-transistor drain and the second-pMOS-transistor drain are a same drain. The first nMOS transistor has a first-nMOS-transistor gate, source, and drain. The first-nMOS-transistor source is coupled to a second voltage source. The second nMOS transistor has a second-nMOS-transistor gate, source, and drain. The second-nMOS-transistor source is coupled to the second voltage source. The first-nMOS-transistor drain and the second-nMOS-transistor drain are a same drain. |
| US09306561B2 |
Touch switches and practical applications therefor
A touch switch apparatus emulating a mechanical switch includes a field effect sensor and an electric field stimulator mechanically associated with the field effect sensor. A field generation signal applied to the field effect sensor causes an electric field to be generated thereabout. The electric field stimulator can be moved between first and second positions with respect to the field effect sensor. When moved into proximity with the field effect sensor, the electric field stimulator disturbs the electric field. A detection circuit coupled to the field effect sensor detects and responds to the disturbance to the electric field. |
| US09306553B2 |
Voltage level shifter with a low-latency voltage boost circuit
Certain aspects of the present disclosure provide a voltage level shifting circuit employing a low latency, AC-coupled voltage boost circuit, as well as other circuits and apparatus incorporating such a level shifting circuit. Such level shifting circuits provide significantly lower latency compared to conventional level shifters (e.g., latency reduced by at least a factor of two). Offering consistent latency over the simulation corners, level shifting circuits described herein also provide significantly lower power consumption and reduced duty cycle distortion compared to conventional level shifters. |
| US09306545B2 |
Master-slave flip-flop circuit and method of operating the master-slave flip-flop circuit
A master-slave flip-flop circuit with a master latch and slave latch has clock generating circuitry which generates a gated clock signal based on the clock signal and a gating control signal. When the gating control signal has a first value, then the gated clock signal has a value dependent on the clock signal, while when the gating control signal has a second value then the gated clock signal has a fixed value independent of the clock signal. At least one component of the master-slave flip-flop circuit is controlled by the gated clock signal so that dynamic switching power can be reduced. The gating control signal is dependent on the input signal or a signal within the master latch and is independent of a slave signal in the slave latch and the output signal of the flip-flop. |
| US09306542B2 |
RF front-end with on-chip transmitter/receiver isolation using a gyrator
An RF front-end with on-chip transmitter/receiver isolation using a gyrator is presented herein. The RF front end is configured to support full-duplex communication and includes a gyrator and a transformer. The gyrator includes two transistors that are configured to isolate the input of a low-noise amplifier (LNA) from the output of a power amplifier (PA). The gyrator is further configured to isolate the output of the PA from the input of the LNA. The gyrator is at least partially or fully capable of being integrated on silicon-based substrate. |
| US09306537B1 |
Integrated circuit device substrates having packaged crystal resonators thereon
An integrated circuit device includes an integrated circuit substrate having a two piece package thereon. The package has a hermetically sealed cavity therein and a crystal resonator within the cavity. The crystal resonator includes at least one electrode electrically coupled to a portion of the integrated circuit substrate by an electrically conductive via, which extends at least partially through the package. The package may include a material selected from a group consisting of glass and ceramics. The crystal resonator includes a crystal blank and first and second electrodes on first and second opposing sides of the crystal blank. The package includes a base having a recess therein and a cap hermetically sealed to the base. The cap includes first and second electrical traces thereon, which are electrically connected to the first and second electrodes of the crystal resonator. |
| US09306535B2 |
Integrated receive filter including matched balun
A duplexer includes a transmit filter and an integrated receive filter configured to filter a receive signal from an antenna. The integrated receive filter includes a receive filter portion having multiple acoustic resonator filter elements and a matched balun configured to convert a single-ended input signal, received at a single-ended input of the matched balun from a single-ended output of the receive filter portion, to a differential output signal. The matched balun being is located in place of a phase matching inductor of the receive filter portion, eliminating need for the phase matching inductor of the receive filter portion and a phase matching inductor of the matched balun. Impedance at the single-ended input of the matched balun includes a complex conjugate of impedance at the single-ended output of the receive filter portion. |
| US09306533B1 |
RF impedance matching network
An RF impedance matching network includes a transformation circuit configured to provide a transformed impedance; a first shunt circuit in parallel to the RF input, the first shunt circuit including a first shunt variable capacitance component comprising (a) a plurality of first shunt capacitors coupled in parallel, and (b) a plurality of first shunt switches coupled to the plurality of first shunt capacitors and configured to connect and disconnect each of the plurality of first shunt capacitors to a first virtual ground; and a second shunt variable capacitance component including (a) a plurality of second shunt capacitors coupled in parallel, and (b) a plurality of second shunt switches coupled to the plurality of second shunt capacitors and configured to connect and disconnect each of the plurality of second shunt capacitors to a second virtual ground. |
| US09306529B2 |
Resonator and band pass filter
A resonator includes a multilayer body including a plurality of dielectric layers. An electrode is disposed on each of the plurality of dielectric layers. The resonator includes ground electrodes disposed on any of the dielectric layers, capacitor electrodes disposed on any of the dielectric layers, and inductor electrodes. The inductor electrodes are located in portions which start from nodes between the inductor electrodes and the capacitor electrodes as start points, pass through line electrodes disposed on dielectric layers different from the dielectric layers on which the capacitor electrodes are disposed and the dielectric layers on which the ground electrodes are disposed, and reach nodes between the inductor electrodes and the ground electrode as end points. The line electrode have a ring-shaped configuration, as viewed in a stacking direction of the dielectric layers. |
| US09306528B2 |
Composite LC resonator and band pass filter
A composite LC resonator includes a ground electrode adjacent to a first principal surface of a multilayer body, a first capacitor electrode farther inward than the ground electrode and defining a first capacitor together with the ground electrode, a first electrode of a second capacitor, a second electrode of the second capacitor defining a second capacitor together with the first electrode of the second capacitor, a first via-electrode defining a first inductor, a first end of the first via-electrode electrically connected to the first capacitor electrode and a second end of the first via-electrode electrically connected to the first electrode of the second capacitor, and a second via-electrode defining a second inductor, a first end of the second via-electrode electrically connected to the second electrode of the second capacitor and a second end of the second via-electrode being electrically connected to the ground electrode. |
| US09306525B2 |
Combined dynamic processing and speaker protection for minimum distortion audio playback loudness enhancement
Apparatuses, methods, computer readable mediums, and systems are described for combined dynamic processing and speaker protection for minimizing distortion in audio playback. In some embodiments, at least one compressed audio signal is received, at least one threshold for a speaker is retrieved, modifications to audio signal compression are determined based on the at least one compressed audio signal and the at least one threshold, information embodying the modifications is transmitted to a dynamic processor, and using the dynamic processor, at least one modified compressed audio signal is produced for the speaker based on the information. |
| US09306524B2 |
Audio signal loudness determination and modification in the frequency domain
Methods of, apparatuses for, and non-transitory computer readable media having instructions thereon that when executed cause carrying out methods of determining and modifying the perceived loudness of a frequency domain audio signal where the frequency resolution, and corresponding temporal coverage of the frequency domain information is not constant. The frequency (and thus temporal) resolution of the perceived loudness processing is maintained constant at the longest block size. One method includes a block combiner and a loudness modification interpolator. |
| US09306523B2 |
Methods and circuits to reduce pop noise in an audio device
A class D amplifier receives and amplifies a differential analog signal which is then differentially integrated. Two pulse width modulators generate pulse signals corresponding to the differentially integrated analog signal and two power units generate output pulse signals. The outputs the power units are coupled to input terminals of integrators via a resistor feedback network. An analog output unit converts the pulse signals to an output analog signal. The differential integration circuitry implements a soft transition between mute/un-mute. In mute, the integrator output is fixed. During the soft transition, the PWM outputs change slowly from a fixed 50% duty cycle to a final value to ensure that no pop noise is present in the output as a result of mode change. |
| US09306522B2 |
Method and circuit for controlled gain reduction of a gain stage
The present document relates to multi-stage amplifiers, such as linear regulators or linear voltage regulators (e.g. low-dropout regulators) configured to provide a constant output voltage subject to load transients. A multi-stage amplifier is described. The multi-stage amplifier comprises a first amplification stage configured to provide a stage output voltage at a stage output node. Furthermore, the amplifier comprises an intermediate amplification stage comprising an amplifier current source configured to provide an amplifier current and an amplifier transistor arranged in series with the amplifier current source. A gate of the amplifier transistor is coupled to the stage output node of the first amplification stage. The intermediate amplification stage is configured to provide an amplified or attenuated stage output voltage at a midpoint between the amplifier current source and the amplifier transistor. |
| US09306519B1 |
Phantom-powered inline preamplifier with variable impedance loading and adjustable interface
Phantom-powered inline preamplifiers capable of variable impedance loading are disclosed with unique adjustable interfaces. By enabling a user to adjust impedance loading from an actively-powered audio preamplifier which takes a microphone electrical signal or another sound source signal as an input, this unique audio preamplifier design with various adjustable impedance loading interface configurations can change sound characteristics according to the user's preference in a recording, production, or live concert environment. In addition, a high pass filter incorporated in a preamplifier with the variable impedance loading feature allows the user to further customize sound characteristics in the recording environment. This novel inline preamplifier, which may be standalone or integrated into a microphone casing, is powered via a microphone cable from a component (e.g. another preamplifier) providing the phantom power. This inline preamplifier may be connected to a conventional microphone and receive phantom-power into the inline preamplifier from a conventional preamplifier. |
| US09306518B2 |
Voltage regulators, amplifiers, memory devices and methods
Circuits, devices and methods are provided, such as an amplifier (e.g., a voltage regulator) that includes a feedback circuit that supplies negative feedback through a feedback path. One such feedback path includes a capacitance coupled in series with a “one-way” isolation circuit through which a feedback signal is coupled. The “one-way” isolation circuit my allow the feedback signal to be coupled from a “downstream” node, such as an output node, to an “upstream” node, such as a node at which an error signal is generated to provide negative feedback. However, the “one-way” isolation circuit may substantially prevent variations in the voltage at the upstream node from being coupled to the capacitance in the isolation circuit. As a result, the voltage at the upstream node may quickly change since charging and discharging of the capacitance responsive to voltage variations at the upstream node may be avoided. |
| US09306517B1 |
Resonant pre-driver for switching amplifier
An arrangement and a method for improving the efficiency of a multistage switching amplifier using a resonant circuit element is presented. The multistage amplifier comprises a pre-driver amplifier, a final stage amplifier and a series L-C arrangement coupled between the pre-driver amplifier and the final stage amplifier. The series L-C arrangement forms a parallel L-C resonant circuit with a gate to source capacitor of an input transistor of the final stage amplifier. An oscillation of energy takes place between the gate to source capacitor of the input transistor of the final stage amplifier and the series L-C arrangement. This oscillation of energy provides the final stage amplifier with driving current and improves efficiency of the overall multistage amplifier arrangement. |
| US09306516B2 |
Single stage switching power amplifier with bidirectional energy flow
A switching amplifier realizes bidirectional energy flow and combines switching and power amplification into one single stage so as to increase system efficiency. The modulator circuit of the amplifier receives and modulates an input signal, and generates and outputs modulated driver signals, which are used by the power driver circuit to generate signals to drive switching transformers of an amplifier circuit of the amplifier, and control signals, which are used to control an output generator circuit so as to allow individual inductors across the load by enabling current flowing through the load to have a path to ground. The amplifier circuit comprises switching transformers as well as circuitries configured to capture energy returned from the load and enable the captured energy to flow back to a power supply circuit of the amplifier through an energy flow-back circuit of the amplifier. |
| US09306514B2 |
Hybrid power amplifier comprising heterojunction bipolar transistors (HBTs) and complementary metal oxide semiconductor (CMOS) devices
A heterojunction bipolar transistor (HBT) hybrid type RF (radio frequency) power amplifier includes a first device including an input terminal for receiving an RF signal, a pre-driver stage for amplifying the received RF signal, and an output terminal, the input terminal, the pre-driver stage and the output terminal being disposed in or over a first substrate; and a second device having a main stage having an HBT amplifier circuit disposed in or over a second substrate to further amplify the RF signal amplified by the pre-driver stage. The RF signal further amplified by the main stage is output through the output terminal of the first device. |
| US09306512B2 |
ASK modulation amplification circuit
An amplitude shift keying (ASK) modulation amplifier circuit includes a first amplifier to which a high frequency signal and a modulating signal are supplied, and that is configured to perform an amplification of the high frequency signal and an ASK modulation, and a second amplifier to which an output of the first amplifier and the modulating signal are supplied, and that is configured to perform an amplification of the output signal from the first amplifier and an ASK modulation. In some configurations, an amplification gain of the second amplifier is set higher than an amplification gain of the first amplifier. |
| US09306510B1 |
Frequency dependent dual solid-state and vacuum tube power amplifier-section instrument amplifier
An audio amplifier apparatus and method which has a preamp, active 2-way crossover, solid-state power amplifier, and tube power amplifier. Audio input from a musical instrument enters the preamp where pre-amplification, equalization, and other processes such as limiting or compression take place. Audio leaves the preamp and goes to a crossover, wherein frequencies below a crossover point are sent to a solid-state power amp via a first signal path, and wherein audio frequencies above the crossover point are sent to a tube power amp via a second signal path. Outputs from the solid-state power amp and tube power amp are sent to external or internal loudspeakers. |
| US09306505B2 |
Low-noise amplifier circuit
A low-noise amplifier (LNA) circuit utilizes the capacitive cross coupling technique with two pairs of NMOS transistors in conjunction with two cross coupled PMOS transistors to obtain a reduced noise figure. By using the cross coupling technique on the PMOS input transistor, the LNA circuit is able to reduce the noise figure below 2 dB without the use of an inductor. This LNA circuit may be used to amplify a signal in the WLAN band or the Bluetooth band, either independently or simultaneously. |
| US09306502B2 |
System providing switchable impedance transformer matching for power amplifiers
System providing switchable impedance transformer matching for power amplifiers. In an exemplary implementation, an amplifier providing switchable impedance matching includes an output inductor (L1) that is part of an output path of the amplifier and a first amplifier stage comprising a first inductor (L4) coupled to the output inductor, the first inductor configured to couple a signal amplified by the first amplifier stage at a first power level to the output inductor in response to a first enable signal. The amplifier also includes a second amplifier stage comprising a second inductor (L5) coupled to the output inductor, the second inductor configured to couple the signal amplified by the second amplifier stage at a second power level to the output inductor in response to a second enable signal. |
| US09306499B2 |
Traveling wave mixer, sampler, and synthetic sampler
An electronic device comprises an input transmission line that receives an input signal, an output transmission line that transmits an output signal, a local oscillator transmission line that transmits a local oscillator signal, multiple amplification and mixing stages arranged in parallel between the input and output transmission lines and each amplifying a received portion of the input signal and mixing the amplified portion of the input signal with the local oscillator signal to produce a portion of the output signal, and multiple amplification stages arranged in parallel between the input and output transmission lines and each amplifying a received portion of the input signal to produce a portion of the output signal. The amplification stages are located proximate an output side of the electronic device, and the amplification and mixing stages are located proximate an input side of the electronic device. |
| US09306497B2 |
Synthesizer method utilizing variable frequency comb lines and frequency toggling
A variable frequency synthesizer and method of outputting the variable frequency is disclosed. The synthesizer comprises a first reference frequency, a direct digital synthesizer (DDS) receiving the first reference frequency and outputting a tuned frequency, a variable frequency comb generator receiving the tuned frequency and outputting a variable frequency comb comprised of a plurality of comb lines, a mixer receiving the variable frequency comb and a signal from an oscillator and outputting an intermediate frequency, a phase lock loop (PLL) receiving a second reference frequency and the intermediate frequency and outputting a phase lock signal, and the oscillator receiving the phase lock signal and outputting a variable synthesized frequency. |
| US09306496B2 |
Frequency multiplier apparatus and operating method thereof
The present invention provides a frequency multiplier apparatus. The frequency multiplier apparatus includes an injection-locked frequency multiplier and a frequency-to-control signal converter. The injection-locked frequency multiplier outputs an output signal having a first frequency in response to an input signal having a first basic frequency. The frequency-to-control signal converter provides a first control signal to the injection-locked frequency multiplier in response to the input signal. The injection-locked frequency multiplier adjusts the first frequency to a second frequency in response to a change of the first control signal when the first basic frequency is changed to a second basic frequency. |
| US09306488B2 |
Dual inverter system and method of controlling the same
A dual inverter system to drive a motor in an electronic apparatus and a method of controlling the same include a first inverter connected to one side of a stator winding of the motor to modulate a pulse width and to adjust power supplied to the motor, a second inverter connected to the other side of the stator winding of the motor to modulate a pulse width and to adjust power supplied to the motor, a first current detector connected to the first inverter to detect a current flowing in the first inverter, a second current detector connected to the second inverter to detect a current flowing in the second inverter, and a controller to control the motor by controlling a pulse-width modulation (PWM) signal applied to the first inverter or the second inverter based on the current flowing in at least one of the first inverter and the second inverter. |
| US09306477B2 |
Control device for hybrid vehicle
In a hybrid vehicle that selects a series mode in which an engine drives a motor generator to generate electric power and a driving motor drives drive wheels, fuel supply to the engine is stopped and motoring in which the motor generator forcedly drives the engine can be performed, failure determination of a front O2 sensor and a rear O2 sensor provided in an exhaust passage of the engine can be performed based on a change in a detection value of the sensors when the fuel supply is stopped, and a throttle valve of the engine is forcedly opened in the motoring. |
| US09306476B2 |
Pavement interlayer
A pavement interlayer, suitable for laying between layers of pavement, includes: at least one layer of interlayer material, a plurality of piezoelectric elements; at least one transmission line, coupled to the plurality of piezoelectric elements, for transmitting power generated by the plurality of piezoelectric elements to an output. |
| US09306469B2 |
Rectifier and electrical power facility
A rectifier and an electrical power facility in which the rectifier is disposed are provided that relate to the field of electromechanical technologies. The rectifier includes a rectifier circuit, a relay, and a controller. The rectifier further includes a detection resistor and a detection circuit, where the detection resistor is connected in series to a winding in the relay, a detection point of the detection circuit is set between the detection resistor and the winding, and an output end of the detection circuit is connected to the controller. When a voltage detected at the detection point of the detection circuit is abnormal, the detection circuit outputs an alarm signal to the controller, and after receiving the alarm signal, the controller stops outputting a driving signal to the driving end of the rectifier circuit. |
| US09306468B2 |
Synchronized isolated AC-AC converter with variable regulated output voltage
In an AC-AC converter comprising a primary side, a secondary side and a regulator, wherein the regulator comprises a voltage regulation circuit configured to determine an error voltage based on an at least partially alternating feedback voltage fed into the regulator from the secondary side of the AC-AC converter and to supply this error voltage and/or an information about this error voltage to the primary side of the AC-AC converter, the regulator comprises an averaging circuit configured to determine an average DC voltage based on the feedback voltage. |
| US09306467B2 |
Micro-inverter with improved control
The invention concerns an electrical module for adapting a first signal of a first system to a second signal of a second system, including: an input arranged so that a power source can be connected thereto, said power source delivering a first signal, said first signal being a direct signal, a converter module arranged to convert the supply voltage into an intermediate rectified signal formed of a direct component and a sinusoidal component; an inverter module arranged to output a signal compatible with a second signal of a second system. |
| US09306464B2 |
Synchronous rectifier control circuits of power converters
A synchronous rectifying control circuit of a power converter is provided. The synchronous rectifying control circuit comprises a synchronous rectifying driver, a charge pump capacitor, and a capacitor. The synchronous rectifying driver is coupled to a transformer for generating a control signal to switch a transistor. The charge pump capacitor is coupled to a power source for generating a charge pump voltage. The capacitor is coupled to store the charge pump voltage. The transistor is coupled to the transformer and operated as a synchronous rectifier. The charge pump voltage is coupled to guarantee a sufficient driving capability for the control signal. |
| US09306463B2 |
Full-bridge quasi resonant DC-DC converter and driving method thereof
A full-bridge quasi-resonant DC-DC converter is provided, including a transformer having a primary winding and a secondary winding, a full-bridge converting circuit electrically connected with the primary winding of the transformer, a resonant capacitor provided between the full-bridge converting circuit and the primary winding, a rectifier circuit electrically connected with the secondary winding of the transformer, and a resonant inductor connected in series with the rectifier circuit. Therefore, the full-bridge quasi-resonant DC-DC converter reduces the switching losses of the switching elements and effectively reduces the size of the converter, while increases the conversion efficiency. |
| US09306460B2 |
Power supply comprising a standby feature
A power supply device including a switch arrangement including switches for generating a square wave output, a switch control arrangement for controlling the switch arrangement, a resonator tank, a rectifier circuitry for rectifying in an output from the tank, and a burst mode operation arrangement configured to facilitate a standby mode of the power supply and including a burst mode restriction arrangement for receiving and evaluating a first feedback parameter associated with a switch of the switch arrangement, the burst mode operation arrangement further receiving and evaluating a second feedback parameter indicative of the output voltage of the power supply device, and being configured to disable and enable the burst mode feature based on the evaluation of both the first feedback parameter and second feedback parameter by controlling an output from the burst mode operation arrangement. |
| US09306459B2 |
Control circuit for burst switching of power converter and method thereof
This invention provides a control circuit for burst switching of a power converter comprising: an adaptive circuit generating an adaptive threshold in response to a feedback signal correlated to an output load of the power converter; and a switching circuit generating a switching signal to switch a transformer of the power converter in accordance with the adaptive threshold and the feedback signal for regulating an output of the power converter. |
| US09306453B2 |
DC/DC converter and an image forming apparatus to which a power is supplied from the DC/DC converter
The power supply apparatus includes a switching element, a voltage output unit configured to generate a DC voltage by a switching operation of the switching element and output the generated DC voltage, a voltage correction unit configured to detect the output voltage and correct the detected voltage, a control unit configured to control operation of the switching element based on the corrected voltage and a threshold voltage, and a voltage increasing unit configured to increase a correction amount by the correction unit based on the operation of the switching element. |
| US09306452B2 |
Multiple power path management with micro-energy harvesting
An apparatus comprises an output port for a circuit load, a first input port for an energy harvest source, an input/output port a second energy source, a first circuit path from the energy harvest source to the second energy source at the input/output port and to the variable load at the output port, a second circuit path from the second energy source to the output port, a cold start circuit that produces a first voltage level at the output port by charging a capacitor at the output port using energy of the energy harvest source, and a main converter circuit that produces a second regulated voltage level at the input/output port using energy of the energy harvest source when the voltage at the output port capacitor is above a specified voltage value and uses the energy of the capacitor at the output port during startup of the main converter circuit. |
| US09306450B2 |
High voltage charge pump
Various embodiments of a high voltage charge pump are described. One embodiment is a charge pump circuit that comprises a plurality of switching stages each including a clock input, a clock input inverse, a clock output, and a clock output inverse. The circuit further comprises a plurality of pumping capacitors, wherein one or more pumping capacitors are coupled to a corresponding switching stage. The circuit also comprises a maximum selection circuit coupled to a last switching stage among the plurality of switching stages, the maximum selection circuit configured to filter noise on the output clock and the output clock inverse of the last switching stage, the maximum selection circuit further configured to generate a DC output voltage based on the output clock and the output clock inverse of the last switching stage. |
| US09306447B2 |
Power supply apparatus with variable circuit loop impedance
When a power conversion unit is in a working mode, the power conversion unit converts an alternating current power from an alternating current power supply apparatus into a direct current power. Then, the power conversion unit sends a power starting signal to a first switch control unit. After the first switch control unit receives the power starting signal, the first switch control unit turns on a first switch unit, so that an overall capacitor impedance formed by a first capacitor and a second capacitor is smaller than a first capacitor impedance formed by the first capacitor. When the power conversion unit is not in the working mode, the first switch control unit turns off the first switch unit, so that the overall capacitor impedance is equal to the first capacitor impedance. |
| US09306441B2 |
Electric machine
The invention relates to an electric machine (101) comprising a stator (103), a rotatably mounted rotor (105) having a magnetizable and coolable rotor section (107) made of a super-conducting material (417), a control unit (109) designed to control a stator flow for inducing a magnetic flow through the superconducting material (417). The invention also relates to a method for operating an electric machine (101). |
| US09306435B2 |
Stator assembly for motor with hall sensor bracket
Disclosed herein is a stator assembly for a motor including: a stator core which includes a rounded base having a plurality of first holes formed in the vertical direction and a plurality of teeth radially formed on the outer circumferential surface of the base; an insulation coating layer formed on the entire surface of the stator core except the inner face of the base and the periphery of the first hole; and one or more connection parts connected to the rounded base. |
| US09306434B2 |
Control apparatus for controlling rotation of joints of robot
A joint of a robot includes a driving motor, a speed reducer that reduces rotation of an output shaft of the motor, and an arm connected to the speed reducer. The joint includes an input encoder that detects a rotational position of the motor and an output encoder that detects a rotational position of the arm. A controller controls the motor based on data indicating the rotational positions of the motor and the arm detected by the input encoder and the output encoder, respectively. The input encoder is arranged with a register that latches and retains an input EC value. The output encoder includes a register that latches and retains an output EC value, and an edge pulse output section that outputs an edge pulse to both registers every time the output EC value changes. In response to the edge pulse, both registers concurrently output EC values to the controller. |
| US09306432B2 |
Stator cooling channel tolerant to localized blockage
A motor is provided including a stator core having a plurality of stator fins projecting outwardly from the stator core. A plurality of stator cooling channels is defined between adjacent stator fins. A flow mixer ring is axially aligned with the stator core and separated therefrom by an axial gap. The flow mixer ring includes a plurality of ring fins projecting inwardly from an interior surface and a plurality of ring cooling channels defined between the plurality of ring fins. The plurality of ring fins extends from a first surface over at least a portion of an axial length of the flow mixer ring. |
| US09306431B2 |
Energy harvesting device
The present invention relates to a very simple and robust wireless batteryless device (100) for harvesting energy. The actuation upon button pressure/release results in a rotation of a first member (1) around its central axis (11) leading to a move of an element (3), which is loosely fixed at the first member (1) from a pivot point (14), and a rotation around the central axis (11) of the second member (2) to which a generator axis of an energy harvester is coupled, the rotation axis of the generator being coincident with the central axis (11). Upon full pressure/release, the element (3) is forced to rotate around the pivot point (14), allowing a vertically raised pin (22) of the second member (2) to disengage a recessed area (31, 32) at each end of a slot (30) of the element (3) and the second member (2) to rotate to its rest position. |
| US09306430B2 |
In-wheel actuator and in-wheel assembly comprising the same
An in-wheel assembly includes an in-wheel actuator and a wheel. The in-wheel actuator includes a driving motor; a hollow shaft which is disposed inside of the driving motor and driven by a rotational speed of the driving motor to rotate; a decelerator which is arranged in an inner space of the hollow shaft and configured to reduce a rotational speed of the hollow shaft and output the reduced rotational speed to an output shaft; and a shaft support which is configured to support the hollow shaft to rotate with respect to the driving motor and the decelerator. The wheel accommodates the in-wheel actuator and is driven by a rotational speed decreased by the decelerator to rotate. |
| US09306428B2 |
Motor cooling system with potted end turns
A thermal control system includes a stator having conductor end turns at opposite axial ends thereof, and first and second cooling systems respectively disposed at the opposite axial stator ends, each cooling system having a cover, a coolant inlet, a coolant outlet, and at least one cooling channel. Thermally conductive potting compound thermally mates the cooling systems with the end turns. A method of cooling end turns includes providing a cooling system for each axial end of the stator, each cooling system having at least one cooling channel that includes a coolant inlet and a coolant outlet, and thermally mating each cooling system to the respective end turns. A method of cooling end turns includes providing separate cooling systems in each axial end plate of an electric machine, and filling space within the end turns, and between the end turns and the cooling systems, with thermally conductive potting compound. |
| US09306424B2 |
Rotor for rotary electric machine
A rotor for a rotary electric machine includes a pair of Lundell-type cores, a plurality of magnets, and a magnet retainer. The pair of Lundell-type cores includes a plurality of claw poles with flange portions projecting to a circumferential direction of the rotor from an end portion on an outer diameter side of each of the claw poles. The plurality of magnets are arranged between the pair of Lundell-type cores, and are magnetized in a direction of reducing flux leakage. The magnet retainer retains each of the magnets, and has side surfaces in the circumferential direction. At least one of the side surfaces is provided with at least one projection for restraining movement of the magnet retainer in an axial direction along a rotary shaft. |
| US09306418B2 |
Uninterruptible power-supply apparatus and method of using the same
An uninterruptible power-supply apparatus has a storage battery including a first electrode and a second electrode, an output cable configured to output a discharge current of the storage battery to an external power line to be a backup target, and a first connection portion configured to externally take out a voltage of the first electrode. |
| US09306414B2 |
Medium voltage power transmission line alternative
The invention is an electrical power system for powering quasi-remote loads wherein local electric utility power is stepped up in voltage and transmitted to a remote battery bank via a low cost, two-conductor, direct burial cable. The system is configured such that current in is this cable is relatively low and constant. The battery bank is used to buffer the low power feed from the electric utility source and the high power, high crest factor remote loads. An inverter, like the type used with off-grid solar power systems, converts the DC battery power to AC power to supply the remote loads. |
| US09306407B2 |
Battery system and method
A battery system comprising at least two battery modules, wherein each battery module consists of at least one battery and a controllable first switching apparatus, which is designed to connect the respective battery module into a current path of the battery system or to electrically bridge the respective battery module, comprising at least one controllable second switching apparatus, which is designed to electrically connect the at least two battery modules in parallel or in series and comprising a control device, which is designed to control the controllable first switching apparatuses and the controllable second switching apparatus as a function of the requested electrical power. In addition, the present invention discloses a method of operating a battery system. |
| US09306405B2 |
POS terminal and method used for a POS terminal
A POS terminal, includes a battery box having a box-side commercial power source circuit to supply power from a commercial power source; a battery charge circuit to charge batteries by power supplied from the box-side commercial power source circuit; a battery discharge circuit to discharge the batteries to a POS terminal main body side; and a charge and discharge changeover switch which connects a battery discharge circuit to the batteries to cause the batteries to be discharged when the battery box is attached to a POS terminal main body, and connects a battery charge circuit to the batteries to cause the batteries to be charged when the battery box is detached from the POS terminal main body. |
| US09306403B2 |
Battery module, battery management system, system for supplying a drive of a machine suitable for generating torque with electrical energy, and a motor vehicle
A battery module includes lithium-ion battery cells and at least one discharge circuit configured to discharge the battery cells. The discharge circuit includes a control signal input, a switch, and a resistor and is configured to close the switch in reaction to a control signal at the control signal input, in order to electrically connect terminals of the battery module. The battery module can then be reliably discharged by a corresponding control signal. |
| US09306402B1 |
Circuits and methods for capacitor charging
Circuits for charging capacitors in connection with oscillators are described. The oscillator may include a mechanical resonator. The circuits may include a charging element and a switched capacitor subcircuit to control operation of the charging element, and may be considered a charging circuit in some scenarios. The charging circuits may provide rapid charging of a capacitor to provide a reference voltage to the oscillator. |
| US09306394B2 |
Distributed load current sensing system
A distributed load current sensing system being connected to a power input terminal that is connected to a main power trunk that has one or multiple load branches connected thereto is disclosed to include a power bus connected to the main power trunk, an active power filter connected to the power bus and a load current sensor device coupled with each load branch for sensing the load current of each load branch and providing the sensed signal to the active power filter so that the active power filter can generate a compensation signal accurately. |
| US09306393B2 |
Battery power supply device and method of controlling power of the same
A battery power supply device is provided. The battery power supply device includes: an input unit that receives external power; a battery power unit that is connected to the input unit to charge a battery with the external power; a current detection unit that detects a current that is supplied to a load and that provides the current to the battery power unit; and an output unit that provides the external power and battery power from one node to the load and that receives a load current from the battery power unit to adjust output of the battery power. |
| US09306388B2 |
Current-limiting circuit and apparatus
Embodiments of the present invention relate to the field of electronic technologies, and provide a current-limiting circuit and apparatus to reduce costs of the current-limiting circuit and an occupied PCB board area. The circuit comprises a detecting resistor, a current-limiting resistor, a precise current unit, a power metal oxide MOS transistor, an operational amplifier OP and an input voltage end. |
| US09306384B2 |
Method of fault clearance
There is a method of fault clearance for a DC power grid (10), wherein the DC power grid (10) includes: a plurality of DC terminals (12a,12b,12c,12d); a plurality of DC power transmission media (14a,14b, 14c,14d) to interconnect the plurality of DC terminals (12a, 12b, 12c, 12d); and a plurality of DC circuit interruption device stations (18), each DC circuit interruption device station (18) being associated with a respective one of the plurality of DC power transmission media (14a,14b, 14c, 14d) and a respective one of the plurality of DC terminals (12a, 12b,12c, 12d), each DC circuit interruption device station (18) including a DC circuit interruption device (20) to selectively interrupt current flow in the associated DC power transmission medium (14a, 14b, 14c, 14d), the method comprising the steps of: (i) detecting one or more faults occurring in the plurality of DC power transmission media (14a, 14b, 14c,14d); (ii) after detecting the or each fault, opening all of the DC circuit interruption devices (20) to interrupt current flow in the plurality of DC power transmission media (14a,14b, 14c,14d); (iii) measuring electrical characteristics of each DC power transmission medium (14a, 14b, 14c,14d); (iv) identifying the or each faulty DC power transmission medium (14a, 14b, 14c, 14d), in which the or each fault is located, based on the measured electrical characteristics of the plurality of DC power transmission media (14a, 14b, 14c, 14d); and (v) after identifying the or each faulty DC power transmission medium (14a, 14b, 14c, 14d) in which the or each fault is located, inhibiting closing of the or each DC circuit interruption device (20) that is associated with the or each faulty DC power transmission medium (14a,14b, 14c,14d), in which the or each fault is located, and closing the or each DC circuit interruption device (20) that is associated with the or each non-faulty DC power transmission medium (14a, 14b, 14c, 14d), in which the or each fault is not located. |
| US09306383B2 |
Low current protection circuit
A low current protection circuit is configured to detect a lowering of a load current flowing a load to perform a low current protection operation and includes: a load current detection configured to detect a load current; a low current detection configured to detect a lowering of the load current by comparing the load current detected by the load current detection unit and a preset reference value; a protection unit configured to perform the low current protection operation when the lowering of the load current is detected by the low current detection unit; and a masking unit configured to mask the low current protection operation of the protection unit from when the lowering of the load current is detected by the low current detection unit to when a masking time period depending on a duty ratio of the external pulse signal elapses. |
| US09306379B2 |
Fuse and power distribution block
A fuse and power distribution block is provided which includes a polymer base, and multiple conductive base blocks for connection with incoming power lines or outgoing accessory lines. Each conductive base block also provides multiple alternative fuse connections on a first upper horizontal platform, a second lower horizontal platform, and a third intermediate vertical platform interconnecting the first and second platforms. The fuse and power distribution block may, depending on the desired accessory system, include 4 or 6 conductive base blocks. The fuse and power distribution block has an attractive transparent polymer cover and shell. |
| US09306378B2 |
Method for producing wire harness, and wire harness
A method for producing a wire harness includes hot pressing a first portion including an edge portion of a nonwoven material, and curing the first portion of the nonwoven material, and thereafter partially overlapping the first portion and a second portion that is softer than the first portion and is the portion of the nonwoven material other than the first portion, so that a wire bundle is covered by the first portion and the second portion. |
| US09306373B2 |
Semiconductor lasers and etched-facet integrated devices having non-uniform trenches
An edge-emitting etched-facet optical semiconductor structure includes a substrate, an active multiple quantum well (MQW) region formed on the substrate, a ridge waveguide formed over the MQW region extending in substantially a longitudinal direction between a waveguide first etched end facet disposed in a first window and a waveguide second etched end facet disposed in a second window, and first and second trenches having non-uniform widths extending in substantially the longitudinal direction between the first and second windows. |
| US09306372B2 |
Method of fabricating and operating an optical modulator
A semiconductor device comprising a substrate; a monolithic gain region disposed on the substrate and operable to produce optical gain in response to current injection, including a first electrode over a first portion of the gain region having a first length L1, with a first current I1 being applied; and a second electrode over a second portion of the gain region having a second length L2, with a second current I2 being applied; wherein I1/L1 is greater than I2/L2. |
| US09306370B2 |
Regenerative optical amplifier for short pulsed lasers, a laser source and a laser workstation
This invention provides a solution for operating a regenerative amplifier using a single electro-optical device, such as a Pockels cell. An efficient cavity geometry of a regenerative amplifier is provided for enabling pulse selection, coupling and releasing to an output by operating a single Pockels cell unit placed essentially in the middle of the optical cavity, between two polarizers, whereas a first polarizer is used for release of an amplified pulse and a second polarizer is used for injection of seed pulses and release of at least one of waste amplified pulses and seed pulses. One side of the cavity, with respect to the location of said Pockels cell, includes an empty space, whereas the other side is provided with a gain medium, which is pumped by a pump source. The regenerative amplifier of such optical design is both efficient and cost effective. The single electro-optical unit works both as the control unit for operating the regenerative amplifier and as an output pulse picker unit. |
| US09306366B2 |
Optical amplifier arrangement
An optical amplifier which integrates a pre-amplifier and a power amplifier in a single rectangular active medium to enable amplification of low power ultra-short pulses to optimal power levels. A seed beam passes through the amplification medium along a first pre-amplification path making multiple traverses of the medium. It is imaged back along the first path to make a double pass of the medium as a pre-amplifier. The beam is then re-imaged into the medium again on a second power amplification path, making multiple traverses of the medium in a single pass. The paths are independent but overlap so that efficient power extraction is achieved. Embodiments based on all passive components are described. |
| US09306365B2 |
Pump device for pumping an amplifying laser medium
A pump device for pumping an amplifying laser medium (1), having a radiation source (13) with a plurality of laser diodes (15, 16) that emit laser beams (17) which have parallel beam axes (a) extending in the direction of a z axis and which diverge at least twice as much in the direction of an x axis perpendicular to the z axis as in the direction of a y axis perpendicular to the z axis and to the x axis. The pump device also has at least one optical component (22, 22′, 22″) with at least one cylinder surface (23), with which at least some of the laser beams (17) emitted by the laser diodes (15, 16) interact. The cylinder surface (23) lies parallel to the x axis and is curved on a plane perpendicular to the x axis. |
| US09306363B1 |
Active bidirectional mode-locked lasers and applications to accurate measurements in navigation systems
In various embodiments, systems and methods can be structured to provide efficient active bidirectional mode-locked lasers, which can be used as intracavity phase interferometer (IPI) sensors. Stable bidirectional mode-locking can be achieved by a combination of a passive mechanism, a passively driven active mechanism, and a beat note detection system. Such systems can be used in guidance, navigation, and control systems, where attitude control of a vehicle relies on accurate measurements of its position and motion. In various embodiments, a detection system can be based on an all fiber intracavity phase interferometer (IPI) active laser capable of delivering accurate simultaneous measurements of all three degrees of rotation and position in a single, compact, cost effective unit. A variation of the same system can include a linear cavity laser for accurate measurements of acceleration without the use of any inertial masses. Additional apparatus, systems, and methods are disclosed. |
| US09306359B2 |
Well co-plane card edge connector
A card edge connector includes a first insulating housing loaded with a plurality of first terminals, a second insulating housing loaded with a plurality of second terminals. A card receiving slot is defined between the first insulating housing and the second insulating housing with a key disposed in the card receiving slot. The first terminals and the second terminals are disposed at two opposite sides of the card receiving slot and comprising contacting portions extending in the card receiving slot. The first insulating housing defines a pair of locking arms at opposite ends thereof and extending towards the second insulating housing, the second insulating housing defines a pair of locking recesses, the locking arms are locking with the locking recesses thereby the first and second insulating housing are snugly attached together. |
| US09306357B2 |
Electrical power connector preparation method
An electrical power connector preparation method including employing a cold drawing technique to draw a metal round rod into a thin thickness conducting contact bar, stamping the thin thickness conducting contact bar to form a mating contact portion and a mounting portion, attaching the thin thickness conducting contact bar to a contact material strip, cutting off the thin thickness conducting contact bar, repeating the aforesaid steps to obtain a large amount of metal contacts at the contact material strip and then shaping the metal contacts, removing the shaped metal contacts from the contact materials trip and electroplating the shaped metal contacts, and then using an insert molding technique to mold electrically insulative terminal blocks on metal contacts so as to obtain electrical power connectors directly, or assembling electrically insulative terminal block and the respective metal contacts with one respective electrically insulative housing to form a respective electrical power connector. |
| US09306356B2 |
Method of manufacturing electrical wire connecting structure and electrical wire connecting structure
In an electrical wire connecting structure and a method of manufacturing the electrical wire connecting structure, a terminal having a tube-shaped portion of 2.0 mm in inner diameter is prepared for an electrical wire having a conductor cross-sectional area of 0.72 to 1.37 mm2, the electrical wire 13 is inserted into an electrical wire insertion port of the tube-shaped portion of the electrical wire, and the tube-shaped portion and the core wire portion of the electrical wire are compressed to be crimp-connected to each other. Furthermore, a terminal having a tube-shaped portion of 3.0 mm in inner diameter is prepared for an electrical wire having a conductor cross-sectional area of 1.22 to 2.65 mm2, the electrical wire is inserted into the electrical wire insertion port of the tube-shaped portion 25 of the electrical wire, and the tube-shaped portion and the core wire portion of the electrical wire are compressed to be crimp-connected to each other. |
| US09306353B2 |
Integrated rotary joint assembly with internal temperature-affecting element
An improved slip-ring has a stator and a rotor, and includes a brush having a proximal end mounted on one of the stator and rotor and having a distal end engaging the other of the stator and rotor. The brush is adapted to convey electrical signals across the interface between the stator and rotor. The improvement includes: the rotor including a support member (1); and a track provided on the other of the stator and rotor, the track being arranged for sliding contact with the brush distal end; and a thermal element (3 or 6) arranged within the support member for selectively affecting the temperature of the rotor; whereby the temperature operating range of the slip-ring may be increased. |
| US09306350B2 |
Method for converting a male connector to a female connector and convertible connector
A method for converting a male connector to a female connector. A connector comprising a header, an insert and a female adapter module. The header is equipped with a plurality of pins forming male contacts. The insert ensures the hermeticity of the male pins in the header. The female adapter module is mounted in the header so as to form a female connector. The female adapter module comprises a plurality of sockets forming female contacts. Each female socket is mounted around a male pin, and a locking housing is mounted around the plurality of sockets so as to tighten each female socket around the associated male pin. |
| US09306346B2 |
Coaxial cable and connector with capacitive coupling
A coaxial cable-connector assembly includes a coaxial cable and a coaxial cable connector. The coaxial cable includes: a central conductor having a connector end; a dielectric layer that overlies the central conductor; and an outer conductor that overlies the dielectric layer having a connector end. The coaxial connector includes: a central conductor extension configured to mate with a mating connector at one end; a first insulative layer interposed between an opposed second end of the central conductor extension and the connector end of the central conductor; an outer conductor extension configured to mate with a mating connector at one end; and a second insulative layer interposed between an opposed second end of the outer conductor extension and the connector end of the outer conductor. This configuration can reduce and/or avoid PIM within the connection of two coaxial connectors. |
| US09306342B2 |
Plug connection for the direct electrical contacting of a circuit board
In a plug connection for the direct electrical contacting of contact surfaces on a circuit board, having a plug receptacle associated with the circuit board, into which the circuit board extends, having a plug pluggable into the plug receptacle, which has a contact carrier having contact elements for the direct electrical contacting of the contact surfaces of the circuit board, and having a contact pressure spring device for pressing the contact elements of the contact carrier against the contact surfaces of the circuit board, the contact pressure spring device is provided in the plug receptacle. |
| US09306336B2 |
High frequency connector
A high frequency connector includes an insulator, a plurality of terminals, a shielding case and a grounding conductor. The insulator includes a tongue plate portion and a base portion. The terminals respectively have a contact portion arranged on a surface of the tongue plate portion. The contact portion is electrically connected with a docking connector. The shielding case covers outside the tongue plate portion and the base portion. A surface of the base portion is closer to the shielding case than the surface of the tongue plate portion. The grounding conductor is formed to a shielding plate and a first flat plate from a metal sheet. The shielding plate is at least partially fixed within the tongue plate portion. The first flat plate is at least partially exposed from the base portion. The shielding plate and the first flat plate are located in a region covered by the shielding case. |
| US09306334B2 |
High speed plug connector having improved high frequency performance
A plug connector (100) includes a shell (10) and a printed circuit board (20) received in the shell. The printed circuit board includes a grounding layer (22), a conductive layer (21) disposed at a first side of the grounding layer, and an insulative layer (23) disposed therebetween. The conductive layer includes a pair of grounding traces (210), and a signal channel disposed between and isolated with the grounding traces. The signal channel includes a signal mating portion (221) disposed at a front portion. Each of the grounding traces includes a grounding mating portion (211) disposed at a front portion. Each of the grounding mating portions has a front end extending beyond the signal mating portion. The printed circuit board includes a pair of connecting traces (214). Each of the front ends of the grounding mating portions directly connects with the grounding layer by corresponding one of the connecting traces. |
| US09306327B1 |
Clip for wire harness
Retainer clip (100) attachable to automotive headlamp (10) for inhibiting second electrical connector (72) of wiring harness (44) from unintentionally separating from mating first connector (52) on the PCB (60) of the lamp. Clip (100) has central first beam (110) to contact lamp (10), lamp-retaining support base (160) depending from one end of first beam (110) to engage lamp (10), and second connector-blocking region (140) extending from an opposite end of first beam (110) that, upon assembly proximate second connector (72), inhibits separation of the connectors (52, 72). Clip (100) is stamped from sheet metal. Support base (165) has engaging arms (164, 166) joined by bight (162) either to be clipped over one fin (22) of heat sink (20) or to be squeezed between two neighboring fins (22). Engaging arms (164, 166) have protruding barbs (165) to resist separation of support base (165) from heat sink (20). |
| US09306325B2 |
Plug, socket and their combined structure of electrical connector
A kind of electrical connector is disclosed in the present invention, with the electrical connector consisting of: a socket, comprising the first insulator and several first terminals with the first insulator set with the holding space; a plug, comprising the second insulator adaptive to the holding space and several second terminals; a first protrusion is formed on the two sides of the rear end of the holding space in the first insulator respectively with the rear end and front end of the first protrusion formed with the first snap groove and a pivot joint groove respectively; a second protrusion is formed on the two sides of the middle section of the holding space in the first insulator; the second protrusion is formed with a second snap groove at its rear end and provided with the holding groove adaptive to the first protrusion respectively on its both side of the front end, with the front end of the holding groove formed with a first snapping point; the second insulator is provided with steps on its both sides, with the second snapping point on the steps; after the plug is placed in the socket, the holding groove on the plug is engaged with the first protrusion in the socket, the first snapping point and the second snapping point is engaged and localized with the first snap groove and the second snap groove respectively to prevent the plug from retreating out of the socket. |
| US09306324B2 |
Coaxial cable connector and threaded connector
An coaxial cable connector is configured to engage with an outer thread of a threaded connector. The coaxial cable connector comprises an inner sleeve, an outer sleeve arranged around the inner sleeve and a nut arranged around the inner sleeve. The nut comprises a metal sheet integral with an inner flange of the nut, wherein the metal sheet is between the inner flange and a cylindrical surface of the inner sleeve. The metal sheet has a fixed side, close to an outer flange of the inner sleeve, fixed to the inner flange of the nut, and a free side, away from the outer flange of the inner sleeve, abutting against the cylindrical surface of the inner sleeve. An empty gap is between the metal sheet and the inner flange. When the nut comprises an inner thread engaging with the outer thread, the outer flange is configured to be between the inner flange and the threaded connector. |
| US09306322B2 |
Patient support apparatus connectors
A patient support apparatus—such as a bed, stretcher, cot, chair, operating table, or the like—includes at least one electrical connector having at least one magnet integrated therein for magnetically retaining the connector with a complementary connector. The connector and the complementary connector may be designed such that they are retained together substantially only by magnetic forces, rather than frictional forces. Multiple magnets may be included within the connectors such that the connectors only couple together in a specific orientation. The connector may connect the patient support apparatus to a mattress positioned thereon, to a wall outlet, to a removable footboard or headboard, to a removable pedestal, or to other devices. The connector may include an internal safety switch that turns on a high voltage connection only when a low voltage connection is established. |
| US09306321B2 |
Electric connector
To prevent, with a simple structure, damage on a component such as a conductive contact at the time of operation of an actuator, an actuator pinching a signal transmission medium by being moved to a connection acting position facing a wiring board is provided with a protective projection protruding toward the wiring board with the actuator being moved to the connection acting position. With this, a gap between the actuator and the printed wiring board is covered with the protective projection from outside, the components such as conductive contacts disposed inside the gap between the actuator and the printed wiring board are prevented from being in contact with a nail of an operator. |
| US09306320B2 |
Connector
Terminal fittings (110) connected to end parts of wires (200) are inserted into cavities (16) of a housing (11). A seal (60) is arranged on a rear surface side of the housing (11), and a holder (40) is arranged on a rear side of the seal (60). A wire cover (70) is arranged rotatably from an open position to a closed position on a rear side of the holder (40). The wire cover (70) includes cover-side rotation center portions (76). The holder (40) includes holder-side rotation center portions (47) configured to support the cover-side rotation center portions (76) and constituting a center of rotation of the wire cover (70). |
| US09306316B2 |
Ferrite core integrated waterproof connector
A ferrite core integrated waterproof connector includes wires (WH) each having a terminal fittings (20) mounted thereon and a housing (10) with terminal accommodating chambers (12A, 12B) for accommodating the terminal fittings (20). A plate-like rubber plug (30) covers a rear surface (10B) of the housing (10) and has wire insertion holes (31) arranged to correspond to the terminal accommodating chambers (12A, 12B). Lips (32) are formed on the inner peripheral surfaces of the wire insertion holes (31) for closely contacting the outer peripheral surfaces of coatings of the wires (WH). At least one ferrite core (50) is embedded in the one-piece rubber plug (30) and has at least one hollow portion 52 concentric with at least some of the wire insertion holes (31). The ferrite core (50) is radially outward of base parts of the lips (32) of the one-piece rubber plug (30). |
| US09306315B2 |
End fitting for a cable with sealing protrusion and enclosure assembly with end fitting
An enclosure assembly for a cable extending in a connection direction includes a mating closure and a sealing enclosure operably coupled to the mating closure in the connection direction. Additionally, the enclosure assembly includes an end fitting operably coupled to the sealing enclosure. The end fitting includes a cable channel extending in the connection direction and is configured to receive the cable. A force applied to the cable is transmitted to the mating closure through the sealing enclosure. |
| US09306308B2 |
Surface-mount type electric connecting terminal, and electronic module unit and circuit board using the same
Provided is a surface-mount type electric connecting terminal which is disposed between opposing conductive objects and is configured to electrically connecting the objects while easily adjusting pressing force and recovery force. The electric connecting terminal includes a cylindrical fixed member which is made from a metallic material; a cylindrical movable member which is slidably inserted in the fixed member and is made from a metallic material; and an electrical conductive spring which is accommodated in the fixed member and whose one end contacts with the bottom of the fixed member and the other end contacts with the bottom of the movable member for thereby allowing the movable member to elastically slide against the fixed member. |
| US09306304B2 |
Shielded flat flexible cable connector with grounding
Methods and apparatuses may provide for a grounding between a shield on a flat flexible cable and a printed circuit board. According to one embodiment, the pins of a connector include ground pins that contact both ground traces on the flat flexible cable and a shield on the flat flexible cable, further connecting the cable to a ground plane. |
| US09306303B2 |
Electrical connector
An electrical connector for a circuit board includes an insulated housing, two narrow metal brackets, and a plurality of conductive contacts. The insulated housing has a connection plate, a raised portion, and two coupling portions at two opposite sides of the raised portion. The raised portion defines a plurality of contact grooves. Each coupling portion is formed in front of the raised portion. The two narrow metal brackets are provided for mounting with the coupling portions of the insulated housing. Each narrow metal bracket has a main plate, front and rear interference tabs for being interfered with one coupling portion of the insulated housing, and at least one positioning tab for being fixed onto the circuit board. The conductive contacts are fitted through the contact grooves of the raised portion. |
| US09306302B2 |
Socket with routed contacts
A socket (130) employs a substrate (310) including a conductive network. As array of first contacts (136) is on a top surface of the substrate (310) and arranged to engage an integrated circuit (110). An array of second contacts (138) is on a bottom surface of the substrate (310) and arranged to engage a circuit board (120). The conductive network electrically connects the first contacts (136) respectively to the second contacts (138), and the first contacts (136) include a roused first contact (136′) that the conductive network routes horizontally in or on the substrate (310). |
| US09306297B2 |
Interlocking poke home contact
A single element electrical connector includes a single conductive contact element formed into a cage structure having a wire insert end and a wire contact end along a longitudinal centerline axis of the connector. One wall of the cage structure includes a tab that extends into a recess included in another wall of the cage structure. The cage structure defines an upper pick-up surface having a surface area suitable for placement of a suction nozzle of a vacuum transfer device, as well as a pair of contact tines biased towards the centerline axis to define a contact pinch point for an exposed core of a wire inserted into the connector. A contact surface is defined by a member of the cage structure for electrical mating contact with a respective contact element on a component on which the connector is mounted. |
| US09306296B2 |
Contacting device of an electric plug-in connector
The invention relates to a contact-making apparatus for establishing electrical contact between a conductor or a plurality of conductors of a cable which is to be connected and a plug connector, comprising an insulating body which can be inserted into a chamber of a plug connector housing which is provided for this purpose, and at least one pressure piece which is suitable for receiving at least one conductor, wherein the at least one pressure piece is connected to the insulating body in a pivotable and articulated manner, and wherein the insulating body comprises at least one recess which in turn contains at least one insulation-displacement terminal, and wherein the pressure piece can be recessed in the at least one recess in the insulating body, and therefore the insulation-displacement terminal makes electrical contact with the end portion of the conductor. |
| US09306293B2 |
Antenna and multi-beam antenna system comprising compact feeds and satellite telecommunication system comprising at least one such antenna
A multi-beam antenna comprises an array of feeds illuminating a reflector, the feeds being associated in a plurality of groups. Each feed comprises a polarizer, two diplexers and four ports operating in four different colours. All the feeds belonging to the same group comprise first ports having the same first colour, or second ports having the same second colour, linked together to form a first beam and third ports having the same third colour, or fourth ports having the same fourth colour, linked together to form a second beam. |
| US09306288B2 |
Small antenna apparatus and method for controlling the same
An antenna apparatus for a mobile terminal is provided. The antenna apparatus includes an antenna pattern, a first electric circuit and a second electric circuit respectively connected between both ends of the antenna pattern and a system ground, and a third electric circuit disposed between the antenna pattern and a feeding line, wherein the first electric circuit and the second electric circuit extend electrical wavelengths of the antenna pattern and the third electric circuit increases input impedance matching. |
| US09306287B2 |
Antenna structure with an effective serial connecting capacitance
In an antenna structure having a serial connected capacitance effect, mainly a metallic planar antenna is provided thereon at least with a first metallic plane board, and a second metallic plane board being close to but not connected to the first metallic plane board to form the effect of capacitance in serial connecting. And more, the antenna structure further has an extension arm made from a microstrip extended from the antenna or the second metallic plane board, and can be optionally grounded or not grounded, for the purpose of adjusting the impedance value of the antenna structure. |
| US09306286B2 |
Radio frequency identification reader antenna and shelf
A radio frequency identification (RFID) reader antenna includes a feeding frame, a upper stub unit connected with the first side of the feeding frame, and a lower stub unit connected with the second side of the feeding frame, wherein the upper stub unit includes M first stubs extending towards the second side of the feeding frame, the lower stub unit includes N second stubs extending towards the first side of the feeding frame, the M first stubs and the N second stubs are arranged alternately intervallic, where M, N are integers that are greater than one. |
| US09306283B2 |
Antenna device and method for increasing loop antenna communication range
A device includes a first loop antenna and a second loop antenna. The first loop antenna includes at least three sides, wherein at least two of the sides form an acute interior angle. The second loop antenna includes at least one side that runs in a substantially parallel direction to one of the at least three sides of the first loop antenna. The first loop antenna and the second loop antenna are arranged substantially on the same plane. |
| US09306279B2 |
Wireless terminal
Embodiments of the present invention provide a wireless terminal including a PCB, an antenna, and a data connector. The PCB has a groove, which divides the PCB into a first part and a second part. The second part is connected to the antenna, the first part is connected to the data connector through a rotating shaft, and connecting wires of the data connector are connected to the second part. The first part and the second part each have a ground. The ground of the first part is connected to a metal casing of the data connector and a ground wire of the data connector is connected to the ground of the second part and the ground wire of the data connector is electrically connected to the metal casing of the data connector. |
| US09306277B2 |
Multi-antenna device and communication device
A multi-antenna device includes a grounding plate, a first antenna and a second antenna. The first antenna includes a first feed element that is grounded to the grounding plate via a first feed point. The second antenna includes a second feed element that is grounded to the grounding plate via a second feed point. The first feed point and the second feed point are disposed such that a straight line connecting the first feed point and a center of the grounding plate and a straight line connecting the second feed point and the center of the grounding plate are substantially perpendicular to each other in a plan view. |
| US09306272B2 |
Device for fixing a satellite antenna for construction equipment
An apparatus for fixing a satellite antenna for a construction machine is disclosed, which can adjust the height of the satellite antenna that is installed outside a cab to receive a signal of a satellite receiver installed inside the cab when the equipment is transported or operated in a workshop having a low ceiling. The apparatus for fixing a satellite antenna for a construction machine that is mounted outside a cab to receive a signal of a satellite receiver installed inside the cab, includes a bracket composed of a first mount portion mounted on an outer surface of the cab, a second mount portion formed to extend from the first mount portion to be bent, and a third mount portion formed to be bent against the second mount portion; a satellite antenna mounted on the second mount portion to receive a satellite signal; and a hanger fixing a pole, which is laid down to prevent the damage of the satellite antenna due to contact with an obstacle when the equipment is transported or operated, to the third mount portion. |
| US09306269B2 |
Electronic apparatus with radio antenna folded in a casing
In the field of electronic apparatuses that can be held in the hand and that comprise a miniaturized radio antenna, an apparatus comprises a casing of generally parallelepipidal form with a main face and a first small side. The antenna extends partly along the main face and partly over the first side. It comprises a conductive structure divided up so as to form a meandering inductive conductive line linked to a main conductive surface which extends over most of the first side and which is folded at the ends of this first side onto a second and a third side adjacent to the main face to form two folded lateral wings, at least one respective slot being provided to separate each wing from the main conductive surface and thus narrow and lengthen the paths of the electric currents going to the folded lateral wings. |
| US09306268B2 |
Electronic device and method for manufacturing the same
An electronic device and a method for manufacturing an outer housing of the electronic device are provided. The electronic device includes an outer housing including a portion including a base including a non-conductive material and a plurality of islands formed on or above the base, wherein the plurality of islands include metallic materials, wherein the plurality of islands are spaced apart from each other, and wherein the plurality of islands form a two-dimensional (2D) pattern. The method includes injection-molding a base and forming a plurality of islands on or above the base, wherein the plurality of islands include metallic materials, and wherein the plurality of islands are spaced apart from each other to form a 2D pattern. |
| US09306264B2 |
Transition between a microstrip protruding into an end of a closed waveguide having stepped sidewalls
A transition (100, 300) from microstrip to waveguide, the waveguide comprising first (120) and second (105, 105′, 105″) interior surfaces connected by side walls (115, 116) whose height (h1, h2, h3) is the shortest distance between said interior surfaces, and a microstrip structure (130, 135, 110) extending into the closed waveguide (105). The microstrip structure comprises a microstrip conductor (130, 135) on a dielectric layer arranged on said first interior surface. The microstrip conductor (130, 135) comprises and is terminated inside the closed waveguide by a patch (135). The height (h1) of the side walls (115, 116) along the distance that the microstrip conductor (130, 135) extends into the closed waveguide (105) being less than half of the greatest height (h3) beyond the microstrip structure's protrusion into the closed waveguide (105). |
| US09306260B2 |
Coupler and electronic apparatus
According to one embodiment, a coupler for transmitting and receiving electromagnetic wave by electromagnetic coupling between the coupler and another, includes a line-shaped coupling element including a first open end and a second open end, a ground plane, a feeding element connecting the coupling element and a feed point, and a short circuiting element connecting the feeding element and the ground plane. The feeding element includes a first end connected to an intermediate portion between the first open end and the second open end of the coupling element, and a second end connected to the feed point. The short circuiting element includes a third end arranged between the first end of the feeding element and the second end of the feeding element, and a fourth end connected to the ground plane. |
| US09306259B2 |
Horn antenna for launching electromagnetic signal from microstrip to dielectric waveguide
A horn antenna is formed within a multilayer substrate and has a generally trapezoidal shaped top plate and bottom plate formed in different layers of the multilayer substrate. A set of densely spaced vias form two sidewalls of the horn antenna by coupling adjacent edges of the top plate and the bottom plate. The horn antenna has a narrow input end and a wider flare end. A microstrip line is coupled to the top plate and a ground plane element is coupled to the bottom plate at the input end of the horn antenna. |
| US09306257B2 |
RF phase shift apparatus having an electrically coupled path separated from an electromagnetically coupled path to provide a substantially constant phase difference therebetween
Circuitry for shifting a phase of a radio frequency (RF) signal. Mutually dissimilar and electrically coupled portions of an electromagnetic transmission line pattern on one side of a substrate interact with another electromagnetic transmission line pattern on the opposing substrate side to convey a RF signal with a phase shift that is determined by the RF signal frequency and respective dimensions of the electromagnetic transmission line patterns and is substantially constant over a wide bandwidth. With multiple implementations of such opposing electromagnetic transmission line patterns having different pattern dimensions and coupled between RF signal switches, multiple phase shifts can be selectively provided. |
| US09306256B2 |
Phase shifting device
A phase shifting device is disclosed. The phase shifting device comprises an input operable to receive an input signal to be adjusted; a coupling device coupled with the input and with an output; and at least one lumped equivalent impedance transformer circuit coupled with the coupling device to receive the input signal, the lumped equivalent impedance transformer circuit having liquid crystal variable capacitors operable to adjust the input signal in response to a bias voltage applied thereto and to provide the adjusted input signal to the coupling device as an output signal. Rather than using a microstrip structure, a lumped element equivalent is instead used, which makes it possible to exploit the advantages of a liquid crystal structure but in a more compact form. |
| US09306251B2 |
Battery pack
A battery pack includes batteries, a fan unit, a case housing the batteries and the fan unit, an air circulation passage formed in the case, an air introduction passage that makes communication between a suction part of the fan unit and outside of the case, and an air discharge passage that makes communication between the outside and an inside of the case. The air circulating passage includes a blow-off side passage that makes communication between a blowoff part of the fan unit and battery passages through which the circulating air flows to exchange heat with the batteries, and a suction side passage that makes communication between the battery passages and the suction part of the fan unit. At least one of the blow-off side passage and the suction side passage is an in-duct passage formed inside a duct disposed in the case. |
| US09306250B2 |
Battery cooling structure
A protrusion 53 is shaped to protrude from a main body 51 toward a supporter non-contact part 23 so as to circumvent a supporter 30. The protrusion 53 includes a protrusion heat transfer surface 55 which is a surface on the battery heat transfer surface 20 side (i.e., an upper side Y2). A heat conduction member 40 contacts with the supporter non-contact part 23 and the protrusion heat transfer surface 55. |
| US09306249B2 |
Method for estimating the temperature at the core of a battery cell
A method of estimating temperature at a core of a module of a traction battery of an electric or hybrid vehicle in which is packaged a plurality of electric charge accumulating elements, the method including: measuring a temperature at a level of an exterior wall of the battery module; and calculating an estimation of the temperature at the core of the battery module on the basis of the measurement of the temperature. |
| US09306247B2 |
Method of detecting battery pack damage
A method is provided for detecting when a vehicle mounted battery pack is damaged from an impact with a piece of road debris or other obstacle. Positioned within the battery pack is a plurality of deformable cooling conduits located between the lower surface of the batteries within the battery pack and the lower battery pack enclosure panel. One or more sensors are incorporated into the cooling conduits which monitor coolant flow rate or pressure. When the cooling conduits deform, a change in coolant flow/pressure occurs that is detected by the sensors integrated into the conduit's coolant channels. A system controller, coupled to a sensor monitoring subsystem, may provide any of a variety of responses when cooling conduit deformation is detected. |
| US09306242B2 |
Lead-acid battery moss guard
A moss guard for a lead-acid battery cell includes a body and a plurality of fingers extending from a side of the body. The plurality of fingers are configured to substantially cover the top surfaces of negative electrodes between the negative electrodes and a positive strap. An end of at least one of the plurality of fingers distal to the body includes a lock, and the lock is configured to resiliently deflect between an engaged position and a disengaged position. The lock is configured to fix the moss guard with respect to positive lugs while in the engaged position. |
| US09306236B2 |
Cable-type secondary battery
Disclosed herein is a cable-type secondary battery having a horizontal cross section of a predetermined shape and extending longitudinally, comprising: a core for supplying lithium ions, which comprises an electrolyte; an inner electrode, comprising an open-structured inner current collector surrounding the outer surface of the core for supplying lithium ions, an inner electrode active material layer formed on the surface of the inner current collector, and a first electrolyte-absorbing layer formed on the outer surface of the inner electrode active material layer; a separation layer surrounding the outer surface of the inner electrode to prevent a short circuit between electrodes; a second electrolyte-absorbing layer formed on the surface of the separator; and an outer electrode surrounding the outer surface of the second electrolyte-absorbing layer and comprising an outer electrode active material layer and an outer current collector. |
| US09306231B2 |
Back-up fuel cell electric generator comprising a compact manifold body, and methods of managing the operation thereof
A fuel cell electric generator designed for back-up in the absence of network electricity supply. The generator comprises a fuel cell stack, means for supplying the stack with a first and a second reagent flow comprising, in turn, pressure reducing means, and a manifold body to communicate with the stack said first and second reagent flows and at least a flow of coolant fluid via a respective coolant loop. The manifold body comprises inside chambers for the mixing of said reagent flows with corresponding re-circulated product flows and a coolant fluid expansion chamber within which said pressure reducing means of said first and second reagent flows are positioned at least partially drowned by said coolant. Method for the start-up and shutdown of the generator, and a method for detecting the flooding of a fuel cell and a method for detecting the presence of gas leakages in the generator are also disclosed. |
| US09306230B2 |
Online estimation of cathode inlet and outlet RH from stack average HFR
A method for estimating cathode inlet and cathode outlet relative humidity (RH) of a fuel cell stack. The method uses a model to estimate the high frequency resistance (HFR) of the fuel cell stack based on water specie balance, and also measures stack HFR. The HFR values from the estimated HFR and the measured HFR are compared, and an error between the HFR values is determined. An online regression algorithm is then utilized to minimize the error and the solution of the regression is the RH profile in the stack including the cathode inlet and outlet relative humidities. |
| US09306229B2 |
Fuel cell system
A fuel cell system includes a fuel cell, a fuel gas supply channel, a fuel off-gas discharge channel, an oxidant gas supply channel, an oxidant off-gas discharge channel, a first shut valve, a second shut valve, a shut valve controller, a temperature detector, a scavenging device, and an elapsed-time detector. The elapsed-time detector is configured to detect an elapsed time elapsed from a timing at which the fuel cell is shut down. The scavenging device scavenges the oxidant gas flow channel and the fuel gas flow channel in sequence if the elapsed time detected by the elapsed-time detector is within a first predetermined period of time. The scavenging device scavenges the fuel gas flow channel and the oxidant gas flow channel in sequence if the elapsed time detected by the elapsed-time detector is outside the first predetermined period of time. |
| US09306227B2 |
Fuel cell and flow field plate for fluid distribution
A flow field plate for use in a fuel cell includes a non-porous plate body having a flow field that extends between first and second ends of the non-porous plate body. The flow field includes a plurality of channels having channel inlets and channel outlets, a fluid inlet portion that diverges from the first end to the channel inlets, and a fluid outlet portion that converges from the channel outlets to the second end. A fuel cell including the flow field plate includes an electrode assembly having an electrolyte between an anode catalyst and a cathode catalyst. The flow field of the flow field plate is side by side with the electrode assembly. A method of processing a flow field plate includes forming the flow field in a non-porous plate body. |
| US09306225B2 |
Bipolar separator assembly for fuel cells and method of making same
A bipolar separator assembly for use with a fuel cell comprising: a plate member having opposing first and second surfaces compatible with fuel gas and oxidant gas, respectively, the plate member having first and second opposing end segments and third and fourth opposing end segments which are transverse to the first and second opposing end segments; first and second pocket members situated adjacent the first and second end segments and extending outward of the first surface, the first and second pocket members being adapted to enclose opposing ends of an anode current collector, and third and fourth pocket members situated adjacent the third and fourth end segments and extending outward of the second surface, the third and fourth pocket members being adapted to enclose opposing ends of a cathode current collector, wherein at least a portion of each of the first, second, third and fourth pocket members is formed separately from the plate member and is releasably positioned relative to the plate member. |
| US09306224B2 |
Cooling module and method for producing a cooling module
The invention relates to method for the manufacture of a cooling module in the form of a body having an inner space for the reception of battery cells, wherein the body has one or more cooling passages extending in parallel to one another between an inlet region and an outlet region and is formed at least partly from a length or from a plurality of lengths of a hollow section. |
| US09306223B2 |
Electrolyte materials, thermal battery components, and thermal batteries for intermediate temperature applications
A eutectic formulation of KOH and NaOH is used as an electrolyte or an electrolyte-separator. An anode, and/or a cathode can contain the eutectic formulation of KOH and NaOH. A battery can contain an electrolyte-separator, an anode, and/or a cathode with the eutectic formulation of KOH and NaOH. The electrolyte in the electrolyte-separator can have a melting point from about 170° C. to about 300° C. making it suitable for use in a thermal battery that does not require a pyrotechnic device for certain high-temperature applications. |
| US09306221B2 |
Fuel electrodes for solid oxide electrochemical cell, processes for producing the same, and solid oxide electrochemical cells
A fuel electrode for a solid oxide electrochemical cell includes: an electrode layer constituted of a mixed phase including an oxide having mixed conductivity and another oxide selected from the group including an aluminum-based oxide and a magnesium-based composite oxide, said another oxide having, supported on a surface part thereof, particles of at least one member selected from nickel, cobalt, and nickel-cobalt alloys. |
| US09306219B2 |
Binder composition for secondary battery, electrode mixture for secondary battery employing it, and secondary battery
A binder composition of the present invention is for a non-aqueous secondary battery with excellent adhesion between an electrode active material and a current collector. A degree of electrode swelling with an electrolytic solution at a high temperature is small. This binder composition can be used in production of an electrode mixture for a non-aqueous secondary battery. The binder composition can comprise a binder made of a fluorinated copolymer having repeating units derived from tetrafluoroethylene and repeating units derived from propylene, and a solvent or dispersing medium, wherein the fluorinated copolymer has a weight average molecular weight of from 10,000 to 300,000. |
| US09306214B2 |
Lithium ion battery
In a lithium ion battery having a discharge capacity of 30 Ah or more and 125 Ah or less, the positive electrode composite has the following configuration: The positive electrode composite contains a mixed active material of layered lithium nickel manganese cobalt composite oxide (NMC) and olivine lithium iron phosphate (LFP), a density of the positive electrode composite is 2.0 g/cm3 or more and 2.6 g/cm3 or less, and an application quantity of the positive electrode composite is 100 g/m2 or more and 200 g/m2 or less. Furthermore, a weight ratio (NMC/LFP) of the mixed active materials is set to 10/90 or more and 60/40 or less. Alternatively, when a discharge capacity is defined as X and the weight ratio is defined as Y, the relation of Y<−0.0067X+1.84 (30≦X≦125) is satisfied. |
| US09306207B2 |
Method of fabricating sulfur-infiltrated mesoporous conductive nanocomposites for cathode of lithium-sulfur secondary battery
Disclosed is method of fabricating sulfur-infiltrated mesoporous conductive nanocomposites for a cathode of a lithium-sulfur secondary battery, whereby a cathode material having a relatively high content of sulfur is fabricated and a high energy density in a lithium-sulfur secondary battery is realized, including: a) performing thermal treatment on sulfur particles in a reactor at a high temperature to melt the sulfur particles; b) adding a mesoporous conductive material in macroscale to a sulfur solution in the reactor; c) pressurizing the mesoporous conductive material in macroscale in the reactor so that the mesoporous conductive material in macroscale is completely immersed in the sulfur solution, and then maintaining the pressurized and molten state; d) cooling the sulfur particles and the mesoporous conductive material in macroscale so that sulfur within pores of the mesoporous conductive material in macroscale is crystallized; and e) grinding sulfur-infiltrated mesoporous conductive composites to fabricate sulfur-infiltrated mesoporous conductive nanocomposites. |
| US09306205B2 |
Rechargeable battery having safety member
A rechargeable battery according includes a plurality of electrode assemblies including a first electrode assembly and a second electrode assembly, a case housing the plurality of electrode assemblies, a cap assembly coupled to the case, and a first safety member including a first conductive plate between the first electrode assembly and the case, a second conductive plate between the second electrode assembly and the case, and a safety fuse between the first conductive plate and the second conductive plate and coupling the first and second conductive plates together. |
| US09306202B2 |
Separator for a secondary battery and secondary battery including the same
A separator for a secondary battery and a secondary battery including the same, the separator including a porous substrate; a patterned fabric layer on at least one side of the porous, the patterned fabric layer having patterns; and a polymer coating layer on the patterned fabric layer. |
| US09306200B2 |
Battery holding device
A battery holding device is configured to hold a capacitor including at least one storage cell and includes a cell holder and a heater wire. The cell holder is provided at a side surface of at least one storage cell and has a concave-convex surface facing the at least one storage cell. The concave-convex surface has a protrusion contacting the at least one storage cell. At least a portion of the heater wire is embedded in the cell holder. |
| US09306198B2 |
Power tool with battery pack ejector
A power tool has a mechanism for forcing a battery pack at least partially from a cavity that receives a battery pack. A biasing member is in the cavity. A member for retaining the biasing member is also in the cavity. The biasing member forces the battery pack at least partially from the cavity. When the battery pack is locked onto the frame, the biasing member is in a compressed condition and when the battery pack is an unlocked position, the biasing member forces the battery pack at least partially from the frame. |
| US09306195B2 |
Electrochemical cells
An electrochemical cell is presented. An anode compartment in the cell contains a sacrificial metal in an amount between about 10 volume percent and about 40 volume percent, based on the volume of the compartment. The sacrificial metal has an oxidation potential less than the oxidation potential of iron. An energy storage device including such an electrochemical cell is also provided. |
| US09306188B2 |
Organic light emitting diode display
An organic light emitting diode display having a flat region having a flat surface, and curved regions disposed at left and right sides of the flat region and formed in curved surfaces, having a display panel including a substrate, which maintains a flat surface in the flat region, and is formed in curved surfaces in the curved regions, and organic light emitting diodes disposed on the substrate, a window disposed in the flat region and the curved regions on the display panel, and a cover member disposed under the display panel, in which the cover member includes a flat cover member disposed in the flat region and curved cover members disposed in the curved regions, and the flat cover member and the curved cover member are formed of different materials or have different thicknesses. |
| US09306187B2 |
Organic light-emitting display device and method of manufacturing the same
Provided is an organic light-emitting display device for forming a strong sealing structure. The organic light-emitting display device includes: a lower electrode that is disposed on a substrate; a first barrier wall that protrudes beyond a top surface of the lower electrode; and a second barrier wall that is disposed on at least a top surface of the first barrier wall and has a cross-section having a reverse-tapered shape, wherein the second barrier wall includes a low temperature viscosity transition (LVT) inorganic material including tin oxide. |
| US09306184B2 |
Ordered organic-organic multilayer growth
An ordered multilayer crystalline organic thin film structure is formed by depositing at least two layers of thin film crystalline organic materials successively wherein the at least two thin film layers are selected to have their surface energies within ±50% of each other, and preferably within ±15% of each other, whereby every thin film layer within the multilayer crystalline organic thin film structure exhibit a quasi-epitaxial relationship with the adjacent crystalline organic thin film. |
| US09306177B2 |
Organic light-emitting layer material, coating liquid for use in forming organic light-emitting layer with organic material, organic light-emitting device produced with coating liquid, light source apparatus with organic light-emitting device, and methods for manufacture thereof
An organic light-emitting device includes an upper electrode, a lower electrode, and a light-emitting layer disposed between the upper and lower electrodes, wherein the light-emitting layer includes a host and a first dopant. The first dopant includes a pyridyltriazole derivative as an auxiliary ligand, the auxiliary ligand of the first dopant contains a functional group R1 or a functional group R2, and the first dopant is displaced toward a surface of the light emitting layer by the action of at least one of the functional groups R1 and R2, wherein the surface is on a side where the upper electrode is present, and also directed to a coating liquid for use in forming the light-emitting layer with an organic material. An organic light-emitting device is produced with the coating liquid, a light source apparatus includes the organic light-emitting device, and methods for manufacture thereof are disclosed. |
| US09306174B2 |
Organic electroluminescent device
A high-efficiency, high-durability organic electroluminescent device, particularly a phosphorescent organic electroluminescent device is provided by using an organic compound of excellent characteristics that exhibits excellent hole-injecting/transporting performance and has high triplet exciton confining capability with an electron blocking ability, and that has high stability in the thin-film state and high luminous efficiency.The organic electroluminescent device includes a pair of electrodes, and a plurality of organic layers sandwiched between the pair of electrodes and including a light emitting layer and an electron blocking layer, wherein a compound of the following general formula (1) having a carbazole ring structure is used as a constituent material of the electron blocking layer and the light emitting layer. |
| US09306173B2 |
Aromatic amine derivative and electroluminescence device using the same
Provided are a novel aromatic amine derivative having a specific structure and an organic electroluminescence device in which an organic thin layer comprising a single layer or plural layers including a light emitting layer is interposed between a cathode and an anode, wherein at least one layer of the above organic thin layer contains the aromatic amine derivative described above in the form of a single component or a mixed component. Thus, the organic electroluminescence device is less liable to be crystallized in molecules, improved in a yield in producing the organic electroluminescence device and extended in a lifetime. |
| US09306172B2 |
Anthra[2,3-b:7,6-b']dithiophene derivatives and their use as organic semiconductors
The invention relates to novel anthra[2,3-b:7,6-b′]dithiophene derivatives, methods of their preparation, their use as semiconductors in organic electronic (OE) devices, and to OE devices comprising these derivatives. |
| US09306169B2 |
Electronic device, polymer compound, organic compound, and method of producing polymer compound
An electronic device that serves as a high-brightness electroluminescent device includes a layer containing a polymer compound having one or more structural units selected from a structural unit represented by formula (1) and a structural unit represented by formula (7) as a charge injection layer and/or a charge transport layer: Wherein R1, R2, R6 and R7 represent certain groups; m1 and m5 represent an integer of 0 or more; when R2 and R7 are plurally present, they may be the same or different; and a hydrogen atom in formula (1) or (7) may be replaced with a substituent other than the certain groups. |
| US09306167B2 |
Field emission device and method of fabricating the same
A field-emission device is disclosed. The device comprises a solid state structure formed of a crystalline material and an amorphous material, wherein an outer surface of the solid state structure is substantially devoid of the amorphous material, and wherein a p-type conductivity of the crystalline material is higher at or near the outer surface than far from the outer surface. |
| US09306166B1 |
Fabrication method of resistance variable memory apparatus
A fabrication method of a resistance variable memory apparatus includes forming an amorphous phase-change material layer on a semiconductor substrate in which a bottom structure is formed, and performing crystallization on the amorphous phase-change material layer through a low-temperature plasma treatment process. |
| US09306164B1 |
Electrode pair fabrication using directed self assembly of diblock copolymers
Structures including alternating first U-shaped electrodes and second U-shaped electrodes and contact pads interconnecting the first and the second U-shaped electrodes are provided. Each of the first U-shaped electrodes includes substantially parallel straight portions connected by a bent portion located on one end of a substrate. Each of the second U-shaped electrodes includes substantially parallel straight portions connected by a bent portion located on an opposite end of the substrate. Every adjacent straight portions of neighboring first and second U-shaped electrodes constitute an electrode pair having a sub-lithographic pitch. Each of the contact pads overlaps and contacts the bent portion of one of the first and the U-shaped electrodes. |
| US09306160B2 |
Memory device having oxygen control layers and manufacturing method of same
A memory device includes a first metal layer and a second metal layer, a metal oxide layer disposed between the first metal layer and the second metal layer, and at least one oxygen control layer disposed between the metal oxide layer and at least one of the first metal layer and the second metal layer. The at least one oxygen control layer has a graded oxygen content. |
| US09306159B2 |
Phase change memory stack with treated sidewalls
Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall. A dielectric material is implanted into the film of the adhesion species to form a sidewall liner. |
| US09306156B2 |
Methods of manufacturing a magnetoresistive random access memory device
In a method of manufacturing an MRAM device, a first sacrificial layer, an etch stop layer, and a second sacrificial layer are sequentially formed on a substrate and then partially etched to form openings therethrough. Lower electrodes are formed to fill the openings. The first and second sacrificial layers and portions of the etch stop layer are removed to form etch stop layer patterns surrounding upper portions of sidewalls of the lower electrodes, respectively. An upper insulating layer pattern is formed between the etch stop layer patterns to partially define an air pad between the lower electrodes. A first magnetic layer, a tunnel barrier layer, a second magnetic layer, and an upper electrode layer are formed, and are etched to form a plurality of magnetic tunnel junction (MTJ) structures. Each MTJ structure includes a sequentially stacked first magnetic layer pattern, tunnel layer pattern, and second magnetic layer pattern, and each of the MTJ structures contacts a corresponding one of the lower electrodes. |
| US09306152B2 |
Magnetic memory and method for manufacturing the same
According to one embodiment, a magnetic memory is disclosed. The magnetic memory includes an underlying structure having conductivity provided on the substrate and including a first layer with a polycrystalline structure and a second layer with an amorphous structure, and a magnetoresistive element provide on the underlying layer. The magnetoresistive element includes a first magnetic layer provided on the underlying layer, a non-magnetic layer provided on the first magnetic layer, and a second magnetic layer provided on the non-magnetic layer. |
| US09306149B2 |
Piezoelectric material, piezoelectric element, liquid discharge head, ultrasonic motor, and dust removing device
Provided is a piezoelectric material that achieves both high piezoelectric performance and high Curie temperature. In addition, provided are a piezoelectric element, a liquid discharge head, an ultrasonic motor, and a dust removing device, which use the piezoelectric material. The piezoelectric material includes a perovskite-type metal oxide that is expressed by the following general formula (1): xBaTiO3-yBiFeO3-zBi(M0.5Ti0.5)O3 (1), where M represents at least one type of element selected from the group consisting of Mg and Ni, x satisfies 0.25≦x≦0.75, y satisfies 0.15≦y≦0.70, z satisfies 0.05≦z≦0.60, and x+y+z=1 is satisfied. |
| US09306146B2 |
Low thermal conductivity thermoelectric materials and method for making the same
A method of manufacturing fiber based and syntactic foam based composite type thermally insulating materials that retain high performance thermoelectric properties, and which can be used as thermoelectric generators or Peltier coolers for a wide range of industrial, commercial, residential and military applications. |
| US09306145B2 |
Methods of synthesizing thermoelectric materials
Methods for synthesis of thermoelectric materials are disclosed. In some embodiments, a method of fabricating a thermoelectric material includes generating a plurality of nanoparticles from a starting material comprising one or more chalcogens and one or more transition metals; and consolidating the nanoparticles under elevated pressure and temperature, wherein the nanoparticles are heated and cooled at a controlled rate. |
| US09306141B2 |
Method for manufacturing semiconductor light emitting device
According to one embodiment, a semiconductor light emitting device includes a semiconductor layer including a first surface, a second surface opposite to the first surface, and a light emitting layer; a p-side electrode provided on the second surface of the semiconductor layer in a region including the light emitting layer; an n-side electrode provided on the second surface of the semiconductor layer in a region not including the light emitting layer; an insulating film being more flexible than the semiconductor layer, the insulating film provided on the second surface and a side surface of the semiconductor layer, and the insulating film having a first opening reaching the p-side electrode and a second opening reaching the n-side electrode; a p-side interconnection layer provided on the insulating film and connected to the p-side electrode; and an n-side interconnection layer provided on the insulating film and connected to the n-side electrode. |
| US09306136B2 |
Bat-wing lens design with multi-die
A batwing beam is produced from an optical emitter having a primary LED lens over a number of LED dies on a package substrate. The LED lens includes a batwing surface formed by rotating a parabolic arc about an end of the parabolic arc over a center of the optical emitter. A center of each of the LED dies is mounted to the package substrate about the focus of a parabola whose arc forms the batwing surface, for example, between about 0.5 to 1.5 of a focal distance from the vertex of the parabola. The batwing surface reflects light from the number of LED dies through total internal reflection (TIR) or through a reflectivity gel coating. |
| US09306131B2 |
Optoelectronic semiconductor chip and method of producing an optoelectronic semiconductor chip
An optoelectronic semiconductor chip having a semiconductor layer sequence includes at least one active layer that generates primary radiation; a plurality of conversion layers that at least partially absorb the primary radiation and convert the primary radiation into secondary radiation of a longer wavelength than the primary radiation; and a roughened portion that extends at least into one of the conversion layers, wherein the roughened portion has a random structure, the semiconductor layer sequence is arranged on a carrier, a top side of the semiconductor layer sequence facing away from the carrier is formed by the roughened portion, the at least one active layer is located between the carrier and the conversion layers, and the roughened portion includes a plurality of recesses free of a semiconductor material. |
| US09306129B2 |
Light-emitting element unit and display device
A light-emitting element unit which can improve color purity of light emitted from a color filter is provided. A display device with high color purity and high color reproducibility is provided. The light-emitting element unit includes a wiring board, a light-emitting element chip provided over the wiring board, a micro optical resonator provided over the wiring board and at the periphery of the light-emitting element chip, and a phosphor layer covering the light-emitting element chip and the micro optical resonator. The display device includes a display panel having a coloring layer and a backlight module having the light-emitting element unit. Examples of the display panel include: a liquid crystal panel; and a display panel including an opening portion provided over a first substrate, MEMS moving over the opening portion in the lateral direction, and a second substrate provided with a coloring layer in a portion corresponding to the opening portion. |
| US09306128B2 |
Light emitting apparatus and surface light source apparatus having the same
Provided are a light emitting apparatus and a surface light source apparatus having the same. The light emitting apparatus comprises a package body, a first color light emitting part in a first cavity of the package body, and a second color light emitting part in a second cavity of the package body. The package body comprises a plurality of cavities. |
| US09306127B2 |
Light emitting device that includes protective film having uniform thickness
A light emitting device includes an electrically conductive member provided with a reflective film; a light emitting element mounted on the reflective film; and a protective film continuously covering a surface of the light emitting element and a surface of the reflective film. A thickness of the protective film on the reflective film in a vicinity of the light emitting element is substantially equal to a thickness of the protective film on the reflective film in the region except for the vicinity of the light emitting element. |
| US09306123B2 |
Light-emitting element
A light-emitting element comprises a light-emitting semiconductor stack comprising a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and a light-emitting layer between the first semiconductor layer and the second semiconductor layer; a first electrode comprising an contact area and an extension electrically connected to the first semiconductor layer, wherein the extension is connected to the contact area; a second electrode on the second semiconductor layer; and a first conductive part and a second conductive part formed on the light-emitting semiconductor stack and respectively electrically connected to the first electrode and the second electrode, wherein the extension is formed beyond a projected area of the second conductive part and not covered by the first conductive part, and the contact area is covered by the first conductive part. |
| US09306114B2 |
III-V compound semiconductor-based-light-emitting diode device with embedded charge carrier barrier
An optoelectronic semiconductor body includes a semiconductor layer sequence having an active region that generates radiation, a first barrier region and a second barrier region, wherein the active region is arranged between the first barrier region and the second barrier region; and at least one charge carrier barrier layer is arranged in the first barrier region, said at least one charge carrier barrier layer being tensile-strained. |
| US09306113B2 |
Silicon light emitting device utilising reach-through effects
A light emitting device comprises a body of an indirect bandgap semiconductor material. A junction region is formed between a first region in the body of a first doping kind and a second region of the body of a second doping kind of first concentration. A third region of the second doping kind of a second concentration is spaced from the junction region by the second region. The second concentration is higher than the first concentration. A terminal arrangement is connected to the body for, in use, reverse biasing the first junction region into a breakdown mode, thereby to cause emission of light. The device is configured such that a depletion region associated with the junction region reaches through the shaped region to reach the third region, before the junction enters the breakdown mode. |
| US09306112B2 |
Photoconductive antenna, terahertz wave generating device, camera, imaging device, and measuring device
A photoconductive antenna is adapted to generate terahertz waves when irradiated by pulsed light. The photoconductive antenna includes first and second conductive layers, a semiconductor layer positioned between the first and second conductive layers, first and second electrodes, and a dielectric layer. The semiconductor layer is made of a semiconductor material having a carrier density that is lower than a carrier density of the semiconductor material of the first conductive layer or the second conducive layer. The first and second electrodes are electrically connected to the first and second conductive layers, respectively. The second electrode has an aperture through which the pulsed light passes. The dielectric layer is made of a dielectric material, and is in contact with a surface of the semiconductor layer having a normal direction extending orthogonal to a lamination direction of the first conductive layer, the semiconductor layer, and the second conductive layer. |
| US09306109B2 |
Semiconductor device manufacturing method
A semiconductor device manufacturing method is provided. The method includes forming a first, second and third films, forming a first mask pattern on the third film, forming a gate electrode by using the first mask pattern, forming a second mask pattern having an opening above a portion of the first mask pattern and a region adjacent to the gate electrode, and performing ion implantation by using the first and second mask patterns. The gate electrode formation includes etching the third film, etching the second film and overetching the second film by using a first, second and third processing gases. A first, second and third depositions formed on the sidewalls of the gate electrode in the third and second films etching and overetching, contain at least one of chlorine or bromine and do not contain fluorine. |
| US09306108B2 |
Radiation detector
In an X-ray strip detector, at least one joining semiconductor film are formed on surface of a sensitive semiconductor film, on the part of X-strips and Y-strips, that is sensitive to incident X-rays to generate electric charge, and on at least an entire sensitive region of a conversion film. The joining semiconductor film has higher resistance value than resistance value of the sensitive semiconductor film. Accordingly, when the electric charge generated in the sensitive semiconductor film are collected in the X-strips and the Y-strips, movement of the electric charge into other adjacent strip electrodes is avoidable. Consequently, crosstalk can be suppressed that the electric charge leak to the adjacent strip electrodes. |
| US09306107B2 |
Buffer layer for high performing and low light degraded solar cells
Methods for forming a photovoltaic device include forming a buffer layer between a transparent electrode and a p-type layer. The buffer layer includes a doped germanium-free silicon base material. The buffer layer has a work function that falls within barrier energies of the transparent electrode and the p-type layer. An intrinsic layer and an n-type layer are formed on the p-type layer. Devices are also provided. |
| US09306104B2 |
Photovoltaic concentrator module with multifunction frame
The invention relates to a photovoltaic concentrator module with multifunction frame and also to a method for production thereof. The concentrator module has a lens- and a base plate, between which a frame extends. Between the lens plate and the frame and/or the base plate and the frame, two sealing compounds and/or adhesive compounds extend, which compounds differ with respect to their hardening time and/or gas permeability. |
| US09306095B2 |
Solar cell and method for manufacturing same
A solar cell includes: a substrate having heat dissipating characteristics; a solar cell bonded to the substrate such that the solar cell is electrically connected on a first conductive line and a second conductive line, which are disposed on a surface of the substrate; a lens, which is bonded to a transparent electrode of the solar cell; a plurality of projections, which maintain a gap between the substrate and the lens; tapered hole sections in the substrate, each of said tapered hole sections having a tapered section of each of the protruding sections fitted therein; and a sealing resin applied to the gap. |
| US09306093B2 |
Chalcopyrite-type semiconductor photovoltaic device
A scribed photovoltaic device, comprising a photovoltaic device configured for generating electrical energy responsive to receiving solar radiation, the photovoltaic device comprising a plurality of electrically connected photovoltaic sections comprising a photovoltaic light absorbing chalcopyrite semiconductor region (“PLACS region”) disposed between first and second electrode regions. The photovoltaic sections can each comprise a scribe channel extending along and into two of the regions, wherein the scribe channel can comprise a pair of spaced opposing sidewalls of one of the regions, a pair of terraces comprising a pair of spaced opposing terrace shoulders, and a second pair of spaced opposing sidewalls of another one of the regions, with the spacing of the second pair of sidewalls being different than the spacing of the first pair of sidewalls. The spacing of the second pair of sidewalls can be less than the spacing of the first pair of sidewalls, and another one of the regions comprises the PLACS region. |
| US09306090B2 |
Composite particle, composite particle dispersion, and photovoltaic device,
A composite particle including a core member including a rare earth ion which shows an upconversion effect and a retaining material which retains the rare earth ion, and a semiconductor member covering a part or all of the surface of the core member, wherein the retaining material includes a semiconductor material having a band gap greater than energy difference necessary for a second step excitation in the rare earth ion to occur, or an insulating material, and the semiconductor member includes a semiconductor material having a band gap smaller than the energy difference between a first excited state and a ground state of the rare earth ion. |
| US09306089B2 |
Solar cell module and solar generator
A solar cell module according to the invention includes a solar cell; a light guiding portion including a first fluorescent substance having a faint color and that emits light having low luminosity factor, the light guiding portion absorbing part of light incident from the outside using the first fluorescent substance and transmitting a first light beam emitted from the first fluorescent substance toward the solar cell; and a converter disposed between the light guiding portion and the solar cell, the converter converting the first light beam incident from the light guiding portion into a second light beam to which the solar cell has higher spectral sensitivity than to the first light beam and causing the second light beam to be incident on the solar cell. Thus, when the solar cell module is used as a window, the solar cell module is highly transparent and highly efficiently generates power. |
| US09306088B1 |
Method for manufacturing back contact solar cells
A method for manufacturing back contact solar cells, comprising steps of: (a) providing a silicon substrate doped with phosphorus; (b) doping the front surface and the rear surface of the substrate homogeneously with boron in a blanket pattern, thereby forming a front side p+ region on the front surface and a rear side p+ region on the rear surface; (c) forming a silicon dioxide layer on the front surface and the rear surface; (d) depositing a phosphorus-containing doping paste on the silicon dioxide layer of the rear surface in a second pattern; (e) heating the silicon substrate in order to locally diffuse phosphorus into the rear surface of the silicon substrate, thereby forming a rear side n+ region on the rear surface of the silicon substrate beneath the phosphorus-containing doping paste; and (f) removing the silicon dioxide layer from the silicon substrate. |
| US09306087B2 |
Method for manufacturing a photovoltaic cell with a locally diffused rear side
A method for manufacturing a photovoltaic cell with a locally diffused rear side, comprising steps of: (a) providing a doped silicon substrate, the substrate comprising a front, sunward facing, surface and a rear surface; (b) forming a silicon dioxide layer on the front surface and the rear surface; (c) depositing a boron-containing doping paste on the rear surface in a pattern, the boron-containing paste comprising a boron compound and a solvent; (d) depositing a phosphorus-containing doping paste on the rear surface in a pattern, the phosphorus-containing doping paste comprising a phosphorus compound and a solvent; (e) heating the silicon substrate in an ambient to a first temperature and for a first time period in order to locally diffuse boron and phosphorus into the rear surface of the silicon substrate. |
| US09306079B2 |
Semiconductor device and method for manufacturing the same
A semiconductor device formed using an oxide semiconductor layer and having small electrical characteristic variation is provided. A highly reliable semiconductor device including an oxide semiconductor layer and exhibiting stable electric characteristics is provided. Further, a method for manufacturing the semiconductor device is provided. In the semiconductor device, an oxide semiconductor layer is used for a channel formation region, a multilayer film which includes an oxide layer in which the oxide semiconductor layer is wrapped is provided, and an edge of the multilayer film has a curvature in a cross section. |
| US09306078B2 |
Stable amorphous metal oxide semiconductor
A thin film semiconductor device has a semiconductor layer including a mixture of an amorphous semiconductor ionic metal oxide and an amorphous insulating covalent metal oxide. A pair of terminals is positioned in communication with the semiconductor layer and define a conductive channel, and a gate terminal is positioned in communication with the conductive channel and further positioned to control conduction of the channel. The invention further includes a method of depositing the mixture including using nitrogen during the deposition process to control the carrier concentration in the resulting semiconductor layer. |
| US09306076B2 |
Semiconductor device and method for manufacturing the same
A semiconductor device in which fluctuation in electric characteristics due to miniaturization is less likely to be caused is provided. The semiconductor device includes an oxide semiconductor film including a first region, a pair of second regions in contact with side surfaces of the first region, and a pair of third regions in contact with side surfaces of the pair of second regions; a gate insulating film provided over the oxide semiconductor film; and a first electrode that is over the gate insulating film and overlaps with the first region. The first region is a CAAC oxide semiconductor region. The pair of second regions and the pair of third regions are each an amorphous oxide semiconductor region containing a dopant. The dopant concentration of the pair of third regions is higher than the dopant concentration of the pair of second regions. |
| US09306073B2 |
Semiconductor device and method for manufacturing semiconductor device
Disclosed is a semiconductor device including an insulating layer, a source electrode and a drain electrode embedded in the insulating layer, an oxide semiconductor layer in contact with the insulating layer, the source electrode, and the drain electrode, a gate insulating layer covering the oxide semiconductor layer, and a gate electrode over the gate insulating layer. The upper surface of the surface of the insulating layer, which is in contact with the oxide semiconductor layer, has a root-mean-square (RMS) roughness of 1 nm or less. There is a difference in height between an upper surface of the insulating layer and each of an upper surface of the source electrode and an upper surface of the drain electrode. The difference in height is preferably 5 nm or more. This structure contributes to the suppression of defects of the semiconductor device and enables their miniaturization. |
| US09306070B2 |
Semiconductor device and method of fabricating the same
A semiconductor device includes: active fins protruding from an active layer and extending in a first direction; a gate structure on the active fins extending in a second direction intersecting the first direction; and a spacer on at least one side of the gate structure, wherein each of the active fins includes a first region and a second region adjacent to the first direction in the first direction, and a width of the first region in the second direction is different from a width of the second region in the second direction. |
| US09306061B2 |
Field effect transistor devices with protective regions
A transistor device includes a first conductivity type drift layer, a second conductivity type first region in the drift layer, a body layer having the second conductivity type on the drift layer including the first region, a source layer on the body layer, and a body contact region that extends through the source layer and the body layer and into the first region. The transistor device further includes a trench through the source layer and the body layer and extending into the drift layer adjacent the first region. The trench has an inner sidewall facing away from the first region. A gate insulator is on the inner sidewall of the trench, and a gate contact is on the gate insulator. |
| US09306056B2 |
Semiconductor device with trench-like feed-throughs
A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated. |
| US09306052B2 |
Compound semiconductor device and method of manufacturing the same
A compound semiconductor device includes: an electron transit layer; an electron supply layer over the electron transit layer; a gate electrode, a source electrode and a drain electrode at a level above the electron supply layer; and a porous electrical insulating film that covers the gate electrode, the source electrode and the drain electrode, the porous electrical insulating film containing an organic constituent, and a cavity being formed around the gate electrode in the porous electrical insulating film. A cross-linking layer is on a surface of the porous electrical insulating film at the cavity side. |
| US09306043B2 |
Bipolar junction transistor and operating and manufacturing method for the same
A bipolar junction transistor and an operating method and a manufacturing method for the same are provided. The bipolar junction transistor comprises a first doped region, a second doped region and a third doped region. The first doped region has a first type conductivity. The second doped region comprises well regions formed in the first doped region, having a second type conductivity opposite to the first type conductivity, and separated from each other by the first doped region. The third doped region has the first type conductivity. The third doped region is formed in the well regions or in the first doped region between the well regions. |
| US09306040B2 |
Nonvolatile memory device and method for fabricating the same
A nonvolatile memory device includes a substrate comprising a first word line formation area, a second word line formation area, and a support area interposed between the first and second word line formation areas; a first stacked structure disposed over the substrate of each of the first and second word line formation areas and having a plurality of interlayer dielectric layers and a plurality of conductive layers that are alternately stacked therein; a second stacked structure disposed over the substrate of the support area and having the plurality of interlayer dielectric layers and a plurality of spaces that are alternately stacked therein; a channel layer disposed in the first stacked structure; and a memory layer interposed between the channel layer and each of the plurality of conductive layers. |
| US09306039B2 |
Method of making split-gate memory cell with substrate stressor region
A memory device, and method of make same, having a substrate of semiconductor material of a first conductivity type, first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween, a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed at least partially over the first region and a first portion of the channel region, a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed at least partially over and insulated from a second portion of the channel region, and a stressor region of embedded silicon carbide formed in the substrate underneath the second gate. |
| US09306034B2 |
Method and apparatus for power device with multiple doped regions
A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type. |
| US09306032B2 |
Method of forming self-aligned metal gate structure in a replacement gate process using tapered interlayer dielectric
A method for manufacturing a semiconductor device includes following steps. A substrate having at least a transistor embedded in an insulating material formed thereon is provided. The transistor includes a metal gate. Next, an etching process is performed to remove a portion of the metal gate to form a recess and to remove a portion of the insulating material to form a tapered part. After forming the recess and the tapered part of the insulating material, a hard mask layer is formed on the substrate to fill up the recess. Subsequently, the hard mask layer is planarized. |
| US09306030B2 |
Semiconductor device and method of manufacturing the same
A semiconductor device includes a semiconductor layer formed on a substrate, an electrode contact window that includes a recess formed on a surface of the semiconductor layer, an inner wall having a slope, and a source electrode, a drain electrode, and a gate electrode formed on the semiconductor layer, in which the drain electrode is in contact with the slope of the inner wall. |
| US09306027B2 |
Semiconductor device and a method for manufacturing a semiconductor device
The characteristics of a semiconductor device are improved. A semiconductor device is formed so as to have a channel layer formed over a substrate, a barrier layer, a trench penetrating through the barrier layer in an opening region, and reaching some point of the channel layer, a gate electrode arranged in the trench via a gate insulation film, and an insulation film formed over the barrier layer outside the opening region. Then, the insulation film has a lamination structure of a Si-rich silicon nitride film, and a N-rich silicon nitride film situated thereunder. Thus, the upper layer of the insulation film is set as the Si-rich silicon nitride film. This enables the improvement of the breakdown voltage, and further, enables the improvement of the etching resistance. Whereas, the lower layer of the insulation film is set as the N-rich silicon nitride film. This can suppress collapse. |
| US09306026B2 |
Semiconductor structure having aluminum oxynitride film on germanium layer and method of fabricating the same
A semiconductor structure includes: a germanium layer 30; and an aluminum oxynitride film 32 that is formed on the germanium layer, wherein: an EOT of the aluminum oxynitride film is 2 nm or less; Cit/Cacc is 0.4 or less; on a presumption that Au acting as a metal film is formed on the aluminum oxynitride film, the Cit is a capacitance value between the germanium layer and the metal film at a frequency of 1 MHz in a case where a voltage of the metal film with respect to the germanium layer is applied to an inversion region side by 0.5 V; and the Cacc is a capacitance value between the germanium layer and the metal film in an accumulation region. |
| US09306015B2 |
Semiconductor device having planar source electrode
A semiconductor device includes a channel layer on a substrate; cell trench patterns in the channel layer; and a source pattern on the cell trench patterns. The source pattern includes: grooves, each having inclined sidewalls and bottom that extends in a horizontal direction in a portion of the channel layer between the cell trench patterns, source regions at the inclined sidewalls of the grooves, source isolation regions at the bottoms of the grooves, and a source electrode at interior regions of the grooves and that has a planar upper surface. |
| US09306013B2 |
Method of forming a gate shield in an ED-CMOS transistor and a base of a bipolar transistor using BICMOS technologies
A method of fabricating a MOSFET transistor in a SiGe BICMOS technology and resulting structure having a drain-gate feedback capacitance shield formed between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since the shield is composed of bipolar base material commonly used in SiGe BICMOS technologies. |
| US09306012B2 |
Strip-ground field plate
Among other things, one or more semiconductor devices and techniques for forming such semiconductor devices are provided. The semiconductor device comprises a strip-ground field plate. The strip-ground field plate is connected to a source region of the semiconductor device and/or a ground plane. The strip-ground field plate provides a release path for a gate edge electric field. The release path directs an electrical field away from a gate region of the semiconductor device. In this way, breakdown voltage and gate charge are improved. |
| US09306011B2 |
Semiconductor device having areas with different conductivity types and different doping concentrations
A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes a plurality of first doping regions of a first doping structure arranged at a main surface of the semiconductor substrate and a plurality of second doping regions of the first doping structure arranged at the main surface of the semiconductor substrate. The first doping regions of the plurality of first doping regions of the first doping structure include dopants of a first conductivity type with different doping concentrations. Further, the second doping regions of the plurality of second doping regions of the first doping structure include dopants of a second conductivity type with different doping concentrations. At least one first doping region of the plurality of first doping regions of the first doping structure partly overlaps at least one second doping region of the plurality of second doping regions of the first doping structure causing an overlap region arranged at the main surface. |
| US09306008B2 |
Semiconductor device and method of fabricating the same
The present disclosure relates to a semiconductor device including an oxygen gettering layer between a group III-V compound semiconductor layer and a dielectric layer, and a method of fabricating the semiconductor device. The semiconductor device may include a compound semiconductor layer; a dielectric layer disposed on the compound semiconductor layer; and an oxygen gettering layer interposed between the compound semiconductor layer and the dielectric layer. The oxygen gettering layer includes a material having a higher oxygen affinity than a material of the compound semiconductor layer. |
| US09306006B2 |
Silicon carbide semiconductor device
There is provided a silicon carbide semiconductor device allowing for suppression of breakage of an element upon short circuit of load. A MOSFET includes a silicon carbide layer, a gate insulating film, a gate electrode, a source electrode, and a drain electrode. The silicon carbide layer includes a drift region, a body region, and a source region. The MOSFET is configured such that a relational expression of n<−0.02RonA+0.7 is established in a case where a contact width of the source region and the source electrode is represented by n (μm) in a cross section in a thickness direction of the silicon carbide layer and a migration direction of carriers in the body region and where on resistance of the MOSFET in a state in which an inversion layer is formed in a channel region is represented by RonA (mΩcm2). |
| US09306005B2 |
Electronic device including graphene
According to example embodiments, an electronic device includes: a semiconductor layer; a graphene directly contacting a desired (and/or alternatively predetermined) area of the semiconductor layer; and a metal layer on the graphene. The desired (and/or alternatively predetermined) area of the semiconductor layer include one of: a constant doping density, a doping density that is equal to or less than 1019 cm−3, and a depletion width of less than or equal to 3 nm. |
| US09306002B2 |
Semiconductor device
A semiconductor device is disclosed. The semiconductor device includes a semiconductor layer of a first conductivity type; an element isolation well of a second conductivity type, which is formed on a surface of the semiconductor layer and isolates an element formation region; a field insulating film configured to cover a surface of the element isolation well; an interlayer insulating film formed on the semiconductor layer; a wiring formed on the interlayer insulating film; and a conductive film formed on the wiring and the field insulating film, a voltage potential of the conductive film being fixed to be a specified voltage potential. |
| US09306000B2 |
Semiconductor device, method of manufacturing the same, and power module
A semiconductor device includes an n-type drain layer, an n-type base layer provided on the n-type drain layer, a p-type base layer and an n-type source layer partially formed in surface layer portions of the n-type base layer and the p-type base layer, respectively, a gate insulation film formed on a surface of the p-type base layer between the n-type source layer and the n-type base layer, a gate electrode formed on the gate insulation film facing the p-type base layer across the gate insulation film, a p-type column layer formed within the n-type base layer to extend from the p-type base layer toward the n-type drain layer, a depletion layer alleviation region arranged between the p-type column layer and the n-type drain layer and including first baryons converted to donors, a source electrode connected to the n-type source layer, and a drain electrode connected to the n-type drain layer. |
| US09305996B2 |
Semiconductor device
After the formation of a first interlayer insulating, an etching stopper film made of SiON is formed thereon. Subsequently, a contact hole extending from the upper surface of the etching stopper film and reaching a high concentration impurity region is formed, and a first plug is formed by filling W into the contact hole. Next, a ferroelectric capacitor, a second interlayer insulating film, and the like are formed. Thereafter, a contact hole extending from the upper surface of the interlayer insulating film and reaching the first plug is formed. Then, the contact hole is filled with W to form a second plug. With this, even when misalignment occurs, the interlayer insulating film is prevented from being etched. |
| US09305990B2 |
Chip-on-film package and device assembly including the same
Provided are a chip-on-film (COF) package and a device assembly including the same. The device assembly includes a COF package including a film substrate on which a plurality of film-through wires are formed. The device assembly includes a panel unit including a panel substrate on which a plurality of panel-through wires are formed. The panel unit is disposed on the COF package. One end of the panel unit is electrically connected to a first end of the COF package. The device assembly includes a control unit disposed below the panel unit. One end of the control unit is electrically connected to a second end of the COF package. |
| US09305988B2 |
Light-emitting device
In a light-emitting device, supply of current is controlled using a transistor having a normal gate electrode (a first gate electrode) and a second gate electrode for controlling threshold voltage. The light-emitting device comprises one or more switches for selecting conduction or non-conduction between the first gate electrode and a drain terminal of the transistor. When the threshold voltage of the transistor is acquired, the first gate electrode and the drain terminal of the transistor are brought into conduction with the switch, and the threshold voltage of the transistor is shifted by controlling the potential of the second gate electrode. |
| US09305977B1 |
Resistive random access memory and method for manufacturing the same
A resistive random access memory including a substrate, a dielectric layer disposed on the substrate and at least one memory cell string is provided. The memory cell string includes memory cells and second vias. The memory cells are vertically and adjacently disposed in the dielectric layer, and each of the memory cells includes a first via, two conductive lines respectively disposed at two sides of the first via and two variable resistance structures respectively disposed between the first via and the conductive lines. In the vertically adjacent two memory cells, the variable resistance structures of the upper memory cell and the variable resistance structures of the lower memory cell are isolated from each other. The second vias are respectively disposed in the dielectric layer under the first vias and connected to the first vias, and the vertically adjacent two first vias are connected by the second via. |
| US09305974B1 |
High density resistive random access memory (RRAM)
A resistive random access memory (RRAM) structure is formed on a supporting substrate and includes a first electrode and a second electrode. The first electrode is made of a silicided fin on the supporting substrate and a first metal liner layer covering the silicided fin. A layer of dielectric material having a configurable resistive property covers at least a portion of the first metal liner. The second electrode is made of a second metal liner layer covering the layer of dielectric material and a metal fill in contact with the second metal liner layer. A non-volatile memory cell includes the RRAM structure electrically connected between an access transistor and a bit line. |
| US09305973B2 |
One-time programmable memories using polysilicon diodes as program selectors
Polysilicon diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, using electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse etc. as OTP element The diode can be constructed by P+/N+ implants on a polysilicon as a program selector. The OTP device can have an OTP element coupled to a polysilicon diode. The OTP devices can be used to construct a two-dimensional OTP memory with the N-terminals of the diodes in a row connected as a wordline and the OTP elements in a column connected as a bitline. |
| US09305969B2 |
Solid-state imaging device operable with two readout modes in two different directions coincident with a moving speed and a moving direction of a moving subject
A solid-state imaging device 1A includes a CCD-type solid-state imaging element 10 having an imaging plane 12 formed of M×N pixels that are two-dimensionally arrayed in M rows and N columns, N signal readout circuits 20 arranged on one end side in the column direction for each of the columns with respect to the imaging plane 12, and N signal readout circuits 30 arranged on the other end side in the column direction for each of the columns with respect to the imaging plane 12, a semiconductor element 50 for digital-converting and then sequentially outputting as serial signals electrical signals output from the signal readout circuits 20 for each of the columns, and a semiconductor element 60 for digital-converting and then sequentially outputting as serial signals electrical signals output from the signal readout circuits 30 for each of the columns. |
| US09305967B1 |
Wafer Level optoelectronic device packages and methods for making the same
Described herein are methods for fabricating a plurality of optoelectronic devices, and the optoelectronic devices resulting from such methods. One such method includes performing through silicon via (TSV) processing on a wafer, which includes a plurality of light detector sensor regions, to thereby form a plurality of vias, and then tenting and plating the vias and performing wafer back metallization. Thereafter, plurality of light source dies are attached to a top surface of the wafer, and a light transmissive material is then molded to encapsulate the light detector sensor regions and the light sensor dies therein. Additionally, opaque barriers including opaque optical crosstalk barriers are fabricated. Further, solder balls or other electrical connectors are attached to the bottom of the wafer. The wafer is eventually diced to separate the wafer into a plurality of optoelectronic devices. |
| US09305966B2 |
Backside structure and method for BSI image sensors
BSI image sensors and methods. In an embodiment, a substrate is provided having a sensor array and a periphery region and having a front side and a back side surface; a bottom anti-reflective coating (BARC) is formed over the back side to a first thickness, over the sensor array region and the periphery region; forming a first dielectric layer over the BARC; a metal shield is formed; selectively removing the metal shield from over the sensor array region; selectively removing the first dielectric layer from over the sensor array region, wherein a portion of the first thickness of the BARC is also removed and a remainder of the first thickness of the BARC remains during the process of selectively removing the first dielectric layer; forming a second dielectric layer over the remainder of the BARC and over the metal shield; and forming a passivation layer over the second dielectric layer. |
| US09305959B2 |
Biometric sensor chip having distributed sensor and control circuitry
A sensor includes a sensor array formed on a first side of a substrate and at least one circuit operative to communicate with the sensor array formed on a second side of the substrate. At least one via extends through the substrate to electrically connect the sensor array to the at least one circuit. Placing the at least one circuit on the second side of the substrate allows the sensor array to occupy substantially all of the first side of the substrate. |
| US09305955B2 |
Method for manufacturing solid-state imaging device, and solid-state imaging device
Certain embodiments provide a method for manufacturing a solid-state imaging device, including thinning a semiconductor substrate, forming a plurality of masking patterns, and forming a groove having inclined surfaces that are inclined relative to a front surface of the semiconductor substrate at a back surface of the semiconductor substrate. A plurality of light receiving sections are provided in a lattice pattern at the front surface of the semiconductor substrate to be thinned. A wiring layer including metal wirings is provided on the front surface of the semiconductor substrate to be thinned. The plurality of masking patterns are arranged in a lattice pattern on the back surface of the thinned semiconductor substrate. The groove is formed by etching the semiconductor substrate between the masking patterns using an etchant having an anisotropic etching property. |
| US09305953B2 |
Imaging device and imaging system
An imaging device includes a light-sensing pixel region; a first pixel region; a second pixel region; a first wiring layer disposed above the light-sensing pixel region; and a second wiring layer disposed above the topmost wiring layer of the wiring layer disposed above the light-sensing pixel region, above the second pixel region. The first pixel region is disposed between the light-sensing pixel region and the second pixel region, adjacent to the light-sensing pixel region and the second pixel region, wherein the first pixel region overlaps, in plan view, a first shielding portion included in the first wiring layer. The second pixel region overlaps, in plan view, a second shielding portion included in the second wiring layer. An electroconductive pattern is formed at the first wiring layer at a position overlapping the second pixel region in plan view. |
| US09305952B2 |
Image sensors with inter-pixel light blocking structures
An image sensor with an array of image sensor pixels is provided. Each pixel may include a photodiode and associated pixel circuits formed in a semiconductor substrate. Buried light shields may be formed on the substrate to present pixel circuitry that is formed in the substrate between two adjacent photodiodes from being exposed to incoming light. Metal interconnect muting structures may be formed over the buried light shields. In one embodiment, light blocking structures may be formed to completely seal the interconnect routing structures. The light blocking structures may be formed on top of the buried light shields or on the surface of the substrate. In another embodiment, planar light blocking structures that are parallel to the surface of the substrate may be formed between metal routing layers to help absorb stray light. Light blocking structures formed in these ways can help reduce optical crosstalk and enhance global shutter efficiency. |
| US09305948B2 |
Dynamic polarizer having material operable to alter its conductivity responsive to an applied stimulus
A dynamically controllable polarizer integrated with an imaging detector to provide “on demand” variable polarization measurements. In one example, an imaging system includes a detector array including a plurality of pixels arranged in a two-dimensional array, and a dynamic polarizer coupled to the detector array, the dynamic polarizer including at least one patterned layer of a material disposed on the detector array, the material being operable to alter its conductivity responsive to an applied stimulus to reversibly transition between a polarizing state and a non-polarizing state. |
| US09305947B2 |
Image sensors having deep trenches including negative charge material
Image sensors are provided including a substrate defining a plurality of pixel regions, the substrate having a first surface and a second surface opposite the first surface. The second surface of the substrate is configured to receive light incident thereon and the substrate defines a deep trench extending from the second surface of the substrate toward the first surface substrate and separating the plurality of pixel regions from each other. In each of the plurality of pixel regions of the substrate, a photoelectric conversion region is provided. A gate electrode is provided on the photoelectric conversion region and a negative fixed charge layer covering the second surface of the substrate and at least a portion of a sidewall of the deep trench is also provided. The image sensors further include a shallow device isolation layer on the first surface of the substrate. The shallow device isolation layer defines an active region in each of the pixel regions and the negative fixed charge layer contacts the shallow device isolation layer. |
| US09305946B2 |
Photoelectric conversion apparatus that maintains image quality and image pickup system
A photoelectric conversion apparatus includes a plurality of pixels arranged in a matrix, a plurality of signal processing units each corresponding to a column of the matrix, and a signal line. Each of the plurality of signal processing units includes a first capacitance and a second capacitance that hold a signal, a switch provided between the signal line and the first capacitance, a capacitance adjustment unit electrically connected to the second capacitance, and a connection unit configured to electrically connect the first capacitance provided to one of signal processing units to the second capacitance provided to another one of the signal processing units. |
| US09305943B2 |
Array substrate and repairing method thereof and display device
An array substrate, a repairing method thereof and a display device, wherein the array substrate includes: a plurality of gate lines and a plurality of data lines provided in a display region, gate lead lines provided in a non-display region and respectively connected to the gate lines and a gate driver IC, and data lead lines provided in the non-display region and respectively connected to the data lines and a data driver IC. The array substrate further includes: at least one first repairing line provided in a same layer as the gate lead lines, and at a position corresponding to a data lead line; and/or, at least one second repairing line provided in a same layer as the data lead lines, and at a position corresponding to a gate lead line. |
| US09305942B2 |
TFT array substrate having metal oxide part and method for manufacturing the same and display device
Embodiments of the present invention provide a TFT array substrate and a method for manufacturing the same and a display device. The TFT array substrate comprises: a base substrate; gate lines, gate electrodes, a gate insulating layer and a semiconductor active layer formed on the base substrate; a metal barrier layer formed on the semiconductor active layer, the metal barrier layer covering the semiconductor active layer; source electrodes and drain electrodes formed on the metal barrier layer, with a metal oxide part being formed between the source electrode and the drain electrode to insulate the source electrode and the drain electrode from each other; and a protection layer formed on the gate insulating layer and the source and drain electrodes, wherein the metal oxide part is formed by oxidizing a part of the metal barrier layer located between the source electrode and the drain electrode. |
| US09305940B2 |
Thin film transistor having an active pattern and a source metal pattern with taper angles
A thin film transistor includes a gate electrode, an active pattern overlapping with the gate electrode and including a semiconductive oxide, and a source metal pattern disposed on the active pattern and including a source electrode and a drain electrode spaced apart from the source electrode. The active pattern underlaps an entire portion of a lower surface of the source metal pattern and minimally protrudes beyond lateral ends of the source metal pattern due to the active pattern having sidewall taper angles that are substantially greater than corresponding and adjacent sidewall taper angles of the overlying source metal pattern. Thus parasitic capacitance may be reduced and performance enhanced. |
| US09305938B2 |
Methods of fabricating integrated structures, and methods of forming vertically-stacked memory cells
Some embodiments include a method of fabricating integrated structures. A metal-containing material is formed over a stack of alternating first and second levels. An opening is formed through the metal-containing material and the stack. Repeating vertically-stacked electrical components are formed along the stack at sidewalls of the opening. Some embodiments include a method of forming vertically-stacked memory cells. Metal-containing material is formed over a stack of alternating silicon dioxide levels and conductively-doped silicon levels. A first opening is formed through the metal-containing material and the stack. Cavities are formed to extend into the conductively-doped silicon levels along sidewalls of the first opening. Charge-blocking dielectric and charge-storage structures are formed within the cavities to leave a second opening. Sidewalls of the second opening are lined with gate dielectric and then channel material is formed within the second opening. |
| US09305937B1 |
Bottom recess process for an outer blocking dielectric layer inside a memory opening
A method of minimizing an overetch or damage to a semiconductor surface underneath a memory opening is provided. A first blocking dielectric layer is formed in a memory opening through a stack of an alternating plurality of material layers and insulator layers. A sacrificial liner is formed over the first blocking dielectric layer. An opening is formed through a horizontal portion of the sacrificial liner. A horizontal portion of the first blocking dielectric layer at a bottom of the memory opening can be etched through the opening in the sacrificial liner. A semiconductor surface of the substrate can be physically exposed at a bottom of the memory opening with minimal overetch and/or surface damage. A second blocking dielectric layer can be formed, before or after formation of the sacrificial liner, to provide a multilayer blocking dielectric. |
| US09305936B2 |
Nonvolatile semiconductor memory device and method of manufacturing the same
According to one embodiment, a nonvolatile semiconductor memory device includes a stacked layer structure including first to n-th semiconductor layers (n is a natural number equal to or larger than 2) stacked in a first direction which is perpendicular to a surface of a semiconductor substrate, and an upper insulating layer stacked on the n-th semiconductor layer, the stacked layer structure extending in a second direction which is parallel to the surface of the semiconductor substrate, and first to n-th NAND strings provided on surfaces of the first to n-th semiconductor layers in a third direction which is perpendicular to the first and second directions respectively. |
| US09305934B1 |
Vertical NAND device containing peripheral devices on epitaxial semiconductor pedestal
A multilevel structure includes a stack of an alternating plurality of electrically conductive layers and insulator layers located over a semiconductor substrate, and an array of memory stack structures located within memory openings through the stack. An epitaxial semiconductor pedestal is provided, which is in epitaxial alignment with a single crystalline substrate semiconductor material in the semiconductor substrate and has a top surface within a horizontal plane located above a plurality of electrically conductive layers within the stack. The contact via structures for the semiconductor devices on the epitaxial semiconductor pedestal can extend can be less than the thickness of the stack. |
| US09305932B2 |
Methods of making three dimensional NAND devices
A method of making a monolithic three dimensional NAND string includes providing a first stack of alternating first material layers and second material layers over a major surface of a substrate. The first material layers include first silicon oxide layers, the second material layers include second silicon oxide layers, and the first silicon oxide layers have a different etch rate from the second silicon oxide when exposed to the same etching medium. The first stack includes a back side opening, a front side opening, and at least a portion of a floating gate layer, a tunnel dielectric and a semiconductor channel located in the front side opening. The method also includes selectively removing the first material layers through the back side opening to form back side control gate recesses between adjacent second material layers. |
| US09305928B2 |
Semiconductor devices having a silicon-germanium channel layer and methods of forming the same
Semiconductor devices having a silicon-germanium channel layer and methods of forming the semiconductor devices are provided. The methods may include forming a silicon-germanium channel layer on a substrate in a peripheral circuit region and sequentially forming a first insulating layer and a second insulating layer on the silicon-germanium channel layer. The methods may also include forming a conductive layer on the substrate, which includes a cell array region and the peripheral circuit region, and patterning the conductive layer to form a conductive line in the cell array region and a gate electrode in the peripheral circuit region. The first insulating layer may be formed at a first temperature and the second insulating layer may be formed at a second temperature higher than the first temperature. |
| US09305927B2 |
Semiconductor device and method of manufacturing the same
A semiconductor device having a buried gate is provided. The semiconductor device is formed in a structure in which a plurality of contacts having small step differences are stacked without forming a metal contact applying an operation voltage to the buried gate in a single contact and a contact pad is formed between the contacts so that failure due to misalignment can be prevented without a separate additional process for forming the contacts. |
| US09305925B2 |
Semiconductor integrated circuit device and manufacturing method thereof
In order to achieve high-speed operation of an eDRAM, the eDRAM includes: a selection MISFET having a gate electrode that serves as a word line, a source region, and a drain region; a source plug electrode coupled to the source region; and a drain plug electrode coupled to the drain region DR1. The eDRAM further includes: a capacitive plug electrode coupled to the drain plug electrode; a bit line coupled to the source plug electrode; a stopper film covering the bit line; and a capacitive element that is formed over the stopper film and has a first electrode, a dielectric film, and a second electrode. The first electrode is coupled to the capacitive plug electrode, and the height of the capacitive plug electrode and that of the bit line are equal to each other. |
| US09305922B2 |
Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device comprises forming an interlayer insulating film on a semiconductor substrate, the interlayer insulating film including a trench, forming a work function metal layer in the trench, forming an insulating film on the work function metal layer, forming a sacrificial film on the insulating film and filling the trench, forming a sacrificial film pattern with a top surface disposed in the trench by etching the sacrificial film, forming an insulating film pattern by selectively etching a portion of the insulating film which is formed higher than the sacrificial film pattern, and forming a work function metal pattern with a top surface disposed in the trench by selectively etching a portion of the work function metal layer which is formed higher than the insulating film pattern. |
| US09305918B2 |
Method for FinFET integrated with capacitor
The present disclosure provides methods to fabricate a semiconductor structure that includes a semiconductor substrate having a first region and a second region; a shallow trench isolation (STI) feature formed in the semiconductor substrate. The STI feature includes a first portion disposed in the first region and having a first thickness T1 and a second portion disposed in the second region and having a second thickness T2 greater than the first depth, the first portion of the STI feature being recessed from the second portion of the STI feature. The semiconductor structure also includes a plurality of fin active regions on the semiconductor substrate; and a plurality of conductive features disposed on the fin active regions and the STI feature, wherein one of the conductive features covers the first portion of the STI feature in the first region. |
| US09305916B1 |
ESD power clamp for silicon-on-insulator (SOI) and FinFET processes lacking parasitic ESD diode
An Electro-Static-Discharge (ESD) protection circuit uses Silicon-On-Insulator (SOI) transistors with buried oxide but no parasitic substrate diode useable for ESD protection. A filter voltage is generated by a resistor and capacitor. When a VDD-to-VSS ESD positive pulse occurs, the filter voltage passes through an n-channel pass transistor and inverted to drive a gate of a big SOI transistor that shunts ESD current. A second path is used for a VSS-to-VDD ESD positive pulse. The filter voltage passes through a p-channel pass transistor to the gate when the positive ESD pulse is applied to VSS. The big SOI transistor can connect between VDD and VSS for a power clamp, and the gates of the n-channel and p-channel pass transistors connect to VDD. A small diode may be added between VDD and VSS to generate a small triggering current to activate grounded-gate transistors near I/O pads for full-chip Pad-based ESD protection. |
| US09305914B2 |
High-voltage transistor, ESD-protection circuit, and use of a high-voltage transistor in an ESD-protection circuit
In the high-voltage transistor, which is suitable for an ESD-protection circuit, there is no doped well or at most a portion of a second well (3) of a second conductivity type opposite a first conductivity type under a contact region (4) for the drain between a first well (2) and a semiconductor material of the substrate (1), said semiconductor material being undoped or being doped for the first conductivity type. Said portion has a lower thickness than a thickness which would provide a good insulation of the first well from the substrate and which would provide a high-breakdown voltage. |
| US09305912B2 |
Stack package and method for manufacturing the same
A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern. |
| US09305910B2 |
Semiconductor device
A semiconductor device includes an insulating substrate having a first conductive pattern on a first insulating substrate; a first semiconductor element having one surface fixed to the first conductive pattern; a printed circuit board having a conductive layer on a second insulating substrate and a plurality of metal pins fixed to the conductive layer; and a third insulating substrate. A portion of pins constituting the metal pins is fixed to other surface of the first semiconductor element, and the printed circuit board with the metal pins is sandwiched between the insulating substrate having the first conductive pattern and the third insulating substrate. |
| US09305906B2 |
Semiconductor light emitting device
In a semiconductor light emitting device, a light emitting structure includes a first-conductivity type semiconductor layer, an active layer, and a second-conductivity type semiconductor layer, which are sequentially formed on a conductive substrate. A second-conductivity type electrode includes a conductive via and an electrical connection part. The conductive via passes through the first-conductivity type semiconductor layer and the active layer, and is connected to the inside of the second-conductivity type semiconductor layer. The electrical connection part extends from the conductive via and is exposed to the outside of the light emitting structure. An insulator electrically separates the second-conductivity type electrode from the conductive substrate, the first-conductivity type semiconductor layer, and the active layer. A passivation layer is formed to cover at least a side surface of the active layer in the light emitting structure. An uneven structure is formed on a path of light emitted from the active layer. |
| US09305902B1 |
Chip package and method for forming the same
A semiconductor device includes a plurality of conductors for connecting another semiconductor device. Each conductor connects to a chip select pad within the semiconductor device through an upper vertical connection formed through an insulation layer formed on a substrate or connected to a straight vertical connection formed through the substrate and the insulation layer. The semiconductor device further includes a plurality of lower vertical connections formed through the substrate and correspondingly connecting to the chip select pads and a chip select terminal. The chip select terminal electrically connects to the die circuit of the semiconductor device while the chip select pads are electrically isolated from the die circuit. The lower vertical connections and the straight vertical connection can be arranged in two dimensions. |
| US09305900B2 |
Semiconductor device and memory device
A semiconductor device includes a substrate, a controller chip, and memory chips. Wiring is formed on the substrate. The controller chip has a rectangular surface area, and is mounted on the substrate. The memory chips have quadrangular surface areas, and are superposed on the substrate on a first major side of the controller chip. The first major side defines a first direction and a first controller terminal block is formed along a first minor side thereof orthogonal to the first direction, and a second controller terminal block is formed along a second major side opposite to the first major side. |
| US09305899B2 |
Method of fabricating semiconductor package
A method of fabricating a semiconductor package includes providing a wafer which includes an upper area having through silicon vias (TSVs) and a lower area not having the TSVs; mounting a semiconductor chip on the upper area of the wafer; forming a passivation layer to a predetermined thickness to cover the semiconductor chip; exposing the TSVs by removing the lower area of the wafer in a state where no support is attached to the wafer; and exposing a top surface of the semiconductor chip by partially removing the passivation layer. |
| US09305897B2 |
Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate
A semiconductor device includes a wafer level substrate having a plurality of first conductive vias formed through the wafer level substrate. A first semiconductor die is mounted to the wafer level substrate. A first surface of the first semiconductor die includes contact pads oriented toward a first surface of the wafer level substrate. A first encapsulant is deposited over the first semiconductor die. A second semiconductor die is mounted to the wafer level substrate. A first surface of the second semiconductor die includes contact pads oriented toward a second surface of the wafer level substrate opposite the first surface of the wafer level substrate. A second encapsulant is deposited over the second semiconductor die. A plurality of bumps is formed over the plurality of first conductive vias. A second conductive via can be formed through the first encapsulant and connected to the first conductive via. The semiconductor packages are stackable. |
| US09305895B2 |
Substrates having ball lands, semiconductor packages including the same, and methods of fabricating semiconductor packages including the same
A package substrate includes a core layer having a first surface and a second surface which are opposite to each other, a ball land pad disposed on the first surface of the core layer, an opening that penetrates the core layer to expose the ball land pad, and a dummy ball land disposed on the second surface of the core layer to surround the opening. The dummy ball land includes at least one sub-pattern and at least one vent hole. Related semiconductor packages and related methods are also provided. |
| US09305887B2 |
Seal ring structure with a v-shaped dielectric layer conformally overlapping a conductive layer
A method of forming a seal ring structure includes the following steps. A substrate is provided, and the substrate includes a seal ring region. A metal stack is formed in the seal ring region. A first dielectric layer covering the metal stack is formed. A part of the first dielectric layer is removed to form an opening to expose the metal stack, and at least a side of the opening is not perpendicular to a top surface of the first dielectric layer. A conductive layer is formed to fill the opening. A second dielectric layer is formed to continuously cover the first dielectric layer and the conductive layer, and the second dielectric layer has a v-shaped surface totally overlapping the conductive layer. |
| US09305883B2 |
Locally raised epitaxy for improved contact by local silicon capping during trench silicide processings
A low resistance contact to a finFET source/drain can be achieved by forming a defect free surface on which to form such contact. The fins of a finFET can be exposed to epitaxial growth conditions to increase the bulk of semiconductive material in the source/drain. Facing growth fronts can merge or can form unmerged facets. A dielectric material can fill voids within the source drain region. A trench spaced from the finFET gate can expose the top portion of faceted epitaxial growth on fins within said trench, such top portions separated by a smooth dielectric surface. A silicon layer selectively formed on the top portions exposed within the trench can be converted to a semiconductor-metal layer, connecting such contact with individual fins in the source drain region. |
| US09305878B2 |
Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects
Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a metal contact structure, an electrically conductive capping layer formed on the metal contact structure, and a conductive via electrically connected to the metal contact structure through the electrically conductive capping layer. |
| US09305876B2 |
Device including a semiconductor chip and wires
A device includes a carrier, a first semiconductor chip arranged over the carrier and a first electrically conductive element arranged over the carrier. The device further includes a first wire electrically coupled to the first electrically conductive element and a second wire electrically coupled to the first electrically conductive element and to the first semiconductor chip. The first electrically conductive element is configured to forward an electrical signal between the first wire and the second wire. |
| US09305869B1 |
Packaged semiconductor device having leadframe features as pressure valves against delamination
A packaged semiconductor device (100) comprising a leadframe having a pad (101) with an assembled semiconductor chip (110), a plurality of straps (102) connecting the pad to side edges of the device package, leads (103), and a package (150) of plastic compound adhering to the leadframe; at least one surface (102a) of the straps covered with a layer (120) of a compound both non-adhesive to polymeric compounds and hydrophobic; the compound (220) selected from a group including fluorinated thiol compounds, fluorinated amine compounds, fluorinated aminesilanes, organosilanes, and their derivatives; or the compound (330) selected from a group including open-pore microcellular metal foams and polymer foams. Further, the package may include an array of holes through the plastic compound, extending from the package surface to the strap surface. |
| US09305868B2 |
Manufacturing method of forming an etch-back type semiconductor package with locking anchorages
A semiconductor package, a substrate and a manufacturing method thereof are provided. The substrate comprises a conductive carrier, a first metal layer and a second metal layer. The first metal layer is formed on the conductive carrier and comprises an lead pad having an upper surface. The second metal layer is formed on the first metal layer and comprises a bond pad. The bond pad overlaps and is in contact with the upper surface of the first metal layer. The upper surface of the lead pad is partially exposed. A part of the bond pad overhang outward from the edge of the lead pad. |
| US09305866B2 |
Intermetallic compound filled vias
Electronic devices including intermetallic columns within vias are provided. Vias are filled with one or more pastes containing metal particles. Thermal treatment of the pastes within the vias converts the particles within the pastes to one or more intermetallic compounds that do not melt during next level packaging. |
| US09305864B2 |
Through silicon via (TSV) isolation structures for noise reduction in 3D integrated circuit
Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in 3D integrated circuit packaging. The isolation TSV structures are surrounded by an oxide liner and surrounding dopant impurity regions. The surrounding dopant impurity regions may be P-type dopant impurity regions that are coupled to ground or N-type dopant impurity regions that may advantageously be coupled to VDD. The TSV isolation structure is advantageously disposed between an active, signal carrying TSV and active semiconductor devices and the TSV isolation structures may be formed in an array that isolates an active, signal carrying TSV structure from active semiconductor devices. |
| US09305863B2 |
Semiconductor device
A first dummy via pattern having high density is arranged in the vicinity of first and second wirings on a semiconductor device, and a second dummy via pattern having low density is arranged in a distant region from the first and second wirings, with reference to the first dummy via pattern. Accordingly, it is possible to suppress expansion of the file size of layout CAD data due to dummy vias, while complying with a design standard regulated for each semiconductor process, regardless of the presence or absence of vias which connect the first wirings to the second wirings. |
| US09305862B2 |
Support mounted electrically interconnected die assembly
Stacked die assemblies are electrically connected to connection sites on any support, without electrical connection to any interposed substrate or leadframe, and without solder. |
| US09305855B2 |
Semiconductor package devices including interposer openings for heat transfer member
A semiconductor package device includes a lower package, an interposer disposed on the lower package and including a ground layer and at least one opening, and an upper package on the interposer. The lower package includes a first package substrate, a first semiconductor chip on the first package substrate, and a first molding compound layer on the first package substrate. The upper package includes a second package substrate and at least one upper semiconductor chip on the second package substrate. A heat transfer member includes a first portion disposed between the interposer and the upper package, a second portion disposed in the at least one opening of the interposer, and a third portion disposed between the interposer and the lower package. |
| US09305851B2 |
Systems and methods for chemical mechanical planarization with fluorescence detection
Systems and methods are provided for performing chemical-mechanical planarization on an article. An example system for performing chemical-mechanical planarization on an article includes a polishing head configured to perform a chemical-mechanical planarization (CMP) on an article, a polishing pad configured to support the article, a light source configured to emit an incident light, a polishing fluid including a plurality of emitter particles capable of emitting a fluorescent light in response to the incident light, a fluorescence light detector configured to detect the fluorescent light, and at least one processor configured to control the polishing head based on the detected fluorescent light. |
| US09305850B2 |
Etching method and etching apparatus of semiconductor wafer
A method and an apparatus of etching a semiconductor wafer are provided. The etching apparatus of a semiconductor wafer having a marker inside includes: a monitoring device capable of monitoring a surface of the semiconductor wafer so as to detect the marker; a nozzle capable of jetting a mixed gas that contains hydrogen fluoride and ozone onto the surface of the semiconductor wafer; a regulator capable of adjusting at least one of hydrogen fluoride concentration and ozone concentration in the mixed gas; and a controller capable of determining whether the marker is detected by the monitoring device and terminating the etching process. |
| US09305848B2 |
Elongated contacts using litho-freeze-litho-etch process
A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which connect to two active areas and/or MOS gates and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a contact etch mask. A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which connect to two active areas and/or MOS gates and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a first level interconnect trench etch mask. A process of forming the integrated circuit using a litho-freeze-litho-etch process for a contact etch mask and a litho-freeze-litho-etch process for a first level interconnect trench etch mask. |
| US09305842B2 |
Fabrication methods of chip device packages
A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposing second surface. A spacer is disposed under the second surface of the semiconductor substrate and a cover plate is disposed under the spacer. A recessed portion is formed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the spacer. Then, a protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion. |
| US09305838B2 |
BEOL interconnect with carbon nanotubes
An integrated circuit with BEOL interconnects may comprise: a substrate including a semiconductor device; a first layer of dielectric over the surface of the substrate, the first layer of dielectric including a filled via for making electrical contact to the semiconductor device; and a second layer of dielectric on the first layer of dielectric, the second layer of dielectric including a trench running perpendicular to the longitudinal axis of the filled via, the trench being filled with an interconnect line, the interconnect line comprising cross-linked carbon nanotubes and being physically and electrically connected to the filled via. Cross-linked CNTs are grown on catalyst particles on the bottom of the trench using growth conditions including a partial pressure of precursor gas greater than the transition partial pressure at which carbon nanotube growth transitions from a parallel carbon nanotube growth mode to a cross-linked carbon nanotube growth mode. |
| US09305837B2 |
Semiconductor arrangement and formation thereof
A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a first metal trace having a first metal trace width between about 30 nm to about 60 nm and a first metal trace length. A second metal trace has a second metal trace width between about 10 nm to about 20 nm and a second metal trace length, the first metal trace length different than the second metal trace length. A dielectric layer is between the first metal trace and the second metal trace. The dielectric layer has a dielectric layer width between the first metal trace and the second metal trace between about 10 nm to about 20 nm. The semiconductor arrangement is formed in a manner that allows metal traces having small dimensions to be formed where the metal traces have different dimensions from one another. |
| US09305835B2 |
Formation of air-gap spacer in transistor
Embodiments of present invention provide a method of forming air spacers in a transistor structure. The method includes forming a gate structure of a transistor on top of a semiconductor substrate; forming a first and a second disposable spacers adjacent to a first and a second sidewall of the gate structure; forming a first and a second conductive studs next to the first and the second disposable spacer; removing the first and second disposable spacers to create empty spaces between the first and second conductive studs and the gate structure; and preserving the empty spaces by forming dielectric plugs at a top of the empty spaces. |
| US09305833B2 |
Semiconductor structures and fabrication method thereof
A method is provided for fabricating a semiconductor structure. The method includes providing a substrate; and forming a conductive layer in one surface of the substrate. The method also includes forming a dielectric layer on the surface of the substrate; and forming an opening exposing a portion of the conductive layer in the dielectric layer. Further, the method includes forming a passivation layer for protecting the portion of the conductive layer on a surface of the portion of the conductive layer on the bottom of the opening using a passivation solution; and cleaning inner surface of the opening using a cleaning solution not reacting with the passivation layer. Further, the method also includes removing the passivation layer; and forming a metal layer connecting with the conductive layer in the opening. |
| US09305824B2 |
Method of manufacturing semiconductor integrated circuit device
Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film.The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film. |
| US09305822B2 |
Alignment marks in non-STI isolation formation and methods of forming the same
A method includes forming a photo resist over a semiconductor substrate of a wafer, patterning the photo resist to form a first opening in the photo resist, and implanting the semiconductor substrate using the photo resist as an implantation mask. An implanted region is formed in the semiconductor substrate, wherein the implanted region is overlapped by the first opening. A coating layer is coated over the photo resist, wherein the coating layer includes a first portion in the first opening, and a second portion over the photo resist. A top surface of the first portion is lower than a top surface of the second portion. The coating layer, the photo resist, and the implanted region are etched to form a second opening in the implanted region. |
| US09305818B2 |
Substrate processing apparatus
A substrate processing apparatus, which utilizes a first transfer apparatus and a second transfer apparatus which are configured to transfer a transfer container containing a plurality of substrates, along a first transfer path and a second transfer path whose lateral positions differ from each other, respectively, including a first load port where the transfer container is loaded and unloaded by the first transfer apparatus, and a second load port that is arranged stepwise with respect to the first load port, with the transfer container being loaded to and unloaded from the second load port by the second transfer apparatus. |
| US09305814B2 |
Method of inspecting substrate processing apparatus and storage medium storing inspection program for executing the method
A method of inspecting a substrate processing apparatus, which is capable of preventing product substrates from being supplied to a substrate processing chamber to be inspected, and inspecting the substrate processing chamber in desired timing. Product wafers W (product substrates) are inhibited from being conveyed into a processing unit to be inspected (substrate processing chamber) according to a selection of a menu option “QC MODE” by an operator, or in response to instruction from a host computer. A QC wafer is permitted to be conveyed from a carrier connected to an associated load port 24 into the processing unit to be inspected, in response to a notification the fact that a wafer stored in the carrier connected to the associated load port 24 is the QC wafer. |
| US09305812B2 |
Die eject assembly for die bonder
Disclosed herein is a die eject assembly for a die bonder that may include a poker pin having an elongate shaft portion with a first end and a second end. The poker pin further includes a base portion having a first end and a second end. The base portion has a maximum diameter that is larger than the maximum diameter of the elongate shaft portion. The elongate shaft portion first end is fixedly attached to the base portion second end. |
| US09305805B2 |
Methods for atomic layer etching
Provided are methods of etching a substrate using atomic layer deposition apparatus. Atomic layer deposition apparatus including a gas distribution plate with a thermal element and remote plasma are discussed. The thermal element is capable of locally changing the temperature of a portion of the surface of the substrate to vaporize an etch layer deposited on the substrate. |
| US09305804B2 |
Plasma etch processes for opening mask layers
Implementations described herein generally relate to semiconductor manufacturing and more particularly to the process of plasma etching an amorphous carbon layer. In one implementation, a method of etching a feature in an amorphous carbon layer is provided. The method comprises transferring a substrate including a patterned photoresist layer disposed above the amorphous carbon layer into an etching chamber, exposing the amorphous carbon layer to a fluorine-free etchant gas mixture including a fluorine-free halogen source gas and a passivation source gas and etching the amorphous carbon layer with a plasma of the fluorine-free etchant gas mixture. It has been found that plasma etching with a fluorine-free halogen based gas mixture reduces the formation of top critical dimension clogging oxides. |
| US09305802B2 |
Methods of forming semiconductor devices using hard masks
Methods of forming a semiconductor device are provided. The methods may include forming an insulating layer including silicon on a substrate and sequentially forming a first hard mask layer and a second hard mask layer on the substrate. The first hard mask layer may include carbon, and the second hard mask layer may include carbon and impurities. The first and second hard mask layers may expose at least a portion of the insulating layer. The methods may also include performing an etching process to selectively remove the second hard mask layer with respect to the insulating layer. A ratio of etch rates between the second hard mask layer and the insulating layer during the etching process may be in a range of about 100:1 to about 10,000:1. |
| US09305800B2 |
Methods for fabricating integrated circuits using directed self-assembly including lithographically-printable assist features
Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming assisting etch resistant fill topographical features that overlie a semiconductor substrate and that define an assisting etch resistant fill confinement well using a photomask. The photomask defines an assisting lithographically-printable mask feature. A block copolymer is deposited into the assisting etch resistant fill confinement well. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The assisting etch resistant fill topographical features direct the etch resistant phase to form an etch resistant plug in the assisting etch resistant fill confinement well. |
| US09305798B2 |
Device and method for stopping etching process
A method for etching a layer assembly, the layer assembly including an intermediate layer sandwiched between an etch layer and a stop layer, the method including a step of etching the etch layer using a first etchant and a step of etching the intermediate layer using a second etchant. The first etchant includes a first etch selectivity of at least 5:1 with respect to the etch layer and the intermediate layer. The second etchant includes a second etch selectivity of at least 5:1 with respect to the intermediate layer and the stop layer. The first etchant being is different from the second etchant. |
| US09305793B2 |
Wafer processing method
A wafer processing method for forming a via hole in a wafer. The wafer processing method includes a filament forming step of applying a pulsed laser beam to the wafer, the pulsed laser beam having a transmission wavelength to the wafer, in the condition where the focal point of the pulsed laser beam is set inside the wafer in a subject area where the via hole is to be formed, thereby forming an amorphous filament inside the wafer in the subject area, and an etching step of etching the amorphous filament formed inside the wafer by using an etching agent to thereby form the via hole inside the wafer. |
| US09305792B2 |
Texture-etchant composition for crystalline silicon wafer and method for texture-etching (1)
Disclosed herein is an etching composition for texturing a crystalline silicon wafer, comprising, based on a total amount of the composition: (A) 0.1 to 20 wt % of an alkaline compound; (B) 0.1 to 50 wt % of a cyclic compound having a boiling point of 100° C. or more; (C) 0.00001 to 10 wt % of a silica-containing compound; and (D) residual water. The etching composition can maximize the absorbance of light of the surface of a crystalline silicon wafer. |
| US09305791B2 |
High productivity combinatorial workflow to screen and design chalcogenide materials as non volatile memory current selector
Combinatorial workflow is provided for evaluating materials and processes for current selector devices in a cross point memory array. Blanket layers, metal-insulator-metal devices, and compete memory structures are combinatorially fabricated on multiple regions of a substrate, with each region having a different material and process condition for the current selector devices. The current selector devices are then characterized, and the data are compared to obtain the optimum materials and processes. |
| US09305788B2 |
Method of fabricating semiconductor device
A method of fabricating a semiconductor device includes: forming a metal layer containing Al; forming an insulating film on the metal layer; forming an opening pattern to the insulating film, the metal layer being exposed in the opening pattern; and forming a wiring layer in the opening pattern, a first portion being disposed between an edge of the wiring layer and an edge of the opening pattern, a width of the first portion being 1 μm or less, and the metal layer being exposed in the first portion. |
| US09305784B2 |
Ion implantation method and ion implantation apparatus
On a plane of a semiconductor wafer, two types of in-plane regions comprising full-width non-ion-implantation regions and partial ion implantation regions, which are alternately arranged one or more times in a direction orthogonal to a scanning direction of an ion beam are created. During the creation of the partial ion implantation regions, reciprocating scanning using the ion beam can be repeated until the target dose can be satisfied while performing or stopping ion beam radiation onto the semiconductor wafer in a state in which the semiconductor wafer can be fixed. During the creation of the full-width non-ion-implantation regions, the semiconductor wafer can be moved without performing the ion beam radiation onto the semiconductor wafer. Then, by repeating fixing and movement of the semiconductor wafer plural times, ion implantation regions and non-ion-implantation regions are created in desired regions of the semiconductor wafer. |
| US09305782B2 |
Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same
A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described. |
| US09305780B2 |
Self-limiting chemical vapor deposition and atomic layer deposition methods
Methods for depositing silicon on a semiconductor or metallic surface include cycling dosing of silane and chlorosilane precursors at a temperature between 50° C. and 300° C., and continuing cycling between three and twenty three cycles until the deposition self-limits via termination of surface sites with Si—H groups. Methods of layer formation include depositing a chlorosilane onto a substrate to form a first layer, wherein the substrate is selected from the group consisting of InxGa1-xAs, InxGa1-xSb, InxGa1-xN, SiGe, and Ge, wherein X is between 0.1 and 0.99. The methods may include pulsing a silane to form a silicon monolayer and cycling dosing of the chlorosilane and the silane. Layered compositions include a first layer selected from the group consisting of InxGa1-xAs, InxGa1-xSb, InxGa1-xN, SiGe, and Ge, wherein X is between 0.1 and 0.99, and a second layer, wherein the second layer comprises Si—H and Si—OH. |
| US09305776B2 |
Oxygen-doped gallium nitride crystal substrate
Disclosed is a gallium nitride crystal substrate having a top surface, a bottom surface, regions of higher oxygen concentrations measured by SIMS, and other regions of lower oxygen concentrations measured by SIMS. The top surface is a C-plane surface. The ratio of the highest oxygen concentration to the lowest oxygen concentration is equal to or more than fifty. |
| US09305775B2 |
Fabrication method of semiconductor memory device
An access device having a reduced height and capable of suppressing leakage current, a method of fabricating the same, and a semiconductor memory device including the same, are provided. The access device may include a stacked structure including a first-type semiconductor layer having a first dopant, a second-type semiconductor layer having a second dopant, and a third-type semiconductor layer. A first counter-doping layer, having a counter-dopant to the first dopant, is interposed between the first-type semiconductor layer and the third-type semiconductor layer. A second counter-doping layer, having a counter-dopant to the second dopant, is interposed between the third-type semiconductor layer and the second-type semiconductor layer. |
| US09305773B2 |
Semiconductor device, nitride semiconductor wafer, and method for forming nitride semiconductor layer
According to one embodiment, a semiconductor device includes a functional layer of a nitride semiconductor. The functional layer is provided on a nitride semiconductor layer including a first stacked multilayer structure provided on a substrate. The first stacked multilayer structure includes a first lower layer, a first intermediate layer, and a first upper layer. The first lower layer contains Si with a first concentration and has a first thickness. The first intermediate layer is provided on the first lower layer to be in contact with the first lower layer, contains Si with a second concentration lower than the first concentration, and has a second thickness thicker than the first thickness. The first upper layer is provided on the first intermediate layer to be in contact with the first intermediate layer, contains Si with a third concentration lower than the second concentration, and has a third thickness. |
| US09305772B2 |
Electronic device using group III nitride semiconductor having specified dislocation density, oxygen/electron concentration, and active layer thickness
The present invention discloses an electronic device using a group III nitride substrate fabricated via the ammonothermal method. By utilizing the high-electron concentration of ammonothermally grown substrates having the dislocation density less than 105 cm−2, combined with a high-purity active layer of Ga1-x-yAlxInyN (0≦x≦1, 0≦y≦1) grown by a vapor phase method, the device can attain high level of breakdown voltage as well as low on-resistance. To realize a good matching between the ammonothermally grown substrate and the high-purity active layer, a transition layer is optionally introduced. The active layer is thicker than a depletion region created by a device structure in the active layer. |
| US09305771B2 |
Prevention of metal loss in wafer processing
An embodiment includes a method comprising: etching a material to expose a metal component in a metal layer, which is located on a substrate, while the substrate is in an etch chamber that is under vacuum; and performing an ash process on the metal component while the substrate is still in the etch chamber that is still under vacuum; wherein the material includes at least one of a dielectric and a mask and the metal component includes at least one of an interconnect, a via, and a contact. Other embodiments are described herein. |
| US09305770B2 |
Method and apparatus for liquid treatment of wafer-shaped articles
An apparatus for treating a wafer-shaped article, comprises a spin chuck for holding a wafer-shaped article in a predetermined orientation, a liquid dispenser for dispensing a treatment liquid onto a downwardly facing surface of a wafer-shaped article when positioned on the spin chuck, and a gas dispenser for dispensing a gas within a gap defined between the downwardly-facing surface of the wafer-shaped article and an upper surface of the spin chuck. |
| US09305769B2 |
Thin wafer handling method
A method includes receiving a carrier with a release layer formed thereon. A first adhesive layer is formed on a wafer. A second adhesive layer is formed over the first adhesive layer or over the release layer. The carrier and the wafer are bonded with the release layer, the first adhesive layer, and the second adhesive layer in between the carrier and the wafer. |
| US09305766B2 |
Method for manufacturing a nanowire structure
The present invention provides a method for aligning nanowires which can be used to fabricate devices comprising nanowires that has well-defined and controlled orientation independently on what substrate they are arranged on. The method comprises the steps of providing nanowires (1) and applying an electrical field (E) over the population of nanowires (1), whereby an electrical dipole moment of the nanowires makes them align along the electrical field (E). Preferably the nanowires are dispersed in a fluid during the steps of providing and aligning. When aligned, the nanowires can be fixated, preferably be deposition on a substrate (2). The electrical field can be utilized in the deposition. Pn-junctions or any net charge introduced in the nanowires (1) may assist in the aligning and deposition process. The method is suitable for continuous processing, e.g. in a roll-to-roll process, on practically any substrate materials and not limited to substrates suitable for particle assisted growth. |
| US09305764B2 |
Plasma light source, inspection apparatus including plasma light source, and method of generating plasma light
A plasma light source includes a chamber having an ionizable medium therein, an ignition source configured to provide first electromagnetic radiation to the chamber, a sustaining source configured to separately provide second electromagnetic radiation to the chamber, a first curved mirror positioned adjacent the chamber, and a second curved mirror positioned opposite the first mirror and arranged to direct the first electromagnetic radiation toward the chamber. The second electromagnetic radiation may be different than the first electromagnetic radiation. Related devices and methods of operation are also discussed. |
| US09305759B2 |
Ionization at intermediate pressure for atmospheric pressure ionization mass spectrometers
An ion source able to ionize liquid and gaseous effluents from interfaced liquid or gaseous separation techniques and from direct introduction of the analyte to the entrance of the ionization region. The liquid effluents from sources such as a liquid chromatograph are ionized by inlet ionization methods and the gaseous effluents from sources such as a gas chromatograph are ionized by a corona or Townsend electrical discharge, or an alpha or beta emitter, or by inlet ionization, or by photoionization. Ionization occurs in an intermediate pressure region linking atmospheric pressure and the vacuum of the mass analyzer. The source has the ability to ionize compounds from both liquid and gaseous sources, which facilitates ionization of volatile compounds separated by gas chromatography, volatile or non-volatile compounds separated by liquid chromatography, or infused into the ionization. The ionization methods can be achieved with a single configuration or with separately optimized configurations. |
| US09305755B2 |
Mass analysis data processing method and mass analysis data processing apparatus
From the data obtained by an LC/MS analysis in which an automatic MSn analysis is performed, all MS2 spectrum data are collected (S1), and a data matrix is created whose elements are peak intensity data with different precursor ions being arrayed in the horizontal direction and the mass-to-charge ratio of the product ions in the vertical direction (S2). By using the data in this data matrix, the correlation coefficients between two precursor ions are computed to create a correlation coefficient matrix (S3). In the correlation coefficient matrix, the diagonal elements whose value is “1” are all replaced by “0” to create an adjacency matrix (S4). A network analysis is performed for the adjacency matrix to create a network map showing the correlations among different precursor ions (MS2spectra) (S5). The network map is displayed on a window of a display unit simultaneously with the result of an MS1 analysis to provide an analysis operator with information on the compounds contained in a sample or the structure thereof (S6). |
| US09305745B2 |
Scanning electron microscope
The purpose of the present invention is to provide a scanning electron microscope that achieves an increase in both resolution and pattern recognition capability. In order to achieve the purpose, the present invention proposes a scanning electron microscope provided with a monochromator that makes an electron beam monochromatic, the monochromator including a magnetic field generator that deflects the electron beam, and an energy selection aperture that passes a part of the electron beam deflected by the magnetic field generator. An aperture that passes some of electrons emitted from the sample and a detector that detects the electrons that have passed through the aperture are disposed on a trajectory to which the electrons emitted from the sample are deflected by a magnetic field generated by the magnetic field generator. |
| US09305744B2 |
Measuring method, data processing apparatus and electron microscope using same
The objective of the invention is to provide a measuring method that can determine pattern contours and dimensions with high precision even if an object to be measured shrinks due to electron beam radiations. In order to achieve this objective, a method, which performs measurements by irradiating an electron beam onto a sample having a pattern formed on a primary coating thereof, prepares an SEM image and contour of the pattern (S201, S202), material parameters of the pattern part and primary coating part of the sample (S203, S204), and a beam condition in irradiating the electron beam onto the sample (S205), and uses these prepared things to calculate a pattern shape or dimensions before the irradiation of the electron beam (S206). |
| US09305739B2 |
Apparatus for ultra high vacuum thermal expansion compensation and method of constructing same
An x-ray tube includes a frame forming a first portion of a vacuum enclosure, a rotating subsystem shaft positioned within the vacuum enclosure and having a first end and a second end, wherein the first end of the rotating subsystem shaft is attached to a first portion of the frame, a target positioned within the vacuum enclosure and attached to the rotating subsystem shaft between the first end and the second end, the target positioned to receive electrons from an electron source positioned within the vacuum enclosure, and a thermal compensator mechanically coupled to the second end of the rotating subsystem shaft and to a second portion of the frame, the thermal compensator forming a second portion of the vacuum enclosure. |
| US09305737B2 |
Liquid filament for incandescent lights
A filament for a light bulb includes a tube and a filament material within the tube, wherein the filament material is configured to be in a liquid state while the light bulb is in use. |
| US09305735B2 |
Reinforced polymer x-ray window
An x-ray window comprising a polymer and carbon nanotubes and/or graphene. The carbon nanotubes and/or graphene can be embedded in the polymer. Multiple layers of polymer, carbon nanotubes, and/or graphene may be used. The polymer with carbon nanotubes and/or graphene can be used as an x-ray window support structure and/or thin film. |
| US09305734B2 |
Semiconductor device for electron emission in a vacuum
A semiconductor device for electron emission in a vacuum comprises a stack of two or more semi-conductor layers of N and P type according to sequence N/(P)/N forming a juxtaposition of two head-to-tail NP junctions, in materials belonging to the III-N family, two adjacent layers forming an interface. The semiconductor materials of the layers of the stack close to the vacuum, where the electrons reach a high energy, have a band gap Eg>c/2, where c is the electron affinity of the semiconductor material, the P-type semiconductor layer being obtained partially or completely, by doping impurities of acceptor type or by piezoelectric effect to exhibit a negative fixed charge in any interface between the layers, a positive bias potential applied to the stack supplying, to a fraction of electrons circulating in the stack, the energy needed for emission in the vacuum by an emissive zone of an output layer. |
| US09305733B2 |
12CaO-7Al2O3 electride hollow cathode
The use of the electride form of 12CaO-7Al2O3, or C12A7, as a low work function electron emitter in a hollow cathode discharge apparatus is described. No heater is required to initiate operation of the present cathode, as is necessary for traditional hollow cathode devices. Because C12A7 has a fully oxidized lattice structure, exposure to oxygen does not degrade the electride. The electride was surrounded by a graphite liner since it was found that the C12A7 electride converts to it's eutectic (CA+C3A) form when heated (through natural hollow cathode operation) in a metal tube. |
| US09305726B2 |
Arc extinguishing contact assembly for a circuit breaker assembly
An arc extinguishing contact assembly for a circuit breaker assembly is provided. The arc extinguishing contact assembly includes a fixed contact assembly, a movable contact assembly and an arc extinguishing assembly. The fixed contact assembly includes a fixed arc contact assembly, a fixed main contact assembly, and a number of movable, intermediate arc contact assemblies. The movable contact assembly includes a movable arc contact assembly and a movable main contact assembly. The arc extinguishing assembly is structured to extinguish an arc generated as the movable contact assembly moves between an open, first position and a closed, second position. |
| US09305719B2 |
Selector for a tap changer
A tap-changer selector for uninterrupted switching between two winding taps of a tapped transformer has fixed contacts arranged circularly in several horizontal planes at a selector housing and a centrally extending rotatable drive shaft in an interior of the selector housing and in each of the horizontal planes of the fixed contacts carries at least one movable contact for connection thereof. The selector housing consists of a plurality of honeycomb segments, and the honeycomb segments are arranged adjacent to one another in the circle in a horizontal plane. A plurality of honeycomb segments arranged in a plane in the circle are arranged vertically one above the other and the honeycomb segments have mounting regions and are so interconnectible by these mounting regions to form when at least two honeycomb segments are connected a mechanically positive connection between at least two mounting regions of the individual honeycomb segments. |
| US09305717B2 |
Electrochemical device having electric storage element and electroye sealed in insulating case
An electrochemical device has a lid, case, electric storage element, electrolyte, and conductive bonding material layer. The case has a via hole and forms a solution chamber between itself and the lid. The electric storage element is accommodated in the solution chamber. The electrolyte is accommodated in the solution chamber. The wiring has a via hole part provided in the via hole and connects the interior and exterior of the solution chamber. The conductive bonding material layer fixes the electric storage element onto the case while electrically connecting the electric storage element and via hole part, where the conductive bonding material layer has a contact area that contacts the case and non-contact area that does not contact the case and the non-contact area is formed in a manner surrounding the via hole. |
| US09305713B2 |
Hybrid nanostructure including gold nanoparticles and photoelectrode for solar cell having the same
There is provided a hybrid nanostructure including Au nanoparticles, a photoelectrode for a solar cell having the hybrid nanostructure, and a solar cell including the photoelectrode. |
| US09305711B2 |
Carbon nanostructure, capacitor, method for processing carbon nanostructure, and method for producing carbon nanostructure
A carbon nanostructure's geometry and electrical characteristics can be controlled. A method for processing a carbon nanostructure according to the present invention includes the steps of: preparing a carbon nanostructure (e.g., a carbon nanotube) (a CNT preparation step); and exposing the carbon nanotube to an energy beam (e.g., an electron beam) while vibrating the carbon nanotube (an exposure step). This facilitates modifying the carbon nanotube in length and electrical characteristics. |
| US09305710B2 |
Method for manufacturing tungsten capacitor element
A method for manufacturing a tungsten capacitor element, which includes: a sintering process for forming an anode body by sintering a tungsten powder or a molded body thereof, a chemical conversion process for forming a dielectric layer on the surface layer of the anode body, a process for forming a semiconductor layer on the dielectric layer, a post-chemical conversion process for repairing the defects generated on the dielectric layer, a non-aqueous electrolysis process for conducting electrolysis operation by immersing the anode body in a solution of a non-aqueous solvent containing an oxidizing agent, and a process of forming a conductor layer on the anode body, in this order. |
| US09305706B2 |
Fractional order capacitor
Disclosed is a fractional order capacitor comprising a dielectric nanocomposite layer of thickness t, comprising a first side, and a second side opposite the first side, a first electrode layer coupled to the first side of the dielectric nanocomposite layer, a second electrode layer coupled to the second side of the dielectric nanocomposite layer, a complex impedance phase angle dependent on at least a material weight percentage of filler material in a dielectric nanocomposite layer. |
| US09305704B2 |
Multilayer ceramic capacitor and manufacturing method thereof
There is provided a multilayer ceramic capacitor including, a ceramic body having a plurality dielectric layers stacked therein and a groove portion recessed inwardly in a lower surface thereof in a width direction, a plurality of first and second internal electrodes disposed in the ceramic body to be alternately exposed through both end surfaces of the ceramic body, having the dielectric layers therebetween, and first and second external electrodes respectively formed on both end portions of the ceramic body and electrically connected to the first and second internal electrodes, respectively. |
| US09305697B2 |
Integrated transformer
An integrated transformer comprising a primary coil and a secondary coil, the primary coil comprising a first subsection and a second subsection, the first subsection extending in a different plane to a plane in which the second subsection extends, the planes spaced from one another, the secondary coil comprising a first subsection and a second subsection, the first subsection extending in a different plane to a plane in which the second subsection extends, the planes spaced from one another, wherein the first subsection of the primary coil is stacked with the second subsection of the secondary coil and the second subsection of the primary coil is stacked with the first subsection of the secondary coil. |
| US09305695B2 |
Current-compensated choke and circuit arrangement with a current-compensated choke
A current-compensated choke features several current paths and includes several windings that are connected in parallel and wound around a common core. The windings preferably are alternately wound on the core in such a way that windings of a common current path are not arranged directly one on top of another. |
| US09305690B2 |
Composite ferrite composition and electronic device
A composite ferrite composition comprises a magnetic material and a non-magnetic material. A mixing ratio of said magnetic material and said non-magnetic material is 20 wt %:80 wt % to 80 wt %:20 wt %. Ni—Cu—Zn based ferrite is used as the magnetic material. Oxides of Zn, Cu, and Si are at least included in a main component of said non-magnetic material. Borosilicate glass is included in a subcomponent of said non-magnetic material. |
| US09305688B2 |
Single photomask high precision thin film resistor
An integrated circuit contains a thin film resistor in which a body of the thin film resistor is disposed over a lower dielectric layer in a system of interconnects in the integrated circuit. Heads of the thin film resistor are disposed over electrodes which are interconnect elements in the lower dielectric layer, which provide electrical connections to a bottom surface of the thin film resistor. Top surfaces of the electrodes are substantially coplanar with a top surface of the lower dielectric layer. A top surface of the thin film resistor is free of electrical connections. An upper dielectric layer is disposed over the thin film resistor. |
| US09305687B2 |
Current sensing resistor
A resistor device includes a resistor plate having opposite first and second surfaces; a first metal layer including first and second portions which are disposed on the first surface of the resistor plate at opposite first and second sides, respectively; and a second metal layer including a first sensing pad, a second sensing pad, a first current pad and a second current pad, separate from one another, wherein the first sensing pad and the first current pad are disposed on the first portion of the first metal layer and the second sensing pad and the second current pad are disposed on the second portion of the first metal layer. A protective layer is preferably provided, overlying the resistor plate and the first metal layer uncovered by the second metal layer. |
| US09305686B2 |
Multilayer ceramic electronic component and manufacturing method thereof
There are provided a multilayer ceramic electronic component that does not require a heat treatment under a reduction atmosphere, and a manufacturing method thereof, wherein a conductive oxide is used as a material of internal and external electrodes and conductive layers having elasticity are formed on the external electrodes. In the case of the multilayer ceramic electronic component, a firing process may be performed under an air atmosphere, such that a manufacturing process may be simplified and manufacturing costs may be reduced. |
| US09305683B1 |
System, apparatus, and method for effectively applying proper sequential alpha-numerics to extruded wire and cable
A process and system for printing sequences of alpha-numeric characters on segments of wire or cable during production. In one embodiment, the process and system comprises printing a sequence of alpha-numeric values onto a first segment of wire up to an input target value. The process and system further comprises printing a sequence of alpha-numeric values onto a second segment of wire up to a second input target value. In one embodiment, the process and system is capable of printing sequences on segments of wire or cable up to variable target values without requiring a shutdown of the production process, and without requiring lag time between printing on subsequent wire or cable segments. |
| US09305680B2 |
Transparent conductive film and manufacturing method therefor
The present invention relates to a transparent conductive film which is excellent in dotting property under a heavy load and excellent in bending resistance. Provided is a transparent conductive film, comprising a flexible transparent base; and a transparent conductive layer formed on the flexible transparent base and including a crystalline indium/tin composite oxide, wherein a compressive residual stress of the transparent conductive layer is 0.4 to 2 GPa. |
| US09305678B2 |
Composition for wire coating member, insulated wire, and wiring harness
To provide a composition for a wire coating member containing a non-crosslinked material at a low cost, which has superior flame retardancy, and is excellent in heat resistance, wear resistance and flexibility, and to provide an insulated wire and a wiring harness containing the composition. The composition contains (A) polypropylene, (B) a polyolefin elastomer, (C) a bromine flame retardant, (D) an antimony trioxide, (E) magnesium hydroxide, either one of (F) (F1) a zinc sulfide and (F2) a zinc oxide and (F3) mercaptobenzimidazole, and (G) a hindered phenolic antioxidant. The insulated wire includes a conductor and an insulation coat made from the composition, wherein the insulation coat has a thickness of 0.5 mm or less, and the insulated wire has an external diameter of 4 mm or less. The wiring harness includes the insulated wire. |
| US09305677B2 |
Boron nitride converted carbon fiber
This disclosure provides systems, methods, and apparatus related to boron nitride converted carbon fiber. In one aspect, a method may include the operations of providing boron oxide and carbon fiber, heating the boron oxide to melt the boron oxide and heating the carbon fiber, mixing a nitrogen-containing gas with boron oxide vapor from molten boron oxide, and converting at least a portion of the carbon fiber to boron nitride. |
| US09305676B2 |
Composite material, electric contact electrode, electric contact film, conductive filler, electric contact structure using composite material, and manufacturing method of composite material
A composite material includes a metal matrix of a metal and a reducing agent. The reducing agent is dispersed in the metal matrix and is capable of reducing an oxide of the metal at room temperature. Even when the oxide of the metal is generated on a surface of the composite material, the reducing agent reduces the oxide of the metal to the metal |
| US09305674B1 |
Method and device for secure, high-density tritium bonded with carbon
A method and device for producing secure, high-density tritium bonded with carbon. A substrate comprising carbon is provided. A precursor is intercalated between carbon in the substrate. The precursor intercalated in the substrate is irradiated until at least a portion of the precursor, preferably a majority of the precursor, is transmutated into tritium and bonds with carbon of the substrate forming bonded tritium. The resulting bonded tritium, tritium bonded with carbon, produces electrons via beta decay. The substrate is preferably a substrate from the list of substrates consisting of highly-ordered pyrolytic graphite, carbon fibers, carbon nanotunes, buckministerfullerenes, and combinations thereof. The precursor is preferably boron-10, more preferably lithium-6. Preferably, thermal neutrons are used to irradiate the precursor. The resulting bonded tritium is preferably used to generate electricity either directly or indirectly. |
| US09305673B2 |
Systems and methods for harvesting and storing materials produced in a nuclear reactor
Systems produce desired isotopes through irradiation in nuclear reactor instrumentation tubes and deposit the same in a robust facility for immediate shipping, handling, and/or consumption. Irradiation targets are inserted and removed through inaccessible areas without plant shutdown and placed in the harvesting facility, such as a plurality of sealable and shipping-safe casks and/or canisters. Systems may connect various structures in a sealed manner to avoid release of dangerous or unwanted matter throughout the nuclear plant, and/or systems may also automatically decontaminate materials to be released. Useable casks or canisters can include plural barriers for containment that are temporarily and selectively removable with specially-configured paths inserted therein. Penetrations in the facilities may limit waste or pneumatic gas escape and allow the same to be removed from the systems without over-pressurization or leakage. Methods include processing irradiation targets through such systems and securely delivering them in such harvesting facilities. |
| US09305671B2 |
Managing electrical power for a nuclear reactor system
An electrical power system for a nuclear power facility includes an active alternating current (AC) power bus configured to be electrically coupled to a plurality of engineered safety feature (ESF) loads of a plurality of nuclear power systems, each of the ESF loads configured to fail to a safe position upon loss of primary AC power; a critical battery system electrically coupled to the active AC bus, the critical battery system comprising a plurality of valve regulated lead acid (VRLA) batteries; and a primary AC power source electrically coupled to the active AC bus. |
| US09305670B2 |
TIP system and TIP monitoring control equipment
A TIP monitoring control equipment has: a process computer, a TIP control panel, and data transmitting unit. The process computer includes a operation input unit, a TIP scanning unit, a first TIP level data transmitting and receiving unit, and a TIP level data storage unit. To a first TIP level data transmitting and receiving unit, an LPRM level signal, an APRM level signal and TIP level data accumulated in the TIP control panel are input in synchronization with a TIP position signal. The TIP control panel includes a TIP driving control unit, a TIP level processing unit, a TIP position processing unit, a TIP level data accumulation unit and a second TIP level data transmitting and receiving unit. The second TIP level data transmitting and receiving unit transmits TIP level data accumulated in the TIP level data accumulation unit to the process computer via the data transmission unit. |
| US09305669B2 |
Controllable long term operation of a nuclear reactor
Exemplary embodiments provide automated nuclear fission reactors and methods for their operation. Exemplary embodiments and aspects include, without limitation, re-use of nuclear fission fuel, alternate fuels and fuel geometries, modular fuel cores, fast fluid cooling, variable burn-up, programmable nuclear thermostats, fast flux irradiation, temperature-driven surface area/volume ratio neutron absorption, low coolant temperature cores, refueling, and the like. |
| US09305666B2 |
Prioritized repair of data storage failures
Embodiments are directed towards managing data storage that may experience a data failure. If a repair event is associated with a data storage failure, a new repair task may be generated and added to a task list. A priority value for each repair task in the task list may be determined based in part on the mean-time-to-data-loss (MTTDL) value associated with each repair task in the task list such that a lower MTTDL may indicate a higher priority value over a lower MTTDL. One or more repair tasks may be promoted to become active repair tasks based on the priority value the repair tasks such that the promoted repair tasks have a higher priority that than other repair tasks in the task list, if any. Each active repair task may be executed to repair one or more associated the storage failures. |
| US09305665B2 |
Memory system and method of controlling memory system
According to one embodiment, when loading of reverse lookup information from a nonvolatile first memory to a randomly accessible second memory has failed, a controller determines whether data at a first physical address is valid or invalid by using lookup information loaded from the first memory to the second memory. |
| US09305664B2 |
Memory repair categorization tracking
An integrated circuit includes a set of non-volatile bits that may be programmed during multiprobe testing of the integrated circuit (IC). A defective portion of the IC is identified by testing the IC during multiprobe testing prior to packaging the IC. The IC is scrapped if the defective portion of IC does not meet repair criteria. A defect category is selected that is indicative of the defective portion, wherein the defect category is selected from a set of defect categories. The defective portion is replaced with a standby repair portion by modifying circuitry on the IC. The selected defect category is recorded in a plurality of non-volatile bits on the IC. The non-volatile bits may be read after extended testing or after end-user deployment in order to track failure rate of repaired ICs based on the defect category. |
| US09305662B2 |
Data storage device and flash memory control method
An identification technique for physically damaged blocks of a flash memory of a data storage device. In the data storage device, a controller coupled to the flash memory writes data into the flash memory with at least one time stamp corresponding to the data. The time stamp is taken into consideration by the controller to identify the physically damaged blocks of the flash memory, and thereby it is prevented from erroneously identifying a physically undamaged block as bad. Thus, the flash memory is prevented from being erroneously regarded as a write protected memory. The lifespan of the flash memory is effectively prolonged. |
| US09305659B2 |
Dynamic program window determination in a memory device
A memory device has an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to determine a program window after a portion of a particular programing operation performed on the memory device is performed and before a subsequent portion of the particular programing operation performed on the memory device is performed. The controller is configured to determine the program window responsive to an amount of program disturb experienced by a particular state of a memory cell. The controller is configured to perform the subsequent portion of the particular programing operation performed on the memory device using the determined program window. |
| US09305657B2 |
Non-volatile memory device and related method of operation
A non-volatile memory device receives a start command through a command line, receives an address through an address line, receives at least one setting value through the address line, receives a confirm command corresponding to the start command through the command line, sets at least one parameter of the non-volatile memory device as the setting value based on the start command, a number of the setting value, and the confirm command, and executes an operation that corresponds to the start command, on a memory cell that corresponds to the address, based on the set parameter. |
| US09305654B2 |
Erase and soft program for vertical NAND flash
Methods, and apparatuses to erase and or soft program a block of NAND memory may include performing an erase cycle on a block of NAND memory comprising two or more sub-blocks, verifying the two or more sub-blocks until a sub-block fails to verify, stopping the verification in response to the failed verify, performing another erase cycle on the block of NAND memory, and re-starting to verify the two or more sub-blocks at the sub-block that failed to verify. |
| US09305653B1 |
Memory array and operating method of same
A method of operating a memory array is disclosed. The memory array includes a plurality of memory cells arranged in rows and columns, wherein a plurality of parallel memory strings correspond to respective ones of the columns, and a plurality of word lines are arranged orthogonal to the plurality of memory strings, each word line being connected to gate electrodes of a corresponding one of the rows of memory cells. The method includes performing a program operation that programs all of the memory cells on edge word lines located at opposite edges of the memory array, and that programs selected memory cells between the edge word lines in the memory array according to input data to be stored in the memory array. Each programmed memory cell has a threshold voltage at a program verify (PV) level. |
| US09305652B2 |
Semiconductor memory device and erasing method thereof
Provided is a semiconductor memory device and a method of erasing the same. The semiconductor memory device includes a memory cell array including a plurality of memory cells; and a peripheral circuit unit configured to apply a pre-erase voltage, an erase voltage, and an erase operation voltage to the memory cell array so as to erase data stored in the plurality of memory cells when an erase operation is performed. The memory cell array includes a plurality of source selection transistors, the plurality of memory cells, and a plurality of drain selection transistors that are connected between a source line and a bit line. When the pre-erase voltage is applied to the source line during the erase operation, different erase operation voltages are applied to an outermost source selection transistor adjacent to the source line among the plurality of source selection transistor and the other selection transistors. |
| US09305641B2 |
Resistance change memory and forming method of the resistance change device
A resistance change memory has a resistance change device and a control circuit for controlling application of voltage to the resistance change device. The resistance change device has a first electrode, a second electrode, and a resistance change layer interposed between the first electrode and the second electrode. A material for the second electrode includes one of members selected from the group consisting of W, Ti, Ta, and nitrides thereof. During forming of the resistance change device, the control circuit performs a second forming treatment succeeding to a first forming treatment. The first forming treatment includes application of voltage such that the potential of the first electrode is higher than the potential of the second electrode. The second forming treatment includes application of voltage such that the potential of the second electrode is higher than the potential of the first electrode. |
| US09305640B2 |
Asymmetric log-likelihood ratio for flash channel
Disclosed is a system and method for reading flash memory cells with dynamically adjusted probability values (e.g., log-likelihood ratios). In connection with reading bit values from flash memory cells, one or more predetermined first probability values are adjusted relative to one or more predetermined second probability values. The one or more predetermined first probability values are associated with reading one or more memory cells programmed to a first binary value, and the one or more predetermined second probability values are associated with reading one or more memory cells programmed to a second binary value. The plurality of bit values read from the plurality of non-volatile memory cells and the one or more adjusted first probability values are provided to a decoder for use in decoding the plurality of bit values. |
| US09305639B2 |
Read-detection in multi-level cell memory
A method and apparatus for detecting N-symbol codewords. The method including: reading q-level memory cells to obtain a read signal having N signal components; detecting the memory cell level corresponding to each component using a first correspondence criterion dependent on reference signal levels; identifying unreliable components; detecting, for each unreliable component, the next-most-closely corresponding memory cell level according to the first correspondence criterion; defining a set of ordered codeword vectors having N symbols corresponding to respective components of the read signal ordered according to a signal level, wherein the symbol values in each ordered codeword vector correspond to one combination of detected memory cell levels; defining, for each read signal, candidate initial vectors having intersected the ordered codeword vectors and plurality of initial vectors; and detecting, if the candidate initial vectors contains a vector, the codeword corresponding to that read signal that depends on the candidate initial vectors. |
| US09305635B2 |
High density memory structure
A semiconductor memory comprises a plurality of sub banks each including one or more rows of memory bit cells connected to a set of local bit lines, wherein the sub banks share a same set of global bit lines for reading/writing data from/to the memory bit cells of the sub banks. The semiconductor memory chip further comprises a plurality of switch elements for each of the sub banks, wherein each of the switch elements connects the local bit line and the global bit line of a corresponding one of the memory bit cells in the sub bank for data transmission between the local bit line and the global bit line. The semiconductor memory chip further comprises a plurality of bank selection signal lines each connected to the switch elements in a corresponding one of the sub banks, wherein the bank selection signal lines carry a plurality of bank selection signals to select one of the sub banks for data transmission between the local bit lines and the global bit lines. |
| US09305629B2 |
Integrated capacitor based power distribution
An embodiment provides power (having low voltage, high current, and high current density) to ultra low voltage non-CMOS based devices using a distributed capacitor that is integrated onto the same chip as the non-CMOS devices. For example, an embodiment provides a spin logic gate adjacent dielectric material and first and second plates of a capacitor. The capacitor discharges low voltage/high current to the spin logic gate using a step down switched mode power supply that charges numerous capacitors during one clock cycle (using a switching element configured in a first orientation) and discharges power from the capacitors during the opposite clock cycle (using the switching element configured in a second orientation). The capacitors discharge the current out of plane and to the spin logic devices without having to traverse long power dissipating interconnect paths. Other embodiments are described herein. |
| US09305627B2 |
Resistance change type memory
According to one embodiment, a resistance change type memory includes a first and a second bit lines, a memory cell connected between the first and second bit lines and including a variable resistance element as a memory element and a first select element including a first control terminal connected to a word line, and an auxiliary circuit connected to the first bit line and including a second select element including a second control terminal connected to a control line. When data is read from the memory cell, a first current in a read current supplied to the first bit line is supplied to the memory element and the first select element, and a second current in the read current is supplied to the second select element. |
| US09305625B2 |
Apparatuses and methods for unit identification in a master/slave memory stack
Apparatuses and methods including a plurality of memory units are disclosed. An example apparatus includes a plurality of memory units. Each of the plurality of memory units include a master/slave identification (ID) node coupled to a first voltage source node via a resistive element. Each of the plurality of memory units further include a master/slave ID circuit configured to determine whether a memory unit is a master memory unit or a slave memory unit based on a voltage level detected at the master/slave ID node. The master/slave ID node of each of the plurality of memory units other than a first memory unit is further coupled to a respective second voltage source node via a through—substrate via (TSV) of a respective adjacent memory unit of the plurality of memory units. |
| US09305624B2 |
Vertical switch three-dimensional memory array
A memory device includes a substrate, and, disposed thereover, an array of vertical memory switches. Each switch has at least three terminals and a cross-sectional area less than 6F2. |
| US09305623B2 |
Write assist circuit for write disturbed memory cell
A circuit comprises a first memory cell, a second memory cell, and a disturb control circuit. The first memory cell has a first port and a second port. The first port is associated with a first write assist circuit. The second port is associated with a second write assist circuit. The second memory cell has a third port and a fourth port. The third port is associated with a third write assist circuit. The fourth port is associated with a fourth write assist circuit. The disturb control circuit is configured to selectively turn on at least one of the first write assist circuit, the second write assist circuit, the third write assist circuit, or the fourth write assist circuit according to whether the first port, the second port, the third port, or the fourth port is determined to be write disturbed. |
| US09305621B2 |
Semiconductor devices and semiconductor systems including the same
Semiconductor systems are provided. The semiconductor system may include a controller and a semiconductor device. The controller may generate command signals and address signals. The semiconductor device may discharge electric charges of a first local line pair and a second local line pair during a predetermined period after a read operation begins according to a combination of the command signals, equalize and pre-charge levels of the first and second local line pairs when a pre-charge operation is executed or the address signals are inputted thereto. The semiconductor device may also sense and amplify data loaded on the first or second local line pair to output the amplified data through an input/output line after the read operation begins. |
| US09305617B2 |
Data and strobe decompressing memory controller and memory control method
Write-leveling, a write-leveling control unit (250) adjusts the delay amounts of DQS control unit (242) and a DQ control unit (244), at first, within a range of less than one clock cycle. Then, with respect to each SDRAM (282), a read-data row acquired by performing a read after a write of an expected value data row is compared value data row, and depending upon the comparison result, the delay amounts of the DQS control unit (242) and the DQ control unit (244) are adjusted in clock-cycle units. At the above write-time, control is performed so that the DQS control unit (242) outputs a data strobe signal (DQS) which is 2×M clock cycles longer than a burst length defined according to a specification, and the DQ control unit (244) adds M units each of data before and after a number of units of expected value data rows that match the burst length in order to output the data. |
| US09305613B2 |
Reconfigurable load-reduced memory buffer
A memory module can include a data buffer having a data bus interface and a dynamic random access memory (DRAM) coupled to the data buffer. The memory module may also include a switch connected in parallel with the data buffer, wherein the switch can selectively bypass the data buffer. In one example, the memory module also includes a registered buffer having an address bus interface, where the switch may selectively bypass the data buffer based on a program signal obtained from an address bus via the address bus interface. |
| US09305609B2 |
System and method of command based and current limit controlled memory device power up
Devices and systems for powering up a memory device, for example, are disclosed. One such memory device includes power up circuitry configured to receive an external power supply and to provide an internal power supply to the memory device upon receipt of a command. The power up circuitry may be configured to provide the internal power supply limited to a peak current, or may be configured to provide the internal power supply not limited to a peak current. The memory device may be, for example, a synchronous dynamic random access memory (SDRAM) device or Flash memory. |
| US09305607B2 |
Logical memory architecture, in particular for MRAM, PCRAM, or RRAM
An architecture and method are provided for reading and writing, in parallel or in series, an electronic memory component based on a two-dimensional matrix of two-terminal binary memory unit cells built into a crossbar architecture. The component includes a logical column-selector located outside the matrix and activating at least one column, one or more cells of which are subjected to read or write processing. Also provided is a component and method with the reading of the status of the cells by differential detection on from two cells of two different rows, either between a storage column and a constant reference column, or between two rows or two storage columns. A component is also provided in which specific selection structure is exclusively dedicated to read operations, and/or in which complementary cells in two complementary columns connected together are encoded in a single atomic operation by means of a single write current. |
| US09305605B2 |
Discrete three-dimensional vertical memory
The present invention discloses a discrete three-dimensional vertical memory (3D-MV). It comprises at least a 3D-array die and at least a peripheral-circuit die. The 3D-array die comprises a plurality of vertical memory strings. At least an off-die peripheral-circuit component of the 3D-MV arrays is located on the peripheral-circuit die instead of the 3D-array die. The 3D-array die and the peripheral-circuit die have substantially different back-end-of-line (BEOL) structures. |
| US09305603B2 |
Method and apparatus for indexing a video stream
Embodiments including a method and apparatus for indexing a video stream are disclosed. In one embodiment, a method for indexing a video stream comprises accessing a video stream comprising a plurality of frames. For each frame, the method determines salient points computes a cross entropy value for each salient point, and sums the cross entropy values to form a frame information number. A sequence of frame information numbers for the plurality of frames in the video streams forms an index value for the video stream. |
| US09305602B2 |
Object-based audio system, object-based audio providing method, and object-based audio playing method using preset function
An object-based audio system, an object-based audio providing method, and an object-based audio playback method using a preset are provided. The object-based audio system includes a reference information providing unit to provide reference information used to refer to a storage location of an object-based audio file, and a preset information providing unit to provide preset information used to control at least one audio object forming the object-based audio file. |
| US09305596B2 |
Multi-sensor media defect scan
Apparatus and method for detecting media defects using a multi-sensor transducer. In some embodiments, a first pattern is written to a first track on a rotatable storage media and a second pattern is written to a second track on the media. A first read sensor of a multi-sensor transducer senses the first pattern from the first track and a second read sensor of the multi-sensor transducer concurrently senses the second pattern from the second track. At least one storage media defect is detected responsive to the sensed first and second patterns. |
| US09305595B2 |
Reader separation dependent linear and track density push for array reader based magnetic recording
A method of operating a multi-reader two-dimensional magnetic recording system includes determining a position of a multi-reader head of the multi-reader two-dimensional magnetic recording system, determining an areal density push according to the position of the multi-reader head, and performing an operation to read data from or write data to a magnetic recording medium according to the areal density push. |
| US09305594B2 |
Cable having audio recording and play back
A cable for transmitting a transmissible element, such as power or data, from a source to a device, the cable includes at least a first plug configured to mate with at least one of the source and the device, and an audio player for playing back audio recording. |
| US09305584B2 |
Determining oscillation characteristic for high-frequency assisted magnetic recording device
A magnetic disk device according to an embodiment includes a magnetic head including a write head with a high-frequency oscillator and a read head, a recording medium, a driving unit configured to moves the magnetic head on the recording medium, a measuring unit configured to obtain a first read signal with no current or a smaller current and a second read signal with a normal current supplied in the normal writing operation, a comparison unit configured to calculate comparative data indicating a comparison result between the first and second read signals, and a determination unit configured to determine an oscillation characteristic from the comparative data. |
| US09305581B2 |
Systems and methods for memory efficient repeatable run out processing
Various embodiments of the present invention provide systems and methods for low overhead disk wobble compensation. As an example, a method for performing synchronous wobble compensation processing is disclosed. The method includes providing a medium that includes a servo data region and a user data region. The servo data region includes a clock recovery pattern and a location pattern. A detectable pattern is written to the user data region a known number of bit periods from the location pattern. The detectable pattern is read back, and a fractional processing delay is calculated. Based at least on the fractional processing delay and a known number of bit periods from the location pattern to the end of the servo data region, a wobble compensation pattern is written an integral number of bit periods from the location pattern. |
| US09305580B2 |
Tape head assembly for linear tape open
A tape head assembly includes a set of data readers configured to simultaneously read data from a set of adjacent data tracks of a tape storage medium, each data track having a width; wherein the width of each data reader of the set along a lateral extension of the tape head assembly is equal to or less than the width of a data track wherein the lateral extension of the tape head assembly is orthogonal to a longitudinal extension of the tape storage medium when arranged in a tape drive containing the tape head assembly spanning at least the set of data tracks during reading; and a servo reader arrangement containing at least one servo reader arranged laterally offset from one of the data readers by less than the width of a data track. |
| US09305578B1 |
Magnetic element with reduced shield-to-shield spacing
A magnetic stack is disclosed. The magnetic stack includes a magnetically responsive lamination that includes a ferromagnetic free layer, a synthetic antiferromagnetic (SAF) structure, and a spacer layer positioned between the ferromagnetic free layer and the SAF structure. The magnetically responsive lamination is separated from a sensed data bit stored in an adjacent medium by an air bearing surface (ABS). The stack also includes a first antiferromagnetic (AFM) structure coupled to the SAF structure a predetermined offset distance from the ABS, and a second AFM structure that is separated from the first AFM structure by a first shield layer. |
| US09305576B2 |
Magnetoresistive element
According to one embodiment, a magnetoresistive element includes a first magnetic layer as a reference layer, a second magnetic layer as a storage layer, a nonmagnetic insulating layer between the first and second magnetic layers, and an antiferromagnetic conductive layer which is adjacent to a side opposite to the nonmagnetic insulating layer side of the second magnetic layer in a vertical direction in which the first and second magnetic layers are stacked. The second magnetic layer includes an area which is magnetically coupled with the antiferromagnetic conductive layer and which has a magnetization direction parallel with a magnetization direction of the second magnetic layer. |
| US09305575B2 |
Heat assisted magnetic recording heads having bilayer heat sinks
Disclosed herein is an apparatus that includes a near field transducer positioned adjacent to an air bearing surface of the apparatus; a first magnetic pole; and a heat sink positioned between the first magnetic pole and the near field transducer, wherein the heat sink includes a first and second portion, with the first portion being adjacent the near field transducer and the second portion being adjacent the first magnetic pole, the first portion including a plasmonic material, and the second portion including a diffusion blocking material. |
| US09305571B2 |
Magnetic devices and magnetic media with graphene overcoat
A magnetic disk according to one embodiment includes a recording layer; and a layer of graphene formed above the recording layer. A nucleation layer may be formed between the recording layer and the graphene layer in some approaches. A magnetic device according to another embodiment includes a transducer; a nucleation layer formed above the transducer; and a layer of graphene formed on the nucleation layer. A method according to one embodiment includes forming a nucleation layer above a magnetic layer of a magnetic disk or magnetic device; and forming a layer of graphene on the nucleation layer. A method according to another embodiment includes depositing SiC above a magnetic layer of a magnetic disk or magnetic device, the SiC being equivalent to several monolayers thick; and surface heating the SiC to selectively evaporate some of the Si from the SiC for forming a layer of graphene on a SiC layer. Additional products and methods are also presented. |
| US09305570B2 |
Systems, methods, apparatus, and computer-readable media for pitch trajectory analysis
Systems, methods, and apparatus for pitch trajectory analysis are described. Such techniques may be used to remove vocals and/or vibrato from an audio mixture signal. For example, such a technique may be used to pre-process the signal before an operation to decompose the mixture signal into individual instrument components. |
| US09305569B2 |
Dialogue system and method for responding to multimodal input using calculated situation adaptability
A dialogue system and a method for the same are disclosed. The dialogue system includes a multimodal input unit receiving speech and non-speech information of a user, a domain reasoner, which stores a plurality of pre-stored situations, each of which is formed by a combination one or more speech and non-speech information, calculating each adaptability of the pre-stored situations on the basis of a generated situation based on the speech and the non-speech information received from the multimodal input unit, and determining a current domain according to the calculated adaptability, a dialogue manager to select a response corresponding to the current domain, and a multimodal output unit to output the response. The dialogue system performs domain reasoning using a situation including information combinations reflected in the domain reasoning process, current information, and a speech recognition result, and reduces the size of a dialogue search space while increasing domain reasoning accuracy. |
| US09305568B2 |
Active acoustic filter with socially determined location-based filter characteristics
There is disclosed active acoustic filter systems and methods. A processor is disposed within a housing configured to interface with a user's ear. A memory stores data defining one or more locations and a respective set of location-based processing parameters associated with each of the one or more locations. A personal computing device external to the housing is coupled to the processor via a first wireless communications link. The personal computing device determines a current location of the active acoustic filter system. The processor generates digitized processed sound by processing digitized ambient sound in accordance with a set of location-based processing parameters retrieved from the memory, the retrieved set of location-based processing parameters associated with the current location of the active acoustic filter system as determined by the personal computing device. |
| US09305560B2 |
Methods, apparatus and articles of manufacture to perform audio watermark decoding
Example methods, apparatus and articles of manufacture to perform audio watermark decoding are disclosed. A disclosed example method includes receiving an audio signal including an audience measurement code embedded therein using a first plurality of frequency components, sampling the audio signal, transforming the sampled audio signal into a first frequency domain representation, determining whether the code is detectable in the first plurality of frequency components of the first frequency domain representation, and when the code is not detected in the first plurality of frequency components, examining a second plurality of frequency components of a second frequency domain representation to determine whether the code is detected, the second plurality of frequency components being offset from the first plurality of frequency components by a first offset, the first offset corresponding to a sampling frequency mismatch. |
| US09305557B2 |
Apparatus and method for processing an audio signal using patch border alignment
Apparatus for processing an audio signal to generate a bandwidth extended signal having a high frequency part and a low frequency part using parametric data for the high frequency part, the parametric data relating to frequency bands of the high frequency part includes a patch border calculator for calculating a patch border such that the patch border coincides with a frequency band border of the frequency bands. The apparatus further includes a patcher for generating a patched signal using the audio signal and the patch border. |
| US09305556B2 |
Apparatus and method for encoding and decoding multi-channel audio signal
Disclosed is an apparatus for encoding and decoding a multi-channel audio signal. The apparatus for encoding the multi-channel audio signal groups channels of a multi-channel audio signal, eliminates redundant information between channels using a mixing matrix including phase information, converts a frequency of the signal, and encodes the signal. |
| US09305555B2 |
Onboard information device
Onboard information device mounted on vehicle to provide information for supporting passenger includes voice acquisition unit that continually detects and acquires voice the passenger utters while the onboard information device is operating; voice recognition unit that recognizes speech contents of the voice the voice acquisition unit acquires; vehicle state detector that detects vehicle state including environmental state in the vehicle, surrounding state of the vehicle or operating state of the vehicle; output controller that creates display data or voice data from the speech contents recognized by the voice recognition unit according to the vehicle state the vehicle state detector detects, and that controls output of the display data or voice data; and output unit that outputs the display data or voice data the output controller creates. It can perform effective conversation support in real time according to recognition result obtained by continually recognizing speech contents of the passenger. |
| US09305553B2 |
Speech recognition accuracy improvement through speaker categories
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for speech recognition. In one aspect, a computer-based method includes receiving a speech corpus at a speech management server system that includes multiple speech recognition engines tuned to different speaker types; using the speech recognition engines to associate the received speech corpus with a selected one of multiple different speaker types; and sending a speaker category identification code that corresponds to the associated speaker type from the speech management server system over a network. The speaker category identification code can be used by any one of speech-interactive applications coupled to the network to select one of an appropriate one of multiple application-accessible speech recognition engines tuned to the different speaker types in response to an indication that a user accessing the application is associated with a particular one of the speaker category identification codes. |
| US09305552B2 |
Systems, computer-implemented methods, and tangible computer-readable storage media for transcription alignment
Disclosed herein are systems, computer-implemented methods, and tangible computer-readable storage media for captioning a media presentation. The method includes receiving automatic speech recognition (ASR) output from a media presentation and a transcription of the media presentation. The method includes selecting via a processor a pair of anchor words in the media presentation based on the ASR output and transcription and generating captions by aligning the transcription with the ASR output between the selected pair of anchor words. The transcription can be human-generated. Selecting pairs of anchor words can be based on a similarity threshold between the ASR output and the transcription. In one variation, commonly used words on a stop list are ineligible as anchor words. The method includes outputting the media presentation with the generated captions. The presentation can be a recording of a live event. |
| US09305550B2 |
Dialogue detector and correction
An apparatus and method for tracking dialogue and other sound signals in film, television or other systems with multiple channel sound is described. One or more audio channels which is expected to carry the speech of persons appearing in the program or other particular types of sounds is inspected to determine if that channel's audio includes particular sounds such as MUEVs, including phonemes corresponding to human speech patterns. If an improper number of particular sounds such as phonemes are found in the channel(s) an action such as a report, an alarm, a correction, or other action is taken. The inspection of the audio channel(s) may be made in conjunction with the appearance of corresponding images associated with the sound, such as visemes in the video signal, to improve the determination of types of sounds such as phonemes. |
| US09305546B2 |
System and method for handling missing speech data
Disclosed herein are systems, computer-implemented methods, and tangible computer-readable media for handling missing speech data. The computer-implemented method includes receiving speech with a missing segment, generating a plurality of hypotheses for the missing segment, identifying a best hypothesis for the missing segment, and recognizing the received speech by inserting the identified best hypothesis for the missing segment. In another method embodiment, the final step is replaced with synthesizing the received speech by inserting the identified best hypothesis for the missing segment. In one aspect, the method further includes identifying a duration for the missing segment and generating the plurality of hypotheses of the identified duration for the missing segment. The step of identifying the best hypothesis for the missing segment can be based on speech context, a pronouncing lexicon, and/or a language model. Each hypothesis can have an identical acoustic score. |
| US09305545B2 |
Speech recognition vocabulary integration for classifying words to identify vocabulary application group
A method for vocabulary integration of speech recognition comprises converting multiple speech signals into multiple words using a processor, applying confidence scores to the multiple words, classifying the multiple words into a plurality of classifications based on classification criteria and the confidence score for each word, determining if one or more of the multiple words are unrecognized based on the plurality of classifications, classifying each unrecognized word and detecting a match for the unrecognized word based on additional classification criteria, and upon detecting a match for an unrecognized word, converting at least a portion of the multiple speech signals corresponding to the unrecognized word into words. |
| US09305544B1 |
Multi-source transfer of delexicalized dependency parsers
A source language sentence is tagged with non-lexical tags, such as part-of-speech tags and is parsed using a lexicalized parser trained in the source language. A target language sentence that is a translation of the source language sentence is tagged with non-lexical labels (e.g., part-of speech tags) and is parsed using a delexicalized parser that has been trained in the source language to produce k-best parses. The best parse is selected based on the parse's alignment with lexicalized parse of the source language sentence. The selected best parse can be used to update the parameter vector of a lexicalized parser for the target language. |
| US09305543B2 |
Intelligent text-to-speech conversion
Techniques for improved text-to-speech processing are disclosed. The improved text-to-speech processing can convert text from an electronic document into an audio output that includes speech associated with the text as well as audio contextual cues. One aspect provides audio contextual cues to the listener when outputting speech (spoken text) pertaining to a document. The audio contextual cues can be based on an analysis of a document prior to a text-to-speech conversion. Another aspect can produce an audio summary for a file. The audio summary for a document can thereafter be presented to a user so that the user can hear a summary of the document without having to process the document to produce its spoken text via text-to-speech conversion. |
| US09305542B2 |
Mobile communication device including text-to-speech module, a touch sensitive screen, and customizable tiles displayed thereon
A customized live the application module can be configured in association with the mobile communication device in order to automatically vocalize the information preselected by a user in a multitude of languages. A text-to-speech application module can be integrated with the customized live tile application module to automatically vocalize the preselected information. The information can be obtained from a tile and/or a website integrated with a remote server and announced after a text to speech conversion process without opening the tile, if the tiles are selected for announcement of information by the device. The information can be obtained in real-time. Such an approach automatically and instantly pushes a vocal alert with respect to the user-selected information on the mobile communication device thereby permitting the user to continue multitasking. Information from tiles can also be rendered on second screens from a mobile device. |
| US09305540B2 |
Frequency domain signal processor for close talking differential microphone array
A system and method for processing close talking differential microphone array (CTDMA) signals in which incoming microphone signals are transformed from time domain signals to frequency domain signals having separable magnitude and phase information. Processing of the frequency domain signals is performed using the magnitude information, following which phase information is reintroduced using phase information of one of the original frequency domain signals. As a result, high pass filtering effects of conventional differential signal processing of CTDMA signals are substantially avoided. |
| US09305529B1 |
Guitar rest
Guitar rest is a portable devise which secures itself onto a guitar neck and provides additional support to a guitar when said guitar is leaning on a vertical surface such as a wall. Such state of leaning is to be understood as the most common practice of vertically resting a guitar on the floor and then leaning the neck of said guitar on an adjacent wall. It is to be understood that said surface is free of any additional parts or aids mounted onto it in order to aid Guitar rest. In this sense Guitar rest is a free-standing devise. Guitar rest can generally be described as being comprised of a neck support unit and a wall rest unit. The neck support unit is designed to grip onto the guitar neck while the wall rest unit comprises a pair of arms by means of which contact and stability at said vertical surface is achieved. |
| US09305517B2 |
Apparatus and method for enhancing photorealism of computer graphic image
An apparatus and method for enhancing photorealism of a computer graphic (CG) image. Since color distribution maps of the CG image and a realistic image are extractable, a color distribution map of an input CG image may be adjusted, thereby enhancing photorealism of the CG image. |
| US09305516B1 |
Electronic device
According to one embodiment, an electronic device comprises, as an example, a memory, a receiver, and a transmitter. The memory is configured to store therein first extended display identification data (EDID) and second EDID comprising a different version of the High-Definition Multimedia Interface (HDMI) from the first EDID. The receiver is configured to receive a video signal from another electronic device. The transmitter is configured to send the first EDID comprising an identification bit to the another electronic device, the another electronic device being configured to respond to the identification bit when the another electronic device supports the version of the HDMI of the second EDID, and to send the second EDID to the another electronic device when the receiver has received a response corresponding to the identification bit from the another electronic device. |
| US09305514B1 |
Detection of relative positions of tablet computers
Tablet computers send relevant geographic and identification data to an application server (one of the tablets, or a local or remote server) which groups them to form a video wall. Once placed next to one another in substantially the same plane, the tablets snap photographs at more or less the same time and these images are transmitted to the application server. The server determines the relative positions of the tablets and then streams a portion of a video or digital image to each of the tablets in order that all tablets display the video or image in an integrated fashion. The tablets may operate independently or may rely upon the remote application server. Relative positions are determined by analyzing features and determining an up-down or left-right relationship between pairs of images, sorting images into vertical and horizontal rows, and placing the images into a grid. |
| US09305512B2 |
Array substrate, display device and method for controlling refresh rate
The present invention discloses array substrate, display device and method for controlling refresh rate of an array substrate. The array substrate includes; a plurality of pixel structures each including gate line, data line, common electrode line, first switching element at intersection of the gate line and the data line, pixel electrode, second switching element, and first transparent electrode. Gate, source and drain of the first switching element are connected to the gate line, the date line and the pixel electrode, respectively. Gate, source and drain of the second switching element are connected to second switching controlling line, common electrode signal terminal and the first transparent electrode, respectively. A first storage capacitance is formed between the pixel electrode and the common electrode line and/or between the pixel electrode and the gate line, and a second storage capacitance is formed between the pixel electrode and the first transparent electrode. |
| US09305509B2 |
Shift register unit, gate driving circuit and display apparatus
The present disclosure relates to the technical field of display. Provided are a shift register unit, a gate driving circuit and a display apparatus, the shift register unit includes an inputting module, a first outputting module and a second outputting module. As compared with the prior art, the structure of the shift register unit can be simplified effectively, and the number of use of the transistors can be further reduced. Embodiments of the present disclosure are used to implement scanning and driving. |
| US09305505B1 |
Display panel and mobile terminal
A display panel comprising a light guide plate; a main light source configured to emit light from a first lateral surface of the light guide plate in a first direction; a sub-light source configured to emit light from a second lateral surface vertical to the first lateral surface of the light guide plate in a second direction perpendicular to the first direction; and a liquid crystal panel provided in a front surface of the light guide plate and configured to output image information. |
| US09305502B2 |
Adjusting method of gamma voltage adjusting device
Disclosed is an adjusting method of a gamma voltage adjusting device. The gamma voltage adjusting device is utilized for providing a liquid crystal panel with N gray levels and includes a printed circuit board assembly and a gamma voltage fine-tuning unit. The adjusting method of the gamma voltage adjusting device includes: generating N+2 gamma voltages with the printed circuit board assembly; inputting the N+2 gamma voltages to the gamma voltage fine-tuning unit; and generating negative polarity driving voltages and positive polarity driving voltages which are symmetrical according to the N+2 gamma voltages. The present invention decreases a number of gamma integrated circuits on the printed circuit board assembly for saving cost by decreasing the 2N gamma voltages in the prior arts to the N+2 gamma voltages. |
| US09305501B2 |
Display device and driving method thereof
A method to drive a display device includes: transmitting at least one data voltage to one or more of a plurality of data lines, scanning one or more of a plurality of gate lines to enable transmission of a gate signal in association with a first frame of a first hold section of a first still image section associated with display of a still image, and scanning one or more of the plurality of gate lines to enable transmission of the gate signal every frame of a first refresh section. The first still image section comprises the first refresh section. |
| US09305497B2 |
Systems, devices, and methods for driving an analog interferometric modulator
Display elements of a display array include at least one fixed layer and a movable layer. The movable layer is positioned with respect to the at least one fixed layer by placing a charge on the movable layer and applying a voltage to the at least one fixed layer. The at least one fixed layer may be two layers positioned on either side of the movable layer. The movable layer may be positioned in a desired position when driving an array of display elements by executing a reset stage, a charging stage, and a bias stage. |
| US09305493B2 |
Organic light emitting diode pixel circuit and display device
Embodiments of the invention provide an organic light emitting diode pixel circuit and a display device so as to address such a problem of non-uniform display of an image on the entire display panel due to different threshold voltages of drive transistors in different pixel elements in a traditional organic light emitting diode pixel circuit. A drive signal generation module in the organic light emitting diode pixel circuit according to an embodiment of the invention reads and stores the threshold voltage of a drive transistor in a threshold voltage reading phase, and in a signal loading phase, receives an image data signal and generates a drive signal from the received image data signal and the threshold voltage of the drive transistor stored in the threshold voltage reading phase so that the drive signal is dependent upon the threshold voltage of the drive transistor. |
| US09305492B2 |
Display device and method for driving the same
An organic EL display device includes a controller, a data driver, and a DRAM which provides a gain correction memory and a threshold voltage correction memory. The data driver sends, to the controller, first and second measurement data Im corresponding to the first and second measuring data voltages Vm, respectively. The controller compares ideal characteristic data IO(P) with the first and second measurement data Im, and updates threshold voltage correction data Vt and gain correction data B2R based on the comparison results. The controller corrects video data Vm based on the threshold voltage correction data Vt and the gain correction data B2R. Thereby, both threshold voltage compensation and gain compensation of a drive transistor are performed with respect to each pixel circuit, while display is performed. |
| US09305488B2 |
Re-interpolation with edge detection for extracting an aging pattern for AMOLED displays
A method that includes an initial uniform pixel measurement and interpolation followed by an edge detection algorithm to recognize the areas that contribute mostly to the estimation error due to the interpolation. The pixels on the detected edges and around their vicinity are also measured, and an aging pattern of the entire display is obtained by re-interpolating the entire measured set of data for the initially measured pixels as well as the pixels around the detected edges. The estimation error is reduced particularly in the presence of aging patterns having highly spatially correlated areas with distinctive edges. |
| US09305487B2 |
Organic light emitting diode display and method for driving display panel thereof
An OLED display and a method for driving a display panel thereof are provided. The layout area of each pixel of the OLED display panel is specially designed to be a rectangle in shape, and the pixels are driven in such a manner that each two sub-pixels are taken as a unit to be driven. As such, according to the interaction manner among sub-pixels of the pixels, two sub-pixels can be viewed as one pixel to achieve more pixels within 1 inch in comparison with the conventional panels, which enables the current AMOLED driving circuit designs to be used in specific high resolution applications. |
| US09305480B2 |
Liquid crystal display device
A display having a data driving integrated circuit includes N number of output channels (where N is an integer) having at least two regions including a first output channel and an Nth output channel, a data output channel group including M data output channels (where M is an integer less than N), the M data output channels supplying pixel data to a corresponding number of the data lines in accordance with a desired resolution of the display, wherein (N−M) output channels are not supplied with pixel data, and the (N−M) output channels are located between the first output channel and the Nth output channel, and a channel selector selecting the M data output channels. |
| US09305478B2 |
Organic light emitting diode display device
An OLED display device includes first and second group pixels that emit light during first and second fields, respectively; first and second scan lines respectively coupled to the first and second group pixels; and first and second power lines for respectively supplying first and second power voltages to the first and second group pixels. The first and second power lines are coupled with first electrodes of the respective storage capacitors of the first and second group pixels, and the first power voltage is supplied as a first level voltage for a first period during which the first group pixels concurrently emit light. The first and second power lines are coupled with first electrodes of the respective storage capacitors of the first and second group pixels, and the first power voltage is supplied as a first level voltage for a first period during which the first group pixels concurrently emit light. |
| US09305476B2 |
Chemical mechanical polishing (CMP) composition for shallow trench isolation (STI) applications and methods of making thereof
Methods for removing, reducing or treating the trace metal contaminants and the smaller fine sized cerium oxide particles from cerium oxide particles, cerium oxide slurry or chemical mechanical polishing (CMP) compositions for Shallow Trench Isolation (STI) process are applied. The treated chemical mechanical polishing (CMP) compositions, or the CMP polishing compositions prepared by using the treated cerium oxide particles or the treated cerium oxide slurry are used to polish substrate that contains at least a surface comprising silicon dioxide film for STI (Shallow trench isolation) processing and applications. The reduced nano-sized particle related defects have been observed due to the reduced trace metal ion contaminants and reduced very smaller fine cerium oxide particles in the Shallow Trench Isolation (STI) CMP polishing. |
| US09305475B2 |
Multipurpose sign bases for supporting temporary roadway safety signs
A multipurpose sign base suitable for supporting temporary signs includes an upstanding mast supportable atop a support surface by a substantially horizontally extending, elongate, support member connected to a lower region of the mast, and by a plurality of elongate leg members of adjustable length each having an upper portion movably connected to a central region of the mast, and each having a lower portion movably connected to a different foot adapted to engage a different area of the support surface at locations arrayed about the mast. An upper region of the mast is connectable to a sign to support and display the sign. The legs and feet have retracted positions near the mast. A rearwardly extending formation of the horizontal support member can be coupled to a vehicle hitch so the sign base also can be supported on a vehicle for transport while displaying a sign. |
| US09305474B2 |
Motorized gift package accessory
The motorized gift package accessory of the present disclosure and related inventions include a base portion, which can be attached, adhesively or otherwise, to a gift package, such as a gift box. An accessory portion is attached to the base portion and contains one or more mobile elements which can be set in motion by a small or miniature motor. User interaction with the motorized gift package accessory is required to initiate the motor which in turn effects movement of the one or more mobile elements. |
| US09305471B1 |
Display for use in managing a patient
A display system for use by a caregiver team in managing a patient includes a substrate panel arranged to be suspended on a wheelchair with a clock face printed on the front surface with at least one manually movable hand to display a selected time. A first window display on the front surface is manually set a selected time period to visit the patient. A plurality of alternate operations on the patient to reduce pressure issues is printed on the rear and a selected one is indicated to the caregiver by moving a marker so that the caregiver is required by the clock time on the clock face to attend the patient, to carry out the selected action and to reset the clock time by an increment determined by the time period and so that the failure to attend the patient is immediately visible. |
| US09305469B2 |
Method of mounting subsea antifouling signs
A subsea antifouling sign and a method for mounting such a sign on a structure to be located subsea. The sign comprises a body of an antifouling material, and a first surface of the body has indicia or markings thereon. An adhesive layer or coating is provided on a second opposing surface, and a protective lining is located on the adhesive layer or coating. The method comprises removing the protective lining from the adhesive layer or coating; and attaching the subsea antifouling sign to the structure by adhering the adhesive layer or coating to a surface of the structure. |
| US09305468B2 |
Systems and methods of providing adjustable signage
Architectural signage and the providing of systems and methods for adjustable signage suitable for operation with one hand. A signage assembly may include a slider panel assembly having a back plate and a plurality of slider portions, where each of the slider portions may include a guidance tongue formed from a portion of the back plate. The guidance tongue may include a lock button extending from a front face of the guidance tongue, wherein the guidance tongue is configured to flex in a direction perpendicular to or from a front face of the back plate to allow insertion of a slidable tab with reduced interference from the lock button, and wherein the lock button is configured to mate with a lock pocket of a slidable tab when the slidable tab is fully extended. |
| US09305463B1 |
Automatically activated in-cabin vehicle camera system
A method is provided for automatically activating an in-cabin camera system whenever the control system determines that the volume level of sounds detected within the car are in excess of a preset sound level, thereby allowing the driver under certain circumstances to monitor occupants of the rear portion of the passenger cabin without stopping the car or turning around in their seat. The system can be configured to analyze the detected sounds and compare those sounds to preset sound patterns, thus helping the system to distinguish between routine background noise and any sounds that indicate that activation of the in-cabin camera system is warranted. |
| US09305460B1 |
Roadway warning light detector and method of warning a motorist
A warning light detector and system to alert a motorist of warning lights is provided. The warning light detector includes a camera that takes digital images of a field of view in front of the automobile, and a detection program to detect any warning lights analyzes these digital images. A control system of the detector activates an alert feature, such as a sound and/or light, to alert the motorist of a warning light when one has been detected by the detection program.An alert feature may be a sound emitted from a speaker or light that flashes and the alert feature may be configured on the detector or be transmitted through the automobile's stereo, warning, or navigational system, for example. A detector may be a mobile device, such as a mobile phone and a warning light detector application program may be downloaded to the mobile device. |
| US09305459B2 |
Automated driver alert system
In accordance with some embodiments, an automated system may be implemented in which alerts to drivers are automatically distributed and implemented at the driver's vehicle. Thus, in some embodiments, no involvement by the driver is needed and everything may be done in an automated fashion including filtering alerts and responding to alerts. In some embodiments, each vehicle need not provide its current location to the Amber Alert System, providing greater privacy in some cases. |
| US09305457B2 |
System for managing a cabin environment in a platform, and associated management method
The system according to the invention comprises a mobile electronic device, at least one local base, arranged near a predefined location in the cabin, an assembly for pairing the mobile electronic device with the local base, and at least one piece of functional equipment for managing the cabin environment. The memory of the mobile electronic device stores at least one software application for controlling the functional equipment. The pairing system is capable of sending the mobile electronic device at least one location identification data of the local base during pairing between the mobile electronic device and the local base, the mobile electronic device being able to configure the control software application, based on the location identification data. |
| US09305452B2 |
Battery over-charge and over-discharge protection system and battery protection method able to release a protection state
A battery protection system applicable to an electronic device includes a battery, a control module, a message generating module and an input interface. The control module is electrically connected to the battery for detecting if the battery is in an abnormal state. The message generating module is electrically connected to the control module for generating a battery-error warning message when the control module detects that the battery is in the abnormal state. The input interface is electrically connected to the control module for transmitting a user command to the control module after the battery-error warning message is generated, thereby enabling the control module to release the abnormal state of the battery according to the user command. A battery protection method is also provided. |
| US09305449B2 |
Laser obstacle detector
The present invention provides a device for assisting a person in determining the presence or identity of obstacles in the person's path, characterized by a housing, a laser projector for generating a laser pattern in a surface in said person's path, a receiver for at least receiving a plurality of images of the laser pattern reflected from the surface and for generating a signal corresponding to said laser pattern reflection and a processor for processing said signal to at least determine the presence or identity of an object, and a warning generator for generating a warning to the person. The present invention also provides a method for assisting a person in determining the presence of an object in a person's path comprising generating a laser pattern comprising a plurality of laser lines on a surface, distinguishing between one or more straight line segments in the laser pattern and distorted line segments of said laser pattern after they are reflected from said surface and evaluating the distortions in said line segments of said laser pattern to determine the presence or identity of an object in the person's path. The present invention can be used to assist the visually impaired in seeing objects in their path or can be used by a sighted user in game play or at night for detecting obstacles. Some of the functions of the present device can be provided in a smart phone which can be adapted with a laser projection as a separate attachment or as part of the smart phone circuitry. |
| US09305448B2 |
Securing distribution lines from pilferages
The instant invention provides a smart system for securing distribution lines from malicious activities in the electricity distribution system, ultimately influencing the power sector in a positive way. The system architecture comprises two major parameters including distribution box and service box contributing mainly to the focal purpose of the system. The system is designed intelligently to improve and impede the process of theft control. The distribution box is designed to provide a high frequency signal having high voltage spikes on the distribution lines. |
| US09305447B2 |
Electronic article surveillance tag deactivation
A method and system for producing an electromagnetic field that exhibits a strong near field that is sufficient to deactivate an electronic article surveillance, EAS, tag and a weak far field that is insufficient to deactivate the EAS tag are disclosed. According to one embodiment, two half-wavelength dipoles spaced apart by about a half-wavelength are excited by oppositely phased signals. |
| US09305445B1 |
Alarm system for passageways
An improved alarm system for monitoring movement through a passageway defined by opposing sidewalls. The alarm system has a lower passage indicator disposed toward the lower ends of the sidewalls, an upper passage indicator disposed toward the upper ends of the sidewalls and a control mechanism configured to sound an alarm if the lower passage indicator indicates passage through the passageway and the upper passage indicator does not. In one embodiment, each of the passage indicator comprises transducers that are configured to direct and receive sound waves, such as ultrasound waves, and provide lower and upper ultrasound waves that act as lower and upper barriers. If only the lower barrier is interrupted, indicating a child passing through the passageway, the control mechanism will generate an alarm signal. If both barriers are interrupted, indicating an adult passing through the passageway, the control mechanism will not generate the alarm signal. |
| US09305439B2 |
Configurable indicator on computing device
A computing device may include a policy agent configured to receive activity information, apply at least one display policy to the activity information, and determine at least one command based on results of the at least one display policy being applied to the activity information, and a multi-colored indicator unit, located on a non-display screen area of the computing device, configured to display at least one of a plurality of colors based on the at least one command. |
| US09305438B2 |
POS network including printing and highlighting
The invention provides for optional printing at a pont of sale (POS). The invention provides a system and computer implemented method for printing information at a POS relating to a purchase transaction at the POS, comprising printing a second alternative instead of a default print, or printing both a default and a second print, in both cases dependent upon the second print being timely delivered to the POS printer. Preferably, the second print depends upon processing business rules related to color in the print. |
| US09305437B1 |
Heuristics for media dispensing in automated teller machines (ATMs)
According to embodiments described in the specification, a method of dispensing media from an ATM is disclosed. The method includes the steps of: at an electronic device including a processor, a memory, and a touch-sensitive display, displaying a first mix of media items for dispensing by the ATM; receiving input from the touch-sensitive display including a first mix adjustment parameter; applying a heuristic based on the received first mix adjustment parameter, and, at the ATM, dispensing a second mix of media items, the second mix responsive to the application of the heuristic. |
| US09305428B2 |
System and method of timing wagers in an integrated wagering and interactive media platform
The invention relates to systems and methods of selecting and placing real-world wagers responsive to one or more wager triggers, obtaining outcomes of the real-world wagers, facilitating user interactions with various interactive media, and revealing the outcomes of the real-world wagers through the interactive media to give an appearance that the outcomes of the real-world wagers resulted from the user interactions even though the outcomes resulted from the real-world wagers and were determined before the user interactions. A real-world wager may be initiated by one or more wager triggers that cause the real-world wager to be placed. The one or more wager triggers may include, without limitation, acquisition of a token, user selection or initiation of interactive media (e.g., selection of a game to play), an occurrence of an event in the interactive media (e.g., based on a user controlled or other in-game action), and/or other events. |
| US09305426B2 |
Method and apparatus for planning and customizing a gaming experience
The invention includes a system and method for planning and customizing a gaming vacation. Initially, a central controller receives preference and configuration data from a user at a user terminal. A preparation code is then determined and associated with the configuration data. The configuration data and the associated preparation code are transmitted from the central controller to a casino server. The central controller provides feedback regarding the user's requests. The feedback may include, for example, marketing offers for the user and/or configuring a gaming device according to the configuration data associated with a preparation code received from a user at the gaming device. |
| US09305424B2 |
System for managing an electronic gaming machine group
Various embodiments are directed to gaming systems and related methods for managing one or more electronic gaming machines (EGMs). The gaming system includes a network management system capable of establishing one or more groups (or collections) of gaming machines. The groups of gaming machines may be defined according to one or more gaming machine characteristics. The grouping of the gaming machines on the casino floor allows the system to dynamically configure these different groups of gaming machines. |
| US09305422B2 |
Method and apparatus for audio scaling at a display showing content in different areas
A method and device for scaling audio content associated with first and second sources at a user apparatus such as a gaming machine. When the gaming machine is in a first condition displaying only game content speakers are controlled to produce game related audio content. In a second condition where the display is controlled to share game content and other content from a remote source in a picture-in-picture arrangement, the method and device control the speaker volumes to associate the audio content with the associated video content to provide audio directionality and primacy. |
| US09305420B2 |
Credit and enabling system for virtual constructs in a hybrid game
Systems and methods in accordance with embodiments of the invention operate a controlled entity hybrid game. A controlled entity hybrid game includes a real world engine constructed to provide a randomly generated payout of real world credits from at least one wager in a gambling game, an entertainment software engine constructed to execute an entertainment game providing outcomes based upon a player's skillful execution of the entertainment game; and a game world engine constructed to manage the entertainment software engine and communicate, to the gambling game, a gameplay gambling event occurrence based upon a player's instruction of a controlled entity to consume an element of the entertainment game that triggers a wager in the gambling game, and change the element on the basis of the randomly generated payout and an entertainment game variable. |
| US09305413B1 |
Fingerprint check to reduce check fraud
A digital image of a surface of a check is received. A check scanning device captures the digital image as the check moves through the check scanning device. A fingerprint is impressed on the surface of the check. A computing system uses the digital image to determine a match score. The match score represents an approximate probability that the fingerprint on the check matches a reference fingerprint. An alert is presented based on the match score. |
| US09305412B2 |
Apparatus, system and method for vehicle authentication management and reporting
Apparatus, system and method for authenticating access to a vehicle, where vehicle events, such as a door lock condition or an operating condition of the vehicle, are reported to an authentication network. Vehicle events are compared to a vehicle schedule to determine if the vehicle events comply with the schedule using authentication rules. If the events are not compliant, an authentication request signal, requiring a predetermined authentication response, is transmitted to the vehicle. Access to the vehicle may be denied until a match to the predetermined authentication response is received. Authentication may include the use of a portable device, which may act as an intermediary between the vehicle and the authentication system. Vehicle events may further be reported to the portable device. Authentication rules may be updated automatically based on further incoming vehicle events, or may be updated manually using a computer. |
| US09305411B2 |
Automatic device and vehicle pairing via detected emitted signals
Methods and systems for a vehicle system that includes intercepting signals associated with a device and isolating identifiers associated with the device. The vehicle registers the device with a vehicle control system. |
| US09305410B2 |
Automatic detection of valet mode for smart entry systems
A key fob assembly includes a mechanical key, a key fob, a control in the key fob, Hall effect switches in the key fob, and magnets associated with the mechanical key. The mechanical key is configured to cooperate with a mechanical lock. The key fob is configured to selectively connect with the mechanical key. The control in the key fob is for transmitting wireless signals to a vehicle to actuate components on the vehicle. The Hall effect switches in the key fob are each in electrical communication with the control. At least one of the Hall effect switches changes an operating state based on detecting a positive magnetic field and at least one other Hall effect switch changes an operating state based on detecting a negative magnetic field. Respective poles of the magnets are disposed such that connection of the mechanical key with the key fob in a storage position aligns the poles of the magnets with respective Hall effect switches for changing the operating state of the respective Hall effect switches. |
| US09305409B2 |
Electronic control unit
An electronic control unit comprises a central processing unit for calculating plural types of control data used for controlling a control object and a non-volatile memory rewritable of data. The processing unit writes sequentially type-affixed control data, in each of which type information indicating a type of control data is affixed to the control data, into a data write-in area in the non-volatile memory. When a hold condition corresponding to one of the plural types of control data is satisfied, the processing unit reads out the type-affixed control data, which includes the control data corresponding to a satisfied hold condition, from the data write-in area based on the type information, and writes the type-affixed control data read out from the data write-in area in a data holding area of the non-volatile memory. |
| US09305402B2 |
Synchronized, interactive augmented reality displays for multifunction devices
A device can receive live video of a real-world, physical environment on a touch sensitive surface. One or more objects can be identified in the live video. An information layer can be generated related to the objects. In some implementations, the information layer can include annotations made by a user through the touch sensitive surface. The information layer and live video can be combined in a display of the device. Data can be received from one or more onboard sensors indicating that the device is in motion. The sensor data can be used to synchronize the live video and the information layer as the perspective of video camera view changes due to the motion. The live video and information layer can be shared with other devices over a communication link. |
| US09305400B2 |
Method and system for augmented reality
A method of augmented reality includes associating tint information with a predetermined graphical object, and receiving a video image of a real scene comprising a feature for detection. The method further includes detecting the feature in the video image of the real scene and selecting a graphical object responsive to the detected feature, and augmenting the video image with the selected graphical object. If the selected graphical object is the predetermined graphical object, the method further includes retrieving the tint information associated with the predetermined graphical object, and modifying the color balance of the video image responsive to the tint information. |
| US09305395B2 |
Dental imaging apparatus
The invention relates to a dental imaging apparatus which includes an x-ray imaging means and at least one color camera for photographing the face of a patient positioned at the imaging station of the apparatus, which at least one color camera is arranged to image the patient's face positioned at the patient support station from different directions, and means arranged into functional connection with said at least one color camera for creating a virtual three-dimensional texture model of the patient's face. |
| US09305393B2 |
Building acceleration structures with synthetic acceleration shapes for use in ray tracing
A synthetic acceleration shape bound primitives composing a 3-D scene, and is defined using a group of fundamental shapes arranged to bound the primitives, and for which intersection results for group members yield an ultimate intersection testing result for the synthetic shape, using a logical operator. For example, two or more spheres are used to bound an object so that each of the spheres is larger than a minimum necessary to bound the object, and a volume defined by an intersection between the shapes defines a smaller volume in which the object is bounded. A ray is found to potentially intersect the object only if it intersects both spheres. In another example, an element may be defined by a volumetric union of component elements. Indicators can determine how groups of shapes should be interpreted. Synthetic shapes can be treated as a single element in a graph or hierarchical arrangement of acceleration elements. |
| US09305392B2 |
Fine-grained parallel traversal for ray tracing
Techniques are disclosed for tracing a ray within a parallel processing unit. A first thread receives a ray or a ray segment for tracing and identifies a first node within an acceleration structure associated with the ray, where the first node is associated with a volume of space traversed by the ray. The thread identifies the child nodes of the first node, where each child node is associated with a different sub-volume of space, and each sub-volume is associated with a corresponding ray segment. The thread determines that two or more nodes are associated with sub-volumes of space that intersect the ray segment. The thread selects one of these nodes for processing by the first thread and another for processing by a second thread. One advantage of the disclosed technique is that the threads in a thread group perform ray tracing more efficiently in that idle time is reduced. |
| US09305390B2 |
System and method for mapping two-dimensional image data to a three-dimensional faceted model
A method for mapping a two-dimensional image data onto a three-dimensional graphic model of an object includes taking a plurality of two-dimensional images of the object. Each two-dimensional image has data, such as temperature data, which is desired to be represented on the three-dimensional graphic model. The three-dimensional model of the object is viewed on a graphic user interface. The three-dimensional model has a plurality of facets, each facet being configured for selectively receiving the data from the two-dimensional images, so that the two-dimensional images are mapped onto the facets of the three-dimensional model. The three-dimensional model can then be analyzed. |
| US09305389B2 |
Reducing seam artifacts when applying a texture to a three-dimensional (3D) model
Embodiments of the present invention include techniques for reducing artifacts in rendered images. In one embodiment, a dual UV engine generates a dual of the graph defined by an initial UV set associated with a 3D model. The dual UV engine then uses existing flattening and layout engines to generate a dual UV set from this dual graph. Using the dual graph to define the dual UV set ensures that the seams corresponding to the initial UV set and the dual UV set minimally intersect. |
| US09305386B2 |
Editable motion trajectories
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for providing a view of a three-dimensional computer animation model, the view including one or more objects, wherein each of the one or more objects is associated with a respective animation setting for adjusting a respective three-dimensional motion trajectory interpolation of the object in the computer animation model between a first and a different second key frame; receiving data describing a user interaction with a visual representation of the animation setting in the view for a first object of the one or more objects, the user interaction being an adjustment of the respective animation setting of the first object; and based on the receiving, adjusting the motion trajectory interpolation of the first object between the particular first and second key frames. |
| US09305384B2 |
Hybrid image decomposition and projection
Hybrid image projection systems and methods can superimpose image components of an input image. An input image can be divided into smaller regions and at least one parameter of each region can be determined. The input image can be decomposed based on the parameter of each region into multiple, less correlated, orthogonal or quasi-orthogonal image components. Each projector can display respective image components so that the images projected may be optically superimposed on a screen. The superposition of orthogonal or quasi-orthogonal image components can result in superposition of images in an existing multi-projector image systems being more insensitive to inter-projector image misalignment. Superimposing orthogonal or quasi-orthogonal images can be used to avoid visible image degradation, and provide more robust image quality in a multiple projector system implementation. |
| US09305379B2 |
Methods and systems for tomographic reconstruction
A method for processing an image of a series of images includes receiving first data representing a first previously reconstructed image and receiving second data representing a second image. A second image is reconstructed in accordance with the first data, the second data and a noise model. The noise model is a likelihood estimation. The second image is reconstructed in accordance with a penalty function. The penalty function is a roughness penalty function. The penalty function is updated by iteratively adjusting an image volume estimate. The penalty function is updated by iteratively adjusting a registration term. The penalty function is a prior image penalty function and the prior image penalty function and a registration term are jointly optimized. The penalty function is determined in accordance with a noise model. The function is a p-norm penalty function. |
| US09305378B1 |
Lenslet, beamwalk and tilt diversity for anisoplanatic imaging by large-aperture telescopes
Systems and methods which combine standard image reconstruction and beam-control techniques with tomographic estimation of three-dimensional atmospheric turbulence to enable high-quality anisoplanatic imaging of distant objects at long range through the atmosphere over an extended field-of-view using a large aperture. More specifically, the systems and methods combine the concepts of atmospheric tomography, forward-model image reconstruction and tip, tilt, beam-walk, and focus control techniques to produce image reconstructions of high quality for large objects that move rapidly as viewed by large apertures in weak or strong extended atmospheric turbulence. |
| US09305374B2 |
Device, method, and graphical user interface for adjusting the appearance of a control
An electronic device with a display displays a user interface on the display. The device determines a first set of content-display values for one or more content-display properties of first content that corresponds to a respective region of the display. The device determines a first set of control-appearance values for one or more control-appearance parameters based on the first set of content-display values. The device displays a control in the respective region of the display, where an appearance of the control is determined based on the first content and the first set of control-appearance values, and displaying the control includes applying a blur operation to the first content to generate first blurred content and overlaying a translucent colored layer over the first blurred content. |
| US09305371B2 |
Translated view navigation for visualizations
Among other things, one or more techniques and/or systems are provided for defining transition zones for navigating a visualization. The visualization may be constructed from geometry of a scene and one or more texture images depicted the scene from various viewpoints. A transition zone may correspond to portions of the visualization that do not have a one-to-one correspondence with a single texture image, but are generated from textured geometry (e.g., a projection of texture imagery onto the geometry). Because a translated view may have visual error (e.g., a portion of the translated view is not correctly represented by the textured geometry), one or more transition zones, specifying translated view experiences (e.g., unrestricted view navigation, restricted view navigation, etc.), may be defined. For example, a snapback force may be applied when a current view corresponds to a transition zone having a relatively higher error. |
| US09305367B2 |
Arithmetic coding for information related to sample adaptive offset processing
An image coding method includes: performing context arithmetic coding to consecutively code (i) first information indicating whether or not to perform sample adaptive offset (SAO) processing for a first region of an image and (ii) second information indicating whether or not to use, in the SAO processing for the first region, information on SAO processing for a region other than the first region, the context arithmetic coding being arithmetic coding using a variable probability, the SAO processing being offset processing on a pixel value; and performing bypass arithmetic coding to code other information which is information on the SAO processing for the first region and different from the first information or the second information, after the first information and the second information are coded, the bypass arithmetic coding being arithmetic coding using a fixed probability. |
| US09305360B2 |
Method and apparatus for image enhancement and edge verification using at least one additional image
An image processing system comprises an image processor configured to perform first and second edge detection operations on respective first and second images to obtain respective first and second edge images, to apply a joint edge weighting operation using edges from the first and second edge images, to generate an edge mask based on results of the edge weighting operation, to utilize the edge mask to obtain a third edge image, and to generate a third image based on the third edge image. By way of example only, in a given embodiment the first image may comprise a first depth image generated by a depth imager, the second image may comprise a two-dimensional image of substantially the same scene as the first image, and the third image may comprise an enhanced depth image having enhanced edge quality relative to the first depth image. |
| US09305359B2 |
Image processing method, image processing apparatus, and computer program product
According to an aspect of the present invention, an image processing method for extracting a pixel having a specific feature includes: extracting pixels representing an object, to which the pixel having the specific feature belongs, from a given input image based on an image feature other than color; extracting principal colors from the pixels; selecting, from a plurality of pre-trained color distribution models deposited in a repository, a color distribution model closest in distance metric, which indicates distance relative to the extracted principal colors, to the extracted principal colors by performing a search through the repository using the extracted principal colors; and segmenting the input image by categorizing pixels in the input image using the selected color distribution model. |
| US09305357B2 |
Automatic surveillance video matting using a shape prior
A novel technique for performing video matting, which is built upon a proposed image matting algorithm that is fully automatic is disclosed. The disclosed methods utilize a PCA-based shape model as a prior for guiding the matting process, so that manual interactions required by most existing image matting methods are unnecessary. By applying the image matting algorithm to these foreground windows, on a per frame basis, a fully automated video matting process is attainable. The process of aligning the shape model with the object is simultaneously optimized based on a quadratic cost function. |
| US09305351B2 |
Method of determining the probabilities of suspect nodules being malignant
Methods of determining a probability of a suspect cancer nodule being malignant are provided. In one embodiment, the method begins with tabulating histogram data of malignant and benign nodules as a function of biomarker values for a specified patient population suspect of having a specific type of cancer. Next, the tabulated histogram data is separated into a plurality of biomarker bins where the bins are ranges of biomarker values, and malignancy probability fractions are calculated for each biomarker bin by dividing a number of true positives in each marker bin by a summed total of all true and false positives in each bin. Finally, a suspect nodule in a patient is scanned, a biomarker value for the suspect nodule determined, and a malignancy probability for the suspect nodule determined by reference to the tabulated histogram data and the malignancy probability fractions. Other embodiments are also disclosed. |
| US09305341B2 |
System and method for measurement of through silicon structures
A system and method for measurement of high aspect ratio through silicon via structures. A preferred embodiment includes a white light source and optical components adapted to provide a measurement beam which is nearly collimated with a measurement spot size of the same order of magnitude as the diameter (or effective diameter) of the TSV. These embodiments include a white light source with a variable aperture and other optical components chosen to control the angular spectrum of the incident light. In preferred embodiments the optical components include an automated XYZ stage and a system controller that are utilized to direct the illumination light so as to illuminate the top and bottom of TSV under analysis. |
| US09305340B2 |
Drawing device and drawing program
A reference point determinator determines, as a reference point, the center of each pixel where a sloped line is located. A candidate line generator generates candidate lines each connecting between a point in a pixel having the start point of the sloped line extracted by an endpoint extractor, and a point in a pixel having the end point of the sloped line. A candidate line selector selects a candidate line having the smallest sum total of distances between the candidate line and the reference points from the candidate lines generated by the candidate line generator. A data corrector corrects the sloped line to the candidate line selected by the candidate line selector. |
| US09305338B1 |
Image detail enhancement and edge sharpening without overshooting
A method can include receiving an input image, performing an edge-preservation enhancement on the input image, performing a local-extrema enhancement on the input image, and performing a digital transient improvement (DTi) operation on the input image. A gradient-based fusion of an output of the edge-preserving enhancement and an output of the local-extrema enhancement may be performed, and a transient-based fusion of an output of the gradient-based fusion and an output of the DTi operation may also be performed. |
| US09305337B2 |
System, method, and apparatus for smoothing of edges in images to remove irregularities
System, method, and apparatus for smoothing of edges in images to remove irregularities are disclosed. In one aspect of the present disclosure, a method of image processing includes, identifying an edge in an image having an associated set of edge characteristics, determining the associated set of edge characteristics, and applying a low pass filter to a pixel of the edge based on the associated set of edge characteristics to generate a second image based on the image, wherein the edge in the image is smoothed in the second image. The method further includes generating a third image which is a blend of the original image and the second (edge-smoothed) image based on the associated set of edge characteristics. |
| US09305335B2 |
Display apparatus and NPR processing method applied thereto
A display apparatus and a Non-Photorealistic Rendering process (NPR) are provided. The display apparatus includes: an image processor which processes an NPR with respect to an image so that brightness of a pixel having a brightness value less than a predetermined brightness value is reduced and a brightness of a pixel having a brightness value greater than the predetermined brightness value is increased. Accordingly, a cartoon effect can be maximized. |
| US09305333B1 |
Display with square root of two aspect ratio
An apparatus may include a housing, an electronic display region, and a controller. The electronic display region may be coupled to the housing, and may have a rectangular shape with a length and a width, the length being approximately a square root of two (√2) times longer than the width. In response to an indication that the housing and the display region have been rotated from the portrait mode to a landscape mode, the controller may be configured to display a first image and a second image, the first image having an aspect ratio defined by a second length of the first image divided by a second width of the first image, wherein the second length is different from the first length, the second width is different from the first width, the second aspect ratio is substantially equal to the first aspect ratio, and the first image being rotated by ninety degrees (90°) from the first orientation with respect to the axis. |
| US09305331B2 |
Image processor and image combination method thereof
An image processor and an image combination method thereof are provided. The image processor includes a processing unit for performing the image combination method, and a storing unit for storing an original image and an output image. The image combination method includes the following steps. First, the original image is received from the storing unit. A first processing procedure scales down the original image to generate a first image. A second processing procedure crops the original image to generate a second image. The first image and the second image are combined to form and then be outputted the output image. Accordingly, the image processor and the image combination method are capable of providing the overview and local detailed content of the original image at the same time. |
| US09305330B2 |
Providing images with zoomspots
Systems, methods, and computer-readable storage media for providing images having zoomspots are provided. In embodiments, an interactive image is provided. Such an interactive image includes a zoomspot that, if selected, results in a magnified portion of the interactive image corresponding with the zoomspot. Subsequently, an indication of a selection of the zoomspot is received. In response thereto, the magnified portion of the interactive image corresponding with the zoomspot is automatically presented. The magnified portion can be presented in accordance with a predetermined location of the interactive image and a predetermined quality. |
| US09305327B2 |
Image processing apparatus and control method thereof
An image processing apparatus and its control method receives a drawing command including a moving image drawing command and a graphics drawing command and performs drawing processing. A drawing command is received, and the moving image drawing command is separated from the graphics drawing command. A graphics drawing unit obtains the result of graphics drawing in accordance with the graphics drawing command. A moving image drawing unit generates moving image data processed in accordance with the moving image drawing command. A composition unit composes the result of graphics drawing by the graphics drawing unit with the moving image data generated by the moving image drawing unit. |
| US09305323B2 |
Communication system for detecting law enforcement violations in a vehicular environment
A communication system (200) comprises a radio communication device (100) comprising a controller (102) having law enforcement information (110) stored therein and a data acquisition device (108) for capturing area conditions surrounding a law enforcement vehicle or law enforcement personnel. The controller (102) detects violations of the law enforcement information based on variety of detection devices, such as video analytics. In response to a detection of a law violation by an offending vehicle, a transmitter (104) within communication device 100 generates an alert to similarly formed secondary devices (220) mounted and/or worn within the network. The system (200) provides an automated response through devices (220) by gathering additional data pertaining to the offending vehicle to detect for additional violations of the law, even across state lines. The system (200) may further facilitate apprehension of an offending vehicle through automated roadblocks. |
| US09305322B2 |
Native application testing
In one embodiment, a method includes deploying an application to a plurality of client system, providing a treatment of the application to a set of client systems by receiving a request from the client system, determining whether the client system belongs in a treat group, remotely activating the treatment, and synchronizing activation of the treatment in response to subsequent requests, and receiving exposure data from the set of client system identifying exposure of the users to the treatment. |
| US09305317B2 |
Systems and methods for collecting and transmitting telematics data from a mobile device
A method of analyzing audio signals, such as for a drive monitoring system, includes recording an audio signal from a mobile device, the audio signal including a background audio stream and a residual audio signal. Communication with an audio database is performed to obtain a reference signal. If a match between the background audio stream and the reference signal is determined, a time alignment between the background audio stream and the reference is computed. At least a portion of the recorded audio signal is aligned with the reference signal using the time alignment. The background audio stream is canceled from the recorded audio signal, to result in the residual audio stream. A computer processor is used to determine a driving behavior factor from the residual audio stream. |
| US09305316B2 |
Behavior sets method and system
A behavior sets system facilitates the dynamic generation of field and rule behavior sets for an insurance policy and claims processing computer system. The behavior sets system includes various modules and graphical user interfaces that provide a streamlined mechanism for creating new behavior sets of field and rule behaviors for the insurance processing architecture. The behavior sets system may include various levels of usability that distinguish between an advanced user of the behavior sets system and basic user that uses the generated field and rule behavior sets. The behavior sets system may also include graphical user interfaces directed to adding, editing, removing, or maintaining the behavior of fields and rules for the insurance policy and claims processing computer system. |
| US09305315B2 |
Auditing custodial accounts
According to one embodiment of the present invention, a system for auditing custodian accounts is provided. The system includes a database system receiving customer and custodian information. A sorting processor performs a sort operation on the received customer and custodian information. A customer and custodian matching processor identifies matches between the sorted customer and custodian information. An interface unit outputs information relating to the existence of matches and non-matches between the customer and custodian information. |
| US09305312B2 |
Express easy-pass checkout at grocery stores and retail establishments for preferred members
A grocery store or retail establishment easy-pass (E-Z) lane system for enabling express non-contact payment of a plurality of items is presented including an E-Z pass express checkout lane having at least a scanner for scanning the plurality of items and provided exclusively to preferred members pre-registered with the grocery store or retail establishment. The system includes an RFID antenna positioned about the E-Z pass express checkout lane for communicating with an RFID transponder issued to a preferred member when the RFID transponder is in close proximity to the RFID antenna. The E-Z pass checkout lane is activated thereafter for use by the preferred member for express checkout without the preferred member furnishing direct payment at the E-Z pass express checkout lane via a personal payment account that is separate and distinct from a prepaid vendor-established and maintained purchasing account. |
| US09305311B2 |
Mobile price matching of planned purchase items
A method may include receiving, from users, information identifying items purchased by the users, the information including a price for each of the items, and storing the information in a database. The method may also include receiving, from a second number of users, additional information identifying items purchased by the second users, the additional information including a price for each of the items, and identifying a first item in the database that matches a second item associated with purchases by one of the second users. The method may further include determining whether the price for the second item is lower than the price for the first item stored in the database and updating the database to include the second price for the first item, in response to determining that the second price is lower than the first price. |
| US09305298B2 |
System and method for location-based authentication
A system, apparatus, method, and machine readable medium are described for location-aware authentication. For example, one embodiment of a location-aware method for user authentication comprises: determining a current location of a mobile device; identifying a location class corresponding to the current location; selecting a set of one or more authentication techniques to provide a sufficient level of user authentication for a current transaction based on the identified location class. |
| US09305297B2 |
Secure online communication through a widget on a web page
A client device requests a web page via a network, where the web page is identified by an identifier and references a widget. Following receipt of the requested web page, the client device requests the widget referenced by the requested web page and presents, within the requested web page, a presentation of the widget. Thereafter, in response to receiving user information within the presentation of the widget, the client device communicates the user information to a server via a secure connection between the widget on the client device and the server while maintaining user context at the client device in the requested web page, where the secure connection is initiated by the client device and employs a secure communication protocol implemented by the widget. |
| US09305295B2 |
Payment processing methods and systems
Systems, methods and apparatus for conducting payment transactions are provided. Pursuant to some embodiments, the payment transactions may be conducted between a consumer operating a mobile device and a merchant. |
| US09305291B1 |
Method and apparatus for third party control of a device
A method and apparatus for third party control of a device have been disclosed. By utilizing a third party to control a device, view and control of a device may be separated. |
| US09305289B2 |
Caching and exposing pre-send data relating to the sender or recipient of an electronic mail message
Technologies are described herein for caching and exposing pre-send data relating to the sender or recipient of an e-mail message. A mail client program is configured to cache recipient and configuration mail tips at a client computer. The configuration mail tips may be retrieved from a server computer and cached when the mail client program is started. Recipient mail tips may be retrieved and cached as each recipient of an e-mail message is identified. When subsequent e-mail messages are created, cached mail tips for an e-mail recipient are utilized instead of retrieving the mail tips from the server computer. The cached mail tips may be updated after a predefined period of time has elapsed. The cached mail tips may also be utilized when the client program is offline or unable to establish a connection to the server computer. |
| US09305283B1 |
Association of item identifiers
A radio-frequency identification (RFID) reader system and an imaging device are provided. The RFID reader system is configured to read an RFID tag attached to an item at a location relative to a barcode. The barcode is associated with the item. Once the RFID reader system identifies the RFID tag, the imaging device uses the placement of the RFID tag and/or features of the RFID tag to identify and read the barcode. The imaging device may also identify the RFID tag. Once the barcode is identified, the barcode and the RFID tag are associated. |
| US09305281B2 |
Method and system for order fulfillment in a distribution center
Order allocation techniques pertaining to stops that a container makes in the process of fulfilling a customer order is disclosed. In one embodiment, this is accomplished by first identifying a pod that stocks the largest number of different items in a customer order. Then, a second pod is identified that stocks the largest number of remaining items in the customer order. The collection of pods defines a container path through the distribution center. |
| US09305278B2 |
System and method for compiling intellectual property asset data
An access server computing system scrapes a set of records maintained by a target computing system in a database which is only made accessible over the Internet with a limited protocol query and an access challenge. The access server accesses the target computing system through an Internet browser interface based on emulating a user query made through the limited protocol, including by automatically passing locator identifier fields to retrieve a corresponding set of record which are stored in the first database. |
| US09305271B2 |
Method and an apparatus for automatically providing a common modelling pattern
At least one embodiment of the present invention is directed to a method and/or an apparatus for automatically providing a common modelling pattern as a function of a plurality of stored process models. The common modelling patterns are identified according to three substeps, namely semantic annotation, extraction of pattern based description and composite process pattern mining. The detected common modelling patterns serve as best practice candidates as regards process engineering. At least one embodiment of the present invention finds application in a variety of domains being related to process management, such as process design, process mining and semantic process planning. |
| US09305270B2 |
Synchronization of recipe structures and bill of materials including the adjustment to manufacturing requirements
A system and method of synchronizing recipes and bills of materials (BOM). An approved recipe is parameterized in a planning interface. A BOM is synchronized with the parameterized recipe. The BOM is then displayed in a graphical user interface to allow a user to modify by a resolve conflict present during synchronization. |
| US09305269B2 |
Relative trajectory cost
Methods and systems for determining routes in a Collaborative Trajectory Options Program (CTOP) enabled Air Traffic Management system are disclosed. A first trajectory with a lowest Network Cost and having an assumed ground delay is identified. A Relative Trajectory Cost of zero is assigned to the first trajectory. A second trajectory is identified and the assumed ground delay of the first trajectory is iteratively incremented until a Network Cost for the second trajectory is approximately equivalent to the Network Cost of the first trajectory. A Relative Trajectory Cost for the second trajectory is determined based at least in part on the iteratively incremented assumed ground delay of the first trajectory. |
| US09305267B2 |
Signal detection algorithms to identify drug effects and drug interactions
An algorithm according to an embodiment of the present invention provides for latent signal detection of adverse events. Embodiments infer the presence of adverse drug events from large observational databases housed by the FDA, WHO, and other governmental organizations. The disclosed algorithms do not require the adverse event to be reported explicitly. Instead, the algorithms infer the presence of adverse events through more common secondary effects. In an embodiment, machine learning techniques are used for this purpose. |
| US09305266B2 |
Objective weighing and ranking
A method comprising using at least one hardware processor for: receiving a multi-objective optimization problem; projecting a Pareto frontier of candidate solutions for said multi-objective optimization problem to a hyperplane; decomposing said hyperplane into multiple Voronoi regions each associated with a candidate solution of said candidate solutions; determining a robustness degree for each candidate solution of said candidate solutions, by computing a hypervolume for each region of said multiple Voronoi regions; and ranking said candidate solutions based on the robustness degree. |
| US09305265B2 |
Method and system for probabilistic processing of data using a bit matrix, tuples, and hash values
A method for probabilistic processing of data, wherein the data is provided in form of a data set S composed of multidimensional n-tuples of the form (x1, . . . , xn), is characterized in that an n-dimensional data structure is generated by way of providing a bit matrix, providing a number K of independent hash functions Hk that are employed in order to address the bits in the matrix, and inserting the n-tuples (x1, . . . , xn) into the bit matrix by computing the hash values Hk(x) for all values x of the n-tuple for each of the number K of independent hash functions Hk, and by setting the resulting bits [Hk(x1), . . . , Hk(xn)] of the matrix. Furthermore, a respective system is disclosed. |
| US09305264B2 |
Method and system for improved pattern matching
Method, system and computer program for determining matching between two time series. They use an improved algorithm partially based in Dynamic Time Warping and Information Retrieval techniques, but solving the problems (as computational complexity, memory requirements . . . ) observed in these matching techniques. |
| US09305262B1 |
Improving customer experience in network-based services
Disclosed herein are systems, devices, and techniques for using collective intelligence to improve a customer's experience when using network-based services. Data generated as a byproduct of one or more customer interactions with the network-based service may be repeatedly gathered, optionally stored, and analyzed to generate collective intelligence information. This collective intelligence information may be compared to various assessed parameters associated with a characteristic (i.e., a type and/or a configuration) of a computer resource(s), parameters associated with a state of the network-based service provider environment, and/or a customer experience criterion specified by the customer. |
| US09305256B2 |
Automated method for modifying neural dynamics
A method for improving neural dynamics includes obtaining prototypical neuron dynamics. The method also includes modifying parameters of a neuron model so that the neuron model matches the prototypical neuron dynamics. The neuron dynamics comprise membrane voltages and/or spike timing. |
| US09305253B2 |
Interface IC and memory card including the same
A memory card includes a memory that stores data, a driver that transmits the data received from the memory, and at least one transmitter that transmits the data received from the driver to a receiver provided in an external main unit. The driver and the at least one transmitter are provided in a single IC (integrated circuit) chip and are not overlapped with each other in a planar view. |
| US09305244B2 |
Target tracking
An apparatus and a method are disclosed for tracking a plurality of targets (e.g. land-based vehicles) The method can include: for a first time-step, estimating a state of each target; at a second time-step, measuring values for a state of a target; for the second time-step, estimating a state of each target using the estimated target states for the first time-step; updating the estimated target states for the second time-step using the measured values; and performing an identity management process to estimate a probability that a particular state measurement corresponds to a particular target by providing a mixing matrix, wherein an element of the mixing matrix is based on an overlap between the updated estimated target states of targets in an underlying state space of the estimated target states. |
| US09305242B2 |
Method and image processing apparatus for image visibility restoration using fisher's linear discriminant based dual dark channel prior
A method and an image processing apparatus for image visibility restoration are provided. The method includes the following steps. After an incoming hazy image is received, each of the incoming pixels is classified as either belonging to a localized light region or a non-localized light region. The localized light region is partitioned into patches according to each patch size in associated with image sizes in a training data set. Localized light patches are determined based on a FLD model and a designated patch size is accordingly determined. Adaptive chromatic parameters and dual dark channel priors corresponding to the designated patch size and a small patch size are determined. The incoming hazy image is restored according to the adaptive chromatic parameters, atmospheric light and a transmission map determined based on the dual dark channel priors to produce and output a de-hazed image. |
| US09305239B2 |
Detecting and processing small text in digital media
A method for recognizing small-font sized text including receiving digital media of a natural scene, the digital media having at least one frame that includes the small-font sized text; generating input maps having values that reflect local properties of corresponding regions in the at least one frame; and detecting regions of the at least one frame that contain the small-font sized text by integrating information from the input maps. The integrated information may include information located between border lines having active pixels therebetween and gaps having a high ratio of non-ink pixels located below a bottom border line and above a top border line in relation to a dominant direction of the text. The active pixels may be pixels having dense changes in character stroke directions. |
| US09305238B2 |
Framework for supporting regular expression-based pattern matching in data streams
Techniques for detecting patterns in one or more data or event streams. A pattern to be detected may be specified using a regular expression. Events received in a data stream are processed during runtime to detect occurrences of the specified pattern in the data stream. In one embodiment, a pattern type or class is determined for the specified pattern and pattern matching is performed using a technique selected based upon the type or class determined for the specified pattern. |
| US09305237B2 |
Methods and systems for detection and identification of concealed materials
Methods and systems for efficiently and accurately detecting and identifying concealed materials. The system includes an analysis subsystem configured to process a number of pixelated images, the number of pixelated images obtained by repeatedly illuminating regions with a electromagnetic radiation source from a number of electromagnetic radiation sources, each repetition performed with a different wavelength. The number of pixelated images, after processing, constitute a vector of processed data at each pixel from a number of pixels. At each pixel, the vector of processed data is compared to a predetermined vector corresponding to a predetermined material, presence of the predetermined material being determined by the comparison. |
| US09305231B2 |
Associating a code with an object
Described are machine vision systems, methods, and apparatus, including computer program products for associating codes with objects. In an embodiment, a machine vision system includes an area-scan camera having a field of view (FOV), the area-scan camera disposed relative to a first workspace such that the FOV covers at least a portion of the first workspace and a dimensioner disposed relative to a second workspace. The machine vision system includes a machine vision processor configured to: determine an image location of a code in an image; determine a ray in a shared coordinate space that is a back-projection of the image location of the code; determine one or more surfaces of one or more objects based on dimensioning data; determine a first surface of the one or more surfaces that intersects the 3D ray; and associate the code with an object associated with the first surface. |
| US09305230B2 |
Internet payment system using credit card imaging
A system and a method for conducting credit card transactions through a mobile device of a user. The mobile device comprises an image acquisition unit and a mobile application operated by the mobile device. The system enables acquiring an image of a client's credit card, using the image acquisition unit; analyzing data of the image; outputting details of the credit card from the analysis; verifying the output details, wherein the verification is further carried out through the mobile application; verifying authorization of inputted monetary transaction, wherein the mobile application enables verifying the authorization by communicating with the billing center, associated with at least one credit company associated with the credit card over at least one communication network, wherein the communication is carried out by the mobile application using the mobile device; and conducting monetary transactions using the verified credit card details. |
| US09305226B1 |
Semantic boosting rules for improving text recognition
The accuracy of a text recognition process can be improved using a set of semantic boosting rules, as may be contained in a sequence or other such arrangement. When text is output from a text recognition process, that text can have alternatives and confidence values for different characters or portions of the string. In order to improve the accuracy, this data can be processed using the organized rules, where rules are applied as long as any preconditions for that rule are satisfied, and each rule has the ability to modify the confidence values or modify one or more of the alternatives. When a result it produced with a minimum confidence level, or all applicable rules have been applied, the result can be provided as a refined text output of the recognition process. |
| US09305225B2 |
Methods and systems for determining user liveness
A method determining user liveness is provided that includes calculating, by a device, eye openness measures for a frame included in captured authentication data, and storing the eye openness measures in a buffer of the device. Moreover the method includes calculating confidence scores from the eye openness measures stored in the buffer, and detecting an eye blink when a maximum confidence score is greater than a threshold score. |
| US09305222B2 |
Image processing apparatus and image processing method
According to one embodiment, an image processing apparatus and an image processing method includes a dictionary generation unit, a processed image generation unit, and a detection unit. The dictionary generation unit generates a single dictionary using a plurality of images of a detection target object picked up by a camera. The plurality of images is obtained by arranging the detection target object at a corresponding plurality of positions in a predetermined range such that a predetermined visual axis of the camera is parallel with a normal-line direction of a detection target surface of the detection target object. The processed image generation unit generates a processed image having the predetermined visual axis as a normal-line direction, based on an image picked up by the camera after generation of the dictionary. The detection unit detects the detection target object included in the processed image by determining a feature value using the dictionary. |
| US09305221B2 |
Method and apparatus for identifying a possible collision object
An imaging unit is arranged in a motor vehicle. The imaging unit is designed for providing, as a function of an image acquired by it, a digital source image of a predefined image size. A first intermediate image of a predefined first intermediate image size is generated by reducing a resolution of the source image for the sake of reducing pixels. Furthermore, a second intermediate image of the predefined image size is generated such that it comprises the first intermediate image. The second intermediate image is analyzed by a predefined detector in order to examine whether an object of a predefined object category is situated in the second intermediate image, the detector being designed for analyzing a predefined image detail and for detecting an object of a predefined object category of a predefined object size range. |
| US09305217B2 |
Object tracking system using robot and object tracking method using a robot
Disclosed are an object tracking system using a robot and an object tracking method using a robot. The present invention provides an object tracking system using a robot and an object tracking method using a robot capable of continuously performing object tracking without missing the corresponding object even when the object deviates from a viewing angle of a camera, in tracking an image based object (person) using a robot. |
| US09305213B2 |
Image layout generating apparatus, image product creation system, image layout generating method, and recording medium for image layout generating program
An image layout generating apparatus includes: a first image arranging unit for extracting a first piece of image data from a plurality of image data, and arrange a first image; an image data extracting unit for extracting a new piece of image data; an arranged image selecting unit configured to calculate an inter-image distance between the new piece of image data and image data of each arranged image, and select one of the arranged images; a second image arranging unit configured to arrange a new image to be above, below, left, or right of the selected arranged image by adjusting a size while maintaining an aspect ratio of the new image; and a size adjusting unit configured to adjust the sizes while maintaining the aspect ratios of all the arranged images so as to configure one set of images in which all of the arranged images overall form a rectangle. |
| US09305211B2 |
Method, apparatus, and computer-readable recording medium for converting document image captured by using camera to dewarped document image
A method and apparatus for generating a dewarped document using a document image captured using a camera are provided. The method includes obtaining the document image captures using the camera, extracting text lines from the document image captured using the camera, determining a projection formula to convert positions of respective points constituting the extracted text lines to coordinates projected on a plane of the dewarped document, determining a target function used to calculate a difference between text lines projected on the place of the dewarped document using the projection formula and real text lines, calculating parameters that minimize the target function, and converting the document image to the dewarped document by substituting the calculated parameters into the projection formula. |
| US09305210B2 |
Electronic apparatus and method for processing document
According to one embodiment, an electronic apparatus includes a display controller, a detector and a processor. The display controller displays a document on a screen of a touch screen display, the document including one or more elements corresponding to a first layer and one or more elements corresponding to a second layer. The detector is configured to detect a position and a contact pressure of a first contact on the screen. The processor is configured to delete either a first element corresponding to the first layer or a second element corresponding to the second layer, by using the position and the contact pressure of the first contact. |
| US09305202B2 |
Portable device having fingerprint recognition function
A portable device having fingerprint recognition function includes an image sensing unit, a microprocessor, a signal transmitting unit, a carrying member, a cleaning unit, and a housing. It is characterized that the cleaning unit removes residual fingerprint from the image sensing unit while the carrying member moves in and out of the housing. The portable device of the present invention is free from fingerprint residue and can reduce security risks. |
| US09305199B2 |
Image reader having image sensor array
An image reader can include an image sensor array. An image reader in one embodiment can include an optical system capable of directing light reflected from a target onto the image sensor array. An image reader can be used for reading a dataform. |
| US09305197B2 |
Optimizing focus plane position of imaging scanner
A method includes the following: (1) projecting a light pattern towards a target object; (2) detecting light returned from the target object through an imaging lens arrangement with an imaging sensor to capture a first image with changes in the position of the focus plane of the imaging lens arrangement; (3) processing the first image to determine an optimized position of the focus plane of the imaging lens arrangement; (4) detecting light returned from the target object with the imaging sensor to capture a second image when the position of the focus plane of the imaging lens arrangement is maintained at the optimized position; and (5) decoding a barcode in the second image. |
| US09305192B2 |
Tuneable NFC-enabled device
An NFC-enabled device configured at least in part as an integrated circuit, the integrated circuit including a controller and a plurality of capacitors. The controller is operable to control one or more of the plurality of capacitors to vary an operating parameter of the NFC-enabled device. |
| US09305188B2 |
Image-display method, projector, image-display system, projector-control method, image-display program, and projector-control program
With a conventional image-display system, a presenter sometimes has difficulty in providing every viewer with an easy-to-see picture. When projecting an image transmitted from a computer operated by the presenter and enabling the viewer to watch the image projected by the projector, the projector receives image data transmitted through two-way communication from the computer operated by the presenter, projects an image represented by the received image data and transmits the received image data to a client computer operated by the viewer through the two-way communication, and the client computer receives the image data transmitted through the two-way communication and displays the image represented by the received image data on its display. |
| US09305186B2 |
Protection of proprietary embedded instruments
A network of storage units has a data path which is at least a portion of the network. The network also has a key storage unit and a gateway storage unit. If the key storage unit stores a key value, the key storage unit transmits a key signal to the gateway storage unit. If the gateway storage unit does not store a gateway value or the key signal is not transmitted to the gateway storage unit, the gateway storage unit does not insert a data path segment in the data path. If the gateway storage unit stores a gateway value and the key signal is transmitted to the gateway storage unit, the gateway storage unit inserts the data path segment. |
| US09305185B1 |
Method and apparatus for securing programming data of a programmable device
Circuitry and methods prevent unauthorized programming, or reprogramming, of a programmable device, by requiring a signature in the configuration data to match a signature previously stored in the programmable device. A programmable integrated circuit device includes an input for configuration data, and programming control circuitry operable to derive a current signature from the configuration data, examine a first bit stored in the programmable integrated circuit device, and when the first bit is in a first state, compare the current signature to a first predetermined signature stored in the programmable integrated circuit device and configure the programmable integrated circuit device according to the configuration data only when the current signature matches the first predetermined signature, and when the first bit is in a second state, configure the programmable integrated circuit device according to the configuration data without comparing the current signature to the first predetermined signature. |
| US09305181B1 |
Obfuscating private information using a transaction identifier
A network interface receives transaction information. A processor determines private information and public information from the received transaction information. The network interface communicates the private information to an obfuscation engine, and receives obfuscated private information. The processor then merges the obfuscated private information with the public information to create a temporary identifier, and then converts the temporary identifier into a transaction identifier. A printer then prints a portion of the public information and the transaction identifier on a transaction receipt. |
| US09305177B2 |
Source identification for unauthorized copies of content
Systems and methods for authentication generate keys from secret credentials shared between authenticating parties and authenticators. Generation of the keys may involve utilizing specialized information in the form of parameters that are used to specialize keys. Keys and/or information derived from keys held by multiple authorities may be used to generate other keys such that signatures requiring such keys and/or information can be verified without access to the keys. Keys may also be derived to form a hierarchy of keys that are distributed such that a key holder's ability to decrypt data depends on the key's position in the hierarchy relative to the position of a key used to encrypt the data. Key hierarchies may also be used to distribute key sets to content processing devices to enable the devices to decrypt content such that sources or potential sources of unauthorized content are identifiable from the decrypted content. |
| US09305176B2 |
Database generation from a spreadsheet
A machine may generate a database from a spreadsheet, track the data from its cells as values of variables, and provide such values to authorized users. The machine may receive an upload spreadsheet that was generated by modification of a source spreadsheet by inclusion of control codes, such as a first control code that labels a column of owner names, a second control code that labels a column of measures, and a third control code that labels a column of values of those measures. The machine may parse the upload spreadsheet based on its control codes. The machine may generate a database that contains a data record in which the value of the measure quantifies a variable, and this variable may have a variable name that includes the owner name of the row and the measure of the row. The machine may allow authorized users to download variables and values. |
| US09305172B2 |
Multi-ring encryption approach to securing a payload using hardware modules
Disclosed are systems and methods of employing a multi-ring encryption approach to secure a data payload. Each ring of encryption may be encrypted from a key derived from a password, such that each subsequent ring of protection is protected by a key derived from the key used to encrypt the previous ring of protection. Further, hardware-based encryption may be employed in one or more of the rings of protection to bind the encrypted payload to the hardware. Such systems and methods may be used to reduce the ability to parallelize an attack on encrypted data while also permitting password-related data to be synchronized across a network. |
| US09305167B2 |
Hardware-enabled prevention of code reuse attacks
Described systems and methods allow protecting a host computer system from malware, such as return-oriented programming (ROP) and jump-oriented programming (JOP) exploits. In some embodiments, a processor of the host system is endowed with two counters configured to store a count of branch instructions and a count of inter-branch instructions, respectively, occurring within a stream of instructions fetched by the processor for execution. Exemplary counted branch instructions include indirect JMP, indirect CALL, and RET on x86 platforms, while inter-branch instructions consist of instructions executed between two consecutive counted branch instructions. The processor may be further configured to generate a processor event, such as an exception, when a value stored in a counter exceeds a predetermined threshold. Such events may be used as triggers for launching a malware analysis to determine whether the host system is subject to a code reuse attack. |
| US09305165B2 |
Methods, systems, and computer readable media for detecting injected machine code
According to one aspect, the subject matter described herein includes a method for detecting injected machine code. The method includes extracting data content from a buffer. The method also includes providing an operating system kernel configured to detect injected machine code. The method further includes executing, using the operating system kernel, the data content on a physical processor. The method further includes monitoring, using the operating system kernel, the execution of the data content to determine whether the data content contains injected machine code indicative of a code injection attack. |